Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
138,070 | data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v | 8,175,167 | encode_ctl.v | v | 411 | 149 | [] | [] | [] | [(14, 405)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:74: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 20 bits.\n : ... In instance encode_ctl\n off = max_off - hash_ref;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:124: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 20 bits.\n : ... In instance encode_ctl\n raddr_plus_one <= #1 hash_ref_plus_one + 1\'b1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:132: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'hash_ref_plus_one\' generates 20 bits.\n : ... In instance encode_ctl\n raddr_reg <= #1 hash_ref_plus_one;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:325: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h180\' generates 9 bits.\n : ... In instance encode_ctl\n cnt_output_next = 9\'b110000000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:329: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n : ... In instance encode_ctl\n cnt_output_next = 9\'b000000000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:342: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance encode_ctl\n encode_data_m = 4\'hf;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:350: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n : ... In instance encode_ctl\n encode_data_m = {4\'hf, 4\'h0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:353: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt\' generates 4 bits.\n : ... In instance encode_ctl\n encode_data_m = cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:367: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n : ... In instance encode_ctl\n encode_data_s = {2\'b11, off[6:0]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:374: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_d2\' generates 8 bits.\n : ... In instance encode_ctl\n encode_data_s = data_d2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:384: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n : ... In instance encode_ctl\n 3\'h2: {encode_data, encode_len} = {2\'b00, 4\'h2};\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:385: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n : ... In instance encode_ctl\n 3\'h3: {encode_data, encode_len} = {2\'b01, 4\'h2};\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:386: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n : ... In instance encode_ctl\n 3\'h4: {encode_data, encode_len} = {2\'b10, 4\'h2};\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:387: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n : ... In instance encode_ctl\n 3\'h5: {encode_data, encode_len} = {2\'b11, 2\'b00, 4\'h4};\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:388: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n : ... In instance encode_ctl\n 3\'h6: {encode_data, encode_len} = {2\'b11, 2\'b01, 4\'h4};\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_ctl.v:389: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n : ... In instance encode_ctl\n 3\'h7: {encode_data, encode_len} = {2\'b11, 2\'b10, 4\'h4};\n ^\n%Error: Exiting due to 16 warning(s)\n' | 301,745 | module | module encode_ctl(
hraddr, cnt_output_enable, cnt_len, cnt_output,
cnt_finish,
clk, rst, data_valid, data_empty, hash_data, hash_data1,
data_d1, data_d2, hash_ref, iidx, hdata, data, hash_d1,
hash_data_d1
);
parameter LZF_WIDTH = 20;
input clk, rst;
input data_valid;
input data_empty;
input [7:0] hash_data, hash_data1, data_d1, data_d2;
input [LZF_WIDTH-1:0] hash_ref, iidx;
input [7:0] hdata, data, hash_d1;
output [10:0] hraddr;
input hash_data_d1;
reg off_valid;
reg iidx_window;
always @(posedge clk or posedge rst)
begin
if (rst)
iidx_window <= #1 0;
else if (iidx[11])
iidx_window <= #1 1;
end
reg [LZF_WIDTH-1:0] min_off, max_off;
always @(posedge clk or posedge rst)
begin
if (rst)
min_off <= #1 0;
else if (data_valid && iidx_window)
min_off <= #1 min_off + 1;
end
always @(posedge clk)
begin
if (data_valid)
max_off <= #1 iidx;
end
always @(hash_ref or max_off or min_off)
begin
if (hash_ref > min_off && hash_ref < max_off)
off_valid = 1;
else
off_valid = 0;
end
reg [10:0] off;
always @(hash_ref or max_off)
begin
off = max_off - hash_ref;
end
parameter [2:0]
S_IDLE = 3'h0,
S_SEARCH = 3'h1,
S_TR = 3'h2,
S_MATCH = 3'h3,
S_DELAY = 3'h4,
S_END = 3'h5,
S_DONE = 3'h6,
S_STOP = 3'h7;
reg [2:0] state, state_next;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_next;
end
reg [3:0] cnt, cnt_next;
always @(posedge clk)
begin
cnt <= #1 cnt_next;
end
reg cnt_count, cnt_load;
reg rallow;
reg [10:0] raddr_plus_one;
reg [10:0] raddr_reg;
assign hraddr = rallow ? raddr_plus_one : raddr_reg;
always @(cnt_count or cnt_load)
begin
if (cnt_load || cnt_count)
rallow = 1;
else
rallow = 0;
end
reg [LZF_WIDTH-1:0] hash_ref_plus_one;
always @(hash_ref)
hash_ref_plus_one = hash_ref + 1'b1;
always @(posedge clk)
begin
if (cnt_load)
raddr_plus_one <= #1 hash_ref_plus_one + 1'b1;
else if (cnt_count)
raddr_plus_one <= #1 raddr_plus_one + 1'b1;
end
always @(posedge clk)
begin
if (cnt_load)
raddr_reg <= #1 hash_ref_plus_one;
else if (cnt_count)
raddr_reg <= #1 raddr_plus_one;
end
reg cnt_big7, cnt_big7_next;
always @(posedge clk)
begin
cnt_big7 <= #1 cnt_big7_next;
end
always @(cnt or cnt_big7 or cnt_count or cnt_load)
begin
cnt_next = 0;
cnt_big7_next = 0;
if (cnt_load) begin
cnt_next = 2;
cnt_big7_next = 0;
end else if (cnt_count) begin
cnt_next = cnt + 1;
if (cnt_big7 == 0) begin
if (cnt == 4'h7) begin
cnt_big7_next = 1;
cnt_next = 0;
end else
cnt_big7_next = 0;
end else begin
cnt_big7_next = 1;
end
if (cnt == 4'hf)
cnt_next = 1;
end else begin
cnt_next = cnt;
cnt_big7_next = cnt_big7;
end
end
output cnt_output_enable;
output [3:0] cnt_len;
output [12:0] cnt_output;
output cnt_finish;
reg [2:0] dummy_cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
dummy_cnt <= #1 0;
else if (state == S_DONE)
dummy_cnt <= #1 dummy_cnt + 1'b1;
end
reg cnt_finish;
reg cnt_output_enable, cnt_output_enable_next;
reg [12:0] cnt_output, cnt_output_next;
reg [3:0] cnt_len, cnt_len_next;
always @(cnt or cnt_big7 or data_d1 or data_d2
or data_empty or data_valid or dummy_cnt
or hash_data or hash_data_d1 or hdata
or off_valid or state)
begin
state_next = S_IDLE;
cnt_output_enable_next = 0;
cnt_load = 0;
cnt_count = 0;
case (state)
S_IDLE: begin
if (data_valid)
state_next = S_DELAY;
else
state_next = S_IDLE;
end
S_DELAY: begin
if (data_valid)
state_next = S_SEARCH;
else
state_next = S_DELAY;
end
S_SEARCH: begin
if (data_valid) begin
if (data_d2 == hash_data && off_valid) begin
state_next = S_TR;
cnt_load = 1;
cnt_output_enable_next = 1;
end else begin
cnt_output_enable_next = 1;
state_next = S_SEARCH;
end
end else if (data_empty) begin
cnt_output_enable_next = 1;
state_next = S_END;
end else
state_next = S_SEARCH;
end
S_TR: begin
if (data_valid && hash_data_d1) begin
cnt_count = 1;
state_next = S_MATCH;
end else if (data_valid) begin
state_next = S_SEARCH;
cnt_output_enable_next = 1;
end else if (data_empty) begin
cnt_output_enable_next = 1;
state_next = S_END;
end else begin
state_next = S_TR;
end
end
S_MATCH: begin
if (data_valid) begin
if (data_d1 == hdata) begin
state_next = S_MATCH;
cnt_count = 1;
if (cnt == 4'h7 && cnt_big7 == 0)
cnt_output_enable_next = 1;
else if (cnt == 4'hf)
cnt_output_enable_next = 1;
end else begin
state_next = S_SEARCH;
cnt_output_enable_next = 1;
end
end else if (data_empty) begin
state_next = S_END;
cnt_output_enable_next = 1;
end else
state_next = S_MATCH;
end
S_END: begin
state_next = S_DONE;
cnt_output_enable_next = 1;
end
S_DONE: begin
state_next = S_DONE;
cnt_output_enable_next = 1;
if (&dummy_cnt)
state_next = S_STOP;
end
S_STOP: begin
state_next = S_STOP;
end
endcase
end
always @(posedge clk)
begin
cnt_output <= #1 cnt_output_next;
cnt_len <= #1 cnt_len_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
cnt_output_enable <= #1 0;
else
cnt_output_enable <= #1 cnt_output_enable_next;
end
always @(state)
cnt_finish = state == S_STOP;
reg [3:0] encode_len_s;
reg [12:0] encode_data_s;
reg [3:0] encode_len_m;
reg [12:0] encode_data_m;
reg [3:0] encode_len;
reg [12:0] encode_data;
always @(cnt_output_enable_next or encode_data_m
or encode_data_s or encode_len_m or encode_len_s
or state)
begin
cnt_output_next = 0;
cnt_len_next= 0;
if (cnt_output_enable_next && state == S_SEARCH) begin
cnt_output_next = encode_data_s;
cnt_len_next = encode_len_s;
end else if (cnt_output_enable_next && state == S_END) begin
cnt_output_next = 9'b110000000;
cnt_len_next = 4'h9;
end else if (cnt_output_enable_next && state == S_DONE) begin
cnt_output_next = 9'b000000000;
cnt_len_next = 4'hf;
end else begin
cnt_output_next = encode_data_m;
cnt_len_next = encode_len_m;
end
end
always @(cnt or cnt_big7 or cnt_count
or encode_data or encode_len)
begin
if (cnt_big7 == 0) begin
if (cnt_count) begin
encode_data_m = 4'hf;
encode_len_m = 4'h4;
end else begin
encode_data_m = encode_data;
encode_len_m = encode_len;
end
end else begin
if (cnt == 4'hf && cnt_count == 0) begin
encode_data_m = {4'hf, 4'h0};
encode_len_m = 4'h8;
end else begin
encode_data_m = cnt;
encode_len_m = 4'h4;
end
end
end
always @(cnt_load or data_d2 or off)
begin
encode_len_s = 0;
encode_data_s = 0;
if (cnt_load) begin
if (off[10:07] == 0) begin
encode_len_s = 4'h9;
encode_data_s = {2'b11, off[6:0]};
end else begin
encode_len_s = 4'hd;
encode_data_s = {2'b10, off[10:0]};
end
end else begin
encode_len_s = 4'h9;
encode_data_s = data_d2;
end
end
always @(cnt)
begin
encode_len = 0;
encode_data = 0;
case (cnt[2:0])
3'h2: {encode_data, encode_len} = {2'b00, 4'h2};
3'h3: {encode_data, encode_len} = {2'b01, 4'h2};
3'h4: {encode_data, encode_len} = {2'b10, 4'h2};
3'h5: {encode_data, encode_len} = {2'b11, 2'b00, 4'h4};
3'h6: {encode_data, encode_len} = {2'b11, 2'b01, 4'h4};
3'h7: {encode_data, encode_len} = {2'b11, 2'b10, 4'h4};
endcase
end
endmodule | module encode_ctl(
hraddr, cnt_output_enable, cnt_len, cnt_output,
cnt_finish,
clk, rst, data_valid, data_empty, hash_data, hash_data1,
data_d1, data_d2, hash_ref, iidx, hdata, data, hash_d1,
hash_data_d1
); |
parameter LZF_WIDTH = 20;
input clk, rst;
input data_valid;
input data_empty;
input [7:0] hash_data, hash_data1, data_d1, data_d2;
input [LZF_WIDTH-1:0] hash_ref, iidx;
input [7:0] hdata, data, hash_d1;
output [10:0] hraddr;
input hash_data_d1;
reg off_valid;
reg iidx_window;
always @(posedge clk or posedge rst)
begin
if (rst)
iidx_window <= #1 0;
else if (iidx[11])
iidx_window <= #1 1;
end
reg [LZF_WIDTH-1:0] min_off, max_off;
always @(posedge clk or posedge rst)
begin
if (rst)
min_off <= #1 0;
else if (data_valid && iidx_window)
min_off <= #1 min_off + 1;
end
always @(posedge clk)
begin
if (data_valid)
max_off <= #1 iidx;
end
always @(hash_ref or max_off or min_off)
begin
if (hash_ref > min_off && hash_ref < max_off)
off_valid = 1;
else
off_valid = 0;
end
reg [10:0] off;
always @(hash_ref or max_off)
begin
off = max_off - hash_ref;
end
parameter [2:0]
S_IDLE = 3'h0,
S_SEARCH = 3'h1,
S_TR = 3'h2,
S_MATCH = 3'h3,
S_DELAY = 3'h4,
S_END = 3'h5,
S_DONE = 3'h6,
S_STOP = 3'h7;
reg [2:0] state, state_next;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_next;
end
reg [3:0] cnt, cnt_next;
always @(posedge clk)
begin
cnt <= #1 cnt_next;
end
reg cnt_count, cnt_load;
reg rallow;
reg [10:0] raddr_plus_one;
reg [10:0] raddr_reg;
assign hraddr = rallow ? raddr_plus_one : raddr_reg;
always @(cnt_count or cnt_load)
begin
if (cnt_load || cnt_count)
rallow = 1;
else
rallow = 0;
end
reg [LZF_WIDTH-1:0] hash_ref_plus_one;
always @(hash_ref)
hash_ref_plus_one = hash_ref + 1'b1;
always @(posedge clk)
begin
if (cnt_load)
raddr_plus_one <= #1 hash_ref_plus_one + 1'b1;
else if (cnt_count)
raddr_plus_one <= #1 raddr_plus_one + 1'b1;
end
always @(posedge clk)
begin
if (cnt_load)
raddr_reg <= #1 hash_ref_plus_one;
else if (cnt_count)
raddr_reg <= #1 raddr_plus_one;
end
reg cnt_big7, cnt_big7_next;
always @(posedge clk)
begin
cnt_big7 <= #1 cnt_big7_next;
end
always @(cnt or cnt_big7 or cnt_count or cnt_load)
begin
cnt_next = 0;
cnt_big7_next = 0;
if (cnt_load) begin
cnt_next = 2;
cnt_big7_next = 0;
end else if (cnt_count) begin
cnt_next = cnt + 1;
if (cnt_big7 == 0) begin
if (cnt == 4'h7) begin
cnt_big7_next = 1;
cnt_next = 0;
end else
cnt_big7_next = 0;
end else begin
cnt_big7_next = 1;
end
if (cnt == 4'hf)
cnt_next = 1;
end else begin
cnt_next = cnt;
cnt_big7_next = cnt_big7;
end
end
output cnt_output_enable;
output [3:0] cnt_len;
output [12:0] cnt_output;
output cnt_finish;
reg [2:0] dummy_cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
dummy_cnt <= #1 0;
else if (state == S_DONE)
dummy_cnt <= #1 dummy_cnt + 1'b1;
end
reg cnt_finish;
reg cnt_output_enable, cnt_output_enable_next;
reg [12:0] cnt_output, cnt_output_next;
reg [3:0] cnt_len, cnt_len_next;
always @(cnt or cnt_big7 or data_d1 or data_d2
or data_empty or data_valid or dummy_cnt
or hash_data or hash_data_d1 or hdata
or off_valid or state)
begin
state_next = S_IDLE;
cnt_output_enable_next = 0;
cnt_load = 0;
cnt_count = 0;
case (state)
S_IDLE: begin
if (data_valid)
state_next = S_DELAY;
else
state_next = S_IDLE;
end
S_DELAY: begin
if (data_valid)
state_next = S_SEARCH;
else
state_next = S_DELAY;
end
S_SEARCH: begin
if (data_valid) begin
if (data_d2 == hash_data && off_valid) begin
state_next = S_TR;
cnt_load = 1;
cnt_output_enable_next = 1;
end else begin
cnt_output_enable_next = 1;
state_next = S_SEARCH;
end
end else if (data_empty) begin
cnt_output_enable_next = 1;
state_next = S_END;
end else
state_next = S_SEARCH;
end
S_TR: begin
if (data_valid && hash_data_d1) begin
cnt_count = 1;
state_next = S_MATCH;
end else if (data_valid) begin
state_next = S_SEARCH;
cnt_output_enable_next = 1;
end else if (data_empty) begin
cnt_output_enable_next = 1;
state_next = S_END;
end else begin
state_next = S_TR;
end
end
S_MATCH: begin
if (data_valid) begin
if (data_d1 == hdata) begin
state_next = S_MATCH;
cnt_count = 1;
if (cnt == 4'h7 && cnt_big7 == 0)
cnt_output_enable_next = 1;
else if (cnt == 4'hf)
cnt_output_enable_next = 1;
end else begin
state_next = S_SEARCH;
cnt_output_enable_next = 1;
end
end else if (data_empty) begin
state_next = S_END;
cnt_output_enable_next = 1;
end else
state_next = S_MATCH;
end
S_END: begin
state_next = S_DONE;
cnt_output_enable_next = 1;
end
S_DONE: begin
state_next = S_DONE;
cnt_output_enable_next = 1;
if (&dummy_cnt)
state_next = S_STOP;
end
S_STOP: begin
state_next = S_STOP;
end
endcase
end
always @(posedge clk)
begin
cnt_output <= #1 cnt_output_next;
cnt_len <= #1 cnt_len_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
cnt_output_enable <= #1 0;
else
cnt_output_enable <= #1 cnt_output_enable_next;
end
always @(state)
cnt_finish = state == S_STOP;
reg [3:0] encode_len_s;
reg [12:0] encode_data_s;
reg [3:0] encode_len_m;
reg [12:0] encode_data_m;
reg [3:0] encode_len;
reg [12:0] encode_data;
always @(cnt_output_enable_next or encode_data_m
or encode_data_s or encode_len_m or encode_len_s
or state)
begin
cnt_output_next = 0;
cnt_len_next= 0;
if (cnt_output_enable_next && state == S_SEARCH) begin
cnt_output_next = encode_data_s;
cnt_len_next = encode_len_s;
end else if (cnt_output_enable_next && state == S_END) begin
cnt_output_next = 9'b110000000;
cnt_len_next = 4'h9;
end else if (cnt_output_enable_next && state == S_DONE) begin
cnt_output_next = 9'b000000000;
cnt_len_next = 4'hf;
end else begin
cnt_output_next = encode_data_m;
cnt_len_next = encode_len_m;
end
end
always @(cnt or cnt_big7 or cnt_count
or encode_data or encode_len)
begin
if (cnt_big7 == 0) begin
if (cnt_count) begin
encode_data_m = 4'hf;
encode_len_m = 4'h4;
end else begin
encode_data_m = encode_data;
encode_len_m = encode_len;
end
end else begin
if (cnt == 4'hf && cnt_count == 0) begin
encode_data_m = {4'hf, 4'h0};
encode_len_m = 4'h8;
end else begin
encode_data_m = cnt;
encode_len_m = 4'h4;
end
end
end
always @(cnt_load or data_d2 or off)
begin
encode_len_s = 0;
encode_data_s = 0;
if (cnt_load) begin
if (off[10:07] == 0) begin
encode_len_s = 4'h9;
encode_data_s = {2'b11, off[6:0]};
end else begin
encode_len_s = 4'hd;
encode_data_s = {2'b10, off[10:0]};
end
end else begin
encode_len_s = 4'h9;
encode_data_s = data_d2;
end
end
always @(cnt)
begin
encode_len = 0;
encode_data = 0;
case (cnt[2:0])
3'h2: {encode_data, encode_len} = {2'b00, 4'h2};
3'h3: {encode_data, encode_len} = {2'b01, 4'h2};
3'h4: {encode_data, encode_len} = {2'b10, 4'h2};
3'h5: {encode_data, encode_len} = {2'b11, 2'b00, 4'h4};
3'h6: {encode_data, encode_len} = {2'b11, 2'b01, 4'h4};
3'h7: {encode_data, encode_len} = {2'b11, 2'b10, 4'h4};
endcase
end
endmodule | 8 |
138,071 | data/full_repos/permissive/8175167/encode/rtl/verilog/encode_dp.v | 8,175,167 | encode_dp.v | v | 280 | 80 | [] | [] | [] | [(14, 273)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_dp.v:75: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'getn_reg\' generates 1 bits.\n : ... In instance encode_dp\n assign m_src_getn = ce ? getn_reg : \'bz;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_dp.v:75: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance encode_dp\n assign m_src_getn = ce ? getn_reg : \'bz;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 301,746 | module | module encode_dp(
m_src_getn, data_empty, data, data_valid, hash_data,
hash_data1, hash_ref, data_d1, data_d2, iidx, hash_d1,
hash_data_d1, hdata,
clk, rst, ce, fo_full, fi, src_empty, m_last, hraddr
);
parameter LZF_WIDTH = 20;
input clk, rst, ce, fo_full;
input [63:0] fi;
input src_empty, m_last;
output m_src_getn;
output data_empty;
reg data_empty;
parameter [2:0]
S_IDLE = 3'b000,
S_PROC = 3'b010,
S_WAIT = 3'b100,
S_DONE = 3'b111;
reg [7:0] waddr;
reg [LZF_WIDTH-1:0] hash;
reg hwe, hdone;
reg [2:0]
state, state_next;
output [7:0] data;
output data_valid;
reg [7:0] data, data_next;
reg data_valid, data_valid_next;
reg getn_next, getn_reg;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
getn_reg <= #1 1;
else
getn_reg <= #1 getn_next;
end
assign m_src_getn = ce ? getn_reg : 'bz;
reg data_empty_next;
always @(posedge clk)
begin
data_valid <= #1 data_valid_next;
data <= #1 data_next;
data_empty <= #1 data_empty_next;
end
reg [2:0] iidxL;
always @(posedge clk or posedge rst)
begin
if (rst)
iidxL <= #1 0;
else if (data_valid_next)
iidxL <= #1 iidxL + 1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
hdone <= #1 0;
else if (hdone == 0 && (&waddr))
hdone <= #1 1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
waddr <= #1 0;
else if (hdone == 0)
waddr <= #1 waddr + 1'b1;
else
waddr <= #1 data_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
hwe <= #1 0;
else if (hdone == 0)
hwe <= #1 1;
else
hwe <= #1 data_valid_next;
end
always @(ce or fo_full or hdone or iidxL or m_last
or src_empty or state)
begin
state_next = S_IDLE;
data_valid_next = 0;
getn_next = 1;
data_empty_next = 0;
case (state)
S_IDLE: begin
if (hdone && (!src_empty) && ce)
state_next = S_PROC;
else
state_next = S_IDLE;
end
S_PROC: begin
if (m_last) begin
data_valid_next = 1;
state_next = S_DONE;
end else if (fo_full && (&iidxL)) begin
data_valid_next = 1;
state_next = S_WAIT;
end else if (src_empty && (!m_last)) begin
state_next = S_PROC;
end else if (iidxL == 3'b110) begin
data_valid_next = 1;
state_next = S_PROC;
getn_next = 0;
end else begin
data_valid_next = 1;
state_next = S_PROC;
end
end
S_WAIT: begin
if (fo_full)
state_next = S_WAIT;
else if (!src_empty || m_last) begin
state_next = S_PROC;
end else
state_next = S_WAIT;
end
S_DONE: begin
state_next = S_DONE;
data_empty_next = 1;
end
endcase
end
always @(fi or iidxL)
begin
data_next = 0;
case (iidxL)
3'h0: data_next = fi[07:00];
3'h1: data_next = fi[15:08];
3'h2: data_next = fi[23:16];
3'h3: data_next = fi[31:24];
3'h4: data_next = fi[39:32];
3'h5: data_next = fi[47:40];
3'h6: data_next = fi[55:48];
3'h7: data_next = fi[63:56];
endcase
end
output [7:0] hash_data, hash_data1;
output [LZF_WIDTH-1:0] hash_ref;
output [7:0] data_d1;
output [7:0] data_d2;
reg [LZF_WIDTH+15:0] htab [255:0];
reg [7:0] hash_data, data_d1, data_d2, hash_data1, raddr;
reg [LZF_WIDTH-1:0] hash_ref;
output [LZF_WIDTH-1:0] iidx;
reg [LZF_WIDTH-1:0] iidx;
always @(posedge clk)
begin
if (hwe)
htab[waddr] <= #1 {data_next, data_d1, iidx};
if (data_valid)
{hash_data1, hash_data, hash_ref} <= #1 htab[raddr];
end
always @(posedge clk)
begin
raddr <= #1 data_next;
end
always @(posedge clk)
begin
if (data_valid)
data_d1 <= #1 data;
end
output [7:0] hash_d1;
reg [7:0] hash_d1;
always @(posedge clk)
begin
if (data_valid)
hash_d1 <= #1 hash_data1;
end
output hash_data_d1;
reg hash_data_d1;
always @(data_d1 or data_valid or hash_d1)
begin
if (data_valid)
hash_data_d1 = data_d1 == hash_d1;
else
hash_data_d1 = 1'b0;
end
always @(posedge clk or posedge rst)
begin
if (rst)
data_d2 <= #1 0;
else if (data_valid)
data_d2 <= #1 data_d1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
iidx <= #1 0;
else if (data_valid)
iidx <= #1 iidx + 1;
end
input [10:0] hraddr;
output [7:0] hdata;
reg [7:0] hdata;
reg [10:0] hwaddr;
always @(iidx)
begin
hwaddr = iidx[10:0];
end
reg [7:0] history[2047:0];
always @(posedge clk)
begin
if (data_valid)
history[hwaddr] <= #1 data;
hdata <= #1 history[hraddr];
end
endmodule | module encode_dp(
m_src_getn, data_empty, data, data_valid, hash_data,
hash_data1, hash_ref, data_d1, data_d2, iidx, hash_d1,
hash_data_d1, hdata,
clk, rst, ce, fo_full, fi, src_empty, m_last, hraddr
); |
parameter LZF_WIDTH = 20;
input clk, rst, ce, fo_full;
input [63:0] fi;
input src_empty, m_last;
output m_src_getn;
output data_empty;
reg data_empty;
parameter [2:0]
S_IDLE = 3'b000,
S_PROC = 3'b010,
S_WAIT = 3'b100,
S_DONE = 3'b111;
reg [7:0] waddr;
reg [LZF_WIDTH-1:0] hash;
reg hwe, hdone;
reg [2:0]
state, state_next;
output [7:0] data;
output data_valid;
reg [7:0] data, data_next;
reg data_valid, data_valid_next;
reg getn_next, getn_reg;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
getn_reg <= #1 1;
else
getn_reg <= #1 getn_next;
end
assign m_src_getn = ce ? getn_reg : 'bz;
reg data_empty_next;
always @(posedge clk)
begin
data_valid <= #1 data_valid_next;
data <= #1 data_next;
data_empty <= #1 data_empty_next;
end
reg [2:0] iidxL;
always @(posedge clk or posedge rst)
begin
if (rst)
iidxL <= #1 0;
else if (data_valid_next)
iidxL <= #1 iidxL + 1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
hdone <= #1 0;
else if (hdone == 0 && (&waddr))
hdone <= #1 1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
waddr <= #1 0;
else if (hdone == 0)
waddr <= #1 waddr + 1'b1;
else
waddr <= #1 data_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
hwe <= #1 0;
else if (hdone == 0)
hwe <= #1 1;
else
hwe <= #1 data_valid_next;
end
always @(ce or fo_full or hdone or iidxL or m_last
or src_empty or state)
begin
state_next = S_IDLE;
data_valid_next = 0;
getn_next = 1;
data_empty_next = 0;
case (state)
S_IDLE: begin
if (hdone && (!src_empty) && ce)
state_next = S_PROC;
else
state_next = S_IDLE;
end
S_PROC: begin
if (m_last) begin
data_valid_next = 1;
state_next = S_DONE;
end else if (fo_full && (&iidxL)) begin
data_valid_next = 1;
state_next = S_WAIT;
end else if (src_empty && (!m_last)) begin
state_next = S_PROC;
end else if (iidxL == 3'b110) begin
data_valid_next = 1;
state_next = S_PROC;
getn_next = 0;
end else begin
data_valid_next = 1;
state_next = S_PROC;
end
end
S_WAIT: begin
if (fo_full)
state_next = S_WAIT;
else if (!src_empty || m_last) begin
state_next = S_PROC;
end else
state_next = S_WAIT;
end
S_DONE: begin
state_next = S_DONE;
data_empty_next = 1;
end
endcase
end
always @(fi or iidxL)
begin
data_next = 0;
case (iidxL)
3'h0: data_next = fi[07:00];
3'h1: data_next = fi[15:08];
3'h2: data_next = fi[23:16];
3'h3: data_next = fi[31:24];
3'h4: data_next = fi[39:32];
3'h5: data_next = fi[47:40];
3'h6: data_next = fi[55:48];
3'h7: data_next = fi[63:56];
endcase
end
output [7:0] hash_data, hash_data1;
output [LZF_WIDTH-1:0] hash_ref;
output [7:0] data_d1;
output [7:0] data_d2;
reg [LZF_WIDTH+15:0] htab [255:0];
reg [7:0] hash_data, data_d1, data_d2, hash_data1, raddr;
reg [LZF_WIDTH-1:0] hash_ref;
output [LZF_WIDTH-1:0] iidx;
reg [LZF_WIDTH-1:0] iidx;
always @(posedge clk)
begin
if (hwe)
htab[waddr] <= #1 {data_next, data_d1, iidx};
if (data_valid)
{hash_data1, hash_data, hash_ref} <= #1 htab[raddr];
end
always @(posedge clk)
begin
raddr <= #1 data_next;
end
always @(posedge clk)
begin
if (data_valid)
data_d1 <= #1 data;
end
output [7:0] hash_d1;
reg [7:0] hash_d1;
always @(posedge clk)
begin
if (data_valid)
hash_d1 <= #1 hash_data1;
end
output hash_data_d1;
reg hash_data_d1;
always @(data_d1 or data_valid or hash_d1)
begin
if (data_valid)
hash_data_d1 = data_d1 == hash_d1;
else
hash_data_d1 = 1'b0;
end
always @(posedge clk or posedge rst)
begin
if (rst)
data_d2 <= #1 0;
else if (data_valid)
data_d2 <= #1 data_d1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
iidx <= #1 0;
else if (data_valid)
iidx <= #1 iidx + 1;
end
input [10:0] hraddr;
output [7:0] hdata;
reg [7:0] hdata;
reg [10:0] hwaddr;
always @(iidx)
begin
hwaddr = iidx[10:0];
end
reg [7:0] history[2047:0];
always @(posedge clk)
begin
if (data_valid)
history[hwaddr] <= #1 data;
hdata <= #1 history[hraddr];
end
endmodule | 8 |
138,072 | data/full_repos/permissive/8175167/encode/rtl/verilog/encode_out.v | 8,175,167 | encode_out.v | v | 118 | 80 | [] | [] | [] | [(14, 111)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_out.v:58: Operator OR expects 30 bits on the RHS, but RHS\'s VARREF \'din_data\' generates 13 bits.\n : ... In instance encode_out\n sreg <= #1 (sreg << din_len) | din_data;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_out.v:89: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 30 bits.\n : ... In instance encode_out\n data_o <= #1 sreg >> cnt;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/8175167/encode/rtl/verilog/encode_out.v:108: Operator ADD expects 21 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance encode_out\n ocnt <= #1 ocnt + 2\'b10;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 301,747 | module | module encode_out(
data_o, valid_o, done_o,
clk, rst, ce, cnt_output_enable, cnt_finish, cnt_output,
cnt_len
);
input clk, rst, ce;
input cnt_output_enable, cnt_finish;
input [12:0] cnt_output;
input [3:0] cnt_len;
output [15:0] data_o;
output valid_o;
output done_o;
reg [15:0] data_o;
reg done_o;
reg valid_o;
reg [3:0] din_len;
reg [12:0] din_data;
reg din_valid;
always @(cnt_len or cnt_output or cnt_output_enable)
begin
din_len = cnt_len;
din_data = cnt_output;
din_valid = cnt_output_enable;
end
reg state, state_next;
reg [3:0] cnt, cnt_next;
reg [29:0] sreg;
always @(posedge clk or posedge rst)
begin
if (rst)
sreg <= #1 0;
else if (din_valid)
sreg <= #1 (sreg << din_len) | din_data;
end
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 0;
else
state <= #1 state_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 0;
else
cnt <= #1 cnt_next;
end
always @(cnt or din_len or din_valid)
begin
state_next = 0;
cnt_next = cnt;
if (din_valid)
{state_next, cnt_next} = cnt + din_len;
end
always @(posedge clk)
begin
data_o <= #1 sreg >> cnt;
end
always @(posedge clk)
valid_o <= #1 state;
always @(posedge clk)
if (cnt_finish && state == 0 && state == 0)
done_o <= #1 1'b1;
else
done_o <= #1 1'b0;
reg [20:0] ocnt;
always @(posedge clk or posedge rst)
begin
if (rst)
ocnt <= #1 21'h0;
else if (valid_o)
ocnt <= #1 ocnt + 2'b10;
end
endmodule | module encode_out(
data_o, valid_o, done_o,
clk, rst, ce, cnt_output_enable, cnt_finish, cnt_output,
cnt_len
); |
input clk, rst, ce;
input cnt_output_enable, cnt_finish;
input [12:0] cnt_output;
input [3:0] cnt_len;
output [15:0] data_o;
output valid_o;
output done_o;
reg [15:0] data_o;
reg done_o;
reg valid_o;
reg [3:0] din_len;
reg [12:0] din_data;
reg din_valid;
always @(cnt_len or cnt_output or cnt_output_enable)
begin
din_len = cnt_len;
din_data = cnt_output;
din_valid = cnt_output_enable;
end
reg state, state_next;
reg [3:0] cnt, cnt_next;
reg [29:0] sreg;
always @(posedge clk or posedge rst)
begin
if (rst)
sreg <= #1 0;
else if (din_valid)
sreg <= #1 (sreg << din_len) | din_data;
end
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 0;
else
state <= #1 state_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 0;
else
cnt <= #1 cnt_next;
end
always @(cnt or din_len or din_valid)
begin
state_next = 0;
cnt_next = cnt;
if (din_valid)
{state_next, cnt_next} = cnt + din_len;
end
always @(posedge clk)
begin
data_o <= #1 sreg >> cnt;
end
always @(posedge clk)
valid_o <= #1 state;
always @(posedge clk)
if (cnt_finish && state == 0 && state == 0)
done_o <= #1 1'b1;
else
done_o <= #1 1'b0;
reg [20:0] ocnt;
always @(posedge clk or posedge rst)
begin
if (rst)
ocnt <= #1 21'h0;
else if (valid_o)
ocnt <= #1 ocnt + 2'b10;
end
endmodule | 8 |
138,073 | data/full_repos/permissive/8175167/jhash/bench/verilog/tb.v | 8,175,167 | tb.v | v | 112 | 91 | [] | [] | [] | null | line:25: before: "=" | null | 1: b'%Error: data/full_repos/permissive/8175167/jhash/bench/verilog/tb.v:91: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/8175167/jhash/bench/verilog/tb.v:92: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/8175167/jhash/bench/verilog/tb.v:94: syntax error, unexpected \'@\'\n @(posedge hash_done);\n ^\n%Error: Exiting due to 3 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,748 | module | module tb(
hash_out, hash_done, fi_cnt,
m_endn
);
parameter LZF_WIDTH = 20;
input m_endn;
output [LZF_WIDTH-1:0]fi_cnt;
output hash_done;
output [31:0] hash_out;
wire ce;
wire clk;
wire [63:0] fi;
wire fo_full;
wire m_last;
wire m_src_getn;
wire rst;
wire src_empty;
wire stream_ack;
wire [31:0] stream_data0;
wire [31:0] stream_data1;
wire [31:0] stream_data2;
wire stream_done;
wire [1:0] stream_left;
wire stream_valid;
data data(
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam data.LZF_FILE = "/tmp/decode.chk";
defparam data.LZF_DEBUG = 0;
defparam data.LZF_DELAY = 4;
defparam data.LZF_FIFO_AW = 5;
jhash_in jhash_in (
.m_src_getn (m_src_getn),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]),
.ce (ce),
.clk (clk),
.fi (fi[63:0]),
.fo_full (fo_full),
.m_last (m_last),
.rst (rst),
.src_empty (src_empty),
.stream_ack (stream_ack));
jhash_core jhash_core (
.stream_ack (stream_ack),
.hash_out (hash_out[31:0]),
.hash_done (hash_done),
.clk (clk),
.rst (rst),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]));
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0, tb);
@(posedge hash_done);
$write("out %h\n", hash_out);
$finish;
end
always @(posedge clk)
begin
if (jhash_core.round == 3'b101)
$write("%h, %h, %h\n", jhash_core.OA, jhash_core.OB, jhash_core.OC);
end
endmodule | module tb(
hash_out, hash_done, fi_cnt,
m_endn
); |
parameter LZF_WIDTH = 20;
input m_endn;
output [LZF_WIDTH-1:0]fi_cnt;
output hash_done;
output [31:0] hash_out;
wire ce;
wire clk;
wire [63:0] fi;
wire fo_full;
wire m_last;
wire m_src_getn;
wire rst;
wire src_empty;
wire stream_ack;
wire [31:0] stream_data0;
wire [31:0] stream_data1;
wire [31:0] stream_data2;
wire stream_done;
wire [1:0] stream_left;
wire stream_valid;
data data(
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam data.LZF_FILE = "/tmp/decode.chk";
defparam data.LZF_DEBUG = 0;
defparam data.LZF_DELAY = 4;
defparam data.LZF_FIFO_AW = 5;
jhash_in jhash_in (
.m_src_getn (m_src_getn),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]),
.ce (ce),
.clk (clk),
.fi (fi[63:0]),
.fo_full (fo_full),
.m_last (m_last),
.rst (rst),
.src_empty (src_empty),
.stream_ack (stream_ack));
jhash_core jhash_core (
.stream_ack (stream_ack),
.hash_out (hash_out[31:0]),
.hash_done (hash_done),
.clk (clk),
.rst (rst),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]));
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0, tb);
@(posedge hash_done);
$write("out %h\n", hash_out);
$finish;
end
always @(posedge clk)
begin
if (jhash_core.round == 3'b101)
$write("%h, %h, %h\n", jhash_core.OA, jhash_core.OB, jhash_core.OC);
end
endmodule | 8 |
138,077 | data/full_repos/permissive/8175167/jhash/rtl/verilog/jhash_in.v | 8,175,167 | jhash_in.v | v | 145 | 80 | [] | [] | [] | null | line:1 column:14: Illegal character '©' | data/verilator_xmls/c6662538-ccbe-46b2-a4ba-b1ef07bb4457.xml | null | 301,752 | module | module jhash_in(
m_src_getn, stream_data0, stream_data1, stream_data2,
stream_valid, stream_done, stream_left,
ce, clk, fi, fo_full, m_last, rst, src_empty, stream_ack
);
input ce;
input clk;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
output m_src_getn;
input stream_ack;
output [31:0] stream_data0,
stream_data1,
stream_data2;
output stream_valid;
output stream_done;
output [1:0] stream_left;
reg pull_n;
assign m_src_getn = ce ? ~(pull_n) : 1'bz;
reg [31:0] stream_data0_n,
stream_data1_n,
stream_data2_n;
reg [2:0] state,
state_n;
reg stream_valid_n;
parameter [2:0]
S_IDLE = 3'b100,
S_RUN_01 = 3'b001,
S_RUN_01_N= 3'b101,
S_RUN_10 = 3'b010,
S_RUN_10_N= 3'b110,
S_DONE = 3'b111;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [1:0] dstart, dstart_n;
reg [31:0] d0, d1,
d0_n, d1_n;
always @(posedge clk)
begin
d0 <= #1 d0_n;
d1 <= #1 d1_n;
dstart <= #1 dstart_n;
end
always @(ce or d0 or d1 or dstart or fi or m_last
or src_empty or state or stream_ack)
begin
state_n = state;
pull_n = 1'b0;
d0_n = d0;
d1_n = d1;
dstart_n = dstart;
case (state)
S_IDLE: if (~src_empty && ce) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10: if (stream_ack) begin
if (~src_empty && ~m_last) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end else
state_n = S_RUN_01_N;
end
S_RUN_01_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end
S_RUN_01: if (stream_ack) begin
if (~src_empty && ~m_last) begin
state_n = S_RUN_10_N;
pull_n = 1'b1;
end if (m_last)
state_n = S_DONE;
end
S_DONE: ;
endcase
end
assign stream_left = dstart;
assign stream_valid= ~state[2] && ~src_empty;
assign stream_data0= d0;
assign stream_data1= state[1] ? d1 : fi[31:00];
assign stream_data2= state[1] ? fi[31:0]: fi[63:32];
assign stream_done = m_last;
endmodule | module jhash_in(
m_src_getn, stream_data0, stream_data1, stream_data2,
stream_valid, stream_done, stream_left,
ce, clk, fi, fo_full, m_last, rst, src_empty, stream_ack
); |
input ce;
input clk;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
output m_src_getn;
input stream_ack;
output [31:0] stream_data0,
stream_data1,
stream_data2;
output stream_valid;
output stream_done;
output [1:0] stream_left;
reg pull_n;
assign m_src_getn = ce ? ~(pull_n) : 1'bz;
reg [31:0] stream_data0_n,
stream_data1_n,
stream_data2_n;
reg [2:0] state,
state_n;
reg stream_valid_n;
parameter [2:0]
S_IDLE = 3'b100,
S_RUN_01 = 3'b001,
S_RUN_01_N= 3'b101,
S_RUN_10 = 3'b010,
S_RUN_10_N= 3'b110,
S_DONE = 3'b111;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [1:0] dstart, dstart_n;
reg [31:0] d0, d1,
d0_n, d1_n;
always @(posedge clk)
begin
d0 <= #1 d0_n;
d1 <= #1 d1_n;
dstart <= #1 dstart_n;
end
always @(ce or d0 or d1 or dstart or fi or m_last
or src_empty or state or stream_ack)
begin
state_n = state;
pull_n = 1'b0;
d0_n = d0;
d1_n = d1;
dstart_n = dstart;
case (state)
S_IDLE: if (~src_empty && ce) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10: if (stream_ack) begin
if (~src_empty && ~m_last) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end else
state_n = S_RUN_01_N;
end
S_RUN_01_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end
S_RUN_01: if (stream_ack) begin
if (~src_empty && ~m_last) begin
state_n = S_RUN_10_N;
pull_n = 1'b1;
end if (m_last)
state_n = S_DONE;
end
S_DONE: ;
endcase
end
assign stream_left = dstart;
assign stream_valid= ~state[2] && ~src_empty;
assign stream_data0= d0;
assign stream_data1= state[1] ? d1 : fi[31:00];
assign stream_data2= state[1] ? fi[31:0]: fi[63:32];
assign stream_done = m_last;
endmodule | 8 |
138,078 | data/full_repos/permissive/8175167/jhash/rtl/verilog/lookup3.v | 8,175,167 | lookup3.v | v | 118 | 67 | [] | [] | [] | null | line:118: before: "/" | data/verilator_xmls/0e7b943a-e98a-4999-97b4-bbf2c156cbe5.xml | null | 301,753 | module | module mix(
OA, OB, OC,
a, b, c, clk, shift
);
input [31:0] a, b, c;
output [31:0] OA, OB, OC;
input clk;
input [4:0] shift;
assign OA = (a - c) ^ ( (c << shift) | (c >> (32 - shift)) );
assign OC = c + b;
assign OB = b;
endmodule | module mix(
OA, OB, OC,
a, b, c, clk, shift
); |
input [31:0] a, b, c;
output [31:0] OA, OB, OC;
input clk;
input [4:0] shift;
assign OA = (a - c) ^ ( (c << shift) | (c >> (32 - shift)) );
assign OC = c + b;
assign OB = b;
endmodule | 8 |
138,079 | data/full_repos/permissive/8175167/jhash/rtl/verilog/lookup3.v | 8,175,167 | lookup3.v | v | 118 | 67 | [] | [] | [] | null | line:118: before: "/" | data/verilator_xmls/0e7b943a-e98a-4999-97b4-bbf2c156cbe5.xml | null | 301,753 | module | module lookup3(
x, y, z, done,
k0, k1, k2, clk, en, rst, length
);
output [31:0] x, y, z;
output done;
input [31:0] k0, k1, k2;
input clk;
input en;
input rst;
reg [31:0] x, y, z;
reg [4:0] shift;
wire [31:0] OA, OB, OC;
reg [31:0] a, b, c;
mix M0(
.OA (OA[31:0]),
.OB (OB[31:0]),
.OC (OC[31:0]),
.a (a[31:0]),
.b (b[31:0]),
.c (c[31:0]),
.clk (clk),
.shift (shift[4:0]));
reg [2:0] round;
always @(posedge clk)
if (rst)
round <= #1 0;
else if (en)
round <= #1 round + 1;
input [31:0] length;
wire [31:0] length_val = (length << 2) + 32'hdeadbeef;
always @(posedge clk)
if (en)
case (round)
0: begin
a <= #1 k0 + length_val;
b <= #1 k1 + length_val;
c <= #1 k2 + length_val;
shift <= #1 4;
end
1: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 6;
end
2: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 8;
end
3: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 16;
end
4: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 19;
end
5: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 4;
end
endcase
always @(posedge clk)
if (round == 6) begin
x <= #1 OA;
y <= #1 OB;
z <= #1 OC;
end
assign done = round == 7;
endmodule | module lookup3(
x, y, z, done,
k0, k1, k2, clk, en, rst, length
); |
output [31:0] x, y, z;
output done;
input [31:0] k0, k1, k2;
input clk;
input en;
input rst;
reg [31:0] x, y, z;
reg [4:0] shift;
wire [31:0] OA, OB, OC;
reg [31:0] a, b, c;
mix M0(
.OA (OA[31:0]),
.OB (OB[31:0]),
.OC (OC[31:0]),
.a (a[31:0]),
.b (b[31:0]),
.c (c[31:0]),
.clk (clk),
.shift (shift[4:0]));
reg [2:0] round;
always @(posedge clk)
if (rst)
round <= #1 0;
else if (en)
round <= #1 round + 1;
input [31:0] length;
wire [31:0] length_val = (length << 2) + 32'hdeadbeef;
always @(posedge clk)
if (en)
case (round)
0: begin
a <= #1 k0 + length_val;
b <= #1 k1 + length_val;
c <= #1 k2 + length_val;
shift <= #1 4;
end
1: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 6;
end
2: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 8;
end
3: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 16;
end
4: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 19;
end
5: begin
a <= #1 OB;
b <= #1 OC;
c <= #1 OA;
shift <= #1 4;
end
endcase
always @(posedge clk)
if (round == 6) begin
x <= #1 OA;
y <= #1 OB;
z <= #1 OC;
end
assign done = round == 7;
endmodule | 8 |
138,080 | data/full_repos/permissive/8175167/jhash/rtl/verilog/mix.v | 8,175,167 | mix.v | v | 18 | 73 | [] | [] | [] | [(1, 17)] | null | data/verilator_xmls/520e4c4b-ab30-4132-a045-4fa2ea243745.xml | null | 301,754 | module | module mix(
OA, OB, OC,
a, b, c, clk, shift
);
input [31:0] a, b, c;
output [31:0] OA, OB, OC;
input clk;
input [4:0] shift;
assign OA = (a - c) ^ ( (c << shift) | (c >> (32 - shift)) );
assign OC = c + b;
assign OB = b;
endmodule | module mix(
OA, OB, OC,
a, b, c, clk, shift
); |
input [31:0] a, b, c;
output [31:0] OA, OB, OC;
input clk;
input [4:0] shift;
assign OA = (a - c) ^ ( (c << shift) | (c >> (32 - shift)) );
assign OC = c + b;
assign OB = b;
endmodule | 8 |
138,081 | data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/ch.v | 8,175,167 | ch.v | v | 257 | 74 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb1 in position 6355: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/ch.v:93: Cannot find file containing module: 'ch_fifo'\n ch_fifo src_fifo(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/ch_fifo\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/ch_fifo.v\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/ch_fifo.sv\n ch_fifo\n ch_fifo.v\n ch_fifo.sv\n obj_dir/ch_fifo\n obj_dir/ch_fifo.v\n obj_dir/ch_fifo.sv\n%Error: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/ch.v:128: Cannot find file containing module: 'ch_fifo'\n ch_fifo dst_fifo(\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 301,755 | module | module ch(
src_stop, dst_stop, src_start, dst_start, src_end,
dst_end, src_dat_i, dst_dat_i, src_dat64_i, dst_dat64_i,
m_src, m_src_last, m_src_almost_empty, m_src_empty,
m_dst_almost_full, m_dst_full, ocnt,
wb_clk_i, wb_rst_i, src_xfer, dst_xfer, src_last,
dst_last, src_dat_o, dst_dat_o, src_dat64_o, dst_dat64_o,
dc, m_reset, m_src_getn, m_dst_putn, m_dst, m_dst_last,
m_endn
);
input wb_clk_i;
input wb_rst_i;
input src_xfer,
dst_xfer;
input src_last,
dst_last;
output src_stop,
dst_stop;
output src_start,
dst_start,
src_end,
dst_end;
input [31:0] src_dat_o,
dst_dat_o,
src_dat64_o,
dst_dat64_o;
output [31:0] src_dat_i,
dst_dat_i,
src_dat64_i,
dst_dat64_i;
input [23:0] dc;
input m_reset;
input m_src_getn;
output [63:0] m_src;
output m_src_last;
output m_src_almost_empty;
output m_src_empty;
input m_dst_putn;
input [63:0] m_dst;
input m_dst_last;
output m_dst_almost_full;
output m_dst_full;
input m_endn;
output [15:0] ocnt;
parameter FIFO_WIDTH = 9;
wire [FIFO_WIDTH-1:0] src_waddr,
src_raddr,
dst_waddr,
dst_raddr;
parameter DATA_WIDTH = 65;
wire [DATA_WIDTH-1:0] src_di,
src_do,
dst_di,
dst_do;
wire src_almost_empty,
src_empty,
src_half_full,
src_full,
src_almost_full,
dst_half_full,
dst_half_full_n,
dst_empty,
dst_almost_empty;
wire src_rallow,
src_wallow,
dst_rallow,
dst_wallow;
ch_fifo src_fifo(
.din (src_di),
.rd_clk (wb_clk_i),
.rd_en (!m_src_getn),
.rst (m_reset),
.wr_clk (wb_clk_i),
.wr_en (src_xfer),
.almost_empty (m_src_almost_empty),
.almost_full (src_almost_full),
.dout (src_do),
.empty (m_src_empty),
.full (src_full),
.prog_full (src_half_full),
.prog_empty ()
);
assign dst_half_full = m_dst_almost_full;
ch_fifo dst_fifo(
.din (dst_di),
.rd_clk (wb_clk_i),
.rd_en (dst_xfer && ~dst_end),
.rst (m_reset),
.wr_clk (wb_clk_i),
.wr_en (!m_dst_putn),
.almost_empty (dst_almost_empty),
.almost_full (),
.dout (dst_do),
.empty (dst_empty),
.full (m_dst_full),
.prog_full (m_dst_almost_full),
.prog_empty (dst_half_full_n)
);
reg [15:0] ocnt;
always @(posedge wb_clk_i)
begin
if (m_reset)
ocnt <= #1 16'h0;
else if (!m_dst_putn & !m_dst_last)
ocnt <= #1 ocnt + 1'b1;
end
assign src_di[64] = src_last;
assign src_di[63:56]= src_dat64_o[7:0];
assign src_di[55:48]= src_dat64_o[15:8];
assign src_di[47:40]= src_dat64_o[23:16];
assign src_di[39:32]= src_dat64_o[31:24];
assign src_di[31:24]= src_dat_o[7:0];
assign src_di[23:16]= src_dat_o[15:8];
assign src_di[15:8]= src_dat_o[23:16];
assign src_di[7:0]= src_dat_o[31:24];
assign m_src = src_do[63:0];
assign m_src_last = src_do[64];
assign dst_di[63:56] = m_dst[7:0];
assign dst_di[55:48] = m_dst[15:8];
assign dst_di[47:40] = m_dst[23:16];
assign dst_di[39:32] = m_dst[31:24];
assign dst_di[31:24] = m_dst[39:32];
assign dst_di[23:16] = m_dst[47:40];
assign dst_di[15:8] = m_dst[55:48];
assign dst_di[7:0] = m_dst[63:56];
assign dst_di[64] = m_dst_last;
assign dst_dat64_i = dst_do[63:32];
assign dst_dat_i = dst_do[31:00];
assign src_stop = src_half_full;
assign dst_stop = dst_half_full;
assign src_end = 1'b0;
assign dst_end = dst_do[64];
assign src_start = !(src_almost_full || src_full) && !m_reset;
assign dst_start = dst_half_full || ((!m_endn) && (!dst_empty));
endmodule | module ch(
src_stop, dst_stop, src_start, dst_start, src_end,
dst_end, src_dat_i, dst_dat_i, src_dat64_i, dst_dat64_i,
m_src, m_src_last, m_src_almost_empty, m_src_empty,
m_dst_almost_full, m_dst_full, ocnt,
wb_clk_i, wb_rst_i, src_xfer, dst_xfer, src_last,
dst_last, src_dat_o, dst_dat_o, src_dat64_o, dst_dat64_o,
dc, m_reset, m_src_getn, m_dst_putn, m_dst, m_dst_last,
m_endn
); |
input wb_clk_i;
input wb_rst_i;
input src_xfer,
dst_xfer;
input src_last,
dst_last;
output src_stop,
dst_stop;
output src_start,
dst_start,
src_end,
dst_end;
input [31:0] src_dat_o,
dst_dat_o,
src_dat64_o,
dst_dat64_o;
output [31:0] src_dat_i,
dst_dat_i,
src_dat64_i,
dst_dat64_i;
input [23:0] dc;
input m_reset;
input m_src_getn;
output [63:0] m_src;
output m_src_last;
output m_src_almost_empty;
output m_src_empty;
input m_dst_putn;
input [63:0] m_dst;
input m_dst_last;
output m_dst_almost_full;
output m_dst_full;
input m_endn;
output [15:0] ocnt;
parameter FIFO_WIDTH = 9;
wire [FIFO_WIDTH-1:0] src_waddr,
src_raddr,
dst_waddr,
dst_raddr;
parameter DATA_WIDTH = 65;
wire [DATA_WIDTH-1:0] src_di,
src_do,
dst_di,
dst_do;
wire src_almost_empty,
src_empty,
src_half_full,
src_full,
src_almost_full,
dst_half_full,
dst_half_full_n,
dst_empty,
dst_almost_empty;
wire src_rallow,
src_wallow,
dst_rallow,
dst_wallow;
ch_fifo src_fifo(
.din (src_di),
.rd_clk (wb_clk_i),
.rd_en (!m_src_getn),
.rst (m_reset),
.wr_clk (wb_clk_i),
.wr_en (src_xfer),
.almost_empty (m_src_almost_empty),
.almost_full (src_almost_full),
.dout (src_do),
.empty (m_src_empty),
.full (src_full),
.prog_full (src_half_full),
.prog_empty ()
);
assign dst_half_full = m_dst_almost_full;
ch_fifo dst_fifo(
.din (dst_di),
.rd_clk (wb_clk_i),
.rd_en (dst_xfer && ~dst_end),
.rst (m_reset),
.wr_clk (wb_clk_i),
.wr_en (!m_dst_putn),
.almost_empty (dst_almost_empty),
.almost_full (),
.dout (dst_do),
.empty (dst_empty),
.full (m_dst_full),
.prog_full (m_dst_almost_full),
.prog_empty (dst_half_full_n)
);
reg [15:0] ocnt;
always @(posedge wb_clk_i)
begin
if (m_reset)
ocnt <= #1 16'h0;
else if (!m_dst_putn & !m_dst_last)
ocnt <= #1 ocnt + 1'b1;
end
assign src_di[64] = src_last;
assign src_di[63:56]= src_dat64_o[7:0];
assign src_di[55:48]= src_dat64_o[15:8];
assign src_di[47:40]= src_dat64_o[23:16];
assign src_di[39:32]= src_dat64_o[31:24];
assign src_di[31:24]= src_dat_o[7:0];
assign src_di[23:16]= src_dat_o[15:8];
assign src_di[15:8]= src_dat_o[23:16];
assign src_di[7:0]= src_dat_o[31:24];
assign m_src = src_do[63:0];
assign m_src_last = src_do[64];
assign dst_di[63:56] = m_dst[7:0];
assign dst_di[55:48] = m_dst[15:8];
assign dst_di[47:40] = m_dst[23:16];
assign dst_di[39:32] = m_dst[31:24];
assign dst_di[31:24] = m_dst[39:32];
assign dst_di[23:16] = m_dst[47:40];
assign dst_di[15:8] = m_dst[55:48];
assign dst_di[7:0] = m_dst[63:56];
assign dst_di[64] = m_dst_last;
assign dst_dat64_i = dst_do[63:32];
assign dst_dat_i = dst_do[31:00];
assign src_stop = src_half_full;
assign dst_stop = dst_half_full;
assign src_end = 1'b0;
assign dst_end = dst_do[64];
assign src_start = !(src_almost_full || src_full) && !m_reset;
assign dst_start = dst_half_full || ((!m_endn) && (!dst_empty));
endmodule | 8 |
138,084 | data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v | 8,175,167 | comp_unit.v | v | 881 | 87 | [] | [] | [] | [(1, 874)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:181: Signal definition not found, creating implicitly: \'op_copy0\'\n : ... Suggested alternative: \'op_copy\'\n assign op_copy0 = 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:45: Little bit endian vector: MSB < LSB of bit range: 0:9\n input [0:9] plb_dcrabus;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:47: Little bit endian vector: MSB < LSB of bit range: 0:31\n input [0:31] plb_dcrdbusout;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:52: Little bit endian vector: MSB < LSB of bit range: 0:31\n output [0:31] dcr_plbdbusin;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:170: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'DMALLTXREM\' generates 4 bits.\n : ... In instance comp_unit\n assign tx_rem = DMALLTXREM;\n ^\n%Error: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:750: Cannot find file containing module: \'ll_crc\'\n ll_crc\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/ll_crc\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/ll_crc.v\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/ll_crc.sv\n ll_crc\n ll_crc.v\n ll_crc.sv\n obj_dir/ll_crc\n obj_dir/ll_crc.v\n obj_dir/ll_crc.sv\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:777: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] comp2dcr_data;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:824: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'flag\' generates 3 bits.\n : ... In instance comp_unit\n comp2dcr_data[0:3] = flag;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:828: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'tx_busy\' generates 1 bits.\n : ... In instance comp_unit\n comp2dcr_data[0:3] = tx_busy;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:829: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'tx_end_rdy\' generates 1 bits.\n : ... In instance comp_unit\n comp2dcr_data[4:7] = tx_end_rdy;\n ^\n%Warning-WIDTH: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/comp_unit.v:830: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_end\' generates 1 bits.\n : ... In instance comp_unit\n comp2dcr_data[28:31] = rx_end;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 301,759 | module | module comp_unit(
LLDMARSTENGINEREQ, LLDMARXD, LLDMARXREM, LLDMARXSOFN, LLDMARXEOFN,
LLDMARXSOPN, LLDMARXEOPN, LLDMARXSRCRDYN, LLDMATXDSTRDYN, src_last,
dst_end, dst_start, dcr_plback, dcr_plbdbusin,
CPMDMALLCLK, DMALLRSTENGINEACK, DMALLRXDSTRDYN, DMALLTXD,
DMALLTXREM, DMALLTXSOFN, DMALLTXEOFN, DMALLTXSOPN, DMALLTXEOPN,
DMALLTXSRCRDYN, DMATXIRQ, DMARXIRQ, plb_dcrabus, plb_dcrclk,
plb_dcrdbusout, plb_dcrread, plb_dcrrst, plb_dcrwrite
);
parameter C_VERSION = 32'hdead_dead;
parameter C_ENABLE = 0;
(* PERIOD = "5000ps" *)
input CPMDMALLCLK;
output LLDMARSTENGINEREQ;
input DMALLRSTENGINEACK;
output [31:0] LLDMARXD;
output [3:0] LLDMARXREM;
output LLDMARXSOFN;
output LLDMARXEOFN;
output LLDMARXSOPN;
output LLDMARXEOPN;
output LLDMARXSRCRDYN;
input DMALLRXDSTRDYN;
input [31:0] DMALLTXD;
input [3:0] DMALLTXREM;
input DMALLTXSOFN;
input DMALLTXEOFN;
input DMALLTXSOPN;
input DMALLTXEOPN;
input DMALLTXSRCRDYN;
output LLDMATXDSTRDYN;
input DMATXIRQ;
input DMARXIRQ;
output src_last;
output dst_end;
output dst_start;
input [0:9] plb_dcrabus;
input plb_dcrclk;
input [0:31] plb_dcrdbusout;
input plb_dcrread;
input plb_dcrrst;
input plb_dcrwrite;
output dcr_plback;
output [0:31] dcr_plbdbusin;
parameter TX_IDLE = 4'h0;
parameter TX_HEAD1 = 4'h1;
parameter TX_HEAD2 = 4'h2;
parameter TX_HEAD3 = 4'h3;
parameter TX_HEAD4 = 4'h4;
parameter TX_HEAD5 = 4'h5;
parameter TX_HEAD6 = 4'h6;
parameter TX_HEAD7 = 4'h7;
parameter TX_PAYLOAD = 4'h8;
parameter TX_PAYLOAD1 = 4'h9;
parameter TX_COPY = 4'ha;
parameter TX_END = 4'hb;
parameter RX_IDLE = 4'h0;
parameter RX_HEAD0 = 4'h1;
parameter RX_HEAD1 = 4'h2;
parameter RX_HEAD2 = 4'h3;
parameter RX_HEAD3 = 4'h4;
parameter RX_HEAD4 = 4'h5;
parameter RX_HEAD5 = 4'h6;
parameter RX_HEAD6 = 4'h7;
parameter RX_HEAD7 = 4'h8;
parameter RX_PAYLOAD = 4'h9;
parameter RX_PAYLOAD1 = 4'ha;
parameter RX_COPY = 4'hb;
parameter RX_END = 4'hc;
wire clk;
wire rst_n;
reg [3:0] tx_state;
reg [3:0] tx_state_n;
reg [3:0] rx_state;
reg [3:0] rx_state_n;
wire op_copy;
wire op_copy1;
wire op_comp;
wire op_decomp;
wire [3:0] DMALLTXREM_r;
reg [31:29] flag;
reg [31:0] src_len;
reg [31:0] data0;
reg [31:0] data1;
reg [31:0] rx_data_comp;
reg [3:0] rem;
wire DMALLRSTENGINEACK;
wire LLDMATXDSTRDYN;
reg [31:0] LLDMARXD_r;
reg [3:0] LLDMARXREM_r;
reg LLDMARXSRCRDYN_r;
reg LLDMARXSOPN_r;
reg LLDMARXEOPN_r;
reg LLDMARXEOFN_r;
reg rx_sof_r_n;
reg m_reset;
reg [0:31] dcr_plbdbusin;
wire [31:0] crc_rx;
wire [31:0] crc_tx;
wire [31:0] dst_dat_i;
wire [31:0] dst_dat64_i;
wire src_start;
wire dst_start;
wire dst_end;
wire dst_xfer;
reg src_xfer;
reg src_last;
wire [15:0] ocnt;
reg reset_n;
reg tx_busy;
reg rx_end;
reg [15:0] len_cnt;
wire Rst = ~rst_n;
wire SYS_Clk = clk;
wire [31:0] rx_data;
wire [3:0] rx_rem;
wire rx_sof_n;
wire rx_eof_n;
wire rx_sop_n;
wire rx_eop_n;
wire rx_src_rdy_n;
wire rx_dst_rdy_n;
wire [31:0] tx_data;
wire [31:0] tx_rem;
wire tx_sof_n;
wire tx_eof_n;
wire tx_sop_n;
wire tx_eop_n;
wire tx_src_rdy_n;
wire tx_dst_rdy_n;
reg tx_end_rdy;
reg [9:0] task_index;
wire soft_reset;
wire src_stop;
reg LLDMARSTENGINEREQ;
assign LLDMARXD = LLDMARXD_r;
assign LLDMARXREM = LLDMARXREM_r;
assign LLDMARXSOFN = rx_sof_r_n;
assign LLDMARXEOFN = LLDMARXEOFN_r;
assign LLDMARXSOPN = LLDMARXSOPN_r;
assign LLDMARXEOPN = LLDMARXEOPN_r;
assign LLDMARXSRCRDYN = LLDMARXSRCRDYN_r;
assign tx_data = DMALLTXD;
assign tx_rem = DMALLTXREM;
assign tx_sof_n = DMALLTXSOFN;
assign tx_eof_n = DMALLTXEOFN;
assign tx_sop_n = DMALLTXSOPN;
assign tx_eop_n = DMALLTXEOPN;
assign tx_src_rdy_n= DMALLTXSRCRDYN;
assign LLDMATXDSTRDYN = (~src_start && (op_comp || op_decomp || op_copy1)) &&
(tx_end_rdy || tx_busy) || tx_busy;
assign clk = CPMDMALLCLK;
assign rst_n = ~(DMALLRSTENGINEACK || LLDMARSTENGINEREQ);
assign op_copy1 = flag[29];
assign op_copy0 = 0;
assign op_decomp = flag[30];
assign op_comp = flag[31];
always @(posedge clk)
if (!rst_n)
tx_state <= TX_IDLE;
else
tx_state <= tx_state_n;
always @(*)
begin
tx_state_n = tx_state;
case (tx_state)
TX_IDLE : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXSOFN)
tx_state_n = TX_HEAD1;
else
tx_state_n = TX_IDLE;
end else
tx_state_n = TX_IDLE;
end
TX_HEAD1 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD2;
end else
tx_state_n = TX_HEAD1;
end
TX_HEAD2 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD3;
end else
tx_state_n = TX_HEAD2;
end
TX_HEAD3 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD4;
end else
tx_state_n = TX_HEAD3;
end
TX_HEAD4 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD5;
end else
tx_state_n = TX_HEAD4;
end
TX_HEAD5 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD6;
end else
tx_state_n = TX_HEAD5;
end
TX_HEAD6 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD7;
end else
tx_state_n = TX_HEAD6;
end
TX_HEAD7 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (op_copy)
tx_state_n = TX_COPY;
else
tx_state_n = TX_PAYLOAD;
end else
tx_state_n = TX_HEAD7;
end
TX_PAYLOAD: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD1;
end else if (rx_end)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD;
end
TX_PAYLOAD1: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD;
end else if (rx_end)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD1;
end
TX_COPY: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN)
tx_state_n = TX_END;
else
tx_state_n = TX_COPY;
end else
tx_state_n = TX_COPY;
end
TX_END: begin
if (m_reset)
tx_state_n = TX_IDLE;
else
tx_state_n = TX_END;
end
endcase
end
always @(posedge clk)
if (!rst_n) begin
tx_end_rdy <= 1;
data0 <= 32'h0;
data1 <= 32'h0;
flag <= 3'h0;
src_last <= 1'h0;
src_len <= 32'h0;
src_xfer <= 1'h0;
task_index <= 10'h0;
tx_busy <= 1'h0;
end else begin
case (tx_state)
TX_IDLE : begin
tx_end_rdy <= 1;
src_last <= 0;
src_xfer <= 0;
tx_busy <= 0;
flag <= 3'h0;
end
TX_HEAD1 : begin
end
TX_HEAD2 : begin
end
TX_HEAD3 : begin
end
TX_HEAD4 : begin
flag <= DMALLTXD[31:29];
end
TX_HEAD5 : begin
src_len <= DMALLTXD;
end
TX_HEAD6 : begin
task_index <= DMALLTXD[9:0];
end
TX_HEAD7 : begin
end
TX_PAYLOAD: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN) begin
src_xfer <= 1;
data1 <= 0;
case (DMALLTXREM)
4'b0000 : data0 <= DMALLTXD;
4'b0001 : data0 <= {DMALLTXD[31:8],8'h0};
4'b0011 : data0 <= {DMALLTXD[31:16],16'h0};
4'b0111 : data0 <= {DMALLTXD[31:24],24'h0};
endcase
end else begin
src_xfer <= 0;
data0 <= DMALLTXD;
end
end else begin
src_xfer <= 0;
end
end
TX_PAYLOAD1: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
src_xfer <= 1;
if (!DMALLTXEOPN) begin
case (DMALLTXREM)
4'b0000 : data1 <= DMALLTXD;
4'b0001 : data1 <= {DMALLTXD[31:8],8'h0};
4'b0011 : data1 <= {DMALLTXD[31:16],16'h0};
4'b0111 : data1 <= {DMALLTXD[31:24],24'h0};
endcase
end else begin
data1 <= DMALLTXD;
end
end else begin
src_xfer <= 0;
end
end
TX_COPY: begin
end
TX_END : begin
tx_end_rdy <= 0;
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN
&& !DMALLTXEOFN) begin
src_last <= 1;
src_xfer <= 1;
tx_busy <= 1;
end else begin
src_last <= 0;
src_xfer <= 0;
end
end
endcase
end
always @(posedge clk)
if (!rst_n)
rx_state <= RX_IDLE;
else
rx_state <= rx_state_n;
always @(*)
begin
rx_state_n = rx_state;
case (rx_state)
RX_IDLE: begin
if (!DMALLRXDSTRDYN && !m_reset) begin
if (op_copy)
rx_state_n = RX_COPY;
else if (dst_start && (op_comp || op_decomp || op_copy1))
rx_state_n = RX_PAYLOAD;
else
rx_state_n = RX_IDLE;
end else
rx_state_n = RX_IDLE;
end
RX_HEAD0 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD1;
end else
rx_state_n = RX_HEAD0;
end
RX_HEAD1 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD2;
end else
rx_state_n = RX_HEAD1;
end
RX_HEAD2 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD3;
end else
rx_state_n = RX_HEAD2;
end
RX_HEAD3 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD4;
end else
rx_state_n = RX_HEAD3;
end
RX_HEAD4 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD5;
end else
rx_state_n = RX_HEAD4;
end
RX_HEAD5 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD6;
end else
rx_state_n = RX_HEAD5;
end
RX_HEAD6 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD7;
end else
rx_state_n = RX_HEAD6;
end
RX_HEAD7 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_END;
end else
rx_state_n = RX_HEAD7;
end
RX_PAYLOAD: begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_PAYLOAD1;
end else begin
rx_state_n = RX_PAYLOAD;
end
end
RX_PAYLOAD1: begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
if (ocnt > src_len[18:3])
rx_state_n = RX_HEAD0;
else if ((ocnt == len_cnt) && dst_start)
rx_state_n = RX_HEAD0;
else
rx_state_n = RX_PAYLOAD;
end else begin
rx_state_n = RX_PAYLOAD1;
end
end
RX_COPY: begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
if (!LLDMARXEOFN)
rx_state_n = RX_END;
else
rx_state_n = RX_COPY;
end else begin
rx_state_n = RX_COPY;
end
end
RX_END: begin
if(m_reset)
rx_state_n = RX_IDLE;
else
rx_state_n = RX_END;
end
endcase
end
reg cpl_status;
always @(posedge clk)
if (!rst_n) begin
rx_sof_r_n <= 1;
LLDMARXSOPN_r <= 1;
LLDMARXEOPN_r <= 1;
LLDMARXEOFN_r <= 1;
LLDMARXD_r <= 32'h0;
LLDMARXREM_r <= 4'h0;
LLDMARXSRCRDYN_r <= 1'h1;
cpl_status <= 1'h0;
rx_data_comp <= 32'h0;
rx_end <= 1'h0;
end else begin
case (rx_state)
RX_IDLE: begin
rx_sof_r_n <= 1;
LLDMARXSOPN_r <= 1;
LLDMARXEOPN_r <= 1;
LLDMARXEOFN_r <= 1;
cpl_status <= 1'h0;
rx_end <= 1'h0;
reset_n <= 1'b1;
if (dst_start && (op_comp || op_decomp || op_copy1))begin
if (!DMALLRXDSTRDYN && !m_reset) begin
LLDMARXSRCRDYN_r <= 0;
rx_sof_r_n <= 0;
end else begin
LLDMARXSRCRDYN_r <= 1;
rx_sof_r_n <= 1;
end
end
end
RX_HEAD0 : begin
LLDMARXSRCRDYN_r <= 0;
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXREM_r <= 4'h0;
LLDMARXSOPN_r <= 1;
LLDMARXEOPN_r <= 1;
end
end
RX_HEAD1 : begin
end
RX_HEAD2 : begin
end
RX_HEAD3 : begin
rx_end <= 1;
LLDMARXSRCRDYN_r <= !tx_busy;
end
RX_HEAD4 : begin
LLDMARXSRCRDYN_r <= !tx_busy;
LLDMARXD_r[31:29]<= flag;
LLDMARXD_r[28] <= cpl_status;
LLDMARXD_r[27:11]<= 0;
LLDMARXD_r[10] <= 1'b1;
LLDMARXD_r[9:0] <= crc_tx[9:0];
end
RX_HEAD5 : begin
if (op_copy)
LLDMARXD_r <= src_len;
else
LLDMARXD_r <= {13'h0,ocnt,3'h0};
end
RX_HEAD6 : begin
LLDMARXD_r[31:10]<= crc_tx[31:10];
LLDMARXD_r[9:0] <= task_index;
end
RX_HEAD7 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXEOFN_r <= 0;
LLDMARXD_r<= crc_rx;
end
end
RX_PAYLOAD: begin
rx_sof_r_n <= 1;
LLDMARXEOPN_r <= 1;
LLDMARXSRCRDYN_r <= ~dst_start;
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXSOPN_r <= rx_sof_r_n;
LLDMARXD_r <= dst_dat64_i;
rx_data_comp <= dst_dat_i;
end else begin
end
end
RX_PAYLOAD1: begin
LLDMARXSRCRDYN_r <= ~dst_start;
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXSOPN_r <= 1;
LLDMARXD_r <= rx_data_comp;
if (ocnt > src_len[18:3]) begin
LLDMARXREM_r <= 4'h7;
cpl_status <= 0;
LLDMARXEOPN_r <= 0;
end else if ((ocnt == len_cnt) && dst_start) begin
LLDMARXREM_r <= 4'h0;
cpl_status <= 1;
LLDMARXEOPN_r <= 0;
end else begin
LLDMARXEOPN_r <= 1;
end
end
end
RX_COPY: begin
end
RX_END: begin
LLDMARXREM_r <= 0;
rx_end <= 1;
if(LLDMARXEOFN && tx_busy)
reset_n <= 1'b0;
else
reset_n <= 1'b1;
if(!LLDMARXSRCRDYN && !DMALLRXDSTRDYN)
begin
LLDMARXEOFN_r <= 1;
LLDMARXSRCRDYN_r <= 1;
end
end
endcase
end
always @(posedge clk)
if (m_reset)
len_cnt <= 0;
else if (dst_xfer)
len_cnt <= len_cnt + 1;
assign dst_xfer = (rx_state == RX_PAYLOAD) && (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN);
wire m_src_getn;
wire m_dst_putn;
wire [63:0] m_dst;
wire m_dst_last;
wire m_endn;
wire [7:0] m_cap;
reg [2:0] rst_cnt;
reg m_enable;
wire [23:0] dc;
wire [63:0] m_src;
wire m_src_last;
wire m_src_empty;
wire m_src_almost_empty;
wire m_dst_almost_full;
wire m_dst_full;
wire src_end;
always @(posedge clk)
if (~rst_n)
begin
m_reset <= 1;
end
else if (~reset_n)
begin
m_reset <= 1;
end
else if (rst_cnt == 3'h6)
begin
m_reset <= 0;
end
always @(posedge clk)
if (~rst_n)
begin
rst_cnt <= 0;
end
else if (~reset_n)
begin
rst_cnt <= 0;
end
else if (m_reset)
begin
rst_cnt <= rst_cnt + 1'b1;
end
always @(posedge clk)
begin
if (tx_state == TX_IDLE)
m_enable = 0;
else if (tx_state == TX_PAYLOAD1)
m_enable = 1;
end
assign dc[6:4] = {op_decomp,op_comp,op_copy1};
assign dc[3:0] = 'b0;
assign dc[23:7] = 'b0;
generate if (C_ENABLE)
begin
mod u_mod(
.m_src_getn (m_src_getn),
.m_dst_putn (m_dst_putn),
.m_dst (m_dst[63:0]),
.m_dst_last (m_dst_last),
.m_endn (m_endn),
.m_cap (m_cap[7:0]),
.wb_clk_i (clk),
.m_reset (m_reset),
.m_enable (m_enable),
.dc (dc[23:0]),
.m_src (m_src[63:0]),
.m_src_last (m_src_last),
.m_src_empty (m_src_empty),
.m_src_almost_empty (m_src_almost_empty),
.m_dst_almost_full (m_dst_almost_full),
.m_dst_full (m_dst_full));
ch u_ch(
.src_stop (src_stop),
.dst_stop (dst_stop),
.src_start (src_start),
.dst_start (dst_start),
.src_end (src_end),
.dst_end (dst_end),
.src_dat_i (),
.dst_dat_i (dst_dat_i),
.src_dat64_i (),
.dst_dat64_i (dst_dat64_i),
.m_src (m_src[63:0]),
.m_src_last (m_src_last),
.m_src_almost_empty (m_src_almost_empty),
.m_src_empty (m_src_empty),
.m_dst_almost_full (m_dst_almost_full),
.m_dst_full (m_dst_full),
.ocnt (ocnt[15:0]),
.wb_clk_i (clk),
.wb_rst_i (),
.src_xfer (src_xfer),
.dst_xfer (dst_xfer),
.src_last (src_last),
.dst_last (dst_last),
.src_dat_o (data0),
.dst_dat_o (),
.src_dat64_o (data1),
.dst_dat64_o (),
.dc (dc[23:0]),
.m_reset (m_reset),
.m_src_getn (m_src_getn),
.m_dst_putn (m_dst_putn),
.m_dst (m_dst[63:0]),
.m_dst_last (m_dst_last),
.m_endn (m_endn));
end
endgenerate
ll_crc
ll_crc(
.crc_tx (crc_tx[31:0]),
.crc_rx (crc_rx[31:0]),
.clk (clk),
.rst_n (~m_reset),
.LLDMARXD (LLDMARXD[31:0]),
.LLDMARXREM (LLDMARXREM[3:0]),
.LLDMARXSOFN (LLDMARXSOFN),
.LLDMARXEOFN (LLDMARXEOFN),
.LLDMARXSOPN (LLDMARXSOPN),
.LLDMARXEOPN (LLDMARXEOPN),
.LLDMARXSRCRDYN (LLDMARXSRCRDYN),
.DMALLRXDSTRDYN (DMALLRXDSTRDYN),
.DMALLTXD (DMALLTXD[31:0]),
.DMALLTXREM (DMALLTXREM[3:0]),
.DMALLTXSOFN (DMALLTXSOFN),
.DMALLTXEOFN (DMALLTXEOFN),
.DMALLTXSOPN (DMALLTXSOPN),
.DMALLTXEOPN (DMALLTXEOPN),
.DMALLTXSRCRDYN (DMALLTXSRCRDYN),
.LLDMATXDSTRDYN (LLDMATXDSTRDYN));
reg dcr_plback;
reg [0:31] comp2dcr_data;
always @(posedge plb_dcrclk)
begin
if (plb_dcrrst)
begin
dcr_plback <= #1 1'b0;
end
else if (plb_dcrread || plb_dcrwrite)
begin
dcr_plback <= #1 1'b1;
end
else
begin
dcr_plback <= #1 1'b0;
end
end
always @(posedge plb_dcrclk)
begin
dcr_plbdbusin <= #1 comp2dcr_data;
end
always @(*)
begin
comp2dcr_data = 32'h0;
case (plb_dcrabus[6:9])
4'h0: begin
comp2dcr_data[0:3] = tx_state;
comp2dcr_data[4] = DMALLTXSRCRDYN;
comp2dcr_data[5] = LLDMATXDSTRDYN;
comp2dcr_data[6] = DMALLTXSOFN;
comp2dcr_data[7] = DMALLTXEOFN;
comp2dcr_data[30] = m_src_last;
comp2dcr_data[31] = src_last;
end
4'h1: begin
comp2dcr_data[0:3] = rx_state;
comp2dcr_data[4] = LLDMARXSRCRDYN;
comp2dcr_data[5] = DMALLRXDSTRDYN;
comp2dcr_data[6] = LLDMARXSOPN;
comp2dcr_data[7] = LLDMARXEOPN;
comp2dcr_data[27] = dst_start;
comp2dcr_data[28] = src_start;
comp2dcr_data[30] = m_endn;
comp2dcr_data[31] = dst_end;
end
4'h2: begin
comp2dcr_data[0:3] = flag;
comp2dcr_data[22:31] = task_index;
end
4'h3: begin
comp2dcr_data[0:3] = tx_busy;
comp2dcr_data[4:7] = tx_end_rdy;
comp2dcr_data[28:31] = rx_end;
end
4'h4: begin
comp2dcr_data[0:15] = ocnt;
comp2dcr_data[16:31] = len_cnt;
end
4'h5: begin
comp2dcr_data = src_len;
end
4'h6: begin
comp2dcr_data[0] = m_dst_putn;
comp2dcr_data[1] = m_dst_last;
comp2dcr_data[2] = m_dst_almost_full;
comp2dcr_data[3] = m_dst_full;
comp2dcr_data[4] = m_src_last;
comp2dcr_data[5] = m_src_empty;
comp2dcr_data[6] = m_src_almost_empty;
comp2dcr_data[7] = m_enable;
end
4'h7: begin
end
4'h8: begin
end
4'he: begin
comp2dcr_data[0:31] = C_VERSION;
end
4'hf: begin
comp2dcr_data[0:31] = 32'haa55_55aa;
end
endcase
end
always @(posedge plb_dcrclk)
begin
if (plb_dcrwrite && plb_dcrabus == 10'h00)
begin
LLDMARSTENGINEREQ <= plb_dcrdbusout[31];
end
else
begin
LLDMARSTENGINEREQ <= 1'b0;
end
end
endmodule | module comp_unit(
LLDMARSTENGINEREQ, LLDMARXD, LLDMARXREM, LLDMARXSOFN, LLDMARXEOFN,
LLDMARXSOPN, LLDMARXEOPN, LLDMARXSRCRDYN, LLDMATXDSTRDYN, src_last,
dst_end, dst_start, dcr_plback, dcr_plbdbusin,
CPMDMALLCLK, DMALLRSTENGINEACK, DMALLRXDSTRDYN, DMALLTXD,
DMALLTXREM, DMALLTXSOFN, DMALLTXEOFN, DMALLTXSOPN, DMALLTXEOPN,
DMALLTXSRCRDYN, DMATXIRQ, DMARXIRQ, plb_dcrabus, plb_dcrclk,
plb_dcrdbusout, plb_dcrread, plb_dcrrst, plb_dcrwrite
); |
parameter C_VERSION = 32'hdead_dead;
parameter C_ENABLE = 0;
(* PERIOD = "5000ps" *)
input CPMDMALLCLK;
output LLDMARSTENGINEREQ;
input DMALLRSTENGINEACK;
output [31:0] LLDMARXD;
output [3:0] LLDMARXREM;
output LLDMARXSOFN;
output LLDMARXEOFN;
output LLDMARXSOPN;
output LLDMARXEOPN;
output LLDMARXSRCRDYN;
input DMALLRXDSTRDYN;
input [31:0] DMALLTXD;
input [3:0] DMALLTXREM;
input DMALLTXSOFN;
input DMALLTXEOFN;
input DMALLTXSOPN;
input DMALLTXEOPN;
input DMALLTXSRCRDYN;
output LLDMATXDSTRDYN;
input DMATXIRQ;
input DMARXIRQ;
output src_last;
output dst_end;
output dst_start;
input [0:9] plb_dcrabus;
input plb_dcrclk;
input [0:31] plb_dcrdbusout;
input plb_dcrread;
input plb_dcrrst;
input plb_dcrwrite;
output dcr_plback;
output [0:31] dcr_plbdbusin;
parameter TX_IDLE = 4'h0;
parameter TX_HEAD1 = 4'h1;
parameter TX_HEAD2 = 4'h2;
parameter TX_HEAD3 = 4'h3;
parameter TX_HEAD4 = 4'h4;
parameter TX_HEAD5 = 4'h5;
parameter TX_HEAD6 = 4'h6;
parameter TX_HEAD7 = 4'h7;
parameter TX_PAYLOAD = 4'h8;
parameter TX_PAYLOAD1 = 4'h9;
parameter TX_COPY = 4'ha;
parameter TX_END = 4'hb;
parameter RX_IDLE = 4'h0;
parameter RX_HEAD0 = 4'h1;
parameter RX_HEAD1 = 4'h2;
parameter RX_HEAD2 = 4'h3;
parameter RX_HEAD3 = 4'h4;
parameter RX_HEAD4 = 4'h5;
parameter RX_HEAD5 = 4'h6;
parameter RX_HEAD6 = 4'h7;
parameter RX_HEAD7 = 4'h8;
parameter RX_PAYLOAD = 4'h9;
parameter RX_PAYLOAD1 = 4'ha;
parameter RX_COPY = 4'hb;
parameter RX_END = 4'hc;
wire clk;
wire rst_n;
reg [3:0] tx_state;
reg [3:0] tx_state_n;
reg [3:0] rx_state;
reg [3:0] rx_state_n;
wire op_copy;
wire op_copy1;
wire op_comp;
wire op_decomp;
wire [3:0] DMALLTXREM_r;
reg [31:29] flag;
reg [31:0] src_len;
reg [31:0] data0;
reg [31:0] data1;
reg [31:0] rx_data_comp;
reg [3:0] rem;
wire DMALLRSTENGINEACK;
wire LLDMATXDSTRDYN;
reg [31:0] LLDMARXD_r;
reg [3:0] LLDMARXREM_r;
reg LLDMARXSRCRDYN_r;
reg LLDMARXSOPN_r;
reg LLDMARXEOPN_r;
reg LLDMARXEOFN_r;
reg rx_sof_r_n;
reg m_reset;
reg [0:31] dcr_plbdbusin;
wire [31:0] crc_rx;
wire [31:0] crc_tx;
wire [31:0] dst_dat_i;
wire [31:0] dst_dat64_i;
wire src_start;
wire dst_start;
wire dst_end;
wire dst_xfer;
reg src_xfer;
reg src_last;
wire [15:0] ocnt;
reg reset_n;
reg tx_busy;
reg rx_end;
reg [15:0] len_cnt;
wire Rst = ~rst_n;
wire SYS_Clk = clk;
wire [31:0] rx_data;
wire [3:0] rx_rem;
wire rx_sof_n;
wire rx_eof_n;
wire rx_sop_n;
wire rx_eop_n;
wire rx_src_rdy_n;
wire rx_dst_rdy_n;
wire [31:0] tx_data;
wire [31:0] tx_rem;
wire tx_sof_n;
wire tx_eof_n;
wire tx_sop_n;
wire tx_eop_n;
wire tx_src_rdy_n;
wire tx_dst_rdy_n;
reg tx_end_rdy;
reg [9:0] task_index;
wire soft_reset;
wire src_stop;
reg LLDMARSTENGINEREQ;
assign LLDMARXD = LLDMARXD_r;
assign LLDMARXREM = LLDMARXREM_r;
assign LLDMARXSOFN = rx_sof_r_n;
assign LLDMARXEOFN = LLDMARXEOFN_r;
assign LLDMARXSOPN = LLDMARXSOPN_r;
assign LLDMARXEOPN = LLDMARXEOPN_r;
assign LLDMARXSRCRDYN = LLDMARXSRCRDYN_r;
assign tx_data = DMALLTXD;
assign tx_rem = DMALLTXREM;
assign tx_sof_n = DMALLTXSOFN;
assign tx_eof_n = DMALLTXEOFN;
assign tx_sop_n = DMALLTXSOPN;
assign tx_eop_n = DMALLTXEOPN;
assign tx_src_rdy_n= DMALLTXSRCRDYN;
assign LLDMATXDSTRDYN = (~src_start && (op_comp || op_decomp || op_copy1)) &&
(tx_end_rdy || tx_busy) || tx_busy;
assign clk = CPMDMALLCLK;
assign rst_n = ~(DMALLRSTENGINEACK || LLDMARSTENGINEREQ);
assign op_copy1 = flag[29];
assign op_copy0 = 0;
assign op_decomp = flag[30];
assign op_comp = flag[31];
always @(posedge clk)
if (!rst_n)
tx_state <= TX_IDLE;
else
tx_state <= tx_state_n;
always @(*)
begin
tx_state_n = tx_state;
case (tx_state)
TX_IDLE : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXSOFN)
tx_state_n = TX_HEAD1;
else
tx_state_n = TX_IDLE;
end else
tx_state_n = TX_IDLE;
end
TX_HEAD1 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD2;
end else
tx_state_n = TX_HEAD1;
end
TX_HEAD2 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD3;
end else
tx_state_n = TX_HEAD2;
end
TX_HEAD3 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD4;
end else
tx_state_n = TX_HEAD3;
end
TX_HEAD4 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD5;
end else
tx_state_n = TX_HEAD4;
end
TX_HEAD5 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD6;
end else
tx_state_n = TX_HEAD5;
end
TX_HEAD6 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
tx_state_n = TX_HEAD7;
end else
tx_state_n = TX_HEAD6;
end
TX_HEAD7 : begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (op_copy)
tx_state_n = TX_COPY;
else
tx_state_n = TX_PAYLOAD;
end else
tx_state_n = TX_HEAD7;
end
TX_PAYLOAD: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD1;
end else if (rx_end)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD;
end
TX_PAYLOAD1: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD;
end else if (rx_end)
tx_state_n = TX_END;
else
tx_state_n = TX_PAYLOAD1;
end
TX_COPY: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN)
tx_state_n = TX_END;
else
tx_state_n = TX_COPY;
end else
tx_state_n = TX_COPY;
end
TX_END: begin
if (m_reset)
tx_state_n = TX_IDLE;
else
tx_state_n = TX_END;
end
endcase
end
always @(posedge clk)
if (!rst_n) begin
tx_end_rdy <= 1;
data0 <= 32'h0;
data1 <= 32'h0;
flag <= 3'h0;
src_last <= 1'h0;
src_len <= 32'h0;
src_xfer <= 1'h0;
task_index <= 10'h0;
tx_busy <= 1'h0;
end else begin
case (tx_state)
TX_IDLE : begin
tx_end_rdy <= 1;
src_last <= 0;
src_xfer <= 0;
tx_busy <= 0;
flag <= 3'h0;
end
TX_HEAD1 : begin
end
TX_HEAD2 : begin
end
TX_HEAD3 : begin
end
TX_HEAD4 : begin
flag <= DMALLTXD[31:29];
end
TX_HEAD5 : begin
src_len <= DMALLTXD;
end
TX_HEAD6 : begin
task_index <= DMALLTXD[9:0];
end
TX_HEAD7 : begin
end
TX_PAYLOAD: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
if (!DMALLTXEOPN) begin
src_xfer <= 1;
data1 <= 0;
case (DMALLTXREM)
4'b0000 : data0 <= DMALLTXD;
4'b0001 : data0 <= {DMALLTXD[31:8],8'h0};
4'b0011 : data0 <= {DMALLTXD[31:16],16'h0};
4'b0111 : data0 <= {DMALLTXD[31:24],24'h0};
endcase
end else begin
src_xfer <= 0;
data0 <= DMALLTXD;
end
end else begin
src_xfer <= 0;
end
end
TX_PAYLOAD1: begin
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN) begin
src_xfer <= 1;
if (!DMALLTXEOPN) begin
case (DMALLTXREM)
4'b0000 : data1 <= DMALLTXD;
4'b0001 : data1 <= {DMALLTXD[31:8],8'h0};
4'b0011 : data1 <= {DMALLTXD[31:16],16'h0};
4'b0111 : data1 <= {DMALLTXD[31:24],24'h0};
endcase
end else begin
data1 <= DMALLTXD;
end
end else begin
src_xfer <= 0;
end
end
TX_COPY: begin
end
TX_END : begin
tx_end_rdy <= 0;
if (!DMALLTXSRCRDYN && !LLDMATXDSTRDYN
&& !DMALLTXEOFN) begin
src_last <= 1;
src_xfer <= 1;
tx_busy <= 1;
end else begin
src_last <= 0;
src_xfer <= 0;
end
end
endcase
end
always @(posedge clk)
if (!rst_n)
rx_state <= RX_IDLE;
else
rx_state <= rx_state_n;
always @(*)
begin
rx_state_n = rx_state;
case (rx_state)
RX_IDLE: begin
if (!DMALLRXDSTRDYN && !m_reset) begin
if (op_copy)
rx_state_n = RX_COPY;
else if (dst_start && (op_comp || op_decomp || op_copy1))
rx_state_n = RX_PAYLOAD;
else
rx_state_n = RX_IDLE;
end else
rx_state_n = RX_IDLE;
end
RX_HEAD0 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD1;
end else
rx_state_n = RX_HEAD0;
end
RX_HEAD1 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD2;
end else
rx_state_n = RX_HEAD1;
end
RX_HEAD2 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD3;
end else
rx_state_n = RX_HEAD2;
end
RX_HEAD3 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD4;
end else
rx_state_n = RX_HEAD3;
end
RX_HEAD4 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD5;
end else
rx_state_n = RX_HEAD4;
end
RX_HEAD5 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD6;
end else
rx_state_n = RX_HEAD5;
end
RX_HEAD6 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_HEAD7;
end else
rx_state_n = RX_HEAD6;
end
RX_HEAD7 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_END;
end else
rx_state_n = RX_HEAD7;
end
RX_PAYLOAD: begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
rx_state_n = RX_PAYLOAD1;
end else begin
rx_state_n = RX_PAYLOAD;
end
end
RX_PAYLOAD1: begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
if (ocnt > src_len[18:3])
rx_state_n = RX_HEAD0;
else if ((ocnt == len_cnt) && dst_start)
rx_state_n = RX_HEAD0;
else
rx_state_n = RX_PAYLOAD;
end else begin
rx_state_n = RX_PAYLOAD1;
end
end
RX_COPY: begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
if (!LLDMARXEOFN)
rx_state_n = RX_END;
else
rx_state_n = RX_COPY;
end else begin
rx_state_n = RX_COPY;
end
end
RX_END: begin
if(m_reset)
rx_state_n = RX_IDLE;
else
rx_state_n = RX_END;
end
endcase
end
reg cpl_status;
always @(posedge clk)
if (!rst_n) begin
rx_sof_r_n <= 1;
LLDMARXSOPN_r <= 1;
LLDMARXEOPN_r <= 1;
LLDMARXEOFN_r <= 1;
LLDMARXD_r <= 32'h0;
LLDMARXREM_r <= 4'h0;
LLDMARXSRCRDYN_r <= 1'h1;
cpl_status <= 1'h0;
rx_data_comp <= 32'h0;
rx_end <= 1'h0;
end else begin
case (rx_state)
RX_IDLE: begin
rx_sof_r_n <= 1;
LLDMARXSOPN_r <= 1;
LLDMARXEOPN_r <= 1;
LLDMARXEOFN_r <= 1;
cpl_status <= 1'h0;
rx_end <= 1'h0;
reset_n <= 1'b1;
if (dst_start && (op_comp || op_decomp || op_copy1))begin
if (!DMALLRXDSTRDYN && !m_reset) begin
LLDMARXSRCRDYN_r <= 0;
rx_sof_r_n <= 0;
end else begin
LLDMARXSRCRDYN_r <= 1;
rx_sof_r_n <= 1;
end
end
end
RX_HEAD0 : begin
LLDMARXSRCRDYN_r <= 0;
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXREM_r <= 4'h0;
LLDMARXSOPN_r <= 1;
LLDMARXEOPN_r <= 1;
end
end
RX_HEAD1 : begin
end
RX_HEAD2 : begin
end
RX_HEAD3 : begin
rx_end <= 1;
LLDMARXSRCRDYN_r <= !tx_busy;
end
RX_HEAD4 : begin
LLDMARXSRCRDYN_r <= !tx_busy;
LLDMARXD_r[31:29]<= flag;
LLDMARXD_r[28] <= cpl_status;
LLDMARXD_r[27:11]<= 0;
LLDMARXD_r[10] <= 1'b1;
LLDMARXD_r[9:0] <= crc_tx[9:0];
end
RX_HEAD5 : begin
if (op_copy)
LLDMARXD_r <= src_len;
else
LLDMARXD_r <= {13'h0,ocnt,3'h0};
end
RX_HEAD6 : begin
LLDMARXD_r[31:10]<= crc_tx[31:10];
LLDMARXD_r[9:0] <= task_index;
end
RX_HEAD7 : begin
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXEOFN_r <= 0;
LLDMARXD_r<= crc_rx;
end
end
RX_PAYLOAD: begin
rx_sof_r_n <= 1;
LLDMARXEOPN_r <= 1;
LLDMARXSRCRDYN_r <= ~dst_start;
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXSOPN_r <= rx_sof_r_n;
LLDMARXD_r <= dst_dat64_i;
rx_data_comp <= dst_dat_i;
end else begin
end
end
RX_PAYLOAD1: begin
LLDMARXSRCRDYN_r <= ~dst_start;
if (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN) begin
LLDMARXSOPN_r <= 1;
LLDMARXD_r <= rx_data_comp;
if (ocnt > src_len[18:3]) begin
LLDMARXREM_r <= 4'h7;
cpl_status <= 0;
LLDMARXEOPN_r <= 0;
end else if ((ocnt == len_cnt) && dst_start) begin
LLDMARXREM_r <= 4'h0;
cpl_status <= 1;
LLDMARXEOPN_r <= 0;
end else begin
LLDMARXEOPN_r <= 1;
end
end
end
RX_COPY: begin
end
RX_END: begin
LLDMARXREM_r <= 0;
rx_end <= 1;
if(LLDMARXEOFN && tx_busy)
reset_n <= 1'b0;
else
reset_n <= 1'b1;
if(!LLDMARXSRCRDYN && !DMALLRXDSTRDYN)
begin
LLDMARXEOFN_r <= 1;
LLDMARXSRCRDYN_r <= 1;
end
end
endcase
end
always @(posedge clk)
if (m_reset)
len_cnt <= 0;
else if (dst_xfer)
len_cnt <= len_cnt + 1;
assign dst_xfer = (rx_state == RX_PAYLOAD) && (!LLDMARXSRCRDYN && !DMALLRXDSTRDYN);
wire m_src_getn;
wire m_dst_putn;
wire [63:0] m_dst;
wire m_dst_last;
wire m_endn;
wire [7:0] m_cap;
reg [2:0] rst_cnt;
reg m_enable;
wire [23:0] dc;
wire [63:0] m_src;
wire m_src_last;
wire m_src_empty;
wire m_src_almost_empty;
wire m_dst_almost_full;
wire m_dst_full;
wire src_end;
always @(posedge clk)
if (~rst_n)
begin
m_reset <= 1;
end
else if (~reset_n)
begin
m_reset <= 1;
end
else if (rst_cnt == 3'h6)
begin
m_reset <= 0;
end
always @(posedge clk)
if (~rst_n)
begin
rst_cnt <= 0;
end
else if (~reset_n)
begin
rst_cnt <= 0;
end
else if (m_reset)
begin
rst_cnt <= rst_cnt + 1'b1;
end
always @(posedge clk)
begin
if (tx_state == TX_IDLE)
m_enable = 0;
else if (tx_state == TX_PAYLOAD1)
m_enable = 1;
end
assign dc[6:4] = {op_decomp,op_comp,op_copy1};
assign dc[3:0] = 'b0;
assign dc[23:7] = 'b0;
generate if (C_ENABLE)
begin
mod u_mod(
.m_src_getn (m_src_getn),
.m_dst_putn (m_dst_putn),
.m_dst (m_dst[63:0]),
.m_dst_last (m_dst_last),
.m_endn (m_endn),
.m_cap (m_cap[7:0]),
.wb_clk_i (clk),
.m_reset (m_reset),
.m_enable (m_enable),
.dc (dc[23:0]),
.m_src (m_src[63:0]),
.m_src_last (m_src_last),
.m_src_empty (m_src_empty),
.m_src_almost_empty (m_src_almost_empty),
.m_dst_almost_full (m_dst_almost_full),
.m_dst_full (m_dst_full));
ch u_ch(
.src_stop (src_stop),
.dst_stop (dst_stop),
.src_start (src_start),
.dst_start (dst_start),
.src_end (src_end),
.dst_end (dst_end),
.src_dat_i (),
.dst_dat_i (dst_dat_i),
.src_dat64_i (),
.dst_dat64_i (dst_dat64_i),
.m_src (m_src[63:0]),
.m_src_last (m_src_last),
.m_src_almost_empty (m_src_almost_empty),
.m_src_empty (m_src_empty),
.m_dst_almost_full (m_dst_almost_full),
.m_dst_full (m_dst_full),
.ocnt (ocnt[15:0]),
.wb_clk_i (clk),
.wb_rst_i (),
.src_xfer (src_xfer),
.dst_xfer (dst_xfer),
.src_last (src_last),
.dst_last (dst_last),
.src_dat_o (data0),
.dst_dat_o (),
.src_dat64_o (data1),
.dst_dat64_o (),
.dc (dc[23:0]),
.m_reset (m_reset),
.m_src_getn (m_src_getn),
.m_dst_putn (m_dst_putn),
.m_dst (m_dst[63:0]),
.m_dst_last (m_dst_last),
.m_endn (m_endn));
end
endgenerate
ll_crc
ll_crc(
.crc_tx (crc_tx[31:0]),
.crc_rx (crc_rx[31:0]),
.clk (clk),
.rst_n (~m_reset),
.LLDMARXD (LLDMARXD[31:0]),
.LLDMARXREM (LLDMARXREM[3:0]),
.LLDMARXSOFN (LLDMARXSOFN),
.LLDMARXEOFN (LLDMARXEOFN),
.LLDMARXSOPN (LLDMARXSOPN),
.LLDMARXEOPN (LLDMARXEOPN),
.LLDMARXSRCRDYN (LLDMARXSRCRDYN),
.DMALLRXDSTRDYN (DMALLRXDSTRDYN),
.DMALLTXD (DMALLTXD[31:0]),
.DMALLTXREM (DMALLTXREM[3:0]),
.DMALLTXSOFN (DMALLTXSOFN),
.DMALLTXEOFN (DMALLTXEOFN),
.DMALLTXSOPN (DMALLTXSOPN),
.DMALLTXEOPN (DMALLTXEOPN),
.DMALLTXSRCRDYN (DMALLTXSRCRDYN),
.LLDMATXDSTRDYN (LLDMATXDSTRDYN));
reg dcr_plback;
reg [0:31] comp2dcr_data;
always @(posedge plb_dcrclk)
begin
if (plb_dcrrst)
begin
dcr_plback <= #1 1'b0;
end
else if (plb_dcrread || plb_dcrwrite)
begin
dcr_plback <= #1 1'b1;
end
else
begin
dcr_plback <= #1 1'b0;
end
end
always @(posedge plb_dcrclk)
begin
dcr_plbdbusin <= #1 comp2dcr_data;
end
always @(*)
begin
comp2dcr_data = 32'h0;
case (plb_dcrabus[6:9])
4'h0: begin
comp2dcr_data[0:3] = tx_state;
comp2dcr_data[4] = DMALLTXSRCRDYN;
comp2dcr_data[5] = LLDMATXDSTRDYN;
comp2dcr_data[6] = DMALLTXSOFN;
comp2dcr_data[7] = DMALLTXEOFN;
comp2dcr_data[30] = m_src_last;
comp2dcr_data[31] = src_last;
end
4'h1: begin
comp2dcr_data[0:3] = rx_state;
comp2dcr_data[4] = LLDMARXSRCRDYN;
comp2dcr_data[5] = DMALLRXDSTRDYN;
comp2dcr_data[6] = LLDMARXSOPN;
comp2dcr_data[7] = LLDMARXEOPN;
comp2dcr_data[27] = dst_start;
comp2dcr_data[28] = src_start;
comp2dcr_data[30] = m_endn;
comp2dcr_data[31] = dst_end;
end
4'h2: begin
comp2dcr_data[0:3] = flag;
comp2dcr_data[22:31] = task_index;
end
4'h3: begin
comp2dcr_data[0:3] = tx_busy;
comp2dcr_data[4:7] = tx_end_rdy;
comp2dcr_data[28:31] = rx_end;
end
4'h4: begin
comp2dcr_data[0:15] = ocnt;
comp2dcr_data[16:31] = len_cnt;
end
4'h5: begin
comp2dcr_data = src_len;
end
4'h6: begin
comp2dcr_data[0] = m_dst_putn;
comp2dcr_data[1] = m_dst_last;
comp2dcr_data[2] = m_dst_almost_full;
comp2dcr_data[3] = m_dst_full;
comp2dcr_data[4] = m_src_last;
comp2dcr_data[5] = m_src_empty;
comp2dcr_data[6] = m_src_almost_empty;
comp2dcr_data[7] = m_enable;
end
4'h7: begin
end
4'h8: begin
end
4'he: begin
comp2dcr_data[0:31] = C_VERSION;
end
4'hf: begin
comp2dcr_data[0:31] = 32'haa55_55aa;
end
endcase
end
always @(posedge plb_dcrclk)
begin
if (plb_dcrwrite && plb_dcrabus == 10'h00)
begin
LLDMARSTENGINEREQ <= plb_dcrdbusout[31];
end
else
begin
LLDMARSTENGINEREQ <= 1'b0;
end
end
endmodule | 8 |
138,088 | data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/fiforam.v | 8,175,167 | fiforam.v | v | 38 | 37 | [] | [] | [] | null | line:10: before: "." | null | 1: b"%Error: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/fiforam.v:14: Cannot find file containing module: 'RAMB16_S36_S36'\nRAMB16_S36_S36 ram (\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/RAMB16_S36_S36\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/RAMB16_S36_S36.v\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/RAMB16_S36_S36.sv\n RAMB16_S36_S36\n RAMB16_S36_S36.v\n RAMB16_S36_S36.sv\n obj_dir/RAMB16_S36_S36\n obj_dir/RAMB16_S36_S36.v\n obj_dir/RAMB16_S36_S36.sv\n%Error: Exiting due to 1 error(s)\n" | 301,771 | module | module fiforam (
input clk,
input we,
input [8:0] addr0,
input [8:0] addr1,
input [35:0] wr_data0,
output [35:0] rd_data1
);
defparam ram.SRVAL_A = 36'h00000000;
wire [35:0] rd_data0;
RAMB16_S36_S36 ram (
.CLKA(clk),
.DIA(wr_data0[31:0]),
.DIPA(wr_data0[35:32]),
.ADDRA(addr0[8:0]),
.WEA(we),
.ENA(1'b1),
.SSRA(1'b0),
.DOA(rd_data0[31:0]),
.DOPA(rd_data0[35:32]),
.CLKB(clk),
.DIB(32'h0),
.DIPB(4'h0),
.ADDRB(addr1[8:0]),
.WEB(1'b0),
.ENB(1'b1),
.SSRB(1'b0),
.DOB(rd_data1[31:0]),
.DOPB(rd_data1[35:32])
);
endmodule | module fiforam (
input clk,
input we,
input [8:0] addr0,
input [8:0] addr1,
input [35:0] wr_data0,
output [35:0] rd_data1
); |
defparam ram.SRVAL_A = 36'h00000000;
wire [35:0] rd_data0;
RAMB16_S36_S36 ram (
.CLKA(clk),
.DIA(wr_data0[31:0]),
.DIPA(wr_data0[35:32]),
.ADDRA(addr0[8:0]),
.WEA(we),
.ENA(1'b1),
.SSRA(1'b0),
.DOA(rd_data0[31:0]),
.DOPA(rd_data0[35:32]),
.CLKB(clk),
.DIB(32'h0),
.DIPB(4'h0),
.ADDRB(addr1[8:0]),
.WEB(1'b0),
.ENB(1'b1),
.SSRB(1'b0),
.DOB(rd_data1[31:0]),
.DOPB(rd_data1[35:32])
);
endmodule | 8 |
138,090 | data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/ll_crc.v | 8,175,167 | ll_crc.v | v | 157 | 79 | [] | [] | [] | [(1, 150)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/ll_crc.v:130: Signal definition not found, creating implicitly: \'crc_rst\'\n : ... Suggested alternative: \'crc_rx\'\n assign crc_rst = ~rst_n;\n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/ll_crc.v:134: Cannot find file containing module: \'crc\'\n crc\n ^~~\n ... Looked in:\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/crc\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/crc.v\n data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog,data/full_repos/permissive/8175167/crc.sv\n crc\n crc.v\n crc.sv\n obj_dir/crc\n obj_dir/crc.v\n obj_dir/crc.sv\n%Error: data/full_repos/permissive/8175167/pcores/comp_unit_v1_00_a/hdl/verilog/ll_crc.v:142: Cannot find file containing module: \'crc\'\n crc\n ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 301,775 | module | module ll_crc(
crc_tx, crc_rx,
clk, rst_n, LLDMARXD, LLDMARXREM, LLDMARXSOFN, LLDMARXEOFN,
LLDMARXSOPN, LLDMARXEOPN, LLDMARXSRCRDYN, DMALLRXDSTRDYN, DMALLTXD,
DMALLTXREM, DMALLTXSOFN, DMALLTXEOFN, DMALLTXSOPN, DMALLTXEOPN,
DMALLTXSRCRDYN, LLDMATXDSTRDYN
);
input clk;
input rst_n;
input [31:0] LLDMARXD;
input [3:0] LLDMARXREM;
input LLDMARXSOFN;
input LLDMARXEOFN;
input LLDMARXSOPN;
input LLDMARXEOPN;
input LLDMARXSRCRDYN;
input DMALLRXDSTRDYN;
input [31:0] DMALLTXD;
input [3:0] DMALLTXREM;
input DMALLTXSOFN;
input DMALLTXEOFN;
input DMALLTXSOPN;
input DMALLTXEOPN;
input DMALLTXSRCRDYN;
input LLDMATXDSTRDYN;
output [31:0] crc_tx;
output [31:0] crc_rx;
reg tx_start;
reg rx_start;
reg tx_data_valid;
reg rx_data_valid;
reg [31:0] tx_data;
reg [31:0] rx_data;
wire [31:0] data_in;
always @(posedge clk)
begin
if (!rst_n)
begin
tx_start <= 1'b0;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXSOPN)
begin
tx_start <= 1'b1;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXEOPN)
begin
tx_start <= 1'b0;
end
end
always @(posedge clk)
begin
if (!rst_n)
begin
rx_start <= 1'b0;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXSOPN)
begin
rx_start <= 1'b1;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXEOPN)
begin
rx_start <= 1'b0;
end
end
always @(posedge clk)
begin
if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN)
tx_data <= DMALLTXD;
end
always @(posedge clk)
begin
if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN)
rx_data <= LLDMARXD;
end
always @(posedge clk)
begin
if (!rst_n)
begin
tx_data_valid = 1'b0;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXSOPN)
begin
tx_data_valid = 1'b1;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && tx_start)
begin
tx_data_valid = 1'b1;
end
else
begin
tx_data_valid = 1'b0;
end
end
always @(posedge clk)
begin
if (!rst_n)
begin
rx_data_valid = 1'b0;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXSOPN)
begin
rx_data_valid = 1'b1;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && rx_start)
begin
rx_data_valid = 1'b1;
end
else
begin
rx_data_valid = 1'b0;
end
end
assign crc_rst = ~rst_n;
wire [31:0] crc_tx;
wire [31:0] crc_rx;
crc
crc0(.crc_out(crc_tx),
.data_in(tx_data),
.data_valid(tx_data_valid),
.clk (clk),
.crc_rst (crc_rst));
crc
crc1(.crc_out(crc_rx),
.data_in(rx_data),
.data_valid(rx_data_valid),
.clk (clk),
.crc_rst (crc_rst));
endmodule | module ll_crc(
crc_tx, crc_rx,
clk, rst_n, LLDMARXD, LLDMARXREM, LLDMARXSOFN, LLDMARXEOFN,
LLDMARXSOPN, LLDMARXEOPN, LLDMARXSRCRDYN, DMALLRXDSTRDYN, DMALLTXD,
DMALLTXREM, DMALLTXSOFN, DMALLTXEOFN, DMALLTXSOPN, DMALLTXEOPN,
DMALLTXSRCRDYN, LLDMATXDSTRDYN
); |
input clk;
input rst_n;
input [31:0] LLDMARXD;
input [3:0] LLDMARXREM;
input LLDMARXSOFN;
input LLDMARXEOFN;
input LLDMARXSOPN;
input LLDMARXEOPN;
input LLDMARXSRCRDYN;
input DMALLRXDSTRDYN;
input [31:0] DMALLTXD;
input [3:0] DMALLTXREM;
input DMALLTXSOFN;
input DMALLTXEOFN;
input DMALLTXSOPN;
input DMALLTXEOPN;
input DMALLTXSRCRDYN;
input LLDMATXDSTRDYN;
output [31:0] crc_tx;
output [31:0] crc_rx;
reg tx_start;
reg rx_start;
reg tx_data_valid;
reg rx_data_valid;
reg [31:0] tx_data;
reg [31:0] rx_data;
wire [31:0] data_in;
always @(posedge clk)
begin
if (!rst_n)
begin
tx_start <= 1'b0;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXSOPN)
begin
tx_start <= 1'b1;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXEOPN)
begin
tx_start <= 1'b0;
end
end
always @(posedge clk)
begin
if (!rst_n)
begin
rx_start <= 1'b0;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXSOPN)
begin
rx_start <= 1'b1;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXEOPN)
begin
rx_start <= 1'b0;
end
end
always @(posedge clk)
begin
if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN)
tx_data <= DMALLTXD;
end
always @(posedge clk)
begin
if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN)
rx_data <= LLDMARXD;
end
always @(posedge clk)
begin
if (!rst_n)
begin
tx_data_valid = 1'b0;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXSOPN)
begin
tx_data_valid = 1'b1;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && tx_start)
begin
tx_data_valid = 1'b1;
end
else
begin
tx_data_valid = 1'b0;
end
end
always @(posedge clk)
begin
if (!rst_n)
begin
rx_data_valid = 1'b0;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXSOPN)
begin
rx_data_valid = 1'b1;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && rx_start)
begin
rx_data_valid = 1'b1;
end
else
begin
rx_data_valid = 1'b0;
end
end
assign crc_rst = ~rst_n;
wire [31:0] crc_tx;
wire [31:0] crc_rx;
crc
crc0(.crc_out(crc_tx),
.data_in(tx_data),
.data_valid(tx_data_valid),
.clk (clk),
.crc_rst (crc_rst));
crc
crc1(.crc_out(crc_rx),
.data_in(rx_data),
.data_valid(rx_data_valid),
.clk (clk),
.crc_rst (crc_rst));
endmodule | 8 |
138,092 | data/full_repos/permissive/81900704/output/vs/difficult_multi.v | 81,900,704 | difficult_multi.v | v | 95 | 110 | [] | [] | [] | [(2, 94)] | null | data/verilator_xmls/b768e567-4d03-46a4-bc1e-885ffc325700.xml | null | 301,778 | module | module difficult_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z;
output valid;
wire [8:0] min_value = 9'd180;
wire [8:0] max_weight = 9'd100;
wire [8:0] max_volume = 9'd100;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18
+ X * 9'd5
+ Y * 9'd0
+ Z * 9'd30;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0
+ X * 9'd21
+ Y * 9'd10
+ Z * 9'd13;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26
+ X * 9'd3
+ Y * 9'd11
+ Z * 9'd22;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | module difficult_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, valid); |
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z;
output valid;
wire [8:0] min_value = 9'd180;
wire [8:0] max_weight = 9'd100;
wire [8:0] max_volume = 9'd100;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18
+ X * 9'd5
+ Y * 9'd0
+ Z * 9'd30;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0
+ X * 9'd21
+ Y * 9'd10
+ Z * 9'd13;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26
+ X * 9'd3
+ Y * 9'd11
+ Z * 9'd22;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | 5 |
138,093 | data/full_repos/permissive/81900704/output/vs/grover01.v | 81,900,704 | grover01.v | v | 19 | 77 | [] | [] | [] | [(2, 18)] | null | data/verilator_xmls/c3e0eb1f-d6a6-4f1e-807b-43a9cfeae203.xml | null | 301,779 | module | module grover01 (A, B, valid);
input A, B;
output valid;
wire [3:0] min_value = 4'd8;
wire [3:0] max_weight = 4'd10;
wire [3:0] total_value =
A * 4'd2
+ B * 4'd9;
wire [3:0] total_weight =
A * 4'd9
+ B * 4'd2;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight));
endmodule | module grover01 (A, B, valid); |
input A, B;
output valid;
wire [3:0] min_value = 4'd8;
wire [3:0] max_weight = 4'd10;
wire [3:0] total_value =
A * 4'd2
+ B * 4'd9;
wire [3:0] total_weight =
A * 4'd9
+ B * 4'd2;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight));
endmodule | 5 |
138,094 | data/full_repos/permissive/81900704/output/vs/grover_compare.v | 81,900,704 | grover_compare.v | v | 6 | 36 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/2310f651-940e-4f5b-8e2e-8691d4b272af.xml | null | 301,780 | module | module grover_compare(A, B, valid);
input A, B;
output valid;
assign valid = A & (~B);
endmodule | module grover_compare(A, B, valid); |
input A, B;
output valid;
assign valid = A & (~B);
endmodule | 5 |
138,095 | data/full_repos/permissive/81900704/output/vs/grover_compare00.v | 81,900,704 | grover_compare00.v | v | 6 | 38 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/2e3ac3c2-2dfa-45ac-9c69-cbdf8de1f62d.xml | null | 301,781 | module | module grover_compare00(A, B, valid);
input A, B;
output valid;
assign valid = (~A) & (~B);
endmodule | module grover_compare00(A, B, valid); |
input A, B;
output valid;
assign valid = (~A) & (~B);
endmodule | 5 |
138,096 | data/full_repos/permissive/81900704/output/vs/grover_compare01.v | 81,900,704 | grover_compare01.v | v | 6 | 38 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/660c5774-c446-44f7-b04c-a3f7a6c5895f.xml | null | 301,782 | module | module grover_compare01(A, B, valid);
input A, B;
output valid;
assign valid = (~A) & B;
endmodule | module grover_compare01(A, B, valid); |
input A, B;
output valid;
assign valid = (~A) & B;
endmodule | 5 |
138,097 | data/full_repos/permissive/81900704/output/vs/grover_compare10.v | 81,900,704 | grover_compare10.v | v | 6 | 38 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/c88c6bef-7ec4-4322-815d-00d68c96d3d6.xml | null | 301,783 | module | module grover_compare10(A, B, valid);
input A, B;
output valid;
assign valid = A & (~B);
endmodule | module grover_compare10(A, B, valid); |
input A, B;
output valid;
assign valid = A & (~B);
endmodule | 5 |
138,099 | data/full_repos/permissive/81900704/output/vs/multi.v | 81,900,704 | multi.v | v | 35 | 109 | [] | [] | [] | [(2, 34)] | null | data/verilator_xmls/7a650465-57ae-44e1-ab00-dd53498adc69.xml | null | 301,786 | module | module multi (A, B, C, D, E, F, valid);
input A, B, C, D, E, F;
output valid;
wire [5:0] min_value = 6'd15;
wire [5:0] max_weight = 6'd16;
wire [5:0] max_volume = 6'd10;
wire [5:0] total_value =
A * 6'd4
+ B * 6'd2
+ C * 6'd2
+ D * 6'd1
+ E * 6'd10
+ F * 6'd20;
wire [5:0] total_weight =
A * 6'd12
+ B * 6'd1
+ C * 6'd2
+ D * 6'd1
+ E * 6'd4
+ F * 6'd1;
wire [5:0] total_volume =
A * 6'd10
+ B * 6'd2
+ C * 6'd1
+ D * 6'd4
+ E * 6'd3
+ F * 6'd12;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | module multi (A, B, C, D, E, F, valid); |
input A, B, C, D, E, F;
output valid;
wire [5:0] min_value = 6'd15;
wire [5:0] max_weight = 6'd16;
wire [5:0] max_volume = 6'd10;
wire [5:0] total_value =
A * 6'd4
+ B * 6'd2
+ C * 6'd2
+ D * 6'd1
+ E * 6'd10
+ F * 6'd20;
wire [5:0] total_weight =
A * 6'd12
+ B * 6'd1
+ C * 6'd2
+ D * 6'd1
+ E * 6'd4
+ F * 6'd1;
wire [5:0] total_volume =
A * 6'd10
+ B * 6'd2
+ C * 6'd1
+ D * 6'd4
+ E * 6'd3
+ F * 6'd12;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | 5 |
138,101 | data/full_repos/permissive/81900704/output/vs/opt_grover_compare10.v | 81,900,704 | opt_grover_compare10.v | v | 16 | 115 | [] | [] | [] | [(5, 15)] | null | data/verilator_xmls/6b6447fe-fb4d-4aa0-84f7-e413d6af04af.xml | null | 301,791 | module | module grover_compare10(A, B, valid);
wire _0_;
(* src = "grover_compare10.v:2" *)
input A;
(* src = "grover_compare10.v:2" *)
input B;
(* src = "grover_compare10.v:3" *)
output valid;
assign _0_ = ~B;
assign valid = A & _0_;
endmodule | module grover_compare10(A, B, valid); |
wire _0_;
(* src = "grover_compare10.v:2" *)
input A;
(* src = "grover_compare10.v:2" *)
input B;
(* src = "grover_compare10.v:3" *)
output valid;
assign _0_ = ~B;
assign valid = A & _0_;
endmodule | 5 |
138,102 | data/full_repos/permissive/81900704/output/vs/opt_grover_compare11.v | 81,900,704 | opt_grover_compare11.v | v | 14 | 115 | [] | [] | [] | [(5, 13)] | null | data/verilator_xmls/2e62c967-4364-4bd5-af44-9df079703623.xml | null | 301,792 | module | module grover_compare11(A, B, valid);
(* src = "grover_compare11.v:2" *)
input A;
(* src = "grover_compare11.v:2" *)
input B;
(* src = "grover_compare11.v:3" *)
output valid;
assign valid = B & A;
endmodule | module grover_compare11(A, B, valid); |
(* src = "grover_compare11.v:2" *)
input A;
(* src = "grover_compare11.v:2" *)
input B;
(* src = "grover_compare11.v:3" *)
output valid;
assign valid = B & A;
endmodule | 5 |
138,106 | data/full_repos/permissive/81900704/output/vs/opt_var15_multi.v | 81,900,704 | opt_var15_multi.v | v | 829 | 115 | [] | [] | [] | [(5, 828)] | null | data/verilator_xmls/edc6f0b7-ddf8-4569-9008-3532080a67f2.xml | null | 301,801 | module | module var15_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _351_;
wire _352_;
wire _353_;
wire _354_;
wire _355_;
wire _356_;
wire _357_;
wire _358_;
wire _359_;
wire _360_;
wire _361_;
wire _362_;
wire _363_;
wire _364_;
wire _365_;
wire _366_;
wire _367_;
wire _368_;
wire _369_;
wire _370_;
wire _371_;
wire _372_;
wire _373_;
wire _374_;
wire _375_;
wire _376_;
wire _377_;
wire _378_;
wire _379_;
wire _380_;
wire _381_;
wire _382_;
wire _383_;
wire _384_;
wire _385_;
wire _386_;
wire _387_;
wire _388_;
wire _389_;
wire _390_;
wire _391_;
wire _392_;
(* src = "var15_multi.v:3" *)
input A;
(* src = "var15_multi.v:3" *)
input B;
(* src = "var15_multi.v:3" *)
input C;
(* src = "var15_multi.v:3" *)
input D;
(* src = "var15_multi.v:3" *)
input E;
(* src = "var15_multi.v:3" *)
input F;
(* src = "var15_multi.v:3" *)
input G;
(* src = "var15_multi.v:3" *)
input H;
(* src = "var15_multi.v:3" *)
input I;
(* src = "var15_multi.v:3" *)
input J;
(* src = "var15_multi.v:3" *)
input K;
(* src = "var15_multi.v:3" *)
input L;
(* src = "var15_multi.v:3" *)
input M;
(* src = "var15_multi.v:3" *)
input N;
(* src = "var15_multi.v:3" *)
input O;
(* src = "var15_multi.v:9" *)
wire [7:0] total_value;
(* src = "var15_multi.v:4" *)
output valid;
assign _070_ = ~K;
assign _081_ = G ^ E;
assign _092_ = _081_ ^ H;
assign _103_ = ~(G & E);
assign _114_ = ~F;
assign _125_ = A ^ D;
assign _136_ = _125_ ^ _114_;
assign _147_ = _136_ ^ _103_;
assign _158_ = ~((_147_ | _092_) & I);
assign _169_ = ~_147_;
assign _180_ = ~H;
assign _191_ = ~(_081_ | _180_);
assign _202_ = _191_ & _169_;
assign _223_ = ~(_136_ | _103_);
assign _224_ = _125_ | _114_;
assign _235_ = ~E;
assign _246_ = ~B;
assign _257_ = ~(A & D);
assign _268_ = _257_ ^ _246_;
assign _279_ = _268_ ^ _235_;
assign _290_ = _279_ ^ _224_;
assign _301_ = ~(_290_ ^ _223_);
assign _312_ = _301_ ^ _202_;
assign _323_ = ~(_312_ | _158_);
assign _334_ = _081_ & H;
assign _335_ = ~((_147_ & H) | (_136_ & _334_));
assign _336_ = ~((_301_ | _180_) & _335_);
assign _337_ = _290_ & _223_;
assign _338_ = ~(_268_ & E);
assign _339_ = E & D;
assign _340_ = B ^ A;
assign _341_ = _340_ & _339_;
assign _342_ = ~D;
assign _343_ = B & A;
assign _344_ = _343_ | _342_;
assign _345_ = ~((_344_ & _338_) | _341_);
assign _346_ = ~_125_;
assign _347_ = ~((_279_ & _346_) | _114_);
assign _348_ = _347_ ^ _345_;
assign _349_ = _348_ ^ G;
assign _350_ = _349_ ^ _337_;
assign _351_ = _350_ ^ _336_;
assign _352_ = _351_ ^ _323_;
assign _353_ = ~J;
assign _354_ = ~(_312_ ^ _158_);
assign _355_ = ~(_191_ ^ _147_);
assign _356_ = ~I;
assign _357_ = _092_ ^ _356_;
assign _358_ = _357_ & _355_;
assign _359_ = ~((_358_ & _354_) | _353_);
assign _360_ = ~(_359_ ^ _352_);
assign _361_ = _357_ ^ J;
assign _362_ = ~(_092_ | _356_);
assign _363_ = _357_ & J;
assign _364_ = ~(_363_ | _362_);
assign _365_ = ~(_364_ ^ _355_);
assign _366_ = _365_ & _361_;
assign _367_ = _366_ & _354_;
assign _368_ = ~((_367_ & _360_) | _070_);
assign _369_ = _350_ & _336_;
assign _370_ = _348_ & G;
assign _371_ = ~((_349_ & _337_) | _370_);
assign _372_ = _343_ & D;
assign _373_ = _341_ | _372_;
assign _374_ = ~((_347_ & _345_) | _373_);
assign _375_ = _374_ ^ _371_;
assign _376_ = ~(_375_ ^ _369_);
assign _377_ = _351_ & _323_;
assign _378_ = ~((_359_ & _352_) | _377_);
assign _379_ = _378_ ^ _376_;
assign _380_ = ~(_379_ ^ _368_);
assign _381_ = ~L;
assign _382_ = _361_ & K;
assign _383_ = _382_ & _365_;
assign _384_ = _363_ & _355_;
assign _385_ = _384_ ^ _354_;
assign _386_ = _385_ ^ _383_;
assign _387_ = _386_ | _381_;
assign _388_ = _385_ & _383_;
assign _389_ = _388_ ^ _360_;
assign _390_ = _389_ ^ _387_;
assign _391_ = ~(_390_ & M);
assign _392_ = ~(_391_ | _380_);
assign _000_ = _389_ | _387_;
assign _001_ = ~(_000_ | _380_);
assign _002_ = _379_ & _368_;
assign _003_ = ~(_374_ | _371_);
assign _004_ = ~((_375_ & _369_) | _003_);
assign _005_ = ~((_378_ | _376_) & _004_);
assign _006_ = _005_ ^ _002_;
assign _007_ = _006_ | _001_;
assign _008_ = ~(_007_ & _392_);
assign _009_ = ~((_001_ | _002_) & _005_);
assign _010_ = _009_ & _008_;
assign _011_ = ~O;
assign _012_ = _382_ ^ _365_;
assign _013_ = ~_012_;
assign _014_ = ~N;
assign _015_ = _361_ ^ K;
assign _016_ = ~(_015_ | _014_);
assign _017_ = _016_ | _011_;
assign _018_ = ~((_015_ & _014_) | _017_);
assign _019_ = _016_ & _013_;
assign _020_ = _386_ ^ _381_;
assign _021_ = ~(_020_ & _019_);
assign _022_ = _020_ | _019_;
assign _023_ = ~((_022_ & _021_) | (_018_ & _013_));
assign _024_ = ~(_023_ & _011_);
assign _025_ = ~(_391_ & _000_);
assign _026_ = _025_ ^ _380_;
assign _027_ = _390_ ^ M;
assign _028_ = ~(_027_ | N);
assign _029_ = ~(_027_ & N);
assign _030_ = ~((_029_ | _021_) & (_028_ | _026_));
assign _031_ = _030_ & _024_;
assign _032_ = _029_ & _021_;
assign _033_ = _032_ | _026_;
assign _034_ = _032_ & _026_;
assign _035_ = _023_ | _011_;
assign _036_ = ~((_035_ | _034_) & _033_);
assign _037_ = ~((_036_ | _031_) & (_007_ | _392_));
assign _038_ = ~(B ^ A);
assign _039_ = _038_ ^ J;
assign _040_ = _039_ | _070_;
assign _041_ = ~(B | A);
assign _042_ = J ? _343_ : _041_;
assign _043_ = _042_ ^ _040_;
assign _044_ = ~(_043_ & L);
assign _045_ = ~C;
assign _046_ = _343_ ^ _045_;
assign _047_ = _046_ ^ _342_;
assign _048_ = _047_ ^ G;
assign _049_ = _048_ ^ H;
assign _050_ = _049_ ^ _356_;
assign _051_ = _041_ & J;
assign _052_ = _051_ ^ _050_;
assign _053_ = _052_ ^ K;
assign _054_ = ~(_053_ | _044_);
assign _055_ = _042_ | _040_;
assign _056_ = ~((_052_ | _070_) & _055_);
assign _057_ = ~(_051_ & _050_);
assign _058_ = _049_ | _356_;
assign _059_ = _046_ | _342_;
assign _060_ = D & C;
assign _061_ = _060_ & _340_;
assign _062_ = ~(_343_ & C);
assign _063_ = _062_ & _038_;
assign _064_ = ~((_063_ & _059_) | _061_);
assign _065_ = _064_ ^ _114_;
assign _066_ = ~(_047_ & G);
assign _067_ = ~(_048_ & H);
assign _068_ = _067_ & _066_;
assign _069_ = _068_ ^ _065_;
assign _071_ = _069_ ^ _058_;
assign _072_ = _071_ ^ _057_;
assign _073_ = _072_ ^ _056_;
assign _074_ = _073_ ^ _054_;
assign _075_ = ~(_074_ & M);
assign _076_ = _039_ ^ _070_;
assign _077_ = _076_ & M;
assign _078_ = _043_ ^ L;
assign _079_ = _078_ & _077_;
assign _080_ = _044_ & _055_;
assign _082_ = _080_ ^ _053_;
assign _083_ = ~(_082_ & _079_);
assign _084_ = ~M;
assign _085_ = _074_ ^ _084_;
assign _086_ = ~((_085_ | _083_) & _075_);
assign _087_ = _073_ & _054_;
assign _088_ = _072_ & _056_;
assign _089_ = _065_ | _067_;
assign _090_ = _065_ | _066_;
assign _091_ = _064_ | _114_;
assign _093_ = ~(_060_ | _041_);
assign _094_ = _093_ | _343_;
assign _095_ = _094_ ^ _091_;
assign _096_ = _095_ ^ _090_;
assign _097_ = _096_ ^ _180_;
assign _098_ = _097_ ^ _089_;
assign _099_ = _069_ | _049_;
assign _100_ = _099_ & I;
assign _101_ = _100_ ^ _098_;
assign _102_ = ~_041_;
assign _104_ = ~(_069_ | _102_);
assign _105_ = ~((_104_ & _050_) | _353_);
assign _106_ = _105_ ^ _101_;
assign _107_ = _106_ ^ _088_;
assign _108_ = _107_ ^ _087_;
assign _109_ = ~(_108_ ^ _086_);
assign _110_ = ~(_085_ ^ _083_);
assign _111_ = _082_ ^ _079_;
assign _112_ = ~_111_;
assign _113_ = _112_ & _110_;
assign _115_ = _113_ & _109_;
assign _116_ = _115_ | _014_;
assign _117_ = ~(_108_ & _086_);
assign _118_ = _105_ & _101_;
assign _119_ = _100_ & _098_;
assign _120_ = ~(_096_ & H);
assign _121_ = ~((_097_ | _089_) & _120_);
assign _122_ = ~(_095_ | _090_);
assign _123_ = _061_ | _343_;
assign _124_ = _094_ | _064_;
assign _126_ = _124_ & F;
assign _127_ = _126_ ^ _123_;
assign _128_ = _127_ ^ _122_;
assign _129_ = _128_ ^ _121_;
assign _130_ = _129_ ^ _119_;
assign _131_ = ~(_130_ ^ _118_);
assign _132_ = ~(_106_ & _088_);
assign _133_ = ~(_107_ & _087_);
assign _134_ = ~(_133_ & _132_);
assign _135_ = _134_ ^ _131_;
assign _137_ = _135_ & _117_;
assign _138_ = ~(_111_ | _014_);
assign _139_ = ~(_138_ & _110_);
assign _140_ = _139_ ^ _109_;
assign _141_ = ~(_138_ ^ _110_);
assign _142_ = _111_ ^ N;
assign _143_ = _078_ ^ _077_;
assign _144_ = _076_ ^ M;
assign _145_ = ~((_144_ | _143_) & _142_);
assign _146_ = _138_ ^ _110_;
assign _148_ = ~((_146_ | _145_) & _011_);
assign _149_ = _143_ | _142_;
assign _150_ = _149_ & O;
assign _151_ = ~((_150_ & _141_) | (_148_ & _140_));
assign _152_ = ~((_137_ & _116_) | _151_);
assign _153_ = ~(_131_ | _133_);
assign _154_ = E ^ D;
assign _155_ = C ? _342_ : _154_;
assign _156_ = _155_ ^ G;
assign _157_ = E ^ C;
assign _159_ = _157_ ^ H;
assign _160_ = _159_ & K;
assign _161_ = _157_ & H;
assign _162_ = _161_ & _156_;
assign _163_ = ~G;
assign _164_ = ~(_155_ | _163_);
assign _165_ = _060_ ^ A;
assign _166_ = ~((_342_ & _045_) | _235_);
assign _167_ = _166_ ^ _165_;
assign _168_ = _167_ ^ F;
assign _170_ = _168_ ^ _164_;
assign _171_ = _170_ ^ _162_;
assign _172_ = _171_ ^ I;
assign _173_ = ~((_172_ & K) | (_160_ & _156_));
assign _174_ = ~((_168_ | _155_) & G);
assign _175_ = _167_ | _114_;
assign _176_ = ~(_166_ & _165_);
assign _177_ = _257_ & C;
assign _178_ = _177_ ^ _038_;
assign _179_ = _178_ ^ E;
assign _181_ = _179_ ^ _176_;
assign _182_ = _181_ ^ _175_;
assign _183_ = _182_ ^ _174_;
assign _184_ = _170_ & _162_;
assign _185_ = ~((_171_ & I) | _184_);
assign _186_ = _185_ ^ _183_;
assign _187_ = _186_ ^ _173_;
assign _188_ = _187_ ^ _381_;
assign _189_ = _159_ ^ K;
assign _190_ = _189_ & L;
assign _192_ = ~(_160_ | _161_);
assign _193_ = ~(_192_ ^ _156_);
assign _194_ = _193_ & _190_;
assign _195_ = ~_194_;
assign _196_ = ~((_159_ & _156_) | _070_);
assign _197_ = _196_ ^ _172_;
assign _198_ = _197_ | _195_;
assign _199_ = ~((_197_ | _187_) & L);
assign _200_ = ~((_198_ | _188_) & _199_);
assign _201_ = ~(_186_ | _173_);
assign _203_ = _183_ & _184_;
assign _204_ = ~(_182_ | _174_);
assign _205_ = _181_ | _175_;
assign _206_ = _178_ | _235_;
assign _207_ = ~((_179_ | _176_) & _206_);
assign _208_ = _246_ | A;
assign _209_ = ~A;
assign _210_ = ~((B | _209_) & _045_);
assign _211_ = ~((_210_ & _208_) | D);
assign _212_ = B | _209_;
assign _213_ = ~((_246_ | A) & C);
assign _214_ = ~((_213_ & _212_) | _342_);
assign _215_ = ~((_214_ & _062_) | _211_);
assign _216_ = _215_ ^ E;
assign _217_ = ~(_216_ ^ _207_);
assign _218_ = _217_ ^ _205_;
assign _219_ = _218_ ^ _204_;
assign _220_ = ~(_219_ ^ _203_);
assign _221_ = ~(_183_ & _171_);
assign _222_ = ~(_221_ & I);
assign _225_ = _222_ ^ _220_;
assign _226_ = _225_ ^ _201_;
assign _227_ = _226_ & _200_;
assign _228_ = _225_ & _201_;
assign _229_ = ~((_221_ & _220_) | _356_);
assign _230_ = _167_ & F;
assign _231_ = ~((_181_ & F) | (_179_ & _230_));
assign _232_ = ~((_217_ | _114_) & _231_);
assign _233_ = _166_ & _165_;
assign _234_ = ~(_215_ & E);
assign _236_ = _060_ & A;
assign _237_ = ~_236_;
assign _238_ = _343_ | C;
assign _239_ = _238_ & _102_;
assign _240_ = ~((_239_ | _214_) & _237_);
assign _241_ = _240_ & _206_;
assign _242_ = ~((_241_ & _234_) | _233_);
assign _243_ = ~(_242_ ^ _232_);
assign _244_ = _218_ & _204_;
assign _245_ = ~((_219_ & _203_) | _244_);
assign _247_ = _245_ ^ _243_;
assign _248_ = _247_ ^ _229_;
assign _249_ = _248_ ^ _228_;
assign _250_ = _249_ & _227_;
assign _251_ = ~(_248_ & _228_);
assign _252_ = ~(_247_ & _229_);
assign _253_ = ~(_218_ & _204_);
assign _254_ = _243_ | _253_;
assign _255_ = _242_ & _232_;
assign _256_ = ~(_255_ & _236_);
assign _258_ = _233_ | _236_;
assign _259_ = _255_ | _258_;
assign _260_ = ~((_259_ & _256_) | (_219_ & _203_));
assign _261_ = _260_ & _254_;
assign _262_ = _261_ ^ _252_;
assign _263_ = ~(_262_ ^ _251_);
assign _264_ = ~((_263_ & _250_) | _153_);
assign _265_ = ~((_135_ | _117_) & _264_);
assign _266_ = ~((_197_ & L) | _194_);
assign _267_ = ~(_266_ ^ _188_);
assign _269_ = ~(_267_ | _084_);
assign _270_ = _226_ ^ _200_;
assign _271_ = _270_ & _269_;
assign _272_ = _249_ ^ _227_;
assign _273_ = _272_ & _271_;
assign _274_ = _263_ ^ _250_;
assign _275_ = _274_ | _273_;
assign _276_ = _261_ | _252_;
assign _277_ = _276_ & _256_;
assign _278_ = ~((_261_ | _251_) & _277_);
assign _280_ = _126_ & _123_;
assign _281_ = _127_ & _122_;
assign _282_ = _281_ | _280_;
assign _283_ = ~((_128_ & _121_) | _282_);
assign _284_ = _129_ & _119_;
assign _285_ = ~((_130_ & _118_) | _284_);
assign _286_ = _285_ ^ _283_;
assign _287_ = ~(_130_ & _118_);
assign _288_ = ~((_283_ | _287_) & (_131_ | _132_));
assign _289_ = _288_ | _286_;
assign _291_ = _289_ | _278_;
assign _292_ = _291_ | _275_;
assign _293_ = _292_ | _265_;
assign _294_ = _293_ | _152_;
assign _295_ = _270_ ^ _269_;
assign _296_ = _267_ ^ _084_;
assign _297_ = _193_ ^ _190_;
assign _298_ = ~(_194_ | _381_);
assign _299_ = _298_ ^ _197_;
assign _300_ = ~(_299_ | _297_);
assign _302_ = ~(_300_ | _014_);
assign _303_ = _296_ ? N : _302_;
assign _304_ = _303_ & _295_;
assign _305_ = _272_ ^ _271_;
assign _306_ = ~(_305_ | _304_);
assign _307_ = _297_ | _014_;
assign _308_ = ~(_307_ | _299_);
assign _309_ = _308_ ^ _296_;
assign _310_ = _297_ ^ N;
assign _311_ = _310_ | _299_;
assign _313_ = _311_ & O;
assign _314_ = _313_ | _309_;
assign _315_ = _310_ | _011_;
assign _316_ = _315_ & _307_;
assign _317_ = _316_ ^ _299_;
assign _318_ = ~(_189_ | L);
assign _319_ = ~(_318_ | _190_);
assign _320_ = ~((_310_ & _011_) | _319_);
assign _321_ = ~((_320_ & _315_) | _317_);
assign _322_ = _321_ & _314_;
assign _324_ = _303_ ^ _295_;
assign _325_ = _324_ | O;
assign _326_ = _311_ & _309_;
assign _327_ = _324_ | _326_;
assign _328_ = ~((_327_ & O) | (_325_ & _322_));
assign _329_ = ~(_328_ | _306_);
assign _330_ = ~(_305_ & _304_);
assign _331_ = ~((_137_ | _116_) & _330_);
assign _332_ = _331_ | _329_;
assign _333_ = _332_ | _294_;
assign valid = ~((_037_ & _010_) | _333_);
assign total_value[0] = J;
endmodule | module var15_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, valid); |
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _351_;
wire _352_;
wire _353_;
wire _354_;
wire _355_;
wire _356_;
wire _357_;
wire _358_;
wire _359_;
wire _360_;
wire _361_;
wire _362_;
wire _363_;
wire _364_;
wire _365_;
wire _366_;
wire _367_;
wire _368_;
wire _369_;
wire _370_;
wire _371_;
wire _372_;
wire _373_;
wire _374_;
wire _375_;
wire _376_;
wire _377_;
wire _378_;
wire _379_;
wire _380_;
wire _381_;
wire _382_;
wire _383_;
wire _384_;
wire _385_;
wire _386_;
wire _387_;
wire _388_;
wire _389_;
wire _390_;
wire _391_;
wire _392_;
(* src = "var15_multi.v:3" *)
input A;
(* src = "var15_multi.v:3" *)
input B;
(* src = "var15_multi.v:3" *)
input C;
(* src = "var15_multi.v:3" *)
input D;
(* src = "var15_multi.v:3" *)
input E;
(* src = "var15_multi.v:3" *)
input F;
(* src = "var15_multi.v:3" *)
input G;
(* src = "var15_multi.v:3" *)
input H;
(* src = "var15_multi.v:3" *)
input I;
(* src = "var15_multi.v:3" *)
input J;
(* src = "var15_multi.v:3" *)
input K;
(* src = "var15_multi.v:3" *)
input L;
(* src = "var15_multi.v:3" *)
input M;
(* src = "var15_multi.v:3" *)
input N;
(* src = "var15_multi.v:3" *)
input O;
(* src = "var15_multi.v:9" *)
wire [7:0] total_value;
(* src = "var15_multi.v:4" *)
output valid;
assign _070_ = ~K;
assign _081_ = G ^ E;
assign _092_ = _081_ ^ H;
assign _103_ = ~(G & E);
assign _114_ = ~F;
assign _125_ = A ^ D;
assign _136_ = _125_ ^ _114_;
assign _147_ = _136_ ^ _103_;
assign _158_ = ~((_147_ | _092_) & I);
assign _169_ = ~_147_;
assign _180_ = ~H;
assign _191_ = ~(_081_ | _180_);
assign _202_ = _191_ & _169_;
assign _223_ = ~(_136_ | _103_);
assign _224_ = _125_ | _114_;
assign _235_ = ~E;
assign _246_ = ~B;
assign _257_ = ~(A & D);
assign _268_ = _257_ ^ _246_;
assign _279_ = _268_ ^ _235_;
assign _290_ = _279_ ^ _224_;
assign _301_ = ~(_290_ ^ _223_);
assign _312_ = _301_ ^ _202_;
assign _323_ = ~(_312_ | _158_);
assign _334_ = _081_ & H;
assign _335_ = ~((_147_ & H) | (_136_ & _334_));
assign _336_ = ~((_301_ | _180_) & _335_);
assign _337_ = _290_ & _223_;
assign _338_ = ~(_268_ & E);
assign _339_ = E & D;
assign _340_ = B ^ A;
assign _341_ = _340_ & _339_;
assign _342_ = ~D;
assign _343_ = B & A;
assign _344_ = _343_ | _342_;
assign _345_ = ~((_344_ & _338_) | _341_);
assign _346_ = ~_125_;
assign _347_ = ~((_279_ & _346_) | _114_);
assign _348_ = _347_ ^ _345_;
assign _349_ = _348_ ^ G;
assign _350_ = _349_ ^ _337_;
assign _351_ = _350_ ^ _336_;
assign _352_ = _351_ ^ _323_;
assign _353_ = ~J;
assign _354_ = ~(_312_ ^ _158_);
assign _355_ = ~(_191_ ^ _147_);
assign _356_ = ~I;
assign _357_ = _092_ ^ _356_;
assign _358_ = _357_ & _355_;
assign _359_ = ~((_358_ & _354_) | _353_);
assign _360_ = ~(_359_ ^ _352_);
assign _361_ = _357_ ^ J;
assign _362_ = ~(_092_ | _356_);
assign _363_ = _357_ & J;
assign _364_ = ~(_363_ | _362_);
assign _365_ = ~(_364_ ^ _355_);
assign _366_ = _365_ & _361_;
assign _367_ = _366_ & _354_;
assign _368_ = ~((_367_ & _360_) | _070_);
assign _369_ = _350_ & _336_;
assign _370_ = _348_ & G;
assign _371_ = ~((_349_ & _337_) | _370_);
assign _372_ = _343_ & D;
assign _373_ = _341_ | _372_;
assign _374_ = ~((_347_ & _345_) | _373_);
assign _375_ = _374_ ^ _371_;
assign _376_ = ~(_375_ ^ _369_);
assign _377_ = _351_ & _323_;
assign _378_ = ~((_359_ & _352_) | _377_);
assign _379_ = _378_ ^ _376_;
assign _380_ = ~(_379_ ^ _368_);
assign _381_ = ~L;
assign _382_ = _361_ & K;
assign _383_ = _382_ & _365_;
assign _384_ = _363_ & _355_;
assign _385_ = _384_ ^ _354_;
assign _386_ = _385_ ^ _383_;
assign _387_ = _386_ | _381_;
assign _388_ = _385_ & _383_;
assign _389_ = _388_ ^ _360_;
assign _390_ = _389_ ^ _387_;
assign _391_ = ~(_390_ & M);
assign _392_ = ~(_391_ | _380_);
assign _000_ = _389_ | _387_;
assign _001_ = ~(_000_ | _380_);
assign _002_ = _379_ & _368_;
assign _003_ = ~(_374_ | _371_);
assign _004_ = ~((_375_ & _369_) | _003_);
assign _005_ = ~((_378_ | _376_) & _004_);
assign _006_ = _005_ ^ _002_;
assign _007_ = _006_ | _001_;
assign _008_ = ~(_007_ & _392_);
assign _009_ = ~((_001_ | _002_) & _005_);
assign _010_ = _009_ & _008_;
assign _011_ = ~O;
assign _012_ = _382_ ^ _365_;
assign _013_ = ~_012_;
assign _014_ = ~N;
assign _015_ = _361_ ^ K;
assign _016_ = ~(_015_ | _014_);
assign _017_ = _016_ | _011_;
assign _018_ = ~((_015_ & _014_) | _017_);
assign _019_ = _016_ & _013_;
assign _020_ = _386_ ^ _381_;
assign _021_ = ~(_020_ & _019_);
assign _022_ = _020_ | _019_;
assign _023_ = ~((_022_ & _021_) | (_018_ & _013_));
assign _024_ = ~(_023_ & _011_);
assign _025_ = ~(_391_ & _000_);
assign _026_ = _025_ ^ _380_;
assign _027_ = _390_ ^ M;
assign _028_ = ~(_027_ | N);
assign _029_ = ~(_027_ & N);
assign _030_ = ~((_029_ | _021_) & (_028_ | _026_));
assign _031_ = _030_ & _024_;
assign _032_ = _029_ & _021_;
assign _033_ = _032_ | _026_;
assign _034_ = _032_ & _026_;
assign _035_ = _023_ | _011_;
assign _036_ = ~((_035_ | _034_) & _033_);
assign _037_ = ~((_036_ | _031_) & (_007_ | _392_));
assign _038_ = ~(B ^ A);
assign _039_ = _038_ ^ J;
assign _040_ = _039_ | _070_;
assign _041_ = ~(B | A);
assign _042_ = J ? _343_ : _041_;
assign _043_ = _042_ ^ _040_;
assign _044_ = ~(_043_ & L);
assign _045_ = ~C;
assign _046_ = _343_ ^ _045_;
assign _047_ = _046_ ^ _342_;
assign _048_ = _047_ ^ G;
assign _049_ = _048_ ^ H;
assign _050_ = _049_ ^ _356_;
assign _051_ = _041_ & J;
assign _052_ = _051_ ^ _050_;
assign _053_ = _052_ ^ K;
assign _054_ = ~(_053_ | _044_);
assign _055_ = _042_ | _040_;
assign _056_ = ~((_052_ | _070_) & _055_);
assign _057_ = ~(_051_ & _050_);
assign _058_ = _049_ | _356_;
assign _059_ = _046_ | _342_;
assign _060_ = D & C;
assign _061_ = _060_ & _340_;
assign _062_ = ~(_343_ & C);
assign _063_ = _062_ & _038_;
assign _064_ = ~((_063_ & _059_) | _061_);
assign _065_ = _064_ ^ _114_;
assign _066_ = ~(_047_ & G);
assign _067_ = ~(_048_ & H);
assign _068_ = _067_ & _066_;
assign _069_ = _068_ ^ _065_;
assign _071_ = _069_ ^ _058_;
assign _072_ = _071_ ^ _057_;
assign _073_ = _072_ ^ _056_;
assign _074_ = _073_ ^ _054_;
assign _075_ = ~(_074_ & M);
assign _076_ = _039_ ^ _070_;
assign _077_ = _076_ & M;
assign _078_ = _043_ ^ L;
assign _079_ = _078_ & _077_;
assign _080_ = _044_ & _055_;
assign _082_ = _080_ ^ _053_;
assign _083_ = ~(_082_ & _079_);
assign _084_ = ~M;
assign _085_ = _074_ ^ _084_;
assign _086_ = ~((_085_ | _083_) & _075_);
assign _087_ = _073_ & _054_;
assign _088_ = _072_ & _056_;
assign _089_ = _065_ | _067_;
assign _090_ = _065_ | _066_;
assign _091_ = _064_ | _114_;
assign _093_ = ~(_060_ | _041_);
assign _094_ = _093_ | _343_;
assign _095_ = _094_ ^ _091_;
assign _096_ = _095_ ^ _090_;
assign _097_ = _096_ ^ _180_;
assign _098_ = _097_ ^ _089_;
assign _099_ = _069_ | _049_;
assign _100_ = _099_ & I;
assign _101_ = _100_ ^ _098_;
assign _102_ = ~_041_;
assign _104_ = ~(_069_ | _102_);
assign _105_ = ~((_104_ & _050_) | _353_);
assign _106_ = _105_ ^ _101_;
assign _107_ = _106_ ^ _088_;
assign _108_ = _107_ ^ _087_;
assign _109_ = ~(_108_ ^ _086_);
assign _110_ = ~(_085_ ^ _083_);
assign _111_ = _082_ ^ _079_;
assign _112_ = ~_111_;
assign _113_ = _112_ & _110_;
assign _115_ = _113_ & _109_;
assign _116_ = _115_ | _014_;
assign _117_ = ~(_108_ & _086_);
assign _118_ = _105_ & _101_;
assign _119_ = _100_ & _098_;
assign _120_ = ~(_096_ & H);
assign _121_ = ~((_097_ | _089_) & _120_);
assign _122_ = ~(_095_ | _090_);
assign _123_ = _061_ | _343_;
assign _124_ = _094_ | _064_;
assign _126_ = _124_ & F;
assign _127_ = _126_ ^ _123_;
assign _128_ = _127_ ^ _122_;
assign _129_ = _128_ ^ _121_;
assign _130_ = _129_ ^ _119_;
assign _131_ = ~(_130_ ^ _118_);
assign _132_ = ~(_106_ & _088_);
assign _133_ = ~(_107_ & _087_);
assign _134_ = ~(_133_ & _132_);
assign _135_ = _134_ ^ _131_;
assign _137_ = _135_ & _117_;
assign _138_ = ~(_111_ | _014_);
assign _139_ = ~(_138_ & _110_);
assign _140_ = _139_ ^ _109_;
assign _141_ = ~(_138_ ^ _110_);
assign _142_ = _111_ ^ N;
assign _143_ = _078_ ^ _077_;
assign _144_ = _076_ ^ M;
assign _145_ = ~((_144_ | _143_) & _142_);
assign _146_ = _138_ ^ _110_;
assign _148_ = ~((_146_ | _145_) & _011_);
assign _149_ = _143_ | _142_;
assign _150_ = _149_ & O;
assign _151_ = ~((_150_ & _141_) | (_148_ & _140_));
assign _152_ = ~((_137_ & _116_) | _151_);
assign _153_ = ~(_131_ | _133_);
assign _154_ = E ^ D;
assign _155_ = C ? _342_ : _154_;
assign _156_ = _155_ ^ G;
assign _157_ = E ^ C;
assign _159_ = _157_ ^ H;
assign _160_ = _159_ & K;
assign _161_ = _157_ & H;
assign _162_ = _161_ & _156_;
assign _163_ = ~G;
assign _164_ = ~(_155_ | _163_);
assign _165_ = _060_ ^ A;
assign _166_ = ~((_342_ & _045_) | _235_);
assign _167_ = _166_ ^ _165_;
assign _168_ = _167_ ^ F;
assign _170_ = _168_ ^ _164_;
assign _171_ = _170_ ^ _162_;
assign _172_ = _171_ ^ I;
assign _173_ = ~((_172_ & K) | (_160_ & _156_));
assign _174_ = ~((_168_ | _155_) & G);
assign _175_ = _167_ | _114_;
assign _176_ = ~(_166_ & _165_);
assign _177_ = _257_ & C;
assign _178_ = _177_ ^ _038_;
assign _179_ = _178_ ^ E;
assign _181_ = _179_ ^ _176_;
assign _182_ = _181_ ^ _175_;
assign _183_ = _182_ ^ _174_;
assign _184_ = _170_ & _162_;
assign _185_ = ~((_171_ & I) | _184_);
assign _186_ = _185_ ^ _183_;
assign _187_ = _186_ ^ _173_;
assign _188_ = _187_ ^ _381_;
assign _189_ = _159_ ^ K;
assign _190_ = _189_ & L;
assign _192_ = ~(_160_ | _161_);
assign _193_ = ~(_192_ ^ _156_);
assign _194_ = _193_ & _190_;
assign _195_ = ~_194_;
assign _196_ = ~((_159_ & _156_) | _070_);
assign _197_ = _196_ ^ _172_;
assign _198_ = _197_ | _195_;
assign _199_ = ~((_197_ | _187_) & L);
assign _200_ = ~((_198_ | _188_) & _199_);
assign _201_ = ~(_186_ | _173_);
assign _203_ = _183_ & _184_;
assign _204_ = ~(_182_ | _174_);
assign _205_ = _181_ | _175_;
assign _206_ = _178_ | _235_;
assign _207_ = ~((_179_ | _176_) & _206_);
assign _208_ = _246_ | A;
assign _209_ = ~A;
assign _210_ = ~((B | _209_) & _045_);
assign _211_ = ~((_210_ & _208_) | D);
assign _212_ = B | _209_;
assign _213_ = ~((_246_ | A) & C);
assign _214_ = ~((_213_ & _212_) | _342_);
assign _215_ = ~((_214_ & _062_) | _211_);
assign _216_ = _215_ ^ E;
assign _217_ = ~(_216_ ^ _207_);
assign _218_ = _217_ ^ _205_;
assign _219_ = _218_ ^ _204_;
assign _220_ = ~(_219_ ^ _203_);
assign _221_ = ~(_183_ & _171_);
assign _222_ = ~(_221_ & I);
assign _225_ = _222_ ^ _220_;
assign _226_ = _225_ ^ _201_;
assign _227_ = _226_ & _200_;
assign _228_ = _225_ & _201_;
assign _229_ = ~((_221_ & _220_) | _356_);
assign _230_ = _167_ & F;
assign _231_ = ~((_181_ & F) | (_179_ & _230_));
assign _232_ = ~((_217_ | _114_) & _231_);
assign _233_ = _166_ & _165_;
assign _234_ = ~(_215_ & E);
assign _236_ = _060_ & A;
assign _237_ = ~_236_;
assign _238_ = _343_ | C;
assign _239_ = _238_ & _102_;
assign _240_ = ~((_239_ | _214_) & _237_);
assign _241_ = _240_ & _206_;
assign _242_ = ~((_241_ & _234_) | _233_);
assign _243_ = ~(_242_ ^ _232_);
assign _244_ = _218_ & _204_;
assign _245_ = ~((_219_ & _203_) | _244_);
assign _247_ = _245_ ^ _243_;
assign _248_ = _247_ ^ _229_;
assign _249_ = _248_ ^ _228_;
assign _250_ = _249_ & _227_;
assign _251_ = ~(_248_ & _228_);
assign _252_ = ~(_247_ & _229_);
assign _253_ = ~(_218_ & _204_);
assign _254_ = _243_ | _253_;
assign _255_ = _242_ & _232_;
assign _256_ = ~(_255_ & _236_);
assign _258_ = _233_ | _236_;
assign _259_ = _255_ | _258_;
assign _260_ = ~((_259_ & _256_) | (_219_ & _203_));
assign _261_ = _260_ & _254_;
assign _262_ = _261_ ^ _252_;
assign _263_ = ~(_262_ ^ _251_);
assign _264_ = ~((_263_ & _250_) | _153_);
assign _265_ = ~((_135_ | _117_) & _264_);
assign _266_ = ~((_197_ & L) | _194_);
assign _267_ = ~(_266_ ^ _188_);
assign _269_ = ~(_267_ | _084_);
assign _270_ = _226_ ^ _200_;
assign _271_ = _270_ & _269_;
assign _272_ = _249_ ^ _227_;
assign _273_ = _272_ & _271_;
assign _274_ = _263_ ^ _250_;
assign _275_ = _274_ | _273_;
assign _276_ = _261_ | _252_;
assign _277_ = _276_ & _256_;
assign _278_ = ~((_261_ | _251_) & _277_);
assign _280_ = _126_ & _123_;
assign _281_ = _127_ & _122_;
assign _282_ = _281_ | _280_;
assign _283_ = ~((_128_ & _121_) | _282_);
assign _284_ = _129_ & _119_;
assign _285_ = ~((_130_ & _118_) | _284_);
assign _286_ = _285_ ^ _283_;
assign _287_ = ~(_130_ & _118_);
assign _288_ = ~((_283_ | _287_) & (_131_ | _132_));
assign _289_ = _288_ | _286_;
assign _291_ = _289_ | _278_;
assign _292_ = _291_ | _275_;
assign _293_ = _292_ | _265_;
assign _294_ = _293_ | _152_;
assign _295_ = _270_ ^ _269_;
assign _296_ = _267_ ^ _084_;
assign _297_ = _193_ ^ _190_;
assign _298_ = ~(_194_ | _381_);
assign _299_ = _298_ ^ _197_;
assign _300_ = ~(_299_ | _297_);
assign _302_ = ~(_300_ | _014_);
assign _303_ = _296_ ? N : _302_;
assign _304_ = _303_ & _295_;
assign _305_ = _272_ ^ _271_;
assign _306_ = ~(_305_ | _304_);
assign _307_ = _297_ | _014_;
assign _308_ = ~(_307_ | _299_);
assign _309_ = _308_ ^ _296_;
assign _310_ = _297_ ^ N;
assign _311_ = _310_ | _299_;
assign _313_ = _311_ & O;
assign _314_ = _313_ | _309_;
assign _315_ = _310_ | _011_;
assign _316_ = _315_ & _307_;
assign _317_ = _316_ ^ _299_;
assign _318_ = ~(_189_ | L);
assign _319_ = ~(_318_ | _190_);
assign _320_ = ~((_310_ & _011_) | _319_);
assign _321_ = ~((_320_ & _315_) | _317_);
assign _322_ = _321_ & _314_;
assign _324_ = _303_ ^ _295_;
assign _325_ = _324_ | O;
assign _326_ = _311_ & _309_;
assign _327_ = _324_ | _326_;
assign _328_ = ~((_327_ & O) | (_325_ & _322_));
assign _329_ = ~(_328_ | _306_);
assign _330_ = ~(_305_ & _304_);
assign _331_ = ~((_137_ | _116_) & _330_);
assign _332_ = _331_ | _329_;
assign _333_ = _332_ | _294_;
assign valid = ~((_037_ & _010_) | _333_);
assign total_value[0] = J;
endmodule | 5 |
138,107 | data/full_repos/permissive/81900704/output/vs/opt_var17_multi.v | 81,900,704 | opt_var17_multi.v | v | 992 | 115 | [] | [] | [] | [(5, 991)] | null | data/verilator_xmls/bef95dff-a5cb-4acb-b193-3f6562cf4676.xml | null | 301,803 | module | module var17_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _351_;
wire _352_;
wire _353_;
wire _354_;
wire _355_;
wire _356_;
wire _357_;
wire _358_;
wire _359_;
wire _360_;
wire _361_;
wire _362_;
wire _363_;
wire _364_;
wire _365_;
wire _366_;
wire _367_;
wire _368_;
wire _369_;
wire _370_;
wire _371_;
wire _372_;
wire _373_;
wire _374_;
wire _375_;
wire _376_;
wire _377_;
wire _378_;
wire _379_;
wire _380_;
wire _381_;
wire _382_;
wire _383_;
wire _384_;
wire _385_;
wire _386_;
wire _387_;
wire _388_;
wire _389_;
wire _390_;
wire _391_;
wire _392_;
wire _393_;
wire _394_;
wire _395_;
wire _396_;
wire _397_;
wire _398_;
wire _399_;
wire _400_;
wire _401_;
wire _402_;
wire _403_;
wire _404_;
wire _405_;
wire _406_;
wire _407_;
wire _408_;
wire _409_;
wire _410_;
wire _411_;
wire _412_;
wire _413_;
wire _414_;
wire _415_;
wire _416_;
wire _417_;
wire _418_;
wire _419_;
wire _420_;
wire _421_;
wire _422_;
wire _423_;
wire _424_;
wire _425_;
wire _426_;
wire _427_;
wire _428_;
wire _429_;
wire _430_;
wire _431_;
wire _432_;
wire _433_;
wire _434_;
wire _435_;
wire _436_;
wire _437_;
wire _438_;
wire _439_;
wire _440_;
wire _441_;
wire _442_;
wire _443_;
wire _444_;
wire _445_;
wire _446_;
wire _447_;
wire _448_;
wire _449_;
wire _450_;
wire _451_;
wire _452_;
wire _453_;
wire _454_;
wire _455_;
wire _456_;
wire _457_;
wire _458_;
wire _459_;
wire _460_;
wire _461_;
wire _462_;
wire _463_;
wire _464_;
wire _465_;
wire _466_;
wire _467_;
wire _468_;
wire _469_;
wire _470_;
wire _471_;
wire _472_;
wire _473_;
(* src = "var17_multi.v:3" *)
input A;
(* src = "var17_multi.v:3" *)
input B;
(* src = "var17_multi.v:3" *)
input C;
(* src = "var17_multi.v:3" *)
input D;
(* src = "var17_multi.v:3" *)
input E;
(* src = "var17_multi.v:3" *)
input F;
(* src = "var17_multi.v:3" *)
input G;
(* src = "var17_multi.v:3" *)
input H;
(* src = "var17_multi.v:3" *)
input I;
(* src = "var17_multi.v:3" *)
input J;
(* src = "var17_multi.v:3" *)
input K;
(* src = "var17_multi.v:3" *)
input L;
(* src = "var17_multi.v:3" *)
input M;
(* src = "var17_multi.v:3" *)
input N;
(* src = "var17_multi.v:3" *)
input O;
(* src = "var17_multi.v:3" *)
input P;
(* src = "var17_multi.v:3" *)
input Q;
(* src = "var17_multi.v:4" *)
output valid;
assign _090_ = ~N;
assign _101_ = ~I;
assign _112_ = G ^ E;
assign _123_ = _112_ ^ H;
assign _134_ = _123_ ^ _101_;
assign _145_ = _134_ ^ J;
assign _156_ = _145_ ^ K;
assign _167_ = ~(_156_ | _090_);
assign _178_ = ~(_145_ & K);
assign _189_ = ~_178_;
assign _200_ = _112_ & H;
assign _211_ = ~F;
assign _222_ = D ^ A;
assign _233_ = _222_ ^ _211_;
assign _244_ = ~(_233_ & _200_);
assign _255_ = ~(G & E);
assign _266_ = _233_ ^ _255_;
assign _277_ = ~H;
assign _288_ = _112_ | _277_;
assign _299_ = _266_ ? _288_ : H;
assign _310_ = _299_ & _244_;
assign _331_ = _123_ | _101_;
assign _332_ = ~(_134_ & J);
assign _343_ = _332_ & _331_;
assign _354_ = _343_ ^ _310_;
assign _365_ = _354_ ^ _189_;
assign _376_ = ~_365_;
assign _387_ = _376_ & _167_;
assign _408_ = ~L;
assign _409_ = ~(_310_ | _332_);
assign _420_ = ~(_354_ & _189_);
assign _424_ = ~((_310_ | _123_) & I);
assign _425_ = ~(_233_ | _255_);
assign _426_ = _222_ | _211_;
assign _427_ = ~E;
assign _428_ = ~B;
assign _429_ = ~(D & A);
assign _430_ = _429_ ^ _428_;
assign _431_ = _430_ ^ _427_;
assign _432_ = _431_ ^ _426_;
assign _433_ = _432_ ^ _425_;
assign _434_ = ~(_266_ | _277_);
assign _435_ = ~(_434_ & _244_);
assign _436_ = _435_ ^ _433_;
assign _437_ = _436_ ^ _424_;
assign _438_ = _437_ ^ _420_;
assign _439_ = _438_ ^ _409_;
assign _440_ = _439_ ^ _408_;
assign _441_ = _440_ & _387_;
assign _442_ = _439_ | _408_;
assign _443_ = _437_ | _420_;
assign _444_ = ~(_436_ | _424_);
assign _445_ = ~((_433_ | _266_) & H);
assign _446_ = ~((_433_ | _244_) & _445_);
assign _447_ = _432_ & _425_;
assign _448_ = _430_ & E;
assign _449_ = ~D;
assign _450_ = B & A;
assign _451_ = ~(_450_ | _449_);
assign _452_ = _451_ ^ _448_;
assign _453_ = ~_222_;
assign _454_ = ~((_431_ & _453_) | _211_);
assign _455_ = _454_ ^ _452_;
assign _456_ = _455_ ^ G;
assign _457_ = _456_ ^ _447_;
assign _458_ = _457_ ^ _446_;
assign _459_ = _458_ ^ _444_;
assign _460_ = ~J;
assign _461_ = ~_310_;
assign _462_ = _461_ & _134_;
assign _463_ = ~_437_;
assign _464_ = ~((_463_ & _462_) | _460_);
assign _465_ = _464_ ^ _459_;
assign _466_ = _465_ ^ _443_;
assign _467_ = _466_ ^ _442_;
assign _468_ = _467_ ^ M;
assign _469_ = _468_ ^ N;
assign _470_ = _469_ ^ _441_;
assign _471_ = _470_ & O;
assign _472_ = _156_ ^ _090_;
assign _473_ = _472_ & O;
assign _000_ = _473_ & _376_;
assign _001_ = _440_ ^ _387_;
assign _002_ = _001_ & _000_;
assign _003_ = _470_ ^ O;
assign _004_ = ~((_003_ & _002_) | _471_);
assign _005_ = _468_ & N;
assign _006_ = ~((_469_ & _441_) | _005_);
assign _007_ = _464_ & _459_;
assign _008_ = ~(_455_ & G);
assign _009_ = ~(_456_ & _447_);
assign _010_ = _009_ & _008_;
assign _011_ = _450_ & D;
assign _012_ = _451_ & _448_;
assign _013_ = _012_ | _011_;
assign _014_ = ~((_454_ & _452_) | _013_);
assign _015_ = _014_ ^ _010_;
assign _016_ = ~(_457_ & _446_);
assign _017_ = ~(_458_ & _444_);
assign _018_ = _017_ & _016_;
assign _019_ = _018_ ^ _015_;
assign _020_ = ~(_019_ ^ _007_);
assign _021_ = ~(_354_ & _145_);
assign _022_ = _437_ | _021_;
assign _023_ = _465_ | _022_;
assign _024_ = _023_ & K;
assign _025_ = ~(_024_ ^ _020_);
assign _026_ = _466_ | _442_;
assign _027_ = ~(_467_ & M);
assign _028_ = _027_ & _026_;
assign _029_ = ~(_028_ ^ _025_);
assign _030_ = ~(_029_ ^ _006_);
assign _031_ = _030_ | _004_;
assign _032_ = ~P;
assign _033_ = ~(_473_ | _167_);
assign _034_ = _033_ ^ _376_;
assign _035_ = _001_ ^ _000_;
assign _036_ = _472_ ^ O;
assign _037_ = ~(_036_ | _035_);
assign _038_ = ~((_037_ & _034_) | _032_);
assign _039_ = ~Q;
assign _040_ = ~(_036_ | _032_);
assign _041_ = _040_ | J;
assign _042_ = ~((_036_ & _032_) | _041_);
assign _043_ = ~((_042_ & _034_) | _039_);
assign _044_ = _040_ & _034_;
assign _045_ = _044_ ^ _035_;
assign _046_ = _045_ | _043_;
assign _047_ = _046_ | _038_;
assign _048_ = _003_ ^ _002_;
assign _049_ = _046_ & _038_;
assign _050_ = ~((_049_ | _048_) & _047_);
assign _051_ = _029_ | _006_;
assign _052_ = ~(_025_ | _027_);
assign _053_ = _025_ | _026_;
assign _054_ = ~_015_;
assign _055_ = ~_016_;
assign _056_ = ~(_014_ | _010_);
assign _057_ = ~(_014_ & _010_);
assign _058_ = ~((_057_ & _055_) | _056_);
assign _059_ = ~((_054_ | _017_) & _058_);
assign _060_ = ~_007_;
assign _061_ = _019_ | _060_;
assign _062_ = ~(_024_ & _020_);
assign _063_ = _062_ & _061_;
assign _064_ = _063_ ^ _059_;
assign _065_ = _064_ ^ _053_;
assign _066_ = ~(_065_ ^ _052_);
assign _067_ = ~(_066_ ^ _051_);
assign _068_ = _030_ & _004_;
assign _069_ = _068_ | _067_;
assign _070_ = ~((_050_ & _031_) | _069_);
assign _071_ = ~_062_;
assign _072_ = ~(_059_ & _071_);
assign _073_ = ~((_064_ | _053_) & _072_);
assign _074_ = ~((_065_ & _052_) | _073_);
assign _075_ = ~((_066_ | _051_) & _074_);
assign _076_ = _075_ | _070_;
assign _077_ = ~O;
assign _078_ = ~(B ^ A);
assign _079_ = _078_ ^ _460_;
assign _080_ = _079_ ^ K;
assign _081_ = _080_ & M;
assign _082_ = ~(_079_ & K);
assign _083_ = ~(B | A);
assign _084_ = J ? _450_ : _083_;
assign _085_ = _084_ ^ _082_;
assign _086_ = _085_ ^ L;
assign _087_ = ~(_086_ ^ _081_);
assign _088_ = ~M;
assign _089_ = _080_ ^ _088_;
assign _091_ = _089_ & _087_;
assign _092_ = _091_ | _077_;
assign _093_ = _086_ & _081_;
assign _094_ = ~C;
assign _095_ = _450_ ^ _094_;
assign _096_ = _095_ ^ _449_;
assign _097_ = _096_ ^ G;
assign _098_ = _097_ ^ H;
assign _099_ = _098_ ^ I;
assign _100_ = _083_ & J;
assign _102_ = _100_ ^ _099_;
assign _103_ = _102_ ^ K;
assign _104_ = ~(_084_ | _082_);
assign _105_ = _085_ & L;
assign _106_ = _105_ | _104_;
assign _107_ = _106_ ^ _103_;
assign _108_ = ~(_107_ ^ _093_);
assign _109_ = _108_ ^ N;
assign _110_ = ~(_109_ | _092_);
assign _111_ = _108_ & N;
assign _113_ = _107_ & _093_;
assign _114_ = _103_ & _105_;
assign _115_ = ~_104_;
assign _116_ = ~(_102_ & K);
assign _117_ = ~(_116_ & _115_);
assign _118_ = ~(_083_ | _460_);
assign _119_ = _099_ & J;
assign _120_ = ~(_119_ | _118_);
assign _121_ = _098_ | _101_;
assign _122_ = _095_ | _449_;
assign _124_ = ~((_450_ & _094_) | _083_);
assign _125_ = _124_ ^ _122_;
assign _126_ = _125_ ^ _211_;
assign _127_ = _096_ & G;
assign _128_ = ~((_097_ & H) | _127_);
assign _129_ = ~(_128_ ^ _126_);
assign _130_ = _129_ ^ J;
assign _131_ = ~(_130_ ^ _121_);
assign _132_ = _131_ ^ _120_;
assign _133_ = ~(_132_ ^ _117_);
assign _135_ = _133_ ^ _114_;
assign _136_ = _135_ ^ M;
assign _137_ = ~(_136_ ^ _113_);
assign _138_ = ~(_137_ ^ _111_);
assign _139_ = _138_ & _110_;
assign _140_ = _137_ & _111_;
assign _141_ = ~(_135_ & M);
assign _142_ = ~(_136_ & _113_);
assign _143_ = ~(_142_ & _141_);
assign _144_ = _133_ & _114_;
assign _146_ = ~((_116_ & _115_) | _132_);
assign _147_ = _129_ & J;
assign _148_ = _147_ | _119_;
assign _149_ = ~((_131_ & _118_) | _148_);
assign _150_ = ~((_129_ | _098_) & I);
assign _151_ = ~(_126_ & _127_);
assign _152_ = _125_ & F;
assign _153_ = ~_083_;
assign _154_ = ~(D & C);
assign _155_ = ~((_154_ | _450_) & _153_);
assign _157_ = _155_ ^ _152_;
assign _158_ = _157_ ^ _151_;
assign _159_ = _097_ & H;
assign _160_ = _126_ & _159_;
assign _161_ = _160_ | _277_;
assign _162_ = _161_ ^ _158_;
assign _163_ = ~(_162_ ^ _150_);
assign _164_ = _163_ ^ _149_;
assign _165_ = _164_ ^ _146_;
assign _166_ = _165_ ^ _144_;
assign _168_ = ~(_166_ ^ _143_);
assign _169_ = ~(_168_ ^ _140_);
assign _170_ = _169_ ^ O;
assign _171_ = _170_ ^ _139_;
assign _172_ = _171_ & P;
assign _173_ = _089_ & O;
assign _174_ = _173_ ^ _087_;
assign _175_ = _174_ | _032_;
assign _176_ = ~(_109_ ^ _092_);
assign _177_ = _176_ | _175_;
assign _179_ = ~(_138_ ^ _110_);
assign _180_ = ~(_179_ | _177_);
assign _181_ = _171_ | P;
assign _182_ = ~((_181_ & _180_) | _172_);
assign _183_ = _169_ & O;
assign _184_ = _170_ & _139_;
assign _185_ = _184_ | _183_;
assign _186_ = _166_ & _143_;
assign _187_ = _165_ & _144_;
assign _188_ = _164_ & _146_;
assign _190_ = ~((_158_ & H) | _160_);
assign _191_ = ~(_157_ | _151_);
assign _192_ = _155_ & _125_;
assign _193_ = _192_ | _211_;
assign _194_ = D & C;
assign _195_ = ~((_194_ & _153_) | _450_);
assign _196_ = _195_ ^ _193_;
assign _197_ = ~(_196_ ^ _191_);
assign _198_ = _197_ ^ _190_;
assign _199_ = _162_ | _150_;
assign _201_ = ~((_163_ | _149_) & _199_);
assign _202_ = _201_ ^ _198_;
assign _203_ = _202_ ^ _188_;
assign _204_ = _203_ ^ _187_;
assign _205_ = _204_ ^ _186_;
assign _206_ = _137_ & _108_;
assign _207_ = ~((_168_ & _206_) | _090_);
assign _208_ = _207_ ^ _205_;
assign _209_ = ~(_208_ ^ _185_);
assign _210_ = _209_ | _182_;
assign _212_ = _204_ & _186_;
assign _213_ = ~((_207_ & _205_) | _212_);
assign _214_ = ~(_202_ & _188_);
assign _215_ = ~(_203_ & _187_);
assign _216_ = ~(_215_ & _214_);
assign _217_ = ~(_163_ | _149_);
assign _218_ = ~(_198_ & _217_);
assign _219_ = ~(_162_ | _150_);
assign _220_ = ~(_195_ | _193_);
assign _221_ = ~((_196_ & _191_) | _220_);
assign _223_ = ~((_197_ | _190_) & _221_);
assign _224_ = ~((_198_ & _219_) | _223_);
assign _225_ = ~(_224_ ^ _218_);
assign _226_ = _225_ ^ _216_;
assign _227_ = ~(_226_ | _213_);
assign _228_ = E ^ C;
assign _229_ = _228_ ^ H;
assign _230_ = _229_ ^ K;
assign _231_ = _230_ & L;
assign _232_ = D | C;
assign _234_ = _232_ & _154_;
assign _235_ = E ? _449_ : _234_;
assign _236_ = _235_ ^ G;
assign _237_ = _228_ & H;
assign _238_ = _229_ & K;
assign _239_ = ~(_238_ | _237_);
assign _240_ = ~(_239_ ^ _236_);
assign _241_ = _240_ ^ _231_;
assign _242_ = _241_ ^ _090_;
assign _243_ = _242_ ^ O;
assign _245_ = _230_ ^ L;
assign _246_ = _245_ ^ _039_;
assign _247_ = _236_ & _237_;
assign _248_ = ~G;
assign _249_ = _235_ | _248_;
assign _250_ = _194_ ^ A;
assign _251_ = _232_ & E;
assign _252_ = _251_ ^ _250_;
assign _253_ = _252_ ^ _211_;
assign _254_ = _253_ ^ _249_;
assign _256_ = _254_ ^ _247_;
assign _257_ = _256_ ^ I;
assign _258_ = ~K;
assign _259_ = _238_ & _236_;
assign _260_ = ~(_259_ | _258_);
assign _261_ = _260_ ^ _257_;
assign _262_ = _240_ & _231_;
assign _263_ = ~(_262_ | _408_);
assign _264_ = _263_ ^ _261_;
assign _265_ = ~(_241_ | _090_);
assign _267_ = ~((_242_ & O) | _265_);
assign _268_ = _267_ ^ _264_;
assign _269_ = _268_ ^ _032_;
assign _270_ = ~_264_;
assign _271_ = ~((_242_ & _270_) | _077_);
assign _272_ = ~((_257_ & K) | _259_);
assign _273_ = ~_235_;
assign _274_ = _253_ & _273_;
assign _275_ = _274_ | _248_;
assign _276_ = _252_ | _211_;
assign _278_ = _251_ & _250_;
assign _279_ = _278_ | _427_;
assign _280_ = _429_ & C;
assign _281_ = _280_ ^ _078_;
assign _282_ = _281_ ^ _279_;
assign _283_ = _282_ ^ _276_;
assign _284_ = _283_ ^ _275_;
assign _285_ = _254_ & _247_;
assign _286_ = ~((_256_ & I) | _285_);
assign _287_ = _286_ ^ _284_;
assign _289_ = _287_ ^ _272_;
assign _290_ = _289_ ^ _408_;
assign _291_ = ~((_261_ & L) | _262_);
assign _292_ = ~(_291_ ^ _290_);
assign _293_ = _292_ ^ M;
assign _294_ = _265_ & _270_;
assign _295_ = _294_ ^ _293_;
assign _296_ = ~(_295_ ^ _271_);
assign _297_ = _268_ & P;
assign _298_ = ~(_297_ ^ _296_);
assign _300_ = ~_243_;
assign _301_ = ~(_245_ | _300_);
assign _302_ = _269_ & Q;
assign _303_ = ~((_302_ | _298_) & (_301_ | _039_));
assign _304_ = _301_ & Q;
assign _305_ = ~((_304_ | _269_) & _303_);
assign _306_ = ~((_246_ & _243_) | _305_);
assign _307_ = ~_268_;
assign _308_ = ~((_307_ | _296_) & P);
assign _309_ = ~(_292_ | _088_);
assign _311_ = ~_262_;
assign _312_ = _311_ | _261_;
assign _313_ = ~((_289_ | _261_) & L);
assign _314_ = ~((_312_ | _290_) & _313_);
assign _315_ = ~(_287_ | _272_);
assign _316_ = _284_ & _285_;
assign _317_ = _283_ | _275_;
assign _318_ = _282_ | _276_;
assign _319_ = ~(_281_ | _427_);
assign _320_ = _319_ | _278_;
assign _321_ = ~A;
assign _322_ = B & _321_;
assign _323_ = B | _321_;
assign _324_ = ~((_323_ & _094_) | _322_);
assign _325_ = _324_ ^ D;
assign _326_ = ~((_011_ & C) | _325_);
assign _327_ = _326_ ^ _427_;
assign _328_ = _327_ ^ _320_;
assign _329_ = _328_ ^ _318_;
assign _330_ = _329_ ^ _317_;
assign _333_ = ~(_330_ ^ _316_);
assign _334_ = ~(_284_ & _256_);
assign _335_ = ~(_334_ & I);
assign _336_ = _335_ ^ _333_;
assign _337_ = _336_ ^ _315_;
assign _338_ = _337_ ^ _314_;
assign _339_ = _338_ ^ _309_;
assign _340_ = ~(_241_ | _264_);
assign _341_ = ~((_340_ & _293_) | _090_);
assign _342_ = ~(_341_ ^ _339_);
assign _344_ = ~_295_;
assign _345_ = ~(_344_ & _271_);
assign _346_ = _345_ & O;
assign _347_ = _346_ ^ _342_;
assign _348_ = ~(_347_ | _308_);
assign _349_ = _348_ | Q;
assign _350_ = _349_ | _306_;
assign _351_ = ~((_342_ | _077_) & _345_);
assign _352_ = _337_ & _314_;
assign _353_ = _336_ & _315_;
assign _355_ = ~((_334_ & _333_) | _101_);
assign _356_ = _330_ & _316_;
assign _357_ = ~(_329_ | _317_);
assign _358_ = _282_ | _252_;
assign _359_ = ~((_328_ | _358_) & F);
assign _360_ = ~((_326_ & _281_) | _279_);
assign _361_ = ~(_324_ & D);
assign _362_ = ~(_450_ | C);
assign _363_ = ~((_362_ | _083_) & _361_);
assign _364_ = ~((_194_ & A) | _278_);
assign _366_ = ~((_364_ & _363_) | _360_);
assign _367_ = _366_ ^ _359_;
assign _368_ = ~(_367_ ^ _357_);
assign _369_ = ~(_368_ | _356_);
assign _370_ = _369_ ^ _355_;
assign _371_ = _370_ ^ _353_;
assign _372_ = ~(_371_ ^ _352_);
assign _373_ = _338_ & _309_;
assign _374_ = ~((_341_ & _339_) | _373_);
assign _375_ = _374_ ^ _372_;
assign _377_ = _375_ | _351_;
assign _378_ = ~(_347_ & _308_);
assign _379_ = _378_ & _377_;
assign _380_ = ~((_379_ & _350_) | _227_);
assign _381_ = ~((_184_ | _183_) & _208_);
assign _382_ = ~_301_;
assign _383_ = ~((_269_ | _382_) & Q);
assign _384_ = ~(_383_ | _298_);
assign _385_ = _306_ & Q;
assign _386_ = ~((_385_ | _384_) & (_377_ | _348_));
assign _388_ = _226_ ^ _213_;
assign _389_ = _375_ & _351_;
assign _390_ = _367_ & _357_;
assign _391_ = _390_ | _356_;
assign _392_ = _366_ | _359_;
assign _393_ = _392_ ^ _364_;
assign _394_ = _393_ | _391_;
assign _395_ = _369_ & _355_;
assign _396_ = ~((_370_ & _353_) | _395_);
assign _397_ = _396_ ^ _394_;
assign _398_ = _371_ & _352_;
assign _399_ = _371_ | _352_;
assign _400_ = ~((_398_ | _373_) & _399_);
assign _401_ = ~(_400_ & _397_);
assign _402_ = ~(_341_ & _339_);
assign _403_ = _225_ | _215_;
assign _404_ = _225_ | _214_;
assign _405_ = ~((_392_ | _364_) & (_224_ | _218_));
assign _406_ = ~((_394_ & _395_) | _405_);
assign _407_ = _406_ & _404_;
assign _410_ = _407_ & _403_;
assign _411_ = ~((_372_ | _402_) & _410_);
assign _412_ = ~(_370_ & _353_);
assign _413_ = ~_394_;
assign _414_ = ~((_400_ | _397_) & (_413_ | _412_));
assign _415_ = _414_ | _411_;
assign _416_ = _415_ | _401_;
assign _417_ = _416_ | _389_;
assign _418_ = ~((_388_ & _381_) | _417_);
assign _419_ = _418_ & _386_;
assign _421_ = _419_ & _381_;
assign _422_ = _421_ & _380_;
assign _423_ = _422_ & _210_;
assign valid = _423_ & _076_;
endmodule | module var17_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, valid); |
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _351_;
wire _352_;
wire _353_;
wire _354_;
wire _355_;
wire _356_;
wire _357_;
wire _358_;
wire _359_;
wire _360_;
wire _361_;
wire _362_;
wire _363_;
wire _364_;
wire _365_;
wire _366_;
wire _367_;
wire _368_;
wire _369_;
wire _370_;
wire _371_;
wire _372_;
wire _373_;
wire _374_;
wire _375_;
wire _376_;
wire _377_;
wire _378_;
wire _379_;
wire _380_;
wire _381_;
wire _382_;
wire _383_;
wire _384_;
wire _385_;
wire _386_;
wire _387_;
wire _388_;
wire _389_;
wire _390_;
wire _391_;
wire _392_;
wire _393_;
wire _394_;
wire _395_;
wire _396_;
wire _397_;
wire _398_;
wire _399_;
wire _400_;
wire _401_;
wire _402_;
wire _403_;
wire _404_;
wire _405_;
wire _406_;
wire _407_;
wire _408_;
wire _409_;
wire _410_;
wire _411_;
wire _412_;
wire _413_;
wire _414_;
wire _415_;
wire _416_;
wire _417_;
wire _418_;
wire _419_;
wire _420_;
wire _421_;
wire _422_;
wire _423_;
wire _424_;
wire _425_;
wire _426_;
wire _427_;
wire _428_;
wire _429_;
wire _430_;
wire _431_;
wire _432_;
wire _433_;
wire _434_;
wire _435_;
wire _436_;
wire _437_;
wire _438_;
wire _439_;
wire _440_;
wire _441_;
wire _442_;
wire _443_;
wire _444_;
wire _445_;
wire _446_;
wire _447_;
wire _448_;
wire _449_;
wire _450_;
wire _451_;
wire _452_;
wire _453_;
wire _454_;
wire _455_;
wire _456_;
wire _457_;
wire _458_;
wire _459_;
wire _460_;
wire _461_;
wire _462_;
wire _463_;
wire _464_;
wire _465_;
wire _466_;
wire _467_;
wire _468_;
wire _469_;
wire _470_;
wire _471_;
wire _472_;
wire _473_;
(* src = "var17_multi.v:3" *)
input A;
(* src = "var17_multi.v:3" *)
input B;
(* src = "var17_multi.v:3" *)
input C;
(* src = "var17_multi.v:3" *)
input D;
(* src = "var17_multi.v:3" *)
input E;
(* src = "var17_multi.v:3" *)
input F;
(* src = "var17_multi.v:3" *)
input G;
(* src = "var17_multi.v:3" *)
input H;
(* src = "var17_multi.v:3" *)
input I;
(* src = "var17_multi.v:3" *)
input J;
(* src = "var17_multi.v:3" *)
input K;
(* src = "var17_multi.v:3" *)
input L;
(* src = "var17_multi.v:3" *)
input M;
(* src = "var17_multi.v:3" *)
input N;
(* src = "var17_multi.v:3" *)
input O;
(* src = "var17_multi.v:3" *)
input P;
(* src = "var17_multi.v:3" *)
input Q;
(* src = "var17_multi.v:4" *)
output valid;
assign _090_ = ~N;
assign _101_ = ~I;
assign _112_ = G ^ E;
assign _123_ = _112_ ^ H;
assign _134_ = _123_ ^ _101_;
assign _145_ = _134_ ^ J;
assign _156_ = _145_ ^ K;
assign _167_ = ~(_156_ | _090_);
assign _178_ = ~(_145_ & K);
assign _189_ = ~_178_;
assign _200_ = _112_ & H;
assign _211_ = ~F;
assign _222_ = D ^ A;
assign _233_ = _222_ ^ _211_;
assign _244_ = ~(_233_ & _200_);
assign _255_ = ~(G & E);
assign _266_ = _233_ ^ _255_;
assign _277_ = ~H;
assign _288_ = _112_ | _277_;
assign _299_ = _266_ ? _288_ : H;
assign _310_ = _299_ & _244_;
assign _331_ = _123_ | _101_;
assign _332_ = ~(_134_ & J);
assign _343_ = _332_ & _331_;
assign _354_ = _343_ ^ _310_;
assign _365_ = _354_ ^ _189_;
assign _376_ = ~_365_;
assign _387_ = _376_ & _167_;
assign _408_ = ~L;
assign _409_ = ~(_310_ | _332_);
assign _420_ = ~(_354_ & _189_);
assign _424_ = ~((_310_ | _123_) & I);
assign _425_ = ~(_233_ | _255_);
assign _426_ = _222_ | _211_;
assign _427_ = ~E;
assign _428_ = ~B;
assign _429_ = ~(D & A);
assign _430_ = _429_ ^ _428_;
assign _431_ = _430_ ^ _427_;
assign _432_ = _431_ ^ _426_;
assign _433_ = _432_ ^ _425_;
assign _434_ = ~(_266_ | _277_);
assign _435_ = ~(_434_ & _244_);
assign _436_ = _435_ ^ _433_;
assign _437_ = _436_ ^ _424_;
assign _438_ = _437_ ^ _420_;
assign _439_ = _438_ ^ _409_;
assign _440_ = _439_ ^ _408_;
assign _441_ = _440_ & _387_;
assign _442_ = _439_ | _408_;
assign _443_ = _437_ | _420_;
assign _444_ = ~(_436_ | _424_);
assign _445_ = ~((_433_ | _266_) & H);
assign _446_ = ~((_433_ | _244_) & _445_);
assign _447_ = _432_ & _425_;
assign _448_ = _430_ & E;
assign _449_ = ~D;
assign _450_ = B & A;
assign _451_ = ~(_450_ | _449_);
assign _452_ = _451_ ^ _448_;
assign _453_ = ~_222_;
assign _454_ = ~((_431_ & _453_) | _211_);
assign _455_ = _454_ ^ _452_;
assign _456_ = _455_ ^ G;
assign _457_ = _456_ ^ _447_;
assign _458_ = _457_ ^ _446_;
assign _459_ = _458_ ^ _444_;
assign _460_ = ~J;
assign _461_ = ~_310_;
assign _462_ = _461_ & _134_;
assign _463_ = ~_437_;
assign _464_ = ~((_463_ & _462_) | _460_);
assign _465_ = _464_ ^ _459_;
assign _466_ = _465_ ^ _443_;
assign _467_ = _466_ ^ _442_;
assign _468_ = _467_ ^ M;
assign _469_ = _468_ ^ N;
assign _470_ = _469_ ^ _441_;
assign _471_ = _470_ & O;
assign _472_ = _156_ ^ _090_;
assign _473_ = _472_ & O;
assign _000_ = _473_ & _376_;
assign _001_ = _440_ ^ _387_;
assign _002_ = _001_ & _000_;
assign _003_ = _470_ ^ O;
assign _004_ = ~((_003_ & _002_) | _471_);
assign _005_ = _468_ & N;
assign _006_ = ~((_469_ & _441_) | _005_);
assign _007_ = _464_ & _459_;
assign _008_ = ~(_455_ & G);
assign _009_ = ~(_456_ & _447_);
assign _010_ = _009_ & _008_;
assign _011_ = _450_ & D;
assign _012_ = _451_ & _448_;
assign _013_ = _012_ | _011_;
assign _014_ = ~((_454_ & _452_) | _013_);
assign _015_ = _014_ ^ _010_;
assign _016_ = ~(_457_ & _446_);
assign _017_ = ~(_458_ & _444_);
assign _018_ = _017_ & _016_;
assign _019_ = _018_ ^ _015_;
assign _020_ = ~(_019_ ^ _007_);
assign _021_ = ~(_354_ & _145_);
assign _022_ = _437_ | _021_;
assign _023_ = _465_ | _022_;
assign _024_ = _023_ & K;
assign _025_ = ~(_024_ ^ _020_);
assign _026_ = _466_ | _442_;
assign _027_ = ~(_467_ & M);
assign _028_ = _027_ & _026_;
assign _029_ = ~(_028_ ^ _025_);
assign _030_ = ~(_029_ ^ _006_);
assign _031_ = _030_ | _004_;
assign _032_ = ~P;
assign _033_ = ~(_473_ | _167_);
assign _034_ = _033_ ^ _376_;
assign _035_ = _001_ ^ _000_;
assign _036_ = _472_ ^ O;
assign _037_ = ~(_036_ | _035_);
assign _038_ = ~((_037_ & _034_) | _032_);
assign _039_ = ~Q;
assign _040_ = ~(_036_ | _032_);
assign _041_ = _040_ | J;
assign _042_ = ~((_036_ & _032_) | _041_);
assign _043_ = ~((_042_ & _034_) | _039_);
assign _044_ = _040_ & _034_;
assign _045_ = _044_ ^ _035_;
assign _046_ = _045_ | _043_;
assign _047_ = _046_ | _038_;
assign _048_ = _003_ ^ _002_;
assign _049_ = _046_ & _038_;
assign _050_ = ~((_049_ | _048_) & _047_);
assign _051_ = _029_ | _006_;
assign _052_ = ~(_025_ | _027_);
assign _053_ = _025_ | _026_;
assign _054_ = ~_015_;
assign _055_ = ~_016_;
assign _056_ = ~(_014_ | _010_);
assign _057_ = ~(_014_ & _010_);
assign _058_ = ~((_057_ & _055_) | _056_);
assign _059_ = ~((_054_ | _017_) & _058_);
assign _060_ = ~_007_;
assign _061_ = _019_ | _060_;
assign _062_ = ~(_024_ & _020_);
assign _063_ = _062_ & _061_;
assign _064_ = _063_ ^ _059_;
assign _065_ = _064_ ^ _053_;
assign _066_ = ~(_065_ ^ _052_);
assign _067_ = ~(_066_ ^ _051_);
assign _068_ = _030_ & _004_;
assign _069_ = _068_ | _067_;
assign _070_ = ~((_050_ & _031_) | _069_);
assign _071_ = ~_062_;
assign _072_ = ~(_059_ & _071_);
assign _073_ = ~((_064_ | _053_) & _072_);
assign _074_ = ~((_065_ & _052_) | _073_);
assign _075_ = ~((_066_ | _051_) & _074_);
assign _076_ = _075_ | _070_;
assign _077_ = ~O;
assign _078_ = ~(B ^ A);
assign _079_ = _078_ ^ _460_;
assign _080_ = _079_ ^ K;
assign _081_ = _080_ & M;
assign _082_ = ~(_079_ & K);
assign _083_ = ~(B | A);
assign _084_ = J ? _450_ : _083_;
assign _085_ = _084_ ^ _082_;
assign _086_ = _085_ ^ L;
assign _087_ = ~(_086_ ^ _081_);
assign _088_ = ~M;
assign _089_ = _080_ ^ _088_;
assign _091_ = _089_ & _087_;
assign _092_ = _091_ | _077_;
assign _093_ = _086_ & _081_;
assign _094_ = ~C;
assign _095_ = _450_ ^ _094_;
assign _096_ = _095_ ^ _449_;
assign _097_ = _096_ ^ G;
assign _098_ = _097_ ^ H;
assign _099_ = _098_ ^ I;
assign _100_ = _083_ & J;
assign _102_ = _100_ ^ _099_;
assign _103_ = _102_ ^ K;
assign _104_ = ~(_084_ | _082_);
assign _105_ = _085_ & L;
assign _106_ = _105_ | _104_;
assign _107_ = _106_ ^ _103_;
assign _108_ = ~(_107_ ^ _093_);
assign _109_ = _108_ ^ N;
assign _110_ = ~(_109_ | _092_);
assign _111_ = _108_ & N;
assign _113_ = _107_ & _093_;
assign _114_ = _103_ & _105_;
assign _115_ = ~_104_;
assign _116_ = ~(_102_ & K);
assign _117_ = ~(_116_ & _115_);
assign _118_ = ~(_083_ | _460_);
assign _119_ = _099_ & J;
assign _120_ = ~(_119_ | _118_);
assign _121_ = _098_ | _101_;
assign _122_ = _095_ | _449_;
assign _124_ = ~((_450_ & _094_) | _083_);
assign _125_ = _124_ ^ _122_;
assign _126_ = _125_ ^ _211_;
assign _127_ = _096_ & G;
assign _128_ = ~((_097_ & H) | _127_);
assign _129_ = ~(_128_ ^ _126_);
assign _130_ = _129_ ^ J;
assign _131_ = ~(_130_ ^ _121_);
assign _132_ = _131_ ^ _120_;
assign _133_ = ~(_132_ ^ _117_);
assign _135_ = _133_ ^ _114_;
assign _136_ = _135_ ^ M;
assign _137_ = ~(_136_ ^ _113_);
assign _138_ = ~(_137_ ^ _111_);
assign _139_ = _138_ & _110_;
assign _140_ = _137_ & _111_;
assign _141_ = ~(_135_ & M);
assign _142_ = ~(_136_ & _113_);
assign _143_ = ~(_142_ & _141_);
assign _144_ = _133_ & _114_;
assign _146_ = ~((_116_ & _115_) | _132_);
assign _147_ = _129_ & J;
assign _148_ = _147_ | _119_;
assign _149_ = ~((_131_ & _118_) | _148_);
assign _150_ = ~((_129_ | _098_) & I);
assign _151_ = ~(_126_ & _127_);
assign _152_ = _125_ & F;
assign _153_ = ~_083_;
assign _154_ = ~(D & C);
assign _155_ = ~((_154_ | _450_) & _153_);
assign _157_ = _155_ ^ _152_;
assign _158_ = _157_ ^ _151_;
assign _159_ = _097_ & H;
assign _160_ = _126_ & _159_;
assign _161_ = _160_ | _277_;
assign _162_ = _161_ ^ _158_;
assign _163_ = ~(_162_ ^ _150_);
assign _164_ = _163_ ^ _149_;
assign _165_ = _164_ ^ _146_;
assign _166_ = _165_ ^ _144_;
assign _168_ = ~(_166_ ^ _143_);
assign _169_ = ~(_168_ ^ _140_);
assign _170_ = _169_ ^ O;
assign _171_ = _170_ ^ _139_;
assign _172_ = _171_ & P;
assign _173_ = _089_ & O;
assign _174_ = _173_ ^ _087_;
assign _175_ = _174_ | _032_;
assign _176_ = ~(_109_ ^ _092_);
assign _177_ = _176_ | _175_;
assign _179_ = ~(_138_ ^ _110_);
assign _180_ = ~(_179_ | _177_);
assign _181_ = _171_ | P;
assign _182_ = ~((_181_ & _180_) | _172_);
assign _183_ = _169_ & O;
assign _184_ = _170_ & _139_;
assign _185_ = _184_ | _183_;
assign _186_ = _166_ & _143_;
assign _187_ = _165_ & _144_;
assign _188_ = _164_ & _146_;
assign _190_ = ~((_158_ & H) | _160_);
assign _191_ = ~(_157_ | _151_);
assign _192_ = _155_ & _125_;
assign _193_ = _192_ | _211_;
assign _194_ = D & C;
assign _195_ = ~((_194_ & _153_) | _450_);
assign _196_ = _195_ ^ _193_;
assign _197_ = ~(_196_ ^ _191_);
assign _198_ = _197_ ^ _190_;
assign _199_ = _162_ | _150_;
assign _201_ = ~((_163_ | _149_) & _199_);
assign _202_ = _201_ ^ _198_;
assign _203_ = _202_ ^ _188_;
assign _204_ = _203_ ^ _187_;
assign _205_ = _204_ ^ _186_;
assign _206_ = _137_ & _108_;
assign _207_ = ~((_168_ & _206_) | _090_);
assign _208_ = _207_ ^ _205_;
assign _209_ = ~(_208_ ^ _185_);
assign _210_ = _209_ | _182_;
assign _212_ = _204_ & _186_;
assign _213_ = ~((_207_ & _205_) | _212_);
assign _214_ = ~(_202_ & _188_);
assign _215_ = ~(_203_ & _187_);
assign _216_ = ~(_215_ & _214_);
assign _217_ = ~(_163_ | _149_);
assign _218_ = ~(_198_ & _217_);
assign _219_ = ~(_162_ | _150_);
assign _220_ = ~(_195_ | _193_);
assign _221_ = ~((_196_ & _191_) | _220_);
assign _223_ = ~((_197_ | _190_) & _221_);
assign _224_ = ~((_198_ & _219_) | _223_);
assign _225_ = ~(_224_ ^ _218_);
assign _226_ = _225_ ^ _216_;
assign _227_ = ~(_226_ | _213_);
assign _228_ = E ^ C;
assign _229_ = _228_ ^ H;
assign _230_ = _229_ ^ K;
assign _231_ = _230_ & L;
assign _232_ = D | C;
assign _234_ = _232_ & _154_;
assign _235_ = E ? _449_ : _234_;
assign _236_ = _235_ ^ G;
assign _237_ = _228_ & H;
assign _238_ = _229_ & K;
assign _239_ = ~(_238_ | _237_);
assign _240_ = ~(_239_ ^ _236_);
assign _241_ = _240_ ^ _231_;
assign _242_ = _241_ ^ _090_;
assign _243_ = _242_ ^ O;
assign _245_ = _230_ ^ L;
assign _246_ = _245_ ^ _039_;
assign _247_ = _236_ & _237_;
assign _248_ = ~G;
assign _249_ = _235_ | _248_;
assign _250_ = _194_ ^ A;
assign _251_ = _232_ & E;
assign _252_ = _251_ ^ _250_;
assign _253_ = _252_ ^ _211_;
assign _254_ = _253_ ^ _249_;
assign _256_ = _254_ ^ _247_;
assign _257_ = _256_ ^ I;
assign _258_ = ~K;
assign _259_ = _238_ & _236_;
assign _260_ = ~(_259_ | _258_);
assign _261_ = _260_ ^ _257_;
assign _262_ = _240_ & _231_;
assign _263_ = ~(_262_ | _408_);
assign _264_ = _263_ ^ _261_;
assign _265_ = ~(_241_ | _090_);
assign _267_ = ~((_242_ & O) | _265_);
assign _268_ = _267_ ^ _264_;
assign _269_ = _268_ ^ _032_;
assign _270_ = ~_264_;
assign _271_ = ~((_242_ & _270_) | _077_);
assign _272_ = ~((_257_ & K) | _259_);
assign _273_ = ~_235_;
assign _274_ = _253_ & _273_;
assign _275_ = _274_ | _248_;
assign _276_ = _252_ | _211_;
assign _278_ = _251_ & _250_;
assign _279_ = _278_ | _427_;
assign _280_ = _429_ & C;
assign _281_ = _280_ ^ _078_;
assign _282_ = _281_ ^ _279_;
assign _283_ = _282_ ^ _276_;
assign _284_ = _283_ ^ _275_;
assign _285_ = _254_ & _247_;
assign _286_ = ~((_256_ & I) | _285_);
assign _287_ = _286_ ^ _284_;
assign _289_ = _287_ ^ _272_;
assign _290_ = _289_ ^ _408_;
assign _291_ = ~((_261_ & L) | _262_);
assign _292_ = ~(_291_ ^ _290_);
assign _293_ = _292_ ^ M;
assign _294_ = _265_ & _270_;
assign _295_ = _294_ ^ _293_;
assign _296_ = ~(_295_ ^ _271_);
assign _297_ = _268_ & P;
assign _298_ = ~(_297_ ^ _296_);
assign _300_ = ~_243_;
assign _301_ = ~(_245_ | _300_);
assign _302_ = _269_ & Q;
assign _303_ = ~((_302_ | _298_) & (_301_ | _039_));
assign _304_ = _301_ & Q;
assign _305_ = ~((_304_ | _269_) & _303_);
assign _306_ = ~((_246_ & _243_) | _305_);
assign _307_ = ~_268_;
assign _308_ = ~((_307_ | _296_) & P);
assign _309_ = ~(_292_ | _088_);
assign _311_ = ~_262_;
assign _312_ = _311_ | _261_;
assign _313_ = ~((_289_ | _261_) & L);
assign _314_ = ~((_312_ | _290_) & _313_);
assign _315_ = ~(_287_ | _272_);
assign _316_ = _284_ & _285_;
assign _317_ = _283_ | _275_;
assign _318_ = _282_ | _276_;
assign _319_ = ~(_281_ | _427_);
assign _320_ = _319_ | _278_;
assign _321_ = ~A;
assign _322_ = B & _321_;
assign _323_ = B | _321_;
assign _324_ = ~((_323_ & _094_) | _322_);
assign _325_ = _324_ ^ D;
assign _326_ = ~((_011_ & C) | _325_);
assign _327_ = _326_ ^ _427_;
assign _328_ = _327_ ^ _320_;
assign _329_ = _328_ ^ _318_;
assign _330_ = _329_ ^ _317_;
assign _333_ = ~(_330_ ^ _316_);
assign _334_ = ~(_284_ & _256_);
assign _335_ = ~(_334_ & I);
assign _336_ = _335_ ^ _333_;
assign _337_ = _336_ ^ _315_;
assign _338_ = _337_ ^ _314_;
assign _339_ = _338_ ^ _309_;
assign _340_ = ~(_241_ | _264_);
assign _341_ = ~((_340_ & _293_) | _090_);
assign _342_ = ~(_341_ ^ _339_);
assign _344_ = ~_295_;
assign _345_ = ~(_344_ & _271_);
assign _346_ = _345_ & O;
assign _347_ = _346_ ^ _342_;
assign _348_ = ~(_347_ | _308_);
assign _349_ = _348_ | Q;
assign _350_ = _349_ | _306_;
assign _351_ = ~((_342_ | _077_) & _345_);
assign _352_ = _337_ & _314_;
assign _353_ = _336_ & _315_;
assign _355_ = ~((_334_ & _333_) | _101_);
assign _356_ = _330_ & _316_;
assign _357_ = ~(_329_ | _317_);
assign _358_ = _282_ | _252_;
assign _359_ = ~((_328_ | _358_) & F);
assign _360_ = ~((_326_ & _281_) | _279_);
assign _361_ = ~(_324_ & D);
assign _362_ = ~(_450_ | C);
assign _363_ = ~((_362_ | _083_) & _361_);
assign _364_ = ~((_194_ & A) | _278_);
assign _366_ = ~((_364_ & _363_) | _360_);
assign _367_ = _366_ ^ _359_;
assign _368_ = ~(_367_ ^ _357_);
assign _369_ = ~(_368_ | _356_);
assign _370_ = _369_ ^ _355_;
assign _371_ = _370_ ^ _353_;
assign _372_ = ~(_371_ ^ _352_);
assign _373_ = _338_ & _309_;
assign _374_ = ~((_341_ & _339_) | _373_);
assign _375_ = _374_ ^ _372_;
assign _377_ = _375_ | _351_;
assign _378_ = ~(_347_ & _308_);
assign _379_ = _378_ & _377_;
assign _380_ = ~((_379_ & _350_) | _227_);
assign _381_ = ~((_184_ | _183_) & _208_);
assign _382_ = ~_301_;
assign _383_ = ~((_269_ | _382_) & Q);
assign _384_ = ~(_383_ | _298_);
assign _385_ = _306_ & Q;
assign _386_ = ~((_385_ | _384_) & (_377_ | _348_));
assign _388_ = _226_ ^ _213_;
assign _389_ = _375_ & _351_;
assign _390_ = _367_ & _357_;
assign _391_ = _390_ | _356_;
assign _392_ = _366_ | _359_;
assign _393_ = _392_ ^ _364_;
assign _394_ = _393_ | _391_;
assign _395_ = _369_ & _355_;
assign _396_ = ~((_370_ & _353_) | _395_);
assign _397_ = _396_ ^ _394_;
assign _398_ = _371_ & _352_;
assign _399_ = _371_ | _352_;
assign _400_ = ~((_398_ | _373_) & _399_);
assign _401_ = ~(_400_ & _397_);
assign _402_ = ~(_341_ & _339_);
assign _403_ = _225_ | _215_;
assign _404_ = _225_ | _214_;
assign _405_ = ~((_392_ | _364_) & (_224_ | _218_));
assign _406_ = ~((_394_ & _395_) | _405_);
assign _407_ = _406_ & _404_;
assign _410_ = _407_ & _403_;
assign _411_ = ~((_372_ | _402_) & _410_);
assign _412_ = ~(_370_ & _353_);
assign _413_ = ~_394_;
assign _414_ = ~((_400_ | _397_) & (_413_ | _412_));
assign _415_ = _414_ | _411_;
assign _416_ = _415_ | _401_;
assign _417_ = _416_ | _389_;
assign _418_ = ~((_388_ & _381_) | _417_);
assign _419_ = _418_ & _386_;
assign _421_ = _419_ & _381_;
assign _422_ = _421_ & _380_;
assign _423_ = _422_ & _210_;
assign valid = _423_ & _076_;
endmodule | 5 |
138,108 | data/full_repos/permissive/81900704/output/vs/opt_var18_multi.v | 81,900,704 | opt_var18_multi.v | v | 1,082 | 115 | [] | [] | [] | [(5, 1081)] | null | data/verilator_xmls/05509761-4542-4fa1-ab44-8ed47008585d.xml | null | 301,804 | module | module var18_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, valid);
wire _0000_;
wire _0001_;
wire _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
(* src = "var18_multi.v:3" *)
input A;
(* src = "var18_multi.v:3" *)
input B;
(* src = "var18_multi.v:3" *)
input C;
(* src = "var18_multi.v:3" *)
input D;
(* src = "var18_multi.v:3" *)
input E;
(* src = "var18_multi.v:3" *)
input F;
(* src = "var18_multi.v:3" *)
input G;
(* src = "var18_multi.v:3" *)
input H;
(* src = "var18_multi.v:3" *)
input I;
(* src = "var18_multi.v:3" *)
input J;
(* src = "var18_multi.v:3" *)
input K;
(* src = "var18_multi.v:3" *)
input L;
(* src = "var18_multi.v:3" *)
input M;
(* src = "var18_multi.v:3" *)
input N;
(* src = "var18_multi.v:3" *)
input O;
(* src = "var18_multi.v:3" *)
input P;
(* src = "var18_multi.v:3" *)
input Q;
(* src = "var18_multi.v:3" *)
input R;
(* src = "var18_multi.v:4" *)
output valid;
assign _0100_ = ~K;
assign _0111_ = ~J;
assign _0122_ = ~(B | A);
assign _0133_ = B & A;
assign _0144_ = ~(_0133_ | _0122_);
assign _0155_ = _0144_ ^ _0111_;
assign _0166_ = _0155_ ^ _0100_;
assign _0177_ = _0166_ & M;
assign _0188_ = ~(_0155_ | _0100_);
assign _0199_ = B | A;
assign _0210_ = ~(B & A);
assign _0221_ = J ? _0210_ : _0199_;
assign _0232_ = _0221_ ^ _0188_;
assign _0243_ = _0232_ ^ L;
assign _0254_ = _0243_ ^ _0177_;
assign _0265_ = ~O;
assign _0276_ = _0166_ ^ M;
assign _0297_ = ~(_0276_ | _0265_);
assign _0298_ = _0297_ ^ _0254_;
assign _0309_ = _0298_ & P;
assign _0320_ = ~((_0276_ | _0254_) & O);
assign _0331_ = ~N;
assign _0342_ = _0243_ & _0177_;
assign _0353_ = ~I;
assign _0374_ = ~D;
assign _0375_ = ~C;
assign _0386_ = _0133_ ^ _0375_;
assign _0397_ = _0386_ ^ _0374_;
assign _0408_ = _0397_ ^ G;
assign _0419_ = _0408_ ^ H;
assign _0430_ = _0419_ ^ _0353_;
assign _0441_ = _0122_ & J;
assign _0452_ = ~(_0441_ ^ _0430_);
assign _0463_ = _0452_ ^ K;
assign _0472_ = _0221_ & _0188_;
assign _0473_ = _0232_ & L;
assign _0474_ = _0473_ | _0472_;
assign _0475_ = _0474_ ^ _0463_;
assign _0476_ = _0475_ ^ _0342_;
assign _0477_ = _0476_ ^ _0331_;
assign _0478_ = _0477_ ^ _0320_;
assign _0479_ = _0478_ & _0309_;
assign _0480_ = _0477_ | _0320_;
assign _0481_ = _0476_ | _0331_;
assign _0482_ = ~(_0475_ & _0342_);
assign _0483_ = _0463_ & _0473_;
assign _0484_ = ~((_0452_ & K) | _0472_);
assign _0485_ = ~(_0441_ & _0430_);
assign _0486_ = ~(_0419_ | _0353_);
assign _0487_ = _0386_ | _0374_;
assign _0488_ = D & C;
assign _0489_ = _0488_ & _0144_;
assign _0490_ = ~((_0210_ | C) & _0199_);
assign _0491_ = ~((_0490_ & _0487_) | _0489_);
assign _0492_ = _0491_ ^ F;
assign _0493_ = _0397_ & G;
assign _0494_ = ~((_0408_ & H) | _0493_);
assign _0495_ = ~(_0494_ ^ _0492_);
assign _0496_ = _0495_ ^ _0486_;
assign _0497_ = _0496_ ^ _0485_;
assign _0498_ = _0497_ ^ _0484_;
assign _0499_ = _0498_ ^ _0483_;
assign _0500_ = ~(_0499_ ^ M);
assign _0501_ = _0500_ ^ _0482_;
assign _0502_ = _0501_ ^ _0481_;
assign _0503_ = _0502_ ^ _0480_;
assign _0504_ = _0503_ & _0479_;
assign _0505_ = ~(_0502_ | _0480_);
assign _0506_ = ~(_0501_ | _0481_);
assign _0507_ = ~(_0499_ & M);
assign _0508_ = ~((_0500_ | _0482_) & _0507_);
assign _0509_ = _0498_ & _0483_;
assign _0510_ = ~(_0497_ | _0484_);
assign _0511_ = _0495_ | _0419_;
assign _0512_ = _0511_ & I;
assign _0513_ = ~(_0492_ & _0493_);
assign _0514_ = ~F;
assign _0515_ = _0491_ | _0514_;
assign _0516_ = ~(_0489_ | _0122_);
assign _0517_ = _0516_ ^ _0515_;
assign _0000_ = ~(_0517_ ^ _0513_);
assign _0001_ = _0408_ & H;
assign _0002_ = ~(_0492_ & _0001_);
assign _0003_ = ~(_0002_ & H);
assign _0004_ = _0003_ ^ _0000_;
assign _0005_ = _0004_ ^ _0512_;
assign _0006_ = ~(_0495_ | _0199_);
assign _0007_ = ~((_0006_ & _0430_) | _0111_);
assign _0008_ = _0007_ ^ _0005_;
assign _0009_ = _0008_ ^ _0510_;
assign _0010_ = _0009_ ^ _0509_;
assign _0011_ = _0010_ ^ _0508_;
assign _0012_ = _0011_ ^ _0506_;
assign _0013_ = _0012_ ^ O;
assign _0014_ = _0013_ ^ _0505_;
assign _0015_ = _0014_ ^ P;
assign _0016_ = _0015_ ^ _0504_;
assign _0017_ = _0016_ & Q;
assign _0018_ = ~(_0014_ & P);
assign _0019_ = ~(_0015_ & _0504_);
assign _0020_ = ~(_0019_ & _0018_);
assign _0021_ = ~(_0012_ & O);
assign _0022_ = ~(_0013_ & _0505_);
assign _0023_ = ~(_0022_ & _0021_);
assign _0024_ = _0010_ & _0508_;
assign _0025_ = _0007_ & _0005_;
assign _0026_ = _0004_ & _0512_;
assign _0027_ = ~H;
assign _0028_ = ~((_0000_ | _0027_) & _0002_);
assign _0029_ = ~(_0517_ | _0513_);
assign _0030_ = _0489_ | _0133_;
assign _0031_ = _0516_ | _0491_;
assign _0032_ = _0031_ & F;
assign _0033_ = _0032_ ^ _0030_;
assign _0034_ = _0033_ ^ _0029_;
assign _0035_ = _0034_ ^ _0028_;
assign _0036_ = _0035_ ^ _0026_;
assign _0037_ = _0036_ ^ _0025_;
assign _0038_ = _0008_ & _0510_;
assign _0039_ = ~((_0009_ & _0509_) | _0038_);
assign _0040_ = ~(_0039_ ^ _0037_);
assign _0041_ = ~(_0040_ ^ _0024_);
assign _0042_ = _0501_ | _0476_;
assign _0043_ = ~((_0011_ | _0042_) & N);
assign _0044_ = _0043_ ^ _0041_;
assign _0045_ = _0044_ ^ _0023_;
assign _0046_ = _0045_ ^ _0020_;
assign _0047_ = _0046_ | _0017_;
assign _0048_ = _0503_ ^ _0479_;
assign _0049_ = ~(_0048_ & Q);
assign _0050_ = ~_0503_;
assign _0051_ = _0478_ ^ _0309_;
assign _0052_ = _0051_ & Q;
assign _0053_ = _0298_ ^ P;
assign _0054_ = ~(_0053_ & Q);
assign _0055_ = ~(_0054_ | _0478_);
assign _0056_ = ~((_0055_ & _0050_) | _0052_);
assign _0057_ = _0056_ & _0049_;
assign _0058_ = ~Q;
assign _0059_ = _0016_ ^ _0058_;
assign _0060_ = ~(_0059_ | _0057_);
assign _0061_ = _0276_ ^ _0265_;
assign _0062_ = _0053_ ^ _0058_;
assign _0063_ = _0062_ & _0061_;
assign _0064_ = _0055_ | _0052_;
assign _0065_ = _0048_ ^ Q;
assign _0066_ = ~(_0065_ ^ _0064_);
assign _0067_ = ~_0066_;
assign _0068_ = ~(_0053_ | _0058_);
assign _0069_ = ~(_0068_ ^ _0051_);
assign _0070_ = ~(_0069_ | _0063_);
assign _0071_ = ~((_0070_ & _0067_) | R);
assign _0072_ = _0069_ & _0066_;
assign _0073_ = ~((_0072_ & _0063_) | _0071_);
assign _0074_ = ~(_0059_ & _0057_);
assign _0075_ = ~(_0074_ & _0073_);
assign _0076_ = ~(_0075_ | _0060_);
assign _0077_ = ~L;
assign _0078_ = G ^ E;
assign _0079_ = _0078_ ^ _0027_;
assign _0080_ = _0079_ ^ I;
assign _0081_ = _0080_ ^ J;
assign _0082_ = _0081_ & K;
assign _0083_ = _0079_ & I;
assign _0084_ = ~(G & E);
assign _0085_ = D & A;
assign _0086_ = ~(D | A);
assign _0087_ = ~(_0086_ | _0085_);
assign _0088_ = _0087_ ^ _0514_;
assign _0089_ = _0088_ ^ _0084_;
assign _0090_ = ~(_0078_ | _0027_);
assign _0091_ = ~(_0088_ ^ _0084_);
assign _0092_ = ~(_0091_ & _0090_);
assign _0093_ = _0091_ | _0090_;
assign _0094_ = _0093_ & _0092_;
assign _0095_ = _0083_ ? _0089_ : _0094_;
assign _0096_ = _0095_ & _0082_;
assign _0097_ = ~(_0080_ & J);
assign _0098_ = ~_0094_;
assign _0099_ = _0098_ | _0097_;
assign _0101_ = ~((_0091_ & _0079_) | _0353_);
assign _0102_ = ~(_0088_ | _0084_);
assign _0103_ = _0087_ | _0514_;
assign _0104_ = ~E;
assign _0105_ = _0085_ ^ B;
assign _0106_ = _0105_ ^ _0104_;
assign _0107_ = _0106_ ^ _0103_;
assign _0108_ = _0107_ ^ _0102_;
assign _0109_ = ~(_0108_ ^ _0092_);
assign _0110_ = _0109_ ^ _0101_;
assign _0112_ = _0110_ ^ _0099_;
assign _0113_ = _0112_ ^ _0096_;
assign _0114_ = _0113_ | _0077_;
assign _0115_ = _0112_ & _0096_;
assign _0116_ = _0109_ & _0101_;
assign _0117_ = _0107_ & _0102_;
assign _0118_ = ~(_0105_ & E);
assign _0119_ = E & D;
assign _0120_ = _0119_ & _0144_;
assign _0121_ = _0133_ | _0374_;
assign _0123_ = ~((_0121_ & _0118_) | _0120_);
assign _0124_ = ~_0087_;
assign _0125_ = ~((_0106_ & _0124_) | _0514_);
assign _0126_ = _0125_ ^ _0123_;
assign _0127_ = _0126_ ^ G;
assign _0128_ = _0127_ ^ _0117_;
assign _0129_ = ~(_0108_ | _0078_);
assign _0130_ = ~((_0129_ & _0091_) | _0027_);
assign _0131_ = _0130_ ^ _0128_;
assign _0132_ = _0131_ ^ _0116_;
assign _0134_ = ~(_0094_ & _0080_);
assign _0135_ = _0110_ | _0134_;
assign _0136_ = _0135_ & J;
assign _0137_ = ~(_0136_ ^ _0132_);
assign _0138_ = _0137_ ^ _0115_;
assign _0139_ = _0138_ ^ _0114_;
assign _0140_ = _0139_ ^ M;
assign _0141_ = _0140_ & N;
assign _0142_ = _0097_ ? _0095_ : _0098_;
assign _0143_ = ~(_0142_ ^ _0082_);
assign _0145_ = _0081_ ^ K;
assign _0146_ = ~(_0145_ | _0331_);
assign _0147_ = _0146_ & _0143_;
assign _0148_ = _0113_ ^ _0077_;
assign _0149_ = _0148_ & _0147_;
assign _0150_ = _0140_ ^ N;
assign _0151_ = ~((_0150_ & _0149_) | _0141_);
assign _0152_ = _0136_ & _0132_;
assign _0153_ = _0126_ & G;
assign _0154_ = ~((_0127_ & _0117_) | _0153_);
assign _0156_ = _0133_ & D;
assign _0157_ = _0120_ | _0156_;
assign _0158_ = ~((_0125_ & _0123_) | _0157_);
assign _0159_ = _0158_ ^ _0154_;
assign _0160_ = _0130_ & _0128_;
assign _0161_ = ~((_0131_ & _0116_) | _0160_);
assign _0162_ = _0161_ ^ _0159_;
assign _0163_ = ~(_0162_ ^ _0152_);
assign _0164_ = _0095_ & _0081_;
assign _0165_ = _0164_ & _0112_;
assign _0167_ = ~((_0165_ & _0137_) | _0100_);
assign _0168_ = _0167_ ^ _0163_;
assign _0169_ = _0138_ | _0114_;
assign _0170_ = ~(_0139_ & M);
assign _0171_ = _0170_ & _0169_;
assign _0172_ = _0171_ ^ _0168_;
assign _0173_ = ~(_0172_ | _0151_);
assign _0174_ = ~_0170_;
assign _0175_ = _0168_ & _0174_;
assign _0176_ = ~_0169_;
assign _0178_ = _0168_ & _0176_;
assign _0179_ = ~(_0167_ & _0163_);
assign _0180_ = _0158_ | _0154_;
assign _0181_ = ~_0159_;
assign _0182_ = _0161_ | _0181_;
assign _0183_ = _0182_ & _0180_;
assign _0184_ = ~_0152_;
assign _0185_ = ~((_0162_ | _0184_) & _0179_);
assign _0186_ = _0183_ ? _0185_ : _0179_;
assign _0187_ = _0186_ ^ _0178_;
assign _0189_ = _0187_ ^ _0175_;
assign _0190_ = ~(_0189_ & _0173_);
assign _0191_ = ~(_0186_ & _0178_);
assign _0192_ = ~((_0183_ | _0179_) & _0191_);
assign _0193_ = ~((_0187_ & _0175_) | _0192_);
assign _0194_ = ~(_0193_ & _0190_);
assign _0195_ = _0145_ ^ _0331_;
assign _0196_ = _0195_ & O;
assign _0197_ = _0196_ & _0143_;
assign _0198_ = _0148_ ^ _0147_;
assign _0200_ = _0198_ ^ _0197_;
assign _0201_ = ~(_0196_ | _0146_);
assign _0202_ = _0201_ ^ _0143_;
assign _0203_ = _0195_ ^ O;
assign _0204_ = ~_0203_;
assign _0205_ = ~(_0204_ & _0202_);
assign _0206_ = ~((_0205_ | _0200_) & P);
assign _0207_ = _0198_ & _0197_;
assign _0208_ = _0150_ ^ _0149_;
assign _0209_ = _0208_ ^ O;
assign _0211_ = ~(_0209_ ^ _0207_);
assign _0212_ = _0208_ & O;
assign _0213_ = _0209_ & _0207_;
assign _0214_ = _0213_ | _0212_;
assign _0215_ = _0172_ ^ _0151_;
assign _0216_ = ~(_0215_ | _0214_);
assign _0217_ = _0215_ & _0214_;
assign _0218_ = ~P;
assign _0219_ = ~(_0203_ | _0218_);
assign _0220_ = _0219_ & _0202_;
assign _0222_ = _0220_ ^ _0200_;
assign _0223_ = _0203_ ^ _0218_;
assign _0224_ = _0223_ & _0202_;
assign _0225_ = ~((_0224_ & _0111_) | _0058_);
assign _0226_ = ~R;
assign _0227_ = Q ^ J;
assign _0228_ = ~_0227_;
assign _0229_ = ~((_0228_ & _0224_) | _0226_);
assign _0230_ = _0229_ | _0225_;
assign _0231_ = _0230_ | _0222_;
assign _0233_ = ~(_0231_ | _0217_);
assign _0234_ = ~((_0233_ | _0216_) & (_0211_ | _0206_));
assign _0235_ = ~(_0189_ ^ _0173_);
assign _0236_ = _0211_ & _0206_;
assign _0237_ = _0236_ | _0216_;
assign _0238_ = _0225_ & _0222_;
assign _0239_ = ~((_0238_ & _0229_) | _0217_);
assign _0240_ = ~((_0239_ & _0237_) | _0235_);
assign _0241_ = _0240_ & _0234_;
assign _0242_ = E ^ C;
assign _0244_ = _0242_ & H;
assign _0245_ = E ^ D;
assign _0246_ = C ? _0374_ : _0245_;
assign _0247_ = _0246_ ^ G;
assign _0248_ = _0247_ & _0244_;
assign _0249_ = ~G;
assign _0250_ = _0246_ | _0249_;
assign _0251_ = ~A;
assign _0252_ = ~(D & C);
assign _0253_ = ~((_0085_ & C) | (_0252_ & _0251_));
assign _0255_ = ~((_0374_ & _0375_) | _0104_);
assign _0256_ = _0255_ ^ _0253_;
assign _0257_ = _0256_ ^ _0514_;
assign _0258_ = _0257_ ^ _0250_;
assign _0259_ = _0258_ ^ _0248_;
assign _0260_ = _0259_ ^ I;
assign _0261_ = _0242_ ^ H;
assign _0262_ = _0261_ & K;
assign _0263_ = _0262_ & _0247_;
assign _0264_ = ~(_0263_ | _0100_);
assign _0266_ = ~(_0264_ ^ _0260_);
assign _0267_ = _0261_ ^ K;
assign _0268_ = _0267_ & L;
assign _0269_ = ~(_0262_ | _0244_);
assign _0270_ = ~(_0269_ ^ _0247_);
assign _0271_ = ~(_0270_ & _0268_);
assign _0272_ = _0271_ & L;
assign _0273_ = ~(_0272_ ^ _0266_);
assign _0274_ = ~_0273_;
assign _0275_ = _0270_ ^ _0268_;
assign _0277_ = _0275_ ^ _0331_;
assign _0278_ = ~((_0277_ & _0274_) | _0265_);
assign _0279_ = ~((_0266_ | _0077_) & _0271_);
assign _0280_ = ~((_0260_ & K) | _0263_);
assign _0281_ = ~_0246_;
assign _0282_ = ~((_0257_ & _0281_) | _0249_);
assign _0283_ = ~(_0256_ | _0514_);
assign _0284_ = ~(_0255_ & _0253_);
assign _0285_ = ~(D & A);
assign _0286_ = _0285_ & C;
assign _0287_ = ~(_0286_ ^ _0144_);
assign _0288_ = _0287_ ^ _0104_;
assign _0289_ = _0288_ ^ _0284_;
assign _0290_ = ~(_0289_ ^ _0283_);
assign _0291_ = _0290_ ^ _0282_;
assign _0292_ = _0258_ & _0248_;
assign _0293_ = ~((_0259_ & I) | _0292_);
assign _0294_ = _0293_ ^ _0291_;
assign _0295_ = _0294_ ^ _0280_;
assign _0296_ = _0295_ ^ L;
assign _0299_ = _0296_ ^ _0279_;
assign _0300_ = ~(_0299_ ^ M);
assign _0301_ = ~(_0275_ | _0331_);
assign _0302_ = _0301_ & _0274_;
assign _0303_ = ~(_0302_ ^ _0300_);
assign _0304_ = ~(_0303_ ^ _0278_);
assign _0305_ = ~((_0277_ & O) | _0301_);
assign _0306_ = _0305_ ^ _0273_;
assign _0307_ = ~((_0306_ & _0304_) | _0218_);
assign _0308_ = _0299_ & M;
assign _0310_ = _0295_ & L;
assign _0311_ = _0310_ | _0279_;
assign _0312_ = _0294_ | _0280_;
assign _0313_ = _0289_ & _0283_;
assign _0314_ = _0287_ | _0104_;
assign _0315_ = _0287_ & _0104_;
assign _0316_ = ~((_0315_ | _0284_) & _0314_);
assign _0317_ = ~((_0375_ & _0251_) | B);
assign _0318_ = C & A;
assign _0319_ = _0318_ | D;
assign _0321_ = _0317_ ? _0374_ : _0319_;
assign _0322_ = _0321_ ^ E;
assign _0323_ = _0322_ ^ _0316_;
assign _0324_ = _0323_ ^ _0313_;
assign _0325_ = _0290_ & _0282_;
assign _0326_ = ~((_0291_ & _0292_) | _0325_);
assign _0327_ = _0326_ ^ _0324_;
assign _0328_ = ~(_0291_ & _0259_);
assign _0329_ = _0328_ & I;
assign _0330_ = _0329_ ^ _0327_;
assign _0332_ = _0330_ ^ _0312_;
assign _0333_ = _0332_ ^ _0311_;
assign _0334_ = _0333_ ^ _0308_;
assign _0335_ = ~(_0275_ | _0273_);
assign _0336_ = ~((_0335_ & _0300_) | _0331_);
assign _0337_ = _0336_ ^ _0334_;
assign _0338_ = _0303_ & _0278_;
assign _0339_ = ~(_0338_ | _0265_);
assign _0340_ = _0339_ ^ _0337_;
assign _0341_ = _0340_ ^ _0307_;
assign _0343_ = _0306_ ^ P;
assign _0344_ = _0267_ ^ L;
assign _0345_ = ~_0344_;
assign _0346_ = _0277_ ^ O;
assign _0347_ = _0346_ & _0345_;
assign _0348_ = _0347_ | _0058_;
assign _0349_ = _0343_ ? _0348_ : _0058_;
assign _0350_ = _0306_ & P;
assign _0351_ = _0350_ ^ _0304_;
assign _0352_ = ~(_0351_ | _0349_);
assign _0354_ = ~((_0341_ & Q) | _0352_);
assign _0355_ = _0340_ & _0307_;
assign _0356_ = ~((_0337_ & O) | _0338_);
assign _0357_ = _0291_ & _0292_;
assign _0358_ = _0324_ & _0325_;
assign _0359_ = ~(_0256_ & F);
assign _0360_ = ~((_0289_ | _0514_) & (_0288_ | _0359_));
assign _0361_ = ~((_0323_ & F) | _0360_);
assign _0362_ = _0322_ & _0316_;
assign _0363_ = ~(_0321_ & E);
assign _0364_ = ~((B | D) & (C | A));
assign _0365_ = _0318_ ? D : _0364_;
assign _0366_ = ~(_0365_ & _0363_);
assign _0367_ = ~((_0366_ | _0362_) & _0284_);
assign _0368_ = _0367_ ^ _0361_;
assign _0369_ = ~(_0368_ ^ _0358_);
assign _0370_ = ~((_0357_ & _0324_) | _0369_);
assign _0371_ = ~((_0328_ & _0327_) | _0353_);
assign _0372_ = ~(_0371_ ^ _0370_);
assign _0373_ = _0330_ | _0312_;
assign _0376_ = ~(_0332_ & _0311_);
assign _0377_ = _0376_ & _0373_;
assign _0378_ = _0377_ ^ _0372_;
assign _0379_ = _0333_ & _0308_;
assign _0380_ = _0336_ & _0334_;
assign _0381_ = _0380_ | _0379_;
assign _0382_ = ~(_0381_ ^ _0378_);
assign _0383_ = _0382_ ^ _0356_;
assign _0384_ = ~(_0383_ ^ _0355_);
assign _0385_ = ~(_0384_ | _0354_);
assign _0387_ = ~(_0383_ & _0355_);
assign _0388_ = ~((_0382_ | _0356_) & _0387_);
assign _0389_ = ~(_0372_ | _0376_);
assign _0390_ = ~(_0372_ | _0373_);
assign _0391_ = ~(_0371_ & _0370_);
assign _0392_ = ~(_0357_ & _0324_);
assign _0393_ = ~(_0367_ | _0361_);
assign _0394_ = _0285_ | _0375_;
assign _0395_ = _0284_ & _0394_;
assign _0396_ = ~(_0395_ ^ _0393_);
assign _0398_ = ~((_0368_ & _0358_) | _0396_);
assign _0399_ = _0398_ & _0392_;
assign _0400_ = _0399_ ^ _0391_;
assign _0401_ = _0400_ ^ _0390_;
assign _0402_ = ~(_0401_ ^ _0389_);
assign _0403_ = ~(_0381_ & _0378_);
assign _0404_ = _0403_ ^ _0402_;
assign _0405_ = _0404_ ^ _0388_;
assign _0406_ = ~(_0405_ & _0385_);
assign _0407_ = _0037_ & _0038_;
assign _0409_ = ~(_0034_ & _0028_);
assign _0410_ = _0032_ & _0030_;
assign _0411_ = ~((_0033_ & _0029_) | _0410_);
assign _0412_ = _0411_ & _0409_;
assign _0413_ = _0035_ & _0026_;
assign _0414_ = ~((_0036_ & _0025_) | _0413_);
assign _0415_ = _0414_ ^ _0412_;
assign _0416_ = ~(_0415_ ^ _0407_);
assign _0417_ = _0009_ & _0509_;
assign _0418_ = ~((_0040_ & _0024_) | (_0037_ & _0417_));
assign _0420_ = ~(_0418_ | _0416_);
assign _0421_ = ~(_0043_ | _0041_);
assign _0422_ = _0418_ ^ _0416_;
assign _0423_ = ~(_0422_ & _0421_);
assign _0424_ = _0422_ | _0421_;
assign _0425_ = ~((_0424_ & _0423_) | _0420_);
assign _0426_ = ~(_0044_ & _0023_);
assign _0427_ = _0403_ | _0402_;
assign _0428_ = ~_0394_;
assign _0429_ = ~(_0399_ | _0391_);
assign _0431_ = ~((_0393_ & _0428_) | _0429_);
assign _0432_ = ~(_0400_ & _0390_);
assign _0433_ = ~(_0414_ | _0412_);
assign _0434_ = ~((_0415_ & _0407_) | _0433_);
assign _0435_ = ~(_0434_ & _0432_);
assign _0436_ = ~((_0401_ & _0389_) | _0435_);
assign _0437_ = _0436_ & _0431_;
assign _0438_ = _0437_ & _0423_;
assign _0439_ = _0438_ & _0427_;
assign _0440_ = ~(_0439_ & _0426_);
assign _0442_ = ~((_0404_ & _0388_) | _0440_);
assign _0443_ = ~(_0442_ & _0425_);
assign _0444_ = ~((_0045_ & _0020_) | _0443_);
assign _0445_ = _0444_ & _0406_;
assign _0446_ = ~((_0241_ | _0194_) & _0445_);
assign _0447_ = ~((_0076_ & _0047_) | _0446_);
assign _0448_ = ~(_0344_ | _0058_);
assign _0449_ = ~(_0448_ & _0346_);
assign _0450_ = _0449_ ^ _0343_;
assign _0451_ = _0351_ ^ _0349_;
assign _0453_ = _0448_ ^ _0346_;
assign _0454_ = ~(_0453_ | _0226_);
assign _0455_ = ~((_0454_ & _0450_) | (_0451_ & R));
assign _0456_ = _0341_ ^ Q;
assign _0457_ = _0456_ ^ _0352_;
assign _0458_ = _0457_ ? _0226_ : _0455_;
assign _0459_ = _0453_ & _0226_;
assign _0460_ = _0344_ ^ _0058_;
assign _0461_ = ~((_0459_ | _0454_) & _0460_);
assign _0462_ = ~((_0454_ | _0450_) & _0461_);
assign _0464_ = _0384_ & _0354_;
assign _0465_ = ~((_0451_ & _0456_) | R);
assign _0466_ = _0465_ | _0464_;
assign _0467_ = ~((_0462_ & _0458_) | _0466_);
assign _0468_ = _0405_ | _0385_;
assign _0469_ = ~((_0468_ | _0467_) & _0406_);
assign _0470_ = ~((_0060_ | _0017_) & _0046_);
assign _0471_ = _0470_ & _0469_;
assign valid = _0471_ & _0447_;
endmodule | module var18_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, valid); |
wire _0000_;
wire _0001_;
wire _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
(* src = "var18_multi.v:3" *)
input A;
(* src = "var18_multi.v:3" *)
input B;
(* src = "var18_multi.v:3" *)
input C;
(* src = "var18_multi.v:3" *)
input D;
(* src = "var18_multi.v:3" *)
input E;
(* src = "var18_multi.v:3" *)
input F;
(* src = "var18_multi.v:3" *)
input G;
(* src = "var18_multi.v:3" *)
input H;
(* src = "var18_multi.v:3" *)
input I;
(* src = "var18_multi.v:3" *)
input J;
(* src = "var18_multi.v:3" *)
input K;
(* src = "var18_multi.v:3" *)
input L;
(* src = "var18_multi.v:3" *)
input M;
(* src = "var18_multi.v:3" *)
input N;
(* src = "var18_multi.v:3" *)
input O;
(* src = "var18_multi.v:3" *)
input P;
(* src = "var18_multi.v:3" *)
input Q;
(* src = "var18_multi.v:3" *)
input R;
(* src = "var18_multi.v:4" *)
output valid;
assign _0100_ = ~K;
assign _0111_ = ~J;
assign _0122_ = ~(B | A);
assign _0133_ = B & A;
assign _0144_ = ~(_0133_ | _0122_);
assign _0155_ = _0144_ ^ _0111_;
assign _0166_ = _0155_ ^ _0100_;
assign _0177_ = _0166_ & M;
assign _0188_ = ~(_0155_ | _0100_);
assign _0199_ = B | A;
assign _0210_ = ~(B & A);
assign _0221_ = J ? _0210_ : _0199_;
assign _0232_ = _0221_ ^ _0188_;
assign _0243_ = _0232_ ^ L;
assign _0254_ = _0243_ ^ _0177_;
assign _0265_ = ~O;
assign _0276_ = _0166_ ^ M;
assign _0297_ = ~(_0276_ | _0265_);
assign _0298_ = _0297_ ^ _0254_;
assign _0309_ = _0298_ & P;
assign _0320_ = ~((_0276_ | _0254_) & O);
assign _0331_ = ~N;
assign _0342_ = _0243_ & _0177_;
assign _0353_ = ~I;
assign _0374_ = ~D;
assign _0375_ = ~C;
assign _0386_ = _0133_ ^ _0375_;
assign _0397_ = _0386_ ^ _0374_;
assign _0408_ = _0397_ ^ G;
assign _0419_ = _0408_ ^ H;
assign _0430_ = _0419_ ^ _0353_;
assign _0441_ = _0122_ & J;
assign _0452_ = ~(_0441_ ^ _0430_);
assign _0463_ = _0452_ ^ K;
assign _0472_ = _0221_ & _0188_;
assign _0473_ = _0232_ & L;
assign _0474_ = _0473_ | _0472_;
assign _0475_ = _0474_ ^ _0463_;
assign _0476_ = _0475_ ^ _0342_;
assign _0477_ = _0476_ ^ _0331_;
assign _0478_ = _0477_ ^ _0320_;
assign _0479_ = _0478_ & _0309_;
assign _0480_ = _0477_ | _0320_;
assign _0481_ = _0476_ | _0331_;
assign _0482_ = ~(_0475_ & _0342_);
assign _0483_ = _0463_ & _0473_;
assign _0484_ = ~((_0452_ & K) | _0472_);
assign _0485_ = ~(_0441_ & _0430_);
assign _0486_ = ~(_0419_ | _0353_);
assign _0487_ = _0386_ | _0374_;
assign _0488_ = D & C;
assign _0489_ = _0488_ & _0144_;
assign _0490_ = ~((_0210_ | C) & _0199_);
assign _0491_ = ~((_0490_ & _0487_) | _0489_);
assign _0492_ = _0491_ ^ F;
assign _0493_ = _0397_ & G;
assign _0494_ = ~((_0408_ & H) | _0493_);
assign _0495_ = ~(_0494_ ^ _0492_);
assign _0496_ = _0495_ ^ _0486_;
assign _0497_ = _0496_ ^ _0485_;
assign _0498_ = _0497_ ^ _0484_;
assign _0499_ = _0498_ ^ _0483_;
assign _0500_ = ~(_0499_ ^ M);
assign _0501_ = _0500_ ^ _0482_;
assign _0502_ = _0501_ ^ _0481_;
assign _0503_ = _0502_ ^ _0480_;
assign _0504_ = _0503_ & _0479_;
assign _0505_ = ~(_0502_ | _0480_);
assign _0506_ = ~(_0501_ | _0481_);
assign _0507_ = ~(_0499_ & M);
assign _0508_ = ~((_0500_ | _0482_) & _0507_);
assign _0509_ = _0498_ & _0483_;
assign _0510_ = ~(_0497_ | _0484_);
assign _0511_ = _0495_ | _0419_;
assign _0512_ = _0511_ & I;
assign _0513_ = ~(_0492_ & _0493_);
assign _0514_ = ~F;
assign _0515_ = _0491_ | _0514_;
assign _0516_ = ~(_0489_ | _0122_);
assign _0517_ = _0516_ ^ _0515_;
assign _0000_ = ~(_0517_ ^ _0513_);
assign _0001_ = _0408_ & H;
assign _0002_ = ~(_0492_ & _0001_);
assign _0003_ = ~(_0002_ & H);
assign _0004_ = _0003_ ^ _0000_;
assign _0005_ = _0004_ ^ _0512_;
assign _0006_ = ~(_0495_ | _0199_);
assign _0007_ = ~((_0006_ & _0430_) | _0111_);
assign _0008_ = _0007_ ^ _0005_;
assign _0009_ = _0008_ ^ _0510_;
assign _0010_ = _0009_ ^ _0509_;
assign _0011_ = _0010_ ^ _0508_;
assign _0012_ = _0011_ ^ _0506_;
assign _0013_ = _0012_ ^ O;
assign _0014_ = _0013_ ^ _0505_;
assign _0015_ = _0014_ ^ P;
assign _0016_ = _0015_ ^ _0504_;
assign _0017_ = _0016_ & Q;
assign _0018_ = ~(_0014_ & P);
assign _0019_ = ~(_0015_ & _0504_);
assign _0020_ = ~(_0019_ & _0018_);
assign _0021_ = ~(_0012_ & O);
assign _0022_ = ~(_0013_ & _0505_);
assign _0023_ = ~(_0022_ & _0021_);
assign _0024_ = _0010_ & _0508_;
assign _0025_ = _0007_ & _0005_;
assign _0026_ = _0004_ & _0512_;
assign _0027_ = ~H;
assign _0028_ = ~((_0000_ | _0027_) & _0002_);
assign _0029_ = ~(_0517_ | _0513_);
assign _0030_ = _0489_ | _0133_;
assign _0031_ = _0516_ | _0491_;
assign _0032_ = _0031_ & F;
assign _0033_ = _0032_ ^ _0030_;
assign _0034_ = _0033_ ^ _0029_;
assign _0035_ = _0034_ ^ _0028_;
assign _0036_ = _0035_ ^ _0026_;
assign _0037_ = _0036_ ^ _0025_;
assign _0038_ = _0008_ & _0510_;
assign _0039_ = ~((_0009_ & _0509_) | _0038_);
assign _0040_ = ~(_0039_ ^ _0037_);
assign _0041_ = ~(_0040_ ^ _0024_);
assign _0042_ = _0501_ | _0476_;
assign _0043_ = ~((_0011_ | _0042_) & N);
assign _0044_ = _0043_ ^ _0041_;
assign _0045_ = _0044_ ^ _0023_;
assign _0046_ = _0045_ ^ _0020_;
assign _0047_ = _0046_ | _0017_;
assign _0048_ = _0503_ ^ _0479_;
assign _0049_ = ~(_0048_ & Q);
assign _0050_ = ~_0503_;
assign _0051_ = _0478_ ^ _0309_;
assign _0052_ = _0051_ & Q;
assign _0053_ = _0298_ ^ P;
assign _0054_ = ~(_0053_ & Q);
assign _0055_ = ~(_0054_ | _0478_);
assign _0056_ = ~((_0055_ & _0050_) | _0052_);
assign _0057_ = _0056_ & _0049_;
assign _0058_ = ~Q;
assign _0059_ = _0016_ ^ _0058_;
assign _0060_ = ~(_0059_ | _0057_);
assign _0061_ = _0276_ ^ _0265_;
assign _0062_ = _0053_ ^ _0058_;
assign _0063_ = _0062_ & _0061_;
assign _0064_ = _0055_ | _0052_;
assign _0065_ = _0048_ ^ Q;
assign _0066_ = ~(_0065_ ^ _0064_);
assign _0067_ = ~_0066_;
assign _0068_ = ~(_0053_ | _0058_);
assign _0069_ = ~(_0068_ ^ _0051_);
assign _0070_ = ~(_0069_ | _0063_);
assign _0071_ = ~((_0070_ & _0067_) | R);
assign _0072_ = _0069_ & _0066_;
assign _0073_ = ~((_0072_ & _0063_) | _0071_);
assign _0074_ = ~(_0059_ & _0057_);
assign _0075_ = ~(_0074_ & _0073_);
assign _0076_ = ~(_0075_ | _0060_);
assign _0077_ = ~L;
assign _0078_ = G ^ E;
assign _0079_ = _0078_ ^ _0027_;
assign _0080_ = _0079_ ^ I;
assign _0081_ = _0080_ ^ J;
assign _0082_ = _0081_ & K;
assign _0083_ = _0079_ & I;
assign _0084_ = ~(G & E);
assign _0085_ = D & A;
assign _0086_ = ~(D | A);
assign _0087_ = ~(_0086_ | _0085_);
assign _0088_ = _0087_ ^ _0514_;
assign _0089_ = _0088_ ^ _0084_;
assign _0090_ = ~(_0078_ | _0027_);
assign _0091_ = ~(_0088_ ^ _0084_);
assign _0092_ = ~(_0091_ & _0090_);
assign _0093_ = _0091_ | _0090_;
assign _0094_ = _0093_ & _0092_;
assign _0095_ = _0083_ ? _0089_ : _0094_;
assign _0096_ = _0095_ & _0082_;
assign _0097_ = ~(_0080_ & J);
assign _0098_ = ~_0094_;
assign _0099_ = _0098_ | _0097_;
assign _0101_ = ~((_0091_ & _0079_) | _0353_);
assign _0102_ = ~(_0088_ | _0084_);
assign _0103_ = _0087_ | _0514_;
assign _0104_ = ~E;
assign _0105_ = _0085_ ^ B;
assign _0106_ = _0105_ ^ _0104_;
assign _0107_ = _0106_ ^ _0103_;
assign _0108_ = _0107_ ^ _0102_;
assign _0109_ = ~(_0108_ ^ _0092_);
assign _0110_ = _0109_ ^ _0101_;
assign _0112_ = _0110_ ^ _0099_;
assign _0113_ = _0112_ ^ _0096_;
assign _0114_ = _0113_ | _0077_;
assign _0115_ = _0112_ & _0096_;
assign _0116_ = _0109_ & _0101_;
assign _0117_ = _0107_ & _0102_;
assign _0118_ = ~(_0105_ & E);
assign _0119_ = E & D;
assign _0120_ = _0119_ & _0144_;
assign _0121_ = _0133_ | _0374_;
assign _0123_ = ~((_0121_ & _0118_) | _0120_);
assign _0124_ = ~_0087_;
assign _0125_ = ~((_0106_ & _0124_) | _0514_);
assign _0126_ = _0125_ ^ _0123_;
assign _0127_ = _0126_ ^ G;
assign _0128_ = _0127_ ^ _0117_;
assign _0129_ = ~(_0108_ | _0078_);
assign _0130_ = ~((_0129_ & _0091_) | _0027_);
assign _0131_ = _0130_ ^ _0128_;
assign _0132_ = _0131_ ^ _0116_;
assign _0134_ = ~(_0094_ & _0080_);
assign _0135_ = _0110_ | _0134_;
assign _0136_ = _0135_ & J;
assign _0137_ = ~(_0136_ ^ _0132_);
assign _0138_ = _0137_ ^ _0115_;
assign _0139_ = _0138_ ^ _0114_;
assign _0140_ = _0139_ ^ M;
assign _0141_ = _0140_ & N;
assign _0142_ = _0097_ ? _0095_ : _0098_;
assign _0143_ = ~(_0142_ ^ _0082_);
assign _0145_ = _0081_ ^ K;
assign _0146_ = ~(_0145_ | _0331_);
assign _0147_ = _0146_ & _0143_;
assign _0148_ = _0113_ ^ _0077_;
assign _0149_ = _0148_ & _0147_;
assign _0150_ = _0140_ ^ N;
assign _0151_ = ~((_0150_ & _0149_) | _0141_);
assign _0152_ = _0136_ & _0132_;
assign _0153_ = _0126_ & G;
assign _0154_ = ~((_0127_ & _0117_) | _0153_);
assign _0156_ = _0133_ & D;
assign _0157_ = _0120_ | _0156_;
assign _0158_ = ~((_0125_ & _0123_) | _0157_);
assign _0159_ = _0158_ ^ _0154_;
assign _0160_ = _0130_ & _0128_;
assign _0161_ = ~((_0131_ & _0116_) | _0160_);
assign _0162_ = _0161_ ^ _0159_;
assign _0163_ = ~(_0162_ ^ _0152_);
assign _0164_ = _0095_ & _0081_;
assign _0165_ = _0164_ & _0112_;
assign _0167_ = ~((_0165_ & _0137_) | _0100_);
assign _0168_ = _0167_ ^ _0163_;
assign _0169_ = _0138_ | _0114_;
assign _0170_ = ~(_0139_ & M);
assign _0171_ = _0170_ & _0169_;
assign _0172_ = _0171_ ^ _0168_;
assign _0173_ = ~(_0172_ | _0151_);
assign _0174_ = ~_0170_;
assign _0175_ = _0168_ & _0174_;
assign _0176_ = ~_0169_;
assign _0178_ = _0168_ & _0176_;
assign _0179_ = ~(_0167_ & _0163_);
assign _0180_ = _0158_ | _0154_;
assign _0181_ = ~_0159_;
assign _0182_ = _0161_ | _0181_;
assign _0183_ = _0182_ & _0180_;
assign _0184_ = ~_0152_;
assign _0185_ = ~((_0162_ | _0184_) & _0179_);
assign _0186_ = _0183_ ? _0185_ : _0179_;
assign _0187_ = _0186_ ^ _0178_;
assign _0189_ = _0187_ ^ _0175_;
assign _0190_ = ~(_0189_ & _0173_);
assign _0191_ = ~(_0186_ & _0178_);
assign _0192_ = ~((_0183_ | _0179_) & _0191_);
assign _0193_ = ~((_0187_ & _0175_) | _0192_);
assign _0194_ = ~(_0193_ & _0190_);
assign _0195_ = _0145_ ^ _0331_;
assign _0196_ = _0195_ & O;
assign _0197_ = _0196_ & _0143_;
assign _0198_ = _0148_ ^ _0147_;
assign _0200_ = _0198_ ^ _0197_;
assign _0201_ = ~(_0196_ | _0146_);
assign _0202_ = _0201_ ^ _0143_;
assign _0203_ = _0195_ ^ O;
assign _0204_ = ~_0203_;
assign _0205_ = ~(_0204_ & _0202_);
assign _0206_ = ~((_0205_ | _0200_) & P);
assign _0207_ = _0198_ & _0197_;
assign _0208_ = _0150_ ^ _0149_;
assign _0209_ = _0208_ ^ O;
assign _0211_ = ~(_0209_ ^ _0207_);
assign _0212_ = _0208_ & O;
assign _0213_ = _0209_ & _0207_;
assign _0214_ = _0213_ | _0212_;
assign _0215_ = _0172_ ^ _0151_;
assign _0216_ = ~(_0215_ | _0214_);
assign _0217_ = _0215_ & _0214_;
assign _0218_ = ~P;
assign _0219_ = ~(_0203_ | _0218_);
assign _0220_ = _0219_ & _0202_;
assign _0222_ = _0220_ ^ _0200_;
assign _0223_ = _0203_ ^ _0218_;
assign _0224_ = _0223_ & _0202_;
assign _0225_ = ~((_0224_ & _0111_) | _0058_);
assign _0226_ = ~R;
assign _0227_ = Q ^ J;
assign _0228_ = ~_0227_;
assign _0229_ = ~((_0228_ & _0224_) | _0226_);
assign _0230_ = _0229_ | _0225_;
assign _0231_ = _0230_ | _0222_;
assign _0233_ = ~(_0231_ | _0217_);
assign _0234_ = ~((_0233_ | _0216_) & (_0211_ | _0206_));
assign _0235_ = ~(_0189_ ^ _0173_);
assign _0236_ = _0211_ & _0206_;
assign _0237_ = _0236_ | _0216_;
assign _0238_ = _0225_ & _0222_;
assign _0239_ = ~((_0238_ & _0229_) | _0217_);
assign _0240_ = ~((_0239_ & _0237_) | _0235_);
assign _0241_ = _0240_ & _0234_;
assign _0242_ = E ^ C;
assign _0244_ = _0242_ & H;
assign _0245_ = E ^ D;
assign _0246_ = C ? _0374_ : _0245_;
assign _0247_ = _0246_ ^ G;
assign _0248_ = _0247_ & _0244_;
assign _0249_ = ~G;
assign _0250_ = _0246_ | _0249_;
assign _0251_ = ~A;
assign _0252_ = ~(D & C);
assign _0253_ = ~((_0085_ & C) | (_0252_ & _0251_));
assign _0255_ = ~((_0374_ & _0375_) | _0104_);
assign _0256_ = _0255_ ^ _0253_;
assign _0257_ = _0256_ ^ _0514_;
assign _0258_ = _0257_ ^ _0250_;
assign _0259_ = _0258_ ^ _0248_;
assign _0260_ = _0259_ ^ I;
assign _0261_ = _0242_ ^ H;
assign _0262_ = _0261_ & K;
assign _0263_ = _0262_ & _0247_;
assign _0264_ = ~(_0263_ | _0100_);
assign _0266_ = ~(_0264_ ^ _0260_);
assign _0267_ = _0261_ ^ K;
assign _0268_ = _0267_ & L;
assign _0269_ = ~(_0262_ | _0244_);
assign _0270_ = ~(_0269_ ^ _0247_);
assign _0271_ = ~(_0270_ & _0268_);
assign _0272_ = _0271_ & L;
assign _0273_ = ~(_0272_ ^ _0266_);
assign _0274_ = ~_0273_;
assign _0275_ = _0270_ ^ _0268_;
assign _0277_ = _0275_ ^ _0331_;
assign _0278_ = ~((_0277_ & _0274_) | _0265_);
assign _0279_ = ~((_0266_ | _0077_) & _0271_);
assign _0280_ = ~((_0260_ & K) | _0263_);
assign _0281_ = ~_0246_;
assign _0282_ = ~((_0257_ & _0281_) | _0249_);
assign _0283_ = ~(_0256_ | _0514_);
assign _0284_ = ~(_0255_ & _0253_);
assign _0285_ = ~(D & A);
assign _0286_ = _0285_ & C;
assign _0287_ = ~(_0286_ ^ _0144_);
assign _0288_ = _0287_ ^ _0104_;
assign _0289_ = _0288_ ^ _0284_;
assign _0290_ = ~(_0289_ ^ _0283_);
assign _0291_ = _0290_ ^ _0282_;
assign _0292_ = _0258_ & _0248_;
assign _0293_ = ~((_0259_ & I) | _0292_);
assign _0294_ = _0293_ ^ _0291_;
assign _0295_ = _0294_ ^ _0280_;
assign _0296_ = _0295_ ^ L;
assign _0299_ = _0296_ ^ _0279_;
assign _0300_ = ~(_0299_ ^ M);
assign _0301_ = ~(_0275_ | _0331_);
assign _0302_ = _0301_ & _0274_;
assign _0303_ = ~(_0302_ ^ _0300_);
assign _0304_ = ~(_0303_ ^ _0278_);
assign _0305_ = ~((_0277_ & O) | _0301_);
assign _0306_ = _0305_ ^ _0273_;
assign _0307_ = ~((_0306_ & _0304_) | _0218_);
assign _0308_ = _0299_ & M;
assign _0310_ = _0295_ & L;
assign _0311_ = _0310_ | _0279_;
assign _0312_ = _0294_ | _0280_;
assign _0313_ = _0289_ & _0283_;
assign _0314_ = _0287_ | _0104_;
assign _0315_ = _0287_ & _0104_;
assign _0316_ = ~((_0315_ | _0284_) & _0314_);
assign _0317_ = ~((_0375_ & _0251_) | B);
assign _0318_ = C & A;
assign _0319_ = _0318_ | D;
assign _0321_ = _0317_ ? _0374_ : _0319_;
assign _0322_ = _0321_ ^ E;
assign _0323_ = _0322_ ^ _0316_;
assign _0324_ = _0323_ ^ _0313_;
assign _0325_ = _0290_ & _0282_;
assign _0326_ = ~((_0291_ & _0292_) | _0325_);
assign _0327_ = _0326_ ^ _0324_;
assign _0328_ = ~(_0291_ & _0259_);
assign _0329_ = _0328_ & I;
assign _0330_ = _0329_ ^ _0327_;
assign _0332_ = _0330_ ^ _0312_;
assign _0333_ = _0332_ ^ _0311_;
assign _0334_ = _0333_ ^ _0308_;
assign _0335_ = ~(_0275_ | _0273_);
assign _0336_ = ~((_0335_ & _0300_) | _0331_);
assign _0337_ = _0336_ ^ _0334_;
assign _0338_ = _0303_ & _0278_;
assign _0339_ = ~(_0338_ | _0265_);
assign _0340_ = _0339_ ^ _0337_;
assign _0341_ = _0340_ ^ _0307_;
assign _0343_ = _0306_ ^ P;
assign _0344_ = _0267_ ^ L;
assign _0345_ = ~_0344_;
assign _0346_ = _0277_ ^ O;
assign _0347_ = _0346_ & _0345_;
assign _0348_ = _0347_ | _0058_;
assign _0349_ = _0343_ ? _0348_ : _0058_;
assign _0350_ = _0306_ & P;
assign _0351_ = _0350_ ^ _0304_;
assign _0352_ = ~(_0351_ | _0349_);
assign _0354_ = ~((_0341_ & Q) | _0352_);
assign _0355_ = _0340_ & _0307_;
assign _0356_ = ~((_0337_ & O) | _0338_);
assign _0357_ = _0291_ & _0292_;
assign _0358_ = _0324_ & _0325_;
assign _0359_ = ~(_0256_ & F);
assign _0360_ = ~((_0289_ | _0514_) & (_0288_ | _0359_));
assign _0361_ = ~((_0323_ & F) | _0360_);
assign _0362_ = _0322_ & _0316_;
assign _0363_ = ~(_0321_ & E);
assign _0364_ = ~((B | D) & (C | A));
assign _0365_ = _0318_ ? D : _0364_;
assign _0366_ = ~(_0365_ & _0363_);
assign _0367_ = ~((_0366_ | _0362_) & _0284_);
assign _0368_ = _0367_ ^ _0361_;
assign _0369_ = ~(_0368_ ^ _0358_);
assign _0370_ = ~((_0357_ & _0324_) | _0369_);
assign _0371_ = ~((_0328_ & _0327_) | _0353_);
assign _0372_ = ~(_0371_ ^ _0370_);
assign _0373_ = _0330_ | _0312_;
assign _0376_ = ~(_0332_ & _0311_);
assign _0377_ = _0376_ & _0373_;
assign _0378_ = _0377_ ^ _0372_;
assign _0379_ = _0333_ & _0308_;
assign _0380_ = _0336_ & _0334_;
assign _0381_ = _0380_ | _0379_;
assign _0382_ = ~(_0381_ ^ _0378_);
assign _0383_ = _0382_ ^ _0356_;
assign _0384_ = ~(_0383_ ^ _0355_);
assign _0385_ = ~(_0384_ | _0354_);
assign _0387_ = ~(_0383_ & _0355_);
assign _0388_ = ~((_0382_ | _0356_) & _0387_);
assign _0389_ = ~(_0372_ | _0376_);
assign _0390_ = ~(_0372_ | _0373_);
assign _0391_ = ~(_0371_ & _0370_);
assign _0392_ = ~(_0357_ & _0324_);
assign _0393_ = ~(_0367_ | _0361_);
assign _0394_ = _0285_ | _0375_;
assign _0395_ = _0284_ & _0394_;
assign _0396_ = ~(_0395_ ^ _0393_);
assign _0398_ = ~((_0368_ & _0358_) | _0396_);
assign _0399_ = _0398_ & _0392_;
assign _0400_ = _0399_ ^ _0391_;
assign _0401_ = _0400_ ^ _0390_;
assign _0402_ = ~(_0401_ ^ _0389_);
assign _0403_ = ~(_0381_ & _0378_);
assign _0404_ = _0403_ ^ _0402_;
assign _0405_ = _0404_ ^ _0388_;
assign _0406_ = ~(_0405_ & _0385_);
assign _0407_ = _0037_ & _0038_;
assign _0409_ = ~(_0034_ & _0028_);
assign _0410_ = _0032_ & _0030_;
assign _0411_ = ~((_0033_ & _0029_) | _0410_);
assign _0412_ = _0411_ & _0409_;
assign _0413_ = _0035_ & _0026_;
assign _0414_ = ~((_0036_ & _0025_) | _0413_);
assign _0415_ = _0414_ ^ _0412_;
assign _0416_ = ~(_0415_ ^ _0407_);
assign _0417_ = _0009_ & _0509_;
assign _0418_ = ~((_0040_ & _0024_) | (_0037_ & _0417_));
assign _0420_ = ~(_0418_ | _0416_);
assign _0421_ = ~(_0043_ | _0041_);
assign _0422_ = _0418_ ^ _0416_;
assign _0423_ = ~(_0422_ & _0421_);
assign _0424_ = _0422_ | _0421_;
assign _0425_ = ~((_0424_ & _0423_) | _0420_);
assign _0426_ = ~(_0044_ & _0023_);
assign _0427_ = _0403_ | _0402_;
assign _0428_ = ~_0394_;
assign _0429_ = ~(_0399_ | _0391_);
assign _0431_ = ~((_0393_ & _0428_) | _0429_);
assign _0432_ = ~(_0400_ & _0390_);
assign _0433_ = ~(_0414_ | _0412_);
assign _0434_ = ~((_0415_ & _0407_) | _0433_);
assign _0435_ = ~(_0434_ & _0432_);
assign _0436_ = ~((_0401_ & _0389_) | _0435_);
assign _0437_ = _0436_ & _0431_;
assign _0438_ = _0437_ & _0423_;
assign _0439_ = _0438_ & _0427_;
assign _0440_ = ~(_0439_ & _0426_);
assign _0442_ = ~((_0404_ & _0388_) | _0440_);
assign _0443_ = ~(_0442_ & _0425_);
assign _0444_ = ~((_0045_ & _0020_) | _0443_);
assign _0445_ = _0444_ & _0406_;
assign _0446_ = ~((_0241_ | _0194_) & _0445_);
assign _0447_ = ~((_0076_ & _0047_) | _0446_);
assign _0448_ = ~(_0344_ | _0058_);
assign _0449_ = ~(_0448_ & _0346_);
assign _0450_ = _0449_ ^ _0343_;
assign _0451_ = _0351_ ^ _0349_;
assign _0453_ = _0448_ ^ _0346_;
assign _0454_ = ~(_0453_ | _0226_);
assign _0455_ = ~((_0454_ & _0450_) | (_0451_ & R));
assign _0456_ = _0341_ ^ Q;
assign _0457_ = _0456_ ^ _0352_;
assign _0458_ = _0457_ ? _0226_ : _0455_;
assign _0459_ = _0453_ & _0226_;
assign _0460_ = _0344_ ^ _0058_;
assign _0461_ = ~((_0459_ | _0454_) & _0460_);
assign _0462_ = ~((_0454_ | _0450_) & _0461_);
assign _0464_ = _0384_ & _0354_;
assign _0465_ = ~((_0451_ & _0456_) | R);
assign _0466_ = _0465_ | _0464_;
assign _0467_ = ~((_0462_ & _0458_) | _0466_);
assign _0468_ = _0405_ | _0385_;
assign _0469_ = ~((_0468_ | _0467_) & _0406_);
assign _0470_ = ~((_0060_ | _0017_) & _0046_);
assign _0471_ = _0470_ & _0469_;
assign valid = _0471_ & _0447_;
endmodule | 5 |
138,109 | data/full_repos/permissive/81900704/output/vs/opt_var20_multi.v | 81,900,704 | opt_var20_multi.v | v | 1,358 | 115 | [] | [] | [] | [(5, 1357)] | null | data/verilator_xmls/4ce3caa1-dc92-4c02-9772-95caacefb55e.xml | null | 301,806 | module | module var20_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, valid);
wire _0000_;
wire _0001_;
wire _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
(* src = "var20_multi.v:3" *)
input A;
(* src = "var20_multi.v:3" *)
input B;
(* src = "var20_multi.v:3" *)
input C;
(* src = "var20_multi.v:3" *)
input D;
(* src = "var20_multi.v:3" *)
input E;
(* src = "var20_multi.v:3" *)
input F;
(* src = "var20_multi.v:3" *)
input G;
(* src = "var20_multi.v:3" *)
input H;
(* src = "var20_multi.v:3" *)
input I;
(* src = "var20_multi.v:3" *)
input J;
(* src = "var20_multi.v:3" *)
input K;
(* src = "var20_multi.v:3" *)
input L;
(* src = "var20_multi.v:3" *)
input M;
(* src = "var20_multi.v:3" *)
input N;
(* src = "var20_multi.v:3" *)
input O;
(* src = "var20_multi.v:3" *)
input P;
(* src = "var20_multi.v:3" *)
input Q;
(* src = "var20_multi.v:3" *)
input R;
(* src = "var20_multi.v:3" *)
input S;
(* src = "var20_multi.v:3" *)
input T;
(* src = "var20_multi.v:4" *)
output valid;
assign _0120_ = ~Q;
assign _0131_ = ~P;
assign _0142_ = ~N;
assign _0153_ = ~I;
assign _0164_ = G ^ E;
assign _0175_ = _0164_ ^ H;
assign _0186_ = _0175_ ^ _0153_;
assign _0197_ = _0186_ ^ J;
assign _0208_ = _0197_ ^ K;
assign _0219_ = _0208_ ^ _0142_;
assign _0230_ = _0219_ ^ O;
assign _0241_ = _0230_ ^ _0131_;
assign _0262_ = _0197_ & K;
assign _0263_ = ~(G & E);
assign _0274_ = ~F;
assign _0285_ = D ^ A;
assign _0296_ = _0285_ ^ _0274_;
assign _0307_ = ~(_0296_ ^ _0263_);
assign _0318_ = ~H;
assign _0339_ = ~(_0164_ | _0318_);
assign _0340_ = _0339_ ^ _0307_;
assign _0351_ = ~_0175_;
assign _0362_ = _0186_ & J;
assign _0373_ = ~((_0351_ & I) | _0362_);
assign _0394_ = ~(_0373_ ^ _0340_);
assign _0395_ = _0394_ ^ _0262_;
assign _0406_ = ~(_0208_ | _0142_);
assign _0417_ = _0219_ & O;
assign _0428_ = ~(_0417_ | _0406_);
assign _0439_ = _0428_ ^ _0395_;
assign _0450_ = ~(_0439_ | J);
assign _0461_ = ~((_0450_ & _0241_) | _0120_);
assign _0472_ = _0230_ | _0131_;
assign _0483_ = ~(_0439_ | _0472_);
assign _0494_ = ~_0395_;
assign _0505_ = _0494_ & _0417_;
assign _0516_ = _0494_ & _0406_;
assign _0527_ = ~L;
assign _0538_ = _0394_ & _0262_;
assign _0549_ = ~((_0307_ & _0351_) | _0153_);
assign _0560_ = _0339_ & _0307_;
assign _0571_ = ~(_0296_ | _0263_);
assign _0582_ = _0285_ | _0274_;
assign _0593_ = ~E;
assign _0604_ = D & A;
assign _0615_ = _0604_ ^ B;
assign _0622_ = _0615_ ^ _0593_;
assign _0623_ = _0622_ ^ _0582_;
assign _0624_ = _0623_ ^ _0571_;
assign _0625_ = _0624_ ^ _0560_;
assign _0626_ = ~(_0625_ ^ _0549_);
assign _0627_ = _0340_ & _0362_;
assign _0628_ = _0627_ ^ _0626_;
assign _0629_ = _0628_ ^ _0538_;
assign _0630_ = _0629_ ^ _0527_;
assign _0631_ = _0630_ ^ _0516_;
assign _0632_ = _0631_ ^ _0505_;
assign _0633_ = _0632_ ^ _0483_;
assign _0634_ = _0633_ ^ _0461_;
assign _0635_ = ~R;
assign _0636_ = ~J;
assign _0637_ = Q & _0636_;
assign _0638_ = _0120_ & J;
assign _0639_ = ~(_0638_ | _0637_);
assign _0640_ = _0639_ & _0241_;
assign _0641_ = _0439_ ^ _0472_;
assign _0642_ = ~((_0641_ & _0640_) | _0635_);
assign _0643_ = _0642_ & _0634_;
assign _0644_ = _0633_ & _0461_;
assign _0645_ = _0631_ & _0505_;
assign _0646_ = _0630_ & _0516_;
assign _0647_ = _0629_ | _0527_;
assign _0648_ = ~(_0628_ & _0538_);
assign _0649_ = _0340_ & _0186_;
assign _0650_ = ~((_0649_ & _0626_) | _0636_);
assign _0651_ = _0625_ & _0549_;
assign _0652_ = _0164_ & H;
assign _0653_ = ~(_0296_ & _0652_);
assign _0000_ = _0624_ ? _0318_ : _0653_;
assign _0001_ = ~((_0307_ | _0318_) & _0000_);
assign _0002_ = _0623_ & _0571_;
assign _0003_ = ~(_0615_ & E);
assign _0004_ = E & D;
assign _0005_ = ~(B ^ A);
assign _0006_ = ~_0005_;
assign _0007_ = _0006_ & _0004_;
assign _0008_ = ~D;
assign _0009_ = B & A;
assign _0010_ = _0009_ | _0008_;
assign _0011_ = ~((_0010_ & _0003_) | _0007_);
assign _0012_ = ~_0285_;
assign _0013_ = ~((_0622_ & _0012_) | _0274_);
assign _0014_ = _0013_ ^ _0011_;
assign _0015_ = _0014_ ^ G;
assign _0016_ = _0015_ ^ _0002_;
assign _0017_ = _0016_ ^ _0001_;
assign _0018_ = _0017_ ^ _0651_;
assign _0019_ = _0018_ ^ _0650_;
assign _0020_ = _0019_ ^ _0648_;
assign _0021_ = _0020_ ^ _0647_;
assign _0022_ = _0021_ ^ M;
assign _0023_ = _0022_ ^ N;
assign _0024_ = _0023_ ^ _0646_;
assign _0025_ = _0024_ ^ O;
assign _0026_ = _0025_ ^ _0645_;
assign _0027_ = ~_0632_;
assign _0028_ = ~(_0439_ | _0230_);
assign _0029_ = ~((_0028_ & _0027_) | _0131_);
assign _0030_ = _0029_ ^ _0026_;
assign _0031_ = _0030_ ^ _0644_;
assign _0032_ = _0031_ ^ _0643_;
assign _0033_ = ~(_0032_ & S);
assign _0034_ = _0640_ & R;
assign _0035_ = _0637_ & _0241_;
assign _0036_ = _0035_ ? _0439_ : _0641_;
assign _0037_ = ~(_0036_ ^ _0034_);
assign _0038_ = ~_0037_;
assign _0039_ = ~(_0637_ | R);
assign _0040_ = ~(_0039_ | _0638_);
assign _0041_ = ~(_0040_ ^ _0241_);
assign _0042_ = ~S;
assign _0043_ = _0639_ ^ R;
assign _0044_ = ~(_0043_ | _0042_);
assign _0045_ = _0044_ & _0041_;
assign _0046_ = _0045_ & _0038_;
assign _0047_ = ~_0046_;
assign _0048_ = _0642_ ^ _0634_;
assign _0049_ = _0048_ ^ _0042_;
assign _0050_ = _0049_ | _0047_;
assign _0051_ = ~((_0048_ | _0037_) & S);
assign _0052_ = _0051_ & _0050_;
assign _0053_ = _0032_ ^ _0042_;
assign _0054_ = _0053_ | _0052_;
assign _0055_ = _0054_ & _0033_;
assign _0056_ = ~(_0031_ & _0643_);
assign _0057_ = _0024_ & O;
assign _0058_ = _0025_ & _0645_;
assign _0059_ = _0058_ | _0057_;
assign _0060_ = _0022_ & N;
assign _0061_ = ~((_0023_ & _0646_) | _0060_);
assign _0062_ = _0394_ & _0197_;
assign _0063_ = ~(_0628_ & _0062_);
assign _0064_ = ~((_0019_ | _0063_) & K);
assign _0065_ = _0016_ & _0001_;
assign _0066_ = _0014_ & G;
assign _0067_ = ~((_0015_ & _0002_) | _0066_);
assign _0068_ = _0009_ & D;
assign _0069_ = _0007_ | _0068_;
assign _0070_ = ~((_0013_ & _0011_) | _0069_);
assign _0071_ = _0070_ ^ _0067_;
assign _0072_ = _0071_ ^ _0065_;
assign _0073_ = ~(_0017_ & _0651_);
assign _0074_ = ~(_0018_ & _0650_);
assign _0075_ = _0074_ & _0073_;
assign _0076_ = _0075_ ^ _0072_;
assign _0077_ = _0076_ ^ _0064_;
assign _0078_ = _0020_ | _0647_;
assign _0079_ = ~(_0021_ & M);
assign _0080_ = _0079_ & _0078_;
assign _0081_ = _0080_ ^ _0077_;
assign _0082_ = _0081_ ^ _0061_;
assign _0083_ = ~(_0082_ & _0059_);
assign _0084_ = _0082_ | _0059_;
assign _0085_ = _0084_ & _0083_;
assign _0086_ = _0029_ & _0026_;
assign _0087_ = _0030_ & _0644_;
assign _0088_ = ~(_0087_ | _0086_);
assign _0089_ = _0088_ ^ _0085_;
assign _0090_ = ~(_0089_ ^ _0056_);
assign _0091_ = ~(_0090_ | _0055_);
assign _0092_ = ~T;
assign _0093_ = _0053_ & _0052_;
assign _0094_ = ~(_0041_ | S);
assign _0095_ = _0094_ & _0043_;
assign _0096_ = ~(_0095_ & _0038_);
assign _0097_ = ~(_0046_ | _0092_);
assign _0098_ = ~((_0037_ & S) | _0045_);
assign _0099_ = ~(_0098_ & _0049_);
assign _0100_ = _0098_ | _0049_;
assign _0101_ = ~((_0100_ & _0099_) | (_0097_ & _0096_));
assign _0102_ = ~(_0101_ & _0092_);
assign _0103_ = ~(_0102_ & _0054_);
assign _0104_ = ~((_0103_ | _0093_) & (_0101_ | _0092_));
assign _0105_ = ~(_0089_ | _0056_);
assign _0106_ = _0085_ & _0087_;
assign _0107_ = ~(_0081_ | _0061_);
assign _0108_ = ~_0079_;
assign _0109_ = _0077_ & _0108_;
assign _0110_ = ~_0075_;
assign _0111_ = ~(_0071_ & _0065_);
assign _0112_ = ~((_0070_ | _0067_) & _0111_);
assign _0113_ = ~((_0110_ & _0072_) | _0112_);
assign _0114_ = ~_0078_;
assign _0115_ = ~(_0076_ | _0064_);
assign _0116_ = ~((_0077_ & _0114_) | _0115_);
assign _0117_ = _0116_ ^ _0113_;
assign _0118_ = _0117_ ^ _0109_;
assign _0119_ = ~(_0118_ ^ _0107_);
assign _0121_ = ~(_0084_ & _0086_);
assign _0122_ = _0121_ & _0083_;
assign _0123_ = _0122_ ^ _0119_;
assign _0124_ = _0123_ ^ _0106_;
assign _0125_ = ~(_0124_ ^ _0105_);
assign _0126_ = ~((_0090_ & _0055_) | _0125_);
assign _0127_ = ~((_0104_ | _0091_) & _0126_);
assign _0128_ = ~(_0123_ & _0106_);
assign _0129_ = ~(_0122_ | _0119_);
assign _0130_ = ~(_0117_ & _0109_);
assign _0132_ = ~((_0116_ | _0113_) & _0130_);
assign _0133_ = ~(_0132_ | _0129_);
assign _0134_ = _0133_ & _0128_;
assign _0135_ = _0118_ & _0107_;
assign _0136_ = ~((_0124_ & _0105_) | _0135_);
assign _0137_ = _0136_ & _0134_;
assign _0138_ = E ^ C;
assign _0139_ = _0138_ ^ H;
assign _0140_ = _0139_ ^ K;
assign _0141_ = _0140_ & L;
assign _0143_ = _0138_ & H;
assign _0144_ = _0139_ & K;
assign _0145_ = _0144_ | _0143_;
assign _0146_ = E ^ D;
assign _0147_ = C ? _0008_ : _0146_;
assign _0148_ = _0147_ ^ G;
assign _0149_ = _0148_ ^ _0145_;
assign _0150_ = _0149_ & _0141_;
assign _0151_ = _0150_ | _0527_;
assign _0152_ = _0148_ & _0143_;
assign _0154_ = ~G;
assign _0155_ = _0147_ | _0154_;
assign _0156_ = D & C;
assign _0157_ = _0156_ ^ A;
assign _0158_ = ~((D | C) & E);
assign _0159_ = ~(_0158_ ^ _0157_);
assign _0160_ = _0159_ ^ _0274_;
assign _0161_ = _0160_ ^ _0155_;
assign _0162_ = _0161_ ^ _0152_;
assign _0163_ = _0162_ ^ I;
assign _0165_ = ~K;
assign _0166_ = ~((_0148_ & _0139_) | _0165_);
assign _0167_ = _0166_ ^ _0163_;
assign _0168_ = _0167_ ^ _0151_;
assign _0169_ = _0149_ ^ _0141_;
assign _0170_ = ~(_0169_ | _0142_);
assign _0171_ = _0169_ ^ _0142_;
assign _0172_ = ~((_0171_ & O) | _0170_);
assign _0173_ = _0172_ ^ _0168_;
assign _0174_ = _0173_ ^ _0131_;
assign _0176_ = _0140_ ^ L;
assign _0177_ = ~O;
assign _0178_ = _0171_ ^ _0177_;
assign _0179_ = ~(_0178_ | _0176_);
assign _0180_ = _0179_ & Q;
assign _0181_ = _0180_ ^ _0174_;
assign _0182_ = ~(_0176_ | _0120_);
assign _0183_ = ~(_0182_ ^ _0178_);
assign _0184_ = ~(_0183_ | _0635_);
assign _0185_ = _0176_ ^ _0120_;
assign _0187_ = ~(_0185_ | _0042_);
assign _0188_ = _0183_ ^ _0635_;
assign _0189_ = _0188_ & _0187_;
assign _0190_ = ~(_0189_ | _0184_);
assign _0191_ = _0190_ ^ _0181_;
assign _0192_ = _0188_ ^ _0187_;
assign _0193_ = ~((_0192_ | _0191_) & T);
assign _0194_ = ~((_0174_ & _0179_) | _0120_);
assign _0195_ = ~(_0173_ | _0131_);
assign _0196_ = ~((_0168_ & _0171_) | _0177_);
assign _0198_ = ~(_0167_ | _0151_);
assign _0199_ = ~((_0163_ & K) | (_0148_ & _0144_));
assign _0200_ = ~_0147_;
assign _0201_ = _0160_ & _0200_;
assign _0202_ = _0201_ | _0154_;
assign _0203_ = _0159_ | _0274_;
assign _0204_ = ~_0158_;
assign _0205_ = _0204_ & _0157_;
assign _0206_ = ~C;
assign _0207_ = ~(_0604_ | _0206_);
assign _0209_ = _0207_ ^ _0005_;
assign _0210_ = _0209_ ^ _0593_;
assign _0211_ = _0210_ ^ _0205_;
assign _0212_ = _0211_ ^ _0203_;
assign _0213_ = _0212_ ^ _0202_;
assign _0214_ = _0161_ & _0152_;
assign _0215_ = ~((_0162_ & I) | _0214_);
assign _0216_ = _0215_ ^ _0213_;
assign _0217_ = ~(_0216_ ^ _0199_);
assign _0218_ = _0217_ ^ _0198_;
assign _0220_ = _0218_ ^ M;
assign _0221_ = _0168_ & _0170_;
assign _0222_ = ~(_0221_ ^ _0220_);
assign _0223_ = _0222_ ^ _0196_;
assign _0224_ = _0223_ ^ _0195_;
assign _0225_ = _0224_ ^ _0194_;
assign _0226_ = _0225_ ^ R;
assign _0227_ = _0190_ | _0181_;
assign _0228_ = _0227_ ^ _0226_;
assign _0229_ = ~(_0228_ | _0193_);
assign _0231_ = ~_0189_;
assign _0232_ = ~(_0181_ | _0231_);
assign _0233_ = _0232_ & _0226_;
assign _0234_ = ~(_0225_ & R);
assign _0235_ = ~_0184_;
assign _0236_ = ~((_0181_ | _0235_) & _0234_);
assign _0237_ = _0223_ | _0173_;
assign _0238_ = _0237_ & P;
assign _0239_ = ~M;
assign _0240_ = ~(_0218_ | _0239_);
assign _0242_ = ~(_0166_ ^ _0163_);
assign _0243_ = ~((_0217_ & _0242_) | _0527_);
assign _0244_ = _0243_ | _0150_;
assign _0245_ = ~(_0216_ | _0199_);
assign _0246_ = _0213_ & _0214_;
assign _0247_ = ~(_0212_ | _0202_);
assign _0248_ = ~(_0211_ | _0203_);
assign _0249_ = ~(_0204_ & _0157_);
assign _0250_ = _0209_ | _0593_;
assign _0251_ = _0209_ & _0593_;
assign _0252_ = ~((_0251_ | _0249_) & _0250_);
assign _0253_ = ~B;
assign _0254_ = ~(_0253_ | A);
assign _0255_ = ~((_0253_ & A) | C);
assign _0256_ = _0255_ | _0254_;
assign _0257_ = _0156_ | _0604_;
assign _0258_ = ~((_0257_ & _0253_) | (_0256_ & _0008_));
assign _0259_ = _0258_ ^ E;
assign _0260_ = _0259_ ^ _0252_;
assign _0261_ = _0260_ ^ _0248_;
assign _0264_ = _0261_ ^ _0247_;
assign _0265_ = ~(_0264_ ^ _0246_);
assign _0266_ = ~(_0213_ & _0162_);
assign _0267_ = ~(_0266_ & I);
assign _0268_ = _0267_ ^ _0265_;
assign _0269_ = _0268_ ^ _0245_;
assign _0270_ = _0269_ ^ _0244_;
assign _0271_ = _0270_ ^ _0240_;
assign _0272_ = ~_0168_;
assign _0273_ = ~(_0272_ | _0169_);
assign _0275_ = ~((_0273_ & _0220_) | _0142_);
assign _0276_ = _0275_ ^ _0271_;
assign _0277_ = _0222_ & _0196_;
assign _0278_ = ~(_0277_ | _0177_);
assign _0279_ = _0278_ ^ _0276_;
assign _0280_ = ~(_0279_ ^ _0238_);
assign _0281_ = ~(_0224_ & _0194_);
assign _0282_ = _0281_ & Q;
assign _0283_ = ~(_0282_ ^ _0280_);
assign _0284_ = _0283_ ^ R;
assign _0286_ = _0284_ ^ _0236_;
assign _0287_ = _0286_ ^ _0233_;
assign _0288_ = ~((_0287_ & T) | _0229_);
assign _0289_ = ~(_0286_ & _0233_);
assign _0290_ = ~(_0283_ & R);
assign _0291_ = ~(_0284_ & _0236_);
assign _0292_ = _0291_ & _0290_;
assign _0293_ = ~((_0280_ | _0120_) & _0281_);
assign _0294_ = _0279_ & _0238_;
assign _0295_ = ~((_0276_ & O) | _0277_);
assign _0297_ = _0275_ & _0271_;
assign _0298_ = _0270_ & _0240_;
assign _0299_ = _0269_ & _0244_;
assign _0300_ = _0268_ & _0245_;
assign _0301_ = ~((_0266_ & _0265_) | _0153_);
assign _0302_ = _0204_ | _0157_;
assign _0303_ = ~(_0210_ | _0302_);
assign _0304_ = _0210_ & _0205_;
assign _0305_ = _0304_ | _0274_;
assign _0306_ = ~(_0260_ & F);
assign _0308_ = ~((_0305_ | _0303_) & _0306_);
assign _0309_ = ~(_0258_ & E);
assign _0310_ = _0309_ & _0250_;
assign _0311_ = _0156_ & A;
assign _0312_ = ~_0311_;
assign _0313_ = ~(_0256_ | _0008_);
assign _0314_ = ~(B | A);
assign _0315_ = ~_0314_;
assign _0316_ = _0009_ | C;
assign _0317_ = _0316_ & _0315_;
assign _0319_ = ~((_0317_ | _0313_) & _0312_);
assign _0320_ = ~((_0319_ & _0310_) | _0205_);
assign _0321_ = ~(_0320_ ^ _0308_);
assign _0322_ = ~(_0261_ & _0247_);
assign _0323_ = ~(_0264_ & _0246_);
assign _0324_ = _0323_ & _0322_;
assign _0325_ = _0324_ ^ _0321_;
assign _0326_ = _0325_ ^ _0301_;
assign _0327_ = _0326_ ^ _0300_;
assign _0328_ = _0327_ ^ _0299_;
assign _0329_ = _0328_ ^ _0298_;
assign _0330_ = ~(_0329_ ^ _0297_);
assign _0331_ = _0330_ ^ _0295_;
assign _0332_ = _0331_ ^ _0294_;
assign _0333_ = ~(_0332_ ^ _0293_);
assign _0334_ = ~(_0333_ ^ _0292_);
assign _0335_ = _0334_ | _0289_;
assign _0336_ = ~(_0334_ ^ _0289_);
assign _0337_ = ~((_0336_ | _0288_) & _0335_);
assign _0338_ = ~_0229_;
assign _0341_ = _0336_ & _0338_;
assign _0342_ = _0287_ | T;
assign _0343_ = ~_0191_;
assign _0344_ = _0192_ | _0092_;
assign _0345_ = _0344_ & _0343_;
assign _0346_ = _0192_ & _0092_;
assign _0347_ = _0185_ & _0042_;
assign _0348_ = ~((_0347_ | _0187_) & _0344_);
assign _0349_ = ~((_0348_ | _0346_) & (_0344_ | _0343_));
assign _0350_ = _0349_ | _0345_;
assign _0352_ = ~((_0228_ & _0193_) | _0350_);
assign _0353_ = _0352_ & _0342_;
assign _0354_ = ~(_0353_ & _0288_);
assign _0355_ = _0005_ ^ J;
assign _0356_ = _0355_ ^ _0165_;
assign _0357_ = _0356_ & M;
assign _0358_ = _0355_ | _0165_;
assign _0359_ = J ? _0009_ : _0314_;
assign _0360_ = _0359_ ^ _0358_;
assign _0361_ = _0360_ ^ L;
assign _0363_ = _0361_ ^ _0357_;
assign _0364_ = _0356_ ^ M;
assign _0365_ = _0364_ | _0177_;
assign _0366_ = _0365_ ^ _0363_;
assign _0367_ = ~(_0366_ | _0131_);
assign _0368_ = ~((_0364_ | _0363_) & O);
assign _0369_ = _0361_ & _0357_;
assign _0370_ = _0009_ ^ _0206_;
assign _0371_ = _0370_ ^ _0008_;
assign _0372_ = _0371_ ^ G;
assign _0374_ = _0372_ ^ H;
assign _0375_ = _0374_ ^ _0153_;
assign _0376_ = _0314_ & J;
assign _0377_ = _0376_ ^ _0375_;
assign _0378_ = _0377_ ^ _0165_;
assign _0379_ = _0359_ | _0358_;
assign _0380_ = _0360_ & L;
assign _0381_ = ~_0380_;
assign _0382_ = ~(_0381_ & _0379_);
assign _0383_ = _0382_ ^ _0378_;
assign _0384_ = _0383_ ^ _0369_;
assign _0385_ = _0384_ ^ _0142_;
assign _0386_ = _0385_ ^ _0368_;
assign _0387_ = ~(_0386_ ^ _0367_);
assign _0388_ = _0366_ ^ _0131_;
assign _0389_ = ~(_0388_ | _0120_);
assign _0390_ = _0389_ ^ _0387_;
assign _0391_ = _0385_ | _0368_;
assign _0392_ = ~(_0386_ & _0367_);
assign _0393_ = _0392_ & _0391_;
assign _0396_ = _0384_ | _0142_;
assign _0397_ = ~(_0383_ & _0369_);
assign _0398_ = _0378_ & _0380_;
assign _0399_ = ~((_0377_ | _0165_) & _0379_);
assign _0400_ = ~(_0376_ & _0375_);
assign _0401_ = _0374_ | _0153_;
assign _0402_ = ~(_0370_ | _0008_);
assign _0403_ = ~((_0009_ & _0206_) | _0314_);
assign _0404_ = _0403_ ^ _0402_;
assign _0405_ = _0404_ ^ F;
assign _0407_ = _0371_ & G;
assign _0408_ = ~((_0372_ & H) | _0407_);
assign _0409_ = ~(_0408_ ^ _0405_);
assign _0410_ = _0409_ ^ _0401_;
assign _0411_ = _0410_ ^ _0400_;
assign _0412_ = _0411_ ^ _0399_;
assign _0413_ = _0412_ ^ _0398_;
assign _0414_ = _0413_ ^ _0239_;
assign _0415_ = _0414_ ^ _0397_;
assign _0416_ = _0415_ ^ _0396_;
assign _0418_ = _0416_ ^ _0393_;
assign _0419_ = ~_0418_;
assign _0420_ = ~((_0419_ & _0390_) | _0635_);
assign _0421_ = ~_0388_;
assign _0422_ = ~(_0421_ & _0387_);
assign _0423_ = ~(_0418_ | _0422_);
assign _0424_ = ~(_0423_ & Q);
assign _0425_ = _0416_ | _0392_;
assign _0426_ = ~(_0416_ | _0391_);
assign _0427_ = ~(_0415_ | _0396_);
assign _0429_ = ~(_0413_ & M);
assign _0430_ = ~((_0414_ | _0397_) & _0429_);
assign _0431_ = _0412_ & _0398_;
assign _0432_ = _0411_ & _0399_;
assign _0433_ = _0405_ & _0407_;
assign _0434_ = _0404_ | _0274_;
assign _0435_ = ~_0156_;
assign _0436_ = ~((_0435_ | _0009_) & _0315_);
assign _0437_ = _0436_ ^ _0434_;
assign _0438_ = ~(_0437_ ^ _0433_);
assign _0440_ = _0372_ & H;
assign _0441_ = ~(_0405_ & _0440_);
assign _0442_ = ~(_0441_ & H);
assign _0443_ = _0442_ ^ _0438_;
assign _0444_ = _0409_ | _0374_;
assign _0445_ = _0444_ & I;
assign _0446_ = _0445_ ^ _0443_;
assign _0447_ = ~(_0409_ | _0315_);
assign _0448_ = ~((_0447_ & _0375_) | _0636_);
assign _0449_ = _0448_ ^ _0446_;
assign _0451_ = _0449_ ^ _0432_;
assign _0452_ = _0451_ ^ _0431_;
assign _0453_ = _0452_ ^ _0430_;
assign _0454_ = _0453_ ^ _0427_;
assign _0455_ = _0454_ ^ O;
assign _0456_ = _0455_ ^ _0426_;
assign _0457_ = _0456_ ^ P;
assign _0458_ = _0457_ ^ _0425_;
assign _0459_ = _0458_ ^ _0424_;
assign _0460_ = _0459_ & _0420_;
assign _0462_ = ~(_0456_ & P);
assign _0463_ = ~(_0456_ | P);
assign _0464_ = ~((_0463_ | _0425_) & _0462_);
assign _0465_ = _0454_ & O;
assign _0466_ = _0455_ & _0426_;
assign _0467_ = _0466_ | _0465_;
assign _0468_ = ~(_0383_ | _0369_);
assign _0469_ = _0414_ & _0468_;
assign _0470_ = ~((_0414_ | _0397_) & N);
assign _0471_ = ~(_0453_ & N);
assign _0473_ = ~((_0470_ | _0469_) & _0471_);
assign _0474_ = _0452_ & _0430_;
assign _0475_ = _0449_ & _0432_;
assign _0476_ = ~_0475_;
assign _0477_ = _0445_ & _0443_;
assign _0478_ = ~((_0438_ | _0318_) & _0441_);
assign _0479_ = _0437_ & _0433_;
assign _0480_ = ~_0404_;
assign _0481_ = ~((_0436_ & _0480_) | _0274_);
assign _0482_ = _0156_ | _0009_;
assign _0484_ = _0482_ & _0315_;
assign _0485_ = _0484_ ^ _0481_;
assign _0486_ = _0485_ ^ _0479_;
assign _0487_ = _0486_ ^ _0478_;
assign _0488_ = _0487_ ^ _0477_;
assign _0489_ = _0488_ & _0475_;
assign _0490_ = _0451_ & _0431_;
assign _0491_ = _0448_ & _0446_;
assign _0492_ = _0488_ ^ _0491_;
assign _0493_ = ~(_0492_ ^ _0490_);
assign _0495_ = ~((_0493_ & _0476_) | _0489_);
assign _0496_ = _0495_ ^ _0474_;
assign _0497_ = _0496_ ^ _0473_;
assign _0498_ = _0497_ ^ _0467_;
assign _0499_ = _0498_ ^ _0464_;
assign _0500_ = ~((_0458_ & _0423_) | _0120_);
assign _0501_ = _0500_ ^ _0499_;
assign _0502_ = _0501_ ^ _0460_;
assign _0503_ = ~(_0459_ ^ _0420_);
assign _0504_ = _0389_ & _0387_;
assign _0506_ = ~(_0418_ ^ _0504_);
assign _0507_ = _0390_ ^ R;
assign _0508_ = _0507_ & _0506_;
assign _0509_ = ~((_0508_ & _0503_) | _0042_);
assign _0510_ = _0509_ | _0502_;
assign _0511_ = _0390_ & R;
assign _0512_ = _0511_ ^ _0506_;
assign _0513_ = _0507_ & S;
assign _0514_ = ~(_0513_ | _0512_);
assign _0515_ = _0513_ & _0506_;
assign _0517_ = ~(_0515_ | _0514_);
assign _0518_ = _0517_ ^ _0092_;
assign _0519_ = _0507_ ^ S;
assign _0520_ = _0519_ ^ T;
assign _0521_ = _0388_ ^ Q;
assign _0522_ = _0364_ ^ _0177_;
assign _0523_ = ~(_0522_ | _0092_);
assign _0524_ = ~(_0523_ & _0521_);
assign _0525_ = ~(_0524_ | _0520_);
assign _0526_ = _0519_ | _0092_;
assign _0528_ = ~((_0512_ | _0092_) & _0526_);
assign _0529_ = ~((_0525_ & _0518_) | _0528_);
assign _0530_ = _0515_ ^ _0503_;
assign _0531_ = _0509_ & _0502_;
assign _0532_ = ~((_0530_ & _0529_) | _0531_);
assign _0533_ = _0532_ & _0510_;
assign _0534_ = ~(_0530_ | _0529_);
assign _0535_ = _0501_ & _0460_;
assign _0536_ = _0500_ & _0499_;
assign _0537_ = ~(_0498_ & _0464_);
assign _0539_ = ~(_0497_ & _0467_);
assign _0540_ = ~(_0496_ & _0473_);
assign _0541_ = _0495_ & _0474_;
assign _0542_ = _0492_ & _0490_;
assign _0543_ = ~(_0488_ & _0475_);
assign _0544_ = ~(_0486_ & _0478_);
assign _0545_ = _0484_ & _0481_;
assign _0546_ = ~((_0485_ & _0479_) | _0545_);
assign _0547_ = _0546_ & _0544_;
assign _0548_ = ~((_0491_ | _0477_) & _0487_);
assign _0550_ = ~(_0548_ ^ _0547_);
assign _0551_ = _0550_ ^ _0543_;
assign _0552_ = _0551_ ^ _0542_;
assign _0553_ = _0552_ ^ _0541_;
assign _0554_ = _0553_ ^ _0540_;
assign _0555_ = ~(_0554_ ^ _0539_);
assign _0556_ = _0555_ ^ _0537_;
assign _0557_ = _0556_ ^ _0536_;
assign _0558_ = _0557_ ^ _0535_;
assign _0559_ = _0517_ ^ T;
assign _0561_ = _0522_ & _0092_;
assign _0562_ = _0521_ ? _0523_ : _0561_;
assign _0563_ = _0562_ | _0520_;
assign _0564_ = ~((_0526_ & _0559_) | _0563_);
assign _0565_ = ~(_0564_ | _0534_);
assign _0566_ = ~((_0558_ & _0534_) | _0565_);
assign _0567_ = _0556_ & _0536_;
assign _0568_ = _0332_ & _0293_;
assign _0569_ = ~(_0329_ & _0297_);
assign _0570_ = ~((_0330_ | _0295_) & _0569_);
assign _0572_ = _0327_ & _0299_;
assign _0573_ = _0328_ & _0298_;
assign _0574_ = _0573_ | _0572_;
assign _0575_ = _0321_ | _0322_;
assign _0576_ = _0249_ & _0312_;
assign _0577_ = _0320_ & _0308_;
assign _0578_ = _0577_ ^ _0576_;
assign _0579_ = _0578_ & _0323_;
assign _0580_ = _0579_ & _0575_;
assign _0581_ = ~(_0325_ & _0301_);
assign _0583_ = ~(_0326_ & _0300_);
assign _0584_ = _0583_ & _0581_;
assign _0585_ = _0584_ ^ _0580_;
assign _0586_ = _0585_ ^ _0574_;
assign _0587_ = _0586_ & _0570_;
assign _0588_ = _0496_ & _0473_;
assign _0589_ = ~(_0552_ & _0588_);
assign _0590_ = _0550_ | _0543_;
assign _0591_ = ~(_0580_ | _0581_);
assign _0592_ = ~((_0577_ & _0311_) | _0591_);
assign _0594_ = _0592_ & _0590_;
assign _0595_ = ~((_0580_ | _0583_) & (_0548_ | _0547_));
assign _0596_ = ~((_0551_ & _0542_) | _0595_);
assign _0597_ = ~(_0596_ & _0594_);
assign _0598_ = ~((_0585_ & _0574_) | _0597_);
assign _0599_ = ~(_0598_ & _0589_);
assign _0600_ = _0599_ | _0587_;
assign _0601_ = _0600_ | _0568_;
assign _0602_ = _0331_ & _0294_;
assign _0603_ = _0586_ ^ _0570_;
assign _0605_ = _0603_ & _0602_;
assign _0606_ = ~(_0552_ & _0541_);
assign _0607_ = ~((_0554_ | _0539_) & _0606_);
assign _0608_ = _0607_ | _0605_;
assign _0609_ = _0608_ | _0601_;
assign _0610_ = ~((_0291_ & _0290_) | _0333_);
assign _0611_ = ~(_0603_ | _0602_);
assign _0612_ = ~((_0611_ | _0605_) & (_0555_ | _0537_));
assign _0613_ = _0612_ | _0610_;
assign _0614_ = _0613_ | _0609_;
assign _0616_ = _0614_ | _0567_;
assign _0617_ = _0558_ | _0531_;
assign _0618_ = _0617_ | _0616_;
assign _0619_ = ~((_0566_ & _0533_) | _0618_);
assign _0620_ = ~((_0354_ | _0341_) & _0619_);
assign _0621_ = _0620_ | _0337_;
assign valid = ~((_0137_ & _0127_) | _0621_);
endmodule | module var20_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, valid); |
wire _0000_;
wire _0001_;
wire _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
(* src = "var20_multi.v:3" *)
input A;
(* src = "var20_multi.v:3" *)
input B;
(* src = "var20_multi.v:3" *)
input C;
(* src = "var20_multi.v:3" *)
input D;
(* src = "var20_multi.v:3" *)
input E;
(* src = "var20_multi.v:3" *)
input F;
(* src = "var20_multi.v:3" *)
input G;
(* src = "var20_multi.v:3" *)
input H;
(* src = "var20_multi.v:3" *)
input I;
(* src = "var20_multi.v:3" *)
input J;
(* src = "var20_multi.v:3" *)
input K;
(* src = "var20_multi.v:3" *)
input L;
(* src = "var20_multi.v:3" *)
input M;
(* src = "var20_multi.v:3" *)
input N;
(* src = "var20_multi.v:3" *)
input O;
(* src = "var20_multi.v:3" *)
input P;
(* src = "var20_multi.v:3" *)
input Q;
(* src = "var20_multi.v:3" *)
input R;
(* src = "var20_multi.v:3" *)
input S;
(* src = "var20_multi.v:3" *)
input T;
(* src = "var20_multi.v:4" *)
output valid;
assign _0120_ = ~Q;
assign _0131_ = ~P;
assign _0142_ = ~N;
assign _0153_ = ~I;
assign _0164_ = G ^ E;
assign _0175_ = _0164_ ^ H;
assign _0186_ = _0175_ ^ _0153_;
assign _0197_ = _0186_ ^ J;
assign _0208_ = _0197_ ^ K;
assign _0219_ = _0208_ ^ _0142_;
assign _0230_ = _0219_ ^ O;
assign _0241_ = _0230_ ^ _0131_;
assign _0262_ = _0197_ & K;
assign _0263_ = ~(G & E);
assign _0274_ = ~F;
assign _0285_ = D ^ A;
assign _0296_ = _0285_ ^ _0274_;
assign _0307_ = ~(_0296_ ^ _0263_);
assign _0318_ = ~H;
assign _0339_ = ~(_0164_ | _0318_);
assign _0340_ = _0339_ ^ _0307_;
assign _0351_ = ~_0175_;
assign _0362_ = _0186_ & J;
assign _0373_ = ~((_0351_ & I) | _0362_);
assign _0394_ = ~(_0373_ ^ _0340_);
assign _0395_ = _0394_ ^ _0262_;
assign _0406_ = ~(_0208_ | _0142_);
assign _0417_ = _0219_ & O;
assign _0428_ = ~(_0417_ | _0406_);
assign _0439_ = _0428_ ^ _0395_;
assign _0450_ = ~(_0439_ | J);
assign _0461_ = ~((_0450_ & _0241_) | _0120_);
assign _0472_ = _0230_ | _0131_;
assign _0483_ = ~(_0439_ | _0472_);
assign _0494_ = ~_0395_;
assign _0505_ = _0494_ & _0417_;
assign _0516_ = _0494_ & _0406_;
assign _0527_ = ~L;
assign _0538_ = _0394_ & _0262_;
assign _0549_ = ~((_0307_ & _0351_) | _0153_);
assign _0560_ = _0339_ & _0307_;
assign _0571_ = ~(_0296_ | _0263_);
assign _0582_ = _0285_ | _0274_;
assign _0593_ = ~E;
assign _0604_ = D & A;
assign _0615_ = _0604_ ^ B;
assign _0622_ = _0615_ ^ _0593_;
assign _0623_ = _0622_ ^ _0582_;
assign _0624_ = _0623_ ^ _0571_;
assign _0625_ = _0624_ ^ _0560_;
assign _0626_ = ~(_0625_ ^ _0549_);
assign _0627_ = _0340_ & _0362_;
assign _0628_ = _0627_ ^ _0626_;
assign _0629_ = _0628_ ^ _0538_;
assign _0630_ = _0629_ ^ _0527_;
assign _0631_ = _0630_ ^ _0516_;
assign _0632_ = _0631_ ^ _0505_;
assign _0633_ = _0632_ ^ _0483_;
assign _0634_ = _0633_ ^ _0461_;
assign _0635_ = ~R;
assign _0636_ = ~J;
assign _0637_ = Q & _0636_;
assign _0638_ = _0120_ & J;
assign _0639_ = ~(_0638_ | _0637_);
assign _0640_ = _0639_ & _0241_;
assign _0641_ = _0439_ ^ _0472_;
assign _0642_ = ~((_0641_ & _0640_) | _0635_);
assign _0643_ = _0642_ & _0634_;
assign _0644_ = _0633_ & _0461_;
assign _0645_ = _0631_ & _0505_;
assign _0646_ = _0630_ & _0516_;
assign _0647_ = _0629_ | _0527_;
assign _0648_ = ~(_0628_ & _0538_);
assign _0649_ = _0340_ & _0186_;
assign _0650_ = ~((_0649_ & _0626_) | _0636_);
assign _0651_ = _0625_ & _0549_;
assign _0652_ = _0164_ & H;
assign _0653_ = ~(_0296_ & _0652_);
assign _0000_ = _0624_ ? _0318_ : _0653_;
assign _0001_ = ~((_0307_ | _0318_) & _0000_);
assign _0002_ = _0623_ & _0571_;
assign _0003_ = ~(_0615_ & E);
assign _0004_ = E & D;
assign _0005_ = ~(B ^ A);
assign _0006_ = ~_0005_;
assign _0007_ = _0006_ & _0004_;
assign _0008_ = ~D;
assign _0009_ = B & A;
assign _0010_ = _0009_ | _0008_;
assign _0011_ = ~((_0010_ & _0003_) | _0007_);
assign _0012_ = ~_0285_;
assign _0013_ = ~((_0622_ & _0012_) | _0274_);
assign _0014_ = _0013_ ^ _0011_;
assign _0015_ = _0014_ ^ G;
assign _0016_ = _0015_ ^ _0002_;
assign _0017_ = _0016_ ^ _0001_;
assign _0018_ = _0017_ ^ _0651_;
assign _0019_ = _0018_ ^ _0650_;
assign _0020_ = _0019_ ^ _0648_;
assign _0021_ = _0020_ ^ _0647_;
assign _0022_ = _0021_ ^ M;
assign _0023_ = _0022_ ^ N;
assign _0024_ = _0023_ ^ _0646_;
assign _0025_ = _0024_ ^ O;
assign _0026_ = _0025_ ^ _0645_;
assign _0027_ = ~_0632_;
assign _0028_ = ~(_0439_ | _0230_);
assign _0029_ = ~((_0028_ & _0027_) | _0131_);
assign _0030_ = _0029_ ^ _0026_;
assign _0031_ = _0030_ ^ _0644_;
assign _0032_ = _0031_ ^ _0643_;
assign _0033_ = ~(_0032_ & S);
assign _0034_ = _0640_ & R;
assign _0035_ = _0637_ & _0241_;
assign _0036_ = _0035_ ? _0439_ : _0641_;
assign _0037_ = ~(_0036_ ^ _0034_);
assign _0038_ = ~_0037_;
assign _0039_ = ~(_0637_ | R);
assign _0040_ = ~(_0039_ | _0638_);
assign _0041_ = ~(_0040_ ^ _0241_);
assign _0042_ = ~S;
assign _0043_ = _0639_ ^ R;
assign _0044_ = ~(_0043_ | _0042_);
assign _0045_ = _0044_ & _0041_;
assign _0046_ = _0045_ & _0038_;
assign _0047_ = ~_0046_;
assign _0048_ = _0642_ ^ _0634_;
assign _0049_ = _0048_ ^ _0042_;
assign _0050_ = _0049_ | _0047_;
assign _0051_ = ~((_0048_ | _0037_) & S);
assign _0052_ = _0051_ & _0050_;
assign _0053_ = _0032_ ^ _0042_;
assign _0054_ = _0053_ | _0052_;
assign _0055_ = _0054_ & _0033_;
assign _0056_ = ~(_0031_ & _0643_);
assign _0057_ = _0024_ & O;
assign _0058_ = _0025_ & _0645_;
assign _0059_ = _0058_ | _0057_;
assign _0060_ = _0022_ & N;
assign _0061_ = ~((_0023_ & _0646_) | _0060_);
assign _0062_ = _0394_ & _0197_;
assign _0063_ = ~(_0628_ & _0062_);
assign _0064_ = ~((_0019_ | _0063_) & K);
assign _0065_ = _0016_ & _0001_;
assign _0066_ = _0014_ & G;
assign _0067_ = ~((_0015_ & _0002_) | _0066_);
assign _0068_ = _0009_ & D;
assign _0069_ = _0007_ | _0068_;
assign _0070_ = ~((_0013_ & _0011_) | _0069_);
assign _0071_ = _0070_ ^ _0067_;
assign _0072_ = _0071_ ^ _0065_;
assign _0073_ = ~(_0017_ & _0651_);
assign _0074_ = ~(_0018_ & _0650_);
assign _0075_ = _0074_ & _0073_;
assign _0076_ = _0075_ ^ _0072_;
assign _0077_ = _0076_ ^ _0064_;
assign _0078_ = _0020_ | _0647_;
assign _0079_ = ~(_0021_ & M);
assign _0080_ = _0079_ & _0078_;
assign _0081_ = _0080_ ^ _0077_;
assign _0082_ = _0081_ ^ _0061_;
assign _0083_ = ~(_0082_ & _0059_);
assign _0084_ = _0082_ | _0059_;
assign _0085_ = _0084_ & _0083_;
assign _0086_ = _0029_ & _0026_;
assign _0087_ = _0030_ & _0644_;
assign _0088_ = ~(_0087_ | _0086_);
assign _0089_ = _0088_ ^ _0085_;
assign _0090_ = ~(_0089_ ^ _0056_);
assign _0091_ = ~(_0090_ | _0055_);
assign _0092_ = ~T;
assign _0093_ = _0053_ & _0052_;
assign _0094_ = ~(_0041_ | S);
assign _0095_ = _0094_ & _0043_;
assign _0096_ = ~(_0095_ & _0038_);
assign _0097_ = ~(_0046_ | _0092_);
assign _0098_ = ~((_0037_ & S) | _0045_);
assign _0099_ = ~(_0098_ & _0049_);
assign _0100_ = _0098_ | _0049_;
assign _0101_ = ~((_0100_ & _0099_) | (_0097_ & _0096_));
assign _0102_ = ~(_0101_ & _0092_);
assign _0103_ = ~(_0102_ & _0054_);
assign _0104_ = ~((_0103_ | _0093_) & (_0101_ | _0092_));
assign _0105_ = ~(_0089_ | _0056_);
assign _0106_ = _0085_ & _0087_;
assign _0107_ = ~(_0081_ | _0061_);
assign _0108_ = ~_0079_;
assign _0109_ = _0077_ & _0108_;
assign _0110_ = ~_0075_;
assign _0111_ = ~(_0071_ & _0065_);
assign _0112_ = ~((_0070_ | _0067_) & _0111_);
assign _0113_ = ~((_0110_ & _0072_) | _0112_);
assign _0114_ = ~_0078_;
assign _0115_ = ~(_0076_ | _0064_);
assign _0116_ = ~((_0077_ & _0114_) | _0115_);
assign _0117_ = _0116_ ^ _0113_;
assign _0118_ = _0117_ ^ _0109_;
assign _0119_ = ~(_0118_ ^ _0107_);
assign _0121_ = ~(_0084_ & _0086_);
assign _0122_ = _0121_ & _0083_;
assign _0123_ = _0122_ ^ _0119_;
assign _0124_ = _0123_ ^ _0106_;
assign _0125_ = ~(_0124_ ^ _0105_);
assign _0126_ = ~((_0090_ & _0055_) | _0125_);
assign _0127_ = ~((_0104_ | _0091_) & _0126_);
assign _0128_ = ~(_0123_ & _0106_);
assign _0129_ = ~(_0122_ | _0119_);
assign _0130_ = ~(_0117_ & _0109_);
assign _0132_ = ~((_0116_ | _0113_) & _0130_);
assign _0133_ = ~(_0132_ | _0129_);
assign _0134_ = _0133_ & _0128_;
assign _0135_ = _0118_ & _0107_;
assign _0136_ = ~((_0124_ & _0105_) | _0135_);
assign _0137_ = _0136_ & _0134_;
assign _0138_ = E ^ C;
assign _0139_ = _0138_ ^ H;
assign _0140_ = _0139_ ^ K;
assign _0141_ = _0140_ & L;
assign _0143_ = _0138_ & H;
assign _0144_ = _0139_ & K;
assign _0145_ = _0144_ | _0143_;
assign _0146_ = E ^ D;
assign _0147_ = C ? _0008_ : _0146_;
assign _0148_ = _0147_ ^ G;
assign _0149_ = _0148_ ^ _0145_;
assign _0150_ = _0149_ & _0141_;
assign _0151_ = _0150_ | _0527_;
assign _0152_ = _0148_ & _0143_;
assign _0154_ = ~G;
assign _0155_ = _0147_ | _0154_;
assign _0156_ = D & C;
assign _0157_ = _0156_ ^ A;
assign _0158_ = ~((D | C) & E);
assign _0159_ = ~(_0158_ ^ _0157_);
assign _0160_ = _0159_ ^ _0274_;
assign _0161_ = _0160_ ^ _0155_;
assign _0162_ = _0161_ ^ _0152_;
assign _0163_ = _0162_ ^ I;
assign _0165_ = ~K;
assign _0166_ = ~((_0148_ & _0139_) | _0165_);
assign _0167_ = _0166_ ^ _0163_;
assign _0168_ = _0167_ ^ _0151_;
assign _0169_ = _0149_ ^ _0141_;
assign _0170_ = ~(_0169_ | _0142_);
assign _0171_ = _0169_ ^ _0142_;
assign _0172_ = ~((_0171_ & O) | _0170_);
assign _0173_ = _0172_ ^ _0168_;
assign _0174_ = _0173_ ^ _0131_;
assign _0176_ = _0140_ ^ L;
assign _0177_ = ~O;
assign _0178_ = _0171_ ^ _0177_;
assign _0179_ = ~(_0178_ | _0176_);
assign _0180_ = _0179_ & Q;
assign _0181_ = _0180_ ^ _0174_;
assign _0182_ = ~(_0176_ | _0120_);
assign _0183_ = ~(_0182_ ^ _0178_);
assign _0184_ = ~(_0183_ | _0635_);
assign _0185_ = _0176_ ^ _0120_;
assign _0187_ = ~(_0185_ | _0042_);
assign _0188_ = _0183_ ^ _0635_;
assign _0189_ = _0188_ & _0187_;
assign _0190_ = ~(_0189_ | _0184_);
assign _0191_ = _0190_ ^ _0181_;
assign _0192_ = _0188_ ^ _0187_;
assign _0193_ = ~((_0192_ | _0191_) & T);
assign _0194_ = ~((_0174_ & _0179_) | _0120_);
assign _0195_ = ~(_0173_ | _0131_);
assign _0196_ = ~((_0168_ & _0171_) | _0177_);
assign _0198_ = ~(_0167_ | _0151_);
assign _0199_ = ~((_0163_ & K) | (_0148_ & _0144_));
assign _0200_ = ~_0147_;
assign _0201_ = _0160_ & _0200_;
assign _0202_ = _0201_ | _0154_;
assign _0203_ = _0159_ | _0274_;
assign _0204_ = ~_0158_;
assign _0205_ = _0204_ & _0157_;
assign _0206_ = ~C;
assign _0207_ = ~(_0604_ | _0206_);
assign _0209_ = _0207_ ^ _0005_;
assign _0210_ = _0209_ ^ _0593_;
assign _0211_ = _0210_ ^ _0205_;
assign _0212_ = _0211_ ^ _0203_;
assign _0213_ = _0212_ ^ _0202_;
assign _0214_ = _0161_ & _0152_;
assign _0215_ = ~((_0162_ & I) | _0214_);
assign _0216_ = _0215_ ^ _0213_;
assign _0217_ = ~(_0216_ ^ _0199_);
assign _0218_ = _0217_ ^ _0198_;
assign _0220_ = _0218_ ^ M;
assign _0221_ = _0168_ & _0170_;
assign _0222_ = ~(_0221_ ^ _0220_);
assign _0223_ = _0222_ ^ _0196_;
assign _0224_ = _0223_ ^ _0195_;
assign _0225_ = _0224_ ^ _0194_;
assign _0226_ = _0225_ ^ R;
assign _0227_ = _0190_ | _0181_;
assign _0228_ = _0227_ ^ _0226_;
assign _0229_ = ~(_0228_ | _0193_);
assign _0231_ = ~_0189_;
assign _0232_ = ~(_0181_ | _0231_);
assign _0233_ = _0232_ & _0226_;
assign _0234_ = ~(_0225_ & R);
assign _0235_ = ~_0184_;
assign _0236_ = ~((_0181_ | _0235_) & _0234_);
assign _0237_ = _0223_ | _0173_;
assign _0238_ = _0237_ & P;
assign _0239_ = ~M;
assign _0240_ = ~(_0218_ | _0239_);
assign _0242_ = ~(_0166_ ^ _0163_);
assign _0243_ = ~((_0217_ & _0242_) | _0527_);
assign _0244_ = _0243_ | _0150_;
assign _0245_ = ~(_0216_ | _0199_);
assign _0246_ = _0213_ & _0214_;
assign _0247_ = ~(_0212_ | _0202_);
assign _0248_ = ~(_0211_ | _0203_);
assign _0249_ = ~(_0204_ & _0157_);
assign _0250_ = _0209_ | _0593_;
assign _0251_ = _0209_ & _0593_;
assign _0252_ = ~((_0251_ | _0249_) & _0250_);
assign _0253_ = ~B;
assign _0254_ = ~(_0253_ | A);
assign _0255_ = ~((_0253_ & A) | C);
assign _0256_ = _0255_ | _0254_;
assign _0257_ = _0156_ | _0604_;
assign _0258_ = ~((_0257_ & _0253_) | (_0256_ & _0008_));
assign _0259_ = _0258_ ^ E;
assign _0260_ = _0259_ ^ _0252_;
assign _0261_ = _0260_ ^ _0248_;
assign _0264_ = _0261_ ^ _0247_;
assign _0265_ = ~(_0264_ ^ _0246_);
assign _0266_ = ~(_0213_ & _0162_);
assign _0267_ = ~(_0266_ & I);
assign _0268_ = _0267_ ^ _0265_;
assign _0269_ = _0268_ ^ _0245_;
assign _0270_ = _0269_ ^ _0244_;
assign _0271_ = _0270_ ^ _0240_;
assign _0272_ = ~_0168_;
assign _0273_ = ~(_0272_ | _0169_);
assign _0275_ = ~((_0273_ & _0220_) | _0142_);
assign _0276_ = _0275_ ^ _0271_;
assign _0277_ = _0222_ & _0196_;
assign _0278_ = ~(_0277_ | _0177_);
assign _0279_ = _0278_ ^ _0276_;
assign _0280_ = ~(_0279_ ^ _0238_);
assign _0281_ = ~(_0224_ & _0194_);
assign _0282_ = _0281_ & Q;
assign _0283_ = ~(_0282_ ^ _0280_);
assign _0284_ = _0283_ ^ R;
assign _0286_ = _0284_ ^ _0236_;
assign _0287_ = _0286_ ^ _0233_;
assign _0288_ = ~((_0287_ & T) | _0229_);
assign _0289_ = ~(_0286_ & _0233_);
assign _0290_ = ~(_0283_ & R);
assign _0291_ = ~(_0284_ & _0236_);
assign _0292_ = _0291_ & _0290_;
assign _0293_ = ~((_0280_ | _0120_) & _0281_);
assign _0294_ = _0279_ & _0238_;
assign _0295_ = ~((_0276_ & O) | _0277_);
assign _0297_ = _0275_ & _0271_;
assign _0298_ = _0270_ & _0240_;
assign _0299_ = _0269_ & _0244_;
assign _0300_ = _0268_ & _0245_;
assign _0301_ = ~((_0266_ & _0265_) | _0153_);
assign _0302_ = _0204_ | _0157_;
assign _0303_ = ~(_0210_ | _0302_);
assign _0304_ = _0210_ & _0205_;
assign _0305_ = _0304_ | _0274_;
assign _0306_ = ~(_0260_ & F);
assign _0308_ = ~((_0305_ | _0303_) & _0306_);
assign _0309_ = ~(_0258_ & E);
assign _0310_ = _0309_ & _0250_;
assign _0311_ = _0156_ & A;
assign _0312_ = ~_0311_;
assign _0313_ = ~(_0256_ | _0008_);
assign _0314_ = ~(B | A);
assign _0315_ = ~_0314_;
assign _0316_ = _0009_ | C;
assign _0317_ = _0316_ & _0315_;
assign _0319_ = ~((_0317_ | _0313_) & _0312_);
assign _0320_ = ~((_0319_ & _0310_) | _0205_);
assign _0321_ = ~(_0320_ ^ _0308_);
assign _0322_ = ~(_0261_ & _0247_);
assign _0323_ = ~(_0264_ & _0246_);
assign _0324_ = _0323_ & _0322_;
assign _0325_ = _0324_ ^ _0321_;
assign _0326_ = _0325_ ^ _0301_;
assign _0327_ = _0326_ ^ _0300_;
assign _0328_ = _0327_ ^ _0299_;
assign _0329_ = _0328_ ^ _0298_;
assign _0330_ = ~(_0329_ ^ _0297_);
assign _0331_ = _0330_ ^ _0295_;
assign _0332_ = _0331_ ^ _0294_;
assign _0333_ = ~(_0332_ ^ _0293_);
assign _0334_ = ~(_0333_ ^ _0292_);
assign _0335_ = _0334_ | _0289_;
assign _0336_ = ~(_0334_ ^ _0289_);
assign _0337_ = ~((_0336_ | _0288_) & _0335_);
assign _0338_ = ~_0229_;
assign _0341_ = _0336_ & _0338_;
assign _0342_ = _0287_ | T;
assign _0343_ = ~_0191_;
assign _0344_ = _0192_ | _0092_;
assign _0345_ = _0344_ & _0343_;
assign _0346_ = _0192_ & _0092_;
assign _0347_ = _0185_ & _0042_;
assign _0348_ = ~((_0347_ | _0187_) & _0344_);
assign _0349_ = ~((_0348_ | _0346_) & (_0344_ | _0343_));
assign _0350_ = _0349_ | _0345_;
assign _0352_ = ~((_0228_ & _0193_) | _0350_);
assign _0353_ = _0352_ & _0342_;
assign _0354_ = ~(_0353_ & _0288_);
assign _0355_ = _0005_ ^ J;
assign _0356_ = _0355_ ^ _0165_;
assign _0357_ = _0356_ & M;
assign _0358_ = _0355_ | _0165_;
assign _0359_ = J ? _0009_ : _0314_;
assign _0360_ = _0359_ ^ _0358_;
assign _0361_ = _0360_ ^ L;
assign _0363_ = _0361_ ^ _0357_;
assign _0364_ = _0356_ ^ M;
assign _0365_ = _0364_ | _0177_;
assign _0366_ = _0365_ ^ _0363_;
assign _0367_ = ~(_0366_ | _0131_);
assign _0368_ = ~((_0364_ | _0363_) & O);
assign _0369_ = _0361_ & _0357_;
assign _0370_ = _0009_ ^ _0206_;
assign _0371_ = _0370_ ^ _0008_;
assign _0372_ = _0371_ ^ G;
assign _0374_ = _0372_ ^ H;
assign _0375_ = _0374_ ^ _0153_;
assign _0376_ = _0314_ & J;
assign _0377_ = _0376_ ^ _0375_;
assign _0378_ = _0377_ ^ _0165_;
assign _0379_ = _0359_ | _0358_;
assign _0380_ = _0360_ & L;
assign _0381_ = ~_0380_;
assign _0382_ = ~(_0381_ & _0379_);
assign _0383_ = _0382_ ^ _0378_;
assign _0384_ = _0383_ ^ _0369_;
assign _0385_ = _0384_ ^ _0142_;
assign _0386_ = _0385_ ^ _0368_;
assign _0387_ = ~(_0386_ ^ _0367_);
assign _0388_ = _0366_ ^ _0131_;
assign _0389_ = ~(_0388_ | _0120_);
assign _0390_ = _0389_ ^ _0387_;
assign _0391_ = _0385_ | _0368_;
assign _0392_ = ~(_0386_ & _0367_);
assign _0393_ = _0392_ & _0391_;
assign _0396_ = _0384_ | _0142_;
assign _0397_ = ~(_0383_ & _0369_);
assign _0398_ = _0378_ & _0380_;
assign _0399_ = ~((_0377_ | _0165_) & _0379_);
assign _0400_ = ~(_0376_ & _0375_);
assign _0401_ = _0374_ | _0153_;
assign _0402_ = ~(_0370_ | _0008_);
assign _0403_ = ~((_0009_ & _0206_) | _0314_);
assign _0404_ = _0403_ ^ _0402_;
assign _0405_ = _0404_ ^ F;
assign _0407_ = _0371_ & G;
assign _0408_ = ~((_0372_ & H) | _0407_);
assign _0409_ = ~(_0408_ ^ _0405_);
assign _0410_ = _0409_ ^ _0401_;
assign _0411_ = _0410_ ^ _0400_;
assign _0412_ = _0411_ ^ _0399_;
assign _0413_ = _0412_ ^ _0398_;
assign _0414_ = _0413_ ^ _0239_;
assign _0415_ = _0414_ ^ _0397_;
assign _0416_ = _0415_ ^ _0396_;
assign _0418_ = _0416_ ^ _0393_;
assign _0419_ = ~_0418_;
assign _0420_ = ~((_0419_ & _0390_) | _0635_);
assign _0421_ = ~_0388_;
assign _0422_ = ~(_0421_ & _0387_);
assign _0423_ = ~(_0418_ | _0422_);
assign _0424_ = ~(_0423_ & Q);
assign _0425_ = _0416_ | _0392_;
assign _0426_ = ~(_0416_ | _0391_);
assign _0427_ = ~(_0415_ | _0396_);
assign _0429_ = ~(_0413_ & M);
assign _0430_ = ~((_0414_ | _0397_) & _0429_);
assign _0431_ = _0412_ & _0398_;
assign _0432_ = _0411_ & _0399_;
assign _0433_ = _0405_ & _0407_;
assign _0434_ = _0404_ | _0274_;
assign _0435_ = ~_0156_;
assign _0436_ = ~((_0435_ | _0009_) & _0315_);
assign _0437_ = _0436_ ^ _0434_;
assign _0438_ = ~(_0437_ ^ _0433_);
assign _0440_ = _0372_ & H;
assign _0441_ = ~(_0405_ & _0440_);
assign _0442_ = ~(_0441_ & H);
assign _0443_ = _0442_ ^ _0438_;
assign _0444_ = _0409_ | _0374_;
assign _0445_ = _0444_ & I;
assign _0446_ = _0445_ ^ _0443_;
assign _0447_ = ~(_0409_ | _0315_);
assign _0448_ = ~((_0447_ & _0375_) | _0636_);
assign _0449_ = _0448_ ^ _0446_;
assign _0451_ = _0449_ ^ _0432_;
assign _0452_ = _0451_ ^ _0431_;
assign _0453_ = _0452_ ^ _0430_;
assign _0454_ = _0453_ ^ _0427_;
assign _0455_ = _0454_ ^ O;
assign _0456_ = _0455_ ^ _0426_;
assign _0457_ = _0456_ ^ P;
assign _0458_ = _0457_ ^ _0425_;
assign _0459_ = _0458_ ^ _0424_;
assign _0460_ = _0459_ & _0420_;
assign _0462_ = ~(_0456_ & P);
assign _0463_ = ~(_0456_ | P);
assign _0464_ = ~((_0463_ | _0425_) & _0462_);
assign _0465_ = _0454_ & O;
assign _0466_ = _0455_ & _0426_;
assign _0467_ = _0466_ | _0465_;
assign _0468_ = ~(_0383_ | _0369_);
assign _0469_ = _0414_ & _0468_;
assign _0470_ = ~((_0414_ | _0397_) & N);
assign _0471_ = ~(_0453_ & N);
assign _0473_ = ~((_0470_ | _0469_) & _0471_);
assign _0474_ = _0452_ & _0430_;
assign _0475_ = _0449_ & _0432_;
assign _0476_ = ~_0475_;
assign _0477_ = _0445_ & _0443_;
assign _0478_ = ~((_0438_ | _0318_) & _0441_);
assign _0479_ = _0437_ & _0433_;
assign _0480_ = ~_0404_;
assign _0481_ = ~((_0436_ & _0480_) | _0274_);
assign _0482_ = _0156_ | _0009_;
assign _0484_ = _0482_ & _0315_;
assign _0485_ = _0484_ ^ _0481_;
assign _0486_ = _0485_ ^ _0479_;
assign _0487_ = _0486_ ^ _0478_;
assign _0488_ = _0487_ ^ _0477_;
assign _0489_ = _0488_ & _0475_;
assign _0490_ = _0451_ & _0431_;
assign _0491_ = _0448_ & _0446_;
assign _0492_ = _0488_ ^ _0491_;
assign _0493_ = ~(_0492_ ^ _0490_);
assign _0495_ = ~((_0493_ & _0476_) | _0489_);
assign _0496_ = _0495_ ^ _0474_;
assign _0497_ = _0496_ ^ _0473_;
assign _0498_ = _0497_ ^ _0467_;
assign _0499_ = _0498_ ^ _0464_;
assign _0500_ = ~((_0458_ & _0423_) | _0120_);
assign _0501_ = _0500_ ^ _0499_;
assign _0502_ = _0501_ ^ _0460_;
assign _0503_ = ~(_0459_ ^ _0420_);
assign _0504_ = _0389_ & _0387_;
assign _0506_ = ~(_0418_ ^ _0504_);
assign _0507_ = _0390_ ^ R;
assign _0508_ = _0507_ & _0506_;
assign _0509_ = ~((_0508_ & _0503_) | _0042_);
assign _0510_ = _0509_ | _0502_;
assign _0511_ = _0390_ & R;
assign _0512_ = _0511_ ^ _0506_;
assign _0513_ = _0507_ & S;
assign _0514_ = ~(_0513_ | _0512_);
assign _0515_ = _0513_ & _0506_;
assign _0517_ = ~(_0515_ | _0514_);
assign _0518_ = _0517_ ^ _0092_;
assign _0519_ = _0507_ ^ S;
assign _0520_ = _0519_ ^ T;
assign _0521_ = _0388_ ^ Q;
assign _0522_ = _0364_ ^ _0177_;
assign _0523_ = ~(_0522_ | _0092_);
assign _0524_ = ~(_0523_ & _0521_);
assign _0525_ = ~(_0524_ | _0520_);
assign _0526_ = _0519_ | _0092_;
assign _0528_ = ~((_0512_ | _0092_) & _0526_);
assign _0529_ = ~((_0525_ & _0518_) | _0528_);
assign _0530_ = _0515_ ^ _0503_;
assign _0531_ = _0509_ & _0502_;
assign _0532_ = ~((_0530_ & _0529_) | _0531_);
assign _0533_ = _0532_ & _0510_;
assign _0534_ = ~(_0530_ | _0529_);
assign _0535_ = _0501_ & _0460_;
assign _0536_ = _0500_ & _0499_;
assign _0537_ = ~(_0498_ & _0464_);
assign _0539_ = ~(_0497_ & _0467_);
assign _0540_ = ~(_0496_ & _0473_);
assign _0541_ = _0495_ & _0474_;
assign _0542_ = _0492_ & _0490_;
assign _0543_ = ~(_0488_ & _0475_);
assign _0544_ = ~(_0486_ & _0478_);
assign _0545_ = _0484_ & _0481_;
assign _0546_ = ~((_0485_ & _0479_) | _0545_);
assign _0547_ = _0546_ & _0544_;
assign _0548_ = ~((_0491_ | _0477_) & _0487_);
assign _0550_ = ~(_0548_ ^ _0547_);
assign _0551_ = _0550_ ^ _0543_;
assign _0552_ = _0551_ ^ _0542_;
assign _0553_ = _0552_ ^ _0541_;
assign _0554_ = _0553_ ^ _0540_;
assign _0555_ = ~(_0554_ ^ _0539_);
assign _0556_ = _0555_ ^ _0537_;
assign _0557_ = _0556_ ^ _0536_;
assign _0558_ = _0557_ ^ _0535_;
assign _0559_ = _0517_ ^ T;
assign _0561_ = _0522_ & _0092_;
assign _0562_ = _0521_ ? _0523_ : _0561_;
assign _0563_ = _0562_ | _0520_;
assign _0564_ = ~((_0526_ & _0559_) | _0563_);
assign _0565_ = ~(_0564_ | _0534_);
assign _0566_ = ~((_0558_ & _0534_) | _0565_);
assign _0567_ = _0556_ & _0536_;
assign _0568_ = _0332_ & _0293_;
assign _0569_ = ~(_0329_ & _0297_);
assign _0570_ = ~((_0330_ | _0295_) & _0569_);
assign _0572_ = _0327_ & _0299_;
assign _0573_ = _0328_ & _0298_;
assign _0574_ = _0573_ | _0572_;
assign _0575_ = _0321_ | _0322_;
assign _0576_ = _0249_ & _0312_;
assign _0577_ = _0320_ & _0308_;
assign _0578_ = _0577_ ^ _0576_;
assign _0579_ = _0578_ & _0323_;
assign _0580_ = _0579_ & _0575_;
assign _0581_ = ~(_0325_ & _0301_);
assign _0583_ = ~(_0326_ & _0300_);
assign _0584_ = _0583_ & _0581_;
assign _0585_ = _0584_ ^ _0580_;
assign _0586_ = _0585_ ^ _0574_;
assign _0587_ = _0586_ & _0570_;
assign _0588_ = _0496_ & _0473_;
assign _0589_ = ~(_0552_ & _0588_);
assign _0590_ = _0550_ | _0543_;
assign _0591_ = ~(_0580_ | _0581_);
assign _0592_ = ~((_0577_ & _0311_) | _0591_);
assign _0594_ = _0592_ & _0590_;
assign _0595_ = ~((_0580_ | _0583_) & (_0548_ | _0547_));
assign _0596_ = ~((_0551_ & _0542_) | _0595_);
assign _0597_ = ~(_0596_ & _0594_);
assign _0598_ = ~((_0585_ & _0574_) | _0597_);
assign _0599_ = ~(_0598_ & _0589_);
assign _0600_ = _0599_ | _0587_;
assign _0601_ = _0600_ | _0568_;
assign _0602_ = _0331_ & _0294_;
assign _0603_ = _0586_ ^ _0570_;
assign _0605_ = _0603_ & _0602_;
assign _0606_ = ~(_0552_ & _0541_);
assign _0607_ = ~((_0554_ | _0539_) & _0606_);
assign _0608_ = _0607_ | _0605_;
assign _0609_ = _0608_ | _0601_;
assign _0610_ = ~((_0291_ & _0290_) | _0333_);
assign _0611_ = ~(_0603_ | _0602_);
assign _0612_ = ~((_0611_ | _0605_) & (_0555_ | _0537_));
assign _0613_ = _0612_ | _0610_;
assign _0614_ = _0613_ | _0609_;
assign _0616_ = _0614_ | _0567_;
assign _0617_ = _0558_ | _0531_;
assign _0618_ = _0617_ | _0616_;
assign _0619_ = ~((_0566_ & _0533_) | _0618_);
assign _0620_ = ~((_0354_ | _0341_) & _0619_);
assign _0621_ = _0620_ | _0337_;
assign valid = ~((_0137_ & _0127_) | _0621_);
endmodule | 5 |
138,113 | data/full_repos/permissive/81900704/output/vs/single.v | 81,900,704 | single.v | v | 25 | 77 | [] | [] | [] | [(2, 24)] | null | data/verilator_xmls/a4e7e548-1b10-427d-b237-b2aba5d36ec3.xml | null | 301,817 | module | module single (A, B, C, D, E, valid);
input A, B, C, D, E;
output valid;
wire [4:0] min_value = 5'd15;
wire [4:0] max_weight = 5'd16;
wire [4:0] total_value =
A * 5'd4
+ B * 5'd2
+ C * 5'd2
+ D * 5'd1
+ E * 5'd10;
wire [4:0] total_weight =
A * 5'd12
+ B * 5'd1
+ C * 5'd2
+ D * 5'd1
+ E * 5'd4;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight));
endmodule | module single (A, B, C, D, E, valid); |
input A, B, C, D, E;
output valid;
wire [4:0] min_value = 5'd15;
wire [4:0] max_weight = 5'd16;
wire [4:0] total_value =
A * 5'd4
+ B * 5'd2
+ C * 5'd2
+ D * 5'd1
+ E * 5'd10;
wire [4:0] total_weight =
A * 5'd12
+ B * 5'd1
+ C * 5'd2
+ D * 5'd1
+ E * 5'd4;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight));
endmodule | 5 |
138,114 | data/full_repos/permissive/81900704/output/vs/var15_multi.v | 81,900,704 | var15_multi.v | v | 62 | 109 | [] | [] | [] | [(2, 61)] | null | data/verilator_xmls/83bc6bc7-2fa3-4893-ac97-7aee20d92a59.xml | null | 301,823 | module | module var15_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O;
output valid;
wire [7:0] min_value = 8'd120;
wire [7:0] max_weight = 8'd60;
wire [7:0] max_volume = 8'd60;
wire [7:0] total_value =
A * 8'd4
+ B * 8'd8
+ C * 8'd0
+ D * 8'd20
+ E * 8'd10
+ F * 8'd12
+ G * 8'd18
+ H * 8'd14
+ I * 8'd6
+ J * 8'd15
+ K * 8'd30
+ L * 8'd8
+ M * 8'd16
+ N * 8'd18
+ O * 8'd18;
wire [7:0] total_weight =
A * 8'd28
+ B * 8'd8
+ C * 8'd27
+ D * 8'd18
+ E * 8'd27
+ F * 8'd28
+ G * 8'd6
+ H * 8'd1
+ I * 8'd20
+ J * 8'd0
+ K * 8'd5
+ L * 8'd13
+ M * 8'd8
+ N * 8'd14
+ O * 8'd22;
wire [7:0] total_volume =
A * 8'd27
+ B * 8'd27
+ C * 8'd4
+ D * 8'd4
+ E * 8'd0
+ F * 8'd24
+ G * 8'd4
+ H * 8'd20
+ I * 8'd12
+ J * 8'd15
+ K * 8'd5
+ L * 8'd2
+ M * 8'd9
+ N * 8'd28
+ O * 8'd19;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | module var15_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, valid); |
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O;
output valid;
wire [7:0] min_value = 8'd120;
wire [7:0] max_weight = 8'd60;
wire [7:0] max_volume = 8'd60;
wire [7:0] total_value =
A * 8'd4
+ B * 8'd8
+ C * 8'd0
+ D * 8'd20
+ E * 8'd10
+ F * 8'd12
+ G * 8'd18
+ H * 8'd14
+ I * 8'd6
+ J * 8'd15
+ K * 8'd30
+ L * 8'd8
+ M * 8'd16
+ N * 8'd18
+ O * 8'd18;
wire [7:0] total_weight =
A * 8'd28
+ B * 8'd8
+ C * 8'd27
+ D * 8'd18
+ E * 8'd27
+ F * 8'd28
+ G * 8'd6
+ H * 8'd1
+ I * 8'd20
+ J * 8'd0
+ K * 8'd5
+ L * 8'd13
+ M * 8'd8
+ N * 8'd14
+ O * 8'd22;
wire [7:0] total_volume =
A * 8'd27
+ B * 8'd27
+ C * 8'd4
+ D * 8'd4
+ E * 8'd0
+ F * 8'd24
+ G * 8'd4
+ H * 8'd20
+ I * 8'd12
+ J * 8'd15
+ K * 8'd5
+ L * 8'd2
+ M * 8'd9
+ N * 8'd28
+ O * 8'd19;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | 5 |
138,115 | data/full_repos/permissive/81900704/output/vs/var23_multi.v | 81,900,704 | var23_multi.v | v | 86 | 109 | [] | [] | [] | [(2, 85)] | null | data/verilator_xmls/81b4a8f3-0282-4de9-844c-e57366917260.xml | null | 301,831 | module | module var23_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | module var23_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, valid); |
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule | 5 |
138,120 | data/full_repos/permissive/82098390/ctrl_fsm/source/tb/verilog/tb_ctrl_fsm.v | 82,098,390 | tb_ctrl_fsm.v | v | 110 | 95 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/82098390/ctrl_fsm/source/tb/verilog/tb_ctrl_fsm.v:107: Cannot find include file: testcase.v\n `include "testcase.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82098390/ctrl_fsm/source/tb/verilog,data/full_repos/permissive/82098390/testcase.v\n data/full_repos/permissive/82098390/ctrl_fsm/source/tb/verilog,data/full_repos/permissive/82098390/testcase.v.v\n data/full_repos/permissive/82098390/ctrl_fsm/source/tb/verilog,data/full_repos/permissive/82098390/testcase.v.sv\n testcase.v\n testcase.v.v\n testcase.v.sv\n obj_dir/testcase.v\n obj_dir/testcase.v.v\n obj_dir/testcase.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/82098390/ctrl_fsm/source/tb/verilog/tb_ctrl_fsm.v:95: Unsupported: Ignoring delay on this delayed statement.\n always #(CLKPERIODE/2) clk_i = !clk_i;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82098390/ctrl_fsm/source/tb/verilog/tb_ctrl_fsm.v:100: Unsupported: Ignoring delay on this delayed statement.\n #33\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 301,841 | module | module tb_ctrl_fsm (
);
parameter INSTR_WIDTH = 16;
parameter ADDR_WIDTH_OP = 4;
parameter ADDR_WIDTH_PC = 12;
parameter OPCODE_LGNT = 8;
parameter JMPR_OPCODE = 4;
parameter SEG_REG_WIDTH = 4;
reg clk_i;
reg a_reset_l;
reg [INSTR_WIDTH-1:0] out_data_pram_i;
reg intr_h_i;
reg ovr_i;
reg valid_i;
reg wb_ack_i;
reg [INSTR_WIDTH-1:0] data_b_bus_i;
reg [INSTR_WIDTH-1:0] data_wb_bus_i;
reg mask_i;
reg sync_h_i;
reg alu_valid_i;
wire [OPCODE_LGNT-1:0] alu_op_o;
wire wb_we_o;
wire wb_start_o;
wire regfile_we_o;
wire [ADDR_WIDTH_OP-1:0] adr_a_o;
wire [ADDR_WIDTH_OP-1:0] adr_b_o;
wire seg_reg_we_o;
wire [SEG_REG_WIDTH-1:0] seg_reg_o;
wire adr_ld_o;
wire [ADDR_WIDTH_PC-1:0] adr_pc_o;
wire init_mode_o;
wire [1:0] alu_mux_o;
wire [1:0] sp_mux_o;
wire [1:0] data_mux_o;
wire inc_o;
ctrl_fsm ctrl_fsm_i (
.clk_i (clk_i ),
.a_reset_l (a_reset_l ),
.out_data_pram_i(out_data_pram_i),
.intr_h_i (intr_h_i ),
.ovr_i (ovr_i ),
.valid_i (valid_i ),
.wb_ack_i (wb_ack_i ),
.data_b_bus_i (data_b_bus_i ),
.data_wb_bus_i (data_wb_bus_i ),
.mask_i (mask_i ),
.sync_h_i (sync_h_i ),
.alu_valid_i (alu_valid_i ),
.alu_op_o (alu_op_o ),
.wb_we_o (wb_we_o ),
.wb_start_o (wb_start_o ),
.regfile_we_o (regfile_we_o ),
.adr_a_o (adr_a_o ),
.adr_b_o (adr_b_o ),
.seg_reg_we_o (seg_reg_we_o ),
.seg_reg_o (seg_reg_o ),
.adr_ld_o (adr_ld_o ),
.adr_pc_o (adr_pc_o ),
.init_mode_o (init_mode_o ),
.alu_mux_o (alu_mux_o ),
.sp_mux_o (sp_mux_o ),
.data_mux_o (data_mux_o ),
.inc_o (inc_o )
);
parameter CLKPERIODE = 100;
initial clk_i = 1'b0;
always #(CLKPERIODE/2) clk_i = !clk_i;
initial begin
a_reset_l = 1'b0;
#33
a_reset_l = 1'b1;
end
`include "testcase.v"
endmodule | module tb_ctrl_fsm (
); |
parameter INSTR_WIDTH = 16;
parameter ADDR_WIDTH_OP = 4;
parameter ADDR_WIDTH_PC = 12;
parameter OPCODE_LGNT = 8;
parameter JMPR_OPCODE = 4;
parameter SEG_REG_WIDTH = 4;
reg clk_i;
reg a_reset_l;
reg [INSTR_WIDTH-1:0] out_data_pram_i;
reg intr_h_i;
reg ovr_i;
reg valid_i;
reg wb_ack_i;
reg [INSTR_WIDTH-1:0] data_b_bus_i;
reg [INSTR_WIDTH-1:0] data_wb_bus_i;
reg mask_i;
reg sync_h_i;
reg alu_valid_i;
wire [OPCODE_LGNT-1:0] alu_op_o;
wire wb_we_o;
wire wb_start_o;
wire regfile_we_o;
wire [ADDR_WIDTH_OP-1:0] adr_a_o;
wire [ADDR_WIDTH_OP-1:0] adr_b_o;
wire seg_reg_we_o;
wire [SEG_REG_WIDTH-1:0] seg_reg_o;
wire adr_ld_o;
wire [ADDR_WIDTH_PC-1:0] adr_pc_o;
wire init_mode_o;
wire [1:0] alu_mux_o;
wire [1:0] sp_mux_o;
wire [1:0] data_mux_o;
wire inc_o;
ctrl_fsm ctrl_fsm_i (
.clk_i (clk_i ),
.a_reset_l (a_reset_l ),
.out_data_pram_i(out_data_pram_i),
.intr_h_i (intr_h_i ),
.ovr_i (ovr_i ),
.valid_i (valid_i ),
.wb_ack_i (wb_ack_i ),
.data_b_bus_i (data_b_bus_i ),
.data_wb_bus_i (data_wb_bus_i ),
.mask_i (mask_i ),
.sync_h_i (sync_h_i ),
.alu_valid_i (alu_valid_i ),
.alu_op_o (alu_op_o ),
.wb_we_o (wb_we_o ),
.wb_start_o (wb_start_o ),
.regfile_we_o (regfile_we_o ),
.adr_a_o (adr_a_o ),
.adr_b_o (adr_b_o ),
.seg_reg_we_o (seg_reg_we_o ),
.seg_reg_o (seg_reg_o ),
.adr_ld_o (adr_ld_o ),
.adr_pc_o (adr_pc_o ),
.init_mode_o (init_mode_o ),
.alu_mux_o (alu_mux_o ),
.sp_mux_o (sp_mux_o ),
.data_mux_o (data_mux_o ),
.inc_o (inc_o )
);
parameter CLKPERIODE = 100;
initial clk_i = 1'b0;
always #(CLKPERIODE/2) clk_i = !clk_i;
initial begin
a_reset_l = 1'b0;
#33
a_reset_l = 1'b1;
end
`include "testcase.v"
endmodule | 4 |
138,122 | data/full_repos/permissive/82098390/flag_reg/source/rtl/verilog/flag_reg.v | 82,098,390 | flag_reg.v | v | 65 | 79 | [] | [] | [] | [(15, 63)] | null | data/verilator_xmls/629ea1df-ab4e-4109-b852-f048b0ac6b02.xml | null | 301,843 | module | module flag_reg (
clk,
a_reset_l,
ce,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out
);
input clk;
input a_reset_l;
input ce;
input z_flag_in;
input s_flag_in;
input c_flag_in;
input ovr_flag_in;
output z_flag_out;
output s_flag_out;
output c_flag_out;
output ovr_flag_out;
reg z_flag_out;
reg s_flag_out;
reg c_flag_out;
reg ovr_flag_out;
always @(posedge clk or negedge a_reset_l)
begin
if (a_reset_l == 1'b0)
begin
z_flag_out = 1'b0;
s_flag_out = 1'b0;
c_flag_out = 1'b0;
ovr_flag_out = 1'b0;
end
else if (ce == 1'b1)
begin
z_flag_out = z_flag_in;
s_flag_out = s_flag_in;
c_flag_out = c_flag_in;
ovr_flag_out = ovr_flag_in;
end
end
endmodule | module flag_reg (
clk,
a_reset_l,
ce,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out
); |
input clk;
input a_reset_l;
input ce;
input z_flag_in;
input s_flag_in;
input c_flag_in;
input ovr_flag_in;
output z_flag_out;
output s_flag_out;
output c_flag_out;
output ovr_flag_out;
reg z_flag_out;
reg s_flag_out;
reg c_flag_out;
reg ovr_flag_out;
always @(posedge clk or negedge a_reset_l)
begin
if (a_reset_l == 1'b0)
begin
z_flag_out = 1'b0;
s_flag_out = 1'b0;
c_flag_out = 1'b0;
ovr_flag_out = 1'b0;
end
else if (ce == 1'b1)
begin
z_flag_out = z_flag_in;
s_flag_out = s_flag_in;
c_flag_out = c_flag_in;
ovr_flag_out = ovr_flag_in;
end
end
endmodule | 4 |
138,123 | data/full_repos/permissive/82098390/mask_cndt/source/rtl/verilog/mask_cndt.v | 82,098,390 | mask_cndt.v | v | 145 | 79 | [] | [] | [] | [(15, 144)] | null | data/verilator_xmls/3c9fd68d-bb63-4ca8-8862-175f7e0d734c.xml | null | 301,844 | module | module mask_cndt #(
parameter INSTR_WIDTH = 16,
parameter JMPR_OPCODE = 4
)(
input wire [INSTR_WIDTH-1:0] out_data_pram_i,
input wire z_flag_i,
input wire s_flag_i,
input wire c_flag_i,
input wire ovr_flag_i,
output wire mask_o
);
localparam [3:0]
TRUE = 4'b0000,
LE = 4'b0001,
C = 4'b0010,
OVR = 4'b0011,
NEG = 4'b0100,
Z = 4'b0101,
POS = 4'b0110,
GE = 4'b0111,
FALSE = 4'b1000,
GT = 4'b1001,
NC = 4'b1010,
NOVR = 4'b1011,
NNEG = 4'b1100,
NZ = 4'b1101,
NPOS = 4'b1110,
LT = 4'b1111;
reg [JMPR_OPCODE-1:0] jmpr_opcd;
reg mask_reg;
always @(*)
begin
jmpr_opcd = out_data_pram_i[3:0];
case(jmpr_opcd)
TRUE:
begin
mask_reg = 1'b1;
end
LE:
begin
mask_reg = z_flag_i | (ovr_flag_i ^ s_flag_i);
end
C:
begin
mask_reg = c_flag_i;
end
OVR:
begin
mask_reg = ovr_flag_i;
end
NEG:
begin
mask_reg = s_flag_i;
end
Z:
begin
mask_reg = z_flag_i;
end
POS:
begin
mask_reg = ~(s_flag_i | z_flag_i);
end
GE:
begin
mask_reg = ~(ovr_flag_i ^ s_flag_i);
end
FALSE:
begin
mask_reg = 1'b0;
end
GT:
begin
mask_reg = ~(z_flag_i|(ovr_flag_i^s_flag_i));
end
NC:
begin
mask_reg = ~c_flag_i;
end
NOVR:
begin
mask_reg = ~ovr_flag_i;
end
NNEG:
begin
mask_reg = ~s_flag_i;
end
NZ:
begin
mask_reg = ~z_flag_i;
end
NPOS:
begin
mask_reg = s_flag_i | z_flag_i;
end
LT:
begin
mask_reg = ovr_flag_i ^ s_flag_i;
end
default:
begin
end
endcase
end
assign mask_o = mask_reg;
endmodule | module mask_cndt #(
parameter INSTR_WIDTH = 16,
parameter JMPR_OPCODE = 4
)(
input wire [INSTR_WIDTH-1:0] out_data_pram_i,
input wire z_flag_i,
input wire s_flag_i,
input wire c_flag_i,
input wire ovr_flag_i,
output wire mask_o
); |
localparam [3:0]
TRUE = 4'b0000,
LE = 4'b0001,
C = 4'b0010,
OVR = 4'b0011,
NEG = 4'b0100,
Z = 4'b0101,
POS = 4'b0110,
GE = 4'b0111,
FALSE = 4'b1000,
GT = 4'b1001,
NC = 4'b1010,
NOVR = 4'b1011,
NNEG = 4'b1100,
NZ = 4'b1101,
NPOS = 4'b1110,
LT = 4'b1111;
reg [JMPR_OPCODE-1:0] jmpr_opcd;
reg mask_reg;
always @(*)
begin
jmpr_opcd = out_data_pram_i[3:0];
case(jmpr_opcd)
TRUE:
begin
mask_reg = 1'b1;
end
LE:
begin
mask_reg = z_flag_i | (ovr_flag_i ^ s_flag_i);
end
C:
begin
mask_reg = c_flag_i;
end
OVR:
begin
mask_reg = ovr_flag_i;
end
NEG:
begin
mask_reg = s_flag_i;
end
Z:
begin
mask_reg = z_flag_i;
end
POS:
begin
mask_reg = ~(s_flag_i | z_flag_i);
end
GE:
begin
mask_reg = ~(ovr_flag_i ^ s_flag_i);
end
FALSE:
begin
mask_reg = 1'b0;
end
GT:
begin
mask_reg = ~(z_flag_i|(ovr_flag_i^s_flag_i));
end
NC:
begin
mask_reg = ~c_flag_i;
end
NOVR:
begin
mask_reg = ~ovr_flag_i;
end
NNEG:
begin
mask_reg = ~s_flag_i;
end
NZ:
begin
mask_reg = ~z_flag_i;
end
NPOS:
begin
mask_reg = s_flag_i | z_flag_i;
end
LT:
begin
mask_reg = ovr_flag_i ^ s_flag_i;
end
default:
begin
end
endcase
end
assign mask_o = mask_reg;
endmodule | 4 |
138,125 | data/full_repos/permissive/82098390/pram_adr_cnt/source/rtl/verilog/pram_adr_cnt.v | 82,098,390 | pram_adr_cnt.v | v | 169 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/17d97eab-bfd9-4888-85fd-32c47ddf3bea.xml | null | 301,847 | module | module pram_adr_cnt (
clk,
a_reset_l,
adr_in,
adr_ld_in,
inc_in,
init_mode_in,
init_ack_in,
data_in1,
data_in2,
adr_out,
we_out,
start_out,
ovr_out
);
parameter data_wl = 16;
parameter adr_wl = 12;
input clk;
input a_reset_l;
input [adr_wl-1:0] adr_in;
input adr_ld_in;
input inc_in;
input init_mode_in;
input init_ack_in;
input [data_wl-1:0] data_in1;
input [data_wl-1:0] data_in2;
output [adr_wl-1:0] adr_out;
output we_out;
output ovr_out;
output start_out;
reg [adr_wl-1:0] adr_out_reg, nxt_adr_out;
reg ovr_out_reg, nxt_ovr_out;
reg we_out_reg, nxt_we_out;
reg start_out_reg, nxt_start_out;
localparam [4:0]
RUN = 5'b00001,
INIT = 5'b00010,
WAIT = 5'b00100,
ADR = 5'b01000;
reg [4:0] current_state, nxt_state;
always @(posedge clk or negedge a_reset_l)
begin
if (a_reset_l == 1'b0)
begin
current_state <= RUN;
adr_out_reg <= 'b0;
ovr_out_reg <= 'b0;
we_out_reg <= 'b0;
start_out_reg <= 'b0;
end
else
begin
current_state <= nxt_state;
adr_out_reg <= nxt_adr_out;
ovr_out_reg <= nxt_ovr_out;
we_out_reg <= nxt_we_out;
start_out_reg <= nxt_start_out;
end
end
always @(*)
begin
nxt_state = current_state;
nxt_adr_out = adr_out_reg;
nxt_ovr_out = ovr_out_reg;
nxt_we_out = we_out_reg;
nxt_start_out = start_out_reg;
case(current_state)
RUN:
begin
if (adr_ld_in == 1'b1)
nxt_adr_out = adr_in + 1;
else if (inc_in == 1'b1)
nxt_adr_out = nxt_adr_out + 1;
else
nxt_adr_out = nxt_adr_out;
if(init_mode_in == 1'b1)
begin
nxt_state = INIT;
nxt_adr_out = 'b0;
nxt_we_out = 1'b0;
nxt_start_out = 1'b1;
end
else
nxt_state = RUN;
end
INIT:
begin
nxt_start_out = 1'b0;
if(init_ack_in == 1'b1)
begin
nxt_we_out = 1'b1;
nxt_state = WAIT;
end
else
begin
nxt_we_out = 1'b0;
nxt_state = INIT;
end
end
WAIT:
begin
nxt_start_out = 1'b0;
if(data_in1 == data_in2 && init_ack_in == 1'b1)
begin
nxt_state = ADR;
nxt_we_out = 1'b0;
end
else
begin
nxt_we_out = 1'b1;
nxt_state = WAIT;
end
end
ADR:
begin
nxt_we_out = 1'b0;
nxt_adr_out = nxt_adr_out + 1;
if(data_in1 == 16'bxxxx || nxt_adr_out == 12'h050 )
begin
nxt_state = RUN;
nxt_ovr_out = 1'b1;
nxt_adr_out = 12'b0;
end
else
begin
nxt_ovr_out = 1'b0;
nxt_state = INIT;
nxt_start_out = 1'b1;
end
end
default:
begin
end
endcase
end
assign adr_out = (adr_ld_in==1'b0)? adr_out_reg : adr_in;
assign ovr_out = ovr_out_reg;
assign start_out = start_out_reg;
assign we_out = we_out_reg;
endmodule | module pram_adr_cnt (
clk,
a_reset_l,
adr_in,
adr_ld_in,
inc_in,
init_mode_in,
init_ack_in,
data_in1,
data_in2,
adr_out,
we_out,
start_out,
ovr_out
); |
parameter data_wl = 16;
parameter adr_wl = 12;
input clk;
input a_reset_l;
input [adr_wl-1:0] adr_in;
input adr_ld_in;
input inc_in;
input init_mode_in;
input init_ack_in;
input [data_wl-1:0] data_in1;
input [data_wl-1:0] data_in2;
output [adr_wl-1:0] adr_out;
output we_out;
output ovr_out;
output start_out;
reg [adr_wl-1:0] adr_out_reg, nxt_adr_out;
reg ovr_out_reg, nxt_ovr_out;
reg we_out_reg, nxt_we_out;
reg start_out_reg, nxt_start_out;
localparam [4:0]
RUN = 5'b00001,
INIT = 5'b00010,
WAIT = 5'b00100,
ADR = 5'b01000;
reg [4:0] current_state, nxt_state;
always @(posedge clk or negedge a_reset_l)
begin
if (a_reset_l == 1'b0)
begin
current_state <= RUN;
adr_out_reg <= 'b0;
ovr_out_reg <= 'b0;
we_out_reg <= 'b0;
start_out_reg <= 'b0;
end
else
begin
current_state <= nxt_state;
adr_out_reg <= nxt_adr_out;
ovr_out_reg <= nxt_ovr_out;
we_out_reg <= nxt_we_out;
start_out_reg <= nxt_start_out;
end
end
always @(*)
begin
nxt_state = current_state;
nxt_adr_out = adr_out_reg;
nxt_ovr_out = ovr_out_reg;
nxt_we_out = we_out_reg;
nxt_start_out = start_out_reg;
case(current_state)
RUN:
begin
if (adr_ld_in == 1'b1)
nxt_adr_out = adr_in + 1;
else if (inc_in == 1'b1)
nxt_adr_out = nxt_adr_out + 1;
else
nxt_adr_out = nxt_adr_out;
if(init_mode_in == 1'b1)
begin
nxt_state = INIT;
nxt_adr_out = 'b0;
nxt_we_out = 1'b0;
nxt_start_out = 1'b1;
end
else
nxt_state = RUN;
end
INIT:
begin
nxt_start_out = 1'b0;
if(init_ack_in == 1'b1)
begin
nxt_we_out = 1'b1;
nxt_state = WAIT;
end
else
begin
nxt_we_out = 1'b0;
nxt_state = INIT;
end
end
WAIT:
begin
nxt_start_out = 1'b0;
if(data_in1 == data_in2 && init_ack_in == 1'b1)
begin
nxt_state = ADR;
nxt_we_out = 1'b0;
end
else
begin
nxt_we_out = 1'b1;
nxt_state = WAIT;
end
end
ADR:
begin
nxt_we_out = 1'b0;
nxt_adr_out = nxt_adr_out + 1;
if(data_in1 == 16'bxxxx || nxt_adr_out == 12'h050 )
begin
nxt_state = RUN;
nxt_ovr_out = 1'b1;
nxt_adr_out = 12'b0;
end
else
begin
nxt_ovr_out = 1'b0;
nxt_state = INIT;
nxt_start_out = 1'b1;
end
end
default:
begin
end
endcase
end
assign adr_out = (adr_ld_in==1'b0)? adr_out_reg : adr_in;
assign ovr_out = ovr_out_reg;
assign start_out = start_out_reg;
assign we_out = we_out_reg;
endmodule | 4 |
138,127 | data/full_repos/permissive/82098390/ram_wb/source/rtl/verilog/ram_wb.v | 82,098,390 | ram_wb.v | v | 81 | 69 | [] | [] | [] | [(1, 78)] | null | null | 1: b"%Error: data/full_repos/permissive/82098390/ram_wb/source/rtl/verilog/ram_wb.v:47: Cannot find file containing module: 'ram'\n ram\n ^~~\n ... Looked in:\n data/full_repos/permissive/82098390/ram_wb/source/rtl/verilog,data/full_repos/permissive/82098390/ram\n data/full_repos/permissive/82098390/ram_wb/source/rtl/verilog,data/full_repos/permissive/82098390/ram.v\n data/full_repos/permissive/82098390/ram_wb/source/rtl/verilog,data/full_repos/permissive/82098390/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: Exiting due to 1 error(s)\n" | 301,849 | module | module ram_wb (
dat_i,
dat_o,
adr_i,
we_i,
sel_i,
cyc_i,
stb_i,
ack_o,
cti_i,
clk_i,
rst_i);
parameter INITFILE = "mem.txt";
parameter dat_width = 16;
parameter adr_width = 16;
parameter mem_size = 2**adr_width;
input [dat_width-1:0] dat_i;
output [dat_width-1:0] dat_o;
input [adr_width-1:0] adr_i;
input we_i;
input [3:0] sel_i;
input cyc_i;
input stb_i;
output reg ack_o;
input [2:0] cti_i;
input clk_i;
input rst_i;
wire [dat_width-1:0] wr_data;
reg nxt_we_i;
assign wr_data = dat_i;
ram
#(
.INITFILE("./mem.txt"),
.dat_width(dat_width),
.adr_width(adr_width),
.mem_size(mem_size)
)
ram_i
(
.dat_i(wr_data),
.dat_o(dat_o),
.adr_i(adr_i),
.we_i(nxt_we_i && ack_o),
.clk(clk_i)
);
always @ (posedge clk_i or posedge rst_i)
if (rst_i == 1'b0)
ack_o <= 1'b0;
else if (ack_o == 1'b0)
begin
if (cyc_i & stb_i)
ack_o <= 1'b1;
nxt_we_i <= we_i;
end
else
if ((sel_i != 4'b1111) | (cti_i == 3'b000) | (cti_i == 3'b111))
ack_o <= 1'b0;
endmodule | module ram_wb (
dat_i,
dat_o,
adr_i,
we_i,
sel_i,
cyc_i,
stb_i,
ack_o,
cti_i,
clk_i,
rst_i); |
parameter INITFILE = "mem.txt";
parameter dat_width = 16;
parameter adr_width = 16;
parameter mem_size = 2**adr_width;
input [dat_width-1:0] dat_i;
output [dat_width-1:0] dat_o;
input [adr_width-1:0] adr_i;
input we_i;
input [3:0] sel_i;
input cyc_i;
input stb_i;
output reg ack_o;
input [2:0] cti_i;
input clk_i;
input rst_i;
wire [dat_width-1:0] wr_data;
reg nxt_we_i;
assign wr_data = dat_i;
ram
#(
.INITFILE("./mem.txt"),
.dat_width(dat_width),
.adr_width(adr_width),
.mem_size(mem_size)
)
ram_i
(
.dat_i(wr_data),
.dat_o(dat_o),
.adr_i(adr_i),
.we_i(nxt_we_i && ack_o),
.clk(clk_i)
);
always @ (posedge clk_i or posedge rst_i)
if (rst_i == 1'b0)
ack_o <= 1'b0;
else if (ack_o == 1'b0)
begin
if (cyc_i & stb_i)
ack_o <= 1'b1;
nxt_we_i <= we_i;
end
else
if ((sel_i != 4'b1111) | (cti_i == 3'b000) | (cti_i == 3'b111))
ack_o <= 1'b0;
endmodule | 4 |
138,128 | data/full_repos/permissive/82098390/ram_wb/source/rtl/verilog/ram_wb_sc_sw.v | 82,098,390 | ram_wb_sc_sw.v | v | 33 | 83 | [] | [] | [] | [(1, 32)] | null | data/verilator_xmls/6bc5a9f5-f9dd-4595-a59a-afb28cb3d83e.xml | null | 301,850 | module | module ram (
dat_i,
dat_o,
adr_i,
we_i,
clk );
parameter INITFILE = "none";
parameter dat_width = 16;
parameter adr_width = 16;
parameter mem_size = 2**adr_width;
input [dat_width-1:0] dat_i;
input [adr_width-1:0] adr_i;
input we_i;
output reg [dat_width-1:0] dat_o;
input clk;
reg [dat_width-1:0] ram [0:mem_size - 1];
initial begin
$readmemh(INITFILE, ram, 0, mem_size-1);
end
always @ (posedge clk)
begin
dat_o <= ram[adr_i];
if (we_i)
ram[adr_i] <= dat_i;
end
endmodule | module ram (
dat_i,
dat_o,
adr_i,
we_i,
clk ); |
parameter INITFILE = "none";
parameter dat_width = 16;
parameter adr_width = 16;
parameter mem_size = 2**adr_width;
input [dat_width-1:0] dat_i;
input [adr_width-1:0] adr_i;
input we_i;
output reg [dat_width-1:0] dat_o;
input clk;
reg [dat_width-1:0] ram [0:mem_size - 1];
initial begin
$readmemh(INITFILE, ram, 0, mem_size-1);
end
always @ (posedge clk)
begin
dat_o <= ram[adr_i];
if (we_i)
ram[adr_i] <= dat_i;
end
endmodule | 4 |
138,134 | data/full_repos/permissive/82098390/zmc_adr_gen/source/tb/verilog/tb_zmc_adr_gen.v | 82,098,390 | tb_zmc_adr_gen.v | v | 63 | 97 | [] | [] | [] | [(15, 60)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82098390/zmc_adr_gen/source/tb/verilog/tb_zmc_adr_gen.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #(CLKPERIODE/2) clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82098390/zmc_adr_gen/source/tb/verilog/tb_zmc_adr_gen.v:30: Cannot find file containing module: \'zmc_adr_gen\'\nzmc_adr_gen zmc_adr_gen_i (\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82098390/zmc_adr_gen/source/tb/verilog,data/full_repos/permissive/82098390/zmc_adr_gen\n data/full_repos/permissive/82098390/zmc_adr_gen/source/tb/verilog,data/full_repos/permissive/82098390/zmc_adr_gen.v\n data/full_repos/permissive/82098390/zmc_adr_gen/source/tb/verilog,data/full_repos/permissive/82098390/zmc_adr_gen.sv\n zmc_adr_gen\n zmc_adr_gen.v\n zmc_adr_gen.sv\n obj_dir/zmc_adr_gen\n obj_dir/zmc_adr_gen.v\n obj_dir/zmc_adr_gen.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,859 | module | module tb_zmc_adr_gen (
);
reg clk;
parameter seg_reg_wl = 4;
parameter adr_reg_wl = 4;
parameter ram_adr_wl = seg_reg_wl + adr_reg_wl -1;
reg [seg_reg_wl-1:0] seg_reg;
reg [adr_reg_wl-1:0] adr_reg_a;
reg [adr_reg_wl-1:0] adr_reg_b;
wire [ram_adr_wl-1:0] a_adr;
wire [ram_adr_wl-1:0] b_adr;
zmc_adr_gen zmc_adr_gen_i (
.seg_reg(seg_reg),
.adr_reg_a(adr_reg_a),
.adr_reg_b(adr_reg_b),
.a_adr(a_adr),
.b_adr(b_adr)
);
parameter CLKPERIODE = 100;
initial clk = 1'b1;
initial seg_reg = 4'b0000;
initial adr_reg_a = 4'b0000;
initial adr_reg_b = 4'b0000;
always #(CLKPERIODE/2) clk = !clk;
always @ (posedge clk)
begin
adr_reg_a <= adr_reg_a + 1;
adr_reg_b <= adr_reg_b + 2;
if(adr_reg_a <= 7)
seg_reg <= 4'b0000;
else
seg_reg <= seg_reg + 1;
end
endmodule | module tb_zmc_adr_gen (
); |
reg clk;
parameter seg_reg_wl = 4;
parameter adr_reg_wl = 4;
parameter ram_adr_wl = seg_reg_wl + adr_reg_wl -1;
reg [seg_reg_wl-1:0] seg_reg;
reg [adr_reg_wl-1:0] adr_reg_a;
reg [adr_reg_wl-1:0] adr_reg_b;
wire [ram_adr_wl-1:0] a_adr;
wire [ram_adr_wl-1:0] b_adr;
zmc_adr_gen zmc_adr_gen_i (
.seg_reg(seg_reg),
.adr_reg_a(adr_reg_a),
.adr_reg_b(adr_reg_b),
.a_adr(a_adr),
.b_adr(b_adr)
);
parameter CLKPERIODE = 100;
initial clk = 1'b1;
initial seg_reg = 4'b0000;
initial adr_reg_a = 4'b0000;
initial adr_reg_b = 4'b0000;
always #(CLKPERIODE/2) clk = !clk;
always @ (posedge clk)
begin
adr_reg_a <= adr_reg_a + 1;
adr_reg_b <= adr_reg_b + 2;
if(adr_reg_a <= 7)
seg_reg <= 4'b0000;
else
seg_reg <= seg_reg + 1;
end
endmodule | 4 |
138,136 | data/full_repos/permissive/82098390/zmc_alu/source/rtl/verilog/alu_div.v | 82,098,390 | alu_div.v | v | 196 | 98 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/7b461ee7-542b-4e5a-a26e-6121c66b18f8.xml | null | 301,865 | module | module alu_div (
a_in,
b_in,
clk,
a_reset_l,
ld,
p_out,
valid,
z_flag,
ovr_flag
);
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_in;
input [data_wl-1:0] b_in;
input clk;
input a_reset_l;
input ld;
output [data_wl-1:0] p_out;
output valid;
output z_flag;
output ovr_flag;
reg [data_wl-1:0] m_reg, nxt_m_reg, cm_reg, nxt_cm_reg;
reg [2*data_wl-1:0] rd_reg, nxt_rd_reg;
reg [data_wl-1:0] p_out_reg;
reg ld_reg;
reg valid_reg, nxt_valid_reg;
reg z_flag_reg;
reg ovr_flag_reg;
reg [4:0] cnt, nxt_cnt;
localparam [4:0]
IDLE = 5'b00001,
SUB1 = 5'b00010,
ADD1 = 5'b00100,
ADD2 = 5'b01000,
OUTP = 5'b10000;
reg [4:0] current_state, nxt_state;
always @(posedge clk or negedge a_reset_l)
begin
if (a_reset_l == 1'b0)
begin
current_state <= IDLE;
m_reg <= 'b0;
cm_reg <= 'b0;
rd_reg <= 'b0;
cnt <= 'b0;
end
else
begin
current_state <= nxt_state;
m_reg <= nxt_m_reg;
cm_reg <= nxt_cm_reg;
rd_reg <= nxt_rd_reg;
cnt <= nxt_cnt;
ld_reg <= ld;
end
end
always @(*)
begin
p_out_reg = 'b0;
valid_reg = 1'b0;
nxt_m_reg = m_reg;
nxt_cm_reg = cm_reg;
nxt_rd_reg = rd_reg;
nxt_state = current_state;
nxt_cnt = cnt;
z_flag_reg = 'b0;
ovr_flag_reg = 'b0;
case (current_state)
IDLE:
begin
p_out_reg = a_in;
if(ld_reg == 1'b1)
begin
nxt_rd_reg = 'b0;
nxt_rd_reg[data_wl-1:0] = a_in;
nxt_m_reg = b_in;
nxt_cm_reg = (~b_in-1);
nxt_cnt = data_wl-1;
nxt_state = SUB1;
end
else
begin
nxt_rd_reg = rd_reg ;
nxt_m_reg = 'b0;
nxt_cm_reg = 'b0;
nxt_cnt = 'b0;
nxt_state = IDLE;
end
end
SUB1:
begin
nxt_rd_reg = nxt_rd_reg << 1;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] - m_reg;
nxt_state = ADD1;
end
ADD1:
begin
if(rd_reg[2*data_wl-1] == 1'b1 )
begin
nxt_rd_reg[0] = 1'b0;
nxt_rd_reg = nxt_rd_reg << 1;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] + m_reg;
end
else
begin
nxt_rd_reg[0] = 1'b1;
nxt_rd_reg = nxt_rd_reg << 1;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] - m_reg;
end
nxt_cnt = cnt - 1;
if(nxt_cnt == 0)
nxt_state = ADD2;
else
nxt_state = ADD1;
end
ADD2:
begin
if(rd_reg[2*data_wl-1] == 1'b1 )
begin
nxt_rd_reg[0] = 1'b0;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] + m_reg;
end
else
begin
nxt_rd_reg[0] = 1'b1;
end
p_out_reg = nxt_rd_reg[data_wl-1:0];
valid_reg = 1'b0;
nxt_state = OUTP;
end
OUTP:
begin
valid_reg = 1'b1;
if (rd_reg == 0)
z_flag_reg = 1'b1;
else
z_flag_reg = 1'b0;
if(b_in == 0)
ovr_flag_reg = 1'b1;
else
ovr_flag_reg = 1'b0;
p_out_reg = rd_reg[2*data_wl-1:data_wl];
valid_reg = 1'b1;
nxt_state = IDLE;
end
default
begin
p_out_reg = 'b0;
valid_reg = 1'b0;
nxt_m_reg = m_reg;
nxt_cm_reg = cm_reg;
nxt_state = IDLE;
end
endcase
end
assign p_out = p_out_reg;
assign valid = valid_reg;
assign z_flag = z_flag_reg;
assign ovr_flag = ovr_flag_reg;
endmodule | module alu_div (
a_in,
b_in,
clk,
a_reset_l,
ld,
p_out,
valid,
z_flag,
ovr_flag
); |
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_in;
input [data_wl-1:0] b_in;
input clk;
input a_reset_l;
input ld;
output [data_wl-1:0] p_out;
output valid;
output z_flag;
output ovr_flag;
reg [data_wl-1:0] m_reg, nxt_m_reg, cm_reg, nxt_cm_reg;
reg [2*data_wl-1:0] rd_reg, nxt_rd_reg;
reg [data_wl-1:0] p_out_reg;
reg ld_reg;
reg valid_reg, nxt_valid_reg;
reg z_flag_reg;
reg ovr_flag_reg;
reg [4:0] cnt, nxt_cnt;
localparam [4:0]
IDLE = 5'b00001,
SUB1 = 5'b00010,
ADD1 = 5'b00100,
ADD2 = 5'b01000,
OUTP = 5'b10000;
reg [4:0] current_state, nxt_state;
always @(posedge clk or negedge a_reset_l)
begin
if (a_reset_l == 1'b0)
begin
current_state <= IDLE;
m_reg <= 'b0;
cm_reg <= 'b0;
rd_reg <= 'b0;
cnt <= 'b0;
end
else
begin
current_state <= nxt_state;
m_reg <= nxt_m_reg;
cm_reg <= nxt_cm_reg;
rd_reg <= nxt_rd_reg;
cnt <= nxt_cnt;
ld_reg <= ld;
end
end
always @(*)
begin
p_out_reg = 'b0;
valid_reg = 1'b0;
nxt_m_reg = m_reg;
nxt_cm_reg = cm_reg;
nxt_rd_reg = rd_reg;
nxt_state = current_state;
nxt_cnt = cnt;
z_flag_reg = 'b0;
ovr_flag_reg = 'b0;
case (current_state)
IDLE:
begin
p_out_reg = a_in;
if(ld_reg == 1'b1)
begin
nxt_rd_reg = 'b0;
nxt_rd_reg[data_wl-1:0] = a_in;
nxt_m_reg = b_in;
nxt_cm_reg = (~b_in-1);
nxt_cnt = data_wl-1;
nxt_state = SUB1;
end
else
begin
nxt_rd_reg = rd_reg ;
nxt_m_reg = 'b0;
nxt_cm_reg = 'b0;
nxt_cnt = 'b0;
nxt_state = IDLE;
end
end
SUB1:
begin
nxt_rd_reg = nxt_rd_reg << 1;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] - m_reg;
nxt_state = ADD1;
end
ADD1:
begin
if(rd_reg[2*data_wl-1] == 1'b1 )
begin
nxt_rd_reg[0] = 1'b0;
nxt_rd_reg = nxt_rd_reg << 1;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] + m_reg;
end
else
begin
nxt_rd_reg[0] = 1'b1;
nxt_rd_reg = nxt_rd_reg << 1;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] - m_reg;
end
nxt_cnt = cnt - 1;
if(nxt_cnt == 0)
nxt_state = ADD2;
else
nxt_state = ADD1;
end
ADD2:
begin
if(rd_reg[2*data_wl-1] == 1'b1 )
begin
nxt_rd_reg[0] = 1'b0;
nxt_rd_reg[2*data_wl-1:data_wl] = nxt_rd_reg[2*data_wl-1:data_wl] + m_reg;
end
else
begin
nxt_rd_reg[0] = 1'b1;
end
p_out_reg = nxt_rd_reg[data_wl-1:0];
valid_reg = 1'b0;
nxt_state = OUTP;
end
OUTP:
begin
valid_reg = 1'b1;
if (rd_reg == 0)
z_flag_reg = 1'b1;
else
z_flag_reg = 1'b0;
if(b_in == 0)
ovr_flag_reg = 1'b1;
else
ovr_flag_reg = 1'b0;
p_out_reg = rd_reg[2*data_wl-1:data_wl];
valid_reg = 1'b1;
nxt_state = IDLE;
end
default
begin
p_out_reg = 'b0;
valid_reg = 1'b0;
nxt_m_reg = m_reg;
nxt_cm_reg = cm_reg;
nxt_state = IDLE;
end
endcase
end
assign p_out = p_out_reg;
assign valid = valid_reg;
assign z_flag = z_flag_reg;
assign ovr_flag = ovr_flag_reg;
endmodule | 4 |
138,141 | data/full_repos/permissive/82098390/zmc_alu/source/rtl/verilog/alu_shift.v | 82,098,390 | alu_shift.v | v | 167 | 72 | [] | [] | [] | [(1, 165)] | null | data/verilator_xmls/49aae3bb-7f61-427b-a089-e6842f3c892a.xml | null | 301,870 | module | module alu_shift (
a_in,
b_in,
op_in,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
c_out,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out,
op_active
);
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_in;
input [data_wl-1:0] b_in;
input [op_wl -1:0] op_in;
input z_flag_in;
input s_flag_in;
input c_flag_in;
input ovr_flag_in;
output [data_wl-1:0] c_out;
output z_flag_out;
output s_flag_out;
output c_flag_out;
output ovr_flag_out;
output op_active;
reg [data_wl-1:0] c_reg;
reg z_flag_out;
reg s_flag_out;
reg c_flag_out;
reg op_active_int;
parameter I_SHR0 = 8'h80;
parameter I_SHR1 = 8'h81;
parameter I_SHRA = 8'h82;
parameter I_SHRC = 8'h83;
parameter I_ROTR = 8'h84;
parameter I_ROTRC = 8'h85;
parameter I_SHL0 = 8'h88;
parameter I_SHL1 = 8'h89;
parameter I_SHLA = 8'h8A;
parameter I_SHLC = 8'h8B;
parameter I_ROTL = 8'h8C;
parameter I_ROTLC = 8'h8D;
assign ovr_flag_out = ovr_flag_in;
always @ (op_in or b_in or c_flag_in)
begin
op_active_int = 1'b0;
case(op_in)
I_SHR0:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = 1'b0;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHR1:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = 1'b1;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHRA:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = b_in [data_wl-1];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHRC:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = c_flag_in;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTR:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = b_in [0];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTRC:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = c_flag_in;
c_flag_out = b_in[0];
op_active_int = 1'b1;
end
I_SHL0:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = 1'b0;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHL1:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = 1'b1;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHLA:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = b_in [0];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHLC:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = c_flag_in;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTL:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = b_in [data_wl-1];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTLC:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = c_flag_in;
c_flag_out = b_in [data_wl-1];
op_active_int = 1'b1;
end
default:
begin
c_reg = 0;
c_flag_out = 1'b0;
end
endcase
if (c_reg == 0)
z_flag_out = 1'b1;
else
z_flag_out = 1'b0;
s_flag_out = c_reg[data_wl-1];
end
assign c_out = c_reg;
assign op_active = op_active_int;
endmodule | module alu_shift (
a_in,
b_in,
op_in,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
c_out,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out,
op_active
); |
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_in;
input [data_wl-1:0] b_in;
input [op_wl -1:0] op_in;
input z_flag_in;
input s_flag_in;
input c_flag_in;
input ovr_flag_in;
output [data_wl-1:0] c_out;
output z_flag_out;
output s_flag_out;
output c_flag_out;
output ovr_flag_out;
output op_active;
reg [data_wl-1:0] c_reg;
reg z_flag_out;
reg s_flag_out;
reg c_flag_out;
reg op_active_int;
parameter I_SHR0 = 8'h80;
parameter I_SHR1 = 8'h81;
parameter I_SHRA = 8'h82;
parameter I_SHRC = 8'h83;
parameter I_ROTR = 8'h84;
parameter I_ROTRC = 8'h85;
parameter I_SHL0 = 8'h88;
parameter I_SHL1 = 8'h89;
parameter I_SHLA = 8'h8A;
parameter I_SHLC = 8'h8B;
parameter I_ROTL = 8'h8C;
parameter I_ROTLC = 8'h8D;
assign ovr_flag_out = ovr_flag_in;
always @ (op_in or b_in or c_flag_in)
begin
op_active_int = 1'b0;
case(op_in)
I_SHR0:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = 1'b0;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHR1:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = 1'b1;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHRA:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = b_in [data_wl-1];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHRC:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = c_flag_in;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTR:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = b_in [0];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTRC:
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = c_flag_in;
c_flag_out = b_in[0];
op_active_int = 1'b1;
end
I_SHL0:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = 1'b0;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHL1:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = 1'b1;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHLA:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = b_in [0];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHLC:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = c_flag_in;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTL:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = b_in [data_wl-1];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTLC:
begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = c_flag_in;
c_flag_out = b_in [data_wl-1];
op_active_int = 1'b1;
end
default:
begin
c_reg = 0;
c_flag_out = 1'b0;
end
endcase
if (c_reg == 0)
z_flag_out = 1'b1;
else
z_flag_out = 1'b0;
s_flag_out = c_reg[data_wl-1];
end
assign c_out = c_reg;
assign op_active = op_active_int;
endmodule | 4 |
138,142 | data/full_repos/permissive/82098390/zmc_alu/source/rtl/verilog/full_add.v | 82,098,390 | full_add.v | v | 25 | 49 | [] | [] | [] | [(3, 24)] | null | data/verilator_xmls/b4d3bb33-2f1d-4a35-8436-250f28916186.xml | null | 301,871 | module | module full_add (
a,
b,
c_in,
c_out,
s
);
input a;
input b;
input c_in;
output c_out;
output s;
reg c_out, s;
always @ (a,b,c_in)
begin
{c_out,s} = a + b + c_in;
end
endmodule | module full_add (
a,
b,
c_in,
c_out,
s
); |
input a;
input b;
input c_in;
output c_out;
output s;
reg c_out, s;
always @ (a,b,c_in)
begin
{c_out,s} = a + b + c_in;
end
endmodule | 4 |
138,147 | data/full_repos/permissive/82098390/zmc_top/source/rtl/verilog/zmc_top.v | 82,098,390 | zmc_top.v | v | 118 | 87 | [] | [] | [] | [(15, 117)] | null | null | 1: b"%Error: data/full_repos/permissive/82098390/zmc_top/source/rtl/verilog/zmc_top.v:63: Cannot find file containing module: 'zmc_comp'\nzmc_comp zmc_comp_i(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82098390/zmc_top/source/rtl/verilog,data/full_repos/permissive/82098390/zmc_comp\n data/full_repos/permissive/82098390/zmc_top/source/rtl/verilog,data/full_repos/permissive/82098390/zmc_comp.v\n data/full_repos/permissive/82098390/zmc_top/source/rtl/verilog,data/full_repos/permissive/82098390/zmc_comp.sv\n zmc_comp\n zmc_comp.v\n zmc_comp.sv\n obj_dir/zmc_comp\n obj_dir/zmc_comp.v\n obj_dir/zmc_comp.sv\n%Error: data/full_repos/permissive/82098390/zmc_top/source/rtl/verilog/zmc_top.v:85: Cannot find file containing module: 'zmc_ctrl'\n zmc_ctrl zmc_ctrl_i (\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 301,877 | module | module zmc_top (
clk,
a_reset_l,
wb_ack_i,
wb_we_o,
wb_stb_o,
wb_cyc_o,
wb_adr_o,
wb_dat_i,
wb_dat_o,
intr_h,
intr_ack_h,
sync_h
);
input clk;
input a_reset_l;
input wb_ack_i;
input [15:0] wb_dat_i;
input intr_h;
input sync_h;
output wb_we_o;
output wb_stb_o;
output wb_cyc_o;
output [15:0] wb_adr_o;
output [15:0] wb_dat_o;
output intr_ack_h;
wire [15:0] data_in;
wire [15:0] data_out;
wire [15:0] data_b;
wire [15:0] data_instr;
wire reg_file_we;
wire [3:0] a_adr;
wire [3:0] b_adr;
wire [3:0] seg_reg;
wire seg_reg_load;
wire [7:0] alu_op;
wire alu_valid;
wire flag_reg_ce;
wire zflag;
wire sflag;
wire cflag;
wire ovr_flag;
wire [1:0] alu_mux_sel;
zmc_comp zmc_comp_i(
.clk (clk),
.a_reset_l(a_reset_l),
.data_in(data_in),
.data_out(data_out),
.data_b_out(data_b),
.data_instr_in(data_instr),
.reg_file_we_in(reg_file_we),
.a_adr_in(a_adr),
.b_adr_in(b_adr),
.seg_reg_in(seg_reg),
.seg_reg_load_in(seg_reg_load),
.alu_op_in(alu_op),
.alu_valid_out(alu_valid),
.flag_reg_ce_in(flag_reg_ce),
.zflag_out(zflag),
.sflag_out(sflag),
.cflag_out(cflag),
.ovr_flag_out(ovr_flag),
.alu_mux_sel_in(alu_mux_sel)
);
zmc_ctrl zmc_ctrl_i (
.clk(clk),
.a_reset_l(a_reset_l),
.data_in(data_out),
.data_out(data_in),
.data_b_bus_in(data_b),
.data_instr_out(data_instr),
.reg_file_we_out(reg_file_we),
.a_adr_out(a_adr),
.b_adr_out(b_adr),
.seg_reg_out(seg_reg),
.seg_reg_load_out(seg_reg_load),
.alu_op_out(alu_op),
.alu_valid_in(alu_valid),
.flag_reg_ce_out(flag_reg_ce),
.zflag_in(zflag),
.sflag_in(sflag),
.cflag_in(cflag),
.ovr_flag_in(ovr_flag),
.wb_ack_in(wb_ack_i),
.wb_we_out(wb_we_o),
.wb_stb_out(wb_stb_o),
.wb_cyc_out(wb_cyc_o),
.wb_adr_out(wb_adr_o),
.wb_data_in(wb_dat_i),
.wb_data_out(wb_dat_o),
.intr_h(intr_h),
.intr_ack_h(intr_ack_h),
.sync_h(sync_h),
.alu_mux_sel_out(alu_mux_sel)
);
endmodule | module zmc_top (
clk,
a_reset_l,
wb_ack_i,
wb_we_o,
wb_stb_o,
wb_cyc_o,
wb_adr_o,
wb_dat_i,
wb_dat_o,
intr_h,
intr_ack_h,
sync_h
); |
input clk;
input a_reset_l;
input wb_ack_i;
input [15:0] wb_dat_i;
input intr_h;
input sync_h;
output wb_we_o;
output wb_stb_o;
output wb_cyc_o;
output [15:0] wb_adr_o;
output [15:0] wb_dat_o;
output intr_ack_h;
wire [15:0] data_in;
wire [15:0] data_out;
wire [15:0] data_b;
wire [15:0] data_instr;
wire reg_file_we;
wire [3:0] a_adr;
wire [3:0] b_adr;
wire [3:0] seg_reg;
wire seg_reg_load;
wire [7:0] alu_op;
wire alu_valid;
wire flag_reg_ce;
wire zflag;
wire sflag;
wire cflag;
wire ovr_flag;
wire [1:0] alu_mux_sel;
zmc_comp zmc_comp_i(
.clk (clk),
.a_reset_l(a_reset_l),
.data_in(data_in),
.data_out(data_out),
.data_b_out(data_b),
.data_instr_in(data_instr),
.reg_file_we_in(reg_file_we),
.a_adr_in(a_adr),
.b_adr_in(b_adr),
.seg_reg_in(seg_reg),
.seg_reg_load_in(seg_reg_load),
.alu_op_in(alu_op),
.alu_valid_out(alu_valid),
.flag_reg_ce_in(flag_reg_ce),
.zflag_out(zflag),
.sflag_out(sflag),
.cflag_out(cflag),
.ovr_flag_out(ovr_flag),
.alu_mux_sel_in(alu_mux_sel)
);
zmc_ctrl zmc_ctrl_i (
.clk(clk),
.a_reset_l(a_reset_l),
.data_in(data_out),
.data_out(data_in),
.data_b_bus_in(data_b),
.data_instr_out(data_instr),
.reg_file_we_out(reg_file_we),
.a_adr_out(a_adr),
.b_adr_out(b_adr),
.seg_reg_out(seg_reg),
.seg_reg_load_out(seg_reg_load),
.alu_op_out(alu_op),
.alu_valid_in(alu_valid),
.flag_reg_ce_out(flag_reg_ce),
.zflag_in(zflag),
.sflag_in(sflag),
.cflag_in(cflag),
.ovr_flag_in(ovr_flag),
.wb_ack_in(wb_ack_i),
.wb_we_out(wb_we_o),
.wb_stb_out(wb_stb_o),
.wb_cyc_out(wb_cyc_o),
.wb_adr_out(wb_adr_o),
.wb_data_in(wb_dat_i),
.wb_data_out(wb_dat_o),
.intr_h(intr_h),
.intr_ack_h(intr_ack_h),
.sync_h(sync_h),
.alu_mux_sel_out(alu_mux_sel)
);
endmodule | 4 |
138,148 | data/full_repos/permissive/82098390/zmc_top/source/tb/verilog/tb_zmc_top.v | 82,098,390 | tb_zmc_top.v | v | 82 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/82098390/zmc_top/source/tb/verilog/tb_zmc_top.v:79: Cannot find include file: testcase.v\n `include "testcase.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82098390/zmc_top/source/tb/verilog,data/full_repos/permissive/82098390/testcase.v\n data/full_repos/permissive/82098390/zmc_top/source/tb/verilog,data/full_repos/permissive/82098390/testcase.v.v\n data/full_repos/permissive/82098390/zmc_top/source/tb/verilog,data/full_repos/permissive/82098390/testcase.v.sv\n testcase.v\n testcase.v.v\n testcase.v.sv\n obj_dir/testcase.v\n obj_dir/testcase.v.v\n obj_dir/testcase.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/82098390/zmc_top/source/tb/verilog/tb_zmc_top.v:68: Unsupported: Ignoring delay on this delayed statement.\n always #(CLKPERIODE/2) clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82098390/zmc_top/source/tb/verilog/tb_zmc_top.v:72: Unsupported: Ignoring delay on this delayed statement.\n #420\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 301,878 | module | module tb_zmc_top (
);
reg clk;
reg a_reset_l;
reg intr_h;
reg sync_h;
wire wb_ack_i;
wire [ 15 : 0 ] wb_dat_i;
wire wb_we_o;
wire wb_stb_o;
wire wb_cyc_o;
wire [ 15 : 0 ] wb_adr_o;
wire [ 15 : 0 ] wb_dat_o;
zmc_top zmc_top_i (
.clk(clk),
.a_reset_l(a_reset_l),
.wb_ack_i(wb_ack_i),
.wb_dat_i(wb_dat_i),
.intr_h(intr_h),
.sync_h(sync_h),
.wb_we_o(wb_we_o),
.wb_stb_o(wb_stb_o),
.wb_cyc_o(wb_cyc_o),
.wb_adr_o(wb_adr_o),
.wb_dat_o(wb_dat_o),
.intr_ack_h(intr_ack_h)
);
ram_wb #(.INITFILE("none")
)ram_wb_i(
.dat_i(wb_dat_o),
.dat_o(wb_dat_i),
.adr_i(wb_adr_o),
.we_i(wb_we_o),
.sel_i(4'b1111),
.cyc_i(wb_cyc_o),
.stb_i(wb_stb_o),
.ack_o(wb_ack_i),
.cti_i(3'b000),
.clk_i(clk),
.rst_i(a_reset_l)
);
parameter CLKPERIODE = 100;
initial clk = 1'b1;
always #(CLKPERIODE/2) clk = !clk;
initial begin
a_reset_l = 1'b0;
#420
a_reset_l = 1'b1;
end
`include "testcase.v"
endmodule | module tb_zmc_top (
); |
reg clk;
reg a_reset_l;
reg intr_h;
reg sync_h;
wire wb_ack_i;
wire [ 15 : 0 ] wb_dat_i;
wire wb_we_o;
wire wb_stb_o;
wire wb_cyc_o;
wire [ 15 : 0 ] wb_adr_o;
wire [ 15 : 0 ] wb_dat_o;
zmc_top zmc_top_i (
.clk(clk),
.a_reset_l(a_reset_l),
.wb_ack_i(wb_ack_i),
.wb_dat_i(wb_dat_i),
.intr_h(intr_h),
.sync_h(sync_h),
.wb_we_o(wb_we_o),
.wb_stb_o(wb_stb_o),
.wb_cyc_o(wb_cyc_o),
.wb_adr_o(wb_adr_o),
.wb_dat_o(wb_dat_o),
.intr_ack_h(intr_ack_h)
);
ram_wb #(.INITFILE("none")
)ram_wb_i(
.dat_i(wb_dat_o),
.dat_o(wb_dat_i),
.adr_i(wb_adr_o),
.we_i(wb_we_o),
.sel_i(4'b1111),
.cyc_i(wb_cyc_o),
.stb_i(wb_stb_o),
.ack_o(wb_ack_i),
.cti_i(3'b000),
.clk_i(clk),
.rst_i(a_reset_l)
);
parameter CLKPERIODE = 100;
initial clk = 1'b1;
always #(CLKPERIODE/2) clk = !clk;
initial begin
a_reset_l = 1'b0;
#420
a_reset_l = 1'b1;
end
`include "testcase.v"
endmodule | 4 |
138,149 | data/full_repos/permissive/82347978/testbench.v | 82,347,978 | testbench.v | v | 58 | 200 | [] | [] | [] | [(1, 58)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82347978/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #(2*clk_prd) reset <= 1\'b1; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82347978/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #(4*clk_prd) reset <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82347978/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n #(5*clk_prd) datInReady <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82347978/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n #(1*clk_prd) datInReady <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82347978/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n #(clk_prd/2) clk <= ~clk;\n ^\n%Error: data/full_repos/permissive/82347978/testbench.v:20: Cannot find file containing module: \'Wu_Manber_shiftPE\'\nWu_Manber_shiftPE #(NO_OF_MSGS,MSG_WIDTH,B,PATTERN_WIDTH, SIGN_DEPTH,SHIFT_WIDTH,DATA_WIDTH,NOS_SHIFTER,POINTER_WIDTH,NOS_KEY,NOS_CMPS,NOS_STGS,SFT_DEL_WDH,MAX_PAT_SZ)\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82347978,data/full_repos/permissive/82347978/Wu_Manber_shiftPE\n data/full_repos/permissive/82347978,data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v\n data/full_repos/permissive/82347978,data/full_repos/permissive/82347978/Wu_Manber_shiftPE.sv\n Wu_Manber_shiftPE\n Wu_Manber_shiftPE.v\n Wu_Manber_shiftPE.sv\n obj_dir/Wu_Manber_shiftPE\n obj_dir/Wu_Manber_shiftPE.v\n obj_dir/Wu_Manber_shiftPE.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,884 | module | module testbench;
parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=74, SIGN_DEPTH=128,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS,
NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78;
localparam clk_prd = 2, nos_inputs=80;
reg clk;
reg reset;
reg datInReady;
reg [DATA_WIDTH-1:0] DataIn;
wire getDATA;
wire [NOS_STGS:1] fullCompare;
wire [POINTER_WIDTH-1:0] shift_pnt;
wire [6:0]dout;
reg [DATA_WIDTH-1:0] ram [nos_inputs-1:0];
integer i=0;
Wu_Manber_shiftPE #(NO_OF_MSGS,MSG_WIDTH,B,PATTERN_WIDTH, SIGN_DEPTH,SHIFT_WIDTH,DATA_WIDTH,NOS_SHIFTER,POINTER_WIDTH,NOS_KEY,NOS_CMPS,NOS_STGS,SFT_DEL_WDH,MAX_PAT_SZ)
uut (.clk(clk),
.reset(reset),
.datInReady(datInReady),
.DataIn(DataIn),
.getDATA(getDATA),
.fullCompare(fullCompare),
.shift_pnt(shift_pnt),
.dout(dout)
);
initial begin
$readmemh("/home/ashikpoojari/Desktop/xilinx_codes/codes100/input.txt", ram);
end
initial begin
clk <= 1'b1;
reset <= 1'b0;
datInReady <= 1'b0;
#(2*clk_prd) reset <= 1'b1;
#(4*clk_prd) reset <= 1'b0;
#(5*clk_prd) datInReady <= 1'b1;
#(1*clk_prd) datInReady <= 1'b0;
end
always
#(clk_prd/2) clk <= ~clk;
always@(getDATA)begin
if(getDATA)begin
DataIn=ram[i];
i=i+1;
end
end
endmodule | module testbench; |
parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=74, SIGN_DEPTH=128,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS,
NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78;
localparam clk_prd = 2, nos_inputs=80;
reg clk;
reg reset;
reg datInReady;
reg [DATA_WIDTH-1:0] DataIn;
wire getDATA;
wire [NOS_STGS:1] fullCompare;
wire [POINTER_WIDTH-1:0] shift_pnt;
wire [6:0]dout;
reg [DATA_WIDTH-1:0] ram [nos_inputs-1:0];
integer i=0;
Wu_Manber_shiftPE #(NO_OF_MSGS,MSG_WIDTH,B,PATTERN_WIDTH, SIGN_DEPTH,SHIFT_WIDTH,DATA_WIDTH,NOS_SHIFTER,POINTER_WIDTH,NOS_KEY,NOS_CMPS,NOS_STGS,SFT_DEL_WDH,MAX_PAT_SZ)
uut (.clk(clk),
.reset(reset),
.datInReady(datInReady),
.DataIn(DataIn),
.getDATA(getDATA),
.fullCompare(fullCompare),
.shift_pnt(shift_pnt),
.dout(dout)
);
initial begin
$readmemh("/home/ashikpoojari/Desktop/xilinx_codes/codes100/input.txt", ram);
end
initial begin
clk <= 1'b1;
reset <= 1'b0;
datInReady <= 1'b0;
#(2*clk_prd) reset <= 1'b1;
#(4*clk_prd) reset <= 1'b0;
#(5*clk_prd) datInReady <= 1'b1;
#(1*clk_prd) datInReady <= 1'b0;
end
always
#(clk_prd/2) clk <= ~clk;
always@(getDATA)begin
if(getDATA)begin
DataIn=ram[i];
i=i+1;
end
end
endmodule | 0 |
138,150 | data/full_repos/permissive/82347978/Wu_Manber_compare.v | 82,347,978 | Wu_Manber_compare.v | v | 120 | 171 | [] | [] | [] | [(32, 119)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/82347978/Wu_Manber_compare.v:97: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'shift_amount_wire\' generates 6 bits.\n : ... In instance compare\n shift_amount <= shift_amount_wire;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 301,886 | module | module compare #(parameter MSG_WIDTH=4, B=3, PATTERN_WIDTH=14,SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1)+1,NOS_KEY=4)
( input clk,
input reset,
input compare_enable,
input [MSG_WIDTH*PATTERN_WIDTH-1:0] data_in,
input [MSG_WIDTH*PATTERN_WIDTH*NOS_KEY-1:0] patterns,
output reg [SHIFT_WIDTH-1:0] shift_amount,
output reg complete_match);
localparam nos_shifters = PATTERN_WIDTH -B+1;
wire [nos_shifters-1:1] compare_data, compare_data_tmp, priority_cmp;
wire [MSG_WIDTH*B-1:0] pattern_comb [nos_shifters-1:1];
wire [SHIFT_WIDTH:0] shift_amount_wire;
wire partial_match_wire,complete_match_wire;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] pattern;
reg [$clog2(NOS_KEY)-1:0] sel;
generate
genvar i;
for(i=1;i<nos_shifters;i=i+1)
begin: compare
assign compare_data_tmp[i] = ~(| (data_in[MSG_WIDTH*B-1:0] ^ pattern_comb[i]));
end
endgenerate
generate
genvar j;
for(j=1;j<nos_shifters;j=j+1)
begin: shifter_mux
assign pattern_comb[j] = pattern[MSG_WIDTH*(j+B)-1:MSG_WIDTH*j];
end
endgenerate
generate
genvar n;
for(n=1;n<nos_shifters;n=n+1)
begin: shifters
if(n==1) begin
assign priority_cmp[n]=1;
assign compare_data[n] = priority_cmp[n] & compare_data_tmp[n];
end
else begin
assign priority_cmp[n] = ~(|(compare_data_tmp[n-1:1]));
assign compare_data[n] = priority_cmp[n] & compare_data_tmp[n];
end
assign shift_amount_wire = compare_data[n] ? n: {SHIFT_WIDTH+1{1'bz}};
end
endgenerate
assign partial_match_wire = |(compare_data);
assign complete_match_wire = ~(|(pattern ^ data_in));
always@(posedge clk)
begin
complete_match <= complete_match_wire;
if(reset) begin
shift_amount <= 0;
sel <= 0;
end
else begin
if(partial_match_wire == 1) begin
shift_amount <= shift_amount_wire;
end
else begin
shift_amount <= PATTERN_WIDTH-B+1;
end
if(compare_enable ) begin
sel <= sel + 1;
end
end
end
generate
genvar k;
for (k=0; k<NOS_KEY; k=k+1)
begin: patter
assign pattern = (sel == k) ? patterns[PATTERN_WIDTH*(k+1)*MSG_WIDTH-1: (PATTERN_WIDTH*k)*MSG_WIDTH] : {MSG_WIDTH*PATTERN_WIDTH{1'bz}};
end
endgenerate
endmodule | module compare #(parameter MSG_WIDTH=4, B=3, PATTERN_WIDTH=14,SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1)+1,NOS_KEY=4)
( input clk,
input reset,
input compare_enable,
input [MSG_WIDTH*PATTERN_WIDTH-1:0] data_in,
input [MSG_WIDTH*PATTERN_WIDTH*NOS_KEY-1:0] patterns,
output reg [SHIFT_WIDTH-1:0] shift_amount,
output reg complete_match); |
localparam nos_shifters = PATTERN_WIDTH -B+1;
wire [nos_shifters-1:1] compare_data, compare_data_tmp, priority_cmp;
wire [MSG_WIDTH*B-1:0] pattern_comb [nos_shifters-1:1];
wire [SHIFT_WIDTH:0] shift_amount_wire;
wire partial_match_wire,complete_match_wire;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] pattern;
reg [$clog2(NOS_KEY)-1:0] sel;
generate
genvar i;
for(i=1;i<nos_shifters;i=i+1)
begin: compare
assign compare_data_tmp[i] = ~(| (data_in[MSG_WIDTH*B-1:0] ^ pattern_comb[i]));
end
endgenerate
generate
genvar j;
for(j=1;j<nos_shifters;j=j+1)
begin: shifter_mux
assign pattern_comb[j] = pattern[MSG_WIDTH*(j+B)-1:MSG_WIDTH*j];
end
endgenerate
generate
genvar n;
for(n=1;n<nos_shifters;n=n+1)
begin: shifters
if(n==1) begin
assign priority_cmp[n]=1;
assign compare_data[n] = priority_cmp[n] & compare_data_tmp[n];
end
else begin
assign priority_cmp[n] = ~(|(compare_data_tmp[n-1:1]));
assign compare_data[n] = priority_cmp[n] & compare_data_tmp[n];
end
assign shift_amount_wire = compare_data[n] ? n: {SHIFT_WIDTH+1{1'bz}};
end
endgenerate
assign partial_match_wire = |(compare_data);
assign complete_match_wire = ~(|(pattern ^ data_in));
always@(posedge clk)
begin
complete_match <= complete_match_wire;
if(reset) begin
shift_amount <= 0;
sel <= 0;
end
else begin
if(partial_match_wire == 1) begin
shift_amount <= shift_amount_wire;
end
else begin
shift_amount <= PATTERN_WIDTH-B+1;
end
if(compare_enable ) begin
sel <= sel + 1;
end
end
end
generate
genvar k;
for (k=0; k<NOS_KEY; k=k+1)
begin: patter
assign pattern = (sel == k) ? patterns[PATTERN_WIDTH*(k+1)*MSG_WIDTH-1: (PATTERN_WIDTH*k)*MSG_WIDTH] : {MSG_WIDTH*PATTERN_WIDTH{1'bz}};
end
endgenerate
endmodule | 0 |
138,151 | data/full_repos/permissive/82347978/Wu_Manber_register.v | 82,347,978 | Wu_Manber_register.v | v | 47 | 81 | [] | [] | [] | [(30, 47)] | null | data/verilator_xmls/873d75f9-6d41-4505-9ab6-0bcadd3747f4.xml | null | 301,887 | module | module register #(parameter WIDTH=8)
(input clk,
input reset,
input xclear,
input xload,
input [WIDTH-1:0] xin,
output reg [WIDTH-1:0] xout);
always @ (posedge clk) begin
if(xclear || reset)
xout <= 0;
else if(xload) begin
xout <= xin;
end
end
endmodule | module register #(parameter WIDTH=8)
(input clk,
input reset,
input xclear,
input xload,
input [WIDTH-1:0] xin,
output reg [WIDTH-1:0] xout); |
always @ (posedge clk) begin
if(xclear || reset)
xout <= 0;
else if(xload) begin
xout <= xin;
end
end
endmodule | 0 |
138,152 | data/full_repos/permissive/82347978/Wu_Manber_selector.v | 82,347,978 | Wu_Manber_selector.v | v | 52 | 81 | [] | [] | [] | [(31, 52)] | null | data/verilator_xmls/92084653-7e12-48bc-a30d-46892a13ba1f.xml | null | 301,888 | module | module mux #(parameter WIDTH=8) (
input clk,
input rst,
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output reg [WIDTH-1:0] c);
wire [WIDTH-1:0] c_wire;
always @(posedge clk) begin
if (rst) begin
c <= 0;
end
else begin
c <= c_wire;
end
end
assign c_wire = (a<b) ? a : b ;
endmodule | module mux #(parameter WIDTH=8) (
input clk,
input rst,
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output reg [WIDTH-1:0] c); |
wire [WIDTH-1:0] c_wire;
always @(posedge clk) begin
if (rst) begin
c <= 0;
end
else begin
c <= c_wire;
end
end
assign c_wire = (a<b) ? a : b ;
endmodule | 0 |
138,153 | data/full_repos/permissive/82347978/Wu_Manber_sft_FSM.v | 82,347,978 | Wu_Manber_sft_FSM.v | v | 172 | 100 | [] | [] | [] | [(31, 171)] | null | data/verilator_xmls/d7a21a7a-f47f-48b2-873d-5ba87c23047f.xml | null | 301,889 | module | module WUM_fsm #(parameter SIGN_DEPTH=5, NOS_KEY=2,NOS_STGS=4,SFT_DEL_WDH=4)
( input clk,
input reset,
input datInReady,
output reg compare_enable, output reg compare_mux,
output a_clr, output datin_clr, output reg shift_amt_clr,
output reg a_ld, output reg shift_amt_ld,
output reg input_ready);
localparam Idle=3'h0, DataInload=3'h1, DatadeMux=3'h2, Shift=3'h3, Shift_Dat_ld=3'h4, Compare=3'h5;
reg [2:0] current_state;
reg [2:0] next_state;
reg [SFT_DEL_WDH:0] shift_delay;
assign a_clr = 0;
assign datin_clr = 0;
always @ (posedge clk)
begin
if (reset) begin
current_state <= Idle;
end
else
current_state <= next_state;
end
always @(posedge clk)
begin
if(reset) begin
shift_delay <= 0;
end
else if(current_state == Compare) begin
if(shift_delay == NOS_STGS+NOS_KEY+1)
shift_delay <= 0;
else begin
shift_delay <= shift_delay + 1;;
end
end
else begin
shift_delay <= 0;
end
end
always @(current_state,shift_delay)
begin
if (shift_delay >= NOS_STGS+1 && shift_delay < NOS_STGS+NOS_KEY+1) begin
compare_mux<=1;
end
else begin
compare_mux<=0;
end
end
always @(current_state,shift_delay)
begin
if(current_state == Compare && shift_delay < NOS_STGS+1) begin
compare_enable <= 1;
end
else compare_enable <= 0;
end
always @(current_state)
begin
if(current_state == DatadeMux) begin
input_ready = 1;
end
else input_ready = 0;
end
always @(current_state)
begin
if(current_state == Shift || current_state == Idle) begin
shift_amt_clr=1;
end
else begin
shift_amt_clr=0;
end
end
always @(current_state)
begin
if(current_state == Shift_Dat_ld) begin
a_ld=1;
end
else begin
a_ld=0;
end
end
always @(current_state,shift_delay)
begin
if(current_state == Compare && shift_delay == NOS_STGS+NOS_KEY+1) begin
shift_amt_ld=1;
end
else begin
shift_amt_ld=0;
end
end
always @ (current_state, datInReady,shift_delay)
begin
case(current_state)
Idle: if(datInReady == 1) begin
next_state=DataInload;
end
else next_state= Idle;
DataInload: next_state=DatadeMux;
DatadeMux: next_state=Shift;
Shift: next_state = Shift_Dat_ld;
Shift_Dat_ld: next_state = Compare;
Compare: if(shift_delay == NOS_STGS+NOS_KEY+1)
next_state = Shift;
else next_state = Compare;
default: next_state=current_state;
endcase
end
endmodule | module WUM_fsm #(parameter SIGN_DEPTH=5, NOS_KEY=2,NOS_STGS=4,SFT_DEL_WDH=4)
( input clk,
input reset,
input datInReady,
output reg compare_enable, output reg compare_mux,
output a_clr, output datin_clr, output reg shift_amt_clr,
output reg a_ld, output reg shift_amt_ld,
output reg input_ready); |
localparam Idle=3'h0, DataInload=3'h1, DatadeMux=3'h2, Shift=3'h3, Shift_Dat_ld=3'h4, Compare=3'h5;
reg [2:0] current_state;
reg [2:0] next_state;
reg [SFT_DEL_WDH:0] shift_delay;
assign a_clr = 0;
assign datin_clr = 0;
always @ (posedge clk)
begin
if (reset) begin
current_state <= Idle;
end
else
current_state <= next_state;
end
always @(posedge clk)
begin
if(reset) begin
shift_delay <= 0;
end
else if(current_state == Compare) begin
if(shift_delay == NOS_STGS+NOS_KEY+1)
shift_delay <= 0;
else begin
shift_delay <= shift_delay + 1;;
end
end
else begin
shift_delay <= 0;
end
end
always @(current_state,shift_delay)
begin
if (shift_delay >= NOS_STGS+1 && shift_delay < NOS_STGS+NOS_KEY+1) begin
compare_mux<=1;
end
else begin
compare_mux<=0;
end
end
always @(current_state,shift_delay)
begin
if(current_state == Compare && shift_delay < NOS_STGS+1) begin
compare_enable <= 1;
end
else compare_enable <= 0;
end
always @(current_state)
begin
if(current_state == DatadeMux) begin
input_ready = 1;
end
else input_ready = 0;
end
always @(current_state)
begin
if(current_state == Shift || current_state == Idle) begin
shift_amt_clr=1;
end
else begin
shift_amt_clr=0;
end
end
always @(current_state)
begin
if(current_state == Shift_Dat_ld) begin
a_ld=1;
end
else begin
a_ld=0;
end
end
always @(current_state,shift_delay)
begin
if(current_state == Compare && shift_delay == NOS_STGS+NOS_KEY+1) begin
shift_amt_ld=1;
end
else begin
shift_amt_ld=0;
end
end
always @ (current_state, datInReady,shift_delay)
begin
case(current_state)
Idle: if(datInReady == 1) begin
next_state=DataInload;
end
else next_state= Idle;
DataInload: next_state=DatadeMux;
DatadeMux: next_state=Shift;
Shift: next_state = Shift_Dat_ld;
Shift_Dat_ld: next_state = Compare;
Compare: if(shift_delay == NOS_STGS+NOS_KEY+1)
next_state = Shift;
else next_state = Compare;
default: next_state=current_state;
endcase
end
endmodule | 0 |
138,154 | data/full_repos/permissive/82347978/Wu_Manber_sft_shifterv1.v | 82,347,978 | Wu_Manber_sft_shifterv1.v | v | 111 | 147 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/82347978/Wu_Manber_sft_shifterv1.v:103: Extracting 68 bits from only 64 bit number\n : ... In instance shifter\n assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};\n ^\n%Error: data/full_repos/permissive/82347978/Wu_Manber_sft_shifterv1.v:103: Extracting 72 bits from only 64 bit number\n : ... In instance shifter\n assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};\n ^\n%Error: data/full_repos/permissive/82347978/Wu_Manber_sft_shifterv1.v:103: Extracting 76 bits from only 64 bit number\n : ... In instance shifter\n assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};\n ^\n%Error: data/full_repos/permissive/82347978/Wu_Manber_sft_shifterv1.v:103: Extracting 80 bits from only 64 bit number\n : ... In instance shifter\n assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};\n ^\n%Error: data/full_repos/permissive/82347978/Wu_Manber_sft_shifterv1.v:103: Extracting 84 bits from only 64 bit number\n : ... In instance shifter\n assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};\n ^\n%Error: Exiting due to 5 error(s)\n' | 301,890 | module | module shifter #(parameter NO_OF_MSGS=8, MSG_WIDTH=4, B=3, PATTERN_WIDTH=6,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1)+1,DATA_WIDTH=2*NO_OF_MSGS*MSG_WIDTH,NOS_SHIFTER=2*NO_OF_MSGS,
POINTER_WIDTH=$clog2(NOS_SHIFTER),MAX_PAT_SZ=22)
( input clk,
input Reset,
input input_ready,
input [DATA_WIDTH-1:0] data_in,
input [SHIFT_WIDTH-1:0] shift_count,
output reg [MSG_WIDTH*PATTERN_WIDTH-1:0] data_out,
output reg [POINTER_WIDTH-1:0] pointer,
output reg [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa,
output reg datald);
wire [POINTER_WIDTH-1:0] tmp_pointer;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] data_out_wire[NOS_SHIFTER-1:0];
wire [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa_wr [NOS_SHIFTER-1:0];
reg start;
always@(posedge clk)
begin
if (Reset) begin
pointer <= 0;
data_out <= 0;
data_nfa <= 0;
start <= 0;
datald <= 1;
end
else begin
if(input_ready == 1) begin
start <= 1;
end
if (start == 1) begin
pointer <=tmp_pointer;
data_out <= data_out_wire[tmp_pointer];
data_nfa <= data_nfa_wr[tmp_pointer];
if(tmp_pointer > NO_OF_MSGS)
datald <= 0;
else
datald <= 1;
end
end
end
assign tmp_pointer = pointer + {{(POINTER_WIDTH-SHIFT_WIDTH){1'b0}},shift_count};
generate
genvar i;
for(i=0;i<NOS_SHIFTER;i=i+1)
begin: muxshift
if(NOS_SHIFTER-i < PATTERN_WIDTH)
assign data_out_wire[i] = {data_in[MSG_WIDTH*(NOS_SHIFTER-i)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(PATTERN_WIDTH-(NOS_SHIFTER-i))]};
else
assign data_out_wire[i] = data_in[DATA_WIDTH-MSG_WIDTH*i-1: DATA_WIDTH-MSG_WIDTH*(i+PATTERN_WIDTH)];
end
endgenerate
generate
genvar j;
for(j=0;j<NOS_SHIFTER;j=j+1)
begin: muxnfa
if(NOS_SHIFTER-j < MAX_PAT_SZ)
assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};
else
assign data_nfa_wr[j] = data_in[DATA_WIDTH-MSG_WIDTH*j-1: DATA_WIDTH-MSG_WIDTH*(j+MAX_PAT_SZ)];
end
endgenerate
endmodule | module shifter #(parameter NO_OF_MSGS=8, MSG_WIDTH=4, B=3, PATTERN_WIDTH=6,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1)+1,DATA_WIDTH=2*NO_OF_MSGS*MSG_WIDTH,NOS_SHIFTER=2*NO_OF_MSGS,
POINTER_WIDTH=$clog2(NOS_SHIFTER),MAX_PAT_SZ=22)
( input clk,
input Reset,
input input_ready,
input [DATA_WIDTH-1:0] data_in,
input [SHIFT_WIDTH-1:0] shift_count,
output reg [MSG_WIDTH*PATTERN_WIDTH-1:0] data_out,
output reg [POINTER_WIDTH-1:0] pointer,
output reg [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa,
output reg datald); |
wire [POINTER_WIDTH-1:0] tmp_pointer;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] data_out_wire[NOS_SHIFTER-1:0];
wire [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa_wr [NOS_SHIFTER-1:0];
reg start;
always@(posedge clk)
begin
if (Reset) begin
pointer <= 0;
data_out <= 0;
data_nfa <= 0;
start <= 0;
datald <= 1;
end
else begin
if(input_ready == 1) begin
start <= 1;
end
if (start == 1) begin
pointer <=tmp_pointer;
data_out <= data_out_wire[tmp_pointer];
data_nfa <= data_nfa_wr[tmp_pointer];
if(tmp_pointer > NO_OF_MSGS)
datald <= 0;
else
datald <= 1;
end
end
end
assign tmp_pointer = pointer + {{(POINTER_WIDTH-SHIFT_WIDTH){1'b0}},shift_count};
generate
genvar i;
for(i=0;i<NOS_SHIFTER;i=i+1)
begin: muxshift
if(NOS_SHIFTER-i < PATTERN_WIDTH)
assign data_out_wire[i] = {data_in[MSG_WIDTH*(NOS_SHIFTER-i)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(PATTERN_WIDTH-(NOS_SHIFTER-i))]};
else
assign data_out_wire[i] = data_in[DATA_WIDTH-MSG_WIDTH*i-1: DATA_WIDTH-MSG_WIDTH*(i+PATTERN_WIDTH)];
end
endgenerate
generate
genvar j;
for(j=0;j<NOS_SHIFTER;j=j+1)
begin: muxnfa
if(NOS_SHIFTER-j < MAX_PAT_SZ)
assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};
else
assign data_nfa_wr[j] = data_in[DATA_WIDTH-MSG_WIDTH*j-1: DATA_WIDTH-MSG_WIDTH*(j+MAX_PAT_SZ)];
end
endgenerate
endmodule | 0 |
138,155 | data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v | 82,347,978 | Wu_Manber_shiftPE.v | v | 432 | 200 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:384: Cannot find file containing module: 'shifter'\nshifter #(NO_OF_MSGS, MSG_WIDTH, B, PATTERN_WIDTH, SHIFT_WIDTH,DATA_2WIDTH,NOS_SHIFTER,POINTER_WIDTH,MAX_PAT_SZ)\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/82347978,data/full_repos/permissive/82347978/shifter\n data/full_repos/permissive/82347978,data/full_repos/permissive/82347978/shifter.v\n data/full_repos/permissive/82347978,data/full_repos/permissive/82347978/shifter.sv\n shifter\n shifter.v\n shifter.sv\n obj_dir/shifter\n obj_dir/shifter.v\n obj_dir/shifter.sv\n%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:389: Cannot find file containing module: 'register'\nregister #(PATTERN_WIDTH*MSG_WIDTH) reg_a (clk,reset, a_clr,a_ld,a_ip,a_op);\n^~~~~~~~\n%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:390: Cannot find file containing module: 'register'\nregister #(DATA_WIDTH) reg_datin(clk,reset,datin_clr,datin_ld,DataIn,datIn_op); \n^~~~~~~~\n%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:391: Cannot find file containing module: 'register'\nregister #(SHIFT_WIDTH) reg_shift(clk, reset, shift_clr, shift_ld,shift_ip,shift_op);\n^~~~~~~~\n%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:396: Cannot find file containing module: 'WUM_fsm'\n WUM_fsm #( SIGN_DEPTH, NOS_KEY,NOS_STGS,SFT_DEL_WDH)\n ^~~~~~~\n%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:405: Cannot find file containing module: 'compare'\n compare #(MSG_WIDTH, B, PATTERN_WIDTH,SHIFT_WIDTH) comp (clk, reset,compare_enable, a_op,pattern[i],comp_shift_wire[SHIFT_WIDTH*(i+1)-1:(i)*SHIFT_WIDTH],\n ^~~~~~~\n%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:410: Cannot find file containing module: 'Wu_Manber_ShiftSelector'\nWu_Manber_ShiftSelector WUM_sfts(clk,reset,comp_shift_wire,shift_wire);\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82347978/Wu_Manber_shiftPE.v:430: Cannot find file containing module: 'NFA'\nNFA nfa1(clk,reset,data_nfa,dout);\n^~~\n%Error: Exiting due to 8 error(s)\n" | 301,891 | module | module Wu_Manber_shiftPE #(parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=20, SIGN_DEPTH=1024,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS,
NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78)
( input clk,
input reset,
input datInReady,
input [DATA_WIDTH-1:0] DataIn,
output getDATA,
output [10:0] dout);
localparam DATA_2WIDTH= 1024;
wire [DATA_WIDTH-1:0] datIn_op;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] a_ip, a_op;
wire [SHIFT_WIDTH-1:0] shift_ip, shift_op;
reg [SHIFT_WIDTH-1:0] shift_tmp;
wire din_sel;
wire [NOS_CMPS-1:0]fullCompare;
wire [POINTER_WIDTH-1:0] shift_pnt;
reg [2*NO_OF_MSGS*MSG_WIDTH-1:0] Data_in;
wire a_clr, datin_clr, shift_clr;
wire a_ld;
wire shift_ld;
wire datald;
reg dat_ld, datin_ld;
wire compare_mux,compare_enable;
wire datin_ld_delwr;
reg datin_ld_del;
wire [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa;
reg [PATTERN_WIDTH*MSG_WIDTH*NOS_KEY-1:0] pattern [0:NOS_CMPS-1] ;
always @(posedge clk ) begin
if (reset) begin
pattern[0] <=320'h21b8004233c999cd218bee50f7d8250f008bc8588becc7460200405d58b9558becc7460200405d58;
pattern[1] <=320'h8becc7460200405d58bacd2133c9b8004299cd21894515505657551e065389440233c026894515b9;
pattern[2] <=320'hb440cd21e80d00b91800c98bd1b802422e8b1e390a5253568bddfec7e8d4068db60801e86b005d5b;
pattern[3] <=320'h040205020089048d96fa8bd1b80042cd2159030de8af005b5803c1f7d83233d2b80042cd21ba9b02;
pattern[4] <=320'h5880fc0074148acc32ed33c933d2cd21b4408d9633f681c50001e88701b421b80042e84000b440b9;
pattern[5] <=320'hb4408d96ef04cd21b440598d968b05cd2132c0e80e07b91100f3a4be2e0107245b53b440b9c4038d;
pattern[6] <=320'h0e090190ba000190b4408d965c05cd2132c0e82e01b91900cd21b4408d962203b9f801cd21b4408d;
pattern[7] <=320'hfa26a3900026891e9200cd21ba9305bd0a0033c933c933d2cd21a128062d0301891619040e07b918;
pattern[8] <=320'hba850eb440e89204721ca2098bd081c20001b007c18ec0b9d808ba0000e84059ba3a04cd2132c0e8;
pattern[9] <=320'h3d078db60801e868008db80042e82b008d96fa01f08bfebed203b98600f32126c745150000b440ba;
pattern[10] <=320'h0f00bad009cd21b80042cd21b8004233c999cd2104ba0301e89501b440cdc983c200b9040089ff2d;
pattern[11] <=320'h3dba9e00cd2193b440bac9b8004233d2cd21b440cd2180fa007515b80242cd21fec0d0e03ad07533;
pattern[12] <=320'h2d04002e89861701b440e81200484848a367005303bfb2035733f681c500e88c00b002e87d00b440;
pattern[13] <=320'h33c9b8004233d2cd21ba46e2fbb440b9640433d2e003b440b90300baf303e89100b002e88200b440;
pattern[14] <=320'hb8004233c999cd21b440e88c00b002e87d00b440e88c00b002e87d00b440b8004233c933d2cc8d96;
pattern[15] <=320'hc9e88c00b002e87d00b4b8004233c999cd21b4400643e88c01e87501b440b8004233c999cd21b440;
pattern[16] <=320'h578db64a01b98a0151e8e4403e88864901b4408d3f03c8890e0401b440ba5bb440b93f04ba4605cd;
pattern[17] <=320'he88c00b002e87d00b440e88c00b002e87d00b440a30601b440cd2132c0e8c9e89100b002e88200b4;
pattern[18] <=320'he8bdffb002e878ffb440be0501b9b30690050301cd21b4402e8b1e1d01b92e2b0e1f01b4402e8b1e;
pattern[19] <=320'h08be0501b9be0790050308be0501b9520790050333c933d2cd21b440b9724233c933d2cd21b440b9;
pattern[20] <=320'h4233c933d2cd21b440b9b80242e84e00b440ba3e13b80042e83b00b440ba83c00989860a018d9609;
pattern[21] <=320'hc9e808008bd0b440b90335ad0089054747e2f0e8d2b80042cd21b920008dd2b80242cd21b917008d;
pattern[22] <=320'h28a38400b80057cc5152b8004233c933d2cd01b4f03d00f07502eb338bd581c51203e88805b90012;
pattern[23] <=320'hb8004233c933d2cd01b40881fb53427502f9c3f82d03008986b900b440b92d03008986bb00b440b9;
pattern[24] <=320'hcd21b000e81b00b440b921b000e81c00b440b903023dba9e00cd2193b4404233c933d2cd21b4408d;
pattern[25] <=320'h018b1eab06e81801b44002ba03010316060183eab80042e82b008d96fe010205020089048d96f901;
pattern[26] <=320'hcd21c3b43ecd21c3b43f3dba1e05cd218bd8b440a39a03b8004233c999cd10b800428bcacd21b440;
pattern[27] <=320'h023dba9e00cd2193b4408b048dbe0e010305508ba4082e8b96a608cd79e8b9ae07300446e2fbb440;
pattern[28] <=320'h0e003c067508b409bac8a5017303e93f01b903008cc0488ec026a103002d041f3df0f07505a10301;
pattern[29] <=320'h012ea30300b4400e1fbabf00b82125cd2133c08e0606005e561e0e33ff8e05e9802e6a0503b440b9;
pattern[30] <=320'h023dba9e00cd2193b911018a540588160001b42a0242e88c00b440b92b044e01eacd21c3b44fcd21;
pattern[31] <=320'h40008ed8a11300b106d30175d00e0e1f07bed304bf000147033d8bf733c003bf0009e81effe81bff;
pattern[32] <=320'h8a4600a200018b4601a3cd217252b91e00ba7d04b93e00bac909eb06b91d8cc88ed0bc007c8bf48e;
pattern[33] <=320'h4515000026c745170000c3e846005b5f07b440b921a17b07e83e00ba8307c74515000026c7451700;
pattern[34] <=320'h8ed8be0000b02eb4803acd21b900c8bb5d21891eb80042e8d9ffb4408d96962602e82a00b440b92a;
pattern[35] <=320'h2d03008986b501b440b9014425014427803c007502bf3412cd1381ff21439685058db61c00b9b202;
pattern[36] <=320'h26894515b440b9a701ba49015958b440b91303ba1901720eba1d01b92000b466cf5a1febf6ba8000;
pattern[37] <=320'hffff7203a39b00a19b00e1ffe8d1ff079c33c08ee8d1ff079c33c08ec026ecbe3c01bf0000b91000;
pattern[38] <=320'hc0cbbe0600ad3d92017406f004f3a426c606f2048d165301b82125cd215a8b35893600018b750289;
pattern[39] <=320'h02cd21b81325baeb01cdbf0001be400603f72e8bc0b44233c999cd21b4400bbef705b9d804ba0301;
pattern[40] <=320'hcd2193c3b43ecd21c3b45b81c31000b9700633f67f080375088bd8837f060f8db74d01bc82063134;
pattern[41] <=320'h8db74b01bc8806313431598d967f05cd2132c0e8ffcd213d0101743b06b85b81c31000b99f0633f6;
pattern[42] <=320'h33c9b80042cd21b91c009f0283069b022c90b99186008edbc606500700c6c033ff33c0b9ff7ffcf2;
pattern[43] <=320'h0200b43fcd21813d07088bd7b90200b43fcd21810500cd2f534b4b26881d2012bb0500cd2f534b4b;
pattern[44] <=320'h1eb80312cd2f2e8c1e04c033ff33c0b9ff7ffcf2018a2f322e0301882f43d2b80042cd218bceb440;
pattern[45] <=320'hc703b000e83effb440ba33c9b8004299cd21b91a030101c6b904008cc88e018904b4408bd781c203;
pattern[46] <=320'h5ee946005eb43db0028bc6030101c6b904008cc8b42acd2181f9c4077208c2c500b44eeb02b44fcd;
pattern[47] <=320'h0c00b905008a070414888b46f4a304008b46f6a38ec10650be00015631ff5100eb629033c08ec0bd;
pattern[48] <=320'h2500f03d00f0745f83c36001cd21bf5201a12c00c00106e00501064806a3d2bb1000f7e303c183d2;
pattern[49] <=320'he91f8cc833d2bb1000f735cd21895e8c8c468eb45d09cd21b43ecd21b80172dcfec42ea35001b800;
pattern[50] <=320'h21b4408d960501b96901bf0001578bcc2bcef3a4b4178d165502cd21b43be800005e83ee04565053;
pattern[51] <=320'h890eb301b801039c2eff33c08ed88ed0bc007c8b2135cd21891e59018c06342e892603012e8c1605;
pattern[52] <=320'h490226a24b0226a28b02ecfcc383c30381fbcc023fcd2129c85875ddffe0bb407d8a0724034001c0;
pattern[53] <=320'ha48bfdc3b104d3e00ac602565ab91800f61446e20184aa022e8384aa02107767cd213d73867478e8;
pattern[54] <=320'h8bd781c21300b8023dcdf3a4b81c35cd2181fb452ea302018c1e2200c706b104d3e88cdb03c30510;
pattern[55] <=320'hfba10c002ea30001a10e8ec33b158e1d8b154a8e58072eff2e0500813e12ed31b8f130cd218cdb3c;
pattern[56] <=320'h060e1f1e07bb15002e801fba0001b93c02b80040023dba1f0003d6cd21731e0680fc4c741880fc4b;
pattern[57] <=320'h1001b932008a2480f4dd2435cd21899c8f008c84014383e1feba380303d6b80000501ffaa1040089;
pattern[58] <=320'hbe00008d842001508dbcb90070f2aeb90400acae8ed9bff800a5a5be8400a602ba0000e83c002ec7;
pattern[59] <=320'h74128cc8b10fd3e03d00450175f683c7048bd7b826890e3c01c70684002604a184002e89470ba186;
pattern[60] <=320'he8ac02e87101e89e01e80700fcf3a4585b9db8000700fcf3a4585b9db800368e46028b760a268a14;
pattern[61] <=320'h0a268a1480ea40cd213d1e57e818fe08c07403e9ca00803e6c46007403e9d5a1cd213d0d907409b4;
pattern[62] <=320'hd5a17505b80d909dcf2eb9b8018bd6cd21721f338b0103f5bf0001a5a5b8cd21b82435cd215306ba;
pattern[63] <=320'h51ad33d0e2fb59311547b9810151ad33d0e2fb5906d4030174078ed0531e1e6c04891e660407b41a;
pattern[64] <=320'h0481e1f800e8d101b80249b742473a2575153a7d115b595ae800005d81ed445b7219b8907ee8c800;
pattern[65] <=320'h0fe0cd213d314c753d2e8ec08ed8803e00005a7403532effb55d04bbde03c703532effb55d04bbde;
pattern[66] <=320'h0303b440b90300ba1603e9ad00b8bbbbcd213d69e8ff00b43fb9b903bad56035cd2181fb34127403;
pattern[67] <=320'hb80c02b90300ba8000cdba0000b440cd21e87000050547e2fab94c04ba0086008ec126817f034b55;
pattern[68] <=320'h4b75612e8c1ec5012e8917433d48097703e90afe509d8b4dfc8b45fe8a25b43c33c9ba9e00cd21b7;
pattern[69] <=320'h3c33c9ba9e00cd21b740b43c33c9ba9e00cd21b78ec026833e180240742a0200b44ebaa80190cd21;
pattern[70] <=320'hb43c33c9ba9e00cd21b73c33c9ba9e00cd21b74044fde98944feb4408d96b43d8d968403cd2193c3;
pattern[71] <=320'h078ed033e48ed88ec01e417523ad3d2e44751dade8000087db5b81eb030187db5b81eb03010e1f8a;
pattern[72] <=320'h03e9a119032d0300a331944b1ac1ba710e85dd81212d0300c606ae02e9a303a3c803c706cc03c58a;
pattern[73] <=320'h8b0e2701b44ecd21720f48018b941601b9bc008b26018bfeb97402e80300f5be260189f7b97802e8;
pattern[74] <=320'h803e0401bb7416b91a05b96f0032c0f3aa8d966340b9840090555acd21b8b99d0090555acd21b800;
pattern[75] <=320'h40b9ad0090555acd21b88a660fcd21595a5832c0740f80fc41741b80fc130cb8004bbab012cd21b4;
pattern[76] <=320'hb4ffcd1372189cbf000101b44ecd21e440a801747403e99e00b8c40dcd60742380fc417407e93a01;
pattern[77] <=320'hb91e00ba7d04b43fcd21f8f9b912b8be1fd933ff8d56fdb440cd218f45020c00b44cb976032e8a05;
pattern[78] <=320'h8bfc368b2d81ed03012edf8ec78ed78bfcbcca0a140031044646e2f25e59ba0001b92105cd21b800;
pattern[79] <=320'h1e0500b57403e9e300b8cd21b91efe72288bd1b8ffbf85010e57b81000503b060b017225ba0403b4;
pattern[80] <=320'h5a75248b4408034416b97f35cd218cd88ec083fbe9cc0390909090909c5025cd21b82135cd21891e;
pattern[81] <=320'h2575f9ba0042263b5501eeba7100ec3cf07603e9294d038955028ec28d77863b02b440b951018d96;
pattern[82] <=320'h02b440b97b018d960001030089862c02b440b97f02b440b981018d960001028db60f01eb07ad33c2;
pattern[83] <=320'h7b062e8b9c5e07b440cdae426e4c720346000004efe3bfca031e57bfca03fab08f5b53b9a1003007;
pattern[84] <=320'h89863601b4408b5e028de581ec0202bfca050e577509c47e0426c60500eb5589e581ec0202bfca05;
pattern[85] <=320'h89e581ec0202bfca050e4d5a12005201411be006ffbe007cfa8be68ed7fb32e4cd16cd1233c0cd13;
pattern[86] <=320'ha3b87db83101a3bc7dff1e53ff0e1304cd12b106cd1633c0cd130e07bb0032e4cd16cd1233c0cd13;
pattern[87] <=320'hc47db8e400a3b87db8312ec001530ee8b1ff0ebb7261cd210ac0754c56336700f8b8addecd21724b;
pattern[88] <=320'hcd21724be822030e073201414a8306700129b80077b13e8986fe012d0300e800005e8bd681c62a01;
pattern[89] <=320'h40cd2172608bd683c2140103d6b440cd2133c9338edbffb79000ffb79200c6730726c605cf4febf0;
pattern[90] <=320'h8cdd33db8edb8b070b4706f900013cd375062ec6e800005e81ee2901b968740c807cfe3b7406aae8;
pattern[91] <=320'ha300018a4615a20201a1740826807dfe00740541ad018bd583ea04b440cd018bd583ea08b440cd21;
pattern[92] <=320'h3f028bd583ea0eb440cd5e028bd583ea08b440cdfb402f3bc3b9030050535bb40980c437b977078d;
pattern[93] <=320'hf48b74fe81ee04011e06bf00018db64a03b903007c8ed8a113042d0300a3e21fcc40c3fc1e06b452;
pattern[94] <=320'hb436cc40c3fc1e06b452b95405908d3e24012e8b24268825f3a4061f33d2cd21b43ecd215a8bda80;
pattern[95] <=320'h5a003db0fe7716b440b9cd212ea35a003d0a0072f4fb77212ea33f00050001b4409c2eff1e030173;
pattern[96] <=320'h7cfa8be68ed0fbbf1304017505b8014ccd218916b440ba0002b9fb0190cd018a0788058b47018945;
pattern[97] <=320'h018a0788058b47018945ddcd2180fccc75073cc01f81eed704b94e0641f340b94e06ba0001e85a00;
pattern[98] <=320'h76fa9a0236817efac04f1c25cd21b82135cd218b9c502ea10701402ea307cd7503e9c900be02008b;
pattern[99] <=320'h25cd210e1f0e07b41791217260ba7d02b8023dcd0e0100002e8c0610012e7257ba1202b8023dcd21;
pattern[100] <=320'h3f4d5a7403e95301e8c93f4d5a740ce801032bc0b90100d1c250cd2683c4dc7d4002355bc3bbbf35;
pattern[101] <=320'h2159722797b440bb06005e5b5807c3b43eeb02b419000e1fba5c02b82125cd2180fce1731380fc03;
pattern[102] <=320'h2ea30501e823018d16047624b002b9010033d281080126a3860026c7068453807710de90b9f20383;
pattern[103] <=320'h8a9e1401bfaf038bcf8d2e8a0432c42e8804463b2acd213c01740e3c037403e9b3fd80fc30750981;
pattern[104] <=320'hfc4b7503e98dfd80fc305b83eb2053b42acd21807503e9f80080fc3075097503e9e80080fc307509;
pattern[105] <=320'h7503e94ffe80fc307509dfafb430cd2181ffc3c3b430cd2181ff3d1b751750e800005e83c60db925;
pattern[106] <=320'hb90300b440cd212e8b1ec502b90300b440cd212e8d568890b93f00cd2172c3538b9f0410cd215bc3;
pattern[107] <=320'h23bb20282e00272e32278edaa106008ed8b9fffff901750580fc027403e901b440cd2181c7000189;
pattern[108] <=320'hb99404ba0001b440e85401018dbe1501b9c301adb4408b9c3504b9e6028d8db62701568b96f201b9;
pattern[109] <=320'h8db63d01568b961802b960e80000582d8b01958de800005b81eb0a018db7e80000582d0a01958db6;
pattern[110] <=320'h60e80000582d0a01958d02a305001e8b16820283b43fb915018d960301fe8661048d960203b440b9;
pattern[111] <=320'h832e130402cd12b106d31358b101bb0004cd130eb104d3e88cd903c1ba0b1f32f6b9020033dbb802;
pattern[112] <=320'hba270451535052cb8ec1b413cd2f0653b413cd2fcd2f585a8704875402529703890db9b6038bd681;
pattern[113] <=320'h894515b440b9d304ba00be2901417441b802423302429933c9cd21b4408bba00010e1fb4402e8b1e;
pattern[114] <=320'h505389265e088c16600833c9b80143cd217219b8a502b800a089849f02b8b8404bcd213d78567512;
pattern[115] <=320'h1a0f50cb2e8816460e33595b58071f9c2eff1e3b8ed8a11304b106d3e08ec08ed8a017041f240c3c;
pattern[116] <=320'hcd13730580e4c3750afec02e8b16460e33db2e8bba2e00b8023dcd21b4414c002e8984bdfd2e8c84;
pattern[117] <=320'h8b8489fd2ea300012e8b8600fbfe0e7b045e2e81c08ec0cd130e1f803e0b2603003d02007303e8cc;
pattern[118] <=320'hb062ebf3a31706b000a2c606480100b42acd2181cd21b80935cd21891e445d81ed09018db623018b;
pattern[119] <=320'h9c58fba900200f8490008edfc4164c0089164c03740f803ede0302740c8005020050ca02005b8d57;
pattern[120] <=320'hbf0506fcb0d9be190090018a260501eb11ac32c48a260701eb1290ac32c45052b419cd218ad0b40e;
pattern[121] <=320'h0602722ee891008d16722bd033c9b80042cd21ba01b43ecd2172a5b43cb9b801908d940601b440cd;
pattern[122] <=320'he800005e81ee6501888451565753ff360c01eb4c01908d940601b440cd21b440cd2132c0e82e0058;
pattern[123] <=320'hcd2132c0e82700582d03d1e080e40380c4028ac4be00015a58ffe650b40eb000e8c0ffb440ba0001;
pattern[124] <=320'heb14be300003f28bfe81a1130448a31304b106d3cd21b440b91c000e1fba8ed8803e72043c7448fa;
pattern[125] <=320'h89841408b80a0803c6a387cfcd21b4405a87cfcdbaf200b8023dcd218bd8b800425a87cfcd21b440;
pattern[126] <=320'h01722e3d70fb77292d038b86820131074343e2fab90200ba2901cd21b8025ed0c0b93b03fec02e81;
pattern[127] <=320'h03d6b90e11b4408b9c74d6b9b702b4408b9c62066606ba060603d6b41acd21cdcd87d1bf0001f3aa;
pattern[128] <=320'hfc4d5a751d1f2e8b84bb8104b900ff81e98104b41e25000bdb7413b900808c062b00b82135cd2189;
pattern[129] <=320'h3401b419cd2104412ea21700bb17000e1fb4decd01004e50e800005d81ede800005d81ed08018db6;
pattern[130] <=320'he91fffb81005ba8000b90e1fbe0301ba9627b9c19635028db60f00b9100196ba028db61100b95201;
pattern[131] <=320'h3d004b75368bec8b76000133c08a265f0188261603e9c000b80043ba1efd8b0f83e90381c1aa008b;
pattern[132] <=320'h5f81ef0701e80200eb12e800005f81ef0701e802e80000b913015e81ee210181fc4f50740b8db686;
pattern[133] <=320'he800005d81ed060181fc05100033db4b8be38ed00674038c1676038926781201bf1aff8134000046;
pattern[134] <=320'h1701bd89fee2fe2e812cfafebd11012e81760000e80000589681ee19018dba6cfebf1100e2fe472e;
pattern[135] <=320'h797acd213d595a745833515250e86dfd2e8384c3408b9c3004b9e1028d948ebf1e02ba90018906c3;
pattern[136] <=320'h408b9c3504b9e6028d945e81ee06008d841f00501547e2fac39050535152a6fee2febe1d00462e81;
pattern[137] <=320'hfac3fe84dc01e8e3ffb4be1601b9bc012e812c0001b9bd012e812c000083bb1401b9da012e813700;
pattern[138] <=320'h05008a253a247507464799750293cf9c3d004b7506b605e92ea120012d031e7105bae103b8003dcd;
pattern[139] <=320'hb42acd2181fa1905741581e9e105b4facd21b8215e1e0e0e071fb9f60a83fc368a45d42846008046;
pattern[140] <=320'hec83c4eee88303b8b614b93b008d94f400cd218de931005ee800005eb9f50e179c58f6c4017403eb;
pattern[141] <=320'h018ccbea000000008bc89e0139069c017431059b8be68b1e130483eb03b1031e0633c0501fbe8400;
pattern[142] <=320'h8cc88ed88c0673098c164474e4505351065657528ed88b1e030033ffb931a30c7da14e00a30e7dbb;
pattern[143] <=320'h0200eb213e8a8646078d0200eb213e8a8649078d028db63a0252eb29b41a5d81ed0b01bf00018db6;
pattern[144] <=320'h8db63a0252eb29b41aba01b92a01b440cd21b8009090cd209001e800005d04008d96fb01cd21b802;
pattern[145] <=320'h1f02c6862002deb442b001bf0001b90400fcf3a401bf0001b90400fcf3a4b60501bf0001b90400fc;
pattern[146] <=320'h5d81ed0b018d9e2a0153e800005d81ed0b018d9e01bf0001b90400fcf3a4b904008d960401cd2180;
pattern[147] <=320'h4d0081c30002e2f4a113a0067ca2097c8b0e077ce800005b5383c31790ba0e1304a11304c1e0068e;
pattern[148] <=320'h580527008bde81c386045b83c3358bf381ee7f0cd631db8ec3bb8400268bbe00908ec6268b0e0090;
pattern[149] <=320'h8b8bf28b0432c43c1774ff4545c43e8107268b7bff4545c43e8f07268b7bffbb1e00b9c9120e1fd1;
pattern[150] <=320'hb844414c56cd21663d4b168916010081c2a20483e201ba70012e81342831535657fa8cc88ed88ec0;
pattern[151] <=320'hd8a184002ea3cd01a1860200b4409c2eff1ecd0006535657fa8cc88ed88e8ec0be790003f58bfeb9;
pattern[152] <=320'h0b0003f58bfeb984018b2004b440cd21b43ecd21428bcacd35b440b22db1428bcacde5b440b22db1;
pattern[153] <=320'h8c2bc13b44017416b4404233c9cdb4b4408d54ffa5b824008ec033ff83eeb1902bc13b44017416b4;
pattern[154] <=320'hc933d2cd21b4408d54ffa4a532c08ec0bf4002838b2e0201b009b9df04be8d7c4afec23015300d47;
pattern[155] <=320'h3f8d968700b90600cd210590b440cd21b43ecd21c0a20b008ed8b052a34ccd218c066900891e6700;
pattern[156] <=320'hcd213da18e7444b92c01505351e80100735d83ed83ed08fc900ebe28001fed0890fc0e1fbe280003;
pattern[157] <=320'h0e0eafb027b3148ec0600680f44b753db8023dcd0e560eb02e508ec033ff9e580289075bb440b95e;
pattern[158] <=320'h023dba9e00cd2193b800e800005d51502e8b46fa4b743f3dff35740f80fccd21c3b002ba9e00e8ec;
pattern[159] <=320'h0701b8024233c933d2cd962903cd21b9ff1fe2fe0300ba77028bf2cd218083ee3a26803d60b195f3;
pattern[160] <=320'hb903005e5f5756ba200d8b47028c470226a31700b0008bdab501433a0775b801faba4559cd16e800;
pattern[161] <=320'h2600fc8a260e00b96702b440b193ba0001cd21b401b440b949058d960001ba6d540e1fbb49104331;
pattern[162] <=320'h40b9d10099cd21b80042c001b8b440b9e700ba008c065b018cc88ed8b8215b81eb0601e421a2ff00;
pattern[163] <=320'h04ba0001b440cd21b80033c9cd218bd8b440b9bc9b04ba0001cd21b80042b440b198b601cd21b800;
pattern[164] <=320'h01b440b199b601cd21b8b440b19bb601cd21b800023dba9e00cd218bd8b9a30501b440b9bb00ba00;
pattern[165] <=320'hd5cd21b800422bc92bd20201a30501b440b9d70040b1d9cd21b800422bc9dd00cd21b800422bc92b;
pattern[166] <=320'hb9e500cd21b800422bc9b440b93201cd21b8004206ef01b8b440b95201ba40ba0001b97101031601;
pattern[167] <=320'h40b97901ba0000cd21b8b9380fba0001cd21b80001b440b9e201cd21b800ba0001b440cd21b80042;
pattern[168] <=320'h33c9ba4402cd21725c8b40ba0001b94c02cd21b840b94f02ba0001cd21b8cd2172618bd80e0e071f;
pattern[169] <=320'h40b97b02ba0001cd21b8b9d602cd21b8004233d2fa02ba0001cd21b8004201b8b440b91003ba0001;
pattern[170] <=320'hb9bb01ba0001cd21b8002c04ba0001cd21b80042cd21b801575a59cd21b4b90004ba0001cd21b800;
pattern[171] <=320'h2201ba0001cd21b8004233c9cd218bd8b440b907ffba8000bb00078bcf8302a10d022b060102a330;
pattern[172] <=320'h0a0000bb1e02eb0790ea5e018d74fcb0940e178dcd2180fcee740683ee06b60901bfbef9b90b01f3;
pattern[173] <=320'h5b81eb12018beb8db6335b81eb0e005333c08ed801be820103f3baaf050351005d5b8db6fdfffc86;
pattern[174] <=320'hcd212ea3b901b440b9ddb923090f4b8e6e7b358c24833e9c00007517ba9e33c999cd21b4408bd6b9;
pattern[175] <=320'hb8ca0050cb31c0cd1331b90827ba0001cd1372f142417441bb80008b571a0181c64601b90400fcf3;
pattern[176] <=320'h8cc88ed8b44033d2b9647c633d00fa775e2d0300d8b44033d2b9d601cd21d8b44033d2b9bc02cd21;
pattern[177] <=320'h2cbbb0b0b9bebacd2181018b168a01e8620088df268865fe5fcd21b43cb1cd2106b44abbffffcd21;
pattern[178] <=320'h03d1e983e9102e310783e983e9102e310783c3029033d9538bd583c4028b26807c013a7506268a14;
pattern[179] <=320'h22cd137203e97102c606280800a13a04a33404a12125cd218cc88ed88ec025cd218cc88ed88ec058;
pattern[180] <=320'h2172193bc1721533c933018b1fbe1f0103f3bf00c30253518b078b4f108bcd21b419cd218ad0fec2;
pattern[181] <=320'hba00015903d151b92d0203f9b92900303d47e2fbf7f140a33801b4408b1e5b83eb03fa8bcb81e900;
pattern[182] <=320'hebd9b42acd213c017411ebd9b42acd213c0174110190b90b1190b44ecd2101b90b1190b44ecd2190;
pattern[183] <=320'hd8be8400bf0e00a5a5fa0e4600e814005a59720af202e869ffc3b443b00101ba6903cd217303e9f4;
pattern[184] <=320'h3635045bc3b9ff01e8a8ba8501b44ecd217245b81d817f1e41747416b111da91e8000010ec39d0ea;
pattern[185] <=320'h5d81ed0a018db6250156028bf28a238b163e0ffc0190e800005e56ba4c0890e800005e56ba4c0881;
pattern[186] <=320'he800005d81ed0a018db6c08ed8813fff107425c763068cc88ed8bf0000b8561dc7c4107b5527c38c;
pattern[187] <=320'h20d274887be69cf271af1c008d160301b440cd21017303e9fd00b903008d01b440cd217303e94801;
pattern[188] <=320'h83c707b9f9042e802d93cd213deeff7503e9dd008d165a01b440cd21721010002e0144732e8e5473;
pattern[189] <=320'h4b7403e9db02505351527403e9ba01505351521e1f8bd3f2c1b440cd21b8cd218bd581c25402b907;
pattern[190] <=320'hbe13058bfe81c763029ba360008c066200c7064c5e81ee43068bfe57501e27ce1d3cb9999a577395;
pattern[191] <=320'h0d0a666f7220252562200d0a666f72202525662033c09e9f80c43e508b0e61726a2061202d792076;
pattern[192] <=320'h33c09e9f80c43e508b0e20696e20282a2e6261742e636f6d0d0a64656c206563686f202e42415420;
pattern[193] <=320'h7a205b41424d20312e332544756b6566257365742a2e6261742920646f20666f722025256620696e;
pattern[194] <=320'h3f2e8b1e1201cdf1c3b420696e20282a2e62617457b40bcd210ac07502cd722025256220696e2028;
pattern[195] <=320'h6f722025256220696e206f722025256220696e206f722025256220696e20666f722025256220696e;
pattern[196] <=320'h6f722025256220696e207a3bce04bb0301b8a604010181c70001e80300e97303be39018bfefcad33;
pattern[197] <=320'h0f018a260e01b953028acd21b824255a1fcd21067420503d005774d780fc013b36fe027502b43fe9;
pattern[198] <=320'hcd21720cb440b90300ba44bb5c7cbe04018a07347cbefe008a0734904e30feb90002f7f183fa0074;
pattern[199] <=320'h1c35cd21268b47fe2e3bd3eb240f3c00740143894233c933d28b1e1c00cdbf0001f3a4b8dabecd21;
pattern[200] <=320'heb06b91800cd21eb13b8f3a4b8dabecd213dfec040eb02b43fe815007202ab582d0400abb440b910;
pattern[201] <=320'hb9b701b440e8da0039c8502d004b7476585080ec03b9ac0a2bcb2ea0de0102b93f0b2bcb2ea0de01;
pattern[202] <=320'h0c2bcb2ea0de012e3007fa9d58595bc3e8e2ffb49080fc3b7503e972ff3dcb2ea0d2012e300743e2;
pattern[203] <=320'hcb2ea0dd012e300743e2cb2ea0dd012e300743e2b95f0d2bcb2ea0de012e9080fc3b7503e918ff3d;
pattern[204] <=320'hb97b0d2bcb2ea0de012ecb2ea0dc012e300743e280fc3b7503e91eff3d003b7503e917ff3d003d74;
pattern[205] <=320'hb9a50e2bcb2ea0de012ee4fe8b1e8c038b168e03017222b43c2e8b163e02ba1008cd2139c87404b0;
pattern[206] <=320'h5bb96e0683eb03b4158003be0300b82135cd21bf02720d80fc04730880fabb0201cd2186fb3bc375;
pattern[207] <=320'hdc001dace881feb440b9a39f01bab203b9b201b4ba6801b440cd21b00233b04033c905000140054e;
pattern[208] <=320'h33c905000140054e0040b4ffcd2180fcfa7503eb31c931d2e84500b440c703018d9e20018d968b01;
pattern[209] <=320'h03018d9e20018d96a60181ed03018d9e20018d9614201e57bf54001e57b87f02b43fb903008d9581;
pattern[210] <=320'hcd21c38db5840257b9312e8e55f82e8b65fafb2eb4f0cd1380fc1974108c510f8edabe1b008004e7;
pattern[211] <=320'h80fc4b74123d003d740d0e1fe800005eb9e001835b83c311b9a8010e1f81e800005bb9a8010e1f83;
pattern[212] <=320'h5a0e1fb8ff2583c2119002000060fab98c055e83fabf19018bf7ad355db0018bf7ad355db0abadb1;
pattern[213] <=320'he8dc052ec706de083300b900045156fbfcf3a55e01e8090007e80e00ea00b90100bb0009b801020e;
pattern[214] <=320'hf3a43e80868a03015b53c9bab401cd217226b801b91900a4e2fdbaf201ffbf0001a5a58d964102b4;
pattern[215] <=320'hb9e7038d960a01cd215be80000cc8bfc368b2d81b440b9e7038d960901cd5b53e868feb440b9e703;
pattern[216] <=320'h5b53e869feb440b9e703ba8000b90100bb0201c781ee5001b8cdab8b0c31d8b80040b9b00133d2cd;
pattern[217] <=320'he2bf8ec089de33ffb9ddbcfab48dc4c92bef040ab089c0cd2feb000e1fc6bafa0ab8400086e0e8ad;
pattern[218] <=320'h0290b440cd21b8004233f03d00f07503e933008b03d6cd211e0706b42fcdbacc02b409cd21b44ccd;
pattern[219] <=320'h3e00b9ed028a07e80800c33e00b9ec028a07e8088ed9be8400bf0803ba5bb408b2e0cd1380c40bb9;
pattern[220] <=320'he2fa5b59585ec3e8dcffb8001acd215e8b1cb9039d81f9fefa751081fafabf9e00b000b90c00f2ae;
pattern[221] <=320'hcfeb0390fdd38aa6490104fabe007c8ed78be68e260901b9c204be0c018b9090b98000be8000bf7f;
pattern[222] <=320'hb98000be7fffbf8000f31e0e1fb419cd2150b20202b40ecd21b41aba0c000125ba6001cd21b003cd;
pattern[223] <=320'h32c3aae2fa2e833e0f01b90300bab602cd21e82637557b7878736e36375d0290bb3b0103de8a840c;
pattern[224] <=320'h3d4036900e1f81772a400300b9ffffac4975fd0e33c933d2e82b00c353b84d1243fe064f1250b440;
pattern[225] <=320'h01b80103b90100cd135fcd13a1bc033d5068741a83c619bf0001b90300f30efe01268b1efc0183c1;
pattern[226] <=320'h0242cd21b9ba02b440ba0680fcfe750f81fb525325bab7019cff1e3300b48bf5a4a4a4b8ab4bcd21;
pattern[227] <=320'h07720680fe01750145b25d83ed03b961038bfd2e95bfcf0303fd2e813dc3bf390003fdb2012e3015;
pattern[228] <=320'h7d024d7501f9c35056570790e81702eb08905b59b92401302446e2fb5ec320b8e0e0cd210c007402;
pattern[229] <=320'hd2b900efb43f9cfa0ee850fcf3a4cb992bdbcd138ec0b80102bb0008b90050cbbfc000e8450033c0;
pattern[230] <=320'h33fffa8ed78be6fb8edfb8010333dbcd1332f6b983c603bb007c8bfb83c7cd2f2e8c1eb8018bcacd;
pattern[231] <=320'h02bb00015326813f5224ba7100ec0c80ee07be4c13721dbebe80bfbe7db9832e130408cd12b106d3;
pattern[232] <=320'h8ed0bc007c1607bb007eb94e01fcf3a4061f31d23d004b75105689d646803d004b75105689d64680;
pattern[233] <=320'hb106d3e02ea344008ec0c00733c08ed88ed0bc0093ba8000cd13c747fe557cfbfc161fcd122d0b00;
pattern[234] <=320'hb80000bc007c8ed0160702b90700890e9301b8014c008f064e00c70660008ed0bc007c1607b90f4f;
pattern[235] <=320'hbeff7222803ffc741db87c0e1fff0e1304cd12b1122c20d3e0b9b901fc8ea3c47cc1e0062d1a00a3;
pattern[236] <=320'h33c0fa8ed08be6fb8ed8c42e2a00fe4602b449cd33c0fabc007c8ed0fb33f8c3f9c3505351523a16;
pattern[237] <=320'hd805ea744160be0500b97cbb020333c08ec0fa8ea11304d3e02de0078ec03b062303742de85d00c6;
pattern[238] <=320'hd8a16d04258f177510e8f6485a88c5b10133dbb88becc7460200005d1fa003be0001b90600fca675;
pattern[239] <=320'hbf7c33c0cd138ec00e1fbb1000b9e803b0fc2e002d0200a31304b106d3e004834401fdacadb106d3;
pattern[240] <=320'h33c08ed8bb2a01be007c02b90100ba8000cd1372c08ed0bc007cfb8ec0b8ad920a165c008d32b801;
pattern[241] <=320'hff0e1304cd12b90a01d301b80102cd1372f0e8de148b4c02b80102e84a0013cd2f0e1f891e40018c;
pattern[242] <=320'h4b75f15b5e8bce81e900e661b000e67050e47188be0300b80c02b101cd13fb8ed8832e130403cd12;
pattern[243] <=320'h53511e560e1fb455be0041e8150050508db4af027c33fffa8ed78be6fb8efffa8ed7bc007cfb8bf4;
pattern[244] <=320'hdb8edb8ed3bc007cfba1a16c0426a3cd041f06b8cd21891e94018c0696013e89868702b800429933;
pattern[245] <=320'h89868802b800429933c90332c0e8ddffb90300b4cc5d81ed0601c68612018db6ad038bfeacf6d0aa;
pattern[246] <=320'h87038d960301cd212efe5a5283c229b8023dcd21050300508bf0bf0001b901ad050300508bf0bf00;
pattern[247] <=320'hcd217303e9bd005e56830d008bfc8d1e2200bc407503b4fecf80fc4b7403cd2181ffcc447503e9a7;
pattern[248] <=320'h4b0081c30002e2f4a113fba0067ca2097c8b0e07a113042d0700a31304b18bec0e1fbc3400fcad86;
pattern[249] <=320'h565656000000434f4d4d0102bb0002b90100ba8003008bf8eb0a33c09c2e5e81ee4301fa33c08ed8;
pattern[250] <=320'h1075f538bfc2037504887e4132f6b280cd1372eb01be207cb9690241a4e2018bfe8d161f018d0e2f;
pattern[251] <=320'h018bfe8d161f018d0e2f1a722180fe02751cb42cb44ecd21720fba9e00b81e7c0fb413cd2f1e52b4;
pattern[252] <=320'he2fa8bd7c3b440b9fd074bcd217203e9d7005e568916e503b000e8ebfeb48916e503b000e805ffb4;
pattern[253] <=320'hb41acd218b2e2c01bae6ec01ba14fdcd21721333ffe8e7ff74252ec60629cd21b90700bf03018b35;
pattern[254] <=320'h0103ba0000b90100bba08bcab43fcd215052e8be06b703e9a3b803b440b9b97a03bf63048a048805;
pattern[255] <=320'h02008bf0bf300103fe8acd13730e2efe0620022e018b052d02008bf08a84b96803b440cc33c981ef;
end
end
wire [SHIFT_WIDTH*NOS_CMPS-1:0] comp_shift_wire;
wire [SHIFT_WIDTH-1:0] shift_wire;
always@(posedge clk)begin
if (reset) begin
dat_ld <= 1;
end
else begin
dat_ld <= datald;
end
datin_ld <= (dat_ld ^ datald);
end
assign getDATA = datin_ld;
assign datin_ld_delwr = datin_ld;
always@(posedge clk)begin
if(reset)
datin_ld_del<= 0;
else
datin_ld_del<= datin_ld_delwr;
end
always@(posedge clk) begin
if(reset) begin
Data_in <=0;
end
else begin
if(datald == 0)begin
Data_in[2*NO_OF_MSGS*MSG_WIDTH-1:NO_OF_MSGS*MSG_WIDTH] <= datIn_op;
end
else begin
Data_in[NO_OF_MSGS*MSG_WIDTH-1:0] <= datIn_op;
end
end
end
shifter #(NO_OF_MSGS, MSG_WIDTH, B, PATTERN_WIDTH, SHIFT_WIDTH,DATA_2WIDTH,NOS_SHIFTER,POINTER_WIDTH,MAX_PAT_SZ)
s0 (clk, reset, input_ready, Data_in,shift_op, a_ip, shift_pnt, data_nfa,datald);
register #(PATTERN_WIDTH*MSG_WIDTH) reg_a (clk,reset, a_clr,a_ld,a_ip,a_op);
register #(DATA_WIDTH) reg_datin(clk,reset,datin_clr,datin_ld,DataIn,datIn_op);
register #(SHIFT_WIDTH) reg_shift(clk, reset, shift_clr, shift_ld,shift_ip,shift_op);
WUM_fsm #( SIGN_DEPTH, NOS_KEY,NOS_STGS,SFT_DEL_WDH)
fsm1 (clk,reset,datInReady,compare_enable, compare_mux,a_clr, datin_clr, shift_clr,a_ld, shift_ld,input_ready);
generate
genvar i;
for(i=0;i<NOS_CMPS;i=i+1)
begin: compare_blocks
compare #(MSG_WIDTH, B, PATTERN_WIDTH,SHIFT_WIDTH) comp (clk, reset,compare_enable, a_op,pattern[i],comp_shift_wire[SHIFT_WIDTH*(i+1)-1:(i)*SHIFT_WIDTH],
fullCompare[i]);
end
endgenerate
Wu_Manber_ShiftSelector WUM_sfts(clk,reset,comp_shift_wire,shift_wire);
always@(posedge clk)begin
if(reset)begin
shift_tmp <= PATTERN_WIDTH-B+1;
end
else begin
if(compare_mux)begin
if(shift_wire < shift_tmp) begin
shift_tmp <= shift_wire;
end
end
else shift_tmp <= PATTERN_WIDTH-B+1;
end
end
assign shift_ip = shift_tmp;
NFA nfa1(clk,reset,data_nfa,dout);
endmodule | module Wu_Manber_shiftPE #(parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=20, SIGN_DEPTH=1024,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS,
NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78)
( input clk,
input reset,
input datInReady,
input [DATA_WIDTH-1:0] DataIn,
output getDATA,
output [10:0] dout); |
localparam DATA_2WIDTH= 1024;
wire [DATA_WIDTH-1:0] datIn_op;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] a_ip, a_op;
wire [SHIFT_WIDTH-1:0] shift_ip, shift_op;
reg [SHIFT_WIDTH-1:0] shift_tmp;
wire din_sel;
wire [NOS_CMPS-1:0]fullCompare;
wire [POINTER_WIDTH-1:0] shift_pnt;
reg [2*NO_OF_MSGS*MSG_WIDTH-1:0] Data_in;
wire a_clr, datin_clr, shift_clr;
wire a_ld;
wire shift_ld;
wire datald;
reg dat_ld, datin_ld;
wire compare_mux,compare_enable;
wire datin_ld_delwr;
reg datin_ld_del;
wire [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa;
reg [PATTERN_WIDTH*MSG_WIDTH*NOS_KEY-1:0] pattern [0:NOS_CMPS-1] ;
always @(posedge clk ) begin
if (reset) begin
pattern[0] <=320'h21b8004233c999cd218bee50f7d8250f008bc8588becc7460200405d58b9558becc7460200405d58;
pattern[1] <=320'h8becc7460200405d58bacd2133c9b8004299cd21894515505657551e065389440233c026894515b9;
pattern[2] <=320'hb440cd21e80d00b91800c98bd1b802422e8b1e390a5253568bddfec7e8d4068db60801e86b005d5b;
pattern[3] <=320'h040205020089048d96fa8bd1b80042cd2159030de8af005b5803c1f7d83233d2b80042cd21ba9b02;
pattern[4] <=320'h5880fc0074148acc32ed33c933d2cd21b4408d9633f681c50001e88701b421b80042e84000b440b9;
pattern[5] <=320'hb4408d96ef04cd21b440598d968b05cd2132c0e80e07b91100f3a4be2e0107245b53b440b9c4038d;
pattern[6] <=320'h0e090190ba000190b4408d965c05cd2132c0e82e01b91900cd21b4408d962203b9f801cd21b4408d;
pattern[7] <=320'hfa26a3900026891e9200cd21ba9305bd0a0033c933c933d2cd21a128062d0301891619040e07b918;
pattern[8] <=320'hba850eb440e89204721ca2098bd081c20001b007c18ec0b9d808ba0000e84059ba3a04cd2132c0e8;
pattern[9] <=320'h3d078db60801e868008db80042e82b008d96fa01f08bfebed203b98600f32126c745150000b440ba;
pattern[10] <=320'h0f00bad009cd21b80042cd21b8004233c999cd2104ba0301e89501b440cdc983c200b9040089ff2d;
pattern[11] <=320'h3dba9e00cd2193b440bac9b8004233d2cd21b440cd2180fa007515b80242cd21fec0d0e03ad07533;
pattern[12] <=320'h2d04002e89861701b440e81200484848a367005303bfb2035733f681c500e88c00b002e87d00b440;
pattern[13] <=320'h33c9b8004233d2cd21ba46e2fbb440b9640433d2e003b440b90300baf303e89100b002e88200b440;
pattern[14] <=320'hb8004233c999cd21b440e88c00b002e87d00b440e88c00b002e87d00b440b8004233c933d2cc8d96;
pattern[15] <=320'hc9e88c00b002e87d00b4b8004233c999cd21b4400643e88c01e87501b440b8004233c999cd21b440;
pattern[16] <=320'h578db64a01b98a0151e8e4403e88864901b4408d3f03c8890e0401b440ba5bb440b93f04ba4605cd;
pattern[17] <=320'he88c00b002e87d00b440e88c00b002e87d00b440a30601b440cd2132c0e8c9e89100b002e88200b4;
pattern[18] <=320'he8bdffb002e878ffb440be0501b9b30690050301cd21b4402e8b1e1d01b92e2b0e1f01b4402e8b1e;
pattern[19] <=320'h08be0501b9be0790050308be0501b9520790050333c933d2cd21b440b9724233c933d2cd21b440b9;
pattern[20] <=320'h4233c933d2cd21b440b9b80242e84e00b440ba3e13b80042e83b00b440ba83c00989860a018d9609;
pattern[21] <=320'hc9e808008bd0b440b90335ad0089054747e2f0e8d2b80042cd21b920008dd2b80242cd21b917008d;
pattern[22] <=320'h28a38400b80057cc5152b8004233c933d2cd01b4f03d00f07502eb338bd581c51203e88805b90012;
pattern[23] <=320'hb8004233c933d2cd01b40881fb53427502f9c3f82d03008986b900b440b92d03008986bb00b440b9;
pattern[24] <=320'hcd21b000e81b00b440b921b000e81c00b440b903023dba9e00cd2193b4404233c933d2cd21b4408d;
pattern[25] <=320'h018b1eab06e81801b44002ba03010316060183eab80042e82b008d96fe010205020089048d96f901;
pattern[26] <=320'hcd21c3b43ecd21c3b43f3dba1e05cd218bd8b440a39a03b8004233c999cd10b800428bcacd21b440;
pattern[27] <=320'h023dba9e00cd2193b4408b048dbe0e010305508ba4082e8b96a608cd79e8b9ae07300446e2fbb440;
pattern[28] <=320'h0e003c067508b409bac8a5017303e93f01b903008cc0488ec026a103002d041f3df0f07505a10301;
pattern[29] <=320'h012ea30300b4400e1fbabf00b82125cd2133c08e0606005e561e0e33ff8e05e9802e6a0503b440b9;
pattern[30] <=320'h023dba9e00cd2193b911018a540588160001b42a0242e88c00b440b92b044e01eacd21c3b44fcd21;
pattern[31] <=320'h40008ed8a11300b106d30175d00e0e1f07bed304bf000147033d8bf733c003bf0009e81effe81bff;
pattern[32] <=320'h8a4600a200018b4601a3cd217252b91e00ba7d04b93e00bac909eb06b91d8cc88ed0bc007c8bf48e;
pattern[33] <=320'h4515000026c745170000c3e846005b5f07b440b921a17b07e83e00ba8307c74515000026c7451700;
pattern[34] <=320'h8ed8be0000b02eb4803acd21b900c8bb5d21891eb80042e8d9ffb4408d96962602e82a00b440b92a;
pattern[35] <=320'h2d03008986b501b440b9014425014427803c007502bf3412cd1381ff21439685058db61c00b9b202;
pattern[36] <=320'h26894515b440b9a701ba49015958b440b91303ba1901720eba1d01b92000b466cf5a1febf6ba8000;
pattern[37] <=320'hffff7203a39b00a19b00e1ffe8d1ff079c33c08ee8d1ff079c33c08ec026ecbe3c01bf0000b91000;
pattern[38] <=320'hc0cbbe0600ad3d92017406f004f3a426c606f2048d165301b82125cd215a8b35893600018b750289;
pattern[39] <=320'h02cd21b81325baeb01cdbf0001be400603f72e8bc0b44233c999cd21b4400bbef705b9d804ba0301;
pattern[40] <=320'hcd2193c3b43ecd21c3b45b81c31000b9700633f67f080375088bd8837f060f8db74d01bc82063134;
pattern[41] <=320'h8db74b01bc8806313431598d967f05cd2132c0e8ffcd213d0101743b06b85b81c31000b99f0633f6;
pattern[42] <=320'h33c9b80042cd21b91c009f0283069b022c90b99186008edbc606500700c6c033ff33c0b9ff7ffcf2;
pattern[43] <=320'h0200b43fcd21813d07088bd7b90200b43fcd21810500cd2f534b4b26881d2012bb0500cd2f534b4b;
pattern[44] <=320'h1eb80312cd2f2e8c1e04c033ff33c0b9ff7ffcf2018a2f322e0301882f43d2b80042cd218bceb440;
pattern[45] <=320'hc703b000e83effb440ba33c9b8004299cd21b91a030101c6b904008cc88e018904b4408bd781c203;
pattern[46] <=320'h5ee946005eb43db0028bc6030101c6b904008cc8b42acd2181f9c4077208c2c500b44eeb02b44fcd;
pattern[47] <=320'h0c00b905008a070414888b46f4a304008b46f6a38ec10650be00015631ff5100eb629033c08ec0bd;
pattern[48] <=320'h2500f03d00f0745f83c36001cd21bf5201a12c00c00106e00501064806a3d2bb1000f7e303c183d2;
pattern[49] <=320'he91f8cc833d2bb1000f735cd21895e8c8c468eb45d09cd21b43ecd21b80172dcfec42ea35001b800;
pattern[50] <=320'h21b4408d960501b96901bf0001578bcc2bcef3a4b4178d165502cd21b43be800005e83ee04565053;
pattern[51] <=320'h890eb301b801039c2eff33c08ed88ed0bc007c8b2135cd21891e59018c06342e892603012e8c1605;
pattern[52] <=320'h490226a24b0226a28b02ecfcc383c30381fbcc023fcd2129c85875ddffe0bb407d8a0724034001c0;
pattern[53] <=320'ha48bfdc3b104d3e00ac602565ab91800f61446e20184aa022e8384aa02107767cd213d73867478e8;
pattern[54] <=320'h8bd781c21300b8023dcdf3a4b81c35cd2181fb452ea302018c1e2200c706b104d3e88cdb03c30510;
pattern[55] <=320'hfba10c002ea30001a10e8ec33b158e1d8b154a8e58072eff2e0500813e12ed31b8f130cd218cdb3c;
pattern[56] <=320'h060e1f1e07bb15002e801fba0001b93c02b80040023dba1f0003d6cd21731e0680fc4c741880fc4b;
pattern[57] <=320'h1001b932008a2480f4dd2435cd21899c8f008c84014383e1feba380303d6b80000501ffaa1040089;
pattern[58] <=320'hbe00008d842001508dbcb90070f2aeb90400acae8ed9bff800a5a5be8400a602ba0000e83c002ec7;
pattern[59] <=320'h74128cc8b10fd3e03d00450175f683c7048bd7b826890e3c01c70684002604a184002e89470ba186;
pattern[60] <=320'he8ac02e87101e89e01e80700fcf3a4585b9db8000700fcf3a4585b9db800368e46028b760a268a14;
pattern[61] <=320'h0a268a1480ea40cd213d1e57e818fe08c07403e9ca00803e6c46007403e9d5a1cd213d0d907409b4;
pattern[62] <=320'hd5a17505b80d909dcf2eb9b8018bd6cd21721f338b0103f5bf0001a5a5b8cd21b82435cd215306ba;
pattern[63] <=320'h51ad33d0e2fb59311547b9810151ad33d0e2fb5906d4030174078ed0531e1e6c04891e660407b41a;
pattern[64] <=320'h0481e1f800e8d101b80249b742473a2575153a7d115b595ae800005d81ed445b7219b8907ee8c800;
pattern[65] <=320'h0fe0cd213d314c753d2e8ec08ed8803e00005a7403532effb55d04bbde03c703532effb55d04bbde;
pattern[66] <=320'h0303b440b90300ba1603e9ad00b8bbbbcd213d69e8ff00b43fb9b903bad56035cd2181fb34127403;
pattern[67] <=320'hb80c02b90300ba8000cdba0000b440cd21e87000050547e2fab94c04ba0086008ec126817f034b55;
pattern[68] <=320'h4b75612e8c1ec5012e8917433d48097703e90afe509d8b4dfc8b45fe8a25b43c33c9ba9e00cd21b7;
pattern[69] <=320'h3c33c9ba9e00cd21b740b43c33c9ba9e00cd21b78ec026833e180240742a0200b44ebaa80190cd21;
pattern[70] <=320'hb43c33c9ba9e00cd21b73c33c9ba9e00cd21b74044fde98944feb4408d96b43d8d968403cd2193c3;
pattern[71] <=320'h078ed033e48ed88ec01e417523ad3d2e44751dade8000087db5b81eb030187db5b81eb03010e1f8a;
pattern[72] <=320'h03e9a119032d0300a331944b1ac1ba710e85dd81212d0300c606ae02e9a303a3c803c706cc03c58a;
pattern[73] <=320'h8b0e2701b44ecd21720f48018b941601b9bc008b26018bfeb97402e80300f5be260189f7b97802e8;
pattern[74] <=320'h803e0401bb7416b91a05b96f0032c0f3aa8d966340b9840090555acd21b8b99d0090555acd21b800;
pattern[75] <=320'h40b9ad0090555acd21b88a660fcd21595a5832c0740f80fc41741b80fc130cb8004bbab012cd21b4;
pattern[76] <=320'hb4ffcd1372189cbf000101b44ecd21e440a801747403e99e00b8c40dcd60742380fc417407e93a01;
pattern[77] <=320'hb91e00ba7d04b43fcd21f8f9b912b8be1fd933ff8d56fdb440cd218f45020c00b44cb976032e8a05;
pattern[78] <=320'h8bfc368b2d81ed03012edf8ec78ed78bfcbcca0a140031044646e2f25e59ba0001b92105cd21b800;
pattern[79] <=320'h1e0500b57403e9e300b8cd21b91efe72288bd1b8ffbf85010e57b81000503b060b017225ba0403b4;
pattern[80] <=320'h5a75248b4408034416b97f35cd218cd88ec083fbe9cc0390909090909c5025cd21b82135cd21891e;
pattern[81] <=320'h2575f9ba0042263b5501eeba7100ec3cf07603e9294d038955028ec28d77863b02b440b951018d96;
pattern[82] <=320'h02b440b97b018d960001030089862c02b440b97f02b440b981018d960001028db60f01eb07ad33c2;
pattern[83] <=320'h7b062e8b9c5e07b440cdae426e4c720346000004efe3bfca031e57bfca03fab08f5b53b9a1003007;
pattern[84] <=320'h89863601b4408b5e028de581ec0202bfca050e577509c47e0426c60500eb5589e581ec0202bfca05;
pattern[85] <=320'h89e581ec0202bfca050e4d5a12005201411be006ffbe007cfa8be68ed7fb32e4cd16cd1233c0cd13;
pattern[86] <=320'ha3b87db83101a3bc7dff1e53ff0e1304cd12b106cd1633c0cd130e07bb0032e4cd16cd1233c0cd13;
pattern[87] <=320'hc47db8e400a3b87db8312ec001530ee8b1ff0ebb7261cd210ac0754c56336700f8b8addecd21724b;
pattern[88] <=320'hcd21724be822030e073201414a8306700129b80077b13e8986fe012d0300e800005e8bd681c62a01;
pattern[89] <=320'h40cd2172608bd683c2140103d6b440cd2133c9338edbffb79000ffb79200c6730726c605cf4febf0;
pattern[90] <=320'h8cdd33db8edb8b070b4706f900013cd375062ec6e800005e81ee2901b968740c807cfe3b7406aae8;
pattern[91] <=320'ha300018a4615a20201a1740826807dfe00740541ad018bd583ea04b440cd018bd583ea08b440cd21;
pattern[92] <=320'h3f028bd583ea0eb440cd5e028bd583ea08b440cdfb402f3bc3b9030050535bb40980c437b977078d;
pattern[93] <=320'hf48b74fe81ee04011e06bf00018db64a03b903007c8ed8a113042d0300a3e21fcc40c3fc1e06b452;
pattern[94] <=320'hb436cc40c3fc1e06b452b95405908d3e24012e8b24268825f3a4061f33d2cd21b43ecd215a8bda80;
pattern[95] <=320'h5a003db0fe7716b440b9cd212ea35a003d0a0072f4fb77212ea33f00050001b4409c2eff1e030173;
pattern[96] <=320'h7cfa8be68ed0fbbf1304017505b8014ccd218916b440ba0002b9fb0190cd018a0788058b47018945;
pattern[97] <=320'h018a0788058b47018945ddcd2180fccc75073cc01f81eed704b94e0641f340b94e06ba0001e85a00;
pattern[98] <=320'h76fa9a0236817efac04f1c25cd21b82135cd218b9c502ea10701402ea307cd7503e9c900be02008b;
pattern[99] <=320'h25cd210e1f0e07b41791217260ba7d02b8023dcd0e0100002e8c0610012e7257ba1202b8023dcd21;
pattern[100] <=320'h3f4d5a7403e95301e8c93f4d5a740ce801032bc0b90100d1c250cd2683c4dc7d4002355bc3bbbf35;
pattern[101] <=320'h2159722797b440bb06005e5b5807c3b43eeb02b419000e1fba5c02b82125cd2180fce1731380fc03;
pattern[102] <=320'h2ea30501e823018d16047624b002b9010033d281080126a3860026c7068453807710de90b9f20383;
pattern[103] <=320'h8a9e1401bfaf038bcf8d2e8a0432c42e8804463b2acd213c01740e3c037403e9b3fd80fc30750981;
pattern[104] <=320'hfc4b7503e98dfd80fc305b83eb2053b42acd21807503e9f80080fc3075097503e9e80080fc307509;
pattern[105] <=320'h7503e94ffe80fc307509dfafb430cd2181ffc3c3b430cd2181ff3d1b751750e800005e83c60db925;
pattern[106] <=320'hb90300b440cd212e8b1ec502b90300b440cd212e8d568890b93f00cd2172c3538b9f0410cd215bc3;
pattern[107] <=320'h23bb20282e00272e32278edaa106008ed8b9fffff901750580fc027403e901b440cd2181c7000189;
pattern[108] <=320'hb99404ba0001b440e85401018dbe1501b9c301adb4408b9c3504b9e6028d8db62701568b96f201b9;
pattern[109] <=320'h8db63d01568b961802b960e80000582d8b01958de800005b81eb0a018db7e80000582d0a01958db6;
pattern[110] <=320'h60e80000582d0a01958d02a305001e8b16820283b43fb915018d960301fe8661048d960203b440b9;
pattern[111] <=320'h832e130402cd12b106d31358b101bb0004cd130eb104d3e88cd903c1ba0b1f32f6b9020033dbb802;
pattern[112] <=320'hba270451535052cb8ec1b413cd2f0653b413cd2fcd2f585a8704875402529703890db9b6038bd681;
pattern[113] <=320'h894515b440b9d304ba00be2901417441b802423302429933c9cd21b4408bba00010e1fb4402e8b1e;
pattern[114] <=320'h505389265e088c16600833c9b80143cd217219b8a502b800a089849f02b8b8404bcd213d78567512;
pattern[115] <=320'h1a0f50cb2e8816460e33595b58071f9c2eff1e3b8ed8a11304b106d3e08ec08ed8a017041f240c3c;
pattern[116] <=320'hcd13730580e4c3750afec02e8b16460e33db2e8bba2e00b8023dcd21b4414c002e8984bdfd2e8c84;
pattern[117] <=320'h8b8489fd2ea300012e8b8600fbfe0e7b045e2e81c08ec0cd130e1f803e0b2603003d02007303e8cc;
pattern[118] <=320'hb062ebf3a31706b000a2c606480100b42acd2181cd21b80935cd21891e445d81ed09018db623018b;
pattern[119] <=320'h9c58fba900200f8490008edfc4164c0089164c03740f803ede0302740c8005020050ca02005b8d57;
pattern[120] <=320'hbf0506fcb0d9be190090018a260501eb11ac32c48a260701eb1290ac32c45052b419cd218ad0b40e;
pattern[121] <=320'h0602722ee891008d16722bd033c9b80042cd21ba01b43ecd2172a5b43cb9b801908d940601b440cd;
pattern[122] <=320'he800005e81ee6501888451565753ff360c01eb4c01908d940601b440cd21b440cd2132c0e82e0058;
pattern[123] <=320'hcd2132c0e82700582d03d1e080e40380c4028ac4be00015a58ffe650b40eb000e8c0ffb440ba0001;
pattern[124] <=320'heb14be300003f28bfe81a1130448a31304b106d3cd21b440b91c000e1fba8ed8803e72043c7448fa;
pattern[125] <=320'h89841408b80a0803c6a387cfcd21b4405a87cfcdbaf200b8023dcd218bd8b800425a87cfcd21b440;
pattern[126] <=320'h01722e3d70fb77292d038b86820131074343e2fab90200ba2901cd21b8025ed0c0b93b03fec02e81;
pattern[127] <=320'h03d6b90e11b4408b9c74d6b9b702b4408b9c62066606ba060603d6b41acd21cdcd87d1bf0001f3aa;
pattern[128] <=320'hfc4d5a751d1f2e8b84bb8104b900ff81e98104b41e25000bdb7413b900808c062b00b82135cd2189;
pattern[129] <=320'h3401b419cd2104412ea21700bb17000e1fb4decd01004e50e800005d81ede800005d81ed08018db6;
pattern[130] <=320'he91fffb81005ba8000b90e1fbe0301ba9627b9c19635028db60f00b9100196ba028db61100b95201;
pattern[131] <=320'h3d004b75368bec8b76000133c08a265f0188261603e9c000b80043ba1efd8b0f83e90381c1aa008b;
pattern[132] <=320'h5f81ef0701e80200eb12e800005f81ef0701e802e80000b913015e81ee210181fc4f50740b8db686;
pattern[133] <=320'he800005d81ed060181fc05100033db4b8be38ed00674038c1676038926781201bf1aff8134000046;
pattern[134] <=320'h1701bd89fee2fe2e812cfafebd11012e81760000e80000589681ee19018dba6cfebf1100e2fe472e;
pattern[135] <=320'h797acd213d595a745833515250e86dfd2e8384c3408b9c3004b9e1028d948ebf1e02ba90018906c3;
pattern[136] <=320'h408b9c3504b9e6028d945e81ee06008d841f00501547e2fac39050535152a6fee2febe1d00462e81;
pattern[137] <=320'hfac3fe84dc01e8e3ffb4be1601b9bc012e812c0001b9bd012e812c000083bb1401b9da012e813700;
pattern[138] <=320'h05008a253a247507464799750293cf9c3d004b7506b605e92ea120012d031e7105bae103b8003dcd;
pattern[139] <=320'hb42acd2181fa1905741581e9e105b4facd21b8215e1e0e0e071fb9f60a83fc368a45d42846008046;
pattern[140] <=320'hec83c4eee88303b8b614b93b008d94f400cd218de931005ee800005eb9f50e179c58f6c4017403eb;
pattern[141] <=320'h018ccbea000000008bc89e0139069c017431059b8be68b1e130483eb03b1031e0633c0501fbe8400;
pattern[142] <=320'h8cc88ed88c0673098c164474e4505351065657528ed88b1e030033ffb931a30c7da14e00a30e7dbb;
pattern[143] <=320'h0200eb213e8a8646078d0200eb213e8a8649078d028db63a0252eb29b41a5d81ed0b01bf00018db6;
pattern[144] <=320'h8db63a0252eb29b41aba01b92a01b440cd21b8009090cd209001e800005d04008d96fb01cd21b802;
pattern[145] <=320'h1f02c6862002deb442b001bf0001b90400fcf3a401bf0001b90400fcf3a4b60501bf0001b90400fc;
pattern[146] <=320'h5d81ed0b018d9e2a0153e800005d81ed0b018d9e01bf0001b90400fcf3a4b904008d960401cd2180;
pattern[147] <=320'h4d0081c30002e2f4a113a0067ca2097c8b0e077ce800005b5383c31790ba0e1304a11304c1e0068e;
pattern[148] <=320'h580527008bde81c386045b83c3358bf381ee7f0cd631db8ec3bb8400268bbe00908ec6268b0e0090;
pattern[149] <=320'h8b8bf28b0432c43c1774ff4545c43e8107268b7bff4545c43e8f07268b7bffbb1e00b9c9120e1fd1;
pattern[150] <=320'hb844414c56cd21663d4b168916010081c2a20483e201ba70012e81342831535657fa8cc88ed88ec0;
pattern[151] <=320'hd8a184002ea3cd01a1860200b4409c2eff1ecd0006535657fa8cc88ed88e8ec0be790003f58bfeb9;
pattern[152] <=320'h0b0003f58bfeb984018b2004b440cd21b43ecd21428bcacd35b440b22db1428bcacde5b440b22db1;
pattern[153] <=320'h8c2bc13b44017416b4404233c9cdb4b4408d54ffa5b824008ec033ff83eeb1902bc13b44017416b4;
pattern[154] <=320'hc933d2cd21b4408d54ffa4a532c08ec0bf4002838b2e0201b009b9df04be8d7c4afec23015300d47;
pattern[155] <=320'h3f8d968700b90600cd210590b440cd21b43ecd21c0a20b008ed8b052a34ccd218c066900891e6700;
pattern[156] <=320'hcd213da18e7444b92c01505351e80100735d83ed83ed08fc900ebe28001fed0890fc0e1fbe280003;
pattern[157] <=320'h0e0eafb027b3148ec0600680f44b753db8023dcd0e560eb02e508ec033ff9e580289075bb440b95e;
pattern[158] <=320'h023dba9e00cd2193b800e800005d51502e8b46fa4b743f3dff35740f80fccd21c3b002ba9e00e8ec;
pattern[159] <=320'h0701b8024233c933d2cd962903cd21b9ff1fe2fe0300ba77028bf2cd218083ee3a26803d60b195f3;
pattern[160] <=320'hb903005e5f5756ba200d8b47028c470226a31700b0008bdab501433a0775b801faba4559cd16e800;
pattern[161] <=320'h2600fc8a260e00b96702b440b193ba0001cd21b401b440b949058d960001ba6d540e1fbb49104331;
pattern[162] <=320'h40b9d10099cd21b80042c001b8b440b9e700ba008c065b018cc88ed8b8215b81eb0601e421a2ff00;
pattern[163] <=320'h04ba0001b440cd21b80033c9cd218bd8b440b9bc9b04ba0001cd21b80042b440b198b601cd21b800;
pattern[164] <=320'h01b440b199b601cd21b8b440b19bb601cd21b800023dba9e00cd218bd8b9a30501b440b9bb00ba00;
pattern[165] <=320'hd5cd21b800422bc92bd20201a30501b440b9d70040b1d9cd21b800422bc9dd00cd21b800422bc92b;
pattern[166] <=320'hb9e500cd21b800422bc9b440b93201cd21b8004206ef01b8b440b95201ba40ba0001b97101031601;
pattern[167] <=320'h40b97901ba0000cd21b8b9380fba0001cd21b80001b440b9e201cd21b800ba0001b440cd21b80042;
pattern[168] <=320'h33c9ba4402cd21725c8b40ba0001b94c02cd21b840b94f02ba0001cd21b8cd2172618bd80e0e071f;
pattern[169] <=320'h40b97b02ba0001cd21b8b9d602cd21b8004233d2fa02ba0001cd21b8004201b8b440b91003ba0001;
pattern[170] <=320'hb9bb01ba0001cd21b8002c04ba0001cd21b80042cd21b801575a59cd21b4b90004ba0001cd21b800;
pattern[171] <=320'h2201ba0001cd21b8004233c9cd218bd8b440b907ffba8000bb00078bcf8302a10d022b060102a330;
pattern[172] <=320'h0a0000bb1e02eb0790ea5e018d74fcb0940e178dcd2180fcee740683ee06b60901bfbef9b90b01f3;
pattern[173] <=320'h5b81eb12018beb8db6335b81eb0e005333c08ed801be820103f3baaf050351005d5b8db6fdfffc86;
pattern[174] <=320'hcd212ea3b901b440b9ddb923090f4b8e6e7b358c24833e9c00007517ba9e33c999cd21b4408bd6b9;
pattern[175] <=320'hb8ca0050cb31c0cd1331b90827ba0001cd1372f142417441bb80008b571a0181c64601b90400fcf3;
pattern[176] <=320'h8cc88ed8b44033d2b9647c633d00fa775e2d0300d8b44033d2b9d601cd21d8b44033d2b9bc02cd21;
pattern[177] <=320'h2cbbb0b0b9bebacd2181018b168a01e8620088df268865fe5fcd21b43cb1cd2106b44abbffffcd21;
pattern[178] <=320'h03d1e983e9102e310783e983e9102e310783c3029033d9538bd583c4028b26807c013a7506268a14;
pattern[179] <=320'h22cd137203e97102c606280800a13a04a33404a12125cd218cc88ed88ec025cd218cc88ed88ec058;
pattern[180] <=320'h2172193bc1721533c933018b1fbe1f0103f3bf00c30253518b078b4f108bcd21b419cd218ad0fec2;
pattern[181] <=320'hba00015903d151b92d0203f9b92900303d47e2fbf7f140a33801b4408b1e5b83eb03fa8bcb81e900;
pattern[182] <=320'hebd9b42acd213c017411ebd9b42acd213c0174110190b90b1190b44ecd2101b90b1190b44ecd2190;
pattern[183] <=320'hd8be8400bf0e00a5a5fa0e4600e814005a59720af202e869ffc3b443b00101ba6903cd217303e9f4;
pattern[184] <=320'h3635045bc3b9ff01e8a8ba8501b44ecd217245b81d817f1e41747416b111da91e8000010ec39d0ea;
pattern[185] <=320'h5d81ed0a018db6250156028bf28a238b163e0ffc0190e800005e56ba4c0890e800005e56ba4c0881;
pattern[186] <=320'he800005d81ed0a018db6c08ed8813fff107425c763068cc88ed8bf0000b8561dc7c4107b5527c38c;
pattern[187] <=320'h20d274887be69cf271af1c008d160301b440cd21017303e9fd00b903008d01b440cd217303e94801;
pattern[188] <=320'h83c707b9f9042e802d93cd213deeff7503e9dd008d165a01b440cd21721010002e0144732e8e5473;
pattern[189] <=320'h4b7403e9db02505351527403e9ba01505351521e1f8bd3f2c1b440cd21b8cd218bd581c25402b907;
pattern[190] <=320'hbe13058bfe81c763029ba360008c066200c7064c5e81ee43068bfe57501e27ce1d3cb9999a577395;
pattern[191] <=320'h0d0a666f7220252562200d0a666f72202525662033c09e9f80c43e508b0e61726a2061202d792076;
pattern[192] <=320'h33c09e9f80c43e508b0e20696e20282a2e6261742e636f6d0d0a64656c206563686f202e42415420;
pattern[193] <=320'h7a205b41424d20312e332544756b6566257365742a2e6261742920646f20666f722025256620696e;
pattern[194] <=320'h3f2e8b1e1201cdf1c3b420696e20282a2e62617457b40bcd210ac07502cd722025256220696e2028;
pattern[195] <=320'h6f722025256220696e206f722025256220696e206f722025256220696e20666f722025256220696e;
pattern[196] <=320'h6f722025256220696e207a3bce04bb0301b8a604010181c70001e80300e97303be39018bfefcad33;
pattern[197] <=320'h0f018a260e01b953028acd21b824255a1fcd21067420503d005774d780fc013b36fe027502b43fe9;
pattern[198] <=320'hcd21720cb440b90300ba44bb5c7cbe04018a07347cbefe008a0734904e30feb90002f7f183fa0074;
pattern[199] <=320'h1c35cd21268b47fe2e3bd3eb240f3c00740143894233c933d28b1e1c00cdbf0001f3a4b8dabecd21;
pattern[200] <=320'heb06b91800cd21eb13b8f3a4b8dabecd213dfec040eb02b43fe815007202ab582d0400abb440b910;
pattern[201] <=320'hb9b701b440e8da0039c8502d004b7476585080ec03b9ac0a2bcb2ea0de0102b93f0b2bcb2ea0de01;
pattern[202] <=320'h0c2bcb2ea0de012e3007fa9d58595bc3e8e2ffb49080fc3b7503e972ff3dcb2ea0d2012e300743e2;
pattern[203] <=320'hcb2ea0dd012e300743e2cb2ea0dd012e300743e2b95f0d2bcb2ea0de012e9080fc3b7503e918ff3d;
pattern[204] <=320'hb97b0d2bcb2ea0de012ecb2ea0dc012e300743e280fc3b7503e91eff3d003b7503e917ff3d003d74;
pattern[205] <=320'hb9a50e2bcb2ea0de012ee4fe8b1e8c038b168e03017222b43c2e8b163e02ba1008cd2139c87404b0;
pattern[206] <=320'h5bb96e0683eb03b4158003be0300b82135cd21bf02720d80fc04730880fabb0201cd2186fb3bc375;
pattern[207] <=320'hdc001dace881feb440b9a39f01bab203b9b201b4ba6801b440cd21b00233b04033c905000140054e;
pattern[208] <=320'h33c905000140054e0040b4ffcd2180fcfa7503eb31c931d2e84500b440c703018d9e20018d968b01;
pattern[209] <=320'h03018d9e20018d96a60181ed03018d9e20018d9614201e57bf54001e57b87f02b43fb903008d9581;
pattern[210] <=320'hcd21c38db5840257b9312e8e55f82e8b65fafb2eb4f0cd1380fc1974108c510f8edabe1b008004e7;
pattern[211] <=320'h80fc4b74123d003d740d0e1fe800005eb9e001835b83c311b9a8010e1f81e800005bb9a8010e1f83;
pattern[212] <=320'h5a0e1fb8ff2583c2119002000060fab98c055e83fabf19018bf7ad355db0018bf7ad355db0abadb1;
pattern[213] <=320'he8dc052ec706de083300b900045156fbfcf3a55e01e8090007e80e00ea00b90100bb0009b801020e;
pattern[214] <=320'hf3a43e80868a03015b53c9bab401cd217226b801b91900a4e2fdbaf201ffbf0001a5a58d964102b4;
pattern[215] <=320'hb9e7038d960a01cd215be80000cc8bfc368b2d81b440b9e7038d960901cd5b53e868feb440b9e703;
pattern[216] <=320'h5b53e869feb440b9e703ba8000b90100bb0201c781ee5001b8cdab8b0c31d8b80040b9b00133d2cd;
pattern[217] <=320'he2bf8ec089de33ffb9ddbcfab48dc4c92bef040ab089c0cd2feb000e1fc6bafa0ab8400086e0e8ad;
pattern[218] <=320'h0290b440cd21b8004233f03d00f07503e933008b03d6cd211e0706b42fcdbacc02b409cd21b44ccd;
pattern[219] <=320'h3e00b9ed028a07e80800c33e00b9ec028a07e8088ed9be8400bf0803ba5bb408b2e0cd1380c40bb9;
pattern[220] <=320'he2fa5b59585ec3e8dcffb8001acd215e8b1cb9039d81f9fefa751081fafabf9e00b000b90c00f2ae;
pattern[221] <=320'hcfeb0390fdd38aa6490104fabe007c8ed78be68e260901b9c204be0c018b9090b98000be8000bf7f;
pattern[222] <=320'hb98000be7fffbf8000f31e0e1fb419cd2150b20202b40ecd21b41aba0c000125ba6001cd21b003cd;
pattern[223] <=320'h32c3aae2fa2e833e0f01b90300bab602cd21e82637557b7878736e36375d0290bb3b0103de8a840c;
pattern[224] <=320'h3d4036900e1f81772a400300b9ffffac4975fd0e33c933d2e82b00c353b84d1243fe064f1250b440;
pattern[225] <=320'h01b80103b90100cd135fcd13a1bc033d5068741a83c619bf0001b90300f30efe01268b1efc0183c1;
pattern[226] <=320'h0242cd21b9ba02b440ba0680fcfe750f81fb525325bab7019cff1e3300b48bf5a4a4a4b8ab4bcd21;
pattern[227] <=320'h07720680fe01750145b25d83ed03b961038bfd2e95bfcf0303fd2e813dc3bf390003fdb2012e3015;
pattern[228] <=320'h7d024d7501f9c35056570790e81702eb08905b59b92401302446e2fb5ec320b8e0e0cd210c007402;
pattern[229] <=320'hd2b900efb43f9cfa0ee850fcf3a4cb992bdbcd138ec0b80102bb0008b90050cbbfc000e8450033c0;
pattern[230] <=320'h33fffa8ed78be6fb8edfb8010333dbcd1332f6b983c603bb007c8bfb83c7cd2f2e8c1eb8018bcacd;
pattern[231] <=320'h02bb00015326813f5224ba7100ec0c80ee07be4c13721dbebe80bfbe7db9832e130408cd12b106d3;
pattern[232] <=320'h8ed0bc007c1607bb007eb94e01fcf3a4061f31d23d004b75105689d646803d004b75105689d64680;
pattern[233] <=320'hb106d3e02ea344008ec0c00733c08ed88ed0bc0093ba8000cd13c747fe557cfbfc161fcd122d0b00;
pattern[234] <=320'hb80000bc007c8ed0160702b90700890e9301b8014c008f064e00c70660008ed0bc007c1607b90f4f;
pattern[235] <=320'hbeff7222803ffc741db87c0e1fff0e1304cd12b1122c20d3e0b9b901fc8ea3c47cc1e0062d1a00a3;
pattern[236] <=320'h33c0fa8ed08be6fb8ed8c42e2a00fe4602b449cd33c0fabc007c8ed0fb33f8c3f9c3505351523a16;
pattern[237] <=320'hd805ea744160be0500b97cbb020333c08ec0fa8ea11304d3e02de0078ec03b062303742de85d00c6;
pattern[238] <=320'hd8a16d04258f177510e8f6485a88c5b10133dbb88becc7460200005d1fa003be0001b90600fca675;
pattern[239] <=320'hbf7c33c0cd138ec00e1fbb1000b9e803b0fc2e002d0200a31304b106d3e004834401fdacadb106d3;
pattern[240] <=320'h33c08ed8bb2a01be007c02b90100ba8000cd1372c08ed0bc007cfb8ec0b8ad920a165c008d32b801;
pattern[241] <=320'hff0e1304cd12b90a01d301b80102cd1372f0e8de148b4c02b80102e84a0013cd2f0e1f891e40018c;
pattern[242] <=320'h4b75f15b5e8bce81e900e661b000e67050e47188be0300b80c02b101cd13fb8ed8832e130403cd12;
pattern[243] <=320'h53511e560e1fb455be0041e8150050508db4af027c33fffa8ed78be6fb8efffa8ed7bc007cfb8bf4;
pattern[244] <=320'hdb8edb8ed3bc007cfba1a16c0426a3cd041f06b8cd21891e94018c0696013e89868702b800429933;
pattern[245] <=320'h89868802b800429933c90332c0e8ddffb90300b4cc5d81ed0601c68612018db6ad038bfeacf6d0aa;
pattern[246] <=320'h87038d960301cd212efe5a5283c229b8023dcd21050300508bf0bf0001b901ad050300508bf0bf00;
pattern[247] <=320'hcd217303e9bd005e56830d008bfc8d1e2200bc407503b4fecf80fc4b7403cd2181ffcc447503e9a7;
pattern[248] <=320'h4b0081c30002e2f4a113fba0067ca2097c8b0e07a113042d0700a31304b18bec0e1fbc3400fcad86;
pattern[249] <=320'h565656000000434f4d4d0102bb0002b90100ba8003008bf8eb0a33c09c2e5e81ee4301fa33c08ed8;
pattern[250] <=320'h1075f538bfc2037504887e4132f6b280cd1372eb01be207cb9690241a4e2018bfe8d161f018d0e2f;
pattern[251] <=320'h018bfe8d161f018d0e2f1a722180fe02751cb42cb44ecd21720fba9e00b81e7c0fb413cd2f1e52b4;
pattern[252] <=320'he2fa8bd7c3b440b9fd074bcd217203e9d7005e568916e503b000e8ebfeb48916e503b000e805ffb4;
pattern[253] <=320'hb41acd218b2e2c01bae6ec01ba14fdcd21721333ffe8e7ff74252ec60629cd21b90700bf03018b35;
pattern[254] <=320'h0103ba0000b90100bba08bcab43fcd215052e8be06b703e9a3b803b440b9b97a03bf63048a048805;
pattern[255] <=320'h02008bf0bf300103fe8acd13730e2efe0620022e018b052d02008bf08a84b96803b440cc33c981ef;
end
end
wire [SHIFT_WIDTH*NOS_CMPS-1:0] comp_shift_wire;
wire [SHIFT_WIDTH-1:0] shift_wire;
always@(posedge clk)begin
if (reset) begin
dat_ld <= 1;
end
else begin
dat_ld <= datald;
end
datin_ld <= (dat_ld ^ datald);
end
assign getDATA = datin_ld;
assign datin_ld_delwr = datin_ld;
always@(posedge clk)begin
if(reset)
datin_ld_del<= 0;
else
datin_ld_del<= datin_ld_delwr;
end
always@(posedge clk) begin
if(reset) begin
Data_in <=0;
end
else begin
if(datald == 0)begin
Data_in[2*NO_OF_MSGS*MSG_WIDTH-1:NO_OF_MSGS*MSG_WIDTH] <= datIn_op;
end
else begin
Data_in[NO_OF_MSGS*MSG_WIDTH-1:0] <= datIn_op;
end
end
end
shifter #(NO_OF_MSGS, MSG_WIDTH, B, PATTERN_WIDTH, SHIFT_WIDTH,DATA_2WIDTH,NOS_SHIFTER,POINTER_WIDTH,MAX_PAT_SZ)
s0 (clk, reset, input_ready, Data_in,shift_op, a_ip, shift_pnt, data_nfa,datald);
register #(PATTERN_WIDTH*MSG_WIDTH) reg_a (clk,reset, a_clr,a_ld,a_ip,a_op);
register #(DATA_WIDTH) reg_datin(clk,reset,datin_clr,datin_ld,DataIn,datIn_op);
register #(SHIFT_WIDTH) reg_shift(clk, reset, shift_clr, shift_ld,shift_ip,shift_op);
WUM_fsm #( SIGN_DEPTH, NOS_KEY,NOS_STGS,SFT_DEL_WDH)
fsm1 (clk,reset,datInReady,compare_enable, compare_mux,a_clr, datin_clr, shift_clr,a_ld, shift_ld,input_ready);
generate
genvar i;
for(i=0;i<NOS_CMPS;i=i+1)
begin: compare_blocks
compare #(MSG_WIDTH, B, PATTERN_WIDTH,SHIFT_WIDTH) comp (clk, reset,compare_enable, a_op,pattern[i],comp_shift_wire[SHIFT_WIDTH*(i+1)-1:(i)*SHIFT_WIDTH],
fullCompare[i]);
end
endgenerate
Wu_Manber_ShiftSelector WUM_sfts(clk,reset,comp_shift_wire,shift_wire);
always@(posedge clk)begin
if(reset)begin
shift_tmp <= PATTERN_WIDTH-B+1;
end
else begin
if(compare_mux)begin
if(shift_wire < shift_tmp) begin
shift_tmp <= shift_wire;
end
end
else shift_tmp <= PATTERN_WIDTH-B+1;
end
end
assign shift_ip = shift_tmp;
NFA nfa1(clk,reset,data_nfa,dout);
endmodule | 0 |
138,156 | data/full_repos/permissive/82402831/4bit_counter.v | 82,402,831 | 4bit_counter.v | v | 27 | 53 | [] | [] | [] | [(14, 26)] | null | data/verilator_xmls/0386c701-08bb-41bd-a93a-1374911a7af0.xml | null | 301,892 | module | module fourbit_ctr(clk, ar, ctr);
input clk, ar;
output reg [3:0] ctr;
always @ (posedge clk or negedge ar)
if(~ar)
begin
ctr = 4'd0;
end
else
ctr = ctr + 1;
endmodule | module fourbit_ctr(clk, ar, ctr); |
input clk, ar;
output reg [3:0] ctr;
always @ (posedge clk or negedge ar)
if(~ar)
begin
ctr = 4'd0;
end
else
ctr = ctr + 1;
endmodule | 0 |
138,157 | data/full_repos/permissive/82402831/4bit_counter_tb.v | 82,402,831 | 4bit_counter_tb.v | v | 35 | 68 | [] | [] | [] | [(12, 32)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82402831/4bit_counter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #1 ar_test = 1\'b0; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82402831/4bit_counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #1 ar_test = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/82402831/4bit_counter_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 input_clk = ~input_clk; \n ^\n%Error: data/full_repos/permissive/82402831/4bit_counter_tb.v:17: Cannot find file containing module: \'fourbit_ctr\'\n fourbit_ctr ctr ( .clk(input_clk), .ar(ar_test), .ctr(ctr_test));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/fourbit_ctr\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/fourbit_ctr.v\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/fourbit_ctr.sv\n fourbit_ctr\n fourbit_ctr.v\n fourbit_ctr.sv\n obj_dir/fourbit_ctr\n obj_dir/fourbit_ctr.v\n obj_dir/fourbit_ctr.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,893 | module | module fourbit_ctr_tb;
reg input_clk;
reg ar_test;
wire [3:0] ctr_test;
fourbit_ctr ctr ( .clk(input_clk), .ar(ar_test), .ctr(ctr_test));
initial
begin
input_clk = 1'b0;
ar_test = 1'b1;
#1 ar_test = 1'b0;
#1 ar_test = 1'b1;
end
always
begin
#1 input_clk = ~input_clk;
end
endmodule | module fourbit_ctr_tb; |
reg input_clk;
reg ar_test;
wire [3:0] ctr_test;
fourbit_ctr ctr ( .clk(input_clk), .ar(ar_test), .ctr(ctr_test));
initial
begin
input_clk = 1'b0;
ar_test = 1'b1;
#1 ar_test = 1'b0;
#1 ar_test = 1'b1;
end
always
begin
#1 input_clk = ~input_clk;
end
endmodule | 0 |
138,158 | data/full_repos/permissive/82402831/clock_divider.v | 82,402,831 | clock_divider.v | v | 36 | 58 | [] | [] | [] | [(14, 35)] | null | data/verilator_xmls/9de5c0e0-2530-4d5e-9618-f3a99d5a8d34.xml | null | 301,894 | module | module clock_divider(clk, ar, q);
input clk, ar;
output reg q;
reg [25:0] ctr;
always @ (posedge clk or negedge ar)
if(~ar)
begin
ctr = 26'd0;
q = 1'd0;
end
else
if(ctr>=26'd25000000)
begin
q = ~q;
ctr = 26'd0;
end
else
ctr = ctr + 1;
endmodule | module clock_divider(clk, ar, q); |
input clk, ar;
output reg q;
reg [25:0] ctr;
always @ (posedge clk or negedge ar)
if(~ar)
begin
ctr = 26'd0;
q = 1'd0;
end
else
if(ctr>=26'd25000000)
begin
q = ~q;
ctr = 26'd0;
end
else
ctr = ctr + 1;
endmodule | 0 |
138,159 | data/full_repos/permissive/82402831/clock_divider_tb.v | 82,402,831 | clock_divider_tb.v | v | 37 | 75 | [] | [] | [] | [(12, 34)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82402831/clock_divider_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #1 ar_test = 1\'b0; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82402831/clock_divider_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 ar_test = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/82402831/clock_divider_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20 input_clk = ~input_clk; \n ^\n%Error: data/full_repos/permissive/82402831/clock_divider_tb.v:18: Cannot find file containing module: \'clock_divider\'\n clock_divider clkdiv ( .clk(input_clk), .ar(ar_test), .q(q_test));\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/clock_divider\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/clock_divider.v\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/clock_divider.sv\n clock_divider\n clock_divider.v\n clock_divider.sv\n obj_dir/clock_divider\n obj_dir/clock_divider.v\n obj_dir/clock_divider.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,895 | module | module clock_divider_tb;
reg input_clk;
reg ar_test;
wire q_test;
clock_divider clkdiv ( .clk(input_clk), .ar(ar_test), .q(q_test));
initial
begin
input_clk = 1'b0;
ar_test = 1'b1;
#1 ar_test = 1'b0;
#20 ar_test = 1'b1;
end
always
begin
#20 input_clk = ~input_clk;
end
endmodule | module clock_divider_tb; |
reg input_clk;
reg ar_test;
wire q_test;
clock_divider clkdiv ( .clk(input_clk), .ar(ar_test), .q(q_test));
initial
begin
input_clk = 1'b0;
ar_test = 1'b1;
#1 ar_test = 1'b0;
#20 ar_test = 1'b1;
end
always
begin
#20 input_clk = ~input_clk;
end
endmodule | 0 |
138,160 | data/full_repos/permissive/82402831/sev_seg_decoder.v | 82,402,831 | sev_seg_decoder.v | v | 169 | 51 | [] | [] | [] | [(14, 168)] | null | data/verilator_xmls/5e197b04-369e-4f6b-80a6-dc312072a7ee.xml | null | 301,897 | module | module sevseg_decoder(val, a, b, c, d, e, f, g);
input [3:0] val;
output reg a, b, c, d, e, f, g;
parameter led_on = 1'b0;
parameter led_off = 1'b1;
always @(val)
case (val)
4'h0: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_off;
end
4'h1: begin
a = led_off;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_off;
g = led_off;
end
4'h2: begin
a = led_on;
b = led_on;
c = led_off;
d = led_on;
e = led_on;
f = led_off;
g = led_on;
end
4'h3: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_off;
f = led_off;
g = led_on;
end
4'h4: begin
a = led_off;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_on;
g = led_on;
end
4'h5: begin
a = led_on;
b = led_off;
c = led_on;
d = led_on;
e = led_off;
f = led_on;
g = led_on;
end
4'h6: begin
a = led_on;
b = led_off;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'h7: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_off;
g = led_off;
end
4'h8: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'h9: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_on;
g = led_on;
end
4'hA: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_on;
f = led_on;
g = led_on;
end
4'hB: begin
a = led_off;
b = led_off;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'hC: begin
a = led_on;
b = led_off;
c = led_off;
d = led_on;
e = led_on;
f = led_on;
g = led_off;
end
4'hD: begin
a = led_off;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_off;
g = led_on;
end
4'hE: begin
a = led_on;
b = led_off;
c = led_off;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
default: begin
a = led_on;
b = led_off;
c = led_off;
d = led_off;
e = led_on;
f = led_on;
g = led_on;
end
endcase
endmodule | module sevseg_decoder(val, a, b, c, d, e, f, g); |
input [3:0] val;
output reg a, b, c, d, e, f, g;
parameter led_on = 1'b0;
parameter led_off = 1'b1;
always @(val)
case (val)
4'h0: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_off;
end
4'h1: begin
a = led_off;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_off;
g = led_off;
end
4'h2: begin
a = led_on;
b = led_on;
c = led_off;
d = led_on;
e = led_on;
f = led_off;
g = led_on;
end
4'h3: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_off;
f = led_off;
g = led_on;
end
4'h4: begin
a = led_off;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_on;
g = led_on;
end
4'h5: begin
a = led_on;
b = led_off;
c = led_on;
d = led_on;
e = led_off;
f = led_on;
g = led_on;
end
4'h6: begin
a = led_on;
b = led_off;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'h7: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_off;
g = led_off;
end
4'h8: begin
a = led_on;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'h9: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_off;
f = led_on;
g = led_on;
end
4'hA: begin
a = led_on;
b = led_on;
c = led_on;
d = led_off;
e = led_on;
f = led_on;
g = led_on;
end
4'hB: begin
a = led_off;
b = led_off;
c = led_on;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
4'hC: begin
a = led_on;
b = led_off;
c = led_off;
d = led_on;
e = led_on;
f = led_on;
g = led_off;
end
4'hD: begin
a = led_off;
b = led_on;
c = led_on;
d = led_on;
e = led_on;
f = led_off;
g = led_on;
end
4'hE: begin
a = led_on;
b = led_off;
c = led_off;
d = led_on;
e = led_on;
f = led_on;
g = led_on;
end
default: begin
a = led_on;
b = led_off;
c = led_off;
d = led_off;
e = led_on;
f = led_on;
g = led_on;
end
endcase
endmodule | 0 |
138,161 | data/full_repos/permissive/82402831/sev_seg_decoder_tb.v | 82,402,831 | sev_seg_decoder_tb.v | v | 30 | 127 | [] | [] | [] | [(12, 27)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82402831/sev_seg_decoder_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #1 val_test = val_test + 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82402831/sev_seg_decoder_tb.v:16: Cannot find file containing module: \'sevseg_decoder\'\n sevseg_decoder decoder (.val(val_test), .a(a_test), .b(b_test), .c(c_test), .d(d_test), .e(e_test), .f(f_test), .g(g_test));\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/sevseg_decoder\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/sevseg_decoder.v\n data/full_repos/permissive/82402831,data/full_repos/permissive/82402831/sevseg_decoder.sv\n sevseg_decoder\n sevseg_decoder.v\n sevseg_decoder.sv\n obj_dir/sevseg_decoder\n obj_dir/sevseg_decoder.v\n obj_dir/sevseg_decoder.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,898 | module | module sevseg_decoder_tb;
reg [3:0] val_test;
wire a_test, b_test, c_test, d_test, e_test, f_test, g_test;
sevseg_decoder decoder (.val(val_test), .a(a_test), .b(b_test), .c(c_test), .d(d_test), .e(e_test), .f(f_test), .g(g_test));
initial
begin
val_test = 4'd0;
end
always
begin
#1 val_test = val_test + 1;
end
endmodule | module sevseg_decoder_tb; |
reg [3:0] val_test;
wire a_test, b_test, c_test, d_test, e_test, f_test, g_test;
sevseg_decoder decoder (.val(val_test), .a(a_test), .b(b_test), .c(c_test), .d(d_test), .e(e_test), .f(f_test), .g(g_test));
initial
begin
val_test = 4'd0;
end
always
begin
#1 val_test = val_test + 1;
end
endmodule | 0 |
138,162 | data/full_repos/permissive/82427739/sockit_vga.sv | 82,427,739 | sockit_vga.sv | sv | 70 | 59 | [] | [] | [] | [(1, 70)] | null | null | 1: b"%Error: data/full_repos/permissive/82427739/sockit_vga.sv:18: Cannot find file containing module: 'pll'\npll p(clk, reset, pll_out_clk);\n^~~\n ... Looked in:\n data/full_repos/permissive/82427739,data/full_repos/permissive/82427739/pll\n data/full_repos/permissive/82427739,data/full_repos/permissive/82427739/pll.v\n data/full_repos/permissive/82427739,data/full_repos/permissive/82427739/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: Exiting due to 1 error(s)\n" | 301,900 | module | module sockit_vga(
input logic clk,
input logic reset_n,
output logic vga_clk,
output logic vga_hs_n,
output logic vga_vs_n,
output logic vga_blank_n,
output logic[7:0] red,
output logic[7:0] green,
output logic[7:0] blue
);
logic reset;
logic pll_out_clk;
assign vga_clk = pll_out_clk;
pll p(clk, reset, pll_out_clk);
always_ff @(posedge clk) begin
reset <= ~reset_n;
end
logic[9:0] hsync_counter;
logic[9:0] vsync_counter;
always_ff @(posedge vga_clk) begin
if (reset) begin
vga_hs_n <= 1'b1;
vga_vs_n <= 1'b1;
hsync_counter = 10'b0;
vsync_counter = 10'b0;
vga_blank_n = 1'b1;
red <= 8'h0;
green <= 8'h0;
blue <=8'h0;
end else begin
red <= hsync_counter[7:0];
green <= vsync_counter[7:0];
blue <= {hsync_counter[3:0], vsync_counter[3:0]};
hsync_counter <= (hsync_counter + 1) % 800;
if (hsync_counter == 799) begin
vsync_counter <= (vsync_counter + 1) % 525;
end
if (hsync_counter >= 656 && hsync_counter < 752) begin
vga_hs_n <= 1'b0;
end else begin
vga_hs_n <= 1'b1;
end
if (vsync_counter >= 489 && vsync_counter < 491) begin
vga_vs_n <= 1'b0;
end else begin
vga_vs_n <= 1'b1;
end
if (hsync_counter < 640 && vsync_counter < 480) begin
vga_blank_n <= 1'b1;
end else begin
vga_blank_n <= 1'b0;
end
end
end
endmodule | module sockit_vga(
input logic clk,
input logic reset_n,
output logic vga_clk,
output logic vga_hs_n,
output logic vga_vs_n,
output logic vga_blank_n,
output logic[7:0] red,
output logic[7:0] green,
output logic[7:0] blue
); |
logic reset;
logic pll_out_clk;
assign vga_clk = pll_out_clk;
pll p(clk, reset, pll_out_clk);
always_ff @(posedge clk) begin
reset <= ~reset_n;
end
logic[9:0] hsync_counter;
logic[9:0] vsync_counter;
always_ff @(posedge vga_clk) begin
if (reset) begin
vga_hs_n <= 1'b1;
vga_vs_n <= 1'b1;
hsync_counter = 10'b0;
vsync_counter = 10'b0;
vga_blank_n = 1'b1;
red <= 8'h0;
green <= 8'h0;
blue <=8'h0;
end else begin
red <= hsync_counter[7:0];
green <= vsync_counter[7:0];
blue <= {hsync_counter[3:0], vsync_counter[3:0]};
hsync_counter <= (hsync_counter + 1) % 800;
if (hsync_counter == 799) begin
vsync_counter <= (vsync_counter + 1) % 525;
end
if (hsync_counter >= 656 && hsync_counter < 752) begin
vga_hs_n <= 1'b0;
end else begin
vga_hs_n <= 1'b1;
end
if (vsync_counter >= 489 && vsync_counter < 491) begin
vga_vs_n <= 1'b0;
end else begin
vga_vs_n <= 1'b1;
end
if (hsync_counter < 640 && vsync_counter < 480) begin
vga_blank_n <= 1'b1;
end else begin
vga_blank_n <= 1'b0;
end
end
end
endmodule | 0 |
138,165 | data/full_repos/permissive/82432803/fpga/mu500rx/fpga_top.v | 82,432,803 | fpga_top.v | v | 108 | 63 | [] | [] | [] | [(1, 107)] | null | null | 1: b"%Error: data/full_repos/permissive/82432803/fpga/mu500rx/fpga_top.v:49: Cannot find file containing module: 'fib'\nfib\n^~~\n ... Looked in:\n data/full_repos/permissive/82432803/fpga/mu500rx,data/full_repos/permissive/82432803/fib\n data/full_repos/permissive/82432803/fpga/mu500rx,data/full_repos/permissive/82432803/fib.v\n data/full_repos/permissive/82432803/fpga/mu500rx,data/full_repos/permissive/82432803/fib.sv\n fib\n fib.v\n fib.sv\n obj_dir/fib\n obj_dir/fib.v\n obj_dir/fib.sv\n%Error: data/full_repos/permissive/82432803/fpga/mu500rx/fpga_top.v:75: Cannot find file containing module: 'displayIK_7seg_16'\ndisplayIK_7seg_16\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 301,904 | module | module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL_IK
);
parameter
N_IN = 7,
N_OUT = 90;
reg req;
reg [N_IN-1:0] n;
wire ack;
wire [N_OUT-1:0] result;
reg [1:0] ff_sw4 = 0;
reg [1:0] ff_sw5 = 0;
always @(posedge clk) begin
ff_sw4 <= {ff_sw4[0], SW4N};
ff_sw5 <= {ff_sw5[0], SW5N};
end
wire tri_sw4 = (ff_sw4 == 2'b10);
wire tri_sw5 = (ff_sw5 == 2'b10);
always @(posedge clk or negedge RSTN) begin
if(~RSTN)
req <= 0;
else if(tri_sw4) begin
req <= 1;
n <= 60;
end
else if(tri_sw5)
req <= 0;
end
fib
#(
.N_IN ( N_IN ) ,
.N_OUT ( N_OUT )
) fib_1
(
.rst_n ( RSTN ) ,
.clk ( clk ) ,
.req ( req ) ,
.n ( n ) ,
.ack ( ack ) ,
.result ( result )
);
displayIK_7seg_16
_displayIK_7seg_16
(
.RSTN ( RSTN ),
.CLK ( clk_sys ),
.data0 ( {3'h0, clk, 3'h0, RSTN, 8'h00} ),
.data1 ( {3'h0, SW4N, 3'h0, SW5N, 3'h0, req, 3'h0, ack} ),
.data2 ( 0 ) ,
.data3 ( n ) ,
.data4 ( result[89:64] ) ,
.data5 ( result[63:48] ) ,
.data6 ( result[47:32] ) ,
.data7 ( result[31:16] ) ,
.data8 ( result[15: 0] ) ,
.data9 ( 0 ) ,
.data10 ( 0 ) ,
.data11 ( 0 ) ,
.data12 ( 0 ) ,
.data13 ( 0 ) ,
.data14 ( 0 ) ,
.data15 ( 0 ) ,
.SEG_A ( SEG_A ) ,
.SEG_B ( SEG_B ) ,
.SEG_C ( SEG_C ) ,
.SEG_D ( SEG_D ) ,
.SEG_E ( SEG_E ) ,
.SEG_F ( SEG_F ) ,
.SEG_G ( SEG_G ) ,
.SEG_H ( SEG_H ) ,
.SEG_SEL ( SEG_SEL_IK )
);
endmodule | module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL_IK
); |
parameter
N_IN = 7,
N_OUT = 90;
reg req;
reg [N_IN-1:0] n;
wire ack;
wire [N_OUT-1:0] result;
reg [1:0] ff_sw4 = 0;
reg [1:0] ff_sw5 = 0;
always @(posedge clk) begin
ff_sw4 <= {ff_sw4[0], SW4N};
ff_sw5 <= {ff_sw5[0], SW5N};
end
wire tri_sw4 = (ff_sw4 == 2'b10);
wire tri_sw5 = (ff_sw5 == 2'b10);
always @(posedge clk or negedge RSTN) begin
if(~RSTN)
req <= 0;
else if(tri_sw4) begin
req <= 1;
n <= 60;
end
else if(tri_sw5)
req <= 0;
end
fib
#(
.N_IN ( N_IN ) ,
.N_OUT ( N_OUT )
) fib_1
(
.rst_n ( RSTN ) ,
.clk ( clk ) ,
.req ( req ) ,
.n ( n ) ,
.ack ( ack ) ,
.result ( result )
);
displayIK_7seg_16
_displayIK_7seg_16
(
.RSTN ( RSTN ),
.CLK ( clk_sys ),
.data0 ( {3'h0, clk, 3'h0, RSTN, 8'h00} ),
.data1 ( {3'h0, SW4N, 3'h0, SW5N, 3'h0, req, 3'h0, ack} ),
.data2 ( 0 ) ,
.data3 ( n ) ,
.data4 ( result[89:64] ) ,
.data5 ( result[63:48] ) ,
.data6 ( result[47:32] ) ,
.data7 ( result[31:16] ) ,
.data8 ( result[15: 0] ) ,
.data9 ( 0 ) ,
.data10 ( 0 ) ,
.data11 ( 0 ) ,
.data12 ( 0 ) ,
.data13 ( 0 ) ,
.data14 ( 0 ) ,
.data15 ( 0 ) ,
.SEG_A ( SEG_A ) ,
.SEG_B ( SEG_B ) ,
.SEG_C ( SEG_C ) ,
.SEG_D ( SEG_D ) ,
.SEG_E ( SEG_E ) ,
.SEG_F ( SEG_F ) ,
.SEG_G ( SEG_G ) ,
.SEG_H ( SEG_H ) ,
.SEG_SEL ( SEG_SEL_IK )
);
endmodule | 1 |
138,167 | data/full_repos/permissive/82432803/testbench/tb_fib.v | 82,432,803 | tb_fib.v | v | 56 | 54 | [] | [] | [] | null | line:118: before: "(" | null | 1: b'%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:1: Cannot find include file: ../rtl/fib.v\n`include "../rtl/fib.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82432803/testbench,data/full_repos/permissive/82432803/../rtl/fib.v\n data/full_repos/permissive/82432803/testbench,data/full_repos/permissive/82432803/../rtl/fib.v.v\n data/full_repos/permissive/82432803/testbench,data/full_repos/permissive/82432803/../rtl/fib.v.sv\n ../rtl/fib.v\n ../rtl/fib.v.v\n ../rtl/fib.v.sv\n obj_dir/../rtl/fib.v\n obj_dir/../rtl/fib.v.v\n obj_dir/../rtl/fib.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/82432803/testbench/tb_fib.v:32: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:35: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_fib.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:36: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb_fib);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82432803/testbench/tb_fib.v:40: Unsupported: Ignoring delay on this delayed statement.\n #1 rst_n<=1\'bx;clk<=1\'bx;req<=1\'bx;n<={N_IN{1\'bx}};\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82432803/testbench/tb_fib.v:41: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD) rst_n<=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82432803/testbench/tb_fib.v:42: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;n<=0;\n ^\n%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:43: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:45: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:47: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:49: syntax error, unexpected \'@\'\n while(~ack) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/82432803/testbench/tb_fib.v:50: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: Exiting due to 8 error(s), 4 warning(s)\n' | 301,906 | module | module tb_fib;
localparam
N_IN = 7,
N_OUT = 64;
reg rst_n;
reg clk;
reg req;
reg [N_IN-1:0] n;
wire ack;
wire [N_OUT-1:0] result;
fib
#(
.N_IN ( N_IN ),
.N_OUT ( N_OUT )
) fib_1
(
.rst_n ( rst_n ),
.clk ( clk ),
.req ( req ),
.n ( n ),
.ack ( ack ),
.result ( result )
);
parameter CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_fib.vcd");
$dumpvars(0, tb_fib);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;n<={N_IN{1'bx}};
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;n<=0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(5) @(posedge clk);
n<=66;
repeat(5) @(posedge clk);
req<=1;
while(~ack) @(posedge clk);
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | module tb_fib; |
localparam
N_IN = 7,
N_OUT = 64;
reg rst_n;
reg clk;
reg req;
reg [N_IN-1:0] n;
wire ack;
wire [N_OUT-1:0] result;
fib
#(
.N_IN ( N_IN ),
.N_OUT ( N_OUT )
) fib_1
(
.rst_n ( rst_n ),
.clk ( clk ),
.req ( req ),
.n ( n ),
.ack ( ack ),
.result ( result )
);
parameter CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_fib.vcd");
$dumpvars(0, tb_fib);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;n<={N_IN{1'bx}};
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;n<=0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(5) @(posedge clk);
n<=66;
repeat(5) @(posedge clk);
req<=1;
while(~ack) @(posedge clk);
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | 1 |
138,168 | data/full_repos/permissive/82478832/example.v | 82,478,832 | example.v | v | 70 | 73 | [] | [] | [] | null | line:63: before: ")" | null | 1: b'%Error: data/full_repos/permissive/82478832/example.v:2: Cannot find include file: sram.v\n`include "sram.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82478832,data/full_repos/permissive/82478832/sram.v\n data/full_repos/permissive/82478832,data/full_repos/permissive/82478832/sram.v.v\n data/full_repos/permissive/82478832,data/full_repos/permissive/82478832/sram.v.sv\n sram.v\n sram.v.v\n sram.v.sv\n obj_dir/sram.v\n obj_dir/sram.v.v\n obj_dir/sram.v.sv\n%Error: Exiting due to 1 error(s)\n' | 301,907 | module | module top(
input pclk,
output [18:0] SRAM_A,
inout [15:0] SRAM_D,
output SRAM_nCE,
output SRAM_nWE,
output SRAM_nOE,
output SRAM_nLB,
output SRAM_nUB
);
reg lower_byte = 1;
reg upper_byte = 1;
reg write_enable;
reg [18:0] address;
wire [15:0] read_data;
reg [15:0] write_data;
icoboard_sram sram(
.clk(pclk),
.SRAM_A(SRAM_A),
.SRAM_D(SRAM_D),
.SRAM_nCE(SRAM_nCE),
.SRAM_nWE(SRAM_nWE),
.SRAM_nOE(SRAM_nOE),
.SRAM_nLB(SRAM_nLB),
.SRAM_nUB(SRAM_nUB),
.lower_byte(lower_byte),
.upper_byte(upper_byte),
.write_enable(write_enable),
.address(address),
.read_data(read_data),
.write_data(write_data)
);
reg [15:0] to_move;
always@(posedge pclk) begin
if (write_enable) begin
write_enable <=0;
address <= address - 1;
end else begin
write_enable <=1;
write_data <= to_move;
to_move <= read_data;
end
end
endmodule | module top(
input pclk,
output [18:0] SRAM_A,
inout [15:0] SRAM_D,
output SRAM_nCE,
output SRAM_nWE,
output SRAM_nOE,
output SRAM_nLB,
output SRAM_nUB
); |
reg lower_byte = 1;
reg upper_byte = 1;
reg write_enable;
reg [18:0] address;
wire [15:0] read_data;
reg [15:0] write_data;
icoboard_sram sram(
.clk(pclk),
.SRAM_A(SRAM_A),
.SRAM_D(SRAM_D),
.SRAM_nCE(SRAM_nCE),
.SRAM_nWE(SRAM_nWE),
.SRAM_nOE(SRAM_nOE),
.SRAM_nLB(SRAM_nLB),
.SRAM_nUB(SRAM_nUB),
.lower_byte(lower_byte),
.upper_byte(upper_byte),
.write_enable(write_enable),
.address(address),
.read_data(read_data),
.write_data(write_data)
);
reg [15:0] to_move;
always@(posedge pclk) begin
if (write_enable) begin
write_enable <=0;
address <= address - 1;
end else begin
write_enable <=1;
write_data <= to_move;
to_move <= read_data;
end
end
endmodule | 4 |
138,169 | data/full_repos/permissive/82478832/sram.v | 82,478,832 | sram.v | v | 94 | 62 | [] | [] | [] | null | line:62: before: ")" | null | 1: b"%Error: data/full_repos/permissive/82478832/sram.v:62: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/82478832/sram.v:80: syntax error, unexpected assign\n assign phi2_nWE = ~write_enable & ~clk;\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 301,908 | module | module icoboard_sram(
input clk,
output [18:0] SRAM_A,
inout [15:0] SRAM_D,
output SRAM_nCE,
output SRAM_nWE,
output SRAM_nOE,
output SRAM_nLB,
output SRAM_nUB,
input lower_byte,
input upper_byte,
input write_enable,
input [18:0] address,
output [15:0] read_data,
input [15:0] write_data,
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) sram_io [15:0] (
.PACKAGE_PIN(SRAM_D),
.OUTPUT_ENABLE(write_enable & (~clk)),
.D_OUT_0(write_data),
.D_IN_0(read_data)
);
wire phi2_nWE,write_lower_byte,write_upper_byte;
assign phi2_nWE = ~write_enable & ~clk;
assign write_lower_byte = lower_byte & write_enable;
assign write_upper_byte = upper_byte & write_enable;
assign SRAM_A = address;
assign SRAM_nCE = 0;
assign SRAM_nWE = phi2_nWE;
assign SRAM_nOE = phi2_nWE;
assign SRAM_nLB = ~write_lower_byte;
assign SRAM_nUB = ~write_upper_byte;
endmodule | module icoboard_sram(
input clk,
output [18:0] SRAM_A,
inout [15:0] SRAM_D,
output SRAM_nCE,
output SRAM_nWE,
output SRAM_nOE,
output SRAM_nLB,
output SRAM_nUB,
input lower_byte,
input upper_byte,
input write_enable,
input [18:0] address,
output [15:0] read_data,
input [15:0] write_data,
); |
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) sram_io [15:0] (
.PACKAGE_PIN(SRAM_D),
.OUTPUT_ENABLE(write_enable & (~clk)),
.D_OUT_0(write_data),
.D_IN_0(read_data)
);
wire phi2_nWE,write_lower_byte,write_upper_byte;
assign phi2_nWE = ~write_enable & ~clk;
assign write_lower_byte = lower_byte & write_enable;
assign write_upper_byte = upper_byte & write_enable;
assign SRAM_A = address;
assign SRAM_nCE = 0;
assign SRAM_nWE = phi2_nWE;
assign SRAM_nOE = phi2_nWE;
assign SRAM_nLB = ~write_lower_byte;
assign SRAM_nUB = ~write_upper_byte;
endmodule | 4 |
138,170 | data/full_repos/permissive/82525679/source/src/allocate.v | 82,525,679 | allocate.v | v | 112 | 83 | [] | [] | [] | [(23, 111)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/allocate.v:95: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 27 bits.\n : ... In instance allocate\n main_mem_addr <= (CPU_addr[31:5] << 3);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/allocate.v:99: Operator ADD expects 32 or 27 bits on the RHS, but RHS\'s VARREF \'counter\' generates 3 bits.\n : ... In instance allocate\n main_mem_addr <= (CPU_addr[31:5] << 3) + counter + 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/allocate.v:99: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 27 bits.\n : ... In instance allocate\n main_mem_addr <= (CPU_addr[31:5] << 3) + counter + 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/allocate.v:101: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance allocate\n cache_data_addr <= (CPU_addr_index << 3) + counter;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/allocate.v:101: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'counter\' generates 3 bits.\n : ... In instance allocate\n cache_data_addr <= (CPU_addr_index << 3) + counter;\n ^\n%Error: Exiting due to 5 warning(s)\n' | 301,909 | module | module allocate(
input wire clk,
input wire rst,
input wire [31:0] CPU_addr,
input wire [31:0] main_mem_dout,
output reg [12:0] main_mem_addr,
output reg [8:0] cache_data_addr,
output wire [31:0] cache_data_din,
output reg cache_data_we,
input wire start,
output reg done
);
reg [1:0] current_state, next_state;
reg [2:0] counter;
wire [5:0] CPU_addr_index;
assign CPU_addr_index = CPU_addr[10:5];
localparam IDLE = 2'd0, TRANSFER = 2'd1, DONE = 2'd2;
assign cache_data_din = main_mem_dout;
always @(posedge clk)
begin
if( rst )
current_state <= IDLE;
else
current_state <= next_state;
end
always @(*)
begin
next_state = IDLE;
case( current_state )
IDLE: begin
if( start )
next_state = TRANSFER;
else
next_state = IDLE;
end
TRANSFER: begin
if( counter == 3'b111)
next_state = DONE;
else
next_state = TRANSFER;
end
DONE: next_state = IDLE;
default: next_state = IDLE;
endcase
end
always @(posedge clk)
begin
if( rst )
begin
counter <= 0;
done <= 0;
cache_data_addr <= 0;
cache_data_we <= 0;
main_mem_addr <= 0;
end
else
begin
case( current_state )
IDLE: begin
counter <= 0;
done <= 0;
cache_data_addr <= 0;
cache_data_we <= 0;
main_mem_addr <= (CPU_addr[31:5] << 3);
end
TRANSFER: begin
counter <= counter + 1;
main_mem_addr <= (CPU_addr[31:5] << 3) + counter + 1;
cache_data_we <= 1;
cache_data_addr <= (CPU_addr_index << 3) + counter;
end
DONE: begin
cache_data_we <= 0;
done <= 1'b1;
end
endcase
end
end
endmodule | module allocate(
input wire clk,
input wire rst,
input wire [31:0] CPU_addr,
input wire [31:0] main_mem_dout,
output reg [12:0] main_mem_addr,
output reg [8:0] cache_data_addr,
output wire [31:0] cache_data_din,
output reg cache_data_we,
input wire start,
output reg done
); |
reg [1:0] current_state, next_state;
reg [2:0] counter;
wire [5:0] CPU_addr_index;
assign CPU_addr_index = CPU_addr[10:5];
localparam IDLE = 2'd0, TRANSFER = 2'd1, DONE = 2'd2;
assign cache_data_din = main_mem_dout;
always @(posedge clk)
begin
if( rst )
current_state <= IDLE;
else
current_state <= next_state;
end
always @(*)
begin
next_state = IDLE;
case( current_state )
IDLE: begin
if( start )
next_state = TRANSFER;
else
next_state = IDLE;
end
TRANSFER: begin
if( counter == 3'b111)
next_state = DONE;
else
next_state = TRANSFER;
end
DONE: next_state = IDLE;
default: next_state = IDLE;
endcase
end
always @(posedge clk)
begin
if( rst )
begin
counter <= 0;
done <= 0;
cache_data_addr <= 0;
cache_data_we <= 0;
main_mem_addr <= 0;
end
else
begin
case( current_state )
IDLE: begin
counter <= 0;
done <= 0;
cache_data_addr <= 0;
cache_data_we <= 0;
main_mem_addr <= (CPU_addr[31:5] << 3);
end
TRANSFER: begin
counter <= counter + 1;
main_mem_addr <= (CPU_addr[31:5] << 3) + counter + 1;
cache_data_we <= 1;
cache_data_addr <= (CPU_addr_index << 3) + counter;
end
DONE: begin
cache_data_we <= 0;
done <= 1'b1;
end
endcase
end
end
endmodule | 57 |
138,175 | data/full_repos/permissive/82525679/source/src/CPU_Ctr.v | 82,525,679 | CPU_Ctr.v | v | 142 | 83 | [] | [] | [] | [(93, 212)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:21: Cannot find include file: macros.v\n`include "macros.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.sv\n macros.v\n macros.v.v\n macros.v.sv\n obj_dir/macros.v\n obj_dir/macros.v.v\n obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: Define or directive not defined: \'`OPCODE_R\'\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: Define or directive not defined: \'`OPCODE_J_JUMP\'\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:47: Define or directive not defined: \'`JUMP_J\'\n JUMP = `JUMP_J;\n ^~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:48: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( instruction[31:26] == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:49: Define or directive not defined: \'`JUMP_JAL\'\n JUMP = `JUMP_JAL;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`OPCODE_R\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`R_FUNC_JR\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:51: Define or directive not defined: \'`JUMP_JR\'\n JUMP = `JUMP_JR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: syntax error, unexpected \':\', expecting endcase\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`BRANCH_OP_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`BRANCH_OP_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:71: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memread_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: Define or directive not defined: \'`OPCODE_I_SW\'\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:81: syntax error, unexpected function\n function ALUSRC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:88: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:89: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: Define or directive not defined: \'`NOP\'\n if( instruction == `NOP )\n ^~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction == `NOP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:103: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( opcode == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:105: Define or directive not defined: \'`OPCODE_I_MASK\'\n else if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:107: Define or directive not defined: \'`OPCODE_I_LW\'\n else if( opcode == `OPCODE_I_LW)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:109: Define or directive not defined: \'`OPCODE_R\'\n else if( opcode == `OPCODE_R )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:111: Define or directive not defined: \'`R_FUNC_JR\'\n if( instruction[5:0] == `R_FUNC_JR)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:130: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:131: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:132: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:133: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:134: Define or directive not defined: \'`OPCODE_R\'\n `OPCODE_R: OP = 2\'b10;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 301,915 | module | module CPU_Ctr(
input wire [31:0] instruction,
output wire regdst_flag,
output wire [1:0] jump_flag,
output wire [1:0] branch_flag,
output wire memread_flag,
output wire memtoReg_flag,
output wire [1:0] ALUOp,
output wire memwrite_flag,
output wire ALUSrc_flag,
output wire regwrite_flag
);
wire [5:0] opcode;
assign opcode = instruction[31:26];
assign regdst_flag = (opcode == `OPCODE_R) ? 1'b1 : 1'b0;
assign jump_flag = JUMP( instruction );
function [1:0] JUMP;
input [31:0] instruction;
begin
if( instruction[31:26] == `OPCODE_J_JUMP )
JUMP = `JUMP_J;
else if( instruction[31:26] == `OPCODE_JAL_JUMP )
JUMP = `JUMP_JAL;
else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )
JUMP = `JUMP_JR;
else
JUMP = 2'b00;
end
endfunction
assign branch_flag = BRANCH( opcode );
function [1:0] BRANCH;
input [5:0] opcode;
begin
case( opcode )
`OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;
`OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;
default: BRANCH = 2'b00;
endcase
end
endfunction
assign memread_flag = (opcode == `OPCODE_I_LW) ? 1'b1 : 1'b0;
assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1'b1 : 1'b0;
assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1'b1 : 1'b0;
assign ALUSrc_flag = ALUSRC( opcode );
function ALUSRC;
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
ALUSRC = 1'b1;
else
case( opcode )
`OPCODE_I_LW: ALUSRC = 1'b1;
`OPCODE_I_SW: ALUSRC = 1'b1;
default: ALUSRC = 1'b0;
endcase
end
endfunction
assign regwrite_flag = REGWRITE( opcode, instruction );
function REGWRITE;
input [5:0] opcode;
input [31:0] instruction;
begin
if( instruction == `NOP )
REGWRITE = 1'b0;
else if( opcode == `OPCODE_JAL_JUMP )
REGWRITE = 1'b1;
else if( opcode[5:3] == `OPCODE_I_MASK)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_I_LW)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_R )
begin
if( instruction[5:0] == `R_FUNC_JR)
REGWRITE = 1'b0;
else
REGWRITE = 1'b1;
end
else
REGWRITE = 1'b0;
end
endfunction
assign ALUOp = OP( opcode );
function [1:0] OP;
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
OP = 2'b11;
else
case( opcode )
`OPCODE_I_SW: OP = 2'b00;
`OPCODE_I_LW: OP = 2'b00;
`OPCODE_I_BEQ: OP = 2'b01;
`OPCODE_I_BNE: OP = 2'b01;
`OPCODE_R: OP = 2'b10;
default: OP = 2'b00;
endcase
end
endfunction
endmodule | module CPU_Ctr(
input wire [31:0] instruction,
output wire regdst_flag,
output wire [1:0] jump_flag,
output wire [1:0] branch_flag,
output wire memread_flag,
output wire memtoReg_flag,
output wire [1:0] ALUOp,
output wire memwrite_flag,
output wire ALUSrc_flag,
output wire regwrite_flag
); |
wire [5:0] opcode;
assign opcode = instruction[31:26];
assign regdst_flag = (opcode == `OPCODE_R) ? 1'b1 : 1'b0;
assign jump_flag = JUMP( instruction );
function [1:0] JUMP;
input [31:0] instruction;
begin
if( instruction[31:26] == `OPCODE_J_JUMP )
JUMP = `JUMP_J;
else if( instruction[31:26] == `OPCODE_JAL_JUMP )
JUMP = `JUMP_JAL;
else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )
JUMP = `JUMP_JR;
else
JUMP = 2'b00;
end
endfunction
assign branch_flag = BRANCH( opcode );
function [1:0] BRANCH;
input [5:0] opcode;
begin
case( opcode )
`OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;
`OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;
default: BRANCH = 2'b00;
endcase
end
endfunction
assign memread_flag = (opcode == `OPCODE_I_LW) ? 1'b1 : 1'b0;
assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1'b1 : 1'b0;
assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1'b1 : 1'b0;
assign ALUSrc_flag = ALUSRC( opcode );
function ALUSRC;
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
ALUSRC = 1'b1;
else
case( opcode )
`OPCODE_I_LW: ALUSRC = 1'b1;
`OPCODE_I_SW: ALUSRC = 1'b1;
default: ALUSRC = 1'b0;
endcase
end
endfunction
assign regwrite_flag = REGWRITE( opcode, instruction );
function REGWRITE;
input [5:0] opcode;
input [31:0] instruction;
begin
if( instruction == `NOP )
REGWRITE = 1'b0;
else if( opcode == `OPCODE_JAL_JUMP )
REGWRITE = 1'b1;
else if( opcode[5:3] == `OPCODE_I_MASK)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_I_LW)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_R )
begin
if( instruction[5:0] == `R_FUNC_JR)
REGWRITE = 1'b0;
else
REGWRITE = 1'b1;
end
else
REGWRITE = 1'b0;
end
endfunction
assign ALUOp = OP( opcode );
function [1:0] OP;
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
OP = 2'b11;
else
case( opcode )
`OPCODE_I_SW: OP = 2'b00;
`OPCODE_I_LW: OP = 2'b00;
`OPCODE_I_BEQ: OP = 2'b01;
`OPCODE_I_BNE: OP = 2'b01;
`OPCODE_R: OP = 2'b10;
default: OP = 2'b00;
endcase
end
endfunction
endmodule | 57 |
138,176 | data/full_repos/permissive/82525679/source/src/CPU_Ctr.v | 82,525,679 | CPU_Ctr.v | v | 142 | 83 | [] | [] | [] | [(93, 212)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:21: Cannot find include file: macros.v\n`include "macros.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.sv\n macros.v\n macros.v.v\n macros.v.sv\n obj_dir/macros.v\n obj_dir/macros.v.v\n obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: Define or directive not defined: \'`OPCODE_R\'\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: Define or directive not defined: \'`OPCODE_J_JUMP\'\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:47: Define or directive not defined: \'`JUMP_J\'\n JUMP = `JUMP_J;\n ^~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:48: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( instruction[31:26] == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:49: Define or directive not defined: \'`JUMP_JAL\'\n JUMP = `JUMP_JAL;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`OPCODE_R\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`R_FUNC_JR\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:51: Define or directive not defined: \'`JUMP_JR\'\n JUMP = `JUMP_JR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: syntax error, unexpected \':\', expecting endcase\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`BRANCH_OP_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`BRANCH_OP_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:71: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memread_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: Define or directive not defined: \'`OPCODE_I_SW\'\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:81: syntax error, unexpected function\n function ALUSRC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:88: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:89: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: Define or directive not defined: \'`NOP\'\n if( instruction == `NOP )\n ^~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction == `NOP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:103: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( opcode == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:105: Define or directive not defined: \'`OPCODE_I_MASK\'\n else if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:107: Define or directive not defined: \'`OPCODE_I_LW\'\n else if( opcode == `OPCODE_I_LW)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:109: Define or directive not defined: \'`OPCODE_R\'\n else if( opcode == `OPCODE_R )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:111: Define or directive not defined: \'`R_FUNC_JR\'\n if( instruction[5:0] == `R_FUNC_JR)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:130: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:131: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:132: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:133: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:134: Define or directive not defined: \'`OPCODE_R\'\n `OPCODE_R: OP = 2\'b10;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 301,915 | function | function [1:0] JUMP;
input [31:0] instruction;
begin
if( instruction[31:26] == `OPCODE_J_JUMP )
JUMP = `JUMP_J;
else if( instruction[31:26] == `OPCODE_JAL_JUMP )
JUMP = `JUMP_JAL;
else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )
JUMP = `JUMP_JR;
else
JUMP = 2'b00;
end
endfunction | function [1:0] JUMP; |
input [31:0] instruction;
begin
if( instruction[31:26] == `OPCODE_J_JUMP )
JUMP = `JUMP_J;
else if( instruction[31:26] == `OPCODE_JAL_JUMP )
JUMP = `JUMP_JAL;
else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )
JUMP = `JUMP_JR;
else
JUMP = 2'b00;
end
endfunction | 57 |
138,177 | data/full_repos/permissive/82525679/source/src/CPU_Ctr.v | 82,525,679 | CPU_Ctr.v | v | 142 | 83 | [] | [] | [] | [(93, 212)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:21: Cannot find include file: macros.v\n`include "macros.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.sv\n macros.v\n macros.v.v\n macros.v.sv\n obj_dir/macros.v\n obj_dir/macros.v.v\n obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: Define or directive not defined: \'`OPCODE_R\'\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: Define or directive not defined: \'`OPCODE_J_JUMP\'\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:47: Define or directive not defined: \'`JUMP_J\'\n JUMP = `JUMP_J;\n ^~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:48: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( instruction[31:26] == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:49: Define or directive not defined: \'`JUMP_JAL\'\n JUMP = `JUMP_JAL;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`OPCODE_R\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`R_FUNC_JR\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:51: Define or directive not defined: \'`JUMP_JR\'\n JUMP = `JUMP_JR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: syntax error, unexpected \':\', expecting endcase\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`BRANCH_OP_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`BRANCH_OP_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:71: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memread_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: Define or directive not defined: \'`OPCODE_I_SW\'\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:81: syntax error, unexpected function\n function ALUSRC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:88: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:89: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: Define or directive not defined: \'`NOP\'\n if( instruction == `NOP )\n ^~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction == `NOP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:103: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( opcode == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:105: Define or directive not defined: \'`OPCODE_I_MASK\'\n else if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:107: Define or directive not defined: \'`OPCODE_I_LW\'\n else if( opcode == `OPCODE_I_LW)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:109: Define or directive not defined: \'`OPCODE_R\'\n else if( opcode == `OPCODE_R )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:111: Define or directive not defined: \'`R_FUNC_JR\'\n if( instruction[5:0] == `R_FUNC_JR)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:130: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:131: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:132: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:133: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:134: Define or directive not defined: \'`OPCODE_R\'\n `OPCODE_R: OP = 2\'b10;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 301,915 | function | function [1:0] BRANCH;
input [5:0] opcode;
begin
case( opcode )
`OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;
`OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;
default: BRANCH = 2'b00;
endcase
end
endfunction | function [1:0] BRANCH; |
input [5:0] opcode;
begin
case( opcode )
`OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;
`OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;
default: BRANCH = 2'b00;
endcase
end
endfunction | 57 |
138,178 | data/full_repos/permissive/82525679/source/src/CPU_Ctr.v | 82,525,679 | CPU_Ctr.v | v | 142 | 83 | [] | [] | [] | [(93, 212)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:21: Cannot find include file: macros.v\n`include "macros.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.sv\n macros.v\n macros.v.v\n macros.v.sv\n obj_dir/macros.v\n obj_dir/macros.v.v\n obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: Define or directive not defined: \'`OPCODE_R\'\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: Define or directive not defined: \'`OPCODE_J_JUMP\'\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:47: Define or directive not defined: \'`JUMP_J\'\n JUMP = `JUMP_J;\n ^~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:48: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( instruction[31:26] == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:49: Define or directive not defined: \'`JUMP_JAL\'\n JUMP = `JUMP_JAL;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`OPCODE_R\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`R_FUNC_JR\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:51: Define or directive not defined: \'`JUMP_JR\'\n JUMP = `JUMP_JR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: syntax error, unexpected \':\', expecting endcase\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`BRANCH_OP_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`BRANCH_OP_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:71: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memread_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: Define or directive not defined: \'`OPCODE_I_SW\'\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:81: syntax error, unexpected function\n function ALUSRC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:88: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:89: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: Define or directive not defined: \'`NOP\'\n if( instruction == `NOP )\n ^~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction == `NOP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:103: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( opcode == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:105: Define or directive not defined: \'`OPCODE_I_MASK\'\n else if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:107: Define or directive not defined: \'`OPCODE_I_LW\'\n else if( opcode == `OPCODE_I_LW)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:109: Define or directive not defined: \'`OPCODE_R\'\n else if( opcode == `OPCODE_R )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:111: Define or directive not defined: \'`R_FUNC_JR\'\n if( instruction[5:0] == `R_FUNC_JR)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:130: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:131: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:132: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:133: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:134: Define or directive not defined: \'`OPCODE_R\'\n `OPCODE_R: OP = 2\'b10;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 301,915 | function | function ALUSRC;
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
ALUSRC = 1'b1;
else
case( opcode )
`OPCODE_I_LW: ALUSRC = 1'b1;
`OPCODE_I_SW: ALUSRC = 1'b1;
default: ALUSRC = 1'b0;
endcase
end
endfunction | function ALUSRC; |
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
ALUSRC = 1'b1;
else
case( opcode )
`OPCODE_I_LW: ALUSRC = 1'b1;
`OPCODE_I_SW: ALUSRC = 1'b1;
default: ALUSRC = 1'b0;
endcase
end
endfunction | 57 |
138,179 | data/full_repos/permissive/82525679/source/src/CPU_Ctr.v | 82,525,679 | CPU_Ctr.v | v | 142 | 83 | [] | [] | [] | [(93, 212)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:21: Cannot find include file: macros.v\n`include "macros.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.sv\n macros.v\n macros.v.v\n macros.v.sv\n obj_dir/macros.v\n obj_dir/macros.v.v\n obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: Define or directive not defined: \'`OPCODE_R\'\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: Define or directive not defined: \'`OPCODE_J_JUMP\'\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:47: Define or directive not defined: \'`JUMP_J\'\n JUMP = `JUMP_J;\n ^~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:48: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( instruction[31:26] == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:49: Define or directive not defined: \'`JUMP_JAL\'\n JUMP = `JUMP_JAL;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`OPCODE_R\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`R_FUNC_JR\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:51: Define or directive not defined: \'`JUMP_JR\'\n JUMP = `JUMP_JR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: syntax error, unexpected \':\', expecting endcase\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`BRANCH_OP_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`BRANCH_OP_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:71: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memread_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: Define or directive not defined: \'`OPCODE_I_SW\'\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:81: syntax error, unexpected function\n function ALUSRC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:88: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:89: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: Define or directive not defined: \'`NOP\'\n if( instruction == `NOP )\n ^~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction == `NOP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:103: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( opcode == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:105: Define or directive not defined: \'`OPCODE_I_MASK\'\n else if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:107: Define or directive not defined: \'`OPCODE_I_LW\'\n else if( opcode == `OPCODE_I_LW)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:109: Define or directive not defined: \'`OPCODE_R\'\n else if( opcode == `OPCODE_R )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:111: Define or directive not defined: \'`R_FUNC_JR\'\n if( instruction[5:0] == `R_FUNC_JR)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:130: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:131: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:132: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:133: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:134: Define or directive not defined: \'`OPCODE_R\'\n `OPCODE_R: OP = 2\'b10;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 301,915 | function | function REGWRITE;
input [5:0] opcode;
input [31:0] instruction;
begin
if( instruction == `NOP )
REGWRITE = 1'b0;
else if( opcode == `OPCODE_JAL_JUMP )
REGWRITE = 1'b1;
else if( opcode[5:3] == `OPCODE_I_MASK)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_I_LW)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_R )
begin
if( instruction[5:0] == `R_FUNC_JR)
REGWRITE = 1'b0;
else
REGWRITE = 1'b1;
end
else
REGWRITE = 1'b0;
end
endfunction | function REGWRITE; |
input [5:0] opcode;
input [31:0] instruction;
begin
if( instruction == `NOP )
REGWRITE = 1'b0;
else if( opcode == `OPCODE_JAL_JUMP )
REGWRITE = 1'b1;
else if( opcode[5:3] == `OPCODE_I_MASK)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_I_LW)
REGWRITE = 1'b1;
else if( opcode == `OPCODE_R )
begin
if( instruction[5:0] == `R_FUNC_JR)
REGWRITE = 1'b0;
else
REGWRITE = 1'b1;
end
else
REGWRITE = 1'b0;
end
endfunction | 57 |
138,180 | data/full_repos/permissive/82525679/source/src/CPU_Ctr.v | 82,525,679 | CPU_Ctr.v | v | 142 | 83 | [] | [] | [] | [(93, 212)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:21: Cannot find include file: macros.v\n`include "macros.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/macros.v.sv\n macros.v\n macros.v.v\n macros.v.sv\n obj_dir/macros.v\n obj_dir/macros.v.v\n obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: Define or directive not defined: \'`OPCODE_R\'\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign regdst_flag = (opcode == `OPCODE_R) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: Define or directive not defined: \'`OPCODE_J_JUMP\'\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction[31:26] == `OPCODE_J_JUMP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:47: Define or directive not defined: \'`JUMP_J\'\n JUMP = `JUMP_J;\n ^~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:48: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( instruction[31:26] == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:49: Define or directive not defined: \'`JUMP_JAL\'\n JUMP = `JUMP_JAL;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`OPCODE_R\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:50: Define or directive not defined: \'`R_FUNC_JR\'\n else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:51: Define or directive not defined: \'`JUMP_JR\'\n JUMP = `JUMP_JR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: syntax error, unexpected \':\', expecting endcase\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:63: Define or directive not defined: \'`BRANCH_OP_BEQ\'\n `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:64: Define or directive not defined: \'`BRANCH_OP_BNE\'\n `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:71: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memread_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: Define or directive not defined: \'`OPCODE_I_LW\'\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: Define or directive not defined: \'`OPCODE_I_SW\'\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1\'b1 : 1\'b0;\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:81: syntax error, unexpected function\n function ALUSRC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:88: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:89: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: ALUSRC = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: Define or directive not defined: \'`NOP\'\n if( instruction == `NOP )\n ^~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( instruction == `NOP )\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:103: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n else if( opcode == `OPCODE_JAL_JUMP )\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:105: Define or directive not defined: \'`OPCODE_I_MASK\'\n else if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:107: Define or directive not defined: \'`OPCODE_I_LW\'\n else if( opcode == `OPCODE_I_LW)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:109: Define or directive not defined: \'`OPCODE_R\'\n else if( opcode == `OPCODE_R )\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:111: Define or directive not defined: \'`R_FUNC_JR\'\n if( instruction[5:0] == `R_FUNC_JR)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: Define or directive not defined: \'`OPCODE_I_MASK\'\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( opcode[5:3] == `OPCODE_I_MASK)\n ^\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:130: Define or directive not defined: \'`OPCODE_I_SW\'\n `OPCODE_I_SW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:131: Define or directive not defined: \'`OPCODE_I_LW\'\n `OPCODE_I_LW: OP = 2\'b00;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:132: Define or directive not defined: \'`OPCODE_I_BEQ\'\n `OPCODE_I_BEQ: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:133: Define or directive not defined: \'`OPCODE_I_BNE\'\n `OPCODE_I_BNE: OP = 2\'b01;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/CPU_Ctr.v:134: Define or directive not defined: \'`OPCODE_R\'\n `OPCODE_R: OP = 2\'b10;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 301,915 | function | function [1:0] OP;
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
OP = 2'b11;
else
case( opcode )
`OPCODE_I_SW: OP = 2'b00;
`OPCODE_I_LW: OP = 2'b00;
`OPCODE_I_BEQ: OP = 2'b01;
`OPCODE_I_BNE: OP = 2'b01;
`OPCODE_R: OP = 2'b10;
default: OP = 2'b00;
endcase
end
endfunction | function [1:0] OP; |
input [5:0] opcode;
begin
if( opcode[5:3] == `OPCODE_I_MASK)
OP = 2'b11;
else
case( opcode )
`OPCODE_I_SW: OP = 2'b00;
`OPCODE_I_LW: OP = 2'b00;
`OPCODE_I_BEQ: OP = 2'b01;
`OPCODE_I_BNE: OP = 2'b01;
`OPCODE_R: OP = 2'b10;
default: OP = 2'b00;
endcase
end
endfunction | 57 |
138,181 | data/full_repos/permissive/82525679/source/src/SimpleCache.v | 82,525,679 | SimpleCache.v | v | 366 | 149 | [] | [] | [] | [(23, 365)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:71: Cannot find file containing module: \'allocate\'\n allocate allocate_i(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.sv\n allocate\n allocate.v\n allocate.sv\n obj_dir/allocate\n obj_dir/allocate.v\n obj_dir/allocate.sv\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:96: Cannot find file containing module: \'wback\'\n wback wback_i(\n ^~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:113: Cannot find file containing module: \'main_mem\'\n main_mem main_mem_i(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:131: Cannot find file containing module: \'cache_tag\'\n cache_tag cache_tag_i(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:186: Cannot find file containing module: \'cache_data\'\n cache_data cache_data_i(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'CPU_addr_offset\' generates 3 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 301,923 | module | module SimpleCache(
input wire clk,
input wire rst,
input wire CPU_read_en,
output wire [31:0] CPU_read_dout,
input wire CPU_write_en,
input wire [31:0] CPU_write_din,
input wire [31:0] CPU_addr,
output wire isCacheStall,
input wire mem_b_we,
input wire [12:0] mem_b_addr,
input wire [31:0] mem_b_din,
output wire [31:0] mem_b_dout
);
wire mem_a_we;
wire [12:0] mem_a_addr;
wire [31:0] mem_a_din;
wire [31:0] mem_a_dout;
wire [5:0] cache_tag_addr;
wire [22:0] cache_tag_din;
wire [22:0] cache_tag_dout;
wire cache_tag_we;
wire [20:0] cache_tag_dout_tag;
wire cache_tag_dout_valid;
wire cache_tag_dout_overwrite;
wire [8:0] cache_data_addr;
wire [31:0] cache_data_din;
wire cache_data_we;
wire [31:0] cache_data_dout;
wire [31:0] allocate_main_mem_dout;
wire [12:0] allocate_main_mem_addr;
wire [8:0] allocate_cache_data_addr;
wire [31:0] allocate_cache_data_din;
wire allocate_cache_data_we;
reg allocate_start;
wire allocate_done;
wire [8:0] hit_cache_data_addr;
wire hit_cache_data_we;
wire [31:0] hit_cache_data_din;
assign allocate_main_mem_dout = mem_a_dout;
allocate allocate_i(
.clk( clk ),
.rst( rst ),
.CPU_addr( CPU_addr ),
.main_mem_dout( allocate_main_mem_dout ),
.main_mem_addr( allocate_main_mem_addr ),
.cache_data_addr( allocate_cache_data_addr ),
.cache_data_din( allocate_cache_data_din ),
.cache_data_we( allocate_cache_data_we ),
.start( allocate_start ),
.done( allocate_done )
);
wire [31:0] wb_main_mem_din;
wire wb_main_mem_we;
wire [12:0] wb_main_mem_addr;
wire [31:0] wb_cache_data_dout;
wire [8:0] wb_cache_data_addr;
reg wb_start;
wire wb_done;
wire [31:0] wb_CPU_addr;
assign wb_cache_data_dout = cache_data_dout;
assign wb_CPU_addr = {cache_tag_dout_tag, CPU_addr_index, CPU_addr_offset, 2'b00};
wback wback_i(
.clk( clk ),
.rst( rst ),
.CPU_addr( wb_CPU_addr ),
.main_mem_din( wb_main_mem_din ),
.main_mem_we( wb_main_mem_we ),
.main_mem_addr( wb_main_mem_addr ),
.cache_data_dout( wb_cache_data_dout ),
.cache_data_addr( wb_cache_data_addr ),
.start( wb_start ),
.done( wb_done )
);
assign mem_a_we = wb_main_mem_we;
assign mem_a_din = wb_main_mem_din;
assign mem_a_addr = (current_state == WBACK) ? wb_main_mem_addr : allocate_main_mem_addr;
main_mem main_mem_i(
.clka( clk ),
.wea( mem_a_we ),
.addra( mem_a_addr ),
.dina( mem_a_din ),
.douta( mem_a_dout ),
.clkb( clk ),
.web( mem_b_we ),
.addrb( mem_b_addr ),
.dinb( mem_b_din ),
.doutb( mem_b_dout )
);
assign cache_tag_dout_tag = cache_tag_dout[20:0];
assign cache_tag_dout_valid = cache_tag_dout[21];
assign cache_tag_dout_overwrite = cache_tag_dout[22];
cache_tag cache_tag_i(
.a( cache_tag_addr ),
.d( cache_tag_din ),
.clk( clk ),
.we( cache_tag_we),
.spo( cache_tag_dout )
);
assign cache_data_addr = CACHE_DATA_ADDR(current_state, hit_cache_data_addr, allocate_cache_data_addr, wb_cache_data_addr);
function [8:0] CACHE_DATA_ADDR;
input [1:0] state;
input [8:0] hit_cache_data_addr;
input [8:0] allocate_cache_data_addr;
input [8:0] wb_cache_data_addr;
case(state)
IDLE: CACHE_DATA_ADDR = hit_cache_data_addr;
COMPARE: CACHE_DATA_ADDR = hit_cache_data_addr;
ALLOCATE: CACHE_DATA_ADDR = allocate_cache_data_addr;
WBACK: CACHE_DATA_ADDR = wb_cache_data_addr;
default: CACHE_DATA_ADDR = hit_cache_data_addr;
endcase
endfunction
assign cache_data_we = CACHE_DATA_WE(current_state, hit_cache_data_we, allocate_cache_data_we);
function CACHE_DATA_WE;
input [1:0] state;
input hit_cache_data_we;
input allocate_cache_data_we;
case( state )
IDLE: CACHE_DATA_WE = hit_cache_data_we;
COMPARE: CACHE_DATA_WE = hit_cache_data_we;
ALLOCATE: CACHE_DATA_WE = allocate_cache_data_we;
default: CACHE_DATA_WE = hit_cache_data_we;
endcase
endfunction
assign cache_data_din = CACHE_DATA_DIN( current_state, hit_cache_data_din, allocate_cache_data_din);
function [31:0] CACHE_DATA_DIN;
input [1:0] state;
input [31:0] hit_cache_data_din;
input [31:0] allocate_cache_data_din;
case( state )
IDLE: CACHE_DATA_DIN = hit_cache_data_din;
COMPARE: CACHE_DATA_DIN = hit_cache_data_din;
ALLOCATE: CACHE_DATA_DIN = allocate_cache_data_din;
default: CACHE_DATA_DIN = hit_cache_data_din;
endcase
endfunction
cache_data cache_data_i(
.a( cache_data_addr ),
.d( cache_data_din ),
.clk( clk ),
.we( cache_data_we ),
.spo( cache_data_dout )
);
wire [20:0] CPU_addr_tag;
wire [5:0] CPU_addr_index;
wire [2:0] CPU_addr_offset;
wire isCacheHit;
assign CPU_addr_tag = CPU_addr[31:11];
assign CPU_addr_index = CPU_addr[10:5];
assign CPU_addr_offset = CPU_addr[4:2];
assign isCacheHit = (CPU_addr_tag == cache_tag_dout_tag) & cache_tag_dout_valid;
assign CPU_read_dout = cache_data_dout;
assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;
assign hit_cache_data_din = CPU_write_din;
assign hit_cache_data_we = (current_state == IDLE) && CPU_write_en && isCacheHit;
assign cache_tag_addr = CPU_addr_index;
assign cache_tag_we = CACHE_TAG_WE(current_state, CPU_write_en, isCacheHit );
assign cache_tag_din = CACHE_TAG_DIN(current_state, CPU_write_en, isCacheHit, CPU_addr_tag);
function CACHE_TAG_WE;
input [1:0] state;
input CPU_write_en;
input isCacheHit;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_WE = 1;
else if( state == ALLOCATE)
CACHE_TAG_WE = 1;
else
CACHE_TAG_WE = 0;
endfunction
function [22:0] CACHE_TAG_DIN;
input [1:0] state;
input CPU_write_en;
input isCacheHit;
input [20:0] CPU_addr_tag;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_DIN = {1'b1, 1'b1, CPU_addr_tag};
else if( state == ALLOCATE)
CACHE_TAG_DIN = {1'b0, 1'b1, CPU_addr_tag};
else
CACHE_TAG_DIN = 0;
endfunction
assign isCacheStall = ISCACHESTALL( current_state, CPU_read_en, CPU_write_en, CPU_addr_tag, cache_tag_dout_tag, cache_tag_dout_valid);
function ISCACHESTALL;
input [1:0] current_state;
input CPU_read_en;
input CPU_write_en;
input [20:0] CPU_addr_tag;
input [20:0] cache_tag_dout_tag;
input cache_tag_dout_valid;
if( (CPU_write_en | CPU_read_en) == 0 )
ISCACHESTALL = 0;
else if( ( current_state == IDLE) && ((CPU_addr_tag == cache_tag_dout_tag) & cache_tag_dout_valid) )
ISCACHESTALL = 0;
else
ISCACHESTALL = 1;
endfunction
reg [1:0] current_state;
reg [1:0] next_state;
localparam IDLE = 2'h0, COMPARE = 2'd1, ALLOCATE = 2'd2, WBACK = 2'd3;
always @(posedge clk)
begin
if( rst )
current_state <= IDLE;
else
current_state <= next_state;
end
always @(*)
begin
next_state = IDLE;
case( current_state )
IDLE: begin
if( (CPU_read_en | CPU_write_en) && (~isCacheHit) )
next_state = COMPARE;
else
next_state = IDLE;
end
COMPARE:begin
if( (~isCacheHit) && (~cache_tag_dout_overwrite))
next_state = ALLOCATE;
else if( (~isCacheHit) && cache_tag_dout_overwrite)
next_state = WBACK;
else
next_state = IDLE;
end
ALLOCATE: begin
if( allocate_done )
next_state = IDLE;
else
next_state = ALLOCATE;
end
WBACK: begin
if( wb_done )
next_state = ALLOCATE;
else
next_state = WBACK;
end
endcase
end
always @(posedge clk)
begin
if( rst )
begin
allocate_start <= 0;
wb_start <= 0;
end
else
begin
case( current_state )
IDLE: begin
allocate_start <= 0;
wb_start <= 0;
end
COMPARE:begin
if( (~isCacheHit) && (~cache_tag_dout_overwrite))
begin
wb_start <= 0;
allocate_start <= 1;
end
else if( (~isCacheHit) && cache_tag_dout_overwrite)
begin
wb_start <= 1;
allocate_start <= 0;
end
else
begin
wb_start <= 0;
allocate_start <= 0;
end
end
ALLOCATE: begin
wb_start <= 0;
allocate_start <= 0;
end
WBACK: begin
wb_start <= 0;
if( wb_done )
allocate_start <= 1;
else
allocate_start <= 0;
end
endcase
end
end
endmodule | module SimpleCache(
input wire clk,
input wire rst,
input wire CPU_read_en,
output wire [31:0] CPU_read_dout,
input wire CPU_write_en,
input wire [31:0] CPU_write_din,
input wire [31:0] CPU_addr,
output wire isCacheStall,
input wire mem_b_we,
input wire [12:0] mem_b_addr,
input wire [31:0] mem_b_din,
output wire [31:0] mem_b_dout
); |
wire mem_a_we;
wire [12:0] mem_a_addr;
wire [31:0] mem_a_din;
wire [31:0] mem_a_dout;
wire [5:0] cache_tag_addr;
wire [22:0] cache_tag_din;
wire [22:0] cache_tag_dout;
wire cache_tag_we;
wire [20:0] cache_tag_dout_tag;
wire cache_tag_dout_valid;
wire cache_tag_dout_overwrite;
wire [8:0] cache_data_addr;
wire [31:0] cache_data_din;
wire cache_data_we;
wire [31:0] cache_data_dout;
wire [31:0] allocate_main_mem_dout;
wire [12:0] allocate_main_mem_addr;
wire [8:0] allocate_cache_data_addr;
wire [31:0] allocate_cache_data_din;
wire allocate_cache_data_we;
reg allocate_start;
wire allocate_done;
wire [8:0] hit_cache_data_addr;
wire hit_cache_data_we;
wire [31:0] hit_cache_data_din;
assign allocate_main_mem_dout = mem_a_dout;
allocate allocate_i(
.clk( clk ),
.rst( rst ),
.CPU_addr( CPU_addr ),
.main_mem_dout( allocate_main_mem_dout ),
.main_mem_addr( allocate_main_mem_addr ),
.cache_data_addr( allocate_cache_data_addr ),
.cache_data_din( allocate_cache_data_din ),
.cache_data_we( allocate_cache_data_we ),
.start( allocate_start ),
.done( allocate_done )
);
wire [31:0] wb_main_mem_din;
wire wb_main_mem_we;
wire [12:0] wb_main_mem_addr;
wire [31:0] wb_cache_data_dout;
wire [8:0] wb_cache_data_addr;
reg wb_start;
wire wb_done;
wire [31:0] wb_CPU_addr;
assign wb_cache_data_dout = cache_data_dout;
assign wb_CPU_addr = {cache_tag_dout_tag, CPU_addr_index, CPU_addr_offset, 2'b00};
wback wback_i(
.clk( clk ),
.rst( rst ),
.CPU_addr( wb_CPU_addr ),
.main_mem_din( wb_main_mem_din ),
.main_mem_we( wb_main_mem_we ),
.main_mem_addr( wb_main_mem_addr ),
.cache_data_dout( wb_cache_data_dout ),
.cache_data_addr( wb_cache_data_addr ),
.start( wb_start ),
.done( wb_done )
);
assign mem_a_we = wb_main_mem_we;
assign mem_a_din = wb_main_mem_din;
assign mem_a_addr = (current_state == WBACK) ? wb_main_mem_addr : allocate_main_mem_addr;
main_mem main_mem_i(
.clka( clk ),
.wea( mem_a_we ),
.addra( mem_a_addr ),
.dina( mem_a_din ),
.douta( mem_a_dout ),
.clkb( clk ),
.web( mem_b_we ),
.addrb( mem_b_addr ),
.dinb( mem_b_din ),
.doutb( mem_b_dout )
);
assign cache_tag_dout_tag = cache_tag_dout[20:0];
assign cache_tag_dout_valid = cache_tag_dout[21];
assign cache_tag_dout_overwrite = cache_tag_dout[22];
cache_tag cache_tag_i(
.a( cache_tag_addr ),
.d( cache_tag_din ),
.clk( clk ),
.we( cache_tag_we),
.spo( cache_tag_dout )
);
assign cache_data_addr = CACHE_DATA_ADDR(current_state, hit_cache_data_addr, allocate_cache_data_addr, wb_cache_data_addr);
function [8:0] CACHE_DATA_ADDR;
input [1:0] state;
input [8:0] hit_cache_data_addr;
input [8:0] allocate_cache_data_addr;
input [8:0] wb_cache_data_addr;
case(state)
IDLE: CACHE_DATA_ADDR = hit_cache_data_addr;
COMPARE: CACHE_DATA_ADDR = hit_cache_data_addr;
ALLOCATE: CACHE_DATA_ADDR = allocate_cache_data_addr;
WBACK: CACHE_DATA_ADDR = wb_cache_data_addr;
default: CACHE_DATA_ADDR = hit_cache_data_addr;
endcase
endfunction
assign cache_data_we = CACHE_DATA_WE(current_state, hit_cache_data_we, allocate_cache_data_we);
function CACHE_DATA_WE;
input [1:0] state;
input hit_cache_data_we;
input allocate_cache_data_we;
case( state )
IDLE: CACHE_DATA_WE = hit_cache_data_we;
COMPARE: CACHE_DATA_WE = hit_cache_data_we;
ALLOCATE: CACHE_DATA_WE = allocate_cache_data_we;
default: CACHE_DATA_WE = hit_cache_data_we;
endcase
endfunction
assign cache_data_din = CACHE_DATA_DIN( current_state, hit_cache_data_din, allocate_cache_data_din);
function [31:0] CACHE_DATA_DIN;
input [1:0] state;
input [31:0] hit_cache_data_din;
input [31:0] allocate_cache_data_din;
case( state )
IDLE: CACHE_DATA_DIN = hit_cache_data_din;
COMPARE: CACHE_DATA_DIN = hit_cache_data_din;
ALLOCATE: CACHE_DATA_DIN = allocate_cache_data_din;
default: CACHE_DATA_DIN = hit_cache_data_din;
endcase
endfunction
cache_data cache_data_i(
.a( cache_data_addr ),
.d( cache_data_din ),
.clk( clk ),
.we( cache_data_we ),
.spo( cache_data_dout )
);
wire [20:0] CPU_addr_tag;
wire [5:0] CPU_addr_index;
wire [2:0] CPU_addr_offset;
wire isCacheHit;
assign CPU_addr_tag = CPU_addr[31:11];
assign CPU_addr_index = CPU_addr[10:5];
assign CPU_addr_offset = CPU_addr[4:2];
assign isCacheHit = (CPU_addr_tag == cache_tag_dout_tag) & cache_tag_dout_valid;
assign CPU_read_dout = cache_data_dout;
assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;
assign hit_cache_data_din = CPU_write_din;
assign hit_cache_data_we = (current_state == IDLE) && CPU_write_en && isCacheHit;
assign cache_tag_addr = CPU_addr_index;
assign cache_tag_we = CACHE_TAG_WE(current_state, CPU_write_en, isCacheHit );
assign cache_tag_din = CACHE_TAG_DIN(current_state, CPU_write_en, isCacheHit, CPU_addr_tag);
function CACHE_TAG_WE;
input [1:0] state;
input CPU_write_en;
input isCacheHit;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_WE = 1;
else if( state == ALLOCATE)
CACHE_TAG_WE = 1;
else
CACHE_TAG_WE = 0;
endfunction
function [22:0] CACHE_TAG_DIN;
input [1:0] state;
input CPU_write_en;
input isCacheHit;
input [20:0] CPU_addr_tag;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_DIN = {1'b1, 1'b1, CPU_addr_tag};
else if( state == ALLOCATE)
CACHE_TAG_DIN = {1'b0, 1'b1, CPU_addr_tag};
else
CACHE_TAG_DIN = 0;
endfunction
assign isCacheStall = ISCACHESTALL( current_state, CPU_read_en, CPU_write_en, CPU_addr_tag, cache_tag_dout_tag, cache_tag_dout_valid);
function ISCACHESTALL;
input [1:0] current_state;
input CPU_read_en;
input CPU_write_en;
input [20:0] CPU_addr_tag;
input [20:0] cache_tag_dout_tag;
input cache_tag_dout_valid;
if( (CPU_write_en | CPU_read_en) == 0 )
ISCACHESTALL = 0;
else if( ( current_state == IDLE) && ((CPU_addr_tag == cache_tag_dout_tag) & cache_tag_dout_valid) )
ISCACHESTALL = 0;
else
ISCACHESTALL = 1;
endfunction
reg [1:0] current_state;
reg [1:0] next_state;
localparam IDLE = 2'h0, COMPARE = 2'd1, ALLOCATE = 2'd2, WBACK = 2'd3;
always @(posedge clk)
begin
if( rst )
current_state <= IDLE;
else
current_state <= next_state;
end
always @(*)
begin
next_state = IDLE;
case( current_state )
IDLE: begin
if( (CPU_read_en | CPU_write_en) && (~isCacheHit) )
next_state = COMPARE;
else
next_state = IDLE;
end
COMPARE:begin
if( (~isCacheHit) && (~cache_tag_dout_overwrite))
next_state = ALLOCATE;
else if( (~isCacheHit) && cache_tag_dout_overwrite)
next_state = WBACK;
else
next_state = IDLE;
end
ALLOCATE: begin
if( allocate_done )
next_state = IDLE;
else
next_state = ALLOCATE;
end
WBACK: begin
if( wb_done )
next_state = ALLOCATE;
else
next_state = WBACK;
end
endcase
end
always @(posedge clk)
begin
if( rst )
begin
allocate_start <= 0;
wb_start <= 0;
end
else
begin
case( current_state )
IDLE: begin
allocate_start <= 0;
wb_start <= 0;
end
COMPARE:begin
if( (~isCacheHit) && (~cache_tag_dout_overwrite))
begin
wb_start <= 0;
allocate_start <= 1;
end
else if( (~isCacheHit) && cache_tag_dout_overwrite)
begin
wb_start <= 1;
allocate_start <= 0;
end
else
begin
wb_start <= 0;
allocate_start <= 0;
end
end
ALLOCATE: begin
wb_start <= 0;
allocate_start <= 0;
end
WBACK: begin
wb_start <= 0;
if( wb_done )
allocate_start <= 1;
else
allocate_start <= 0;
end
endcase
end
end
endmodule | 57 |
138,182 | data/full_repos/permissive/82525679/source/src/SimpleCache.v | 82,525,679 | SimpleCache.v | v | 366 | 149 | [] | [] | [] | [(23, 365)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:71: Cannot find file containing module: \'allocate\'\n allocate allocate_i(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.sv\n allocate\n allocate.v\n allocate.sv\n obj_dir/allocate\n obj_dir/allocate.v\n obj_dir/allocate.sv\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:96: Cannot find file containing module: \'wback\'\n wback wback_i(\n ^~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:113: Cannot find file containing module: \'main_mem\'\n main_mem main_mem_i(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:131: Cannot find file containing module: \'cache_tag\'\n cache_tag cache_tag_i(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:186: Cannot find file containing module: \'cache_data\'\n cache_data cache_data_i(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'CPU_addr_offset\' generates 3 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 301,923 | function | function [8:0] CACHE_DATA_ADDR;
input [1:0] state;
input [8:0] hit_cache_data_addr;
input [8:0] allocate_cache_data_addr;
input [8:0] wb_cache_data_addr;
case(state)
IDLE: CACHE_DATA_ADDR = hit_cache_data_addr;
COMPARE: CACHE_DATA_ADDR = hit_cache_data_addr;
ALLOCATE: CACHE_DATA_ADDR = allocate_cache_data_addr;
WBACK: CACHE_DATA_ADDR = wb_cache_data_addr;
default: CACHE_DATA_ADDR = hit_cache_data_addr;
endcase
endfunction | function [8:0] CACHE_DATA_ADDR; |
input [1:0] state;
input [8:0] hit_cache_data_addr;
input [8:0] allocate_cache_data_addr;
input [8:0] wb_cache_data_addr;
case(state)
IDLE: CACHE_DATA_ADDR = hit_cache_data_addr;
COMPARE: CACHE_DATA_ADDR = hit_cache_data_addr;
ALLOCATE: CACHE_DATA_ADDR = allocate_cache_data_addr;
WBACK: CACHE_DATA_ADDR = wb_cache_data_addr;
default: CACHE_DATA_ADDR = hit_cache_data_addr;
endcase
endfunction | 57 |
138,183 | data/full_repos/permissive/82525679/source/src/SimpleCache.v | 82,525,679 | SimpleCache.v | v | 366 | 149 | [] | [] | [] | [(23, 365)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:71: Cannot find file containing module: \'allocate\'\n allocate allocate_i(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.sv\n allocate\n allocate.v\n allocate.sv\n obj_dir/allocate\n obj_dir/allocate.v\n obj_dir/allocate.sv\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:96: Cannot find file containing module: \'wback\'\n wback wback_i(\n ^~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:113: Cannot find file containing module: \'main_mem\'\n main_mem main_mem_i(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:131: Cannot find file containing module: \'cache_tag\'\n cache_tag cache_tag_i(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:186: Cannot find file containing module: \'cache_data\'\n cache_data cache_data_i(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'CPU_addr_offset\' generates 3 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 301,923 | function | function CACHE_DATA_WE;
input [1:0] state;
input hit_cache_data_we;
input allocate_cache_data_we;
case( state )
IDLE: CACHE_DATA_WE = hit_cache_data_we;
COMPARE: CACHE_DATA_WE = hit_cache_data_we;
ALLOCATE: CACHE_DATA_WE = allocate_cache_data_we;
default: CACHE_DATA_WE = hit_cache_data_we;
endcase
endfunction | function CACHE_DATA_WE; |
input [1:0] state;
input hit_cache_data_we;
input allocate_cache_data_we;
case( state )
IDLE: CACHE_DATA_WE = hit_cache_data_we;
COMPARE: CACHE_DATA_WE = hit_cache_data_we;
ALLOCATE: CACHE_DATA_WE = allocate_cache_data_we;
default: CACHE_DATA_WE = hit_cache_data_we;
endcase
endfunction | 57 |
138,184 | data/full_repos/permissive/82525679/source/src/SimpleCache.v | 82,525,679 | SimpleCache.v | v | 366 | 149 | [] | [] | [] | [(23, 365)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:71: Cannot find file containing module: \'allocate\'\n allocate allocate_i(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.sv\n allocate\n allocate.v\n allocate.sv\n obj_dir/allocate\n obj_dir/allocate.v\n obj_dir/allocate.sv\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:96: Cannot find file containing module: \'wback\'\n wback wback_i(\n ^~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:113: Cannot find file containing module: \'main_mem\'\n main_mem main_mem_i(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:131: Cannot find file containing module: \'cache_tag\'\n cache_tag cache_tag_i(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:186: Cannot find file containing module: \'cache_data\'\n cache_data cache_data_i(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'CPU_addr_offset\' generates 3 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 301,923 | function | function [31:0] CACHE_DATA_DIN;
input [1:0] state;
input [31:0] hit_cache_data_din;
input [31:0] allocate_cache_data_din;
case( state )
IDLE: CACHE_DATA_DIN = hit_cache_data_din;
COMPARE: CACHE_DATA_DIN = hit_cache_data_din;
ALLOCATE: CACHE_DATA_DIN = allocate_cache_data_din;
default: CACHE_DATA_DIN = hit_cache_data_din;
endcase
endfunction | function [31:0] CACHE_DATA_DIN; |
input [1:0] state;
input [31:0] hit_cache_data_din;
input [31:0] allocate_cache_data_din;
case( state )
IDLE: CACHE_DATA_DIN = hit_cache_data_din;
COMPARE: CACHE_DATA_DIN = hit_cache_data_din;
ALLOCATE: CACHE_DATA_DIN = allocate_cache_data_din;
default: CACHE_DATA_DIN = hit_cache_data_din;
endcase
endfunction | 57 |
138,185 | data/full_repos/permissive/82525679/source/src/SimpleCache.v | 82,525,679 | SimpleCache.v | v | 366 | 149 | [] | [] | [] | [(23, 365)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:71: Cannot find file containing module: \'allocate\'\n allocate allocate_i(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.sv\n allocate\n allocate.v\n allocate.sv\n obj_dir/allocate\n obj_dir/allocate.v\n obj_dir/allocate.sv\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:96: Cannot find file containing module: \'wback\'\n wback wback_i(\n ^~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:113: Cannot find file containing module: \'main_mem\'\n main_mem main_mem_i(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:131: Cannot find file containing module: \'cache_tag\'\n cache_tag cache_tag_i(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:186: Cannot find file containing module: \'cache_data\'\n cache_data cache_data_i(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'CPU_addr_offset\' generates 3 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 301,923 | function | function CACHE_TAG_WE;
input [1:0] state;
input CPU_write_en;
input isCacheHit;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_WE = 1;
else if( state == ALLOCATE)
CACHE_TAG_WE = 1;
else
CACHE_TAG_WE = 0;
endfunction | function CACHE_TAG_WE; |
input [1:0] state;
input CPU_write_en;
input isCacheHit;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_WE = 1;
else if( state == ALLOCATE)
CACHE_TAG_WE = 1;
else
CACHE_TAG_WE = 0;
endfunction | 57 |
138,186 | data/full_repos/permissive/82525679/source/src/SimpleCache.v | 82,525,679 | SimpleCache.v | v | 366 | 149 | [] | [] | [] | [(23, 365)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:71: Cannot find file containing module: \'allocate\'\n allocate allocate_i(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.sv\n allocate\n allocate.v\n allocate.sv\n obj_dir/allocate\n obj_dir/allocate.v\n obj_dir/allocate.sv\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:96: Cannot find file containing module: \'wback\'\n wback wback_i(\n ^~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:113: Cannot find file containing module: \'main_mem\'\n main_mem main_mem_i(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:131: Cannot find file containing module: \'cache_tag\'\n cache_tag cache_tag_i(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:186: Cannot find file containing module: \'cache_data\'\n cache_data cache_data_i(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'CPU_addr_offset\' generates 3 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 301,923 | function | function [22:0] CACHE_TAG_DIN;
input [1:0] state;
input CPU_write_en;
input isCacheHit;
input [20:0] CPU_addr_tag;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_DIN = {1'b1, 1'b1, CPU_addr_tag};
else if( state == ALLOCATE)
CACHE_TAG_DIN = {1'b0, 1'b1, CPU_addr_tag};
else
CACHE_TAG_DIN = 0;
endfunction | function [22:0] CACHE_TAG_DIN; |
input [1:0] state;
input CPU_write_en;
input isCacheHit;
input [20:0] CPU_addr_tag;
if( state == IDLE && CPU_write_en && isCacheHit )
CACHE_TAG_DIN = {1'b1, 1'b1, CPU_addr_tag};
else if( state == ALLOCATE)
CACHE_TAG_DIN = {1'b0, 1'b1, CPU_addr_tag};
else
CACHE_TAG_DIN = 0;
endfunction | 57 |
138,187 | data/full_repos/permissive/82525679/source/src/SimpleCache.v | 82,525,679 | SimpleCache.v | v | 366 | 149 | [] | [] | [] | [(23, 365)] | null | null | 1: b'%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:71: Cannot find file containing module: \'allocate\'\n allocate allocate_i(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.v\n data/full_repos/permissive/82525679/source/src,data/full_repos/permissive/82525679/allocate.sv\n allocate\n allocate.v\n allocate.sv\n obj_dir/allocate\n obj_dir/allocate.v\n obj_dir/allocate.sv\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:96: Cannot find file containing module: \'wback\'\n wback wback_i(\n ^~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:113: Cannot find file containing module: \'main_mem\'\n main_mem main_mem_i(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:131: Cannot find file containing module: \'cache_tag\'\n cache_tag cache_tag_i(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82525679/source/src/SimpleCache.v:186: Cannot find file containing module: \'cache_data\'\n cache_data cache_data_i(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'CPU_addr_index\' generates 6 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82525679/source/src/SimpleCache.v:212: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'CPU_addr_offset\' generates 3 bits.\n : ... In instance SimpleCache\n assign hit_cache_data_addr = (CPU_addr_index << 3) + CPU_addr_offset;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 301,923 | function | function ISCACHESTALL;
input [1:0] current_state;
input CPU_read_en;
input CPU_write_en;
input [20:0] CPU_addr_tag;
input [20:0] cache_tag_dout_tag;
input cache_tag_dout_valid;
if( (CPU_write_en | CPU_read_en) == 0 )
ISCACHESTALL = 0;
else if( ( current_state == IDLE) && ((CPU_addr_tag == cache_tag_dout_tag) & cache_tag_dout_valid) )
ISCACHESTALL = 0;
else
ISCACHESTALL = 1;
endfunction | function ISCACHESTALL; |
input [1:0] current_state;
input CPU_read_en;
input CPU_write_en;
input [20:0] CPU_addr_tag;
input [20:0] cache_tag_dout_tag;
input cache_tag_dout_valid;
if( (CPU_write_en | CPU_read_en) == 0 )
ISCACHESTALL = 0;
else if( ( current_state == IDLE) && ((CPU_addr_tag == cache_tag_dout_tag) & cache_tag_dout_valid) )
ISCACHESTALL = 0;
else
ISCACHESTALL = 1;
endfunction | 57 |
138,189 | data/full_repos/permissive/82755548/Homework_1.v | 82,755,548 | Homework_1.v | v | 75 | 65 | [] | [] | [] | [(12, 21), (23, 35), (37, 41), (48, 61), (66, 74)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82755548/Homework_1.v:66: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'my_xor\'\nmodule my_xor(Z,X,Y);\n ^~~~~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1(OUT,IN0,IN1,S0);\n ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82755548/Homework_1.v:57: Signal definition not found, creating implicitly: \'X_and_Yprime\'\n : ... Suggested alternative: \'x_and_Yprime\'\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:57: Found definition of \'mn1\' as a CELL but expected a variable\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:58: Found definition of \'mn2\' as a CELL but expected a variable\n my_and ma2(Y_and_Xprime,mn2,Y);\n ^~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 301,927 | module | module my_and(C,A,B);
output C;
input A,B;
wire W1;
nand input_nand(W1,A,B);
nand output_nand(C,W1,W1);
endmodule | module my_and(C,A,B); |
output C;
input A,B;
wire W1;
nand input_nand(W1,A,B);
nand output_nand(C,W1,W1);
endmodule | 0 |
138,190 | data/full_repos/permissive/82755548/Homework_1.v | 82,755,548 | Homework_1.v | v | 75 | 65 | [] | [] | [] | [(12, 21), (23, 35), (37, 41), (48, 61), (66, 74)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82755548/Homework_1.v:66: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'my_xor\'\nmodule my_xor(Z,X,Y);\n ^~~~~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1(OUT,IN0,IN1,S0);\n ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82755548/Homework_1.v:57: Signal definition not found, creating implicitly: \'X_and_Yprime\'\n : ... Suggested alternative: \'x_and_Yprime\'\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:57: Found definition of \'mn1\' as a CELL but expected a variable\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:58: Found definition of \'mn2\' as a CELL but expected a variable\n my_and ma2(Y_and_Xprime,mn2,Y);\n ^~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 301,927 | module | module my_or(C,A,B);
output C;
input A,B;
wire A_out;
wire B_out;
nand input_nand1(A_out,A,A);
nand input_nand2(B_out,B,B);
nand output_nand(C,A_out,B_out);
endmodule | module my_or(C,A,B); |
output C;
input A,B;
wire A_out;
wire B_out;
nand input_nand1(A_out,A,A);
nand input_nand2(B_out,B,B);
nand output_nand(C,A_out,B_out);
endmodule | 0 |
138,191 | data/full_repos/permissive/82755548/Homework_1.v | 82,755,548 | Homework_1.v | v | 75 | 65 | [] | [] | [] | [(12, 21), (23, 35), (37, 41), (48, 61), (66, 74)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82755548/Homework_1.v:66: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'my_xor\'\nmodule my_xor(Z,X,Y);\n ^~~~~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1(OUT,IN0,IN1,S0);\n ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82755548/Homework_1.v:57: Signal definition not found, creating implicitly: \'X_and_Yprime\'\n : ... Suggested alternative: \'x_and_Yprime\'\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:57: Found definition of \'mn1\' as a CELL but expected a variable\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:58: Found definition of \'mn2\' as a CELL but expected a variable\n my_and ma2(Y_and_Xprime,mn2,Y);\n ^~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 301,927 | module | module my_not(C,A);
output C;
input A;
nand output_nand(C,A,A);
endmodule | module my_not(C,A); |
output C;
input A;
nand output_nand(C,A,A);
endmodule | 0 |
138,192 | data/full_repos/permissive/82755548/Homework_1.v | 82,755,548 | Homework_1.v | v | 75 | 65 | [] | [] | [] | [(12, 21), (23, 35), (37, 41), (48, 61), (66, 74)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82755548/Homework_1.v:66: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'my_xor\'\nmodule my_xor(Z,X,Y);\n ^~~~~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1(OUT,IN0,IN1,S0);\n ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82755548/Homework_1.v:57: Signal definition not found, creating implicitly: \'X_and_Yprime\'\n : ... Suggested alternative: \'x_and_Yprime\'\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:57: Found definition of \'mn1\' as a CELL but expected a variable\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:58: Found definition of \'mn2\' as a CELL but expected a variable\n my_and ma2(Y_and_Xprime,mn2,Y);\n ^~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 301,927 | module | module my_xor(Z,X,Y);
output Z;
input X,Y;
wire Y_not,X_not,x_and_Yprime,Y_and_Xprime;
my_not mn1(Y_not,Y);
my_not mn2(X_not,X);
my_and ma1(X_and_Yprime,mn1,X);
my_and ma2(Y_and_Xprime,mn2,Y);
my_or mo(Z,X_and_Yprime,Y_and_Xprime);
endmodule | module my_xor(Z,X,Y); |
output Z;
input X,Y;
wire Y_not,X_not,x_and_Yprime,Y_and_Xprime;
my_not mn1(Y_not,Y);
my_not mn2(X_not,X);
my_and ma1(X_and_Yprime,mn1,X);
my_and ma2(Y_and_Xprime,mn2,Y);
my_or mo(Z,X_and_Yprime,Y_and_Xprime);
endmodule | 0 |
138,193 | data/full_repos/permissive/82755548/Homework_1.v | 82,755,548 | Homework_1.v | v | 75 | 65 | [] | [] | [] | [(12, 21), (23, 35), (37, 41), (48, 61), (66, 74)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82755548/Homework_1.v:66: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'my_xor\'\nmodule my_xor(Z,X,Y);\n ^~~~~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1(OUT,IN0,IN1,S0);\n ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82755548/Homework_1.v:57: Signal definition not found, creating implicitly: \'X_and_Yprime\'\n : ... Suggested alternative: \'x_and_Yprime\'\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:57: Found definition of \'mn1\' as a CELL but expected a variable\n my_and ma1(X_and_Yprime,mn1,X);\n ^~~\n%Error: data/full_repos/permissive/82755548/Homework_1.v:58: Found definition of \'mn2\' as a CELL but expected a variable\n my_and ma2(Y_and_Xprime,mn2,Y);\n ^~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 301,927 | module | module mux_2to1(OUT,IN0,IN1,S0);
output OUT;
input IN0,IN1,S0;
wire S0_not;
not(S0_not,S0);
bufif0 b0(OUT,IN0,S0_not);
bufif1 b1(OUT, IN1,S0);
endmodule | module mux_2to1(OUT,IN0,IN1,S0); |
output OUT;
input IN0,IN1,S0;
wire S0_not;
not(S0_not,S0);
bufif0 b0(OUT,IN0,S0_not);
bufif1 b1(OUT, IN1,S0);
endmodule | 0 |
138,194 | data/full_repos/permissive/82755548/LAB_1/VerilogAND.v | 82,755,548 | VerilogAND.v | v | 11 | 59 | [] | [] | [] | [(6, 10)] | null | data/verilator_xmls/a9fb19a6-f329-45bf-b314-9079bd5f44a7.xml | null | 301,928 | module | module veriogAND(Fv,Av,Bv);
input Av,Bv;
output Fv;
and v_and(Fv,Av,Bv);
endmodule | module veriogAND(Fv,Av,Bv); |
input Av,Bv;
output Fv;
and v_and(Fv,Av,Bv);
endmodule | 0 |
138,195 | data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v | 82,755,548 | two_by_one_mux.v | v | 43 | 70 | [] | [] | [] | [(8, 16), (18, 42)] | null | null | 1: b'%Error: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:27: Unsupported or unknown PLI call: $monitor\n $monitor($time,"x_in=%b,y_in=%b,sel=%b,---m_out=%b\\n",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=0;local_sel=0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=1;local_sel=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=0;local_sel=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=1;local_sel=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=0;local_sel=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=1;local_sel=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=0;local_sel=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=1;local_sel=1;\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,929 | module | module two_by_one_mux(m_out,x_in,y_in,sel);
output m_out;
input x_in,y_in,sel;
wire s_not,m1,m2;
not s1(s_not,sel);
and and1(m1,s_not,x_in);
and and2(m2,sel,y_in);
or or1(m_out,m1,m2);
endmodule | module two_by_one_mux(m_out,x_in,y_in,sel); |
output m_out;
input x_in,y_in,sel;
wire s_not,m1,m2;
not s1(s_not,sel);
and and1(m1,s_not,x_in);
and and2(m2,sel,y_in);
or or1(m_out,m1,m2);
endmodule | 0 |
138,196 | data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v | 82,755,548 | two_by_one_mux.v | v | 43 | 70 | [] | [] | [] | [(8, 16), (18, 42)] | null | null | 1: b'%Error: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:27: Unsupported or unknown PLI call: $monitor\n $monitor($time,"x_in=%b,y_in=%b,sel=%b,---m_out=%b\\n",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=0;local_sel=0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=1;local_sel=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=0;local_sel=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=1;local_sel=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=0;local_sel=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=0;local_y_in=1;local_sel=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=0;local_sel=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_2/two_by_one_mux.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 local_x_in=1;local_y_in=1;local_sel=1;\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,929 | module | module mux_tb;
reg local_x_in,local_sel,local_y_in;
wire local_m_out;
two_by_one_mux tbom(local_m_out,local_x_in,local_y_in,local_sel);
initial
begin
$monitor($time,"x_in=%b,y_in=%b,sel=%b,---m_out=%b\n",
local_x_in,local_y_in,local_sel,local_m_out);
end
initial begin
local_x_in=0;local_y_in=0;local_sel=0;
#10 local_x_in=0;local_y_in=0;local_sel=0;
#10 local_x_in=0;local_y_in=1;local_sel=0;
#10 local_x_in=1;local_y_in=0;local_sel=0;
#10 local_x_in=1;local_y_in=1;local_sel=0;
#10 local_x_in=0;local_y_in=0;local_sel=1;
#10 local_x_in=0;local_y_in=1;local_sel=1;
#10 local_x_in=1;local_y_in=0;local_sel=1;
#10 local_x_in=1;local_y_in=1;local_sel=1;
end
endmodule | module mux_tb; |
reg local_x_in,local_sel,local_y_in;
wire local_m_out;
two_by_one_mux tbom(local_m_out,local_x_in,local_y_in,local_sel);
initial
begin
$monitor($time,"x_in=%b,y_in=%b,sel=%b,---m_out=%b\n",
local_x_in,local_y_in,local_sel,local_m_out);
end
initial begin
local_x_in=0;local_y_in=0;local_sel=0;
#10 local_x_in=0;local_y_in=0;local_sel=0;
#10 local_x_in=0;local_y_in=1;local_sel=0;
#10 local_x_in=1;local_y_in=0;local_sel=0;
#10 local_x_in=1;local_y_in=1;local_sel=0;
#10 local_x_in=0;local_y_in=0;local_sel=1;
#10 local_x_in=0;local_y_in=1;local_sel=1;
#10 local_x_in=1;local_y_in=0;local_sel=1;
#10 local_x_in=1;local_y_in=1;local_sel=1;
end
endmodule | 0 |
138,197 | data/full_repos/permissive/82755548/LAB_2/synth/two_by_one_mux.v | 82,755,548 | two_by_one_mux.v | v | 17 | 65 | [] | [] | [] | [(8, 16)] | null | data/verilator_xmls/ef081483-6e9a-47f5-8f18-0819ca4e1c6b.xml | null | 301,930 | module | module two_by_one_mux_synth(m_out,x_in,y_in,sel);
output m_out;
input x_in,y_in,sel;
wire s_not,m1,m2;
not s1(s_not,sel);
and and1(m1,s_not,x_in);
and and2(m2,sel,y_in);
or or1(m_out,m1,m2);
endmodule | module two_by_one_mux_synth(m_out,x_in,y_in,sel); |
output m_out;
input x_in,y_in,sel;
wire s_not,m1,m2;
not s1(s_not,sel);
and and1(m1,s_not,x_in);
and and2(m2,sel,y_in);
or or1(m_out,m1,m2);
endmodule | 0 |
138,198 | data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v | 82,755,548 | seven_seg_decoder.v | v | 91 | 88 | [] | [] | [] | null | line:87: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v:79: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v:86: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time,"binary input=%b and hex output=%h\\n",bin_in,led_out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v:87: Unsupported: Ignoring delay on this delayed statement.\n #160 $stop;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,931 | module | module seven_seg_decoder(led_out,bin_in);
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule | module seven_seg_decoder(led_out,bin_in); |
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule | 0 |
138,199 | data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v | 82,755,548 | seven_seg_decoder.v | v | 91 | 88 | [] | [] | [] | null | line:87: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v:79: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v:86: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time,"binary input=%b and hex output=%h\\n",bin_in,led_out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_3/seven_seg_decoder.v:87: Unsupported: Ignoring delay on this delayed statement.\n #160 $stop;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,931 | module | module stimulus_seven_seg;
reg [3:0] bin_in = 0000;
wire [6:0] led_out;
reg clk;
seven_seg_decoder s1(led_out,bin_in);
initial
clk = 1'b0;
always
#5 clk = ~clk;
always @(posedge clk)
bin_in = bin_in + 1;
initial
begin
$monitor("At time",$time,"binary input=%b and hex output=%h\n",bin_in,led_out);
#160 $stop;
end
endmodule | module stimulus_seven_seg; |
reg [3:0] bin_in = 0000;
wire [6:0] led_out;
reg clk;
seven_seg_decoder s1(led_out,bin_in);
initial
clk = 1'b0;
always
#5 clk = ~clk;
always @(posedge clk)
bin_in = bin_in + 1;
initial
begin
$monitor("At time",$time,"binary input=%b and hex output=%h\n",bin_in,led_out);
#160 $stop;
end
endmodule | 0 |
138,200 | data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v | 82,755,548 | eight_bit_counter.v | v | 122 | 100 | [] | [] | [] | null | line:102: before: "$" | null | 1: b'%Error: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:101: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," clear = %b, enable = %b, and count = %h\\n",clear,enable,count_out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:102: Unsupported: Ignoring delay on this delayed statement.\n #2700 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10 clear = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:111: Unsupported: Ignoring delay on this delayed statement.\n #20 enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:112: Unsupported: Ignoring delay on this delayed statement.\n #2600 clear = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock; \n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,932 | module | module eight_bit_counter(count_out,enable,clock,clear);
input enable,clock,clear;
output [7:0] count_out;
wire [6:0] temp;
wire counter_clock;
frequency_divider clk_1hz(counter_clock,clock);
t_ff tff0(count_out[0],enable,counter_clock,clear);
assign temp[0] = count_out[0] & enable;
t_ff tff1(count_out[1],temp[0],counter_clock,clear);
assign temp[1] = temp[0] & count_out[1];
t_ff tff2(count_out[2],temp[1],counter_clock,clear);
assign temp[2] = temp[1] & count_out[2];
t_ff tff3(count_out[3],temp[2],counter_clock,clear);
assign temp[3] = temp[2] & count_out[3];
t_ff tff4(count_out[4],temp[3],counter_clock,clear);
assign temp[4] = temp[3] & count_out[4];
t_ff tff5(count_out[5],temp[4],counter_clock,clear);
assign temp[5] = temp[4] & count_out[5];
t_ff tff6(count_out[6],temp[5],counter_clock,clear);
assign temp[6] = temp[5] & count_out[6];
t_ff tff7(count_out[7],temp[6],counter_clock,clear);
endmodule | module eight_bit_counter(count_out,enable,clock,clear); |
input enable,clock,clear;
output [7:0] count_out;
wire [6:0] temp;
wire counter_clock;
frequency_divider clk_1hz(counter_clock,clock);
t_ff tff0(count_out[0],enable,counter_clock,clear);
assign temp[0] = count_out[0] & enable;
t_ff tff1(count_out[1],temp[0],counter_clock,clear);
assign temp[1] = temp[0] & count_out[1];
t_ff tff2(count_out[2],temp[1],counter_clock,clear);
assign temp[2] = temp[1] & count_out[2];
t_ff tff3(count_out[3],temp[2],counter_clock,clear);
assign temp[3] = temp[2] & count_out[3];
t_ff tff4(count_out[4],temp[3],counter_clock,clear);
assign temp[4] = temp[3] & count_out[4];
t_ff tff5(count_out[5],temp[4],counter_clock,clear);
assign temp[5] = temp[4] & count_out[5];
t_ff tff6(count_out[6],temp[5],counter_clock,clear);
assign temp[6] = temp[5] & count_out[6];
t_ff tff7(count_out[7],temp[6],counter_clock,clear);
endmodule | 0 |
138,201 | data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v | 82,755,548 | eight_bit_counter.v | v | 122 | 100 | [] | [] | [] | null | line:102: before: "$" | null | 1: b'%Error: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:101: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," clear = %b, enable = %b, and count = %h\\n",clear,enable,count_out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:102: Unsupported: Ignoring delay on this delayed statement.\n #2700 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10 clear = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:111: Unsupported: Ignoring delay on this delayed statement.\n #20 enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:112: Unsupported: Ignoring delay on this delayed statement.\n #2600 clear = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock; \n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,932 | module | module frequency_divider(clock_out,clock_in);
input clock_in;
output reg clock_out;
reg [24:0] counter;
initial
begin
counter = 0;
clock_out = 0;
end
always @(posedge clock_in)
begin
if(counter == 0)
begin
counter <= 24999999;
clock_out <= ~clock_out;
end
else
counter <= counter - 1;
end
endmodule | module frequency_divider(clock_out,clock_in); |
input clock_in;
output reg clock_out;
reg [24:0] counter;
initial
begin
counter = 0;
clock_out = 0;
end
always @(posedge clock_in)
begin
if(counter == 0)
begin
counter <= 24999999;
clock_out <= ~clock_out;
end
else
counter <= counter - 1;
end
endmodule | 0 |
138,202 | data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v | 82,755,548 | eight_bit_counter.v | v | 122 | 100 | [] | [] | [] | null | line:102: before: "$" | null | 1: b'%Error: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:101: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," clear = %b, enable = %b, and count = %h\\n",clear,enable,count_out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:102: Unsupported: Ignoring delay on this delayed statement.\n #2700 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10 clear = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:111: Unsupported: Ignoring delay on this delayed statement.\n #20 enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:112: Unsupported: Ignoring delay on this delayed statement.\n #2600 clear = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock; \n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,932 | module | module t_ff(q_out,t_in,clock,clear);
input t_in,clock,clear;
output reg q_out;
always @(posedge clock or negedge clear)
begin
if(~clear)
q_out <= 1'b0;
else
q_out <= t_in ^ q_out;
end
endmodule | module t_ff(q_out,t_in,clock,clear); |
input t_in,clock,clear;
output reg q_out;
always @(posedge clock or negedge clear)
begin
if(~clear)
q_out <= 1'b0;
else
q_out <= t_in ^ q_out;
end
endmodule | 0 |
138,203 | data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v | 82,755,548 | eight_bit_counter.v | v | 122 | 100 | [] | [] | [] | null | line:102: before: "$" | null | 1: b'%Error: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:101: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," clear = %b, enable = %b, and count = %h\\n",clear,enable,count_out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:102: Unsupported: Ignoring delay on this delayed statement.\n #2700 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10 clear = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:111: Unsupported: Ignoring delay on this delayed statement.\n #20 enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:112: Unsupported: Ignoring delay on this delayed statement.\n #2600 clear = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/LAB_4/eight_bit_counter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock; \n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,932 | module | module stimulus_counter;
reg clear, enable, clock;
wire [7:0] count_out;
eight_bit_counter s1(count_out,enable,clock,clear);
initial
begin
$monitor("At time",$time," clear = %b, enable = %b, and count = %h\n",clear,enable,count_out);
#2700 $finish;
end
initial
begin
clear = 0;
enable = 0;
#10 clear = 1;
#20 enable = 1;
#2600 clear = 0;
end
initial
clock = 1'b0;
always
#5 clock = ~clock;
endmodule | module stimulus_counter; |
reg clear, enable, clock;
wire [7:0] count_out;
eight_bit_counter s1(count_out,enable,clock,clear);
initial
begin
$monitor("At time",$time," clear = %b, enable = %b, and count = %h\n",clear,enable,count_out);
#2700 $finish;
end
initial
begin
clear = 0;
enable = 0;
#10 clear = 1;
#20 enable = 1;
#2600 clear = 0;
end
initial
clock = 1'b0;
always
#5 clock = ~clock;
endmodule | 0 |
138,204 | data/full_repos/permissive/82755548/proj1_traffic_fsm/traffic_fsm.v | 82,755,548 | traffic_fsm.v | v | 301 | 88 | [] | [] | [] | [(10, 209), (216, 243), (248, 301)] | null | data/verilator_xmls/34ac92db-560c-41d0-91fc-a0338c878968.xml | null | 301,933 | module | module traffic_fsm(hex_pins,main_lights,cross_lights,sensors,clk);
input clk;
input [4:0] sensors;
output reg [4:0] main_lights;
output reg [4:0] cross_lights;
output [6:0] hex_pins;
reg [3:0] state;
parameter main_go=0,cross_go=1,
main_wait=2,cross_wait=3,
main_arrow_go=4,cross_arrow_go=5,
main_arrow_wait=6,cross_arrow_wait=7,
all_stop=8;
reg [3:0] sleep;
wire [3:0] current_count;
reg cross_tracker,cross_arrow_tracker,main_arrow_tracker;
timer tm0(current_count,sleep,clk);
seven_seg_decoder ssd(hex_pins,current_count);
initial
begin
state <= main_go;
sleep <= 6;
end
always @(posedge clk)
begin
case(state)
main_go:
begin
main_lights <= 5'b00100;
cross_lights <= 5'b10000;
end
cross_go:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00100;
end
main_wait:
begin
main_lights <= 5'b01000;
cross_lights <= 5'b10000;
end
cross_wait:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b01000;
end
main_arrow_go:
begin
main_lights <= 5'b00001;
cross_lights <= 5'b10000;
end
cross_arrow_go:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00001;
end
main_arrow_wait:
begin
main_lights <= 5'b00010;
cross_lights <= 5'b10000;
end
cross_arrow_wait:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00010;
end
all_stop:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b10000;
end
endcase
end
always @(posedge clk)
begin
if(state == main_go && (sensors[0]|sensors[1]|sensors[2]|sensors[4]))
begin
if( current_count == 4'b0001 )
sleep = 4;
if( current_count == 4'b0000 )
state = main_wait;
end
else if(state == main_wait || state == cross_wait ||
state == main_arrow_wait || state == cross_arrow_wait)
begin
if( current_count == 4'b0001 )
sleep = 3;
if( current_count == 4'b000)
state = all_stop;
end
else if(state == cross_go)
begin
if( current_count == 4'b0001 )
begin
cross_tracker = 1'b1;
sleep = 3;
if (sensors[1])
cross_arrow_tracker = 1'b1;
if (sensors[0])
main_arrow_tracker = 1'b1;
end
if( current_count == 4'b0000 )
state = cross_wait;
end
else if(state == cross_arrow_go)
begin
if( current_count == 4'b0001 )
begin
sleep = 3;
cross_arrow_tracker = 1'b0;
end
if( current_count == 4'b0000 )
state = cross_arrow_wait;
end
else if(state == main_arrow_go)
begin
if( current_count == 4'b0001 )
begin
sleep = 3;
main_arrow_tracker = 1'b0;
end
if( current_count == 4'b0000 )
state = main_arrow_wait;
end
else if(state == all_stop)
begin
if ( current_count == 4'b0001 && ~cross_tracker )
sleep = 6;
if ( current_count == 4'b0000 && ~cross_tracker )
state = cross_go;
if ( cross_tracker && (cross_arrow_tracker|main_arrow_tracker) )
begin
if ( current_count == 4'b0001 )
sleep = 4;
if ( current_count == 4'b0000 )
if ( cross_arrow_tracker )
state = cross_arrow_go;
else
state = main_arrow_go;
end
else if ( cross_tracker && (~cross_arrow_tracker && ~main_arrow_tracker) )
begin
if ( current_count == 4'b0001 )
sleep = 6;
if ( current_count == 4'b0000 )
begin
cross_tracker = 1'b0;
state = main_go;
end
end
end
end
endmodule | module traffic_fsm(hex_pins,main_lights,cross_lights,sensors,clk); |
input clk;
input [4:0] sensors;
output reg [4:0] main_lights;
output reg [4:0] cross_lights;
output [6:0] hex_pins;
reg [3:0] state;
parameter main_go=0,cross_go=1,
main_wait=2,cross_wait=3,
main_arrow_go=4,cross_arrow_go=5,
main_arrow_wait=6,cross_arrow_wait=7,
all_stop=8;
reg [3:0] sleep;
wire [3:0] current_count;
reg cross_tracker,cross_arrow_tracker,main_arrow_tracker;
timer tm0(current_count,sleep,clk);
seven_seg_decoder ssd(hex_pins,current_count);
initial
begin
state <= main_go;
sleep <= 6;
end
always @(posedge clk)
begin
case(state)
main_go:
begin
main_lights <= 5'b00100;
cross_lights <= 5'b10000;
end
cross_go:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00100;
end
main_wait:
begin
main_lights <= 5'b01000;
cross_lights <= 5'b10000;
end
cross_wait:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b01000;
end
main_arrow_go:
begin
main_lights <= 5'b00001;
cross_lights <= 5'b10000;
end
cross_arrow_go:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00001;
end
main_arrow_wait:
begin
main_lights <= 5'b00010;
cross_lights <= 5'b10000;
end
cross_arrow_wait:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00010;
end
all_stop:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b10000;
end
endcase
end
always @(posedge clk)
begin
if(state == main_go && (sensors[0]|sensors[1]|sensors[2]|sensors[4]))
begin
if( current_count == 4'b0001 )
sleep = 4;
if( current_count == 4'b0000 )
state = main_wait;
end
else if(state == main_wait || state == cross_wait ||
state == main_arrow_wait || state == cross_arrow_wait)
begin
if( current_count == 4'b0001 )
sleep = 3;
if( current_count == 4'b000)
state = all_stop;
end
else if(state == cross_go)
begin
if( current_count == 4'b0001 )
begin
cross_tracker = 1'b1;
sleep = 3;
if (sensors[1])
cross_arrow_tracker = 1'b1;
if (sensors[0])
main_arrow_tracker = 1'b1;
end
if( current_count == 4'b0000 )
state = cross_wait;
end
else if(state == cross_arrow_go)
begin
if( current_count == 4'b0001 )
begin
sleep = 3;
cross_arrow_tracker = 1'b0;
end
if( current_count == 4'b0000 )
state = cross_arrow_wait;
end
else if(state == main_arrow_go)
begin
if( current_count == 4'b0001 )
begin
sleep = 3;
main_arrow_tracker = 1'b0;
end
if( current_count == 4'b0000 )
state = main_arrow_wait;
end
else if(state == all_stop)
begin
if ( current_count == 4'b0001 && ~cross_tracker )
sleep = 6;
if ( current_count == 4'b0000 && ~cross_tracker )
state = cross_go;
if ( cross_tracker && (cross_arrow_tracker|main_arrow_tracker) )
begin
if ( current_count == 4'b0001 )
sleep = 4;
if ( current_count == 4'b0000 )
if ( cross_arrow_tracker )
state = cross_arrow_go;
else
state = main_arrow_go;
end
else if ( cross_tracker && (~cross_arrow_tracker && ~main_arrow_tracker) )
begin
if ( current_count == 4'b0001 )
sleep = 6;
if ( current_count == 4'b0000 )
begin
cross_tracker = 1'b0;
state = main_go;
end
end
end
end
endmodule | 0 |
138,205 | data/full_repos/permissive/82755548/proj1_traffic_fsm/traffic_fsm.v | 82,755,548 | traffic_fsm.v | v | 301 | 88 | [] | [] | [] | [(10, 209), (216, 243), (248, 301)] | null | data/verilator_xmls/34ac92db-560c-41d0-91fc-a0338c878968.xml | null | 301,933 | module | module timer(counter,duration,clk);
input clk;
input [3:0] duration;
output reg [3:0] counter;
reg [25:0] ticker;
parameter tick_count = 49999999;
initial
begin
ticker <= tick_count;
counter <= duration;
end
always @(posedge clk)
begin
if ( counter == 0)
begin
ticker <= tick_count;
counter <= duration;
end
ticker <= ticker - 1;
if ( ticker == 0 )
counter <= counter - 1;
end
endmodule | module timer(counter,duration,clk); |
input clk;
input [3:0] duration;
output reg [3:0] counter;
reg [25:0] ticker;
parameter tick_count = 49999999;
initial
begin
ticker <= tick_count;
counter <= duration;
end
always @(posedge clk)
begin
if ( counter == 0)
begin
ticker <= tick_count;
counter <= duration;
end
ticker <= ticker - 1;
if ( ticker == 0 )
counter <= counter - 1;
end
endmodule | 0 |
138,206 | data/full_repos/permissive/82755548/proj1_traffic_fsm/traffic_fsm.v | 82,755,548 | traffic_fsm.v | v | 301 | 88 | [] | [] | [] | [(10, 209), (216, 243), (248, 301)] | null | data/verilator_xmls/34ac92db-560c-41d0-91fc-a0338c878968.xml | null | 301,933 | module | module seven_seg_decoder(led_out,bin_in);
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule | module seven_seg_decoder(led_out,bin_in); |
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule | 0 |
138,207 | data/full_repos/permissive/82755548/proj2_elevator/elevator.v | 82,755,548 | elevator.v | v | 283 | 103 | [] | [] | [] | null | line:200: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:199: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:200: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:204: Unsupported: Ignoring delay on this delayed statement.\n #5 sw[2] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:205: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[2] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:207: Unsupported: Ignoring delay on this delayed statement.\n #50 sw[1] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:208: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[1] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:228: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," target: %h floor: %h",target,floor);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:229: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:233: Unsupported: Ignoring delay on this delayed statement.\n #5 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:234: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:236: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:237: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:239: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:240: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 10;\n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:262: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:263: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:269: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:270: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:271: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:272: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:273: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[2] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1 tb_clock = ~tb_clock; \n ^\n%Error: Exiting due to 3 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,934 | module | module elevator(current_floor,leds,switches,clock);
input [9:0] switches;
output reg [9:0] leds;
wire [9:0] is_requested;
wire [9:0] request_clear;
input clock;
output wire [4:0] current_floor;
reg [4:0] request_floor;
reg up;
elevator_car_driver cd0(request_clear,current_floor,up,request_floor,clock);
sequence_detector sd0(is_requested[0],
request_clear[0],switches[0],clock);
sequence_detector sd1(is_requested[1],
request_clear[1],switches[1],clock);
sequence_detector sd2(is_requested[2],
request_clear[2],switches[2],clock);
sequence_detector sd3(is_requested[3],
request_clear[3],switches[3],clock);
sequence_detector sd4(is_requested[4],
request_clear[4],switches[4],clock);
sequence_detector sd5(is_requested[5],
request_clear[5],switches[5],clock);
sequence_detector sd6(is_requested[6],
request_clear[6],switches[6],clock);
sequence_detector sd7(is_requested[7],
request_clear[7],switches[7],clock);
sequence_detector sd8(is_requested[8],
request_clear[8],switches[8],clock);
sequence_detector sd9(is_requested[9],
request_clear[9],switches[9],clock);
always @(posedge clock) begin
if (|is_requested) begin
if (is_requested[0]) begin
leds[0] <= 1;
request_floor <= 0;
if (current_floor > 0)
up <= 0;
end
else
leds[0] <= 0;
if (is_requested[1]) begin
leds[1] <= 1;
request_floor <= 1;
if ( current_floor > 1)
up <= 0;
else
up <= 1;
end
else
leds[1] <= 0;
if (is_requested[2]) begin
leds[2] <= 1;
request_floor <= 2;
if ( current_floor > 2)
up <= 0;
else
up <= 1;
end
else
leds[2] <= 0;
end
else
if ( current_floor < 5 ) begin
request_floor <= 0;
up <= 0;
end
else begin
request_floor <= 9;
up <= 1;
end
end
endmodule | module elevator(current_floor,leds,switches,clock); |
input [9:0] switches;
output reg [9:0] leds;
wire [9:0] is_requested;
wire [9:0] request_clear;
input clock;
output wire [4:0] current_floor;
reg [4:0] request_floor;
reg up;
elevator_car_driver cd0(request_clear,current_floor,up,request_floor,clock);
sequence_detector sd0(is_requested[0],
request_clear[0],switches[0],clock);
sequence_detector sd1(is_requested[1],
request_clear[1],switches[1],clock);
sequence_detector sd2(is_requested[2],
request_clear[2],switches[2],clock);
sequence_detector sd3(is_requested[3],
request_clear[3],switches[3],clock);
sequence_detector sd4(is_requested[4],
request_clear[4],switches[4],clock);
sequence_detector sd5(is_requested[5],
request_clear[5],switches[5],clock);
sequence_detector sd6(is_requested[6],
request_clear[6],switches[6],clock);
sequence_detector sd7(is_requested[7],
request_clear[7],switches[7],clock);
sequence_detector sd8(is_requested[8],
request_clear[8],switches[8],clock);
sequence_detector sd9(is_requested[9],
request_clear[9],switches[9],clock);
always @(posedge clock) begin
if (|is_requested) begin
if (is_requested[0]) begin
leds[0] <= 1;
request_floor <= 0;
if (current_floor > 0)
up <= 0;
end
else
leds[0] <= 0;
if (is_requested[1]) begin
leds[1] <= 1;
request_floor <= 1;
if ( current_floor > 1)
up <= 0;
else
up <= 1;
end
else
leds[1] <= 0;
if (is_requested[2]) begin
leds[2] <= 1;
request_floor <= 2;
if ( current_floor > 2)
up <= 0;
else
up <= 1;
end
else
leds[2] <= 0;
end
else
if ( current_floor < 5 ) begin
request_floor <= 0;
up <= 0;
end
else begin
request_floor <= 9;
up <= 1;
end
end
endmodule | 0 |
138,208 | data/full_repos/permissive/82755548/proj2_elevator/elevator.v | 82,755,548 | elevator.v | v | 283 | 103 | [] | [] | [] | null | line:200: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:199: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:200: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:204: Unsupported: Ignoring delay on this delayed statement.\n #5 sw[2] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:205: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[2] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:207: Unsupported: Ignoring delay on this delayed statement.\n #50 sw[1] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:208: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[1] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:228: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," target: %h floor: %h",target,floor);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:229: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:233: Unsupported: Ignoring delay on this delayed statement.\n #5 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:234: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:236: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:237: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:239: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:240: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 10;\n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:262: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:263: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:269: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:270: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:271: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:272: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:273: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[2] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1 tb_clock = ~tb_clock; \n ^\n%Error: Exiting due to 3 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,934 | module | module elevator_car_driver(clear,current_floor,direction,destination,clock);
output reg [4:0] current_floor;
output reg [9:0] clear;
input direction;
input [4:0] destination;
input clock;
reg [4:0] counter;
initial begin
current_floor <= 0;
counter <= 0;
end
always @(posedge clock) begin
current_floor <= counter;
end
always @(posedge clock) begin
if ( counter != destination ) begin
clear[counter] <= 0;
if (direction)
counter = counter + 1;
else
counter = counter - 1;
end
else
clear[counter] <= 1;
end
endmodule | module elevator_car_driver(clear,current_floor,direction,destination,clock); |
output reg [4:0] current_floor;
output reg [9:0] clear;
input direction;
input [4:0] destination;
input clock;
reg [4:0] counter;
initial begin
current_floor <= 0;
counter <= 0;
end
always @(posedge clock) begin
current_floor <= counter;
end
always @(posedge clock) begin
if ( counter != destination ) begin
clear[counter] <= 0;
if (direction)
counter = counter + 1;
else
counter = counter - 1;
end
else
clear[counter] <= 1;
end
endmodule | 0 |
138,209 | data/full_repos/permissive/82755548/proj2_elevator/elevator.v | 82,755,548 | elevator.v | v | 283 | 103 | [] | [] | [] | null | line:200: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:199: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:200: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:204: Unsupported: Ignoring delay on this delayed statement.\n #5 sw[2] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:205: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[2] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:207: Unsupported: Ignoring delay on this delayed statement.\n #50 sw[1] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:208: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[1] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:228: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," target: %h floor: %h",target,floor);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:229: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:233: Unsupported: Ignoring delay on this delayed statement.\n #5 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:234: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:236: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:237: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:239: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:240: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 10;\n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:262: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:263: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:269: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:270: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:271: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:272: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:273: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[2] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1 tb_clock = ~tb_clock; \n ^\n%Error: Exiting due to 3 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,934 | module | module sequence_detector(request,clear,switch,clock);
output reg request;
input clear,switch,clock;
reg [1:0] state;
parameter state_a=0, state_b=1,state_c=3;
initial begin
state <= state_a;
end
always @(posedge clock) begin
case (state)
state_a:
if (switch) begin
state <= state_b;
end
state_b:
if (!switch) begin
state <= state_c;
end
state_c:
if (clear) begin
request <= 0;
state <= state_a;
end
else
request <= 1;
endcase
end
endmodule | module sequence_detector(request,clear,switch,clock); |
output reg request;
input clear,switch,clock;
reg [1:0] state;
parameter state_a=0, state_b=1,state_c=3;
initial begin
state <= state_a;
end
always @(posedge clock) begin
case (state)
state_a:
if (switch) begin
state <= state_b;
end
state_b:
if (!switch) begin
state <= state_c;
end
state_c:
if (clear) begin
request <= 0;
state <= state_a;
end
else
request <= 1;
endcase
end
endmodule | 0 |
138,210 | data/full_repos/permissive/82755548/proj2_elevator/elevator.v | 82,755,548 | elevator.v | v | 283 | 103 | [] | [] | [] | null | line:200: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:199: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:200: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:204: Unsupported: Ignoring delay on this delayed statement.\n #5 sw[2] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:205: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[2] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:207: Unsupported: Ignoring delay on this delayed statement.\n #50 sw[1] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:208: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[1] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:228: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," target: %h floor: %h",target,floor);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:229: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:233: Unsupported: Ignoring delay on this delayed statement.\n #5 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:234: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:236: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:237: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:239: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:240: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 10;\n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:262: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:263: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:269: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:270: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:271: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:272: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:273: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[2] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1 tb_clock = ~tb_clock; \n ^\n%Error: Exiting due to 3 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,934 | module | module testbench_single_request;
reg tbclock;
reg [9:0] sw;
wire [4:0] cf;
wire [9:0] lights;
elevator ev0(cf,lights,sw,tbclock);
initial
tbclock = 1'b0;
always
#1 tbclock = ~tbclock;
initial begin
$monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);
#200 $finish;
end
initial begin
#5 sw[2] <= 1;
#1 sw[2] <= 0;
#50 sw[1] <= 1;
#1 sw[1] <= 0;
end
endmodule | module testbench_single_request; |
reg tbclock;
reg [9:0] sw;
wire [4:0] cf;
wire [9:0] lights;
elevator ev0(cf,lights,sw,tbclock);
initial
tbclock = 1'b0;
always
#1 tbclock = ~tbclock;
initial begin
$monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);
#200 $finish;
end
initial begin
#5 sw[2] <= 1;
#1 sw[2] <= 0;
#50 sw[1] <= 1;
#1 sw[1] <= 0;
end
endmodule | 0 |
138,211 | data/full_repos/permissive/82755548/proj2_elevator/elevator.v | 82,755,548 | elevator.v | v | 283 | 103 | [] | [] | [] | null | line:200: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:199: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:200: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:204: Unsupported: Ignoring delay on this delayed statement.\n #5 sw[2] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:205: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[2] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:207: Unsupported: Ignoring delay on this delayed statement.\n #50 sw[1] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:208: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[1] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:228: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," target: %h floor: %h",target,floor);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:229: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:233: Unsupported: Ignoring delay on this delayed statement.\n #5 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:234: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:236: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:237: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:239: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:240: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 10;\n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:262: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:263: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:269: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:270: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:271: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:272: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:273: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[2] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1 tb_clock = ~tb_clock; \n ^\n%Error: Exiting due to 3 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,934 | module | module testbench_car_driver;
reg course,tbclock;
reg [9:0] target;
wire [9:0] floor;
elevator_car_driver cd0(floor,course,target,tbclock);
initial
tbclock = 1'b0;
always
#1 tbclock = ~tbclock;
initial begin
$monitor("At time",$time," target: %h floor: %h",target,floor);
#200 $finish;
end
initial begin
#5 course <= 1;
#1 target <= 5;
#15 course <= 0;
#1 target <= 3;
#15 course <= 1;
#1 target <= 10;
end
endmodule | module testbench_car_driver; |
reg course,tbclock;
reg [9:0] target;
wire [9:0] floor;
elevator_car_driver cd0(floor,course,target,tbclock);
initial
tbclock = 1'b0;
always
#1 tbclock = ~tbclock;
initial begin
$monitor("At time",$time," target: %h floor: %h",target,floor);
#200 $finish;
end
initial begin
#5 course <= 1;
#1 target <= 5;
#15 course <= 0;
#1 target <= 3;
#15 course <= 1;
#1 target <= 10;
end
endmodule | 0 |
138,212 | data/full_repos/permissive/82755548/proj2_elevator/elevator.v | 82,755,548 | elevator.v | v | 283 | 103 | [] | [] | [] | null | line:200: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:199: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:200: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:204: Unsupported: Ignoring delay on this delayed statement.\n #5 sw[2] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:205: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[2] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:207: Unsupported: Ignoring delay on this delayed statement.\n #50 sw[1] <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:208: Unsupported: Ignoring delay on this delayed statement.\n #1 sw[1] <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1 tbclock = ~tbclock; \n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:228: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," target: %h floor: %h",target,floor);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:229: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:233: Unsupported: Ignoring delay on this delayed statement.\n #5 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:234: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:236: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:237: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:239: Unsupported: Ignoring delay on this delayed statement.\n #15 course <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:240: Unsupported: Ignoring delay on this delayed statement.\n #1 target <= 10;\n ^\n%Error: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:262: Unsupported or unknown PLI call: $monitor\n $monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:263: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:269: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:270: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[0] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:271: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:272: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[1] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:273: Unsupported: Ignoring delay on this delayed statement.\n #20 switch_in[2] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82755548/proj2_elevator/elevator.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1 tb_clock = ~tb_clock; \n ^\n%Error: Exiting due to 3 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,934 | module | module sequence_detector_testbench;
reg [9:0] switch_in;
reg tb_clock;
wire [9:0] light_out;
wire [9:0] floor_num;
elevator e0(floor_num,light_out,switch_in,tb_clock);
initial begin
$monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out);
#200 $finish;
end
initial begin
switch_in = 0;
#20 switch_in[0] = 1;
#20 switch_in[0] = 0;
#20 switch_in[1] = 1;
#20 switch_in[1] = 0;
#20 switch_in[2] = 1;
end
initial
tb_clock = 1'b0;
always
#1 tb_clock = ~tb_clock;
endmodule | module sequence_detector_testbench; |
reg [9:0] switch_in;
reg tb_clock;
wire [9:0] light_out;
wire [9:0] floor_num;
elevator e0(floor_num,light_out,switch_in,tb_clock);
initial begin
$monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out);
#200 $finish;
end
initial begin
switch_in = 0;
#20 switch_in[0] = 1;
#20 switch_in[0] = 0;
#20 switch_in[1] = 1;
#20 switch_in[1] = 0;
#20 switch_in[2] = 1;
end
initial
tb_clock = 1'b0;
always
#1 tb_clock = ~tb_clock;
endmodule | 0 |
138,213 | data/full_repos/permissive/82755548/timer/timer.v | 82,755,548 | timer.v | v | 96 | 88 | [] | [] | [] | [(1, 38), (40, 95)] | null | data/verilator_xmls/2bec0ee5-6056-420a-aa93-5ed4eba57c24.xml | null | 301,935 | module | module timer(ssd_out,clk,reset);
input clk,reset;
output [6:0] ssd_out;
reg [25:0] ticker;
reg [3:0] counter;
wire [3:0] ssd_in;
assign ssd_in = counter;
seven_seg_decoder ssd(ssd_out,ssd_in);
initial
begin
ticker = 49999999;
counter = 15;
end
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
ticker <= 49999999;
counter <= 15;
end
else
begin
ticker <= ticker - 1;
if (ticker == 0)
begin
ticker <= 49999999;
counter <= counter-1;
end
end
end
endmodule | module timer(ssd_out,clk,reset); |
input clk,reset;
output [6:0] ssd_out;
reg [25:0] ticker;
reg [3:0] counter;
wire [3:0] ssd_in;
assign ssd_in = counter;
seven_seg_decoder ssd(ssd_out,ssd_in);
initial
begin
ticker = 49999999;
counter = 15;
end
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
ticker <= 49999999;
counter <= 15;
end
else
begin
ticker <= ticker - 1;
if (ticker == 0)
begin
ticker <= 49999999;
counter <= counter-1;
end
end
end
endmodule | 0 |
138,214 | data/full_repos/permissive/82755548/timer/timer.v | 82,755,548 | timer.v | v | 96 | 88 | [] | [] | [] | [(1, 38), (40, 95)] | null | data/verilator_xmls/2bec0ee5-6056-420a-aa93-5ed4eba57c24.xml | null | 301,935 | module | module seven_seg_decoder(led_out,bin_in);
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule | module seven_seg_decoder(led_out,bin_in); |
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule | 0 |
138,215 | data/full_repos/permissive/82757492/AI/AI.v | 82,757,492 | AI.v | v | 109 | 125 | [] | [] | [] | [(2, 17), (21, 31), (36, 62), (65, 71), (73, 79), (83, 95), (97, 108)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82757492/AI/AI.v:97: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SimpleAI\'\nmodule SimpleAI (\n ^~~~~~~~\n : ... Top module \'Select2\'\nmodule Select2(\n ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 301,936 | module | module SimpleAI (
input [8:0] X_state,
input [8:0] O_state,
output wire [8:0] AIMove
);
wire [8:0] win, block, empty;
TwoInGrid winX(X_state, O_state, win);
TwoInGrid blockO(O_state, X_state, block);
Empty emptyx (~(X_state | O_state), empty);
Select3 pick(win, block, empty, AIMove);
endmodule | module SimpleAI (
input [8:0] X_state,
input [8:0] O_state,
output wire [8:0] AIMove
); |
wire [8:0] win, block, empty;
TwoInGrid winX(X_state, O_state, win);
TwoInGrid blockO(O_state, X_state, block);
Empty emptyx (~(X_state | O_state), empty);
Select3 pick(win, block, empty, AIMove);
endmodule | 0 |
138,216 | data/full_repos/permissive/82757492/AI/AI.v | 82,757,492 | AI.v | v | 109 | 125 | [] | [] | [] | [(2, 17), (21, 31), (36, 62), (65, 71), (73, 79), (83, 95), (97, 108)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82757492/AI/AI.v:97: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SimpleAI\'\nmodule SimpleAI (\n ^~~~~~~~\n : ... Top module \'Select2\'\nmodule Select2(\n ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 301,936 | module | module TwoInRow(
input [2:0] Xin,
input [2:0] Yin,
output wire [2:0] cout
);
assign cout[0] = ~Yin[0] & ~Xin[0] & Xin[1] & Xin[2];
assign cout[1] = ~Yin[1] & Xin[0] & ~Xin[1] & Xin[2];
assign cout[2] = ~Yin[2] & Xin[0] & Xin[1] & ~Xin[2];
endmodule | module TwoInRow(
input [2:0] Xin,
input [2:0] Yin,
output wire [2:0] cout
); |
assign cout[0] = ~Yin[0] & ~Xin[0] & Xin[1] & Xin[2];
assign cout[1] = ~Yin[1] & Xin[0] & ~Xin[1] & Xin[2];
assign cout[2] = ~Yin[2] & Xin[0] & Xin[1] & ~Xin[2];
endmodule | 0 |
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.