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137,899 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module latch(input G, input D, output reg Q, output reg QN);
always@(G or D)
begin
if (G)
begin
Q <= D;
QN <= ~D;
end
end
endmodule | module latch(input G, input D, output reg Q, output reg QN); |
always@(G or D)
begin
if (G)
begin
Q <= D;
QN <= ~D;
end
end
endmodule | 17 |
137,900 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module aoi211(input A, input B, input C, output Y);
assign Y = ~((A&B)|C);
endmodule | module aoi211(input A, input B, input C, output Y); |
assign Y = ~((A&B)|C);
endmodule | 17 |
137,901 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module oai211(input A, input B, input C, output Y);
assign Y = ~((A|B)&C);
endmodule | module oai211(input A, input B, input C, output Y); |
assign Y = ~((A|B)&C);
endmodule | 17 |
137,902 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module halfadder(input A, input B, output C, output Y);
assign Y = A^B;
assign C = A&B;
endmodule | module halfadder(input A, input B, output C, output Y); |
assign Y = A^B;
assign C = A&B;
endmodule | 17 |
137,903 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module fulladder(input A, input B, input CI, output CO, output Y);
assign Y = (A^B)^CI;
assign CO = ((A&B)|(B&CI))|(CI&A);
endmodule | module fulladder(input A, input B, input CI, output CO, output Y); |
assign Y = (A^B)^CI;
assign CO = ((A&B)|(B&CI))|(CI&A);
endmodule | 17 |
137,906 | data/full_repos/permissive/80622510/verilog/benchmarks_large/dspfilters/slowfil_srl_fixedtaps.v | 80,622,510 | slowfil_srl_fixedtaps.v | v | 24 | 237 | [] | [] | [] | [(1, 21), (71, 271)] | null | null | 1: b'%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/dspfilters/slowfil_srl_fixedtaps.v:23: Cannot find include file: slowfil_srl.vh\n`include "slowfil_srl.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80622510/verilog/benchmarks_large/dspfilters,data/full_repos/permissive/80622510/slowfil_srl.vh\n data/full_repos/permissive/80622510/verilog/benchmarks_large/dspfilters,data/full_repos/permissive/80622510/slowfil_srl.vh.v\n data/full_repos/permissive/80622510/verilog/benchmarks_large/dspfilters,data/full_repos/permissive/80622510/slowfil_srl.vh.sv\n slowfil_srl.vh\n slowfil_srl.vh.v\n slowfil_srl.vh.sv\n obj_dir/slowfil_srl.vh\n obj_dir/slowfil_srl.vh.v\n obj_dir/slowfil_srl.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 300,714 | module | module slowfil_srl_fixedtaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_result);
`ifdef FORMAL
parameter NTAPS=16, IW=9, TW=IW, OW=2*IW+5;
`else
parameter NTAPS=128, IW=12, TW=IW, OW=2*IW+7;
`endif
parameter [0:0] FIXED_TAPS=0;
input wire i_clk, i_reset;
input wire i_tap_wr;
input wire [(TW-1):0] i_tap;
input wire i_ce;
input wire [(IW-1):0] i_sample;
output wire o_ce;
output wire [(OW-1):0] o_result;
slowfil_srl #(.FIXED_TAPS(1), .NTAPS(NTAPS), .IW(IW), .TW(TW), .INITIAL_COEFFS("taps.hex")) fir (.i_clk(i_clk), .i_reset(i_reset), .i_tap_wr(i_tap_wr), .i_tap(i_tap), .i_ce(i_ce), .i_sample(i_sample), .o_ce(o_ce), .o_result(o_result));
endmodule | module slowfil_srl_fixedtaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_result); |
`ifdef FORMAL
parameter NTAPS=16, IW=9, TW=IW, OW=2*IW+5;
`else
parameter NTAPS=128, IW=12, TW=IW, OW=2*IW+7;
`endif
parameter [0:0] FIXED_TAPS=0;
input wire i_clk, i_reset;
input wire i_tap_wr;
input wire [(TW-1):0] i_tap;
input wire i_ce;
input wire [(IW-1):0] i_sample;
output wire o_ce;
output wire [(OW-1):0] o_result;
slowfil_srl #(.FIXED_TAPS(1), .NTAPS(NTAPS), .IW(IW), .TW(TW), .INITIAL_COEFFS("taps.hex")) fir (.i_clk(i_clk), .i_reset(i_reset), .i_tap_wr(i_tap_wr), .i_tap(i_tap), .i_ce(i_ce), .i_sample(i_sample), .o_ce(o_ce), .o_result(o_result));
endmodule | 17 |
137,907 | data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v | 80,622,510 | udp_complete_64_top.v | v | 336 | 85 | [] | [] | [] | [(1, 315)] | null | null | 1: b'%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:317: Cannot find include file: verilog-ethernet/rtl/udp_complete_64.v\n`include "verilog-ethernet/rtl/udp_complete_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet,data/full_repos/permissive/80622510/verilog-ethernet/rtl/udp_complete_64.v\n data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet,data/full_repos/permissive/80622510/verilog-ethernet/rtl/udp_complete_64.v.v\n data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet,data/full_repos/permissive/80622510/verilog-ethernet/rtl/udp_complete_64.v.sv\n verilog-ethernet/rtl/udp_complete_64.v\n verilog-ethernet/rtl/udp_complete_64.v.v\n verilog-ethernet/rtl/udp_complete_64.v.sv\n obj_dir/verilog-ethernet/rtl/udp_complete_64.v\n obj_dir/verilog-ethernet/rtl/udp_complete_64.v.v\n obj_dir/verilog-ethernet/rtl/udp_complete_64.v.sv\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:318: Cannot find include file: verilog-ethernet/rtl/udp_64.v\n`include "verilog-ethernet/rtl/udp_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:319: Cannot find include file: verilog-ethernet/rtl/ip_complete_64.v\n`include "verilog-ethernet/rtl/ip_complete_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:320: Cannot find include file: verilog-ethernet/rtl/ip_arb_mux.v\n`include "verilog-ethernet/rtl/ip_arb_mux.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:321: Cannot find include file: verilog-ethernet/rtl/../lib/axis/rtl/arbiter.v\n`include "verilog-ethernet/rtl/../lib/axis/rtl/arbiter.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:322: Cannot find include file: verilog-ethernet/rtl/arp_64.v\n`include "verilog-ethernet/rtl/arp_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:323: Cannot find include file: verilog-ethernet/rtl/ip_64.v\n`include "verilog-ethernet/rtl/ip_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:324: Cannot find include file: verilog-ethernet/rtl/eth_arb_mux.v\n`include "verilog-ethernet/rtl/eth_arb_mux.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:325: Cannot find include file: verilog-ethernet/rtl/udp_checksum_gen_64.v\n`include "verilog-ethernet/rtl/udp_checksum_gen_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:326: Cannot find include file: verilog-ethernet/rtl/udp_ip_tx_64.v\n`include "verilog-ethernet/rtl/udp_ip_tx_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:327: Cannot find include file: verilog-ethernet/rtl/udp_ip_rx_64.v\n`include "verilog-ethernet/rtl/udp_ip_rx_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:328: Cannot find include file: verilog-ethernet/lib/axis/rtl/axis_fifo.v\n`include "verilog-ethernet/lib/axis/rtl/axis_fifo.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:329: Cannot find include file: verilog-ethernet/rtl/ip_eth_tx_64.v\n`include "verilog-ethernet/rtl/ip_eth_tx_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:330: Cannot find include file: verilog-ethernet/rtl/ip_eth_rx_64.v\n`include "verilog-ethernet/rtl/ip_eth_rx_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:331: Cannot find include file: verilog-ethernet/rtl/arp_cache.v\n`include "verilog-ethernet/rtl/arp_cache.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:332: Cannot find include file: verilog-ethernet/rtl/arp_eth_tx_64.v\n`include "verilog-ethernet/rtl/arp_eth_tx_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:333: Cannot find include file: verilog-ethernet/rtl/arp_eth_rx_64.v\n`include "verilog-ethernet/rtl/arp_eth_rx_64.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:334: Cannot find include file: verilog-ethernet/lib/axis/rtl/priority_encoder.v\n`include "verilog-ethernet/lib/axis/rtl/priority_encoder.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/ethernet/udp_complete_64_top.v:335: Cannot find include file: verilog-ethernet/rtl/lfsr.v\n`include "verilog-ethernet/rtl/lfsr.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n' | 300,715 | module | module udp_complete_64_top #(
parameter ARP_CACHE_ADDR_WIDTH = 9,
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2,
parameter ARP_REQUEST_TIMEOUT = 125000000*30,
parameter UDP_CHECKSUM_GEN_ENABLE = 1,
parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11,
parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3
)
(
input wire clk,
input wire rst,
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [5:0] s_udp_ip_dscp,
input wire [1:0] s_udp_ip_ecn,
input wire [7:0] s_udp_ip_ttl,
input wire [31:0] s_udp_ip_source_ip,
input wire [31:0] s_udp_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [63:0] s_udp_payload_axis_tdata,
input wire [7:0] s_udp_payload_axis_tkeep,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_udp_eth_dest_mac,
output wire [47:0] m_udp_eth_src_mac,
output wire [15:0] m_udp_eth_type,
output wire [3:0] m_udp_ip_version,
output wire [3:0] m_udp_ip_ihl,
output wire [5:0] m_udp_ip_dscp,
output wire [1:0] m_udp_ip_ecn,
output wire [15:0] m_udp_ip_length,
output wire [15:0] m_udp_ip_identification,
output wire [2:0] m_udp_ip_flags,
output wire [12:0] m_udp_ip_fragment_offset,
output wire [7:0] m_udp_ip_ttl,
output wire [7:0] m_udp_ip_protocol,
output wire [15:0] m_udp_ip_header_checksum,
output wire [31:0] m_udp_ip_source_ip,
output wire [31:0] m_udp_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
output wire ip_rx_busy,
output wire ip_tx_busy,
output wire udp_rx_busy,
output wire udp_tx_busy,
output wire ip_rx_error_header_early_termination,
output wire ip_rx_error_payload_early_termination,
output wire ip_rx_error_invalid_header,
output wire ip_rx_error_invalid_checksum,
output wire ip_tx_error_payload_early_termination,
output wire ip_tx_error_arp_failed,
output wire udp_rx_error_header_early_termination,
output wire udp_rx_error_payload_early_termination,
output wire udp_tx_error_payload_early_termination,
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_arp_cache
);
udp_complete_64 #(
.ARP_CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT),
.UDP_CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
) top
(
.clk(clk),
.rst(rst),
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_ip_eth_dest_mac(m_ip_eth_dest_mac),
.m_ip_eth_src_mac(m_ip_eth_src_mac),
.m_ip_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_udp_ip_dscp(s_udp_ip_dscp),
.s_udp_ip_ecn(s_udp_ip_ecn),
.s_udp_ip_ttl(s_udp_ip_ttl),
.s_udp_ip_source_ip(s_udp_ip_source_ip),
.s_udp_ip_dest_ip(s_udp_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_length(s_udp_length),
.s_udp_checksum(s_udp_checksum),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_udp_eth_dest_mac(m_udp_eth_dest_mac),
.m_udp_eth_src_mac(m_udp_eth_src_mac),
.m_udp_eth_type(m_udp_eth_type),
.m_udp_ip_version(m_udp_ip_version),
.m_udp_ip_ihl(m_udp_ip_ihl),
.m_udp_ip_dscp(m_udp_ip_dscp),
.m_udp_ip_ecn(m_udp_ip_ecn),
.m_udp_ip_length(m_udp_ip_length),
.m_udp_ip_identification(m_udp_ip_identification),
.m_udp_ip_flags(m_udp_ip_flags),
.m_udp_ip_fragment_offset(m_udp_ip_fragment_offset),
.m_udp_ip_ttl(m_udp_ip_ttl),
.m_udp_ip_protocol(m_udp_ip_protocol),
.m_udp_ip_header_checksum(m_udp_ip_header_checksum),
.m_udp_ip_source_ip(m_udp_ip_source_ip),
.m_udp_ip_dest_ip(m_udp_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
.ip_rx_busy(ip_rx_busy),
.ip_tx_busy(ip_tx_busy),
.udp_rx_busy(udp_rx_busy),
.udp_tx_busy(udp_tx_busy),
.ip_rx_error_header_early_termination(ip_rx_error_header_early_termination),
.ip_rx_error_payload_early_termination(ip_rx_error_payload_early_termination),
.ip_rx_error_invalid_header(ip_rx_error_invalid_header),
.ip_rx_error_invalid_checksum(ip_rx_error_invalid_checksum),
.ip_tx_error_payload_early_termination(ip_tx_error_payload_early_termination),
.ip_tx_error_arp_failed(ip_tx_error_arp_failed),
.udp_rx_error_header_early_termination(udp_rx_error_header_early_termination),
.udp_rx_error_payload_early_termination(udp_rx_error_payload_early_termination),
.udp_tx_error_payload_early_termination(udp_tx_error_payload_early_termination),
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(clear_arp_cache)
);
endmodule | module udp_complete_64_top #(
parameter ARP_CACHE_ADDR_WIDTH = 9,
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2,
parameter ARP_REQUEST_TIMEOUT = 125000000*30,
parameter UDP_CHECKSUM_GEN_ENABLE = 1,
parameter UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH = 11,
parameter UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH = 3
)
(
input wire clk,
input wire rst,
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [5:0] s_udp_ip_dscp,
input wire [1:0] s_udp_ip_ecn,
input wire [7:0] s_udp_ip_ttl,
input wire [31:0] s_udp_ip_source_ip,
input wire [31:0] s_udp_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [63:0] s_udp_payload_axis_tdata,
input wire [7:0] s_udp_payload_axis_tkeep,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_udp_eth_dest_mac,
output wire [47:0] m_udp_eth_src_mac,
output wire [15:0] m_udp_eth_type,
output wire [3:0] m_udp_ip_version,
output wire [3:0] m_udp_ip_ihl,
output wire [5:0] m_udp_ip_dscp,
output wire [1:0] m_udp_ip_ecn,
output wire [15:0] m_udp_ip_length,
output wire [15:0] m_udp_ip_identification,
output wire [2:0] m_udp_ip_flags,
output wire [12:0] m_udp_ip_fragment_offset,
output wire [7:0] m_udp_ip_ttl,
output wire [7:0] m_udp_ip_protocol,
output wire [15:0] m_udp_ip_header_checksum,
output wire [31:0] m_udp_ip_source_ip,
output wire [31:0] m_udp_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
output wire ip_rx_busy,
output wire ip_tx_busy,
output wire udp_rx_busy,
output wire udp_tx_busy,
output wire ip_rx_error_header_early_termination,
output wire ip_rx_error_payload_early_termination,
output wire ip_rx_error_invalid_header,
output wire ip_rx_error_invalid_checksum,
output wire ip_tx_error_payload_early_termination,
output wire ip_tx_error_arp_failed,
output wire udp_rx_error_header_early_termination,
output wire udp_rx_error_payload_early_termination,
output wire udp_tx_error_payload_early_termination,
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_arp_cache
); |
udp_complete_64 #(
.ARP_CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT),
.UDP_CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH(UDP_CHECKSUM_PAYLOAD_FIFO_ADDR_WIDTH),
.UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH(UDP_CHECKSUM_HEADER_FIFO_ADDR_WIDTH)
) top
(
.clk(clk),
.rst(rst),
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_ip_eth_dest_mac(m_ip_eth_dest_mac),
.m_ip_eth_src_mac(m_ip_eth_src_mac),
.m_ip_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_udp_ip_dscp(s_udp_ip_dscp),
.s_udp_ip_ecn(s_udp_ip_ecn),
.s_udp_ip_ttl(s_udp_ip_ttl),
.s_udp_ip_source_ip(s_udp_ip_source_ip),
.s_udp_ip_dest_ip(s_udp_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_length(s_udp_length),
.s_udp_checksum(s_udp_checksum),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_udp_eth_dest_mac(m_udp_eth_dest_mac),
.m_udp_eth_src_mac(m_udp_eth_src_mac),
.m_udp_eth_type(m_udp_eth_type),
.m_udp_ip_version(m_udp_ip_version),
.m_udp_ip_ihl(m_udp_ip_ihl),
.m_udp_ip_dscp(m_udp_ip_dscp),
.m_udp_ip_ecn(m_udp_ip_ecn),
.m_udp_ip_length(m_udp_ip_length),
.m_udp_ip_identification(m_udp_ip_identification),
.m_udp_ip_flags(m_udp_ip_flags),
.m_udp_ip_fragment_offset(m_udp_ip_fragment_offset),
.m_udp_ip_ttl(m_udp_ip_ttl),
.m_udp_ip_protocol(m_udp_ip_protocol),
.m_udp_ip_header_checksum(m_udp_ip_header_checksum),
.m_udp_ip_source_ip(m_udp_ip_source_ip),
.m_udp_ip_dest_ip(m_udp_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
.ip_rx_busy(ip_rx_busy),
.ip_tx_busy(ip_tx_busy),
.udp_rx_busy(udp_rx_busy),
.udp_tx_busy(udp_tx_busy),
.ip_rx_error_header_early_termination(ip_rx_error_header_early_termination),
.ip_rx_error_payload_early_termination(ip_rx_error_payload_early_termination),
.ip_rx_error_invalid_header(ip_rx_error_invalid_header),
.ip_rx_error_invalid_checksum(ip_rx_error_invalid_checksum),
.ip_tx_error_payload_early_termination(ip_tx_error_payload_early_termination),
.ip_tx_error_arp_failed(ip_tx_error_arp_failed),
.udp_rx_error_header_early_termination(udp_rx_error_header_early_termination),
.udp_rx_error_payload_early_termination(udp_rx_error_payload_early_termination),
.udp_tx_error_payload_early_termination(udp_tx_error_payload_early_termination),
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(clear_arp_cache)
);
endmodule | 17 |
137,908 | data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v | 80,622,510 | marlann_compute.v | v | 564 | 133 | [] | [] | [] | null | line:150 column:26: Illegal character "'" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:167: Operator OR expects 11 bits on the LHS, but LHS\'s VARREF \'memlock_res\' generates 10 bits.\n : ... In instance marlann_compute\n {memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10\'b 0 : memlock_mask);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:167: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s CONST \'10\'h0\' generates 10 bits.\n : ... In instance marlann_compute\n {memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10\'b 0 : memlock_mask);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:167: Operator COND expects 11 bits on the Conditional False, but Conditional False\'s VARREF \'memlock_mask\' generates 10 bits.\n : ... In instance marlann_compute\n {memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10\'b 0 : memlock_mask);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:218: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance marlann_compute\n mem_rd0_addr <= \'bx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:227: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_rd0_addr <= s1_insn[31:15] >> 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:238: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_rd0_addr <= (s1_insn[31:15] + VBP) >> 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:297: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[0*9 +: 9] <= s4_coeff[0*8 +: 8] ? $signed(mem_rdata[0*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:297: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[0*9 +: 9] <= s4_coeff[0*8 +: 8] ? $signed(mem_rdata[0*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:298: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[1*9 +: 9] <= s4_coeff[1*8 +: 8] ? $signed(mem_rdata[1*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:298: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[1*9 +: 9] <= s4_coeff[1*8 +: 8] ? $signed(mem_rdata[1*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:299: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[2*9 +: 9] <= s4_coeff[2*8 +: 8] ? $signed(mem_rdata[2*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:299: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[2*9 +: 9] <= s4_coeff[2*8 +: 8] ? $signed(mem_rdata[2*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:300: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[3*9 +: 9] <= s4_coeff[3*8 +: 8] ? $signed(mem_rdata[3*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:300: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[3*9 +: 9] <= s4_coeff[3*8 +: 8] ? $signed(mem_rdata[3*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:301: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[4*9 +: 9] <= s4_coeff[4*8 +: 8] ? $signed(mem_rdata[4*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:301: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[4*9 +: 9] <= s4_coeff[4*8 +: 8] ? $signed(mem_rdata[4*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:302: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[5*9 +: 9] <= s4_coeff[5*8 +: 8] ? $signed(mem_rdata[5*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:302: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[5*9 +: 9] <= s4_coeff[5*8 +: 8] ? $signed(mem_rdata[5*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:303: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[6*9 +: 9] <= s4_coeff[6*8 +: 8] ? $signed(mem_rdata[6*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:303: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[6*9 +: 9] <= s4_coeff[6*8 +: 8] ? $signed(mem_rdata[6*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:304: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[7*9 +: 9] <= s4_coeff[7*8 +: 8] ? $signed(mem_rdata[7*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:304: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[7*9 +: 9] <= s4_coeff[7*8 +: 8] ? $signed(mem_rdata[7*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:307: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance marlann_compute\n mem_rd1_addr <= \'bx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:336: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_rd1_addr <= (s4_insn[31:15] + LBP) >> 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the LHS, but LHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:398: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:398: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:398: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the LHS, but LHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:401: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:401: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:401: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:404: Operator GTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 9 bits.\n : ... In instance marlann_compute\n s8_maxen <= ($signed(s7_max[0*9 +: 9]) > $signed(acc0zn)) || ($signed(s7_max[1*9 +: 9]) > $signed(acc0zn));\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:404: Operator GTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 9 bits.\n : ... In instance marlann_compute\n s8_maxen <= ($signed(s7_max[0*9 +: 9]) > $signed(acc0zn)) || ($signed(s7_max[1*9 +: 9]) > $signed(acc0zn));\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:437: Operator ADD expects 32 bits on the RHS, but RHS\'s SIGNED generates 20 bits.\n : ... In instance marlann_compute\n new_acc0_add = $signed(new_acc0_add) + $signed(s8_sum0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:438: Operator ADD expects 32 bits on the RHS, but RHS\'s SIGNED generates 20 bits.\n : ... In instance marlann_compute\n new_acc1_add = $signed(new_acc1_add) + $signed(s8_sum1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:441: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'s8_max\' generates 9 bits.\n : ... In instance marlann_compute\n new_acc0_max = s8_maxen ? s8_max : new_acc0_max;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:502: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_wr_addr = pre_mem_wr_addr >> 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:506: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_wr_addr = pre_mem_wr_addr >> 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:516: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n : ... In instance marlann_compute\n pre_mem_wr_wdata <= {\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance marlann_compute\n pre_mem_wr_en <= {!s9_insn[0], !s9_insn[1]};\n ^~\n%Error: Exiting due to 49 warning(s)\n' | 300,716 | module | module marlann_compute #(
parameter integer NB = 2,
parameter integer CODE_SIZE = 512,
parameter integer COEFF_SIZE = 512
) (
input clock,
input reset,
output busy,
input cmd_valid,
output cmd_ready,
input [31:0] cmd_insn,
output mem_ren,
output [ 7:0] mem_wen,
output [15:0] mem_addr,
output [63:0] mem_wdata,
input [63:0] mem_rdata,
output tick_simd,
output tick_nosimd
);
integer i;
reg [31:0] code_mem [0:CODE_SIZE-1];
reg [64*NB-1:0] coeff_mem [0:COEFF_SIZE-1];
reg [31:0] acc0, acc1;
reg [16:0] VBP, LBP, SBP;
reg [ 8:0] CBP;
reg mem_rd0_en;
reg [15:0] mem_rd0_addr;
reg mem_rd1_en;
reg [15:0] mem_rd1_addr;
reg [ 7:0] mem_wr_en;
reg [15:0] mem_wr_addr;
reg [63:0] mem_wr_wdata;
assign mem_ren = mem_rd0_en || mem_rd1_en;
assign mem_wen = mem_wr_en;
assign mem_addr = ({16{mem_rd0_en}} & mem_rd0_addr) | ({16{mem_rd1_en}} & mem_rd1_addr) | ({16{|mem_wr_en}} & mem_wr_addr);
assign mem_wdata = mem_wr_wdata;
wire [16:0] cmd_insn_maddr = cmd_insn[31:15];
wire [8:0] cmd_insn_caddr = cmd_insn[14:6];
wire [5:0] cmd_insn_opcode = cmd_insn[5:0];
reg s1_en;
wire [ 31:0] s1_insn;
wire s1_stall;
reg s2_en;
reg [ 31:0] s2_insn;
reg s3_en;
reg [ 31:0] s3_insn;
reg s3a_en;
reg [ 31:0] s3a_insn;
reg s4_en;
reg [ 31:0] s4_insn;
reg [ NB*64-1:0] s4_coeff;
reg s5_en;
reg [ 31:0] s5_insn;
reg [ 8*9-1:0] s5_max;
reg s6_en;
reg [ 31:0] s6_insn;
reg [ 4*9-1:0] s6_max;
reg s7_en;
reg [ 31:0] s7_insn;
wire [ NB*128-1:0] s7_prod;
reg [ 2*9-1:0] s7_max;
reg s8_en;
reg [ 31:0] s8_insn;
reg [ 19:0] s8_sum0;
reg [ 19:0] s8_sum1;
reg [ 8:0] s8_max;
reg s8_maxen;
reg s9_en;
reg [ 31:0] s9_insn;
reg [9:0] memlock_res;
reg [9:0] memlock_mask;
reg memlock_expect;
always @* begin
memlock_mask = 0;
case (s1_insn[5:0])
4, 5, 6: memlock_mask = 1 << 0;
28, 29, 30, 32, 33, 34: begin
memlock_mask = 1 << 4;
end
40, 41, 42, 43, 45: memlock_mask = 1 << 0;
16, 17, 18, 20, 21, 22, 24, 25, 26: memlock_mask = 1 << 9;
endcase
if (!s1_en || reset)
memlock_mask = 0;
end
reg maxlock_a;
reg maxlock_b;
reg maxlock_a_q;
always @* begin
maxlock_a = 0;
maxlock_b = 0;
case (s1_insn[5:0] & 6'b 1111_00)
28, 32, 40, 44: maxlock_a = 1;
endcase
case (s1_insn[5:0])
41, 43, 45, 47: maxlock_b = 1;
endcase
if (!s1_en || reset) begin
maxlock_a = 0;
maxlock_b = 0;
end
end
assign s1_stall = |(memlock_res & memlock_mask) || (maxlock_b && maxlock_a_q);
always @(posedge clock) begin
{memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10'b 0 : memlock_mask);
maxlock_a_q <= maxlock_a && !s1_stall;
if (reset) begin
memlock_res <= 0;
memlock_expect <= 0;
maxlock_a_q <= 0;
end
end
assign cmd_ready = !s1_stall;
assign busy = |{s1_en, s2_en, s3_en, s4_en, s5_en, s6_en, s7_en, s8_en};
reg [31:0] s1_insn_direct;
reg [31:0] s1_insn_codemem;
reg s1_insn_sel;
assign s1_insn = s1_insn_sel ? s1_insn_codemem : s1_insn_direct;
wire [16:0] s1_insn_maddr = s1_insn[31:15];
wire [8:0] s1_insn_caddr = s1_insn[14:6];
wire [5:0] s1_insn_opcode = s1_insn[5:0];
always @(posedge clock) begin
if (!s1_stall) begin
s1_en <= cmd_valid && cmd_ready;
s1_insn_direct <= cmd_insn;
s1_insn_codemem <= code_mem[cmd_insn[14:6]];
s1_insn_sel <= cmd_insn[5:0] == 3;
end
if (reset) begin
s1_en <= 0;
end
end
reg s2_tick_simd;
always @(posedge clock) begin
s2_en <= 0;
s2_insn <= s1_insn;
s2_tick_simd <= 0;
mem_rd0_en <= 0;
mem_rd0_addr <= 'bx;
if (!reset && s1_en && !s1_stall) begin
s2_en <= 1;
case (s1_insn[5:0])
4, 5, 6: begin
mem_rd0_en <= 1;
mem_rd0_addr <= s1_insn[31:15] >> 1;
end
8, 9: begin
VBP <= s1_insn[31:15] + (s1_insn[0] ? VBP : 0);
end
40, 41, 42, 43, 45: begin
mem_rd0_en <= 1;
mem_rd0_addr <= (s1_insn[31:15] + VBP) >> 1;
s2_tick_simd <= 1;
end
endcase
end
end
assign tick_simd = s2_tick_simd;
assign tick_nosimd = s2_en && !tick_simd;
always @(posedge clock) begin
s3_en <= 0;
s3_insn <= s2_insn;
if (!reset && s2_en) begin
s3_en <= 1;
end
end
always @(posedge clock) begin
s3a_en <= 0;
s3a_insn <= s3_insn;
if (!reset && s3_en) begin
s3a_en <= 1;
end
end
always @(posedge clock) begin
s4_en <= 0;
s4_insn <= s3a_insn;
s4_coeff <= coeff_mem[s3a_insn[14:6] + CBP];
if (!reset && s3a_en) begin
s4_en <= 1;
if (s3a_insn[5:0] == 14 || s3a_insn[5:0] == 15) begin
CBP <= s3a_insn[14:6] + (s3a_insn[0] ? CBP : 0);
end
end
end
always @(posedge clock) begin
s5_en <= 0;
s5_insn <= s4_insn;
s5_max[0*9 +: 9] <= s4_coeff[0*8 +: 8] ? $signed(mem_rdata[0*8 +: 8]) : 9'h100;
s5_max[1*9 +: 9] <= s4_coeff[1*8 +: 8] ? $signed(mem_rdata[1*8 +: 8]) : 9'h100;
s5_max[2*9 +: 9] <= s4_coeff[2*8 +: 8] ? $signed(mem_rdata[2*8 +: 8]) : 9'h100;
s5_max[3*9 +: 9] <= s4_coeff[3*8 +: 8] ? $signed(mem_rdata[3*8 +: 8]) : 9'h100;
s5_max[4*9 +: 9] <= s4_coeff[4*8 +: 8] ? $signed(mem_rdata[4*8 +: 8]) : 9'h100;
s5_max[5*9 +: 9] <= s4_coeff[5*8 +: 8] ? $signed(mem_rdata[5*8 +: 8]) : 9'h100;
s5_max[6*9 +: 9] <= s4_coeff[6*8 +: 8] ? $signed(mem_rdata[6*8 +: 8]) : 9'h100;
s5_max[7*9 +: 9] <= s4_coeff[7*8 +: 8] ? $signed(mem_rdata[7*8 +: 8]) : 9'h100;
mem_rd1_en <= 0;
mem_rd1_addr <= 'bx;
if (!reset && s4_en) begin
s5_en <= 1;
case (s4_insn[5:0])
4: begin
code_mem[s4_insn[14:6]] <= mem_rdata[31:0];
end
5: begin
coeff_mem[s4_insn[14:6]][63:0] <= mem_rdata;
end
6: begin
coeff_mem[s4_insn[14:6]][127:64] <= mem_rdata;
end
10, 11: begin
LBP <= s4_insn[31:15] + (s4_insn[0] ? LBP : 0);
end
28, 29, 30, 32, 33, 34: begin
mem_rd1_en <= 1;
mem_rd1_addr <= (s4_insn[31:15] + LBP) >> 1;
end
endcase
end
end
always @(posedge clock) begin
s6_en <= 0;
s6_insn <= s5_insn;
s6_max[0*9 +: 9] <= $signed(s5_max[0*9 +: 9]) > $signed(s5_max[1*9 +: 9]) ? s5_max[0*9 +: 9] : s5_max[1*9 +: 9];
s6_max[1*9 +: 9] <= $signed(s5_max[2*9 +: 9]) > $signed(s5_max[3*9 +: 9]) ? s5_max[2*9 +: 9] : s5_max[3*9 +: 9];
s6_max[2*9 +: 9] <= $signed(s5_max[4*9 +: 9]) > $signed(s5_max[5*9 +: 9]) ? s5_max[4*9 +: 9] : s5_max[5*9 +: 9];
s6_max[3*9 +: 9] <= $signed(s5_max[6*9 +: 9]) > $signed(s5_max[7*9 +: 9]) ? s5_max[6*9 +: 9] : s5_max[7*9 +: 9];
if (!reset && s5_en) begin
s6_en <= 1;
end
end
wire [NB*64-1:0] mulA = {mem_rdata, mem_rdata};
marlann_compute_mul2 mul [NB*4-1:0] (
.clock (clock ),
.A (mulA ),
.B (s4_coeff),
.X (s7_prod )
);
always @(posedge clock) begin
s7_en <= 0;
s7_insn <= s6_insn;
s7_max[0*9 +: 9] <= $signed(s6_max[0*9 +: 9]) > $signed(s6_max[1*9 +: 9]) ? s6_max[0*9 +: 9] : s6_max[1*9 +: 9];
s7_max[1*9 +: 9] <= $signed(s6_max[2*9 +: 9]) > $signed(s6_max[3*9 +: 9]) ? s6_max[2*9 +: 9] : s6_max[3*9 +: 9];
if (!reset && s6_en) begin
s7_en <= 1;
end
end
reg [31:0] acc0zn;
always @* begin
acc0zn = s7_insn[1] ? 0 : acc0;
acc0zn = s7_insn[2] ? 32'h 8000_0000 : acc0zn;
end
always @(posedge clock) begin
s8_en <= 0;
s8_insn <= s7_insn;
s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +
$signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);
s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +
$signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);
s8_max <= $signed(s7_max[0*9 +: 9]) > $signed(s7_max[1*9 +: 9]) ? s7_max[0*9 +: 9] : s7_max[1*9 +: 9];
s8_maxen <= ($signed(s7_max[0*9 +: 9]) > $signed(acc0zn)) || ($signed(s7_max[1*9 +: 9]) > $signed(acc0zn));
if (!reset && s7_en) begin
s8_en <= 1;
end
end
reg [31:0] new_acc0_add;
reg [31:0] new_acc1_add;
reg [31:0] new_acc0_max;
reg [31:0] new_acc0;
reg [31:0] new_acc1;
wire [31:0] acc0_shifted = $signed(acc0) >>> s8_insn[14:6];
wire [31:0] acc1_shifted = $signed(acc1) >>> s8_insn[14:6];
reg [7:0] acc0_saturated;
reg [7:0] acc1_saturated;
reg new_acc0_max_cmp;
reg new_acc0_max_cmp_q;
always @* begin
new_acc0_add = s8_insn[1] ? 0 : acc0;
new_acc1_add = s8_insn[1] || s8_insn[2] ? 0 : acc1;
new_acc0_max = s8_insn[2] ? 32'h 8000_0000 : new_acc0_add;
new_acc0_add = $signed(new_acc0_add) + $signed(s8_sum0);
new_acc1_add = $signed(new_acc1_add) + $signed(s8_sum1);
if (s8_max != 9'h 100)
new_acc0_max = s8_maxen ? s8_max : new_acc0_max;
new_acc0 = s8_insn[0] ? new_acc0_max : new_acc0_add;
new_acc1 = new_acc1_add;
end
always @(posedge clock) begin
s9_en <= 0;
s9_insn <= s8_insn;
if (!reset && s8_en) begin
s9_en <= 1;
if (s8_insn[5:3] == 3'b 101) begin
acc0 <= new_acc0;
acc1 <= new_acc1;
end
if (s8_insn[5:0] == 28 || s8_insn[5:0] == 29) begin
acc0 <= mem_rdata[31:0];
end
if (s8_insn[5:0] == 28 || s8_insn[5:0] == 30) begin
acc1 <= mem_rdata[63:32];
end
if (s8_insn[5:0] == 32 || s8_insn[5:0] == 33) begin
acc0 <= acc0 + mem_rdata[31:0];
end
if (s8_insn[5:0] == 32 || s8_insn[5:0] == 34) begin
acc1 <= acc1 + mem_rdata[63:32];
end
end
if (&acc0_shifted[31:7] == |acc0_shifted[31:7])
acc0_saturated <= acc0_shifted[7:0];
else
acc0_saturated <= acc0_shifted[31] ? -128 : 127;
if (&acc1_shifted[31:7] == |acc1_shifted[31:7])
acc1_saturated <= acc1_shifted[7:0];
else
acc1_saturated <= acc1_shifted[31] ? -128 : 127;
end
reg [ 7:0] pre_mem_wr_en;
reg [16:0] pre_mem_wr_addr;
reg [63:0] pre_mem_wr_wdata;
always @* begin
if (pre_mem_wr_addr[0]) begin
mem_wr_en = pre_mem_wr_en << 1;
mem_wr_addr = pre_mem_wr_addr >> 1;
mem_wr_wdata = pre_mem_wr_wdata << 8;
end else begin
mem_wr_en = pre_mem_wr_en;
mem_wr_addr = pre_mem_wr_addr >> 1;
mem_wr_wdata = pre_mem_wr_wdata;
end
end
wire [5:0] s9_insn_opcode = s9_insn[5:0];
always @(posedge clock) begin
pre_mem_wr_en <= 0;
pre_mem_wr_addr <= s9_insn[31:15] + SBP;
pre_mem_wr_wdata <= {
{8{!s9_insn[2] || !acc1_saturated[7]}} & acc1_saturated,
{8{!s9_insn[2] || !acc0_saturated[7]}} & acc0_saturated
};
if (s9_en) begin
if (s9_insn[5:3] == 3'b 010) begin
pre_mem_wr_en <= {!s9_insn[0], !s9_insn[1]};
end
if (s9_insn[5:2] == 4'b 0110) begin
pre_mem_wr_en <= {{4{!s9_insn[0]}}, {4{!s9_insn[1]}}};
pre_mem_wr_wdata <= {acc1, acc0};
end
if (s9_insn[5:0] == 12 || s9_insn[5:0] == 13) begin
SBP <= s9_insn[31:15] + (s9_insn[0] ? SBP : 0);
end
end
if (reset || !s9_en) begin
pre_mem_wr_en <= 0;
end
end
endmodule | module marlann_compute #(
parameter integer NB = 2,
parameter integer CODE_SIZE = 512,
parameter integer COEFF_SIZE = 512
) (
input clock,
input reset,
output busy,
input cmd_valid,
output cmd_ready,
input [31:0] cmd_insn,
output mem_ren,
output [ 7:0] mem_wen,
output [15:0] mem_addr,
output [63:0] mem_wdata,
input [63:0] mem_rdata,
output tick_simd,
output tick_nosimd
); |
integer i;
reg [31:0] code_mem [0:CODE_SIZE-1];
reg [64*NB-1:0] coeff_mem [0:COEFF_SIZE-1];
reg [31:0] acc0, acc1;
reg [16:0] VBP, LBP, SBP;
reg [ 8:0] CBP;
reg mem_rd0_en;
reg [15:0] mem_rd0_addr;
reg mem_rd1_en;
reg [15:0] mem_rd1_addr;
reg [ 7:0] mem_wr_en;
reg [15:0] mem_wr_addr;
reg [63:0] mem_wr_wdata;
assign mem_ren = mem_rd0_en || mem_rd1_en;
assign mem_wen = mem_wr_en;
assign mem_addr = ({16{mem_rd0_en}} & mem_rd0_addr) | ({16{mem_rd1_en}} & mem_rd1_addr) | ({16{|mem_wr_en}} & mem_wr_addr);
assign mem_wdata = mem_wr_wdata;
wire [16:0] cmd_insn_maddr = cmd_insn[31:15];
wire [8:0] cmd_insn_caddr = cmd_insn[14:6];
wire [5:0] cmd_insn_opcode = cmd_insn[5:0];
reg s1_en;
wire [ 31:0] s1_insn;
wire s1_stall;
reg s2_en;
reg [ 31:0] s2_insn;
reg s3_en;
reg [ 31:0] s3_insn;
reg s3a_en;
reg [ 31:0] s3a_insn;
reg s4_en;
reg [ 31:0] s4_insn;
reg [ NB*64-1:0] s4_coeff;
reg s5_en;
reg [ 31:0] s5_insn;
reg [ 8*9-1:0] s5_max;
reg s6_en;
reg [ 31:0] s6_insn;
reg [ 4*9-1:0] s6_max;
reg s7_en;
reg [ 31:0] s7_insn;
wire [ NB*128-1:0] s7_prod;
reg [ 2*9-1:0] s7_max;
reg s8_en;
reg [ 31:0] s8_insn;
reg [ 19:0] s8_sum0;
reg [ 19:0] s8_sum1;
reg [ 8:0] s8_max;
reg s8_maxen;
reg s9_en;
reg [ 31:0] s9_insn;
reg [9:0] memlock_res;
reg [9:0] memlock_mask;
reg memlock_expect;
always @* begin
memlock_mask = 0;
case (s1_insn[5:0])
4, 5, 6: memlock_mask = 1 << 0;
28, 29, 30, 32, 33, 34: begin
memlock_mask = 1 << 4;
end
40, 41, 42, 43, 45: memlock_mask = 1 << 0;
16, 17, 18, 20, 21, 22, 24, 25, 26: memlock_mask = 1 << 9;
endcase
if (!s1_en || reset)
memlock_mask = 0;
end
reg maxlock_a;
reg maxlock_b;
reg maxlock_a_q;
always @* begin
maxlock_a = 0;
maxlock_b = 0;
case (s1_insn[5:0] & 6'b 1111_00)
28, 32, 40, 44: maxlock_a = 1;
endcase
case (s1_insn[5:0])
41, 43, 45, 47: maxlock_b = 1;
endcase
if (!s1_en || reset) begin
maxlock_a = 0;
maxlock_b = 0;
end
end
assign s1_stall = |(memlock_res & memlock_mask) || (maxlock_b && maxlock_a_q);
always @(posedge clock) begin
{memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10'b 0 : memlock_mask);
maxlock_a_q <= maxlock_a && !s1_stall;
if (reset) begin
memlock_res <= 0;
memlock_expect <= 0;
maxlock_a_q <= 0;
end
end
assign cmd_ready = !s1_stall;
assign busy = |{s1_en, s2_en, s3_en, s4_en, s5_en, s6_en, s7_en, s8_en};
reg [31:0] s1_insn_direct;
reg [31:0] s1_insn_codemem;
reg s1_insn_sel;
assign s1_insn = s1_insn_sel ? s1_insn_codemem : s1_insn_direct;
wire [16:0] s1_insn_maddr = s1_insn[31:15];
wire [8:0] s1_insn_caddr = s1_insn[14:6];
wire [5:0] s1_insn_opcode = s1_insn[5:0];
always @(posedge clock) begin
if (!s1_stall) begin
s1_en <= cmd_valid && cmd_ready;
s1_insn_direct <= cmd_insn;
s1_insn_codemem <= code_mem[cmd_insn[14:6]];
s1_insn_sel <= cmd_insn[5:0] == 3;
end
if (reset) begin
s1_en <= 0;
end
end
reg s2_tick_simd;
always @(posedge clock) begin
s2_en <= 0;
s2_insn <= s1_insn;
s2_tick_simd <= 0;
mem_rd0_en <= 0;
mem_rd0_addr <= 'bx;
if (!reset && s1_en && !s1_stall) begin
s2_en <= 1;
case (s1_insn[5:0])
4, 5, 6: begin
mem_rd0_en <= 1;
mem_rd0_addr <= s1_insn[31:15] >> 1;
end
8, 9: begin
VBP <= s1_insn[31:15] + (s1_insn[0] ? VBP : 0);
end
40, 41, 42, 43, 45: begin
mem_rd0_en <= 1;
mem_rd0_addr <= (s1_insn[31:15] + VBP) >> 1;
s2_tick_simd <= 1;
end
endcase
end
end
assign tick_simd = s2_tick_simd;
assign tick_nosimd = s2_en && !tick_simd;
always @(posedge clock) begin
s3_en <= 0;
s3_insn <= s2_insn;
if (!reset && s2_en) begin
s3_en <= 1;
end
end
always @(posedge clock) begin
s3a_en <= 0;
s3a_insn <= s3_insn;
if (!reset && s3_en) begin
s3a_en <= 1;
end
end
always @(posedge clock) begin
s4_en <= 0;
s4_insn <= s3a_insn;
s4_coeff <= coeff_mem[s3a_insn[14:6] + CBP];
if (!reset && s3a_en) begin
s4_en <= 1;
if (s3a_insn[5:0] == 14 || s3a_insn[5:0] == 15) begin
CBP <= s3a_insn[14:6] + (s3a_insn[0] ? CBP : 0);
end
end
end
always @(posedge clock) begin
s5_en <= 0;
s5_insn <= s4_insn;
s5_max[0*9 +: 9] <= s4_coeff[0*8 +: 8] ? $signed(mem_rdata[0*8 +: 8]) : 9'h100;
s5_max[1*9 +: 9] <= s4_coeff[1*8 +: 8] ? $signed(mem_rdata[1*8 +: 8]) : 9'h100;
s5_max[2*9 +: 9] <= s4_coeff[2*8 +: 8] ? $signed(mem_rdata[2*8 +: 8]) : 9'h100;
s5_max[3*9 +: 9] <= s4_coeff[3*8 +: 8] ? $signed(mem_rdata[3*8 +: 8]) : 9'h100;
s5_max[4*9 +: 9] <= s4_coeff[4*8 +: 8] ? $signed(mem_rdata[4*8 +: 8]) : 9'h100;
s5_max[5*9 +: 9] <= s4_coeff[5*8 +: 8] ? $signed(mem_rdata[5*8 +: 8]) : 9'h100;
s5_max[6*9 +: 9] <= s4_coeff[6*8 +: 8] ? $signed(mem_rdata[6*8 +: 8]) : 9'h100;
s5_max[7*9 +: 9] <= s4_coeff[7*8 +: 8] ? $signed(mem_rdata[7*8 +: 8]) : 9'h100;
mem_rd1_en <= 0;
mem_rd1_addr <= 'bx;
if (!reset && s4_en) begin
s5_en <= 1;
case (s4_insn[5:0])
4: begin
code_mem[s4_insn[14:6]] <= mem_rdata[31:0];
end
5: begin
coeff_mem[s4_insn[14:6]][63:0] <= mem_rdata;
end
6: begin
coeff_mem[s4_insn[14:6]][127:64] <= mem_rdata;
end
10, 11: begin
LBP <= s4_insn[31:15] + (s4_insn[0] ? LBP : 0);
end
28, 29, 30, 32, 33, 34: begin
mem_rd1_en <= 1;
mem_rd1_addr <= (s4_insn[31:15] + LBP) >> 1;
end
endcase
end
end
always @(posedge clock) begin
s6_en <= 0;
s6_insn <= s5_insn;
s6_max[0*9 +: 9] <= $signed(s5_max[0*9 +: 9]) > $signed(s5_max[1*9 +: 9]) ? s5_max[0*9 +: 9] : s5_max[1*9 +: 9];
s6_max[1*9 +: 9] <= $signed(s5_max[2*9 +: 9]) > $signed(s5_max[3*9 +: 9]) ? s5_max[2*9 +: 9] : s5_max[3*9 +: 9];
s6_max[2*9 +: 9] <= $signed(s5_max[4*9 +: 9]) > $signed(s5_max[5*9 +: 9]) ? s5_max[4*9 +: 9] : s5_max[5*9 +: 9];
s6_max[3*9 +: 9] <= $signed(s5_max[6*9 +: 9]) > $signed(s5_max[7*9 +: 9]) ? s5_max[6*9 +: 9] : s5_max[7*9 +: 9];
if (!reset && s5_en) begin
s6_en <= 1;
end
end
wire [NB*64-1:0] mulA = {mem_rdata, mem_rdata};
marlann_compute_mul2 mul [NB*4-1:0] (
.clock (clock ),
.A (mulA ),
.B (s4_coeff),
.X (s7_prod )
);
always @(posedge clock) begin
s7_en <= 0;
s7_insn <= s6_insn;
s7_max[0*9 +: 9] <= $signed(s6_max[0*9 +: 9]) > $signed(s6_max[1*9 +: 9]) ? s6_max[0*9 +: 9] : s6_max[1*9 +: 9];
s7_max[1*9 +: 9] <= $signed(s6_max[2*9 +: 9]) > $signed(s6_max[3*9 +: 9]) ? s6_max[2*9 +: 9] : s6_max[3*9 +: 9];
if (!reset && s6_en) begin
s7_en <= 1;
end
end
reg [31:0] acc0zn;
always @* begin
acc0zn = s7_insn[1] ? 0 : acc0;
acc0zn = s7_insn[2] ? 32'h 8000_0000 : acc0zn;
end
always @(posedge clock) begin
s8_en <= 0;
s8_insn <= s7_insn;
s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +
$signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);
s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +
$signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);
s8_max <= $signed(s7_max[0*9 +: 9]) > $signed(s7_max[1*9 +: 9]) ? s7_max[0*9 +: 9] : s7_max[1*9 +: 9];
s8_maxen <= ($signed(s7_max[0*9 +: 9]) > $signed(acc0zn)) || ($signed(s7_max[1*9 +: 9]) > $signed(acc0zn));
if (!reset && s7_en) begin
s8_en <= 1;
end
end
reg [31:0] new_acc0_add;
reg [31:0] new_acc1_add;
reg [31:0] new_acc0_max;
reg [31:0] new_acc0;
reg [31:0] new_acc1;
wire [31:0] acc0_shifted = $signed(acc0) >>> s8_insn[14:6];
wire [31:0] acc1_shifted = $signed(acc1) >>> s8_insn[14:6];
reg [7:0] acc0_saturated;
reg [7:0] acc1_saturated;
reg new_acc0_max_cmp;
reg new_acc0_max_cmp_q;
always @* begin
new_acc0_add = s8_insn[1] ? 0 : acc0;
new_acc1_add = s8_insn[1] || s8_insn[2] ? 0 : acc1;
new_acc0_max = s8_insn[2] ? 32'h 8000_0000 : new_acc0_add;
new_acc0_add = $signed(new_acc0_add) + $signed(s8_sum0);
new_acc1_add = $signed(new_acc1_add) + $signed(s8_sum1);
if (s8_max != 9'h 100)
new_acc0_max = s8_maxen ? s8_max : new_acc0_max;
new_acc0 = s8_insn[0] ? new_acc0_max : new_acc0_add;
new_acc1 = new_acc1_add;
end
always @(posedge clock) begin
s9_en <= 0;
s9_insn <= s8_insn;
if (!reset && s8_en) begin
s9_en <= 1;
if (s8_insn[5:3] == 3'b 101) begin
acc0 <= new_acc0;
acc1 <= new_acc1;
end
if (s8_insn[5:0] == 28 || s8_insn[5:0] == 29) begin
acc0 <= mem_rdata[31:0];
end
if (s8_insn[5:0] == 28 || s8_insn[5:0] == 30) begin
acc1 <= mem_rdata[63:32];
end
if (s8_insn[5:0] == 32 || s8_insn[5:0] == 33) begin
acc0 <= acc0 + mem_rdata[31:0];
end
if (s8_insn[5:0] == 32 || s8_insn[5:0] == 34) begin
acc1 <= acc1 + mem_rdata[63:32];
end
end
if (&acc0_shifted[31:7] == |acc0_shifted[31:7])
acc0_saturated <= acc0_shifted[7:0];
else
acc0_saturated <= acc0_shifted[31] ? -128 : 127;
if (&acc1_shifted[31:7] == |acc1_shifted[31:7])
acc1_saturated <= acc1_shifted[7:0];
else
acc1_saturated <= acc1_shifted[31] ? -128 : 127;
end
reg [ 7:0] pre_mem_wr_en;
reg [16:0] pre_mem_wr_addr;
reg [63:0] pre_mem_wr_wdata;
always @* begin
if (pre_mem_wr_addr[0]) begin
mem_wr_en = pre_mem_wr_en << 1;
mem_wr_addr = pre_mem_wr_addr >> 1;
mem_wr_wdata = pre_mem_wr_wdata << 8;
end else begin
mem_wr_en = pre_mem_wr_en;
mem_wr_addr = pre_mem_wr_addr >> 1;
mem_wr_wdata = pre_mem_wr_wdata;
end
end
wire [5:0] s9_insn_opcode = s9_insn[5:0];
always @(posedge clock) begin
pre_mem_wr_en <= 0;
pre_mem_wr_addr <= s9_insn[31:15] + SBP;
pre_mem_wr_wdata <= {
{8{!s9_insn[2] || !acc1_saturated[7]}} & acc1_saturated,
{8{!s9_insn[2] || !acc0_saturated[7]}} & acc0_saturated
};
if (s9_en) begin
if (s9_insn[5:3] == 3'b 010) begin
pre_mem_wr_en <= {!s9_insn[0], !s9_insn[1]};
end
if (s9_insn[5:2] == 4'b 0110) begin
pre_mem_wr_en <= {{4{!s9_insn[0]}}, {4{!s9_insn[1]}}};
pre_mem_wr_wdata <= {acc1, acc0};
end
if (s9_insn[5:0] == 12 || s9_insn[5:0] == 13) begin
SBP <= s9_insn[31:15] + (s9_insn[0] ? SBP : 0);
end
end
if (reset || !s9_en) begin
pre_mem_wr_en <= 0;
end
end
endmodule | 17 |
137,909 | data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v | 80,622,510 | marlann_compute.v | v | 564 | 133 | [] | [] | [] | null | line:150 column:26: Illegal character "'" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:167: Operator OR expects 11 bits on the LHS, but LHS\'s VARREF \'memlock_res\' generates 10 bits.\n : ... In instance marlann_compute\n {memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10\'b 0 : memlock_mask);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:167: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s CONST \'10\'h0\' generates 10 bits.\n : ... In instance marlann_compute\n {memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10\'b 0 : memlock_mask);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:167: Operator COND expects 11 bits on the Conditional False, but Conditional False\'s VARREF \'memlock_mask\' generates 10 bits.\n : ... In instance marlann_compute\n {memlock_res, memlock_expect} <= memlock_res | (s1_stall ? 10\'b 0 : memlock_mask);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:218: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance marlann_compute\n mem_rd0_addr <= \'bx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:227: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_rd0_addr <= s1_insn[31:15] >> 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:238: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_rd0_addr <= (s1_insn[31:15] + VBP) >> 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:297: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[0*9 +: 9] <= s4_coeff[0*8 +: 8] ? $signed(mem_rdata[0*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:297: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[0*9 +: 9] <= s4_coeff[0*8 +: 8] ? $signed(mem_rdata[0*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:298: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[1*9 +: 9] <= s4_coeff[1*8 +: 8] ? $signed(mem_rdata[1*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:298: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[1*9 +: 9] <= s4_coeff[1*8 +: 8] ? $signed(mem_rdata[1*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:299: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[2*9 +: 9] <= s4_coeff[2*8 +: 8] ? $signed(mem_rdata[2*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:299: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[2*9 +: 9] <= s4_coeff[2*8 +: 8] ? $signed(mem_rdata[2*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:300: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[3*9 +: 9] <= s4_coeff[3*8 +: 8] ? $signed(mem_rdata[3*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:300: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[3*9 +: 9] <= s4_coeff[3*8 +: 8] ? $signed(mem_rdata[3*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:301: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[4*9 +: 9] <= s4_coeff[4*8 +: 8] ? $signed(mem_rdata[4*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:301: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[4*9 +: 9] <= s4_coeff[4*8 +: 8] ? $signed(mem_rdata[4*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:302: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[5*9 +: 9] <= s4_coeff[5*8 +: 8] ? $signed(mem_rdata[5*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:302: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[5*9 +: 9] <= s4_coeff[5*8 +: 8] ? $signed(mem_rdata[5*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:303: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[6*9 +: 9] <= s4_coeff[6*8 +: 8] ? $signed(mem_rdata[6*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:303: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[6*9 +: 9] <= s4_coeff[6*8 +: 8] ? $signed(mem_rdata[6*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:304: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 8 bits.\n : ... In instance marlann_compute\n s5_max[7*9 +: 9] <= s4_coeff[7*8 +: 8] ? $signed(mem_rdata[7*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:304: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n : ... In instance marlann_compute\n s5_max[7*9 +: 9] <= s4_coeff[7*8 +: 8] ? $signed(mem_rdata[7*8 +: 8]) : 9\'h100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:307: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance marlann_compute\n mem_rd1_addr <= \'bx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:336: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_rd1_addr <= (s4_insn[31:15] + LBP) >> 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the LHS, but LHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:397: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum0 <= $signed(s7_prod[ 0 +: 16]) + $signed(s7_prod[ 16 +: 16]) + $signed(s7_prod[ 32 +: 16]) + $signed(s7_prod[ 48 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:398: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:398: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:398: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[ 64 +: 16]) + $signed(s7_prod[ 80 +: 16]) + $signed(s7_prod[ 96 +: 16]) + $signed(s7_prod[112 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the LHS, but LHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:400: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n s8_sum1 <= $signed(s7_prod[128 +: 16]) + $signed(s7_prod[144 +: 16]) + $signed(s7_prod[160 +: 16]) + $signed(s7_prod[176 +: 16]) +\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:401: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:401: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:401: Operator ADD expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n : ... In instance marlann_compute\n $signed(s7_prod[192 +: 16]) + $signed(s7_prod[208 +: 16]) + $signed(s7_prod[224 +: 16]) + $signed(s7_prod[240 +: 16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:404: Operator GTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 9 bits.\n : ... In instance marlann_compute\n s8_maxen <= ($signed(s7_max[0*9 +: 9]) > $signed(acc0zn)) || ($signed(s7_max[1*9 +: 9]) > $signed(acc0zn));\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:404: Operator GTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 9 bits.\n : ... In instance marlann_compute\n s8_maxen <= ($signed(s7_max[0*9 +: 9]) > $signed(acc0zn)) || ($signed(s7_max[1*9 +: 9]) > $signed(acc0zn));\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:437: Operator ADD expects 32 bits on the RHS, but RHS\'s SIGNED generates 20 bits.\n : ... In instance marlann_compute\n new_acc0_add = $signed(new_acc0_add) + $signed(s8_sum0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:438: Operator ADD expects 32 bits on the RHS, but RHS\'s SIGNED generates 20 bits.\n : ... In instance marlann_compute\n new_acc1_add = $signed(new_acc1_add) + $signed(s8_sum1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:441: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'s8_max\' generates 9 bits.\n : ... In instance marlann_compute\n new_acc0_max = s8_maxen ? s8_max : new_acc0_max;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:502: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_wr_addr = pre_mem_wr_addr >> 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:506: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance marlann_compute\n mem_wr_addr = pre_mem_wr_addr >> 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:516: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n : ... In instance marlann_compute\n pre_mem_wr_wdata <= {\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_large/marlann/marlann_compute.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance marlann_compute\n pre_mem_wr_en <= {!s9_insn[0], !s9_insn[1]};\n ^~\n%Error: Exiting due to 49 warning(s)\n' | 300,716 | module | module marlann_compute_mul2 (
input clock,
input [15:0] A, B,
output [31:0] X
);
reg [15:0] r1A, r2A, r3A;
reg [15:0] r1B, r2B, r3B;
always @(posedge clock) begin
r1A <= $signed(A[7:0]) * $signed(B[7:0]);
r1B <= $signed(A[15:8]) * $signed(B[15:8]);
r2A <= r1A;
r2B <= r1B;
r3A <= r2A;
r3B <= r2B;
end
assign X = {r3B, r3A};
endmodule | module marlann_compute_mul2 (
input clock,
input [15:0] A, B,
output [31:0] X
); |
reg [15:0] r1A, r2A, r3A;
reg [15:0] r1B, r2B, r3B;
always @(posedge clock) begin
r1A <= $signed(A[7:0]) * $signed(B[7:0]);
r1B <= $signed(A[15:8]) * $signed(B[15:8]);
r2A <= r1A;
r2B <= r1B;
r3A <= r2A;
r3B <= r2B;
end
assign X = {r3B, r3A};
endmodule | 17 |
137,912 | data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v | 80,622,510 | sddac_tb.v | v | 44 | 55 | [] | [] | [] | null | line:55: before: "=" | null | 1: b'%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:4: Cannot find include file: constants.vams\n`include "constants.vams" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac,data/full_repos/permissive/80622510/constants.vams\n data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac,data/full_repos/permissive/80622510/constants.vams.v\n data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac,data/full_repos/permissive/80622510/constants.vams.sv\n constants.vams\n constants.vams.v\n constants.vams.sv\n obj_dir/constants.vams\n obj_dir/constants.vams.v\n obj_dir/constants.vams.sv\n%Warning-STMTDLY: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("sddac_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #4 rst_n = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #526288 $finish; \n ^\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:39: Define or directive not defined: \'`M_TWO_PI\'\n sig <= $sin(`M_TWO_PI*phase)*10000.0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80622510/verilog/benchmarks_large/sddac/sddac_tb.v:39: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n sig <= $sin(`M_TWO_PI*phase)*10000.0;\n ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 300,727 | module | module tb;
reg clk = 0;
reg rst_n = 0;
reg signed [15:0] sig = 0;
wire dac_out;
real phase = 0.0;
integer fhandle;
always #1 clk=~clk;
sddac dut(clk, rst_n, sig, dac_out);
initial
begin
$dumpfile("sddac_tb.vcd");
$dumpvars;
fhandle = $fopen("sddac_out.txt","w");
#4 rst_n = 1'b1;
#526288 $finish;
end
always @(posedge clk)
begin
if (rst_n == 1'b1)
begin
$fwrite(fhandle, "%d\n", dac_out);
sig <= $sin(`M_TWO_PI*phase)*10000.0;
phase <= phase + 0.001;
end
end
endmodule | module tb; |
reg clk = 0;
reg rst_n = 0;
reg signed [15:0] sig = 0;
wire dac_out;
real phase = 0.0;
integer fhandle;
always #1 clk=~clk;
sddac dut(clk, rst_n, sig, dac_out);
initial
begin
$dumpfile("sddac_tb.vcd");
$dumpvars;
fhandle = $fopen("sddac_out.txt","w");
#4 rst_n = 1'b1;
#526288 $finish;
end
always @(posedge clk)
begin
if (rst_n == 1'b1)
begin
$fwrite(fhandle, "%d\n", dac_out);
sig <= $sin(`M_TWO_PI*phase)*10000.0;
phase <= phase + 0.001;
end
end
endmodule | 17 |
137,913 | data/full_repos/permissive/80622510/verilog/benchmarks_small/cic/cic5.v | 80,622,510 | cic5.v | v | 65 | 54 | [] | [] | [] | [(6, 65)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_small/cic/cic5.v:26: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n : ... In instance cic5\n int_s[i] <= 16\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80622510/verilog/benchmarks_small/cic/cic5.v:40: Operator ADD expects 28 bits on the RHS, but RHS\'s VARREF \'d_in\' generates 16 bits.\n : ... In instance cic5\n int_s[1] <= int_s[1] + d_in;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,729 | module | module cic5(
input clk,
input rst_n,
input signed [15:0] d_in,
output reg signed [27:0] d_out,
output reg d_out_valid
);
reg signed [27:0] int_s [1:5];
reg signed [27:0] comb_s [1:5];
reg signed [27:0] tmp [1:5];
reg [2:0] decimation_count;
integer i;
always @(posedge clk)
begin
if (rst_n == 1'b0)
begin
for (i=1; i<=5; i=i+1) begin
int_s[i] <= 16'd0;
comb_s[i] <= 28'd0;
end
decimation_count <= 0;
d_out_valid <= 0;
d_out <= 0;
end
else
begin
d_out_valid <= 1'b0;
decimation_count <= decimation_count + 1;
int_s[1] <= int_s[1] + d_in;
for (i=2; i<=5; i=i+1) begin
int_s[i] <= int_s[i] + int_s[i-1];
end
if (decimation_count == 3'd4)
begin
tmp[1] = int_s[5] - comb_s[1];
comb_s[1] <= int_s[5];
for (i=2; i<=5; i=i+1) begin
tmp[i] = tmp[i-1] - comb_s[i];
comb_s[i] <= tmp[i-1];
end
decimation_count <= 0;
d_out_valid <= 1'b1;
d_out <= tmp[5];
end;
end;
end
endmodule | module cic5(
input clk,
input rst_n,
input signed [15:0] d_in,
output reg signed [27:0] d_out,
output reg d_out_valid
); |
reg signed [27:0] int_s [1:5];
reg signed [27:0] comb_s [1:5];
reg signed [27:0] tmp [1:5];
reg [2:0] decimation_count;
integer i;
always @(posedge clk)
begin
if (rst_n == 1'b0)
begin
for (i=1; i<=5; i=i+1) begin
int_s[i] <= 16'd0;
comb_s[i] <= 28'd0;
end
decimation_count <= 0;
d_out_valid <= 0;
d_out <= 0;
end
else
begin
d_out_valid <= 1'b0;
decimation_count <= decimation_count + 1;
int_s[1] <= int_s[1] + d_in;
for (i=2; i<=5; i=i+1) begin
int_s[i] <= int_s[i] + int_s[i-1];
end
if (decimation_count == 3'd4)
begin
tmp[1] = int_s[5] - comb_s[1];
comb_s[1] <= int_s[5];
for (i=2; i<=5; i=i+1) begin
tmp[i] = tmp[i-1] - comb_s[i];
comb_s[i] <= tmp[i-1];
end
decimation_count <= 0;
d_out_valid <= 1'b1;
d_out <= tmp[5];
end;
end;
end
endmodule | 17 |
137,916 | data/full_repos/permissive/80622510/verilog/benchmarks_small/various/crc32.v | 80,622,510 | crc32.v | v | 283 | 76 | [] | [] | [] | [(8, 283)] | null | data/verilator_xmls/c088300c-ff59-4196-b220-2199b2657a33.xml | null | 300,732 | module | module crc32 (input [7:0] din, input clk, input rst_n, output [31:0] dout);
reg [31:0] crctbl [255:0];
reg [31:0] crc;
initial
begin
crctbl[0] <= 32'h00000000;
crctbl[1] <= 32'h77073096;
crctbl[2] <= 32'hEE0E612C;
crctbl[3] <= 32'h990951BA;
crctbl[4] <= 32'h076DC419;
crctbl[5] <= 32'h706AF48F;
crctbl[6] <= 32'hE963A535;
crctbl[7] <= 32'h9E6495A3;
crctbl[8] <= 32'h0EDB8832;
crctbl[9] <= 32'h79DCB8A4;
crctbl[10] <= 32'hE0D5E91E;
crctbl[11] <= 32'h97D2D988;
crctbl[12] <= 32'h09B64C2B;
crctbl[13] <= 32'h7EB17CBD;
crctbl[14] <= 32'hE7B82D07;
crctbl[15] <= 32'h90BF1D91;
crctbl[16] <= 32'h1DB71064;
crctbl[17] <= 32'h6AB020F2;
crctbl[18] <= 32'hF3B97148;
crctbl[19] <= 32'h84BE41DE;
crctbl[20] <= 32'h1ADAD47D;
crctbl[21] <= 32'h6DDDE4EB;
crctbl[22] <= 32'hF4D4B551;
crctbl[23] <= 32'h83D385C7;
crctbl[24] <= 32'h136C9856;
crctbl[25] <= 32'h646BA8C0;
crctbl[26] <= 32'hFD62F97A;
crctbl[27] <= 32'h8A65C9EC;
crctbl[28] <= 32'h14015C4F;
crctbl[29] <= 32'h63066CD9;
crctbl[30] <= 32'hFA0F3D63;
crctbl[31] <= 32'h8D080DF5;
crctbl[32] <= 32'h3B6E20C8;
crctbl[33] <= 32'h4C69105E;
crctbl[34] <= 32'hD56041E4;
crctbl[35] <= 32'hA2677172;
crctbl[36] <= 32'h3C03E4D1;
crctbl[37] <= 32'h4B04D447;
crctbl[38] <= 32'hD20D85FD;
crctbl[39] <= 32'hA50AB56B;
crctbl[40] <= 32'h35B5A8FA;
crctbl[41] <= 32'h42B2986C;
crctbl[42] <= 32'hDBBBC9D6;
crctbl[43] <= 32'hACBCF940;
crctbl[44] <= 32'h32D86CE3;
crctbl[45] <= 32'h45DF5C75;
crctbl[46] <= 32'hDCD60DCF;
crctbl[47] <= 32'hABD13D59;
crctbl[48] <= 32'h26D930AC;
crctbl[49] <= 32'h51DE003A;
crctbl[50] <= 32'hC8D75180;
crctbl[51] <= 32'hBFD06116;
crctbl[52] <= 32'h21B4F4B5;
crctbl[53] <= 32'h56B3C423;
crctbl[54] <= 32'hCFBA9599;
crctbl[55] <= 32'hB8BDA50F;
crctbl[56] <= 32'h2802B89E;
crctbl[57] <= 32'h5F058808;
crctbl[58] <= 32'hC60CD9B2;
crctbl[59] <= 32'hB10BE924;
crctbl[60] <= 32'h2F6F7C87;
crctbl[61] <= 32'h58684C11;
crctbl[62] <= 32'hC1611DAB;
crctbl[63] <= 32'hB6662D3D;
crctbl[64] <= 32'h76DC4190;
crctbl[65] <= 32'h01DB7106;
crctbl[66] <= 32'h98D220BC;
crctbl[67] <= 32'hEFD5102A;
crctbl[68] <= 32'h71B18589;
crctbl[69] <= 32'h06B6B51F;
crctbl[70] <= 32'h9FBFE4A5;
crctbl[71] <= 32'hE8B8D433;
crctbl[72] <= 32'h7807C9A2;
crctbl[73] <= 32'h0F00F934;
crctbl[74] <= 32'h9609A88E;
crctbl[75] <= 32'hE10E9818;
crctbl[76] <= 32'h7F6A0DBB;
crctbl[77] <= 32'h086D3D2D;
crctbl[78] <= 32'h91646C97;
crctbl[79] <= 32'hE6635C01;
crctbl[80] <= 32'h6B6B51F4;
crctbl[81] <= 32'h1C6C6162;
crctbl[82] <= 32'h856530D8;
crctbl[83] <= 32'hF262004E;
crctbl[84] <= 32'h6C0695ED;
crctbl[85] <= 32'h1B01A57B;
crctbl[86] <= 32'h8208F4C1;
crctbl[87] <= 32'hF50FC457;
crctbl[88] <= 32'h65B0D9C6;
crctbl[89] <= 32'h12B7E950;
crctbl[90] <= 32'h8BBEB8EA;
crctbl[91] <= 32'hFCB9887C;
crctbl[92] <= 32'h62DD1DDF;
crctbl[93] <= 32'h15DA2D49;
crctbl[94] <= 32'h8CD37CF3;
crctbl[95] <= 32'hFBD44C65;
crctbl[96] <= 32'h4DB26158;
crctbl[97] <= 32'h3AB551CE;
crctbl[98] <= 32'hA3BC0074;
crctbl[99] <= 32'hD4BB30E2;
crctbl[100] <= 32'h4ADFA541;
crctbl[101] <= 32'h3DD895D7;
crctbl[102] <= 32'hA4D1C46D;
crctbl[103] <= 32'hD3D6F4FB;
crctbl[104] <= 32'h4369E96A;
crctbl[105] <= 32'h346ED9FC;
crctbl[106] <= 32'hAD678846;
crctbl[107] <= 32'hDA60B8D0;
crctbl[108] <= 32'h44042D73;
crctbl[109] <= 32'h33031DE5;
crctbl[110] <= 32'hAA0A4C5F;
crctbl[111] <= 32'hDD0D7CC9;
crctbl[112] <= 32'h5005713C;
crctbl[113] <= 32'h270241AA;
crctbl[114] <= 32'hBE0B1010;
crctbl[115] <= 32'hC90C2086;
crctbl[116] <= 32'h5768B525;
crctbl[117] <= 32'h206F85B3;
crctbl[118] <= 32'hB966D409;
crctbl[119] <= 32'hCE61E49F;
crctbl[120] <= 32'h5EDEF90E;
crctbl[121] <= 32'h29D9C998;
crctbl[122] <= 32'hB0D09822;
crctbl[123] <= 32'hC7D7A8B4;
crctbl[124] <= 32'h59B33D17;
crctbl[125] <= 32'h2EB40D81;
crctbl[126] <= 32'hB7BD5C3B;
crctbl[127] <= 32'hC0BA6CAD;
crctbl[128] <= 32'hEDB88320;
crctbl[129] <= 32'h9ABFB3B6;
crctbl[130] <= 32'h03B6E20C;
crctbl[131] <= 32'h74B1D29A;
crctbl[132] <= 32'hEAD54739;
crctbl[133] <= 32'h9DD277AF;
crctbl[134] <= 32'h04DB2615;
crctbl[135] <= 32'h73DC1683;
crctbl[136] <= 32'hE3630B12;
crctbl[137] <= 32'h94643B84;
crctbl[138] <= 32'h0D6D6A3E;
crctbl[139] <= 32'h7A6A5AA8;
crctbl[140] <= 32'hE40ECF0B;
crctbl[141] <= 32'h9309FF9D;
crctbl[142] <= 32'h0A00AE27;
crctbl[143] <= 32'h7D079EB1;
crctbl[144] <= 32'hF00F9344;
crctbl[145] <= 32'h8708A3D2;
crctbl[146] <= 32'h1E01F268;
crctbl[147] <= 32'h6906C2FE;
crctbl[148] <= 32'hF762575D;
crctbl[149] <= 32'h806567CB;
crctbl[150] <= 32'h196C3671;
crctbl[151] <= 32'h6E6B06E7;
crctbl[152] <= 32'hFED41B76;
crctbl[153] <= 32'h89D32BE0;
crctbl[154] <= 32'h10DA7A5A;
crctbl[155] <= 32'h67DD4ACC;
crctbl[156] <= 32'hF9B9DF6F;
crctbl[157] <= 32'h8EBEEFF9;
crctbl[158] <= 32'h17B7BE43;
crctbl[159] <= 32'h60B08ED5;
crctbl[160] <= 32'hD6D6A3E8;
crctbl[161] <= 32'hA1D1937E;
crctbl[162] <= 32'h38D8C2C4;
crctbl[163] <= 32'h4FDFF252;
crctbl[164] <= 32'hD1BB67F1;
crctbl[165] <= 32'hA6BC5767;
crctbl[166] <= 32'h3FB506DD;
crctbl[167] <= 32'h48B2364B;
crctbl[168] <= 32'hD80D2BDA;
crctbl[169] <= 32'hAF0A1B4C;
crctbl[170] <= 32'h36034AF6;
crctbl[171] <= 32'h41047A60;
crctbl[172] <= 32'hDF60EFC3;
crctbl[173] <= 32'hA867DF55;
crctbl[174] <= 32'h316E8EEF;
crctbl[175] <= 32'h4669BE79;
crctbl[176] <= 32'hCB61B38C;
crctbl[177] <= 32'hBC66831A;
crctbl[178] <= 32'h256FD2A0;
crctbl[179] <= 32'h5268E236;
crctbl[180] <= 32'hCC0C7795;
crctbl[181] <= 32'hBB0B4703;
crctbl[182] <= 32'h220216B9;
crctbl[183] <= 32'h5505262F;
crctbl[184] <= 32'hC5BA3BBE;
crctbl[185] <= 32'hB2BD0B28;
crctbl[186] <= 32'h2BB45A92;
crctbl[187] <= 32'h5CB36A04;
crctbl[188] <= 32'hC2D7FFA7;
crctbl[189] <= 32'hB5D0CF31;
crctbl[190] <= 32'h2CD99E8B;
crctbl[191] <= 32'h5BDEAE1D;
crctbl[192] <= 32'h9B64C2B0;
crctbl[193] <= 32'hEC63F226;
crctbl[194] <= 32'h756AA39C;
crctbl[195] <= 32'h026D930A;
crctbl[196] <= 32'h9C0906A9;
crctbl[197] <= 32'hEB0E363F;
crctbl[198] <= 32'h72076785;
crctbl[199] <= 32'h05005713;
crctbl[200] <= 32'h95BF4A82;
crctbl[201] <= 32'hE2B87A14;
crctbl[202] <= 32'h7BB12BAE;
crctbl[203] <= 32'h0CB61B38;
crctbl[204] <= 32'h92D28E9B;
crctbl[205] <= 32'hE5D5BE0D;
crctbl[206] <= 32'h7CDCEFB7;
crctbl[207] <= 32'h0BDBDF21;
crctbl[208] <= 32'h86D3D2D4;
crctbl[209] <= 32'hF1D4E242;
crctbl[210] <= 32'h68DDB3F8;
crctbl[211] <= 32'h1FDA836E;
crctbl[212] <= 32'h81BE16CD;
crctbl[213] <= 32'hF6B9265B;
crctbl[214] <= 32'h6FB077E1;
crctbl[215] <= 32'h18B74777;
crctbl[216] <= 32'h88085AE6;
crctbl[217] <= 32'hFF0F6A70;
crctbl[218] <= 32'h66063BCA;
crctbl[219] <= 32'h11010B5C;
crctbl[220] <= 32'h8F659EFF;
crctbl[221] <= 32'hF862AE69;
crctbl[222] <= 32'h616BFFD3;
crctbl[223] <= 32'h166CCF45;
crctbl[224] <= 32'hA00AE278;
crctbl[225] <= 32'hD70DD2EE;
crctbl[226] <= 32'h4E048354;
crctbl[227] <= 32'h3903B3C2;
crctbl[228] <= 32'hA7672661;
crctbl[229] <= 32'hD06016F7;
crctbl[230] <= 32'h4969474D;
crctbl[231] <= 32'h3E6E77DB;
crctbl[232] <= 32'hAED16A4A;
crctbl[233] <= 32'hD9D65ADC;
crctbl[234] <= 32'h40DF0B66;
crctbl[235] <= 32'h37D83BF0;
crctbl[236] <= 32'hA9BCAE53;
crctbl[237] <= 32'hDEBB9EC5;
crctbl[238] <= 32'h47B2CF7F;
crctbl[239] <= 32'h30B5FFE9;
crctbl[240] <= 32'hBDBDF21C;
crctbl[241] <= 32'hCABAC28A;
crctbl[242] <= 32'h53B39330;
crctbl[243] <= 32'h24B4A3A6;
crctbl[244] <= 32'hBAD03605;
crctbl[245] <= 32'hCDD70693;
crctbl[246] <= 32'h54DE5729;
crctbl[247] <= 32'h23D967BF;
crctbl[248] <= 32'hB3667A2E;
crctbl[249] <= 32'hC4614AB8;
crctbl[250] <= 32'h5D681B02;
crctbl[251] <= 32'h2A6F2B94;
crctbl[252] <= 32'hB40BBE37;
crctbl[253] <= 32'hC30C8EA1;
crctbl[254] <= 32'h5A05DF1B;
crctbl[255] <= 32'h2D02EF8D;
end
always @(posedge clk)
begin
if (rst_n == 1'b0)
crc <= 32'hFFFFFFFF;
else
crc <= (crc >> 8) ^ crctbl[(crc[7:0] ^ din)];
end
assign dout = crc;
endmodule | module crc32 (input [7:0] din, input clk, input rst_n, output [31:0] dout); |
reg [31:0] crctbl [255:0];
reg [31:0] crc;
initial
begin
crctbl[0] <= 32'h00000000;
crctbl[1] <= 32'h77073096;
crctbl[2] <= 32'hEE0E612C;
crctbl[3] <= 32'h990951BA;
crctbl[4] <= 32'h076DC419;
crctbl[5] <= 32'h706AF48F;
crctbl[6] <= 32'hE963A535;
crctbl[7] <= 32'h9E6495A3;
crctbl[8] <= 32'h0EDB8832;
crctbl[9] <= 32'h79DCB8A4;
crctbl[10] <= 32'hE0D5E91E;
crctbl[11] <= 32'h97D2D988;
crctbl[12] <= 32'h09B64C2B;
crctbl[13] <= 32'h7EB17CBD;
crctbl[14] <= 32'hE7B82D07;
crctbl[15] <= 32'h90BF1D91;
crctbl[16] <= 32'h1DB71064;
crctbl[17] <= 32'h6AB020F2;
crctbl[18] <= 32'hF3B97148;
crctbl[19] <= 32'h84BE41DE;
crctbl[20] <= 32'h1ADAD47D;
crctbl[21] <= 32'h6DDDE4EB;
crctbl[22] <= 32'hF4D4B551;
crctbl[23] <= 32'h83D385C7;
crctbl[24] <= 32'h136C9856;
crctbl[25] <= 32'h646BA8C0;
crctbl[26] <= 32'hFD62F97A;
crctbl[27] <= 32'h8A65C9EC;
crctbl[28] <= 32'h14015C4F;
crctbl[29] <= 32'h63066CD9;
crctbl[30] <= 32'hFA0F3D63;
crctbl[31] <= 32'h8D080DF5;
crctbl[32] <= 32'h3B6E20C8;
crctbl[33] <= 32'h4C69105E;
crctbl[34] <= 32'hD56041E4;
crctbl[35] <= 32'hA2677172;
crctbl[36] <= 32'h3C03E4D1;
crctbl[37] <= 32'h4B04D447;
crctbl[38] <= 32'hD20D85FD;
crctbl[39] <= 32'hA50AB56B;
crctbl[40] <= 32'h35B5A8FA;
crctbl[41] <= 32'h42B2986C;
crctbl[42] <= 32'hDBBBC9D6;
crctbl[43] <= 32'hACBCF940;
crctbl[44] <= 32'h32D86CE3;
crctbl[45] <= 32'h45DF5C75;
crctbl[46] <= 32'hDCD60DCF;
crctbl[47] <= 32'hABD13D59;
crctbl[48] <= 32'h26D930AC;
crctbl[49] <= 32'h51DE003A;
crctbl[50] <= 32'hC8D75180;
crctbl[51] <= 32'hBFD06116;
crctbl[52] <= 32'h21B4F4B5;
crctbl[53] <= 32'h56B3C423;
crctbl[54] <= 32'hCFBA9599;
crctbl[55] <= 32'hB8BDA50F;
crctbl[56] <= 32'h2802B89E;
crctbl[57] <= 32'h5F058808;
crctbl[58] <= 32'hC60CD9B2;
crctbl[59] <= 32'hB10BE924;
crctbl[60] <= 32'h2F6F7C87;
crctbl[61] <= 32'h58684C11;
crctbl[62] <= 32'hC1611DAB;
crctbl[63] <= 32'hB6662D3D;
crctbl[64] <= 32'h76DC4190;
crctbl[65] <= 32'h01DB7106;
crctbl[66] <= 32'h98D220BC;
crctbl[67] <= 32'hEFD5102A;
crctbl[68] <= 32'h71B18589;
crctbl[69] <= 32'h06B6B51F;
crctbl[70] <= 32'h9FBFE4A5;
crctbl[71] <= 32'hE8B8D433;
crctbl[72] <= 32'h7807C9A2;
crctbl[73] <= 32'h0F00F934;
crctbl[74] <= 32'h9609A88E;
crctbl[75] <= 32'hE10E9818;
crctbl[76] <= 32'h7F6A0DBB;
crctbl[77] <= 32'h086D3D2D;
crctbl[78] <= 32'h91646C97;
crctbl[79] <= 32'hE6635C01;
crctbl[80] <= 32'h6B6B51F4;
crctbl[81] <= 32'h1C6C6162;
crctbl[82] <= 32'h856530D8;
crctbl[83] <= 32'hF262004E;
crctbl[84] <= 32'h6C0695ED;
crctbl[85] <= 32'h1B01A57B;
crctbl[86] <= 32'h8208F4C1;
crctbl[87] <= 32'hF50FC457;
crctbl[88] <= 32'h65B0D9C6;
crctbl[89] <= 32'h12B7E950;
crctbl[90] <= 32'h8BBEB8EA;
crctbl[91] <= 32'hFCB9887C;
crctbl[92] <= 32'h62DD1DDF;
crctbl[93] <= 32'h15DA2D49;
crctbl[94] <= 32'h8CD37CF3;
crctbl[95] <= 32'hFBD44C65;
crctbl[96] <= 32'h4DB26158;
crctbl[97] <= 32'h3AB551CE;
crctbl[98] <= 32'hA3BC0074;
crctbl[99] <= 32'hD4BB30E2;
crctbl[100] <= 32'h4ADFA541;
crctbl[101] <= 32'h3DD895D7;
crctbl[102] <= 32'hA4D1C46D;
crctbl[103] <= 32'hD3D6F4FB;
crctbl[104] <= 32'h4369E96A;
crctbl[105] <= 32'h346ED9FC;
crctbl[106] <= 32'hAD678846;
crctbl[107] <= 32'hDA60B8D0;
crctbl[108] <= 32'h44042D73;
crctbl[109] <= 32'h33031DE5;
crctbl[110] <= 32'hAA0A4C5F;
crctbl[111] <= 32'hDD0D7CC9;
crctbl[112] <= 32'h5005713C;
crctbl[113] <= 32'h270241AA;
crctbl[114] <= 32'hBE0B1010;
crctbl[115] <= 32'hC90C2086;
crctbl[116] <= 32'h5768B525;
crctbl[117] <= 32'h206F85B3;
crctbl[118] <= 32'hB966D409;
crctbl[119] <= 32'hCE61E49F;
crctbl[120] <= 32'h5EDEF90E;
crctbl[121] <= 32'h29D9C998;
crctbl[122] <= 32'hB0D09822;
crctbl[123] <= 32'hC7D7A8B4;
crctbl[124] <= 32'h59B33D17;
crctbl[125] <= 32'h2EB40D81;
crctbl[126] <= 32'hB7BD5C3B;
crctbl[127] <= 32'hC0BA6CAD;
crctbl[128] <= 32'hEDB88320;
crctbl[129] <= 32'h9ABFB3B6;
crctbl[130] <= 32'h03B6E20C;
crctbl[131] <= 32'h74B1D29A;
crctbl[132] <= 32'hEAD54739;
crctbl[133] <= 32'h9DD277AF;
crctbl[134] <= 32'h04DB2615;
crctbl[135] <= 32'h73DC1683;
crctbl[136] <= 32'hE3630B12;
crctbl[137] <= 32'h94643B84;
crctbl[138] <= 32'h0D6D6A3E;
crctbl[139] <= 32'h7A6A5AA8;
crctbl[140] <= 32'hE40ECF0B;
crctbl[141] <= 32'h9309FF9D;
crctbl[142] <= 32'h0A00AE27;
crctbl[143] <= 32'h7D079EB1;
crctbl[144] <= 32'hF00F9344;
crctbl[145] <= 32'h8708A3D2;
crctbl[146] <= 32'h1E01F268;
crctbl[147] <= 32'h6906C2FE;
crctbl[148] <= 32'hF762575D;
crctbl[149] <= 32'h806567CB;
crctbl[150] <= 32'h196C3671;
crctbl[151] <= 32'h6E6B06E7;
crctbl[152] <= 32'hFED41B76;
crctbl[153] <= 32'h89D32BE0;
crctbl[154] <= 32'h10DA7A5A;
crctbl[155] <= 32'h67DD4ACC;
crctbl[156] <= 32'hF9B9DF6F;
crctbl[157] <= 32'h8EBEEFF9;
crctbl[158] <= 32'h17B7BE43;
crctbl[159] <= 32'h60B08ED5;
crctbl[160] <= 32'hD6D6A3E8;
crctbl[161] <= 32'hA1D1937E;
crctbl[162] <= 32'h38D8C2C4;
crctbl[163] <= 32'h4FDFF252;
crctbl[164] <= 32'hD1BB67F1;
crctbl[165] <= 32'hA6BC5767;
crctbl[166] <= 32'h3FB506DD;
crctbl[167] <= 32'h48B2364B;
crctbl[168] <= 32'hD80D2BDA;
crctbl[169] <= 32'hAF0A1B4C;
crctbl[170] <= 32'h36034AF6;
crctbl[171] <= 32'h41047A60;
crctbl[172] <= 32'hDF60EFC3;
crctbl[173] <= 32'hA867DF55;
crctbl[174] <= 32'h316E8EEF;
crctbl[175] <= 32'h4669BE79;
crctbl[176] <= 32'hCB61B38C;
crctbl[177] <= 32'hBC66831A;
crctbl[178] <= 32'h256FD2A0;
crctbl[179] <= 32'h5268E236;
crctbl[180] <= 32'hCC0C7795;
crctbl[181] <= 32'hBB0B4703;
crctbl[182] <= 32'h220216B9;
crctbl[183] <= 32'h5505262F;
crctbl[184] <= 32'hC5BA3BBE;
crctbl[185] <= 32'hB2BD0B28;
crctbl[186] <= 32'h2BB45A92;
crctbl[187] <= 32'h5CB36A04;
crctbl[188] <= 32'hC2D7FFA7;
crctbl[189] <= 32'hB5D0CF31;
crctbl[190] <= 32'h2CD99E8B;
crctbl[191] <= 32'h5BDEAE1D;
crctbl[192] <= 32'h9B64C2B0;
crctbl[193] <= 32'hEC63F226;
crctbl[194] <= 32'h756AA39C;
crctbl[195] <= 32'h026D930A;
crctbl[196] <= 32'h9C0906A9;
crctbl[197] <= 32'hEB0E363F;
crctbl[198] <= 32'h72076785;
crctbl[199] <= 32'h05005713;
crctbl[200] <= 32'h95BF4A82;
crctbl[201] <= 32'hE2B87A14;
crctbl[202] <= 32'h7BB12BAE;
crctbl[203] <= 32'h0CB61B38;
crctbl[204] <= 32'h92D28E9B;
crctbl[205] <= 32'hE5D5BE0D;
crctbl[206] <= 32'h7CDCEFB7;
crctbl[207] <= 32'h0BDBDF21;
crctbl[208] <= 32'h86D3D2D4;
crctbl[209] <= 32'hF1D4E242;
crctbl[210] <= 32'h68DDB3F8;
crctbl[211] <= 32'h1FDA836E;
crctbl[212] <= 32'h81BE16CD;
crctbl[213] <= 32'hF6B9265B;
crctbl[214] <= 32'h6FB077E1;
crctbl[215] <= 32'h18B74777;
crctbl[216] <= 32'h88085AE6;
crctbl[217] <= 32'hFF0F6A70;
crctbl[218] <= 32'h66063BCA;
crctbl[219] <= 32'h11010B5C;
crctbl[220] <= 32'h8F659EFF;
crctbl[221] <= 32'hF862AE69;
crctbl[222] <= 32'h616BFFD3;
crctbl[223] <= 32'h166CCF45;
crctbl[224] <= 32'hA00AE278;
crctbl[225] <= 32'hD70DD2EE;
crctbl[226] <= 32'h4E048354;
crctbl[227] <= 32'h3903B3C2;
crctbl[228] <= 32'hA7672661;
crctbl[229] <= 32'hD06016F7;
crctbl[230] <= 32'h4969474D;
crctbl[231] <= 32'h3E6E77DB;
crctbl[232] <= 32'hAED16A4A;
crctbl[233] <= 32'hD9D65ADC;
crctbl[234] <= 32'h40DF0B66;
crctbl[235] <= 32'h37D83BF0;
crctbl[236] <= 32'hA9BCAE53;
crctbl[237] <= 32'hDEBB9EC5;
crctbl[238] <= 32'h47B2CF7F;
crctbl[239] <= 32'h30B5FFE9;
crctbl[240] <= 32'hBDBDF21C;
crctbl[241] <= 32'hCABAC28A;
crctbl[242] <= 32'h53B39330;
crctbl[243] <= 32'h24B4A3A6;
crctbl[244] <= 32'hBAD03605;
crctbl[245] <= 32'hCDD70693;
crctbl[246] <= 32'h54DE5729;
crctbl[247] <= 32'h23D967BF;
crctbl[248] <= 32'hB3667A2E;
crctbl[249] <= 32'hC4614AB8;
crctbl[250] <= 32'h5D681B02;
crctbl[251] <= 32'h2A6F2B94;
crctbl[252] <= 32'hB40BBE37;
crctbl[253] <= 32'hC30C8EA1;
crctbl[254] <= 32'h5A05DF1B;
crctbl[255] <= 32'h2D02EF8D;
end
always @(posedge clk)
begin
if (rst_n == 1'b0)
crc <= 32'hFFFFFFFF;
else
crc <= (crc >> 8) ^ crctbl[(crc[7:0] ^ din)];
end
assign dout = crc;
endmodule | 17 |
137,918 | data/full_repos/permissive/80622510/verilog/benchmarks_small/various/pwm256.v | 80,622,510 | pwm256.v | v | 33 | 47 | [] | [] | [] | [(6, 32)] | null | data/verilator_xmls/6663807d-beb5-4b6d-acf2-f5262a2aec1b.xml | null | 300,734 | module | module pwm256(
input clk,
input rst_n,
input [7:0] d_in,
output reg pwm_out
);
reg signed [7:0] counter;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
counter <= 8'd0;
pwm_out <= 1'b0;
end
else
begin
counter <= counter + 8'd1;
if (counter >= d_in)
pwm_out <= 1'b1;
else
pwm_out <= 1'b0;
end
end
endmodule | module pwm256(
input clk,
input rst_n,
input [7:0] d_in,
output reg pwm_out
); |
reg signed [7:0] counter;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
counter <= 8'd0;
pwm_out <= 1'b0;
end
else
begin
counter <= counter + 8'd1;
if (counter >= d_in)
pwm_out <= 1'b1;
else
pwm_out <= 1'b0;
end
end
endmodule | 17 |
137,920 | data/full_repos/permissive/80738432/testbench.sv | 80,738,432 | testbench.sv | sv | 82 | 38 | [] | [] | [] | null | line:5: before: "s" | null | 1: b'%Error: data/full_repos/permissive/80738432/testbench.sv:5: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n parameter period = 1s / freq;\n ^~\n%Warning-STMTDLY: data/full_repos/permissive/80738432/testbench.sv:32: Unsupported: Ignoring delay on this delayed statement.\n #hperiod;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80738432/testbench.sv:38: Unsupported: Ignoring delay on this delayed statement.\n #50ns;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80738432/testbench.sv:40: Unsupported: Ignoring delay on this delayed statement.\n #1us;\n ^\n%Error: data/full_repos/permissive/80738432/testbench.sv:78: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80738432/testbench.sv:79: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("dump.vcd");\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n' | 300,736 | module | module top();
parameter freq = 50_000_000;
parameter period = 1s / freq;
parameter hperiod = period / 2;
wire clk;
wire rst_n;
wire sonar_echo;
wire sonar_trig;
wire[7:0] uart_data_in;
wire[7:0] uart_data_out;
wire uart_oen;
wire uart_wen;
wire uart_rxrdy;
wire uart_txrdy;
wire servo_pwm;
reg clk_reg = 0;
reg rst_n_reg = 1;
assign clk = clk_reg;
assign rst_n = rst_n_reg;
always begin
#hperiod;
clk_reg = !clk_reg;
end
initial begin
#50ns;
rst_n_reg = 0;
#1us;
rst_n_reg = 1;
end
echo dut(
.clk(clk),
.rst_n(rst_n),
.echo(1'b0),
.trig(sonar_trig),
.data_in(uart_data_in),
.data_out(uart_data_out),
.oen(uart_oen),
.wen(uart_wen),
.rxrdy(uart_rxrdy),
.txrdy(uart_txrdy),
.servo_pwm(servo_pwm)
);
sonar_vip sonar_vip(
.clk(clk),
.rst_n(rst_n),
.echo(sonar_echo),
.trig(sonar_trig)
);
coreuart_vip uart_vip(
.clk(clk),
.rst_n(rst_n),
.data_in(uart_data_in),
.data_out(uart_data_out),
.oen(uart_oen),
.wen(uart_wen),
.rxrdy(uart_rxrdy),
.txrdy(uart_txrdy)
);
initial begin
$dumpvars;
$dumpfile ("dump.vcd");
end
endmodule | module top(); |
parameter freq = 50_000_000;
parameter period = 1s / freq;
parameter hperiod = period / 2;
wire clk;
wire rst_n;
wire sonar_echo;
wire sonar_trig;
wire[7:0] uart_data_in;
wire[7:0] uart_data_out;
wire uart_oen;
wire uart_wen;
wire uart_rxrdy;
wire uart_txrdy;
wire servo_pwm;
reg clk_reg = 0;
reg rst_n_reg = 1;
assign clk = clk_reg;
assign rst_n = rst_n_reg;
always begin
#hperiod;
clk_reg = !clk_reg;
end
initial begin
#50ns;
rst_n_reg = 0;
#1us;
rst_n_reg = 1;
end
echo dut(
.clk(clk),
.rst_n(rst_n),
.echo(1'b0),
.trig(sonar_trig),
.data_in(uart_data_in),
.data_out(uart_data_out),
.oen(uart_oen),
.wen(uart_wen),
.rxrdy(uart_rxrdy),
.txrdy(uart_txrdy),
.servo_pwm(servo_pwm)
);
sonar_vip sonar_vip(
.clk(clk),
.rst_n(rst_n),
.echo(sonar_echo),
.trig(sonar_trig)
);
coreuart_vip uart_vip(
.clk(clk),
.rst_n(rst_n),
.data_in(uart_data_in),
.data_out(uart_data_out),
.oen(uart_oen),
.wen(uart_wen),
.rxrdy(uart_rxrdy),
.txrdy(uart_txrdy)
);
initial begin
$dumpvars;
$dumpfile ("dump.vcd");
end
endmodule | 0 |
137,921 | data/full_repos/permissive/80738432/src/control_unit.v | 80,738,432 | control_unit.v | v | 213 | 120 | [] | [] | [] | null | line:9: before: "=" | data/verilator_xmls/44a14228-33dc-44a2-bb78-24a9ea202e12.xml | null | 300,737 | module | module control_unit (
input wire clk,
input wire rst_n,
input wire[7:0] cmd,
input wire rx_rdy,
input wire tx_rdy,
output reg cmd_oen = 1,
output reg data_wen = 1,
output reg[7:0] data = 0,
input wire[7:0] servo_angle,
output reg[7:0] start_angle,
output reg[7:0] end_angle,
input wire servo_cycle_done,
input wire sonar_ready,
input wire[7:0] sonar_distance,
output reg sonar_measure = 0
);
reg[7:0] distance = 0;
parameter AUTO_MODE = 1'b0;
parameter MANUAL_MODE = 1'b1;
reg mode = AUTO_MODE;
parameter IDLE = 4'h0;
parameter FETCH_CMD = 4'h1;
parameter FETCH_DATA_PRE = 4'h2;
parameter FETCH_DATA = 4'h3;
parameter WAIT_SERVO_DONE = 4'h4;
parameter START_MEASURE = 4'h5;
parameter MEASURE = 4'h6;
parameter WAIT_TX_RDY = 4'h7;
parameter SEND_DATA = 4'h8;
parameter SEND_DATA_POST = 4'h9;
reg[3:0] state = IDLE;
reg[3:0] next_state = IDLE;
reg send_data_type = 0;
parameter MANUAL_CMD = 4'h0;
parameter SET_ANGLE_CMD = 2'h0;
parameter SET_MODE_CMD = 2'h1;
parameter MEASURE_CMD = 2'h2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = IDLE;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = IDLE;
end else begin
case(state)
IDLE: begin
if (rx_rdy) begin
next_state = FETCH_CMD;
end else if (mode == AUTO_MODE) begin
next_state = WAIT_SERVO_DONE;
end
end
FETCH_CMD: begin
case (cmd[7:4])
MANUAL_CMD: begin
case (cmd[3:2])
SET_ANGLE_CMD: begin
next_state = FETCH_DATA_PRE;
end
SET_MODE_CMD: begin
next_state = IDLE;
end
MEASURE_CMD: begin
next_state = START_MEASURE;
end
endcase
end
default: begin
next_state = IDLE;
end
endcase
end
FETCH_DATA_PRE: begin
if (rx_rdy) begin
next_state = FETCH_DATA;
end
end
FETCH_DATA: begin
next_state = IDLE;
end
WAIT_SERVO_DONE: begin
if (servo_cycle_done) begin
next_state = START_MEASURE;
end
end
START_MEASURE: begin
next_state = MEASURE;
end
MEASURE: begin
if (sonar_ready) begin
next_state = WAIT_TX_RDY;
end
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
next_state = SEND_DATA;
end
end
SEND_DATA: begin
next_state = SEND_DATA_POST;
end
SEND_DATA_POST: begin
case(send_data_type)
0: next_state = WAIT_TX_RDY;
1: next_state = IDLE;
endcase
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
mode = AUTO_MODE;
cmd_oen = 1;
data_wen = 1;
data = 0;
sonar_measure = 0;
start_angle = 8'h00;
end_angle = 8'hFE;
end else begin
case(state)
IDLE: begin
cmd_oen = 1;
data_wen = 1;
sonar_measure = 0;
end
FETCH_CMD: begin
cmd_oen = 0;
case (cmd[7:4])
MANUAL_CMD: begin
case (cmd[3:2])
SET_MODE_CMD: begin
mode = cmd[0];
end
endcase
end
default: begin
if (cmd[3:0] < cmd[7:4]) begin
start_angle = {cmd[3:0], 4'h0};
end_angle = {cmd[7:4], 4'h0};
end else begin
start_angle = {cmd[7:4], 4'h0};
end_angle = {cmd[3:0], 4'h0};
end
end
endcase
end
FETCH_DATA_PRE: begin
cmd_oen = 1;
end
FETCH_DATA: begin
start_angle = cmd;
end_angle = cmd;
cmd_oen = 0;
end
WAIT_SERVO_DONE: begin
end
START_MEASURE: begin
sonar_measure = 1;
end
MEASURE: begin
sonar_measure = 0;
distance = sonar_distance;
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
case(send_data_type)
0: data = {distance[7:1], 1'b0};
1: data = {servo_angle[7:1], 1'b1};
endcase
end
end
SEND_DATA: begin
data_wen = 0;
end
SEND_DATA_POST: begin
data_wen = 1;
send_data_type = !send_data_type;
end
endcase
end
end
endmodule | module control_unit (
input wire clk,
input wire rst_n,
input wire[7:0] cmd,
input wire rx_rdy,
input wire tx_rdy,
output reg cmd_oen = 1,
output reg data_wen = 1,
output reg[7:0] data = 0,
input wire[7:0] servo_angle,
output reg[7:0] start_angle,
output reg[7:0] end_angle,
input wire servo_cycle_done,
input wire sonar_ready,
input wire[7:0] sonar_distance,
output reg sonar_measure = 0
); |
reg[7:0] distance = 0;
parameter AUTO_MODE = 1'b0;
parameter MANUAL_MODE = 1'b1;
reg mode = AUTO_MODE;
parameter IDLE = 4'h0;
parameter FETCH_CMD = 4'h1;
parameter FETCH_DATA_PRE = 4'h2;
parameter FETCH_DATA = 4'h3;
parameter WAIT_SERVO_DONE = 4'h4;
parameter START_MEASURE = 4'h5;
parameter MEASURE = 4'h6;
parameter WAIT_TX_RDY = 4'h7;
parameter SEND_DATA = 4'h8;
parameter SEND_DATA_POST = 4'h9;
reg[3:0] state = IDLE;
reg[3:0] next_state = IDLE;
reg send_data_type = 0;
parameter MANUAL_CMD = 4'h0;
parameter SET_ANGLE_CMD = 2'h0;
parameter SET_MODE_CMD = 2'h1;
parameter MEASURE_CMD = 2'h2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = IDLE;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = IDLE;
end else begin
case(state)
IDLE: begin
if (rx_rdy) begin
next_state = FETCH_CMD;
end else if (mode == AUTO_MODE) begin
next_state = WAIT_SERVO_DONE;
end
end
FETCH_CMD: begin
case (cmd[7:4])
MANUAL_CMD: begin
case (cmd[3:2])
SET_ANGLE_CMD: begin
next_state = FETCH_DATA_PRE;
end
SET_MODE_CMD: begin
next_state = IDLE;
end
MEASURE_CMD: begin
next_state = START_MEASURE;
end
endcase
end
default: begin
next_state = IDLE;
end
endcase
end
FETCH_DATA_PRE: begin
if (rx_rdy) begin
next_state = FETCH_DATA;
end
end
FETCH_DATA: begin
next_state = IDLE;
end
WAIT_SERVO_DONE: begin
if (servo_cycle_done) begin
next_state = START_MEASURE;
end
end
START_MEASURE: begin
next_state = MEASURE;
end
MEASURE: begin
if (sonar_ready) begin
next_state = WAIT_TX_RDY;
end
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
next_state = SEND_DATA;
end
end
SEND_DATA: begin
next_state = SEND_DATA_POST;
end
SEND_DATA_POST: begin
case(send_data_type)
0: next_state = WAIT_TX_RDY;
1: next_state = IDLE;
endcase
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
mode = AUTO_MODE;
cmd_oen = 1;
data_wen = 1;
data = 0;
sonar_measure = 0;
start_angle = 8'h00;
end_angle = 8'hFE;
end else begin
case(state)
IDLE: begin
cmd_oen = 1;
data_wen = 1;
sonar_measure = 0;
end
FETCH_CMD: begin
cmd_oen = 0;
case (cmd[7:4])
MANUAL_CMD: begin
case (cmd[3:2])
SET_MODE_CMD: begin
mode = cmd[0];
end
endcase
end
default: begin
if (cmd[3:0] < cmd[7:4]) begin
start_angle = {cmd[3:0], 4'h0};
end_angle = {cmd[7:4], 4'h0};
end else begin
start_angle = {cmd[7:4], 4'h0};
end_angle = {cmd[3:0], 4'h0};
end
end
endcase
end
FETCH_DATA_PRE: begin
cmd_oen = 1;
end
FETCH_DATA: begin
start_angle = cmd;
end_angle = cmd;
cmd_oen = 0;
end
WAIT_SERVO_DONE: begin
end
START_MEASURE: begin
sonar_measure = 1;
end
MEASURE: begin
sonar_measure = 0;
distance = sonar_distance;
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
case(send_data_type)
0: data = {distance[7:1], 1'b0};
1: data = {servo_angle[7:1], 1'b1};
endcase
end
end
SEND_DATA: begin
data_wen = 0;
end
SEND_DATA_POST: begin
data_wen = 1;
send_data_type = !send_data_type;
end
endcase
end
end
endmodule | 0 |
137,922 | data/full_repos/permissive/80738432/src/coreuart_vip.v | 80,738,432 | coreuart_vip.v | v | 36 | 68 | [] | [] | [] | null | line:5: before: "=" | null | 1: b"%Error: data/full_repos/permissive/80738432/src/coreuart_vip.v:15: syntax error, unexpected '@'\n @ (negedge wen);\n ^\n%Error: data/full_repos/permissive/80738432/src/coreuart_vip.v:18: syntax error, unexpected '@'\n repeat (11) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/80738432/src/coreuart_vip.v:24: Unsupported or unknown PLI call: $urandom\n int delay = $urandom() % 100 + 100;\n ^~~~~~~~\n%Error: data/full_repos/permissive/80738432/src/coreuart_vip.v:26: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n #(delay * 1ms);\n ^~~\n%Error: data/full_repos/permissive/80738432/src/coreuart_vip.v:31: syntax error, unexpected '@'\n while (oen) @(posedge clk);\n ^\n%Error: Exiting due to 5 error(s)\n" | 300,738 | module | module coreuart_vip (
input wire clk,
input wire rst_n,
output reg rxrdy = 0,
output reg txrdy = 1,
output reg[7:0] data_out = 8'hF3,
input wire oen,
input wire wen,
input wire[7:0] data_in
);
always begin
@ (negedge wen);
@ (posedge clk);
txrdy = 0;
repeat (11) @ (posedge clk);
txrdy = 1;
end
always begin
int delay = $urandom() % 100 + 100;
$display($sformatf("Chosen delay: %d clocks", delay));
#(delay * 1ms);
@(posedge clk);
rxrdy = 1;
data_out = 8'h8F;
$display($sformatf("Random data from UART: %h", data_out));
while (oen) @(posedge clk);
@(posedge clk);
rxrdy = 0;
end
endmodule | module coreuart_vip (
input wire clk,
input wire rst_n,
output reg rxrdy = 0,
output reg txrdy = 1,
output reg[7:0] data_out = 8'hF3,
input wire oen,
input wire wen,
input wire[7:0] data_in
); |
always begin
@ (negedge wen);
@ (posedge clk);
txrdy = 0;
repeat (11) @ (posedge clk);
txrdy = 1;
end
always begin
int delay = $urandom() % 100 + 100;
$display($sformatf("Chosen delay: %d clocks", delay));
#(delay * 1ms);
@(posedge clk);
rxrdy = 1;
data_out = 8'h8F;
$display($sformatf("Random data from UART: %h", data_out));
while (oen) @(posedge clk);
@(posedge clk);
rxrdy = 0;
end
endmodule | 0 |
137,923 | data/full_repos/permissive/80738432/src/echo.v | 80,738,432 | echo.v | v | 76 | 53 | [] | [] | [] | [(1, 75)] | null | null | 1: b"%Error: data/full_repos/permissive/80738432/src/echo.v:30: Cannot find file containing module: 'servo_driver'\n servo_driver #(.freq(freq)) servo(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80738432/src,data/full_repos/permissive/80738432/servo_driver\n data/full_repos/permissive/80738432/src,data/full_repos/permissive/80738432/servo_driver.v\n data/full_repos/permissive/80738432/src,data/full_repos/permissive/80738432/servo_driver.sv\n servo_driver\n servo_driver.v\n servo_driver.sv\n obj_dir/servo_driver\n obj_dir/servo_driver.v\n obj_dir/servo_driver.sv\n%Error: data/full_repos/permissive/80738432/src/echo.v:38: Cannot find file containing module: 'servo_fsm'\n servo_fsm #(.PWM_CYCLES_PER_ITER(1)) servo_ctrl(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80738432/src/echo.v:48: Cannot find file containing module: 'sonar_driver'\n sonar_driver #(.freq(freq)) sonar(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/80738432/src/echo.v:58: Cannot find file containing module: 'control_unit'\n control_unit cu(\n ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 300,739 | module | module echo #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire rxrdy,
input wire txrdy,
input wire[7:0] data_out,
output wire oen,
output wire wen,
output wire[7:0] data_in,
output wire servo_pwm,
input wire echo,
output wire trig
);
wire[7:0] servo_angle;
wire[7:0] servo_sangle;
wire[7:0] servo_eangle;
wire servo_cycle_done;
wire[7:0] sonar_distance;
wire sonar_measure;
wire sonar_ready;
servo_driver #(.freq(freq)) servo(
.clk(clk),
.rst_n(rst_n),
.servo_pwm(servo_pwm),
.angle(servo_angle),
.cycle_done(servo_cycle_done)
);
servo_fsm #(.PWM_CYCLES_PER_ITER(1)) servo_ctrl(
.clk(clk),
.rst_n(rst_n),
.servo_cycle_done(servo_cycle_done),
.servo_angle(servo_angle),
.move_en(sonar_ready),
.start_angle(servo_sangle),
.end_angle(servo_eangle)
);
sonar_driver #(.freq(freq)) sonar(
.clk(clk),
.rst_n(rst_n),
.echo(echo),
.trig(trig),
.measure(sonar_measure),
.ready(sonar_ready),
.distance(sonar_distance)
);
control_unit cu(
.clk(clk),
.rst_n(rst_n),
.cmd(data_out),
.cmd_oen(oen),
.data(data_in),
.data_wen(wen),
.rx_rdy(rxrdy),
.tx_rdy(txrdy),
.servo_cycle_done(servo_cycle_done),
.servo_angle(servo_angle),
.start_angle(servo_sangle),
.end_angle(servo_eangle),
.sonar_distance(sonar_distance),
.sonar_measure(sonar_measure),
.sonar_ready(sonar_ready)
);
endmodule | module echo #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire rxrdy,
input wire txrdy,
input wire[7:0] data_out,
output wire oen,
output wire wen,
output wire[7:0] data_in,
output wire servo_pwm,
input wire echo,
output wire trig
); |
wire[7:0] servo_angle;
wire[7:0] servo_sangle;
wire[7:0] servo_eangle;
wire servo_cycle_done;
wire[7:0] sonar_distance;
wire sonar_measure;
wire sonar_ready;
servo_driver #(.freq(freq)) servo(
.clk(clk),
.rst_n(rst_n),
.servo_pwm(servo_pwm),
.angle(servo_angle),
.cycle_done(servo_cycle_done)
);
servo_fsm #(.PWM_CYCLES_PER_ITER(1)) servo_ctrl(
.clk(clk),
.rst_n(rst_n),
.servo_cycle_done(servo_cycle_done),
.servo_angle(servo_angle),
.move_en(sonar_ready),
.start_angle(servo_sangle),
.end_angle(servo_eangle)
);
sonar_driver #(.freq(freq)) sonar(
.clk(clk),
.rst_n(rst_n),
.echo(echo),
.trig(trig),
.measure(sonar_measure),
.ready(sonar_ready),
.distance(sonar_distance)
);
control_unit cu(
.clk(clk),
.rst_n(rst_n),
.cmd(data_out),
.cmd_oen(oen),
.data(data_in),
.data_wen(wen),
.rx_rdy(rxrdy),
.tx_rdy(txrdy),
.servo_cycle_done(servo_cycle_done),
.servo_angle(servo_angle),
.start_angle(servo_sangle),
.end_angle(servo_eangle),
.sonar_distance(sonar_distance),
.sonar_measure(sonar_measure),
.sonar_ready(sonar_ready)
);
endmodule | 0 |
137,924 | data/full_repos/permissive/80738432/src/servo_driver.v | 80,738,432 | servo_driver.v | v | 94 | 82 | [] | [] | [] | null | line:6: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80738432/src/servo_driver.v:11: Operator DIV expects 32 or 26 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n : ... In instance servo_driver\n parameter CYCLES_PER_ANGLE = (CYCLES_1_MS * 2) / 8\'hFF;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 300,740 | module | module servo_driver #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire[7:0] angle,
output reg servo_pwm = 0,
output reg cycle_done = 0
);
parameter CYCLES_1_MS = freq / 1_000;
parameter CYCLES_PER_ANGLE = (CYCLES_1_MS * 2) / 8'hFF;
parameter CYCLES_21u33_MS = CYCLES_1_MS * 21 + CYCLES_1_MS / 3;
parameter CYCLES_22_MS = CYCLES_1_MS * 22;
reg[7:0] angle_reg = 0;
reg[31:0] counter = 0;
reg[31:0] pulse_width = 0;
reg[1:0] state = 0;
reg[1:0] next_state = 0;
parameter GET_ANGLE = 2'b00;
parameter GET_WIDTH = 2'b01;
parameter HIGH_PULSE = 2'b10;
parameter LOW_PULSE = 2'b11;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = GET_ANGLE;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = GET_ANGLE;
end else begin
case (state)
GET_ANGLE: begin
next_state = GET_WIDTH;
end
GET_WIDTH: begin
next_state = HIGH_PULSE;
end
HIGH_PULSE: begin
if (counter == pulse_width) begin
next_state = LOW_PULSE;
end
end
LOW_PULSE: begin
if (counter == 0) begin
next_state = GET_ANGLE;
end
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
servo_pwm = 0;
cycle_done = 0;
counter = 0;
angle_reg = 0;
pulse_width = 0;
end else begin
case (state)
GET_ANGLE: begin
angle_reg = angle;
cycle_done = 1;
counter = CYCLES_22_MS;
end
GET_WIDTH: begin
pulse_width = CYCLES_21u33_MS - angle_reg * CYCLES_PER_ANGLE;
servo_pwm = 1;
cycle_done = 0;
end
HIGH_PULSE: begin
counter = counter - 1;
servo_pwm = 1;
end
LOW_PULSE: begin
counter = counter - 1;
servo_pwm = 0;
end
endcase
end
end
endmodule | module servo_driver #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire[7:0] angle,
output reg servo_pwm = 0,
output reg cycle_done = 0
); |
parameter CYCLES_1_MS = freq / 1_000;
parameter CYCLES_PER_ANGLE = (CYCLES_1_MS * 2) / 8'hFF;
parameter CYCLES_21u33_MS = CYCLES_1_MS * 21 + CYCLES_1_MS / 3;
parameter CYCLES_22_MS = CYCLES_1_MS * 22;
reg[7:0] angle_reg = 0;
reg[31:0] counter = 0;
reg[31:0] pulse_width = 0;
reg[1:0] state = 0;
reg[1:0] next_state = 0;
parameter GET_ANGLE = 2'b00;
parameter GET_WIDTH = 2'b01;
parameter HIGH_PULSE = 2'b10;
parameter LOW_PULSE = 2'b11;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = GET_ANGLE;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = GET_ANGLE;
end else begin
case (state)
GET_ANGLE: begin
next_state = GET_WIDTH;
end
GET_WIDTH: begin
next_state = HIGH_PULSE;
end
HIGH_PULSE: begin
if (counter == pulse_width) begin
next_state = LOW_PULSE;
end
end
LOW_PULSE: begin
if (counter == 0) begin
next_state = GET_ANGLE;
end
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
servo_pwm = 0;
cycle_done = 0;
counter = 0;
angle_reg = 0;
pulse_width = 0;
end else begin
case (state)
GET_ANGLE: begin
angle_reg = angle;
cycle_done = 1;
counter = CYCLES_22_MS;
end
GET_WIDTH: begin
pulse_width = CYCLES_21u33_MS - angle_reg * CYCLES_PER_ANGLE;
servo_pwm = 1;
cycle_done = 0;
end
HIGH_PULSE: begin
counter = counter - 1;
servo_pwm = 1;
end
LOW_PULSE: begin
counter = counter - 1;
servo_pwm = 0;
end
endcase
end
end
endmodule | 0 |
137,925 | data/full_repos/permissive/80738432/src/servo_fsm.v | 80,738,432 | servo_fsm.v | v | 108 | 98 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/6eb2d958-2e4c-48b3-992e-cb2e96ffbe18.xml | null | 300,741 | module | module servo_fsm #(parameter PWM_CYCLES_PER_ITER = 1)(
input wire clk,
input wire rst_n,
input wire servo_cycle_done,
output reg[7:0] servo_angle = 8'h80,
input wire move_en,
input wire[7:0] start_angle,
input wire[7:0] end_angle
);
reg[1:0] state = 0;
reg[1:0] next_state = 0;
parameter WAIT_SERVO = 2'b00;
parameter DIVIDE = 2'b01;
parameter ANGLE_UPD = 2'b10;
parameter DIR_UPD = 2'b11;
reg[8:0] divider = PWM_CYCLES_PER_ITER - 1;
reg servo_dir = 0;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = WAIT_SERVO;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = WAIT_SERVO;
end else begin
case (state)
WAIT_SERVO: begin
if (servo_cycle_done) begin
next_state = DIVIDE;
end
end
DIVIDE: begin
if (divider == 0 && move_en == 1) begin
next_state = ANGLE_UPD;
end else begin
next_state = WAIT_SERVO;
end
end
ANGLE_UPD: begin
next_state = DIR_UPD;
end
DIR_UPD: begin
next_state = WAIT_SERVO;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
divider = PWM_CYCLES_PER_ITER;
servo_dir = 0;
servo_angle = 8'h80;
end else begin
case (state)
WAIT_SERVO: begin
end
DIVIDE: begin
if (divider == 0) begin
divider = PWM_CYCLES_PER_ITER - 1;
end else begin
divider = divider - 1;
end
end
ANGLE_UPD: begin
if (servo_dir) begin
servo_angle = servo_angle + 1;
end else begin
servo_angle = servo_angle - 1;
end
end
DIR_UPD: begin
if (servo_angle <= start_angle) begin
servo_dir = 1;
end else if (servo_angle >= end_angle) begin
servo_dir = 0;
end
end
endcase
end
end
endmodule | module servo_fsm #(parameter PWM_CYCLES_PER_ITER = 1)(
input wire clk,
input wire rst_n,
input wire servo_cycle_done,
output reg[7:0] servo_angle = 8'h80,
input wire move_en,
input wire[7:0] start_angle,
input wire[7:0] end_angle
); |
reg[1:0] state = 0;
reg[1:0] next_state = 0;
parameter WAIT_SERVO = 2'b00;
parameter DIVIDE = 2'b01;
parameter ANGLE_UPD = 2'b10;
parameter DIR_UPD = 2'b11;
reg[8:0] divider = PWM_CYCLES_PER_ITER - 1;
reg servo_dir = 0;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = WAIT_SERVO;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = WAIT_SERVO;
end else begin
case (state)
WAIT_SERVO: begin
if (servo_cycle_done) begin
next_state = DIVIDE;
end
end
DIVIDE: begin
if (divider == 0 && move_en == 1) begin
next_state = ANGLE_UPD;
end else begin
next_state = WAIT_SERVO;
end
end
ANGLE_UPD: begin
next_state = DIR_UPD;
end
DIR_UPD: begin
next_state = WAIT_SERVO;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
divider = PWM_CYCLES_PER_ITER;
servo_dir = 0;
servo_angle = 8'h80;
end else begin
case (state)
WAIT_SERVO: begin
end
DIVIDE: begin
if (divider == 0) begin
divider = PWM_CYCLES_PER_ITER - 1;
end else begin
divider = divider - 1;
end
end
ANGLE_UPD: begin
if (servo_dir) begin
servo_angle = servo_angle + 1;
end else begin
servo_angle = servo_angle - 1;
end
end
DIR_UPD: begin
if (servo_angle <= start_angle) begin
servo_dir = 1;
end else if (servo_angle >= end_angle) begin
servo_dir = 0;
end
end
endcase
end
end
endmodule | 0 |
137,926 | data/full_repos/permissive/80738432/src/sonar_driver.v | 80,738,432 | sonar_driver.v | v | 118 | 93 | [] | [] | [] | null | line:5: before: "=" | data/verilator_xmls/2df45ccb-208c-4ec6-b239-6c7217947043.xml | null | 300,742 | module | module sonar_driver #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire measure,
output reg ready = 1,
output wire[7:0] distance,
input wire echo,
output reg trig = 0
);
parameter CYCLES_10_US = freq / 100_000;
parameter CYCLE_PERIOD = 1_000_000_000 / freq;
parameter SOUND_SPEED = 343210;
parameter NM_PER_CYCLE = SOUND_SPEED * CYCLE_PERIOD / 1000;
parameter ECHO_TIMEOUT = freq / 100;
parameter TIMEOUT = freq;
reg[31:0] counter = 0;
reg[31:0] timeout = 0;
reg[31:0] i_dist = 0;
reg[2:0] state = 0;
reg[2:0] next_state = 0;
parameter IDLE = 3'h0;
parameter TRIG = 3'h1;
parameter WAIT_ECHO = 3'h2;
parameter MEASURING = 3'h3;
parameter READY = 3'h4;
assign distance = i_dist[31:24];
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = IDLE;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = IDLE;
end else begin
case (state)
IDLE: begin
if (measure == 1) begin
next_state = TRIG;
end
end
TRIG: begin
if (counter == 0) begin
next_state = WAIT_ECHO;
end
end
WAIT_ECHO: begin
if (echo == 1) begin
next_state = MEASURING;
end else if (timeout == 0) begin
next_state = READY;
end
end
MEASURING: begin
if (echo == 0) begin
next_state = READY;
end else if (timeout == 0) begin
next_state = READY;
end
end
READY: begin
next_state = IDLE;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
trig = 0;
i_dist = 0;
ready = 1;
counter = 0;
end else begin
case (state)
IDLE: begin
if (measure == 1) begin
ready = 0;
counter = CYCLES_10_US;
timeout = ECHO_TIMEOUT;
end
end
TRIG: begin
i_dist = 0;
trig = 1;
counter = counter - 1;
end
WAIT_ECHO: begin
timeout = timeout - 1;
trig = 0;
end
MEASURING: begin
timeout = timeout - 1;
i_dist = i_dist + NM_PER_CYCLE;
end
READY: begin
ready = 1;
end
endcase
end
end
endmodule | module sonar_driver #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire measure,
output reg ready = 1,
output wire[7:0] distance,
input wire echo,
output reg trig = 0
); |
parameter CYCLES_10_US = freq / 100_000;
parameter CYCLE_PERIOD = 1_000_000_000 / freq;
parameter SOUND_SPEED = 343210;
parameter NM_PER_CYCLE = SOUND_SPEED * CYCLE_PERIOD / 1000;
parameter ECHO_TIMEOUT = freq / 100;
parameter TIMEOUT = freq;
reg[31:0] counter = 0;
reg[31:0] timeout = 0;
reg[31:0] i_dist = 0;
reg[2:0] state = 0;
reg[2:0] next_state = 0;
parameter IDLE = 3'h0;
parameter TRIG = 3'h1;
parameter WAIT_ECHO = 3'h2;
parameter MEASURING = 3'h3;
parameter READY = 3'h4;
assign distance = i_dist[31:24];
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = IDLE;
end else begin
state = next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = IDLE;
end else begin
case (state)
IDLE: begin
if (measure == 1) begin
next_state = TRIG;
end
end
TRIG: begin
if (counter == 0) begin
next_state = WAIT_ECHO;
end
end
WAIT_ECHO: begin
if (echo == 1) begin
next_state = MEASURING;
end else if (timeout == 0) begin
next_state = READY;
end
end
MEASURING: begin
if (echo == 0) begin
next_state = READY;
end else if (timeout == 0) begin
next_state = READY;
end
end
READY: begin
next_state = IDLE;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
trig = 0;
i_dist = 0;
ready = 1;
counter = 0;
end else begin
case (state)
IDLE: begin
if (measure == 1) begin
ready = 0;
counter = CYCLES_10_US;
timeout = ECHO_TIMEOUT;
end
end
TRIG: begin
i_dist = 0;
trig = 1;
counter = counter - 1;
end
WAIT_ECHO: begin
timeout = timeout - 1;
trig = 0;
end
MEASURING: begin
timeout = timeout - 1;
i_dist = i_dist + NM_PER_CYCLE;
end
READY: begin
ready = 1;
end
endcase
end
end
endmodule | 0 |
137,927 | data/full_repos/permissive/80738432/src/sonar_vip.v | 80,738,432 | sonar_vip.v | v | 57 | 93 | [] | [] | [] | null | line:1: before: "int" | null | 1: b'%Error: data/full_repos/permissive/80738432/src/sonar_vip.v:41: Unsupported or unknown PLI call: $urandom\n counter = ($urandom() % 1500 + 10) * 2 * 1_000_000 / NM_PER_CYCLE;\n ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,743 | module | module sonar_vip #(int freq = 50_000_000) (
input wire clk,
input wire rst_n,
output reg echo = 0,
input wire trig
);
parameter CYCLE_PERIOD = 1_000_000_000 / freq;
parameter SOUND_SPEED = 343210;
parameter NM_PER_CYCLE = SOUND_SPEED * CYCLE_PERIOD / 1000;
reg[31:0] counter = 0;
reg[1:0] state = 0;
parameter IDLE = 2'b00;
parameter TRIG = 2'b01;
parameter RANDOMIZE = 2'b10;
parameter SEND_ECHO = 2'b11;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
state = IDLE;
echo = 0;
counter = 0;
end else begin
case (state)
IDLE: begin
if (trig == 1) begin
state = TRIG;
end
end
TRIG: begin
if (trig == 0) begin
state = RANDOMIZE;
end
end
RANDOMIZE: begin
counter = ($urandom() % 1500 + 10) * 2 * 1_000_000 / NM_PER_CYCLE;
$display($sformatf("Distance length: %d clocks", counter));
echo = 1;
state = SEND_ECHO;
end
SEND_ECHO: begin
counter--;
if (counter == 0) begin
echo = 0;
state = IDLE;
end
end
endcase
end
end
endmodule | module sonar_vip #(int freq = 50_000_000) (
input wire clk,
input wire rst_n,
output reg echo = 0,
input wire trig
); |
parameter CYCLE_PERIOD = 1_000_000_000 / freq;
parameter SOUND_SPEED = 343210;
parameter NM_PER_CYCLE = SOUND_SPEED * CYCLE_PERIOD / 1000;
reg[31:0] counter = 0;
reg[1:0] state = 0;
parameter IDLE = 2'b00;
parameter TRIG = 2'b01;
parameter RANDOMIZE = 2'b10;
parameter SEND_ECHO = 2'b11;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
state = IDLE;
echo = 0;
counter = 0;
end else begin
case (state)
IDLE: begin
if (trig == 1) begin
state = TRIG;
end
end
TRIG: begin
if (trig == 0) begin
state = RANDOMIZE;
end
end
RANDOMIZE: begin
counter = ($urandom() % 1500 + 10) * 2 * 1_000_000 / NM_PER_CYCLE;
$display($sformatf("Distance length: %d clocks", counter));
echo = 1;
state = SEND_ECHO;
end
SEND_ECHO: begin
counter--;
if (counter == 0) begin
echo = 0;
state = IDLE;
end
end
endcase
end
end
endmodule | 0 |
137,930 | data/full_repos/permissive/80873024/example/rtl/CSRs.v | 80,873,024 | CSRs.v | v | 243 | 73 | [] | [] | [] | [(1, 241)] | null | data/verilator_xmls/7432e4e3-40a3-4638-a0c7-c7f720dd8666.xml | null | 300,750 | module | module CSRs(
input [11:0] cadr_i,
output cvalid_o,
output [63:0] cdat_o,
input [63:0] cdat_i,
input coe_i,
input cwe_i,
input mie_0,
input mie_mpie,
input mpie_mie,
input mpie_1,
output [63:0] mtvec_o,
output [63:0] mepc_o,
output [3:0] cause_o,
input [63:0] ia_i,
input [63:0] pc_i,
output mie_o,
output mpie_o,
input ft0_i,
input tick_i,
input mcause_2,
input mcause_3,
input mcause_11,
input mcause_irq_i,
input mepc_ia,
input mepc_pc,
input irq_i,
output take_irq_o,
input reset_i,
input clk_i
);
reg mpie, mie;
reg [63:0] mtvec;
reg [63:0] mscratch;
reg [63:0] mepc;
reg [4:0] mcause;
reg [63:0] mbadaddr;
reg [63:0] mcycle;
reg [63:0] mtime;
reg [63:0] minstret;
reg irqEn;
wire mpie_mux, mie_mux;
wire [63:0] mtvec_mux;
wire [63:0] mscratch_mux;
wire [63:0] mepc_mux;
wire [4:0] mcause_mux;
wire [63:0] mbadaddr_mux;
wire [63:0] mcycle_mux;
wire [63:0] mtime_mux;
assign mtvec_o = mtvec;
assign mepc_o = mepc;
wire csrv_misa = (cadr_i == 12'hF10);
wire csrv_mvendorid = (cadr_i == 12'hF11);
wire csrv_marchid = (cadr_i == 12'hF12);
wire csrv_mimpid = (cadr_i == 12'hF13);
wire csrv_mhartid = (cadr_i == 12'hF14);
wire csrv_mstatus = (cadr_i == 12'h300);
wire csrv_medeleg = (cadr_i == 12'h302);
wire csrv_mideleg = (cadr_i == 12'h303);
wire csrv_mie = (cadr_i == 12'h304);
wire csrv_mtvec = (cadr_i == 12'h305);
wire csrv_mscratch = (cadr_i == 12'h340);
wire csrv_mepc = (cadr_i == 12'h341);
wire csrv_mcause = (cadr_i == 12'h342);
wire csrv_mbadaddr = (cadr_i == 12'h343);
wire csrv_mip = (cadr_i == 12'h344);
wire csrv_mcycle = (cadr_i == 12'hF00);
wire csrv_mtime = (cadr_i == 12'hF01);
wire csrv_minstret = (cadr_i == 12'hF02);
assign cvalid_o = |{
csrv_misa, csrv_mvendorid, csrv_marchid,
csrv_mimpid, csrv_mhartid, csrv_mstatus,
csrv_medeleg, csrv_mideleg, csrv_mie,
csrv_mtvec, csrv_mscratch, csrv_mepc,
csrv_mcause, csrv_mbadaddr, csrv_mip,
csrv_mcycle, csrv_mtime, csrv_minstret
};
wire [63:0] csrd_misa = {2'b10, 36'd0, 26'b00000001000000000100000000};
wire [63:0] csrd_mvendorid = 64'd0;
wire [63:0] csrd_marchid = 64'd0;
wire [63:0] csrd_mimpid = 64'h1161008010000000;
wire [63:0] csrd_mhartid = 64'd0;
wire [63:0] csrd_mstatus = {
1'b0,
34'd0,
5'b00000,
4'b0000,
3'b000,
2'b00,
2'b00,
2'b11,
2'b10,
1'b1,
mpie, 3'b000,
mie, 3'b000
};
wire [63:0] csrd_medeleg = 64'd0;
wire [63:0] csrd_mideleg = 64'd0;
wire [63:0] csrd_mie = {
52'd0,
irqEn,
11'd0
};
wire [63:0] csrd_mtvec = mtvec;
wire [63:0] csrd_mscratch = mscratch;
wire [63:0] csrd_mepc = mepc;
wire [63:0] csrd_mcause = {
mcause[4],
59'd0,
mcause[3:0]
};
wire [63:0] csrd_mbadaddr = mbadaddr;
wire [63:0] csrd_mip = {
52'd0,
irq_i,
11'd0
};
wire [63:0] csrd_mcycle = mcycle;
wire [63:0] csrd_mtime = mtime;
wire [63:0] csrd_minstret = minstret;
assign take_irq_o = mie & irqEn & irq_i;
assign cdat_o =
(csrv_misa ? csrd_misa : 0) |
(csrv_mvendorid ? csrd_mvendorid : 0) |
(csrv_marchid ? csrd_marchid : 0) |
(csrv_mimpid ? csrd_mimpid : 0) |
(csrv_mhartid ? csrd_mhartid : 0) |
(csrv_mstatus ? csrd_mstatus : 0) |
(csrv_medeleg ? csrd_medeleg : 0) |
(csrv_mideleg ? csrd_mideleg : 0) |
(csrv_mie ? csrd_mie : 0) |
(csrv_mtvec ? csrd_mtvec : 0) |
(csrv_mscratch ? csrd_mscratch : 0) |
(csrv_mepc ? csrd_mepc : 0) |
(csrv_mcause ? csrd_mcause : 0) |
(csrv_mbadaddr ? csrd_mbadaddr : 0) |
(csrv_mip ? csrd_mip : 0) |
(csrv_mcycle ? csrd_mcycle : 0) |
(csrv_mtime ? csrd_mtime : 0) |
(csrv_minstret ? csrd_minstret : 0);
wire irqEn_cdat = csrv_mie & cwe_i;
wire irqEn_irqEn = ~|{irqEn_cdat, reset_i};
wire irqEn_mux =
(irqEn_cdat ? cdat_i[11] : 0) |
(irqEn_irqEn ? irqEn : 0);
wire mstatus_we = csrv_mstatus & cwe_i;
wire mie_mie = ~|{mie_0, mie_mpie, mstatus_we};
assign mie_mux =
(mie_0 ? 0 : 0) |
(mie_mpie ? mpie : 0) |
(mstatus_we ? cdat_i[3] : 0) |
(mie_mie ? mie : 0);
wire mpie_mpie = ~|{mpie_mie, mpie_1, mstatus_we};
assign mpie_mux =
(mpie_mie ? mie : 0) |
(mpie_1 ? 1 : 0) |
(mstatus_we ? cdat_i[7] : 0) |
(mpie_mpie ? mpie : 0);
assign mie_o = mie;
assign mpie_o = mpie;
wire mtvec_we = csrv_mtvec & cwe_i;
wire mtvec_mtvec = ~|{mtvec_we, reset_i};
assign mtvec_mux =
(mtvec_we ? cdat_i : 0) |
(reset_i ? 64'hFFFF_FFFF_FFFF_FE00 : 0) |
(mtvec_mtvec ? mtvec : 0);
wire mscratch_we = csrv_mscratch & cwe_i;
assign mscratch_mux = (mscratch_we ? cdat_i : mscratch);
wire mepc_we = csrv_mepc & cwe_i;
wire mepc_mepc = ~|{mepc_we, mepc_ia, mepc_pc};
assign mepc_mux =
(mepc_we ? cdat_i : 0) |
(mepc_ia ? ia_i : 0) |
(mepc_pc ? pc_i : 0) |
(mepc_mepc ? mepc : 0);
wire mcause_we = csrv_mcause & cwe_i;
wire mcause_mcause = ~|{mcause_2, mcause_3, mcause_11, mcause_we};
assign cause_o = mcause_mux[3:0];
assign mcause_mux =
(mcause_we ? {cdat_i[63], cdat_i[3:0]} : 0) |
(mcause_2 ? {mcause_irq_i, 4'd2} : 0) |
(mcause_3 ? {mcause_irq_i, 4'd3} : 0) |
(mcause_11 ? {mcause_irq_i, 4'd11} : 0) |
(mcause_mcause ? mcause : 0);
wire mbadaddr_we = csrv_mbadaddr & cwe_i;
assign mbadaddr_mux = (mbadaddr_we ? cdat_i : mbadaddr);
assign mcycle_mux = (~reset_i ? mcycle + 1 : 0);
assign mtime_mux =
(~reset_i & tick_i ? mtime + 64'd1 : 0) |
(~reset_i & ~tick_i ? mtime : 0);
always @(posedge clk_i) begin
minstret <= minstret;
if (reset_i) begin
minstret <= 64'd0;
end
else begin
if (ft0_i) begin
minstret <= minstret + 1;
end
end
end
always @(posedge clk_i) begin
mie <= mie_mux;
mpie <= mpie_mux;
mtvec <= mtvec_mux;
mscratch <= mscratch_mux;
mepc <= mepc_mux;
mcause <= mcause_mux;
mbadaddr <= mbadaddr_mux;
mcycle <= mcycle_mux;
mtime <= mtime_mux;
irqEn <= irqEn_mux;
end
endmodule | module CSRs(
input [11:0] cadr_i,
output cvalid_o,
output [63:0] cdat_o,
input [63:0] cdat_i,
input coe_i,
input cwe_i,
input mie_0,
input mie_mpie,
input mpie_mie,
input mpie_1,
output [63:0] mtvec_o,
output [63:0] mepc_o,
output [3:0] cause_o,
input [63:0] ia_i,
input [63:0] pc_i,
output mie_o,
output mpie_o,
input ft0_i,
input tick_i,
input mcause_2,
input mcause_3,
input mcause_11,
input mcause_irq_i,
input mepc_ia,
input mepc_pc,
input irq_i,
output take_irq_o,
input reset_i,
input clk_i
); |
reg mpie, mie;
reg [63:0] mtvec;
reg [63:0] mscratch;
reg [63:0] mepc;
reg [4:0] mcause;
reg [63:0] mbadaddr;
reg [63:0] mcycle;
reg [63:0] mtime;
reg [63:0] minstret;
reg irqEn;
wire mpie_mux, mie_mux;
wire [63:0] mtvec_mux;
wire [63:0] mscratch_mux;
wire [63:0] mepc_mux;
wire [4:0] mcause_mux;
wire [63:0] mbadaddr_mux;
wire [63:0] mcycle_mux;
wire [63:0] mtime_mux;
assign mtvec_o = mtvec;
assign mepc_o = mepc;
wire csrv_misa = (cadr_i == 12'hF10);
wire csrv_mvendorid = (cadr_i == 12'hF11);
wire csrv_marchid = (cadr_i == 12'hF12);
wire csrv_mimpid = (cadr_i == 12'hF13);
wire csrv_mhartid = (cadr_i == 12'hF14);
wire csrv_mstatus = (cadr_i == 12'h300);
wire csrv_medeleg = (cadr_i == 12'h302);
wire csrv_mideleg = (cadr_i == 12'h303);
wire csrv_mie = (cadr_i == 12'h304);
wire csrv_mtvec = (cadr_i == 12'h305);
wire csrv_mscratch = (cadr_i == 12'h340);
wire csrv_mepc = (cadr_i == 12'h341);
wire csrv_mcause = (cadr_i == 12'h342);
wire csrv_mbadaddr = (cadr_i == 12'h343);
wire csrv_mip = (cadr_i == 12'h344);
wire csrv_mcycle = (cadr_i == 12'hF00);
wire csrv_mtime = (cadr_i == 12'hF01);
wire csrv_minstret = (cadr_i == 12'hF02);
assign cvalid_o = |{
csrv_misa, csrv_mvendorid, csrv_marchid,
csrv_mimpid, csrv_mhartid, csrv_mstatus,
csrv_medeleg, csrv_mideleg, csrv_mie,
csrv_mtvec, csrv_mscratch, csrv_mepc,
csrv_mcause, csrv_mbadaddr, csrv_mip,
csrv_mcycle, csrv_mtime, csrv_minstret
};
wire [63:0] csrd_misa = {2'b10, 36'd0, 26'b00000001000000000100000000};
wire [63:0] csrd_mvendorid = 64'd0;
wire [63:0] csrd_marchid = 64'd0;
wire [63:0] csrd_mimpid = 64'h1161008010000000;
wire [63:0] csrd_mhartid = 64'd0;
wire [63:0] csrd_mstatus = {
1'b0,
34'd0,
5'b00000,
4'b0000,
3'b000,
2'b00,
2'b00,
2'b11,
2'b10,
1'b1,
mpie, 3'b000,
mie, 3'b000
};
wire [63:0] csrd_medeleg = 64'd0;
wire [63:0] csrd_mideleg = 64'd0;
wire [63:0] csrd_mie = {
52'd0,
irqEn,
11'd0
};
wire [63:0] csrd_mtvec = mtvec;
wire [63:0] csrd_mscratch = mscratch;
wire [63:0] csrd_mepc = mepc;
wire [63:0] csrd_mcause = {
mcause[4],
59'd0,
mcause[3:0]
};
wire [63:0] csrd_mbadaddr = mbadaddr;
wire [63:0] csrd_mip = {
52'd0,
irq_i,
11'd0
};
wire [63:0] csrd_mcycle = mcycle;
wire [63:0] csrd_mtime = mtime;
wire [63:0] csrd_minstret = minstret;
assign take_irq_o = mie & irqEn & irq_i;
assign cdat_o =
(csrv_misa ? csrd_misa : 0) |
(csrv_mvendorid ? csrd_mvendorid : 0) |
(csrv_marchid ? csrd_marchid : 0) |
(csrv_mimpid ? csrd_mimpid : 0) |
(csrv_mhartid ? csrd_mhartid : 0) |
(csrv_mstatus ? csrd_mstatus : 0) |
(csrv_medeleg ? csrd_medeleg : 0) |
(csrv_mideleg ? csrd_mideleg : 0) |
(csrv_mie ? csrd_mie : 0) |
(csrv_mtvec ? csrd_mtvec : 0) |
(csrv_mscratch ? csrd_mscratch : 0) |
(csrv_mepc ? csrd_mepc : 0) |
(csrv_mcause ? csrd_mcause : 0) |
(csrv_mbadaddr ? csrd_mbadaddr : 0) |
(csrv_mip ? csrd_mip : 0) |
(csrv_mcycle ? csrd_mcycle : 0) |
(csrv_mtime ? csrd_mtime : 0) |
(csrv_minstret ? csrd_minstret : 0);
wire irqEn_cdat = csrv_mie & cwe_i;
wire irqEn_irqEn = ~|{irqEn_cdat, reset_i};
wire irqEn_mux =
(irqEn_cdat ? cdat_i[11] : 0) |
(irqEn_irqEn ? irqEn : 0);
wire mstatus_we = csrv_mstatus & cwe_i;
wire mie_mie = ~|{mie_0, mie_mpie, mstatus_we};
assign mie_mux =
(mie_0 ? 0 : 0) |
(mie_mpie ? mpie : 0) |
(mstatus_we ? cdat_i[3] : 0) |
(mie_mie ? mie : 0);
wire mpie_mpie = ~|{mpie_mie, mpie_1, mstatus_we};
assign mpie_mux =
(mpie_mie ? mie : 0) |
(mpie_1 ? 1 : 0) |
(mstatus_we ? cdat_i[7] : 0) |
(mpie_mpie ? mpie : 0);
assign mie_o = mie;
assign mpie_o = mpie;
wire mtvec_we = csrv_mtvec & cwe_i;
wire mtvec_mtvec = ~|{mtvec_we, reset_i};
assign mtvec_mux =
(mtvec_we ? cdat_i : 0) |
(reset_i ? 64'hFFFF_FFFF_FFFF_FE00 : 0) |
(mtvec_mtvec ? mtvec : 0);
wire mscratch_we = csrv_mscratch & cwe_i;
assign mscratch_mux = (mscratch_we ? cdat_i : mscratch);
wire mepc_we = csrv_mepc & cwe_i;
wire mepc_mepc = ~|{mepc_we, mepc_ia, mepc_pc};
assign mepc_mux =
(mepc_we ? cdat_i : 0) |
(mepc_ia ? ia_i : 0) |
(mepc_pc ? pc_i : 0) |
(mepc_mepc ? mepc : 0);
wire mcause_we = csrv_mcause & cwe_i;
wire mcause_mcause = ~|{mcause_2, mcause_3, mcause_11, mcause_we};
assign cause_o = mcause_mux[3:0];
assign mcause_mux =
(mcause_we ? {cdat_i[63], cdat_i[3:0]} : 0) |
(mcause_2 ? {mcause_irq_i, 4'd2} : 0) |
(mcause_3 ? {mcause_irq_i, 4'd3} : 0) |
(mcause_11 ? {mcause_irq_i, 4'd11} : 0) |
(mcause_mcause ? mcause : 0);
wire mbadaddr_we = csrv_mbadaddr & cwe_i;
assign mbadaddr_mux = (mbadaddr_we ? cdat_i : mbadaddr);
assign mcycle_mux = (~reset_i ? mcycle + 1 : 0);
assign mtime_mux =
(~reset_i & tick_i ? mtime + 64'd1 : 0) |
(~reset_i & ~tick_i ? mtime : 0);
always @(posedge clk_i) begin
minstret <= minstret;
if (reset_i) begin
minstret <= 64'd0;
end
else begin
if (ft0_i) begin
minstret <= minstret + 1;
end
end
end
always @(posedge clk_i) begin
mie <= mie_mux;
mpie <= mpie_mux;
mtvec <= mtvec_mux;
mscratch <= mscratch_mux;
mepc <= mepc_mux;
mcause <= mcause_mux;
mbadaddr <= mbadaddr_mux;
mcycle <= mcycle_mux;
mtime <= mtime_mux;
irqEn <= irqEn_mux;
end
endmodule | 4 |
137,931 | data/full_repos/permissive/80873024/example/rtl/PolarisCPU.v | 80,873,024 | PolarisCPU.v | v | 358 | 113 | [] | [] | [] | [(5, 356)] | null | null | 1: b"%Error: data/full_repos/permissive/80873024/example/rtl/PolarisCPU.v:212: Cannot find file containing module: 'Sequencer'\n Sequencer s(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80873024/example/rtl,data/full_repos/permissive/80873024/Sequencer\n data/full_repos/permissive/80873024/example/rtl,data/full_repos/permissive/80873024/Sequencer.v\n data/full_repos/permissive/80873024/example/rtl,data/full_repos/permissive/80873024/Sequencer.sv\n Sequencer\n Sequencer.v\n Sequencer.sv\n obj_dir/Sequencer\n obj_dir/Sequencer.v\n obj_dir/Sequencer.sv\n%Error: data/full_repos/permissive/80873024/example/rtl/PolarisCPU.v:297: Cannot find file containing module: 'xrs'\n xrs xrs(\n ^~~\n%Error: data/full_repos/permissive/80873024/example/rtl/PolarisCPU.v:305: Cannot find file containing module: 'alu'\n alu alu(\n ^~~\n%Error: data/full_repos/permissive/80873024/example/rtl/PolarisCPU.v:323: Cannot find file containing module: 'CSRs'\n CSRs csrs(\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 300,752 | module | module PolarisCPU(
output fence_o,
output trap_o,
output [3:0] cause_o,
output [63:0] mepc_o,
output mpie_o,
output mie_o,
input irq_i,
input iack_i,
input [31:0] idat_i,
output [63:0] iadr_o,
output istb_o,
input dack_i,
input [63:0] ddat_i,
output [63:0] ddat_o,
output [63:0] dadr_o,
output dwe_o,
output dcyc_o,
output dstb_o,
output [1:0] dsiz_o,
output dsigned_o,
output [11:0] cadr_o,
output coe_o,
output cwe_o,
input cvalid_i,
output [63:0] cdat_o,
input [63:0] cdat_i,
input clk_i,
input reset_i
);
wire pc_mbvec, pc_pcPlus4;
wire ft0_o;
wire iadr_pc;
wire ir_idat;
reg ft0;
reg rst;
reg [63:0] pc, ia;
wire [63:0] pc_mux, ia_mux;
reg [31:0] ir;
wire [31:0] ir_mux;
reg xt0, xt1, xt2, xt3, xt4;
wire xt0_o, xt1_o, xt2_o, xt3_o, xt4_o;
wire [4:0] ra_mux;
wire ra_ir1, ra_ir2, ra_ird;
wire rdat_alu, rdat_pc;
wire [63:0] rdat_i, rdat_o;
wire rwe_o;
reg [63:0] alua, alub;
wire [63:0] alua_mux, alub_mux;
wire alua_rdat, alua_0, alua_ia;
wire alub_rdat, alub_imm12i, alub_imm12s, alub_imm20u, alub_imm20uj;
wire [63:0] imm12i, imm12s, imm12sb;
wire pc_alu;
wire cflag_i;
wire sum_en;
wire and_en;
wire xor_en;
wire invB_en;
wire lsh_en;
wire rsh_en;
wire ltu_en, lts_en;
wire [63:0] aluResult, aluXResult;
wire cflag_o;
wire vflag_o;
wire zflag_o;
wire [3:0] rmask_i;
wire sx32_en;
wire alua_alua;
wire alub_alub;
wire [63:0] imm20u, imm20uj;
wire ia_pc;
wire dadr_alu;
wire dcyc_1;
wire dstb_1;
wire dsiz_fn3;
wire rdat_ddat;
wire ddat_rdat;
wire [7:0] ccr_mux;
reg [7:0] ccr;
wire ccr_alu;
wire alub_imm12sb;
reg trap;
wire mcause_2, mcause_3, mcause_11;
wire pc_mtvec;
reg [63:0] mepc;
wire [63:0] mepc_mux;
wire mepc_ia;
wire pc_mepc;
wire mie, mpie;
wire mie_0, mie_mpie;
wire mpie_mie, mpie_1;
wire rdat_cdat, cdat_rdat;
wire coe_1, cwe_1;
wire cdat_imm5;
wire cdat_alu;
wire alub_imm5;
wire alua_cdat;
wire icvalid_i;
wire [63:0] icdat_i;
wire [63:0] mtvec_i;
wire take_irq;
wire mepc_pc;
wire mcause_irq_o;
wire cvalid = icvalid_i | cvalid_i;
wire [63:0] ucdat_i = icdat_i | cdat_i;
wire rdNotZero = |ir[11:7];
wire r1NotZero = |ir[19:15];
wire [63:0] imm5 = {59'b0, ir[19:15]};
assign coe_o = coe_1 & rdNotZero;
assign cwe_o = cwe_1 & r1NotZero;
assign cadr_o = ir[31:20];
assign cdat_o = (cdat_rdat ? rdat_o : 0) |
(cdat_alu ? aluXResult : 0) |
(cdat_imm5 ? imm5 : 0);
wire ltFlag = aluXResult[63] ^ vflag_o;
assign ccr_mux = ccr_alu ? {cflag_o, ~cflag_o, ~ltFlag, ltFlag, 2'b00, ~zflag_o, zflag_o} : ccr;
assign dsigned_o = dsiz_fn3 & ~ir[14];
assign dsiz_o = dsiz_fn3 ? ir[13:12] : 2'b00;
assign dcyc_o = dcyc_1;
assign dstb_o = dstb_1;
assign dadr_o = (dadr_alu ? aluXResult : 64'd0);
assign ddat_o = (ddat_rdat ? rdat_o : 0);
assign aluXResult = (sx32_en ? {{32{aluResult[31]}}, aluResult[31:0]} : aluResult);
assign imm12i = {{52{ir[31]}}, ir[31:20]};
assign imm12s = {{52{ir[31]}}, ir[31:25], ir[11:7]};
assign imm12sb = {{51{ir[31]}}, ir[31], ir[7], ir[30:25], ir[11:8], 1'b0};
assign imm20u = {{32{ir[31]}}, ir[31:12], 12'd0};
assign imm20uj = {{43{ir[31]}}, ir[31], ir[19:12], ir[20], ir[30:21], 1'b0};
assign alua_alua = ~|{alua_rdat, alua_0, alua_ia, alua_cdat};
assign alub_alub = ~|{alub_rdat, alub_imm12i, alub_imm12s, alub_imm12sb, alub_imm20u, alub_imm20uj, alub_imm5};
assign alua_mux =
(alua_ia ? ia : 0) |
(alua_rdat ? rdat_o : 0) |
(alua_cdat ? ucdat_i : 0) |
(alua_alua ? alua : 0);
assign alub_mux =
(alub_rdat ? rdat_o : 0) |
(alub_imm12i ? imm12i : 0) |
(alub_imm12s ? imm12s : 0) |
(alub_imm12sb ? imm12sb : 0) |
(alub_imm20u ? imm20u : 0) |
(alub_imm20uj ? imm20uj : 0) |
(alub_imm5 ? imm5 : 0) |
(alub_alub ? alub : 0);
assign rdat_i = (rdat_alu ? aluXResult : 0) |
(rdat_ddat ? ddat_i : 0) |
(rdat_cdat ? ucdat_i : 0) |
(rdat_pc ? pc : 0);
assign ra_mux = (ra_ir1 ? ir[19:15] : 0) |
(ra_ir2 ? ir[24:20] : 0) |
(ra_ird ? ir[11:7] : 0);
wire pc_pc = ~|{pc_mbvec,pc_pcPlus4,pc_alu,pc_mtvec,pc_mepc};
assign pc_mux = (pc_mbvec ? 64'hFFFF_FFFF_FFFF_FF00 : 64'h0) |
(pc_pcPlus4 ? pc + 4 : 64'h0) |
(pc_alu ? aluXResult : 64'h0) |
(pc_mtvec ? mtvec_i : 64'h0) |
(pc_mepc ? mepc_o : 64'h0) |
(pc_pc ? pc : 64'h0);
wire ia_ia = ~ia_pc;
assign ia_mux = (ia_pc ? pc : 0) |
(ia_ia ? ia : 0);
assign iadr_o = iadr_pc ? pc : 0;
wire ir_ir = ~ir_idat;
assign ir_mux = (ir_idat ? idat_i : 0) |
(ir_ir ? ir : 0);
always @(posedge clk_i) begin
rst <= reset_i;
pc <= pc_mux;
ia <= ia_mux;
ft0 <= ft0_o;
xt0 <= xt0_o;
xt1 <= xt1_o;
xt2 <= xt2_o;
xt3 <= xt3_o;
xt4 <= xt4_o;
ir <= ir_mux;
alua <= alua_mux;
alub <= alub_mux;
ccr <= ccr_mux;
trap <= trap_o;
end
Sequencer s(
.xt0_o(xt0_o),
.xt1_o(xt1_o),
.xt2_o(xt2_o),
.xt3_o(xt3_o),
.xt0(xt0),
.xt1(xt1),
.xt2(xt2),
.xt3(xt3),
.ft0(ft0),
.istb_o(istb_o),
.iadr_pc(iadr_pc),
.iack_i(iack_i),
.pc_mbvec(pc_mbvec),
.pc_pcPlus4(pc_pcPlus4),
.ir_idat(ir_idat),
.ir(ir),
.ft0_o(ft0_o),
.rdat_pc(rdat_pc),
.sum_en(sum_en),
.pc_alu(pc_alu),
.ra_ir1(ra_ir1),
.ra_ir2(ra_ir2),
.ra_ird(ra_ird),
.alua_rdat(alua_rdat),
.alub_rdat(alub_rdat),
.alub_imm12i(alub_imm12i),
.rwe_o(rwe_o),
.rdat_alu(rdat_alu),
.and_en(and_en),
.xor_en(xor_en),
.invB_en(invB_en),
.lsh_en(lsh_en),
.rsh_en(rsh_en),
.cflag_i(cflag_i),
.sx32_en(sx32_en),
.alua_0(alua_0),
.alub_imm20u(alub_imm20u),
.ia_pc(ia_pc),
.alua_ia(alua_ia),
.dadr_alu(dadr_alu),
.dcyc_1(dcyc_1),
.dstb_1(dstb_1),
.dsiz_fn3(dsiz_fn3),
.rdat_ddat(rdat_ddat),
.dack_i(dack_i),
.ddat_rdat(ddat_rdat),
.alub_imm12s(alub_imm12s),
.dwe_o(dwe_o),
.alub_imm20uj(alub_imm20uj),
.ccr_alu(ccr_alu),
.alub_imm12sb(alub_imm12sb),
.xt4_o(xt4_o),
.xt4(xt4),
.ccr(ccr),
.fence_o(fence_o),
.trap_o(trap_o),
.trap(trap),
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.pc_mtvec(pc_mtvec),
.mepc_ia(mepc_ia),
.pc_mepc(pc_mepc),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mie_mpie(mie_mpie),
.mie_0(mie_0),
.csrok_i(cvalid),
.rdat_cdat(rdat_cdat),
.coe_o(coe_1),
.cdat_rdat(cdat_rdat),
.cwe_o(cwe_1),
.cdat_imm5(cdat_imm5),
.cdat_alu(cdat_alu),
.alub_imm5(alub_imm5),
.alua_cdat(alua_cdat),
.take_irq(take_irq),
.mepc_pc(mepc_pc),
.mcause_irq_o(mcause_irq_o),
.ltu_en(ltu_en),
.lts_en(lts_en),
.rst(rst)
);
xrs xrs(
.clk_i(clk_i),
.ra_i(ra_mux),
.rdat_i(rdat_i),
.rdat_o(rdat_o),
.rmask_i({4{rwe_o}})
);
alu alu(
.inA_i(alua),
.inB_i(alub),
.cflag_i(cflag_i),
.sum_en_i(sum_en),
.and_en_i(and_en),
.xor_en_i(xor_en),
.invB_en_i(invB_en),
.lsh_en_i(lsh_en),
.rsh_en_i(rsh_en),
.ltu_en_i(ltu_en),
.lts_en_i(lts_en),
.out_o(aluResult),
.cflag_o(cflag_o),
.vflag_o(vflag_o),
.zflag_o(zflag_o)
);
CSRs csrs(
.cadr_i(cadr_o),
.cvalid_o(icvalid_i),
.cdat_o(icdat_i),
.cdat_i(cdat_o),
.coe_i(coe_o),
.cwe_i(cwe_o),
.mie_0(mie_0),
.mie_mpie(mie_mpie),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mtvec_o(mtvec_i),
.mepc_o(mepc_o),
.mie_o(mie_o),
.mpie_o(mpie_o),
.ft0_i(ft0),
.tick_i(1'b0),
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.mepc_ia(mepc_ia),
.mepc_pc(mepc_pc),
.ia_i(ia),
.pc_i(pc),
.cause_o(cause_o),
.irq_i(irq_i),
.take_irq_o(take_irq),
.mcause_irq_i(mcause_irq_o),
.reset_i(reset_i),
.clk_i(clk_i)
);
endmodule | module PolarisCPU(
output fence_o,
output trap_o,
output [3:0] cause_o,
output [63:0] mepc_o,
output mpie_o,
output mie_o,
input irq_i,
input iack_i,
input [31:0] idat_i,
output [63:0] iadr_o,
output istb_o,
input dack_i,
input [63:0] ddat_i,
output [63:0] ddat_o,
output [63:0] dadr_o,
output dwe_o,
output dcyc_o,
output dstb_o,
output [1:0] dsiz_o,
output dsigned_o,
output [11:0] cadr_o,
output coe_o,
output cwe_o,
input cvalid_i,
output [63:0] cdat_o,
input [63:0] cdat_i,
input clk_i,
input reset_i
); |
wire pc_mbvec, pc_pcPlus4;
wire ft0_o;
wire iadr_pc;
wire ir_idat;
reg ft0;
reg rst;
reg [63:0] pc, ia;
wire [63:0] pc_mux, ia_mux;
reg [31:0] ir;
wire [31:0] ir_mux;
reg xt0, xt1, xt2, xt3, xt4;
wire xt0_o, xt1_o, xt2_o, xt3_o, xt4_o;
wire [4:0] ra_mux;
wire ra_ir1, ra_ir2, ra_ird;
wire rdat_alu, rdat_pc;
wire [63:0] rdat_i, rdat_o;
wire rwe_o;
reg [63:0] alua, alub;
wire [63:0] alua_mux, alub_mux;
wire alua_rdat, alua_0, alua_ia;
wire alub_rdat, alub_imm12i, alub_imm12s, alub_imm20u, alub_imm20uj;
wire [63:0] imm12i, imm12s, imm12sb;
wire pc_alu;
wire cflag_i;
wire sum_en;
wire and_en;
wire xor_en;
wire invB_en;
wire lsh_en;
wire rsh_en;
wire ltu_en, lts_en;
wire [63:0] aluResult, aluXResult;
wire cflag_o;
wire vflag_o;
wire zflag_o;
wire [3:0] rmask_i;
wire sx32_en;
wire alua_alua;
wire alub_alub;
wire [63:0] imm20u, imm20uj;
wire ia_pc;
wire dadr_alu;
wire dcyc_1;
wire dstb_1;
wire dsiz_fn3;
wire rdat_ddat;
wire ddat_rdat;
wire [7:0] ccr_mux;
reg [7:0] ccr;
wire ccr_alu;
wire alub_imm12sb;
reg trap;
wire mcause_2, mcause_3, mcause_11;
wire pc_mtvec;
reg [63:0] mepc;
wire [63:0] mepc_mux;
wire mepc_ia;
wire pc_mepc;
wire mie, mpie;
wire mie_0, mie_mpie;
wire mpie_mie, mpie_1;
wire rdat_cdat, cdat_rdat;
wire coe_1, cwe_1;
wire cdat_imm5;
wire cdat_alu;
wire alub_imm5;
wire alua_cdat;
wire icvalid_i;
wire [63:0] icdat_i;
wire [63:0] mtvec_i;
wire take_irq;
wire mepc_pc;
wire mcause_irq_o;
wire cvalid = icvalid_i | cvalid_i;
wire [63:0] ucdat_i = icdat_i | cdat_i;
wire rdNotZero = |ir[11:7];
wire r1NotZero = |ir[19:15];
wire [63:0] imm5 = {59'b0, ir[19:15]};
assign coe_o = coe_1 & rdNotZero;
assign cwe_o = cwe_1 & r1NotZero;
assign cadr_o = ir[31:20];
assign cdat_o = (cdat_rdat ? rdat_o : 0) |
(cdat_alu ? aluXResult : 0) |
(cdat_imm5 ? imm5 : 0);
wire ltFlag = aluXResult[63] ^ vflag_o;
assign ccr_mux = ccr_alu ? {cflag_o, ~cflag_o, ~ltFlag, ltFlag, 2'b00, ~zflag_o, zflag_o} : ccr;
assign dsigned_o = dsiz_fn3 & ~ir[14];
assign dsiz_o = dsiz_fn3 ? ir[13:12] : 2'b00;
assign dcyc_o = dcyc_1;
assign dstb_o = dstb_1;
assign dadr_o = (dadr_alu ? aluXResult : 64'd0);
assign ddat_o = (ddat_rdat ? rdat_o : 0);
assign aluXResult = (sx32_en ? {{32{aluResult[31]}}, aluResult[31:0]} : aluResult);
assign imm12i = {{52{ir[31]}}, ir[31:20]};
assign imm12s = {{52{ir[31]}}, ir[31:25], ir[11:7]};
assign imm12sb = {{51{ir[31]}}, ir[31], ir[7], ir[30:25], ir[11:8], 1'b0};
assign imm20u = {{32{ir[31]}}, ir[31:12], 12'd0};
assign imm20uj = {{43{ir[31]}}, ir[31], ir[19:12], ir[20], ir[30:21], 1'b0};
assign alua_alua = ~|{alua_rdat, alua_0, alua_ia, alua_cdat};
assign alub_alub = ~|{alub_rdat, alub_imm12i, alub_imm12s, alub_imm12sb, alub_imm20u, alub_imm20uj, alub_imm5};
assign alua_mux =
(alua_ia ? ia : 0) |
(alua_rdat ? rdat_o : 0) |
(alua_cdat ? ucdat_i : 0) |
(alua_alua ? alua : 0);
assign alub_mux =
(alub_rdat ? rdat_o : 0) |
(alub_imm12i ? imm12i : 0) |
(alub_imm12s ? imm12s : 0) |
(alub_imm12sb ? imm12sb : 0) |
(alub_imm20u ? imm20u : 0) |
(alub_imm20uj ? imm20uj : 0) |
(alub_imm5 ? imm5 : 0) |
(alub_alub ? alub : 0);
assign rdat_i = (rdat_alu ? aluXResult : 0) |
(rdat_ddat ? ddat_i : 0) |
(rdat_cdat ? ucdat_i : 0) |
(rdat_pc ? pc : 0);
assign ra_mux = (ra_ir1 ? ir[19:15] : 0) |
(ra_ir2 ? ir[24:20] : 0) |
(ra_ird ? ir[11:7] : 0);
wire pc_pc = ~|{pc_mbvec,pc_pcPlus4,pc_alu,pc_mtvec,pc_mepc};
assign pc_mux = (pc_mbvec ? 64'hFFFF_FFFF_FFFF_FF00 : 64'h0) |
(pc_pcPlus4 ? pc + 4 : 64'h0) |
(pc_alu ? aluXResult : 64'h0) |
(pc_mtvec ? mtvec_i : 64'h0) |
(pc_mepc ? mepc_o : 64'h0) |
(pc_pc ? pc : 64'h0);
wire ia_ia = ~ia_pc;
assign ia_mux = (ia_pc ? pc : 0) |
(ia_ia ? ia : 0);
assign iadr_o = iadr_pc ? pc : 0;
wire ir_ir = ~ir_idat;
assign ir_mux = (ir_idat ? idat_i : 0) |
(ir_ir ? ir : 0);
always @(posedge clk_i) begin
rst <= reset_i;
pc <= pc_mux;
ia <= ia_mux;
ft0 <= ft0_o;
xt0 <= xt0_o;
xt1 <= xt1_o;
xt2 <= xt2_o;
xt3 <= xt3_o;
xt4 <= xt4_o;
ir <= ir_mux;
alua <= alua_mux;
alub <= alub_mux;
ccr <= ccr_mux;
trap <= trap_o;
end
Sequencer s(
.xt0_o(xt0_o),
.xt1_o(xt1_o),
.xt2_o(xt2_o),
.xt3_o(xt3_o),
.xt0(xt0),
.xt1(xt1),
.xt2(xt2),
.xt3(xt3),
.ft0(ft0),
.istb_o(istb_o),
.iadr_pc(iadr_pc),
.iack_i(iack_i),
.pc_mbvec(pc_mbvec),
.pc_pcPlus4(pc_pcPlus4),
.ir_idat(ir_idat),
.ir(ir),
.ft0_o(ft0_o),
.rdat_pc(rdat_pc),
.sum_en(sum_en),
.pc_alu(pc_alu),
.ra_ir1(ra_ir1),
.ra_ir2(ra_ir2),
.ra_ird(ra_ird),
.alua_rdat(alua_rdat),
.alub_rdat(alub_rdat),
.alub_imm12i(alub_imm12i),
.rwe_o(rwe_o),
.rdat_alu(rdat_alu),
.and_en(and_en),
.xor_en(xor_en),
.invB_en(invB_en),
.lsh_en(lsh_en),
.rsh_en(rsh_en),
.cflag_i(cflag_i),
.sx32_en(sx32_en),
.alua_0(alua_0),
.alub_imm20u(alub_imm20u),
.ia_pc(ia_pc),
.alua_ia(alua_ia),
.dadr_alu(dadr_alu),
.dcyc_1(dcyc_1),
.dstb_1(dstb_1),
.dsiz_fn3(dsiz_fn3),
.rdat_ddat(rdat_ddat),
.dack_i(dack_i),
.ddat_rdat(ddat_rdat),
.alub_imm12s(alub_imm12s),
.dwe_o(dwe_o),
.alub_imm20uj(alub_imm20uj),
.ccr_alu(ccr_alu),
.alub_imm12sb(alub_imm12sb),
.xt4_o(xt4_o),
.xt4(xt4),
.ccr(ccr),
.fence_o(fence_o),
.trap_o(trap_o),
.trap(trap),
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.pc_mtvec(pc_mtvec),
.mepc_ia(mepc_ia),
.pc_mepc(pc_mepc),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mie_mpie(mie_mpie),
.mie_0(mie_0),
.csrok_i(cvalid),
.rdat_cdat(rdat_cdat),
.coe_o(coe_1),
.cdat_rdat(cdat_rdat),
.cwe_o(cwe_1),
.cdat_imm5(cdat_imm5),
.cdat_alu(cdat_alu),
.alub_imm5(alub_imm5),
.alua_cdat(alua_cdat),
.take_irq(take_irq),
.mepc_pc(mepc_pc),
.mcause_irq_o(mcause_irq_o),
.ltu_en(ltu_en),
.lts_en(lts_en),
.rst(rst)
);
xrs xrs(
.clk_i(clk_i),
.ra_i(ra_mux),
.rdat_i(rdat_i),
.rdat_o(rdat_o),
.rmask_i({4{rwe_o}})
);
alu alu(
.inA_i(alua),
.inB_i(alub),
.cflag_i(cflag_i),
.sum_en_i(sum_en),
.and_en_i(and_en),
.xor_en_i(xor_en),
.invB_en_i(invB_en),
.lsh_en_i(lsh_en),
.rsh_en_i(rsh_en),
.ltu_en_i(ltu_en),
.lts_en_i(lts_en),
.out_o(aluResult),
.cflag_o(cflag_o),
.vflag_o(vflag_o),
.zflag_o(zflag_o)
);
CSRs csrs(
.cadr_i(cadr_o),
.cvalid_o(icvalid_i),
.cdat_o(icdat_i),
.cdat_i(cdat_o),
.coe_i(coe_o),
.cwe_i(cwe_o),
.mie_0(mie_0),
.mie_mpie(mie_mpie),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mtvec_o(mtvec_i),
.mepc_o(mepc_o),
.mie_o(mie_o),
.mpie_o(mpie_o),
.ft0_i(ft0),
.tick_i(1'b0),
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.mepc_ia(mepc_ia),
.mepc_pc(mepc_pc),
.ia_i(ia),
.pc_i(pc),
.cause_o(cause_o),
.irq_i(irq_i),
.take_irq_o(take_irq),
.mcause_irq_i(mcause_irq_o),
.reset_i(reset_i),
.clk_i(clk_i)
);
endmodule | 4 |
137,936 | data/full_repos/permissive/80873024/rtl/queue_8x9.v | 80,873,024 | queue_8x9.v | v | 86 | 73 | [] | [] | [] | [(3, 84)] | null | data/verilator_xmls/87ef3fa8-cb82-46e5-8ff2-76d8512d0c66.xml | null | 300,760 | module | module queue_8x9(
input clk,
input reset,
input nchar,
input lchar,
input [7:0] char_i,
input stb_i,
output ack_o,
output [8:0] dat_o,
output full_o,
output empty_o,
output [7:0] occupied_tb,
output [2:0] rp_tb,
output [2:0] wp_tb,
output we_tb
);
reg [8:0] queue[0:7];
reg [7:0] occupied;
reg [2:0] rp, wp;
reg oe_r;
assign ack_o = oe_r;
assign dat_o = queue[rp];
assign full_o = occupied[wp];
assign empty_o = ~occupied[rp];
wire is_eop = (char_i[1:0] == 2'b01) | (char_i[1:0] == 2'b10);
wire we = (nchar | (lchar & is_eop));
wire ptrs_eq = (wp == rp);
always @(posedge clk) begin
oe_r <= oe_r;
if(reset) begin
oe_r <= 0;
end
else if(stb_i) begin
oe_r <= 1;
end
else if(oe_r) begin
oe_r <= 0;
end
end
wire should_set_occupied_flag = (~ack_o & we & ~occupied[wp]);
wire read_write_concurrently = (ack_o & we & ptrs_eq);
wire should_store = should_set_occupied_flag | read_write_concurrently;
wire should_pop_queue = ack_o & occupied[rp];
always @(posedge clk) begin
occupied <= occupied;
rp <= rp;
wp <= wp;
if(reset) begin
occupied <= 8'h00;
rp <= 3'd0;
wp <= 3'd0;
end
else begin
if(should_store) begin
queue[wp] <= {lchar, char_i};
wp <= wp + 1;
end
if(should_set_occupied_flag) begin
occupied[wp] <= 1;
end
if(should_pop_queue) begin
if(~read_write_concurrently) begin
occupied[rp] <= 0;
end
rp <= rp + 1;
end
end
end
assign occupied_tb = occupied;
assign rp_tb = rp;
assign wp_tb = wp;
assign we_tb = we;
endmodule | module queue_8x9(
input clk,
input reset,
input nchar,
input lchar,
input [7:0] char_i,
input stb_i,
output ack_o,
output [8:0] dat_o,
output full_o,
output empty_o,
output [7:0] occupied_tb,
output [2:0] rp_tb,
output [2:0] wp_tb,
output we_tb
); |
reg [8:0] queue[0:7];
reg [7:0] occupied;
reg [2:0] rp, wp;
reg oe_r;
assign ack_o = oe_r;
assign dat_o = queue[rp];
assign full_o = occupied[wp];
assign empty_o = ~occupied[rp];
wire is_eop = (char_i[1:0] == 2'b01) | (char_i[1:0] == 2'b10);
wire we = (nchar | (lchar & is_eop));
wire ptrs_eq = (wp == rp);
always @(posedge clk) begin
oe_r <= oe_r;
if(reset) begin
oe_r <= 0;
end
else if(stb_i) begin
oe_r <= 1;
end
else if(oe_r) begin
oe_r <= 0;
end
end
wire should_set_occupied_flag = (~ack_o & we & ~occupied[wp]);
wire read_write_concurrently = (ack_o & we & ptrs_eq);
wire should_store = should_set_occupied_flag | read_write_concurrently;
wire should_pop_queue = ack_o & occupied[rp];
always @(posedge clk) begin
occupied <= occupied;
rp <= rp;
wp <= wp;
if(reset) begin
occupied <= 8'h00;
rp <= 3'd0;
wp <= 3'd0;
end
else begin
if(should_store) begin
queue[wp] <= {lchar, char_i};
wp <= wp + 1;
end
if(should_set_occupied_flag) begin
occupied[wp] <= 1;
end
if(should_pop_queue) begin
if(~read_write_concurrently) begin
occupied[rp] <= 0;
end
rp <= rp + 1;
end
end
end
assign occupied_tb = occupied;
assign rp_tb = rp;
assign wp_tb = wp;
assign we_tb = we;
endmodule | 4 |
137,939 | data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v | 80,873,024 | rx_DS_char_tb.v | v | 111 | 63 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10; rxClk = ~rxClk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v:64: syntax error, unexpected null, expecting TYPE-IDENTIFIER\n task null;\n ^~~~\n%Error: data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v:66: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v:73: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wtf.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80873024/rtl/rx_DS_char_tb.v:74: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 300,763 | module | module rx_DS_char_tb();
reg rxClk, rxReset, dv;
reg [1:0] d;
wire [7:0] q;
wire nchar, lchar;
wire parityError;
rx_DS_char charDecoder(
.rxClk(rxClk),
.rxReset(rxReset),
.d(d),
.dValid(dv),
.q(q),
.nchar(nchar),
.lchar(lchar),
.parityError(parityError)
);
always begin
#10; rxClk = ~rxClk;
end
task bitPair;
input [1:0] pair;
begin
{dv, d} <= {1'b1, pair};
#20;
{dv, d} <= {1'b0, pair};
#20;
end
endtask
task nch;
input oddp;
input [7:0] chr;
begin
bitPair({1'b0, oddp});
bitPair(chr[1:0]);
bitPair(chr[3:2]);
bitPair(chr[5:4]);
bitPair(chr[7:6]);
end
endtask
task lch;
input oddp;
input [1:0] chr;
begin
bitPair({1'b1, oddp});
bitPair(chr);
end
endtask
task null;
input oddp;
begin
lch(oddp, 2'b11);
lch(0, 0);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{rxClk, rxReset, dv, d} <= 0;
#10;
rxReset <= 1;
#20;
rxReset <= 0;
#20;
null(0);
null(0);
nch(1, 8'h41);
lch(0, 2);
null(1);
null(0);
nch(1, 8'h4F);
lch(1, 2);
lch(1, 3);
lch(1, 0);
null(1);
null(0);
nch(1, 8'h41);
nch(1, 8'h62);
nch(0, 8'h63);
nch(1, 8'h64);
lch(1, 2);
null(1);
null(0);
$display("@I Done.");
$stop;
end
endmodule | module rx_DS_char_tb(); |
reg rxClk, rxReset, dv;
reg [1:0] d;
wire [7:0] q;
wire nchar, lchar;
wire parityError;
rx_DS_char charDecoder(
.rxClk(rxClk),
.rxReset(rxReset),
.d(d),
.dValid(dv),
.q(q),
.nchar(nchar),
.lchar(lchar),
.parityError(parityError)
);
always begin
#10; rxClk = ~rxClk;
end
task bitPair;
input [1:0] pair;
begin
{dv, d} <= {1'b1, pair};
#20;
{dv, d} <= {1'b0, pair};
#20;
end
endtask
task nch;
input oddp;
input [7:0] chr;
begin
bitPair({1'b0, oddp});
bitPair(chr[1:0]);
bitPair(chr[3:2]);
bitPair(chr[5:4]);
bitPair(chr[7:6]);
end
endtask
task lch;
input oddp;
input [1:0] chr;
begin
bitPair({1'b1, oddp});
bitPair(chr);
end
endtask
task null;
input oddp;
begin
lch(oddp, 2'b11);
lch(0, 0);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{rxClk, rxReset, dv, d} <= 0;
#10;
rxReset <= 1;
#20;
rxReset <= 0;
#20;
null(0);
null(0);
nch(1, 8'h41);
lch(0, 2);
null(1);
null(0);
nch(1, 8'h4F);
lch(1, 2);
lch(1, 3);
lch(1, 0);
null(1);
null(0);
nch(1, 8'h41);
nch(1, 8'h62);
nch(0, 8'h63);
nch(1, 8'h64);
lch(1, 2);
null(1);
null(0);
$display("@I Done.");
$stop;
end
endmodule | 4 |
137,940 | data/full_repos/permissive/80873024/rtl/rx_DS_SE.v | 80,873,024 | rx_DS_SE.v | v | 107 | 67 | [] | [] | [] | [(23, 105)] | null | data/verilator_xmls/73e00616-8fb1-4ba3-b9a5-bafe47a75cfa.xml | null | 300,764 | module | module rx_DS_SE(
input d,
input s,
input rxClk,
input rxReset,
output [1:0] dq,
output dqValid
);
wire rxPhase = d ^ s;
reg d_r, rxPhase_r;
always @(posedge rxClk) begin
if(rxReset) begin
d_r <= 0;
rxPhase_r <= 0;
end
else begin
d_r <= d;
rxPhase_r <= rxPhase;
end
end
reg rxPhase_rr;
always @(posedge rxClk) begin
if(rxReset) begin
rxPhase_rr <= 0;
end
else begin
rxPhase_rr <= rxPhase_r;
end
end
wire edgeDetect = rxPhase_r ^ rxPhase_rr;
wire bit0Enable = edgeDetect & rxPhase_r;
wire bit1Enable = edgeDetect & ~rxPhase_r;
reg bit0_r, bit1_r;
always @(posedge rxClk) begin
if(rxReset) begin
bit0_r <= 0;
bit1_r <= 0;
end
else begin
if(bit0Enable) begin
bit0_r <= d_r;
end
if(bit1Enable) begin
bit1_r <= d_r;
end
end
end
reg q0, q1, qen, qnfe;
always @(posedge rxClk) begin
if(rxReset) begin
q0 <= 0;
q1 <= 0;
qen <= 0;
qnfe <= 0;
end
else begin
q0 <= bit0_r;
q1 <= bit1_r;
qen <= bit0Enable;
qnfe <= qen | qnfe;
end
end
assign dq = {q1, q0};
assign dqValid = qen & qnfe;
endmodule | module rx_DS_SE(
input d,
input s,
input rxClk,
input rxReset,
output [1:0] dq,
output dqValid
); |
wire rxPhase = d ^ s;
reg d_r, rxPhase_r;
always @(posedge rxClk) begin
if(rxReset) begin
d_r <= 0;
rxPhase_r <= 0;
end
else begin
d_r <= d;
rxPhase_r <= rxPhase;
end
end
reg rxPhase_rr;
always @(posedge rxClk) begin
if(rxReset) begin
rxPhase_rr <= 0;
end
else begin
rxPhase_rr <= rxPhase_r;
end
end
wire edgeDetect = rxPhase_r ^ rxPhase_rr;
wire bit0Enable = edgeDetect & rxPhase_r;
wire bit1Enable = edgeDetect & ~rxPhase_r;
reg bit0_r, bit1_r;
always @(posedge rxClk) begin
if(rxReset) begin
bit0_r <= 0;
bit1_r <= 0;
end
else begin
if(bit0Enable) begin
bit0_r <= d_r;
end
if(bit1Enable) begin
bit1_r <= d_r;
end
end
end
reg q0, q1, qen, qnfe;
always @(posedge rxClk) begin
if(rxReset) begin
q0 <= 0;
q1 <= 0;
qen <= 0;
qnfe <= 0;
end
else begin
q0 <= bit0_r;
q1 <= bit1_r;
qen <= bit0Enable;
qnfe <= qen | qnfe;
end
end
assign dq = {q1, q0};
assign dqValid = qen & qnfe;
endmodule | 4 |
137,946 | data/full_repos/permissive/80873024/rtl/tx_DS_SE.v | 80,873,024 | tx_DS_SE.v | v | 46 | 69 | [] | [] | [] | [(20, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE.v:28: Duplicate declaration of signal: 'D'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg D, S;\n ^\n data/full_repos/permissive/80873024/rtl/tx_DS_SE.v:25: ... Location of original declaration\n output D,\n ^\n%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE.v:28: Duplicate declaration of signal: 'S'\n reg D, S;\n ^\n data/full_repos/permissive/80873024/rtl/tx_DS_SE.v:26: ... Location of original declaration\n output S\n ^\n%Error: Exiting due to 2 error(s)\n" | 300,770 | module | module tx_DS_SE(
input TxClk,
input TxReset,
input Tx1,
input Tx0,
output D,
output S
);
reg D, S;
wire nextD = Tx1;
wire nextS = (Tx0 & ~(D^S)) | (Tx1 & (D^S));
always @(posedge TxClk) begin
D <= D;
S <= S;
if(TxReset) begin
{D, S} <= 2'b00;
end
else if(Tx0 | Tx1) begin
{D, S} <= {nextD, nextS};
end
end
endmodule | module tx_DS_SE(
input TxClk,
input TxReset,
input Tx1,
input Tx0,
output D,
output S
); |
reg D, S;
wire nextD = Tx1;
wire nextS = (Tx0 & ~(D^S)) | (Tx1 & (D^S));
always @(posedge TxClk) begin
D <= D;
S <= S;
if(TxReset) begin
{D, S} <= 2'b00;
end
else if(Tx0 | Tx1) begin
{D, S} <= {nextD, nextS};
end
end
endmodule | 4 |
137,948 | data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v | 80,873,024 | tx_DS_SE_tb.v | v | 285 | 33 | [] | [] | [] | null | line:97: before: "(" | null | 1: b'%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v:3: Cannot find include file: asserts.vh\n`include "asserts.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80873024/rtl,data/full_repos/permissive/80873024/asserts.vh\n data/full_repos/permissive/80873024/rtl,data/full_repos/permissive/80873024/asserts.vh.v\n data/full_repos/permissive/80873024/rtl,data/full_repos/permissive/80873024/asserts.vh.sv\n asserts.vh\n asserts.vh.v\n asserts.vh.sv\n obj_dir/asserts.vh\n obj_dir/asserts.vh.v\n obj_dir/asserts.vh.sv\n%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v:11: Define or directive not defined: \'`DEFIO\'\n `DEFIO(TxClk,1,0)\n ^~~~~~\n%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v:11: syntax error, unexpected \'(\'\n `DEFIO(TxClk,1,0)\n ^~~~~\n%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v:12: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(D,o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v:13: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(S,o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wtf.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80873024/rtl/tx_DS_SE_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n' | 300,772 | module | module tx_DS_SE_tb();
reg [11:0] story_tb;
reg TxClk, TxReset, Tx1, Tx0;
wire D_o, S_o;
`DEFIO(TxClk,1,0)
`DEFASSERT0(D,o)
`DEFASSERT0(S,o)
tx_DS_SE transmitter(
.TxClk(TxClk),
.TxReset(TxReset),
.Tx1(Tx1),
.Tx0(Tx0),
.D(D_o),
.S(S_o)
);
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
story_tb <= 12'h000;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h001;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h002;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h003;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h010;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h011;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h012;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h013;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h020;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h021;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h022;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h023;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h030;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h031;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h032;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h033;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h040;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h041;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h042;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h043;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h050;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h051;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h052;
{Tx0, Tx1} = 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h053;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h060;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h061;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h062;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h070;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h071;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h072;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h080;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h081;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h082;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h090;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h091;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h092;
{Tx1, Tx0} <= 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
$display("@I Done.");
$stop;
end
endmodule | module tx_DS_SE_tb(); |
reg [11:0] story_tb;
reg TxClk, TxReset, Tx1, Tx0;
wire D_o, S_o;
`DEFIO(TxClk,1,0)
`DEFASSERT0(D,o)
`DEFASSERT0(S,o)
tx_DS_SE transmitter(
.TxClk(TxClk),
.TxReset(TxReset),
.Tx1(Tx1),
.Tx0(Tx0),
.D(D_o),
.S(S_o)
);
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
story_tb <= 12'h000;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h001;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h002;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h003;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h010;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h011;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h012;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h013;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h020;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h021;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h022;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h023;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h030;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h031;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h032;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h033;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h040;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h041;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h042;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h043;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h050;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h051;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h052;
{Tx0, Tx1} = 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h053;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h060;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h061;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h062;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h070;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h071;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h072;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h080;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h081;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h082;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h090;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h091;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h092;
{Tx1, Tx0} <= 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
$display("@I Done.");
$stop;
end
endmodule | 4 |
137,951 | data/full_repos/permissive/80923531/rtl/impl_top.v | 80,923,531 | impl_top.v | v | 88 | 78 | [] | [] | [] | [(13, 87)] | null | null | 1: b"%Error: data/full_repos/permissive/80923531/rtl/impl_top.v:56: Cannot find file containing module: 'uart_rx'\nuart_rx #(\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/80923531/rtl,data/full_repos/permissive/80923531/uart_rx\n data/full_repos/permissive/80923531/rtl,data/full_repos/permissive/80923531/uart_rx.v\n data/full_repos/permissive/80923531/rtl,data/full_repos/permissive/80923531/uart_rx.sv\n uart_rx\n uart_rx.v\n uart_rx.sv\n obj_dir/uart_rx\n obj_dir/uart_rx.v\n obj_dir/uart_rx.sv\n%Error: data/full_repos/permissive/80923531/rtl/impl_top.v:73: Cannot find file containing module: 'uart_tx'\nuart_tx #(\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 300,800 | module | module impl_top (
input clk ,
input sw_0 ,
input sw_1 ,
input wire uart_rxd,
output wire uart_txd,
output wire [7:0] led
);
parameter CLK_HZ = 50000000;
parameter BIT_RATE = 9600;
parameter PAYLOAD_BITS = 8;
wire [PAYLOAD_BITS-1:0] uart_rx_data;
wire uart_rx_valid;
wire uart_rx_break;
wire uart_tx_busy;
wire [PAYLOAD_BITS-1:0] uart_tx_data;
wire uart_tx_en;
reg [PAYLOAD_BITS-1:0] led_reg;
assign led = led_reg;
assign uart_tx_data = uart_rx_data;
assign uart_tx_en = uart_rx_valid;
always @(posedge clk) begin
if(!sw_0) begin
led_reg <= 8'hF0;
end else if(uart_rx_valid) begin
led_reg <= uart_rx_data[7:0];
end
end
uart_rx #(
.BIT_RATE(BIT_RATE),
.PAYLOAD_BITS(PAYLOAD_BITS),
.CLK_HZ (CLK_HZ )
) i_uart_rx(
.clk (clk ),
.resetn (sw_0 ),
.uart_rxd (uart_rxd ),
.uart_rx_en (1'b1 ),
.uart_rx_break(uart_rx_break),
.uart_rx_valid(uart_rx_valid),
.uart_rx_data (uart_rx_data )
);
uart_tx #(
.BIT_RATE(BIT_RATE),
.PAYLOAD_BITS(PAYLOAD_BITS),
.CLK_HZ (CLK_HZ )
) i_uart_tx(
.clk (clk ),
.resetn (sw_0 ),
.uart_txd (uart_txd ),
.uart_tx_en (uart_tx_en ),
.uart_tx_busy (uart_tx_busy ),
.uart_tx_data (uart_tx_data )
);
endmodule | module impl_top (
input clk ,
input sw_0 ,
input sw_1 ,
input wire uart_rxd,
output wire uart_txd,
output wire [7:0] led
); |
parameter CLK_HZ = 50000000;
parameter BIT_RATE = 9600;
parameter PAYLOAD_BITS = 8;
wire [PAYLOAD_BITS-1:0] uart_rx_data;
wire uart_rx_valid;
wire uart_rx_break;
wire uart_tx_busy;
wire [PAYLOAD_BITS-1:0] uart_tx_data;
wire uart_tx_en;
reg [PAYLOAD_BITS-1:0] led_reg;
assign led = led_reg;
assign uart_tx_data = uart_rx_data;
assign uart_tx_en = uart_rx_valid;
always @(posedge clk) begin
if(!sw_0) begin
led_reg <= 8'hF0;
end else if(uart_rx_valid) begin
led_reg <= uart_rx_data[7:0];
end
end
uart_rx #(
.BIT_RATE(BIT_RATE),
.PAYLOAD_BITS(PAYLOAD_BITS),
.CLK_HZ (CLK_HZ )
) i_uart_rx(
.clk (clk ),
.resetn (sw_0 ),
.uart_rxd (uart_rxd ),
.uart_rx_en (1'b1 ),
.uart_rx_break(uart_rx_break),
.uart_rx_valid(uart_rx_valid),
.uart_rx_data (uart_rx_data )
);
uart_tx #(
.BIT_RATE(BIT_RATE),
.PAYLOAD_BITS(PAYLOAD_BITS),
.CLK_HZ (CLK_HZ )
) i_uart_tx(
.clk (clk ),
.resetn (sw_0 ),
.uart_txd (uart_txd ),
.uart_tx_en (uart_tx_en ),
.uart_tx_busy (uart_tx_busy ),
.uart_tx_data (uart_tx_data )
);
endmodule | 42 |
137,954 | data/full_repos/permissive/80923531/test/tb.v | 80,923,531 | tb.v | v | 135 | 77 | [] | [] | [] | null | line:39: before: "assign" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/80923531/test/tb.v:39: Unsupported: Ignoring delay on this delayed statement.\nalways begin #(CLK_P/2) assign clk = ~clk; end\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80923531/test/tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #BIT_P; uart_rxd = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80923531/test/tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #BIT_P; uart_rxd = to_send[i];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80923531/test/tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #BIT_P; uart_rxd = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80923531/test/tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80923531/test/tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #40 resetn = 1\'b1;\n ^\n%Error: data/full_repos/permissive/80923531/test/tb.v:93: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./work/waves-sys.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/80923531/test/tb.v:94: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,tb);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,803 | module | module tb;
reg clk ;
reg resetn ;
wire [3:0] sw ;
wire [2:0] rgb0 ;
wire [2:0] rgb1 ;
wire [2:0] rgb2 ;
wire [2:0] rgb3 ;
wire [3:0] led ;
reg uart_rxd ;
localparam BIT_RATE = 11520;
localparam BIT_P = (1000000000/BIT_RATE);
localparam CLK_HZ = 50000000;
localparam CLK_P = 1000000000/ CLK_HZ;
assign sw = {2'b0, 1'b1, resetn};
always begin #(CLK_P/2) assign clk = ~clk; end
task send_byte;
input [7:0] to_send;
integer i;
begin
$display("Sending byte: %d, %b at time %d", to_send,to_send, $time);
#BIT_P; uart_rxd = 1'b0;
for(i=0; i < 8; i = i+1) begin
#BIT_P; uart_rxd = to_send[i];
end
#BIT_P; uart_rxd = 1'b1;
#1000;
end
endtask
task write_register;
input [7:0] register;
input [7:0] value ;
begin
$display("Write register %d with %h", register, value);
send_byte(register);
send_byte(value);
end
endtask
task read_register;
input [7:0] register;
begin
$display("Read register: %d", register);
send_byte(register);
end
endtask
reg [7:0] bytes;
reg [7:0] p_bytes;
initial begin
resetn = 1'b0;
clk = 1'b0;
uart_rxd = 1'b1;
#40 resetn = 1'b1;
$dumpfile("./work/waves-sys.vcd");
$dumpvars(0,tb);
send_byte("A");
send_byte("1");
send_byte("B");
send_byte("2");
send_byte("C");
send_byte("3");
send_byte("D");
send_byte("4");
send_byte(0);
send_byte("a");
send_byte("b");
send_byte("c");
send_byte("d");
send_byte(0);
send_byte(0);
$display("Finish simulation at time %d", $time);
$finish();
end
impl_top #(
.BIT_RATE(BIT_RATE),
.CLK_HZ (CLK_HZ )
) i_dut (
.clk (clk ),
.sw_0 (sw ),
.led (led ),
.uart_rxd (uart_rxd)
);
endmodule | module tb; |
reg clk ;
reg resetn ;
wire [3:0] sw ;
wire [2:0] rgb0 ;
wire [2:0] rgb1 ;
wire [2:0] rgb2 ;
wire [2:0] rgb3 ;
wire [3:0] led ;
reg uart_rxd ;
localparam BIT_RATE = 11520;
localparam BIT_P = (1000000000/BIT_RATE);
localparam CLK_HZ = 50000000;
localparam CLK_P = 1000000000/ CLK_HZ;
assign sw = {2'b0, 1'b1, resetn};
always begin #(CLK_P/2) assign clk = ~clk; end
task send_byte;
input [7:0] to_send;
integer i;
begin
$display("Sending byte: %d, %b at time %d", to_send,to_send, $time);
#BIT_P; uart_rxd = 1'b0;
for(i=0; i < 8; i = i+1) begin
#BIT_P; uart_rxd = to_send[i];
end
#BIT_P; uart_rxd = 1'b1;
#1000;
end
endtask
task write_register;
input [7:0] register;
input [7:0] value ;
begin
$display("Write register %d with %h", register, value);
send_byte(register);
send_byte(value);
end
endtask
task read_register;
input [7:0] register;
begin
$display("Read register: %d", register);
send_byte(register);
end
endtask
reg [7:0] bytes;
reg [7:0] p_bytes;
initial begin
resetn = 1'b0;
clk = 1'b0;
uart_rxd = 1'b1;
#40 resetn = 1'b1;
$dumpfile("./work/waves-sys.vcd");
$dumpvars(0,tb);
send_byte("A");
send_byte("1");
send_byte("B");
send_byte("2");
send_byte("C");
send_byte("3");
send_byte("D");
send_byte("4");
send_byte(0);
send_byte("a");
send_byte("b");
send_byte("c");
send_byte("d");
send_byte(0);
send_byte(0);
$display("Finish simulation at time %d", $time);
$finish();
end
impl_top #(
.BIT_RATE(BIT_RATE),
.CLK_HZ (CLK_HZ )
) i_dut (
.clk (clk ),
.sw_0 (sw ),
.led (led ),
.uart_rxd (uart_rxd)
);
endmodule | 42 |
137,958 | data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_dc.v | 81,091,795 | generic_fifo_dc.v | v | 282 | 78 | [] | [] | [] | [(135, 280)] | null | null | 1: b'%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_dc.v:62: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog,data/full_repos/permissive/81091795/timescale.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_dc.v:181: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n .do( dout ),\n ^~\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_dc.v:181: syntax error, unexpected \'(\', expecting \')\'\n .do( dout ),\n ^~~~\n%Error: Exiting due to 3 error(s)\n' | 301,203 | module | module generic_fifo_dc(rd_clk, wr_clk, rst, clr, din, we, dout, re,
full, empty, full_n, empty_n, level );
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
input rd_clk, wr_clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input re;
output full;
output empty;
output full_n;
output empty_n;
output [1:0] level;
reg [aw:0] wp;
wire [aw:0] wp_pl1;
reg [aw:0] rp;
wire [aw:0] rp_pl1;
reg [aw:0] wp_s, rp_s;
wire [aw:0] diff;
reg [aw:0] diff_r1, diff_r2;
reg re_r, we_r;
reg full, empty, full_n, empty_n;
reg [1:0] level;
generic_dpram #(aw,dw) u0(
.rclk( rd_clk ),
.rrst( !rst ),
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp[aw-1:0] ),
.do( dout ),
.wclk( wr_clk ),
.wrst( !rst ),
.wce( 1'b1 ),
.we( we ),
.waddr( wp[aw-1:0] ),
.di( din )
);
always @(posedge wr_clk `DC_FIFO_ASYNC_RESET)
if(!rst) wp <= #1 {aw+1{1'b0}};
else
if(clr) wp <= #1 {aw+1{1'b0}};
else
if(we) wp <= #1 wp_pl1;
assign wp_pl1 = wp + { {aw{1'b0}}, 1'b1};
always @(posedge rd_clk `DC_FIFO_ASYNC_RESET)
if(!rst) rp <= #1 {aw+1{1'b0}};
else
if(clr) rp <= #1 {aw+1{1'b0}};
else
if(re) rp <= #1 rp_pl1;
assign rp_pl1 = rp + { {aw{1'b0}}, 1'b1};
always @(posedge rd_clk) wp_s <= #1 wp;
always @(posedge wr_clk) rp_s <= #1 rp;
always @(posedge rd_clk)
empty <= #1 (wp_s == rp) | (re & (wp_s == rp_pl1));
always @(posedge wr_clk)
full <= #1 ((wp[aw-1:0] == rp_s[aw-1:0]) & (wp[aw] != rp_s[aw])) |
(we & (wp_pl1[aw-1:0] == rp_s[aw-1:0]) & (wp_pl1[aw] != rp_s[aw]));
assign diff = wp-rp;
always @(posedge rd_clk)
re_r <= #1 re;
always @(posedge rd_clk)
diff_r1 <= #1 diff;
always @(posedge rd_clk)
empty_n <= #1 (diff_r1 < n) | ((diff_r1==n) & (re | re_r));
always @(posedge wr_clk)
we_r <= #1 we;
always @(posedge wr_clk)
diff_r2 <= #1 diff;
always @(posedge wr_clk)
full_n <= #1 (diff_r2 > max_size-n) | ((diff_r2==max_size-n) & (we | we_r));
always @(posedge wr_clk)
level <= #1 {2{diff[aw]}} | diff[aw-1:aw-2];
always @(posedge wr_clk)
if(we & full)
$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
always @(posedge rd_clk)
if(re & empty)
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
endmodule | module generic_fifo_dc(rd_clk, wr_clk, rst, clr, din, we, dout, re,
full, empty, full_n, empty_n, level ); |
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
input rd_clk, wr_clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input re;
output full;
output empty;
output full_n;
output empty_n;
output [1:0] level;
reg [aw:0] wp;
wire [aw:0] wp_pl1;
reg [aw:0] rp;
wire [aw:0] rp_pl1;
reg [aw:0] wp_s, rp_s;
wire [aw:0] diff;
reg [aw:0] diff_r1, diff_r2;
reg re_r, we_r;
reg full, empty, full_n, empty_n;
reg [1:0] level;
generic_dpram #(aw,dw) u0(
.rclk( rd_clk ),
.rrst( !rst ),
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp[aw-1:0] ),
.do( dout ),
.wclk( wr_clk ),
.wrst( !rst ),
.wce( 1'b1 ),
.we( we ),
.waddr( wp[aw-1:0] ),
.di( din )
);
always @(posedge wr_clk `DC_FIFO_ASYNC_RESET)
if(!rst) wp <= #1 {aw+1{1'b0}};
else
if(clr) wp <= #1 {aw+1{1'b0}};
else
if(we) wp <= #1 wp_pl1;
assign wp_pl1 = wp + { {aw{1'b0}}, 1'b1};
always @(posedge rd_clk `DC_FIFO_ASYNC_RESET)
if(!rst) rp <= #1 {aw+1{1'b0}};
else
if(clr) rp <= #1 {aw+1{1'b0}};
else
if(re) rp <= #1 rp_pl1;
assign rp_pl1 = rp + { {aw{1'b0}}, 1'b1};
always @(posedge rd_clk) wp_s <= #1 wp;
always @(posedge wr_clk) rp_s <= #1 rp;
always @(posedge rd_clk)
empty <= #1 (wp_s == rp) | (re & (wp_s == rp_pl1));
always @(posedge wr_clk)
full <= #1 ((wp[aw-1:0] == rp_s[aw-1:0]) & (wp[aw] != rp_s[aw])) |
(we & (wp_pl1[aw-1:0] == rp_s[aw-1:0]) & (wp_pl1[aw] != rp_s[aw]));
assign diff = wp-rp;
always @(posedge rd_clk)
re_r <= #1 re;
always @(posedge rd_clk)
diff_r1 <= #1 diff;
always @(posedge rd_clk)
empty_n <= #1 (diff_r1 < n) | ((diff_r1==n) & (re | re_r));
always @(posedge wr_clk)
we_r <= #1 we;
always @(posedge wr_clk)
diff_r2 <= #1 diff;
always @(posedge wr_clk)
full_n <= #1 (diff_r2 > max_size-n) | ((diff_r2==max_size-n) & (we | we_r));
always @(posedge wr_clk)
level <= #1 {2{diff[aw]}} | diff[aw-1:aw-2];
always @(posedge wr_clk)
if(we & full)
$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
always @(posedge rd_clk)
if(re & empty)
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
endmodule | 1 |
137,959 | data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_sc_b.v | 81,091,795 | generic_fifo_sc_b.v | v | 297 | 78 | [] | [] | [] | [(146, 295)] | null | null | 1: b'%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_sc_b.v:62: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog,data/full_repos/permissive/81091795/timescale.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_sc_b.v:196: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n .do( dout ),\n ^~\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/tags/start/rtl/verilog/generic_fifo_sc_b.v:196: syntax error, unexpected \'(\', expecting \')\'\n .do( dout ),\n ^~~~\n%Error: Exiting due to 3 error(s)\n' | 301,205 | module | module generic_fifo_sc_b(clk, rst, clr, din, we, dout, re,
full, empty, full_r, empty_r,
full_n, empty_n, full_n_r, empty_n_r,
level);
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input re;
output full, full_r;
output empty, empty_r;
output full_n, full_n_r;
output empty_n, empty_n_r;
output [1:0] level;
reg [aw:0] wp;
wire [aw:0] wp_pl1;
reg [aw:0] rp;
wire [aw:0] rp_pl1;
reg full_r;
reg empty_r;
wire [aw:0] diff;
reg [aw:0] diff_r;
reg re_r, we_r;
wire full_n, empty_n;
reg full_n_r, empty_n_r;
reg [1:0] level;
generic_dpram #(aw,dw) u0(
.rclk( clk ),
.rrst( !rst ),
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp[aw-1:0] ),
.do( dout ),
.wclk( clk ),
.wrst( !rst ),
.wce( 1'b1 ),
.we( we ),
.waddr( wp[aw-1:0] ),
.di( din )
);
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) wp <= #1 {aw+1{1'b0}};
else
if(clr) wp <= #1 {aw+1{1'b0}};
else
if(we) wp <= #1 wp_pl1;
assign wp_pl1 = wp + { {aw{1'b0}}, 1'b1};
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) rp <= #1 {aw+1{1'b0}};
else
if(clr) rp <= #1 {aw+1{1'b0}};
else
if(re) rp <= #1 rp_pl1;
assign rp_pl1 = rp + { {aw{1'b0}}, 1'b1};
assign empty = (wp == rp);
assign full = (wp[aw-1:0] == rp[aw-1:0]) & (wp[aw] != rp[aw]);
always @(posedge clk)
empty_r <= #1 (wp == rp) | (re & (wp == rp_pl1));
always @(posedge clk)
full_r <= #1 ((wp[aw-1:0] == rp[aw-1:0]) & (wp[aw] != rp[aw])) |
(we & (wp_pl1[aw-1:0] == rp[aw-1:0]) & (wp_pl1[aw] != rp[aw]));
assign diff = wp-rp;
assign empty_n = diff < n;
assign full_n = !(diff < (max_size-n+1));
always @(posedge clk)
level <= #1 {2{diff[aw]}} | diff[aw-1:aw-2];
always @(posedge clk)
re_r <= #1 re;
always @(posedge clk)
diff_r <= #1 diff;
always @(posedge clk)
empty_n_r <= #1 (diff_r < n) | ((diff_r==n) & (re | re_r));
always @(posedge clk)
we_r <= #1 we;
always @(posedge clk)
full_n_r <= #1 (diff_r > max_size-n) | ((diff_r==max_size-n) & (we | we_r));
always @(posedge clk)
if(we & full)
$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
always @(posedge clk)
if(re & empty)
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
endmodule | module generic_fifo_sc_b(clk, rst, clr, din, we, dout, re,
full, empty, full_r, empty_r,
full_n, empty_n, full_n_r, empty_n_r,
level); |
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input re;
output full, full_r;
output empty, empty_r;
output full_n, full_n_r;
output empty_n, empty_n_r;
output [1:0] level;
reg [aw:0] wp;
wire [aw:0] wp_pl1;
reg [aw:0] rp;
wire [aw:0] rp_pl1;
reg full_r;
reg empty_r;
wire [aw:0] diff;
reg [aw:0] diff_r;
reg re_r, we_r;
wire full_n, empty_n;
reg full_n_r, empty_n_r;
reg [1:0] level;
generic_dpram #(aw,dw) u0(
.rclk( clk ),
.rrst( !rst ),
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp[aw-1:0] ),
.do( dout ),
.wclk( clk ),
.wrst( !rst ),
.wce( 1'b1 ),
.we( we ),
.waddr( wp[aw-1:0] ),
.di( din )
);
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) wp <= #1 {aw+1{1'b0}};
else
if(clr) wp <= #1 {aw+1{1'b0}};
else
if(we) wp <= #1 wp_pl1;
assign wp_pl1 = wp + { {aw{1'b0}}, 1'b1};
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) rp <= #1 {aw+1{1'b0}};
else
if(clr) rp <= #1 {aw+1{1'b0}};
else
if(re) rp <= #1 rp_pl1;
assign rp_pl1 = rp + { {aw{1'b0}}, 1'b1};
assign empty = (wp == rp);
assign full = (wp[aw-1:0] == rp[aw-1:0]) & (wp[aw] != rp[aw]);
always @(posedge clk)
empty_r <= #1 (wp == rp) | (re & (wp == rp_pl1));
always @(posedge clk)
full_r <= #1 ((wp[aw-1:0] == rp[aw-1:0]) & (wp[aw] != rp[aw])) |
(we & (wp_pl1[aw-1:0] == rp[aw-1:0]) & (wp_pl1[aw] != rp[aw]));
assign diff = wp-rp;
assign empty_n = diff < n;
assign full_n = !(diff < (max_size-n+1));
always @(posedge clk)
level <= #1 {2{diff[aw]}} | diff[aw-1:aw-2];
always @(posedge clk)
re_r <= #1 re;
always @(posedge clk)
diff_r <= #1 diff;
always @(posedge clk)
empty_n_r <= #1 (diff_r < n) | ((diff_r==n) & (re | re_r));
always @(posedge clk)
we_r <= #1 we;
always @(posedge clk)
full_n_r <= #1 (diff_r > max_size-n) | ((diff_r==max_size-n) & (we | we_r));
always @(posedge clk)
if(we & full)
$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
always @(posedge clk)
if(re & empty)
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
endmodule | 1 |
137,961 | data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v | 81,091,795 | generic_fifo_lfsr.v | v | 224 | 93 | [] | [] | [] | [(60, 222)] | null | null | 1: b'%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:49: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:188: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n .do(q)\n ^~\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:188: syntax error, unexpected \'(\', expecting \')\'\n .do(q)\n ^\n%Error: Exiting due to 3 error(s)\n' | 301,210 | module | module generic_fifo_lfsr (
clk,
nReset,
rst,
wreq,
rreq,
d,
q,
empty,
full,
aempty,
afull
);
parameter aw = 3;
parameter dw = 8;
input clk;
input nReset;
input rst;
input wreq;
input rreq;
input [dw:1] d;
output [dw:1] q;
output empty;
output full;
output aempty;
output afull;
reg empty, full;
reg [aw:1] rp, wp;
wire [dw:1] ramq;
wire fwreq, frreq;
`ifdef FIFO_ALL_ENTRIES
function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction
`else
function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = ~(q[3] ^ q[2]);
4: lsb = ~(q[4] ^ q[3]);
5: lsb = ~(q[5] ^ q[3]);
6: lsb = ~(q[6] ^ q[5]);
7: lsb = ~(q[7] ^ q[6]);
8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = ~(q[9] ^ q[5]);
10: lsb = ~(q[10] ^ q[7]);
11: lsb = ~(q[11] ^ q[9]);
12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = ~(q[15] ^ q[14]);
16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction
`endif
`ifdef RW_CHECK
assign fwreq = wreq & ~full;
assign frreq = rreq & ~empty;
`else
assign fwreq = wreq;
assign frreq = rreq;
`endif
always @(posedge clk or negedge nReset)
if (~nReset) rp <= #1 0;
else if (rst) rp <= #1 0;
else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};
always @(posedge clk or negedge nReset)
if (~nReset) wp <= #1 0;
else if (rst) wp <= #1 0;
else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};
generic_dpram #(aw, dw)
fiforam (
.wclk(clk),
.wrst(1'b0),
.wce(1'b1),
.we(fwreq),
.waddr(wp),
.di(d),
.rclk(clk),
.rrst(1'b0),
.rce(1'b1),
.oe(1'b1),
.raddr(rp),
.do(q)
);
assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
always @(posedge clk or negedge nReset)
if (~nReset)
empty <= #1 1'b1;
else if (rst)
empty <= #1 1'b1;
else
empty <= #1 aempty | (empty & (~fwreq + frreq));
assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
always @(posedge clk or negedge nReset)
if (~nReset)
full <= #1 1'b0;
else if (rst)
full <= #1 1'b0;
else
full <= #1 afull | ( full & (~frreq + fwreq) );
always @(posedge clk)
if (full & fwreq)
$display("Writing while FIFO full\n");
always @(posedge clk)
if (empty & frreq)
$display("Reading while FIFO empty\n");
endmodule | module generic_fifo_lfsr (
clk,
nReset,
rst,
wreq,
rreq,
d,
q,
empty,
full,
aempty,
afull
); |
parameter aw = 3;
parameter dw = 8;
input clk;
input nReset;
input rst;
input wreq;
input rreq;
input [dw:1] d;
output [dw:1] q;
output empty;
output full;
output aempty;
output afull;
reg empty, full;
reg [aw:1] rp, wp;
wire [dw:1] ramq;
wire fwreq, frreq;
`ifdef FIFO_ALL_ENTRIES
function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction
`else
function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = ~(q[3] ^ q[2]);
4: lsb = ~(q[4] ^ q[3]);
5: lsb = ~(q[5] ^ q[3]);
6: lsb = ~(q[6] ^ q[5]);
7: lsb = ~(q[7] ^ q[6]);
8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = ~(q[9] ^ q[5]);
10: lsb = ~(q[10] ^ q[7]);
11: lsb = ~(q[11] ^ q[9]);
12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = ~(q[15] ^ q[14]);
16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction
`endif
`ifdef RW_CHECK
assign fwreq = wreq & ~full;
assign frreq = rreq & ~empty;
`else
assign fwreq = wreq;
assign frreq = rreq;
`endif
always @(posedge clk or negedge nReset)
if (~nReset) rp <= #1 0;
else if (rst) rp <= #1 0;
else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};
always @(posedge clk or negedge nReset)
if (~nReset) wp <= #1 0;
else if (rst) wp <= #1 0;
else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};
generic_dpram #(aw, dw)
fiforam (
.wclk(clk),
.wrst(1'b0),
.wce(1'b1),
.we(fwreq),
.waddr(wp),
.di(d),
.rclk(clk),
.rrst(1'b0),
.rce(1'b1),
.oe(1'b1),
.raddr(rp),
.do(q)
);
assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
always @(posedge clk or negedge nReset)
if (~nReset)
empty <= #1 1'b1;
else if (rst)
empty <= #1 1'b1;
else
empty <= #1 aempty | (empty & (~fwreq + frreq));
assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
always @(posedge clk or negedge nReset)
if (~nReset)
full <= #1 1'b0;
else if (rst)
full <= #1 1'b0;
else
full <= #1 afull | ( full & (~frreq + fwreq) );
always @(posedge clk)
if (full & fwreq)
$display("Writing while FIFO full\n");
always @(posedge clk)
if (empty & frreq)
$display("Reading while FIFO empty\n");
endmodule | 1 |
137,962 | data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v | 81,091,795 | generic_fifo_lfsr.v | v | 224 | 93 | [] | [] | [] | [(60, 222)] | null | null | 1: b'%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:49: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:188: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n .do(q)\n ^~\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:188: syntax error, unexpected \'(\', expecting \')\'\n .do(q)\n ^\n%Error: Exiting due to 3 error(s)\n' | 301,210 | function | function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction | function lsb; |
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction | 1 |
137,963 | data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v | 81,091,795 | generic_fifo_lfsr.v | v | 224 | 93 | [] | [] | [] | [(60, 222)] | null | null | 1: b'%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:49: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.v\n data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog,data/full_repos/permissive/81091795/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:188: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n .do(q)\n ^~\n%Error: data/full_repos/permissive/81091795/hdlCoresTparty/generic_fifos/trunk/rtl/verilog/generic_fifo_lfsr.v:188: syntax error, unexpected \'(\', expecting \')\'\n .do(q)\n ^\n%Error: Exiting due to 3 error(s)\n' | 301,210 | function | function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = ~(q[3] ^ q[2]);
4: lsb = ~(q[4] ^ q[3]);
5: lsb = ~(q[5] ^ q[3]);
6: lsb = ~(q[6] ^ q[5]);
7: lsb = ~(q[7] ^ q[6]);
8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = ~(q[9] ^ q[5]);
10: lsb = ~(q[10] ^ q[7]);
11: lsb = ~(q[11] ^ q[9]);
12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = ~(q[15] ^ q[14]);
16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction | function lsb; |
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = ~(q[3] ^ q[2]);
4: lsb = ~(q[4] ^ q[3]);
5: lsb = ~(q[5] ^ q[3]);
6: lsb = ~(q[6] ^ q[5]);
7: lsb = ~(q[7] ^ q[6]);
8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = ~(q[9] ^ q[5]);
10: lsb = ~(q[10] ^ q[7]);
11: lsb = ~(q[11] ^ q[9]);
12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = ~(q[15] ^ q[14]);
16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction | 1 |
137,967 | data/full_repos/permissive/81255704/HW_QSYS/HW_QSYS_bb.v | 81,255,704 | HW_QSYS_bb.v | v | 99 | 59 | [] | [] | [] | [(2, 98)] | null | data/verilator_xmls/964c7c35-3473-4273-98d0-eba0983c17e2.xml | null | 301,258 | module | module HW_QSYS (
clk_125_clk,
clk_50_clk,
i2c_scl_export,
i2c_sda_export,
key_export,
ledg_export,
ledr_export,
lpddr2_mem_ca,
lpddr2_mem_ck,
lpddr2_mem_ck_n,
lpddr2_mem_cke,
lpddr2_mem_cs_n,
lpddr2_mem_dm,
lpddr2_mem_dq,
lpddr2_mem_dqs,
lpddr2_mem_dqs_n,
lpddr2_global_reset_reset_n,
lpddr2_oct_rzqin,
lpddr2_pll_ref_clk_clk,
lpddr2_pll_sharing_pll_mem_clk,
lpddr2_pll_sharing_pll_write_clk,
lpddr2_pll_sharing_pll_locked,
lpddr2_pll_sharing_pll_write_clk_pre_phy_clk,
lpddr2_pll_sharing_pll_addr_cmd_clk,
lpddr2_pll_sharing_pll_avl_clk,
lpddr2_pll_sharing_pll_config_clk,
lpddr2_pll_sharing_pll_mem_phy_clk,
lpddr2_pll_sharing_afi_phy_clk,
lpddr2_pll_sharing_pll_avl_phy_clk,
lpddr2_status_local_init_done,
lpddr2_status_local_cal_success,
lpddr2_status_local_cal_fail,
reset_reset_n,
sd_sd_clk,
sd_sd_cmd,
sd_sd_dat,
sram_bridge_out_sram_tcm_data_out,
sram_bridge_out_sram_tcm_address_out,
sram_bridge_out_sram_tcm_outputenable_n_out,
sram_bridge_out_sram_tcm_chipselect_n_out,
sram_bridge_out_sram_tcm_byteenable_n_out,
sram_bridge_out_sram_tcm_write_n_out,
video_RGB_OUT,
video_HD,
video_VD,
video_DEN,
video_clk_clk);
input clk_125_clk;
input clk_50_clk;
output i2c_scl_export;
inout i2c_sda_export;
input [3:0] key_export;
output [7:0] ledg_export;
output [7:0] ledr_export;
output [9:0] lpddr2_mem_ca;
output [0:0] lpddr2_mem_ck;
output [0:0] lpddr2_mem_ck_n;
output [0:0] lpddr2_mem_cke;
output [0:0] lpddr2_mem_cs_n;
output [3:0] lpddr2_mem_dm;
inout [31:0] lpddr2_mem_dq;
inout [3:0] lpddr2_mem_dqs;
inout [3:0] lpddr2_mem_dqs_n;
input lpddr2_global_reset_reset_n;
input lpddr2_oct_rzqin;
input lpddr2_pll_ref_clk_clk;
output lpddr2_pll_sharing_pll_mem_clk;
output lpddr2_pll_sharing_pll_write_clk;
output lpddr2_pll_sharing_pll_locked;
output lpddr2_pll_sharing_pll_write_clk_pre_phy_clk;
output lpddr2_pll_sharing_pll_addr_cmd_clk;
output lpddr2_pll_sharing_pll_avl_clk;
output lpddr2_pll_sharing_pll_config_clk;
output lpddr2_pll_sharing_pll_mem_phy_clk;
output lpddr2_pll_sharing_afi_phy_clk;
output lpddr2_pll_sharing_pll_avl_phy_clk;
output lpddr2_status_local_init_done;
output lpddr2_status_local_cal_success;
output lpddr2_status_local_cal_fail;
input reset_reset_n;
output sd_sd_clk;
inout sd_sd_cmd;
inout [3:0] sd_sd_dat;
inout [15:0] sram_bridge_out_sram_tcm_data_out;
output [18:0] sram_bridge_out_sram_tcm_address_out;
output [0:0] sram_bridge_out_sram_tcm_outputenable_n_out;
output [0:0] sram_bridge_out_sram_tcm_chipselect_n_out;
output [1:0] sram_bridge_out_sram_tcm_byteenable_n_out;
output [0:0] sram_bridge_out_sram_tcm_write_n_out;
output [23:0] video_RGB_OUT;
output video_HD;
output video_VD;
output video_DEN;
output video_clk_clk;
endmodule | module HW_QSYS (
clk_125_clk,
clk_50_clk,
i2c_scl_export,
i2c_sda_export,
key_export,
ledg_export,
ledr_export,
lpddr2_mem_ca,
lpddr2_mem_ck,
lpddr2_mem_ck_n,
lpddr2_mem_cke,
lpddr2_mem_cs_n,
lpddr2_mem_dm,
lpddr2_mem_dq,
lpddr2_mem_dqs,
lpddr2_mem_dqs_n,
lpddr2_global_reset_reset_n,
lpddr2_oct_rzqin,
lpddr2_pll_ref_clk_clk,
lpddr2_pll_sharing_pll_mem_clk,
lpddr2_pll_sharing_pll_write_clk,
lpddr2_pll_sharing_pll_locked,
lpddr2_pll_sharing_pll_write_clk_pre_phy_clk,
lpddr2_pll_sharing_pll_addr_cmd_clk,
lpddr2_pll_sharing_pll_avl_clk,
lpddr2_pll_sharing_pll_config_clk,
lpddr2_pll_sharing_pll_mem_phy_clk,
lpddr2_pll_sharing_afi_phy_clk,
lpddr2_pll_sharing_pll_avl_phy_clk,
lpddr2_status_local_init_done,
lpddr2_status_local_cal_success,
lpddr2_status_local_cal_fail,
reset_reset_n,
sd_sd_clk,
sd_sd_cmd,
sd_sd_dat,
sram_bridge_out_sram_tcm_data_out,
sram_bridge_out_sram_tcm_address_out,
sram_bridge_out_sram_tcm_outputenable_n_out,
sram_bridge_out_sram_tcm_chipselect_n_out,
sram_bridge_out_sram_tcm_byteenable_n_out,
sram_bridge_out_sram_tcm_write_n_out,
video_RGB_OUT,
video_HD,
video_VD,
video_DEN,
video_clk_clk); |
input clk_125_clk;
input clk_50_clk;
output i2c_scl_export;
inout i2c_sda_export;
input [3:0] key_export;
output [7:0] ledg_export;
output [7:0] ledr_export;
output [9:0] lpddr2_mem_ca;
output [0:0] lpddr2_mem_ck;
output [0:0] lpddr2_mem_ck_n;
output [0:0] lpddr2_mem_cke;
output [0:0] lpddr2_mem_cs_n;
output [3:0] lpddr2_mem_dm;
inout [31:0] lpddr2_mem_dq;
inout [3:0] lpddr2_mem_dqs;
inout [3:0] lpddr2_mem_dqs_n;
input lpddr2_global_reset_reset_n;
input lpddr2_oct_rzqin;
input lpddr2_pll_ref_clk_clk;
output lpddr2_pll_sharing_pll_mem_clk;
output lpddr2_pll_sharing_pll_write_clk;
output lpddr2_pll_sharing_pll_locked;
output lpddr2_pll_sharing_pll_write_clk_pre_phy_clk;
output lpddr2_pll_sharing_pll_addr_cmd_clk;
output lpddr2_pll_sharing_pll_avl_clk;
output lpddr2_pll_sharing_pll_config_clk;
output lpddr2_pll_sharing_pll_mem_phy_clk;
output lpddr2_pll_sharing_afi_phy_clk;
output lpddr2_pll_sharing_pll_avl_phy_clk;
output lpddr2_status_local_init_done;
output lpddr2_status_local_cal_success;
output lpddr2_status_local_cal_fail;
input reset_reset_n;
output sd_sd_clk;
inout sd_sd_cmd;
inout [3:0] sd_sd_dat;
inout [15:0] sram_bridge_out_sram_tcm_data_out;
output [18:0] sram_bridge_out_sram_tcm_address_out;
output [0:0] sram_bridge_out_sram_tcm_outputenable_n_out;
output [0:0] sram_bridge_out_sram_tcm_chipselect_n_out;
output [1:0] sram_bridge_out_sram_tcm_byteenable_n_out;
output [0:0] sram_bridge_out_sram_tcm_write_n_out;
output [23:0] video_RGB_OUT;
output video_HD;
output video_VD;
output video_DEN;
output video_clk_clk;
endmodule | 13 |
137,969 | data/full_repos/permissive/81255704/ip/sd_cont/sd_clock_divider.v | 81,255,704 | sd_clock_divider.v | v | 80 | 71 | [] | ['general public license', 'free software foundation'] | [] | [(49, 77)] | null | data/verilator_xmls/9c33727b-7f5e-462a-a0d4-d71087bf5550.xml | null | 301,531 | module | module sd_clock_divider (
input CLK,
input [7:0] DIVIDER,
input RST,
output SD_CLK
);
reg [7:0] ClockDiv;
reg SD_CLK_O;
assign SD_CLK = DIVIDER[7] ? CLK : SD_CLK_O;
always @(posedge CLK or posedge RST)
begin
if (RST) begin
ClockDiv <= 8'b0000_0000;
SD_CLK_O <= 0;
end
else if (ClockDiv == DIVIDER) begin
ClockDiv <= 0;
SD_CLK_O <= ~SD_CLK_O;
end else begin
ClockDiv <= ClockDiv + 8'h1;
SD_CLK_O <= SD_CLK_O;
end
end
endmodule | module sd_clock_divider (
input CLK,
input [7:0] DIVIDER,
input RST,
output SD_CLK
); |
reg [7:0] ClockDiv;
reg SD_CLK_O;
assign SD_CLK = DIVIDER[7] ? CLK : SD_CLK_O;
always @(posedge CLK or posedge RST)
begin
if (RST) begin
ClockDiv <= 8'b0000_0000;
SD_CLK_O <= 0;
end
else if (ClockDiv == DIVIDER) begin
ClockDiv <= 0;
SD_CLK_O <= ~SD_CLK_O;
end else begin
ClockDiv <= ClockDiv + 8'h1;
SD_CLK_O <= SD_CLK_O;
end
end
endmodule | 13 |
137,971 | data/full_repos/permissive/81548712/fpga/mu500rx/displayik_7seg_16.v | 81,548,712 | displayik_7seg_16.v | v | 384 | 67 | [] | [] | [] | [(2, 164), (166, 321), (323, 354), (356, 382)] | null | data/verilator_xmls/600bdefb-b4ae-447d-a157-639e7ed04578.xml | null | 301,544 | module | module displayIK_7seg_16
(
input wire CLK,
input wire RSTN,
input wire [15:0] data0,
input wire [15:0] data1,
input wire [15:0] data2,
input wire [15:0] data3,
input wire [15:0] data4,
input wire [15:0] data5,
input wire [15:0] data6,
input wire [15:0] data7,
input wire [15:0] data8,
input wire [15:0] data9,
input wire [15:0] data10,
input wire [15:0] data11,
input wire [15:0] data12,
input wire [15:0] data13,
input wire [15:0] data14,
input wire [15:0] data15,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL
);
wire [31:0] SEG_0,SEG_1,SEG_2,SEG_3,SEG_4,SEG_5,SEG_6,SEG_7;
wire [31:0] SEG_8,SEG_9,SEG_10,SEG_11,SEG_12,SEG_13,SEG_14,SEG_15;
display_module_async_16b
i0
(
.data (data0),
.SEG_32 (SEG_0)
);
display_module_async_16b
i1
(
.data (data1),
.SEG_32 (SEG_1)
);
display_module_async_16b
i2
(
.data (data2),
.SEG_32 (SEG_2)
);
display_module_async_16b
i3
(
.data (data3),
.SEG_32 (SEG_3)
);
display_module_async_16b
i4
(
.data (data4),
.SEG_32 (SEG_4)
);
display_module_async_16b
i5
(
.data (data5),
.SEG_32 (SEG_5)
);
display_module_async_16b
i6
(
.data (data6),
.SEG_32 (SEG_6)
);
display_module_async_16b
i7
(
.data (data7),
.SEG_32 (SEG_7)
);
display_module_async_16b
i8
(
.data (data8),
.SEG_32 (SEG_8)
);
display_module_async_16b
i9
(
.data (data9),
.SEG_32 (SEG_9)
);
display_module_async_16b
i10
(
.data (data10),
.SEG_32 (SEG_10)
);
display_module_async_16b
i11
(
.data (data11),
.SEG_32 (SEG_11)
);
display_module_async_16b
i12
(
.data (data12),
.SEG_32 (SEG_12)
);
display_module_async_16b
i13
(
.data (data13),
.SEG_32 (SEG_13)
);
display_module_async_16b
i14
(
.data (data14),
.SEG_32 (SEG_14)
);
display_module_async_16b
i15
(
.data (data15),
.SEG_32 (SEG_15)
);
dynamic_displayIK_16
i16
(
.CLK (CLK),
.RST (RSTN),
.SEG_0 (SEG_0),
.SEG_1 (SEG_1),
.SEG_2 (SEG_2),
.SEG_3 (SEG_3),
.SEG_4 (SEG_4),
.SEG_5 (SEG_5),
.SEG_6 (SEG_6),
.SEG_7 (SEG_7),
.SEG_8 (SEG_8),
.SEG_9 (SEG_9),
.SEG_10 (SEG_10),
.SEG_11 (SEG_11),
.SEG_12 (SEG_12),
.SEG_13 (SEG_13),
.SEG_14 (SEG_14),
.SEG_15 (SEG_15),
.SEG_A (SEG_A),
.SEG_B (SEG_B),
.SEG_C (SEG_C),
.SEG_D (SEG_D),
.SEG_E (SEG_E),
.SEG_F (SEG_F),
.SEG_G (SEG_G),
.SEG_H (SEG_H),
.SEG_SEL (SEG_SEL)
);
endmodule | module displayIK_7seg_16
(
input wire CLK,
input wire RSTN,
input wire [15:0] data0,
input wire [15:0] data1,
input wire [15:0] data2,
input wire [15:0] data3,
input wire [15:0] data4,
input wire [15:0] data5,
input wire [15:0] data6,
input wire [15:0] data7,
input wire [15:0] data8,
input wire [15:0] data9,
input wire [15:0] data10,
input wire [15:0] data11,
input wire [15:0] data12,
input wire [15:0] data13,
input wire [15:0] data14,
input wire [15:0] data15,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL
); |
wire [31:0] SEG_0,SEG_1,SEG_2,SEG_3,SEG_4,SEG_5,SEG_6,SEG_7;
wire [31:0] SEG_8,SEG_9,SEG_10,SEG_11,SEG_12,SEG_13,SEG_14,SEG_15;
display_module_async_16b
i0
(
.data (data0),
.SEG_32 (SEG_0)
);
display_module_async_16b
i1
(
.data (data1),
.SEG_32 (SEG_1)
);
display_module_async_16b
i2
(
.data (data2),
.SEG_32 (SEG_2)
);
display_module_async_16b
i3
(
.data (data3),
.SEG_32 (SEG_3)
);
display_module_async_16b
i4
(
.data (data4),
.SEG_32 (SEG_4)
);
display_module_async_16b
i5
(
.data (data5),
.SEG_32 (SEG_5)
);
display_module_async_16b
i6
(
.data (data6),
.SEG_32 (SEG_6)
);
display_module_async_16b
i7
(
.data (data7),
.SEG_32 (SEG_7)
);
display_module_async_16b
i8
(
.data (data8),
.SEG_32 (SEG_8)
);
display_module_async_16b
i9
(
.data (data9),
.SEG_32 (SEG_9)
);
display_module_async_16b
i10
(
.data (data10),
.SEG_32 (SEG_10)
);
display_module_async_16b
i11
(
.data (data11),
.SEG_32 (SEG_11)
);
display_module_async_16b
i12
(
.data (data12),
.SEG_32 (SEG_12)
);
display_module_async_16b
i13
(
.data (data13),
.SEG_32 (SEG_13)
);
display_module_async_16b
i14
(
.data (data14),
.SEG_32 (SEG_14)
);
display_module_async_16b
i15
(
.data (data15),
.SEG_32 (SEG_15)
);
dynamic_displayIK_16
i16
(
.CLK (CLK),
.RST (RSTN),
.SEG_0 (SEG_0),
.SEG_1 (SEG_1),
.SEG_2 (SEG_2),
.SEG_3 (SEG_3),
.SEG_4 (SEG_4),
.SEG_5 (SEG_5),
.SEG_6 (SEG_6),
.SEG_7 (SEG_7),
.SEG_8 (SEG_8),
.SEG_9 (SEG_9),
.SEG_10 (SEG_10),
.SEG_11 (SEG_11),
.SEG_12 (SEG_12),
.SEG_13 (SEG_13),
.SEG_14 (SEG_14),
.SEG_15 (SEG_15),
.SEG_A (SEG_A),
.SEG_B (SEG_B),
.SEG_C (SEG_C),
.SEG_D (SEG_D),
.SEG_E (SEG_E),
.SEG_F (SEG_F),
.SEG_G (SEG_G),
.SEG_H (SEG_H),
.SEG_SEL (SEG_SEL)
);
endmodule | 10 |
137,972 | data/full_repos/permissive/81548712/fpga/mu500rx/displayik_7seg_16.v | 81,548,712 | displayik_7seg_16.v | v | 384 | 67 | [] | [] | [] | [(2, 164), (166, 321), (323, 354), (356, 382)] | null | data/verilator_xmls/600bdefb-b4ae-447d-a157-639e7ed04578.xml | null | 301,544 | module | module dynamic_displayIK_16
(
input wire CLK,
input wire RST,
input wire [31:0] SEG_0,
input wire [31:0] SEG_1,
input wire [31:0] SEG_2,
input wire [31:0] SEG_3,
input wire [31:0] SEG_4,
input wire [31:0] SEG_5,
input wire [31:0] SEG_6,
input wire [31:0] SEG_7,
input wire [31:0] SEG_8,
input wire [31:0] SEG_9,
input wire [31:0] SEG_10,
input wire [31:0] SEG_11,
input wire [31:0] SEG_12,
input wire [31:0] SEG_13,
input wire [31:0] SEG_14,
input wire [31:0] SEG_15,
output reg [7:0] SEG_A,
output reg [7:0] SEG_B,
output reg [7:0] SEG_C,
output reg [7:0] SEG_D,
output reg [7:0] SEG_E,
output reg [7:0] SEG_F,
output reg [7:0] SEG_G,
output reg [7:0] SEG_H,
output reg [8:0] SEG_SEL
);
localparam DEF_MAX = 16'h7FFF;
localparam COUNT_MAX = 3'b111;
reg [2:0] COUNTER;
reg [15:0] DEF_COUNTER;
always @(posedge CLK or negedge RST) begin
if(!RST) begin
SEG_A <= 8'hFC;
SEG_B <= 8'hFC;
SEG_C <= 8'hFC;
SEG_D <= 8'hFC;
SEG_E <= 8'hFC;
SEG_F <= 8'hFC;
SEG_G <= 8'hFC;
SEG_H <= 8'hFC;
SEG_SEL <=9'h1FF;
COUNTER <= 3'h0;
DEF_COUNTER <= 16'h0000;
end else begin
if(DEF_COUNTER != DEF_MAX) begin
DEF_COUNTER <= DEF_COUNTER + 16'd1;
SEG_SEL <=9'h000;
end
else begin
DEF_COUNTER <= 16'h0000;
case(COUNTER)
3'd0: begin
SEG_A <= SEG_0[31:24];
SEG_B <= SEG_0[23:16];
SEG_C <= SEG_0[15:8];
SEG_D <= SEG_0[7:0];
SEG_E <= SEG_1[31:24];
SEG_F <= SEG_1[23:16];
SEG_G <= SEG_1[15:8];
SEG_H <= SEG_1[7:0];
SEG_SEL <= 9'b0_0000_0001;
end
3'd1: begin
SEG_A <= SEG_2[31:24];
SEG_B <= SEG_2[23:16];
SEG_C <= SEG_2[15:8];
SEG_D <= SEG_2[7:0];
SEG_E <= SEG_3[31:24];
SEG_F <= SEG_3[23:16];
SEG_G <= SEG_3[15:8];
SEG_H <= SEG_3[7:0];
SEG_SEL <= 9'b0_0000_0010;
end
3'd2: begin
SEG_A <= SEG_4[31:24];
SEG_B <= SEG_4[23:16];
SEG_C <= SEG_4[15:8];
SEG_D <= SEG_4[7:0];
SEG_E <= SEG_5[31:24];
SEG_F <= SEG_5[23:16];
SEG_G <= SEG_5[15:8];
SEG_H <= SEG_5[7:0];
SEG_SEL <= 9'b0_0000_0100;
end
3'd3: begin
SEG_A <= SEG_6[31:24];
SEG_B <= SEG_6[23:16];
SEG_C <= SEG_6[15:8];
SEG_D <= SEG_6[7:0];
SEG_E <= SEG_7[31:24];
SEG_F <= SEG_7[23:16];
SEG_G <= SEG_7[15:8];
SEG_H <= SEG_7[7:0];
SEG_SEL <= 9'b0_0000_1000;
end
3'd4: begin
SEG_A <= SEG_8[31:24];
SEG_B <= SEG_8[23:16];
SEG_C <= SEG_8[15:8];
SEG_D <= SEG_8[7:0];
SEG_E <= SEG_9[31:24];
SEG_F <= SEG_9[23:16];
SEG_G <= SEG_9[15:8];
SEG_H <= SEG_9[7:0];
SEG_SEL <= 9'b0_0001_0000;
end
3'd5: begin
SEG_A <= SEG_10[31:24];
SEG_B <= SEG_10[23:16];
SEG_C <= SEG_10[15:8];
SEG_D <= SEG_10[7:0];
SEG_E <= SEG_11[31:24];
SEG_F <= SEG_11[23:16];
SEG_G <= SEG_11[15:8];
SEG_H <= SEG_11[7:0];
SEG_SEL <= 9'b0_0010_0000;
end
3'd6: begin
SEG_A <= SEG_12[31:24];
SEG_B <= SEG_12[23:16];
SEG_C <= SEG_12[15:8];
SEG_D <= SEG_12[7:0];
SEG_E <= SEG_13[31:24];
SEG_F <= SEG_13[23:16];
SEG_G <= SEG_13[15:8];
SEG_H <= SEG_13[7:0];
SEG_SEL <= 9'b0_0100_0000;
end
3'd7: begin
SEG_A <= SEG_14[31:24];
SEG_B <= SEG_14[23:16];
SEG_C <= SEG_14[15:8];
SEG_D <= SEG_14[7:0];
SEG_E <= SEG_15[31:24];
SEG_F <= SEG_15[23:16];
SEG_G <= SEG_15[15:8];
SEG_H <= SEG_15[7:0];
SEG_SEL <= 9'b0_1000_0000;
end
endcase
if(COUNTER == COUNT_MAX) begin
COUNTER <= 3'd0;
end else begin
COUNTER <= COUNTER + 3'd1;
end
end
end
end
endmodule | module dynamic_displayIK_16
(
input wire CLK,
input wire RST,
input wire [31:0] SEG_0,
input wire [31:0] SEG_1,
input wire [31:0] SEG_2,
input wire [31:0] SEG_3,
input wire [31:0] SEG_4,
input wire [31:0] SEG_5,
input wire [31:0] SEG_6,
input wire [31:0] SEG_7,
input wire [31:0] SEG_8,
input wire [31:0] SEG_9,
input wire [31:0] SEG_10,
input wire [31:0] SEG_11,
input wire [31:0] SEG_12,
input wire [31:0] SEG_13,
input wire [31:0] SEG_14,
input wire [31:0] SEG_15,
output reg [7:0] SEG_A,
output reg [7:0] SEG_B,
output reg [7:0] SEG_C,
output reg [7:0] SEG_D,
output reg [7:0] SEG_E,
output reg [7:0] SEG_F,
output reg [7:0] SEG_G,
output reg [7:0] SEG_H,
output reg [8:0] SEG_SEL
); |
localparam DEF_MAX = 16'h7FFF;
localparam COUNT_MAX = 3'b111;
reg [2:0] COUNTER;
reg [15:0] DEF_COUNTER;
always @(posedge CLK or negedge RST) begin
if(!RST) begin
SEG_A <= 8'hFC;
SEG_B <= 8'hFC;
SEG_C <= 8'hFC;
SEG_D <= 8'hFC;
SEG_E <= 8'hFC;
SEG_F <= 8'hFC;
SEG_G <= 8'hFC;
SEG_H <= 8'hFC;
SEG_SEL <=9'h1FF;
COUNTER <= 3'h0;
DEF_COUNTER <= 16'h0000;
end else begin
if(DEF_COUNTER != DEF_MAX) begin
DEF_COUNTER <= DEF_COUNTER + 16'd1;
SEG_SEL <=9'h000;
end
else begin
DEF_COUNTER <= 16'h0000;
case(COUNTER)
3'd0: begin
SEG_A <= SEG_0[31:24];
SEG_B <= SEG_0[23:16];
SEG_C <= SEG_0[15:8];
SEG_D <= SEG_0[7:0];
SEG_E <= SEG_1[31:24];
SEG_F <= SEG_1[23:16];
SEG_G <= SEG_1[15:8];
SEG_H <= SEG_1[7:0];
SEG_SEL <= 9'b0_0000_0001;
end
3'd1: begin
SEG_A <= SEG_2[31:24];
SEG_B <= SEG_2[23:16];
SEG_C <= SEG_2[15:8];
SEG_D <= SEG_2[7:0];
SEG_E <= SEG_3[31:24];
SEG_F <= SEG_3[23:16];
SEG_G <= SEG_3[15:8];
SEG_H <= SEG_3[7:0];
SEG_SEL <= 9'b0_0000_0010;
end
3'd2: begin
SEG_A <= SEG_4[31:24];
SEG_B <= SEG_4[23:16];
SEG_C <= SEG_4[15:8];
SEG_D <= SEG_4[7:0];
SEG_E <= SEG_5[31:24];
SEG_F <= SEG_5[23:16];
SEG_G <= SEG_5[15:8];
SEG_H <= SEG_5[7:0];
SEG_SEL <= 9'b0_0000_0100;
end
3'd3: begin
SEG_A <= SEG_6[31:24];
SEG_B <= SEG_6[23:16];
SEG_C <= SEG_6[15:8];
SEG_D <= SEG_6[7:0];
SEG_E <= SEG_7[31:24];
SEG_F <= SEG_7[23:16];
SEG_G <= SEG_7[15:8];
SEG_H <= SEG_7[7:0];
SEG_SEL <= 9'b0_0000_1000;
end
3'd4: begin
SEG_A <= SEG_8[31:24];
SEG_B <= SEG_8[23:16];
SEG_C <= SEG_8[15:8];
SEG_D <= SEG_8[7:0];
SEG_E <= SEG_9[31:24];
SEG_F <= SEG_9[23:16];
SEG_G <= SEG_9[15:8];
SEG_H <= SEG_9[7:0];
SEG_SEL <= 9'b0_0001_0000;
end
3'd5: begin
SEG_A <= SEG_10[31:24];
SEG_B <= SEG_10[23:16];
SEG_C <= SEG_10[15:8];
SEG_D <= SEG_10[7:0];
SEG_E <= SEG_11[31:24];
SEG_F <= SEG_11[23:16];
SEG_G <= SEG_11[15:8];
SEG_H <= SEG_11[7:0];
SEG_SEL <= 9'b0_0010_0000;
end
3'd6: begin
SEG_A <= SEG_12[31:24];
SEG_B <= SEG_12[23:16];
SEG_C <= SEG_12[15:8];
SEG_D <= SEG_12[7:0];
SEG_E <= SEG_13[31:24];
SEG_F <= SEG_13[23:16];
SEG_G <= SEG_13[15:8];
SEG_H <= SEG_13[7:0];
SEG_SEL <= 9'b0_0100_0000;
end
3'd7: begin
SEG_A <= SEG_14[31:24];
SEG_B <= SEG_14[23:16];
SEG_C <= SEG_14[15:8];
SEG_D <= SEG_14[7:0];
SEG_E <= SEG_15[31:24];
SEG_F <= SEG_15[23:16];
SEG_G <= SEG_15[15:8];
SEG_H <= SEG_15[7:0];
SEG_SEL <= 9'b0_1000_0000;
end
endcase
if(COUNTER == COUNT_MAX) begin
COUNTER <= 3'd0;
end else begin
COUNTER <= COUNTER + 3'd1;
end
end
end
end
endmodule | 10 |
137,973 | data/full_repos/permissive/81548712/fpga/mu500rx/displayik_7seg_16.v | 81,548,712 | displayik_7seg_16.v | v | 384 | 67 | [] | [] | [] | [(2, 164), (166, 321), (323, 354), (356, 382)] | null | data/verilator_xmls/600bdefb-b4ae-447d-a157-639e7ed04578.xml | null | 301,544 | module | module display_module_async_16b
(
input wire [15:0] data,
output wire [31:0] SEG_32
);
display_module_async
i0
(
.SEG_VAL (data[3:0]),
.SEG (SEG_32[7:0])
);
display_module_async
i1
(
.SEG_VAL (data[7:4]),
.SEG (SEG_32[15:8])
);
display_module_async
i2
(
.SEG_VAL (data[11:8]),
.SEG (SEG_32[23:16])
);
display_module_async
i3
(
.SEG_VAL (data[15:12]),
.SEG (SEG_32[31:24])
);
endmodule | module display_module_async_16b
(
input wire [15:0] data,
output wire [31:0] SEG_32
); |
display_module_async
i0
(
.SEG_VAL (data[3:0]),
.SEG (SEG_32[7:0])
);
display_module_async
i1
(
.SEG_VAL (data[7:4]),
.SEG (SEG_32[15:8])
);
display_module_async
i2
(
.SEG_VAL (data[11:8]),
.SEG (SEG_32[23:16])
);
display_module_async
i3
(
.SEG_VAL (data[15:12]),
.SEG (SEG_32[31:24])
);
endmodule | 10 |
137,974 | data/full_repos/permissive/81548712/fpga/mu500rx/displayik_7seg_16.v | 81,548,712 | displayik_7seg_16.v | v | 384 | 67 | [] | [] | [] | [(2, 164), (166, 321), (323, 354), (356, 382)] | null | data/verilator_xmls/600bdefb-b4ae-447d-a157-639e7ed04578.xml | null | 301,544 | module | module display_module_async
(
input wire [3:0] SEG_VAL,
output reg [7:0] SEG
);
always @ (*) begin
case (SEG_VAL)
4'h0: SEG <= 8'b11111100;
4'h1: SEG <= 8'b01100000;
4'h2: SEG <= 8'b11011010;
4'h3: SEG <= 8'b11110010;
4'h4: SEG <= 8'b01100110;
4'h5: SEG <= 8'b10110110;
4'h6: SEG <= 8'b10111110;
4'h7: SEG <= 8'b11100000;
4'h8: SEG <= 8'b11111110;
4'h9: SEG <= 8'b11110110;
4'ha: SEG <= 8'b11101110;
4'hb: SEG <= 8'b00111110;
4'hc: SEG <= 8'b00011010;
4'hd: SEG <= 8'b01111010;
4'he: SEG <= 8'b10011110;
4'hf: SEG <= 8'b10001110;
endcase
end
endmodule | module display_module_async
(
input wire [3:0] SEG_VAL,
output reg [7:0] SEG
); |
always @ (*) begin
case (SEG_VAL)
4'h0: SEG <= 8'b11111100;
4'h1: SEG <= 8'b01100000;
4'h2: SEG <= 8'b11011010;
4'h3: SEG <= 8'b11110010;
4'h4: SEG <= 8'b01100110;
4'h5: SEG <= 8'b10110110;
4'h6: SEG <= 8'b10111110;
4'h7: SEG <= 8'b11100000;
4'h8: SEG <= 8'b11111110;
4'h9: SEG <= 8'b11110110;
4'ha: SEG <= 8'b11101110;
4'hb: SEG <= 8'b00111110;
4'hc: SEG <= 8'b00011010;
4'hd: SEG <= 8'b01111010;
4'he: SEG <= 8'b10011110;
4'hf: SEG <= 8'b10001110;
endcase
end
endmodule | 10 |
137,975 | data/full_repos/permissive/81548712/fpga/mu500rx/fpga_top.v | 81,548,712 | fpga_top.v | v | 151 | 63 | [] | [] | [] | [(1, 150)] | null | null | 1: b"%Error: data/full_repos/permissive/81548712/fpga/mu500rx/fpga_top.v:59: Cannot find file containing module: 'me_top'\nme_top\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/81548712/fpga/mu500rx,data/full_repos/permissive/81548712/me_top\n data/full_repos/permissive/81548712/fpga/mu500rx,data/full_repos/permissive/81548712/me_top.v\n data/full_repos/permissive/81548712/fpga/mu500rx,data/full_repos/permissive/81548712/me_top.sv\n me_top\n me_top.v\n me_top.sv\n obj_dir/me_top\n obj_dir/me_top.v\n obj_dir/me_top.sv\n%Error: data/full_repos/permissive/81548712/fpga/mu500rx/fpga_top.v:80: Cannot find file containing module: 'memory_single_port'\nmemory_single_port\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81548712/fpga/mu500rx/fpga_top.v:93: Cannot find file containing module: 'memory_single_port'\nmemory_single_port\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81548712/fpga/mu500rx/fpga_top.v:118: Cannot find file containing module: 'displayIK_7seg_16'\ndisplayIK_7seg_16\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 301,545 | module | module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL_IK
);
parameter TB_LENGTH = 16;
parameter SW_LENGTH = 64;
parameter PE_OUT_WIDTH = 8;
parameter MEMORY_SW = "../memory_sw.mif";
parameter MEMORY_TB = "../memory_tb.mif";
localparam ADDR_SW = $clog2(SW_LENGTH**2);
localparam ADDR_TB = $clog2(TB_LENGTH**2);
localparam CNT_WIDTH = $clog2((SW_LENGTH-TB_LENGTH+1)**2);
localparam SAD_WIDTH = $clog2(TB_LENGTH**2) + PE_OUT_WIDTH;
reg req;
wire [SAD_WIDTH-1:0] min_sad;
wire [CNT_WIDTH-1:0] min_mvec;
wire ack;
wire [7:0] pel_sw;
wire [7:0] pel_tb;
wire [ADDR_SW-1:0] addr_sw;
wire [ADDR_TB-1:0] addr_tb;
reg [1:0] ff_sw4 = 0;
reg [1:0] ff_sw5 = 0;
always @(posedge clk) begin
ff_sw4 <= {ff_sw4[0], SW4N};
ff_sw5 <= {ff_sw5[0], SW5N};
end
wire tri_sw4 = (ff_sw4 == 2'b10);
wire tri_sw5 = (ff_sw5 == 2'b10);
always @(posedge clk or negedge RSTN) begin
if(~RSTN)
req <= 0;
else if(tri_sw4)
req <= 1;
else if(tri_sw5)
req <= 0;
end
me_top
#(
.TB_LENGTH ( TB_LENGTH ),
.SW_LENGTH ( SW_LENGTH ),
.PE_OUT_WIDTH ( PE_OUT_WIDTH )
) _me_top
(
.rst_n ( RSTN ),
.clk ( clk ),
.req ( req ),
.min_sad ( min_sad ),
.min_mvec ( min_mvec ),
.ack ( ack ),
.pel_sw ( pel_sw ),
.pel_tb ( pel_tb ),
.addr_sw ( addr_sw ),
.addr_tb ( addr_tb )
);
memory_single_port
#(.DWIDTH ( 8 ),
.AWIDTH ( ADDR_SW ),
.CONTENT ( MEMORY_SW ) )
_memory_sw
(
.clock ( clk ),
.wren ( 1'b0 ),
.address ( addr_sw ),
.data ( 8'd0 ),
.q ( pel_sw )
);
memory_single_port
#(.DWIDTH ( 8 ),
.AWIDTH ( ADDR_TB ),
.CONTENT ( MEMORY_TB ) )
_memory_tb
(
.clock ( clk ),
.wren ( 1'b0 ),
.address ( addr_tb ),
.data ( 8'd0 ),
.q ( pel_tb )
);
displayIK_7seg_16
_displayIK_7seg_16
(
.RSTN ( RSTN ),
.CLK ( clk_sys ),
.data0 ( {3'h0, clk, 3'h0, RSTN, 8'h00} ),
.data1 ( {3'h0, SW4N, 3'h0, SW5N, 3'h0, req, 3'h0, ack} ),
.data2 ( 0 ),
.data3 ( 0 ),
.data4 ( min_sad ),
.data5 ( min_mvec ),
.data6 ( 0 ),
.data7 ( 0 ),
.data8 ( pel_sw ),
.data9 ( pel_tb ),
.data10 ( 0 ),
.data11 ( 0 ),
.data12 ( 0 ),
.data13 ( 0 ),
.data14 ( 0 ),
.data15 ( 0 ),
.SEG_A ( SEG_A ),
.SEG_B ( SEG_B ),
.SEG_C ( SEG_C ),
.SEG_D ( SEG_D ),
.SEG_E ( SEG_E ),
.SEG_F ( SEG_F ),
.SEG_G ( SEG_G ),
.SEG_H ( SEG_H ),
.SEG_SEL ( SEG_SEL_IK )
);
endmodule | module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL_IK
); |
parameter TB_LENGTH = 16;
parameter SW_LENGTH = 64;
parameter PE_OUT_WIDTH = 8;
parameter MEMORY_SW = "../memory_sw.mif";
parameter MEMORY_TB = "../memory_tb.mif";
localparam ADDR_SW = $clog2(SW_LENGTH**2);
localparam ADDR_TB = $clog2(TB_LENGTH**2);
localparam CNT_WIDTH = $clog2((SW_LENGTH-TB_LENGTH+1)**2);
localparam SAD_WIDTH = $clog2(TB_LENGTH**2) + PE_OUT_WIDTH;
reg req;
wire [SAD_WIDTH-1:0] min_sad;
wire [CNT_WIDTH-1:0] min_mvec;
wire ack;
wire [7:0] pel_sw;
wire [7:0] pel_tb;
wire [ADDR_SW-1:0] addr_sw;
wire [ADDR_TB-1:0] addr_tb;
reg [1:0] ff_sw4 = 0;
reg [1:0] ff_sw5 = 0;
always @(posedge clk) begin
ff_sw4 <= {ff_sw4[0], SW4N};
ff_sw5 <= {ff_sw5[0], SW5N};
end
wire tri_sw4 = (ff_sw4 == 2'b10);
wire tri_sw5 = (ff_sw5 == 2'b10);
always @(posedge clk or negedge RSTN) begin
if(~RSTN)
req <= 0;
else if(tri_sw4)
req <= 1;
else if(tri_sw5)
req <= 0;
end
me_top
#(
.TB_LENGTH ( TB_LENGTH ),
.SW_LENGTH ( SW_LENGTH ),
.PE_OUT_WIDTH ( PE_OUT_WIDTH )
) _me_top
(
.rst_n ( RSTN ),
.clk ( clk ),
.req ( req ),
.min_sad ( min_sad ),
.min_mvec ( min_mvec ),
.ack ( ack ),
.pel_sw ( pel_sw ),
.pel_tb ( pel_tb ),
.addr_sw ( addr_sw ),
.addr_tb ( addr_tb )
);
memory_single_port
#(.DWIDTH ( 8 ),
.AWIDTH ( ADDR_SW ),
.CONTENT ( MEMORY_SW ) )
_memory_sw
(
.clock ( clk ),
.wren ( 1'b0 ),
.address ( addr_sw ),
.data ( 8'd0 ),
.q ( pel_sw )
);
memory_single_port
#(.DWIDTH ( 8 ),
.AWIDTH ( ADDR_TB ),
.CONTENT ( MEMORY_TB ) )
_memory_tb
(
.clock ( clk ),
.wren ( 1'b0 ),
.address ( addr_tb ),
.data ( 8'd0 ),
.q ( pel_tb )
);
displayIK_7seg_16
_displayIK_7seg_16
(
.RSTN ( RSTN ),
.CLK ( clk_sys ),
.data0 ( {3'h0, clk, 3'h0, RSTN, 8'h00} ),
.data1 ( {3'h0, SW4N, 3'h0, SW5N, 3'h0, req, 3'h0, ack} ),
.data2 ( 0 ),
.data3 ( 0 ),
.data4 ( min_sad ),
.data5 ( min_mvec ),
.data6 ( 0 ),
.data7 ( 0 ),
.data8 ( pel_sw ),
.data9 ( pel_tb ),
.data10 ( 0 ),
.data11 ( 0 ),
.data12 ( 0 ),
.data13 ( 0 ),
.data14 ( 0 ),
.data15 ( 0 ),
.SEG_A ( SEG_A ),
.SEG_B ( SEG_B ),
.SEG_C ( SEG_C ),
.SEG_D ( SEG_D ),
.SEG_E ( SEG_E ),
.SEG_F ( SEG_F ),
.SEG_G ( SEG_G ),
.SEG_H ( SEG_H ),
.SEG_SEL ( SEG_SEL_IK )
);
endmodule | 10 |
137,979 | data/full_repos/permissive/81548712/rtl/pe_line.v | 81,548,712 | pe_line.v | v | 53 | 45 | [] | [] | [] | null | None: at end of input | null | 1: b"%Error: data/full_repos/permissive/81548712/rtl/pe_line.v:29: Cannot find file containing module: 'pe'\n pe _pe\n ^~\n ... Looked in:\n data/full_repos/permissive/81548712/rtl,data/full_repos/permissive/81548712/pe\n data/full_repos/permissive/81548712/rtl,data/full_repos/permissive/81548712/pe.v\n data/full_repos/permissive/81548712/rtl,data/full_repos/permissive/81548712/pe.sv\n pe\n pe.v\n pe.sv\n obj_dir/pe\n obj_dir/pe.v\n obj_dir/pe.sv\n%Error: Exiting due to 1 error(s)\n" | 301,552 | module | module pe_line
#(
parameter ARRAY_SIZE = 16
) (
input wire rst_n,
input wire clk,
input wire en_sw,
input wire en_tb,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output wire [7:0] nxt_sw,
output wire [7:0] nxt_tb,
output wire [ARRAY_SIZE*8-1:0] ad
);
wire [7:0] tmp_sw [0:ARRAY_SIZE];
wire [7:0] tmp_tb [0:ARRAY_SIZE];
wire [7:0] w_ad [0:ARRAY_SIZE-1];
assign tmp_sw[0] = pel_sw;
assign tmp_tb[0] = pel_tb;
assign nxt_sw = tmp_sw[ARRAY_SIZE];
assign nxt_tb = tmp_tb[ARRAY_SIZE];
genvar i;
generate
for(i=0; i<ARRAY_SIZE; i=i+1) begin :PE_LINE
pe _pe
(
.rst_n ( rst_n ),
.clk ( clk ),
.en_sw ( en_sw ),
.en_tb ( en_tb ),
.pel_sw ( tmp_sw[i] ),
.pel_tb ( tmp_tb[i] ),
.nxt_sw ( tmp_sw[i+1] ),
.nxt_tb ( tmp_tb[i+1] ),
.ad ( w_ad[i] )
);
end
endgenerate
generate
for (i=0; i<ARRAY_SIZE; i=i+1) begin: PACK
assign ad[8*(i+1)-1:8*i] = w_ad[i];
end
endgenerate
endmodule | module pe_line
#(
parameter ARRAY_SIZE = 16
) (
input wire rst_n,
input wire clk,
input wire en_sw,
input wire en_tb,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output wire [7:0] nxt_sw,
output wire [7:0] nxt_tb,
output wire [ARRAY_SIZE*8-1:0] ad
); |
wire [7:0] tmp_sw [0:ARRAY_SIZE];
wire [7:0] tmp_tb [0:ARRAY_SIZE];
wire [7:0] w_ad [0:ARRAY_SIZE-1];
assign tmp_sw[0] = pel_sw;
assign tmp_tb[0] = pel_tb;
assign nxt_sw = tmp_sw[ARRAY_SIZE];
assign nxt_tb = tmp_tb[ARRAY_SIZE];
genvar i;
generate
for(i=0; i<ARRAY_SIZE; i=i+1) begin :PE_LINE
pe _pe
(
.rst_n ( rst_n ),
.clk ( clk ),
.en_sw ( en_sw ),
.en_tb ( en_tb ),
.pel_sw ( tmp_sw[i] ),
.pel_tb ( tmp_tb[i] ),
.nxt_sw ( tmp_sw[i+1] ),
.nxt_tb ( tmp_tb[i+1] ),
.ad ( w_ad[i] )
);
end
endgenerate
generate
for (i=0; i<ARRAY_SIZE; i=i+1) begin: PACK
assign ad[8*(i+1)-1:8*i] = w_ad[i];
end
endgenerate
endmodule | 10 |
137,981 | data/full_repos/permissive/81549247/rtl/me_top.v | 81,549,247 | me_top.v | v | 87 | 79 | [] | [] | [] | [(1, 86)] | null | null | 1: b"%Error: data/full_repos/permissive/81549247/rtl/me_top.v:34: Cannot find file containing module: 'control_unit'\ncontrol_unit\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81549247/rtl,data/full_repos/permissive/81549247/control_unit\n data/full_repos/permissive/81549247/rtl,data/full_repos/permissive/81549247/control_unit.v\n data/full_repos/permissive/81549247/rtl,data/full_repos/permissive/81549247/control_unit.sv\n control_unit\n control_unit.v\n control_unit.sv\n obj_dir/control_unit\n obj_dir/control_unit.v\n obj_dir/control_unit.sv\n%Error: data/full_repos/permissive/81549247/rtl/me_top.v:56: Cannot find file containing module: 'addr_gen'\naddr_gen\n^~~~~~~~\n%Error: data/full_repos/permissive/81549247/rtl/me_top.v:70: Cannot find file containing module: 'pe_array'\npe_array\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 301,564 | module | module me_top
#(
parameter TB_LENGTH = 16,
parameter SW_LENGTH = 64,
parameter PE_OUT_WIDTH = 8
) (
input wire rst_n,
input wire clk,
input wire req,
input wire [SAD_WIDTH-1:0] threshold,
output wire [SAD_WIDTH-1:0] min_sad,
output wire [CNT_WIDTH-1:0] min_mvec,
output wire ack,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output wire [ADDR_SW-1:0] addr_sw,
output wire [ADDR_TB-1:0] addr_tb
);
localparam ADDR_SW = $clog2(SW_LENGTH**2);
localparam ADDR_TB = $clog2(TB_LENGTH**2);
localparam CNT_WIDTH = $clog2((SW_LENGTH-TB_LENGTH+1)**2);
localparam SAD_WIDTH = $clog2(TB_LENGTH**2) + PE_OUT_WIDTH;
wire clr;
wire en_addr_sw;
wire en_addr_tb;
wire en_pearray_sw;
wire en_pearray_tb;
wire [SAD_WIDTH-1:0] sad;
control_unit
#(.SAD_WIDTH ( SAD_WIDTH ),
.CNT_WIDTH ( CNT_WIDTH ),
.TB_LENGTH ( TB_LENGTH ),
.SW_LENGTH ( SW_LENGTH ) )
_control_unit
(
.rst_n ( rst_n ),
.clk ( clk ),
.req ( req ),
.threshold ( threshold ),
.sad ( sad ),
.clr ( clr ),
.en_addr_sw ( en_addr_sw ),
.en_addr_tb ( en_addr_tb ),
.en_pearray_sw ( en_pearray_sw ),
.en_pearray_tb ( en_pearray_tb ),
.min_sad ( min_sad ),
.min_mvec ( min_mvec ),
.ack ( ack )
);
addr_gen
#(.ADDR_SW ( ADDR_SW ),
.ADDR_TB ( ADDR_TB ) )
_addr_gen
(
.rst_n ( rst_n ),
.clk ( clk ),
.clr ( clr ),
.en_sw ( en_addr_sw ),
.en_tb ( en_addr_tb ),
.addr_sw ( addr_sw ),
.addr_tb ( addr_tb )
);
pe_array
#(
.TB_LENGTH ( TB_LENGTH ),
.SW_LENGTH ( SW_LENGTH ),
.SAD_WIDTH ( SAD_WIDTH ) )
_pe_array
(
.rst_n ( rst_n ),
.clk ( clk ),
.en_sw ( en_pearray_sw ),
.en_tb ( en_pearray_tb ),
.pel_sw ( pel_sw ),
.pel_tb ( pel_tb ),
.sad ( sad )
);
endmodule | module me_top
#(
parameter TB_LENGTH = 16,
parameter SW_LENGTH = 64,
parameter PE_OUT_WIDTH = 8
) (
input wire rst_n,
input wire clk,
input wire req,
input wire [SAD_WIDTH-1:0] threshold,
output wire [SAD_WIDTH-1:0] min_sad,
output wire [CNT_WIDTH-1:0] min_mvec,
output wire ack,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output wire [ADDR_SW-1:0] addr_sw,
output wire [ADDR_TB-1:0] addr_tb
); |
localparam ADDR_SW = $clog2(SW_LENGTH**2);
localparam ADDR_TB = $clog2(TB_LENGTH**2);
localparam CNT_WIDTH = $clog2((SW_LENGTH-TB_LENGTH+1)**2);
localparam SAD_WIDTH = $clog2(TB_LENGTH**2) + PE_OUT_WIDTH;
wire clr;
wire en_addr_sw;
wire en_addr_tb;
wire en_pearray_sw;
wire en_pearray_tb;
wire [SAD_WIDTH-1:0] sad;
control_unit
#(.SAD_WIDTH ( SAD_WIDTH ),
.CNT_WIDTH ( CNT_WIDTH ),
.TB_LENGTH ( TB_LENGTH ),
.SW_LENGTH ( SW_LENGTH ) )
_control_unit
(
.rst_n ( rst_n ),
.clk ( clk ),
.req ( req ),
.threshold ( threshold ),
.sad ( sad ),
.clr ( clr ),
.en_addr_sw ( en_addr_sw ),
.en_addr_tb ( en_addr_tb ),
.en_pearray_sw ( en_pearray_sw ),
.en_pearray_tb ( en_pearray_tb ),
.min_sad ( min_sad ),
.min_mvec ( min_mvec ),
.ack ( ack )
);
addr_gen
#(.ADDR_SW ( ADDR_SW ),
.ADDR_TB ( ADDR_TB ) )
_addr_gen
(
.rst_n ( rst_n ),
.clk ( clk ),
.clr ( clr ),
.en_sw ( en_addr_sw ),
.en_tb ( en_addr_tb ),
.addr_sw ( addr_sw ),
.addr_tb ( addr_tb )
);
pe_array
#(
.TB_LENGTH ( TB_LENGTH ),
.SW_LENGTH ( SW_LENGTH ),
.SAD_WIDTH ( SAD_WIDTH ) )
_pe_array
(
.rst_n ( rst_n ),
.clk ( clk ),
.en_sw ( en_pearray_sw ),
.en_tb ( en_pearray_tb ),
.pel_sw ( pel_sw ),
.pel_tb ( pel_tb ),
.sad ( sad )
);
endmodule | 2 |
137,988 | data/full_repos/permissive/81549979/rtl/control_double.v | 81,549,979 | control_double.v | v | 298 | 75 | [] | [] | [] | [(1, 297)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:72: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n default : state_main <= \'dx;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:104: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n state_addr_sw <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:105: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n cnt_addr_sw <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:138: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n state_addr_tb <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:139: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n cnt_addr_tb <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:172: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n state_pearray_sw <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:173: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n cnt_pearray_sw <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:225: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n state_valid <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:226: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n cnt_dummy <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:227: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n cnt_w <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:228: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n cnt_h <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:260: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n state_done <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:261: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n cnt_done <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:290: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n min_sad <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_double.v:291: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_double\n min_mvec <= \'dx;\n ^~\n%Error: Exiting due to 15 warning(s)\n' | 301,579 | module | module control_double
(
input wire rst_n,
input wire clk,
input wire req,
input wire [15:0] sad,
output wire clr,
output wire en_addr_sw,
output wire en_addr_tb,
output wire en_paarray_sw,
output reg en_paarray_tb,
output reg [15:0] min_sad,
output reg [9:0] min_mvec,
output wire ack
);
localparam TB_LENGTH = 8;
localparam SW_LENGTH = 32;
localparam INIT = 4'b0000;
localparam WAIT_REQ = 4'b0001;
localparam RUNNING = 4'b0010;
localparam WAIT_REQ_FALL = 4'b0011;
localparam WAIT_RUN = 4'b0100;
localparam ACTIVE = 4'b0101;
localparam DONE = 4'b0110;
localparam WAIT_DUMMY_CYCLE = 4'b0111;
localparam WAIT_SRCH_END = 4'b1000;
localparam DONE_CNT = 4'b1001;
localparam DONE_ACTIVE = 4'b1010;
localparam CNT_ADDR_SW_END = SW_LENGTH**2-2;
localparam CNT_ADDR_TB_END = TB_LENGTH**2-1;
localparam CNT_PEARRAY_SW_END = SW_LENGTH**2+(SW_LENGTH-TB_LENGTH-1);
localparam CNT_DUMMY_CYCLE = SW_LENGTH-TB_LENGTH+7;
localparam VEC_WIDTH = $clog2(SW_LENGTH+1);
localparam MAX_SAD = 16'hFFFF;
reg [3:0] state_main;
reg [3:0] state_addr_sw;
reg [12:0] cnt_addr_sw;
reg [3:0] state_addr_tb;
reg [8:0] cnt_addr_tb;
reg [3:0] state_pearray_sw;
reg [12:0] cnt_pearray_sw;
reg [3:0] state_valid;
reg [10:0] cnt_dummy;
reg [5:0] cnt_w;
reg [5:0] cnt_h;
reg [3:0] state_done;
reg cnt_done;
assign ack = (state_main == WAIT_REQ_FALL);
assign clr = (state_main == WAIT_REQ);
assign en_addr_sw = (cnt_addr_sw != 0);
assign en_addr_tb = (cnt_addr_tb != 0);
assign en_paarray_sw = (cnt_pearray_sw != 0);
wire valid = (cnt_w > (TB_LENGTH-2)) && (cnt_h > (TB_LENGTH-2));
wire done = (state_done == DONE_ACTIVE);
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state_main <= INIT;
end else begin
case(state_main)
INIT : state_main <= #1 WAIT_REQ;
WAIT_REQ : if( req) state_main <= #1 RUNNING;
RUNNING : if(done) state_main <= #1 WAIT_REQ_FALL;
WAIT_REQ_FALL : if(~req) state_main <= #1 WAIT_REQ;
default : state_main <= 'dx;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_sw <= INIT;
cnt_addr_sw <= 0;
end else begin
case(state_addr_sw)
INIT: begin
state_addr_sw <= #1 WAIT_RUN;
cnt_addr_sw <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_sw <= #1 ACTIVE;
cnt_addr_sw <= #1 0;
end
ACTIVE: begin
if(cnt_addr_sw==CNT_ADDR_SW_END)
state_addr_sw <= #1 DONE;
cnt_addr_sw <= #1 cnt_addr_sw + 1;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_sw <= #1 WAIT_RUN;
cnt_addr_sw <= #1 0;
end
default: begin
state_addr_sw <= 'dx;
cnt_addr_sw <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_tb <= INIT;
cnt_addr_tb <= 0;
end else begin
case(state_addr_tb)
INIT: begin
state_addr_tb <= #1 WAIT_RUN;
cnt_addr_tb <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_tb <= #1 ACTIVE;
cnt_addr_tb <= #1 0;
end
ACTIVE: begin
if(cnt_addr_tb==CNT_ADDR_TB_END)
state_addr_tb <= #1 DONE;
cnt_addr_tb <= #1 cnt_addr_tb + 1;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_tb <= #1 WAIT_RUN;
cnt_addr_tb <= #1 0;
end
default: begin
state_addr_tb <= 'dx;
cnt_addr_tb <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_pearray_sw <= INIT;
cnt_pearray_sw <= 0;
end else begin
case(state_pearray_sw)
INIT: begin
state_pearray_sw <= #1 WAIT_RUN;
cnt_pearray_sw <= #1 0;
end
WAIT_RUN: begin
if(state_addr_sw==ACTIVE)
state_pearray_sw <= #1 ACTIVE;
cnt_pearray_sw <= #1 0;
end
ACTIVE: begin
if(cnt_pearray_sw==CNT_PEARRAY_SW_END)
state_pearray_sw <= #1 DONE;
cnt_pearray_sw <= #1 cnt_pearray_sw + 1;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_pearray_sw <= #1 WAIT_RUN;
cnt_pearray_sw <= #1 0;
end
default: begin
state_pearray_sw <= 'dx;
cnt_pearray_sw <= 'dx;
end
endcase
end
end
always @(posedge clk)
en_paarray_tb <= en_addr_tb;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_valid <= INIT;
cnt_dummy <= 0;
cnt_w <= 0;
cnt_h <= 0;
end else begin
case(state_valid)
INIT: begin
state_valid <= #1 WAIT_RUN;
cnt_dummy <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_valid <= #1 WAIT_DUMMY_CYCLE;
cnt_dummy <= #1 0;
end
WAIT_DUMMY_CYCLE: begin
if(cnt_dummy==CNT_DUMMY_CYCLE)
state_valid <= #1 ACTIVE;
cnt_dummy <= #1 cnt_dummy + 1;
end
ACTIVE: begin
if((cnt_w==(SW_LENGTH-1))&&(cnt_h==(SW_LENGTH-1)))
state_valid <= #1 DONE;
cnt_dummy <= #1 0;
if(cnt_h < (SW_LENGTH-1))
cnt_h <= #1 cnt_h + 1;
else begin
cnt_h <= #1 0;
cnt_w <= #1 cnt_w + 1;
end
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_valid <= #1 WAIT_RUN;
cnt_dummy <= #1 0;
cnt_w <= #1 0;
cnt_h <= #1 0;
end
default: begin
state_valid <= 'dx;
cnt_dummy <= 'dx;
cnt_w <= 'dx;
cnt_h <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)begin
state_done <= INIT;
cnt_done <= 0;
end else begin
case (state_done)
INIT: begin
state_done <= #1 WAIT_SRCH_END;
cnt_done <= #1 0;
end
WAIT_SRCH_END: begin
if(cnt_w==SW_LENGTH)
state_done <= #1 DONE_CNT;
cnt_done <= #1 0;
end
DONE_CNT: begin
if(cnt_done==1'b1)
state_done <= #1 DONE_ACTIVE;
cnt_done <= #1 cnt_done + 1;
end
DONE_ACTIVE: begin
state_done <= #1 WAIT_SRCH_END;
cnt_done <= #1 0;
end
default: begin
state_done <= 'dx;
cnt_done <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_sad <= MAX_SAD;
min_mvec <= 0;
end else begin
case(state_main)
INIT: begin
min_sad <= #1 MAX_SAD;
min_mvec <= #1 0;
end
WAIT_REQ: begin
min_sad <= #1 MAX_SAD;
min_mvec <= #1 0;
end
RUNNING: begin
if(valid && (min_sad > sad)) begin
min_sad <= #1 sad;
min_mvec <= #1 {cnt_w[4:0], cnt_h[4:0]};
end
end
WAIT_REQ_FALL: ;
default:begin
min_sad <= 'dx;
min_mvec <= 'dx;
end
endcase
end
end
endmodule | module control_double
(
input wire rst_n,
input wire clk,
input wire req,
input wire [15:0] sad,
output wire clr,
output wire en_addr_sw,
output wire en_addr_tb,
output wire en_paarray_sw,
output reg en_paarray_tb,
output reg [15:0] min_sad,
output reg [9:0] min_mvec,
output wire ack
); |
localparam TB_LENGTH = 8;
localparam SW_LENGTH = 32;
localparam INIT = 4'b0000;
localparam WAIT_REQ = 4'b0001;
localparam RUNNING = 4'b0010;
localparam WAIT_REQ_FALL = 4'b0011;
localparam WAIT_RUN = 4'b0100;
localparam ACTIVE = 4'b0101;
localparam DONE = 4'b0110;
localparam WAIT_DUMMY_CYCLE = 4'b0111;
localparam WAIT_SRCH_END = 4'b1000;
localparam DONE_CNT = 4'b1001;
localparam DONE_ACTIVE = 4'b1010;
localparam CNT_ADDR_SW_END = SW_LENGTH**2-2;
localparam CNT_ADDR_TB_END = TB_LENGTH**2-1;
localparam CNT_PEARRAY_SW_END = SW_LENGTH**2+(SW_LENGTH-TB_LENGTH-1);
localparam CNT_DUMMY_CYCLE = SW_LENGTH-TB_LENGTH+7;
localparam VEC_WIDTH = $clog2(SW_LENGTH+1);
localparam MAX_SAD = 16'hFFFF;
reg [3:0] state_main;
reg [3:0] state_addr_sw;
reg [12:0] cnt_addr_sw;
reg [3:0] state_addr_tb;
reg [8:0] cnt_addr_tb;
reg [3:0] state_pearray_sw;
reg [12:0] cnt_pearray_sw;
reg [3:0] state_valid;
reg [10:0] cnt_dummy;
reg [5:0] cnt_w;
reg [5:0] cnt_h;
reg [3:0] state_done;
reg cnt_done;
assign ack = (state_main == WAIT_REQ_FALL);
assign clr = (state_main == WAIT_REQ);
assign en_addr_sw = (cnt_addr_sw != 0);
assign en_addr_tb = (cnt_addr_tb != 0);
assign en_paarray_sw = (cnt_pearray_sw != 0);
wire valid = (cnt_w > (TB_LENGTH-2)) && (cnt_h > (TB_LENGTH-2));
wire done = (state_done == DONE_ACTIVE);
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state_main <= INIT;
end else begin
case(state_main)
INIT : state_main <= #1 WAIT_REQ;
WAIT_REQ : if( req) state_main <= #1 RUNNING;
RUNNING : if(done) state_main <= #1 WAIT_REQ_FALL;
WAIT_REQ_FALL : if(~req) state_main <= #1 WAIT_REQ;
default : state_main <= 'dx;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_sw <= INIT;
cnt_addr_sw <= 0;
end else begin
case(state_addr_sw)
INIT: begin
state_addr_sw <= #1 WAIT_RUN;
cnt_addr_sw <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_sw <= #1 ACTIVE;
cnt_addr_sw <= #1 0;
end
ACTIVE: begin
if(cnt_addr_sw==CNT_ADDR_SW_END)
state_addr_sw <= #1 DONE;
cnt_addr_sw <= #1 cnt_addr_sw + 1;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_sw <= #1 WAIT_RUN;
cnt_addr_sw <= #1 0;
end
default: begin
state_addr_sw <= 'dx;
cnt_addr_sw <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_tb <= INIT;
cnt_addr_tb <= 0;
end else begin
case(state_addr_tb)
INIT: begin
state_addr_tb <= #1 WAIT_RUN;
cnt_addr_tb <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_tb <= #1 ACTIVE;
cnt_addr_tb <= #1 0;
end
ACTIVE: begin
if(cnt_addr_tb==CNT_ADDR_TB_END)
state_addr_tb <= #1 DONE;
cnt_addr_tb <= #1 cnt_addr_tb + 1;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_tb <= #1 WAIT_RUN;
cnt_addr_tb <= #1 0;
end
default: begin
state_addr_tb <= 'dx;
cnt_addr_tb <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_pearray_sw <= INIT;
cnt_pearray_sw <= 0;
end else begin
case(state_pearray_sw)
INIT: begin
state_pearray_sw <= #1 WAIT_RUN;
cnt_pearray_sw <= #1 0;
end
WAIT_RUN: begin
if(state_addr_sw==ACTIVE)
state_pearray_sw <= #1 ACTIVE;
cnt_pearray_sw <= #1 0;
end
ACTIVE: begin
if(cnt_pearray_sw==CNT_PEARRAY_SW_END)
state_pearray_sw <= #1 DONE;
cnt_pearray_sw <= #1 cnt_pearray_sw + 1;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_pearray_sw <= #1 WAIT_RUN;
cnt_pearray_sw <= #1 0;
end
default: begin
state_pearray_sw <= 'dx;
cnt_pearray_sw <= 'dx;
end
endcase
end
end
always @(posedge clk)
en_paarray_tb <= en_addr_tb;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_valid <= INIT;
cnt_dummy <= 0;
cnt_w <= 0;
cnt_h <= 0;
end else begin
case(state_valid)
INIT: begin
state_valid <= #1 WAIT_RUN;
cnt_dummy <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_valid <= #1 WAIT_DUMMY_CYCLE;
cnt_dummy <= #1 0;
end
WAIT_DUMMY_CYCLE: begin
if(cnt_dummy==CNT_DUMMY_CYCLE)
state_valid <= #1 ACTIVE;
cnt_dummy <= #1 cnt_dummy + 1;
end
ACTIVE: begin
if((cnt_w==(SW_LENGTH-1))&&(cnt_h==(SW_LENGTH-1)))
state_valid <= #1 DONE;
cnt_dummy <= #1 0;
if(cnt_h < (SW_LENGTH-1))
cnt_h <= #1 cnt_h + 1;
else begin
cnt_h <= #1 0;
cnt_w <= #1 cnt_w + 1;
end
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_valid <= #1 WAIT_RUN;
cnt_dummy <= #1 0;
cnt_w <= #1 0;
cnt_h <= #1 0;
end
default: begin
state_valid <= 'dx;
cnt_dummy <= 'dx;
cnt_w <= 'dx;
cnt_h <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)begin
state_done <= INIT;
cnt_done <= 0;
end else begin
case (state_done)
INIT: begin
state_done <= #1 WAIT_SRCH_END;
cnt_done <= #1 0;
end
WAIT_SRCH_END: begin
if(cnt_w==SW_LENGTH)
state_done <= #1 DONE_CNT;
cnt_done <= #1 0;
end
DONE_CNT: begin
if(cnt_done==1'b1)
state_done <= #1 DONE_ACTIVE;
cnt_done <= #1 cnt_done + 1;
end
DONE_ACTIVE: begin
state_done <= #1 WAIT_SRCH_END;
cnt_done <= #1 0;
end
default: begin
state_done <= 'dx;
cnt_done <= 'dx;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_sad <= MAX_SAD;
min_mvec <= 0;
end else begin
case(state_main)
INIT: begin
min_sad <= #1 MAX_SAD;
min_mvec <= #1 0;
end
WAIT_REQ: begin
min_sad <= #1 MAX_SAD;
min_mvec <= #1 0;
end
RUNNING: begin
if(valid && (min_sad > sad)) begin
min_sad <= #1 sad;
min_mvec <= #1 {cnt_w[4:0], cnt_h[4:0]};
end
end
WAIT_REQ_FALL: ;
default:begin
min_sad <= 'dx;
min_mvec <= 'dx;
end
endcase
end
end
endmodule | 2 |
137,989 | data/full_repos/permissive/81549979/rtl/control_integer.v | 81,549,979 | control_integer.v | v | 228 | 63 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:54: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n default : state_main <= #1 \'dx;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:82: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n state_addr_sw <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:121: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n state_addr_tb <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:122: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n en_addr_tb <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:158: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n cnt_h <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:159: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n cnt_w <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:218: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n state_done <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:219: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n cnt_done <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:220: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n min_sad <= \'dx;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_integer.v:221: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_integer\n min_diff <= \'dx;\n ^~\n%Error: Exiting due to 10 warning(s)\n' | 301,580 | module | module control_integer
(
input wire rst_n,
input wire clk,
input wire req,
input wire [15:0] sad,
input wire [3:0] vec_diff,
input wire [11:0] init_pos,
output wire clr,
output wire en_addr_sw,
output reg en_addr_tb,
output wire en_sadarray_sw,
output wire en_sadarray_tb,
output wire [11:0] init_mvec,
output reg [15:0] min_sad,
output reg [3:0] min_diff,
output wire ack
);
localparam SW_LENGTH = 18;
localparam TB_LENGTH = 16;
localparam INIT = 4'b0000;
localparam WAIT_REQ = 4'b0001;
localparam RUNNING = 4'b0010;
localparam WAIT_REQ_FALL = 4'b0011;
localparam WAIT_RUN = 4'b0100;
localparam ACTIVE = 4'b0101;
localparam DISABLE = 4'b0110;
localparam DONE = 4'b0111;
localparam WAIT_SW_DONE = 4'b1000;
localparam WAIT_DUMMY = 4'b1001;
localparam UPDATE_MIN = 4'b1010;
localparam MAX_SAD = 16'hFFFF;
reg [3:0] state_main;
assign ack = (state_main==WAIT_REQ_FALL);
assign clr = (state_main==WAIT_REQ);
assign en_addr_sw = (state_addr_sw==ACTIVE);
wire done = (state_done==DONE);
assign init_mvec = init_pos;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state_main <= INIT;
end else begin
case(state_main)
INIT : state_main <= #1 WAIT_REQ;
WAIT_REQ : if( req) state_main <= #1 RUNNING;
RUNNING : if(done) state_main <= #1 WAIT_REQ_FALL;
WAIT_REQ_FALL : if(~req) state_main <= #1 WAIT_REQ;
default : state_main <= #1 'dx;
endcase
end
end
reg [3:0] state_addr_sw;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_sw <= INIT;
end else begin
case(state_addr_sw)
INIT: begin
state_addr_sw <= #1 WAIT_RUN;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_sw <= #1 ACTIVE;
end
ACTIVE: begin
if((cnt_h==2) && (cnt_w==SW_LENGTH))
state_addr_sw <= #1 DONE;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_sw <= #1 WAIT_RUN;
end
default: begin
state_addr_sw <= 'dx;
end
endcase
end
end
reg [3:0] state_addr_tb;
reg tb_addr_dly;
reg tb_addr_dly2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_tb <= INIT;
en_addr_tb <= 0;
end else begin
case(state_addr_tb)
INIT: begin
state_addr_tb <= #1 WAIT_RUN;
en_addr_tb <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_tb <= #1 ACTIVE;
en_addr_tb <= #1 0;
end
ACTIVE: begin
if(cnt_h==(SW_LENGTH-1) && (cnt_w==(SW_LENGTH-1)))
state_addr_tb <= #1 DONE;
if((cnt_h > 1) && (cnt_w > 1))
en_addr_tb <= #1 1;
else
en_addr_tb <= #1 0;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_tb <= WAIT_RUN;
en_addr_tb <= #1 0;
end
default : begin
state_addr_tb <= 'dx;
en_addr_tb <= 'dx;
end
endcase
end
end
reg [6:0] cnt_h;
reg [6:0] cnt_w;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cnt_h <= 0;
cnt_w <= 0;
end else begin
case (state_addr_sw)
INIT: begin
cnt_h <= #1 0;
cnt_w <= #1 0;
end
WAIT_RUN: begin
cnt_h <= #1 0;
cnt_w <= #1 0;
end
ACTIVE: begin
if(cnt_h==(SW_LENGTH-1)) begin
cnt_h <= 0;
cnt_w <= #1 cnt_w + 1;
end else begin
cnt_h <= #1 cnt_h + 1;
end
end
DONE: begin
cnt_h <= #1 0;
cnt_w <= #1 0;
end
default : begin
cnt_h <= 'dx;
cnt_w <= 'dx;
end
endcase
end
end
localparam N_sw=2;
localparam N_tb=2;
reg [N_sw-1:0] sw_dly;
reg [N_tb-1:0] tb_dly;
assign en_sadarray_sw = sw_dly[N_sw-1];
assign en_sadarray_tb = tb_dly[N_tb-1];
always @(posedge clk) begin
sw_dly <= #1 {sw_dly[N_sw-2:0], en_addr_sw};
tb_dly <= #1 {tb_dly[N_tb-2:0], en_addr_tb};
end
reg [3:0] state_done;
reg [1:0] cnt_done;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state_done <= INIT;
cnt_done <= 0;
min_sad <= MAX_SAD;
min_diff <= 4'b0000;
end else begin
case (state_done)
INIT: begin
state_done <= #1 WAIT_SW_DONE;
cnt_done <= #1 0;
min_sad <= #1 MAX_SAD;
min_diff <= #1 4'b0000;
end
WAIT_SW_DONE: begin
if(state_addr_sw==DONE)
state_done <= #1 WAIT_DUMMY;
cnt_done <= #1 0;
min_sad <= #1 MAX_SAD;
min_diff <= #1 4'b0000;
end
WAIT_DUMMY: begin
if(cnt_done==2'd2)
state_done <= #1 UPDATE_MIN;
cnt_done <= #1 cnt_done + 1;
end
UPDATE_MIN: begin
state_done <= #1 DONE;
cnt_done <= #1 0;
min_sad <= #1 sad;
min_diff <= #1 vec_diff;
end
DONE: begin
if(state_main==WAIT_REQ)
state_done <= #1 WAIT_SW_DONE;
cnt_done <= #1 0;
end
default: begin
state_done <= 'dx;
cnt_done <= 'dx;
min_sad <= 'dx;
min_diff <= 'dx;
end
endcase
end
end
endmodule | module control_integer
(
input wire rst_n,
input wire clk,
input wire req,
input wire [15:0] sad,
input wire [3:0] vec_diff,
input wire [11:0] init_pos,
output wire clr,
output wire en_addr_sw,
output reg en_addr_tb,
output wire en_sadarray_sw,
output wire en_sadarray_tb,
output wire [11:0] init_mvec,
output reg [15:0] min_sad,
output reg [3:0] min_diff,
output wire ack
); |
localparam SW_LENGTH = 18;
localparam TB_LENGTH = 16;
localparam INIT = 4'b0000;
localparam WAIT_REQ = 4'b0001;
localparam RUNNING = 4'b0010;
localparam WAIT_REQ_FALL = 4'b0011;
localparam WAIT_RUN = 4'b0100;
localparam ACTIVE = 4'b0101;
localparam DISABLE = 4'b0110;
localparam DONE = 4'b0111;
localparam WAIT_SW_DONE = 4'b1000;
localparam WAIT_DUMMY = 4'b1001;
localparam UPDATE_MIN = 4'b1010;
localparam MAX_SAD = 16'hFFFF;
reg [3:0] state_main;
assign ack = (state_main==WAIT_REQ_FALL);
assign clr = (state_main==WAIT_REQ);
assign en_addr_sw = (state_addr_sw==ACTIVE);
wire done = (state_done==DONE);
assign init_mvec = init_pos;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state_main <= INIT;
end else begin
case(state_main)
INIT : state_main <= #1 WAIT_REQ;
WAIT_REQ : if( req) state_main <= #1 RUNNING;
RUNNING : if(done) state_main <= #1 WAIT_REQ_FALL;
WAIT_REQ_FALL : if(~req) state_main <= #1 WAIT_REQ;
default : state_main <= #1 'dx;
endcase
end
end
reg [3:0] state_addr_sw;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_sw <= INIT;
end else begin
case(state_addr_sw)
INIT: begin
state_addr_sw <= #1 WAIT_RUN;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_sw <= #1 ACTIVE;
end
ACTIVE: begin
if((cnt_h==2) && (cnt_w==SW_LENGTH))
state_addr_sw <= #1 DONE;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_sw <= #1 WAIT_RUN;
end
default: begin
state_addr_sw <= 'dx;
end
endcase
end
end
reg [3:0] state_addr_tb;
reg tb_addr_dly;
reg tb_addr_dly2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_addr_tb <= INIT;
en_addr_tb <= 0;
end else begin
case(state_addr_tb)
INIT: begin
state_addr_tb <= #1 WAIT_RUN;
en_addr_tb <= #1 0;
end
WAIT_RUN: begin
if(state_main==RUNNING)
state_addr_tb <= #1 ACTIVE;
en_addr_tb <= #1 0;
end
ACTIVE: begin
if(cnt_h==(SW_LENGTH-1) && (cnt_w==(SW_LENGTH-1)))
state_addr_tb <= #1 DONE;
if((cnt_h > 1) && (cnt_w > 1))
en_addr_tb <= #1 1;
else
en_addr_tb <= #1 0;
end
DONE: begin
if(state_main==WAIT_REQ_FALL)
state_addr_tb <= WAIT_RUN;
en_addr_tb <= #1 0;
end
default : begin
state_addr_tb <= 'dx;
en_addr_tb <= 'dx;
end
endcase
end
end
reg [6:0] cnt_h;
reg [6:0] cnt_w;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cnt_h <= 0;
cnt_w <= 0;
end else begin
case (state_addr_sw)
INIT: begin
cnt_h <= #1 0;
cnt_w <= #1 0;
end
WAIT_RUN: begin
cnt_h <= #1 0;
cnt_w <= #1 0;
end
ACTIVE: begin
if(cnt_h==(SW_LENGTH-1)) begin
cnt_h <= 0;
cnt_w <= #1 cnt_w + 1;
end else begin
cnt_h <= #1 cnt_h + 1;
end
end
DONE: begin
cnt_h <= #1 0;
cnt_w <= #1 0;
end
default : begin
cnt_h <= 'dx;
cnt_w <= 'dx;
end
endcase
end
end
localparam N_sw=2;
localparam N_tb=2;
reg [N_sw-1:0] sw_dly;
reg [N_tb-1:0] tb_dly;
assign en_sadarray_sw = sw_dly[N_sw-1];
assign en_sadarray_tb = tb_dly[N_tb-1];
always @(posedge clk) begin
sw_dly <= #1 {sw_dly[N_sw-2:0], en_addr_sw};
tb_dly <= #1 {tb_dly[N_tb-2:0], en_addr_tb};
end
reg [3:0] state_done;
reg [1:0] cnt_done;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
state_done <= INIT;
cnt_done <= 0;
min_sad <= MAX_SAD;
min_diff <= 4'b0000;
end else begin
case (state_done)
INIT: begin
state_done <= #1 WAIT_SW_DONE;
cnt_done <= #1 0;
min_sad <= #1 MAX_SAD;
min_diff <= #1 4'b0000;
end
WAIT_SW_DONE: begin
if(state_addr_sw==DONE)
state_done <= #1 WAIT_DUMMY;
cnt_done <= #1 0;
min_sad <= #1 MAX_SAD;
min_diff <= #1 4'b0000;
end
WAIT_DUMMY: begin
if(cnt_done==2'd2)
state_done <= #1 UPDATE_MIN;
cnt_done <= #1 cnt_done + 1;
end
UPDATE_MIN: begin
state_done <= #1 DONE;
cnt_done <= #1 0;
min_sad <= #1 sad;
min_diff <= #1 vec_diff;
end
DONE: begin
if(state_main==WAIT_REQ)
state_done <= #1 WAIT_SW_DONE;
cnt_done <= #1 0;
end
default: begin
state_done <= 'dx;
cnt_done <= 'dx;
min_sad <= 'dx;
min_diff <= 'dx;
end
endcase
end
end
endmodule | 2 |
137,990 | data/full_repos/permissive/81549979/rtl/control_top.v | 81,549,979 | control_top.v | v | 163 | 65 | [] | [] | [] | [(1, 162)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_top.v:122: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_top\n state_main <= \'dx;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 301,581 | module | module control_top
(
input wire rst_n,
input wire clk,
input wire req,
output reg ack,
output reg [11:0] min_mvec,
output reg [15:0] min_sad,
output reg req_d,
input wire [9:0] min_mvec_d,
input wire ack_d,
output reg req_i,
output reg [11:0] init_pos_i ,
input wire [15:0] min_sad_i,
input wire [3:0] min_diff_i,
input wire ack_i
);
localparam INIT = 4'd0;
localparam WAIT_REQ = 4'd1;
localparam START_ME_DOUBLE = 4'd2;
localparam WAIT_ME_DOUBLE = 4'd3;
localparam DONE_ME_DOUBLE = 4'd4;
localparam CALC_INIT_MVEC = 4'd5;
localparam START_ME_INTEGER = 4'd6;
localparam WAIT_ME_INTEGER = 4'd7;
localparam DONE_ME_INTEGER = 4'd8;
localparam CALC_MVEC = 4'd9;
localparam DONE = 4'd10;
localparam WAIT_REQ_FALL = 4'd11;
reg [3:0] state_main;
reg [9:0] mvec_d;
reg [3:0] diff_i;
reg [11:0] mvec;
wire [5:0] mvec_decoded_h;
wire [5:0] mvec_decoded_w;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_main <= INIT;
req_d <= 0;
req_i <= 0;
mvec_d <= 0;
init_pos_i <= 0;
diff_i <= 0;
mvec <= 0;
min_mvec <= 0;
min_sad <= 0;
ack <= 0;
end else begin
case(state_main)
INIT: begin
state_main <= #1 WAIT_REQ;
mvec_d <= #1 0;
init_pos_i <= #1 0;
diff_i <= #1 0;
mvec <= #1 0;
min_mvec <= #1 0;
min_sad <= #1 0;
ack <= #1 0;
end
WAIT_REQ: begin
if(req)
state_main <= #1 START_ME_DOUBLE;
end
START_ME_DOUBLE: begin
state_main <= #1 WAIT_ME_DOUBLE;
req_d <= #1 1;
end
WAIT_ME_DOUBLE: begin
if(ack_d)
state_main <= #1 DONE_ME_DOUBLE;
end
DONE_ME_DOUBLE: begin
state_main <= #1 CALC_INIT_MVEC;
mvec_d <= #1 min_mvec_d;
req_d <= #1 0;
end
CALC_INIT_MVEC: begin
state_main <= #1 START_ME_INTEGER;
init_pos_i[11:6] <= #1 decode_mvec(mvec_d[9:5]);
init_pos_i[5:0] <= #1 decode_mvec(mvec_d[4:0]);
end
START_ME_INTEGER: begin
state_main <= #1 WAIT_ME_INTEGER;
req_i <= #1 1;
end
WAIT_ME_INTEGER: begin
if(ack_i)
state_main <= #1 DONE_ME_INTEGER;
end
DONE_ME_INTEGER: begin
state_main <= #1 CALC_MVEC;
diff_i <= #1 min_diff_i;
req_i <= #1 0;
end
CALC_MVEC: begin
state_main <= #1 DONE;
mvec[11:6] <= #1 init_pos_i[11:6] + {4'd0, diff_i[3:2]};
mvec[5:0] <= #1 init_pos_i[5:0] + {4'd0, diff_i[1:0]};
end
DONE: begin
state_main <= #1 WAIT_REQ_FALL;
min_mvec <= #1 mvec;
min_sad <= #1 min_sad_i;
ack <= #1 1;
end
WAIT_REQ_FALL: begin
if(~req) begin
state_main <= #1 WAIT_REQ;
ack <= #1 0;
end
end
default: begin
state_main <= 'dx;
end
endcase
end
end
function [5:0] decode_mvec;
input [4:0] mvec_in;
begin
case(mvec_in)
5'd7 : decode_mvec = 6'd0;
5'd8 : decode_mvec = 6'd1;
5'd9 : decode_mvec = 6'd3;
5'd10 : decode_mvec = 6'd5;
5'd11 : decode_mvec = 6'd7;
5'd12 : decode_mvec = 6'd9;
5'd13 : decode_mvec = 6'd11;
5'd14 : decode_mvec = 6'd13;
5'd15 : decode_mvec = 6'd15;
5'd16 : decode_mvec = 6'd17;
5'd17 : decode_mvec = 6'd19;
5'd18 : decode_mvec = 6'd21;
5'd19 : decode_mvec = 6'd23;
5'd20 : decode_mvec = 6'd25;
5'd21 : decode_mvec = 6'd27;
5'd22 : decode_mvec = 6'd29;
5'd23 : decode_mvec = 6'd31;
5'd24 : decode_mvec = 6'd33;
5'd25 : decode_mvec = 6'd35;
5'd26 : decode_mvec = 6'd37;
5'd27 : decode_mvec = 6'd39;
5'd28 : decode_mvec = 6'd41;
5'd29 : decode_mvec = 6'd43;
5'd30 : decode_mvec = 6'd45;
5'd31 : decode_mvec = 6'd46;
default: decode_mvec = 6'dx;
endcase
end
endfunction
endmodule | module control_top
(
input wire rst_n,
input wire clk,
input wire req,
output reg ack,
output reg [11:0] min_mvec,
output reg [15:0] min_sad,
output reg req_d,
input wire [9:0] min_mvec_d,
input wire ack_d,
output reg req_i,
output reg [11:0] init_pos_i ,
input wire [15:0] min_sad_i,
input wire [3:0] min_diff_i,
input wire ack_i
); |
localparam INIT = 4'd0;
localparam WAIT_REQ = 4'd1;
localparam START_ME_DOUBLE = 4'd2;
localparam WAIT_ME_DOUBLE = 4'd3;
localparam DONE_ME_DOUBLE = 4'd4;
localparam CALC_INIT_MVEC = 4'd5;
localparam START_ME_INTEGER = 4'd6;
localparam WAIT_ME_INTEGER = 4'd7;
localparam DONE_ME_INTEGER = 4'd8;
localparam CALC_MVEC = 4'd9;
localparam DONE = 4'd10;
localparam WAIT_REQ_FALL = 4'd11;
reg [3:0] state_main;
reg [9:0] mvec_d;
reg [3:0] diff_i;
reg [11:0] mvec;
wire [5:0] mvec_decoded_h;
wire [5:0] mvec_decoded_w;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state_main <= INIT;
req_d <= 0;
req_i <= 0;
mvec_d <= 0;
init_pos_i <= 0;
diff_i <= 0;
mvec <= 0;
min_mvec <= 0;
min_sad <= 0;
ack <= 0;
end else begin
case(state_main)
INIT: begin
state_main <= #1 WAIT_REQ;
mvec_d <= #1 0;
init_pos_i <= #1 0;
diff_i <= #1 0;
mvec <= #1 0;
min_mvec <= #1 0;
min_sad <= #1 0;
ack <= #1 0;
end
WAIT_REQ: begin
if(req)
state_main <= #1 START_ME_DOUBLE;
end
START_ME_DOUBLE: begin
state_main <= #1 WAIT_ME_DOUBLE;
req_d <= #1 1;
end
WAIT_ME_DOUBLE: begin
if(ack_d)
state_main <= #1 DONE_ME_DOUBLE;
end
DONE_ME_DOUBLE: begin
state_main <= #1 CALC_INIT_MVEC;
mvec_d <= #1 min_mvec_d;
req_d <= #1 0;
end
CALC_INIT_MVEC: begin
state_main <= #1 START_ME_INTEGER;
init_pos_i[11:6] <= #1 decode_mvec(mvec_d[9:5]);
init_pos_i[5:0] <= #1 decode_mvec(mvec_d[4:0]);
end
START_ME_INTEGER: begin
state_main <= #1 WAIT_ME_INTEGER;
req_i <= #1 1;
end
WAIT_ME_INTEGER: begin
if(ack_i)
state_main <= #1 DONE_ME_INTEGER;
end
DONE_ME_INTEGER: begin
state_main <= #1 CALC_MVEC;
diff_i <= #1 min_diff_i;
req_i <= #1 0;
end
CALC_MVEC: begin
state_main <= #1 DONE;
mvec[11:6] <= #1 init_pos_i[11:6] + {4'd0, diff_i[3:2]};
mvec[5:0] <= #1 init_pos_i[5:0] + {4'd0, diff_i[1:0]};
end
DONE: begin
state_main <= #1 WAIT_REQ_FALL;
min_mvec <= #1 mvec;
min_sad <= #1 min_sad_i;
ack <= #1 1;
end
WAIT_REQ_FALL: begin
if(~req) begin
state_main <= #1 WAIT_REQ;
ack <= #1 0;
end
end
default: begin
state_main <= 'dx;
end
endcase
end
end
function [5:0] decode_mvec;
input [4:0] mvec_in;
begin
case(mvec_in)
5'd7 : decode_mvec = 6'd0;
5'd8 : decode_mvec = 6'd1;
5'd9 : decode_mvec = 6'd3;
5'd10 : decode_mvec = 6'd5;
5'd11 : decode_mvec = 6'd7;
5'd12 : decode_mvec = 6'd9;
5'd13 : decode_mvec = 6'd11;
5'd14 : decode_mvec = 6'd13;
5'd15 : decode_mvec = 6'd15;
5'd16 : decode_mvec = 6'd17;
5'd17 : decode_mvec = 6'd19;
5'd18 : decode_mvec = 6'd21;
5'd19 : decode_mvec = 6'd23;
5'd20 : decode_mvec = 6'd25;
5'd21 : decode_mvec = 6'd27;
5'd22 : decode_mvec = 6'd29;
5'd23 : decode_mvec = 6'd31;
5'd24 : decode_mvec = 6'd33;
5'd25 : decode_mvec = 6'd35;
5'd26 : decode_mvec = 6'd37;
5'd27 : decode_mvec = 6'd39;
5'd28 : decode_mvec = 6'd41;
5'd29 : decode_mvec = 6'd43;
5'd30 : decode_mvec = 6'd45;
5'd31 : decode_mvec = 6'd46;
default: decode_mvec = 6'dx;
endcase
end
endfunction
endmodule | 2 |
137,991 | data/full_repos/permissive/81549979/rtl/control_top.v | 81,549,979 | control_top.v | v | 163 | 65 | [] | [] | [] | [(1, 162)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/81549979/rtl/control_top.v:122: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance control_top\n state_main <= \'dx;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 301,581 | function | function [5:0] decode_mvec;
input [4:0] mvec_in;
begin
case(mvec_in)
5'd7 : decode_mvec = 6'd0;
5'd8 : decode_mvec = 6'd1;
5'd9 : decode_mvec = 6'd3;
5'd10 : decode_mvec = 6'd5;
5'd11 : decode_mvec = 6'd7;
5'd12 : decode_mvec = 6'd9;
5'd13 : decode_mvec = 6'd11;
5'd14 : decode_mvec = 6'd13;
5'd15 : decode_mvec = 6'd15;
5'd16 : decode_mvec = 6'd17;
5'd17 : decode_mvec = 6'd19;
5'd18 : decode_mvec = 6'd21;
5'd19 : decode_mvec = 6'd23;
5'd20 : decode_mvec = 6'd25;
5'd21 : decode_mvec = 6'd27;
5'd22 : decode_mvec = 6'd29;
5'd23 : decode_mvec = 6'd31;
5'd24 : decode_mvec = 6'd33;
5'd25 : decode_mvec = 6'd35;
5'd26 : decode_mvec = 6'd37;
5'd27 : decode_mvec = 6'd39;
5'd28 : decode_mvec = 6'd41;
5'd29 : decode_mvec = 6'd43;
5'd30 : decode_mvec = 6'd45;
5'd31 : decode_mvec = 6'd46;
default: decode_mvec = 6'dx;
endcase
end
endfunction | function [5:0] decode_mvec; |
input [4:0] mvec_in;
begin
case(mvec_in)
5'd7 : decode_mvec = 6'd0;
5'd8 : decode_mvec = 6'd1;
5'd9 : decode_mvec = 6'd3;
5'd10 : decode_mvec = 6'd5;
5'd11 : decode_mvec = 6'd7;
5'd12 : decode_mvec = 6'd9;
5'd13 : decode_mvec = 6'd11;
5'd14 : decode_mvec = 6'd13;
5'd15 : decode_mvec = 6'd15;
5'd16 : decode_mvec = 6'd17;
5'd17 : decode_mvec = 6'd19;
5'd18 : decode_mvec = 6'd21;
5'd19 : decode_mvec = 6'd23;
5'd20 : decode_mvec = 6'd25;
5'd21 : decode_mvec = 6'd27;
5'd22 : decode_mvec = 6'd29;
5'd23 : decode_mvec = 6'd31;
5'd24 : decode_mvec = 6'd33;
5'd25 : decode_mvec = 6'd35;
5'd26 : decode_mvec = 6'd37;
5'd27 : decode_mvec = 6'd39;
5'd28 : decode_mvec = 6'd41;
5'd29 : decode_mvec = 6'd43;
5'd30 : decode_mvec = 6'd45;
5'd31 : decode_mvec = 6'd46;
default: decode_mvec = 6'dx;
endcase
end
endfunction | 2 |
137,992 | data/full_repos/permissive/81549979/rtl/memory_tb.v | 81,549,979 | memory_tb.v | v | 105 | 48 | [] | [] | [] | null | line:34: before: "." | null | 1: b"%Error: data/full_repos/permissive/81549979/rtl/memory_tb.v:22: Cannot find file containing module: 'memory_dual_port'\nmemory_dual_port memory_dual_port_A\n^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/memory_dual_port\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/memory_dual_port.v\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/memory_dual_port.sv\n memory_dual_port\n memory_dual_port.v\n memory_dual_port.sv\n obj_dir/memory_dual_port\n obj_dir/memory_dual_port.v\n obj_dir/memory_dual_port.sv\n%Error: data/full_repos/permissive/81549979/rtl/memory_tb.v:38: Cannot find file containing module: 'memory_dual_port'\nmemory_dual_port memory_dual_port_B\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/rtl/memory_tb.v:54: Cannot find file containing module: 'memory_dual_port'\nmemory_dual_port memory_dual_port_C\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/rtl/memory_tb.v:70: Cannot find file containing module: 'memory_dual_port'\nmemory_dual_port memory_dual_port_D\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 301,583 | module | module memory_tb
(
input wire rst_n,
input wire clk,
input wire [5:0] addr_a,
input wire [7:0] addr_b,
output wire [31:0] data_a,
output reg [7:0] data_b
);
parameter MEM_TB_A = "";
parameter MEM_TB_B = "";
parameter MEM_TB_C = "";
parameter MEM_TB_D = "";
wire [7:0] data_b_A;
wire [7:0] data_b_B;
wire [7:0] data_b_C;
wire [7:0] data_b_D;
memory_dual_port memory_dual_port_A
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[31:24] ) ,
.q_b ( data_b_A )
);
defparam memory_dual_port_A.DWIDTH = 8;
defparam memory_dual_port_A.AWIDTH = 6;
defparam memory_dual_port_A.CONTENT = MEM_TB_A;
memory_dual_port memory_dual_port_B
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[23:16] ) ,
.q_b ( data_b_B )
);
defparam memory_dual_port_B.DWIDTH = 8;
defparam memory_dual_port_B.AWIDTH = 6;
defparam memory_dual_port_B.CONTENT = MEM_TB_B;
memory_dual_port memory_dual_port_C
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[15:8] ) ,
.q_b ( data_b_C )
);
defparam memory_dual_port_C.DWIDTH = 8;
defparam memory_dual_port_C.AWIDTH = 6;
defparam memory_dual_port_C.CONTENT = MEM_TB_C;
memory_dual_port memory_dual_port_D
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[7:0] ) ,
.q_b ( data_b_D )
);
defparam memory_dual_port_D.DWIDTH = 8;
defparam memory_dual_port_D.AWIDTH = 6;
defparam memory_dual_port_D.CONTENT = MEM_TB_D;
reg [1:0] sel;
always @(posedge clk) begin
sel <= #1 {addr_b[4], addr_b[0]};
end
always @(*) begin
case (sel)
2'b00: data_b <= #1 data_b_A;
2'b01: data_b <= #1 data_b_B;
2'b10: data_b <= #1 data_b_C;
2'b11: data_b <= #1 data_b_D;
default: data_b <= 8'dx;
endcase
end
endmodule | module memory_tb
(
input wire rst_n,
input wire clk,
input wire [5:0] addr_a,
input wire [7:0] addr_b,
output wire [31:0] data_a,
output reg [7:0] data_b
); |
parameter MEM_TB_A = "";
parameter MEM_TB_B = "";
parameter MEM_TB_C = "";
parameter MEM_TB_D = "";
wire [7:0] data_b_A;
wire [7:0] data_b_B;
wire [7:0] data_b_C;
wire [7:0] data_b_D;
memory_dual_port memory_dual_port_A
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[31:24] ) ,
.q_b ( data_b_A )
);
defparam memory_dual_port_A.DWIDTH = 8;
defparam memory_dual_port_A.AWIDTH = 6;
defparam memory_dual_port_A.CONTENT = MEM_TB_A;
memory_dual_port memory_dual_port_B
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[23:16] ) ,
.q_b ( data_b_B )
);
defparam memory_dual_port_B.DWIDTH = 8;
defparam memory_dual_port_B.AWIDTH = 6;
defparam memory_dual_port_B.CONTENT = MEM_TB_B;
memory_dual_port memory_dual_port_C
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[15:8] ) ,
.q_b ( data_b_C )
);
defparam memory_dual_port_C.DWIDTH = 8;
defparam memory_dual_port_C.AWIDTH = 6;
defparam memory_dual_port_C.CONTENT = MEM_TB_C;
memory_dual_port memory_dual_port_D
(
.address_a ( addr_a ) ,
.address_b ( {addr_b[7:5], addr_b[3:1]} ) ,
.clock ( clk ) ,
.data_a ( 8'd0 ) ,
.data_b ( 8'd0 ) ,
.wren_a ( 1'b0 ) ,
.wren_b ( 1'b0 ) ,
.q_a ( data_a[7:0] ) ,
.q_b ( data_b_D )
);
defparam memory_dual_port_D.DWIDTH = 8;
defparam memory_dual_port_D.AWIDTH = 6;
defparam memory_dual_port_D.CONTENT = MEM_TB_D;
reg [1:0] sel;
always @(posedge clk) begin
sel <= #1 {addr_b[4], addr_b[0]};
end
always @(*) begin
case (sel)
2'b00: data_b <= #1 data_b_A;
2'b01: data_b <= #1 data_b_B;
2'b10: data_b <= #1 data_b_C;
2'b11: data_b <= #1 data_b_D;
default: data_b <= 8'dx;
endcase
end
endmodule | 2 |
137,994 | data/full_repos/permissive/81549979/rtl/me_integer.v | 81,549,979 | me_integer.v | v | 72 | 39 | [] | [] | [] | [(1, 71)] | null | null | 1: b"%Error: data/full_repos/permissive/81549979/rtl/me_integer.v:27: Cannot find file containing module: 'control_integer'\ncontrol_integer _control_integer\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/control_integer\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/control_integer.v\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/control_integer.sv\n control_integer\n control_integer.v\n control_integer.sv\n obj_dir/control_integer\n obj_dir/control_integer.v\n obj_dir/control_integer.sv\n%Error: data/full_repos/permissive/81549979/rtl/me_integer.v:46: Cannot find file containing module: 'addr_gen_integer'\naddr_gen_integer _addr_gen_integer\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/rtl/me_integer.v:58: Cannot find file containing module: 'SAD_array'\nSAD_array _SAD_array\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 301,585 | module | module me_integer
(
input wire rst_n,
input wire clk,
input wire req,
input wire [11:0] init_pos,
output wire [15:0] min_sad,
output wire [3:0] min_diff,
output wire ack,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output wire [11:0] addr_sw,
output wire [7:0] addr_tb
);
wire [11:0] init_mvec;
wire en_addr_sw;
wire en_addr_tb;
wire clr;
wire en_sadarray_sw;
wire en_sadarray_tb;
wire [3:0] vec_diff;
wire [15:0] sad;
control_integer _control_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.sad ( sad ) ,
.vec_diff ( vec_diff ) ,
.init_pos ( init_pos ) ,
.clr ( clr ) ,
.en_addr_sw ( en_addr_sw ) ,
.en_addr_tb ( en_addr_tb ) ,
.en_sadarray_sw ( en_sadarray_sw ) ,
.en_sadarray_tb ( en_sadarray_tb ) ,
.init_mvec ( init_mvec ) ,
.min_sad ( min_sad ) ,
.min_diff ( min_diff ) ,
.ack ( ack )
);
addr_gen_integer _addr_gen_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_addr_sw ) ,
.en_tb ( en_addr_tb ) ,
.init_mvec ( init_mvec ) ,
.addr_sw ( addr_sw ) ,
.addr_tb ( addr_tb )
);
SAD_array _SAD_array
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sadarray_sw ) ,
.en_tb ( en_sadarray_tb ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.vec_diff ( vec_diff ) ,
.sad ( sad )
);
endmodule | module me_integer
(
input wire rst_n,
input wire clk,
input wire req,
input wire [11:0] init_pos,
output wire [15:0] min_sad,
output wire [3:0] min_diff,
output wire ack,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output wire [11:0] addr_sw,
output wire [7:0] addr_tb
); |
wire [11:0] init_mvec;
wire en_addr_sw;
wire en_addr_tb;
wire clr;
wire en_sadarray_sw;
wire en_sadarray_tb;
wire [3:0] vec_diff;
wire [15:0] sad;
control_integer _control_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.sad ( sad ) ,
.vec_diff ( vec_diff ) ,
.init_pos ( init_pos ) ,
.clr ( clr ) ,
.en_addr_sw ( en_addr_sw ) ,
.en_addr_tb ( en_addr_tb ) ,
.en_sadarray_sw ( en_sadarray_sw ) ,
.en_sadarray_tb ( en_sadarray_tb ) ,
.init_mvec ( init_mvec ) ,
.min_sad ( min_sad ) ,
.min_diff ( min_diff ) ,
.ack ( ack )
);
addr_gen_integer _addr_gen_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_addr_sw ) ,
.en_tb ( en_addr_tb ) ,
.init_mvec ( init_mvec ) ,
.addr_sw ( addr_sw ) ,
.addr_tb ( addr_tb )
);
SAD_array _SAD_array
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sadarray_sw ) ,
.en_tb ( en_sadarray_tb ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.vec_diff ( vec_diff ) ,
.sad ( sad )
);
endmodule | 2 |
137,995 | data/full_repos/permissive/81549979/rtl/me_top.v | 81,549,979 | me_top.v | v | 87 | 32 | [] | [] | [] | [(1, 86)] | null | null | 1: b"%Error: data/full_repos/permissive/81549979/rtl/me_top.v:30: Cannot find file containing module: 'control_top'\ncontrol_top _control_top\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/control_top\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/control_top.v\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/control_top.sv\n control_top\n control_top.v\n control_top.sv\n obj_dir/control_top\n obj_dir/control_top.v\n obj_dir/control_top.sv\n%Error: data/full_repos/permissive/81549979/rtl/me_top.v:53: Cannot find file containing module: 'me_double'\nme_double _me_double\n^~~~~~~~~\n%Error: data/full_repos/permissive/81549979/rtl/me_top.v:69: Cannot find file containing module: 'me_integer'\nme_integer _me_integer\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 301,586 | module | module me_top
(
input wire rst_n,
input wire clk,
input wire req,
output wire [15:0] min_sad,
output wire [11:0] min_mvec,
output wire ack,
input wire [31:0] pel_sw_d,
input wire [31:0] pel_tb_d,
input wire [7:0] pel_sw_i,
input wire [7:0] pel_tb_i,
output wire [9:0] addr_sw_d,
output wire [5:0] addr_tb_d,
output wire [11:0] addr_sw_i,
output wire [7:0] addr_tb_i
);
wire req_d;
wire ack_d;
wire req_i;
wire ack_i;
wire [11:0] init_pos_i;
wire [9:0] min_mvec_d;
wire [15:0] min_sad_i;
wire [3:0] min_diff_i;
control_top _control_top
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.ack ( ack ) ,
.min_mvec ( min_mvec ) ,
.min_sad ( min_sad ) ,
.req_d ( req_d ) ,
.min_mvec_d ( min_mvec_d ) ,
.ack_d ( ack_d ) ,
.req_i ( req_i ) ,
.init_pos_i ( init_pos_i ) ,
.min_sad_i ( min_sad_i ) ,
.min_diff_i ( min_diff_i ),
.ack_i ( ack_i )
);
me_double _me_double
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req_d ) ,
.min_sad ( ) ,
.min_mvec ( min_mvec_d ) ,
.ack ( ack_d ) ,
.pel_sw ( pel_sw_d ) ,
.pel_tb ( pel_tb_d ) ,
.addr_sw ( addr_sw_d ) ,
.addr_tb ( addr_tb_d )
);
me_integer _me_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req_i ) ,
.init_pos ( init_pos_i ) ,
.min_sad ( min_sad_i ) ,
.min_diff ( min_diff_i ) ,
.ack ( ack_i ) ,
.pel_sw ( pel_sw_i ) ,
.pel_tb ( pel_tb_i ) ,
.addr_sw ( addr_sw_i ) ,
.addr_tb ( addr_tb_i )
);
endmodule | module me_top
(
input wire rst_n,
input wire clk,
input wire req,
output wire [15:0] min_sad,
output wire [11:0] min_mvec,
output wire ack,
input wire [31:0] pel_sw_d,
input wire [31:0] pel_tb_d,
input wire [7:0] pel_sw_i,
input wire [7:0] pel_tb_i,
output wire [9:0] addr_sw_d,
output wire [5:0] addr_tb_d,
output wire [11:0] addr_sw_i,
output wire [7:0] addr_tb_i
); |
wire req_d;
wire ack_d;
wire req_i;
wire ack_i;
wire [11:0] init_pos_i;
wire [9:0] min_mvec_d;
wire [15:0] min_sad_i;
wire [3:0] min_diff_i;
control_top _control_top
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.ack ( ack ) ,
.min_mvec ( min_mvec ) ,
.min_sad ( min_sad ) ,
.req_d ( req_d ) ,
.min_mvec_d ( min_mvec_d ) ,
.ack_d ( ack_d ) ,
.req_i ( req_i ) ,
.init_pos_i ( init_pos_i ) ,
.min_sad_i ( min_sad_i ) ,
.min_diff_i ( min_diff_i ),
.ack_i ( ack_i )
);
me_double _me_double
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req_d ) ,
.min_sad ( ) ,
.min_mvec ( min_mvec_d ) ,
.ack ( ack_d ) ,
.pel_sw ( pel_sw_d ) ,
.pel_tb ( pel_tb_d ) ,
.addr_sw ( addr_sw_d ) ,
.addr_tb ( addr_tb_d )
);
me_integer _me_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req_i ) ,
.init_pos ( init_pos_i ) ,
.min_sad ( min_sad_i ) ,
.min_diff ( min_diff_i ) ,
.ack ( ack_i ) ,
.pel_sw ( pel_sw_i ) ,
.pel_tb ( pel_tb_i ) ,
.addr_sw ( addr_sw_i ) ,
.addr_tb ( addr_tb_i )
);
endmodule | 2 |
137,998 | data/full_repos/permissive/81549979/rtl/SAD_array.v | 81,549,979 | SAD_array.v | v | 329 | 48 | [] | [] | [] | [(3, 327)] | null | null | 1: b"%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:37: Cannot find file containing module: 'SAD'\nSAD SAD_I\n^~~\n ... Looked in:\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/SAD\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/SAD.v\n data/full_repos/permissive/81549979/rtl,data/full_repos/permissive/81549979/SAD.sv\n SAD\n SAD.v\n SAD.sv\n obj_dir/SAD\n obj_dir/SAD.v\n obj_dir/SAD.sv\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:50: Cannot find file containing module: 'SAD'\nSAD SAD_H\n^~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:63: Cannot find file containing module: 'SAD'\nSAD SAD_G\n^~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:76: Cannot find file containing module: 'shift_register'\nshift_register #(.DEPTH(15), .DWIDTH(8) )\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:86: Cannot find file containing module: 'SAD'\nSAD SAD_F\n^~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:99: Cannot find file containing module: 'SAD'\nSAD SAD_E\n^~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:112: Cannot find file containing module: 'SAD'\nSAD SAD_D\n^~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:125: Cannot find file containing module: 'shift_register'\nshift_register #(.DEPTH(15), .DWIDTH(8) )\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:135: Cannot find file containing module: 'SAD'\nSAD SAD_C\n^~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:148: Cannot find file containing module: 'SAD'\nSAD SAD_B\n^~~\n%Error: data/full_repos/permissive/81549979/rtl/SAD_array.v:161: Cannot find file containing module: 'SAD'\nSAD SAD_A\n^~~\n%Error: Exiting due to 11 error(s)\n" | 301,592 | module | module SAD_array
(
input wire rst_n,
input wire clk,
input wire clr,
input wire en_sw,
input wire en_tb,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output reg [3:0] vec_diff,
output reg [15:0] sad
);
wire [15:0] sad_A;
wire [15:0] sad_B;
wire [15:0] sad_C;
wire [15:0] sad_D;
wire [15:0] sad_E;
wire [15:0] sad_F;
wire [15:0] sad_G;
wire [15:0] sad_H;
wire [15:0] sad_I;
wire [7:0] pel_sw_I;
wire [7:0] pel_sw_H;
wire [7:0] pel_sw_G;
wire [7:0] pel_sr_G_to_F;
wire [7:0] pel_sw_F;
wire [7:0] pel_sw_E;
wire [7:0] pel_sw_D;
wire [7:0] pel_sr_D_to_C;
wire [7:0] pel_sw_C;
wire [7:0] pel_sw_B;
SAD SAD_I
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_I ) ,
.sad ( sad_I )
);
SAD SAD_H
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_I ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_H ) ,
.sad ( sad_H )
);
SAD SAD_G
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_H ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_G ) ,
.sad ( sad_G )
);
shift_register #(.DEPTH(15), .DWIDTH(8) )
sr_G_to_F
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.en ( en_sw ) ,
.d ( pel_sw_G ) ,
.q ( pel_sr_G_to_F )
);
SAD SAD_F
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sr_G_to_F ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_F ) ,
.sad ( sad_F )
);
SAD SAD_E
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_F ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_E ) ,
.sad ( sad_E )
);
SAD SAD_D
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_E ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_D ) ,
.sad ( sad_D )
);
shift_register #(.DEPTH(15), .DWIDTH(8) )
sr_D_to_C
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.en ( en_sw ) ,
.d ( pel_sw_D ) ,
.q ( pel_sr_D_to_C )
);
SAD SAD_C
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sr_D_to_C ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_C ) ,
.sad ( sad_C )
);
SAD SAD_B
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_C ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_B ) ,
.sad ( sad_B )
);
SAD SAD_A
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_B ) ,
.pel_tb ( pel_tb ) ,
.sad ( sad_A )
);
localparam VEC_DIFF_A = 4'b0000;
localparam VEC_DIFF_B = 4'b0001;
localparam VEC_DIFF_C = 4'b0010;
localparam VEC_DIFF_D = 4'b0100;
localparam VEC_DIFF_E = 4'b0101;
localparam VEC_DIFF_F = 4'b0110;
localparam VEC_DIFF_G = 4'b1000;
localparam VEC_DIFF_H = 4'b1001;
localparam VEC_DIFF_I = 4'b1010;
reg [15:0] min_AB;
reg [15:0] min_CD;
reg [15:0] min_EF;
reg [15:0] min_GH;
reg [15:0] min_I;
reg [3:0] diff_AB;
reg [3:0] diff_CD;
reg [3:0] diff_EF;
reg [3:0] diff_GH;
reg [3:0] diff_I;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_AB <= 0;
min_CD <= 0;
min_EF <= 0;
min_GH <= 0;
min_I <= 0;
diff_AB <= 0;
diff_CD <= 0;
diff_EF <= 0;
diff_GH <= 0;
diff_I <= 0;
end else begin
if(sad_A < sad_B) begin
min_AB <= #1 sad_A;
diff_AB <= #1 VEC_DIFF_A;
end else begin
min_AB <= #1 sad_B;
diff_AB <= #1 VEC_DIFF_B;
end
if(sad_C < sad_D) begin
min_CD <= #1 sad_C;
diff_CD <= #1 VEC_DIFF_C;
end else begin
min_CD <= #1 sad_D;
diff_CD <= #1 VEC_DIFF_D;
end
if(sad_E < sad_F) begin
min_EF <= #1 sad_E;
diff_EF <= #1 VEC_DIFF_E;
end else begin
min_EF <= #1 sad_F;
diff_EF <= #1 VEC_DIFF_F;
end
if(sad_G < sad_H) begin
min_GH <= #1 sad_G;
diff_GH <= #1 VEC_DIFF_G;
end else begin
min_GH <= #1 sad_H;
diff_GH <= #1 VEC_DIFF_H;
end
min_I <= #1 sad_I;
diff_I <= #1 VEC_DIFF_I;
end
end
reg [15:0] min_ABCD;
reg [15:0] min_EFGH;
reg [15:0] min_I_2;
reg [3:0] diff_ABCD;
reg [3:0] diff_EFGH;
reg [3:0] diff_I_2;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_ABCD <= 0;
min_EFGH <= 0;
min_I_2 <= 0;
diff_ABCD <= 0;
diff_EFGH <= 0;
diff_I_2 <= 0;
end else begin
if(min_AB < min_CD) begin
min_ABCD <= #1 min_AB;
diff_ABCD <= #1 diff_AB;
end else begin
min_ABCD <= #1 min_CD;
diff_ABCD <= #1 diff_CD;
end
if(min_EF < min_GH) begin
min_EFGH <= #1 min_EF;
diff_EFGH <= #1 diff_EF;
end else begin
min_EFGH <= #1 min_GH;
diff_EFGH <= #1 diff_GH;
end
min_I_2 <= #1 min_I;
diff_I_2 <= #1 diff_I;
end
end
reg [15:0] min_ABCDEFGH;
reg [15:0] min_I_3;
reg [3:0] diff_ABCDEFGH;
reg [3:0] diff_I_3;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_ABCDEFGH <= 0;
min_I_3 <= 0;
diff_ABCDEFGH <= 0;
diff_I_3 <= 0;
end else begin
if(min_ABCD < min_EFGH) begin
min_ABCDEFGH <= #1 min_ABCD;
diff_ABCDEFGH <= #1 diff_ABCD;
end else begin
min_ABCDEFGH <= #1 min_EFGH;
diff_ABCDEFGH <= #1 diff_EFGH;
end
min_I_3 <= #1 min_I_2;
diff_I_3 <= #1 diff_I_2;
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
sad <= 0;
vec_diff <= 0;
end else begin
if(min_ABCDEFGH < min_I_3) begin
sad <= #1 min_ABCDEFGH;
vec_diff <= #1 diff_ABCDEFGH;
end else begin
sad <= #1 min_I_3;
vec_diff <= #1 diff_I_3;
end
end
end
endmodule | module SAD_array
(
input wire rst_n,
input wire clk,
input wire clr,
input wire en_sw,
input wire en_tb,
input wire [7:0] pel_sw,
input wire [7:0] pel_tb,
output reg [3:0] vec_diff,
output reg [15:0] sad
); |
wire [15:0] sad_A;
wire [15:0] sad_B;
wire [15:0] sad_C;
wire [15:0] sad_D;
wire [15:0] sad_E;
wire [15:0] sad_F;
wire [15:0] sad_G;
wire [15:0] sad_H;
wire [15:0] sad_I;
wire [7:0] pel_sw_I;
wire [7:0] pel_sw_H;
wire [7:0] pel_sw_G;
wire [7:0] pel_sr_G_to_F;
wire [7:0] pel_sw_F;
wire [7:0] pel_sw_E;
wire [7:0] pel_sw_D;
wire [7:0] pel_sr_D_to_C;
wire [7:0] pel_sw_C;
wire [7:0] pel_sw_B;
SAD SAD_I
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_I ) ,
.sad ( sad_I )
);
SAD SAD_H
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_I ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_H ) ,
.sad ( sad_H )
);
SAD SAD_G
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_H ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_G ) ,
.sad ( sad_G )
);
shift_register #(.DEPTH(15), .DWIDTH(8) )
sr_G_to_F
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.en ( en_sw ) ,
.d ( pel_sw_G ) ,
.q ( pel_sr_G_to_F )
);
SAD SAD_F
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sr_G_to_F ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_F ) ,
.sad ( sad_F )
);
SAD SAD_E
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_F ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_E ) ,
.sad ( sad_E )
);
SAD SAD_D
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_E ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_D ) ,
.sad ( sad_D )
);
shift_register #(.DEPTH(15), .DWIDTH(8) )
sr_D_to_C
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.en ( en_sw ) ,
.d ( pel_sw_D ) ,
.q ( pel_sr_D_to_C )
);
SAD SAD_C
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sr_D_to_C ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_C ) ,
.sad ( sad_C )
);
SAD SAD_B
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_C ) ,
.pel_tb ( pel_tb ) ,
.nxt_sw ( pel_sw_B ) ,
.sad ( sad_B )
);
SAD SAD_A
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.clr ( clr ) ,
.en_sw ( en_sw ) ,
.en_tb ( en_tb ) ,
.pel_sw ( pel_sw_B ) ,
.pel_tb ( pel_tb ) ,
.sad ( sad_A )
);
localparam VEC_DIFF_A = 4'b0000;
localparam VEC_DIFF_B = 4'b0001;
localparam VEC_DIFF_C = 4'b0010;
localparam VEC_DIFF_D = 4'b0100;
localparam VEC_DIFF_E = 4'b0101;
localparam VEC_DIFF_F = 4'b0110;
localparam VEC_DIFF_G = 4'b1000;
localparam VEC_DIFF_H = 4'b1001;
localparam VEC_DIFF_I = 4'b1010;
reg [15:0] min_AB;
reg [15:0] min_CD;
reg [15:0] min_EF;
reg [15:0] min_GH;
reg [15:0] min_I;
reg [3:0] diff_AB;
reg [3:0] diff_CD;
reg [3:0] diff_EF;
reg [3:0] diff_GH;
reg [3:0] diff_I;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_AB <= 0;
min_CD <= 0;
min_EF <= 0;
min_GH <= 0;
min_I <= 0;
diff_AB <= 0;
diff_CD <= 0;
diff_EF <= 0;
diff_GH <= 0;
diff_I <= 0;
end else begin
if(sad_A < sad_B) begin
min_AB <= #1 sad_A;
diff_AB <= #1 VEC_DIFF_A;
end else begin
min_AB <= #1 sad_B;
diff_AB <= #1 VEC_DIFF_B;
end
if(sad_C < sad_D) begin
min_CD <= #1 sad_C;
diff_CD <= #1 VEC_DIFF_C;
end else begin
min_CD <= #1 sad_D;
diff_CD <= #1 VEC_DIFF_D;
end
if(sad_E < sad_F) begin
min_EF <= #1 sad_E;
diff_EF <= #1 VEC_DIFF_E;
end else begin
min_EF <= #1 sad_F;
diff_EF <= #1 VEC_DIFF_F;
end
if(sad_G < sad_H) begin
min_GH <= #1 sad_G;
diff_GH <= #1 VEC_DIFF_G;
end else begin
min_GH <= #1 sad_H;
diff_GH <= #1 VEC_DIFF_H;
end
min_I <= #1 sad_I;
diff_I <= #1 VEC_DIFF_I;
end
end
reg [15:0] min_ABCD;
reg [15:0] min_EFGH;
reg [15:0] min_I_2;
reg [3:0] diff_ABCD;
reg [3:0] diff_EFGH;
reg [3:0] diff_I_2;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_ABCD <= 0;
min_EFGH <= 0;
min_I_2 <= 0;
diff_ABCD <= 0;
diff_EFGH <= 0;
diff_I_2 <= 0;
end else begin
if(min_AB < min_CD) begin
min_ABCD <= #1 min_AB;
diff_ABCD <= #1 diff_AB;
end else begin
min_ABCD <= #1 min_CD;
diff_ABCD <= #1 diff_CD;
end
if(min_EF < min_GH) begin
min_EFGH <= #1 min_EF;
diff_EFGH <= #1 diff_EF;
end else begin
min_EFGH <= #1 min_GH;
diff_EFGH <= #1 diff_GH;
end
min_I_2 <= #1 min_I;
diff_I_2 <= #1 diff_I;
end
end
reg [15:0] min_ABCDEFGH;
reg [15:0] min_I_3;
reg [3:0] diff_ABCDEFGH;
reg [3:0] diff_I_3;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
min_ABCDEFGH <= 0;
min_I_3 <= 0;
diff_ABCDEFGH <= 0;
diff_I_3 <= 0;
end else begin
if(min_ABCD < min_EFGH) begin
min_ABCDEFGH <= #1 min_ABCD;
diff_ABCDEFGH <= #1 diff_ABCD;
end else begin
min_ABCDEFGH <= #1 min_EFGH;
diff_ABCDEFGH <= #1 diff_EFGH;
end
min_I_3 <= #1 min_I_2;
diff_I_3 <= #1 diff_I_2;
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
sad <= 0;
vec_diff <= 0;
end else begin
if(min_ABCDEFGH < min_I_3) begin
sad <= #1 min_ABCDEFGH;
vec_diff <= #1 diff_ABCDEFGH;
end else begin
sad <= #1 min_I_3;
vec_diff <= #1 diff_I_3;
end
end
end
endmodule | 2 |
138,000 | data/full_repos/permissive/81549979/testbench/memory_dual_port.v | 81,549,979 | memory_dual_port.v | v | 41 | 39 | [] | [] | [] | [(2, 39)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:4: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [AWIDTH-1:0] address_a,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:5: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [AWIDTH-1:0] address_b,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:7: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [DWIDTH-1:0] data_a,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [DWIDTH-1:0] data_b,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:11: Little bit endian vector: MSB < LSB of bit range: -1:0\n output reg [DWIDTH-1:0] q_a,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:12: Little bit endian vector: MSB < LSB of bit range: -1:0\n output reg [DWIDTH-1:0] q_b\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:19: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [DWIDTH-1:0] core [0:2**AWIDTH-1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:28: Bit extraction of array[0:0] requires 1 bit index, not 2 bits.\n : ... In instance memory_dual_port\n core[address_a] <= #1 data_a;\n ^\n%Warning-WIDTH: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:30: Bit extraction of array[0:0] requires 1 bit index, not 2 bits.\n : ... In instance memory_dual_port\n core[address_b] <= #1 data_b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:35: Bit extraction of array[0:0] requires 1 bit index, not 2 bits.\n : ... In instance memory_dual_port\n q_a <= #1 core[address_a];\n ^\n%Warning-WIDTH: data/full_repos/permissive/81549979/testbench/memory_dual_port.v:36: Bit extraction of array[0:0] requires 1 bit index, not 2 bits.\n : ... In instance memory_dual_port\n q_b <= #1 core[address_b];\n ^\n%Error: Exiting due to 11 warning(s)\n' | 301,595 | module | module memory_dual_port
(
input wire [AWIDTH-1:0] address_a,
input wire [AWIDTH-1:0] address_b,
input wire clock,
input wire [DWIDTH-1:0] data_a,
input wire [DWIDTH-1:0] data_b,
input wire wren_a,
input wire wren_b,
output reg [DWIDTH-1:0] q_a,
output reg [DWIDTH-1:0] q_b
);
parameter DWIDTH = 0;
parameter AWIDTH = 0;
parameter CONTENT = "";
reg [DWIDTH-1:0] core [0:2**AWIDTH-1];
initial begin
$readmemh(CONTENT, core);
end
always @(posedge clock) begin
if(wren_a)
core[address_a] <= #1 data_a;
if(wren_b)
core[address_b] <= #1 data_b;
end
always @(posedge clock) begin
q_a <= #1 core[address_a];
q_b <= #1 core[address_b];
end
endmodule | module memory_dual_port
(
input wire [AWIDTH-1:0] address_a,
input wire [AWIDTH-1:0] address_b,
input wire clock,
input wire [DWIDTH-1:0] data_a,
input wire [DWIDTH-1:0] data_b,
input wire wren_a,
input wire wren_b,
output reg [DWIDTH-1:0] q_a,
output reg [DWIDTH-1:0] q_b
); |
parameter DWIDTH = 0;
parameter AWIDTH = 0;
parameter CONTENT = "";
reg [DWIDTH-1:0] core [0:2**AWIDTH-1];
initial begin
$readmemh(CONTENT, core);
end
always @(posedge clock) begin
if(wren_a)
core[address_a] <= #1 data_a;
if(wren_b)
core[address_b] <= #1 data_b;
end
always @(posedge clock) begin
q_a <= #1 core[address_a];
q_b <= #1 core[address_b];
end
endmodule | 2 |
138,001 | data/full_repos/permissive/81549979/testbench/tb_me_double.v | 81,549,979 | tb_me_double.v | v | 117 | 51 | [] | [] | [] | null | line:404: before: "." | null | 1: b'%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:1: Cannot find include file: ./memory_dual_port.v\n`include "./memory_dual_port.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v.v\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v.sv\n ./memory_dual_port.v\n ./memory_dual_port.v.v\n ./memory_dual_port.v.sv\n obj_dir/./memory_dual_port.v\n obj_dir/./memory_dual_port.v.v\n obj_dir/./memory_dual_port.v.sv\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:2: Cannot find include file: ../rtl/addr_gen.v\n`include "../rtl/addr_gen.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:3: Cannot find include file: ../rtl/control_double.v\n`include "../rtl/control_double.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:4: Cannot find include file: ../rtl/memory_sw.v\n`include "../rtl/memory_sw.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:5: Cannot find include file: ../rtl/memory_tb.v\n`include "../rtl/memory_tb.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:6: Cannot find include file: ../rtl/pe.v\n`include "../rtl/pe.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:7: Cannot find include file: ../rtl/pe_line.v\n`include "../rtl/pe_line.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:8: Cannot find include file: ../rtl/shift_register.v\n`include "../rtl/shift_register.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:9: Cannot find include file: ../rtl/sum.v\n`include "../rtl/sum.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:10: Cannot find include file: ../rtl/pe_array.v\n`include "../rtl/pe_array.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:11: Cannot find include file: ../rtl/pa_array.v\n`include "../rtl/pa_array.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:12: Cannot find include file: ../rtl/me_double.v\n`include "../rtl/me_double.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_double.v:87: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:90: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_me_double.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:91: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb_me_double);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_double.v:95: Unsupported: Ignoring delay on this delayed statement.\n #1 rst_n<=1\'bx;clk<=1\'bx;req<=1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_double.v:96: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD) rst_n<=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_double.v:97: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:98: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:100: syntax error, unexpected \'@\'\n repeat(3) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:102: syntax error, unexpected \'@\'\n while(~ack) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:107: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_double.v:109: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: Exiting due to 19 error(s), 4 warning(s)\n' | 301,596 | module | module tb_me_double;
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memory/memory_tb_B.txt";
localparam MEM_TB_C = "../memory/memory_tb_C.txt";
localparam MEM_TB_D = "../memory/memory_tb_D.txt";
reg rst_n;
reg clk;
reg req;
wire [15:0] min_sad;
wire [4:0] min_mvec_h;
wire [4:0] min_mvec_w;
wire ack;
wire [31:0] pel_sw;
wire [31:0] pel_tb;
wire [9:0] addr_sw;
wire [5:0] addr_tb;
me_double _me_double
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.min_sad ( min_sad ) ,
.min_mvec ( {min_mvec_w, min_mvec_h} ) ,
.ack ( ack ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.addr_sw ( addr_sw ) ,
.addr_tb ( addr_tb )
);
memory_sw
_memory_sw
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_sw ) ,
.addr_b ( 12'd0 ) ,
.data_a ( pel_sw ) ,
.data_b ( )
);
defparam _memory_sw.MEM_SW_A = MEM_SW_A;
defparam _memory_sw.MEM_SW_B = MEM_SW_B;
defparam _memory_sw.MEM_SW_C = MEM_SW_C;
defparam _memory_sw.MEM_SW_D = MEM_SW_D;
memory_tb
_memory_tb
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_tb ) ,
.addr_b ( 8'd0 ) ,
.data_a ( pel_tb ) ,
.data_b ( )
);
defparam _memory_tb.MEM_TB_A = MEM_TB_A;
defparam _memory_tb.MEM_TB_B = MEM_TB_B;
defparam _memory_tb.MEM_TB_C = MEM_TB_C;
defparam _memory_tb.MEM_TB_D = MEM_TB_D;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_me_double.vcd");
$dumpvars(0, tb_me_double);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(3) @(posedge clk);
req<=1;
while(~ack) @(posedge clk);
$display("motion vector");
$display(" h : %d", min_mvec_h);
$display(" w : %d", min_mvec_w);
$display(" sad: %d", min_sad);
repeat(10) @(posedge clk);
req<=0;
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | module tb_me_double; |
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memory/memory_tb_B.txt";
localparam MEM_TB_C = "../memory/memory_tb_C.txt";
localparam MEM_TB_D = "../memory/memory_tb_D.txt";
reg rst_n;
reg clk;
reg req;
wire [15:0] min_sad;
wire [4:0] min_mvec_h;
wire [4:0] min_mvec_w;
wire ack;
wire [31:0] pel_sw;
wire [31:0] pel_tb;
wire [9:0] addr_sw;
wire [5:0] addr_tb;
me_double _me_double
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.min_sad ( min_sad ) ,
.min_mvec ( {min_mvec_w, min_mvec_h} ) ,
.ack ( ack ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.addr_sw ( addr_sw ) ,
.addr_tb ( addr_tb )
);
memory_sw
_memory_sw
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_sw ) ,
.addr_b ( 12'd0 ) ,
.data_a ( pel_sw ) ,
.data_b ( )
);
defparam _memory_sw.MEM_SW_A = MEM_SW_A;
defparam _memory_sw.MEM_SW_B = MEM_SW_B;
defparam _memory_sw.MEM_SW_C = MEM_SW_C;
defparam _memory_sw.MEM_SW_D = MEM_SW_D;
memory_tb
_memory_tb
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_tb ) ,
.addr_b ( 8'd0 ) ,
.data_a ( pel_tb ) ,
.data_b ( )
);
defparam _memory_tb.MEM_TB_A = MEM_TB_A;
defparam _memory_tb.MEM_TB_B = MEM_TB_B;
defparam _memory_tb.MEM_TB_C = MEM_TB_C;
defparam _memory_tb.MEM_TB_D = MEM_TB_D;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_me_double.vcd");
$dumpvars(0, tb_me_double);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(3) @(posedge clk);
req<=1;
while(~ack) @(posedge clk);
$display("motion vector");
$display(" h : %d", min_mvec_h);
$display(" w : %d", min_mvec_w);
$display(" sad: %d", min_sad);
repeat(10) @(posedge clk);
req<=0;
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | 2 |
138,002 | data/full_repos/permissive/81549979/testbench/tb_me_integer.v | 81,549,979 | tb_me_integer.v | v | 120 | 76 | [] | [] | [] | null | line:358: before: "." | null | 1: b'%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:1: Cannot find include file: ./memory_dual_port.v\n`include "./memory_dual_port.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v.v\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v.sv\n ./memory_dual_port.v\n ./memory_dual_port.v.v\n ./memory_dual_port.v.sv\n obj_dir/./memory_dual_port.v\n obj_dir/./memory_dual_port.v.v\n obj_dir/./memory_dual_port.v.sv\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:2: Cannot find include file: ../rtl/addr_gen_integer.v\n`include "../rtl/addr_gen_integer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:3: Cannot find include file: ../rtl/control_integer.v\n`include "../rtl/control_integer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:4: Cannot find include file: ../rtl/memory_sw.v\n`include "../rtl/memory_sw.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:5: Cannot find include file: ../rtl/memory_tb.v\n`include "../rtl/memory_tb.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:6: Cannot find include file: ../rtl/shift_register.v\n`include "../rtl/shift_register.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:7: Cannot find include file: ../rtl/SAD.v\n`include "../rtl/SAD.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:8: Cannot find include file: ../rtl/SAD_array.v\n`include "../rtl/SAD_array.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:9: Cannot find include file: ../rtl/me_integer.v\n`include "../rtl/me_integer.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:89: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:92: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_me_integer.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:93: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb_me_integer);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:97: Unsupported: Ignoring delay on this delayed statement.\n #1 rst_n<=1\'bx;clk<=1\'bx;req<=1\'bx;init_pos_h<=6\'dx;init_pos_w<=6\'dx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:98: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD) rst_n<=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:99: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;init_pos_h<=6\'d0;init_pos_w<=6\'d0;\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:100: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:102: syntax error, unexpected \'@\'\n repeat(3) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:105: syntax error, unexpected \'@\'\n while(~ack) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:110: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_integer.v:112: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: Exiting due to 16 error(s), 4 warning(s)\n' | 301,597 | module | module tb_me_integer;
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memory/memory_tb_B.txt";
localparam MEM_TB_C = "../memory/memory_tb_C.txt";
localparam MEM_TB_D = "../memory/memory_tb_D.txt";
reg rst_n;
reg clk;
reg req;
reg [5:0] init_pos_h;
reg [5:0] init_pos_w;
wire [15:0] min_sad;
wire [1:0] min_diff_h;
wire [1:0] min_diff_w;
wire ack;
wire [7:0] pel_sw;
wire [7:0] pel_tb;
wire [11:0] addr_sw;
wire [5:0] addr_sw_h;
wire [5:0] addr_sw_w;
wire [7:0] addr_tb;
me_integer _me_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.init_pos ( {init_pos_w, init_pos_h} ) ,
.min_sad ( min_sad ) ,
.min_diff ( {min_diff_w, min_diff_h} ) ,
.ack ( ack ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.addr_sw ( {addr_sw_w, addr_sw_h} ) ,
.addr_tb ( addr_tb )
);
memory_sw
_memory_sw
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( 10'd0 ) ,
.addr_b ( {addr_sw_w, addr_sw_h} ) ,
.data_a ( ) ,
.data_b ( pel_sw )
);
defparam _memory_sw.MEM_SW_A = MEM_SW_A;
defparam _memory_sw.MEM_SW_B = MEM_SW_B;
defparam _memory_sw.MEM_SW_C = MEM_SW_C;
defparam _memory_sw.MEM_SW_D = MEM_SW_D;
memory_tb
_memory_tb
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( 6'd0 ) ,
.addr_b ( addr_tb ) ,
.data_a ( ) ,
.data_b ( pel_tb )
);
defparam _memory_tb.MEM_TB_A = MEM_TB_A;
defparam _memory_tb.MEM_TB_B = MEM_TB_B;
defparam _memory_tb.MEM_TB_C = MEM_TB_C;
defparam _memory_tb.MEM_TB_D = MEM_TB_D;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_me_integer.vcd");
$dumpvars(0, tb_me_integer);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;init_pos_h<=6'dx;init_pos_w<=6'dx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;init_pos_h<=6'd0;init_pos_w<=6'd0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(3) @(posedge clk);
req<=1;init_pos_h<=6'd44;init_pos_w<=6'd22;
while(~ack) @(posedge clk);
$display("motion vector");
$display(" diff_h : %d", $signed(min_diff_h));
$display(" diff_w : %d", $signed(min_diff_w));
$display(" sad : %d", min_sad);
repeat(10) @(posedge clk);
req<=0;
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | module tb_me_integer; |
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memory/memory_tb_B.txt";
localparam MEM_TB_C = "../memory/memory_tb_C.txt";
localparam MEM_TB_D = "../memory/memory_tb_D.txt";
reg rst_n;
reg clk;
reg req;
reg [5:0] init_pos_h;
reg [5:0] init_pos_w;
wire [15:0] min_sad;
wire [1:0] min_diff_h;
wire [1:0] min_diff_w;
wire ack;
wire [7:0] pel_sw;
wire [7:0] pel_tb;
wire [11:0] addr_sw;
wire [5:0] addr_sw_h;
wire [5:0] addr_sw_w;
wire [7:0] addr_tb;
me_integer _me_integer
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.init_pos ( {init_pos_w, init_pos_h} ) ,
.min_sad ( min_sad ) ,
.min_diff ( {min_diff_w, min_diff_h} ) ,
.ack ( ack ) ,
.pel_sw ( pel_sw ) ,
.pel_tb ( pel_tb ) ,
.addr_sw ( {addr_sw_w, addr_sw_h} ) ,
.addr_tb ( addr_tb )
);
memory_sw
_memory_sw
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( 10'd0 ) ,
.addr_b ( {addr_sw_w, addr_sw_h} ) ,
.data_a ( ) ,
.data_b ( pel_sw )
);
defparam _memory_sw.MEM_SW_A = MEM_SW_A;
defparam _memory_sw.MEM_SW_B = MEM_SW_B;
defparam _memory_sw.MEM_SW_C = MEM_SW_C;
defparam _memory_sw.MEM_SW_D = MEM_SW_D;
memory_tb
_memory_tb
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( 6'd0 ) ,
.addr_b ( addr_tb ) ,
.data_a ( ) ,
.data_b ( pel_tb )
);
defparam _memory_tb.MEM_TB_A = MEM_TB_A;
defparam _memory_tb.MEM_TB_B = MEM_TB_B;
defparam _memory_tb.MEM_TB_C = MEM_TB_C;
defparam _memory_tb.MEM_TB_D = MEM_TB_D;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_me_integer.vcd");
$dumpvars(0, tb_me_integer);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;init_pos_h<=6'dx;init_pos_w<=6'dx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;init_pos_h<=6'd0;init_pos_w<=6'd0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(3) @(posedge clk);
req<=1;init_pos_h<=6'd44;init_pos_w<=6'd22;
while(~ack) @(posedge clk);
$display("motion vector");
$display(" diff_h : %d", $signed(min_diff_h));
$display(" diff_w : %d", $signed(min_diff_w));
$display(" sad : %d", min_sad);
repeat(10) @(posedge clk);
req<=0;
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | 2 |
138,003 | data/full_repos/permissive/81549979/testbench/tb_me_top.v | 81,549,979 | tb_me_top.v | v | 132 | 51 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:1: Cannot find include file: ./memory_dual_port.v\n`include "./memory_dual_port.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v.v\n data/full_repos/permissive/81549979/testbench,data/full_repos/permissive/81549979/./memory_dual_port.v.sv\n ./memory_dual_port.v\n ./memory_dual_port.v.v\n ./memory_dual_port.v.sv\n obj_dir/./memory_dual_port.v\n obj_dir/./memory_dual_port.v.v\n obj_dir/./memory_dual_port.v.sv\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:2: Cannot find include file: ../rtl/memory_sw.v\n`include "../rtl/memory_sw.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:3: Cannot find include file: ../rtl/memory_tb.v\n`include "../rtl/memory_tb.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:4: Cannot find include file: ../rtl/addr_gen.v\n`include "../rtl/addr_gen.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:5: Cannot find include file: ../rtl/control_double.v\n`include "../rtl/control_double.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:6: Cannot find include file: ../rtl/pe.v\n`include "../rtl/pe.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:7: Cannot find include file: ../rtl/pe_line.v\n`include "../rtl/pe_line.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:8: Cannot find include file: ../rtl/shift_register.v\n`include "../rtl/shift_register.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:9: Cannot find include file: ../rtl/sum.v\n`include "../rtl/sum.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:10: Cannot find include file: ../rtl/pe_array.v\n`include "../rtl/pe_array.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:11: Cannot find include file: ../rtl/pa_array.v\n`include "../rtl/pa_array.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:12: Cannot find include file: ../rtl/me_double.v\n`include "../rtl/me_double.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:13: Cannot find include file: ../rtl/addr_gen_integer.v\n`include "../rtl/addr_gen_integer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:14: Cannot find include file: ../rtl/control_integer.v\n`include "../rtl/control_integer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:15: Cannot find include file: ../rtl/SAD.v\n`include "../rtl/SAD.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:16: Cannot find include file: ../rtl/SAD_array.v\n`include "../rtl/SAD_array.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:17: Cannot find include file: ../rtl/me_integer.v\n`include "../rtl/me_integer.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:18: Cannot find include file: ../rtl/control_top.v\n`include "../rtl/control_top.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:19: Cannot find include file: ../rtl/me_top.v\n`include "../rtl/me_top.v" \n ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_top.v:102: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:105: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_me_top.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:106: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb_me_top);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_top.v:110: Unsupported: Ignoring delay on this delayed statement.\n #1 rst_n<=1\'bx;clk<=1\'bx;req<=1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_top.v:111: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD) rst_n<=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/81549979/testbench/tb_me_top.v:112: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:113: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:115: syntax error, unexpected \'@\'\n repeat(3) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:117: syntax error, unexpected \'@\'\n while(~ack) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:122: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/81549979/testbench/tb_me_top.v:124: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: Exiting due to 26 error(s), 4 warning(s)\n' | 301,598 | module | module tb_me_top;
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memory/memory_tb_B.txt";
localparam MEM_TB_C = "../memory/memory_tb_C.txt";
localparam MEM_TB_D = "../memory/memory_tb_D.txt";
reg rst_n;
reg clk;
reg req;
wire [15:0] min_sad;
wire [5:0] min_mvec_h;
wire [5:0] min_mvec_w;
wire ack;
wire [31:0] pel_sw_d;
wire [31:0] pel_tb_d;
wire [9:0] addr_sw_d;
wire [5:0] addr_tb_d;
wire [7:0] pel_sw_i;
wire [7:0] pel_tb_i;
wire [11:0] addr_sw_i;
wire [7:0] addr_tb_i;
me_top _me_top
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.min_sad ( min_sad ) ,
.min_mvec ( {min_mvec_h, min_mvec_w} ) ,
.ack ( ack ) ,
.pel_sw_d ( pel_sw_d ) ,
.pel_tb_d ( pel_tb_d ) ,
.addr_sw_d ( addr_sw_d ) ,
.addr_tb_d ( addr_tb_d ) ,
.pel_sw_i ( pel_sw_i ) ,
.pel_tb_i ( pel_tb_i ) ,
.addr_sw_i ( addr_sw_i ) ,
.addr_tb_i ( addr_tb_i )
);
memory_sw
_memory_sw
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_sw_d ) ,
.addr_b ( addr_sw_i ) ,
.data_a ( pel_sw_d ) ,
.data_b ( pel_sw_i )
);
defparam _memory_sw.MEM_SW_A = MEM_SW_A;
defparam _memory_sw.MEM_SW_B = MEM_SW_B;
defparam _memory_sw.MEM_SW_C = MEM_SW_C;
defparam _memory_sw.MEM_SW_D = MEM_SW_D;
memory_tb
_memory_tb
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_tb_d ) ,
.addr_b ( addr_tb_i ) ,
.data_a ( pel_tb_d ) ,
.data_b ( pel_tb_i )
);
defparam _memory_tb.MEM_TB_A = MEM_TB_A;
defparam _memory_tb.MEM_TB_B = MEM_TB_B;
defparam _memory_tb.MEM_TB_C = MEM_TB_C;
defparam _memory_tb.MEM_TB_D = MEM_TB_D;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_me_top.vcd");
$dumpvars(0, tb_me_top);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(3) @(posedge clk);
req<=1;
while(~ack) @(posedge clk);
$display("motion vector");
$display(" h : %d", min_mvec_h);
$display(" w : %d", min_mvec_w);
$display(" sad: %d", min_sad);
repeat(10) @(posedge clk);
req<=0;
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | module tb_me_top; |
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memory/memory_tb_B.txt";
localparam MEM_TB_C = "../memory/memory_tb_C.txt";
localparam MEM_TB_D = "../memory/memory_tb_D.txt";
reg rst_n;
reg clk;
reg req;
wire [15:0] min_sad;
wire [5:0] min_mvec_h;
wire [5:0] min_mvec_w;
wire ack;
wire [31:0] pel_sw_d;
wire [31:0] pel_tb_d;
wire [9:0] addr_sw_d;
wire [5:0] addr_tb_d;
wire [7:0] pel_sw_i;
wire [7:0] pel_tb_i;
wire [11:0] addr_sw_i;
wire [7:0] addr_tb_i;
me_top _me_top
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.req ( req ) ,
.min_sad ( min_sad ) ,
.min_mvec ( {min_mvec_h, min_mvec_w} ) ,
.ack ( ack ) ,
.pel_sw_d ( pel_sw_d ) ,
.pel_tb_d ( pel_tb_d ) ,
.addr_sw_d ( addr_sw_d ) ,
.addr_tb_d ( addr_tb_d ) ,
.pel_sw_i ( pel_sw_i ) ,
.pel_tb_i ( pel_tb_i ) ,
.addr_sw_i ( addr_sw_i ) ,
.addr_tb_i ( addr_tb_i )
);
memory_sw
_memory_sw
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_sw_d ) ,
.addr_b ( addr_sw_i ) ,
.data_a ( pel_sw_d ) ,
.data_b ( pel_sw_i )
);
defparam _memory_sw.MEM_SW_A = MEM_SW_A;
defparam _memory_sw.MEM_SW_B = MEM_SW_B;
defparam _memory_sw.MEM_SW_C = MEM_SW_C;
defparam _memory_sw.MEM_SW_D = MEM_SW_D;
memory_tb
_memory_tb
(
.rst_n ( rst_n ) ,
.clk ( clk ) ,
.addr_a ( addr_tb_d ) ,
.addr_b ( addr_tb_i ) ,
.data_a ( pel_tb_d ) ,
.data_b ( pel_tb_i )
);
defparam _memory_tb.MEM_TB_A = MEM_TB_A;
defparam _memory_tb.MEM_TB_B = MEM_TB_B;
defparam _memory_tb.MEM_TB_C = MEM_TB_C;
defparam _memory_tb.MEM_TB_D = MEM_TB_D;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_me_top.vcd");
$dumpvars(0, tb_me_top);
end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;req<=1'bx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;req<=0;
repeat(5) @(posedge clk);
rst_n<=1;
repeat(3) @(posedge clk);
req<=1;
while(~ack) @(posedge clk);
$display("motion vector");
$display(" h : %d", min_mvec_h);
$display(" w : %d", min_mvec_w);
$display(" sad: %d", min_sad);
repeat(10) @(posedge clk);
req<=0;
repeat(10) @(posedge clk);
$finish(2);
end
endmodule | 2 |
138,004 | data/full_repos/permissive/81582723/alu.v | 81,582,723 | alu.v | v | 35 | 77 | [] | [] | [] | [(8, 34)] | null | data/verilator_xmls/b226a965-2128-45b1-ba96-74b2d4636976.xml | null | 301,599 | module | module alu (input [7:0] a,b,
input [3:0] opcode,
output reg [7:0] y);
reg [7:0] o, an, n, x, add, sub, rs, rsn;
always @* begin
o <= a | b;
an <= a & b;
n <= ~a;
x <= a ^ b;
add <= a + b;
sub <= a - b;
rs <= a >> 1;
rsn <= a >> b;
case (opcode)
4'h0: y <= o;
4'h1: y <= an;
4'h2: y <= n;
4'h3: y <= x;
4'h4: y <= add;
4'h5: y <= sub;
4'h6: y <= rs;
4'h7: y <= rsn;
default: y <= 8'bZ;
endcase
end
endmodule | module alu (input [7:0] a,b,
input [3:0] opcode,
output reg [7:0] y); |
reg [7:0] o, an, n, x, add, sub, rs, rsn;
always @* begin
o <= a | b;
an <= a & b;
n <= ~a;
x <= a ^ b;
add <= a + b;
sub <= a - b;
rs <= a >> 1;
rsn <= a >> b;
case (opcode)
4'h0: y <= o;
4'h1: y <= an;
4'h2: y <= n;
4'h3: y <= x;
4'h4: y <= add;
4'h5: y <= sub;
4'h6: y <= rs;
4'h7: y <= rsn;
default: y <= 8'bZ;
endcase
end
endmodule | 1 |
138,005 | data/full_repos/permissive/81582723/control_unit.v | 81,582,723 | control_unit.v | v | 175 | 93 | [] | [] | [] | [(8, 157), (159, 174)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/81582723/control_unit.v:159: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'control\'\nmodule control (input clk, reset, interrupt,\n ^~~~~~~\n : ... Top module \'pc\'\nmodule pc(input clk, reset, jump,\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81582723/control_unit.v:52: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance control\n {instruction, regfile_data, usermem_data_out, usermem_address} <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81582723/control_unit.v:53: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance control\n {rw, regfile_regwrite} <= 1\'b0;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 301,600 | module | module control (input clk, reset, interrupt,
input [7:0] datamem_data, datamem_address, regfile_out1,
input [7:0] regfile_out2, alu_out, usermem_data_in,
output reg [3:0] alu_opcode,
output reg [7:0] regfile_data,usermem_data_out,
output reg [1:0] regfile_read1, regfile_read2, regfile_writereg,
output reg [7:0] usermem_address, pc_jmpaddr,
output reg rw, regfile_regwrite, pc_jump);
parameter state0 = 3'b001;
parameter state1 = 3'b010;
parameter state2 = 3'b100;
reg [2:0] stage;
reg [7:0] instruction_c;
reg [7:0] instruction;
reg [7:0] prevaddr;
reg is_onecyc;
reg is_rts;
reg is_nop;
reg eq;
always @(*) begin
instruction_c <= datamem_data;
is_onecyc <= (instruction_c[7:4] <= 4'h7);
is_rts <= (instruction_c[7:4] == 4'hb);
is_nop <= (instruction_c == 8'h9f);
alu_opcode <= instruction_c[7:4];
regfile_read1 <= is_onecyc ? instruction_c[3:2] : instruction[3:2];
regfile_read2 <= is_onecyc ? instruction_c[1:0] : instruction[1:0];
regfile_writereg <= instruction[1:0];
eq <= (regfile_out1 == regfile_out2);
end
always @(posedge clk)
if(interrupt == 1)
begin
prevaddr <= datamem_address;
pc_jump <= 1;
pc_jmpaddr <= 8'hfd;
stage <= state2;
end
else if(reset == 1)
begin
{instruction, regfile_data, usermem_data_out, usermem_address} <= 8'b0;
{rw, regfile_regwrite} <= 1'b0;
pc_jump <= 1;
pc_jmpaddr <= 8'b0;
stage <= state2;
end
else if (stage == state0)
begin
rw <= 0;
instruction <= datamem_data;
if (is_onecyc)
begin
rw <= 0;
regfile_regwrite <= 1;
regfile_data <= alu_out;
stage <= state0;
end
else if (is_onecyc == 0)
if (is_rts)
begin
pc_jump <= 1;
regfile_regwrite <= 0;
pc_jmpaddr <= prevaddr + 1;
stage <= state2;
end
else if (is_rts == 0)
if (is_nop)
stage <= state0;
else
stage <= state1;
end
else if (stage == state1)
begin
pc_jmpaddr <= datamem_data;
case (instruction[7:4])
4'h8:
begin
rw <= 0;
regfile_regwrite <= 1;
regfile_data <= datamem_data;
stage <= state0;
end
4'h9:
begin
regfile_regwrite <= 0;
rw <= 0;
pc_jump <= 1;
stage <= state2;
end
4'ha:
begin
regfile_regwrite <= 0;
rw <= 0;
prevaddr <= datamem_address;
pc_jump <= 1;
stage <= state2;
end
4'hc:
begin
rw <= 0;
regfile_regwrite <= 0;
if(eq)
begin
prevaddr <= datamem_address;
pc_jump <= 1;
end
stage <= state2;
end
4'hd:
begin
rw <= 0;
regfile_regwrite <= 0;
if(eq == 0)
begin
prevaddr <= datamem_address;
pc_jump <= 1;
end
stage <= state2;
end
4'he:
begin
rw <= 1;
regfile_regwrite <= 0;
usermem_address <= datamem_data;
usermem_data_out <= regfile_out1;
stage <= state0;
end
4'hf:
begin
rw <= 0;
usermem_address <= datamem_data;
regfile_regwrite <= 1;
regfile_data <= usermem_data_in;
stage <= state0;
end
endcase
end
else if(stage == state2)
begin
instruction <= datamem_data;
pc_jump <= 0;
stage <= state0;
end
endmodule | module control (input clk, reset, interrupt,
input [7:0] datamem_data, datamem_address, regfile_out1,
input [7:0] regfile_out2, alu_out, usermem_data_in,
output reg [3:0] alu_opcode,
output reg [7:0] regfile_data,usermem_data_out,
output reg [1:0] regfile_read1, regfile_read2, regfile_writereg,
output reg [7:0] usermem_address, pc_jmpaddr,
output reg rw, regfile_regwrite, pc_jump); |
parameter state0 = 3'b001;
parameter state1 = 3'b010;
parameter state2 = 3'b100;
reg [2:0] stage;
reg [7:0] instruction_c;
reg [7:0] instruction;
reg [7:0] prevaddr;
reg is_onecyc;
reg is_rts;
reg is_nop;
reg eq;
always @(*) begin
instruction_c <= datamem_data;
is_onecyc <= (instruction_c[7:4] <= 4'h7);
is_rts <= (instruction_c[7:4] == 4'hb);
is_nop <= (instruction_c == 8'h9f);
alu_opcode <= instruction_c[7:4];
regfile_read1 <= is_onecyc ? instruction_c[3:2] : instruction[3:2];
regfile_read2 <= is_onecyc ? instruction_c[1:0] : instruction[1:0];
regfile_writereg <= instruction[1:0];
eq <= (regfile_out1 == regfile_out2);
end
always @(posedge clk)
if(interrupt == 1)
begin
prevaddr <= datamem_address;
pc_jump <= 1;
pc_jmpaddr <= 8'hfd;
stage <= state2;
end
else if(reset == 1)
begin
{instruction, regfile_data, usermem_data_out, usermem_address} <= 8'b0;
{rw, regfile_regwrite} <= 1'b0;
pc_jump <= 1;
pc_jmpaddr <= 8'b0;
stage <= state2;
end
else if (stage == state0)
begin
rw <= 0;
instruction <= datamem_data;
if (is_onecyc)
begin
rw <= 0;
regfile_regwrite <= 1;
regfile_data <= alu_out;
stage <= state0;
end
else if (is_onecyc == 0)
if (is_rts)
begin
pc_jump <= 1;
regfile_regwrite <= 0;
pc_jmpaddr <= prevaddr + 1;
stage <= state2;
end
else if (is_rts == 0)
if (is_nop)
stage <= state0;
else
stage <= state1;
end
else if (stage == state1)
begin
pc_jmpaddr <= datamem_data;
case (instruction[7:4])
4'h8:
begin
rw <= 0;
regfile_regwrite <= 1;
regfile_data <= datamem_data;
stage <= state0;
end
4'h9:
begin
regfile_regwrite <= 0;
rw <= 0;
pc_jump <= 1;
stage <= state2;
end
4'ha:
begin
regfile_regwrite <= 0;
rw <= 0;
prevaddr <= datamem_address;
pc_jump <= 1;
stage <= state2;
end
4'hc:
begin
rw <= 0;
regfile_regwrite <= 0;
if(eq)
begin
prevaddr <= datamem_address;
pc_jump <= 1;
end
stage <= state2;
end
4'hd:
begin
rw <= 0;
regfile_regwrite <= 0;
if(eq == 0)
begin
prevaddr <= datamem_address;
pc_jump <= 1;
end
stage <= state2;
end
4'he:
begin
rw <= 1;
regfile_regwrite <= 0;
usermem_address <= datamem_data;
usermem_data_out <= regfile_out1;
stage <= state0;
end
4'hf:
begin
rw <= 0;
usermem_address <= datamem_data;
regfile_regwrite <= 1;
regfile_data <= usermem_data_in;
stage <= state0;
end
endcase
end
else if(stage == state2)
begin
instruction <= datamem_data;
pc_jump <= 0;
stage <= state0;
end
endmodule | 1 |
138,006 | data/full_repos/permissive/81582723/control_unit.v | 81,582,723 | control_unit.v | v | 175 | 93 | [] | [] | [] | [(8, 157), (159, 174)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/81582723/control_unit.v:159: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'control\'\nmodule control (input clk, reset, interrupt,\n ^~~~~~~\n : ... Top module \'pc\'\nmodule pc(input clk, reset, jump,\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81582723/control_unit.v:52: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance control\n {instruction, regfile_data, usermem_data_out, usermem_address} <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81582723/control_unit.v:53: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance control\n {rw, regfile_regwrite} <= 1\'b0;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 301,600 | module | module pc(input clk, reset, jump,
input [7:0] jmpaddr,
output reg[7:0] data);
always @(posedge clk) begin
if (reset == 1)
data <= 8'b0;
else if (reset == 0)
begin
if (jump == 1)
data <= jmpaddr;
else
data <= data + 1;
end
end
endmodule | module pc(input clk, reset, jump,
input [7:0] jmpaddr,
output reg[7:0] data); |
always @(posedge clk) begin
if (reset == 1)
data <= 8'b0;
else if (reset == 0)
begin
if (jump == 1)
data <= jmpaddr;
else
data <= data + 1;
end
end
endmodule | 1 |
138,010 | data/full_repos/permissive/81582723/regfile.v | 81,582,723 | regfile.v | v | 27 | 85 | [] | [] | [] | [(8, 26)] | null | data/verilator_xmls/c70cc247-6dba-45b6-ae0b-e66a851d27a1.xml | null | 301,603 | module | module regfile (input [1:0] readreg1, readreg2, writereg,
input [7:0] data,
input clk, regwrite,
output [7:0] read1, read2);
reg [7:0] registerfile [3:0];
initial begin
registerfile[2'd0] <= 8'b0;
registerfile[2'd1] <= 8'b0;
registerfile[2'd2] <= 8'b0;
registerfile[2'd3] <= 8'b0;
end
always @(posedge clk) begin
if(regwrite == 1)
registerfile[writereg] <= data;
end
assign read1 = (regwrite && readreg1 == writereg)? data: registerfile[readreg1];
assign read2 = regwrite? data: registerfile[readreg2];
endmodule | module regfile (input [1:0] readreg1, readreg2, writereg,
input [7:0] data,
input clk, regwrite,
output [7:0] read1, read2); |
reg [7:0] registerfile [3:0];
initial begin
registerfile[2'd0] <= 8'b0;
registerfile[2'd1] <= 8'b0;
registerfile[2'd2] <= 8'b0;
registerfile[2'd3] <= 8'b0;
end
always @(posedge clk) begin
if(regwrite == 1)
registerfile[writereg] <= data;
end
assign read1 = (regwrite && readreg1 == writereg)? data: registerfile[readreg1];
assign read2 = regwrite? data: registerfile[readreg2];
endmodule | 1 |
138,019 | data/full_repos/permissive/81638292/Verilog/Core/CPU.v | 81,638,292 | CPU.v | v | 46 | 447 | [] | [] | [] | [(6, 46)] | null | null | 1: b"%Error: data/full_repos/permissive/81638292/Verilog/Core/CPU.v:39: Cannot find file containing module: 'ProgramCounter'\nProgramCounter pc(.clk(clk), .rst(rst), .addr(romaddr), .next_addr(next_addr));\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81638292/Verilog/Core,data/full_repos/permissive/81638292/ProgramCounter\n data/full_repos/permissive/81638292/Verilog/Core,data/full_repos/permissive/81638292/ProgramCounter.v\n data/full_repos/permissive/81638292/Verilog/Core,data/full_repos/permissive/81638292/ProgramCounter.sv\n ProgramCounter\n ProgramCounter.v\n ProgramCounter.sv\n obj_dir/ProgramCounter\n obj_dir/ProgramCounter.v\n obj_dir/ProgramCounter.sv\n%Error: data/full_repos/permissive/81638292/Verilog/Core/CPU.v:41: Cannot find file containing module: 'DataPath'\n%Error: data/full_repos/permissive/81638292/Verilog/Core/CPU.v:43: Cannot find file containing module: 'Decoder'\nDecoder dc(.word(romout), .Z(Z), .C(C), .N(N), .V(V), .rs1(rs1), .rs2(rs2), .rd(rd), .alu_op(alu_op), .imm_uj(imm_uj), .imm_u(imm_u), .imm_i(imm_i), .imm_s(imm_s), .imm_sb(imm_sb), .r(r), .uj(uj), .u(u), .u_control(u_control), .i(i), .s(s), .sb(sb), .load_pc(load_pc), .mem_read(mem_read), .mem_read_sext(mem_read_sext), .iobytes(iobytes), .imm_sext(imm_sext));\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 301,612 | module | module CPU(
clk,
rst,
memout,
memwrite,
memin,
memaddr,
romout,
romaddr,
iobytes
);
input clk, rst;
input [31:0] memout;
input [31:0] romout;
output memwrite;
output [31:0] memin;
output [31:0] memaddr;
output [31:0] romaddr;
output [3:0] iobytes;
wire Z, C, N, V;
wire [4:0] rs1, rs2, rd;
wire [31:0] imm_uj, imm_u, imm_i, imm_s, imm_sb, next_addr, o;
wire [3:0] alu_op;
wire r, uj, u, u_control, i, s, sb;
wire load_pc, mem_read, mem_read_sext, imm_sext;
assign memwrite = s;
assign memaddr = o;
ProgramCounter pc(.clk(clk), .rst(rst), .addr(romaddr), .next_addr(next_addr));
DataPath dp(.pc(romaddr), .clk(clk), .memin(memin), .next_addr(next_addr), .rst(rst), .rs1(rs1), .rs2(rs2), .rd(rd), .alu_op(alu_op), .imm_uj(imm_uj), .imm_u(imm_u), .imm_i(imm_i), .imm_s(imm_s), .imm_sb(imm_sb), .memout(memout), .o(o), .r(r), .uj(uj), .u(u), .u_control(u_control), .i(i), .s(s), .sb(sb), .load_pc(load_pc), .mem_read(mem_read), .mem_read_sext(mem_read_sext), .iobytes(iobytes), .Z(Z), .C(C), .N(N), .V(V), .imm_sext(imm_sext));
Decoder dc(.word(romout), .Z(Z), .C(C), .N(N), .V(V), .rs1(rs1), .rs2(rs2), .rd(rd), .alu_op(alu_op), .imm_uj(imm_uj), .imm_u(imm_u), .imm_i(imm_i), .imm_s(imm_s), .imm_sb(imm_sb), .r(r), .uj(uj), .u(u), .u_control(u_control), .i(i), .s(s), .sb(sb), .load_pc(load_pc), .mem_read(mem_read), .mem_read_sext(mem_read_sext), .iobytes(iobytes), .imm_sext(imm_sext));
endmodule | module CPU(
clk,
rst,
memout,
memwrite,
memin,
memaddr,
romout,
romaddr,
iobytes
); |
input clk, rst;
input [31:0] memout;
input [31:0] romout;
output memwrite;
output [31:0] memin;
output [31:0] memaddr;
output [31:0] romaddr;
output [3:0] iobytes;
wire Z, C, N, V;
wire [4:0] rs1, rs2, rd;
wire [31:0] imm_uj, imm_u, imm_i, imm_s, imm_sb, next_addr, o;
wire [3:0] alu_op;
wire r, uj, u, u_control, i, s, sb;
wire load_pc, mem_read, mem_read_sext, imm_sext;
assign memwrite = s;
assign memaddr = o;
ProgramCounter pc(.clk(clk), .rst(rst), .addr(romaddr), .next_addr(next_addr));
DataPath dp(.pc(romaddr), .clk(clk), .memin(memin), .next_addr(next_addr), .rst(rst), .rs1(rs1), .rs2(rs2), .rd(rd), .alu_op(alu_op), .imm_uj(imm_uj), .imm_u(imm_u), .imm_i(imm_i), .imm_s(imm_s), .imm_sb(imm_sb), .memout(memout), .o(o), .r(r), .uj(uj), .u(u), .u_control(u_control), .i(i), .s(s), .sb(sb), .load_pc(load_pc), .mem_read(mem_read), .mem_read_sext(mem_read_sext), .iobytes(iobytes), .Z(Z), .C(C), .N(N), .V(V), .imm_sext(imm_sext));
Decoder dc(.word(romout), .Z(Z), .C(C), .N(N), .V(V), .rs1(rs1), .rs2(rs2), .rd(rd), .alu_op(alu_op), .imm_uj(imm_uj), .imm_u(imm_u), .imm_i(imm_i), .imm_s(imm_s), .imm_sb(imm_sb), .r(r), .uj(uj), .u(u), .u_control(u_control), .i(i), .s(s), .sb(sb), .load_pc(load_pc), .mem_read(mem_read), .mem_read_sext(mem_read_sext), .iobytes(iobytes), .imm_sext(imm_sext));
endmodule | 2 |
138,021 | data/full_repos/permissive/81638292/Verilog/Core/Decoder.v | 81,638,292 | Decoder.v | v | 81 | 130 | [] | [] | [] | [(6, 81)] | null | null | 1: b"%Error: data/full_repos/permissive/81638292/Verilog/Core/Decoder.v:71: Cannot find file containing module: 'Mux8'\nMux8 #(1) mux8(.A(Z), .B(~Z), .C(1'b0), .D(1'b0), .E(signed_comp), .F(~signed_comp), .G(N), .H(~N), .sel(funct3), .O(condition));\n^~~~\n ... Looked in:\n data/full_repos/permissive/81638292/Verilog/Core,data/full_repos/permissive/81638292/Mux8\n data/full_repos/permissive/81638292/Verilog/Core,data/full_repos/permissive/81638292/Mux8.v\n data/full_repos/permissive/81638292/Verilog/Core,data/full_repos/permissive/81638292/Mux8.sv\n Mux8\n Mux8.v\n Mux8.sv\n obj_dir/Mux8\n obj_dir/Mux8.v\n obj_dir/Mux8.sv\n%Error: data/full_repos/permissive/81638292/Verilog/Core/Decoder.v:76: Cannot find file containing module: 'Mux4'\nMux4 #(4) mux4(.A(4'b0001), .B(4'b0011), .C(4'b1111), .D(4'b0000), .sel(funct3[1:0]), .O(iobytes));\n^~~~\n%Error: Exiting due to 2 error(s)\n" | 301,614 | module | module Decoder(
word,
Z,
C,
N,
V,
rs1,
rs2,
rd,
alu_op,
imm_uj,
imm_u,
imm_i,
imm_s,
imm_sb,
imm_sext,
r,
uj,
u,
u_control,
i,
s,
sb,
load_pc,
mem_read,
mem_read_sext,
iobytes
);
input [31:0] word;
input Z, C, N, V;
output [4:0] rs1, rs2, rd;
output [31:0] imm_uj, imm_u, imm_i, imm_s, imm_sb;
output [3:0] alu_op;
output r, uj, u, u_control, i, s, sb;
output load_pc, mem_read, mem_read_sext, imm_sext;
output [3:0] iobytes;
wire arith, load_store;
wire [2:0] funct3;
wire condition, signed_comp;
assign funct3 = word[14:12];
assign u_control = (word[5]);
assign arith = (word[4:2] === 3'b100);
assign load_store = (word[4:2] === 3'b000) & ~word[6];
assign u = (word[4:2] === 3'b101);
assign uj = (word[4:2] === 3'b011);
assign r = arith & word[5];
assign i = (arith | load_store) & (~word[5]);
assign s = load_store & word[5] & ~word[6];
assign sb = load_store & word[6];
assign rd = word[11:7];
assign rs1 = word[19:15];
assign rs2 = word[24:20];
assign imm_uj = {{11{word[31]}}, word[31], word[19:12], word[20], word[30:21], 1'b0};
assign imm_u = {word[31:12], 12'b0};
assign imm_i = {{20{word[31]}}, word[31:20]};
assign imm_s = {{20{word[31]}}, word[31:25], word[11:7]};
assign imm_sb = {{19{word[31]}}, word[31], word[7], word[30:25], word[11:8], 1'b0};
assign signed_comp = (V)? ~N: N;
assign imm_sext = (arith & (funct3 === 3'b011));
Mux8 #(1) mux8(.A(Z), .B(~Z), .C(1'b0), .D(1'b0), .E(signed_comp), .F(~signed_comp), .G(N), .H(~N), .sel(funct3), .O(condition));
assign load_pc = (word[6] & condition) | (word[6] & word[2]);
assign alu_op = arith? { ((r | (funct3 === 3'b101)) & word[30]), funct3}: {~load_store, 3'b000};
Mux4 #(4) mux4(.A(4'b0001), .B(4'b0011), .C(4'b1111), .D(4'b0000), .sel(funct3[1:0]), .O(iobytes));
assign mem_read = load_store & ~(s);
assign mem_read_sext = ~funct3[2];
endmodule | module Decoder(
word,
Z,
C,
N,
V,
rs1,
rs2,
rd,
alu_op,
imm_uj,
imm_u,
imm_i,
imm_s,
imm_sb,
imm_sext,
r,
uj,
u,
u_control,
i,
s,
sb,
load_pc,
mem_read,
mem_read_sext,
iobytes
); |
input [31:0] word;
input Z, C, N, V;
output [4:0] rs1, rs2, rd;
output [31:0] imm_uj, imm_u, imm_i, imm_s, imm_sb;
output [3:0] alu_op;
output r, uj, u, u_control, i, s, sb;
output load_pc, mem_read, mem_read_sext, imm_sext;
output [3:0] iobytes;
wire arith, load_store;
wire [2:0] funct3;
wire condition, signed_comp;
assign funct3 = word[14:12];
assign u_control = (word[5]);
assign arith = (word[4:2] === 3'b100);
assign load_store = (word[4:2] === 3'b000) & ~word[6];
assign u = (word[4:2] === 3'b101);
assign uj = (word[4:2] === 3'b011);
assign r = arith & word[5];
assign i = (arith | load_store) & (~word[5]);
assign s = load_store & word[5] & ~word[6];
assign sb = load_store & word[6];
assign rd = word[11:7];
assign rs1 = word[19:15];
assign rs2 = word[24:20];
assign imm_uj = {{11{word[31]}}, word[31], word[19:12], word[20], word[30:21], 1'b0};
assign imm_u = {word[31:12], 12'b0};
assign imm_i = {{20{word[31]}}, word[31:20]};
assign imm_s = {{20{word[31]}}, word[31:25], word[11:7]};
assign imm_sb = {{19{word[31]}}, word[31], word[7], word[30:25], word[11:8], 1'b0};
assign signed_comp = (V)? ~N: N;
assign imm_sext = (arith & (funct3 === 3'b011));
Mux8 #(1) mux8(.A(Z), .B(~Z), .C(1'b0), .D(1'b0), .E(signed_comp), .F(~signed_comp), .G(N), .H(~N), .sel(funct3), .O(condition));
assign load_pc = (word[6] & condition) | (word[6] & word[2]);
assign alu_op = arith? { ((r | (funct3 === 3'b101)) & word[30]), funct3}: {~load_store, 3'b000};
Mux4 #(4) mux4(.A(4'b0001), .B(4'b0011), .C(4'b1111), .D(4'b0000), .sel(funct3[1:0]), .O(iobytes));
assign mem_read = load_store & ~(s);
assign mem_read_sext = ~funct3[2];
endmodule | 2 |
138,023 | data/full_repos/permissive/81638292/Verilog/Core/Mux.v | 81,638,292 | Mux.v | v | 37 | 49 | [] | [] | [] | [(6, 12), (14, 24), (26, 36)] | null | data/verilator_xmls/04dcbb3c-07df-4416-a725-2d2f3e21093a.xml | null | 301,616 | module | module Mux2(A, B, sel, O);
parameter width = 32;
input sel;
input [width - 1:0] A, B;
output [width - 1:0] O;
assign O = (sel)? B : A;
endmodule | module Mux2(A, B, sel, O); |
parameter width = 32;
input sel;
input [width - 1:0] A, B;
output [width - 1:0] O;
assign O = (sel)? B : A;
endmodule | 2 |
138,024 | data/full_repos/permissive/81638292/Verilog/Core/Mux.v | 81,638,292 | Mux.v | v | 37 | 49 | [] | [] | [] | [(6, 12), (14, 24), (26, 36)] | null | data/verilator_xmls/04dcbb3c-07df-4416-a725-2d2f3e21093a.xml | null | 301,616 | module | module Mux4(A, B, C, D, sel, O);
parameter width = 32;
input [1:0] sel;
input [width - 1:0] A, B, C, D;
output [width - 1:0] O;
wire [width - 1:0] w1, w2;
Mux2 #(width) m1(A, B, sel[0], w1);
Mux2 #(width) m2(C, D, sel[0], w2);
Mux2 #(width) m3(w1, w2, sel[1], O);
endmodule | module Mux4(A, B, C, D, sel, O); |
parameter width = 32;
input [1:0] sel;
input [width - 1:0] A, B, C, D;
output [width - 1:0] O;
wire [width - 1:0] w1, w2;
Mux2 #(width) m1(A, B, sel[0], w1);
Mux2 #(width) m2(C, D, sel[0], w2);
Mux2 #(width) m3(w1, w2, sel[1], O);
endmodule | 2 |
138,025 | data/full_repos/permissive/81638292/Verilog/Core/Mux.v | 81,638,292 | Mux.v | v | 37 | 49 | [] | [] | [] | [(6, 12), (14, 24), (26, 36)] | null | data/verilator_xmls/04dcbb3c-07df-4416-a725-2d2f3e21093a.xml | null | 301,616 | module | module Mux8(A, B, C, D, E, F, G, H, sel, O);
parameter width = 32;
input [2:0] sel;
input [width - 1:0] A, B, C, D, E, F, G, H;
output [width - 1:0] O;
wire [width - 1:0] w1, w2;
Mux4 #(width) m1(A, B, C, D, sel[1:0], w1);
Mux4 #(width) m2(E, F, G, H, sel[1:0], w2);
Mux2 #(width) m3(w1, w2, sel[2], O);
endmodule | module Mux8(A, B, C, D, E, F, G, H, sel, O); |
parameter width = 32;
input [2:0] sel;
input [width - 1:0] A, B, C, D, E, F, G, H;
output [width - 1:0] O;
wire [width - 1:0] w1, w2;
Mux4 #(width) m1(A, B, C, D, sel[1:0], w1);
Mux4 #(width) m2(E, F, G, H, sel[1:0], w2);
Mux2 #(width) m3(w1, w2, sel[2], O);
endmodule | 2 |
138,026 | data/full_repos/permissive/81638292/Verilog/Core/ProgramCounter.v | 81,638,292 | ProgramCounter.v | v | 19 | 50 | [] | [] | [] | [(6, 18)] | null | data/verilator_xmls/f1c9d995-ff87-4a99-98af-3f5198722908.xml | null | 301,617 | module | module ProgramCounter(clk, rst, next_addr, addr);
parameter memorySize = 16;
input clk, rst;
input [31:0] next_addr;
output reg [31:0] addr;
always @ (posedge clk) begin
if (rst)
addr <= 32'b0;
else
addr <= addr + next_addr;
end
endmodule | module ProgramCounter(clk, rst, next_addr, addr); |
parameter memorySize = 16;
input clk, rst;
input [31:0] next_addr;
output reg [31:0] addr;
always @ (posedge clk) begin
if (rst)
addr <= 32'b0;
else
addr <= addr + next_addr;
end
endmodule | 2 |
138,028 | data/full_repos/permissive/81638292/Verilog/Verification/CPU_tb.v | 81,638,292 | CPU_tb.v | v | 79 | 39 | [] | [] | [] | [(7, 79)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/81638292/Verilog/Verification/CPU_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/81638292/Verilog/Verification/CPU_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #101;\n ^\n%Error: data/full_repos/permissive/81638292/Verilog/Verification/CPU_tb.v:24: Cannot find file containing module: \'CPU\'\n CPU uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/81638292/Verilog/Verification,data/full_repos/permissive/81638292/CPU\n data/full_repos/permissive/81638292/Verilog/Verification,data/full_repos/permissive/81638292/CPU.v\n data/full_repos/permissive/81638292/Verilog/Verification,data/full_repos/permissive/81638292/CPU.sv\n CPU\n CPU.v\n CPU.sv\n obj_dir/CPU\n obj_dir/CPU.v\n obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,619 | module | module CPU_tb;
reg clk;
reg rst;
reg [31: 0] memout;
wire [31: 0] romout;
wire [31: 0] memin;
wire [31: 0] memaddr;
wire [31: 0] romaddr;
wire [3: 0] iobytes;
wire memwrite;
CPU uut (
.clk(clk),
.rst(rst),
.memout(memout),
.romout(romout),
.memin(memin),
.memwrite(memwrite),
.memaddr(memaddr),
.romaddr(romaddr),
.iobytes(iobytes)
);
always #5 clk = ~clk;
reg [31:0] rom [15:0];
initial begin
rom[0] = 32'hFFC12403;
rom[1] = 32'hFFC10113;
rom[2] = 32'h01041293;
rom[3] = 32'hFE512E23;
rom[4] = 32'hFFC10113;
rom[5] = 32'hFFFF04B7;
rom[6] = 32'h009472B3;
rom[7] = 32'hFE512E23;
rom[8] = 32'hFFC10113;
rom[9] = 32'h0000006F;
end
assign romout = rom[romaddr[5:2]];
initial begin
clk = 0;
rst = 1;
memout = 32'hABCD4321;
#101;
rst = 0;
end
endmodule | module CPU_tb; |
reg clk;
reg rst;
reg [31: 0] memout;
wire [31: 0] romout;
wire [31: 0] memin;
wire [31: 0] memaddr;
wire [31: 0] romaddr;
wire [3: 0] iobytes;
wire memwrite;
CPU uut (
.clk(clk),
.rst(rst),
.memout(memout),
.romout(romout),
.memin(memin),
.memwrite(memwrite),
.memaddr(memaddr),
.romaddr(romaddr),
.iobytes(iobytes)
);
always #5 clk = ~clk;
reg [31:0] rom [15:0];
initial begin
rom[0] = 32'hFFC12403;
rom[1] = 32'hFFC10113;
rom[2] = 32'h01041293;
rom[3] = 32'hFE512E23;
rom[4] = 32'hFFC10113;
rom[5] = 32'hFFFF04B7;
rom[6] = 32'h009472B3;
rom[7] = 32'hFE512E23;
rom[8] = 32'hFFC10113;
rom[9] = 32'h0000006F;
end
assign romout = rom[romaddr[5:2]];
initial begin
clk = 0;
rst = 1;
memout = 32'hABCD4321;
#101;
rst = 0;
end
endmodule | 2 |
138,029 | data/full_repos/permissive/81638292/Verilog/Xilinx/CleanInput.v | 81,638,292 | CleanInput.v | v | 54 | 61 | [] | [] | [] | [(6, 20), (22, 31), (33, 43), (45, 53)] | null | data/verilator_xmls/01e2664a-860e-4103-919c-3ca11c385894.xml | null | 301,620 | module | module D_FF (clk, rst, D, Q);
input clk, rst, D;
output reg Q;
always @(posedge clk or posedge rst) begin
if (rst) begin
Q <= 1'b0;
end
else begin
Q <= D;
end
end
endmodule | module D_FF (clk, rst, D, Q); |
input clk, rst, D;
output reg Q;
always @(posedge clk or posedge rst) begin
if (rst) begin
Q <= 1'b0;
end
else begin
Q <= D;
end
end
endmodule | 2 |
138,030 | data/full_repos/permissive/81638292/Verilog/Xilinx/CleanInput.v | 81,638,292 | CleanInput.v | v | 54 | 61 | [] | [] | [] | [(6, 20), (22, 31), (33, 43), (45, 53)] | null | data/verilator_xmls/01e2664a-860e-4103-919c-3ca11c385894.xml | null | 301,620 | module | module Debouncer(clk, rst, sig, stb);
input clk, rst, sig;
output stb;
wire q[1:0];
D_FF f1(.clk(clk), .rst(rst), .D(sig), .Q(q[0]));
D_FF f2(.clk(clk), .rst(rst), .D(q[0]), .Q(stb));
endmodule | module Debouncer(clk, rst, sig, stb); |
input clk, rst, sig;
output stb;
wire q[1:0];
D_FF f1(.clk(clk), .rst(rst), .D(sig), .Q(q[0]));
D_FF f2(.clk(clk), .rst(rst), .D(q[0]), .Q(stb));
endmodule | 2 |
138,031 | data/full_repos/permissive/81638292/Verilog/Xilinx/CleanInput.v | 81,638,292 | CleanInput.v | v | 54 | 61 | [] | [] | [] | [(6, 20), (22, 31), (33, 43), (45, 53)] | null | data/verilator_xmls/01e2664a-860e-4103-919c-3ca11c385894.xml | null | 301,620 | module | module Synchronizer(clk, rst, sig, stb);
input clk, rst, sig;
output stb;
wire q[2:0];
D_FF f1(.clk(clk), .rst(rst), .D(sig), .Q(q[0]));
D_FF f2(.clk(clk), .rst(rst), .D(q[0]), .Q(q[1]));
assign stb = q[0] && q[1];
endmodule | module Synchronizer(clk, rst, sig, stb); |
input clk, rst, sig;
output stb;
wire q[2:0];
D_FF f1(.clk(clk), .rst(rst), .D(sig), .Q(q[0]));
D_FF f2(.clk(clk), .rst(rst), .D(q[0]), .Q(q[1]));
assign stb = q[0] && q[1];
endmodule | 2 |
138,032 | data/full_repos/permissive/81638292/Verilog/Xilinx/CleanInput.v | 81,638,292 | CleanInput.v | v | 54 | 61 | [] | [] | [] | [(6, 20), (22, 31), (33, 43), (45, 53)] | null | data/verilator_xmls/01e2664a-860e-4103-919c-3ca11c385894.xml | null | 301,620 | module | module Cleaner(clk, rst, sig, stb);
input clk, rst, sig;
output stb;
wire q;
Debouncer d(.clk(clk), .rst(rst), .sig(sig), .stb(q));
Synchronizer s(.clk(clk), .rst(rst), .sig(q), .stb(stb));
endmodule | module Cleaner(clk, rst, sig, stb); |
input clk, rst, sig;
output stb;
wire q;
Debouncer d(.clk(clk), .rst(rst), .sig(sig), .stb(q));
Synchronizer s(.clk(clk), .rst(rst), .sig(q), .stb(stb));
endmodule | 2 |
138,033 | data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v | 81,638,292 | Computer.v | v | 54 | 162 | [] | [] | [] | [(6, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:15: Cannot find file containing module: 'Cleaner'\n Cleaner clean0(.clk(clk), .rst(rst), .sig(switchIn[0]), .stb(cleanSwitches[0]));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/81638292/Verilog/Xilinx,data/full_repos/permissive/81638292/Cleaner\n data/full_repos/permissive/81638292/Verilog/Xilinx,data/full_repos/permissive/81638292/Cleaner.v\n data/full_repos/permissive/81638292/Verilog/Xilinx,data/full_repos/permissive/81638292/Cleaner.sv\n Cleaner\n Cleaner.v\n Cleaner.sv\n obj_dir/Cleaner\n obj_dir/Cleaner.v\n obj_dir/Cleaner.sv\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:16: Cannot find file containing module: 'Cleaner'\n Cleaner clean1(.clk(clk), .rst(rst), .sig(switchIn[1]), .stb(cleanSwitches[1]));\n ^~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:17: Cannot find file containing module: 'Cleaner'\n Cleaner clean2(.clk(clk), .rst(rst), .sig(switchIn[2]), .stb(cleanSwitches[2]));\n ^~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:18: Cannot find file containing module: 'Cleaner'\n Cleaner clean3(.clk(clk), .rst(rst), .sig(switchIn[3]), .stb(cleanSwitches[3]));\n ^~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:19: Cannot find file containing module: 'Cleaner'\n Cleaner clean4(.clk(clk), .rst(rst), .sig(switchIn[4]), .stb(cleanSwitches[4]));\n ^~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:20: Cannot find file containing module: 'Cleaner'\n Cleaner clean5(.clk(clk), .rst(rst), .sig(switchIn[5]), .stb(cleanSwitches[5])); \n ^~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:21: Cannot find file containing module: 'Cleaner'\n Cleaner clean6(.clk(clk), .rst(rst), .sig(switchIn[6]), .stb(cleanSwitches[6]));\n ^~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:22: Cannot find file containing module: 'Cleaner'\n Cleaner clean7(.clk(clk), .rst(rst), .sig(switchIn[7]), .stb(cleanSwitches[7]));\n ^~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:39: Cannot find file containing module: 'CPU'\n CPU cpu(.clk(clk_counter[1]), .rst(rst),\n ^~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:50: Cannot find file containing module: 'RAMmanager'\n RAMmanager ram(.clk(clk_counter[1]), .levers(cleanSwitches), .display(display), .writeEnables(writeEnables), .memin(memin), .memaddr(memaddr), .memout(memout));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:51: Cannot find file containing module: 'ROMmanager'\n ROMmanager rom(.clk(clk), .romaddr(romaddr), .romout(romout));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/81638292/Verilog/Xilinx/Computer.v:52: Cannot find file containing module: 'Output'\n Output out(.clk(clk_counter[1]), .rst(rst), .num(display), .segs(segs), .pos(pos));\n ^~~~~~\n%Error: Exiting due to 12 error(s)\n" | 301,621 | module | module Computer(clk, rst, segs, pos, switchIn);
input clk, rst;
input [7:0]switchIn;
output [6:0]segs;
output [3:0]pos;
reg [1:0]clk_counter;
wire [31:0]cleanSwitches;
assign cleanSwitches[31:8] = 24'b0;
Cleaner clean0(.clk(clk), .rst(rst), .sig(switchIn[0]), .stb(cleanSwitches[0]));
Cleaner clean1(.clk(clk), .rst(rst), .sig(switchIn[1]), .stb(cleanSwitches[1]));
Cleaner clean2(.clk(clk), .rst(rst), .sig(switchIn[2]), .stb(cleanSwitches[2]));
Cleaner clean3(.clk(clk), .rst(rst), .sig(switchIn[3]), .stb(cleanSwitches[3]));
Cleaner clean4(.clk(clk), .rst(rst), .sig(switchIn[4]), .stb(cleanSwitches[4]));
Cleaner clean5(.clk(clk), .rst(rst), .sig(switchIn[5]), .stb(cleanSwitches[5]));
Cleaner clean6(.clk(clk), .rst(rst), .sig(switchIn[6]), .stb(cleanSwitches[6]));
Cleaner clean7(.clk(clk), .rst(rst), .sig(switchIn[7]), .stb(cleanSwitches[7]));
wire [31:0]romaddr;
wire [31:0]romout;
wire [ 3:0]iobytes;
wire memwrite;
wire [ 3:0]writeEnables;
wire [31:0]memin, memout, memaddr;
always @(posedge clk) begin
if (rst)
clk_counter <= 0;
else
clk_counter <= clk_counter + 1;
end
CPU cpu(.clk(clk_counter[1]), .rst(rst),
.memout(memout),
.memwrite(memwrite),
.memin(memin),
.memaddr(memaddr),
.romout(romout),
.romaddr(romaddr),
.iobytes(iobytes));
assign writeEnables = iobytes & {4{memwrite}};
wire [31:0]display;
RAMmanager ram(.clk(clk_counter[1]), .levers(cleanSwitches), .display(display), .writeEnables(writeEnables), .memin(memin), .memaddr(memaddr), .memout(memout));
ROMmanager rom(.clk(clk), .romaddr(romaddr), .romout(romout));
Output out(.clk(clk_counter[1]), .rst(rst), .num(display), .segs(segs), .pos(pos));
endmodule | module Computer(clk, rst, segs, pos, switchIn); |
input clk, rst;
input [7:0]switchIn;
output [6:0]segs;
output [3:0]pos;
reg [1:0]clk_counter;
wire [31:0]cleanSwitches;
assign cleanSwitches[31:8] = 24'b0;
Cleaner clean0(.clk(clk), .rst(rst), .sig(switchIn[0]), .stb(cleanSwitches[0]));
Cleaner clean1(.clk(clk), .rst(rst), .sig(switchIn[1]), .stb(cleanSwitches[1]));
Cleaner clean2(.clk(clk), .rst(rst), .sig(switchIn[2]), .stb(cleanSwitches[2]));
Cleaner clean3(.clk(clk), .rst(rst), .sig(switchIn[3]), .stb(cleanSwitches[3]));
Cleaner clean4(.clk(clk), .rst(rst), .sig(switchIn[4]), .stb(cleanSwitches[4]));
Cleaner clean5(.clk(clk), .rst(rst), .sig(switchIn[5]), .stb(cleanSwitches[5]));
Cleaner clean6(.clk(clk), .rst(rst), .sig(switchIn[6]), .stb(cleanSwitches[6]));
Cleaner clean7(.clk(clk), .rst(rst), .sig(switchIn[7]), .stb(cleanSwitches[7]));
wire [31:0]romaddr;
wire [31:0]romout;
wire [ 3:0]iobytes;
wire memwrite;
wire [ 3:0]writeEnables;
wire [31:0]memin, memout, memaddr;
always @(posedge clk) begin
if (rst)
clk_counter <= 0;
else
clk_counter <= clk_counter + 1;
end
CPU cpu(.clk(clk_counter[1]), .rst(rst),
.memout(memout),
.memwrite(memwrite),
.memin(memin),
.memaddr(memaddr),
.romout(romout),
.romaddr(romaddr),
.iobytes(iobytes));
assign writeEnables = iobytes & {4{memwrite}};
wire [31:0]display;
RAMmanager ram(.clk(clk_counter[1]), .levers(cleanSwitches), .display(display), .writeEnables(writeEnables), .memin(memin), .memaddr(memaddr), .memout(memout));
ROMmanager rom(.clk(clk), .romaddr(romaddr), .romout(romout));
Output out(.clk(clk_counter[1]), .rst(rst), .num(display), .segs(segs), .pos(pos));
endmodule | 2 |
138,040 | data/full_repos/permissive/81675391/src/main.v | 81,675,391 | main.v | v | 45 | 171 | [] | [] | [] | null | line:31: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/81675391/src/main.v:31: Unsupported: Ignoring delay on this delayed statement.\n initial #sim_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/81675391/src/main.v:41: Unsupported: Ignoring delay on this delayed statement.\n #5 {clk, clr} <= {!clk, 1\'b1};\n ^\n%Error: data/full_repos/permissive/81675391/src/main.v:25: Cannot find file containing module: \'control_unit\'\n control_unit CU (IR, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MOC, ZF, N, C, V, Cond, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP, clk, clr);\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81675391/src,data/full_repos/permissive/81675391/control_unit\n data/full_repos/permissive/81675391/src,data/full_repos/permissive/81675391/control_unit.v\n data/full_repos/permissive/81675391/src,data/full_repos/permissive/81675391/control_unit.sv\n control_unit\n control_unit.v\n control_unit.sv\n obj_dir/control_unit\n obj_dir/control_unit.v\n obj_dir/control_unit.sv\n%Error: data/full_repos/permissive/81675391/src/main.v:27: Cannot find file containing module: \'data_path\'\n data_path DP (IR, MOC, Cond, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP, clk, clr);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,637 | module | module main;
reg clk, clr;
wire [31:0] IR;
wire SE;
wire [1:0] size;
wire FR_ld;
wire RF_ld;
wire IR_ld;
wire MAR_ld;
wire MDR_ld;
wire R_W;
wire MOV;
wire MOC;
wire ZF, N, C, V;
wire Cond;
wire MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME;
wire [4:0] OP;
control_unit CU (IR, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MOC, ZF, N, C, V, Cond, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP, clk, clr);
data_path DP (IR, MOC, Cond, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP, clk, clr);
parameter sim_time = 3000;
initial #sim_time $finish;
initial begin
clk = 1'b0;
clr = 1'b0;
repeat (450)
begin
#5 {clk, clr} <= {!clk, 1'b1};
end
end
endmodule | module main; |
reg clk, clr;
wire [31:0] IR;
wire SE;
wire [1:0] size;
wire FR_ld;
wire RF_ld;
wire IR_ld;
wire MAR_ld;
wire MDR_ld;
wire R_W;
wire MOV;
wire MOC;
wire ZF, N, C, V;
wire Cond;
wire MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME;
wire [4:0] OP;
control_unit CU (IR, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MOC, ZF, N, C, V, Cond, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP, clk, clr);
data_path DP (IR, MOC, Cond, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP, clk, clr);
parameter sim_time = 3000;
initial #sim_time $finish;
initial begin
clk = 1'b0;
clr = 1'b0;
repeat (450)
begin
#5 {clk, clr} <= {!clk, 1'b1};
end
end
endmodule | 0 |
138,041 | data/full_repos/permissive/81675391/src/control_unit/control_signals_encoder.v | 81,675,391 | control_signals_encoder.v | v | 1,277 | 92 | [] | [] | [] | [(1, 1276)] | null | data/verilator_xmls/877e56cb-96b9-410b-b894-efbf78a4aaff.xml | null | 301,638 | module | module control_signals_encoder (
input [5:0] S,
output reg SE,
output reg[1:0] size,
output reg FR_ld,
output reg RF_ld,
output reg IR,
output reg MAR_ld,
output reg MDR_ld,
output reg R_W,
output reg MOV,
output reg MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME,
output reg[4:0] OP
);
always @ (S) begin
case (S)
6'b000000:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b000001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b000010:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b10001;
end
6'b000011:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 1;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000101:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 1;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000110:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 1;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000111:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b001000:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b001001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 1;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b001010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b001011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b001100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00010;
end
6'b001101:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b001110:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b001111:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010000:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b010010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 1;
OP <= 5'b10000;
end
6'b010011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010101:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010110:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010111:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 1;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b011000:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 1;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00010;
end
6'b011001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b011010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b011011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00010;
end
6'b011100:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b011101:
begin
SE <= 1;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b011110:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b011111:
begin
SE <= 1;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100000:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100001:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b100011:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100100:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100101:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b100110:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 1;
OP <= 5'b10000;
end
6'b100111:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101000:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 1;
OP <= 5'b10000;
end
6'b101010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10001;
end
6'b101011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_1 <= 0;
MC_2 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10010;
end
6'b101100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10011;
end
6'b101101:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101110:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101111:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 1;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 1;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b110000:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b110001:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b110010:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b110011:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
default:
$display("Error: Control Signals Encoder. State not recognized S = %b", S);
endcase
end
endmodule | module control_signals_encoder (
input [5:0] S,
output reg SE,
output reg[1:0] size,
output reg FR_ld,
output reg RF_ld,
output reg IR,
output reg MAR_ld,
output reg MDR_ld,
output reg R_W,
output reg MOV,
output reg MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME,
output reg[4:0] OP
); |
always @ (S) begin
case (S)
6'b000000:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b000001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b000010:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b10001;
end
6'b000011:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 1;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000101:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 1;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000110:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 1;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b000111:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b001000:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b001001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 1;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b001010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b001011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b001100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00010;
end
6'b001101:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b001110:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b001111:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010000:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b010010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 1;
OP <= 5'b10000;
end
6'b010011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010101:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010110:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b010111:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 1;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b011000:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 1;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00010;
end
6'b011001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10000;
end
6'b011010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00100;
end
6'b011011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 1;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b00010;
end
6'b011100:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b011101:
begin
SE <= 1;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b011110:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b011111:
begin
SE <= 1;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100000:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100001:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b100011:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100100:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b100101:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 1;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b100110:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 1;
OP <= 5'b10000;
end
6'b100111:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101000:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101001:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 0;
MOV <= 0;
MA_1 <= 1;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 1;
OP <= 5'b10000;
end
6'b101010:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10001;
end
6'b101011:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_1 <= 0;
MC_2 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10010;
end
6'b101100:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 1;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 1;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 1;
ME <= 0;
OP <= 5'b10011;
end
6'b101101:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101110:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 1;
R_W <= 1;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 0;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b101111:
begin
SE <= 0;
size <= 2'b00;
FR_ld <= 0;
RF_ld <= 0;
IR <= 1;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 0;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 1;
MC_0 <= 1;
MD <= 1;
ME <= 0;
OP <= 5'b01101;
end
6'b110000:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b110001:
begin
SE <= 0;
size <= 2'b10;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b110010:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
6'b110011:
begin
SE <= 0;
size <= 2'b01;
FR_ld <= 0;
RF_ld <= 0;
IR <= 0;
MAR_ld <= 0;
MDR_ld <= 0;
R_W <= 0;
MOV <= 1;
MA_1 <= 0;
MA_0 <= 0;
MB_1 <= 1;
MB_0 <= 0;
MC_2 <= 0;
MC_1 <= 0;
MC_0 <= 0;
MD <= 0;
ME <= 0;
OP <= 5'b00000;
end
default:
$display("Error: Control Signals Encoder. State not recognized S = %b", S);
endcase
end
endmodule | 0 |
138,042 | data/full_repos/permissive/81675391/src/control_unit/control_unit.v | 81,675,391 | control_unit.v | v | 29 | 162 | [] | [] | [] | [(1, 28)] | null | null | 1: b"%Error: data/full_repos/permissive/81675391/src/control_unit/control_unit.v:24: Cannot find file containing module: 'next_state_decoder'\n next_state_decoder NSD (next_state_w, current_state_w, IR, COND, MOC);\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81675391/src/control_unit,data/full_repos/permissive/81675391/next_state_decoder\n data/full_repos/permissive/81675391/src/control_unit,data/full_repos/permissive/81675391/next_state_decoder.v\n data/full_repos/permissive/81675391/src/control_unit,data/full_repos/permissive/81675391/next_state_decoder.sv\n next_state_decoder\n next_state_decoder.v\n next_state_decoder.sv\n obj_dir/next_state_decoder\n obj_dir/next_state_decoder.v\n obj_dir/next_state_decoder.sv\n%Error: data/full_repos/permissive/81675391/src/control_unit/control_unit.v:25: Cannot find file containing module: 'state_register'\n state_register SR (current_state_w, next_state_w, clk, clr);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/control_unit/control_unit.v:26: Cannot find file containing module: 'control_signals_encoder'\n control_signals_encoder CSE (current_state_w, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP);\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 301,639 | module | module control_unit (
input [31:0] IR,
output SE,
output [1:0] size,
output FR_ld,
output RF_ld,
output IR_ld,
output MAR_ld,
output MDR_ld,
output R_W,
output MOV,
input MOC,
input ZF, N, C, V,
input COND,
output MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME,
output [4:0] OP,
input clk, clr
);
wire [5:0] current_state_w, next_state_w;
next_state_decoder NSD (next_state_w, current_state_w, IR, COND, MOC);
state_register SR (current_state_w, next_state_w, clk, clr);
control_signals_encoder CSE (current_state_w, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP);
endmodule | module control_unit (
input [31:0] IR,
output SE,
output [1:0] size,
output FR_ld,
output RF_ld,
output IR_ld,
output MAR_ld,
output MDR_ld,
output R_W,
output MOV,
input MOC,
input ZF, N, C, V,
input COND,
output MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME,
output [4:0] OP,
input clk, clr
); |
wire [5:0] current_state_w, next_state_w;
next_state_decoder NSD (next_state_w, current_state_w, IR, COND, MOC);
state_register SR (current_state_w, next_state_w, clk, clr);
control_signals_encoder CSE (current_state_w, SE, size, FR_ld, RF_ld, IR_ld, MAR_ld, MDR_ld, R_W, MOV, MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME, OP);
endmodule | 0 |
138,043 | data/full_repos/permissive/81675391/src/control_unit/next_state_decoder.v | 81,675,391 | next_state_decoder.v | v | 492 | 114 | [] | [] | [] | [(1, 491)] | null | data/verilator_xmls/7f9cd83f-af37-4cf2-ad5a-51f330cfbf9a.xml | null | 301,640 | module | module next_state_decoder (
output reg[5:0] NS,
input [5:0] S,
input [31:0] IR,
input Cond, MOC
);
always @ (S, MOC, Cond) begin
case (S)
6'b000000: NS <= 6'b000001;
6'b000001: NS <= 6'b000010;
6'b000010: NS <= 6'b000011;
6'b000011:
if (!MOC)
NS <= 6'b000011;
else
NS <= 6'b000100;
6'b000100:
begin
if (!Cond)
NS <= 6'b000001;
else
begin
if ((IR[27:25] == 3'b001) || (IR[27:25] == 3'b000 && IR[4] == 1'b0))
if (IR[24:23] == 2'b10)
NS <= 6'b000101;
else
if (IR[20] == 1'b1)
NS <= 6'b000110;
else
NS <= 6'b000111;
else if (IR[27:25] == 3'b101)
if(IR[24] == 1'b0)
NS <= 6'b001000;
else
NS <= 6'b001001;
else if(IR[27:26] == 2'b01)
if(IR[24] == 1'b0)
NS <= 6'b001010;
else
if(IR[23] == 1'b1)
NS <= 6'b001011;
else
NS <= 6'b001100;
else if(IR[27:25] == 3'b000 && IR[4] == 1'b1)
if(IR[24] == 1'b0)
NS <= 6'b011001;
else
if(IR[23] == 1'b1)
NS <= 6'b011010;
else
NS <= 6'b011011;
else
begin
$display("Error: Could not decipher the instruction. Returning to fetch state.");
NS <= 6'b000001;
end
end
end
6'b000101: NS <= 6'b000001;
6'b000110: NS <= 6'b000001;
6'b000111: NS <= 6'b000001;
6'b001000: NS <= 6'b000001;
6'b001001: NS <= 6'b001000;
6'b001010:
if(IR[20] == 1'b1)
if(IR[22] == 1'b1)
NS <= 6'b001101;
else
NS <= 6'b001111;
else
NS <= 6'b010010;
6'b001011:
if(IR[20] == 1'b1)
if(IR[22] == 1'b1)
NS <= 6'b001101;
else
NS <= 6'b001111;
else
NS <= 6'b010010;
6'b001100:
if(IR[20] == 1'b1)
if(IR[22] == 1'b1)
NS <= 6'b001101;
else
NS <= 6'b001111;
else
NS <= 6'b010010;
6'b001101: NS <= 6'b001110;
6'b001110:
if(!MOC)
NS <= 6'b001110;
else
NS <= 6'b010001;
6'b001111: NS <= 6'b010000;
6'b010000:
if(!MOC)
NS <= 6'b010000;
else
NS <= 6'b010001;
6'b010001:
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b010010:
if(IR[22] == 1'b1)
NS <= 6'b010011;
else
NS <= 6'b010101;
6'b010011: NS <= 6'b010100;
6'b010100:
if(!MOC)
NS <= 6'b010100;
else
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b010101: NS <= 6'b010110;
6'b010110:
if(!MOC)
NS <= 6'b010100;
else
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b010111: NS <= 6'b000001;
6'b011000: NS <= 6'b000001;
6'b011001:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
if (IR[20] == 1'b1)
if (IR[6] == 1'b1)
if (IR[5] == 1'b1)
NS <= 6'b011100;
else
NS <= 6'b011110;
else
NS <= 6'b100000;
else
NS <= 6'b100011;
else
NS <= 6'b100110;
6'b011010:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
if (IR[20] == 1'b1)
if (IR[6] == 1'b1)
if (IR[5] == 1'b1)
NS <= 6'b011100;
else
NS <= 6'b011110;
else
NS <= 6'b100000;
else
NS <= 6'b100011;
else
NS <= 6'b100110;
6'b011011:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
if (IR[20] == 1'b1)
if (IR[6] == 1'b1)
if (IR[5] == 1'b1)
NS <= 6'b011100;
else
NS <= 6'b011110;
else
NS <= 6'b100000;
else
NS <= 6'b100011;
else
NS <= 6'b100110;
6'b011100: NS <= 6'b011101;
6'b011101:
if(MOC)
NS <= 6'b100010;
else
NS <= 6'b011101;
6'b011110: NS <= 6'b011111;
6'b011111:
if(MOC)
NS <= 6'b100010;
else
NS <= 6'b011111;
6'b100000: NS <= 6'b100001;
6'b100001:
if(MOC)
NS <= 6'b100010;
else
NS <= 6'b100001;
6'b100010:
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b100011: NS <= 6'b100100;
6'b100100:
if(MOC)
NS <= 6'b100101;
else
NS <= 6'b100100;
6'b100101:
if(IR[24] == 1'b0)
NS <= 6'b011001;
else
if(IR[23] == 1'b1)
NS <= 6'b011010;
else
NS <= 6'b011011;
6'b100110:
if(IR[6] == 1'b1)
NS <= 6'b100111;
else
NS <= 6'b110010;
6'b100111: NS <= 6'b101000;
6'b101000:
if(MOC)
NS <= 6'b101001;
else
NS <= 6'b101000;
6'b101001:
if(IR[24] == 1'b0)
NS <= 6'b101010;
else
if(IR[23] == 1'b1)
NS <= 6'b101011;
else
NS <= 6'b101100;
6'b101010:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
NS <= 6'b101101;
else
NS <= 6'b110000;
6'b101011:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
NS <= 6'b101101;
else
NS <= 6'b110000;
6'b101100:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
NS <= 6'b101101;
else
NS <= 6'b110000;
6'b101101: NS <= 6'b101110;
6'b101110:
if(MOC)
NS <= 6'b101111;
else
NS <= 6'b101110;
6'b101111:
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b110000: NS <= 6'b110001;
6'b110001:
if(MOC)
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
else
NS <= 6'b110001;
6'b110010: NS <= 6'b110011;
6'b110011:
if(MOC)
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
else
NS <= 6'b110011;
default:
begin
$display("Error: Undefined state. Returning to state 0.");
NS <= 6'b000000;
end
endcase
end
endmodule | module next_state_decoder (
output reg[5:0] NS,
input [5:0] S,
input [31:0] IR,
input Cond, MOC
); |
always @ (S, MOC, Cond) begin
case (S)
6'b000000: NS <= 6'b000001;
6'b000001: NS <= 6'b000010;
6'b000010: NS <= 6'b000011;
6'b000011:
if (!MOC)
NS <= 6'b000011;
else
NS <= 6'b000100;
6'b000100:
begin
if (!Cond)
NS <= 6'b000001;
else
begin
if ((IR[27:25] == 3'b001) || (IR[27:25] == 3'b000 && IR[4] == 1'b0))
if (IR[24:23] == 2'b10)
NS <= 6'b000101;
else
if (IR[20] == 1'b1)
NS <= 6'b000110;
else
NS <= 6'b000111;
else if (IR[27:25] == 3'b101)
if(IR[24] == 1'b0)
NS <= 6'b001000;
else
NS <= 6'b001001;
else if(IR[27:26] == 2'b01)
if(IR[24] == 1'b0)
NS <= 6'b001010;
else
if(IR[23] == 1'b1)
NS <= 6'b001011;
else
NS <= 6'b001100;
else if(IR[27:25] == 3'b000 && IR[4] == 1'b1)
if(IR[24] == 1'b0)
NS <= 6'b011001;
else
if(IR[23] == 1'b1)
NS <= 6'b011010;
else
NS <= 6'b011011;
else
begin
$display("Error: Could not decipher the instruction. Returning to fetch state.");
NS <= 6'b000001;
end
end
end
6'b000101: NS <= 6'b000001;
6'b000110: NS <= 6'b000001;
6'b000111: NS <= 6'b000001;
6'b001000: NS <= 6'b000001;
6'b001001: NS <= 6'b001000;
6'b001010:
if(IR[20] == 1'b1)
if(IR[22] == 1'b1)
NS <= 6'b001101;
else
NS <= 6'b001111;
else
NS <= 6'b010010;
6'b001011:
if(IR[20] == 1'b1)
if(IR[22] == 1'b1)
NS <= 6'b001101;
else
NS <= 6'b001111;
else
NS <= 6'b010010;
6'b001100:
if(IR[20] == 1'b1)
if(IR[22] == 1'b1)
NS <= 6'b001101;
else
NS <= 6'b001111;
else
NS <= 6'b010010;
6'b001101: NS <= 6'b001110;
6'b001110:
if(!MOC)
NS <= 6'b001110;
else
NS <= 6'b010001;
6'b001111: NS <= 6'b010000;
6'b010000:
if(!MOC)
NS <= 6'b010000;
else
NS <= 6'b010001;
6'b010001:
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b010010:
if(IR[22] == 1'b1)
NS <= 6'b010011;
else
NS <= 6'b010101;
6'b010011: NS <= 6'b010100;
6'b010100:
if(!MOC)
NS <= 6'b010100;
else
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b010101: NS <= 6'b010110;
6'b010110:
if(!MOC)
NS <= 6'b010100;
else
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b010111: NS <= 6'b000001;
6'b011000: NS <= 6'b000001;
6'b011001:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
if (IR[20] == 1'b1)
if (IR[6] == 1'b1)
if (IR[5] == 1'b1)
NS <= 6'b011100;
else
NS <= 6'b011110;
else
NS <= 6'b100000;
else
NS <= 6'b100011;
else
NS <= 6'b100110;
6'b011010:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
if (IR[20] == 1'b1)
if (IR[6] == 1'b1)
if (IR[5] == 1'b1)
NS <= 6'b011100;
else
NS <= 6'b011110;
else
NS <= 6'b100000;
else
NS <= 6'b100011;
else
NS <= 6'b100110;
6'b011011:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
if (IR[20] == 1'b1)
if (IR[6] == 1'b1)
if (IR[5] == 1'b1)
NS <= 6'b011100;
else
NS <= 6'b011110;
else
NS <= 6'b100000;
else
NS <= 6'b100011;
else
NS <= 6'b100110;
6'b011100: NS <= 6'b011101;
6'b011101:
if(MOC)
NS <= 6'b100010;
else
NS <= 6'b011101;
6'b011110: NS <= 6'b011111;
6'b011111:
if(MOC)
NS <= 6'b100010;
else
NS <= 6'b011111;
6'b100000: NS <= 6'b100001;
6'b100001:
if(MOC)
NS <= 6'b100010;
else
NS <= 6'b100001;
6'b100010:
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b100011: NS <= 6'b100100;
6'b100100:
if(MOC)
NS <= 6'b100101;
else
NS <= 6'b100100;
6'b100101:
if(IR[24] == 1'b0)
NS <= 6'b011001;
else
if(IR[23] == 1'b1)
NS <= 6'b011010;
else
NS <= 6'b011011;
6'b100110:
if(IR[6] == 1'b1)
NS <= 6'b100111;
else
NS <= 6'b110010;
6'b100111: NS <= 6'b101000;
6'b101000:
if(MOC)
NS <= 6'b101001;
else
NS <= 6'b101000;
6'b101001:
if(IR[24] == 1'b0)
NS <= 6'b101010;
else
if(IR[23] == 1'b1)
NS <= 6'b101011;
else
NS <= 6'b101100;
6'b101010:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
NS <= 6'b101101;
else
NS <= 6'b110000;
6'b101011:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
NS <= 6'b101101;
else
NS <= 6'b110000;
6'b101100:
if (!(IR[5] == 1'b1 && IR[20] == 1'b0))
NS <= 6'b101101;
else
NS <= 6'b110000;
6'b101101: NS <= 6'b101110;
6'b101110:
if(MOC)
NS <= 6'b101111;
else
NS <= 6'b101110;
6'b101111:
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
6'b110000: NS <= 6'b110001;
6'b110001:
if(MOC)
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
else
NS <= 6'b110001;
6'b110010: NS <= 6'b110011;
6'b110011:
if(MOC)
if(IR[24] == 1'b1 && IR[21]==1'b0)
NS <= 6'b000001;
else
if(IR[23] == 1'b1)
NS <= 6'b010111;
else
NS <= 6'b011000;
else
NS <= 6'b110011;
default:
begin
$display("Error: Undefined state. Returning to state 0.");
NS <= 6'b000000;
end
endcase
end
endmodule | 0 |
138,044 | data/full_repos/permissive/81675391/src/control_unit/state_register.v | 81,675,391 | state_register.v | v | 12 | 31 | [] | [] | [] | null | line:6: before: "clr" | data/verilator_xmls/85de8d07-9ec5-4d4f-9a6f-183a06d50b85.xml | null | 301,641 | module | module state_register (
output reg[5:0] Q,
input [5:0] D,
input clk, clr
);
always @(posedge clk, clr)
if(clr == 1'b0)
Q <= 6'b000000;
else
Q <= D;
endmodule | module state_register (
output reg[5:0] Q,
input [5:0] D,
input clk, clr
); |
always @(posedge clk, clr)
if(clr == 1'b0)
Q <= 6'b000000;
else
Q <= D;
endmodule | 0 |
138,045 | data/full_repos/permissive/81675391/src/data_path/alu.v | 81,675,391 | alu.v | v | 125 | 124 | [] | [] | [] | [(1, 124)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:16: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:22: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:30: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:37: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:44: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:47: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'C_in\' generates 1 bits.\n : ... In instance alu\n {Flags[1], O} = A + B + C_in; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:51: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:54: Operator NOT expects 33 bits on the LHS, but LHS\'s VARREF \'C_in\' generates 1 bits.\n : ... In instance alu\n {Flags[1], O} = A - B - ~C_in; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:58: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:61: Operator NOT expects 33 bits on the LHS, but LHS\'s VARREF \'C_in\' generates 1 bits.\n : ... In instance alu\n {Flags[1], O} = B - A - ~C_in; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:65: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:70: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:76: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:84: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:91: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:96: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:102: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:108: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:114: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'O\' generates 32 bits.\n : ... In instance alu\n Flags[2] = !O; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:119: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance alu\n 5\'b10001: O = A + 3\'b100; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:120: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance alu\n 5\'b10010: O = A + B + 3\'b100; \n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/alu.v:121: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance alu\n 5\'b10011: O = A - B + 3\'b100; \n ^\n%Error: Exiting due to 22 warning(s)\n' | 301,642 | module | module alu (output reg [31:0] O, output reg [3:0] Flags, input [31:0] A, B, input [4:0] OP, input C_in, shifter_carry_out);
always@(OP, A, B)
case(OP)
5'b00000: begin
O = A & B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b00001: begin
O = A ^ B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b00010: begin
{Flags[1], O} = A - B;
Flags[0] = (A[31] != B[31])
&& (O[31] == B[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00011: begin
{Flags[1], O} = B - A;
Flags[0] = (A[31] != B[31])
&& (O[31] == A[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00100: begin
{Flags[1], O} = A + B;
Flags[0] = (A[31] == B[31])
&& (A[31] != O[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00101: begin
{Flags[1], O} = A + B + C_in;
Flags[0] = ((A[31] == B[31])
&& A[31] != O[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00110: begin
{Flags[1], O} = A - B - ~C_in;
Flags[0] = (A[31] != B[31])
&& (O[31] == B[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00111: begin
{Flags[1], O} = B - A - ~C_in;
Flags[0] = (A[31] != B[31])
&& (O[31] == A[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b01000: begin
O = A & B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01001: begin
O = A ^ B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01010: begin
{Flags[1], O} = A - B;
Flags[0] = (A[31] != B[31])
&& (O[31] == B[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b01011: begin
{Flags[1], O} = A + B;
Flags[0] = (A[31] == B[31])
&& (A[31] != O[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b01100: begin
O = A | B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01101: begin
O = B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01110: begin
O = A & ~B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01111: begin
O = ~B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b10000: O = A;
5'b10001: O = A + 3'b100;
5'b10010: O = A + B + 3'b100;
5'b10011: O = A - B + 3'b100;
endcase
endmodule | module alu (output reg [31:0] O, output reg [3:0] Flags, input [31:0] A, B, input [4:0] OP, input C_in, shifter_carry_out); |
always@(OP, A, B)
case(OP)
5'b00000: begin
O = A & B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b00001: begin
O = A ^ B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b00010: begin
{Flags[1], O} = A - B;
Flags[0] = (A[31] != B[31])
&& (O[31] == B[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00011: begin
{Flags[1], O} = B - A;
Flags[0] = (A[31] != B[31])
&& (O[31] == A[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00100: begin
{Flags[1], O} = A + B;
Flags[0] = (A[31] == B[31])
&& (A[31] != O[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00101: begin
{Flags[1], O} = A + B + C_in;
Flags[0] = ((A[31] == B[31])
&& A[31] != O[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00110: begin
{Flags[1], O} = A - B - ~C_in;
Flags[0] = (A[31] != B[31])
&& (O[31] == B[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b00111: begin
{Flags[1], O} = B - A - ~C_in;
Flags[0] = (A[31] != B[31])
&& (O[31] == A[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b01000: begin
O = A & B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01001: begin
O = A ^ B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01010: begin
{Flags[1], O} = A - B;
Flags[0] = (A[31] != B[31])
&& (O[31] == B[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b01011: begin
{Flags[1], O} = A + B;
Flags[0] = (A[31] == B[31])
&& (A[31] != O[31]);
Flags[3] = O[31];
Flags[2] = !O;
end
5'b01100: begin
O = A | B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01101: begin
O = B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01110: begin
O = A & ~B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b01111: begin
O = ~B;
Flags[3] = O[31];
Flags[2] = !O;
Flags[1] = shifter_carry_out;
end
5'b10000: O = A;
5'b10001: O = A + 3'b100;
5'b10010: O = A + B + 3'b100;
5'b10011: O = A - B + 3'b100;
endcase
endmodule | 0 |
138,046 | data/full_repos/permissive/81675391/src/data_path/condition_tester.v | 81,675,391 | condition_tester.v | v | 53 | 80 | [] | [] | [] | [(1, 52)] | null | data/verilator_xmls/2eef93ab-973d-47ed-9623-0565c1992983.xml | null | 301,643 | module | module condition_tester (output reg Cond, input [3:0] Code, input N, ZF, C, V);
parameter EQ = 4'b0000;
parameter NE = 4'b0001;
parameter CS = 4'b0010;
parameter CC = 4'b0011;
parameter MI = 4'b0100;
parameter PL = 4'b0101;
parameter VS = 4'b0110;
parameter VC = 4'b0111;
parameter HI = 4'b1000;
parameter LS = 4'b1001;
parameter GE = 4'b1010;
parameter LT = 4'b1011;
parameter GT = 4'b1100;
parameter LE = 4'b1101;
parameter AL = 4'b1110;
always@(Code, N, ZF, C, V) begin
case(Code)
EQ:
Cond <= ZF == 1;
NE:
Cond <= ZF == 0;
CS:
Cond <= C == 1;
CC:
Cond <= C == 0;
MI:
Cond <= N == 1;
PL:
Cond <= N == 0;
VS:
Cond <= V == 1;
VC:
Cond <= V == 0;
HI:
Cond <= (C == 1 && ZF == 0);
LS:
Cond <= (C == 0 && ZF == 1);
GE:
Cond <= N == V;
LT:
Cond <= N != V;
GT:
Cond <= (ZF == 0 && N == V);
LE:
Cond <= (ZF == 1 || N != V);
AL:
Cond <= 1;
endcase
end
endmodule | module condition_tester (output reg Cond, input [3:0] Code, input N, ZF, C, V); |
parameter EQ = 4'b0000;
parameter NE = 4'b0001;
parameter CS = 4'b0010;
parameter CC = 4'b0011;
parameter MI = 4'b0100;
parameter PL = 4'b0101;
parameter VS = 4'b0110;
parameter VC = 4'b0111;
parameter HI = 4'b1000;
parameter LS = 4'b1001;
parameter GE = 4'b1010;
parameter LT = 4'b1011;
parameter GT = 4'b1100;
parameter LE = 4'b1101;
parameter AL = 4'b1110;
always@(Code, N, ZF, C, V) begin
case(Code)
EQ:
Cond <= ZF == 1;
NE:
Cond <= ZF == 0;
CS:
Cond <= C == 1;
CC:
Cond <= C == 0;
MI:
Cond <= N == 1;
PL:
Cond <= N == 0;
VS:
Cond <= V == 1;
VC:
Cond <= V == 0;
HI:
Cond <= (C == 1 && ZF == 0);
LS:
Cond <= (C == 0 && ZF == 1);
GE:
Cond <= N == V;
LT:
Cond <= N != V;
GT:
Cond <= (ZF == 0 && N == V);
LE:
Cond <= (ZF == 1 || N != V);
AL:
Cond <= 1;
endcase
end
endmodule | 0 |
138,047 | data/full_repos/permissive/81675391/src/data_path/data_path.v | 81,675,391 | data_path.v | v | 100 | 159 | [] | [] | [] | [(1, 99)] | null | null | 1: b"%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:57: Cannot find file containing module: 'dflipflop'\n dflipflop IR (current_IR, data_out, clk, IR_ld);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81675391/src/data_path,data/full_repos/permissive/81675391/dflipflop\n data/full_repos/permissive/81675391/src/data_path,data/full_repos/permissive/81675391/dflipflop.v\n data/full_repos/permissive/81675391/src/data_path,data/full_repos/permissive/81675391/dflipflop.sv\n dflipflop\n dflipflop.v\n dflipflop.sv\n obj_dir/dflipflop\n obj_dir/dflipflop.v\n obj_dir/dflipflop.sv\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:58: Cannot find file containing module: 'dflipflop'\n dflipflop MAR (current_MAR, alu_out, clk, MAR_ld);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:59: Cannot find file containing module: 'dflipflop'\n dflipflop MDR (current_MDR, mux_E_to_MDR, clk, MDR_ld);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:60: Cannot find file containing module: 'dflipflop_4'\n dflipflop_4 FR (current_flags, alu_flags, clk, FR_ld);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:63: Cannot find file containing module: 'mux_4x1_4'\n mux_4x1_4 mux_A (mux_A_to_RF, {MA_1, MA_0}, current_IR[19:16], current_IR[15:12], PC, (current_IR[15:12] + 1'b1)); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:64: Cannot find file containing module: 'mux_5x1_4'\n mux_5x1_4 mux_C (mux_C_to_RF, {MC_2, MC_1, MC_0}, current_IR[15:12], PC, current_IR[19:16], (current_IR[15:12] + 1'b1), LR); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:65: Cannot find file containing module: 'mux_2x1_5'\n mux_2x1_5 mux_D (mux_D_to_ALU, MD, {1'b0, current_IR[24:21]}, OP );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:66: Cannot find file containing module: 'mux_4x1_32'\n mux_4x1_32 mux_B (mux_B_to_ALU, {MB_1, MB_0}, NPI_32, shifter_to_mux_B, current_MDR, ZERO);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:67: Cannot find file containing module: 'mux_2x1_32'\n mux_2x1_32 mux_E (mux_E_to_MDR, ME, data_out, alu_out);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:70: Cannot find file containing module: 'alu'\n alu mega_alu(alu_out, alu_flags, rf_PA_to_ALU, mux_B_to_ALU, mux_D_to_ALU, current_flags[1], shifter_carry_out);\n ^~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:73: Cannot find file containing module: 'condition_tester'\n condition_tester cond_test(Cond, current_IR[31:28], current_flags[3], current_flags[2], current_flags[1], current_flags[0]);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:76: Cannot find file containing module: 'shifter'\n shifter mega_shifter (shifter_to_mux_B, shifter_carry_out, current_IR, rf_PB_to_shifter, current_flags[1]);\n ^~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:79: Cannot find file containing module: 'ram_256'\n ram_256 ram (mem_data_out_to_sign_extender, MOC, current_MDR, R_W, MOV, current_MAR[7:0], size);\n ^~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:82: Cannot find file containing module: 'sign_extender'\n sign_extender sign_extend (data_out , mem_data_out_to_sign_extender, size[0], SE);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/data_path.v:85: Cannot find file containing module: 'register_file'\n register_file RF (rf_PA_to_ALU, rf_PB_to_shifter, alu_out, mux_A_to_RF, current_IR[3:0], mux_C_to_RF, clk, RF_ld);\n ^~~~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n" | 301,644 | module | module data_path(
output [31:0] IR_OUT,
output MOC,
output Cond,
input SE,
input [1:0] size,
input FR_ld,
input RF_ld,
input IR_ld,
input MAR_ld,
input MDR_ld,
input R_W,
input MOV,
input MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME,
input [4:0] OP,
input clk, clr
);
parameter PC = 4'b1111;
parameter LR = 4'b1110;
parameter NPI_32 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
parameter ZERO = 32'b00000000000000000000000000000000;
wire [3:0] mux_A_to_RF, mux_C_to_RF;
wire [4:0] mux_D_to_ALU;
wire [31:0] mux_B_to_ALU, mux_E_to_MDR;
wire [31:0] current_IR, current_MAR, current_MDR;
wire [3:0] current_flags;
wire [31:0] shifter_to_mux_B;
wire shifter_carry_out;
wire [31:0] rf_PA_to_ALU, rf_PB_to_shifter;
wire [31:0] mem_data_out_to_sign_extender;
wire [3:0] alu_flags;
wire [31:0] data_out;
wire [31:0] alu_out;
dflipflop IR (current_IR, data_out, clk, IR_ld);
dflipflop MAR (current_MAR, alu_out, clk, MAR_ld);
dflipflop MDR (current_MDR, mux_E_to_MDR, clk, MDR_ld);
dflipflop_4 FR (current_flags, alu_flags, clk, FR_ld);
mux_4x1_4 mux_A (mux_A_to_RF, {MA_1, MA_0}, current_IR[19:16], current_IR[15:12], PC, (current_IR[15:12] + 1'b1));
mux_5x1_4 mux_C (mux_C_to_RF, {MC_2, MC_1, MC_0}, current_IR[15:12], PC, current_IR[19:16], (current_IR[15:12] + 1'b1), LR);
mux_2x1_5 mux_D (mux_D_to_ALU, MD, {1'b0, current_IR[24:21]}, OP );
mux_4x1_32 mux_B (mux_B_to_ALU, {MB_1, MB_0}, NPI_32, shifter_to_mux_B, current_MDR, ZERO);
mux_2x1_32 mux_E (mux_E_to_MDR, ME, data_out, alu_out);
alu mega_alu(alu_out, alu_flags, rf_PA_to_ALU, mux_B_to_ALU, mux_D_to_ALU, current_flags[1], shifter_carry_out);
condition_tester cond_test(Cond, current_IR[31:28], current_flags[3], current_flags[2], current_flags[1], current_flags[0]);
shifter mega_shifter (shifter_to_mux_B, shifter_carry_out, current_IR, rf_PB_to_shifter, current_flags[1]);
ram_256 ram (mem_data_out_to_sign_extender, MOC, current_MDR, R_W, MOV, current_MAR[7:0], size);
sign_extender sign_extend (data_out , mem_data_out_to_sign_extender, size[0], SE);
register_file RF (rf_PA_to_ALU, rf_PB_to_shifter, alu_out, mux_A_to_RF, current_IR[3:0], mux_C_to_RF, clk, RF_ld);
assign IR_OUT = current_IR;
initial begin
$display("----------------------------------------------");
end
always @ (current_MAR) begin
$display("Data Path: MAR = %d", current_MAR);
end
endmodule | module data_path(
output [31:0] IR_OUT,
output MOC,
output Cond,
input SE,
input [1:0] size,
input FR_ld,
input RF_ld,
input IR_ld,
input MAR_ld,
input MDR_ld,
input R_W,
input MOV,
input MA_1, MA_0, MB_1, MB_0, MC_2, MC_1, MC_0, MD, ME,
input [4:0] OP,
input clk, clr
); |
parameter PC = 4'b1111;
parameter LR = 4'b1110;
parameter NPI_32 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
parameter ZERO = 32'b00000000000000000000000000000000;
wire [3:0] mux_A_to_RF, mux_C_to_RF;
wire [4:0] mux_D_to_ALU;
wire [31:0] mux_B_to_ALU, mux_E_to_MDR;
wire [31:0] current_IR, current_MAR, current_MDR;
wire [3:0] current_flags;
wire [31:0] shifter_to_mux_B;
wire shifter_carry_out;
wire [31:0] rf_PA_to_ALU, rf_PB_to_shifter;
wire [31:0] mem_data_out_to_sign_extender;
wire [3:0] alu_flags;
wire [31:0] data_out;
wire [31:0] alu_out;
dflipflop IR (current_IR, data_out, clk, IR_ld);
dflipflop MAR (current_MAR, alu_out, clk, MAR_ld);
dflipflop MDR (current_MDR, mux_E_to_MDR, clk, MDR_ld);
dflipflop_4 FR (current_flags, alu_flags, clk, FR_ld);
mux_4x1_4 mux_A (mux_A_to_RF, {MA_1, MA_0}, current_IR[19:16], current_IR[15:12], PC, (current_IR[15:12] + 1'b1));
mux_5x1_4 mux_C (mux_C_to_RF, {MC_2, MC_1, MC_0}, current_IR[15:12], PC, current_IR[19:16], (current_IR[15:12] + 1'b1), LR);
mux_2x1_5 mux_D (mux_D_to_ALU, MD, {1'b0, current_IR[24:21]}, OP );
mux_4x1_32 mux_B (mux_B_to_ALU, {MB_1, MB_0}, NPI_32, shifter_to_mux_B, current_MDR, ZERO);
mux_2x1_32 mux_E (mux_E_to_MDR, ME, data_out, alu_out);
alu mega_alu(alu_out, alu_flags, rf_PA_to_ALU, mux_B_to_ALU, mux_D_to_ALU, current_flags[1], shifter_carry_out);
condition_tester cond_test(Cond, current_IR[31:28], current_flags[3], current_flags[2], current_flags[1], current_flags[0]);
shifter mega_shifter (shifter_to_mux_B, shifter_carry_out, current_IR, rf_PB_to_shifter, current_flags[1]);
ram_256 ram (mem_data_out_to_sign_extender, MOC, current_MDR, R_W, MOV, current_MAR[7:0], size);
sign_extender sign_extend (data_out , mem_data_out_to_sign_extender, size[0], SE);
register_file RF (rf_PA_to_ALU, rf_PB_to_shifter, alu_out, mux_A_to_RF, current_IR[3:0], mux_C_to_RF, clk, RF_ld);
assign IR_OUT = current_IR;
initial begin
$display("----------------------------------------------");
end
always @ (current_MAR) begin
$display("Data Path: MAR = %d", current_MAR);
end
endmodule | 0 |
138,048 | data/full_repos/permissive/81675391/src/data_path/ram_256.v | 81,675,391 | ram_256.v | v | 114 | 81 | [] | [] | [] | null | line:22: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/81675391/src/data_path/ram_256.v:106: Unsupported: Ignoring delay on this delayed statement.\n #2200 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/ram_256.v:96: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s FSCANF \'%b\' generates 32 bits.\n : ... In instance ram_256\n while(!($feof(fd)) && $fscanf(fd, "%b", data)) begin\n ^~\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,645 | module | module ram_256 (
output reg[31:0] DataOut,
output reg MOC,
input [31:0] DataIn,
input R_W,
input MOV,
input [7:0] Address,
input [1:0] size
);
reg[7:0] Mem[0:255];
integer fd, code;
reg[7:0] data, ptr;
task print_memory;
begin
ptr = 0;
$display("Address | Content");
$display("----------------------------------------------");
repeat(256 / 4) begin
$write("%d |", ptr);
repeat(4) begin
$write(" %b", Mem[ptr]);
ptr = ptr + 1;
end
$write("\n");
end
end
endtask
always @(MOV, R_W)
begin
if (MOV)
begin
if(R_W)
case(size)
2'b00:
begin
DataOut[7:0] <= Mem[Address];
DataOut[31:8] <= 24'b0;
end
2'b01:
begin
DataOut[15:8] <= Mem[Address];
DataOut[7:0] <= Mem[Address + 1];
DataOut[31:16] <= 16'b0;
end
2'b10:
begin
DataOut[31:24] <= Mem[Address];
DataOut[23:16] <= Mem[Address+1];
DataOut[15:8] <= Mem[Address+2];
DataOut[7:0] <= Mem[Address+3];
end
endcase
else
case(size)
2'b00: Mem[Address] <= DataIn[7:0];
2'b01:
begin
Mem[Address] <= DataIn[15:8];
Mem[Address + 1] <= DataIn[7:0];
end
2'b10:
begin
Mem[Address] <= DataIn[31:24];
Mem[Address+1] <= DataIn[23:16];
Mem[Address+2] <= DataIn[15:8];
Mem[Address+3] <= DataIn[7:0];
end
endcase
MOC = 1;
end
else
begin
MOC = 0;
end
end
initial begin
ptr = 0;
fd = $fopen("../test/input/testcode_arm1.txt", "r");
while(!($feof(fd)) && $fscanf(fd, "%b", data)) begin
Mem[ptr] = data;
ptr = ptr + 1;
end
$display("----------------------------------------------");
$display("\nInitial memory content. Instructions Loaded.\n");
print_memory();
$display("\n");
#2200
$display("----------------------------------------------");
$display("\nFinal memory content.\n");
print_memory();
end
endmodule | module ram_256 (
output reg[31:0] DataOut,
output reg MOC,
input [31:0] DataIn,
input R_W,
input MOV,
input [7:0] Address,
input [1:0] size
); |
reg[7:0] Mem[0:255];
integer fd, code;
reg[7:0] data, ptr;
task print_memory;
begin
ptr = 0;
$display("Address | Content");
$display("----------------------------------------------");
repeat(256 / 4) begin
$write("%d |", ptr);
repeat(4) begin
$write(" %b", Mem[ptr]);
ptr = ptr + 1;
end
$write("\n");
end
end
endtask
always @(MOV, R_W)
begin
if (MOV)
begin
if(R_W)
case(size)
2'b00:
begin
DataOut[7:0] <= Mem[Address];
DataOut[31:8] <= 24'b0;
end
2'b01:
begin
DataOut[15:8] <= Mem[Address];
DataOut[7:0] <= Mem[Address + 1];
DataOut[31:16] <= 16'b0;
end
2'b10:
begin
DataOut[31:24] <= Mem[Address];
DataOut[23:16] <= Mem[Address+1];
DataOut[15:8] <= Mem[Address+2];
DataOut[7:0] <= Mem[Address+3];
end
endcase
else
case(size)
2'b00: Mem[Address] <= DataIn[7:0];
2'b01:
begin
Mem[Address] <= DataIn[15:8];
Mem[Address + 1] <= DataIn[7:0];
end
2'b10:
begin
Mem[Address] <= DataIn[31:24];
Mem[Address+1] <= DataIn[23:16];
Mem[Address+2] <= DataIn[15:8];
Mem[Address+3] <= DataIn[7:0];
end
endcase
MOC = 1;
end
else
begin
MOC = 0;
end
end
initial begin
ptr = 0;
fd = $fopen("../test/input/testcode_arm1.txt", "r");
while(!($feof(fd)) && $fscanf(fd, "%b", data)) begin
Mem[ptr] = data;
ptr = ptr + 1;
end
$display("----------------------------------------------");
$display("\nInitial memory content. Instructions Loaded.\n");
print_memory();
$display("\n");
#2200
$display("----------------------------------------------");
$display("\nFinal memory content.\n");
print_memory();
end
endmodule | 0 |
138,049 | data/full_repos/permissive/81675391/src/data_path/register_file.v | 81,675,391 | register_file.v | v | 29 | 108 | [] | [] | [] | [(1, 28)] | null | null | 1: b"%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:5: Cannot find file containing module: 'decoder_4to16'\n decoder_4to16 decoder (E, Dec, Ld);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/81675391/src/data_path,data/full_repos/permissive/81675391/decoder_4to16\n data/full_repos/permissive/81675391/src/data_path,data/full_repos/permissive/81675391/decoder_4to16.v\n data/full_repos/permissive/81675391/src/data_path,data/full_repos/permissive/81675391/decoder_4to16.sv\n decoder_4to16\n decoder_4to16.v\n decoder_4to16.sv\n obj_dir/decoder_4to16\n obj_dir/decoder_4to16.v\n obj_dir/decoder_4to16.sv\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:7: Cannot find file containing module: 'dflipflop'\n dflipflop R0 (Q0, IntA, Clk, E[0]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:8: Cannot find file containing module: 'dflipflop'\n dflipflop R1 (Q1, IntA, Clk, E[1]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:9: Cannot find file containing module: 'dflipflop'\n dflipflop R2 (Q2, IntA, Clk, E[2]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:10: Cannot find file containing module: 'dflipflop'\n dflipflop R3 (Q3, IntA, Clk, E[3]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:11: Cannot find file containing module: 'dflipflop'\n dflipflop R4 (Q4, IntA, Clk, E[4]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:12: Cannot find file containing module: 'dflipflop'\n dflipflop R5 (Q5, IntA, Clk, E[5]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:13: Cannot find file containing module: 'dflipflop'\n dflipflop R6 (Q6, IntA, Clk, E[6]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:14: Cannot find file containing module: 'dflipflop'\n dflipflop R7 (Q7, IntA, Clk, E[7]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:15: Cannot find file containing module: 'dflipflop'\n dflipflop R8 (Q8, IntA, Clk, E[8]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:16: Cannot find file containing module: 'dflipflop'\n dflipflop R9 (Q9, IntA, Clk, E[9]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:17: Cannot find file containing module: 'dflipflop'\n dflipflop R10 (Q10, IntA, Clk, E[10]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:18: Cannot find file containing module: 'dflipflop'\n dflipflop R11 (Q11, IntA, Clk, E[11]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:19: Cannot find file containing module: 'dflipflop'\n dflipflop R12 (Q12, IntA, Clk, E[12]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:20: Cannot find file containing module: 'dflipflop'\n dflipflop R13 (Q13, IntA, Clk, E[13]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:21: Cannot find file containing module: 'dflipflop'\n dflipflop R14 (Q14, IntA, Clk, E[14]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:22: Cannot find file containing module: 'dflipflop'\n dflipflop R15 (Q15, IntA, Clk, E[15]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:25: Cannot find file containing module: 'mux_16x1_32'\n mux_16x1_32 muxA (OutA, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, SA);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/81675391/src/data_path/register_file.v:26: Cannot find file containing module: 'mux_16x1_32'\n mux_16x1_32 muxB (OutB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, SB);\n ^~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n" | 301,646 | module | module register_file (output [31:0] OutA, OutB, input [31:0] IntA, input [3:0] SA, SB, Dec, input Clk, Ld);
wire [31:0] Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15;
wire [15:0] E;
decoder_4to16 decoder (E, Dec, Ld);
dflipflop R0 (Q0, IntA, Clk, E[0]);
dflipflop R1 (Q1, IntA, Clk, E[1]);
dflipflop R2 (Q2, IntA, Clk, E[2]);
dflipflop R3 (Q3, IntA, Clk, E[3]);
dflipflop R4 (Q4, IntA, Clk, E[4]);
dflipflop R5 (Q5, IntA, Clk, E[5]);
dflipflop R6 (Q6, IntA, Clk, E[6]);
dflipflop R7 (Q7, IntA, Clk, E[7]);
dflipflop R8 (Q8, IntA, Clk, E[8]);
dflipflop R9 (Q9, IntA, Clk, E[9]);
dflipflop R10 (Q10, IntA, Clk, E[10]);
dflipflop R11 (Q11, IntA, Clk, E[11]);
dflipflop R12 (Q12, IntA, Clk, E[12]);
dflipflop R13 (Q13, IntA, Clk, E[13]);
dflipflop R14 (Q14, IntA, Clk, E[14]);
dflipflop R15 (Q15, IntA, Clk, E[15]);
mux_16x1_32 muxA (OutA, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, SA);
mux_16x1_32 muxB (OutB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, SB);
endmodule | module register_file (output [31:0] OutA, OutB, input [31:0] IntA, input [3:0] SA, SB, Dec, input Clk, Ld); |
wire [31:0] Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15;
wire [15:0] E;
decoder_4to16 decoder (E, Dec, Ld);
dflipflop R0 (Q0, IntA, Clk, E[0]);
dflipflop R1 (Q1, IntA, Clk, E[1]);
dflipflop R2 (Q2, IntA, Clk, E[2]);
dflipflop R3 (Q3, IntA, Clk, E[3]);
dflipflop R4 (Q4, IntA, Clk, E[4]);
dflipflop R5 (Q5, IntA, Clk, E[5]);
dflipflop R6 (Q6, IntA, Clk, E[6]);
dflipflop R7 (Q7, IntA, Clk, E[7]);
dflipflop R8 (Q8, IntA, Clk, E[8]);
dflipflop R9 (Q9, IntA, Clk, E[9]);
dflipflop R10 (Q10, IntA, Clk, E[10]);
dflipflop R11 (Q11, IntA, Clk, E[11]);
dflipflop R12 (Q12, IntA, Clk, E[12]);
dflipflop R13 (Q13, IntA, Clk, E[13]);
dflipflop R14 (Q14, IntA, Clk, E[14]);
dflipflop R15 (Q15, IntA, Clk, E[15]);
mux_16x1_32 muxA (OutA, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, SA);
mux_16x1_32 muxB (OutB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, SB);
endmodule | 0 |
138,050 | data/full_repos/permissive/81675391/src/data_path/shifter.v | 81,675,391 | shifter.v | v | 121 | 135 | [] | [] | [] | [(1, 120)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/shifter.v:14: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance shifter\n {temp} = IR[7:0];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/shifter.v:15: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 64 bits.\n : ... In instance shifter\n {OUT} = {temp, temp} >> (2 * IR[11:8]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/shifter.v:74: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'C_in\' generates 1 bits.\n : ... In instance shifter\n {OUT} <= (C_in << 31) | (RM >> 1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/shifter.v:79: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 64 bits.\n : ... In instance shifter\n {OUT} <= {RM, RM} >> IR[11:7];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/shifter.v:91: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 12 bits.\n : ... In instance shifter\n {OUT} <= IR[11:0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/81675391/src/data_path/shifter.v:103: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n : ... In instance shifter\n {OUT} <= {IR[11:8], IR[3:0]};\n ^~\n%Error: Exiting due to 6 warning(s)\n' | 301,647 | module | module shifter (output reg[31:0] OUT, output reg shifter_carry_out, input [31:0] IR, RM, input C_in);
reg [31:0] temp;
always @ (IR, RM)
if((IR[27:25] == 3'b001) || (IR[27:25] == 3'b000 && IR[4] == 1'b0))
if(IR[25] == 1'b1)
begin
{temp} = IR[7:0];
{OUT} = {temp, temp} >> (2 * IR[11:8]);
if(IR[11:8] == 4'b0000)
shifter_carry_out = C_in;
else
shifter_carry_out = OUT[31];
end
else if(IR[25] == 1'b0 && IR[4] == 1'b0)
case(IR[6:5])
2'b00: if(IR[11:7] == 5'b00000)
begin
{OUT} <= RM;
shifter_carry_out <= C_in;
end
else
begin
{OUT} <= RM << IR[11:7];
shifter_carry_out <= RM[32-{IR[11:7]}];
end
2'b01: if(IR[11:7] == 5'b00000)
begin
{OUT} <= 32'b0;
shifter_carry_out <= RM[31];
end
else
begin
{OUT} <= RM >> IR[11:7];
shifter_carry_out <= RM[{IR[11:7]}-1];
end
2'b10: if(IR[11:7] == 5'b00000)
if(RM[31] == 1'b0)
begin
{OUT} <= 32'b0;
shifter_carry_out <= RM[31];
end
else
begin
{OUT} <= 32'hFFFFFFFF;
shifter_carry_out <= RM[31];
end
else
begin
{OUT} <= $signed(RM) >>> IR[11:7];
shifter_carry_out <= RM[{IR[11:7]}-1];
end
2'b11: if(IR[11:7] == 5'b00000)
begin
{OUT} <= (C_in << 31) | (RM >> 1);
shifter_carry_out <= RM[0];
end
else
begin
{OUT} <= {RM, RM} >> IR[11:7];
shifter_carry_out <= RM[{IR[11:7]}-1];
end
endcase
else
$display("Error: Shift by Register Is not implemented!");
else if(IR[27:26] == 2'b01)
if(IR[25] == 1'b0)
{OUT} <= IR[11:0];
else
{OUT} <= RM;
else if(IR[27:25] == 3'b000 && IR[4] == 1'b1)
if(IR[22] == 1'b1)
{OUT} <= {IR[11:8], IR[3:0]};
else
{OUT} <= RM;
else if(IR[27:25] == 3'b101)
{OUT} <= {{8{IR[23]}},IR[23:0]} << 2;
else
$display("Error: Unexpected instruction");
endmodule | module shifter (output reg[31:0] OUT, output reg shifter_carry_out, input [31:0] IR, RM, input C_in); |
reg [31:0] temp;
always @ (IR, RM)
if((IR[27:25] == 3'b001) || (IR[27:25] == 3'b000 && IR[4] == 1'b0))
if(IR[25] == 1'b1)
begin
{temp} = IR[7:0];
{OUT} = {temp, temp} >> (2 * IR[11:8]);
if(IR[11:8] == 4'b0000)
shifter_carry_out = C_in;
else
shifter_carry_out = OUT[31];
end
else if(IR[25] == 1'b0 && IR[4] == 1'b0)
case(IR[6:5])
2'b00: if(IR[11:7] == 5'b00000)
begin
{OUT} <= RM;
shifter_carry_out <= C_in;
end
else
begin
{OUT} <= RM << IR[11:7];
shifter_carry_out <= RM[32-{IR[11:7]}];
end
2'b01: if(IR[11:7] == 5'b00000)
begin
{OUT} <= 32'b0;
shifter_carry_out <= RM[31];
end
else
begin
{OUT} <= RM >> IR[11:7];
shifter_carry_out <= RM[{IR[11:7]}-1];
end
2'b10: if(IR[11:7] == 5'b00000)
if(RM[31] == 1'b0)
begin
{OUT} <= 32'b0;
shifter_carry_out <= RM[31];
end
else
begin
{OUT} <= 32'hFFFFFFFF;
shifter_carry_out <= RM[31];
end
else
begin
{OUT} <= $signed(RM) >>> IR[11:7];
shifter_carry_out <= RM[{IR[11:7]}-1];
end
2'b11: if(IR[11:7] == 5'b00000)
begin
{OUT} <= (C_in << 31) | (RM >> 1);
shifter_carry_out <= RM[0];
end
else
begin
{OUT} <= {RM, RM} >> IR[11:7];
shifter_carry_out <= RM[{IR[11:7]}-1];
end
endcase
else
$display("Error: Shift by Register Is not implemented!");
else if(IR[27:26] == 2'b01)
if(IR[25] == 1'b0)
{OUT} <= IR[11:0];
else
{OUT} <= RM;
else if(IR[27:25] == 3'b000 && IR[4] == 1'b1)
if(IR[22] == 1'b1)
{OUT} <= {IR[11:8], IR[3:0]};
else
{OUT} <= RM;
else if(IR[27:25] == 3'b101)
{OUT} <= {{8{IR[23]}},IR[23:0]} << 2;
else
$display("Error: Unexpected instruction");
endmodule | 0 |
138,051 | data/full_repos/permissive/81675391/src/data_path/sign_extender.v | 81,675,391 | sign_extender.v | v | 15 | 82 | [] | [] | [] | null | line:15: before: "^" | data/verilator_xmls/c7669406-63de-4cbf-84f8-8a1b73e000d2.xml | null | 301,648 | module | module sign_extender (output reg [31:0] ext, input [31:0] unext, input size, en);
parameter BYTE = 1'b0;
parameter HALF = 1'b1;
always @ (unext) begin
if(en)
case(size)
BYTE: ext <= {{24{unext[7]}},unext[7:0]};
HALF: ext <= {{16{unext[15]}},unext[15:0]};
endcase
else
ext <= unext;
end
endmodule | module sign_extender (output reg [31:0] ext, input [31:0] unext, input size, en); |
parameter BYTE = 1'b0;
parameter HALF = 1'b1;
always @ (unext) begin
if(en)
case(size)
BYTE: ext <= {{24{unext[7]}},unext[7:0]};
HALF: ext <= {{16{unext[15]}},unext[15:0]};
endcase
else
ext <= unext;
end
endmodule | 0 |
138,052 | data/full_repos/permissive/81675391/src/misc/decoder_4to16.v | 81,675,391 | decoder_4to16.v | v | 24 | 66 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/a6c2a20a-3f60-4355-8b03-78e209086a49.xml | null | 301,649 | module | module decoder_4to16 (output reg [15:0]E, input [3:0]D, input L);
always @(D, L)
if(!L) E <= 16'b0000000000000000;
else
case(D)
4'b0000: E <= 16'b0000000000000001;
4'b0001: E <= 16'b0000000000000010;
4'b0010: E <= 16'b0000000000000100;
4'b0011: E <= 16'b0000000000001000;
4'b0100: E <= 16'b0000000000010000;
4'b0101: E <= 16'b0000000000100000;
4'b0110: E <= 16'b0000000001000000;
4'b0111: E <= 16'b0000000010000000;
4'b1000: E <= 16'b0000000100000000;
4'b1001: E <= 16'b0000001000000000;
4'b1010: E <= 16'b0000010000000000;
4'b1011: E <= 16'b0000100000000000;
4'b1100: E <= 16'b0001000000000000;
4'b1101: E <= 16'b0010000000000000;
4'b1110: E <= 16'b0100000000000000;
4'b1111: E <= 16'b1000000000000000;
endcase
endmodule | module decoder_4to16 (output reg [15:0]E, input [3:0]D, input L); |
always @(D, L)
if(!L) E <= 16'b0000000000000000;
else
case(D)
4'b0000: E <= 16'b0000000000000001;
4'b0001: E <= 16'b0000000000000010;
4'b0010: E <= 16'b0000000000000100;
4'b0011: E <= 16'b0000000000001000;
4'b0100: E <= 16'b0000000000010000;
4'b0101: E <= 16'b0000000000100000;
4'b0110: E <= 16'b0000000001000000;
4'b0111: E <= 16'b0000000010000000;
4'b1000: E <= 16'b0000000100000000;
4'b1001: E <= 16'b0000001000000000;
4'b1010: E <= 16'b0000010000000000;
4'b1011: E <= 16'b0000100000000000;
4'b1100: E <= 16'b0001000000000000;
4'b1101: E <= 16'b0010000000000000;
4'b1110: E <= 16'b0100000000000000;
4'b1111: E <= 16'b1000000000000000;
endcase
endmodule | 0 |
138,053 | data/full_repos/permissive/81675391/src/misc/dflipflop.v | 81,675,391 | dflipflop.v | v | 6 | 70 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/e3d65d63-e1d9-4683-bd7e-e350e3cfa507.xml | null | 301,650 | module | module dflipflop(output reg [31:0] Q, input [31:0] D, input clk, ld);
always @(posedge clk)
if(ld)
Q <= D;
endmodule | module dflipflop(output reg [31:0] Q, input [31:0] D, input clk, ld); |
always @(posedge clk)
if(ld)
Q <= D;
endmodule | 0 |
138,054 | data/full_repos/permissive/81675391/src/misc/dflipflop_4.v | 81,675,391 | dflipflop_4.v | v | 6 | 70 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/ae8b755d-20ac-49d4-a473-e38d34e314e9.xml | null | 301,651 | module | module dflipflop_4(output reg [3:0] Q, input [3:0] D, input clk, ld);
always @(posedge clk)
if(ld)
Q <= D;
endmodule | module dflipflop_4(output reg [3:0] Q, input [3:0] D, input clk, ld); |
always @(posedge clk)
if(ld)
Q <= D;
endmodule | 0 |
138,055 | data/full_repos/permissive/81675391/src/misc/mux_16x1_32.v | 81,675,391 | mux_16x1_32.v | v | 26 | 96 | [] | [] | [] | [(1, 25)] | null | data/verilator_xmls/6ffc1b00-4095-4fe8-94ac-fd5eaffacd63.xml | null | 301,652 | module | module mux_16x1_32(Y, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, S);
output reg [31:0] Y;
input [31:0] I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
input [3:0] S;
always @(S, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15)
case (S)
4'b0000: Y <= I0;
4'b0001: Y <= I1;
4'b0010: Y <= I2;
4'b0011: Y <= I3;
4'b0100: Y <= I4;
4'b0101: Y <= I5;
4'b0110: Y <= I6;
4'b0111: Y <= I7;
4'b1000: Y <= I8;
4'b1001: Y <= I9;
4'b1010: Y <= I10;
4'b1011: Y <= I11;
4'b1100: Y <= I12;
4'b1101: Y <= I13;
4'b1110: Y <= I14;
4'b1111: Y <= I15;
endcase
endmodule | module mux_16x1_32(Y, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, S); |
output reg [31:0] Y;
input [31:0] I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
input [3:0] S;
always @(S, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15)
case (S)
4'b0000: Y <= I0;
4'b0001: Y <= I1;
4'b0010: Y <= I2;
4'b0011: Y <= I3;
4'b0100: Y <= I4;
4'b0101: Y <= I5;
4'b0110: Y <= I6;
4'b0111: Y <= I7;
4'b1000: Y <= I8;
4'b1001: Y <= I9;
4'b1010: Y <= I10;
4'b1011: Y <= I11;
4'b1100: Y <= I12;
4'b1101: Y <= I13;
4'b1110: Y <= I14;
4'b1111: Y <= I15;
endcase
endmodule | 0 |
138,056 | data/full_repos/permissive/81675391/src/misc/mux_2x1_32.v | 81,675,391 | mux_2x1_32.v | v | 6 | 71 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/6e3e274d-1046-424b-837d-e3c09e93e4e3.xml | null | 301,653 | module | module mux_2x1_32 (output reg [31:0] Y, input S, input [31:0] I0, I1);
always @ (S, I0, I1)
if (S) Y <= I1;
else Y <= I0;
endmodule | module mux_2x1_32 (output reg [31:0] Y, input S, input [31:0] I0, I1); |
always @ (S, I0, I1)
if (S) Y <= I1;
else Y <= I0;
endmodule | 0 |
138,057 | data/full_repos/permissive/81675391/src/misc/mux_2x1_5.v | 81,675,391 | mux_2x1_5.v | v | 6 | 68 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/15af5850-8b71-4dd5-966a-a12c5427fda1.xml | null | 301,654 | module | module mux_2x1_5 (output reg [4:0] Y, input S, input [4:0] I0, I1);
always @ (S, I0, I1)
if (S) Y <= I1;
else Y <= I0;
endmodule | module mux_2x1_5 (output reg [4:0] Y, input S, input [4:0] I0, I1); |
always @ (S, I0, I1)
if (S) Y <= I1;
else Y <= I0;
endmodule | 0 |
138,058 | data/full_repos/permissive/81675391/src/misc/mux_4x1_32.v | 81,675,391 | mux_4x1_32.v | v | 10 | 84 | [] | [] | [] | [(1, 9)] | null | data/verilator_xmls/78784228-3c91-4eb1-9600-c52ffe26fa34.xml | null | 301,655 | module | module mux_4x1_32 (output reg [31:0] Y, input [1:0]S, input [31:0] I0, I1, I2, I3);
always @ (S, I0, I1, I2, I3)
case (S)
2'b00: Y <= I0;
2'b01: Y <= I1;
2'b10: Y <= I2;
2'b11: Y <= I3;
endcase
endmodule | module mux_4x1_32 (output reg [31:0] Y, input [1:0]S, input [31:0] I0, I1, I2, I3); |
always @ (S, I0, I1, I2, I3)
case (S)
2'b00: Y <= I0;
2'b01: Y <= I1;
2'b10: Y <= I2;
2'b11: Y <= I3;
endcase
endmodule | 0 |
138,059 | data/full_repos/permissive/81675391/src/misc/mux_5x1_4.v | 81,675,391 | mux_5x1_4.v | v | 12 | 85 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/252c40ec-1b52-40bc-87ba-1ee4f86382a7.xml | null | 301,657 | module | module mux_5x1_4 (output reg [3:0] Y, input [2:0]S, input [3:0] I0, I1, I2, I3, I4);
always @ (S, I0, I1, I2, I3, I4)
case (S)
3'b000: Y <= I0;
3'b001: Y <= I1;
3'b010: Y <= I2;
3'b011: Y <= I3;
3'b100: Y <= I4;
default: Y <= 4'bxxxx;
endcase
endmodule | module mux_5x1_4 (output reg [3:0] Y, input [2:0]S, input [3:0] I0, I1, I2, I3, I4); |
always @ (S, I0, I1, I2, I3, I4)
case (S)
3'b000: Y <= I0;
3'b001: Y <= I1;
3'b010: Y <= I2;
3'b011: Y <= I3;
3'b100: Y <= I4;
default: Y <= 4'bxxxx;
endcase
endmodule | 0 |
138,060 | data/full_repos/permissive/8175167/decode/bench/verilog/tb.v | 8,175,167 | tb.v | v | 180 | 91 | [] | [] | [] | null | line:100: before: "." | null | 1: b'%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb.v:125: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb.v:126: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb.v:133: syntax error, unexpected \'@\'\n @(posedge out_done);\n ^\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb.v:159: Unsupported or unknown PLI call: $fputc\n $fputc(o, out_data);\n ^~~~~~\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb.v:166: Unsupported or unknown PLI call: $dumpflush\n $dumpflush(".");\n ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,734 | module | module tb(
stream_empty, out_valid, out_done, out_data, fi_cnt,
ce_decode,
m_endn
);
parameter IN_WIDTH = 13;
parameter NEED_STR_WIDTH = 4;
parameter OUT_WIDTH = 8;
parameter LZF_WIDTH = 20;
output ce_decode;
output [LZF_WIDTH-1:0]fi_cnt;
output [7:0] out_data;
output out_done;
output out_valid;
output stream_empty;
input m_endn;
wire ce;
wire clk;
wire [63:0] fi;
wire fo_full;
wire m_last;
wire m_src_getn;
wire rst;
wire src_empty;
wire stream_ack;
wire stream_done;
wire stream_valid;
wire [NEED_STR_WIDTH-1:0] stream_width;
wire [IN_WIDTH-1:0] stream_data;
integer c, cnt, o;
parameter SRC_FILE = "/home/kevin/lzf-hg.git/files/texbook.pdf";
parameter LZS_FILE = "/home/kevin/lzf-hg.git/files/01";
parameter OUT_FILE = "/tmp/t.lzs";
parameter LZS_SIZE = 299;
reg [255:0] lzs_file;
reg [31:0] lzs_size;
reg [255:0] src_file;
`ifdef ABC
tb_data tb_data(
.stream_valid (stream_valid),
.stream_data (stream_data[IN_WIDTH-1:0]),
.stream_empty (stream_empty),
.fo_full (fo_full),
.clk (clk),
.ce_decode (ce_decode),
.rst (rst),
.stream_ack (stream_ack),
.stream_width (stream_width[3:0]));
`else
data data(
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam data.LZF_FILE = "/tmp/decode.src";
defparam data.LZF_DEBUG = 0;
defparam data.LZF_DELAY = 4;
defparam data.LZF_FIFO_AW = 5;
decode_in decode_in(
.m_src_getn (m_src_getn),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.clk (clk),
.rst (rst),
.ce (ce),
.m_last (m_last),
.fo_full (fo_full),
.src_empty (src_empty),
.fi (fi[63:0]),
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack));
`endif
initial
begin : VCD_and_MEM
$dumpfile("tb.vcd");
$dumpvars(0,tb);
if (0 == $value$plusargs("SRC_FILE=%s", src_file))
src_file = SRC_FILE;
c = $fopen(src_file, "r");
o = $fopen(OUT_FILE, "w");
cnt = 0;
@(posedge out_done);
$finish;
end
decode_ctl decode_ctl(
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack),
.out_data (out_data[7:0]),
.out_valid (out_valid),
.out_done (out_done),
.clk (clk),
.rst (rst),
.ce (ce),
.fo_full (fo_full),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done));
reg [7:0] s_data;
always @(posedge clk)
begin
if (out_valid) begin
$fputc(o, out_data);
s_data = $fgetc(c);
if (s_data === out_data) begin
$write("cnt %h: right %h \n", cnt, out_data);
end else begin
$write("cnt %h: right/current %h/%h\n",
cnt, s_data, out_data);
$dumpflush(".");
end
cnt = cnt + 1;
end
end
endmodule | module tb(
stream_empty, out_valid, out_done, out_data, fi_cnt,
ce_decode,
m_endn
); |
parameter IN_WIDTH = 13;
parameter NEED_STR_WIDTH = 4;
parameter OUT_WIDTH = 8;
parameter LZF_WIDTH = 20;
output ce_decode;
output [LZF_WIDTH-1:0]fi_cnt;
output [7:0] out_data;
output out_done;
output out_valid;
output stream_empty;
input m_endn;
wire ce;
wire clk;
wire [63:0] fi;
wire fo_full;
wire m_last;
wire m_src_getn;
wire rst;
wire src_empty;
wire stream_ack;
wire stream_done;
wire stream_valid;
wire [NEED_STR_WIDTH-1:0] stream_width;
wire [IN_WIDTH-1:0] stream_data;
integer c, cnt, o;
parameter SRC_FILE = "/home/kevin/lzf-hg.git/files/texbook.pdf";
parameter LZS_FILE = "/home/kevin/lzf-hg.git/files/01";
parameter OUT_FILE = "/tmp/t.lzs";
parameter LZS_SIZE = 299;
reg [255:0] lzs_file;
reg [31:0] lzs_size;
reg [255:0] src_file;
`ifdef ABC
tb_data tb_data(
.stream_valid (stream_valid),
.stream_data (stream_data[IN_WIDTH-1:0]),
.stream_empty (stream_empty),
.fo_full (fo_full),
.clk (clk),
.ce_decode (ce_decode),
.rst (rst),
.stream_ack (stream_ack),
.stream_width (stream_width[3:0]));
`else
data data(
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam data.LZF_FILE = "/tmp/decode.src";
defparam data.LZF_DEBUG = 0;
defparam data.LZF_DELAY = 4;
defparam data.LZF_FIFO_AW = 5;
decode_in decode_in(
.m_src_getn (m_src_getn),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.clk (clk),
.rst (rst),
.ce (ce),
.m_last (m_last),
.fo_full (fo_full),
.src_empty (src_empty),
.fi (fi[63:0]),
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack));
`endif
initial
begin : VCD_and_MEM
$dumpfile("tb.vcd");
$dumpvars(0,tb);
if (0 == $value$plusargs("SRC_FILE=%s", src_file))
src_file = SRC_FILE;
c = $fopen(src_file, "r");
o = $fopen(OUT_FILE, "w");
cnt = 0;
@(posedge out_done);
$finish;
end
decode_ctl decode_ctl(
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack),
.out_data (out_data[7:0]),
.out_valid (out_valid),
.out_done (out_done),
.clk (clk),
.rst (rst),
.ce (ce),
.fo_full (fo_full),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done));
reg [7:0] s_data;
always @(posedge clk)
begin
if (out_valid) begin
$fputc(o, out_data);
s_data = $fgetc(c);
if (s_data === out_data) begin
$write("cnt %h: right %h \n", cnt, out_data);
end else begin
$write("cnt %h: right/current %h/%h\n",
cnt, s_data, out_data);
$dumpflush(".");
end
cnt = cnt + 1;
end
end
endmodule | 8 |
138,061 | data/full_repos/permissive/8175167/decode/bench/verilog/tb_data.v | 8,175,167 | tb_data.v | v | 150 | 80 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb_data.v:92: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb_data.v:94: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb_data.v:97: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb_data.v:113: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/8175167/decode/bench/verilog/tb_data.v:135: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/8175167/decode/bench/verilog/tb_data.v:142: Unsupported: Ignoring delay on this delayed statement.\n always #7.5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n' | 301,735 | module | module tb_data(
stream_valid, stream_data, stream_empty, fo_full, clk,
ce_decode, rst,
stream_ack, stream_width
);
parameter LZF_FILE = "/home/kevin/lzf-hg.git/lzs/01.lzs";
parameter LZF_WIDTH = 20;
parameter LZF_SIZE = 65536;
parameter IN_WIDTH = 13;
integer src_file , src_cnt;
reg [15:0] left;
reg [63:0] src_char;
reg [15:0] temp;
reg [LZF_WIDTH-1:0] src_size;
output stream_valid;
output [IN_WIDTH-1:0] stream_data;
output stream_empty;
output fo_full;
input stream_ack;
input [3:0] stream_width;
output clk;
output ce_decode;
output rst;
reg ce_decode;
reg clk;
reg fo_full;
reg rst;
reg [IN_WIDTH-1:0] stream_data;
reg stream_empty;
reg stream_valid;
task getword;
input [31:0] file;
output [15:0] data;
reg [7:0] low, high;
begin
high = $fgetc(file);
low = $fgetc(file);
data = high << 8 | low;
end
endtask
reg [255:0] lzs_file;
reg dummy;
initial begin
ce_decode = 0;
fo_full = 0;
rst = 0;
if (0 == $value$plusargs("LZS_FILE=%s", lzs_file))
lzs_file = LZF_FILE;
if (0 == $value$plusargs("LZS_SIZE=%d", src_size))
src_size = LZF_SIZE;
src_file = $fopen(lzs_file, "r");
stream_valid = 0;
stream_data = 0;
stream_empty = 0;
left = 0;
rst = 0;
@(negedge clk);
rst = 1;
@(negedge clk);
@(negedge clk);
rst = 0;
@(negedge clk);
ce_decode = 1;
getword(src_file, temp);
src_char[63:48] = temp;
getword(src_file, temp);
src_char[47:32] = temp;
getword(src_file, temp);
src_char[31:16] = temp;
getword(src_file, temp);
src_char[15:00] = temp;
left = 64;
stream_valid = 1;
for (src_cnt = 2; src_cnt < src_size; dummy = 1) begin
stream_data = src_char[63:64-IN_WIDTH];
@(posedge clk);
if (stream_ack) begin
src_char = src_char << stream_width;
if (left - stream_width < 32) begin
getword(src_file, temp);
$write("data %h, left %d, used %d, %h, temp %h\n",
src_char[63:64-IN_WIDTH], left, stream_width,
src_char, temp);
src_char = src_char | (temp << (48 - left + stream_width));
left = left + 'd16;
src_cnt = src_cnt + 2;
end else begin
$write("data %h, left %d, used %d, %h, temp %h, %h\n",
src_char[63:64-IN_WIDTH], left, stream_width,
src_char, temp, src_char >> 3);
end
left = left - stream_width;
end
end
stream_valid = 0;
stream_empty = 1;
@(negedge clk);
end
initial begin
clk = 1'b0;
end
always #7.5 clk = !clk;
endmodule | module tb_data(
stream_valid, stream_data, stream_empty, fo_full, clk,
ce_decode, rst,
stream_ack, stream_width
); |
parameter LZF_FILE = "/home/kevin/lzf-hg.git/lzs/01.lzs";
parameter LZF_WIDTH = 20;
parameter LZF_SIZE = 65536;
parameter IN_WIDTH = 13;
integer src_file , src_cnt;
reg [15:0] left;
reg [63:0] src_char;
reg [15:0] temp;
reg [LZF_WIDTH-1:0] src_size;
output stream_valid;
output [IN_WIDTH-1:0] stream_data;
output stream_empty;
output fo_full;
input stream_ack;
input [3:0] stream_width;
output clk;
output ce_decode;
output rst;
reg ce_decode;
reg clk;
reg fo_full;
reg rst;
reg [IN_WIDTH-1:0] stream_data;
reg stream_empty;
reg stream_valid;
task getword;
input [31:0] file;
output [15:0] data;
reg [7:0] low, high;
begin
high = $fgetc(file);
low = $fgetc(file);
data = high << 8 | low;
end
endtask
reg [255:0] lzs_file;
reg dummy;
initial begin
ce_decode = 0;
fo_full = 0;
rst = 0;
if (0 == $value$plusargs("LZS_FILE=%s", lzs_file))
lzs_file = LZF_FILE;
if (0 == $value$plusargs("LZS_SIZE=%d", src_size))
src_size = LZF_SIZE;
src_file = $fopen(lzs_file, "r");
stream_valid = 0;
stream_data = 0;
stream_empty = 0;
left = 0;
rst = 0;
@(negedge clk);
rst = 1;
@(negedge clk);
@(negedge clk);
rst = 0;
@(negedge clk);
ce_decode = 1;
getword(src_file, temp);
src_char[63:48] = temp;
getword(src_file, temp);
src_char[47:32] = temp;
getword(src_file, temp);
src_char[31:16] = temp;
getword(src_file, temp);
src_char[15:00] = temp;
left = 64;
stream_valid = 1;
for (src_cnt = 2; src_cnt < src_size; dummy = 1) begin
stream_data = src_char[63:64-IN_WIDTH];
@(posedge clk);
if (stream_ack) begin
src_char = src_char << stream_width;
if (left - stream_width < 32) begin
getword(src_file, temp);
$write("data %h, left %d, used %d, %h, temp %h\n",
src_char[63:64-IN_WIDTH], left, stream_width,
src_char, temp);
src_char = src_char | (temp << (48 - left + stream_width));
left = left + 'd16;
src_cnt = src_cnt + 2;
end else begin
$write("data %h, left %d, used %d, %h, temp %h, %h\n",
src_char[63:64-IN_WIDTH], left, stream_width,
src_char, temp, src_char >> 3);
end
left = left - stream_width;
end
end
stream_valid = 0;
stream_empty = 1;
@(negedge clk);
end
initial begin
clk = 1'b0;
end
always #7.5 clk = !clk;
endmodule | 8 |
138,062 | data/full_repos/permissive/8175167/decode/rtl/verilog/decode.v | 8,175,167 | decode.v | v | 104 | 138 | [] | [] | [] | [(14, 98)] | null | null | 1: b"%Error: data/full_repos/permissive/8175167/decode/rtl/verilog/decode.v:54: Cannot find file containing module: 'decode_in'\n decode_in decode_in ( \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/decode/rtl/verilog,data/full_repos/permissive/8175167/decode_in\n data/full_repos/permissive/8175167/decode/rtl/verilog,data/full_repos/permissive/8175167/decode_in.v\n data/full_repos/permissive/8175167/decode/rtl/verilog,data/full_repos/permissive/8175167/decode_in.sv\n decode_in\n decode_in.v\n decode_in.sv\n obj_dir/decode_in\n obj_dir/decode_in.v\n obj_dir/decode_in.sv\n%Error: data/full_repos/permissive/8175167/decode/rtl/verilog/decode.v:70: Cannot find file containing module: 'decode_ctl'\n decode_ctl decode_ctl ( \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/8175167/decode/rtl/verilog/decode.v:86: Cannot find file containing module: 'decode_out'\n decode_out decode_out ( \n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 301,736 | module | module decode(
valid_o, m_src_getn, done_o, data_o,
src_empty, rst, m_last, fo_full, fi, clk, ce
);
output [15:0] data_o;
output done_o;
output m_src_getn;
output valid_o;
input ce;
input clk;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
wire [7:0] out_data;
wire out_done;
wire out_valid;
wire stream_ack;
wire [12:0] stream_data;
wire stream_done;
wire stream_valid;
wire [3:0] stream_width;
decode_in decode_in (
.m_src_getn (m_src_getn),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.clk (clk),
.rst (rst),
.ce (ce),
.m_last (m_last),
.fo_full (fo_full),
.src_empty (src_empty),
.fi (fi[63:0]),
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack));
decode_ctl decode_ctl (
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack),
.out_data (out_data[7:0]),
.out_valid (out_valid),
.out_done (out_done),
.clk (clk),
.rst (rst),
.ce (ce),
.fo_full (fo_full),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done));
decode_out decode_out (
.data_o (data_o[15:0]),
.valid_o (valid_o),
.done_o (done_o),
.clk (clk),
.rst (rst),
.out_valid (out_valid),
.out_done (out_done),
.out_data (out_data[7:0]));
endmodule | module decode(
valid_o, m_src_getn, done_o, data_o,
src_empty, rst, m_last, fo_full, fi, clk, ce
); |
output [15:0] data_o;
output done_o;
output m_src_getn;
output valid_o;
input ce;
input clk;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
wire [7:0] out_data;
wire out_done;
wire out_valid;
wire stream_ack;
wire [12:0] stream_data;
wire stream_done;
wire stream_valid;
wire [3:0] stream_width;
decode_in decode_in (
.m_src_getn (m_src_getn),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.clk (clk),
.rst (rst),
.ce (ce),
.m_last (m_last),
.fo_full (fo_full),
.src_empty (src_empty),
.fi (fi[63:0]),
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack));
decode_ctl decode_ctl (
.stream_width (stream_width[3:0]),
.stream_ack (stream_ack),
.out_data (out_data[7:0]),
.out_valid (out_valid),
.out_done (out_done),
.clk (clk),
.rst (rst),
.ce (ce),
.fo_full (fo_full),
.stream_data (stream_data[12:0]),
.stream_valid (stream_valid),
.stream_done (stream_done));
decode_out decode_out (
.data_o (data_o[15:0]),
.valid_o (valid_o),
.done_o (done_o),
.clk (clk),
.rst (rst),
.out_valid (out_valid),
.out_done (out_done),
.out_data (out_data[7:0]));
endmodule | 8 |
138,063 | data/full_repos/permissive/8175167/decode/rtl/verilog/decode_ctl.v | 8,175,167 | decode_ctl.v | v | 282 | 80 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/8175167/decode/rtl/verilog/decode_ctl.v:107: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s SEL generates 7 bits.\n : ... In instance decode_ctl\n off_n = stream_data[10:4];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/8175167/decode/rtl/verilog/decode_ctl.v:223: Cannot find file containing module: \'generic_tpram\'\n generic_tpram history_mem (.clk_a(clk),\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/decode/rtl/verilog,data/full_repos/permissive/8175167/generic_tpram\n data/full_repos/permissive/8175167/decode/rtl/verilog,data/full_repos/permissive/8175167/generic_tpram.v\n data/full_repos/permissive/8175167/decode/rtl/verilog,data/full_repos/permissive/8175167/generic_tpram.sv\n generic_tpram\n generic_tpram.v\n generic_tpram.sv\n obj_dir/generic_tpram\n obj_dir/generic_tpram.v\n obj_dir/generic_tpram.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 301,737 | module | module decode_ctl (
stream_width, stream_ack, out_data, out_valid, out_done,
clk, rst, ce, fo_full, stream_data, stream_valid,
stream_done
);
input clk,
rst,
ce,
fo_full;
input [12:0] stream_data;
input stream_valid;
input stream_done;
output [3:0] stream_width;
output stream_ack;
output [7:0] out_data;
output out_valid;
output out_done;
reg stream_ack;
reg [3:0] stream_width;
parameter [2:0]
S_IDLE = 3'h0,
S_PROC = 3'h1,
S_LEN1 = 3'h2,
S_LEN2 = 3'h3,
S_LEN3 = 3'h4,
S_WAIT = 3'h5,
S_COPY = 3'h6,
S_END = 3'h7;
reg [2:0]
state, state_n;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [3:0] cnt, cnt_n;
reg cnt_load, cnt_dec;
reg [10:0] off, off_n;
reg off_load, off_load_n;
reg out_valid_n;
reg [7:0] out_data_n;
always @(ce or cnt or fo_full or state
or stream_data or stream_done or stream_valid)
begin
stream_width = 4'h0;
stream_ack = 1'b0;
state_n = state;
cnt_load = 1'b0;
cnt_n = cnt;
cnt_dec = 1'b0;
off_n = 11'h0;
off_load_n = 1'b0;
out_data_n = 8'h0;
out_valid_n = 1'b0;
case (state)
S_IDLE: begin
if (ce)
state_n = S_PROC;
end
S_PROC: begin
if (stream_valid) begin
if (stream_data[12:4] == 9'b110000000) begin
state_n = S_END;
end else if (~stream_data[12]) begin
stream_width = 4'h9;
stream_ack = 1'b1;
out_valid_n = 1'b1;
out_data_n = stream_data[11:4];
end else begin
if (~stream_data[11]) begin
stream_width = 4'hd;
off_n = stream_data[10:0];
end else begin
stream_width = 4'h9;
off_n = stream_data[10:4];
end
off_load_n = 1'b1;
stream_ack = 1'b1;
state_n = S_LEN1;
end
end else if (stream_done) begin
state_n = S_END;
end
end
S_LEN1: begin
if (stream_valid) begin
stream_width = 4'h2;
stream_ack = 1'b1;
cnt_load = 1'b1;
state_n = S_WAIT;
case (stream_data[12:11])
2'b00: cnt_n = 4'b0010;
2'b01: cnt_n = 4'b0011;
2'b10: cnt_n = 4'b0100;
2'b11: begin
cnt_load = 1'b0;
state_n = S_LEN2;
end
endcase
end else if (stream_done) begin
state_n = S_END;
end
end
S_LEN2: begin
if (stream_valid) begin
stream_width = 4'h2;
stream_ack = 1'b1;
cnt_load = 1'b1;
state_n = S_WAIT;
case (stream_data[12:11])
2'b00: cnt_n = 4'b0101;
2'b01: cnt_n = 4'b0110;
2'b10: cnt_n = 4'b0111;
2'b11: begin
cnt_n = 4'b1000;
state_n = S_COPY;
end
endcase
end else if (stream_done) begin
state_n = S_END;
end
end
S_COPY: begin
if (fo_full) begin
state_n = S_COPY;
end else begin
if (|cnt) begin
cnt_dec = 1'b1;
end else begin
state_n = S_LEN3;
end
end
end
S_LEN3: begin
if (stream_valid) begin
stream_width = 4'h4;
stream_ack = 1'b1;
cnt_load = 1'b1;
cnt_n = stream_data[12:09];
if (stream_data[12:09] == 4'b1111) begin
state_n = S_COPY;
end else begin
state_n = S_WAIT;
end
end else if (stream_done) begin
state_n = S_END;
end
end
S_WAIT: begin
if (fo_full) begin
state_n = S_WAIT;
end else begin
if (|cnt) begin
cnt_dec = 1'b1;
end else begin
state_n = S_PROC;
end
end
end
endcase
end
reg [7:0] out_data_r;
reg out_valid_r;
always @(posedge clk or posedge rst)
begin
if (rst)
out_valid_r <= #1 1'b0;
else
out_valid_r <= #1 out_valid_n;
end
always @(posedge clk)
out_data_r <= #1 out_data_n;
wire [7:0] hdata;
reg [10:0] waddr, raddr;
always @(posedge clk or posedge rst)
begin
if (rst)
waddr <= #1 11'h0;
else if (out_valid)
waddr <= #1 waddr + 1'b1;
end
generic_tpram history_mem (.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
.we_a(out_valid),
.oe_a(1'b0),
.addr_a(waddr),
.di_a(out_data),
.do_a(),
.clk_b(clk),
.rst_b(rst),
.ce_b(1'b1),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(raddr),
.di_b(),
.do_b(hdata));
defparam history_mem.aw = 11;
defparam history_mem.dw = 8;
reg hwe;
always @(posedge clk)
hwe <= #1 cnt_dec;
always @(posedge clk)
begin
if (cnt_load)
cnt <= #1 cnt_n;
else if (cnt_dec)
cnt <= #1 cnt - 1'b1;
end
always @(posedge clk)
begin
off <= #1 off_n;
off_load <= #1 off_load_n;
end
always @(posedge clk)
begin
if (off_load)
raddr <= #1 waddr - off;
else if (cnt_dec)
raddr <= #1 raddr + 1'b1;
end
reg [7:0] out_data_d;
always @(posedge clk)
begin
if (out_valid)
out_data_d <= #1 out_data;
end
assign out_done = state == S_END;
assign out_data = out_valid_r ? out_data_r :
waddr == raddr ? out_data_d : hdata;
assign out_valid = out_valid_r | hwe;
endmodule | module decode_ctl (
stream_width, stream_ack, out_data, out_valid, out_done,
clk, rst, ce, fo_full, stream_data, stream_valid,
stream_done
); |
input clk,
rst,
ce,
fo_full;
input [12:0] stream_data;
input stream_valid;
input stream_done;
output [3:0] stream_width;
output stream_ack;
output [7:0] out_data;
output out_valid;
output out_done;
reg stream_ack;
reg [3:0] stream_width;
parameter [2:0]
S_IDLE = 3'h0,
S_PROC = 3'h1,
S_LEN1 = 3'h2,
S_LEN2 = 3'h3,
S_LEN3 = 3'h4,
S_WAIT = 3'h5,
S_COPY = 3'h6,
S_END = 3'h7;
reg [2:0]
state, state_n;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [3:0] cnt, cnt_n;
reg cnt_load, cnt_dec;
reg [10:0] off, off_n;
reg off_load, off_load_n;
reg out_valid_n;
reg [7:0] out_data_n;
always @(ce or cnt or fo_full or state
or stream_data or stream_done or stream_valid)
begin
stream_width = 4'h0;
stream_ack = 1'b0;
state_n = state;
cnt_load = 1'b0;
cnt_n = cnt;
cnt_dec = 1'b0;
off_n = 11'h0;
off_load_n = 1'b0;
out_data_n = 8'h0;
out_valid_n = 1'b0;
case (state)
S_IDLE: begin
if (ce)
state_n = S_PROC;
end
S_PROC: begin
if (stream_valid) begin
if (stream_data[12:4] == 9'b110000000) begin
state_n = S_END;
end else if (~stream_data[12]) begin
stream_width = 4'h9;
stream_ack = 1'b1;
out_valid_n = 1'b1;
out_data_n = stream_data[11:4];
end else begin
if (~stream_data[11]) begin
stream_width = 4'hd;
off_n = stream_data[10:0];
end else begin
stream_width = 4'h9;
off_n = stream_data[10:4];
end
off_load_n = 1'b1;
stream_ack = 1'b1;
state_n = S_LEN1;
end
end else if (stream_done) begin
state_n = S_END;
end
end
S_LEN1: begin
if (stream_valid) begin
stream_width = 4'h2;
stream_ack = 1'b1;
cnt_load = 1'b1;
state_n = S_WAIT;
case (stream_data[12:11])
2'b00: cnt_n = 4'b0010;
2'b01: cnt_n = 4'b0011;
2'b10: cnt_n = 4'b0100;
2'b11: begin
cnt_load = 1'b0;
state_n = S_LEN2;
end
endcase
end else if (stream_done) begin
state_n = S_END;
end
end
S_LEN2: begin
if (stream_valid) begin
stream_width = 4'h2;
stream_ack = 1'b1;
cnt_load = 1'b1;
state_n = S_WAIT;
case (stream_data[12:11])
2'b00: cnt_n = 4'b0101;
2'b01: cnt_n = 4'b0110;
2'b10: cnt_n = 4'b0111;
2'b11: begin
cnt_n = 4'b1000;
state_n = S_COPY;
end
endcase
end else if (stream_done) begin
state_n = S_END;
end
end
S_COPY: begin
if (fo_full) begin
state_n = S_COPY;
end else begin
if (|cnt) begin
cnt_dec = 1'b1;
end else begin
state_n = S_LEN3;
end
end
end
S_LEN3: begin
if (stream_valid) begin
stream_width = 4'h4;
stream_ack = 1'b1;
cnt_load = 1'b1;
cnt_n = stream_data[12:09];
if (stream_data[12:09] == 4'b1111) begin
state_n = S_COPY;
end else begin
state_n = S_WAIT;
end
end else if (stream_done) begin
state_n = S_END;
end
end
S_WAIT: begin
if (fo_full) begin
state_n = S_WAIT;
end else begin
if (|cnt) begin
cnt_dec = 1'b1;
end else begin
state_n = S_PROC;
end
end
end
endcase
end
reg [7:0] out_data_r;
reg out_valid_r;
always @(posedge clk or posedge rst)
begin
if (rst)
out_valid_r <= #1 1'b0;
else
out_valid_r <= #1 out_valid_n;
end
always @(posedge clk)
out_data_r <= #1 out_data_n;
wire [7:0] hdata;
reg [10:0] waddr, raddr;
always @(posedge clk or posedge rst)
begin
if (rst)
waddr <= #1 11'h0;
else if (out_valid)
waddr <= #1 waddr + 1'b1;
end
generic_tpram history_mem (.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
.we_a(out_valid),
.oe_a(1'b0),
.addr_a(waddr),
.di_a(out_data),
.do_a(),
.clk_b(clk),
.rst_b(rst),
.ce_b(1'b1),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(raddr),
.di_b(),
.do_b(hdata));
defparam history_mem.aw = 11;
defparam history_mem.dw = 8;
reg hwe;
always @(posedge clk)
hwe <= #1 cnt_dec;
always @(posedge clk)
begin
if (cnt_load)
cnt <= #1 cnt_n;
else if (cnt_dec)
cnt <= #1 cnt - 1'b1;
end
always @(posedge clk)
begin
off <= #1 off_n;
off_load <= #1 off_load_n;
end
always @(posedge clk)
begin
if (off_load)
raddr <= #1 waddr - off;
else if (cnt_dec)
raddr <= #1 raddr + 1'b1;
end
reg [7:0] out_data_d;
always @(posedge clk)
begin
if (out_valid)
out_data_d <= #1 out_data;
end
assign out_done = state == S_END;
assign out_data = out_valid_r ? out_data_r :
waddr == raddr ? out_data_d : hdata;
assign out_valid = out_valid_r | hwe;
endmodule | 8 |
138,065 | data/full_repos/permissive/8175167/decode/rtl/verilog/decode_out.v | 8,175,167 | decode_out.v | v | 68 | 80 | [] | [] | [] | [(13, 67)] | null | data/verilator_xmls/dc9d5a0e-287c-4eac-bcce-c8cf91d4c5f9.xml | null | 301,739 | module | module decode_out (
data_o, valid_o, done_o,
clk, rst, out_valid, out_done, out_data
);
input clk,
rst;
input out_valid, out_done;
input [7:0] out_data;
output [15:0] data_o;
output valid_o, done_o;
reg [15:0] data_o;
reg done_o;
reg valid_o;
reg cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 1'b0;
else if (out_valid)
cnt <= #1 cnt + 1'b1;
end
always @(posedge clk)
begin
if (~cnt && out_valid)
data_o[7:0] <= #1 out_data;
end
always @(posedge clk)
begin
if (cnt && out_valid)
data_o[15:8] <= #1 out_data;
end
always @(posedge clk)
begin
if ((&cnt) && out_valid)
valid_o <= #1 1'b1;
else
valid_o <= #1 1'b0;
end
always @(posedge clk)
done_o <= #1 out_done;
endmodule | module decode_out (
data_o, valid_o, done_o,
clk, rst, out_valid, out_done, out_data
); |
input clk,
rst;
input out_valid, out_done;
input [7:0] out_data;
output [15:0] data_o;
output valid_o, done_o;
reg [15:0] data_o;
reg done_o;
reg valid_o;
reg cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 1'b0;
else if (out_valid)
cnt <= #1 cnt + 1'b1;
end
always @(posedge clk)
begin
if (~cnt && out_valid)
data_o[7:0] <= #1 out_data;
end
always @(posedge clk)
begin
if (cnt && out_valid)
data_o[15:8] <= #1 out_data;
end
always @(posedge clk)
begin
if ((&cnt) && out_valid)
valid_o <= #1 1'b1;
else
valid_o <= #1 1'b0;
end
always @(posedge clk)
done_o <= #1 out_done;
endmodule | 8 |
138,066 | data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v | 8,175,167 | system_tb.v | v | 232 | 80 | [] | [] | [] | null | line:27: before: "=" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n forever #(sys_clk_PERIOD/2.00)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n #(sys_rst_LENGTH) sys_rst = ~sys_rst;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:34: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] IP2Bus_Data;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:39: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] Bus2IP_Addr;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:40: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] Bus2IP_Data;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:42: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3] Bus2IP_BE;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:44: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire [0:7] Bus2IP_BurstLength;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:52: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] IP2Bus_Mst_Addr;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:53: Little bit endian vector: MSB < LSB of bit range: 0:3\n reg [0:3] IP2Bus_Mst_BE;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:61: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] Bus2IP_MstRd_d;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:63: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] IP2Bus_MstWr_d;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:69: Little bit endian vector: MSB < LSB of bit range: 0:9\n reg [0:9] DCR_ABus;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:70: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] DCR_Sl_DBus;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:72: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] Sl_dcrDBus;\n ^\n%Error: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:75: Cannot find file containing module: \'system\'\n system\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/edk/simulation/behavioral,data/full_repos/permissive/8175167/system\n data/full_repos/permissive/8175167/edk/simulation/behavioral,data/full_repos/permissive/8175167/system.v\n data/full_repos/permissive/8175167/edk/simulation/behavioral,data/full_repos/permissive/8175167/system.sv\n system\n system.v\n system.sv\n obj_dir/system\n obj_dir/system.v\n obj_dir/system.sv\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:142: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] IP2Bus_Data_i;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:150: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] IP2Bus_Mst_Addr_i;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:151: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3] IP2Bus_Mst_BE_i;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:154: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] IP2Bus_MstWr_d_i;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:158: Little bit endian vector: MSB < LSB of bit range: 0:9\n wire [0:9] DCR_ABus_i;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:159: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] DCR_Sl_DBus_i;\n ^\n%Error: data/full_repos/permissive/8175167/edk/simulation/behavioral/system_tb.v:182: Cannot find file containing module: \'lldma_tb\'\n lldma_tb \n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,741 | module | module system_tb
(
);
real sys_clk_PERIOD = 10000.000000;
real sys_rst_LENGTH = 160000;
reg sys_clk;
reg sys_rst;
wire Bus2IP_Clk;
wire Bus2IP_Reset;
reg [0:31] IP2Bus_Data;
reg IP2Bus_WrAck;
reg IP2Bus_RdAck;
reg IP2Bus_AddrAck;
reg IP2Bus_Error;
wire [0:31] Bus2IP_Addr;
wire [0:31] Bus2IP_Data;
wire Bus2IP_RNW;
wire [0:3] Bus2IP_BE;
wire Bus2IP_Burst;
wire [0:7] Bus2IP_BurstLength;
wire Bus2IP_CS;
wire Bus2IP_WrReq;
wire Bus2IP_RdReq;
wire Bus2IP_RdCE;
wire Bus2IP_WrCE;
reg IP2Bus_MstRd_Req;
reg IP2Bus_MstWr_Req;
reg [0:31] IP2Bus_Mst_Addr;
reg [0:3] IP2Bus_Mst_BE;
reg IP2Bus_Mst_Lock;
reg IP2Bus_Mst_Reset;
wire Bus2IP_Mst_CmdAck;
wire Bus2IP_Mst_Cmplt;
wire Bus2IP_Mst_Error;
wire Bus2IP_Mst_Rearbitrate;
wire Bus2IP_Mst_Cmd_Timeout;
wire [0:31] Bus2IP_MstRd_d;
wire Bus2IP_MstRd_src_rdy_n;
reg [0:31] IP2Bus_MstWr_d;
wire Bus2IP_MstWr_dst_rdy_n;
wire tx_interrupt;
wire rx_interrupt;
reg DCR_Read;
reg DCR_Write;
reg [0:9] DCR_ABus;
reg [0:31] DCR_Sl_DBus;
wire Sl_dcrAck;
wire [0:31] Sl_dcrDBus;
wire Sl_dcrTimeoutWait;
system
dut (
.sys_clk ( sys_clk ),
.sys_rst ( sys_rst ),
.Bus2IP_Clk ( Bus2IP_Clk ),
.Bus2IP_Reset ( Bus2IP_Reset ),
.IP2Bus_Data ( IP2Bus_Data ),
.IP2Bus_WrAck ( IP2Bus_WrAck ),
.IP2Bus_RdAck ( IP2Bus_RdAck ),
.IP2Bus_AddrAck ( IP2Bus_AddrAck ),
.IP2Bus_Error ( IP2Bus_Error ),
.Bus2IP_Addr ( Bus2IP_Addr ),
.Bus2IP_Data ( Bus2IP_Data ),
.Bus2IP_RNW ( Bus2IP_RNW ),
.Bus2IP_BE ( Bus2IP_BE ),
.Bus2IP_Burst ( Bus2IP_Burst ),
.Bus2IP_BurstLength ( Bus2IP_BurstLength ),
.Bus2IP_CS ( Bus2IP_CS ),
.Bus2IP_WrReq ( Bus2IP_WrReq ),
.Bus2IP_RdReq ( Bus2IP_RdReq ),
.Bus2IP_RdCE ( Bus2IP_RdCE ),
.Bus2IP_WrCE ( Bus2IP_WrCE ),
.IP2Bus_MstRd_Req ( IP2Bus_MstRd_Req ),
.IP2Bus_MstWr_Req ( IP2Bus_MstWr_Req ),
.IP2Bus_Mst_Addr ( IP2Bus_Mst_Addr ),
.IP2Bus_Mst_BE ( IP2Bus_Mst_BE ),
.IP2Bus_Mst_Lock ( IP2Bus_Mst_Lock ),
.IP2Bus_Mst_Reset ( IP2Bus_Mst_Reset ),
.Bus2IP_Mst_CmdAck ( Bus2IP_Mst_CmdAck ),
.Bus2IP_Mst_Cmplt ( Bus2IP_Mst_Cmplt ),
.Bus2IP_Mst_Error ( Bus2IP_Mst_Error ),
.Bus2IP_Mst_Rearbitrate ( Bus2IP_Mst_Rearbitrate ),
.Bus2IP_Mst_Cmd_Timeout ( Bus2IP_Mst_Cmd_Timeout ),
.Bus2IP_MstRd_d ( Bus2IP_MstRd_d ),
.Bus2IP_MstRd_src_rdy_n ( Bus2IP_MstRd_src_rdy_n ),
.IP2Bus_MstWr_d ( IP2Bus_MstWr_d ),
.Bus2IP_MstWr_dst_rdy_n ( Bus2IP_MstWr_dst_rdy_n ),
.tx_interrupt ( tx_interrupt ),
.rx_interrupt ( rx_interrupt ),
.DCR_Read ( DCR_Read ),
.DCR_Write ( DCR_Write ),
.DCR_ABus ( DCR_ABus ),
.DCR_Sl_DBus ( DCR_Sl_DBus ),
.Sl_dcrAck ( Sl_dcrAck ),
.Sl_dcrDBus ( Sl_dcrDBus ),
.Sl_dcrTimeoutWait ( Sl_dcrTimeoutWait )
);
initial
begin
sys_clk = 1'b0;
forever #(sys_clk_PERIOD/2.00)
sys_clk = ~sys_clk;
end
initial
begin
sys_rst = 1'b0;
#(sys_rst_LENGTH) sys_rst = ~sys_rst;
end
wire [0:31] IP2Bus_Data_i;
wire IP2Bus_WrAck_i;
wire IP2Bus_RdAck_i;
wire IP2Bus_AddrAck_i;
wire IP2Bus_Error_i;
wire IP2Bus_MstRd_Req_i;
wire IP2Bus_MstWr_Req_i;
wire [0:31] IP2Bus_Mst_Addr_i;
wire [0:3] IP2Bus_Mst_BE_i;
wire IP2Bus_Mst_Lock_i;
wire IP2Bus_Mst_Reset_i;
wire [0:31] IP2Bus_MstWr_d_i;
wire DCR_Read_i;
wire DCR_Write_i;
wire [0:9] DCR_ABus_i;
wire [0:31] DCR_Sl_DBus_i;
always @(*)
begin
IP2Bus_Data = IP2Bus_Data_i;
IP2Bus_WrAck = IP2Bus_WrAck_i;
IP2Bus_RdAck = IP2Bus_RdAck_i;
IP2Bus_AddrAck = IP2Bus_AddrAck_i;
IP2Bus_Error = IP2Bus_Error_i;
IP2Bus_MstRd_Req=IP2Bus_MstRd_Req_i;
IP2Bus_MstWr_Req=IP2Bus_MstWr_Req_i;
IP2Bus_Mst_Addr=IP2Bus_Mst_Addr_i;
IP2Bus_Mst_BE=IP2Bus_Mst_BE_i;
IP2Bus_Mst_Lock=IP2Bus_Mst_Lock_i;
IP2Bus_Mst_Reset=IP2Bus_Mst_Reset_i;
IP2Bus_MstWr_d=IP2Bus_MstWr_d_i;
DCR_Sl_DBus = DCR_Sl_DBus_i;
DCR_ABus = DCR_ABus_i;
DCR_Read = DCR_Read_i;
DCR_Write = DCR_Write_i;
end
lldma_tb
lldma_tb (
.rx_interrupt(rx_interrupt),
.tx_interrrupt(tx_interrupt),
.Bus2IP_Clk ( Bus2IP_Clk ),
.Bus2IP_Reset ( Bus2IP_Reset ),
.IP2Bus_Data ( IP2Bus_Data_i ),
.IP2Bus_WrAck ( IP2Bus_WrAck_i ),
.IP2Bus_RdAck ( IP2Bus_RdAck_i ),
.IP2Bus_AddrAck ( IP2Bus_AddrAck_i ),
.IP2Bus_Error ( IP2Bus_Error_i ),
.Bus2IP_Addr ( Bus2IP_Addr ),
.Bus2IP_Data ( Bus2IP_Data ),
.Bus2IP_RNW ( Bus2IP_RNW ),
.Bus2IP_BE ( Bus2IP_BE ),
.Bus2IP_Burst ( Bus2IP_Burst ),
.Bus2IP_BurstLength ( Bus2IP_BurstLength ),
.Bus2IP_CS ( Bus2IP_CS ),
.Bus2IP_WrReq ( Bus2IP_WrReq ),
.Bus2IP_RdReq ( Bus2IP_RdReq ),
.Bus2IP_RdCE ( Bus2IP_RdCE ),
.IP2Bus_MstRd_Req ( IP2Bus_MstRd_Req_i ),
.IP2Bus_MstWr_Req ( IP2Bus_MstWr_Req_i ),
.IP2Bus_Mst_Addr ( IP2Bus_Mst_Addr_i ),
.IP2Bus_Mst_BE ( IP2Bus_Mst_BE_i ),
.IP2Bus_Mst_Lock ( IP2Bus_Mst_Lock_i ),
.IP2Bus_Mst_Reset ( IP2Bus_Mst_Reset_i ),
.Bus2IP_Mst_CmdAck ( Bus2IP_Mst_CmdAck ),
.Bus2IP_Mst_Cmplt ( Bus2IP_Mst_Cmplt ),
.Bus2IP_Mst_Error ( Bus2IP_Mst_Error ),
.Bus2IP_Mst_Rearbitrate ( Bus2IP_Mst_Rearbitrate ),
.Bus2IP_Mst_Cmd_Timeout ( Bus2IP_Mst_Cmd_Timeout ),
.Bus2IP_MstRd_d ( Bus2IP_MstRd_d ),
.Bus2IP_MstRd_src_rdy_n ( Bus2IP_MstRd_src_rdy_n ),
.IP2Bus_MstWr_d ( IP2Bus_MstWr_d_i ),
.Bus2IP_MstWr_dst_rdy_n ( Bus2IP_MstWr_dst_rdy_n ),
.DCR_Read ( DCR_Read_i ),
.DCR_Write ( DCR_Write_i ),
.DCR_ABus ( DCR_ABus_i ),
.DCR_Sl_DBus ( DCR_Sl_DBus_i ),
.Sl_dcrAck ( Sl_dcrAck ),
.Sl_dcrDBus ( Sl_dcrDBus ),
.Sl_dcrTimeoutWait ( Sl_dcrTimeoutWait )
);
endmodule | module system_tb
(
); |
real sys_clk_PERIOD = 10000.000000;
real sys_rst_LENGTH = 160000;
reg sys_clk;
reg sys_rst;
wire Bus2IP_Clk;
wire Bus2IP_Reset;
reg [0:31] IP2Bus_Data;
reg IP2Bus_WrAck;
reg IP2Bus_RdAck;
reg IP2Bus_AddrAck;
reg IP2Bus_Error;
wire [0:31] Bus2IP_Addr;
wire [0:31] Bus2IP_Data;
wire Bus2IP_RNW;
wire [0:3] Bus2IP_BE;
wire Bus2IP_Burst;
wire [0:7] Bus2IP_BurstLength;
wire Bus2IP_CS;
wire Bus2IP_WrReq;
wire Bus2IP_RdReq;
wire Bus2IP_RdCE;
wire Bus2IP_WrCE;
reg IP2Bus_MstRd_Req;
reg IP2Bus_MstWr_Req;
reg [0:31] IP2Bus_Mst_Addr;
reg [0:3] IP2Bus_Mst_BE;
reg IP2Bus_Mst_Lock;
reg IP2Bus_Mst_Reset;
wire Bus2IP_Mst_CmdAck;
wire Bus2IP_Mst_Cmplt;
wire Bus2IP_Mst_Error;
wire Bus2IP_Mst_Rearbitrate;
wire Bus2IP_Mst_Cmd_Timeout;
wire [0:31] Bus2IP_MstRd_d;
wire Bus2IP_MstRd_src_rdy_n;
reg [0:31] IP2Bus_MstWr_d;
wire Bus2IP_MstWr_dst_rdy_n;
wire tx_interrupt;
wire rx_interrupt;
reg DCR_Read;
reg DCR_Write;
reg [0:9] DCR_ABus;
reg [0:31] DCR_Sl_DBus;
wire Sl_dcrAck;
wire [0:31] Sl_dcrDBus;
wire Sl_dcrTimeoutWait;
system
dut (
.sys_clk ( sys_clk ),
.sys_rst ( sys_rst ),
.Bus2IP_Clk ( Bus2IP_Clk ),
.Bus2IP_Reset ( Bus2IP_Reset ),
.IP2Bus_Data ( IP2Bus_Data ),
.IP2Bus_WrAck ( IP2Bus_WrAck ),
.IP2Bus_RdAck ( IP2Bus_RdAck ),
.IP2Bus_AddrAck ( IP2Bus_AddrAck ),
.IP2Bus_Error ( IP2Bus_Error ),
.Bus2IP_Addr ( Bus2IP_Addr ),
.Bus2IP_Data ( Bus2IP_Data ),
.Bus2IP_RNW ( Bus2IP_RNW ),
.Bus2IP_BE ( Bus2IP_BE ),
.Bus2IP_Burst ( Bus2IP_Burst ),
.Bus2IP_BurstLength ( Bus2IP_BurstLength ),
.Bus2IP_CS ( Bus2IP_CS ),
.Bus2IP_WrReq ( Bus2IP_WrReq ),
.Bus2IP_RdReq ( Bus2IP_RdReq ),
.Bus2IP_RdCE ( Bus2IP_RdCE ),
.Bus2IP_WrCE ( Bus2IP_WrCE ),
.IP2Bus_MstRd_Req ( IP2Bus_MstRd_Req ),
.IP2Bus_MstWr_Req ( IP2Bus_MstWr_Req ),
.IP2Bus_Mst_Addr ( IP2Bus_Mst_Addr ),
.IP2Bus_Mst_BE ( IP2Bus_Mst_BE ),
.IP2Bus_Mst_Lock ( IP2Bus_Mst_Lock ),
.IP2Bus_Mst_Reset ( IP2Bus_Mst_Reset ),
.Bus2IP_Mst_CmdAck ( Bus2IP_Mst_CmdAck ),
.Bus2IP_Mst_Cmplt ( Bus2IP_Mst_Cmplt ),
.Bus2IP_Mst_Error ( Bus2IP_Mst_Error ),
.Bus2IP_Mst_Rearbitrate ( Bus2IP_Mst_Rearbitrate ),
.Bus2IP_Mst_Cmd_Timeout ( Bus2IP_Mst_Cmd_Timeout ),
.Bus2IP_MstRd_d ( Bus2IP_MstRd_d ),
.Bus2IP_MstRd_src_rdy_n ( Bus2IP_MstRd_src_rdy_n ),
.IP2Bus_MstWr_d ( IP2Bus_MstWr_d ),
.Bus2IP_MstWr_dst_rdy_n ( Bus2IP_MstWr_dst_rdy_n ),
.tx_interrupt ( tx_interrupt ),
.rx_interrupt ( rx_interrupt ),
.DCR_Read ( DCR_Read ),
.DCR_Write ( DCR_Write ),
.DCR_ABus ( DCR_ABus ),
.DCR_Sl_DBus ( DCR_Sl_DBus ),
.Sl_dcrAck ( Sl_dcrAck ),
.Sl_dcrDBus ( Sl_dcrDBus ),
.Sl_dcrTimeoutWait ( Sl_dcrTimeoutWait )
);
initial
begin
sys_clk = 1'b0;
forever #(sys_clk_PERIOD/2.00)
sys_clk = ~sys_clk;
end
initial
begin
sys_rst = 1'b0;
#(sys_rst_LENGTH) sys_rst = ~sys_rst;
end
wire [0:31] IP2Bus_Data_i;
wire IP2Bus_WrAck_i;
wire IP2Bus_RdAck_i;
wire IP2Bus_AddrAck_i;
wire IP2Bus_Error_i;
wire IP2Bus_MstRd_Req_i;
wire IP2Bus_MstWr_Req_i;
wire [0:31] IP2Bus_Mst_Addr_i;
wire [0:3] IP2Bus_Mst_BE_i;
wire IP2Bus_Mst_Lock_i;
wire IP2Bus_Mst_Reset_i;
wire [0:31] IP2Bus_MstWr_d_i;
wire DCR_Read_i;
wire DCR_Write_i;
wire [0:9] DCR_ABus_i;
wire [0:31] DCR_Sl_DBus_i;
always @(*)
begin
IP2Bus_Data = IP2Bus_Data_i;
IP2Bus_WrAck = IP2Bus_WrAck_i;
IP2Bus_RdAck = IP2Bus_RdAck_i;
IP2Bus_AddrAck = IP2Bus_AddrAck_i;
IP2Bus_Error = IP2Bus_Error_i;
IP2Bus_MstRd_Req=IP2Bus_MstRd_Req_i;
IP2Bus_MstWr_Req=IP2Bus_MstWr_Req_i;
IP2Bus_Mst_Addr=IP2Bus_Mst_Addr_i;
IP2Bus_Mst_BE=IP2Bus_Mst_BE_i;
IP2Bus_Mst_Lock=IP2Bus_Mst_Lock_i;
IP2Bus_Mst_Reset=IP2Bus_Mst_Reset_i;
IP2Bus_MstWr_d=IP2Bus_MstWr_d_i;
DCR_Sl_DBus = DCR_Sl_DBus_i;
DCR_ABus = DCR_ABus_i;
DCR_Read = DCR_Read_i;
DCR_Write = DCR_Write_i;
end
lldma_tb
lldma_tb (
.rx_interrupt(rx_interrupt),
.tx_interrrupt(tx_interrupt),
.Bus2IP_Clk ( Bus2IP_Clk ),
.Bus2IP_Reset ( Bus2IP_Reset ),
.IP2Bus_Data ( IP2Bus_Data_i ),
.IP2Bus_WrAck ( IP2Bus_WrAck_i ),
.IP2Bus_RdAck ( IP2Bus_RdAck_i ),
.IP2Bus_AddrAck ( IP2Bus_AddrAck_i ),
.IP2Bus_Error ( IP2Bus_Error_i ),
.Bus2IP_Addr ( Bus2IP_Addr ),
.Bus2IP_Data ( Bus2IP_Data ),
.Bus2IP_RNW ( Bus2IP_RNW ),
.Bus2IP_BE ( Bus2IP_BE ),
.Bus2IP_Burst ( Bus2IP_Burst ),
.Bus2IP_BurstLength ( Bus2IP_BurstLength ),
.Bus2IP_CS ( Bus2IP_CS ),
.Bus2IP_WrReq ( Bus2IP_WrReq ),
.Bus2IP_RdReq ( Bus2IP_RdReq ),
.Bus2IP_RdCE ( Bus2IP_RdCE ),
.IP2Bus_MstRd_Req ( IP2Bus_MstRd_Req_i ),
.IP2Bus_MstWr_Req ( IP2Bus_MstWr_Req_i ),
.IP2Bus_Mst_Addr ( IP2Bus_Mst_Addr_i ),
.IP2Bus_Mst_BE ( IP2Bus_Mst_BE_i ),
.IP2Bus_Mst_Lock ( IP2Bus_Mst_Lock_i ),
.IP2Bus_Mst_Reset ( IP2Bus_Mst_Reset_i ),
.Bus2IP_Mst_CmdAck ( Bus2IP_Mst_CmdAck ),
.Bus2IP_Mst_Cmplt ( Bus2IP_Mst_Cmplt ),
.Bus2IP_Mst_Error ( Bus2IP_Mst_Error ),
.Bus2IP_Mst_Rearbitrate ( Bus2IP_Mst_Rearbitrate ),
.Bus2IP_Mst_Cmd_Timeout ( Bus2IP_Mst_Cmd_Timeout ),
.Bus2IP_MstRd_d ( Bus2IP_MstRd_d ),
.Bus2IP_MstRd_src_rdy_n ( Bus2IP_MstRd_src_rdy_n ),
.IP2Bus_MstWr_d ( IP2Bus_MstWr_d_i ),
.Bus2IP_MstWr_dst_rdy_n ( Bus2IP_MstWr_dst_rdy_n ),
.DCR_Read ( DCR_Read_i ),
.DCR_Write ( DCR_Write_i ),
.DCR_ABus ( DCR_ABus_i ),
.DCR_Sl_DBus ( DCR_Sl_DBus_i ),
.Sl_dcrAck ( Sl_dcrAck ),
.Sl_dcrDBus ( Sl_dcrDBus ),
.Sl_dcrTimeoutWait ( Sl_dcrTimeoutWait )
);
endmodule | 8 |
138,068 | data/full_repos/permissive/8175167/encode/bench/verilog/top.v | 8,175,167 | top.v | v | 150 | 80 | [] | [] | [] | null | line:1171: before: "." | null | 1: b'%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:15: Cannot find include file: ../../rtl/verilog/encode_dp.v\n`include "../../rtl/verilog/encode_dp.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/encode/bench/verilog,data/full_repos/permissive/8175167/../../rtl/verilog/encode_dp.v\n data/full_repos/permissive/8175167/encode/bench/verilog,data/full_repos/permissive/8175167/../../rtl/verilog/encode_dp.v.v\n data/full_repos/permissive/8175167/encode/bench/verilog,data/full_repos/permissive/8175167/../../rtl/verilog/encode_dp.v.sv\n ../../rtl/verilog/encode_dp.v\n ../../rtl/verilog/encode_dp.v.v\n ../../rtl/verilog/encode_dp.v.sv\n obj_dir/../../rtl/verilog/encode_dp.v\n obj_dir/../../rtl/verilog/encode_dp.v.v\n obj_dir/../../rtl/verilog/encode_dp.v.sv\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:16: Cannot find include file: ../../rtl/verilog/encode_ctl.v\n`include "../../rtl/verilog/encode_ctl.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:17: Cannot find include file: ../../rtl/verilog/encode_out.v\n`include "../../rtl/verilog/encode_out.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:18: Cannot find include file: ../../rtl/verilog/encode.v\n`include "../../rtl/verilog/encode.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:19: Cannot find include file: data.v\n`include "data.v" \n ^~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:99: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:100: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, top);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:123: Unsupported or unknown PLI call: $dumpflush\n $dumpflush(".");\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:126: Unsupported or unknown PLI call: $fputc\n $fputc(f, encode.out.data_o[15:08]);\n ^~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:135: Unsupported or unknown PLI call: $dumpflush\n $dumpflush(".");\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/bench/verilog/top.v:138: Unsupported or unknown PLI call: $fputc\n $fputc(f, encode.out.data_o[07:00]);\n ^~~~~~\n%Error: Exiting due to 11 error(s)\n' | 301,743 | module | module top(
valid_o, fi_cnt, done_o, data_o,
m_endn
);
parameter LZF_WIDTH = 20;
input m_endn;
output [15:0] data_o;
output done_o;
output [LZF_WIDTH-1:0]fi_cnt;
output valid_o;
wire ce;
wire clk;
wire [63:0] fi;
wire fo_full;
wire m_last;
wire m_src_getn;
wire rst;
wire src_empty;
data data(
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam
data.LZF_FILE = "/tmp/encode.src";
defparam
data.LZF_DEBUG = 0;
defparam
data.LZF_DELAY = 20;
defparam
data.LZF_FIFO_AW = 15;
encode encode(
.data_o (data_o[15:0]),
.done_o (done_o),
.m_src_getn (m_src_getn),
.valid_o (valid_o),
.ce (ce),
.clk (clk),
.fi (fi[63:0]),
.fo_full (fo_full),
.m_last (m_last),
.rst (rst),
.src_empty (src_empty));
parameter OUT_FILE = "/tmp/t.lzs";
integer f;
parameter CHECK_FILE = "/tmp/encode.chk";
integer c, cnt;
initial begin
$dumpfile("tb.vcd");
$dumpvars(0, top);
$write("using %s as source file size is %d\n",
data.LZF_FILE, data.fi_cnt);
$write("using %s as check file\n",
CHECK_FILE);
$write("output file is %s\n",
OUT_FILE);
end
reg [7:0] data;
always @(posedge clk or posedge rst)
begin
if (rst) begin
f = $fopen(OUT_FILE, "w");
c = $fopen(CHECK_FILE, "r");
cnt = 0;
end else if (encode.out.valid_o) begin
data = $fgetc(c);
if (data != encode.out.data_o[15:08]) begin
$write("cnt %h: right/current %h/%h\n",
cnt, data, encode.out.data_o[15:08]);
$dumpflush(".");
$stop;
end
$fputc(f, encode.out.data_o[15:08]);
cnt = cnt + 1;
data = $fgetc(c);
if (data != encode.out.data_o[07:00]) begin
$write("cnt %h: right/current %h/%h\n",
cnt, data, encode.out.data_o[07:00]);
$dumpflush(".");
$stop;
end
$fputc(f, encode.out.data_o[07:00]);
cnt = cnt + 1;
end
end
endmodule | module top(
valid_o, fi_cnt, done_o, data_o,
m_endn
); |
parameter LZF_WIDTH = 20;
input m_endn;
output [15:0] data_o;
output done_o;
output [LZF_WIDTH-1:0]fi_cnt;
output valid_o;
wire ce;
wire clk;
wire [63:0] fi;
wire fo_full;
wire m_last;
wire m_src_getn;
wire rst;
wire src_empty;
data data(
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam
data.LZF_FILE = "/tmp/encode.src";
defparam
data.LZF_DEBUG = 0;
defparam
data.LZF_DELAY = 20;
defparam
data.LZF_FIFO_AW = 15;
encode encode(
.data_o (data_o[15:0]),
.done_o (done_o),
.m_src_getn (m_src_getn),
.valid_o (valid_o),
.ce (ce),
.clk (clk),
.fi (fi[63:0]),
.fo_full (fo_full),
.m_last (m_last),
.rst (rst),
.src_empty (src_empty));
parameter OUT_FILE = "/tmp/t.lzs";
integer f;
parameter CHECK_FILE = "/tmp/encode.chk";
integer c, cnt;
initial begin
$dumpfile("tb.vcd");
$dumpvars(0, top);
$write("using %s as source file size is %d\n",
data.LZF_FILE, data.fi_cnt);
$write("using %s as check file\n",
CHECK_FILE);
$write("output file is %s\n",
OUT_FILE);
end
reg [7:0] data;
always @(posedge clk or posedge rst)
begin
if (rst) begin
f = $fopen(OUT_FILE, "w");
c = $fopen(CHECK_FILE, "r");
cnt = 0;
end else if (encode.out.valid_o) begin
data = $fgetc(c);
if (data != encode.out.data_o[15:08]) begin
$write("cnt %h: right/current %h/%h\n",
cnt, data, encode.out.data_o[15:08]);
$dumpflush(".");
$stop;
end
$fputc(f, encode.out.data_o[15:08]);
cnt = cnt + 1;
data = $fgetc(c);
if (data != encode.out.data_o[07:00]) begin
$write("cnt %h: right/current %h/%h\n",
cnt, data, encode.out.data_o[07:00]);
$dumpflush(".");
$stop;
end
$fputc(f, encode.out.data_o[07:00]);
cnt = cnt + 1;
end
end
endmodule | 8 |
138,069 | data/full_repos/permissive/8175167/encode/rtl/verilog/encode.v | 8,175,167 | encode.v | v | 126 | 80 | [] | [] | [] | null | line:39: before: "," | null | 1: b"%Error: data/full_repos/permissive/8175167/encode/rtl/verilog/encode.v:60: Cannot find file containing module: 'encode_dp'\n encode_dp dp( \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/8175167/encode/rtl/verilog,data/full_repos/permissive/8175167/encode_dp\n data/full_repos/permissive/8175167/encode/rtl/verilog,data/full_repos/permissive/8175167/encode_dp.v\n data/full_repos/permissive/8175167/encode/rtl/verilog,data/full_repos/permissive/8175167/encode_dp.sv\n encode_dp\n encode_dp.v\n encode_dp.sv\n obj_dir/encode_dp\n obj_dir/encode_dp.v\n obj_dir/encode_dp.sv\n%Error: data/full_repos/permissive/8175167/encode/rtl/verilog/encode.v:84: Cannot find file containing module: 'encode_ctl'\n encode_ctl ctl( \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/8175167/encode/rtl/verilog/encode.v:106: Cannot find file containing module: 'encode_out'\n encode_out out( \n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 301,744 | module | module encode(
valid_o, m_src_getn, done_o, data_o,
src_empty, rst, m_last, fo_full, fi, clk, ce
);
parameter LZF_WIDTH = 20;
(* PERIOD = "5000ps" *)
input clk;
input ce;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
output [15:0] data_o;
output done_o;
output m_src_getn;
output valid_o;
wire cnt_finish;
wire [3:0] cnt_len;
wire [12:0] cnt_output;
wire cnt_output_enable;
wire [7:0] data;
wire [7:0] data_d1;
wire [7:0] data_d2;
wire data_empty;
wire data_valid;
wire [7:0] hash_d1;
wire [7:0] hash_data;
wire [7:0] hash_data1;
wire hash_data_d1;
wire [LZF_WIDTH-1:0] hash_ref;
wire [7:0] hdata;
wire [10:0] hraddr;
wire [LZF_WIDTH-1:0] iidx;
encode_dp dp(
.m_src_getn (m_src_getn),
.data_empty (data_empty),
.data (data[7:0]),
.data_valid (data_valid),
.hash_data (hash_data[7:0]),
.hash_data1 (hash_data1[7:0]),
.hash_ref (hash_ref[LZF_WIDTH-1:0]),
.data_d1 (data_d1[7:0]),
.data_d2 (data_d2[7:0]),
.iidx (iidx[LZF_WIDTH-1:0]),
.hash_d1 (hash_d1[7:0]),
.hash_data_d1 (hash_data_d1),
.hdata (hdata[7:0]),
.clk (clk),
.rst (rst),
.ce (ce),
.fo_full (fo_full),
.fi (fi[63:0]),
.src_empty (src_empty),
.m_last (m_last),
.hraddr (hraddr[10:0]));
encode_ctl ctl(
.hraddr (hraddr[10:0]),
.cnt_output_enable (cnt_output_enable),
.cnt_len (cnt_len[3:0]),
.cnt_output (cnt_output[12:0]),
.cnt_finish (cnt_finish),
.clk (clk),
.rst (rst),
.data_valid (data_valid),
.data_empty (data_empty),
.hash_data (hash_data[7:0]),
.hash_data1 (hash_data1[7:0]),
.data_d1 (data_d1[7:0]),
.data_d2 (data_d2[7:0]),
.hash_ref (hash_ref[LZF_WIDTH-1:0]),
.iidx (iidx[LZF_WIDTH-1:0]),
.hdata (hdata[7:0]),
.data (data[7:0]),
.hash_d1 (hash_d1[7:0]),
.hash_data_d1 (hash_data_d1));
encode_out out(
.data_o (data_o[15:0]),
.valid_o (valid_o),
.done_o (done_o),
.clk (clk),
.rst (rst),
.ce (ce),
.cnt_output_enable (cnt_output_enable),
.cnt_finish (cnt_finish),
.cnt_output (cnt_output[12:0]),
.cnt_len (cnt_len[3:0]));
endmodule | module encode(
valid_o, m_src_getn, done_o, data_o,
src_empty, rst, m_last, fo_full, fi, clk, ce
); |
parameter LZF_WIDTH = 20;
(* PERIOD = "5000ps" *)
input clk;
input ce;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
output [15:0] data_o;
output done_o;
output m_src_getn;
output valid_o;
wire cnt_finish;
wire [3:0] cnt_len;
wire [12:0] cnt_output;
wire cnt_output_enable;
wire [7:0] data;
wire [7:0] data_d1;
wire [7:0] data_d2;
wire data_empty;
wire data_valid;
wire [7:0] hash_d1;
wire [7:0] hash_data;
wire [7:0] hash_data1;
wire hash_data_d1;
wire [LZF_WIDTH-1:0] hash_ref;
wire [7:0] hdata;
wire [10:0] hraddr;
wire [LZF_WIDTH-1:0] iidx;
encode_dp dp(
.m_src_getn (m_src_getn),
.data_empty (data_empty),
.data (data[7:0]),
.data_valid (data_valid),
.hash_data (hash_data[7:0]),
.hash_data1 (hash_data1[7:0]),
.hash_ref (hash_ref[LZF_WIDTH-1:0]),
.data_d1 (data_d1[7:0]),
.data_d2 (data_d2[7:0]),
.iidx (iidx[LZF_WIDTH-1:0]),
.hash_d1 (hash_d1[7:0]),
.hash_data_d1 (hash_data_d1),
.hdata (hdata[7:0]),
.clk (clk),
.rst (rst),
.ce (ce),
.fo_full (fo_full),
.fi (fi[63:0]),
.src_empty (src_empty),
.m_last (m_last),
.hraddr (hraddr[10:0]));
encode_ctl ctl(
.hraddr (hraddr[10:0]),
.cnt_output_enable (cnt_output_enable),
.cnt_len (cnt_len[3:0]),
.cnt_output (cnt_output[12:0]),
.cnt_finish (cnt_finish),
.clk (clk),
.rst (rst),
.data_valid (data_valid),
.data_empty (data_empty),
.hash_data (hash_data[7:0]),
.hash_data1 (hash_data1[7:0]),
.data_d1 (data_d1[7:0]),
.data_d2 (data_d2[7:0]),
.hash_ref (hash_ref[LZF_WIDTH-1:0]),
.iidx (iidx[LZF_WIDTH-1:0]),
.hdata (hdata[7:0]),
.data (data[7:0]),
.hash_d1 (hash_d1[7:0]),
.hash_data_d1 (hash_data_d1));
encode_out out(
.data_o (data_o[15:0]),
.valid_o (valid_o),
.done_o (done_o),
.clk (clk),
.rst (rst),
.ce (ce),
.cnt_output_enable (cnt_output_enable),
.cnt_finish (cnt_finish),
.cnt_output (cnt_output[12:0]),
.cnt_len (cnt_len[3:0]));
endmodule | 8 |
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