Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
137,604 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void post_randomize();
string str_temp;
net_size = (48*2)+16+(payload_size*8);
pad_size = net_size % 64;
str_raw_pkt_crc = {""};
raw_pkt = {this.DA,this.SA,this.ETHER_TYPE};
$sformat(str_temp,"%h",{this.DA,this.SA,this.ETHER_TYPE});
str_raw_pkt_crc = {str_raw_pkt_crc,str_temp};
foreach(PAYLOAD[i]) begin
raw_pkt = {raw_pkt,this.PAYLOAD[i]};
$sformat(str_temp,"%h",this.PAYLOAD[i]);
str_raw_pkt_crc = {str_raw_pkt_crc,str_temp};
end
raw_pkt_crc = raw_pkt;
this.CRC=clc_CRC(net_size);
raw_pkt_crc = {raw_pkt_crc,this.CRC};
$sformat(str_temp,"%h",this.CRC);
str_raw_pkt_crc = {str_raw_pkt_crc,str_temp};
$display("-=-=-=-=-=-=-=-=-=-=RAW PKT-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
$display("%0h",raw_pkt);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
$display("-=-=-=-=-=-=-=-=-=-=RAW PKT CRC-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
$display("%0h",raw_pkt_crc);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
$display("-=-=-=-=-=-=-=-=-=-=STR RAW PKT CRC-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
$display(str_raw_pkt_crc);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
endfunction | function void post_randomize(); |
string str_temp;
net_size = (48*2)+16+(payload_size*8);
pad_size = net_size % 64;
str_raw_pkt_crc = {""};
raw_pkt = {this.DA,this.SA,this.ETHER_TYPE};
$sformat(str_temp,"%h",{this.DA,this.SA,this.ETHER_TYPE});
str_raw_pkt_crc = {str_raw_pkt_crc,str_temp};
foreach(PAYLOAD[i]) begin
raw_pkt = {raw_pkt,this.PAYLOAD[i]};
$sformat(str_temp,"%h",this.PAYLOAD[i]);
str_raw_pkt_crc = {str_raw_pkt_crc,str_temp};
end
raw_pkt_crc = raw_pkt;
this.CRC=clc_CRC(net_size);
raw_pkt_crc = {raw_pkt_crc,this.CRC};
$sformat(str_temp,"%h",this.CRC);
str_raw_pkt_crc = {str_raw_pkt_crc,str_temp};
$display("-=-=-=-=-=-=-=-=-=-=RAW PKT-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
$display("%0h",raw_pkt);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
$display("-=-=-=-=-=-=-=-=-=-=RAW PKT CRC-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
$display("%0h",raw_pkt_crc);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
$display("-=-=-=-=-=-=-=-=-=-=STR RAW PKT CRC-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
$display(str_raw_pkt_crc);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
endfunction | 1 |
137,605 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void build_frame_mem();
integer create_new = (net_size/64);
integer last_ptr,k,j;
reg [7:0] flength;
rem = net_size%64;
flength = rem/8;
case(flength)
8'd0: last_bvalid = 8'b1111_1111;
8'd1: last_bvalid = 8'b1000_0000;
8'd2: last_bvalid = 8'b1100_0000;
8'd3: last_bvalid = 8'b1110_0000;
8'd4: last_bvalid = 8'b1111_0000;
8'd5: last_bvalid = 8'b1111_1000;
8'd6: last_bvalid = 8'b1111_1100;
8'd7: last_bvalid = 8'b1111_1110;
endcase
if(debug_print)
$display("rem:%0d",rem);
if(rem>0)
pack_frame_memload = new [create_new+1];
else
pack_frame_memload = new [create_new];
for(k=0,j=net_size-1;k<(net_size/64);k=k+1,j=j-64) begin
pack_frame_memload[k] = raw_pkt[j-:64];
end
if(rem>0) begin
for(integer l=rem;l>0;l--) begin
pack_frame_memload[k]= {pack_frame_memload[k],raw_pkt[l-1]};
end
for(integer l=64-rem;l>0;l--) begin
pack_frame_memload[k]= {pack_frame_memload[k],1'b0};
end
end
if(debug_print)
$display("net_size:%0d",net_size);
$display("-=-=-=-=-=-=Packed MEM Data-=-=-=-=-=-=-=-=-=-");
for(integer i=0;i<pack_frame_memload.size();i++) begin
$write("%0h",this.pack_frame_memload[i],":");
end
$display("\n-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
frag_length = pack_frame_memload.size();
endfunction | function void build_frame_mem(); |
integer create_new = (net_size/64);
integer last_ptr,k,j;
reg [7:0] flength;
rem = net_size%64;
flength = rem/8;
case(flength)
8'd0: last_bvalid = 8'b1111_1111;
8'd1: last_bvalid = 8'b1000_0000;
8'd2: last_bvalid = 8'b1100_0000;
8'd3: last_bvalid = 8'b1110_0000;
8'd4: last_bvalid = 8'b1111_0000;
8'd5: last_bvalid = 8'b1111_1000;
8'd6: last_bvalid = 8'b1111_1100;
8'd7: last_bvalid = 8'b1111_1110;
endcase
if(debug_print)
$display("rem:%0d",rem);
if(rem>0)
pack_frame_memload = new [create_new+1];
else
pack_frame_memload = new [create_new];
for(k=0,j=net_size-1;k<(net_size/64);k=k+1,j=j-64) begin
pack_frame_memload[k] = raw_pkt[j-:64];
end
if(rem>0) begin
for(integer l=rem;l>0;l--) begin
pack_frame_memload[k]= {pack_frame_memload[k],raw_pkt[l-1]};
end
for(integer l=64-rem;l>0;l--) begin
pack_frame_memload[k]= {pack_frame_memload[k],1'b0};
end
end
if(debug_print)
$display("net_size:%0d",net_size);
$display("-=-=-=-=-=-=Packed MEM Data-=-=-=-=-=-=-=-=-=-");
for(integer i=0;i<pack_frame_memload.size();i++) begin
$write("%0h",this.pack_frame_memload[i],":");
end
$display("\n-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
frag_length = pack_frame_memload.size();
endfunction | 1 |
137,606 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void build_frame_crc();
endfunction | function void build_frame_crc(); |
endfunction | 1 |
137,607 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function new();
endfunction | function new(); |
endfunction | 1 |
137,608 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function reg [31:0] addr_gen();
do
randomize(mem_addr);
while(ethernet_mem_data.exists(mem_addr));
return mem_addr;
endfunction | function reg [31:0] addr_gen(); |
do
randomize(mem_addr);
while(ethernet_mem_data.exists(mem_addr));
return mem_addr;
endfunction | 1 |
137,609 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function new();
eth_frame = new();
addr_gen_obj = new();
endfunction | function new(); |
eth_frame = new();
addr_gen_obj = new();
endfunction | 1 |
137,610 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function string exp_str();
string temp_str;
temp_str = eth_frame.str_raw_pkt_crc;
return temp_str;
endfunction | function string exp_str(); |
string temp_str;
temp_str = eth_frame.str_raw_pkt_crc;
return temp_str;
endfunction | 1 |
137,611 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void build_ethernet_frame();
assert(eth_frame.randomize() with {payload_size==64;});
eth_frame.print();
eth_frame.build_frame_mem();
endfunction | function void build_ethernet_frame(); |
assert(eth_frame.randomize() with {payload_size==64;});
eth_frame.print();
eth_frame.build_frame_mem();
endfunction | 1 |
137,612 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void mem_fill();
assert(addr_gen_obj.randomize());
$display("-=-=-=-=-=-=-=-=-=-=MEM FILL-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
for(integer i=0;i<eth_frame.pack_frame_memload.size();i++) begin
mem_addr_local = addr_gen_obj.addr_gen();
if(ethernet_mem_data.exists(mem_addr_local)) begin
$display("Something Wrong !!!! mem occupied @ addr :%032h",mem_addr_local);
$finish;
end else begin
ethernet_mem_data[mem_addr_local]= eth_frame.pack_frame_memload[i];
$display("%064h stored @ mem location: %032h",eth_frame.pack_frame_memload[i],mem_addr_local);
if(i==0) begin
mem_addr_local_head = mem_addr_local;
end else if(i==(eth_frame.pack_frame_memload.size()-1)) begin
ethernet_mem_link_addr[mem_addr_local] = mem_addr_local_head;
ethernet_mem_link_addr[mem_addr_local_prev] = mem_addr_local;
end else begin
ethernet_mem_link_addr[mem_addr_local_prev] = mem_addr_local;
end
mem_addr_local_prev = mem_addr_local;
end
end
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
if(debug_print) begin
disp_mem();
disp_mem_link_addr();
end
mem_link_hdr_fill();
disp_mem();
link_walk(mem_addr_local_head);
endfunction | function void mem_fill(); |
assert(addr_gen_obj.randomize());
$display("-=-=-=-=-=-=-=-=-=-=MEM FILL-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
for(integer i=0;i<eth_frame.pack_frame_memload.size();i++) begin
mem_addr_local = addr_gen_obj.addr_gen();
if(ethernet_mem_data.exists(mem_addr_local)) begin
$display("Something Wrong !!!! mem occupied @ addr :%032h",mem_addr_local);
$finish;
end else begin
ethernet_mem_data[mem_addr_local]= eth_frame.pack_frame_memload[i];
$display("%064h stored @ mem location: %032h",eth_frame.pack_frame_memload[i],mem_addr_local);
if(i==0) begin
mem_addr_local_head = mem_addr_local;
end else if(i==(eth_frame.pack_frame_memload.size()-1)) begin
ethernet_mem_link_addr[mem_addr_local] = mem_addr_local_head;
ethernet_mem_link_addr[mem_addr_local_prev] = mem_addr_local;
end else begin
ethernet_mem_link_addr[mem_addr_local_prev] = mem_addr_local;
end
mem_addr_local_prev = mem_addr_local;
end
end
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
if(debug_print) begin
disp_mem();
disp_mem_link_addr();
end
mem_link_hdr_fill();
disp_mem();
link_walk(mem_addr_local_head);
endfunction | 1 |
137,613 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function logic [63:0] link_hdr_fill();
create_link_hdr.head_ptr = mem_addr_local_head;
create_link_hdr.ctrl_data.QoS = eth_frame.QoS;
create_link_hdr.ctrl_data.last_bvalid = eth_frame.last_bvalid;
create_link_hdr.ctrl_data.frag_length = eth_frame.frag_length;
create_link_hdr.ctrl_data.reserved = 0;
$display("-=-=-=-=-=-=-=-=-=-=-LINK HDR-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=");
$display("link_hdr head_ptr:%032h Ctrl_data:%032h",create_link_hdr.head_ptr,create_link_hdr.ctrl_data);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
return create_link_hdr;
endfunction | function logic [63:0] link_hdr_fill(); |
create_link_hdr.head_ptr = mem_addr_local_head;
create_link_hdr.ctrl_data.QoS = eth_frame.QoS;
create_link_hdr.ctrl_data.last_bvalid = eth_frame.last_bvalid;
create_link_hdr.ctrl_data.frag_length = eth_frame.frag_length;
create_link_hdr.ctrl_data.reserved = 0;
$display("-=-=-=-=-=-=-=-=-=-=-LINK HDR-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=");
$display("link_hdr head_ptr:%032h Ctrl_data:%032h",create_link_hdr.head_ptr,create_link_hdr.ctrl_data);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
return create_link_hdr;
endfunction | 1 |
137,614 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void mem_link_hdr_fill();
logic [31:0] index;
if(ethernet_mem_link_addr.first(index))
do
ethernet_mem_data[index+8]= ethernet_mem_link_addr[index];
while(ethernet_mem_link_addr.next(index));
endfunction | function void mem_link_hdr_fill(); |
logic [31:0] index;
if(ethernet_mem_link_addr.first(index))
do
ethernet_mem_data[index+8]= ethernet_mem_link_addr[index];
while(ethernet_mem_link_addr.next(index));
endfunction | 1 |
137,615 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void disp_mem();
logic [31:0] index;
$display("-=-=-=-=-=-=-=-=-=-=MEM DISP-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
if(ethernet_mem_data.first(index))
do
$display("mem_location: %064h :: data_stored: %064h",index,ethernet_mem_data[index]);
while(ethernet_mem_data.next(index));
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
endfunction | function void disp_mem(); |
logic [31:0] index;
$display("-=-=-=-=-=-=-=-=-=-=MEM DISP-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
if(ethernet_mem_data.first(index))
do
$display("mem_location: %064h :: data_stored: %064h",index,ethernet_mem_data[index]);
while(ethernet_mem_data.next(index));
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
endfunction | 1 |
137,616 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void disp_mem_link_addr();
logic [31:0] index;
$display("-=-=-=-=-=-=-=-=-=-=MEM LINK DISP-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
if(ethernet_mem_link_addr.first(index))
do
$display("mem_location: %032h :: nxt_mem_link_addr: %032h",index,ethernet_mem_link_addr[index]);
while(ethernet_mem_link_addr.next(index));
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
endfunction | function void disp_mem_link_addr(); |
logic [31:0] index;
$display("-=-=-=-=-=-=-=-=-=-=MEM LINK DISP-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
if(ethernet_mem_link_addr.first(index))
do
$display("mem_location: %032h :: nxt_mem_link_addr: %032h",index,ethernet_mem_link_addr[index]);
while(ethernet_mem_link_addr.next(index));
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
endfunction | 1 |
137,617 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void link_walk(input logic[31:0] start);
logic [31:0] ptr;
ptr = start;
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=LINK WALK-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
do
begin
$display("MEM_ADDR:%032h MEM_DATA:%064h",ptr,ethernet_mem_data[ptr]);
ptr = ethernet_mem_link_addr[ptr];
end
while(start!=ptr);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
endfunction | function void link_walk(input logic[31:0] start); |
logic [31:0] ptr;
ptr = start;
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=LINK WALK-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
do
begin
$display("MEM_ADDR:%032h MEM_DATA:%064h",ptr,ethernet_mem_data[ptr]);
ptr = ethernet_mem_link_addr[ptr];
end
while(start!=ptr);
$display("-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=");
endfunction | 1 |
137,618 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv | 79,197,809 | ethernet_tb.sv | sv | 235 | 93 | [] | [] | [] | null | line:3: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:3: Cannot find include file: files.sv\n`include "files.sv" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv.sv\n files.sv\n files.sv.v\n files.sv.sv\n obj_dir/files.sv\n obj_dir/files.sv.v\n obj_dir/files.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport ethernet_frame_pkg::*;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:34: syntax error, unexpected \'@\', expecting \';\'\ndefault clocking axi_clocking @(posedge clks.clk);\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:41: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.clk = 0;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:47: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.rst = 0;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:49: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.rst = 1;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n f = $fopen("mmap.txt","w");\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:62: syntax error, unexpected do\n do\n ^~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:69: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ethernet_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:71: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mac_core.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:79: syntax error, unexpected while\n while (i<5) begin\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:88: syntax error, unexpected \'=\', expecting \',\' or \';\'\n pkt_gen_mem_fill pkt = new();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:89: syntax error, unexpected \'(\', expecting IDENTIFIER\n pkt.build_ethernet_frame();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:90: syntax error, unexpected \'(\', expecting IDENTIFIER\n pkt.mem_fill();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:93: syntax error, unexpected \'[\', expecting IDENTIFIER\n eth_tx_check.esstore[num]=pkt.exp_str();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:98: syntax error, unexpected \'.\', expecting IDENTIFIER\n tb_axi_master.axi_waddr.push_back(generate_wr_addr_to_axi(num));\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:99: syntax error, unexpected \'.\', expecting IDENTIFIER\n tb_axi_master.axi_wdata.push_back(pkt.link_hdr_fill());\n ^\n%Error: Exiting due to 17 error(s)\n' | 299,858 | module | module ethernet_tb;
AXI_clks clks ();
AXI_rd_addr_ch rd_addr_ch();
AXI_rd_data_ch rd_data_ch();
AXI_wr_data_ch wr_data_ch();
AXI_wr_addr_ch wr_addr_ch();
AXI_wr_resp_ch wr_resp_ch();
tx_xgmii xgmii_tx();
MEMIF_CRC #(.DWIDTH(32),.AWIDTH(4)) memif_crcf0();
MEMIF_CRC #(.DWIDTH(32),.AWIDTH(4)) memif_crcf1();
MEMIF_CRC #(.DWIDTH(32),.AWIDTH(4)) memif_crcf2();
MEMIF_PKTD #(.DWIDTH(64),.AWIDTH(6)) memif_pdfifo0();
MEMIF_PKTD #(.DWIDTH(64),.AWIDTH(6)) memif_pdfifo1();
MEMIF_PKTD #(.DWIDTH(64),.AWIDTH(6)) memif_pdfifo2();
MEMIF_PKTC #(.DWIDTH(16),.AWIDTH(6)) memif_pcfifo0();
MEMIF_PKTC #(.DWIDTH(16),.AWIDTH(6)) memif_pcfifo1();
MEMIF_PKTC #(.DWIDTH(16),.AWIDTH(6)) memif_pcfifo2();
MEMIF_SWCHADDR #(.DWIDTH(36),.AWIDTH(5)) memif_swchaddr();
MEMIF_SWCHDATA #(.DWIDTH(32),.AWIDTH(5)) memif_swchdata();
MEMIF_SWCHRSP #(.DWIDTH(6),.AWIDTH(5)) memif_swchrsp ();
logic [31:0] start_addr;
default clocking axi_clocking @(posedge clks.clk);
endclocking
initial begin
start_addr =32'hFFFF_0008;
clks.clk = 0;
forever #5 clks.clk = ~clks.clk;
end
initial begin
clks.rst = 1; #2;
clks.rst = 0;
##5; #4;
clks.rst = 1;
##10;
traffic_gen();
dump_mem_to_file();
##500;
$finish;
end
function void dump_mem_to_file();
logic [31:0] index;
integer f,w;
f = $fopen("mmap.txt","w");
if(ethernet_mem_data.first(index))
do
$fwrite(f,"mem[%h]=%0h\n",index,ethernet_mem_data[index]);
while(ethernet_mem_data.next(index));
$fclose(f);
endfunction
initial begin
$dumpvars(0,ethernet_tb);
`ifndef CG
$dumpfile("mac_core.vcd");
`else
$dumpfile("mac_core_cg.vcd");
`endif
end
task traffic_gen();
int i =0;
while (i<5) begin
generate_pkt(i);
i++;
end
endtask
task generate_pkt(int num);
pkt_gen_mem_fill pkt = new();
pkt.build_ethernet_frame();
pkt.mem_fill();
$display("-----exp_str store-----");
$display(pkt.exp_str());
eth_tx_check.esstore[num]=pkt.exp_str();
$display("----------------------");
tb_axi_master.axi_waddr.push_back(generate_wr_addr_to_axi(num));
tb_axi_master.axi_wdata.push_back(pkt.link_hdr_fill());
$display("ETH_TB::axi_waddr:%h axi_wdata:%h",tb_axi_master.axi_waddr[num],
tb_axi_master.axi_wdata[num]);
endtask
function logic [31:0] generate_wr_addr_to_axi(int num);
return (start_addr+((num%16)*8));
endfunction
`ifndef GATE
eth_core tx( clks.to_rtl,
wr_addr_ch.slave_if,
wr_data_ch.slave_if,
wr_resp_ch.slave_if,
rd_addr_ch.master_if,
rd_data_ch.master_if,
xgmii_tx.from_rtl,
memif_crcf0,
memif_crcf1,
memif_crcf2,
memif_pdfifo0,
memif_pdfifo1,
memif_pdfifo2,
memif_pcfifo0,
memif_pcfifo1,
memif_pcfifo2,
memif_swchaddr,
memif_swchdata,
memif_swchrsp
);
`else
eth_core TX ( clks.to_rtl.clk ,
clks.to_rtl.rst ,
wr_addr_ch.slave_if.AWID , wr_addr_ch.slave_if.AWADDR ,
wr_addr_ch.slave_if.AWLEN , wr_addr_ch.slave_if.AWSIZE ,
wr_addr_ch.slave_if.AWBURST , wr_addr_ch.slave_if.AWLOCK ,
wr_addr_ch.slave_if.AWCACHE , wr_addr_ch.slave_if.AWPROT ,
wr_addr_ch.slave_if.AWVALID , wr_addr_ch.slave_if.AWREADY ,
wr_data_ch.slave_if.WID , wr_data_ch.slave_if.WDATA ,
wr_data_ch.slave_if.WLAST , wr_data_ch.slave_if.WVALID ,
wr_data_ch.slave_if.WREADY , wr_resp_ch.slave_if.BID ,
wr_resp_ch.slave_if.BRESP , wr_resp_ch.slave_if.BUSER ,
wr_resp_ch.slave_if.BVALID , wr_resp_ch.slave_if.BREADY ,
rd_addr_ch.master_if.ARID , rd_addr_ch.master_if.ARADDR ,
rd_addr_ch.master_if.ARLEN , rd_addr_ch.master_if.ARSIZE ,
rd_addr_ch.master_if.ARBURST , rd_addr_ch.master_if.ARLOCK ,
rd_addr_ch.master_if.ARCACHE , rd_addr_ch.master_if.ARPROT ,
rd_addr_ch.master_if.ARQOS , rd_addr_ch.master_if.ARREGION ,
rd_addr_ch.master_if.ARUSER , rd_addr_ch.master_if.ARVALID ,
rd_addr_ch.master_if.ARREADY , rd_data_ch.master_if.RID ,
rd_data_ch.master_if.RDATA , rd_data_ch.master_if.RRESP ,
rd_data_ch.master_if.RLAST , rd_data_ch.master_if.RUSER ,
rd_data_ch.master_if.RVALID , rd_data_ch.master_if.RREADY ,
xgmii_tx.from_rtl.TXC , xgmii_tx.from_rtl.TXD , xgmii_tx.from_rtl.TXCLK,
memif_crcf0.from_fifo.f0_waddr , memif_crcf0.from_fifo.f0_wdata ,
memif_crcf0.from_fifo.f0_write , memif_crcf0.from_fifo.f0_raddr ,
memif_crcf0.from_fifo.f0_rdata , memif_crcf1.from_fifo.f0_waddr ,
memif_crcf1.from_fifo.f0_wdata , memif_crcf1.from_fifo.f0_write ,
memif_crcf1.from_fifo.f0_raddr , memif_crcf1.from_fifo.f0_rdata ,
memif_crcf2.from_fifo.f0_waddr , memif_crcf2.from_fifo.f0_wdata ,
memif_crcf2.from_fifo.f0_write , memif_crcf2.from_fifo.f0_raddr ,
memif_crcf2.from_fifo.f0_rdata , memif_pdfifo0.from_fifo.f0_waddr ,
memif_pdfifo0.from_fifo.f0_wdata , memif_pdfifo0.from_fifo.f0_write ,
memif_pdfifo0.from_fifo.f0_raddr , memif_pdfifo0.from_fifo.f0_rdata ,
memif_pdfifo1.from_fifo.f0_waddr , memif_pdfifo1.from_fifo.f0_wdata ,
memif_pdfifo1.from_fifo.f0_write , memif_pdfifo1.from_fifo.f0_raddr ,
memif_pdfifo1.from_fifo.f0_rdata , memif_pdfifo2.from_fifo.f0_waddr ,
memif_pdfifo2.from_fifo.f0_wdata , memif_pdfifo2.from_fifo.f0_write ,
memif_pdfifo2.from_fifo.f0_raddr , memif_pdfifo2.from_fifo.f0_rdata ,
memif_pcfifo0.from_fifo.f0_waddr , memif_pcfifo0.from_fifo.f0_wdata ,
memif_pcfifo0.from_fifo.f0_write , memif_pcfifo0.from_fifo.f0_raddr ,
memif_pcfifo0.from_fifo.f0_rdata , memif_pcfifo1.from_fifo.f0_waddr ,
memif_pcfifo1.from_fifo.f0_wdata , memif_pcfifo1.from_fifo.f0_write ,
memif_pcfifo1.from_fifo.f0_raddr , memif_pcfifo1.from_fifo.f0_rdata ,
memif_pcfifo2.from_fifo.f0_waddr , memif_pcfifo2.from_fifo.f0_wdata ,
memif_pcfifo2.from_fifo.f0_write , memif_pcfifo2.from_fifo.f0_raddr ,
memif_pcfifo2.from_fifo.f0_rdata , memif_swchaddr.from_fifo.f0_waddr ,
memif_swchaddr.from_fifo.f0_wdata , memif_swchaddr.from_fifo.f0_write ,
memif_swchaddr.from_fifo.f0_raddr , memif_swchaddr.from_fifo.f0_rdata ,
memif_swchdata.from_fifo.f0_waddr , memif_swchdata.from_fifo.f0_wdata ,
memif_swchdata.from_fifo.f0_write , memif_swchdata.from_fifo.f0_raddr ,
memif_swchdata.from_fifo.f0_rdata , memif_swchrsp.from_fifo.f0_waddr ,
memif_swchrsp.from_fifo.f0_wdata , memif_swchrsp.from_fifo.f0_write ,
memif_swchrsp.from_fifo.f0_raddr , memif_swchrsp.from_fifo.f0_rdata );
`endif
axi_master_model tb_axi_master( wr_addr_ch.master_if,
wr_data_ch.master_if,
wr_resp_ch.master_if,
clks.to_rtl
);
axi_slave_model tb_axi_slave (
clks.to_rtl,
rd_addr_ch.slave_if,
rd_data_ch.slave_if
);
mem_model_crc #(.DWIDTH(32),.AWIDTH(4)) mem_model_crcf0 (memif_crcf0,clks);
mem_model_crc #(.DWIDTH(32),.AWIDTH(4)) mem_model_crcf1 (memif_crcf1,clks);
mem_model_crc #(.DWIDTH(32),.AWIDTH(4)) mem_model_crcf2 (memif_crcf2,clks);
mem_model_pktd #(.DWIDTH(64),.AWIDTH(6)) mem_model_pdfifo0 (memif_pdfifo0,clks);
mem_model_pktd #(.DWIDTH(64),.AWIDTH(6)) mem_model_pdfifo1 (memif_pdfifo1,clks);
mem_model_pktd #(.DWIDTH(64),.AWIDTH(6)) mem_model_pdfifo2 (memif_pdfifo2,clks);
mem_model_pktc #(.DWIDTH(16),.AWIDTH(6)) mem_model_pcfifo0 (memif_pcfifo0,clks);
mem_model_pktc #(.DWIDTH(16),.AWIDTH(6)) mem_model_pcfifo1 (memif_pcfifo1,clks);
mem_model_pktc #(.DWIDTH(16),.AWIDTH(6)) mem_model_pcfifo2 (memif_pcfifo2,clks);
mem_model_swchaddr #(.DWIDTH(36),.AWIDTH(5)) mem_model_swchaddrfifo (memif_swchaddr,clks);
mem_model_swchdata #(.DWIDTH(32),.AWIDTH(5)) mem_model_swchdatafifo (memif_swchdata,clks);
mem_model_swchrsp #(.DWIDTH(6) ,.AWIDTH(5)) mem_model_swchrspfifo (memif_swchrsp ,clks);
eth_tx_protocol_check eth_tx_check(xgmii_tx.to_tb);
`ifdef SAIF_ANA
initial begin
##15;
$set_toggle_region (tx);
$toggle_start;
##480
$toggle_stop;
$toggle_report("eth_core.saif", 3.2e-9, "ethernet_tb.tx");
end
`endif
endmodule | module ethernet_tb; |
AXI_clks clks ();
AXI_rd_addr_ch rd_addr_ch();
AXI_rd_data_ch rd_data_ch();
AXI_wr_data_ch wr_data_ch();
AXI_wr_addr_ch wr_addr_ch();
AXI_wr_resp_ch wr_resp_ch();
tx_xgmii xgmii_tx();
MEMIF_CRC #(.DWIDTH(32),.AWIDTH(4)) memif_crcf0();
MEMIF_CRC #(.DWIDTH(32),.AWIDTH(4)) memif_crcf1();
MEMIF_CRC #(.DWIDTH(32),.AWIDTH(4)) memif_crcf2();
MEMIF_PKTD #(.DWIDTH(64),.AWIDTH(6)) memif_pdfifo0();
MEMIF_PKTD #(.DWIDTH(64),.AWIDTH(6)) memif_pdfifo1();
MEMIF_PKTD #(.DWIDTH(64),.AWIDTH(6)) memif_pdfifo2();
MEMIF_PKTC #(.DWIDTH(16),.AWIDTH(6)) memif_pcfifo0();
MEMIF_PKTC #(.DWIDTH(16),.AWIDTH(6)) memif_pcfifo1();
MEMIF_PKTC #(.DWIDTH(16),.AWIDTH(6)) memif_pcfifo2();
MEMIF_SWCHADDR #(.DWIDTH(36),.AWIDTH(5)) memif_swchaddr();
MEMIF_SWCHDATA #(.DWIDTH(32),.AWIDTH(5)) memif_swchdata();
MEMIF_SWCHRSP #(.DWIDTH(6),.AWIDTH(5)) memif_swchrsp ();
logic [31:0] start_addr;
default clocking axi_clocking @(posedge clks.clk);
endclocking
initial begin
start_addr =32'hFFFF_0008;
clks.clk = 0;
forever #5 clks.clk = ~clks.clk;
end
initial begin
clks.rst = 1; #2;
clks.rst = 0;
##5; #4;
clks.rst = 1;
##10;
traffic_gen();
dump_mem_to_file();
##500;
$finish;
end
function void dump_mem_to_file();
logic [31:0] index;
integer f,w;
f = $fopen("mmap.txt","w");
if(ethernet_mem_data.first(index))
do
$fwrite(f,"mem[%h]=%0h\n",index,ethernet_mem_data[index]);
while(ethernet_mem_data.next(index));
$fclose(f);
endfunction
initial begin
$dumpvars(0,ethernet_tb);
`ifndef CG
$dumpfile("mac_core.vcd");
`else
$dumpfile("mac_core_cg.vcd");
`endif
end
task traffic_gen();
int i =0;
while (i<5) begin
generate_pkt(i);
i++;
end
endtask
task generate_pkt(int num);
pkt_gen_mem_fill pkt = new();
pkt.build_ethernet_frame();
pkt.mem_fill();
$display("-----exp_str store-----");
$display(pkt.exp_str());
eth_tx_check.esstore[num]=pkt.exp_str();
$display("----------------------");
tb_axi_master.axi_waddr.push_back(generate_wr_addr_to_axi(num));
tb_axi_master.axi_wdata.push_back(pkt.link_hdr_fill());
$display("ETH_TB::axi_waddr:%h axi_wdata:%h",tb_axi_master.axi_waddr[num],
tb_axi_master.axi_wdata[num]);
endtask
function logic [31:0] generate_wr_addr_to_axi(int num);
return (start_addr+((num%16)*8));
endfunction
`ifndef GATE
eth_core tx( clks.to_rtl,
wr_addr_ch.slave_if,
wr_data_ch.slave_if,
wr_resp_ch.slave_if,
rd_addr_ch.master_if,
rd_data_ch.master_if,
xgmii_tx.from_rtl,
memif_crcf0,
memif_crcf1,
memif_crcf2,
memif_pdfifo0,
memif_pdfifo1,
memif_pdfifo2,
memif_pcfifo0,
memif_pcfifo1,
memif_pcfifo2,
memif_swchaddr,
memif_swchdata,
memif_swchrsp
);
`else
eth_core TX ( clks.to_rtl.clk ,
clks.to_rtl.rst ,
wr_addr_ch.slave_if.AWID , wr_addr_ch.slave_if.AWADDR ,
wr_addr_ch.slave_if.AWLEN , wr_addr_ch.slave_if.AWSIZE ,
wr_addr_ch.slave_if.AWBURST , wr_addr_ch.slave_if.AWLOCK ,
wr_addr_ch.slave_if.AWCACHE , wr_addr_ch.slave_if.AWPROT ,
wr_addr_ch.slave_if.AWVALID , wr_addr_ch.slave_if.AWREADY ,
wr_data_ch.slave_if.WID , wr_data_ch.slave_if.WDATA ,
wr_data_ch.slave_if.WLAST , wr_data_ch.slave_if.WVALID ,
wr_data_ch.slave_if.WREADY , wr_resp_ch.slave_if.BID ,
wr_resp_ch.slave_if.BRESP , wr_resp_ch.slave_if.BUSER ,
wr_resp_ch.slave_if.BVALID , wr_resp_ch.slave_if.BREADY ,
rd_addr_ch.master_if.ARID , rd_addr_ch.master_if.ARADDR ,
rd_addr_ch.master_if.ARLEN , rd_addr_ch.master_if.ARSIZE ,
rd_addr_ch.master_if.ARBURST , rd_addr_ch.master_if.ARLOCK ,
rd_addr_ch.master_if.ARCACHE , rd_addr_ch.master_if.ARPROT ,
rd_addr_ch.master_if.ARQOS , rd_addr_ch.master_if.ARREGION ,
rd_addr_ch.master_if.ARUSER , rd_addr_ch.master_if.ARVALID ,
rd_addr_ch.master_if.ARREADY , rd_data_ch.master_if.RID ,
rd_data_ch.master_if.RDATA , rd_data_ch.master_if.RRESP ,
rd_data_ch.master_if.RLAST , rd_data_ch.master_if.RUSER ,
rd_data_ch.master_if.RVALID , rd_data_ch.master_if.RREADY ,
xgmii_tx.from_rtl.TXC , xgmii_tx.from_rtl.TXD , xgmii_tx.from_rtl.TXCLK,
memif_crcf0.from_fifo.f0_waddr , memif_crcf0.from_fifo.f0_wdata ,
memif_crcf0.from_fifo.f0_write , memif_crcf0.from_fifo.f0_raddr ,
memif_crcf0.from_fifo.f0_rdata , memif_crcf1.from_fifo.f0_waddr ,
memif_crcf1.from_fifo.f0_wdata , memif_crcf1.from_fifo.f0_write ,
memif_crcf1.from_fifo.f0_raddr , memif_crcf1.from_fifo.f0_rdata ,
memif_crcf2.from_fifo.f0_waddr , memif_crcf2.from_fifo.f0_wdata ,
memif_crcf2.from_fifo.f0_write , memif_crcf2.from_fifo.f0_raddr ,
memif_crcf2.from_fifo.f0_rdata , memif_pdfifo0.from_fifo.f0_waddr ,
memif_pdfifo0.from_fifo.f0_wdata , memif_pdfifo0.from_fifo.f0_write ,
memif_pdfifo0.from_fifo.f0_raddr , memif_pdfifo0.from_fifo.f0_rdata ,
memif_pdfifo1.from_fifo.f0_waddr , memif_pdfifo1.from_fifo.f0_wdata ,
memif_pdfifo1.from_fifo.f0_write , memif_pdfifo1.from_fifo.f0_raddr ,
memif_pdfifo1.from_fifo.f0_rdata , memif_pdfifo2.from_fifo.f0_waddr ,
memif_pdfifo2.from_fifo.f0_wdata , memif_pdfifo2.from_fifo.f0_write ,
memif_pdfifo2.from_fifo.f0_raddr , memif_pdfifo2.from_fifo.f0_rdata ,
memif_pcfifo0.from_fifo.f0_waddr , memif_pcfifo0.from_fifo.f0_wdata ,
memif_pcfifo0.from_fifo.f0_write , memif_pcfifo0.from_fifo.f0_raddr ,
memif_pcfifo0.from_fifo.f0_rdata , memif_pcfifo1.from_fifo.f0_waddr ,
memif_pcfifo1.from_fifo.f0_wdata , memif_pcfifo1.from_fifo.f0_write ,
memif_pcfifo1.from_fifo.f0_raddr , memif_pcfifo1.from_fifo.f0_rdata ,
memif_pcfifo2.from_fifo.f0_waddr , memif_pcfifo2.from_fifo.f0_wdata ,
memif_pcfifo2.from_fifo.f0_write , memif_pcfifo2.from_fifo.f0_raddr ,
memif_pcfifo2.from_fifo.f0_rdata , memif_swchaddr.from_fifo.f0_waddr ,
memif_swchaddr.from_fifo.f0_wdata , memif_swchaddr.from_fifo.f0_write ,
memif_swchaddr.from_fifo.f0_raddr , memif_swchaddr.from_fifo.f0_rdata ,
memif_swchdata.from_fifo.f0_waddr , memif_swchdata.from_fifo.f0_wdata ,
memif_swchdata.from_fifo.f0_write , memif_swchdata.from_fifo.f0_raddr ,
memif_swchdata.from_fifo.f0_rdata , memif_swchrsp.from_fifo.f0_waddr ,
memif_swchrsp.from_fifo.f0_wdata , memif_swchrsp.from_fifo.f0_write ,
memif_swchrsp.from_fifo.f0_raddr , memif_swchrsp.from_fifo.f0_rdata );
`endif
axi_master_model tb_axi_master( wr_addr_ch.master_if,
wr_data_ch.master_if,
wr_resp_ch.master_if,
clks.to_rtl
);
axi_slave_model tb_axi_slave (
clks.to_rtl,
rd_addr_ch.slave_if,
rd_data_ch.slave_if
);
mem_model_crc #(.DWIDTH(32),.AWIDTH(4)) mem_model_crcf0 (memif_crcf0,clks);
mem_model_crc #(.DWIDTH(32),.AWIDTH(4)) mem_model_crcf1 (memif_crcf1,clks);
mem_model_crc #(.DWIDTH(32),.AWIDTH(4)) mem_model_crcf2 (memif_crcf2,clks);
mem_model_pktd #(.DWIDTH(64),.AWIDTH(6)) mem_model_pdfifo0 (memif_pdfifo0,clks);
mem_model_pktd #(.DWIDTH(64),.AWIDTH(6)) mem_model_pdfifo1 (memif_pdfifo1,clks);
mem_model_pktd #(.DWIDTH(64),.AWIDTH(6)) mem_model_pdfifo2 (memif_pdfifo2,clks);
mem_model_pktc #(.DWIDTH(16),.AWIDTH(6)) mem_model_pcfifo0 (memif_pcfifo0,clks);
mem_model_pktc #(.DWIDTH(16),.AWIDTH(6)) mem_model_pcfifo1 (memif_pcfifo1,clks);
mem_model_pktc #(.DWIDTH(16),.AWIDTH(6)) mem_model_pcfifo2 (memif_pcfifo2,clks);
mem_model_swchaddr #(.DWIDTH(36),.AWIDTH(5)) mem_model_swchaddrfifo (memif_swchaddr,clks);
mem_model_swchdata #(.DWIDTH(32),.AWIDTH(5)) mem_model_swchdatafifo (memif_swchdata,clks);
mem_model_swchrsp #(.DWIDTH(6) ,.AWIDTH(5)) mem_model_swchrspfifo (memif_swchrsp ,clks);
eth_tx_protocol_check eth_tx_check(xgmii_tx.to_tb);
`ifdef SAIF_ANA
initial begin
##15;
$set_toggle_region (tx);
$toggle_start;
##480
$toggle_stop;
$toggle_report("eth_core.saif", 3.2e-9, "ethernet_tb.tx");
end
`endif
endmodule | 1 |
137,619 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv | 79,197,809 | ethernet_tb.sv | sv | 235 | 93 | [] | [] | [] | null | line:3: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:3: Cannot find include file: files.sv\n`include "files.sv" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv.sv\n files.sv\n files.sv.v\n files.sv.sv\n obj_dir/files.sv\n obj_dir/files.sv.v\n obj_dir/files.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport ethernet_frame_pkg::*;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:34: syntax error, unexpected \'@\', expecting \';\'\ndefault clocking axi_clocking @(posedge clks.clk);\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:41: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.clk = 0;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:47: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.rst = 0;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:49: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.rst = 1;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n f = $fopen("mmap.txt","w");\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:62: syntax error, unexpected do\n do\n ^~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:69: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ethernet_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:71: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mac_core.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:79: syntax error, unexpected while\n while (i<5) begin\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:88: syntax error, unexpected \'=\', expecting \',\' or \';\'\n pkt_gen_mem_fill pkt = new();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:89: syntax error, unexpected \'(\', expecting IDENTIFIER\n pkt.build_ethernet_frame();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:90: syntax error, unexpected \'(\', expecting IDENTIFIER\n pkt.mem_fill();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:93: syntax error, unexpected \'[\', expecting IDENTIFIER\n eth_tx_check.esstore[num]=pkt.exp_str();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:98: syntax error, unexpected \'.\', expecting IDENTIFIER\n tb_axi_master.axi_waddr.push_back(generate_wr_addr_to_axi(num));\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:99: syntax error, unexpected \'.\', expecting IDENTIFIER\n tb_axi_master.axi_wdata.push_back(pkt.link_hdr_fill());\n ^\n%Error: Exiting due to 17 error(s)\n' | 299,858 | function | function void dump_mem_to_file();
logic [31:0] index;
integer f,w;
f = $fopen("mmap.txt","w");
if(ethernet_mem_data.first(index))
do
$fwrite(f,"mem[%h]=%0h\n",index,ethernet_mem_data[index]);
while(ethernet_mem_data.next(index));
$fclose(f);
endfunction | function void dump_mem_to_file(); |
logic [31:0] index;
integer f,w;
f = $fopen("mmap.txt","w");
if(ethernet_mem_data.first(index))
do
$fwrite(f,"mem[%h]=%0h\n",index,ethernet_mem_data[index]);
while(ethernet_mem_data.next(index));
$fclose(f);
endfunction | 1 |
137,620 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv | 79,197,809 | ethernet_tb.sv | sv | 235 | 93 | [] | [] | [] | null | line:3: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:3: Cannot find include file: files.sv\n`include "files.sv" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/files.sv.sv\n files.sv\n files.sv.v\n files.sv.sv\n obj_dir/files.sv\n obj_dir/files.sv.v\n obj_dir/files.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport ethernet_frame_pkg::*;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:34: syntax error, unexpected \'@\', expecting \';\'\ndefault clocking axi_clocking @(posedge clks.clk);\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:41: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.clk = 0;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:47: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.rst = 0;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:49: syntax error, unexpected \'=\', expecting IDENTIFIER\n clks.rst = 1;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n f = $fopen("mmap.txt","w");\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:62: syntax error, unexpected do\n do\n ^~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:69: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ethernet_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:71: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mac_core.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:79: syntax error, unexpected while\n while (i<5) begin\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:88: syntax error, unexpected \'=\', expecting \',\' or \';\'\n pkt_gen_mem_fill pkt = new();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:89: syntax error, unexpected \'(\', expecting IDENTIFIER\n pkt.build_ethernet_frame();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:90: syntax error, unexpected \'(\', expecting IDENTIFIER\n pkt.mem_fill();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:93: syntax error, unexpected \'[\', expecting IDENTIFIER\n eth_tx_check.esstore[num]=pkt.exp_str();\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:98: syntax error, unexpected \'.\', expecting IDENTIFIER\n tb_axi_master.axi_waddr.push_back(generate_wr_addr_to_axi(num));\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_tb.sv:99: syntax error, unexpected \'.\', expecting IDENTIFIER\n tb_axi_master.axi_wdata.push_back(pkt.link_hdr_fill());\n ^\n%Error: Exiting due to 17 error(s)\n' | 299,858 | function | function logic [31:0] generate_wr_addr_to_axi(int num);
return (start_addr+((num%16)*8));
endfunction | function logic [31:0] generate_wr_addr_to_axi(int num); |
return (start_addr+((num%16)*8));
endfunction | 1 |
137,622 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/TB_CRC_block.sv | 79,197,809 | TB_CRC_block.sv | sv | 228 | 420 | [] | [] | [] | null | line:24: before: "function" | data/verilator_xmls/18d4ced6-ea80-42d7-8ae1-468f0d3756bc.xml | null | 299,862 | function | function [31:0] nextCRC32_D64;
input [63:0] Data;
input [31:0] crc;
reg [63:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[63] ^ d[61] ^ d[60] ^ d[58] ^ d[55] ^ d[54] ^ d[53] ^ d[50] ^ d[48] ^ d[47] ^ d[45] ^ d[44] ^ d[37] ^ d[34] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[2] ^ c[5] ^ c[12] ^ c[13] ^ c[15] ^ c[16] ^ c[18] ^ c[21] ^ c[22] ^ c[23] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[1] = d[63] ^ d[62] ^ d[60] ^ d[59] ^ d[58] ^ d[56] ^ d[53] ^ d[51] ^ d[50] ^ d[49] ^ d[47] ^ d[46] ^ d[44] ^ d[38] ^ d[37] ^ d[35] ^ d[34] ^ d[33] ^ d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[12] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[2] = d[59] ^ d[58] ^ d[57] ^ d[55] ^ d[53] ^ d[52] ^ d[51] ^ d[44] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[32] ^ d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[12] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[27];
newcrc[3] = d[60] ^ d[59] ^ d[58] ^ d[56] ^ d[54] ^ d[53] ^ d[52] ^ d[45] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[33] ^ d[32] ^ d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[0] ^ c[1] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[13] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[28];
newcrc[4] = d[63] ^ d[59] ^ d[58] ^ d[57] ^ d[50] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[44] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[33] ^ d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[1] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[13] ^ c[14] ^ c[15] ^ c[16] ^ c[18] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[5] = d[63] ^ d[61] ^ d[59] ^ d[55] ^ d[54] ^ d[53] ^ d[51] ^ d[50] ^ d[49] ^ d[46] ^ d[44] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[37] ^ d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[12] ^ c[14] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[23] ^ c[27] ^ c[29] ^ c[31];
newcrc[6] = d[62] ^ d[60] ^ d[56] ^ d[55] ^ d[54] ^ d[52] ^ d[51] ^ d[50] ^ d[47] ^ d[45] ^ d[43] ^ d[42] ^ d[41] ^ d[40] ^ d[38] ^ d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[6] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[13] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[28] ^ c[30];
newcrc[7] = d[60] ^ d[58] ^ d[57] ^ d[56] ^ d[54] ^ d[52] ^ d[51] ^ d[50] ^ d[47] ^ d[46] ^ d[45] ^ d[43] ^ d[42] ^ d[41] ^ d[39] ^ d[37] ^ d[34] ^ d[32] ^ d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[5] ^ c[7] ^ c[9] ^ c[10] ^ c[11] ^ c[13] ^ c[14] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[28];
newcrc[8] = d[63] ^ d[60] ^ d[59] ^ d[57] ^ d[54] ^ d[52] ^ d[51] ^ d[50] ^ d[46] ^ d[45] ^ d[43] ^ d[42] ^ d[40] ^ d[38] ^ d[37] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[8] ^ c[10] ^ c[11] ^ c[13] ^ c[14] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[25] ^ c[27] ^ c[28] ^ c[31];
newcrc[9] = d[61] ^ d[60] ^ d[58] ^ d[55] ^ d[53] ^ d[52] ^ d[51] ^ d[47] ^ d[46] ^ d[44] ^ d[43] ^ d[41] ^ d[39] ^ d[38] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[15] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[63] ^ d[62] ^ d[60] ^ d[59] ^ d[58] ^ d[56] ^ d[55] ^ d[52] ^ d[50] ^ d[42] ^ d[40] ^ d[39] ^ d[36] ^ d[35] ^ d[33] ^ d[32] ^ d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[18] ^ c[20] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[11] = d[59] ^ d[58] ^ d[57] ^ d[56] ^ d[55] ^ d[54] ^ d[51] ^ d[50] ^ d[48] ^ d[47] ^ d[45] ^ d[44] ^ d[43] ^ d[41] ^ d[40] ^ d[36] ^ d[33] ^ d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[1] ^ c[4] ^ c[8] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[15] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27];
newcrc[12] = d[63] ^ d[61] ^ d[59] ^ d[57] ^ d[56] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[47] ^ d[46] ^ d[42] ^ d[41] ^ d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29] ^ c[31];
newcrc[13] = d[62] ^ d[60] ^ d[58] ^ d[57] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[48] ^ d[47] ^ d[43] ^ d[42] ^ d[32] ^ d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[0] ^ c[10] ^ c[11] ^ c[15] ^ c[16] ^ c[18] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[14] = d[63] ^ d[61] ^ d[59] ^ d[58] ^ d[56] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[49] ^ d[48] ^ d[44] ^ d[43] ^ d[33] ^ d[32] ^ d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[0] ^ c[1] ^ c[11] ^ c[12] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[15] = d[62] ^ d[60] ^ d[59] ^ d[57] ^ d[56] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[50] ^ d[49] ^ d[45] ^ d[44] ^ d[34] ^ d[33] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[1] ^ c[2] ^ c[12] ^ c[13] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[30];
newcrc[16] = d[57] ^ d[56] ^ d[51] ^ d[48] ^ d[47] ^ d[46] ^ d[44] ^ d[37] ^ d[35] ^ d[32] ^ d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[3] ^ c[5] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[19] ^ c[24] ^ c[25];
newcrc[17] = d[58] ^ d[57] ^ d[52] ^ d[49] ^ d[48] ^ d[47] ^ d[45] ^ d[38] ^ d[36] ^ d[33] ^ d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[4] ^ c[6] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[25] ^ c[26];
newcrc[18] = d[59] ^ d[58] ^ d[53] ^ d[50] ^ d[49] ^ d[48] ^ d[46] ^ d[39] ^ d[37] ^ d[34] ^ d[32] ^ d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[0] ^ c[2] ^ c[5] ^ c[7] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[21] ^ c[26] ^ c[27];
newcrc[19] = d[60] ^ d[59] ^ d[54] ^ d[51] ^ d[50] ^ d[49] ^ d[47] ^ d[40] ^ d[38] ^ d[35] ^ d[33] ^ d[32] ^ d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[0] ^ c[1] ^ c[3] ^ c[6] ^ c[8] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[22] ^ c[27] ^ c[28];
newcrc[20] = d[61] ^ d[60] ^ d[55] ^ d[52] ^ d[51] ^ d[50] ^ d[48] ^ d[41] ^ d[39] ^ d[36] ^ d[34] ^ d[33] ^ d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[1] ^ c[2] ^ c[4] ^ c[7] ^ c[9] ^ c[16] ^ c[18] ^ c[19] ^ c[20] ^ c[23] ^ c[28] ^ c[29];
newcrc[21] = d[62] ^ d[61] ^ d[56] ^ d[53] ^ d[52] ^ d[51] ^ d[49] ^ d[42] ^ d[40] ^ d[37] ^ d[35] ^ d[34] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[2] ^ c[3] ^ c[5] ^ c[8] ^ c[10] ^ c[17] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[29] ^ c[30];
newcrc[22] = d[62] ^ d[61] ^ d[60] ^ d[58] ^ d[57] ^ d[55] ^ d[52] ^ d[48] ^ d[47] ^ d[45] ^ d[44] ^ d[43] ^ d[41] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[2] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[15] ^ c[16] ^ c[20] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[23] = d[62] ^ d[60] ^ d[59] ^ d[56] ^ d[55] ^ d[54] ^ d[50] ^ d[49] ^ d[47] ^ d[46] ^ d[42] ^ d[39] ^ d[38] ^ d[36] ^ d[35] ^ d[34] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[22] ^ c[23] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[24] = d[63] ^ d[61] ^ d[60] ^ d[57] ^ d[56] ^ d[55] ^ d[51] ^ d[50] ^ d[48] ^ d[47] ^ d[43] ^ d[40] ^ d[39] ^ d[37] ^ d[36] ^ d[35] ^ d[32] ^ d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[0] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[25] = d[62] ^ d[61] ^ d[58] ^ d[57] ^ d[56] ^ d[52] ^ d[51] ^ d[49] ^ d[48] ^ d[44] ^ d[41] ^ d[40] ^ d[38] ^ d[37] ^ d[36] ^ d[33] ^ d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[1] ^ c[4] ^ c[5] ^ c[6] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[29] ^ c[30];
newcrc[26] = d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[57] ^ d[55] ^ d[54] ^ d[52] ^ d[49] ^ d[48] ^ d[47] ^ d[44] ^ d[42] ^ d[41] ^ d[39] ^ d[38] ^ d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[6] ^ c[7] ^ c[9] ^ c[10] ^ c[12] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[27] = d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[58] ^ d[56] ^ d[55] ^ d[53] ^ d[50] ^ d[49] ^ d[48] ^ d[45] ^ d[43] ^ d[42] ^ d[40] ^ d[39] ^ d[32] ^ d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[0] ^ c[7] ^ c[8] ^ c[10] ^ c[11] ^ c[13] ^ c[16] ^ c[17] ^ c[18] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[28] = d[63] ^ d[62] ^ d[61] ^ d[59] ^ d[57] ^ d[56] ^ d[54] ^ d[51] ^ d[50] ^ d[49] ^ d[46] ^ d[44] ^ d[43] ^ d[41] ^ d[40] ^ d[33] ^ d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[1] ^ c[8] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[17] ^ c[18] ^ c[19] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[29] = d[63] ^ d[62] ^ d[60] ^ d[58] ^ d[57] ^ d[55] ^ d[52] ^ d[51] ^ d[50] ^ d[47] ^ d[45] ^ d[44] ^ d[42] ^ d[41] ^ d[34] ^ d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[2] ^ c[9] ^ c[10] ^ c[12] ^ c[13] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30] ^ c[31];
newcrc[30] = d[63] ^ d[61] ^ d[59] ^ d[58] ^ d[56] ^ d[53] ^ d[52] ^ d[51] ^ d[48] ^ d[46] ^ d[45] ^ d[43] ^ d[42] ^ d[35] ^ d[32] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[0] ^ c[3] ^ c[10] ^ c[11] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[31] = d[62] ^ d[60] ^ d[59] ^ d[57] ^ d[54] ^ d[53] ^ d[52] ^ d[49] ^ d[47] ^ d[46] ^ d[44] ^ d[43] ^ d[36] ^ d[33] ^ d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[1] ^ c[4] ^ c[11] ^ c[12] ^ c[14] ^ c[15] ^ c[17] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[27] ^ c[28] ^ c[30];
nextCRC32_D64 = newcrc;
end
endfunction | function [31:0] nextCRC32_D64; |
input [63:0] Data;
input [31:0] crc;
reg [63:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[63] ^ d[61] ^ d[60] ^ d[58] ^ d[55] ^ d[54] ^ d[53] ^ d[50] ^ d[48] ^ d[47] ^ d[45] ^ d[44] ^ d[37] ^ d[34] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[2] ^ c[5] ^ c[12] ^ c[13] ^ c[15] ^ c[16] ^ c[18] ^ c[21] ^ c[22] ^ c[23] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[1] = d[63] ^ d[62] ^ d[60] ^ d[59] ^ d[58] ^ d[56] ^ d[53] ^ d[51] ^ d[50] ^ d[49] ^ d[47] ^ d[46] ^ d[44] ^ d[38] ^ d[37] ^ d[35] ^ d[34] ^ d[33] ^ d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[12] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[2] = d[59] ^ d[58] ^ d[57] ^ d[55] ^ d[53] ^ d[52] ^ d[51] ^ d[44] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[32] ^ d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[12] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[27];
newcrc[3] = d[60] ^ d[59] ^ d[58] ^ d[56] ^ d[54] ^ d[53] ^ d[52] ^ d[45] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[33] ^ d[32] ^ d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[0] ^ c[1] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[13] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[28];
newcrc[4] = d[63] ^ d[59] ^ d[58] ^ d[57] ^ d[50] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[44] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[33] ^ d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[1] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[13] ^ c[14] ^ c[15] ^ c[16] ^ c[18] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[5] = d[63] ^ d[61] ^ d[59] ^ d[55] ^ d[54] ^ d[53] ^ d[51] ^ d[50] ^ d[49] ^ d[46] ^ d[44] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[37] ^ d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[12] ^ c[14] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[23] ^ c[27] ^ c[29] ^ c[31];
newcrc[6] = d[62] ^ d[60] ^ d[56] ^ d[55] ^ d[54] ^ d[52] ^ d[51] ^ d[50] ^ d[47] ^ d[45] ^ d[43] ^ d[42] ^ d[41] ^ d[40] ^ d[38] ^ d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[6] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[13] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[28] ^ c[30];
newcrc[7] = d[60] ^ d[58] ^ d[57] ^ d[56] ^ d[54] ^ d[52] ^ d[51] ^ d[50] ^ d[47] ^ d[46] ^ d[45] ^ d[43] ^ d[42] ^ d[41] ^ d[39] ^ d[37] ^ d[34] ^ d[32] ^ d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[5] ^ c[7] ^ c[9] ^ c[10] ^ c[11] ^ c[13] ^ c[14] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[28];
newcrc[8] = d[63] ^ d[60] ^ d[59] ^ d[57] ^ d[54] ^ d[52] ^ d[51] ^ d[50] ^ d[46] ^ d[45] ^ d[43] ^ d[42] ^ d[40] ^ d[38] ^ d[37] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[8] ^ c[10] ^ c[11] ^ c[13] ^ c[14] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[25] ^ c[27] ^ c[28] ^ c[31];
newcrc[9] = d[61] ^ d[60] ^ d[58] ^ d[55] ^ d[53] ^ d[52] ^ d[51] ^ d[47] ^ d[46] ^ d[44] ^ d[43] ^ d[41] ^ d[39] ^ d[38] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[15] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[63] ^ d[62] ^ d[60] ^ d[59] ^ d[58] ^ d[56] ^ d[55] ^ d[52] ^ d[50] ^ d[42] ^ d[40] ^ d[39] ^ d[36] ^ d[35] ^ d[33] ^ d[32] ^ d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[18] ^ c[20] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[11] = d[59] ^ d[58] ^ d[57] ^ d[56] ^ d[55] ^ d[54] ^ d[51] ^ d[50] ^ d[48] ^ d[47] ^ d[45] ^ d[44] ^ d[43] ^ d[41] ^ d[40] ^ d[36] ^ d[33] ^ d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[1] ^ c[4] ^ c[8] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[15] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27];
newcrc[12] = d[63] ^ d[61] ^ d[59] ^ d[57] ^ d[56] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[47] ^ d[46] ^ d[42] ^ d[41] ^ d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29] ^ c[31];
newcrc[13] = d[62] ^ d[60] ^ d[58] ^ d[57] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[48] ^ d[47] ^ d[43] ^ d[42] ^ d[32] ^ d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[0] ^ c[10] ^ c[11] ^ c[15] ^ c[16] ^ c[18] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[14] = d[63] ^ d[61] ^ d[59] ^ d[58] ^ d[56] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[49] ^ d[48] ^ d[44] ^ d[43] ^ d[33] ^ d[32] ^ d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[0] ^ c[1] ^ c[11] ^ c[12] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[15] = d[62] ^ d[60] ^ d[59] ^ d[57] ^ d[56] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[50] ^ d[49] ^ d[45] ^ d[44] ^ d[34] ^ d[33] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[1] ^ c[2] ^ c[12] ^ c[13] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[30];
newcrc[16] = d[57] ^ d[56] ^ d[51] ^ d[48] ^ d[47] ^ d[46] ^ d[44] ^ d[37] ^ d[35] ^ d[32] ^ d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[3] ^ c[5] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[19] ^ c[24] ^ c[25];
newcrc[17] = d[58] ^ d[57] ^ d[52] ^ d[49] ^ d[48] ^ d[47] ^ d[45] ^ d[38] ^ d[36] ^ d[33] ^ d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[4] ^ c[6] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[25] ^ c[26];
newcrc[18] = d[59] ^ d[58] ^ d[53] ^ d[50] ^ d[49] ^ d[48] ^ d[46] ^ d[39] ^ d[37] ^ d[34] ^ d[32] ^ d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[0] ^ c[2] ^ c[5] ^ c[7] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[21] ^ c[26] ^ c[27];
newcrc[19] = d[60] ^ d[59] ^ d[54] ^ d[51] ^ d[50] ^ d[49] ^ d[47] ^ d[40] ^ d[38] ^ d[35] ^ d[33] ^ d[32] ^ d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[0] ^ c[1] ^ c[3] ^ c[6] ^ c[8] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[22] ^ c[27] ^ c[28];
newcrc[20] = d[61] ^ d[60] ^ d[55] ^ d[52] ^ d[51] ^ d[50] ^ d[48] ^ d[41] ^ d[39] ^ d[36] ^ d[34] ^ d[33] ^ d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[1] ^ c[2] ^ c[4] ^ c[7] ^ c[9] ^ c[16] ^ c[18] ^ c[19] ^ c[20] ^ c[23] ^ c[28] ^ c[29];
newcrc[21] = d[62] ^ d[61] ^ d[56] ^ d[53] ^ d[52] ^ d[51] ^ d[49] ^ d[42] ^ d[40] ^ d[37] ^ d[35] ^ d[34] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[2] ^ c[3] ^ c[5] ^ c[8] ^ c[10] ^ c[17] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[29] ^ c[30];
newcrc[22] = d[62] ^ d[61] ^ d[60] ^ d[58] ^ d[57] ^ d[55] ^ d[52] ^ d[48] ^ d[47] ^ d[45] ^ d[44] ^ d[43] ^ d[41] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[2] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[15] ^ c[16] ^ c[20] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[23] = d[62] ^ d[60] ^ d[59] ^ d[56] ^ d[55] ^ d[54] ^ d[50] ^ d[49] ^ d[47] ^ d[46] ^ d[42] ^ d[39] ^ d[38] ^ d[36] ^ d[35] ^ d[34] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[22] ^ c[23] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[24] = d[63] ^ d[61] ^ d[60] ^ d[57] ^ d[56] ^ d[55] ^ d[51] ^ d[50] ^ d[48] ^ d[47] ^ d[43] ^ d[40] ^ d[39] ^ d[37] ^ d[36] ^ d[35] ^ d[32] ^ d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[0] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[25] = d[62] ^ d[61] ^ d[58] ^ d[57] ^ d[56] ^ d[52] ^ d[51] ^ d[49] ^ d[48] ^ d[44] ^ d[41] ^ d[40] ^ d[38] ^ d[37] ^ d[36] ^ d[33] ^ d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[1] ^ c[4] ^ c[5] ^ c[6] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[29] ^ c[30];
newcrc[26] = d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[57] ^ d[55] ^ d[54] ^ d[52] ^ d[49] ^ d[48] ^ d[47] ^ d[44] ^ d[42] ^ d[41] ^ d[39] ^ d[38] ^ d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[6] ^ c[7] ^ c[9] ^ c[10] ^ c[12] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[27] = d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[58] ^ d[56] ^ d[55] ^ d[53] ^ d[50] ^ d[49] ^ d[48] ^ d[45] ^ d[43] ^ d[42] ^ d[40] ^ d[39] ^ d[32] ^ d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[0] ^ c[7] ^ c[8] ^ c[10] ^ c[11] ^ c[13] ^ c[16] ^ c[17] ^ c[18] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[28] = d[63] ^ d[62] ^ d[61] ^ d[59] ^ d[57] ^ d[56] ^ d[54] ^ d[51] ^ d[50] ^ d[49] ^ d[46] ^ d[44] ^ d[43] ^ d[41] ^ d[40] ^ d[33] ^ d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[1] ^ c[8] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[17] ^ c[18] ^ c[19] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[29] = d[63] ^ d[62] ^ d[60] ^ d[58] ^ d[57] ^ d[55] ^ d[52] ^ d[51] ^ d[50] ^ d[47] ^ d[45] ^ d[44] ^ d[42] ^ d[41] ^ d[34] ^ d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[2] ^ c[9] ^ c[10] ^ c[12] ^ c[13] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30] ^ c[31];
newcrc[30] = d[63] ^ d[61] ^ d[59] ^ d[58] ^ d[56] ^ d[53] ^ d[52] ^ d[51] ^ d[48] ^ d[46] ^ d[45] ^ d[43] ^ d[42] ^ d[35] ^ d[32] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[0] ^ c[3] ^ c[10] ^ c[11] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[31] = d[62] ^ d[60] ^ d[59] ^ d[57] ^ d[54] ^ d[53] ^ d[52] ^ d[49] ^ d[47] ^ d[46] ^ d[44] ^ d[43] ^ d[36] ^ d[33] ^ d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[1] ^ c[4] ^ c[11] ^ c[12] ^ c[14] ^ c[15] ^ c[17] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[27] ^ c[28] ^ c[30];
nextCRC32_D64 = newcrc;
end
endfunction | 1 |
137,623 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/TB_CRC_block.sv | 79,197,809 | TB_CRC_block.sv | sv | 228 | 420 | [] | [] | [] | null | line:24: before: "function" | data/verilator_xmls/18d4ced6-ea80-42d7-8ae1-468f0d3756bc.xml | null | 299,862 | function | function [31:0] nextCRC32_D8;
input [7:0] Data;
input [31:0] crc;
reg [7:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[6] ^ d[0] ^ c[24] ^ c[30];
newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[30] ^ c[31];
newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[24] ^ c[26] ^ c[27] ^ c[29];
newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[25] ^ c[26] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[10] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[7] ^ d[3] ^ c[11] ^ c[27] ^ c[31];
newcrc[20] = d[4] ^ c[12] ^ c[28];
newcrc[21] = d[5] ^ c[13] ^ c[29];
newcrc[22] = d[0] ^ c[14] ^ c[24];
newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[15] ^ c[24] ^ c[25] ^ c[30];
newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[16] ^ c[25] ^ c[26] ^ c[31];
newcrc[25] = d[3] ^ d[2] ^ c[17] ^ c[26] ^ c[27];
newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[18] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[19] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[20] ^ c[26] ^ c[29] ^ c[30];
newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[21] ^ c[27] ^ c[30] ^ c[31];
newcrc[30] = d[7] ^ d[4] ^ c[22] ^ c[28] ^ c[31];
newcrc[31] = d[5] ^ c[23] ^ c[29];
nextCRC32_D8 = newcrc;
end
endfunction | function [31:0] nextCRC32_D8; |
input [7:0] Data;
input [31:0] crc;
reg [7:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[6] ^ d[0] ^ c[24] ^ c[30];
newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[30] ^ c[31];
newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[24] ^ c[26] ^ c[27] ^ c[29];
newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[25] ^ c[26] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[10] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[7] ^ d[3] ^ c[11] ^ c[27] ^ c[31];
newcrc[20] = d[4] ^ c[12] ^ c[28];
newcrc[21] = d[5] ^ c[13] ^ c[29];
newcrc[22] = d[0] ^ c[14] ^ c[24];
newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[15] ^ c[24] ^ c[25] ^ c[30];
newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[16] ^ c[25] ^ c[26] ^ c[31];
newcrc[25] = d[3] ^ d[2] ^ c[17] ^ c[26] ^ c[27];
newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[18] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[19] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[20] ^ c[26] ^ c[29] ^ c[30];
newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[21] ^ c[27] ^ c[30] ^ c[31];
newcrc[30] = d[7] ^ d[4] ^ c[22] ^ c[28] ^ c[31];
newcrc[31] = d[5] ^ c[23] ^ c[29];
nextCRC32_D8 = newcrc;
end
endfunction | 1 |
137,624 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/TB_CRC_block.sv | 79,197,809 | TB_CRC_block.sv | sv | 228 | 420 | [] | [] | [] | null | line:24: before: "function" | data/verilator_xmls/18d4ced6-ea80-42d7-8ae1-468f0d3756bc.xml | null | 299,862 | function | function [31:0] nextCRC32_D16;
input [15:0] Data;
input [31:0] crc;
reg [15:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[16] ^ c[22] ^ c[25] ^ c[26] ^ c[28];
newcrc[1] = d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[28] ^ c[29];
newcrc[2] = d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[18] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[29] ^ c[30];
newcrc[3] = d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[4] = d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[16] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[24] ^ c[27] ^ c[28] ^ c[31];
newcrc[5] = d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[26] ^ c[29];
newcrc[6] = d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[27] ^ c[30];
newcrc[7] = d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[16] ^ c[18] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[31];
newcrc[8] = d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[24] ^ c[26] ^ c[27] ^ c[28];
newcrc[9] = d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[25] ^ c[27] ^ c[28] ^ c[29];
newcrc[10] = d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[16] ^ c[18] ^ c[19] ^ c[21] ^ c[25] ^ c[29] ^ c[30];
newcrc[11] = d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[25] ^ c[28] ^ c[30] ^ c[31];
newcrc[12] = d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[13] = d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[23] ^ c[26] ^ c[29] ^ c[30];
newcrc[14] = d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[15] = d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[31];
newcrc[16] = d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[16] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[17] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[18] ^ c[22] ^ c[23] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[19] ^ c[23] ^ c[24] ^ c[27] ^ c[31];
newcrc[20] = d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[20] ^ c[24] ^ c[25] ^ c[28];
newcrc[21] = d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[21] ^ c[25] ^ c[26] ^ c[29];
newcrc[22] = d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[6] ^ c[16] ^ c[25] ^ c[27] ^ c[28] ^ c[30];
newcrc[23] = d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[7] ^ c[16] ^ c[17] ^ c[22] ^ c[25] ^ c[29] ^ c[31];
newcrc[24] = d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[8] ^ c[17] ^ c[18] ^ c[23] ^ c[26] ^ c[30];
newcrc[25] = d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[9] ^ c[18] ^ c[19] ^ c[24] ^ c[27] ^ c[31];
newcrc[26] = d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[10] ^ c[16] ^ c[19] ^ c[20] ^ c[22] ^ c[26];
newcrc[27] = d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[11] ^ c[17] ^ c[20] ^ c[21] ^ c[23] ^ c[27];
newcrc[28] = d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[12] ^ c[18] ^ c[21] ^ c[22] ^ c[24] ^ c[28];
newcrc[29] = d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[13] ^ c[19] ^ c[22] ^ c[23] ^ c[25] ^ c[29];
newcrc[30] = d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[14] ^ c[20] ^ c[23] ^ c[24] ^ c[26] ^ c[30];
newcrc[31] = d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[15] ^ c[21] ^ c[24] ^ c[25] ^ c[27] ^ c[31];
nextCRC32_D16 = newcrc;
end
endfunction | function [31:0] nextCRC32_D16; |
input [15:0] Data;
input [31:0] crc;
reg [15:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[16] ^ c[22] ^ c[25] ^ c[26] ^ c[28];
newcrc[1] = d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[28] ^ c[29];
newcrc[2] = d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[18] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[29] ^ c[30];
newcrc[3] = d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[4] = d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[16] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[24] ^ c[27] ^ c[28] ^ c[31];
newcrc[5] = d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[26] ^ c[29];
newcrc[6] = d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[27] ^ c[30];
newcrc[7] = d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[16] ^ c[18] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[31];
newcrc[8] = d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[24] ^ c[26] ^ c[27] ^ c[28];
newcrc[9] = d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[25] ^ c[27] ^ c[28] ^ c[29];
newcrc[10] = d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[16] ^ c[18] ^ c[19] ^ c[21] ^ c[25] ^ c[29] ^ c[30];
newcrc[11] = d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[25] ^ c[28] ^ c[30] ^ c[31];
newcrc[12] = d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[13] = d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[23] ^ c[26] ^ c[29] ^ c[30];
newcrc[14] = d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[15] = d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[31];
newcrc[16] = d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[16] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[17] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[18] ^ c[22] ^ c[23] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[19] ^ c[23] ^ c[24] ^ c[27] ^ c[31];
newcrc[20] = d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[20] ^ c[24] ^ c[25] ^ c[28];
newcrc[21] = d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[21] ^ c[25] ^ c[26] ^ c[29];
newcrc[22] = d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[6] ^ c[16] ^ c[25] ^ c[27] ^ c[28] ^ c[30];
newcrc[23] = d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[7] ^ c[16] ^ c[17] ^ c[22] ^ c[25] ^ c[29] ^ c[31];
newcrc[24] = d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[8] ^ c[17] ^ c[18] ^ c[23] ^ c[26] ^ c[30];
newcrc[25] = d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[9] ^ c[18] ^ c[19] ^ c[24] ^ c[27] ^ c[31];
newcrc[26] = d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[10] ^ c[16] ^ c[19] ^ c[20] ^ c[22] ^ c[26];
newcrc[27] = d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[11] ^ c[17] ^ c[20] ^ c[21] ^ c[23] ^ c[27];
newcrc[28] = d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[12] ^ c[18] ^ c[21] ^ c[22] ^ c[24] ^ c[28];
newcrc[29] = d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[13] ^ c[19] ^ c[22] ^ c[23] ^ c[25] ^ c[29];
newcrc[30] = d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[14] ^ c[20] ^ c[23] ^ c[24] ^ c[26] ^ c[30];
newcrc[31] = d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[15] ^ c[21] ^ c[24] ^ c[25] ^ c[27] ^ c[31];
nextCRC32_D16 = newcrc;
end
endfunction | 1 |
137,625 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/TB_CRC_block.sv | 79,197,809 | TB_CRC_block.sv | sv | 228 | 420 | [] | [] | [] | null | line:24: before: "function" | data/verilator_xmls/18d4ced6-ea80-42d7-8ae1-468f0d3756bc.xml | null | 299,862 | function | function [31:0] nextCRC32_D32;
input [31:0] Data;
input [31:0] crc;
reg [31:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[9] ^ c[10] ^ c[12] ^ c[16] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[1] = d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[16] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
newcrc[2] = d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[24] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[25] ^ c[27] ^ c[31];
newcrc[4] = d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[8] ^ c[11] ^ c[12] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[29] ^ c[30] ^ c[31];
newcrc[5] = d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[6] = d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[7] = d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[7] ^ c[8] ^ c[10] ^ c[15] ^ c[16] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29];
newcrc[8] = d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[8] ^ c[10] ^ c[11] ^ c[12] ^ c[17] ^ c[22] ^ c[23] ^ c[28] ^ c[31];
newcrc[9] = d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[18] ^ c[23] ^ c[24] ^ c[29];
newcrc[10] = d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[11] = d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
newcrc[12] = d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[12] ^ c[13] ^ c[15] ^ c[17] ^ c[18] ^ c[21] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[13] = d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[25] ^ c[28] ^ c[31];
newcrc[14] = d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[20] ^ c[23] ^ c[26] ^ c[29];
newcrc[15] = d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[15] ^ c[16] ^ c[18] ^ c[20] ^ c[21] ^ c[24] ^ c[27] ^ c[30];
newcrc[16] = d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[4] ^ c[5] ^ c[8] ^ c[12] ^ c[13] ^ c[17] ^ c[19] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[29] ^ c[30];
newcrc[17] = d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[5] ^ c[6] ^ c[9] ^ c[13] ^ c[14] ^ c[18] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[30] ^ c[31];
newcrc[18] = d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[31];
newcrc[19] = d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29];
newcrc[20] = d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[21] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[9] ^ c[10] ^ c[13] ^ c[17] ^ c[18] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[22] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[0] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[23] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[9] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[24] = d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[7] ^ c[10] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[27] ^ c[28] ^ c[30];
newcrc[25] = d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[8] ^ c[11] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[28] ^ c[29] ^ c[31];
newcrc[26] = d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[6] ^ c[10] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[31];
newcrc[27] = d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[1] ^ c[4] ^ c[5] ^ c[7] ^ c[11] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[29];
newcrc[28] = d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[2] ^ c[5] ^ c[6] ^ c[8] ^ c[12] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[29] = d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[3] ^ c[6] ^ c[7] ^ c[9] ^ c[13] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[30] = d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[14] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[31] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[5] ^ c[8] ^ c[9] ^ c[11] ^ c[15] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
nextCRC32_D32 = newcrc;
end
endfunction | function [31:0] nextCRC32_D32; |
input [31:0] Data;
input [31:0] crc;
reg [31:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[9] ^ c[10] ^ c[12] ^ c[16] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[1] = d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[16] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
newcrc[2] = d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[24] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[25] ^ c[27] ^ c[31];
newcrc[4] = d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[8] ^ c[11] ^ c[12] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[29] ^ c[30] ^ c[31];
newcrc[5] = d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[6] = d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[7] = d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[7] ^ c[8] ^ c[10] ^ c[15] ^ c[16] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29];
newcrc[8] = d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[8] ^ c[10] ^ c[11] ^ c[12] ^ c[17] ^ c[22] ^ c[23] ^ c[28] ^ c[31];
newcrc[9] = d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[18] ^ c[23] ^ c[24] ^ c[29];
newcrc[10] = d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[11] = d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
newcrc[12] = d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[12] ^ c[13] ^ c[15] ^ c[17] ^ c[18] ^ c[21] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[13] = d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[25] ^ c[28] ^ c[31];
newcrc[14] = d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[20] ^ c[23] ^ c[26] ^ c[29];
newcrc[15] = d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[15] ^ c[16] ^ c[18] ^ c[20] ^ c[21] ^ c[24] ^ c[27] ^ c[30];
newcrc[16] = d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[4] ^ c[5] ^ c[8] ^ c[12] ^ c[13] ^ c[17] ^ c[19] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[29] ^ c[30];
newcrc[17] = d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[5] ^ c[6] ^ c[9] ^ c[13] ^ c[14] ^ c[18] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[30] ^ c[31];
newcrc[18] = d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[31];
newcrc[19] = d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29];
newcrc[20] = d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[21] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[9] ^ c[10] ^ c[13] ^ c[17] ^ c[18] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[22] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[0] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[23] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[9] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[24] = d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[7] ^ c[10] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[27] ^ c[28] ^ c[30];
newcrc[25] = d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[8] ^ c[11] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[28] ^ c[29] ^ c[31];
newcrc[26] = d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[6] ^ c[10] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[31];
newcrc[27] = d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[1] ^ c[4] ^ c[5] ^ c[7] ^ c[11] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[29];
newcrc[28] = d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[2] ^ c[5] ^ c[6] ^ c[8] ^ c[12] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[29] = d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[3] ^ c[6] ^ c[7] ^ c[9] ^ c[13] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[30] = d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[14] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[31] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[5] ^ c[8] ^ c[9] ^ c[11] ^ c[15] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
nextCRC32_D32 = newcrc;
end
endfunction | 1 |
137,626 | data/full_repos/permissive/79199761/delay_eight_cycles.v | 79,199,761 | delay_eight_cycles.v | v | 39 | 104 | [] | [] | [] | [(3, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:26: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_1 (.in(in_value), .out(value_1_2), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79199761,data/full_repos/permissive/79199761/Nbit_reg\n data/full_repos/permissive/79199761,data/full_repos/permissive/79199761/Nbit_reg.v\n data/full_repos/permissive/79199761,data/full_repos/permissive/79199761/Nbit_reg.sv\n Nbit_reg\n Nbit_reg.v\n Nbit_reg.sv\n obj_dir/Nbit_reg\n obj_dir/Nbit_reg.v\n obj_dir/Nbit_reg.sv\n%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:27: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_2 (.in(value_1_2),.out(value_2_3), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:28: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_3 (.in(value_2_3), .out(value_3_4), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:29: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_4 (.in(value_3_4), .out(value_4_5), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:30: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_5 (.in(value_4_5), .out(value_5_6), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:31: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_6 (.in(value_5_6), .out(value_6_7), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:32: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_7 (.in(value_6_7), .out(value_7_8), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/79199761/delay_eight_cycles.v:33: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(n) stage_8 (.in(value_7_8), .out(value_8_9), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));\n ^~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 299,863 | module | module delay_eight_cycles( clk,
gwe,
rst,
in_value,
out_value
);
parameter n = 1;
input clk;
input gwe;
input rst;
input [n-1:0] in_value;
output [n-1:0] out_value;
wire [n-1:0] value_1_2;
wire [n-1:0] value_2_3;
wire [n-1:0] value_3_4;
wire [n-1:0] value_4_5;
wire [n-1:0] value_5_6;
wire [n-1:0] value_6_7;
wire [n-1:0] value_7_8;
wire [n-1:0] value_8_9;
Nbit_reg #(n) stage_1 (.in(in_value), .out(value_1_2), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_2 (.in(value_1_2),.out(value_2_3), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_3 (.in(value_2_3), .out(value_3_4), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_4 (.in(value_3_4), .out(value_4_5), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_5 (.in(value_4_5), .out(value_5_6), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_6 (.in(value_5_6), .out(value_6_7), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_7 (.in(value_6_7), .out(value_7_8), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_8 (.in(value_7_8), .out(value_8_9), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
assign out_value = value_8_9;
endmodule | module delay_eight_cycles( clk,
gwe,
rst,
in_value,
out_value
); |
parameter n = 1;
input clk;
input gwe;
input rst;
input [n-1:0] in_value;
output [n-1:0] out_value;
wire [n-1:0] value_1_2;
wire [n-1:0] value_2_3;
wire [n-1:0] value_3_4;
wire [n-1:0] value_4_5;
wire [n-1:0] value_5_6;
wire [n-1:0] value_6_7;
wire [n-1:0] value_7_8;
wire [n-1:0] value_8_9;
Nbit_reg #(n) stage_1 (.in(in_value), .out(value_1_2), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_2 (.in(value_1_2),.out(value_2_3), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_3 (.in(value_2_3), .out(value_3_4), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_4 (.in(value_3_4), .out(value_4_5), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_5 (.in(value_4_5), .out(value_5_6), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_6 (.in(value_5_6), .out(value_6_7), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_7 (.in(value_6_7), .out(value_7_8), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
Nbit_reg #(n) stage_8 (.in(value_7_8), .out(value_8_9), .clk(clk), .we(1'd1), .gwe(gwe), .rst(rst));
assign out_value = value_8_9;
endmodule | 0 |
137,627 | data/full_repos/permissive/79199761/DUAL_RAM.v | 79,199,761 | DUAL_RAM.v | v | 29 | 62 | [] | [] | [] | [(2, 26)] | null | data/verilator_xmls/f30b1000-5955-4af1-bac2-40a9443ab3b8.xml | null | 299,864 | module | module ram_1r1w(clk, gwe, rst, rsel, rdata, wsel, wdata, we);
parameter bit_width = 16;
parameter addr_width = 3;
localparam ram_size = 1 << addr_width;
input clk, gwe, rst;
input [addr_width-1:0] rsel, wsel;
input [bit_width-1:0] wdata;
input we;
output [bit_width-1:0] rdata;
reg [bit_width-1:0] mem_state [ram_size-1:0];
integer i;
assign #(1) rdata = mem_state[rsel];
always @(posedge clk)
begin
if (gwe & rst)
for (i=0; i<ram_size; i=i+1)
mem_state[i] = 0;
else if (gwe & we)
mem_state[wsel] = wdata;
end
endmodule | module ram_1r1w(clk, gwe, rst, rsel, rdata, wsel, wdata, we); |
parameter bit_width = 16;
parameter addr_width = 3;
localparam ram_size = 1 << addr_width;
input clk, gwe, rst;
input [addr_width-1:0] rsel, wsel;
input [bit_width-1:0] wdata;
input we;
output [bit_width-1:0] rdata;
reg [bit_width-1:0] mem_state [ram_size-1:0];
integer i;
assign #(1) rdata = mem_state[rsel];
always @(posedge clk)
begin
if (gwe & rst)
for (i=0; i<ram_size; i=i+1)
mem_state[i] = 0;
else if (gwe & we)
mem_state[wsel] = wdata;
end
endmodule | 0 |
137,628 | data/full_repos/permissive/79199761/lc4_insn_cache.v | 79,199,761 | lc4_insn_cache.v | v | 103 | 128 | [] | [] | [] | null | line:85: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/79199761/lc4_insn_cache.v:32: Signal definition not found, creating implicitly: \'vld\'\n : ... Suggested alternative: \'cvld\'\nassign vld = cmem[blockid][16];\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/79199761/lc4_insn_cache.v:31: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n : ... In instance lc4_insn_cache\nassign tag = addr[15:7];\n ^\n%Warning-WIDTH: data/full_repos/permissive/79199761/lc4_insn_cache.v:86: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n : ... In instance lc4_insn_cache\n cmem[i] <= #0 16\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79199761/lc4_insn_cache.v:91: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 8 bits.\n : ... In instance lc4_insn_cache\n tagcmem[miss_addr_8d[6:0]] <= #1 miss_8d ? miss_addr_8d[15:7]:tagcmem[miss_addr_8d[6:0]]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/79199761/lc4_insn_cache.v:91: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n : ... In instance lc4_insn_cache\n tagcmem[miss_addr_8d[6:0]] <= #1 miss_8d ? miss_addr_8d[15:7]:tagcmem[miss_addr_8d[6:0]]; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/79199761/lc4_insn_cache.v:95: Operator COND expects 17 bits on the Conditional False, but Conditional False\'s CONST \'16\'h0\' generates 16 bits.\n : ... In instance lc4_insn_cache\nassign data = hit ? cmem[blockid] : 16\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/79199761/lc4_insn_cache.v:95: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s COND generates 17 bits.\n : ... In instance lc4_insn_cache\nassign data = hit ? cmem[blockid] : 16\'h0;\n ^\n%Error: Exiting due to 7 warning(s)\n' | 299,865 | module | module lc4_insn_cache (
input clk,
input gwe,
input rst,
input [15:0] mem_idata,
output [15:0] mem_iaddr,
input [15:0] addr,
output valid,
output [15:0] data
);
wire [6:0] blockid;
wire [7:0] tag;
reg [16:0] cmem [127:0];
reg [7:0] tagcmem [127:0];
reg hit;
reg cmp;
reg [15:0] miss_addr,miss_addr_1d,miss_addr_2d,miss_addr_3d,miss_addr_4d,miss_addr_5d,miss_addr_6d,miss_addr_7d,miss_addr_8d;
reg [16:0] mem0;
wire cvld;
reg miss,miss_1d,miss_2d,miss_3d,miss_4d,miss_5d,miss_6d,miss_7d,miss_8d;
assign blockid = addr[6:0];
assign tag = addr[15:7];
assign vld = cmem[blockid][16];
always @(*) begin
cmp = (tagcmem[blockid] == tag);
hit = cmp & vld ;
miss= ~hit;
end
always @(posedge clk) begin
if(rst) begin
miss_1d <= 0;
miss_2d <= 0;
miss_3d <= 0;
miss_4d <= 0;
miss_5d <= 0;
miss_6d <= 0;
miss_7d <= 0;
miss_8d <= 0;
miss_addr <= 0;
miss_addr_1d <= 0;
miss_addr_2d <= 0;
miss_addr_3d <= 0;
miss_addr_4d <= 0;
miss_addr_5d <= 0;
miss_addr_6d <= 0;
miss_addr_7d <= 0;
miss_addr_8d <= 0;
end else begin
miss_1d <= #1 miss;
miss_2d <= #1 miss_1d;
miss_3d <= #1 miss_2d;
miss_4d <= #1 miss_3d;
miss_5d <= #1 miss_4d;
miss_6d <= #1 miss_5d;
miss_7d <= #1 miss_6d;
miss_8d <= #1 miss_7d;
miss_addr_1d <= #1 miss ? addr : 16'h0;
miss_addr_2d <= #1 miss_addr_1d;
miss_addr_3d <= #1 miss_addr_2d;
miss_addr_4d <= #1 miss_addr_3d;
miss_addr_5d <= #1 miss_addr_4d;
miss_addr_6d <= #1 miss_addr_5d;
miss_addr_7d <= #1 miss_addr_6d;
miss_addr_8d <= #1 miss_addr_7d;
end
end
assign cvld = cmem[miss_addr_7d[6:0]][16];
always @(posedge clk) begin
if(rst) begin
for(integer i=0;i<128;i=i+1) begin
cmem[i] <= #0 16'b0;
tagcmem[i] <= #0 8'h0;
end
end else begin
cmem[miss_addr_8d[6:0]] <= #1 miss_8d ? {1'b1,mem_idata}:cmem[miss_addr_8d[6:0]];
tagcmem[miss_addr_8d[6:0]] <= #1 miss_8d ? miss_addr_8d[15:7]:tagcmem[miss_addr_8d[6:0]];
end
end
assign data = hit ? cmem[blockid] : 16'h0;
assign valid = hit;
assign mem_iaddr = ~hit ? addr : 16'h0;
assign mem0 = cmem[0];
endmodule | module lc4_insn_cache (
input clk,
input gwe,
input rst,
input [15:0] mem_idata,
output [15:0] mem_iaddr,
input [15:0] addr,
output valid,
output [15:0] data
); |
wire [6:0] blockid;
wire [7:0] tag;
reg [16:0] cmem [127:0];
reg [7:0] tagcmem [127:0];
reg hit;
reg cmp;
reg [15:0] miss_addr,miss_addr_1d,miss_addr_2d,miss_addr_3d,miss_addr_4d,miss_addr_5d,miss_addr_6d,miss_addr_7d,miss_addr_8d;
reg [16:0] mem0;
wire cvld;
reg miss,miss_1d,miss_2d,miss_3d,miss_4d,miss_5d,miss_6d,miss_7d,miss_8d;
assign blockid = addr[6:0];
assign tag = addr[15:7];
assign vld = cmem[blockid][16];
always @(*) begin
cmp = (tagcmem[blockid] == tag);
hit = cmp & vld ;
miss= ~hit;
end
always @(posedge clk) begin
if(rst) begin
miss_1d <= 0;
miss_2d <= 0;
miss_3d <= 0;
miss_4d <= 0;
miss_5d <= 0;
miss_6d <= 0;
miss_7d <= 0;
miss_8d <= 0;
miss_addr <= 0;
miss_addr_1d <= 0;
miss_addr_2d <= 0;
miss_addr_3d <= 0;
miss_addr_4d <= 0;
miss_addr_5d <= 0;
miss_addr_6d <= 0;
miss_addr_7d <= 0;
miss_addr_8d <= 0;
end else begin
miss_1d <= #1 miss;
miss_2d <= #1 miss_1d;
miss_3d <= #1 miss_2d;
miss_4d <= #1 miss_3d;
miss_5d <= #1 miss_4d;
miss_6d <= #1 miss_5d;
miss_7d <= #1 miss_6d;
miss_8d <= #1 miss_7d;
miss_addr_1d <= #1 miss ? addr : 16'h0;
miss_addr_2d <= #1 miss_addr_1d;
miss_addr_3d <= #1 miss_addr_2d;
miss_addr_4d <= #1 miss_addr_3d;
miss_addr_5d <= #1 miss_addr_4d;
miss_addr_6d <= #1 miss_addr_5d;
miss_addr_7d <= #1 miss_addr_6d;
miss_addr_8d <= #1 miss_addr_7d;
end
end
assign cvld = cmem[miss_addr_7d[6:0]][16];
always @(posedge clk) begin
if(rst) begin
for(integer i=0;i<128;i=i+1) begin
cmem[i] <= #0 16'b0;
tagcmem[i] <= #0 8'h0;
end
end else begin
cmem[miss_addr_8d[6:0]] <= #1 miss_8d ? {1'b1,mem_idata}:cmem[miss_addr_8d[6:0]];
tagcmem[miss_addr_8d[6:0]] <= #1 miss_8d ? miss_addr_8d[15:7]:tagcmem[miss_addr_8d[6:0]];
end
end
assign data = hit ? cmem[blockid] : 16'h0;
assign valid = hit;
assign mem_iaddr = ~hit ? addr : 16'h0;
assign mem0 = cmem[0];
endmodule | 0 |
137,629 | data/full_repos/permissive/79199761/lc4_insn_set_assc_cache.sv | 79,199,761 | lc4_insn_set_assc_cache.sv | sv | 173 | 129 | [] | [] | [] | null | line:64: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/79199761/lc4_insn_set_assc_cache.sv:51: Signal definition not found, creating implicitly: \'cvalid\'\n : ... Suggested alternative: \'valid\'\nassign cvalid = cdata[16];\n ^~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/79199761/lc4_insn_set_assc_cache.sv:58: Signal definition not found, creating implicitly: \'vld\'\n : ... Suggested alternative: \'valid\'\nassign {vld,data} = hit ? cdata : 17\'h0;\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/79199761/lc4_insn_set_assc_cache.sv:155: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n : ... In instance lc4_insn_cache\n tagcmem[i] <= #0 9\'h0; \n ^~\n%Error: Exiting due to 3 warning(s)\n' | 299,866 | module | module lc4_insn_cache (
input clk,
input gwe,
input rst,
input [15:0] mem_idata,
output [15:0] mem_iaddr,
input [15:0] addr,
output valid,
output [15:0] data
);
reg [16:0] cmem [127:0];
reg [1:0] lru_bit [63:0];
reg [9:0] tagcmem [127:0];
wire mblockid;
wire [9:0] tag,stag0,stag1,mtag,mstag0,mstag1;
wire cmp0,cmp1,blockindex;
wire [6:0] cmemindex,mcmemindex,mbaddr0,mbaddr1,tag_index0,tag_index1;
wire [5:0] setid,msetid;
wire rblock0,rblock1,replaceblock;
wire [16:0] cdata,mcdata;
wire [1:0] mlru_bit;
reg dvalid;
reg hit;
reg cmp;
reg [15:0] miss_addr,miss_addr_1d,miss_addr_2d,miss_addr_3d,miss_addr_4d,miss_addr_5d,miss_addr_6d,miss_addr_7d,miss_addr_8d;
reg [16:0] mem0;
reg miss,miss_1d,miss_2d,miss_3d,miss_4d,miss_5d,miss_6d,miss_7d,miss_8d;
reg mhit,mmiss;
wire mcmp0,mcmp1,mblockindex,mcvalid;
assign {tag,setid} = addr;
assign tag_index0 = {setid,1'b0};
assign tag_index1 = {setid,1'b1};
assign stag0 = tagcmem[tag_index0];
assign stag1 = tagcmem[tag_index1];
assign cmp0 = (tag == stag0);
assign cmp1 = (tag == stag1);
assign blockindex = (~cmp0 & cmp1);
assign cmemindex = {setid,blockindex};
assign cdata = cmem[cmemindex];
assign cvalid = cdata[16];
always @(*) begin
hit = ( (cmp0 & cvalid) | (cmp1 & cvalid) );
miss = ~hit;
end
assign {vld,data} = hit ? cdata : 17'h0;
assign valid = hit;
always @(posedge clk) begin
if(rst) begin
for(integer i=0;i<64;i=i+1) begin
lru_bit [i] <= #0 2'b10;
end
end else begin
lru_bit[setid] <= #1 hit ? (blockindex ? 2'b10: 2'b01) : lru_bit[setid];
if(replaceblock & rblock0 & mmiss) begin
lru_bit[msetid] <= #1 2'b01;
end
if(replaceblock & rblock1 & mmiss) begin
lru_bit[msetid] <= #1 2'b10;
end
end
end
assign mem_iaddr = miss ? addr : 16'h0;
always @(posedge clk) begin
if(rst) begin
miss_1d <= #0 0;
miss_2d <= #0 0;
miss_3d <= #0 0;
miss_4d <= #0 0;
miss_5d <= #0 0;
miss_6d <= #0 0;
miss_7d <= #0 0;
miss_8d <= #0 0;
miss_addr <= #0 0;
miss_addr_1d <= #0 0;
miss_addr_2d <= #0 0;
miss_addr_3d <= #0 0;
miss_addr_4d <= #0 0;
miss_addr_5d <= #0 0;
miss_addr_6d <= #0 0;
miss_addr_7d <= #0 0;
miss_addr_8d <= #0 0;
end else begin
miss_1d <= #1 miss;
miss_2d <= #1 miss_1d;
miss_3d <= #1 miss_2d;
miss_4d <= #1 miss_3d;
miss_5d <= #1 miss_4d;
miss_6d <= #1 miss_5d;
miss_7d <= #1 miss_6d;
miss_8d <= #1 miss_7d;
miss_addr_1d <= #1 miss ? addr : 16'h0;
miss_addr_2d <= #1 miss_addr_1d;
miss_addr_3d <= #1 miss_addr_2d;
miss_addr_4d <= #1 miss_addr_3d;
miss_addr_5d <= #1 miss_addr_4d;
miss_addr_6d <= #1 miss_addr_5d;
miss_addr_7d <= #1 miss_addr_6d;
miss_addr_8d <= #1 miss_addr_7d;
end
end
assign {mtag,msetid} = miss_addr_8d;
assign mbaddr0 = {msetid,1'b0};
assign mbaddr1 = {msetid,1'b1};
assign mlru_bit = lru_bit[msetid];
assign rblock0 = (mlru_bit == 2'b10);
assign rblock1 = (mlru_bit == 2'b01);
assign replaceblock = miss_8d;
assign mstag0 = tagcmem[mbaddr0];
assign mstag1 = tagcmem[mbaddr1];
assign mcmp0 = (mtag == mstag0);
assign mcmp1 = (mtag == mstag1);
assign mblockindex = (~mcmp0 & mcmp1);
assign mcmemindex = {msetid,mblockindex};
assign mcdata = cmem[mcmemindex];
assign mcvalid = mcdata[16];
always @(*) begin
mhit = ( (mcmp0 & mcvalid) | (mcmp1 & mcvalid) );
mmiss = ~mhit;
end
always @(posedge clk) begin
if(rst) begin
for(integer i=0;i<128;i=i+1) begin
cmem[i] <= #0 17'b0;
tagcmem[i] <= #0 9'h0;
end
end else begin
if(replaceblock & rblock0 & mmiss) begin
cmem[mbaddr0] <= #1 {1'b1,mem_idata};
tagcmem[mbaddr0] <= #1 mtag;
end
if(replaceblock & rblock1 & mmiss) begin
cmem[mbaddr1] <= #1 {1'b1,mem_idata};
tagcmem[mbaddr1] <= #1 mtag;
end
end
end
endmodule | module lc4_insn_cache (
input clk,
input gwe,
input rst,
input [15:0] mem_idata,
output [15:0] mem_iaddr,
input [15:0] addr,
output valid,
output [15:0] data
); |
reg [16:0] cmem [127:0];
reg [1:0] lru_bit [63:0];
reg [9:0] tagcmem [127:0];
wire mblockid;
wire [9:0] tag,stag0,stag1,mtag,mstag0,mstag1;
wire cmp0,cmp1,blockindex;
wire [6:0] cmemindex,mcmemindex,mbaddr0,mbaddr1,tag_index0,tag_index1;
wire [5:0] setid,msetid;
wire rblock0,rblock1,replaceblock;
wire [16:0] cdata,mcdata;
wire [1:0] mlru_bit;
reg dvalid;
reg hit;
reg cmp;
reg [15:0] miss_addr,miss_addr_1d,miss_addr_2d,miss_addr_3d,miss_addr_4d,miss_addr_5d,miss_addr_6d,miss_addr_7d,miss_addr_8d;
reg [16:0] mem0;
reg miss,miss_1d,miss_2d,miss_3d,miss_4d,miss_5d,miss_6d,miss_7d,miss_8d;
reg mhit,mmiss;
wire mcmp0,mcmp1,mblockindex,mcvalid;
assign {tag,setid} = addr;
assign tag_index0 = {setid,1'b0};
assign tag_index1 = {setid,1'b1};
assign stag0 = tagcmem[tag_index0];
assign stag1 = tagcmem[tag_index1];
assign cmp0 = (tag == stag0);
assign cmp1 = (tag == stag1);
assign blockindex = (~cmp0 & cmp1);
assign cmemindex = {setid,blockindex};
assign cdata = cmem[cmemindex];
assign cvalid = cdata[16];
always @(*) begin
hit = ( (cmp0 & cvalid) | (cmp1 & cvalid) );
miss = ~hit;
end
assign {vld,data} = hit ? cdata : 17'h0;
assign valid = hit;
always @(posedge clk) begin
if(rst) begin
for(integer i=0;i<64;i=i+1) begin
lru_bit [i] <= #0 2'b10;
end
end else begin
lru_bit[setid] <= #1 hit ? (blockindex ? 2'b10: 2'b01) : lru_bit[setid];
if(replaceblock & rblock0 & mmiss) begin
lru_bit[msetid] <= #1 2'b01;
end
if(replaceblock & rblock1 & mmiss) begin
lru_bit[msetid] <= #1 2'b10;
end
end
end
assign mem_iaddr = miss ? addr : 16'h0;
always @(posedge clk) begin
if(rst) begin
miss_1d <= #0 0;
miss_2d <= #0 0;
miss_3d <= #0 0;
miss_4d <= #0 0;
miss_5d <= #0 0;
miss_6d <= #0 0;
miss_7d <= #0 0;
miss_8d <= #0 0;
miss_addr <= #0 0;
miss_addr_1d <= #0 0;
miss_addr_2d <= #0 0;
miss_addr_3d <= #0 0;
miss_addr_4d <= #0 0;
miss_addr_5d <= #0 0;
miss_addr_6d <= #0 0;
miss_addr_7d <= #0 0;
miss_addr_8d <= #0 0;
end else begin
miss_1d <= #1 miss;
miss_2d <= #1 miss_1d;
miss_3d <= #1 miss_2d;
miss_4d <= #1 miss_3d;
miss_5d <= #1 miss_4d;
miss_6d <= #1 miss_5d;
miss_7d <= #1 miss_6d;
miss_8d <= #1 miss_7d;
miss_addr_1d <= #1 miss ? addr : 16'h0;
miss_addr_2d <= #1 miss_addr_1d;
miss_addr_3d <= #1 miss_addr_2d;
miss_addr_4d <= #1 miss_addr_3d;
miss_addr_5d <= #1 miss_addr_4d;
miss_addr_6d <= #1 miss_addr_5d;
miss_addr_7d <= #1 miss_addr_6d;
miss_addr_8d <= #1 miss_addr_7d;
end
end
assign {mtag,msetid} = miss_addr_8d;
assign mbaddr0 = {msetid,1'b0};
assign mbaddr1 = {msetid,1'b1};
assign mlru_bit = lru_bit[msetid];
assign rblock0 = (mlru_bit == 2'b10);
assign rblock1 = (mlru_bit == 2'b01);
assign replaceblock = miss_8d;
assign mstag0 = tagcmem[mbaddr0];
assign mstag1 = tagcmem[mbaddr1];
assign mcmp0 = (mtag == mstag0);
assign mcmp1 = (mtag == mstag1);
assign mblockindex = (~mcmp0 & mcmp1);
assign mcmemindex = {msetid,mblockindex};
assign mcdata = cmem[mcmemindex];
assign mcvalid = mcdata[16];
always @(*) begin
mhit = ( (mcmp0 & mcvalid) | (mcmp1 & mcvalid) );
mmiss = ~mhit;
end
always @(posedge clk) begin
if(rst) begin
for(integer i=0;i<128;i=i+1) begin
cmem[i] <= #0 17'b0;
tagcmem[i] <= #0 9'h0;
end
end else begin
if(replaceblock & rblock0 & mmiss) begin
cmem[mbaddr0] <= #1 {1'b1,mem_idata};
tagcmem[mbaddr0] <= #1 mtag;
end
if(replaceblock & rblock1 & mmiss) begin
cmem[mbaddr1] <= #1 {1'b1,mem_idata};
tagcmem[mbaddr1] <= #1 mtag;
end
end
end
endmodule | 0 |
137,630 | data/full_repos/permissive/79199761/Nbit_reg.v | 79,199,761 | Nbit_reg.v | v | 30 | 105 | [] | [] | [] | [(1, 29)] | null | data/verilator_xmls/2cecded4-9d8e-40cc-826d-1e192a78da44.xml | null | 299,868 | module | module Nbit_reg(
in,
out,
clk,
we,
gwe,
rst
);
parameter n=1;
input [n-1:0] in;
output reg [n-1:0] out;
input clk;
input we;
input gwe;
input rst;
always @(posedge clk) begin
if(rst) begin
out <= #1 0;
end else begin
out <= #1 we ? in : out;
end
end
endmodule | module Nbit_reg(
in,
out,
clk,
we,
gwe,
rst
); |
parameter n=1;
input [n-1:0] in;
output reg [n-1:0] out;
input clk;
input we;
input gwe;
input rst;
always @(posedge clk) begin
if(rst) begin
out <= #1 0;
end else begin
out <= #1 we ? in : out;
end
end
endmodule | 0 |
137,631 | data/full_repos/permissive/79199761/test_lc4_insn_cache.v | 79,199,761 | test_lc4_insn_cache.v | v | 143 | 131 | [] | [] | [] | [(15, 136)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:62: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:83: Unsupported: Ignoring delay on this delayed statement.\n #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:87: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Error: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:96: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:113: Unsupported: Ignoring delay on this delayed statement.\n #10; $finish;\n ^\n%Error: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:119: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:132: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("cache_design.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79199761/test_lc4_insn_cache.v:133: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(10,testbench_v);\n ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,869 | module | module testbench_v;
integer input_file, output_file, errors, linenum;
reg clk;
reg rst;
wire [15:0] mem_idata;
wire [15:0] mem_iaddr;
wire [15:0] req_addr;
wire [15:0] delayer_data;
reg [15:0] addr;
wire valid;
wire [15:0] data;
lc4_insn_cache uut (
.clk(clk),
.gwe(gwe),
.rst(rst),
.mem_idata(mem_idata),
.mem_iaddr(req_addr),
.addr(addr),
.valid(valid),
.data(data)
);
assign delayer_data = req_addr ^ (16'b1010_1010_1010_1010);
delay_eight_cycles #(16) delayer (.clk(clk),
.gwe(gwe),
.rst(rst),
.in_value(delayer_data),
.out_value(mem_idata));
reg expected_valid;
reg [15:0] expected_data;
always #5 clk <= ~clk;
initial begin
clk = 0;
rst = 1;
addr = 0;
errors = 0;
linenum = 0;
input_file = $fopen(`INPUT, "r");
if (input_file == `NULL) begin
$display("Error opening file: ", `INPUT);
$finish;
end
#80;
rst = 0;
#2;
$display("Starting test...");
while (2 == $fscanf(input_file, "%h %d", addr, expected_valid)) begin
@(posedge clk);
linenum = linenum + 1;
$display("%t linemun:%d addr:%d expected_valid:%d",$time,linenum,addr,expected_valid);
if (valid !== expected_valid) begin
$display("%t Error at line %d: Value of valid should have been %d, but was %d instead",$time, linenum, expected_valid, valid);
errors = errors + 1;
#10; $finish;
end
if (valid === 1) begin
expected_data = addr ^ (16'b1010_1010_1010_1010);
if (data !== expected_data) begin
$display("%t Error at line %d: Value of data should have been %h, but was %h instead",$time, linenum, expected_data, data);
errors = errors + 1;
#10; $finish;
end
end
@(negedge clk);
end
if (input_file) $fclose(input_file);
if (output_file) $fclose(output_file);
$display("Simulation finished: %d test cases %d errors", linenum, errors);
$finish;
end
initial begin
$dumpfile("cache_design.vcd");
$dumpvars(10,testbench_v);
end
endmodule | module testbench_v; |
integer input_file, output_file, errors, linenum;
reg clk;
reg rst;
wire [15:0] mem_idata;
wire [15:0] mem_iaddr;
wire [15:0] req_addr;
wire [15:0] delayer_data;
reg [15:0] addr;
wire valid;
wire [15:0] data;
lc4_insn_cache uut (
.clk(clk),
.gwe(gwe),
.rst(rst),
.mem_idata(mem_idata),
.mem_iaddr(req_addr),
.addr(addr),
.valid(valid),
.data(data)
);
assign delayer_data = req_addr ^ (16'b1010_1010_1010_1010);
delay_eight_cycles #(16) delayer (.clk(clk),
.gwe(gwe),
.rst(rst),
.in_value(delayer_data),
.out_value(mem_idata));
reg expected_valid;
reg [15:0] expected_data;
always #5 clk <= ~clk;
initial begin
clk = 0;
rst = 1;
addr = 0;
errors = 0;
linenum = 0;
input_file = $fopen(`INPUT, "r");
if (input_file == `NULL) begin
$display("Error opening file: ", `INPUT);
$finish;
end
#80;
rst = 0;
#2;
$display("Starting test...");
while (2 == $fscanf(input_file, "%h %d", addr, expected_valid)) begin
@(posedge clk);
linenum = linenum + 1;
$display("%t linemun:%d addr:%d expected_valid:%d",$time,linenum,addr,expected_valid);
if (valid !== expected_valid) begin
$display("%t Error at line %d: Value of valid should have been %d, but was %d instead",$time, linenum, expected_valid, valid);
errors = errors + 1;
#10; $finish;
end
if (valid === 1) begin
expected_data = addr ^ (16'b1010_1010_1010_1010);
if (data !== expected_data) begin
$display("%t Error at line %d: Value of data should have been %h, but was %h instead",$time, linenum, expected_data, data);
errors = errors + 1;
#10; $finish;
end
end
@(negedge clk);
end
if (input_file) $fclose(input_file);
if (output_file) $fclose(output_file);
$display("Simulation finished: %d test cases %d errors", linenum, errors);
$finish;
end
initial begin
$dumpfile("cache_design.vcd");
$dumpvars(10,testbench_v);
end
endmodule | 0 |
137,632 | data/full_repos/permissive/79295554/apps/blink/blink_app.v | 79,295,554 | blink_app.v | v | 24 | 74 | [] | [] | [] | [(8, 23)] | null | null | 1: b'%Error: data/full_repos/permissive/79295554/apps/blink/blink_app.v:11: Cannot find file containing module: \'OSCH\'\nOSCH #(.NOM_FREQ("133.00")) osch(.STDBY(1\'b0), .OSC(clock), .SEDSTDBY());\n^~~~\n ... Looked in:\n data/full_repos/permissive/79295554/apps/blink,data/full_repos/permissive/79295554/OSCH\n data/full_repos/permissive/79295554/apps/blink,data/full_repos/permissive/79295554/OSCH.v\n data/full_repos/permissive/79295554/apps/blink,data/full_repos/permissive/79295554/OSCH.sv\n OSCH\n OSCH.v\n OSCH.sv\n obj_dir/OSCH\n obj_dir/OSCH.v\n obj_dir/OSCH.sv\n%Error: Exiting due to 1 error(s)\n' | 299,874 | module | module top(output reg [7:0] leds);
wire clock;
OSCH #(.NOM_FREQ("133.00")) osch(.STDBY(1'b0), .OSC(clock), .SEDSTDBY());
reg [31:0] counter;
initial counter <= 32'b0;
always @(posedge clock)
begin
counter <= counter + 1'b1;
leds <= ~counter[31:24];
end
endmodule | module top(output reg [7:0] leds); |
wire clock;
OSCH #(.NOM_FREQ("133.00")) osch(.STDBY(1'b0), .OSC(clock), .SEDSTDBY());
reg [31:0] counter;
initial counter <= 32'b0;
always @(posedge clock)
begin
counter <= counter + 1'b1;
leds <= ~counter[31:24];
end
endmodule | 3 |
137,633 | data/full_repos/permissive/79295554/apps/blink/blink_sim.v | 79,295,554 | blink_sim.v | v | 21 | 77 | [] | [] | [] | null | line:17: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79295554/apps/blink/blink_sim.v:16: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/79295554/apps/blink/blink_sim.v:12: Cannot find file containing module: \'top\'\ntop top(.leds(leds));\n^~~\n ... Looked in:\n data/full_repos/permissive/79295554/apps/blink,data/full_repos/permissive/79295554/top\n data/full_repos/permissive/79295554/apps/blink,data/full_repos/permissive/79295554/top.v\n data/full_repos/permissive/79295554/apps/blink,data/full_repos/permissive/79295554/top.sv\n top\n top.v\n top.sv\n obj_dir/top\n obj_dir/top.v\n obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,875 | module | module sim();
wire [7:0] leds;
top top(.leds(leds));
initial
begin
#100
$finish;
end
endmodule | module sim(); |
wire [7:0] leds;
top top(.leds(leds));
initial
begin
#100
$finish;
end
endmodule | 3 |
137,634 | data/full_repos/permissive/79295554/apps/memory/memory_app.v | 79,295,554 | memory_app.v | v | 155 | 80 | [] | [] | [] | [(8, 154)] | null | null | 1: b'%Error: data/full_repos/permissive/79295554/apps/memory/memory_app.v:13: Cannot find file containing module: \'OSCH\'\nOSCH #(.NOM_FREQ("133.00")) osch_inst(\n^~~~\n ... Looked in:\n data/full_repos/permissive/79295554/apps/memory,data/full_repos/permissive/79295554/OSCH\n data/full_repos/permissive/79295554/apps/memory,data/full_repos/permissive/79295554/OSCH.v\n data/full_repos/permissive/79295554/apps/memory,data/full_repos/permissive/79295554/OSCH.sv\n OSCH\n OSCH.v\n OSCH.sv\n obj_dir/OSCH\n obj_dir/OSCH.v\n obj_dir/OSCH.sv\n%Error: data/full_repos/permissive/79295554/apps/memory/memory_app.v:19: Cannot find file containing module: \'button\'\nbutton resetn_inst(\n^~~~~~\n%Error: data/full_repos/permissive/79295554/apps/memory/memory_app.v:75: Cannot find file containing module: \'true_dual_port_ram_writefirst_reg1\'\ntrue_dual_port_ram_writefirst_reg1 #(.DATA_WIDTH(8), .ADDR_WIDTH(10)) ram_inst(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 299,876 | module | module top(
output reg [7:0] leds,
input wire resetn_pin);
wire clock;
OSCH #(.NOM_FREQ("133.00")) osch_inst(
.STDBY(1'b0),
.OSC(clock),
.SEDSTDBY());
wire resetn;
button resetn_inst(
.clock(clock),
.signal(resetn),
.signal_pin(resetn_pin));
`define TRUE_DUAL_PORT
`ifdef TRUE_DUAL_PORT
reg [9:0] addr1;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
addr1 <= 10'h000;
else
addr1 <= addr1 + 10'h001;
end
reg [9:0] addr2;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
addr2 <= 10'h000;
else
addr2 <= addr2 + 10'h003;
end
reg [7:0] idata1;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
idata1 <= 8'h00;
else
idata1 <= idata1 + 8'h05;
end
reg [7:0] idata2;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
idata2 <= 8'h00;
else
idata2 <= idata1 + 8'h07;
end
reg [3:0] control;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
control <= 4'b0;
else
control <= control + 4'b1;
end
wire [7:0] odata1;
wire [7:0] odata2;
true_dual_port_ram_writefirst_reg1 #(.DATA_WIDTH(8), .ADDR_WIDTH(10)) ram_inst(
.clock1(clock),
.enable1(control[0]),
.write1(control[1]),
.addr1(addr1),
.idata1(idata1),
.odata1(odata1),
.clock2(clock),
.enable2(control[2]),
.write2(control[3]),
.addr2(addr2),
.idata2(idata2),
.odata2(odata2));
reg [7:0] rdata;
always @(posedge clock)
begin
rdata <= odata1 + odata2;
end
`endif
`ifdef SIMPLE_DUAL_PORT
reg [3:0] waddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 4'h0;
else
waddr <= waddr + 4'h1;
end
reg [7:0] wdata;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
wdata <= 8'h00;
else
wdata <= wdata + 8'h03;
end
reg [3:0] raddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 4'h0;
else
raddr <= raddr + 4'h5;
end
reg [1:0] control;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
control <= 2'b0;
else
control <= control + 2'b1;
end
wire [7:0] rdata;
simple_dual_port_ram_reg1 #(.DATA_WIDTH(8), .ADDR_WIDTH(4)) ram_inst(
.wclock(clock),
.wenable(control[0]),
.waddr(waddr),
.wdata(wdata),
.rclock(clock),
.renable(control[1]),
.raddr(raddr),
.rdata(rdata));
`endif
always @(posedge clock or negedge resetn)
begin
if (!resetn)
leds <= 8'b10101010;
else
begin
leds <= ~rdata;
end
end
endmodule | module top(
output reg [7:0] leds,
input wire resetn_pin); |
wire clock;
OSCH #(.NOM_FREQ("133.00")) osch_inst(
.STDBY(1'b0),
.OSC(clock),
.SEDSTDBY());
wire resetn;
button resetn_inst(
.clock(clock),
.signal(resetn),
.signal_pin(resetn_pin));
`define TRUE_DUAL_PORT
`ifdef TRUE_DUAL_PORT
reg [9:0] addr1;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
addr1 <= 10'h000;
else
addr1 <= addr1 + 10'h001;
end
reg [9:0] addr2;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
addr2 <= 10'h000;
else
addr2 <= addr2 + 10'h003;
end
reg [7:0] idata1;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
idata1 <= 8'h00;
else
idata1 <= idata1 + 8'h05;
end
reg [7:0] idata2;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
idata2 <= 8'h00;
else
idata2 <= idata1 + 8'h07;
end
reg [3:0] control;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
control <= 4'b0;
else
control <= control + 4'b1;
end
wire [7:0] odata1;
wire [7:0] odata2;
true_dual_port_ram_writefirst_reg1 #(.DATA_WIDTH(8), .ADDR_WIDTH(10)) ram_inst(
.clock1(clock),
.enable1(control[0]),
.write1(control[1]),
.addr1(addr1),
.idata1(idata1),
.odata1(odata1),
.clock2(clock),
.enable2(control[2]),
.write2(control[3]),
.addr2(addr2),
.idata2(idata2),
.odata2(odata2));
reg [7:0] rdata;
always @(posedge clock)
begin
rdata <= odata1 + odata2;
end
`endif
`ifdef SIMPLE_DUAL_PORT
reg [3:0] waddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 4'h0;
else
waddr <= waddr + 4'h1;
end
reg [7:0] wdata;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
wdata <= 8'h00;
else
wdata <= wdata + 8'h03;
end
reg [3:0] raddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 4'h0;
else
raddr <= raddr + 4'h5;
end
reg [1:0] control;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
control <= 2'b0;
else
control <= control + 2'b1;
end
wire [7:0] rdata;
simple_dual_port_ram_reg1 #(.DATA_WIDTH(8), .ADDR_WIDTH(4)) ram_inst(
.wclock(clock),
.wenable(control[0]),
.waddr(waddr),
.wdata(wdata),
.rclock(clock),
.renable(control[1]),
.raddr(raddr),
.rdata(rdata));
`endif
always @(posedge clock or negedge resetn)
begin
if (!resetn)
leds <= 8'b10101010;
else
begin
leds <= ~rdata;
end
end
endmodule | 3 |
137,636 | data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v | 79,295,554 | pipeline_sim.v | v | 60 | 66 | [] | [] | [] | null | line:54: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v:51: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v:53: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v:57: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock = ~clock;\n ^\n%Error: data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v:18: Cannot find file containing module: \'axis_counter\'\naxis_counter counter(\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/apps/pipeline,data/full_repos/permissive/79295554/axis_counter\n data/full_repos/permissive/79295554/apps/pipeline,data/full_repos/permissive/79295554/axis_counter.v\n data/full_repos/permissive/79295554/apps/pipeline,data/full_repos/permissive/79295554/axis_counter.sv\n axis_counter\n axis_counter.v\n axis_counter.sv\n obj_dir/axis_counter\n obj_dir/axis_counter.v\n obj_dir/axis_counter.sv\n%Error: data/full_repos/permissive/79295554/apps/pipeline/pipeline_sim.v:30: Cannot find file containing module: \'axis_fifo\'\naxis_fifo #(.SIZE(7)) fifo(\n^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,878 | module | module test();
reg clock, resetn;
wire [7:0] data1;
wire valid1, ready1;
reg enabled;
axis_counter counter(
.clock(clock),
.resetn(resetn),
.odata(data1),
.ovalid(valid1),
.oready(ready1 && enabled));
wire [7:0] data2;
wire valid2;
reg ready2;
wire [2:0] size;
axis_fifo #(.SIZE(7)) fifo(
.clock(clock),
.resetn(resetn),
.size(size),
.idata(data1),
.ivalid(valid1 && enabled),
.iready(ready1),
.odata(data2),
.ovalid(valid2),
.oready(ready2));
initial
begin
resetn = 1'b0;
clock = 1'b1;
ready2 = 1'b0;
enabled = 1'b1;
#5
resetn = 1'b1;
#20
ready2 = 1'b1;
#20
enabled = 1'b0;
#20
$finish;
end
always #1 clock = ~clock;
endmodule | module test(); |
reg clock, resetn;
wire [7:0] data1;
wire valid1, ready1;
reg enabled;
axis_counter counter(
.clock(clock),
.resetn(resetn),
.odata(data1),
.ovalid(valid1),
.oready(ready1 && enabled));
wire [7:0] data2;
wire valid2;
reg ready2;
wire [2:0] size;
axis_fifo #(.SIZE(7)) fifo(
.clock(clock),
.resetn(resetn),
.size(size),
.idata(data1),
.ivalid(valid1 && enabled),
.iready(ready1),
.odata(data2),
.ovalid(valid2),
.oready(ready2));
initial
begin
resetn = 1'b0;
clock = 1'b1;
ready2 = 1'b0;
enabled = 1'b1;
#5
resetn = 1'b1;
#20
ready2 = 1'b1;
#20
enabled = 1'b0;
#20
$finish;
end
always #1 clock = ~clock;
endmodule | 3 |
137,638 | data/full_repos/permissive/79295554/apps/rs232rx/rs232rx_app.v | 79,295,554 | rs232rx_app.v | v | 66 | 84 | [] | [] | [] | [(8, 65)] | null | null | 1: b'%Error: data/full_repos/permissive/79295554/apps/rs232rx/rs232rx_app.v:17: Cannot find file containing module: \'OSCH\'\nOSCH #(.NOM_FREQ("133.00")) osch_inst(\n^~~~\n ... Looked in:\n data/full_repos/permissive/79295554/apps/rs232rx,data/full_repos/permissive/79295554/OSCH\n data/full_repos/permissive/79295554/apps/rs232rx,data/full_repos/permissive/79295554/OSCH.v\n data/full_repos/permissive/79295554/apps/rs232rx,data/full_repos/permissive/79295554/OSCH.sv\n OSCH\n OSCH.v\n OSCH.sv\n obj_dir/OSCH\n obj_dir/OSCH.v\n obj_dir/OSCH.sv\n%Error: data/full_repos/permissive/79295554/apps/rs232rx/rs232rx_app.v:23: Cannot find file containing module: \'button\'\nbutton button_inst(\n^~~~~~\n%Error: data/full_repos/permissive/79295554/apps/rs232rx/rs232rx_app.v:33: Cannot find file containing module: \'rs232_to_axis2\'\nrs232_to_axis2 #(.CLOCK_FREQ(133000000), .BAUD_RATE(BAUD_RATE)) rs232_to_axis_inst(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/apps/rs232rx/rs232rx_app.v:43: Cannot find file containing module: \'axis_to_rs232\'\naxis_to_rs232 #(.CLOCK_FREQ(133000000), .BAUD_RATE(BAUD_RATE)) axis_to_rs232_inst(\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 299,880 | module | module top(
output reg [7:0] leds,
input wire resetn_pin,
input wire rxd_pin,
output wire rtsn_pin,
output wire txd_pin,
input wire ctsn_pin);
wire clock;
OSCH #(.NOM_FREQ("133.00")) osch_inst(
.STDBY(1'b0),
.OSC(clock),
.SEDSTDBY());
wire resetn;
button button_inst(
.clock(clock),
.signal(resetn),
.signal_pin(resetn_pin));
localparam BAUD_RATE = 12000000;
wire [7:0] data;
wire overflow, valid, ready;
rs232_to_axis2 #(.CLOCK_FREQ(133000000), .BAUD_RATE(BAUD_RATE)) rs232_to_axis_inst(
.clock(clock),
.resetn(resetn),
.overflow(overflow),
.rxd_pin(rxd_pin),
.rtsn_pin(rtsn_pin),
.odata(data),
.ovalid(valid),
.oready(ready));
axis_to_rs232 #(.CLOCK_FREQ(133000000), .BAUD_RATE(BAUD_RATE)) axis_to_rs232_inst(
.clock(clock),
.resetn(resetn),
.idata(~data),
.ivalid(valid),
.iready(ready),
.txd_pin(txd_pin),
.ctsn_pin(ctsn_pin));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
leds <= 8'b10101010;
else
begin
leds[7] <= ~overflow;
leds[6] <= ~valid;
leds[5] <= ~ready;
if (valid && ready)
leds[4:0] <= ~data[4:0];
end
end
endmodule | module top(
output reg [7:0] leds,
input wire resetn_pin,
input wire rxd_pin,
output wire rtsn_pin,
output wire txd_pin,
input wire ctsn_pin); |
wire clock;
OSCH #(.NOM_FREQ("133.00")) osch_inst(
.STDBY(1'b0),
.OSC(clock),
.SEDSTDBY());
wire resetn;
button button_inst(
.clock(clock),
.signal(resetn),
.signal_pin(resetn_pin));
localparam BAUD_RATE = 12000000;
wire [7:0] data;
wire overflow, valid, ready;
rs232_to_axis2 #(.CLOCK_FREQ(133000000), .BAUD_RATE(BAUD_RATE)) rs232_to_axis_inst(
.clock(clock),
.resetn(resetn),
.overflow(overflow),
.rxd_pin(rxd_pin),
.rtsn_pin(rtsn_pin),
.odata(data),
.ovalid(valid),
.oready(ready));
axis_to_rs232 #(.CLOCK_FREQ(133000000), .BAUD_RATE(BAUD_RATE)) axis_to_rs232_inst(
.clock(clock),
.resetn(resetn),
.idata(~data),
.ivalid(valid),
.iready(ready),
.txd_pin(txd_pin),
.ctsn_pin(ctsn_pin));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
leds <= 8'b10101010;
else
begin
leds[7] <= ~overflow;
leds[6] <= ~valid;
leds[5] <= ~ready;
if (valid && ready)
leds[4:0] <= ~data[4:0];
end
end
endmodule | 3 |
137,641 | data/full_repos/permissive/79295554/sby/axis_fifo_tb.v | 79,295,554 | axis_fifo_tb.v | v | 130 | 66 | [] | [] | [] | null | line:107: before: "(" | null | 1: b"%Error: data/full_repos/permissive/79295554/sby/axis_fifo_tb.v:125: syntax error, unexpected '(', expecting property\n restrict (ivalid || $past(ivalid));\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 299,883 | module | module axis_fifo_tb (
input wire clock,
input wire resetn,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready);
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) bus1 (
.clock(clock),
.resetn(resetn),
.data(idata),
.valid(ivalid),
.ready(iready),
.count(count1),
.sdata(sdata1),
.saved());
`ifdef VER1
wire [1:0] size2;
axis_fifo_ver1 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size2),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER2
wire [1:0] size2;
axis_fifo_ver2 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size2),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER3
wire [1:0] size1;
wire [2:0] size2 = size1 + ovalid;
axis_fifo_ver3 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size1),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER4
wire [1:0] size1;
wire [2:0] size2 = size1 + ovalid;
axis_fifo_ver4 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size1),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
wire [2:0] count2;
wire [7:0] sdata2;
wire saved2;
axis_bus #(.COUNT_WIDTH(3)) bus2 (
.clock(clock),
.resetn(resetn),
.data(odata),
.valid(ovalid),
.ready(oready),
.count(count2),
.sdata(sdata2),
.saved(saved2));
initial assume (!resetn);
always @(posedge clock)
begin
if (resetn)
begin
assert (count1 == size2 + count2);
if (saved2)
assert(sdata1 == sdata2);
end
if (resetn && $past(resetn))
begin
assert (size2 == $past(size2
+ (ivalid && iready) - (ovalid && oready)));
restrict (ivalid || $past(ivalid));
restrict (oready || $past(oready));
end
end
endmodule | module axis_fifo_tb (
input wire clock,
input wire resetn,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready); |
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) bus1 (
.clock(clock),
.resetn(resetn),
.data(idata),
.valid(ivalid),
.ready(iready),
.count(count1),
.sdata(sdata1),
.saved());
`ifdef VER1
wire [1:0] size2;
axis_fifo_ver1 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size2),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER2
wire [1:0] size2;
axis_fifo_ver2 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size2),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER3
wire [1:0] size1;
wire [2:0] size2 = size1 + ovalid;
axis_fifo_ver3 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size1),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
`ifdef VER4
wire [1:0] size1;
wire [2:0] size2 = size1 + ovalid;
axis_fifo_ver4 #(.ADDR_WIDTH(2)) fifo (
.clock(clock),
.resetn(resetn),
.size(size1),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
`endif
wire [2:0] count2;
wire [7:0] sdata2;
wire saved2;
axis_bus #(.COUNT_WIDTH(3)) bus2 (
.clock(clock),
.resetn(resetn),
.data(odata),
.valid(ovalid),
.ready(oready),
.count(count2),
.sdata(sdata2),
.saved(saved2));
initial assume (!resetn);
always @(posedge clock)
begin
if (resetn)
begin
assert (count1 == size2 + count2);
if (saved2)
assert(sdata1 == sdata2);
end
if (resetn && $past(resetn))
begin
assert (size2 == $past(size2
+ (ivalid && iready) - (ovalid && oready)));
restrict (ivalid || $past(ivalid));
restrict (oready || $past(oready));
end
end
endmodule | 3 |
137,642 | data/full_repos/permissive/79295554/sby/axis_register_tb.v | 79,295,554 | axis_register_tb.v | v | 80 | 66 | [] | [] | [] | null | line:57: before: "(" | null | 1: b"%Error: data/full_repos/permissive/79295554/sby/axis_register_tb.v:75: syntax error, unexpected '(', expecting property\n restrict (ivalid || $past(ivalid));\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 299,884 | module | module axis_register_tb (
input wire clock,
input wire resetn,
output wire [1:0] size,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready);
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) axis_bus_inst1 (
.clock(clock),
.resetn(resetn),
.data(idata),
.valid(ivalid),
.ready(iready),
.count(count1),
.sdata(sdata1),
.saved());
axis_register axis_register_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
wire [2:0] count2;
wire [7:0] sdata2;
wire saved2;
axis_bus #(.COUNT_WIDTH(3)) axis_bus_inst2 (
.clock(clock),
.resetn(resetn),
.data(odata),
.valid(ovalid),
.ready(oready),
.count(count2),
.sdata(sdata2),
.saved(saved2));
initial assume (!resetn);
always @(posedge clock)
begin
if (resetn)
begin
assert (count1 == size + count2);
if (saved2)
assert(sdata1 == sdata2);
end
if (resetn && $past(resetn))
begin
assert (size == $past(size
+ (ivalid && iready) - (ovalid && oready)));
restrict (ivalid || $past(ivalid));
restrict (oready || $past(oready));
end
end
endmodule | module axis_register_tb (
input wire clock,
input wire resetn,
output wire [1:0] size,
input wire [7:0] idata,
input wire ivalid,
output wire iready,
output wire [7:0] odata,
output wire ovalid,
input wire oready); |
wire [2:0] count1;
wire [7:0] sdata1;
axis_bus #(.COUNT_WIDTH(3)) axis_bus_inst1 (
.clock(clock),
.resetn(resetn),
.data(idata),
.valid(ivalid),
.ready(iready),
.count(count1),
.sdata(sdata1),
.saved());
axis_register axis_register_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ivalid),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
wire [2:0] count2;
wire [7:0] sdata2;
wire saved2;
axis_bus #(.COUNT_WIDTH(3)) axis_bus_inst2 (
.clock(clock),
.resetn(resetn),
.data(odata),
.valid(ovalid),
.ready(oready),
.count(count2),
.sdata(sdata2),
.saved(saved2));
initial assume (!resetn);
always @(posedge clock)
begin
if (resetn)
begin
assert (count1 == size + count2);
if (saved2)
assert(sdata1 == sdata2);
end
if (resetn && $past(resetn))
begin
assert (size == $past(size
+ (ivalid && iready) - (ovalid && oready)));
restrict (ivalid || $past(ivalid));
restrict (oready || $past(oready));
end
end
endmodule | 3 |
137,647 | data/full_repos/permissive/79295554/src/axis_fifo.v | 79,295,554 | axis_fifo.v | v | 246 | 84 | [] | [] | [] | [(12, 57), (63, 107), (113, 176), (182, 245)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/axis_fifo.v:63: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'axis_fifo_ver1\'\nmodule axis_fifo_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver2\'\nmodule axis_fifo_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver3\'\nmodule axis_fifo_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver4\'\nmodule axis_fifo_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:198: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:211: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n size <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:221: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:133: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:146: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:154: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n raddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:80: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver2\n size <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:90: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:30: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:41: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n raddr <= 1\'b0;\n ^~\n%Error: Exiting due to 4 error(s), 8 warning(s)\n' | 299,886 | module | module axis_fifo_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output wire [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready);
reg [ADDR_WIDTH-1:0] raddr;
reg [ADDR_WIDTH-1:0] waddr;
assign size = waddr - raddr;
assign iready = !(&size);
assign ovalid = (|size);
simple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(ivalid && iready),
.waddr(waddr),
.wdata(idata),
.raddr(raddr),
.rdata(odata));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 1'b0;
else if (ivalid && iready)
waddr <= waddr + 1'b1;
end
always @(posedge clock)
begin
if (!resetn)
raddr <= 1'b0;
else if (ovalid && oready)
raddr <= raddr + 1'b1;
end
`ifdef FORMAL
initial assert (!resetn);
`endif
endmodule | module axis_fifo_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output wire [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready); |
reg [ADDR_WIDTH-1:0] raddr;
reg [ADDR_WIDTH-1:0] waddr;
assign size = waddr - raddr;
assign iready = !(&size);
assign ovalid = (|size);
simple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(ivalid && iready),
.waddr(waddr),
.wdata(idata),
.raddr(raddr),
.rdata(odata));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 1'b0;
else if (ivalid && iready)
waddr <= waddr + 1'b1;
end
always @(posedge clock)
begin
if (!resetn)
raddr <= 1'b0;
else if (ovalid && oready)
raddr <= raddr + 1'b1;
end
`ifdef FORMAL
initial assert (!resetn);
`endif
endmodule | 3 |
137,648 | data/full_repos/permissive/79295554/src/axis_fifo.v | 79,295,554 | axis_fifo.v | v | 246 | 84 | [] | [] | [] | [(12, 57), (63, 107), (113, 176), (182, 245)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/axis_fifo.v:63: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'axis_fifo_ver1\'\nmodule axis_fifo_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver2\'\nmodule axis_fifo_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver3\'\nmodule axis_fifo_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver4\'\nmodule axis_fifo_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:198: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:211: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n size <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:221: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:133: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:146: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:154: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n raddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:80: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver2\n size <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:90: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:30: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:41: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n raddr <= 1\'b0;\n ^~\n%Error: Exiting due to 4 error(s), 8 warning(s)\n' | 299,886 | module | module axis_fifo_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output reg [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready);
assign iready = !(&size);
assign ovalid = (|size);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
size <= 1'b0;
else if ((ivalid && iready) && !(ovalid && oready))
size <= size + 1'b1;
else if (!(ivalid && iready) && (ovalid && oready))
size <= size - 1'b1;
end
reg [ADDR_WIDTH-1:0] raddr;
wire [ADDR_WIDTH-1:0] waddr = raddr + size;
simple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(ivalid && iready),
.waddr(waddr),
.wdata(idata),
.raddr(raddr),
.rdata(odata));
always @(posedge clock)
begin
if (ovalid && oready)
raddr <= raddr + 1'b1;
end
`ifdef FORMAL
initial assert (!resetn);
`endif
endmodule | module axis_fifo_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output reg [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready); |
assign iready = !(&size);
assign ovalid = (|size);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
size <= 1'b0;
else if ((ivalid && iready) && !(ovalid && oready))
size <= size + 1'b1;
else if (!(ivalid && iready) && (ovalid && oready))
size <= size - 1'b1;
end
reg [ADDR_WIDTH-1:0] raddr;
wire [ADDR_WIDTH-1:0] waddr = raddr + size;
simple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(ivalid && iready),
.waddr(waddr),
.wdata(idata),
.raddr(raddr),
.rdata(odata));
always @(posedge clock)
begin
if (ovalid && oready)
raddr <= raddr + 1'b1;
end
`ifdef FORMAL
initial assert (!resetn);
`endif
endmodule | 3 |
137,649 | data/full_repos/permissive/79295554/src/axis_fifo.v | 79,295,554 | axis_fifo.v | v | 246 | 84 | [] | [] | [] | [(12, 57), (63, 107), (113, 176), (182, 245)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/axis_fifo.v:63: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'axis_fifo_ver1\'\nmodule axis_fifo_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver2\'\nmodule axis_fifo_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver3\'\nmodule axis_fifo_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver4\'\nmodule axis_fifo_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:198: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:211: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n size <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:221: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:133: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:146: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:154: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n raddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:80: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver2\n size <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:90: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:30: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:41: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n raddr <= 1\'b0;\n ^~\n%Error: Exiting due to 4 error(s), 8 warning(s)\n' | 299,886 | module | module axis_fifo_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output wire [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output reg ovalid,
input wire oready);
reg [ADDR_WIDTH-1:0] raddr;
reg [ADDR_WIDTH-1:0] waddr;
assign size = waddr - raddr;
assign iready = !(&size);
wire wenable = ivalid && iready;
wire renable = (|size) && (!ovalid || oready);
simple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(wenable),
.waddr(waddr),
.wdata(idata),
.rclock(clock),
.renable(renable),
.raddr(raddr),
.rdata(odata));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 1'b0;
else if (wenable)
waddr <= waddr + 1'b1;
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 1'b0;
else if (renable)
raddr <= raddr + 1'b1;
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
ovalid <= 1'b0;
else
ovalid <= (|size) || (ovalid && !oready);
end
`ifdef FORMAL
initial assert (!resetn);
always @(posedge clock)
begin
if (resetn)
assert (size <= 1 || ovalid);
end
`endif
endmodule | module axis_fifo_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output wire [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output reg ovalid,
input wire oready); |
reg [ADDR_WIDTH-1:0] raddr;
reg [ADDR_WIDTH-1:0] waddr;
assign size = waddr - raddr;
assign iready = !(&size);
wire wenable = ivalid && iready;
wire renable = (|size) && (!ovalid || oready);
simple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(wenable),
.waddr(waddr),
.wdata(idata),
.rclock(clock),
.renable(renable),
.raddr(raddr),
.rdata(odata));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 1'b0;
else if (wenable)
waddr <= waddr + 1'b1;
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 1'b0;
else if (renable)
raddr <= raddr + 1'b1;
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
ovalid <= 1'b0;
else
ovalid <= (|size) || (ovalid && !oready);
end
`ifdef FORMAL
initial assert (!resetn);
always @(posedge clock)
begin
if (resetn)
assert (size <= 1 || ovalid);
end
`endif
endmodule | 3 |
137,650 | data/full_repos/permissive/79295554/src/axis_fifo.v | 79,295,554 | axis_fifo.v | v | 246 | 84 | [] | [] | [] | [(12, 57), (63, 107), (113, 176), (182, 245)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/axis_fifo.v:63: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'axis_fifo_ver1\'\nmodule axis_fifo_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver2\'\nmodule axis_fifo_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver3\'\nmodule axis_fifo_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n : ... Top module \'axis_fifo_ver4\'\nmodule axis_fifo_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:198: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:211: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n size <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:221: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver4\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:133: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:146: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:154: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver3\n raddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:80: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver2\n size <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:90: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/axis_fifo.v:30: Cannot find file containing module: \'simple_dual_port_ram_reg0\'\nsimple_dual_port_ram_reg0 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:41: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/axis_fifo.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance axis_fifo_ver1\n raddr <= 1\'b0;\n ^~\n%Error: Exiting due to 4 error(s), 8 warning(s)\n' | 299,886 | module | module axis_fifo_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output reg [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output reg ovalid,
input wire oready);
reg [ADDR_WIDTH-1:0] raddr;
wire [ADDR_WIDTH-1:0] waddr = raddr + size;
wire renable = (|size) && (!ovalid || oready);
simple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(ivalid && iready),
.waddr(waddr),
.wdata(idata),
.rclock(clock),
.renable(renable),
.raddr(raddr),
.rdata(odata));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
size <= 1'b0;
else if ((ivalid && iready) && !(renable))
size <= size + 1'b1;
else if (!(ivalid && iready) && renable)
size <= size - 1'b1;
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 1'b0;
else if (renable)
raddr <= raddr + 1'b1;
end
assign iready = !(&size);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
ovalid <= 1'b0;
else
ovalid <= (|size) || (ovalid && !oready);
end
`ifdef FORMAL
initial assert (!resetn);
always @(posedge clock)
begin
if (resetn)
assert (size <= 1 || ovalid);
end
`endif
endmodule | module axis_fifo_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire clock,
input wire resetn,
output reg [ADDR_WIDTH-1:0] size,
input wire [DATA_WIDTH-1:0] idata,
input wire ivalid,
output wire iready,
output wire [DATA_WIDTH-1:0] odata,
output reg ovalid,
input wire oready); |
reg [ADDR_WIDTH-1:0] raddr;
wire [ADDR_WIDTH-1:0] waddr = raddr + size;
wire renable = (|size) && (!ovalid || oready);
simple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram (
.wclock(clock),
.wenable(ivalid && iready),
.waddr(waddr),
.wdata(idata),
.rclock(clock),
.renable(renable),
.raddr(raddr),
.rdata(odata));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
size <= 1'b0;
else if ((ivalid && iready) && !(renable))
size <= size + 1'b1;
else if (!(ivalid && iready) && renable)
size <= size - 1'b1;
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 1'b0;
else if (renable)
raddr <= raddr + 1'b1;
end
assign iready = !(&size);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
ovalid <= 1'b0;
else
ovalid <= (|size) || (ovalid && !oready);
end
`ifdef FORMAL
initial assert (!resetn);
always @(posedge clock)
begin
if (resetn)
assert (size <= 1 || ovalid);
end
`endif
endmodule | 3 |
137,652 | data/full_repos/permissive/79295554/src/push_to_axis.v | 79,295,554 | push_to_axis.v | v | 261 | 116 | [] | [] | [] | [(13, 47), (54, 88), (95, 129), (136, 170), (177, 260)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/push_to_axis.v:54: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'push_to_axis_ver1\'\nmodule push_to_axis_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver2\'\nmodule push_to_axis_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver3\'\nmodule push_to_axis_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver4\'\nmodule push_to_axis_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver5\'\nmodule push_to_axis_ver5 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH-1)) (\n ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:202: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:213: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:218: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) memory (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:150: Cannot find file containing module: \'axis_fifo_ver4\'\naxis_fifo_ver4 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:109: Cannot find file containing module: \'axis_fifo_ver3\'\naxis_fifo_ver3 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:68: Cannot find file containing module: \'axis_fifo_ver2\'\naxis_fifo_ver2 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:27: Cannot find file containing module: \'axis_fifo_ver1\'\naxis_fifo_ver1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 299,889 | module | module push_to_axis_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready);
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | module push_to_axis_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready); |
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | 3 |
137,653 | data/full_repos/permissive/79295554/src/push_to_axis.v | 79,295,554 | push_to_axis.v | v | 261 | 116 | [] | [] | [] | [(13, 47), (54, 88), (95, 129), (136, 170), (177, 260)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/push_to_axis.v:54: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'push_to_axis_ver1\'\nmodule push_to_axis_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver2\'\nmodule push_to_axis_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver3\'\nmodule push_to_axis_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver4\'\nmodule push_to_axis_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver5\'\nmodule push_to_axis_ver5 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH-1)) (\n ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:202: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:213: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:218: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) memory (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:150: Cannot find file containing module: \'axis_fifo_ver4\'\naxis_fifo_ver4 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:109: Cannot find file containing module: \'axis_fifo_ver3\'\naxis_fifo_ver3 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:68: Cannot find file containing module: \'axis_fifo_ver2\'\naxis_fifo_ver2 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:27: Cannot find file containing module: \'axis_fifo_ver1\'\naxis_fifo_ver1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 299,889 | module | module push_to_axis_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready);
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver2 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | module push_to_axis_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready); |
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver2 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | 3 |
137,654 | data/full_repos/permissive/79295554/src/push_to_axis.v | 79,295,554 | push_to_axis.v | v | 261 | 116 | [] | [] | [] | [(13, 47), (54, 88), (95, 129), (136, 170), (177, 260)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/push_to_axis.v:54: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'push_to_axis_ver1\'\nmodule push_to_axis_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver2\'\nmodule push_to_axis_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver3\'\nmodule push_to_axis_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver4\'\nmodule push_to_axis_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver5\'\nmodule push_to_axis_ver5 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH-1)) (\n ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:202: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:213: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:218: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) memory (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:150: Cannot find file containing module: \'axis_fifo_ver4\'\naxis_fifo_ver4 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:109: Cannot find file containing module: \'axis_fifo_ver3\'\naxis_fifo_ver3 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:68: Cannot find file containing module: \'axis_fifo_ver2\'\naxis_fifo_ver2 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:27: Cannot find file containing module: \'axis_fifo_ver1\'\naxis_fifo_ver1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 299,889 | module | module push_to_axis_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready);
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver3 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | module push_to_axis_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready); |
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver3 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | 3 |
137,655 | data/full_repos/permissive/79295554/src/push_to_axis.v | 79,295,554 | push_to_axis.v | v | 261 | 116 | [] | [] | [] | [(13, 47), (54, 88), (95, 129), (136, 170), (177, 260)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/push_to_axis.v:54: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'push_to_axis_ver1\'\nmodule push_to_axis_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver2\'\nmodule push_to_axis_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver3\'\nmodule push_to_axis_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver4\'\nmodule push_to_axis_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver5\'\nmodule push_to_axis_ver5 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH-1)) (\n ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:202: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:213: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:218: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) memory (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:150: Cannot find file containing module: \'axis_fifo_ver4\'\naxis_fifo_ver4 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:109: Cannot find file containing module: \'axis_fifo_ver3\'\naxis_fifo_ver3 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:68: Cannot find file containing module: \'axis_fifo_ver2\'\naxis_fifo_ver2 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:27: Cannot find file containing module: \'axis_fifo_ver1\'\naxis_fifo_ver1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 299,889 | module | module push_to_axis_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready);
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver4 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | module push_to_axis_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output wire iafull,
output wire [DATA_WIDTH-1:0] odata,
output wire ovalid,
input wire oready); |
wire [ADDR_WIDTH-1:0] size;
wire iready;
axis_fifo_ver4 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (
.clock(clock),
.resetn(resetn),
.size(size),
.idata(idata),
.ivalid(ienable),
.iready(iready),
.odata(odata),
.ovalid(ovalid),
.oready(oready));
assign iafull = (size >= AFULL_LIMIT);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else if (ienable && !iready)
overflow <= 1'b1;
end
endmodule | 3 |
137,656 | data/full_repos/permissive/79295554/src/push_to_axis.v | 79,295,554 | push_to_axis.v | v | 261 | 116 | [] | [] | [] | [(13, 47), (54, 88), (95, 129), (136, 170), (177, 260)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/push_to_axis.v:54: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'push_to_axis_ver1\'\nmodule push_to_axis_ver1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver2\'\nmodule push_to_axis_ver2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver3\'\nmodule push_to_axis_ver3 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver4\'\nmodule push_to_axis_ver4 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH - 1)) (\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'push_to_axis_ver5\'\nmodule push_to_axis_ver5 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH-1)) (\n ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:202: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n waddr <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/push_to_axis.v:213: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance push_to_axis_ver5\n raddr <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:218: Cannot find file containing module: \'simple_dual_port_ram_reg1\'\nsimple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) memory (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.v\n data/full_repos/permissive/79295554/src,data/full_repos/permissive/79295554/simple_dual_port_ram_reg1.sv\n simple_dual_port_ram_reg1\n simple_dual_port_ram_reg1.v\n simple_dual_port_ram_reg1.sv\n obj_dir/simple_dual_port_ram_reg1\n obj_dir/simple_dual_port_ram_reg1.v\n obj_dir/simple_dual_port_ram_reg1.sv\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:150: Cannot find file containing module: \'axis_fifo_ver4\'\naxis_fifo_ver4 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:109: Cannot find file containing module: \'axis_fifo_ver3\'\naxis_fifo_ver3 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:68: Cannot find file containing module: \'axis_fifo_ver2\'\naxis_fifo_ver2 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79295554/src/push_to_axis.v:27: Cannot find file containing module: \'axis_fifo_ver1\'\naxis_fifo_ver1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) axis_fifo_inst (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 299,889 | module | module push_to_axis_ver5 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH-1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output reg iafull,
output wire [DATA_WIDTH-1:0] odata,
output reg ovalid,
input wire oready);
wire wenable = ienable;
reg [ADDR_WIDTH-1:0] waddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 1'b0;
else if (wenable)
waddr <= waddr + 1'b1;
end
wire renable;
reg [ADDR_WIDTH-1:0] raddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 1'b0;
else if (renable)
raddr <= raddr + 1'b1;
end
simple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) memory (
.wclock(clock),
.wenable(wenable),
.waddr(waddr),
.wdata(idata),
.rclock(clock),
.renable(renable),
.raddr(raddr),
.rdata(odata));
wire [ADDR_WIDTH-1:0] size = waddr - raddr;
assign renable = (|size) && (!ovalid || oready);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
ovalid <= 1'b0;
else
ovalid <= renable || (ovalid && !oready);
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
iafull <= 1'b1;
else
iafull <= (size >= AFULL_LIMIT);
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else
overflow <= overflow || ((&size) && wenable && !renable);
end
endmodule | module push_to_axis_ver5 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4, AFULL_LIMIT = 1 << (ADDR_WIDTH-1)) (
input wire clock,
input wire resetn,
output reg overflow,
input wire [DATA_WIDTH-1:0] idata,
input wire ienable,
output reg iafull,
output wire [DATA_WIDTH-1:0] odata,
output reg ovalid,
input wire oready); |
wire wenable = ienable;
reg [ADDR_WIDTH-1:0] waddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
waddr <= 1'b0;
else if (wenable)
waddr <= waddr + 1'b1;
end
wire renable;
reg [ADDR_WIDTH-1:0] raddr;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
raddr <= 1'b0;
else if (renable)
raddr <= raddr + 1'b1;
end
simple_dual_port_ram_reg1 #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) memory (
.wclock(clock),
.wenable(wenable),
.waddr(waddr),
.wdata(idata),
.rclock(clock),
.renable(renable),
.raddr(raddr),
.rdata(odata));
wire [ADDR_WIDTH-1:0] size = waddr - raddr;
assign renable = (|size) && (!ovalid || oready);
always @(posedge clock or negedge resetn)
begin
if (!resetn)
ovalid <= 1'b0;
else
ovalid <= renable || (ovalid && !oready);
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
iafull <= 1'b1;
else
iafull <= (size >= AFULL_LIMIT);
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
overflow <= 1'b0;
else
overflow <= overflow || ((&size) && wenable && !renable);
end
endmodule | 3 |
137,660 | data/full_repos/permissive/79295554/src/rs232tx.v | 79,295,554 | rs232tx.v | v | 120 | 80 | [] | [] | [] | null | line:15: before: "real" | null | 1: b'%Warning-REALCVT: data/full_repos/permissive/79295554/src/rs232tx.v:32: Implicit conversion of real to integer\nlocalparam integer BAUD_COUNT = 1.0 * CLOCK_FREQ / BAUD_RATE;\n ^\n ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/rs232tx.v:41: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n : ... In instance axis_to_rs232\n baud_counter <= BAUD_COUNT - 2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79295554/src/rs232tx.v:43: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n : ... In instance axis_to_rs232\n baud_counter <= BAUD_COUNT - 2;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 299,891 | module | module axis_to_rs232 #(parameter real CLOCK_FREQ=133000000, BAUD_RATE=115200) (
input wire clock,
input wire resetn,
input wire [7:0] idata,
input wire ivalid,
output reg iready,
output reg txd_pin,
input wire ctsn_pin);
localparam integer BAUD_COUNT = 1.0 * CLOCK_FREQ / BAUD_RATE;
localparam integer BAUD_WIDTH = $clog2(BAUD_COUNT - 1);
reg [BAUD_WIDTH:0] baud_counter;
wire baud_tick = baud_counter[BAUD_WIDTH];
always @(posedge clock or negedge resetn)
begin
if (!resetn)
baud_counter <= BAUD_COUNT - 2;
else if (baud_tick || (iready && ivalid))
baud_counter <= BAUD_COUNT - 2;
else
baud_counter <= baud_counter - 1'b1;
end
reg [7:0] buffer;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
{buffer, txd_pin} <= 9'b111111111;
else if (iready && ivalid)
{buffer, txd_pin} <= {idata, 1'b0};
else if (baud_tick)
{buffer, txd_pin} <= {1'b1, buffer};
end
reg [3:0] state;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
state <= 4'b0000;
else if (iready && ivalid)
state <= 4'b0000;
else if (baud_tick)
state <= state + 4'b0001;
end
reg ctsn, ctsn_pin2;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
{ctsn, ctsn_pin2} <= 2'b11;
else
{ctsn, ctsn_pin2} <= {ctsn_pin2, ctsn_pin};
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
iready <= 1'b0;
else if ((iready && ivalid) || ctsn)
iready <= 1'b0;
else
iready <= (state[3] && state[1]) || iready;
end
endmodule | module axis_to_rs232 #(parameter real CLOCK_FREQ=133000000, BAUD_RATE=115200) (
input wire clock,
input wire resetn,
input wire [7:0] idata,
input wire ivalid,
output reg iready,
output reg txd_pin,
input wire ctsn_pin); |
localparam integer BAUD_COUNT = 1.0 * CLOCK_FREQ / BAUD_RATE;
localparam integer BAUD_WIDTH = $clog2(BAUD_COUNT - 1);
reg [BAUD_WIDTH:0] baud_counter;
wire baud_tick = baud_counter[BAUD_WIDTH];
always @(posedge clock or negedge resetn)
begin
if (!resetn)
baud_counter <= BAUD_COUNT - 2;
else if (baud_tick || (iready && ivalid))
baud_counter <= BAUD_COUNT - 2;
else
baud_counter <= baud_counter - 1'b1;
end
reg [7:0] buffer;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
{buffer, txd_pin} <= 9'b111111111;
else if (iready && ivalid)
{buffer, txd_pin} <= {idata, 1'b0};
else if (baud_tick)
{buffer, txd_pin} <= {1'b1, buffer};
end
reg [3:0] state;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
state <= 4'b0000;
else if (iready && ivalid)
state <= 4'b0000;
else if (baud_tick)
state <= state + 4'b0001;
end
reg ctsn, ctsn_pin2;
always @(posedge clock or negedge resetn)
begin
if (!resetn)
{ctsn, ctsn_pin2} <= 2'b11;
else
{ctsn, ctsn_pin2} <= {ctsn_pin2, ctsn_pin};
end
always @(posedge clock or negedge resetn)
begin
if (!resetn)
iready <= 1'b0;
else if ((iready && ivalid) || ctsn)
iready <= 1'b0;
else
iready <= (state[3] && state[1]) || iready;
end
endmodule | 3 |
137,661 | data/full_repos/permissive/79295554/src/sdp_ram.v | 79,295,554 | sdp_ram.v | v | 76 | 87 | [] | [] | [] | [(12, 31), (37, 75)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/sdp_ram.v:37: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'simple_dual_port_ram_reg0\'\nmodule simple_dual_port_ram_reg0 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simple_dual_port_ram_reg1\'\nmodule simple_dual_port_ram_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 299,892 | module | module simple_dual_port_ram_reg0 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire wclock,
input wire wenable,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] wdata,
input wire [ADDR_WIDTH-1:0] raddr,
output wire [DATA_WIDTH-1:0] rdata)
;
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
always @(posedge wclock)
begin
if (wenable)
memory[waddr] <= wdata;
end
assign rdata = memory[raddr];
endmodule | module simple_dual_port_ram_reg0 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire wclock,
input wire wenable,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] wdata,
input wire [ADDR_WIDTH-1:0] raddr,
output wire [DATA_WIDTH-1:0] rdata)
; |
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
always @(posedge wclock)
begin
if (wenable)
memory[waddr] <= wdata;
end
assign rdata = memory[raddr];
endmodule | 3 |
137,662 | data/full_repos/permissive/79295554/src/sdp_ram.v | 79,295,554 | sdp_ram.v | v | 76 | 87 | [] | [] | [] | [(12, 31), (37, 75)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/sdp_ram.v:37: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'simple_dual_port_ram_reg0\'\nmodule simple_dual_port_ram_reg0 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simple_dual_port_ram_reg1\'\nmodule simple_dual_port_ram_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 299,892 | module | module simple_dual_port_ram_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire wclock,
input wire wenable,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] wdata,
input wire rclock,
input wire renable,
input wire [ADDR_WIDTH-1:0] raddr,
output reg [DATA_WIDTH-1:0] rdata);
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
always @(posedge wclock)
begin
if (wenable)
memory[waddr] <= wdata;
end
always @(posedge rclock)
begin
if (renable)
rdata <= memory[raddr];
end
`ifdef FORMAL
always @(posedge wclock)
begin
if (wenable && renable)
assert (waddr != raddr);
end
always @(posedge rclock)
begin
if (wenable && renable)
assert (waddr != raddr);
end
`endif
endmodule | module simple_dual_port_ram_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 4) (
input wire wclock,
input wire wenable,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] wdata,
input wire rclock,
input wire renable,
input wire [ADDR_WIDTH-1:0] raddr,
output reg [DATA_WIDTH-1:0] rdata); |
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
always @(posedge wclock)
begin
if (wenable)
memory[waddr] <= wdata;
end
always @(posedge rclock)
begin
if (renable)
rdata <= memory[raddr];
end
`ifdef FORMAL
always @(posedge wclock)
begin
if (wenable && renable)
assert (waddr != raddr);
end
always @(posedge rclock)
begin
if (wenable && renable)
assert (waddr != raddr);
end
`endif
endmodule | 3 |
137,663 | data/full_repos/permissive/79295554/src/tdp_ram.v | 79,295,554 | tdp_ram.v | v | 199 | 97 | [] | [] | [] | [(12, 49), (55, 96), (102, 145), (151, 198)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/tdp_ram.v:55: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'true_dual_port_ram_readfirst_reg1\'\nmodule true_dual_port_ram_readfirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_readfirst_reg2\'\nmodule true_dual_port_ram_readfirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg1\'\nmodule true_dual_port_ram_writefirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg2\'\nmodule true_dual_port_ram_writefirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 299,893 | module | module true_dual_port_ram_readfirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
;
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
always @(posedge clock1)
begin
if (enable1)
begin
odata1 <= memory[addr1];
if (write1)
memory[addr1] <= idata1;
end
end
always @(posedge clock2)
begin
if (enable2)
begin
odata2 <= memory[addr2];
if (write2)
memory[addr2] <= idata2;
end
end
endmodule | module true_dual_port_ram_readfirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
; |
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
always @(posedge clock1)
begin
if (enable1)
begin
odata1 <= memory[addr1];
if (write1)
memory[addr1] <= idata1;
end
end
always @(posedge clock2)
begin
if (enable2)
begin
odata2 <= memory[addr2];
if (write2)
memory[addr2] <= idata2;
end
end
endmodule | 3 |
137,664 | data/full_repos/permissive/79295554/src/tdp_ram.v | 79,295,554 | tdp_ram.v | v | 199 | 97 | [] | [] | [] | [(12, 49), (55, 96), (102, 145), (151, 198)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/tdp_ram.v:55: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'true_dual_port_ram_readfirst_reg1\'\nmodule true_dual_port_ram_readfirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_readfirst_reg2\'\nmodule true_dual_port_ram_readfirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg1\'\nmodule true_dual_port_ram_writefirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg2\'\nmodule true_dual_port_ram_writefirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 299,893 | module | module true_dual_port_ram_readfirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
;
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1)
begin
if (enable1)
begin
odata1_reg <= memory[addr1];
if (write1)
memory[addr1] <= idata1;
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2)
begin
if (enable2)
begin
odata2_reg <= memory[addr2];
if (write2)
memory[addr2] <= idata2;
end
odata2 <= odata2_reg;
end
endmodule | module true_dual_port_ram_readfirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
; |
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1)
begin
if (enable1)
begin
odata1_reg <= memory[addr1];
if (write1)
memory[addr1] <= idata1;
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2)
begin
if (enable2)
begin
odata2_reg <= memory[addr2];
if (write2)
memory[addr2] <= idata2;
end
odata2 <= odata2_reg;
end
endmodule | 3 |
137,665 | data/full_repos/permissive/79295554/src/tdp_ram.v | 79,295,554 | tdp_ram.v | v | 199 | 97 | [] | [] | [] | [(12, 49), (55, 96), (102, 145), (151, 198)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/tdp_ram.v:55: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'true_dual_port_ram_readfirst_reg1\'\nmodule true_dual_port_ram_readfirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_readfirst_reg2\'\nmodule true_dual_port_ram_readfirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg1\'\nmodule true_dual_port_ram_writefirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg2\'\nmodule true_dual_port_ram_writefirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 299,893 | module | module true_dual_port_ram_writefirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
;
reg [DATA_WIDTH-1:0] memory[(1<<ADDR_WIDTH)-1:0]
;
always @(posedge clock1)
begin
if (enable1)
begin
odata1 <= memory[addr1];
if (write1)
begin
memory[addr1] <= idata1;
odata1 <= idata1;
end
end
end
always @(posedge clock2)
begin
if (enable2)
begin
odata2 <= memory[addr2];
if (write2)
begin
memory[addr2] <= idata2;
odata2 <= idata2;
end
end
end
endmodule | module true_dual_port_ram_writefirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
; |
reg [DATA_WIDTH-1:0] memory[(1<<ADDR_WIDTH)-1:0]
;
always @(posedge clock1)
begin
if (enable1)
begin
odata1 <= memory[addr1];
if (write1)
begin
memory[addr1] <= idata1;
odata1 <= idata1;
end
end
end
always @(posedge clock2)
begin
if (enable2)
begin
odata2 <= memory[addr2];
if (write2)
begin
memory[addr2] <= idata2;
odata2 <= idata2;
end
end
end
endmodule | 3 |
137,666 | data/full_repos/permissive/79295554/src/tdp_ram.v | 79,295,554 | tdp_ram.v | v | 199 | 97 | [] | [] | [] | [(12, 49), (55, 96), (102, 145), (151, 198)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79295554/src/tdp_ram.v:55: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'true_dual_port_ram_readfirst_reg1\'\nmodule true_dual_port_ram_readfirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_readfirst_reg2\'\nmodule true_dual_port_ram_readfirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg1\'\nmodule true_dual_port_ram_writefirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'true_dual_port_ram_writefirst_reg2\'\nmodule true_dual_port_ram_writefirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 299,893 | module | module true_dual_port_ram_writefirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
;
reg [DATA_WIDTH-1:0] memory[(1<<ADDR_WIDTH)-1:0]
;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1)
begin
if (enable1)
begin
odata1_reg <= memory[addr1];
if (write1)
begin
memory[addr1] <= idata1;
odata1_reg <= idata1;
end
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2)
begin
if (enable2)
begin
odata2_reg <= memory[addr2];
if (write2)
begin
memory[addr2] <= idata2;
odata2_reg <= idata2;
end
end
odata2 <= odata2_reg;
end
endmodule | module true_dual_port_ram_writefirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
; |
reg [DATA_WIDTH-1:0] memory[(1<<ADDR_WIDTH)-1:0]
;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1)
begin
if (enable1)
begin
odata1_reg <= memory[addr1];
if (write1)
begin
memory[addr1] <= idata1;
odata1_reg <= idata1;
end
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2)
begin
if (enable2)
begin
odata2_reg <= memory[addr2];
if (write2)
begin
memory[addr2] <= idata2;
odata2_reg <= idata2;
end
end
odata2 <= odata2_reg;
end
endmodule | 3 |
137,668 | data/full_repos/permissive/79391315/src/VGAController.v | 79,391,315 | VGAController.v | v | 114 | 128 | [] | [] | [] | [(3, 113)] | null | null | 1: b'%Warning-UNSIGNED: data/full_repos/permissive/79391315/src/VGAController.v:80: Comparison is constant due to unsigned arithmetic\n : ... In instance VGAController\n if (YTiming >= 0 && YTiming < YSynchPulse)\n ^~\n ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/79391315/src/VGAController.v:88: Comparison is constant due to unsigned arithmetic\n : ... In instance VGAController\n if (XTiming >= 0 && XTiming < XSynchPulse)\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 299,895 | module | module VGAController (PixelClock,
inRed,
inGreen,
inBlue,
outRed,
outGreen,
outBlue,
VertSynchOut,
HorSynchOut,
XPosition,
YPosition);
parameter XLimit = 1688;
parameter XVisible = 1280;
parameter XSynchPulse = 112;
parameter XBackPorch = 248;
parameter YLimit = 1066;
parameter YVisible = 1024;
parameter YSynchPulse = 3;
parameter YBackPorch = 38;
input PixelClock;
input [7:0] inRed;
input [7:0] inGreen;
input [7:0] inBlue;
output [7:0] outRed;
output [7:0] outGreen;
output [7:0] outBlue;
output VertSynchOut;
output HorSynchOut;
output [10:0] XPosition;
output [10:0] YPosition;
reg [10:0] XTiming;
reg [10:0] YTiming;
reg HorSynch;
reg VertSynch;
assign XPosition = XTiming - (XSynchPulse + XBackPorch);
assign YPosition = YTiming - (YSynchPulse + YBackPorch);
always@(posedge PixelClock)
begin
if (XTiming >= XLimit)
XTiming <= 11'd0;
else
XTiming <= XTiming + 1;
end
always@(posedge PixelClock)
begin
if (YTiming >= YLimit && XTiming >= XLimit)
YTiming <= 11'd0;
else if (XTiming >= XLimit && YTiming < YLimit)
YTiming <= YTiming + 1;
else
YTiming <= YTiming;
end
always@(posedge PixelClock)
begin
if (YTiming >= 0 && YTiming < YSynchPulse)
VertSynch <= 1'b0;
else
VertSynch <= 1'b1;
end
always@(posedge PixelClock)
begin
if (XTiming >= 0 && XTiming < XSynchPulse)
HorSynch <= 1'b0;
else
HorSynch <= 1'b1;
end
assign outRed = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inRed : 8'b0;
assign outGreen = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inGreen : 8'b0;
assign outBlue = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inBlue : 8'b0;
assign VertSynchOut = VertSynch;
assign HorSynchOut = HorSynch;
initial
begin
XTiming = 11'b0;
YTiming = 11'b0;
HorSynch = 1'b1;
VertSynch = 1'b1;
end
endmodule | module VGAController (PixelClock,
inRed,
inGreen,
inBlue,
outRed,
outGreen,
outBlue,
VertSynchOut,
HorSynchOut,
XPosition,
YPosition); |
parameter XLimit = 1688;
parameter XVisible = 1280;
parameter XSynchPulse = 112;
parameter XBackPorch = 248;
parameter YLimit = 1066;
parameter YVisible = 1024;
parameter YSynchPulse = 3;
parameter YBackPorch = 38;
input PixelClock;
input [7:0] inRed;
input [7:0] inGreen;
input [7:0] inBlue;
output [7:0] outRed;
output [7:0] outGreen;
output [7:0] outBlue;
output VertSynchOut;
output HorSynchOut;
output [10:0] XPosition;
output [10:0] YPosition;
reg [10:0] XTiming;
reg [10:0] YTiming;
reg HorSynch;
reg VertSynch;
assign XPosition = XTiming - (XSynchPulse + XBackPorch);
assign YPosition = YTiming - (YSynchPulse + YBackPorch);
always@(posedge PixelClock)
begin
if (XTiming >= XLimit)
XTiming <= 11'd0;
else
XTiming <= XTiming + 1;
end
always@(posedge PixelClock)
begin
if (YTiming >= YLimit && XTiming >= XLimit)
YTiming <= 11'd0;
else if (XTiming >= XLimit && YTiming < YLimit)
YTiming <= YTiming + 1;
else
YTiming <= YTiming;
end
always@(posedge PixelClock)
begin
if (YTiming >= 0 && YTiming < YSynchPulse)
VertSynch <= 1'b0;
else
VertSynch <= 1'b1;
end
always@(posedge PixelClock)
begin
if (XTiming >= 0 && XTiming < XSynchPulse)
HorSynch <= 1'b0;
else
HorSynch <= 1'b1;
end
assign outRed = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inRed : 8'b0;
assign outGreen = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inGreen : 8'b0;
assign outBlue = (XTiming >= (XSynchPulse + XBackPorch) && XTiming <= (XSynchPulse + XBackPorch + XVisible)) ? inBlue : 8'b0;
assign VertSynchOut = VertSynch;
assign HorSynchOut = HorSynch;
initial
begin
XTiming = 11'b0;
YTiming = 11'b0;
HorSynch = 1'b1;
VertSynch = 1'b1;
end
endmodule | 3 |
137,669 | data/full_repos/permissive/79391315/src/VGAInterface.v | 79,391,315 | VGAInterface.v | v | 371 | 153 | [] | [] | [] | [(11, 369)] | null | null | 1: b"%Error: data/full_repos/permissive/79391315/src/VGAInterface.v:339: Too many digits for 8 bit number: 8'b111111111\n blueValue <= 8'b111111111;\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 299,896 | module | module VGAInterface(
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS
);
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
reg aresetPll = 0;
wire pixelClock;
wire [10:0] XPixelPosition;
wire [10:0] YPixelPosition;
reg [7:0] redValue;
reg [7:0] greenValue;
reg [7:0] blueValue;
reg [1:0] movement = 0;
parameter r = 15;
reg [20:0] slowClockCounter = 0;
wire slowClock;
reg [20:0] fastClockCounter = 0;
wire fastClock;
reg [10:0] XDotPosition = 500;
reg [10:0] YDotPosition = 500;
reg [10:0] P1x = 225;
reg [10:0] P1y = 500;
reg [10:0] P2x = 1030;
reg [10:0] P2y = 500;
reg [3:0] P1Score = 0;
reg [3:0] P2Score = 0;
reg flag =1'b0;
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b1;
assign VGA_CLK = pixelClock;
assign LEDR[10:0] = SW[1] ? YDotPosition : XDotPosition;
assign slowClock = slowClockCounter[16];
always@ (posedge CLOCK_50)
begin
slowClockCounter <= slowClockCounter + 1;
end
assign fastClock = fastClockCounter[17];
always@ (posedge CLOCK_50)
begin
fastClockCounter <= fastClockCounter + 1;
end
always@(posedge fastClock)
begin
if (SW[0] == 1'b0)
begin
if (KEY[2] == 1'b0 && KEY[3] == 1'b0)
P1y <= P1y;
else if (KEY[2] == 1'b0) begin
if (P1y+125 >896)
P1y <= 771;
else
P1y <= P1y + 1;
end
else if (KEY[3] == 1'b0) begin
if(P1y < 128)
P1y <= 128;
else
P1y <= P1y - 1;
end
end
else if (SW[0] == 1'b1 || flag==1)
P1y <= 500;
end
always@(posedge fastClock)
begin
if (SW[0] == 1'b0)
begin
if (KEY[0] == 1'b0 && KEY[1] == 1'b0)
P2y <= P2y;
else if (KEY[0] == 1'b0) begin
if(P2y+125 > 896)
P2y <= 771;
else
P2y <= P2y + 1;
end
else if (KEY[1] == 1'b0) begin
if(P2y < 128)
P2y <= 128;
else
P2y <= P2y - 1;
end
end
else if (SW[0] == 1'b1 || flag ==1)
P2y <= 500;
end
always@(posedge slowClock)
begin
if (SW[0] == 1'b0)
begin
case(movement)
0: begin
XDotPosition <= XDotPosition + 1;
YDotPosition <= YDotPosition - 1;
end
1: begin
XDotPosition <= XDotPosition + 1;
YDotPosition <= YDotPosition + 1;
end
2: begin
XDotPosition <= XDotPosition - 1;
YDotPosition <= YDotPosition + 1;
end
3: begin
XDotPosition <= XDotPosition - 1;
YDotPosition <= YDotPosition - 1;
end
endcase
if(YDotPosition - r <= 128 && movement == 0)
movement = 1;
else if (YDotPosition - r <= 128 && movement == 3)
movement = 2;
else if (YDotPosition + r >= 896 && movement == 1)
movement = 0;
else if (YDotPosition + r >= 896 && movement == 2)
movement = 3;
else if (XDotPosition -r <= P1x+25 && YDotPosition > P1y && YDotPosition < P1y+125 && movement == 2)
movement = 1;
else if (XDotPosition -r<= P1x+25 && YDotPosition > P1y && YDotPosition < P1y+125 && movement == 3)
movement = 0;
else if (XDotPosition + r >= P2x && YDotPosition > P2y && YDotPosition < P2y+125 && movement == 1)
movement = 2;
else if (XDotPosition + r >= P2x && YDotPosition > P2y && YDotPosition < P2y+125 && movement == 0)
movement = 3;
else if (XDotPosition - r <= 160) begin
P2Score = P2Score + 1;
XDotPosition <= 640;
YDotPosition <= 512;
end
else if (XDotPosition + r >= 1120)begin
P1Score = P1Score + 1;
XDotPosition <= 640;
YDotPosition <= 512;
end
if(P1Score == 10 || P2Score ==10) begin
P1Score<=0;
P2Score<=0;
flag <=1;
end
end
else
begin
XDotPosition <= 500;
YDotPosition <= 500;
P1Score <= 0;
P2Score <= 0;
end
end
VGAFrequency VGAFreq (aresetPll, CLOCK_50, pixelClock);
VGAController VGAControl (pixelClock, redValue, greenValue, blueValue, VGA_R, VGA_G, VGA_B, VGA_VS, VGA_HS, XPixelPosition, YPixelPosition);
always@ (posedge pixelClock)
begin
begin
if (XPixelPosition < 160)
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b11111111;
end
else if (XPixelPosition > 1120)
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b11111111;
end
else if (YPixelPosition < 128 && XPixelPosition > 160 && XPixelPosition < 1120)
begin
redValue <= 8'b11111111;
blueValue <= 8'b11111111;
greenValue <= 8'b00000000;
end
else if (XPixelPosition < 1120 && XPixelPosition > 160 && YPixelPosition > 896)
begin
redValue <= 8'b11111111;
blueValue <= 8'b11111111;
greenValue <= 8'b00000000;
end
else if (XPixelPosition > P1x && XPixelPosition < P1x+25 && YPixelPosition > P1y && YPixelPosition < P1y+125)
begin
redValue <= 8'b00000000;
blueValue <= 8'b111111111;
greenValue <= 8'b11111111;
end
else if (XPixelPosition > P2x && XPixelPosition < P2x+25 && YPixelPosition > P2y && YPixelPosition < P2y+125)
begin
redValue <= 8'b00000000;
blueValue <= 8'b11111111;
greenValue <= 8'b11111111;
end
else if (((XPixelPosition-XDotPosition)**2
+ (YPixelPosition-YDotPosition)**2) < 15**2)
begin
redValue <= 8'b11111111;
blueValue <= 8'b00000000;
greenValue <= 8'b00000000;
end
else
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b00000000;
end
end
end
ScoreDecoder p1(P1Score, HEX7, HEX6);
ScoreDecoder p2(P2Score, HEX5, HEX4);
endmodule | module VGAInterface(
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS
); |
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
reg aresetPll = 0;
wire pixelClock;
wire [10:0] XPixelPosition;
wire [10:0] YPixelPosition;
reg [7:0] redValue;
reg [7:0] greenValue;
reg [7:0] blueValue;
reg [1:0] movement = 0;
parameter r = 15;
reg [20:0] slowClockCounter = 0;
wire slowClock;
reg [20:0] fastClockCounter = 0;
wire fastClock;
reg [10:0] XDotPosition = 500;
reg [10:0] YDotPosition = 500;
reg [10:0] P1x = 225;
reg [10:0] P1y = 500;
reg [10:0] P2x = 1030;
reg [10:0] P2y = 500;
reg [3:0] P1Score = 0;
reg [3:0] P2Score = 0;
reg flag =1'b0;
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b1;
assign VGA_CLK = pixelClock;
assign LEDR[10:0] = SW[1] ? YDotPosition : XDotPosition;
assign slowClock = slowClockCounter[16];
always@ (posedge CLOCK_50)
begin
slowClockCounter <= slowClockCounter + 1;
end
assign fastClock = fastClockCounter[17];
always@ (posedge CLOCK_50)
begin
fastClockCounter <= fastClockCounter + 1;
end
always@(posedge fastClock)
begin
if (SW[0] == 1'b0)
begin
if (KEY[2] == 1'b0 && KEY[3] == 1'b0)
P1y <= P1y;
else if (KEY[2] == 1'b0) begin
if (P1y+125 >896)
P1y <= 771;
else
P1y <= P1y + 1;
end
else if (KEY[3] == 1'b0) begin
if(P1y < 128)
P1y <= 128;
else
P1y <= P1y - 1;
end
end
else if (SW[0] == 1'b1 || flag==1)
P1y <= 500;
end
always@(posedge fastClock)
begin
if (SW[0] == 1'b0)
begin
if (KEY[0] == 1'b0 && KEY[1] == 1'b0)
P2y <= P2y;
else if (KEY[0] == 1'b0) begin
if(P2y+125 > 896)
P2y <= 771;
else
P2y <= P2y + 1;
end
else if (KEY[1] == 1'b0) begin
if(P2y < 128)
P2y <= 128;
else
P2y <= P2y - 1;
end
end
else if (SW[0] == 1'b1 || flag ==1)
P2y <= 500;
end
always@(posedge slowClock)
begin
if (SW[0] == 1'b0)
begin
case(movement)
0: begin
XDotPosition <= XDotPosition + 1;
YDotPosition <= YDotPosition - 1;
end
1: begin
XDotPosition <= XDotPosition + 1;
YDotPosition <= YDotPosition + 1;
end
2: begin
XDotPosition <= XDotPosition - 1;
YDotPosition <= YDotPosition + 1;
end
3: begin
XDotPosition <= XDotPosition - 1;
YDotPosition <= YDotPosition - 1;
end
endcase
if(YDotPosition - r <= 128 && movement == 0)
movement = 1;
else if (YDotPosition - r <= 128 && movement == 3)
movement = 2;
else if (YDotPosition + r >= 896 && movement == 1)
movement = 0;
else if (YDotPosition + r >= 896 && movement == 2)
movement = 3;
else if (XDotPosition -r <= P1x+25 && YDotPosition > P1y && YDotPosition < P1y+125 && movement == 2)
movement = 1;
else if (XDotPosition -r<= P1x+25 && YDotPosition > P1y && YDotPosition < P1y+125 && movement == 3)
movement = 0;
else if (XDotPosition + r >= P2x && YDotPosition > P2y && YDotPosition < P2y+125 && movement == 1)
movement = 2;
else if (XDotPosition + r >= P2x && YDotPosition > P2y && YDotPosition < P2y+125 && movement == 0)
movement = 3;
else if (XDotPosition - r <= 160) begin
P2Score = P2Score + 1;
XDotPosition <= 640;
YDotPosition <= 512;
end
else if (XDotPosition + r >= 1120)begin
P1Score = P1Score + 1;
XDotPosition <= 640;
YDotPosition <= 512;
end
if(P1Score == 10 || P2Score ==10) begin
P1Score<=0;
P2Score<=0;
flag <=1;
end
end
else
begin
XDotPosition <= 500;
YDotPosition <= 500;
P1Score <= 0;
P2Score <= 0;
end
end
VGAFrequency VGAFreq (aresetPll, CLOCK_50, pixelClock);
VGAController VGAControl (pixelClock, redValue, greenValue, blueValue, VGA_R, VGA_G, VGA_B, VGA_VS, VGA_HS, XPixelPosition, YPixelPosition);
always@ (posedge pixelClock)
begin
begin
if (XPixelPosition < 160)
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b11111111;
end
else if (XPixelPosition > 1120)
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b11111111;
end
else if (YPixelPosition < 128 && XPixelPosition > 160 && XPixelPosition < 1120)
begin
redValue <= 8'b11111111;
blueValue <= 8'b11111111;
greenValue <= 8'b00000000;
end
else if (XPixelPosition < 1120 && XPixelPosition > 160 && YPixelPosition > 896)
begin
redValue <= 8'b11111111;
blueValue <= 8'b11111111;
greenValue <= 8'b00000000;
end
else if (XPixelPosition > P1x && XPixelPosition < P1x+25 && YPixelPosition > P1y && YPixelPosition < P1y+125)
begin
redValue <= 8'b00000000;
blueValue <= 8'b111111111;
greenValue <= 8'b11111111;
end
else if (XPixelPosition > P2x && XPixelPosition < P2x+25 && YPixelPosition > P2y && YPixelPosition < P2y+125)
begin
redValue <= 8'b00000000;
blueValue <= 8'b11111111;
greenValue <= 8'b11111111;
end
else if (((XPixelPosition-XDotPosition)**2
+ (YPixelPosition-YDotPosition)**2) < 15**2)
begin
redValue <= 8'b11111111;
blueValue <= 8'b00000000;
greenValue <= 8'b00000000;
end
else
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b00000000;
end
end
end
ScoreDecoder p1(P1Score, HEX7, HEX6);
ScoreDecoder p2(P2Score, HEX5, HEX4);
endmodule | 3 |
137,675 | data/full_repos/permissive/79817529/example RTL/00_HDMI_LVDS/LVDS_test/LVDS_test.v | 79,817,529 | LVDS_test.v | v | 158 | 117 | [] | [] | [] | [(3, 152)] | null | null | 1: b'%Error: Cannot find file containing module: RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n ... Looked in:\n data/full_repos/permissive/79817529/example/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n data/full_repos/permissive/79817529/example/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.v\n data/full_repos/permissive/79817529/example/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.sv\n RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.v\n RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.sv\n obj_dir/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n obj_dir/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.v\n obj_dir/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/79817529/example\n%Error: Cannot find file containing module: RTL/00_HDMI_LVDS/LVDS_test/LVDS_test.v\n%Error: Exiting due to 3 error(s)\n' | 299,913 | module | module LVDS_test(
input clk,
output channel1_p,
output channel1_n,
output channel2_p,
output channel2_n,
output channel3_p,
output channel3_n,
output channel4_p,
output channel4_n,
output clock_p,
output clock_n,
output reg led
);
reg [7:0] RGBimg;
reg [30:0] Contador=0;
parameter ScreenX = 1280;
parameter ScreenY = 800;
parameter BlankingVertical = 12;
parameter BlankingHorizontal = 50;
wire clo,clk6x,clk_lckd, clkdcm;
reg [7:0] Red = 8'h0;
reg [7:0] Blue = 8'h0;
reg [7:0] Green = 8'hFF;
reg [10:0] ContadorX = ScreenX+BlankingHorizontal-3;
reg [10:0] ContadorY = ScreenY+BlankingVertical;
assign clkprueba =clk6x;
wire HSync =((ContadorX>ScreenX) & (ContadorX<(ScreenX+(BlankingHorizontal/2))))?0:1;
wire VSync =((ContadorY>ScreenY) & (ContadorY<(ScreenY+(BlankingVertical/2))))?0:1;
wire DataEnable = ((ContadorX<ScreenX) & (ContadorY<ScreenY));
always @(posedge clk6x) begin
ContadorX <= (ContadorX==(ScreenX+BlankingHorizontal)) ? 0 : ContadorX+1;
if(ContadorX==(ScreenX+BlankingHorizontal)) ContadorY <= (ContadorY==(ScreenY+BlankingVertical)) ? 0 : ContadorY+1;
end
DCM_SP #(
.CLKIN_PERIOD (83),
.CLKFX_MULTIPLY (6),
.CLKFX_DIVIDE (1)
)
dcm_main (
.CLKIN (clk),
.CLKFB (clo),
.RST (1'b0),
.CLK0 (clkdcm),
.CLKFX (clk6x),
.LOCKED (clk_lckd)
);
BUFG clk_bufg (.I(clkdcm), .O(clo) ) ;
video_lvds videoencoder (
.DotClock(clk6x),
.HSync(HSync),
.VSync(VSync),
.DataEnable(DataEnable),
.Red(Red),
.Green(Green),
.Blue(Blue),
.channel1_p(channel1_p),
.channel1_n(channel1_n),
.channel2_p(channel2_p),
.channel2_n(channel2_n),
.channel3_p(channel3_p),
.channel3_n(channel3_n),
.channel4_p(channel4_p),
.channel4_n(channel4_n),
.clock_p(clock_p),
.clock_n(clock_n)
);
always @(posedge clk6x)
begin
if (led) begin
if(ContadorX < ScreenX/8) begin Blue <= 8'b00; Red <= 8'b0; Green <= 8'b0;
end else if(ContadorX < ScreenX/4) begin Blue <= 8'hFF; Red <= 8'b0; Green <= 8'b0;
end else if(ContadorX < 3*ScreenX/8) begin Blue <= 8'b00; Red <= 8'HFF; Green <= 8'b0;
end else if(ContadorX < ScreenX/2) begin Blue <= 8'hff; Red <= 8'hff; Green <= 8'b0;
end else if(ContadorX < 5*ScreenX/8) begin Blue <= 8'b0; Red <= 8'b0; Green <= 8'hff;
end else if(ContadorX < 3*ScreenX/4) begin Blue <= 8'hff; Red <= 8'b0; Green <= 8'hff;
end else if(ContadorX < 7*ScreenX/8) begin Blue <= 8'b0; Red <= 8'hff; Green <= 8'hff;
end else begin Blue <= 8'b11111111; Red <= 8'hff; Green <= 8'b11111111;
end
end else begin
Red <= 00;
Green <= 0;
Blue <= RGBimg;
end
end
always @(posedge clk6x)
begin
Contador <= Contador + 1;
if (Contador==36000000*2)
begin
led <= ~led;
Contador <= 0;
end
end
parameter tm = (1<<12) -1;
reg [7:0] ram [0:tm];
always @(clk6x) begin
if ((ContadorX+ (ScreenX*ContadorY))<tm )
RGBimg = ram[ContadorX+ (ScreenX*ContadorY)] ;
else
RGBimg = 8'h00;
end
initial
begin
$readmemh("/scriptimg2ram/image.mem", ram);
end
endmodule | module LVDS_test(
input clk,
output channel1_p,
output channel1_n,
output channel2_p,
output channel2_n,
output channel3_p,
output channel3_n,
output channel4_p,
output channel4_n,
output clock_p,
output clock_n,
output reg led
); |
reg [7:0] RGBimg;
reg [30:0] Contador=0;
parameter ScreenX = 1280;
parameter ScreenY = 800;
parameter BlankingVertical = 12;
parameter BlankingHorizontal = 50;
wire clo,clk6x,clk_lckd, clkdcm;
reg [7:0] Red = 8'h0;
reg [7:0] Blue = 8'h0;
reg [7:0] Green = 8'hFF;
reg [10:0] ContadorX = ScreenX+BlankingHorizontal-3;
reg [10:0] ContadorY = ScreenY+BlankingVertical;
assign clkprueba =clk6x;
wire HSync =((ContadorX>ScreenX) & (ContadorX<(ScreenX+(BlankingHorizontal/2))))?0:1;
wire VSync =((ContadorY>ScreenY) & (ContadorY<(ScreenY+(BlankingVertical/2))))?0:1;
wire DataEnable = ((ContadorX<ScreenX) & (ContadorY<ScreenY));
always @(posedge clk6x) begin
ContadorX <= (ContadorX==(ScreenX+BlankingHorizontal)) ? 0 : ContadorX+1;
if(ContadorX==(ScreenX+BlankingHorizontal)) ContadorY <= (ContadorY==(ScreenY+BlankingVertical)) ? 0 : ContadorY+1;
end
DCM_SP #(
.CLKIN_PERIOD (83),
.CLKFX_MULTIPLY (6),
.CLKFX_DIVIDE (1)
)
dcm_main (
.CLKIN (clk),
.CLKFB (clo),
.RST (1'b0),
.CLK0 (clkdcm),
.CLKFX (clk6x),
.LOCKED (clk_lckd)
);
BUFG clk_bufg (.I(clkdcm), .O(clo) ) ;
video_lvds videoencoder (
.DotClock(clk6x),
.HSync(HSync),
.VSync(VSync),
.DataEnable(DataEnable),
.Red(Red),
.Green(Green),
.Blue(Blue),
.channel1_p(channel1_p),
.channel1_n(channel1_n),
.channel2_p(channel2_p),
.channel2_n(channel2_n),
.channel3_p(channel3_p),
.channel3_n(channel3_n),
.channel4_p(channel4_p),
.channel4_n(channel4_n),
.clock_p(clock_p),
.clock_n(clock_n)
);
always @(posedge clk6x)
begin
if (led) begin
if(ContadorX < ScreenX/8) begin Blue <= 8'b00; Red <= 8'b0; Green <= 8'b0;
end else if(ContadorX < ScreenX/4) begin Blue <= 8'hFF; Red <= 8'b0; Green <= 8'b0;
end else if(ContadorX < 3*ScreenX/8) begin Blue <= 8'b00; Red <= 8'HFF; Green <= 8'b0;
end else if(ContadorX < ScreenX/2) begin Blue <= 8'hff; Red <= 8'hff; Green <= 8'b0;
end else if(ContadorX < 5*ScreenX/8) begin Blue <= 8'b0; Red <= 8'b0; Green <= 8'hff;
end else if(ContadorX < 3*ScreenX/4) begin Blue <= 8'hff; Red <= 8'b0; Green <= 8'hff;
end else if(ContadorX < 7*ScreenX/8) begin Blue <= 8'b0; Red <= 8'hff; Green <= 8'hff;
end else begin Blue <= 8'b11111111; Red <= 8'hff; Green <= 8'b11111111;
end
end else begin
Red <= 00;
Green <= 0;
Blue <= RGBimg;
end
end
always @(posedge clk6x)
begin
Contador <= Contador + 1;
if (Contador==36000000*2)
begin
led <= ~led;
Contador <= 0;
end
end
parameter tm = (1<<12) -1;
reg [7:0] ram [0:tm];
always @(clk6x) begin
if ((ContadorX+ (ScreenX*ContadorY))<tm )
RGBimg = ram[ContadorX+ (ScreenX*ContadorY)] ;
else
RGBimg = 8'h00;
end
initial
begin
$readmemh("/scriptimg2ram/image.mem", ram);
end
endmodule | 4 |
137,676 | data/full_repos/permissive/79817529/example RTL/00_HDMI_LVDS/LVDS_test/LVDS_test_TB.v | 79,817,529 | LVDS_test_TB.v | v | 24 | 37 | [] | [] | [] | null | line:20: before: "$" | null | 1: b'%Error: Cannot find file containing module: RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n ... Looked in:\n data/full_repos/permissive/79817529/example/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n data/full_repos/permissive/79817529/example/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.v\n data/full_repos/permissive/79817529/example/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.sv\n RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.v\n RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.sv\n obj_dir/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529\n obj_dir/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.v\n obj_dir/RTL/00_HDMI_LVDS/LVDS_test,data/full_repos/permissive/79817529.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/79817529/example\n%Error: Cannot find file containing module: RTL/00_HDMI_LVDS/LVDS_test/LVDS_test_TB.v\n%Error: Exiting due to 3 error(s)\n' | 299,914 | module | module LVDS_test_TB ();
reg sys_clk_i, sys_rst_i;
LVDS_test uut(.clk(sys_clk_i));
initial begin
sys_clk_i = 1;
end
always sys_clk_i = #2000 ~sys_clk_i;
initial begin: TEST_CASE
$dumpfile("LVDS_test_TB.vcd");
$dumpvars(-1, uut);
#1000000 $finish;
end
endmodule | module LVDS_test_TB (); |
reg sys_clk_i, sys_rst_i;
LVDS_test uut(.clk(sys_clk_i));
initial begin
sys_clk_i = 1;
end
always sys_clk_i = #2000 ~sys_clk_i;
initial begin: TEST_CASE
$dumpfile("LVDS_test_TB.vcd");
$dumpvars(-1, uut);
#1000000 $finish;
end
endmodule | 4 |
137,678 | data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_basys/sum4b/testbench.v | 79,817,529 | testbench.v | v | 55 | 81 | [] | [] | [] | null | line:49: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_basys/sum4b/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("el valor de %d + %d = 0x%d%d", xi,yi,co,zi) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_basys/sum4b/testbench.v:36: Cannot find file containing module: \'sum4b\'\n sum4b uut (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_basys/sum4b,data/full_repos/permissive/79817529/sum4b\n data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_basys/sum4b,data/full_repos/permissive/79817529/sum4b.v\n data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_basys/sum4b,data/full_repos/permissive/79817529/sum4b.sv\n sum4b\n sum4b.v\n sum4b.sv\n obj_dir/sum4b\n obj_dir/sum4b.v\n obj_dir/sum4b.sv\n%Warning-WIDTH: data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_basys/sum4b/testbench.v:46: Operator LT expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'yi\' generates 4 bits.\n : ... In instance testbench\n for (yi = 0; yi < 16; yi = yi + 1) begin\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,924 | module | module testbench;
reg [3:0] xi;
reg [3:0] yi;
wire co;
wire [3:0] zi;
sum4b uut (
.xi(xi),
.yi(yi),
.co(co),
.zi(zi)
);
initial begin
xi=0;
for (yi = 0; yi < 16; yi = yi + 1) begin
if (yi==0)
xi=xi+1;
#5 $display("el valor de %d + %d = 0x%d%d", xi,yi,co,zi) ;
end
end
endmodule | module testbench; |
reg [3:0] xi;
reg [3:0] yi;
wire co;
wire [3:0] zi;
sum4b uut (
.xi(xi),
.yi(yi),
.co(co),
.zi(zi)
);
initial begin
xi=0;
for (yi = 0; yi < 16; yi = yi + 1) begin
if (yi==0)
xi=xi+1;
#5 $display("el valor de %d + %d = 0x%d%d", xi,yi,co,zi) ;
end
end
endmodule | 4 |
137,679 | data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_quacho/sum4b/testbench.v | 79,817,529 | testbench.v | v | 55 | 81 | [] | [] | [] | null | line:49: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_quacho/sum4b/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("el valor de %d + %d = %d", xi,yi,zi) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_quacho/sum4b/testbench.v:36: Cannot find file containing module: \'sum4b\'\n sum4b uut (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_quacho/sum4b,data/full_repos/permissive/79817529/sum4b\n data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_quacho/sum4b,data/full_repos/permissive/79817529/sum4b.v\n data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_quacho/sum4b,data/full_repos/permissive/79817529/sum4b.sv\n sum4b\n sum4b.v\n sum4b.sv\n obj_dir/sum4b\n obj_dir/sum4b.v\n obj_dir/sum4b.sv\n%Warning-WIDTH: data/full_repos/permissive/79817529/lab/lab02-sumador4b/src_ise_quacho/sum4b/testbench.v:46: Operator LT expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'yi\' generates 4 bits.\n : ... In instance testbench\n for (yi = 0; yi < 16; yi = yi + 1) begin\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,927 | module | module testbench;
reg [3:0] xi;
reg [3:0] yi;
wire co;
wire [3:0] zi;
sum4b uut (
.xi(xi),
.yi(yi),
.co(co),
.zi(zi)
);
initial begin
xi=0;
for (yi = 0; yi < 16; yi = yi + 1) begin
if (yi==0)
xi=xi+1;
#5 $display("el valor de %d + %d = %d", xi,yi,zi) ;
end
end
endmodule | module testbench; |
reg [3:0] xi;
reg [3:0] yi;
wire co;
wire [3:0] zi;
sum4b uut (
.xi(xi),
.yi(yi),
.co(co),
.zi(zi)
);
initial begin
xi=0;
for (yi = 0; yi < 16; yi = yi + 1) begin
if (yi==0)
xi=xi+1;
#5 $display("el valor de %d + %d = %d", xi,yi,zi) ;
end
end
endmodule | 4 |
137,680 | data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v | 79,817,529 | BCD2SSeg_TB.v | v | 39 | 42 | [] | [] | [] | null | line:35: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n BCD = 0; #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n BCD = 1; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n BCD = 2; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n BCD = 3; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n BCD = 4; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n BCD = 5; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n BCD = 6; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n BCD = 7; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n BCD = 8; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n BCD = 9; #10;\n ^\n%Error: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:34: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("BCDtoSSeg_TB.vcd");\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab03-BCD2SSeg/src_ise_basys2/BCD2SSeg/BCD2SSeg_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n #(200) $finish;\n ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,931 | module | module BCDtoSSeg_TB;
reg [3:0] BCD;
wire [6:0] SSeg;
BCDtoSSeg uut (
.BCD(BCD),
.SSeg(SSeg)
);
initial begin
BCD = 0; #10;
BCD = 1; #10;
BCD = 2; #10;
BCD = 3; #10;
BCD = 4; #10;
BCD = 5; #10;
BCD = 6; #10;
BCD = 7; #10;
BCD = 8; #10;
BCD = 9; #10;
end
initial begin: TEST_CASE
$dumpfile("BCDtoSSeg_TB.vcd");
#(200) $finish;
end
endmodule | module BCDtoSSeg_TB; |
reg [3:0] BCD;
wire [6:0] SSeg;
BCDtoSSeg uut (
.BCD(BCD),
.SSeg(SSeg)
);
initial begin
BCD = 0; #10;
BCD = 1; #10;
BCD = 2; #10;
BCD = 3; #10;
BCD = 4; #10;
BCD = 5; #10;
BCD = 6; #10;
BCD = 7; #10;
BCD = 8; #10;
BCD = 9; #10;
end
initial begin: TEST_CASE
$dumpfile("BCDtoSSeg_TB.vcd");
#(200) $finish;
end
endmodule | 4 |
137,681 | data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v | 79,817,529 | testbench.v | v | 66 | 81 | [] | [] | [] | null | line:59: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10 init = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n #2; init = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2; init = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n #25 $display("el valor de %d * %d = %d", MD,MR,pp) ;\n ^\n%Error: data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v:38: Cannot find file containing module: \'multiplicador\'\n multiplicador uut (\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador,data/full_repos/permissive/79817529/multiplicador\n data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador,data/full_repos/permissive/79817529/multiplicador.v\n data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador,data/full_repos/permissive/79817529/multiplicador.sv\n multiplicador\n multiplicador.v\n multiplicador.sv\n obj_dir/multiplicador\n obj_dir/multiplicador.v\n obj_dir/multiplicador.sv\n%Warning-WIDTH: data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_ise_basys2/multiplicador/testbench.v:53: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'MR\' generates 3 bits.\n : ... In instance testbench\n for (MR = 0; MR < 8; MR = MR + 1) begin\n ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,944 | module | module testbench;
reg [2:0] MR;
reg [2:0] MD;
reg init;
reg clk;
wire [5:0] pp;
wire done;
multiplicador uut (
.MR(MR),
.MD(MD),
.init(init),
.clk(clk),
.pp(pp),
.done(done)
);
always #1 clk = ~clk;
initial begin
#10 init = 0;
clk = 0;
MD=0;
for (MR = 0; MR < 8; MR = MR + 1) begin
if(MR==0)begin
MD=MD+1;
end
#2; init = 1;
#2; init = 0;
#25 $display("el valor de %d * %d = %d", MD,MR,pp) ;
end
end
endmodule | module testbench; |
reg [2:0] MR;
reg [2:0] MD;
reg init;
reg clk;
wire [5:0] pp;
wire done;
multiplicador uut (
.MR(MR),
.MD(MD),
.init(init),
.clk(clk),
.pp(pp),
.done(done)
);
always #1 clk = ~clk;
initial begin
#10 init = 0;
clk = 0;
MD=0;
for (MR = 0; MR < 8; MR = MR + 1) begin
if(MR==0)begin
MD=MD+1;
end
#2; init = 1;
#2; init = 0;
#25 $display("el valor de %d * %d = %d", MD,MR,pp) ;
end
end
endmodule | 4 |
137,682 | data/full_repos/permissive/79817529/lab/lab05_multiplicador_ASM/src_makefile/multiplicador/multiplicador.v | 79,817,529 | multiplicador.v | v | 129 | 83 | [] | [] | [] | [(21, 128)] | null | data/verilator_xmls/92e4f905-d003-47bd-9692-adfcbc7c31ff.xml | null | 299,945 | module | module multiplicador( input [2:0] MR,
input [2:0] MD,
input init,
input clk,
output reg [5:0] pp,
output reg done
);
reg sh;
reg rst;
reg add;
reg [5:0] A;
reg [2:0] B;
wire z;
reg [2:0] status =0;
assign z=(B==0)?1:0;
always @(posedge clk) begin
if (rst) begin
A = {3'b000,MD};
B = MR;
end
else begin
if (sh) begin
A= A << 1;
B = B >> 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
pp =0;
end
else begin
if (add) begin
pp =pp+A;
end
end
end
parameter START =0, CHECK =1, ADD =2, SHIFT =3, END1 =4;
always @(posedge clk) begin
case (status)
START: begin
sh=0;
add=0;
if (init) begin
status=CHECK;
done =0;
rst=1;
end
end
CHECK: begin
done=0;
rst=0;
sh=0;
add=0;
if (B[0]==1)
status=ADD;
else
status=SHIFT;
end
ADD: begin
done=0;
rst=0;
sh=0;
add=1;
status=SHIFT;
end
SHIFT: begin
done=0;
rst=0;
sh=1;
add=0;
if (z==1)
status=END1;
else
status=CHECK;
end
END1: begin
done =1;
rst =0;
sh =0;
add =0;
status =START;
end
default:
status =START;
endcase
end
endmodule | module multiplicador( input [2:0] MR,
input [2:0] MD,
input init,
input clk,
output reg [5:0] pp,
output reg done
); |
reg sh;
reg rst;
reg add;
reg [5:0] A;
reg [2:0] B;
wire z;
reg [2:0] status =0;
assign z=(B==0)?1:0;
always @(posedge clk) begin
if (rst) begin
A = {3'b000,MD};
B = MR;
end
else begin
if (sh) begin
A= A << 1;
B = B >> 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
pp =0;
end
else begin
if (add) begin
pp =pp+A;
end
end
end
parameter START =0, CHECK =1, ADD =2, SHIFT =3, END1 =4;
always @(posedge clk) begin
case (status)
START: begin
sh=0;
add=0;
if (init) begin
status=CHECK;
done =0;
rst=1;
end
end
CHECK: begin
done=0;
rst=0;
sh=0;
add=0;
if (B[0]==1)
status=ADD;
else
status=SHIFT;
end
ADD: begin
done=0;
rst=0;
sh=0;
add=1;
status=SHIFT;
end
SHIFT: begin
done=0;
rst=0;
sh=1;
add=0;
if (z==1)
status=END1;
else
status=CHECK;
end
END1: begin
done =1;
rst =0;
sh =0;
add =0;
status =START;
end
default:
status =START;
endcase
end
endmodule | 4 |
137,683 | data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v | 79,817,529 | alu.v | v | 78 | 88 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xf3 in position 195: invalid continuation byte | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:8: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] sseg,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:54: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n : ... In instance alu\n 2\'b00: int_bcd <={8\'b00,sal_suma};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:55: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n : ... In instance alu\n 2\'b01: int_bcd <={8\'b00,sal_resta};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:56: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 14 bits.\n : ... In instance alu\n 2\'b10: int_bcd <={8\'b00,sal_mult};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:57: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n : ... In instance alu\n 2\'b11: int_bcd <={8\'b00,sal_div};\n ^~\n%Error: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:67: Cannot find file containing module: \'sum4b\'\nsum4b sum(. init(init_suma),.xi({1\'b0,portA}), .yi({1\'b0,portB}),.sal(sal_suma));\n^~~~~\n ... Looked in:\n data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu,data/full_repos/permissive/79817529/sum4b\n data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu,data/full_repos/permissive/79817529/sum4b.v\n data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu,data/full_repos/permissive/79817529/sum4b.sv\n sum4b\n sum4b.v\n sum4b.sv\n obj_dir/sum4b\n obj_dir/sum4b.v\n obj_dir/sum4b.sv\n%Error: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:68: Cannot find file containing module: \'multiplicador\'\nmultiplicador mul ( .MR(portA), .MD(portB), .init(init_mult),.clk(clk), .pp(sal_mult));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/alu.v:69: Cannot find file containing module: \'display\'\ndisplay dp( .num(int_bcd), .clk(clk), .sseg(sseg), .an(an), .rst(rst));\n^~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n' | 299,947 | module | module alu(
input [2:0] portA,
input [2:0] portB,
input [1:0] opcode,
output [0:6] sseg,
output [3:0] an,
input clk,
input rst
);
wire [3:0] sal_suma;
wire [3:0] sal_resta;
wire [3:0] sal_div;
wire [5:0] sal_mult;
reg [3:0] init;
wire init_suma;
wire init_resta;
wire init_mult;
wire init_div;
assign init_suma= init[0];
assign init_resta=init[1];
assign init_mult=init[2];
assign init_div=init[3];
reg [15:0]int_bcd;
wire [3:0] operacion;
always @(*) begin
case(opcode)
2'b00: init<=1;
2'b01: init<=2;
2'b10: init<=4;
2'b11: init<=8;
default:
init <= 0;
endcase
end
always @(*) begin
case(opcode)
2'b00: int_bcd <={8'b00,sal_suma};
2'b01: int_bcd <={8'b00,sal_resta};
2'b10: int_bcd <={8'b00,sal_mult};
2'b11: int_bcd <={8'b00,sal_div};
default:
int_bcd <= 0;
endcase
end
sum4b sum(. init(init_suma),.xi({1'b0,portA}), .yi({1'b0,portB}),.sal(sal_suma));
multiplicador mul ( .MR(portA), .MD(portB), .init(init_mult),.clk(clk), .pp(sal_mult));
display dp( .num(int_bcd), .clk(clk), .sseg(sseg), .an(an), .rst(rst));
endmodule | module alu(
input [2:0] portA,
input [2:0] portB,
input [1:0] opcode,
output [0:6] sseg,
output [3:0] an,
input clk,
input rst
); |
wire [3:0] sal_suma;
wire [3:0] sal_resta;
wire [3:0] sal_div;
wire [5:0] sal_mult;
reg [3:0] init;
wire init_suma;
wire init_resta;
wire init_mult;
wire init_div;
assign init_suma= init[0];
assign init_resta=init[1];
assign init_mult=init[2];
assign init_div=init[3];
reg [15:0]int_bcd;
wire [3:0] operacion;
always @(*) begin
case(opcode)
2'b00: init<=1;
2'b01: init<=2;
2'b10: init<=4;
2'b11: init<=8;
default:
init <= 0;
endcase
end
always @(*) begin
case(opcode)
2'b00: int_bcd <={8'b00,sal_suma};
2'b01: int_bcd <={8'b00,sal_resta};
2'b10: int_bcd <={8'b00,sal_mult};
2'b11: int_bcd <={8'b00,sal_div};
default:
int_bcd <= 0;
endcase
end
sum4b sum(. init(init_suma),.xi({1'b0,portA}), .yi({1'b0,portB}),.sal(sal_suma));
multiplicador mul ( .MR(portA), .MD(portB), .init(init_mult),.clk(clk), .pp(sal_mult));
display dp( .num(int_bcd), .clk(clk), .sseg(sseg), .an(an), .rst(rst));
endmodule | 4 |
137,684 | data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v | 79,817,529 | testbench.v | v | 78 | 81 | [] | [] | [] | [(25, 76)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n #50 opcode = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n #50 opcode = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n #50 opcode = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:70: Unsupported: Ignoring delay on this delayed statement.\n #50 opcode = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:35: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] sseg;\n ^\n%Error: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/testbench.v:39: Cannot find file containing module: \'alu\'\n alu uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu,data/full_repos/permissive/79817529/alu\n data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu,data/full_repos/permissive/79817529/alu.v\n data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu,data/full_repos/permissive/79817529/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,948 | module | module testbench;
reg [2:0] portA;
reg [2:0] portB;
reg [1:0] opcode;
reg clk;
reg rst;
wire [0:6] sseg;
wire [3:0] an;
alu uut (
.portA(portA),
.portB(portB),
.opcode(opcode),
.sseg(sseg),
.an(an),
.clk(clk),
.rst(rst)
);
initial begin
opcode = 0;
clk = 0;
rst = 1;
portA=5;
portB=3;
#10;
rst = 0;
#50 opcode = 0;
#50 opcode = 1;
#50 opcode = 2;
#50 opcode = 3;
end
always #1 clk = ~clk;
endmodule | module testbench; |
reg [2:0] portA;
reg [2:0] portB;
reg [1:0] opcode;
reg clk;
reg rst;
wire [0:6] sseg;
wire [3:0] an;
alu uut (
.portA(portA),
.portB(portB),
.opcode(opcode),
.sseg(sseg),
.an(an),
.clk(clk),
.rst(rst)
);
initial begin
opcode = 0;
clk = 0;
rst = 1;
portA=5;
portB=3;
#10;
rst = 0;
#50 opcode = 0;
#50 opcode = 1;
#50 opcode = 2;
#50 opcode = 3;
end
always #1 clk = ~clk;
endmodule | 4 |
137,685 | data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/scr/sum4bcc/sum4b.v | 79,817,529 | sum4b.v | v | 19 | 35 | [] | [] | [] | [(3, 18)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/79817529/lab/lab06_Unidad_aritmetica/alu/scr/sum4bcc/sum4b.v:14: Signal definition not found, creating implicitly: \'Cout\'\n assign Cout = st[4];\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 299,953 | module | module sum4b(init, xi, yi,co,sal);
input init;
input [3 :0] xi;
input [3 :0] yi;
output co;
output [3 :0] sal;
wire [4:0] st;
assign sal= st[3:0];
assign Cout = st[4];
assign st = xi+yi;
endmodule | module sum4b(init, xi, yi,co,sal); |
input init;
input [3 :0] xi;
input [3 :0] yi;
output co;
output [3 :0] sal;
wire [4:0] st;
assign sal= st[3:0];
assign Cout = st[4];
assign st = xi+yi;
endmodule | 4 |
137,691 | data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp/buffer_ram_dp.v | 79,817,529 | buffer_ram_dp.v | v | 58 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xf3 in position 590: invalid continuation byte | data/verilator_xmls/862ad6b9-ce56-4072-9510-8b22bd4c12e7.xml | null | 299,964 | module | module buffer_ram_dp#(
parameter AW = 15,
parameter DW = 16,
parameter imageFILE= "ramdp/image.men")
(
input clk,
input [AW-1: 0] addr_in,
input [DW-1: 0] data_in,
input regwrite,
output reg [DW-1: 0] data_out,
input [AW-1: 0] addr_out,
input regread
);
localparam NPOS = 2 ** AW;
reg [DW-1: 0] ram [0: NPOS-1];
always @(posedge clk) begin
if (regwrite == 1)
ram[addr_in] <= data_in;
end
always @(posedge clk) begin
if (regread == 1)
data_out <= ram[addr_out];
end
initial begin
$readmemh(imageFILE, ram);
end
endmodule | module buffer_ram_dp#(
parameter AW = 15,
parameter DW = 16,
parameter imageFILE= "ramdp/image.men")
(
input clk,
input [AW-1: 0] addr_in,
input [DW-1: 0] data_in,
input regwrite,
output reg [DW-1: 0] data_out,
input [AW-1: 0] addr_out,
input regread
); |
localparam NPOS = 2 ** AW;
reg [DW-1: 0] ram [0: NPOS-1];
always @(posedge clk) begin
if (regwrite == 1)
ram[addr_in] <= data_in;
end
always @(posedge clk) begin
if (regread == 1)
data_out <= ram[addr_out];
end
initial begin
$readmemh(imageFILE, ram);
end
endmodule | 4 |
137,692 | data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp/TB_ram.v | 79,817,529 | TB_ram.v | v | 66 | 117 | [] | [] | [] | [(25, 64)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp/TB_ram.v:59: Unsupported: Ignoring delay on this delayed statement.\n # 10 regread=1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp/TB_ram.v:63: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk ;\n ^\n%Error: data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp/TB_ram.v:39: Cannot find file containing module: \'buffer_ram_dp\'\n buffer_ram_dp uut (\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp,data/full_repos/permissive/79817529/buffer_ram_dp\n data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp,data/full_repos/permissive/79817529/buffer_ram_dp.v\n data/full_repos/permissive/79817529/lab/P01-01RAM/ramdp,data/full_repos/permissive/79817529/buffer_ram_dp.sv\n buffer_ram_dp\n buffer_ram_dp.v\n buffer_ram_dp.sv\n obj_dir/buffer_ram_dp\n obj_dir/buffer_ram_dp.v\n obj_dir/buffer_ram_dp.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,965 | module | module TB_ram;
reg clk;
reg [14:0] addr_in;
reg [15:0] data_in;
reg regwrite;
reg [14:0] addr_out;
reg regread;
wire [15:0] data_out;
buffer_ram_dp uut (
.clk(clk),
.addr_in(addr_in),
.data_in(data_in),
.regwrite(regwrite),
.data_out(data_out),
.addr_out(addr_out),
.regread(regread)
);
initial begin
clk = 0;
addr_in = 0;
data_in = 0;
regwrite = 0;
addr_out = 0;
regread = 0;
# 10 regread=1;
end
always #1 clk = ~clk ;
endmodule | module TB_ram; |
reg clk;
reg [14:0] addr_in;
reg [15:0] data_in;
reg regwrite;
reg [14:0] addr_out;
reg regread;
wire [15:0] data_out;
buffer_ram_dp uut (
.clk(clk),
.addr_in(addr_in),
.data_in(data_in),
.regwrite(regwrite),
.data_out(data_out),
.addr_out(addr_out),
.regread(regread)
);
initial begin
clk = 0;
addr_in = 0;
data_in = 0;
regwrite = 0;
addr_out = 0;
regread = 0;
# 10 regread=1;
end
always #1 clk = ~clk ;
endmodule | 4 |
137,693 | data/full_repos/permissive/79837113/cpet561/lab1/nios_system/nios_system_bb.v | 79,837,113 | nios_system_bb.v | v | 13 | 30 | [] | [] | [] | [(2, 12)] | null | data/verilator_xmls/7019881d-3954-4379-ba18-05e9103d4563.xml | null | 299,971 | module | module nios_system (
clk_clk,
reset_reset_n,
switches_export,
leds_export);
input clk_clk;
input reset_reset_n;
input [7:0] switches_export;
output [7:0] leds_export;
endmodule | module nios_system (
clk_clk,
reset_reset_n,
switches_export,
leds_export); |
input clk_clk;
input reset_reset_n;
input [7:0] switches_export;
output [7:0] leds_export;
endmodule | 0 |
137,694 | data/full_repos/permissive/79837113/cpet561/lab2/nios_system/nios_system_bb.v | 79,837,113 | nios_system_bb.v | v | 15 | 37 | [] | [] | [] | [(2, 14)] | null | data/verilator_xmls/b2b02113-4d39-4f9d-b1d4-e7117a788574.xml | null | 300,050 | module | module nios_system (
clk_clk,
i_switch_export,
i_trigger_export,
o_accumulator_export,
reset_reset_n);
input clk_clk;
input [7:0] i_switch_export;
input i_trigger_export;
output [15:0] o_accumulator_export;
input reset_reset_n;
endmodule | module nios_system (
clk_clk,
i_switch_export,
i_trigger_export,
o_accumulator_export,
reset_reset_n); |
input clk_clk;
input [7:0] i_switch_export;
input i_trigger_export;
output [15:0] o_accumulator_export;
input reset_reset_n;
endmodule | 0 |
137,695 | data/full_repos/permissive/79837113/cpet561/lab3/part1/quartus/nios_system/nios_system_bb.v | 79,837,113 | nios_system_bb.v | v | 13 | 27 | [] | [] | [] | [(2, 12)] | null | data/verilator_xmls/8fdc2100-4c80-4a74-be4a-917d80dc2dbb.xml | null | 300,129 | module | module nios_system (
clk_clk,
reset_reset_n,
leds_export,
key1_export);
input clk_clk;
input reset_reset_n;
output [7:0] leds_export;
input key1_export;
endmodule | module nios_system (
clk_clk,
reset_reset_n,
leds_export,
key1_export); |
input clk_clk;
input reset_reset_n;
output [7:0] leds_export;
input key1_export;
endmodule | 0 |
137,696 | data/full_repos/permissive/79837113/cpet561/lab3/part2/quartus/nios_system/nios_system_bb.v | 79,837,113 | nios_system_bb.v | v | 13 | 27 | [] | [] | [] | [(2, 12)] | null | data/verilator_xmls/8d4bb621-2e0b-4a82-a56b-c7e83390d6c0.xml | null | 300,207 | module | module nios_system (
clk_clk,
key1_export,
leds_export,
reset_reset_n);
input clk_clk;
input key1_export;
output [7:0] leds_export;
input reset_reset_n;
endmodule | module nios_system (
clk_clk,
key1_export,
leds_export,
reset_reset_n); |
input clk_clk;
input key1_export;
output [7:0] leds_export;
input reset_reset_n;
endmodule | 0 |
137,697 | data/full_repos/permissive/79837113/cpet561/lab4/lab4_quartus/nios_system_bb.v | 79,837,113 | nios_system_bb.v | v | 29 | 38 | [] | [] | [] | [(2, 28)] | null | data/verilator_xmls/c7168f42-3261-4075-9580-06ccefee4e95.xml | null | 300,244 | module | module nios_system (
bus_bridge_acknowledge,
bus_bridge_irq,
bus_bridge_address,
bus_bridge_bus_enable,
bus_bridge_byte_enable,
bus_bridge_rw,
bus_bridge_write_data,
bus_bridge_read_data,
clk_clk,
iicclockbit_export,
iicdatabit_export,
reset_reset_n);
input bus_bridge_acknowledge;
input bus_bridge_irq;
output [10:0] bus_bridge_address;
output bus_bridge_bus_enable;
output [3:0] bus_bridge_byte_enable;
output bus_bridge_rw;
output [31:0] bus_bridge_write_data;
input [31:0] bus_bridge_read_data;
input clk_clk;
output iicclockbit_export;
inout iicdatabit_export;
input reset_reset_n;
endmodule | module nios_system (
bus_bridge_acknowledge,
bus_bridge_irq,
bus_bridge_address,
bus_bridge_bus_enable,
bus_bridge_byte_enable,
bus_bridge_rw,
bus_bridge_write_data,
bus_bridge_read_data,
clk_clk,
iicclockbit_export,
iicdatabit_export,
reset_reset_n); |
input bus_bridge_acknowledge;
input bus_bridge_irq;
output [10:0] bus_bridge_address;
output bus_bridge_bus_enable;
output [3:0] bus_bridge_byte_enable;
output bus_bridge_rw;
output [31:0] bus_bridge_write_data;
input [31:0] bus_bridge_read_data;
input clk_clk;
output iicclockbit_export;
inout iicdatabit_export;
input reset_reset_n;
endmodule | 0 |
137,698 | data/full_repos/permissive/79837113/cpet561/lab5/lab5_files/filter_mult.v | 79,837,113 | filter_mult.v | v | 41 | 63 | [] | [] | [] | [(3, 41)] | null | data/verilator_xmls/f84ee59e-9adf-464e-8a2a-72692860c2d6.xml | null | 300,372 | module | module filter_mult (
dataa,
datab,
result
);
input [35:0] dataa;
input [35:0] datab;
output [71:0] result;
reg [71:0] result_reg;
reg [35:0] dataa_comp;
reg [35:0] datab_comp;
reg [71:0] dataa_ext;
reg [71:0] datab_ext;
reg [1:0] sign;
always @(dataa, datab) begin
if ((dataa[35] == 1'b0) && (datab[35] == 1'b0)) begin
sign = 2'b00;
result_reg = dataa * datab;
end
else if ((dataa[35] == 1'b1) && (datab[35] == 1'b1)) begin
sign = 2'b11;
dataa_comp = (~dataa) + 36'h1;
datab_comp = (~datab) + 36'h1;
result_reg = dataa_comp * datab_comp;
end
else begin
sign = 2'b10;
dataa_ext = {{36{dataa[35]}}, dataa};
datab_ext = {{36{datab[35]}}, datab};
result_reg = dataa_ext * datab_ext;
end
end
assign result = result_reg;
endmodule | module filter_mult (
dataa,
datab,
result
); |
input [35:0] dataa;
input [35:0] datab;
output [71:0] result;
reg [71:0] result_reg;
reg [35:0] dataa_comp;
reg [35:0] datab_comp;
reg [71:0] dataa_ext;
reg [71:0] datab_ext;
reg [1:0] sign;
always @(dataa, datab) begin
if ((dataa[35] == 1'b0) && (datab[35] == 1'b0)) begin
sign = 2'b00;
result_reg = dataa * datab;
end
else if ((dataa[35] == 1'b1) && (datab[35] == 1'b1)) begin
sign = 2'b11;
dataa_comp = (~dataa) + 36'h1;
datab_comp = (~datab) + 36'h1;
result_reg = dataa_comp * datab_comp;
end
else begin
sign = 2'b10;
dataa_ext = {{36{dataa[35]}}, dataa};
datab_ext = {{36{datab[35]}}, datab};
result_reg = dataa_ext * datab_ext;
end
end
assign result = result_reg;
endmodule | 0 |
137,699 | data/full_repos/permissive/79837113/cpet561/lab5/lab5_files/test_filter_tb.v | 79,837,113 | test_filter_tb.v | v | 76 | 72 | [] | [] | [] | null | line:55: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79837113/cpet561/lab5/lab5_files/test_filter_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk_50 = ~clk_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79837113/cpet561/lab5/lab5_files/test_filter_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #2000 reset = 1\'b0;\n ^\n%Error: data/full_repos/permissive/79837113/cpet561/lab5/lab5_files/test_filter_tb.v:58: syntax error, unexpected \'@\'\n @(posedge clk_50);\n ^\n%Error: data/full_repos/permissive/79837113/cpet561/lab5/lab5_files/test_filter_tb.v:64: syntax error, unexpected \'@\'\n @(posedge clk_50);\n ^\n%Error: data/full_repos/permissive/79837113/cpet561/lab5/lab5_files/test_filter_tb.v:67: syntax error, unexpected \'@\'\n @(posedge clk_50);\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,373 | module | module test_filter_tb ();
wire signed [31:0] audioSample_w;
wire signed [31:0] audioSampleFiltered_w;
reg clk_50;
reg reset;
reg dataReq;
reg signed [15:0] audioSampleArray[39:0];
reg signed [15:0] audioSample;
reg signed [15:0] audioSampleFiltered;
integer fileIn, fileOut, status, i;
audio_filter audio_filter_inst (
.i_clk_50(clk_50),
.i_reset(reset),
.i_audioSample(audioSample_w),
.i_dataReq(dataReq),
.i_filterReset(1'b0),
.o_audioSampleFiltered(audioSampleFiltered_w)
);
assign audioSample_w = {audioSample, audioSample};
always #10 clk_50 = ~clk_50;
initial begin
clk_50 = 1'b0;
reset = 1'b1;
dataReq = 1'b0;
#2000 reset = 1'b0;
end
initial begin
fileIn = $fopen("one_cycle_200_8k.csv", "r");
fileOut = $fopen("filter_out.csv", "w");
for (i=0; i<40; i=i+1) begin
status = $fscanf(fileIn, "%h\n", audioSampleArray[i]);
end
$fclose(fileIn);
repeat (100) begin
for (i=0; i<40; i=i+1) begin
repeat (1100) begin
@(posedge clk_50);
end
audioSample = audioSampleArray[i];
audioSampleFiltered = audioSampleFiltered_w[15:0];
$fwrite(fileOut, "%d\n", ($signed(audioSampleFiltered)));
repeat (2) begin
@(posedge clk_50);
end
dataReq = 1'b1;
@(posedge clk_50);
dataReq = 1'b0;
end
end
$fclose(fileIn);
$stop;
end
endmodule | module test_filter_tb (); |
wire signed [31:0] audioSample_w;
wire signed [31:0] audioSampleFiltered_w;
reg clk_50;
reg reset;
reg dataReq;
reg signed [15:0] audioSampleArray[39:0];
reg signed [15:0] audioSample;
reg signed [15:0] audioSampleFiltered;
integer fileIn, fileOut, status, i;
audio_filter audio_filter_inst (
.i_clk_50(clk_50),
.i_reset(reset),
.i_audioSample(audioSample_w),
.i_dataReq(dataReq),
.i_filterReset(1'b0),
.o_audioSampleFiltered(audioSampleFiltered_w)
);
assign audioSample_w = {audioSample, audioSample};
always #10 clk_50 = ~clk_50;
initial begin
clk_50 = 1'b0;
reset = 1'b1;
dataReq = 1'b0;
#2000 reset = 1'b0;
end
initial begin
fileIn = $fopen("one_cycle_200_8k.csv", "r");
fileOut = $fopen("filter_out.csv", "w");
for (i=0; i<40; i=i+1) begin
status = $fscanf(fileIn, "%h\n", audioSampleArray[i]);
end
$fclose(fileIn);
repeat (100) begin
for (i=0; i<40; i=i+1) begin
repeat (1100) begin
@(posedge clk_50);
end
audioSample = audioSampleArray[i];
audioSampleFiltered = audioSampleFiltered_w[15:0];
$fwrite(fileOut, "%d\n", ($signed(audioSampleFiltered)));
repeat (2) begin
@(posedge clk_50);
end
dataReq = 1'b1;
@(posedge clk_50);
dataReq = 1'b0;
end
end
$fclose(fileIn);
$stop;
end
endmodule | 0 |
137,700 | data/full_repos/permissive/79837113/cpet561/lab6/codec_adc_interface.v | 79,837,113 | codec_adc_interface.v | v | 64 | 72 | [] | [] | [] | [(10, 64)] | null | data/verilator_xmls/2e754df0-2086-4f21-bb6a-1ef597679ce0.xml | null | 300,374 | module | module codec_adc_interface (i_clk_50,
i_AUD_ADCDAT,
i_adclrckFallingEdge,
i_adclrckRisingEdge,
i_bclkRisingEdge,
o_audioSampleADC,
o_dataReady );
input i_clk_50;
input i_AUD_ADCDAT;
input i_adclrckFallingEdge;
input i_adclrckRisingEdge;
input i_bclkRisingEdge;
output [31:0] o_audioSampleADC;
output o_dataReady;
reg [15:0] shiftRegRight;
reg [15:0] shiftRegLeft;
reg dataReady;
reg [4:0] acquireLeft;
reg [4:0] acquireRight;
assign o_audioSampleADC = {shiftRegLeft, shiftRegRight};
assign o_dataReady = dataReady;
always @(posedge i_clk_50) begin
if (i_adclrckFallingEdge) begin
acquireLeft <= 5'd17;
dataReady <= 1'b1;
end
else if (i_adclrckRisingEdge) begin
acquireRight <= 5'd17;
end
else if ((acquireLeft != 5'd0) && i_bclkRisingEdge) begin
acquireLeft <= acquireLeft - 5'd1;
shiftRegLeft[0] <= i_AUD_ADCDAT;
shiftRegLeft[15:1] <= shiftRegLeft[14:0];
end
else if ((acquireRight != 5'd0) && i_bclkRisingEdge) begin
acquireRight <= acquireRight - 5'd1;
shiftRegRight[0] <= i_AUD_ADCDAT;
shiftRegRight[15:1] <= shiftRegRight[14:0];
end
else begin
dataReady <= 1'b0;
end
end
endmodule | module codec_adc_interface (i_clk_50,
i_AUD_ADCDAT,
i_adclrckFallingEdge,
i_adclrckRisingEdge,
i_bclkRisingEdge,
o_audioSampleADC,
o_dataReady ); |
input i_clk_50;
input i_AUD_ADCDAT;
input i_adclrckFallingEdge;
input i_adclrckRisingEdge;
input i_bclkRisingEdge;
output [31:0] o_audioSampleADC;
output o_dataReady;
reg [15:0] shiftRegRight;
reg [15:0] shiftRegLeft;
reg dataReady;
reg [4:0] acquireLeft;
reg [4:0] acquireRight;
assign o_audioSampleADC = {shiftRegLeft, shiftRegRight};
assign o_dataReady = dataReady;
always @(posedge i_clk_50) begin
if (i_adclrckFallingEdge) begin
acquireLeft <= 5'd17;
dataReady <= 1'b1;
end
else if (i_adclrckRisingEdge) begin
acquireRight <= 5'd17;
end
else if ((acquireLeft != 5'd0) && i_bclkRisingEdge) begin
acquireLeft <= acquireLeft - 5'd1;
shiftRegLeft[0] <= i_AUD_ADCDAT;
shiftRegLeft[15:1] <= shiftRegLeft[14:0];
end
else if ((acquireRight != 5'd0) && i_bclkRisingEdge) begin
acquireRight <= acquireRight - 5'd1;
shiftRegRight[0] <= i_AUD_ADCDAT;
shiftRegRight[15:1] <= shiftRegRight[14:0];
end
else begin
dataReady <= 1'b0;
end
end
endmodule | 0 |
137,701 | data/full_repos/permissive/79837113/cpet561/lab6/codec_dac_interface.v | 79,837,113 | codec_dac_interface.v | v | 68 | 72 | [] | [] | [] | [(10, 68)] | null | data/verilator_xmls/b0176633-0bb5-4355-8e55-fc20e6040f01.xml | null | 300,375 | module | module codec_dac_interface (i_clk_50,
i_audioSample,
i_daclrckFallingEdge,
i_daclrckRisingEdge,
i_bclkRisingEdge,
o_dataReq,
o_AUD_DACDAT);
input i_clk_50;
input [31:0] i_audioSample;
input i_daclrckFallingEdge;
input i_daclrckRisingEdge;
input i_bclkRisingEdge;
output o_dataReq;
output o_AUD_DACDAT;
reg [16:0] shiftReg;
reg AUD_BCLK_d1;
reg AUD_BCLK_d2;
reg AUD_BCLK_d3;
reg AUD_BCLK_d4;
reg AUD_DACLRCK_d1;
reg AUD_DACLRCK_d2;
reg AUD_DACLRCK_d3;
reg AUD_DACLRCK_d4;
reg dataReq;
reg latchAudioSample;
assign o_AUD_DACDAT = shiftReg[16];
assign o_dataReq = dataReq;
always @(posedge i_clk_50) begin
if (i_daclrckFallingEdge) begin
dataReq <= 1'b1;
end
else if (dataReq == 1'b1) begin
latchAudioSample = 1'b1;
dataReq <= 1'b0;
end
else if (latchAudioSample == 1'b1) begin
latchAudioSample = 1'b0;
shiftReg[15:0] <= i_audioSample[31:16];
end
else if (i_daclrckRisingEdge) begin
shiftReg[15:0] <= i_audioSample[15:0];
end
else if (i_bclkRisingEdge) begin
shiftReg[16:1] <= shiftReg[15:0];
shiftReg[0] <= 1'b0;
end
end
endmodule | module codec_dac_interface (i_clk_50,
i_audioSample,
i_daclrckFallingEdge,
i_daclrckRisingEdge,
i_bclkRisingEdge,
o_dataReq,
o_AUD_DACDAT); |
input i_clk_50;
input [31:0] i_audioSample;
input i_daclrckFallingEdge;
input i_daclrckRisingEdge;
input i_bclkRisingEdge;
output o_dataReq;
output o_AUD_DACDAT;
reg [16:0] shiftReg;
reg AUD_BCLK_d1;
reg AUD_BCLK_d2;
reg AUD_BCLK_d3;
reg AUD_BCLK_d4;
reg AUD_DACLRCK_d1;
reg AUD_DACLRCK_d2;
reg AUD_DACLRCK_d3;
reg AUD_DACLRCK_d4;
reg dataReq;
reg latchAudioSample;
assign o_AUD_DACDAT = shiftReg[16];
assign o_dataReq = dataReq;
always @(posedge i_clk_50) begin
if (i_daclrckFallingEdge) begin
dataReq <= 1'b1;
end
else if (dataReq == 1'b1) begin
latchAudioSample = 1'b1;
dataReq <= 1'b0;
end
else if (latchAudioSample == 1'b1) begin
latchAudioSample = 1'b0;
shiftReg[15:0] <= i_audioSample[31:16];
end
else if (i_daclrckRisingEdge) begin
shiftReg[15:0] <= i_audioSample[15:0];
end
else if (i_bclkRisingEdge) begin
shiftReg[16:1] <= shiftReg[15:0];
shiftReg[0] <= 1'b0;
end
end
endmodule | 0 |
137,702 | data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test/DE1_SoC_SDRAM_RTL_Test.v | 79,837,113 | DE1_SoC_SDRAM_RTL_Test.v | v | 310 | 80 | [] | [] | [] | [(36, 309)] | null | null | 1: b'%Error: data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test/DE1_SoC_SDRAM_RTL_Test.v:211: Cannot find file containing module: \'pll\'\npll u0(\n^~~\n ... Looked in:\n data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test,data/full_repos/permissive/79837113/pll\n data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test,data/full_repos/permissive/79837113/pll.v\n data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test,data/full_repos/permissive/79837113/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test/DE1_SoC_SDRAM_RTL_Test.v:220: Cannot find file containing module: \'Sdram_Control\'\nSdram_Control u1 ( \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test/DE1_SoC_SDRAM_RTL_Test.v:260: Cannot find file containing module: \'RW_Test\'\n RW_Test u2(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test/DE1_SoC_SDRAM_RTL_Test.v:301: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'test_result\' generates 3 bits.\n : ... In instance DE1_SoC_SDRAM_RTL_Test\nassign LEDR[2:0] = KEY[0]?test_result:4\'b1111;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/79837113/cpet561/lab6/DE1_SoC_SDRAM_RTL_Test/DE1_SoC_SDRAM_RTL_Test.v:301: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n : ... In instance DE1_SoC_SDRAM_RTL_Test\nassign LEDR[2:0] = KEY[0]?test_result:4\'b1111;\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 300,376 | module | module DE1_SoC_SDRAM_RTL_Test(
inout ADC_CS_N,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
output FAN_CTRL,
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
input IRDA_RXD,
output IRDA_TXD,
input [3:0] KEY,
output [9:0] LEDR,
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
input [9:0] SW,
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
wire [15:0] writedata;
wire [15:0] readdata;
wire write;
wire read;
wire clk_test;
pll u0(
.refclk( CLOCK_50),
.rst(1'b0),
.outclk_0(clk_test),
.outclk_1(),
.locked()
);
Sdram_Control u1 (
.REF_CLK(CLOCK_50),
.RESET_N(test_software_reset_n),
.WR_DATA(writedata),
.WR(write),
.WR_ADDR(0),
.WR_MAX_ADDR(25'h1ffffff),
.WR_LENGTH(9'h80),
.WR_LOAD(!test_global_reset_n ),
.WR_CLK(clk_test),
.RD_DATA(readdata),
.RD(read),
.RD_ADDR(0),
.RD_MAX_ADDR(25'h1ffffff),
.RD_LENGTH(9'h80),
.RD_LOAD(!test_global_reset_n ),
.RD_CLK(clk_test),
.SA(DRAM_ADDR),
.BA(DRAM_BA),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
wire test_software_reset_n;
wire test_global_reset_n;
wire test_start_n;
wire sdram_test_pass;
wire sdram_test_fail;
wire sdram_test_complete;
RW_Test u2(
.iCLK(clk_test),
.iRST_n(test_software_reset_n),
.iBUTTON(test_start_n),
.write(write),
.writedata(writedata),
.read(read),
.readdata(readdata),
.drv_status_pass(sdram_test_pass),
.drv_status_fail(sdram_test_fail),
.drv_status_test_complete(sdram_test_complete)
);
reg [31:0] cont;
always@(posedge CLOCK_50)
cont<=(cont==32'd4_000_001)?32'd0:cont+1'b1;
reg[4:0] sample;
always@(posedge CLOCK_50)
begin
if(cont==32'd4_000_000)
sample[4:0]={sample[3:0],KEY[0]};
else
sample[4:0]=sample[4:0];
end
assign test_software_reset_n=(sample[1:0]==2'b10)?1'b0:1'b1;
assign test_global_reset_n =(sample[3:2]==2'b10)?1'b0:1'b1;
assign test_start_n =(sample[4:3]==2'b01)?1'b0:1'b1;
wire [2:0] test_result;
assign test_result[0] = KEY[0];
assign test_result[1] = sdram_test_complete? sdram_test_pass : heart_beat[23];
assign test_result[2] = heart_beat[23];
assign LEDR[2:0] = KEY[0]?test_result:4'b1111;
reg [23:0] heart_beat;
always @ (posedge CLOCK_50)
begin
heart_beat <= heart_beat + 1;
end
endmodule | module DE1_SoC_SDRAM_RTL_Test(
inout ADC_CS_N,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
output FAN_CTRL,
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
input IRDA_RXD,
output IRDA_TXD,
input [3:0] KEY,
output [9:0] LEDR,
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
input [9:0] SW,
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
); |
wire [15:0] writedata;
wire [15:0] readdata;
wire write;
wire read;
wire clk_test;
pll u0(
.refclk( CLOCK_50),
.rst(1'b0),
.outclk_0(clk_test),
.outclk_1(),
.locked()
);
Sdram_Control u1 (
.REF_CLK(CLOCK_50),
.RESET_N(test_software_reset_n),
.WR_DATA(writedata),
.WR(write),
.WR_ADDR(0),
.WR_MAX_ADDR(25'h1ffffff),
.WR_LENGTH(9'h80),
.WR_LOAD(!test_global_reset_n ),
.WR_CLK(clk_test),
.RD_DATA(readdata),
.RD(read),
.RD_ADDR(0),
.RD_MAX_ADDR(25'h1ffffff),
.RD_LENGTH(9'h80),
.RD_LOAD(!test_global_reset_n ),
.RD_CLK(clk_test),
.SA(DRAM_ADDR),
.BA(DRAM_BA),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
wire test_software_reset_n;
wire test_global_reset_n;
wire test_start_n;
wire sdram_test_pass;
wire sdram_test_fail;
wire sdram_test_complete;
RW_Test u2(
.iCLK(clk_test),
.iRST_n(test_software_reset_n),
.iBUTTON(test_start_n),
.write(write),
.writedata(writedata),
.read(read),
.readdata(readdata),
.drv_status_pass(sdram_test_pass),
.drv_status_fail(sdram_test_fail),
.drv_status_test_complete(sdram_test_complete)
);
reg [31:0] cont;
always@(posedge CLOCK_50)
cont<=(cont==32'd4_000_001)?32'd0:cont+1'b1;
reg[4:0] sample;
always@(posedge CLOCK_50)
begin
if(cont==32'd4_000_000)
sample[4:0]={sample[3:0],KEY[0]};
else
sample[4:0]=sample[4:0];
end
assign test_software_reset_n=(sample[1:0]==2'b10)?1'b0:1'b1;
assign test_global_reset_n =(sample[3:2]==2'b10)?1'b0:1'b1;
assign test_start_n =(sample[4:3]==2'b01)?1'b0:1'b1;
wire [2:0] test_result;
assign test_result[0] = KEY[0];
assign test_result[1] = sdram_test_complete? sdram_test_pass : heart_beat[23];
assign test_result[2] = heart_beat[23];
assign LEDR[2:0] = KEY[0]?test_result:4'b1111;
reg [23:0] heart_beat;
always @ (posedge CLOCK_50)
begin
heart_beat <= heart_beat + 1;
end
endmodule | 0 |
137,703 | data/full_repos/permissive/79837113/cpet561/pipeline_ex/not_pipelined/quartus/lab4_quartus/nios_sytem/nios_sytem_bb.v | 79,837,113 | nios_sytem_bb.v | v | 33 | 42 | [] | [] | [] | [(2, 32)] | null | data/verilator_xmls/ec6fc81f-a07b-4b99-addd-320484c99a44.xml | null | 300,393 | module | module nios_sytem (
bus_bridge_acknowledge,
bus_bridge_irq,
bus_bridge_address,
bus_bridge_bus_enable,
bus_bridge_byte_enable,
bus_bridge_rw,
bus_bridge_write_data,
bus_bridge_read_data,
clk_clk,
eight_bit_input_export,
reset_reset_n,
sixteen_bit_output_export,
iicdatabit_export,
iicclockbit_export);
input bus_bridge_acknowledge;
input bus_bridge_irq;
output [10:0] bus_bridge_address;
output bus_bridge_bus_enable;
output [3:0] bus_bridge_byte_enable;
output bus_bridge_rw;
output [31:0] bus_bridge_write_data;
input [31:0] bus_bridge_read_data;
input clk_clk;
input [7:0] eight_bit_input_export;
input reset_reset_n;
output [15:0] sixteen_bit_output_export;
inout iicdatabit_export;
output iicclockbit_export;
endmodule | module nios_sytem (
bus_bridge_acknowledge,
bus_bridge_irq,
bus_bridge_address,
bus_bridge_bus_enable,
bus_bridge_byte_enable,
bus_bridge_rw,
bus_bridge_write_data,
bus_bridge_read_data,
clk_clk,
eight_bit_input_export,
reset_reset_n,
sixteen_bit_output_export,
iicdatabit_export,
iicclockbit_export); |
input bus_bridge_acknowledge;
input bus_bridge_irq;
output [10:0] bus_bridge_address;
output bus_bridge_bus_enable;
output [3:0] bus_bridge_byte_enable;
output bus_bridge_rw;
output [31:0] bus_bridge_write_data;
input [31:0] bus_bridge_read_data;
input clk_clk;
input [7:0] eight_bit_input_export;
input reset_reset_n;
output [15:0] sixteen_bit_output_export;
inout iicdatabit_export;
output iicclockbit_export;
endmodule | 0 |
137,704 | data/full_repos/permissive/79951855/src/arithmetic_logic_unit.v | 79,951,855 | arithmetic_logic_unit.v | v | 32 | 98 | [] | [] | [] | [(1, 30)] | null | data/verilator_xmls/451fbe79-1b15-4e02-b6ec-2782f68e37ca.xml | null | 300,433 | module | module arithmetic_logic_unit(input [15:0] x,
input [15:0] y,
input zx,
input nx,
input zy,
input ny,
input f,
input no,
output [15:0] out,
output zr,
output ng);
wire [15:0] x_stage1 = {16{~zx}} & x;
wire [15:0] y_stage1 = {16{~zy}} & y;
wire [15:0] x_stage2 = ({16{nx}} & ~x_stage1) | ({16{~nx}} & x_stage1);
wire [15:0] y_stage2 = ({16{ny}} & ~y_stage1) | ({16{~ny}} & y_stage1);
wire [15:0] f_output = ({16{f}} & (x_stage2 + y_stage2)) | ({16{~f}} & (x_stage2 & y_stage2));
wire [15:0] out_stage1 = ({16{no}} & ~f_output) | ({16{~no}} & f_output);
assign out = out_stage1;
assign zr = ~|out_stage1;
assign ng = out_stage1[15];
endmodule | module arithmetic_logic_unit(input [15:0] x,
input [15:0] y,
input zx,
input nx,
input zy,
input ny,
input f,
input no,
output [15:0] out,
output zr,
output ng); |
wire [15:0] x_stage1 = {16{~zx}} & x;
wire [15:0] y_stage1 = {16{~zy}} & y;
wire [15:0] x_stage2 = ({16{nx}} & ~x_stage1) | ({16{~nx}} & x_stage1);
wire [15:0] y_stage2 = ({16{ny}} & ~y_stage1) | ({16{~ny}} & y_stage1);
wire [15:0] f_output = ({16{f}} & (x_stage2 + y_stage2)) | ({16{~f}} & (x_stage2 & y_stage2));
wire [15:0] out_stage1 = ({16{no}} & ~f_output) | ({16{~no}} & f_output);
assign out = out_stage1;
assign zr = ~|out_stage1;
assign ng = out_stage1[15];
endmodule | 1 |
137,708 | data/full_repos/permissive/79951855/src/tests/program_counter_test.v | 79,951,855 | program_counter_test.v | v | 66 | 55 | [] | [] | [] | null | line:21: before: ";" | null | 1: b'%Error: data/full_repos/permissive/79951855/src/tests/program_counter_test.v:13: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79951855/src/tests/program_counter_test.v:14: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/program_counter_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/program_counter_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/program_counter_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("out: %4h", out);\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,444 | module | module program_counter_test;
reg clk;
reg rst;
reg load;
reg inc;
reg [14:0] in;
wire [14:0] out;
program_counter pc1(clk, rst, inc, load, in, out);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
$display("Reset the counter");
clk=0;
rst=1;
#1;
clk=1;
display;
$display("Set in to 0x2bcd");
in=15'h2bcd;
rst=0;
clk=0;
#1;
clk=1;
display;
$display("Set the load bit");
load = 1;
clk=0;
clk=1;
display;
$display("Unset the load bit");
load = 0;
clk=0;
clk=1;
display;
$display("Set the inc bit");
inc = 1;
clk=0;
clk=1;
display;
$display("Cycle the clock again");
clk=0;
clk=1;
display;
$display("Set the rst bit");
rst = 1;
clk=0;
clk=1;
display;
end
task display;
#1 $display("out: %4h", out);
endtask
endmodule | module program_counter_test; |
reg clk;
reg rst;
reg load;
reg inc;
reg [14:0] in;
wire [14:0] out;
program_counter pc1(clk, rst, inc, load, in, out);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
$display("Reset the counter");
clk=0;
rst=1;
#1;
clk=1;
display;
$display("Set in to 0x2bcd");
in=15'h2bcd;
rst=0;
clk=0;
#1;
clk=1;
display;
$display("Set the load bit");
load = 1;
clk=0;
clk=1;
display;
$display("Unset the load bit");
load = 0;
clk=0;
clk=1;
display;
$display("Set the inc bit");
inc = 1;
clk=0;
clk=1;
display;
$display("Cycle the clock again");
clk=0;
clk=1;
display;
$display("Set the rst bit");
rst = 1;
clk=0;
clk=1;
display;
end
task display;
#1 $display("out: %4h", out);
endtask
endmodule | 1 |
137,709 | data/full_repos/permissive/79951855/src/tests/ram16_test.v | 79,951,855 | ram16_test.v | v | 56 | 64 | [] | [] | [] | null | line:22: before: ";" | null | 1: b'%Error: data/full_repos/permissive/79951855/src/tests/ram16_test.v:12: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79951855/src/tests/ram16_test.v:13: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/ram16_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/ram16_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/ram16_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/ram16_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/ram16_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79951855/src/tests/ram16_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("out: %4h\\n", out);\n ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,445 | module | module ram16_test;
reg [3:0] address;
reg [15:0] in;
reg load;
wire [15:0] out;
reg clk;
ram16 theRam(.address(address), .in(in), .load(load),
.clk(clk), .out(out));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
$display("Set register 0 to abcd and read it...");
clk = 0;
in = 16'habcd;
address = 4'h0;
load = 1;
#1;
clk=1;
display;
$display("Wait a cycle and see what it reads...");
#1;
clk=0;
load=0;
#1;
clk=1;
display;
$display("Set register d to 0110 and read from it...");
in=16'h0110;
address=4'hd;
load=1;
clk=0;
#1;
clk=1;
display;
$display("Now read from register 0...");
load=0;
address=4'h0;
clk=0;
#1;
clk=1;
display;
end
task display;
#1 $display("out: %4h\n", out);
endtask
endmodule | module ram16_test; |
reg [3:0] address;
reg [15:0] in;
reg load;
wire [15:0] out;
reg clk;
ram16 theRam(.address(address), .in(in), .load(load),
.clk(clk), .out(out));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
$display("Set register 0 to abcd and read it...");
clk = 0;
in = 16'habcd;
address = 4'h0;
load = 1;
#1;
clk=1;
display;
$display("Wait a cycle and see what it reads...");
#1;
clk=0;
load=0;
#1;
clk=1;
display;
$display("Set register d to 0110 and read from it...");
in=16'h0110;
address=4'hd;
load=1;
clk=0;
#1;
clk=1;
display;
$display("Now read from register 0...");
load=0;
address=4'h0;
clk=0;
#1;
clk=1;
display;
end
task display;
#1 $display("out: %4h\n", out);
endtask
endmodule | 1 |
137,716 | data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v | 79,992,736 | ALU_Cell_1bit.v | v | 127 | 80 | [] | [] | [] | [(19, 126)] | null | null | 1: b"%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:57: Cannot find file containing module: 'Mux_4_to_1'\nMux_4_to_1 b2v_inst(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1.v\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1.sv\n Mux_4_to_1\n Mux_4_to_1.v\n Mux_4_to_1.sv\n obj_dir/Mux_4_to_1\n obj_dir/Mux_4_to_1.v\n obj_dir/Mux_4_to_1.sv\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:66: Cannot find file containing module: 'Mux_2_to_1'\nMux_2_to_1 b2v_inst11(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:73: Cannot find file containing module: 'Mux_2_to_1'\nMux_2_to_1 b2v_inst13(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:80: Cannot find file containing module: 'Mux_2_to_1'\nMux_2_to_1 b2v_inst14(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:87: Cannot find file containing module: 'Mux_2_to_1'\nMux_2_to_1 b2v_inst2(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:96: Cannot find file containing module: 'Mux_4_to_1'\nMux_4_to_1 b2v_inst4(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:109: Cannot find file containing module: 'Mux_2_to_1'\nMux_2_to_1 b2v_inst8(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_1bit.v:116: Cannot find file containing module: 'Full_adder'\nFull_adder b2v_inst9(\n^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 300,452 | module | module ALU_Cell_1bit(
A,
B,
A_from_next_bit,
C_in,
FS,
F,
C_out
);
input wire A;
input wire B;
input wire A_from_next_bit;
input wire C_in;
input wire [4:0] FS;
output wire F;
output wire C_out;
wire [1:0] logic_S;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_6 = 0;
assign SYNTHESIZED_WIRE_7 = 1;
Mux_4_to_1 b2v_inst(
.I1(FS[0]),
.I2(FS[1]),
.I3(FS[2]),
.I4(FS[3]),
.S(logic_S),
.OUT(SYNTHESIZED_WIRE_2));
Mux_2_to_1 b2v_inst11(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_0),
.I2(SYNTHESIZED_WIRE_1),
.OUT(SYNTHESIZED_WIRE_3));
Mux_2_to_1 b2v_inst13(
.S(FS[4]),
.I1(SYNTHESIZED_WIRE_2),
.I2(SYNTHESIZED_WIRE_3),
.OUT(F));
Mux_2_to_1 b2v_inst14(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_4),
.I2(logic_S[1]),
.OUT(C_out));
Mux_2_to_1 b2v_inst2(
.S(FS[0]),
.I1(logic_S[1]),
.I2(SYNTHESIZED_WIRE_5),
.OUT(SYNTHESIZED_WIRE_9));
assign SYNTHESIZED_WIRE_5 = ~logic_S[1];
Mux_4_to_1 b2v_inst4(
.I1(SYNTHESIZED_WIRE_6),
.I2(SYNTHESIZED_WIRE_7),
.I3(logic_S[0]),
.I4(SYNTHESIZED_WIRE_8),
.S(FS[2:1]),
.OUT(SYNTHESIZED_WIRE_10));
assign SYNTHESIZED_WIRE_8 = ~logic_S[0];
Mux_2_to_1 b2v_inst8(
.S(FS[0]),
.I1(C_in),
.I2(A_from_next_bit),
.OUT(SYNTHESIZED_WIRE_1));
Full_adder b2v_inst9(
.B(SYNTHESIZED_WIRE_9),
.A(SYNTHESIZED_WIRE_10),
.C_in(C_in),
.S(SYNTHESIZED_WIRE_0),
.C_out(SYNTHESIZED_WIRE_4));
assign logic_S[0] = B;
assign logic_S[1] = A;
endmodule | module ALU_Cell_1bit(
A,
B,
A_from_next_bit,
C_in,
FS,
F,
C_out
); |
input wire A;
input wire B;
input wire A_from_next_bit;
input wire C_in;
input wire [4:0] FS;
output wire F;
output wire C_out;
wire [1:0] logic_S;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_6 = 0;
assign SYNTHESIZED_WIRE_7 = 1;
Mux_4_to_1 b2v_inst(
.I1(FS[0]),
.I2(FS[1]),
.I3(FS[2]),
.I4(FS[3]),
.S(logic_S),
.OUT(SYNTHESIZED_WIRE_2));
Mux_2_to_1 b2v_inst11(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_0),
.I2(SYNTHESIZED_WIRE_1),
.OUT(SYNTHESIZED_WIRE_3));
Mux_2_to_1 b2v_inst13(
.S(FS[4]),
.I1(SYNTHESIZED_WIRE_2),
.I2(SYNTHESIZED_WIRE_3),
.OUT(F));
Mux_2_to_1 b2v_inst14(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_4),
.I2(logic_S[1]),
.OUT(C_out));
Mux_2_to_1 b2v_inst2(
.S(FS[0]),
.I1(logic_S[1]),
.I2(SYNTHESIZED_WIRE_5),
.OUT(SYNTHESIZED_WIRE_9));
assign SYNTHESIZED_WIRE_5 = ~logic_S[1];
Mux_4_to_1 b2v_inst4(
.I1(SYNTHESIZED_WIRE_6),
.I2(SYNTHESIZED_WIRE_7),
.I3(logic_S[0]),
.I4(SYNTHESIZED_WIRE_8),
.S(FS[2:1]),
.OUT(SYNTHESIZED_WIRE_10));
assign SYNTHESIZED_WIRE_8 = ~logic_S[0];
Mux_2_to_1 b2v_inst8(
.S(FS[0]),
.I1(C_in),
.I2(A_from_next_bit),
.OUT(SYNTHESIZED_WIRE_1));
Full_adder b2v_inst9(
.B(SYNTHESIZED_WIRE_9),
.A(SYNTHESIZED_WIRE_10),
.C_in(C_in),
.S(SYNTHESIZED_WIRE_0),
.C_out(SYNTHESIZED_WIRE_4));
assign logic_S[0] = B;
assign logic_S[1] = A;
endmodule | 2 |
137,717 | data/full_repos/permissive/79992736/src/ALU_Cell_4bit.v | 79,992,736 | ALU_Cell_4bit.v | v | 89 | 80 | [] | [] | [] | [(19, 88)] | null | null | 1: b"%Error: data/full_repos/permissive/79992736/src/ALU_Cell_4bit.v:47: Cannot find file containing module: 'ALU_Cell_1bit'\nALU_Cell_1bit b2v_inst(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/ALU_Cell_1bit\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/ALU_Cell_1bit.v\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/ALU_Cell_1bit.sv\n ALU_Cell_1bit\n ALU_Cell_1bit.v\n ALU_Cell_1bit.sv\n obj_dir/ALU_Cell_1bit\n obj_dir/ALU_Cell_1bit.v\n obj_dir/ALU_Cell_1bit.sv\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_4bit.v:57: Cannot find file containing module: 'ALU_Cell_1bit'\nALU_Cell_1bit b2v_inst1(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_4bit.v:67: Cannot find file containing module: 'ALU_Cell_1bit'\nALU_Cell_1bit b2v_inst4(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/ALU_Cell_4bit.v:77: Cannot find file containing module: 'ALU_Cell_1bit'\nALU_Cell_1bit b2v_inst5(\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 300,453 | module | module ALU_Cell_4bit(
A_from_next_bit,
C_in,
A,
B,
FS,
C_out,
F
);
input wire A_from_next_bit;
input wire C_in;
input wire [3:0] A;
input wire [3:0] B;
input wire [4:0] FS;
output wire C_out;
output wire [3:0] F;
wire [3:0] F_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
ALU_Cell_1bit b2v_inst(
.A(A[3]),
.B(B[3]),
.C_in(SYNTHESIZED_WIRE_0),
.A_from_next_bit(A_from_next_bit),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[3]),
.C_out(C_out));
ALU_Cell_1bit b2v_inst1(
.A(A[1]),
.B(B[1]),
.C_in(SYNTHESIZED_WIRE_1),
.A_from_next_bit(A[2]),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[1]),
.C_out(SYNTHESIZED_WIRE_2));
ALU_Cell_1bit b2v_inst4(
.A(A[2]),
.B(B[2]),
.C_in(SYNTHESIZED_WIRE_2),
.A_from_next_bit(A[3]),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[2]),
.C_out(SYNTHESIZED_WIRE_0));
ALU_Cell_1bit b2v_inst5(
.A(A[0]),
.B(B[0]),
.C_in(C_in),
.A_from_next_bit(A[1]),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[0]),
.C_out(SYNTHESIZED_WIRE_1));
assign F = F_ALTERA_SYNTHESIZED;
endmodule | module ALU_Cell_4bit(
A_from_next_bit,
C_in,
A,
B,
FS,
C_out,
F
); |
input wire A_from_next_bit;
input wire C_in;
input wire [3:0] A;
input wire [3:0] B;
input wire [4:0] FS;
output wire C_out;
output wire [3:0] F;
wire [3:0] F_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
ALU_Cell_1bit b2v_inst(
.A(A[3]),
.B(B[3]),
.C_in(SYNTHESIZED_WIRE_0),
.A_from_next_bit(A_from_next_bit),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[3]),
.C_out(C_out));
ALU_Cell_1bit b2v_inst1(
.A(A[1]),
.B(B[1]),
.C_in(SYNTHESIZED_WIRE_1),
.A_from_next_bit(A[2]),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[1]),
.C_out(SYNTHESIZED_WIRE_2));
ALU_Cell_1bit b2v_inst4(
.A(A[2]),
.B(B[2]),
.C_in(SYNTHESIZED_WIRE_2),
.A_from_next_bit(A[3]),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[2]),
.C_out(SYNTHESIZED_WIRE_0));
ALU_Cell_1bit b2v_inst5(
.A(A[0]),
.B(B[0]),
.C_in(C_in),
.A_from_next_bit(A[1]),
.FS(FS),
.F(F_ALTERA_SYNTHESIZED[0]),
.C_out(SYNTHESIZED_WIRE_1));
assign F = F_ALTERA_SYNTHESIZED;
endmodule | 2 |
137,718 | data/full_repos/permissive/79992736/src/Arith_SR_16bit.v | 79,992,736 | Arith_SR_16bit.v | v | 11 | 29 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/1c15a888-7b37-4ec1-b704-9e97a1c7d649.xml | null | 300,454 | module | module Arith_SR_16bit(F, A);
input signed[15:0] A;
output reg signed[15:0] F;
always @(A)
begin
F = A >>> 1;
end
endmodule | module Arith_SR_16bit(F, A); |
input signed[15:0] A;
output reg signed[15:0] F;
always @(A)
begin
F = A >>> 1;
end
endmodule | 2 |
137,719 | data/full_repos/permissive/79992736/src/Bit_OP_16bit.v | 79,992,736 | Bit_OP_16bit.v | v | 64 | 51 | [] | [] | [] | [(1, 62)] | null | data/verilator_xmls/c9f0f19f-821e-4381-910b-267c1186c02b.xml | null | 300,455 | module | module Bit_OP_16bit(F, A, BS, S);
input[15:0] A;
input[3:0] BS;
input S;
output reg[15:0] F;
always @(A) begin
case (BS[3:0])
4'b0000: begin F = {A[15:1],S};
end
4'b0001: begin F = {A[15:2],S,A[0]};
end
4'b0010: begin F = {A[15:3],S,A[1:0]};
end
4'b0011: begin F = {A[15:4],S,A[2:0]};
end
4'b0100: begin F = {A[15:5],S,A[3:0]};
end
4'b0101: begin F = {A[15:6],S,A[4:0]};
end
4'b0110: begin F = {A[15:7],S,A[5:0]};
end
4'b0111: begin F = {A[15:8],S,A[6:0]};
end
4'b1000: begin F = {A[15:9],S,A[7:0]};
end
4'b1001: begin F = {A[15:10],S,A[8:0]};
end
4'b1010: begin F = {A[15:11],S,A[9:0]};
end
4'b1011: begin F = {A[15:12],S,A[10:0]};
end
4'b1100: begin F = {A[15:13],S,A[11:0]};
end
4'b1101: begin F = {A[15:14],S,A[12:0]};
end
4'b1110: begin F = {A[15],S,A[13:0]};
end
4'b1111: begin F = {S,A[14:0]};
end
endcase
end
endmodule | module Bit_OP_16bit(F, A, BS, S); |
input[15:0] A;
input[3:0] BS;
input S;
output reg[15:0] F;
always @(A) begin
case (BS[3:0])
4'b0000: begin F = {A[15:1],S};
end
4'b0001: begin F = {A[15:2],S,A[0]};
end
4'b0010: begin F = {A[15:3],S,A[1:0]};
end
4'b0011: begin F = {A[15:4],S,A[2:0]};
end
4'b0100: begin F = {A[15:5],S,A[3:0]};
end
4'b0101: begin F = {A[15:6],S,A[4:0]};
end
4'b0110: begin F = {A[15:7],S,A[5:0]};
end
4'b0111: begin F = {A[15:8],S,A[6:0]};
end
4'b1000: begin F = {A[15:9],S,A[7:0]};
end
4'b1001: begin F = {A[15:10],S,A[8:0]};
end
4'b1010: begin F = {A[15:11],S,A[9:0]};
end
4'b1011: begin F = {A[15:12],S,A[10:0]};
end
4'b1100: begin F = {A[15:13],S,A[11:0]};
end
4'b1101: begin F = {A[15:14],S,A[12:0]};
end
4'b1110: begin F = {A[15],S,A[13:0]};
end
4'b1111: begin F = {S,A[14:0]};
end
endcase
end
endmodule | 2 |
137,720 | data/full_repos/permissive/79992736/src/Bit_Test_16bit.v | 79,992,736 | Bit_Test_16bit.v | v | 63 | 36 | [] | [] | [] | [(1, 61)] | null | data/verilator_xmls/7c33e3bc-d02d-4c10-85a2-49588224fb62.xml | null | 300,456 | module | module Bit_Test_16bit(F, A, BS);
input[15:0] A;
input[3:0] BS;
output reg F;
always @(A) begin
case (BS[3:0])
4'b0000: begin F = A[0];
end
4'b0001: begin F = A[1];
end
4'b0010: begin F = A[2];
end
4'b0011: begin F = A[3];
end
4'b0100: begin F = A[4];
end
4'b0101: begin F = A[5];
end
4'b0110: begin F = A[6];
end
4'b0111: begin F = A[7];
end
4'b1000: begin F = A[8];
end
4'b1001: begin F = A[9];
end
4'b1010: begin F = A[10];
end
4'b1011: begin F = A[11];
end
4'b1100: begin F = A[12];
end
4'b1101: begin F = A[13];
end
4'b1110: begin F = A[14];
end
4'b1111: begin F = A[15];
end
endcase
end
endmodule | module Bit_Test_16bit(F, A, BS); |
input[15:0] A;
input[3:0] BS;
output reg F;
always @(A) begin
case (BS[3:0])
4'b0000: begin F = A[0];
end
4'b0001: begin F = A[1];
end
4'b0010: begin F = A[2];
end
4'b0011: begin F = A[3];
end
4'b0100: begin F = A[4];
end
4'b0101: begin F = A[5];
end
4'b0110: begin F = A[6];
end
4'b0111: begin F = A[7];
end
4'b1000: begin F = A[8];
end
4'b1001: begin F = A[9];
end
4'b1010: begin F = A[10];
end
4'b1011: begin F = A[11];
end
4'b1100: begin F = A[12];
end
4'b1101: begin F = A[13];
end
4'b1110: begin F = A[14];
end
4'b1111: begin F = A[15];
end
endcase
end
endmodule | 2 |
137,724 | data/full_repos/permissive/79992736/src/decoder3to8.v | 79,992,736 | decoder3to8.v | v | 28 | 58 | [] | [] | [] | [(1, 27)] | null | data/verilator_xmls/b0722f8c-044f-40e0-8d9f-d69f4c1cbb4d.xml | null | 300,460 | module | module decoder3to8(S, m0, m1, m2, m3, m4, m5, m6, m7);
input [2:0]S;
output m0, m1, m2, m3, m4, m5, m6, m7;
wire not_S0, not_S1, not_S2;
wire b0, b1, b2, b3;
not not0(not_S0, S[0]);
not not1(not_S1, S[1]);
not not2(not_S2, S[2]);
and and0(b0, not_S1, not_S0);
and and1(b1, not_S1, S[0]);
and and2(b2, S[1], not_S0);
and and3(b3, S[1], S[0]);
and and4(m0, not_S2, b0);
and and5(m1, not_S2, b1);
and and6(m2, not_S2, b2);
and and7(m3, not_S2, b3);
and and8(m4, S[2], b0);
and and9(m5, S[2], b1);
and and10(m6, S[2], b2);
and and11(m7, S[2], b3);
endmodule | module decoder3to8(S, m0, m1, m2, m3, m4, m5, m6, m7); |
input [2:0]S;
output m0, m1, m2, m3, m4, m5, m6, m7;
wire not_S0, not_S1, not_S2;
wire b0, b1, b2, b3;
not not0(not_S0, S[0]);
not not1(not_S1, S[1]);
not not2(not_S2, S[2]);
and and0(b0, not_S1, not_S0);
and and1(b1, not_S1, S[0]);
and and2(b2, S[1], not_S0);
and and3(b3, S[1], S[0]);
and and4(m0, not_S2, b0);
and and5(m1, not_S2, b1);
and and6(m2, not_S2, b2);
and and7(m3, not_S2, b3);
and and8(m4, S[2], b0);
and and9(m5, S[2], b1);
and and10(m6, S[2], b2);
and and11(m7, S[2], b3);
endmodule | 2 |
137,727 | data/full_repos/permissive/79992736/src/Full_adder.v | 79,992,736 | Full_adder.v | v | 35 | 56 | [] | [] | [] | [(1, 34)] | null | data/verilator_xmls/b8c4ee9e-344a-484a-a52d-519ee7b4f3d6.xml | null | 300,463 | module | module Full_adder(
B,
A,
C_in,
S,
C_out
);
input wire B;
input wire A;
input wire C_in;
output wire S;
output wire C_out;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_3 = A & B;
assign SYNTHESIZED_WIRE_2 = C_in & SYNTHESIZED_WIRE_4;
assign S = SYNTHESIZED_WIRE_4 ^ C_in;
assign SYNTHESIZED_WIRE_4 = A ^ B;
assign C_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
endmodule | module Full_adder(
B,
A,
C_in,
S,
C_out
); |
input wire B;
input wire A;
input wire C_in;
output wire S;
output wire C_out;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_3 = A & B;
assign SYNTHESIZED_WIRE_2 = C_in & SYNTHESIZED_WIRE_4;
assign S = SYNTHESIZED_WIRE_4 ^ C_in;
assign SYNTHESIZED_WIRE_4 = A ^ B;
assign C_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
endmodule | 2 |
137,729 | data/full_repos/permissive/79992736/src/GPIO_Board_test.v | 79,992,736 | GPIO_Board_test.v | v | 62 | 88 | [] | [] | [] | [(1, 51), (54, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:34: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d0(HEX_seg_count,HEX0[0],HEX0[1],HEX0[2],HEX0[3],HEX0[4],HEX0[5],HEX0[6]);\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/decoder3to8\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/decoder3to8.v\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/decoder3to8.sv\n decoder3to8\n decoder3to8.v\n decoder3to8.sv\n obj_dir/decoder3to8\n obj_dir/decoder3to8.v\n obj_dir/decoder3to8.sv\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:35: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d1(HEX_seg_count,HEX1[1],HEX1[2],HEX1[3],HEX1[4],HEX1[5],HEX1[6],HEX1[0]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:36: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d2(HEX_seg_count,HEX2[2],HEX2[3],HEX2[4],HEX2[5],HEX2[6],HEX2[0],HEX2[1]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:37: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d3(HEX_seg_count,HEX3[3],HEX3[4],HEX3[5],HEX3[6],HEX3[0],HEX3[1],HEX3[2]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:38: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d4(HEX_seg_count,HEX4[4],HEX4[5],HEX4[6],HEX4[0],HEX4[1],HEX4[2],HEX4[3]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:39: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d5(HEX_seg_count,HEX5[5],HEX5[6],HEX5[0],HEX5[1],HEX5[2],HEX5[3],HEX5[4]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:40: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d6(HEX_seg_count,HEX6[6],HEX6[0],HEX6[1],HEX6[2],HEX6[3],HEX6[4],HEX6[5]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:41: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d7(HEX_seg_count,HEX7[0],HEX7[1],HEX7[2],HEX7[3],HEX7[4],HEX7[5],HEX7[6]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:43: Cannot find file containing module: 'GPIO_Board'\n GPIO_Board DUT(\n ^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 300,465 | module | module GPIO_Board_test(CLOCK_50, GPIO0_D);
input CLOCK_50;
output [31:0] GPIO0_D;
wire [31:0]count;
count_32bit counter1(CLOCK_50, count);
wire GPIO_clock;
assign GPIO_clock = CLOCK_50;
wire [15:0]R0, R1, R2, R3, R4, R5, R6, R7;
assign R0 = {count[31:24], count[31:24]};
assign R1 = {count[31:28], count[31:28], count[31:28], count[31:28]};
assign R2 = {count[27:24], count[27:24], count[27:24], count[27:24]};
assign R3 = {count[27:24], count[31:28], count[27:24], count[31:28]};
assign R4 = ~R3;
assign R5 = ~R2;
assign R6 = ~R1;
assign R7 = ~R0;
wire HEX0_DP, HEX1_DP, HEX2_DP, HEX3_DP, HEX4_DP, HEX5_DP, HEX6_DP, HEX7_DP;
assign HEX0_DP = count[27];
assign HEX1_DP = ~count[27];
assign HEX2_DP = count[27];
assign HEX3_DP = ~count[27];
assign HEX4_DP = count[27];
assign HEX5_DP = ~count[27];
assign HEX6_DP = count[27];
assign HEX7_DP = ~count[27];
wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire [2:0] HEX_seg_count;
assign HEX_seg_count = count[28:26];
decoder3to8 d0(HEX_seg_count,HEX0[0],HEX0[1],HEX0[2],HEX0[3],HEX0[4],HEX0[5],HEX0[6]);
decoder3to8 d1(HEX_seg_count,HEX1[1],HEX1[2],HEX1[3],HEX1[4],HEX1[5],HEX1[6],HEX1[0]);
decoder3to8 d2(HEX_seg_count,HEX2[2],HEX2[3],HEX2[4],HEX2[5],HEX2[6],HEX2[0],HEX2[1]);
decoder3to8 d3(HEX_seg_count,HEX3[3],HEX3[4],HEX3[5],HEX3[6],HEX3[0],HEX3[1],HEX3[2]);
decoder3to8 d4(HEX_seg_count,HEX4[4],HEX4[5],HEX4[6],HEX4[0],HEX4[1],HEX4[2],HEX4[3]);
decoder3to8 d5(HEX_seg_count,HEX5[5],HEX5[6],HEX5[0],HEX5[1],HEX5[2],HEX5[3],HEX5[4]);
decoder3to8 d6(HEX_seg_count,HEX6[6],HEX6[0],HEX6[1],HEX6[2],HEX6[3],HEX6[4],HEX6[5]);
decoder3to8 d7(HEX_seg_count,HEX7[0],HEX7[1],HEX7[2],HEX7[3],HEX7[4],HEX7[5],HEX7[6]);
GPIO_Board DUT(
GPIO_clock,
R0, R1, R2, R3, R4, R5, R6, R7,
HEX0, HEX0_DP, HEX1, HEX1_DP,
HEX2, HEX2_DP, HEX3, HEX3_DP,
HEX4, HEX4_DP, HEX5, HEX5_DP,
HEX6, HEX6_DP, HEX7, HEX7_DP, GPIO0_D);
endmodule | module GPIO_Board_test(CLOCK_50, GPIO0_D); |
input CLOCK_50;
output [31:0] GPIO0_D;
wire [31:0]count;
count_32bit counter1(CLOCK_50, count);
wire GPIO_clock;
assign GPIO_clock = CLOCK_50;
wire [15:0]R0, R1, R2, R3, R4, R5, R6, R7;
assign R0 = {count[31:24], count[31:24]};
assign R1 = {count[31:28], count[31:28], count[31:28], count[31:28]};
assign R2 = {count[27:24], count[27:24], count[27:24], count[27:24]};
assign R3 = {count[27:24], count[31:28], count[27:24], count[31:28]};
assign R4 = ~R3;
assign R5 = ~R2;
assign R6 = ~R1;
assign R7 = ~R0;
wire HEX0_DP, HEX1_DP, HEX2_DP, HEX3_DP, HEX4_DP, HEX5_DP, HEX6_DP, HEX7_DP;
assign HEX0_DP = count[27];
assign HEX1_DP = ~count[27];
assign HEX2_DP = count[27];
assign HEX3_DP = ~count[27];
assign HEX4_DP = count[27];
assign HEX5_DP = ~count[27];
assign HEX6_DP = count[27];
assign HEX7_DP = ~count[27];
wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire [2:0] HEX_seg_count;
assign HEX_seg_count = count[28:26];
decoder3to8 d0(HEX_seg_count,HEX0[0],HEX0[1],HEX0[2],HEX0[3],HEX0[4],HEX0[5],HEX0[6]);
decoder3to8 d1(HEX_seg_count,HEX1[1],HEX1[2],HEX1[3],HEX1[4],HEX1[5],HEX1[6],HEX1[0]);
decoder3to8 d2(HEX_seg_count,HEX2[2],HEX2[3],HEX2[4],HEX2[5],HEX2[6],HEX2[0],HEX2[1]);
decoder3to8 d3(HEX_seg_count,HEX3[3],HEX3[4],HEX3[5],HEX3[6],HEX3[0],HEX3[1],HEX3[2]);
decoder3to8 d4(HEX_seg_count,HEX4[4],HEX4[5],HEX4[6],HEX4[0],HEX4[1],HEX4[2],HEX4[3]);
decoder3to8 d5(HEX_seg_count,HEX5[5],HEX5[6],HEX5[0],HEX5[1],HEX5[2],HEX5[3],HEX5[4]);
decoder3to8 d6(HEX_seg_count,HEX6[6],HEX6[0],HEX6[1],HEX6[2],HEX6[3],HEX6[4],HEX6[5]);
decoder3to8 d7(HEX_seg_count,HEX7[0],HEX7[1],HEX7[2],HEX7[3],HEX7[4],HEX7[5],HEX7[6]);
GPIO_Board DUT(
GPIO_clock,
R0, R1, R2, R3, R4, R5, R6, R7,
HEX0, HEX0_DP, HEX1, HEX1_DP,
HEX2, HEX2_DP, HEX3, HEX3_DP,
HEX4, HEX4_DP, HEX5, HEX5_DP,
HEX6, HEX6_DP, HEX7, HEX7_DP, GPIO0_D);
endmodule | 2 |
137,730 | data/full_repos/permissive/79992736/src/GPIO_Board_test.v | 79,992,736 | GPIO_Board_test.v | v | 62 | 88 | [] | [] | [] | [(1, 51), (54, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:34: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d0(HEX_seg_count,HEX0[0],HEX0[1],HEX0[2],HEX0[3],HEX0[4],HEX0[5],HEX0[6]);\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/decoder3to8\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/decoder3to8.v\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/decoder3to8.sv\n decoder3to8\n decoder3to8.v\n decoder3to8.sv\n obj_dir/decoder3to8\n obj_dir/decoder3to8.v\n obj_dir/decoder3to8.sv\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:35: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d1(HEX_seg_count,HEX1[1],HEX1[2],HEX1[3],HEX1[4],HEX1[5],HEX1[6],HEX1[0]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:36: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d2(HEX_seg_count,HEX2[2],HEX2[3],HEX2[4],HEX2[5],HEX2[6],HEX2[0],HEX2[1]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:37: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d3(HEX_seg_count,HEX3[3],HEX3[4],HEX3[5],HEX3[6],HEX3[0],HEX3[1],HEX3[2]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:38: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d4(HEX_seg_count,HEX4[4],HEX4[5],HEX4[6],HEX4[0],HEX4[1],HEX4[2],HEX4[3]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:39: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d5(HEX_seg_count,HEX5[5],HEX5[6],HEX5[0],HEX5[1],HEX5[2],HEX5[3],HEX5[4]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:40: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d6(HEX_seg_count,HEX6[6],HEX6[0],HEX6[1],HEX6[2],HEX6[3],HEX6[4],HEX6[5]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:41: Cannot find file containing module: 'decoder3to8'\n decoder3to8 d7(HEX_seg_count,HEX7[0],HEX7[1],HEX7[2],HEX7[3],HEX7[4],HEX7[5],HEX7[6]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/GPIO_Board_test.v:43: Cannot find file containing module: 'GPIO_Board'\n GPIO_Board DUT(\n ^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 300,465 | module | module count_32bit(clock, out);
input clock;
output reg [31:0]out;
always @(posedge clock)
out <= out + 1'b1;
endmodule | module count_32bit(clock, out); |
input clock;
output reg [31:0]out;
always @(posedge clock)
out <= out + 1'b1;
endmodule | 2 |
137,732 | data/full_repos/permissive/79992736/src/ID_00_Handler.v | 79,992,736 | ID_00_Handler.v | v | 31 | 92 | [] | [] | [] | [(1, 31)] | null | data/verilator_xmls/b6cc8244-ce2f-4234-8bc4-0218951596b4.xml | null | 300,467 | module | module ID_00_Handler (ISin, CWout, literal);
input [13:0] ISin;
output reg [15:0] literal;
output reg [18:0] CWout;
always @(ISin) begin
casex (ISin[13:9])
5'b00000: begin CWout = 19'b0000000000000000000;
literal= 16'b1111111111111111; end
5'b001xx: begin CWout = {6'b101001,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b010xx: begin CWout = {6'b101101,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b011xx: begin CWout = {6'b010001,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b101xx: begin CWout = {6'b011101,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b110xx: begin CWout = {6'b001101,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
endcase
end
endmodule | module ID_00_Handler (ISin, CWout, literal); |
input [13:0] ISin;
output reg [15:0] literal;
output reg [18:0] CWout;
always @(ISin) begin
casex (ISin[13:9])
5'b00000: begin CWout = 19'b0000000000000000000;
literal= 16'b1111111111111111; end
5'b001xx: begin CWout = {6'b101001,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b010xx: begin CWout = {6'b101101,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b011xx: begin CWout = {6'b010001,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b101xx: begin CWout = {6'b011101,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
5'b110xx: begin CWout = {6'b001101,ISin[10:8],ISin[10:8],7'b0000100};
literal = {8'b00000000,ISin[7:0]}; end
endcase
end
endmodule | 2 |
137,735 | data/full_repos/permissive/79992736/src/ID_11_Handler.v | 79,992,736 | ID_11_Handler.v | v | 15 | 69 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/ce967253-8091-42ee-b749-63865832656e.xml | null | 300,470 | module | module ID_11_Handler (ISin, CWout, literal);
input [13:0] ISin;
output reg [15:0] literal;
output reg [18:0] CWout;
always @(ISin) begin
CWout = {6'b010101,ISin[13:11],10'b0000000100};
literal = {ISin[10],ISin[10],ISin[10],ISin[10],ISin[10],ISin[10:0]};
end
endmodule | module ID_11_Handler (ISin, CWout, literal); |
input [13:0] ISin;
output reg [15:0] literal;
output reg [18:0] CWout;
always @(ISin) begin
CWout = {6'b010101,ISin[13:11],10'b0000000100};
literal = {ISin[10],ISin[10],ISin[10],ISin[10],ISin[10],ISin[10:0]};
end
endmodule | 2 |
137,737 | data/full_repos/permissive/79992736/src/Mem_Ad_Red.v | 79,992,736 | Mem_Ad_Red.v | v | 8 | 36 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/889e0ae0-d974-448f-9bea-e22ba0ffef20.xml | null | 300,474 | module | module Mem_Ad_Red(AddOut, Literal);
input[15:0] Literal;
output[7:0] AddOut;
assign AddOut = Literal [7:0];
endmodule | module Mem_Ad_Red(AddOut, Literal); |
input[15:0] Literal;
output[7:0] AddOut;
assign AddOut = Literal [7:0];
endmodule | 2 |
137,739 | data/full_repos/permissive/79992736/src/Multiply_16bit.v | 79,992,736 | Multiply_16bit.v | v | 8 | 32 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/362d43eb-c4af-4e92-852b-a70ec667e86b.xml | null | 300,476 | module | module Multiply_16bit(F, A, B);
input signed[15:0] A, B;
output signed[15:0] F;
assign F = A*B;
endmodule | module Multiply_16bit(F, A, B); |
input signed[15:0] A, B;
output signed[15:0] F;
assign F = A*B;
endmodule | 2 |
137,742 | data/full_repos/permissive/79992736/src/mux_4to1_19bit.v | 79,992,736 | mux_4to1_19bit.v | v | 27 | 61 | [] | [] | [] | [(1, 27)] | null | null | 1: b"%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:7: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1.v\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1.sv\n Mux_4_to_1\n Mux_4_to_1.v\n Mux_4_to_1.sv\n obj_dir/Mux_4_to_1\n obj_dir/Mux_4_to_1.v\n obj_dir/Mux_4_to_1.sv\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:8: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:9: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux2(S, i1[2], i2[2], i3[2], i4[2], Q[2]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:10: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux3(S, i1[3], i2[3], i3[3], i4[3], Q[3]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:11: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux4(S, i1[4], i2[4], i3[4], i4[4], Q[4]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:12: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux5(S, i1[5], i2[5], i3[5], i4[5], Q[5]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:13: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux6(S, i1[6], i2[6], i3[6], i4[6], Q[6]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:14: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux7(S, i1[7], i2[7], i3[7], i4[7], Q[7]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:15: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux8(S, i1[8], i2[8], i3[8], i4[8], Q[8]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:16: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux9(S, i1[9], i2[9], i3[9], i4[9], Q[9]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:17: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux10(S, i1[10], i2[10], i3[10], i4[10], Q[10]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:18: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux11(S, i1[11], i2[11], i3[11], i4[11], Q[11]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:19: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux12(S, i1[12], i2[12], i3[12], i4[12], Q[12]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:20: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux13(S, i1[13], i2[13], i3[13], i4[13], Q[13]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:21: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux14(S, i1[14], i2[14], i3[14], i4[14], Q[14]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:22: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux15(S, i1[15], i2[15], i3[15], i4[15], Q[15]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:23: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux16(S, i1[16], i2[16], i3[16], i4[16], Q[16]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:24: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux17(S, i1[17], i2[17], i3[17], i4[17], Q[17]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_19bit.v:25: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux18(S, i1[18], i2[18], i3[18], i4[18], Q[18]);\n ^~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n" | 300,482 | module | module mux_4to1_19bit(S, i1, i2, i3, i4, Q);
input[18:0] i1, i2, i3, i4;
input[1:0] S;
output[18:0] Q;
Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);
Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);
Mux_4_to_1 mux2(S, i1[2], i2[2], i3[2], i4[2], Q[2]);
Mux_4_to_1 mux3(S, i1[3], i2[3], i3[3], i4[3], Q[3]);
Mux_4_to_1 mux4(S, i1[4], i2[4], i3[4], i4[4], Q[4]);
Mux_4_to_1 mux5(S, i1[5], i2[5], i3[5], i4[5], Q[5]);
Mux_4_to_1 mux6(S, i1[6], i2[6], i3[6], i4[6], Q[6]);
Mux_4_to_1 mux7(S, i1[7], i2[7], i3[7], i4[7], Q[7]);
Mux_4_to_1 mux8(S, i1[8], i2[8], i3[8], i4[8], Q[8]);
Mux_4_to_1 mux9(S, i1[9], i2[9], i3[9], i4[9], Q[9]);
Mux_4_to_1 mux10(S, i1[10], i2[10], i3[10], i4[10], Q[10]);
Mux_4_to_1 mux11(S, i1[11], i2[11], i3[11], i4[11], Q[11]);
Mux_4_to_1 mux12(S, i1[12], i2[12], i3[12], i4[12], Q[12]);
Mux_4_to_1 mux13(S, i1[13], i2[13], i3[13], i4[13], Q[13]);
Mux_4_to_1 mux14(S, i1[14], i2[14], i3[14], i4[14], Q[14]);
Mux_4_to_1 mux15(S, i1[15], i2[15], i3[15], i4[15], Q[15]);
Mux_4_to_1 mux16(S, i1[16], i2[16], i3[16], i4[16], Q[16]);
Mux_4_to_1 mux17(S, i1[17], i2[17], i3[17], i4[17], Q[17]);
Mux_4_to_1 mux18(S, i1[18], i2[18], i3[18], i4[18], Q[18]);
endmodule | module mux_4to1_19bit(S, i1, i2, i3, i4, Q); |
input[18:0] i1, i2, i3, i4;
input[1:0] S;
output[18:0] Q;
Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);
Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);
Mux_4_to_1 mux2(S, i1[2], i2[2], i3[2], i4[2], Q[2]);
Mux_4_to_1 mux3(S, i1[3], i2[3], i3[3], i4[3], Q[3]);
Mux_4_to_1 mux4(S, i1[4], i2[4], i3[4], i4[4], Q[4]);
Mux_4_to_1 mux5(S, i1[5], i2[5], i3[5], i4[5], Q[5]);
Mux_4_to_1 mux6(S, i1[6], i2[6], i3[6], i4[6], Q[6]);
Mux_4_to_1 mux7(S, i1[7], i2[7], i3[7], i4[7], Q[7]);
Mux_4_to_1 mux8(S, i1[8], i2[8], i3[8], i4[8], Q[8]);
Mux_4_to_1 mux9(S, i1[9], i2[9], i3[9], i4[9], Q[9]);
Mux_4_to_1 mux10(S, i1[10], i2[10], i3[10], i4[10], Q[10]);
Mux_4_to_1 mux11(S, i1[11], i2[11], i3[11], i4[11], Q[11]);
Mux_4_to_1 mux12(S, i1[12], i2[12], i3[12], i4[12], Q[12]);
Mux_4_to_1 mux13(S, i1[13], i2[13], i3[13], i4[13], Q[13]);
Mux_4_to_1 mux14(S, i1[14], i2[14], i3[14], i4[14], Q[14]);
Mux_4_to_1 mux15(S, i1[15], i2[15], i3[15], i4[15], Q[15]);
Mux_4_to_1 mux16(S, i1[16], i2[16], i3[16], i4[16], Q[16]);
Mux_4_to_1 mux17(S, i1[17], i2[17], i3[17], i4[17], Q[17]);
Mux_4_to_1 mux18(S, i1[18], i2[18], i3[18], i4[18], Q[18]);
endmodule | 2 |
137,743 | data/full_repos/permissive/79992736/src/mux_4to1_2bit.v | 79,992,736 | mux_4to1_2bit.v | v | 11 | 55 | [] | [] | [] | [(1, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/79992736/src/mux_4to1_2bit.v:7: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1.v\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/Mux_4_to_1.sv\n Mux_4_to_1\n Mux_4_to_1.v\n Mux_4_to_1.sv\n obj_dir/Mux_4_to_1\n obj_dir/Mux_4_to_1.v\n obj_dir/Mux_4_to_1.sv\n%Error: data/full_repos/permissive/79992736/src/mux_4to1_2bit.v:8: Cannot find file containing module: 'Mux_4_to_1'\n Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 300,483 | module | module mux_4to1_2bit(S, i1, i2, i3, i4, Q);
input[1:0] i1, i2, i3, i4;
input[1:0] S;
output[1:0] Q;
Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);
Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);
endmodule | module mux_4to1_2bit(S, i1, i2, i3, i4, Q); |
input[1:0] i1, i2, i3, i4;
input[1:0] S;
output[1:0] Q;
Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);
Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);
endmodule | 2 |
137,746 | data/full_repos/permissive/79992736/src/mux_8to1_16bit.v | 79,992,736 | mux_8to1_16bit.v | v | 25 | 91 | [] | [] | [] | [(1, 24)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:3: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] i1, i2, i3, i4, i5, i6, i7, i8;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:4: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] S;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:5: Little bit endian vector: MSB < LSB of bit range: 0:15\noutput [0:15] Q;\n ^\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:7: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux0(Q[0], S, i1[0], i2[0], i3[0], i4[0], i5[0], i6[0], i7[0], i8[0]);\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/mux8to1\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/mux8to1.v\n data/full_repos/permissive/79992736/src,data/full_repos/permissive/79992736/mux8to1.sv\n mux8to1\n mux8to1.v\n mux8to1.sv\n obj_dir/mux8to1\n obj_dir/mux8to1.v\n obj_dir/mux8to1.sv\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:8: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux1(Q[1], S, i1[1], i2[1], i3[1], i4[1], i5[1], i6[1], i7[1], i8[1]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:9: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux2(Q[2], S, i1[2], i2[2], i3[2], i4[2], i5[2], i6[2], i7[2], i8[2]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:10: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux3(Q[3], S, i1[3], i2[3], i3[3], i4[3], i5[3], i6[3], i7[3], i8[3]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:11: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux4(Q[4], S, i1[4], i2[4], i3[4], i4[4], i5[4], i6[4], i7[4], i8[4]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:12: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux5(Q[5], S, i1[5], i2[5], i3[5], i4[5], i5[5], i6[5], i7[5], i8[5]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:13: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux6(Q[6], S, i1[6], i2[6], i3[6], i4[6], i5[6], i6[6], i7[6], i8[6]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:14: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux7(Q[7], S, i1[7], i2[7], i3[7], i4[7], i5[7], i6[7], i7[7], i8[7]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:15: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux8(Q[8], S, i1[8], i2[8], i3[8], i4[8], i5[8], i6[8], i7[8], i8[8]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:16: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux9(Q[9], S, i1[9], i2[9], i3[9], i4[9], i5[9], i6[9], i7[9], i8[9]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:17: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux10(Q[10], S, i1[10], i2[10], i3[10], i4[10], i5[10], i6[10], i7[10], i8[10]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:18: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux11(Q[11], S, i1[11], i2[11], i3[11], i4[11], i5[11], i6[11], i7[11], i8[11]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:19: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux12(Q[12], S, i1[12], i2[12], i3[12], i4[12], i5[12], i6[12], i7[12], i8[12]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:20: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux13(Q[13], S, i1[13], i2[13], i3[13], i4[13], i5[13], i6[13], i7[13], i8[13]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:21: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux14(Q[14], S, i1[14], i2[14], i3[14], i4[14], i5[14], i6[14], i7[14], i8[14]);\n ^~~~~~~\n%Error: data/full_repos/permissive/79992736/src/mux_8to1_16bit.v:22: Cannot find file containing module: \'mux8to1\'\n mux8to1 mux15(Q[15], S, i1[15], i2[15], i3[15], i4[15], i5[15], i6[15], i7[15], i8[15]);\n ^~~~~~~\n%Error: Exiting due to 16 error(s), 3 warning(s)\n' | 300,486 | module | module mux_8to1_16bit(Q, S, i1, i2, i3, i4, i5, i6, i7, i8);
input [0:15] i1, i2, i3, i4, i5, i6, i7, i8;
input [0:2] S;
output [0:15] Q;
mux8to1 mux0(Q[0], S, i1[0], i2[0], i3[0], i4[0], i5[0], i6[0], i7[0], i8[0]);
mux8to1 mux1(Q[1], S, i1[1], i2[1], i3[1], i4[1], i5[1], i6[1], i7[1], i8[1]);
mux8to1 mux2(Q[2], S, i1[2], i2[2], i3[2], i4[2], i5[2], i6[2], i7[2], i8[2]);
mux8to1 mux3(Q[3], S, i1[3], i2[3], i3[3], i4[3], i5[3], i6[3], i7[3], i8[3]);
mux8to1 mux4(Q[4], S, i1[4], i2[4], i3[4], i4[4], i5[4], i6[4], i7[4], i8[4]);
mux8to1 mux5(Q[5], S, i1[5], i2[5], i3[5], i4[5], i5[5], i6[5], i7[5], i8[5]);
mux8to1 mux6(Q[6], S, i1[6], i2[6], i3[6], i4[6], i5[6], i6[6], i7[6], i8[6]);
mux8to1 mux7(Q[7], S, i1[7], i2[7], i3[7], i4[7], i5[7], i6[7], i7[7], i8[7]);
mux8to1 mux8(Q[8], S, i1[8], i2[8], i3[8], i4[8], i5[8], i6[8], i7[8], i8[8]);
mux8to1 mux9(Q[9], S, i1[9], i2[9], i3[9], i4[9], i5[9], i6[9], i7[9], i8[9]);
mux8to1 mux10(Q[10], S, i1[10], i2[10], i3[10], i4[10], i5[10], i6[10], i7[10], i8[10]);
mux8to1 mux11(Q[11], S, i1[11], i2[11], i3[11], i4[11], i5[11], i6[11], i7[11], i8[11]);
mux8to1 mux12(Q[12], S, i1[12], i2[12], i3[12], i4[12], i5[12], i6[12], i7[12], i8[12]);
mux8to1 mux13(Q[13], S, i1[13], i2[13], i3[13], i4[13], i5[13], i6[13], i7[13], i8[13]);
mux8to1 mux14(Q[14], S, i1[14], i2[14], i3[14], i4[14], i5[14], i6[14], i7[14], i8[14]);
mux8to1 mux15(Q[15], S, i1[15], i2[15], i3[15], i4[15], i5[15], i6[15], i7[15], i8[15]);
endmodule | module mux_8to1_16bit(Q, S, i1, i2, i3, i4, i5, i6, i7, i8); |
input [0:15] i1, i2, i3, i4, i5, i6, i7, i8;
input [0:2] S;
output [0:15] Q;
mux8to1 mux0(Q[0], S, i1[0], i2[0], i3[0], i4[0], i5[0], i6[0], i7[0], i8[0]);
mux8to1 mux1(Q[1], S, i1[1], i2[1], i3[1], i4[1], i5[1], i6[1], i7[1], i8[1]);
mux8to1 mux2(Q[2], S, i1[2], i2[2], i3[2], i4[2], i5[2], i6[2], i7[2], i8[2]);
mux8to1 mux3(Q[3], S, i1[3], i2[3], i3[3], i4[3], i5[3], i6[3], i7[3], i8[3]);
mux8to1 mux4(Q[4], S, i1[4], i2[4], i3[4], i4[4], i5[4], i6[4], i7[4], i8[4]);
mux8to1 mux5(Q[5], S, i1[5], i2[5], i3[5], i4[5], i5[5], i6[5], i7[5], i8[5]);
mux8to1 mux6(Q[6], S, i1[6], i2[6], i3[6], i4[6], i5[6], i6[6], i7[6], i8[6]);
mux8to1 mux7(Q[7], S, i1[7], i2[7], i3[7], i4[7], i5[7], i6[7], i7[7], i8[7]);
mux8to1 mux8(Q[8], S, i1[8], i2[8], i3[8], i4[8], i5[8], i6[8], i7[8], i8[8]);
mux8to1 mux9(Q[9], S, i1[9], i2[9], i3[9], i4[9], i5[9], i6[9], i7[9], i8[9]);
mux8to1 mux10(Q[10], S, i1[10], i2[10], i3[10], i4[10], i5[10], i6[10], i7[10], i8[10]);
mux8to1 mux11(Q[11], S, i1[11], i2[11], i3[11], i4[11], i5[11], i6[11], i7[11], i8[11]);
mux8to1 mux12(Q[12], S, i1[12], i2[12], i3[12], i4[12], i5[12], i6[12], i7[12], i8[12]);
mux8to1 mux13(Q[13], S, i1[13], i2[13], i3[13], i4[13], i5[13], i6[13], i7[13], i8[13]);
mux8to1 mux14(Q[14], S, i1[14], i2[14], i3[14], i4[14], i5[14], i6[14], i7[14], i8[14]);
mux8to1 mux15(Q[15], S, i1[15], i2[15], i3[15], i4[15], i5[15], i6[15], i7[15], i8[15]);
endmodule | 2 |
137,755 | data/full_repos/permissive/79992736/src/reg_file_tb.v | 79,992,736 | reg_file_tb.v | v | 69 | 101 | [] | [] | [] | null | line:65: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79992736/src/reg_file_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 clock = ~clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79992736/src/reg_file_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #2 not_reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79992736/src/reg_file_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 not_reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79992736/src/reg_file_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20 D = $random; \n ^\n%Error: data/full_repos/permissive/79992736/src/reg_file_tb.v:60: Unsupported or unknown PLI call: $monitor\n$monitor("t:%d\\tclk:%b\\tWR:%b\\tDA:%d\\tD:%h\\tAA:%d\\tA:%h\\tBA:%d\\tB:%h\\tR0-7:%h %h %h %h %h %h %h %h",\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/79992736/src/reg_file_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#1000 $finish;\n^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,496 | module | module reg_file_tb;
parameter bit_width = 8;
reg clock, not_reset, write;
reg [2:0] DA, AA, BA;
reg [bit_width-1:0] D;
wire [bit_width-1:0] A, B, R0, R1, R2, R3, R4, R5, R6, R7;
reg_8x8_bit dut(
.clock (clock),
.reset (not_reset),
.WR (write),
.DA (DA),
.AA (AA),
.BA (BA),
.D (D),
.A (A),
.B (B),
.R0 (R0),
.R1 (R1),
.R2 (R2),
.R3 (R3),
.R4 (R4),
.R5 (R5),
.R6 (R6),
.R7 (R7)
);
initial
begin
clock <= 1'b0;
forever
#10 clock = ~clock;
end
initial
begin
#2 not_reset = 1'b0;
#5 not_reset = 1'b1;
DA = 3'b0;
forever
begin
#20 D = $random;
DA = DA + 3'b1;
AA = $random;
BA = $random;
write = $random;
end
end
initial
$monitor("t:%d\tclk:%b\tWR:%b\tDA:%d\tD:%h\tAA:%d\tA:%h\tBA:%d\tB:%h\tR0-7:%h %h %h %h %h %h %h %h",
$time, clock, write, DA, D, AA, A, BA, B, R0, R1, R2, R3, R4, R5, R6, R7);
initial
#1000 $finish;
endmodule | module reg_file_tb; |
parameter bit_width = 8;
reg clock, not_reset, write;
reg [2:0] DA, AA, BA;
reg [bit_width-1:0] D;
wire [bit_width-1:0] A, B, R0, R1, R2, R3, R4, R5, R6, R7;
reg_8x8_bit dut(
.clock (clock),
.reset (not_reset),
.WR (write),
.DA (DA),
.AA (AA),
.BA (BA),
.D (D),
.A (A),
.B (B),
.R0 (R0),
.R1 (R1),
.R2 (R2),
.R3 (R3),
.R4 (R4),
.R5 (R5),
.R6 (R6),
.R7 (R7)
);
initial
begin
clock <= 1'b0;
forever
#10 clock = ~clock;
end
initial
begin
#2 not_reset = 1'b0;
#5 not_reset = 1'b1;
DA = 3'b0;
forever
begin
#20 D = $random;
DA = DA + 3'b1;
AA = $random;
BA = $random;
write = $random;
end
end
initial
$monitor("t:%d\tclk:%b\tWR:%b\tDA:%d\tD:%h\tAA:%d\tA:%h\tBA:%d\tB:%h\tR0-7:%h %h %h %h %h %h %h %h",
$time, clock, write, DA, D, AA, A, BA, B, R0, R1, R2, R3, R4, R5, R6, R7);
initial
#1000 $finish;
endmodule | 2 |
137,774 | data/full_repos/permissive/80039510/tb_file.v | 80,039,510 | tb_file.v | v | 27 | 50 | [] | [] | [] | [(1, 26)] | null | null | 1: b'%Error: data/full_repos/permissive/80039510/tb_file.v:11: Unsupported or unknown PLI call: $monitor\n$monitor(t_clk, t_in, t_out);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/80039510/tb_file.v:16: Unsupported: Ignoring delay on this delayed statement.\n#10 t_in = 7;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80039510/tb_file.v:17: Unsupported: Ignoring delay on this delayed statement.\n#10 t_in = 10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/80039510/tb_file.v:18: Unsupported: Ignoring delay on this delayed statement.\n#10 t_in = 4;\n^\n%Warning-STMTDLY: data/full_repos/permissive/80039510/tb_file.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10 t_in = 13;\n^\n%Warning-STMTDLY: data/full_repos/permissive/80039510/tb_file.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 t_clk = !t_clk;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,506 | module | module top_tb;
reg [7:0] t_in;
reg t_clk;
wire [7:0] t_out;
top tb_top( .in(t_in), .clk(t_clk), .out(t_out));
initial
begin
$monitor(t_clk, t_in, t_out);
t_in = 23;
t_clk = 1'b0;
#10 t_in = 7;
#10 t_in = 10;
#10 t_in = 4;
#10 t_in = 13;
end
always
#5 t_clk = !t_clk;
endmodule | module top_tb; |
reg [7:0] t_in;
reg t_clk;
wire [7:0] t_out;
top tb_top( .in(t_in), .clk(t_clk), .out(t_out));
initial
begin
$monitor(t_clk, t_in, t_out);
t_in = 23;
t_clk = 1'b0;
#10 t_in = 7;
#10 t_in = 10;
#10 t_in = 4;
#10 t_in = 13;
end
always
#5 t_clk = !t_clk;
endmodule | 1 |
137,776 | data/full_repos/permissive/80246680/src/Raster_Laser_Projector/Raster_Laser_Projector_bb.v | 80,246,680 | Raster_Laser_Projector_bb.v | v | 31 | 33 | [] | [] | [] | [(2, 30)] | null | data/verilator_xmls/75738535-ec7d-4a7f-a7a6-ec01f1f8fb9c.xml | null | 300,520 | module | module Raster_Laser_Projector (
clk_100k_clk,
clk_100mhz_clk,
clk_50mhz_in_clk,
pixel_clk_clk,
polygon_ctrl_clk_clk,
reset_reset_n,
video_in_TD_CLK27,
video_in_TD_DATA,
video_in_TD_HS,
video_in_TD_VS,
video_in_clk27_reset,
video_in_TD_RESET,
video_in_overflow_flag);
output clk_100k_clk;
output clk_100mhz_clk;
input clk_50mhz_in_clk;
output pixel_clk_clk;
output polygon_ctrl_clk_clk;
input reset_reset_n;
input video_in_TD_CLK27;
input [7:0] video_in_TD_DATA;
input video_in_TD_HS;
input video_in_TD_VS;
input video_in_clk27_reset;
output video_in_TD_RESET;
output video_in_overflow_flag;
endmodule | module Raster_Laser_Projector (
clk_100k_clk,
clk_100mhz_clk,
clk_50mhz_in_clk,
pixel_clk_clk,
polygon_ctrl_clk_clk,
reset_reset_n,
video_in_TD_CLK27,
video_in_TD_DATA,
video_in_TD_HS,
video_in_TD_VS,
video_in_clk27_reset,
video_in_TD_RESET,
video_in_overflow_flag); |
output clk_100k_clk;
output clk_100mhz_clk;
input clk_50mhz_in_clk;
output pixel_clk_clk;
output polygon_ctrl_clk_clk;
input reset_reset_n;
input video_in_TD_CLK27;
input [7:0] video_in_TD_DATA;
input video_in_TD_HS;
input video_in_TD_VS;
input video_in_clk27_reset;
output video_in_TD_RESET;
output video_in_overflow_flag;
endmodule | 1 |
137,777 | data/full_repos/permissive/80246680/src/Video_In/Raster_Laser_Projector_bb.v | 80,246,680 | Raster_Laser_Projector_bb.v | v | 11 | 32 | [] | [] | [] | [(2, 10)] | null | data/verilator_xmls/c7387352-b651-4072-baf0-30ae7ce92432.xml | null | 300,558 | module | module Raster_Laser_Projector (
clk_50mhz_in_clk,
pixel_clk_clk,
reset_reset_n);
input clk_50mhz_in_clk;
output pixel_clk_clk;
input reset_reset_n;
endmodule | module Raster_Laser_Projector (
clk_50mhz_in_clk,
pixel_clk_clk,
reset_reset_n); |
input clk_50mhz_in_clk;
output pixel_clk_clk;
input reset_reset_n;
endmodule | 1 |
137,779 | data/full_repos/permissive/80257330/alu.v | 80,257,330 | alu.v | v | 16 | 49 | [] | [] | [] | null | line:8: before: "assign" | data/verilator_xmls/69496cdb-cd10-4673-b4db-96ddebce7cc7.xml | null | 300,593 | module | module alu (input1, input2, aluselect, dataout);
input [15:0] input1,input2;
input [1:0] aluselect;
output reg[15:0] dataout;
always @(aluselect)
begin
if (aluselect == 2'b00) begin
assign dataout = input1|input2;
end else if (aluselect == 2'b01) begin
assign dataout = input1&input2;
end else if (aluselect == 2'b10) begin
assign dataout = input1+input2;
end
end
endmodule | module alu (input1, input2, aluselect, dataout); |
input [15:0] input1,input2;
input [1:0] aluselect;
output reg[15:0] dataout;
always @(aluselect)
begin
if (aluselect == 2'b00) begin
assign dataout = input1|input2;
end else if (aluselect == 2'b01) begin
assign dataout = input1&input2;
end else if (aluselect == 2'b10) begin
assign dataout = input1+input2;
end
end
endmodule | 0 |
137,780 | data/full_repos/permissive/80257330/controlUnit.v | 80,257,330 | controlUnit.v | v | 118 | 93 | [] | [] | [] | [(1, 117)] | null | data/verilator_xmls/d8315be8-b8cd-4389-ac69-1093b8e1cbc7.xml | null | 300,594 | module | module controlunit(opcode,aluselect,isImmediate,writeEnable,readMem,writeMem,jump,push,pop);
input [3:0] opcode;
output reg [1:0] aluselect;
output reg isImmediate,writeEnable,readMem,writeMem,jump,push,pop;
initial begin
readMem<=0;
writeMem<=0;
aluselect<=2'b00;
isImmediate<=0;
writeEnable<=0;
jump<=0;
push<=0;
pop<=0;
end
always @(opcode) begin
if(opcode==4'h0) begin
jump<=0;
isImmediate<=0;
aluselect<=2'b00;
readMem<=0;
writeMem<=0;
writeEnable<=1;
push<=0;
pop<=0;
end else if (opcode==4'h1) begin
jump<=0;
aluselect<=2'b00;
isImmediate<=1;
readMem<=0;
writeMem<=0;
writeEnable<=1;
push<=0;
pop<=0;
end else if (opcode==4'h2) begin
jump<=0;
isImmediate<=0;
aluselect<=2'b01;
readMem<=0;
writeMem<=0;
writeEnable<=1;
push<=0;
pop<=0;
end else if (opcode==4'h3) begin
jump<=0;
aluselect<=2'b01;
isImmediate<=1;
writeEnable<=1;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h4) begin
jump<=0;
isImmediate<=0;
aluselect<=2'b10;
writeEnable<=1;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h5) begin
jump<=0;
isImmediate<=1;
aluselect<=2'b10;
writeEnable<=1;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h6) begin
writeEnable<=0;
isImmediate<=0;
jump<=1;
aluselect<=2'b11;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h7) begin
jump<=0;
isImmediate<=0;
readMem<=1;
aluselect<=2'b11;
writeEnable<=1;
writeMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h8) begin
jump<=0;
writeMem<=1;
isImmediate<=0;
aluselect<=2'b11;
writeEnable<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h9) begin
jump<=0;
writeMem<=0;
isImmediate<=0;
aluselect<=2'b11;
writeEnable<=0;
readMem<=0;
push<=1;
pop<=0;
end else if (opcode==4'ha) begin
jump<=0;
writeMem<=0;
isImmediate<=0;
aluselect<=2'b11;
writeEnable<=1;
readMem<=0;
push<=0;
pop<=1;
end
end
endmodule | module controlunit(opcode,aluselect,isImmediate,writeEnable,readMem,writeMem,jump,push,pop); |
input [3:0] opcode;
output reg [1:0] aluselect;
output reg isImmediate,writeEnable,readMem,writeMem,jump,push,pop;
initial begin
readMem<=0;
writeMem<=0;
aluselect<=2'b00;
isImmediate<=0;
writeEnable<=0;
jump<=0;
push<=0;
pop<=0;
end
always @(opcode) begin
if(opcode==4'h0) begin
jump<=0;
isImmediate<=0;
aluselect<=2'b00;
readMem<=0;
writeMem<=0;
writeEnable<=1;
push<=0;
pop<=0;
end else if (opcode==4'h1) begin
jump<=0;
aluselect<=2'b00;
isImmediate<=1;
readMem<=0;
writeMem<=0;
writeEnable<=1;
push<=0;
pop<=0;
end else if (opcode==4'h2) begin
jump<=0;
isImmediate<=0;
aluselect<=2'b01;
readMem<=0;
writeMem<=0;
writeEnable<=1;
push<=0;
pop<=0;
end else if (opcode==4'h3) begin
jump<=0;
aluselect<=2'b01;
isImmediate<=1;
writeEnable<=1;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h4) begin
jump<=0;
isImmediate<=0;
aluselect<=2'b10;
writeEnable<=1;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h5) begin
jump<=0;
isImmediate<=1;
aluselect<=2'b10;
writeEnable<=1;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h6) begin
writeEnable<=0;
isImmediate<=0;
jump<=1;
aluselect<=2'b11;
writeMem<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h7) begin
jump<=0;
isImmediate<=0;
readMem<=1;
aluselect<=2'b11;
writeEnable<=1;
writeMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h8) begin
jump<=0;
writeMem<=1;
isImmediate<=0;
aluselect<=2'b11;
writeEnable<=0;
readMem<=0;
push<=0;
pop<=0;
end else if (opcode==4'h9) begin
jump<=0;
writeMem<=0;
isImmediate<=0;
aluselect<=2'b11;
writeEnable<=0;
readMem<=0;
push<=1;
pop<=0;
end else if (opcode==4'ha) begin
jump<=0;
writeMem<=0;
isImmediate<=0;
aluselect<=2'b11;
writeEnable<=1;
readMem<=0;
push<=0;
pop<=1;
end
end
endmodule | 0 |
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.