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137,408 | data/full_repos/permissive/78588001/lab1/barrel_shifter_tb.v | 78,588,001 | barrel_shifter_tb.v | v | 67 | 81 | [] | [] | [] | [(25, 65)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1/barrel_shifter_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1/barrel_shifter_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1/barrel_shifter_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/78588001/lab1/barrel_shifter_tb.v:35: Cannot find file containing module: \'barrel_shifter\'\n barrel_shifter uut (\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/barrel_shifter\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/barrel_shifter.v\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/barrel_shifter.sv\n barrel_shifter\n barrel_shifter.v\n barrel_shifter.sv\n obj_dir/barrel_shifter\n obj_dir/barrel_shifter.v\n obj_dir/barrel_shifter.sv\n%Warning-WIDTH: data/full_repos/permissive/78588001/lab1/barrel_shifter_tb.v:51: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance barrel_shifter_tb\n shift_amount = 1\'d1;\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,505 | module | module barrel_shifter_tb;
reg [7:0] d_in;
reg [2:0] shift_amount;
wire [7:0] d_out;
barrel_shifter uut (
.d_in(d_in),
.shift_amount(shift_amount),
.d_out(d_out)
);
initial begin
d_in = 0;
shift_amount = 0;
#100;
d_in = 8'b01000000;
shift_amount = 1'd1;
#100;
d_in = 8'b00010000;
shift_amount = 3'b010;
#100;
d_in = 8'b00100000;
shift_amount = 3'b100;
end
endmodule | module barrel_shifter_tb; |
reg [7:0] d_in;
reg [2:0] shift_amount;
wire [7:0] d_out;
barrel_shifter uut (
.d_in(d_in),
.shift_amount(shift_amount),
.d_out(d_out)
);
initial begin
d_in = 0;
shift_amount = 0;
#100;
d_in = 8'b01000000;
shift_amount = 1'd1;
#100;
d_in = 8'b00010000;
shift_amount = 3'b010;
#100;
d_in = 8'b00100000;
shift_amount = 3'b100;
end
endmodule | 0 |
137,409 | data/full_repos/permissive/78588001/lab1/bi_directional_shift.v | 78,588,001 | bi_directional_shift.v | v | 47 | 83 | [] | [] | [] | [(21, 46)] | null | null | 1: b"%Error: data/full_repos/permissive/78588001/lab1/bi_directional_shift.v:31: Cannot find file containing module: 'barrel_shifter'\nbarrel_shifter left_1(\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/barrel_shifter\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/barrel_shifter.v\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/barrel_shifter.sv\n barrel_shifter\n barrel_shifter.v\n barrel_shifter.sv\n obj_dir/barrel_shifter\n obj_dir/barrel_shifter.v\n obj_dir/barrel_shifter.sv\n%Error: data/full_repos/permissive/78588001/lab1/bi_directional_shift.v:37: Cannot find file containing module: 'right_barrel_shifter'\nright_barrel_shifter right_1 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 299,506 | module | module bi_directional_shift(
input [7:0] d_in,
input [2:0] shift_amount,
input shift_direction,
output wire [7:0] shifter_out
);
wire [7:0] l_d_out;
wire [7:0] r_d_out;
barrel_shifter left_1(
.d_in (d_in),
.shift_amount (shift_amount),
.d_out (l_d_out)
);
right_barrel_shifter right_1 (
.d_in (d_in),
.shift_amount (shift_amount),
.d_out (r_d_out)
);
assign shifter_out = (shift_direction) ? r_d_out : l_d_out;
endmodule | module bi_directional_shift(
input [7:0] d_in,
input [2:0] shift_amount,
input shift_direction,
output wire [7:0] shifter_out
); |
wire [7:0] l_d_out;
wire [7:0] r_d_out;
barrel_shifter left_1(
.d_in (d_in),
.shift_amount (shift_amount),
.d_out (l_d_out)
);
right_barrel_shifter right_1 (
.d_in (d_in),
.shift_amount (shift_amount),
.d_out (r_d_out)
);
assign shifter_out = (shift_direction) ? r_d_out : l_d_out;
endmodule | 0 |
137,410 | data/full_repos/permissive/78588001/lab1/right_barrel_shifter.v | 78,588,001 | right_barrel_shifter.v | v | 47 | 83 | [] | [] | [] | [(21, 46)] | null | data/verilator_xmls/19c407d7-b68c-4261-ab03-04e33a6e7f46.xml | null | 299,508 | module | module right_barrel_shifter(
input [7:0] d_in,
input [2:0] shift_amount,
output reg [7:0] d_out
);
always @* begin
case (shift_amount)
0 : d_out = d_in;
1 : d_out = {d_in[0], d_in[7:1]};
2 : d_out = {d_in[1:0], d_in[7:2]};
3 : d_out = {d_in[2:0], d_in[7:3]};
4 : d_out = {d_in[3:0], d_in[7:4]};
5 : d_out = {d_in[4:0], d_in[7:5]};
6 : d_out = {d_in[5:0], d_in[7:6]};
7 : d_out = 0;
endcase
end
endmodule | module right_barrel_shifter(
input [7:0] d_in,
input [2:0] shift_amount,
output reg [7:0] d_out
); |
always @* begin
case (shift_amount)
0 : d_out = d_in;
1 : d_out = {d_in[0], d_in[7:1]};
2 : d_out = {d_in[1:0], d_in[7:2]};
3 : d_out = {d_in[2:0], d_in[7:3]};
4 : d_out = {d_in[3:0], d_in[7:4]};
5 : d_out = {d_in[4:0], d_in[7:5]};
6 : d_out = {d_in[5:0], d_in[7:6]};
7 : d_out = 0;
endcase
end
endmodule | 0 |
137,411 | data/full_repos/permissive/78588001/lab1/right_barrel_shifter_tb.v | 78,588,001 | right_barrel_shifter_tb.v | v | 66 | 81 | [] | [] | [] | [(25, 64)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1/right_barrel_shifter_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1/right_barrel_shifter_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1/right_barrel_shifter_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/78588001/lab1/right_barrel_shifter_tb.v:35: Cannot find file containing module: \'right_barrel_shifter\'\n right_barrel_shifter uut (\n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/right_barrel_shifter\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/right_barrel_shifter.v\n data/full_repos/permissive/78588001/lab1,data/full_repos/permissive/78588001/right_barrel_shifter.sv\n right_barrel_shifter\n right_barrel_shifter.v\n right_barrel_shifter.sv\n obj_dir/right_barrel_shifter\n obj_dir/right_barrel_shifter.v\n obj_dir/right_barrel_shifter.sv\n%Warning-WIDTH: data/full_repos/permissive/78588001/lab1/right_barrel_shifter_tb.v:51: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance right_barrel_shifter_tb\n shift_amount = 1\'d1;\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,509 | module | module right_barrel_shifter_tb;
reg [7:0] d_in;
reg [2:0] shift_amount;
wire [7:0] d_out;
right_barrel_shifter uut (
.d_in(d_in),
.shift_amount(shift_amount),
.d_out(d_out)
);
initial begin
d_in = 0;
shift_amount = 0;
#100;
d_in = 8'b00000001;
shift_amount = 1'd1;
#100;
d_in = 8'b10000000;
shift_amount = 3'b010;
#100;
d_in = 8'b00010000;
shift_amount = 3'b100;
end
endmodule | module right_barrel_shifter_tb; |
reg [7:0] d_in;
reg [2:0] shift_amount;
wire [7:0] d_out;
right_barrel_shifter uut (
.d_in(d_in),
.shift_amount(shift_amount),
.d_out(d_out)
);
initial begin
d_in = 0;
shift_amount = 0;
#100;
d_in = 8'b00000001;
shift_amount = 1'd1;
#100;
d_in = 8'b10000000;
shift_amount = 3'b010;
#100;
d_in = 8'b00010000;
shift_amount = 3'b100;
end
endmodule | 0 |
137,412 | data/full_repos/permissive/78588001/lab1_reverse/bit_reverse.v | 78,588,001 | bit_reverse.v | v | 51 | 83 | [] | [] | [] | [(21, 51)] | null | data/verilator_xmls/9e3a0dbf-f998-4eeb-8ce8-4363d134e847.xml | null | 299,510 | module | module bit_reverse(
input wire [7:0] d_in,
output reg [7:0] d_out
);
integer i;
reg [3:0] reverse_count = 4'b1000;
reg [7:0] reversed;
always @*
begin
for(i=0;i<8;i=i+1)
begin
reversed[i] = d_in[7-i];
end
d_out = reversed>>(8-reverse_count);
end
endmodule | module bit_reverse(
input wire [7:0] d_in,
output reg [7:0] d_out
); |
integer i;
reg [3:0] reverse_count = 4'b1000;
reg [7:0] reversed;
always @*
begin
for(i=0;i<8;i=i+1)
begin
reversed[i] = d_in[7-i];
end
d_out = reversed>>(8-reverse_count);
end
endmodule | 0 |
137,413 | data/full_repos/permissive/78588001/lab1_reverse/bit_reverse_tb.v | 78,588,001 | bit_reverse_tb.v | v | 52 | 81 | [] | [] | [] | [(25, 50)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1_reverse/bit_reverse_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/78588001/lab1_reverse/bit_reverse_tb.v:34: Cannot find file containing module: \'bit_reverse\'\n bit_reverse uut (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bit_reverse\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bit_reverse.v\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bit_reverse.sv\n bit_reverse\n bit_reverse.v\n bit_reverse.sv\n obj_dir/bit_reverse\n obj_dir/bit_reverse.v\n obj_dir/bit_reverse.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,511 | module | module bit_reverse_tb;
reg [7:0] d_in;
wire [7:0] d_out;
bit_reverse uut (
.d_in(d_in),
.d_out(d_out)
);
initial begin
d_in = 0;
#100;
d_in = 8'b10100001;
end
endmodule | module bit_reverse_tb; |
reg [7:0] d_in;
wire [7:0] d_out;
bit_reverse uut (
.d_in(d_in),
.d_out(d_out)
);
initial begin
d_in = 0;
#100;
d_in = 8'b10100001;
end
endmodule | 0 |
137,414 | data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift.v | 78,588,001 | bi_directional_shift.v | v | 68 | 92 | [] | [] | [] | [(24, 67)] | null | null | 1: b"%Error: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift.v:37: Cannot find file containing module: 'bit_reverse'\nbit_reverse pre (\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bit_reverse\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bit_reverse.v\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bit_reverse.sv\n bit_reverse\n bit_reverse.v\n bit_reverse.sv\n obj_dir/bit_reverse\n obj_dir/bit_reverse.v\n obj_dir/bit_reverse.sv\n%Error: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift.v:42: Cannot find file containing module: 'mux2_1'\nmux2_1 mux1 (\n^~~~~~\n%Error: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift.v:49: Cannot find file containing module: 'left_barrel_shifter'\nleft_barrel_shifter left_1 (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift.v:55: Cannot find file containing module: 'bit_reverse'\nbit_reverse post (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift.v:60: Cannot find file containing module: 'mux2_1'\nmux2_1 mux2 (\n^~~~~~\n%Error: Exiting due to 5 error(s)\n" | 299,512 | module | module bi_directional_shift(
input wire [7:0] d_in,
input wire [2:0] shift_amount,
input wire shift_direction,
output wire [7:0] shifter_out
);
wire [7:0] pre_reverse;
wire [7:0] l_d_out;
wire [7:0] post_reverse;
wire [7:0] mux1_out;
bit_reverse pre (
.d_in (d_in),
.d_out (pre_reverse)
);
mux2_1 mux1 (
.input1 (d_in),
.input2 (pre_reverse),
.select (shift_direction),
.selected_out (mux1_out)
);
left_barrel_shifter left_1 (
.d_in (mux1_out),
.shift_amount (shift_amount),
.d_out (l_d_out)
);
bit_reverse post (
.d_in (l_d_out),
.d_out (post_reverse)
);
mux2_1 mux2 (
.input1 (l_d_out),
.input2 (post_reverse),
.select (shift_direction),
.selected_out (shifter_out)
);
endmodule | module bi_directional_shift(
input wire [7:0] d_in,
input wire [2:0] shift_amount,
input wire shift_direction,
output wire [7:0] shifter_out
); |
wire [7:0] pre_reverse;
wire [7:0] l_d_out;
wire [7:0] post_reverse;
wire [7:0] mux1_out;
bit_reverse pre (
.d_in (d_in),
.d_out (pre_reverse)
);
mux2_1 mux1 (
.input1 (d_in),
.input2 (pre_reverse),
.select (shift_direction),
.selected_out (mux1_out)
);
left_barrel_shifter left_1 (
.d_in (mux1_out),
.shift_amount (shift_amount),
.d_out (l_d_out)
);
bit_reverse post (
.d_in (l_d_out),
.d_out (post_reverse)
);
mux2_1 mux2 (
.input1 (l_d_out),
.input2 (post_reverse),
.select (shift_direction),
.selected_out (shifter_out)
);
endmodule | 0 |
137,415 | data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift_tb.v | 78,588,001 | bi_directional_shift_tb.v | v | 66 | 86 | [] | [] | [] | [(25, 64)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/78588001/lab1_reverse/bi_directional_shift_tb.v:36: Cannot find file containing module: \'bi_directional_shift\'\n bi_directional_shift uut (\n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bi_directional_shift\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bi_directional_shift.v\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/bi_directional_shift.sv\n bi_directional_shift\n bi_directional_shift.v\n bi_directional_shift.sv\n obj_dir/bi_directional_shift\n obj_dir/bi_directional_shift.v\n obj_dir/bi_directional_shift.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,513 | module | module bi_directional_shift_tb;
reg [7:0] d_in;
reg [2:0] shift_amount;
reg shift_direction;
wire [7:0] shifter_out;
bi_directional_shift uut (
.d_in(d_in),
.shift_amount(shift_amount),
.shift_direction(shift_direction),
.shifter_out(shifter_out)
);
initial begin
d_in = 0;
shift_amount = 0;
shift_direction = 0;
#100;
d_in = 8'b00010000;
shift_amount = 3'b010;
shift_direction = 1'b1;
#100;
d_in = 8'b00010000;
shift_amount = 3'b010;
shift_direction = 1'b0;
end
endmodule | module bi_directional_shift_tb; |
reg [7:0] d_in;
reg [2:0] shift_amount;
reg shift_direction;
wire [7:0] shifter_out;
bi_directional_shift uut (
.d_in(d_in),
.shift_amount(shift_amount),
.shift_direction(shift_direction),
.shifter_out(shifter_out)
);
initial begin
d_in = 0;
shift_amount = 0;
shift_direction = 0;
#100;
d_in = 8'b00010000;
shift_amount = 3'b010;
shift_direction = 1'b1;
#100;
d_in = 8'b00010000;
shift_amount = 3'b010;
shift_direction = 1'b0;
end
endmodule | 0 |
137,416 | data/full_repos/permissive/78588001/lab1_reverse/mux2_1.v | 78,588,001 | mux2_1.v | v | 31 | 83 | [] | [] | [] | [(21, 30)] | null | data/verilator_xmls/d18d1cf4-6b25-4d66-aa3b-59045ffefe06.xml | null | 299,516 | module | module mux2_1(
input wire [7:0] input1,
input wire [7:0] input2,
input wire select,
output wire [7:0] selected_out
);
assign selected_out = (select) ? input2 : input1;
endmodule | module mux2_1(
input wire [7:0] input1,
input wire [7:0] input2,
input wire select,
output wire [7:0] selected_out
); |
assign selected_out = (select) ? input2 : input1;
endmodule | 0 |
137,417 | data/full_repos/permissive/78588001/lab1_reverse/mux2_1_tb.v | 78,588,001 | mux2_1_tb.v | v | 64 | 81 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1_reverse/mux2_1_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab1_reverse/mux2_1_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/78588001/lab1_reverse/mux2_1_tb.v:36: Cannot find file containing module: \'mux2_1\'\n mux2_1 uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/mux2_1\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/mux2_1.v\n data/full_repos/permissive/78588001/lab1_reverse,data/full_repos/permissive/78588001/mux2_1.sv\n mux2_1\n mux2_1.v\n mux2_1.sv\n obj_dir/mux2_1\n obj_dir/mux2_1.v\n obj_dir/mux2_1.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,517 | module | module mux2_1_tb;
reg [7:0] input1;
reg [7:0] input2;
reg select;
wire [7:0] selected_out;
mux2_1 uut (
.input1(input1),
.input2(input2),
.select(select),
.selected_out(selected_out)
);
initial begin
input1 = 0;
input2 = 0;
select = 0;
#100;
input1 = 8'b10000001;
input2 = 8'b10101010;
select = 1'b1;
#100;
select = 1'b0;
end
endmodule | module mux2_1_tb; |
reg [7:0] input1;
reg [7:0] input2;
reg select;
wire [7:0] selected_out;
mux2_1 uut (
.input1(input1),
.input2(input2),
.select(select),
.selected_out(selected_out)
);
initial begin
input1 = 0;
input2 = 0;
select = 0;
#100;
input1 = 8'b10000001;
input2 = 8'b10101010;
select = 1'b1;
#100;
select = 1'b0;
end
endmodule | 0 |
137,418 | data/full_repos/permissive/78588001/lab2/comparator.v | 78,588,001 | comparator.v | v | 30 | 83 | [] | [] | [] | [(21, 29)] | null | data/verilator_xmls/98ae135c-3cb6-40f9-bf6b-698f9b96bd8e.xml | null | 299,518 | module | module comparator(
input wire [3:0] a_const,
input wire [3:0] b_var,
output wire d_out
);
assign d_out = (b_var < a_const) ? 1:((a_const==4'b1111) ? 1:0);
endmodule | module comparator(
input wire [3:0] a_const,
input wire [3:0] b_var,
output wire d_out
); |
assign d_out = (b_var < a_const) ? 1:((a_const==4'b1111) ? 1:0);
endmodule | 0 |
137,419 | data/full_repos/permissive/78588001/lab2/counter.v | 78,588,001 | counter.v | v | 38 | 83 | [] | [] | [] | [(21, 37)] | null | data/verilator_xmls/33348346-7203-49b6-bec6-95cb67773adf.xml | null | 299,519 | module | module counter(
input wire clk,
output reg [3:0] count
);
initial begin
count = 4'b0000;
end
always @(posedge clk)
begin
count = (count==4'b1111) ? 0:(count+1);
end
endmodule | module counter(
input wire clk,
output reg [3:0] count
); |
initial begin
count = 4'b0000;
end
always @(posedge clk)
begin
count = (count==4'b1111) ? 0:(count+1);
end
endmodule | 0 |
137,420 | data/full_repos/permissive/78588001/lab2/counter_tb.v | 78,588,001 | counter_tb.v | v | 56 | 81 | [] | [] | [] | [(25, 54)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/counter_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/counter_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/78588001/lab2/counter_tb.v:34: Cannot find file containing module: \'counter\'\n counter uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/counter\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/counter.v\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/counter.sv\n counter\n counter.v\n counter.sv\n obj_dir/counter\n obj_dir/counter.v\n obj_dir/counter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,520 | module | module counter_tb;
reg clk;
wire [3:0] counter;
counter uut (
.clk(clk),
.counter(counter)
);
initial begin
clk = 0;
#100;
forever begin
#5 clk=~clk;
end
end
endmodule | module counter_tb; |
reg clk;
wire [3:0] counter;
counter uut (
.clk(clk),
.counter(counter)
);
initial begin
clk = 0;
#100;
forever begin
#5 clk=~clk;
end
end
endmodule | 0 |
137,421 | data/full_repos/permissive/78588001/lab2/decoder2_4.v | 78,588,001 | decoder2_4.v | v | 51 | 82 | [] | [] | [] | [(21, 50)] | null | data/verilator_xmls/0b54bb27-c99e-42f3-93a5-7d1d56e15f67.xml | null | 299,521 | module | module decoder2_4(
input wire clk, reset,
input wire pwm,
output reg [3:0] an
);
localparam N = 18;
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
always @(posedge clk, posedge reset)
if (reset)
q_reg <= 0;
else
q_reg <= q_next;
assign q_next = q_reg + 1;
always @*
case (q_reg[N-1:N-2])
2'b00: an = {3'b111, ~pwm};
2'b01: an = {2'b11, ~pwm, 1'b1};
2'b10: an = {1'b1, ~pwm, 2'b11};
2'b11: an = {~pwm, 3'b111};
endcase
endmodule | module decoder2_4(
input wire clk, reset,
input wire pwm,
output reg [3:0] an
); |
localparam N = 18;
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
always @(posedge clk, posedge reset)
if (reset)
q_reg <= 0;
else
q_reg <= q_next;
assign q_next = q_reg + 1;
always @*
case (q_reg[N-1:N-2])
2'b00: an = {3'b111, ~pwm};
2'b01: an = {2'b11, ~pwm, 1'b1};
2'b10: an = {1'b1, ~pwm, 2'b11};
2'b11: an = {~pwm, 3'b111};
endcase
endmodule | 0 |
137,422 | data/full_repos/permissive/78588001/lab2/fourBitCounter.v | 78,588,001 | fourBitCounter.v | v | 35 | 83 | [] | [] | [] | [(21, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/78588001/lab2/fourBitCounter.v:30: Can't find definition of variable: 'enable'\n end else if (enable) begin\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 299,522 | module | module fourBitCounter(
input wire clk,
input wire reset,
output reg [3:0] counter_out
);
always @(posedge clk)
if (reset) begin
counter_out <= 4'b0 ;
end else if (enable) begin
counter_out <= counter_out + 1;
end
endmodule | module fourBitCounter(
input wire clk,
input wire reset,
output reg [3:0] counter_out
); |
always @(posedge clk)
if (reset) begin
counter_out <= 4'b0 ;
end else if (enable) begin
counter_out <= counter_out + 1;
end
endmodule | 0 |
137,423 | data/full_repos/permissive/78588001/lab2/freq_divider.v | 78,588,001 | freq_divider.v | v | 43 | 83 | [] | [] | [] | [(21, 42)] | null | data/verilator_xmls/8196d1e5-903e-45d3-bf5f-a4750c85fd94.xml | null | 299,523 | module | module freq_divider(
input wire clk,
output reg new_clk
);
reg [3:0] count;
initial begin
count = 0;
end
always@(posedge clk)
begin
count <= count+1;
end
always@*
begin
new_clk = (count==0) ? 1:0;
end
endmodule | module freq_divider(
input wire clk,
output reg new_clk
); |
reg [3:0] count;
initial begin
count = 0;
end
always@(posedge clk)
begin
count <= count+1;
end
always@*
begin
new_clk = (count==0) ? 1:0;
end
endmodule | 0 |
137,424 | data/full_repos/permissive/78588001/lab2/mux4_1.v | 78,588,001 | mux4_1.v | v | 40 | 83 | [] | [] | [] | [(21, 39)] | null | data/verilator_xmls/7e18a8bd-ab88-46a2-a42d-9440a42f533e.xml | null | 299,524 | module | module mux4_1(
input wire [3:0] input1,
input wire [3:0] input2,
input wire [3:0] input3,
input wire [3:0] input4,
input wire [1:0] select,
output reg [3:0] selected_out
);
always@*
case(select)
2'b00 : selected_out = input1;
2'b01 : selected_out = input2;
2'b10 : selected_out = input3;
2'b11 : selected_out = input4;
endcase
endmodule | module mux4_1(
input wire [3:0] input1,
input wire [3:0] input2,
input wire [3:0] input3,
input wire [3:0] input4,
input wire [1:0] select,
output reg [3:0] selected_out
); |
always@*
case(select)
2'b00 : selected_out = input1;
2'b01 : selected_out = input2;
2'b10 : selected_out = input3;
2'b11 : selected_out = input4;
endcase
endmodule | 0 |
137,425 | data/full_repos/permissive/78588001/lab2/mux4_1_tb.v | 78,588,001 | mux4_1_tb.v | v | 81 | 81 | [] | [] | [] | [(25, 79)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/mux4_1_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/mux4_1_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/mux4_1_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/mux4_1_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/78588001/lab2/mux4_1_tb.v:38: Cannot find file containing module: \'mux4_1\'\n mux4_1 uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/mux4_1\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/mux4_1.v\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/mux4_1.sv\n mux4_1\n mux4_1.v\n mux4_1.sv\n obj_dir/mux4_1\n obj_dir/mux4_1.v\n obj_dir/mux4_1.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,525 | module | module mux4_1_tb;
reg [3:0] input1;
reg [3:0] input2;
reg [3:0] input3;
reg [3:0] input4;
reg [1:0] select;
wire [3:0] selected_out;
mux4_1 uut (
.input1(input1),
.input2(input2),
.input3(input3),
.input4(input4),
.select(select),
.selected_out(selected_out)
);
initial begin
input1 = 0;
input2 = 0;
input3 = 0;
input4 = 0;
select = 0;
#100;
input1 = 4'b1000;
input2 = 4'b0100;
input3 = 4'b0010;
input4 = 4'b0001;
select = 2'b00;
#100;
select = 2'b01;
#100;
select = 2'b10;
#100;
select = 2'b11;
end
endmodule | module mux4_1_tb; |
reg [3:0] input1;
reg [3:0] input2;
reg [3:0] input3;
reg [3:0] input4;
reg [1:0] select;
wire [3:0] selected_out;
mux4_1 uut (
.input1(input1),
.input2(input2),
.input3(input3),
.input4(input4),
.select(select),
.selected_out(selected_out)
);
initial begin
input1 = 0;
input2 = 0;
input3 = 0;
input4 = 0;
select = 0;
#100;
input1 = 4'b1000;
input2 = 4'b0100;
input3 = 4'b0010;
input4 = 4'b0001;
select = 2'b00;
#100;
select = 2'b01;
#100;
select = 2'b10;
#100;
select = 2'b11;
end
endmodule | 0 |
137,426 | data/full_repos/permissive/78588001/lab2/PWM.v | 78,588,001 | PWM.v | v | 59 | 83 | [] | [] | [] | [(21, 58)] | null | null | 1: b"%Error: data/full_repos/permissive/78588001/lab2/PWM.v:35: Cannot find file containing module: 'freq_divider'\nfreq_divider freq1 (\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/freq_divider\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/freq_divider.v\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/freq_divider.sv\n freq_divider\n freq_divider.v\n freq_divider.sv\n obj_dir/freq_divider\n obj_dir/freq_divider.v\n obj_dir/freq_divider.sv\n%Error: data/full_repos/permissive/78588001/lab2/PWM.v:40: Cannot find file containing module: 'counter'\ncounter counter1 (\n^~~~~~~\n%Error: data/full_repos/permissive/78588001/lab2/PWM.v:45: Cannot find file containing module: 'comparator'\ncomparator comp1 (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/78588001/lab2/PWM.v:51: Cannot find file containing module: 'decoder2_4'\ndecoder2_4 dec1 (\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 299,526 | module | module PWM(
input wire clk, reset,
input wire [3:0] duty_cycle,
output wire [7:0] sevenSegData,
output pwm,
output [3:0] an
);
wire new_clock;
wire [3:0] count;
assign sevenSegData = 8'b00100101;
freq_divider freq1 (
.clk (clk),
.new_clk (new_clock)
);
counter counter1 (
.clk (new_clock),
.count (count)
);
comparator comp1 (
.a_const (duty_cycle),
.b_var (count),
.d_out (pwm)
);
decoder2_4 dec1 (
.clk (clk),
.reset (reset),
.pwm (pwm),
.an (an)
);
endmodule | module PWM(
input wire clk, reset,
input wire [3:0] duty_cycle,
output wire [7:0] sevenSegData,
output pwm,
output [3:0] an
); |
wire new_clock;
wire [3:0] count;
assign sevenSegData = 8'b00100101;
freq_divider freq1 (
.clk (clk),
.new_clk (new_clock)
);
counter counter1 (
.clk (new_clock),
.count (count)
);
comparator comp1 (
.a_const (duty_cycle),
.b_var (count),
.d_out (pwm)
);
decoder2_4 dec1 (
.clk (clk),
.reset (reset),
.pwm (pwm),
.an (an)
);
endmodule | 0 |
137,427 | data/full_repos/permissive/78588001/lab2/PWM_tb.v | 78,588,001 | PWM_tb.v | v | 66 | 81 | [] | [] | [] | [(25, 64)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/PWM_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/PWM_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/PWM_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab2/PWM_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Error: data/full_repos/permissive/78588001/lab2/PWM_tb.v:35: Cannot find file containing module: \'PWM\'\n PWM uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/PWM\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/PWM.v\n data/full_repos/permissive/78588001/lab2,data/full_repos/permissive/78588001/PWM.sv\n PWM\n PWM.v\n PWM.sv\n obj_dir/PWM\n obj_dir/PWM.v\n obj_dir/PWM.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,527 | module | module PWM_tb;
reg clk;
reg [3:0] duty_cycle;
wire pwm;
PWM uut (
.clk(clk),
.duty_cycle(duty_cycle),
.pwm(pwm)
);
initial begin
clk = 0;
duty_cycle = 0;
#100;
forever begin
#5 clk=~clk;
end
end
initial begin
#1000;
duty_cycle = 4'b0011;
#1000;
duty_cycle = 4'b0111;
end
endmodule | module PWM_tb; |
reg clk;
reg [3:0] duty_cycle;
wire pwm;
PWM uut (
.clk(clk),
.duty_cycle(duty_cycle),
.pwm(pwm)
);
initial begin
clk = 0;
duty_cycle = 0;
#100;
forever begin
#5 clk=~clk;
end
end
initial begin
#1000;
duty_cycle = 4'b0011;
#1000;
duty_cycle = 4'b0111;
end
endmodule | 0 |
137,428 | data/full_repos/permissive/78588001/lab3/bin2sevenSeg.v | 78,588,001 | bin2sevenSeg.v | v | 108 | 89 | [] | [] | [] | [(21, 108)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/78588001/lab3/bin2sevenSeg.v:94: Operator ADD expects 4 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance bin2sevenSeg\n fullOutputCopy[11:8] = fullOutputCopy[11:8] + 2\'b11;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/78588001/lab3/bin2sevenSeg.v:98: Operator ADD expects 5 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance bin2sevenSeg\n fullOutputCopy[13:9] = fullOutputCopy[13:9] + 2\'b11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/78588001/lab3/bin2sevenSeg.v:96: Operator GTE expects 5 bits on the RHS, but RHS\'s CONST \'4\'h5\' generates 4 bits.\n : ... In instance bin2sevenSeg\n else if (fullOutputCopy[13:9] >= 4\'d5) \n ^~\n%Error: Exiting due to 3 warning(s)\n' | 299,529 | module | module bin2sevenSeg (
input wire clk,
input wire [13:0] d_in,
output reg [15:0] fullOutput,
output reg [3:0] segA,
output reg [3:0] segB,
output reg [3:0] segC,
output reg [3:0] segD,
output reg [13:0] d_out
);
reg [13:0] d_inCopy;
reg [15:0] fullOutputCopy;
reg copyDone;
initial begin
fullOutput = 0;
segA = 0;
segB = 0;
segC = 0;
segD = 0;
d_inCopy = 0;
end
integer i;
always @(d_in)
begin
for(i=0;i<14;i=i+1)
begin
d_inCopy[i] = d_in[i];
end
d_out = d_inCopy;
copyDone = 1'b1;
end
always @(posedge copyDone)
begin
for(i=0;i<14;i=i+1)
begin
case (fullOutputCopy[3:0])
4'b0000: fullOutputCopy[3:0] <= 4'b0000;
4'b0001: fullOutputCopy[3:0] <= 4'b0001;
4'b0010: fullOutputCopy[3:0] <= 4'b0010;
4'b0011: fullOutputCopy[3:0] <= 4'b0011;
4'b0100: fullOutputCopy[3:0] <= 4'b0100;
4'b0101: fullOutputCopy[3:0] <= 4'b1000;
4'b0110: fullOutputCopy[3:0] <= 4'b1001;
4'b0111: fullOutputCopy[3:0] <= 4'b1010;
4'b1000: fullOutputCopy[3:0] <= 4'b1011;
4'b1001: fullOutputCopy[3:0] <= 4'b1100;
default: fullOutputCopy[3:0] <= 4'b0000;
endcase
case (fullOutputCopy[7:4])
4'b0000: fullOutputCopy[7:4] <= 4'b0000;
4'b0001: fullOutputCopy[7:4] <= 4'b0001;
4'b0010: fullOutputCopy[7:4] <= 4'b0010;
4'b0011: fullOutputCopy[7:4] <= 4'b0011;
4'b0100: fullOutputCopy[7:4] <= 4'b0100;
4'b0101: fullOutputCopy[7:4] <= 4'b1000;
4'b0110: fullOutputCopy[7:4] <= 4'b1001;
4'b0111: fullOutputCopy[7:4] <= 4'b1010;
4'b1000: fullOutputCopy[7:4] <= 4'b1011;
4'b1001: fullOutputCopy[7:4] <= 4'b1100;
default: fullOutputCopy[7:4] <= 4'b0000;
endcase
if (fullOutputCopy[11:8] >= 4'd5)
begin
fullOutputCopy[11:8] = fullOutputCopy[11:8] + 2'b11;
end
else if (fullOutputCopy[13:9] >= 4'd5)
begin
fullOutputCopy[13:9] = fullOutputCopy[13:9] + 2'b11;
end
fullOutputCopy[0] = d_out[13];
d_out = d_out << 1;
fullOutputCopy = fullOutputCopy << 1;
end
fullOutput = fullOutputCopy;
copyDone = 1'b0;
end
endmodule | module bin2sevenSeg (
input wire clk,
input wire [13:0] d_in,
output reg [15:0] fullOutput,
output reg [3:0] segA,
output reg [3:0] segB,
output reg [3:0] segC,
output reg [3:0] segD,
output reg [13:0] d_out
); |
reg [13:0] d_inCopy;
reg [15:0] fullOutputCopy;
reg copyDone;
initial begin
fullOutput = 0;
segA = 0;
segB = 0;
segC = 0;
segD = 0;
d_inCopy = 0;
end
integer i;
always @(d_in)
begin
for(i=0;i<14;i=i+1)
begin
d_inCopy[i] = d_in[i];
end
d_out = d_inCopy;
copyDone = 1'b1;
end
always @(posedge copyDone)
begin
for(i=0;i<14;i=i+1)
begin
case (fullOutputCopy[3:0])
4'b0000: fullOutputCopy[3:0] <= 4'b0000;
4'b0001: fullOutputCopy[3:0] <= 4'b0001;
4'b0010: fullOutputCopy[3:0] <= 4'b0010;
4'b0011: fullOutputCopy[3:0] <= 4'b0011;
4'b0100: fullOutputCopy[3:0] <= 4'b0100;
4'b0101: fullOutputCopy[3:0] <= 4'b1000;
4'b0110: fullOutputCopy[3:0] <= 4'b1001;
4'b0111: fullOutputCopy[3:0] <= 4'b1010;
4'b1000: fullOutputCopy[3:0] <= 4'b1011;
4'b1001: fullOutputCopy[3:0] <= 4'b1100;
default: fullOutputCopy[3:0] <= 4'b0000;
endcase
case (fullOutputCopy[7:4])
4'b0000: fullOutputCopy[7:4] <= 4'b0000;
4'b0001: fullOutputCopy[7:4] <= 4'b0001;
4'b0010: fullOutputCopy[7:4] <= 4'b0010;
4'b0011: fullOutputCopy[7:4] <= 4'b0011;
4'b0100: fullOutputCopy[7:4] <= 4'b0100;
4'b0101: fullOutputCopy[7:4] <= 4'b1000;
4'b0110: fullOutputCopy[7:4] <= 4'b1001;
4'b0111: fullOutputCopy[7:4] <= 4'b1010;
4'b1000: fullOutputCopy[7:4] <= 4'b1011;
4'b1001: fullOutputCopy[7:4] <= 4'b1100;
default: fullOutputCopy[7:4] <= 4'b0000;
endcase
if (fullOutputCopy[11:8] >= 4'd5)
begin
fullOutputCopy[11:8] = fullOutputCopy[11:8] + 2'b11;
end
else if (fullOutputCopy[13:9] >= 4'd5)
begin
fullOutputCopy[13:9] = fullOutputCopy[13:9] + 2'b11;
end
fullOutputCopy[0] = d_out[13];
d_out = d_out << 1;
fullOutputCopy = fullOutputCopy << 1;
end
fullOutput = fullOutputCopy;
copyDone = 1'b0;
end
endmodule | 0 |
137,429 | data/full_repos/permissive/78588001/lab3/bin2sevenSeg_tb.v | 78,588,001 | bin2sevenSeg_tb.v | v | 65 | 81 | [] | [] | [] | [(25, 63)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/bin2sevenSeg_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/78588001/lab3/bin2sevenSeg_tb.v:40: Cannot find file containing module: \'bin2sevenSeg\'\n bin2sevenSeg uut (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/bin2sevenSeg\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/bin2sevenSeg.v\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/bin2sevenSeg.sv\n bin2sevenSeg\n bin2sevenSeg.v\n bin2sevenSeg.sv\n obj_dir/bin2sevenSeg\n obj_dir/bin2sevenSeg.v\n obj_dir/bin2sevenSeg.sv\n%Warning-WIDTH: data/full_repos/permissive/78588001/lab3/bin2sevenSeg_tb.v:60: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance bin2sevenSeg_tb\n d_in = 4\'d11;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,530 | module | module bin2sevenSeg_tb;
reg clk;
reg [13:0] d_in;
wire [15:0] fullOutput;
wire [3:0] segA;
wire [3:0] segB;
wire [3:0] segC;
wire [3:0] segD;
wire [13:0] d_out;
bin2sevenSeg uut (
.clk(clk),
.d_in(d_in),
.fullOutput(fullOutput),
.segA(segA),
.segB(segB),
.segC(segC),
.segD(segD),
.d_out(d_out)
);
initial begin
clk = 0;
d_in = 0;
#100;
d_in = 4'd11;
end
endmodule | module bin2sevenSeg_tb; |
reg clk;
reg [13:0] d_in;
wire [15:0] fullOutput;
wire [3:0] segA;
wire [3:0] segB;
wire [3:0] segC;
wire [3:0] segD;
wire [13:0] d_out;
bin2sevenSeg uut (
.clk(clk),
.d_in(d_in),
.fullOutput(fullOutput),
.segA(segA),
.segB(segB),
.segC(segC),
.segD(segD),
.d_out(d_out)
);
initial begin
clk = 0;
d_in = 0;
#100;
d_in = 4'd11;
end
endmodule | 0 |
137,430 | data/full_repos/permissive/78588001/lab3/car_detector.v | 78,588,001 | car_detector.v | v | 99 | 83 | [] | [] | [] | [(21, 98)] | null | data/verilator_xmls/9e770328-90ba-4587-9f56-fae43724e5af.xml | null | 299,531 | module | module car_detector(
input wire clk, res,
input wire sensorA,
input wire sensorB,
output wire [3:0] car_count
);
localparam abUnblocked=2'b00, aBlocked=2'b01, abBlocked=2'b10, bBlocked=2'b11;
reg [1:0] current_state;
reg increase, decrease;
reg [3:0] count = 0;
initial begin
increase = 0;
decrease = 0;
current_state = 0;
end
always@(posedge clk, posedge res) begin
if (res)
current_state <= abUnblocked;
else
begin
increase <= 0;
decrease <= 0;
case(current_state)
abUnblocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
end
aBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
decrease <= 1;
end
abBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
bBlocked: if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
increase <= 1;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
default: current_state <= abUnblocked;
endcase
if(increase)
count <= count + 1'b1;
else if(decrease)
count <= count - 1'b1;
end
end
assign car_count = count;
endmodule | module car_detector(
input wire clk, res,
input wire sensorA,
input wire sensorB,
output wire [3:0] car_count
); |
localparam abUnblocked=2'b00, aBlocked=2'b01, abBlocked=2'b10, bBlocked=2'b11;
reg [1:0] current_state;
reg increase, decrease;
reg [3:0] count = 0;
initial begin
increase = 0;
decrease = 0;
current_state = 0;
end
always@(posedge clk, posedge res) begin
if (res)
current_state <= abUnblocked;
else
begin
increase <= 0;
decrease <= 0;
case(current_state)
abUnblocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
end
aBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
decrease <= 1;
end
abBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
bBlocked: if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
increase <= 1;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
default: current_state <= abUnblocked;
endcase
if(increase)
count <= count + 1'b1;
else if(decrease)
count <= count - 1'b1;
end
end
assign car_count = count;
endmodule | 0 |
137,431 | data/full_repos/permissive/78588001/lab3/car_detector_tb.v | 78,588,001 | car_detector_tb.v | v | 88 | 81 | [] | [] | [] | [(25, 86)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #102;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/78588001/lab3/car_detector_tb.v:37: Cannot find file containing module: \'car_detector\'\n car_detector uut (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/car_detector\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/car_detector.v\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/car_detector.sv\n car_detector\n car_detector.v\n car_detector.sv\n obj_dir/car_detector\n obj_dir/car_detector.v\n obj_dir/car_detector.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,532 | module | module car_detector_tb;
reg clk;
reg res;
reg sensorA;
reg sensorB;
wire [3:0] car_count;
car_detector uut (
.clk(clk),
.res(res),
.sensorA(sensorA),
.sensorB(sensorB),
.car_count(car_count)
);
initial begin
forever begin
#5 clk = ~clk;
end
end
initial begin
clk = 0;
res = 0;
sensorA = 0;
sensorB = 0;
#102;
res = 1'b1;
#5;
res = 1'b0;
#50;
sensorA = 1'b1;
#50;
sensorB = 1'b1;
#50;
sensorA = 1'b0;
#50;
sensorB = 1'b0;
#100;
sensorB = 1'b1;
#50;
sensorA = 1'b1;
#50;
sensorB = 1'b0;
#50;
sensorA = 1'b0;
end
endmodule | module car_detector_tb; |
reg clk;
reg res;
reg sensorA;
reg sensorB;
wire [3:0] car_count;
car_detector uut (
.clk(clk),
.res(res),
.sensorA(sensorA),
.sensorB(sensorB),
.car_count(car_count)
);
initial begin
forever begin
#5 clk = ~clk;
end
end
initial begin
clk = 0;
res = 0;
sensorA = 0;
sensorB = 0;
#102;
res = 1'b1;
#5;
res = 1'b0;
#50;
sensorA = 1'b1;
#50;
sensorB = 1'b1;
#50;
sensorA = 1'b0;
#50;
sensorB = 1'b0;
#100;
sensorB = 1'b1;
#50;
sensorA = 1'b1;
#50;
sensorB = 1'b0;
#50;
sensorA = 1'b0;
end
endmodule | 0 |
137,432 | data/full_repos/permissive/78588001/lab3/sevenSegValue.v | 78,588,001 | sevenSegValue.v | v | 28 | 57 | [] | [] | [] | [(2, 27)] | null | data/verilator_xmls/ae9d3130-0b8b-4b77-81a1-5ae289c41fd3.xml | null | 299,534 | module | module sevenSegValue (
input wire [3:0] d_in,
output reg [3:0] an,
output reg [7:0] sseg
);
always @*
begin
case(d_in)
4'b0000: sseg[7:0] = 8'b00000011;
4'b0001: sseg[7:0] = 8'b10011111;
4'b0010: sseg[7:0] = 8'b00100101;
4'b0011: sseg[7:0] = 8'b00001101;
4'b0100: sseg[7:0] = 8'b10011001;
4'b0101: sseg[7:0] = 8'b01001001;
4'b0110: sseg[7:0] = 8'b01000001;
4'b0111: sseg[7:0] = 8'b00011111;
4'b1000: sseg[7:0] = 8'b00000001;
4'b1001: sseg[7:0] = 8'b00001001;
default: sseg[7:0] = 8'b01110001;
endcase
an = 4'b1110;
end
endmodule | module sevenSegValue (
input wire [3:0] d_in,
output reg [3:0] an,
output reg [7:0] sseg
); |
always @*
begin
case(d_in)
4'b0000: sseg[7:0] = 8'b00000011;
4'b0001: sseg[7:0] = 8'b10011111;
4'b0010: sseg[7:0] = 8'b00100101;
4'b0011: sseg[7:0] = 8'b00001101;
4'b0100: sseg[7:0] = 8'b10011001;
4'b0101: sseg[7:0] = 8'b01001001;
4'b0110: sseg[7:0] = 8'b01000001;
4'b0111: sseg[7:0] = 8'b00011111;
4'b1000: sseg[7:0] = 8'b00000001;
4'b1001: sseg[7:0] = 8'b00001001;
default: sseg[7:0] = 8'b01110001;
endcase
an = 4'b1110;
end
endmodule | 0 |
137,433 | data/full_repos/permissive/78588001/lab3/top.v | 78,588,001 | top.v | v | 66 | 82 | [] | [] | [] | [(21, 65)] | null | null | 1: b"%Error: data/full_repos/permissive/78588001/lab3/top.v:34: Cannot find file containing module: 'debouncer'\ndebouncer dbA (\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/debouncer\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/debouncer.v\n data/full_repos/permissive/78588001/lab3,data/full_repos/permissive/78588001/debouncer.sv\n debouncer\n debouncer.v\n debouncer.sv\n obj_dir/debouncer\n obj_dir/debouncer.v\n obj_dir/debouncer.sv\n%Error: data/full_repos/permissive/78588001/lab3/top.v:42: Cannot find file containing module: 'debouncer'\ndebouncer dbB (\n^~~~~~~~~\n%Error: data/full_repos/permissive/78588001/lab3/top.v:50: Cannot find file containing module: 'car_detector'\ncar_detector count1(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/78588001/lab3/top.v:59: Cannot find file containing module: 'sevenSegValue'\nsevenSegValue brd1(\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 299,535 | module | module top(
input wire clk, reset,
input wire sensorA,
input wire sensorB,
output wire sensorAdb,
output wire sensorBdb,
output wire [3:0] enable,
output wire [7:0] sseg
);
wire [3:0] counter;
debouncer dbA (
.clk (clk),
.reset (reset),
.sw (sensorA),
.db (sensorAdb)
);
debouncer dbB (
.clk (clk),
.reset (reset),
.sw (sensorB),
.db (sensorBdb)
);
car_detector count1(
.clk (clk),
.res (reset),
.sensorA (sensorAdb),
.sensorB (sensorBdb),
.car_count (counter)
);
sevenSegValue brd1(
.d_in (counter),
.an (enable),
.sseg (sseg)
);
endmodule | module top(
input wire clk, reset,
input wire sensorA,
input wire sensorB,
output wire sensorAdb,
output wire sensorBdb,
output wire [3:0] enable,
output wire [7:0] sseg
); |
wire [3:0] counter;
debouncer dbA (
.clk (clk),
.reset (reset),
.sw (sensorA),
.db (sensorAdb)
);
debouncer dbB (
.clk (clk),
.reset (reset),
.sw (sensorB),
.db (sensorBdb)
);
car_detector count1(
.clk (clk),
.res (reset),
.sensorA (sensorAdb),
.sensorB (sensorBdb),
.car_count (counter)
);
sevenSegValue brd1(
.d_in (counter),
.an (enable),
.sseg (sseg)
);
endmodule | 0 |
137,434 | data/full_repos/permissive/78588001/lab4/asm_ex.v | 78,588,001 | asm_ex.v | v | 82 | 83 | [] | [] | [] | [(21, 81)] | null | data/verilator_xmls/054daff3-5ded-4176-a3ea-b83c2af434e2.xml | null | 299,536 | module | module asm_ex(
input clk, start, reset,
input [3:0] din,
output reg [6:0] dout,
output reg done_tick
);
reg [1:0] next_s, current_s;
reg [3:0] next_n, n;
reg [6:0] next_fn, fn;
localparam idle=2'b00, op=2'b01, done=2'b10;
always @(posedge clk, posedge reset)
if (reset)
begin
current_s <= idle;
n <= 0;
fn <= 1;
end
else
begin
current_s <= next_s;
n <= next_n;
fn <= next_fn;
end
always @* begin
next_s = current_s;
next_n = n;
next_fn = fn;
done_tick = 0;
dout = 0;
case(current_s)
idle:
begin
next_n=0;
next_fn=1;
next_s = (start) ? ((din==0) ? done:op) : idle;
end
op:
begin
next_n = n + 1;
next_fn = fn + 5;
next_s = (n==din) ? done : op;
end
done:
begin
done_tick = 1'b1;
dout = fn;
next_s = idle;
end
default: next_s = idle;
endcase
end
endmodule | module asm_ex(
input clk, start, reset,
input [3:0] din,
output reg [6:0] dout,
output reg done_tick
); |
reg [1:0] next_s, current_s;
reg [3:0] next_n, n;
reg [6:0] next_fn, fn;
localparam idle=2'b00, op=2'b01, done=2'b10;
always @(posedge clk, posedge reset)
if (reset)
begin
current_s <= idle;
n <= 0;
fn <= 1;
end
else
begin
current_s <= next_s;
n <= next_n;
fn <= next_fn;
end
always @* begin
next_s = current_s;
next_n = n;
next_fn = fn;
done_tick = 0;
dout = 0;
case(current_s)
idle:
begin
next_n=0;
next_fn=1;
next_s = (start) ? ((din==0) ? done:op) : idle;
end
op:
begin
next_n = n + 1;
next_fn = fn + 5;
next_s = (n==din) ? done : op;
end
done:
begin
done_tick = 1'b1;
dout = fn;
next_s = idle;
end
default: next_s = idle;
endcase
end
endmodule | 0 |
137,435 | data/full_repos/permissive/78588001/lab4/top_asm_ex.v | 78,588,001 | top_asm_ex.v | v | 47 | 83 | [] | [] | [] | [(21, 46)] | null | null | 1: b"%Error: data/full_repos/permissive/78588001/lab4/top_asm_ex.v:31: Cannot find file containing module: 'asm_ex'\nasm_ex uut(\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/78588001/lab4,data/full_repos/permissive/78588001/asm_ex\n data/full_repos/permissive/78588001/lab4,data/full_repos/permissive/78588001/asm_ex.v\n data/full_repos/permissive/78588001/lab4,data/full_repos/permissive/78588001/asm_ex.sv\n asm_ex\n asm_ex.v\n asm_ex.sv\n obj_dir/asm_ex\n obj_dir/asm_ex.v\n obj_dir/asm_ex.sv\n%Error: data/full_repos/permissive/78588001/lab4/top_asm_ex.v:40: Cannot find file containing module: 'sevenSegValue'\nsevenSegValue uut1(\n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 299,538 | module | module top_asm_ex(
input reset, clk,
input [4:0] sw,
output [3:0] an,
output [7:0] sseg,
output [0:0] led
);
wire [6:0] dout;
asm_ex uut(
.clk (clk),
.start (sw[4]),
.reset (reset),
.din (sw[3:0]),
.dout(dout),
.done_tick (led)
);
sevenSegValue uut1(
.d_in(dout),
.an(an),
.sseg(sseg)
);
endmodule | module top_asm_ex(
input reset, clk,
input [4:0] sw,
output [3:0] an,
output [7:0] sseg,
output [0:0] led
); |
wire [6:0] dout;
asm_ex uut(
.clk (clk),
.start (sw[4]),
.reset (reset),
.din (sw[3:0]),
.dout(dout),
.done_tick (led)
);
sevenSegValue uut1(
.d_in(dout),
.an(an),
.sseg(sseg)
);
endmodule | 0 |
137,436 | data/full_repos/permissive/78589716/bench/verilog/t_myla.v | 78,589,716 | t_myla.v | v | 275 | 88 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:4: Cannot find include file: myla.vh\n`include "myla.vh" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78589716/bench/verilog,data/full_repos/permissive/78589716/myla.vh\n data/full_repos/permissive/78589716/bench/verilog,data/full_repos/permissive/78589716/myla.vh.v\n data/full_repos/permissive/78589716/bench/verilog,data/full_repos/permissive/78589716/myla.vh.sv\n myla.vh\n myla.vh.v\n myla.vh.sv\n obj_dir/myla.vh\n obj_dir/myla.vh.v\n obj_dir/myla.vh.sv\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:8: Define or directive not defined: \'`DBITS\'\n parameter DBITS = `DBITS;\n ^~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:8: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter DBITS = `DBITS;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:9: Define or directive not defined: \'`QBITS\'\n parameter QBITS = `QBITS;\n ^~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:9: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter QBITS = `QBITS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:52: Unsupported: Ignoring delay on this delayed statement.\n #50 CLK_O <= ~CLK_O;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:60: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:60: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:68: Define or directive not defined: \'`LAQDATA\'\n ADR_O <= `LAQDATA;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:68: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ADR_O <= `LAQDATA;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:72: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:72: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:77: Define or directive not defined: \'`LAQDATA\'\n ADR_O <= `LAQDATA;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ADR_O <= `LAQDATA;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:79: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:79: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:81: Define or directive not defined: \'`LAQSTAT\'\n ADR_O <= `LAQSTAT;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ADR_O <= `LAQSTAT;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:85: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:85: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:93: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wtf.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:94: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:98: Define or directive not defined: \'`LAQSTAT\'\n ADR_O <= `LAQSTAT;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ADR_O <= `LAQSTAT;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:104: Unsupported: wait statements\n wait(CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:105: Unsupported: wait statements\n wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:113: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:113: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:115: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:115: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:116: Define or directive not defined: \'`LAQSTAT\'\n ADR_O <= `LAQSTAT;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:116: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ADR_O <= `LAQSTAT;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:120: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:120: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:136: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:136: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:138: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:138: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:140: Define or directive not defined: \'`LAQSTAT\'\n ADR_O <= `LAQSTAT;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:140: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ADR_O <= `LAQSTAT;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:145: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:145: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:161: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:161: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:163: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:163: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:165: Define or directive not defined: \'`LAQDATA\'\n ADR_O <= `LAQDATA;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:165: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ADR_O <= `LAQDATA;\n ^\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:170: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:170: Unsupported: wait statements\n wait(CLK_O); wait(~CLK_O);\n ^~~~\n%Error: data/full_repos/permissive/78589716/bench/verilog/t_myla.v:174: Define or directive not defined: \'`DBITS\'\n if(DAT_I != `DBITS\'d5) begin\n ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 299,539 | module | module TEST_MYLA;
parameter DBITS = `DBITS;
parameter QBITS = `QBITS;
reg CLK_O;
reg RES_O;
reg ADR_O;
reg WE_O;
reg CYC_O;
reg STB_O;
wire ACK_I;
wire [DBITS-1:0] DAT_I;
reg [DBITS-1:0] CHAN_O;
reg GATE_O;
reg [15:0] STORY_O;
MYLA #(
.DBITS(DBITS),
.QBITS(QBITS)
) myla(
.CLK_I(CLK_O),
.RES_I(RES_O),
.ADR_I(ADR_O),
.WE_I(WE_O),
.CYC_I(CYC_O),
.STB_I(STB_O),
.ACK_O(ACK_I),
.DAT_O(DAT_I),
.CHAN_I(CHAN_O),
.GATE_I(GATE_O)
);
always begin
#50 CLK_O <= ~CLK_O;
end
task push_data;
input [DBITS-1:0] data;
begin
CHAN_O <= data;
GATE_O <= 1;
wait(CLK_O); wait(~CLK_O);
end
endtask
task check_data;
input [DBITS-1:0] expected;
input [DBITS-1:0] status_expected;
begin
ADR_O <= `LAQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I !== expected) begin
$display("Pattern mismatch on byte %d.", expected); $stop;
end
ADR_O <= `LAQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I !== status_expected) begin
$display("Unexpected status $%04X; did we read beyond end of queue?", DAT_I); $stop;
end
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
RES_O <= 0;
CLK_O <= 0;
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 0;
STB_O <= 0;
CHAN_O <= 0;
GATE_O <= 0;
wait(CLK_O);
wait(~CLK_O);
STORY_O <= 0;
RES_O <= 1;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h01) begin
$display("Expected queue to be empty."); $stop;
end
STORY_O <= 16'h0010;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(5);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h00) begin
$display("Expected queue to be neither full nor empty."); $stop;
end
STORY_O <= 16'h0020;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(5);
ADR_O <= `LAQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != `DBITS'd5) begin
$display("Head of the queue doesn't have the right data byte."); $stop;
end
STORY_O <= 16'h0030;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(1);
push_data(2);
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != `DBITS'd1) begin
$display("Expected 1 for first entry."); $stop;
end
ADR_O <= `LAQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQDATA;
WE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `DBITS'd2) begin
$display("Expected 2 for second byte."); $stop;
end
STORY_O <= 16'h0040;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(0);
push_data(1);
push_data(2);
push_data(3);
push_data(4);
push_data(5);
push_data(6);
push_data(7);
push_data(8);
push_data(9);
push_data(10);
push_data(11);
push_data(12);
push_data(13);
push_data(14);
push_data(15);
push_data(16);
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `LAQSF_FULL) begin
$display("Before popping first byte, queue must be full."); $stop;
end
check_data(0, 0);
check_data(1, 0); STORY_O <= 16'h0140;
check_data(2, 0); STORY_O <= 16'h0240;
check_data(3, 0); STORY_O <= 16'h0340;
check_data(4, 0); STORY_O <= 16'h0440;
check_data(5, 0); STORY_O <= 16'h0540;
check_data(6, 0); STORY_O <= 16'h0640;
check_data(7, 0); STORY_O <= 16'h0740;
check_data(8, 0); STORY_O <= 16'h0840;
check_data(9, 0); STORY_O <= 16'h0940;
check_data(10, 0); STORY_O <= 16'h0A40;
check_data(11, 0); STORY_O <= 16'h0B40;
check_data(12, 0); STORY_O <= 16'h0C40;
check_data(13, 0); STORY_O <= 16'h0D40;
check_data(14, `LAQSF_EMPTY);
STORY_O <= -1;
wait(CLK_O); wait(~CLK_O);
$stop;
end
endmodule | module TEST_MYLA; |
parameter DBITS = `DBITS;
parameter QBITS = `QBITS;
reg CLK_O;
reg RES_O;
reg ADR_O;
reg WE_O;
reg CYC_O;
reg STB_O;
wire ACK_I;
wire [DBITS-1:0] DAT_I;
reg [DBITS-1:0] CHAN_O;
reg GATE_O;
reg [15:0] STORY_O;
MYLA #(
.DBITS(DBITS),
.QBITS(QBITS)
) myla(
.CLK_I(CLK_O),
.RES_I(RES_O),
.ADR_I(ADR_O),
.WE_I(WE_O),
.CYC_I(CYC_O),
.STB_I(STB_O),
.ACK_O(ACK_I),
.DAT_O(DAT_I),
.CHAN_I(CHAN_O),
.GATE_I(GATE_O)
);
always begin
#50 CLK_O <= ~CLK_O;
end
task push_data;
input [DBITS-1:0] data;
begin
CHAN_O <= data;
GATE_O <= 1;
wait(CLK_O); wait(~CLK_O);
end
endtask
task check_data;
input [DBITS-1:0] expected;
input [DBITS-1:0] status_expected;
begin
ADR_O <= `LAQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I !== expected) begin
$display("Pattern mismatch on byte %d.", expected); $stop;
end
ADR_O <= `LAQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I !== status_expected) begin
$display("Unexpected status $%04X; did we read beyond end of queue?", DAT_I); $stop;
end
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
RES_O <= 0;
CLK_O <= 0;
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 0;
STB_O <= 0;
CHAN_O <= 0;
GATE_O <= 0;
wait(CLK_O);
wait(~CLK_O);
STORY_O <= 0;
RES_O <= 1;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h01) begin
$display("Expected queue to be empty."); $stop;
end
STORY_O <= 16'h0010;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(5);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h00) begin
$display("Expected queue to be neither full nor empty."); $stop;
end
STORY_O <= 16'h0020;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(5);
ADR_O <= `LAQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != `DBITS'd5) begin
$display("Head of the queue doesn't have the right data byte."); $stop;
end
STORY_O <= 16'h0030;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(1);
push_data(2);
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != `DBITS'd1) begin
$display("Expected 1 for first entry."); $stop;
end
ADR_O <= `LAQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQDATA;
WE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `DBITS'd2) begin
$display("Expected 2 for second byte."); $stop;
end
STORY_O <= 16'h0040;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
push_data(0);
push_data(1);
push_data(2);
push_data(3);
push_data(4);
push_data(5);
push_data(6);
push_data(7);
push_data(8);
push_data(9);
push_data(10);
push_data(11);
push_data(12);
push_data(13);
push_data(14);
push_data(15);
push_data(16);
GATE_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `LAQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `LAQSF_FULL) begin
$display("Before popping first byte, queue must be full."); $stop;
end
check_data(0, 0);
check_data(1, 0); STORY_O <= 16'h0140;
check_data(2, 0); STORY_O <= 16'h0240;
check_data(3, 0); STORY_O <= 16'h0340;
check_data(4, 0); STORY_O <= 16'h0440;
check_data(5, 0); STORY_O <= 16'h0540;
check_data(6, 0); STORY_O <= 16'h0640;
check_data(7, 0); STORY_O <= 16'h0740;
check_data(8, 0); STORY_O <= 16'h0840;
check_data(9, 0); STORY_O <= 16'h0940;
check_data(10, 0); STORY_O <= 16'h0A40;
check_data(11, 0); STORY_O <= 16'h0B40;
check_data(12, 0); STORY_O <= 16'h0C40;
check_data(13, 0); STORY_O <= 16'h0D40;
check_data(14, `LAQSF_EMPTY);
STORY_O <= -1;
wait(CLK_O); wait(~CLK_O);
$stop;
end
endmodule | 2 |
137,437 | data/full_repos/permissive/78589716/rtl/verilog/myla.v | 78,589,716 | myla.v | v | 70 | 76 | [] | [] | [] | [(34, 96)] | null | null | 1: b'%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:4: Cannot find include file: myla.vh\n`include "myla.vh" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78589716/rtl/verilog,data/full_repos/permissive/78589716/myla.vh\n data/full_repos/permissive/78589716/rtl/verilog,data/full_repos/permissive/78589716/myla.vh.v\n data/full_repos/permissive/78589716/rtl/verilog,data/full_repos/permissive/78589716/myla.vh.sv\n myla.vh\n myla.vh.v\n myla.vh.sv\n obj_dir/myla.vh\n obj_dir/myla.vh.v\n obj_dir/myla.vh.sv\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:21: Define or directive not defined: \'`DBITS\'\n parameter DBITS = `DBITS;\n ^~~~~~\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter DBITS = `DBITS;\n ^\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:22: Define or directive not defined: \'`QBITS\'\n parameter QBITS = `QBITS;\n ^~~~~~\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:22: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter QBITS = `QBITS;\n ^\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:45: Define or directive not defined: \'`LAQSTAT\'\n wire laqstat_addressed = (ADR_I == `LAQSTAT) & ack & ~WE_I;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire laqstat_addressed = (ADR_I == `LAQSTAT) & ack & ~WE_I;\n ^\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:46: Define or directive not defined: \'`LAQDATA\'\n wire laqdata_addressed = (ADR_I == `LAQDATA) & ack & ~WE_I;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire laqdata_addressed = (ADR_I == `LAQDATA) & ack & ~WE_I;\n ^\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:47: Define or directive not defined: \'`LAQDATA\'\n wire laqpop_addressed = (ADR_I == `LAQDATA) & ack & WE_I & ~queue_empty;\n ^~~~~~~~\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:47: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire laqpop_addressed = (ADR_I == `LAQDATA) & ack & WE_I & ~queue_empty;\n ^\n%Error: data/full_repos/permissive/78589716/rtl/verilog/myla.v:48: Define or directive not defined: \'`DBITS\'\n wire [DBITS-1:0] laqstat_value = {`DBITS\'d0, queue_full, queue_empty};\n ^~~~~~\n%Error: Exiting due to 12 error(s)\n' | 299,540 | module | module MYLA(
input CLK_I,
input RES_I,
input ADR_I,
input WE_I,
input CYC_I,
input STB_I,
output ACK_O,
output [DBITS-1:0] DAT_O,
input [DBITS-1:0] CHAN_I,
input GATE_I
);
parameter DBITS = `DBITS;
parameter QBITS = `QBITS;
reg [DBITS-1:0] queue[0:(1<<QBITS)-1];
reg [QBITS-1:0] rp;
reg [QBITS-1:0] wp;
wire [QBITS-1:0] next_wp;
wire queue_full;
wire queue_empty;
reg ack;
assign next_wp = wp + 1;
assign queue_full = (next_wp == rp);
assign queue_empty = (rp == wp);
assign ACK_O = ack;
always @(posedge CLK_I) begin
if(~RES_I) begin
ack <= CYC_I & STB_I;
end else begin
ack <= 0;
end
end
wire laqstat_addressed = (ADR_I == `LAQSTAT) & ack & ~WE_I;
wire laqdata_addressed = (ADR_I == `LAQDATA) & ack & ~WE_I;
wire laqpop_addressed = (ADR_I == `LAQDATA) & ack & WE_I & ~queue_empty;
wire [DBITS-1:0] laqstat_value = {`DBITS'd0, queue_full, queue_empty};
wire [DBITS-1:0] laqdata_value = queue[rp];
wire [QBITS-1:0] next_rp = RES_I ? 0 : (laqpop_addressed ? rp+1 : rp);
assign DAT_O =
(laqstat_addressed ? laqstat_value : 0) |
(laqdata_addressed ? laqdata_value : 0);
always @(posedge CLK_I) begin
rp <= next_rp;
end
always @(posedge CLK_I) begin
if(~RES_I) begin
if(GATE_I & ~queue_full) begin
queue[wp] <= CHAN_I;
wp <= next_wp;
end
end else begin
wp <= 0;
end
end
endmodule | module MYLA(
input CLK_I,
input RES_I,
input ADR_I,
input WE_I,
input CYC_I,
input STB_I,
output ACK_O,
output [DBITS-1:0] DAT_O,
input [DBITS-1:0] CHAN_I,
input GATE_I
); |
parameter DBITS = `DBITS;
parameter QBITS = `QBITS;
reg [DBITS-1:0] queue[0:(1<<QBITS)-1];
reg [QBITS-1:0] rp;
reg [QBITS-1:0] wp;
wire [QBITS-1:0] next_wp;
wire queue_full;
wire queue_empty;
reg ack;
assign next_wp = wp + 1;
assign queue_full = (next_wp == rp);
assign queue_empty = (rp == wp);
assign ACK_O = ack;
always @(posedge CLK_I) begin
if(~RES_I) begin
ack <= CYC_I & STB_I;
end else begin
ack <= 0;
end
end
wire laqstat_addressed = (ADR_I == `LAQSTAT) & ack & ~WE_I;
wire laqdata_addressed = (ADR_I == `LAQDATA) & ack & ~WE_I;
wire laqpop_addressed = (ADR_I == `LAQDATA) & ack & WE_I & ~queue_empty;
wire [DBITS-1:0] laqstat_value = {`DBITS'd0, queue_full, queue_empty};
wire [DBITS-1:0] laqdata_value = queue[rp];
wire [QBITS-1:0] next_rp = RES_I ? 0 : (laqpop_addressed ? rp+1 : rp);
assign DAT_O =
(laqstat_addressed ? laqstat_value : 0) |
(laqdata_addressed ? laqdata_value : 0);
always @(posedge CLK_I) begin
rp <= next_rp;
end
always @(posedge CLK_I) begin
if(~RES_I) begin
if(GATE_I & ~queue_full) begin
queue[wp] <= CHAN_I;
wp <= next_wp;
end
end else begin
wp <= 0;
end
end
endmodule | 2 |
137,438 | data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v | 78,697,642 | Arria10_tb.v | v | 191 | 54 | [] | [] | [] | [(1, 190)] | null | null | 1: b'%Error: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:123: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("arria10_argInOuts.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:124: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, top0);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n #500\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78697642/bin/arria10_debuggers/testbenches/Arria10_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,542 | module | module Arria10_tb;
reg clk;
reg reset;
reg [6:0] addr;
wire [31:0] readdata;
reg [31:0] writedata;
wire io_rdata;
reg chipselect;
reg write;
reg read;
wire [5:0] awid;
wire [31:0] awuser;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire awlock;
wire [3:0] awcache;
wire [2:0] awprot;
wire [3:0] awqos;
wire awvalid;
reg awready;
wire [5:0] arid;
wire [31:0] aruser;
wire [31:0] araddr;
wire [7:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
wire arlock;
wire [3:0] arcache;
wire [2:0] arprot;
wire [3:0] arqos;
wire arvalid;
reg arready;
wire [511:0] wdata;
wire [63:0] wtrb;
wire wlast;
wire wvalid;
reg wready;
reg [5:0] rid;
reg [31:0] ruser;
reg [511:0] rdata;
reg [1:0] rresp;
reg rlast;
reg rvalid;
wire rready;
reg [5:0] bid;
reg [31:0] buser;
reg [1:0] bresp;
reg bvalid;
wire bready;
Top_DUT top0 (.clock (clk),
.reset (reset),
.io_raddr (clk),
.io_wen (write),
.io_waddr (clk),
.io_rdata (io_rdata),
.io_S_AVALON_readdata (readdata),
.io_S_AVALON_address (addr),
.io_S_AVALON_chipselect (chipselect),
.io_S_AVALON_write (write),
.io_S_AVALON_read (read),
.io_S_AVALON_writedata (writedata),
.io_M_AXI_0_AWID (awid),
.io_M_AXI_0_AWUSER (awuser),
.io_M_AXI_0_AWADDR (awaddr),
.io_M_AXI_0_AWLEN (awlen),
.io_M_AXI_0_AWSIZE (awsize),
.io_M_AXI_0_AWBURST (awburst),
.io_M_AXI_0_AWLOCK (awlock),
.io_M_AXI_0_AWCACHE (awcache),
.io_M_AXI_0_AWPROT (awprot),
.io_M_AXI_0_AWQOS (awqos),
.io_M_AXI_0_AWVALID (awvalid),
.io_M_AXI_0_AWREADY (awready),
.io_M_AXI_0_ARID (arid),
.io_M_AXI_0_ARUSER (aruser),
.io_M_AXI_0_ARADDR (araddr),
.io_M_AXI_0_ARLEN (arlen),
.io_M_AXI_0_ARSIZE (arsize),
.io_M_AXI_0_ARBURST (arburst),
.io_M_AXI_0_ARLOCK (arlock),
.io_M_AXI_0_ARCACHE (arcache),
.io_M_AXI_0_ARPROT (arprot),
.io_M_AXI_0_ARQOS (arqos),
.io_M_AXI_0_ARVALID (arvalid),
.io_M_AXI_0_ARREADY (arready),
.io_M_AXI_0_WDATA (wdata),
.io_M_AXI_0_WSTRB (wtrb),
.io_M_AXI_0_WLAST (wlast),
.io_M_AXI_0_WVALID (wvalid),
.io_M_AXI_0_WREADY (wready),
.io_M_AXI_0_RID (rid),
.io_M_AXI_0_RUSER (ruser),
.io_M_AXI_0_RDATA (rdata),
.io_M_AXI_0_RRESP (rresp),
.io_M_AXI_0_RLAST (rlast),
.io_M_AXI_0_RVALID (rvalid),
.io_M_AXI_0_RREADY (rready),
.io_M_AXI_0_BID (bid),
.io_M_AXI_0_BUSER (buser),
.io_M_AXI_0_BRESP (bresp),
.io_M_AXI_0_BVALID (bvalid),
.io_M_AXI_0_BREADY (bready));
initial
begin
$dumpfile("arria10_argInOuts.vcd");
$dumpvars(0, top0);
clk = 0;
chipselect = 1;
reset = 0;
write = 0;
addr = 0;
writedata = 0;
chipselect = 0;
write = 0;
read = 0;
awready = 0;
arready = 0;
wready = 0;
rid = 6'b0;
ruser = 32'b0;
rdata = 512'b0;
rresp = 2'b0;
rlast = 0;
rvalid = 0;
bid = 0;
buser = 32'b1;
bresp = 2'b0;
bvalid = 0;
#10
reset = 1;
#10
reset = 0;
awready = 1;
#10
wready = 1;
#20
addr = 10'h0;
writedata = 32'h1;
write = 1;
#10
write = 0;
#500
bvalid = 1;
bid = 6'b100000;
#5000
read = 1;
#30
addr = 10'h1;
$finish;
end
always
#5 clk = !clk;
endmodule | module Arria10_tb; |
reg clk;
reg reset;
reg [6:0] addr;
wire [31:0] readdata;
reg [31:0] writedata;
wire io_rdata;
reg chipselect;
reg write;
reg read;
wire [5:0] awid;
wire [31:0] awuser;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire awlock;
wire [3:0] awcache;
wire [2:0] awprot;
wire [3:0] awqos;
wire awvalid;
reg awready;
wire [5:0] arid;
wire [31:0] aruser;
wire [31:0] araddr;
wire [7:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
wire arlock;
wire [3:0] arcache;
wire [2:0] arprot;
wire [3:0] arqos;
wire arvalid;
reg arready;
wire [511:0] wdata;
wire [63:0] wtrb;
wire wlast;
wire wvalid;
reg wready;
reg [5:0] rid;
reg [31:0] ruser;
reg [511:0] rdata;
reg [1:0] rresp;
reg rlast;
reg rvalid;
wire rready;
reg [5:0] bid;
reg [31:0] buser;
reg [1:0] bresp;
reg bvalid;
wire bready;
Top_DUT top0 (.clock (clk),
.reset (reset),
.io_raddr (clk),
.io_wen (write),
.io_waddr (clk),
.io_rdata (io_rdata),
.io_S_AVALON_readdata (readdata),
.io_S_AVALON_address (addr),
.io_S_AVALON_chipselect (chipselect),
.io_S_AVALON_write (write),
.io_S_AVALON_read (read),
.io_S_AVALON_writedata (writedata),
.io_M_AXI_0_AWID (awid),
.io_M_AXI_0_AWUSER (awuser),
.io_M_AXI_0_AWADDR (awaddr),
.io_M_AXI_0_AWLEN (awlen),
.io_M_AXI_0_AWSIZE (awsize),
.io_M_AXI_0_AWBURST (awburst),
.io_M_AXI_0_AWLOCK (awlock),
.io_M_AXI_0_AWCACHE (awcache),
.io_M_AXI_0_AWPROT (awprot),
.io_M_AXI_0_AWQOS (awqos),
.io_M_AXI_0_AWVALID (awvalid),
.io_M_AXI_0_AWREADY (awready),
.io_M_AXI_0_ARID (arid),
.io_M_AXI_0_ARUSER (aruser),
.io_M_AXI_0_ARADDR (araddr),
.io_M_AXI_0_ARLEN (arlen),
.io_M_AXI_0_ARSIZE (arsize),
.io_M_AXI_0_ARBURST (arburst),
.io_M_AXI_0_ARLOCK (arlock),
.io_M_AXI_0_ARCACHE (arcache),
.io_M_AXI_0_ARPROT (arprot),
.io_M_AXI_0_ARQOS (arqos),
.io_M_AXI_0_ARVALID (arvalid),
.io_M_AXI_0_ARREADY (arready),
.io_M_AXI_0_WDATA (wdata),
.io_M_AXI_0_WSTRB (wtrb),
.io_M_AXI_0_WLAST (wlast),
.io_M_AXI_0_WVALID (wvalid),
.io_M_AXI_0_WREADY (wready),
.io_M_AXI_0_RID (rid),
.io_M_AXI_0_RUSER (ruser),
.io_M_AXI_0_RDATA (rdata),
.io_M_AXI_0_RRESP (rresp),
.io_M_AXI_0_RLAST (rlast),
.io_M_AXI_0_RVALID (rvalid),
.io_M_AXI_0_RREADY (rready),
.io_M_AXI_0_BID (bid),
.io_M_AXI_0_BUSER (buser),
.io_M_AXI_0_BRESP (bresp),
.io_M_AXI_0_BVALID (bvalid),
.io_M_AXI_0_BREADY (bready));
initial
begin
$dumpfile("arria10_argInOuts.vcd");
$dumpvars(0, top0);
clk = 0;
chipselect = 1;
reset = 0;
write = 0;
addr = 0;
writedata = 0;
chipselect = 0;
write = 0;
read = 0;
awready = 0;
arready = 0;
wready = 0;
rid = 6'b0;
ruser = 32'b0;
rdata = 512'b0;
rresp = 2'b0;
rlast = 0;
rvalid = 0;
bid = 0;
buser = 32'b1;
bresp = 2'b0;
bvalid = 0;
#10
reset = 1;
#10
reset = 0;
awready = 1;
#10
wready = 1;
#20
addr = 10'h0;
writedata = 32'h1;
write = 1;
#10
write = 0;
#500
bvalid = 1;
bid = 6'b100000;
#5000
read = 1;
#30
addr = 10'h1;
$finish;
end
always
#5 clk = !clk;
endmodule | 98 |
137,441 | data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/RetimeShiftRegister.sv | 78,697,642 | RetimeShiftRegister.sv | sv | 41 | 92 | [] | [] | [] | null | line:13: before: "]" | data/verilator_xmls/47c05f3f-bf92-4c97-8e33-63ea03cba016.xml | null | 299,550 | module | module RetimeShiftRegister
#(
parameter WIDTH = 1,
parameter STAGES = 1)
(
input clock,
input reset,
input flow,
input [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
integer i;
reg [WIDTH-1:0] sr[STAGES];
always @(posedge clock) begin
if (reset) begin
for(i=0; i<STAGES; i=i+1) begin
sr[i] <= {WIDTH{1'b0}};
end
end else begin
if (flow) begin
sr[0] <= in;
for(i=1; i<STAGES; i=i+1) begin
sr[i] <= sr[i-1];
end
end
end
end
always @(*) begin
out <= sr[STAGES-1];
end
endmodule | module RetimeShiftRegister
#(
parameter WIDTH = 1,
parameter STAGES = 1)
(
input clock,
input reset,
input flow,
input [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
); |
integer i;
reg [WIDTH-1:0] sr[STAGES];
always @(posedge clock) begin
if (reset) begin
for(i=0; i<STAGES; i=i+1) begin
sr[i] <= {WIDTH{1'b0}};
end
end else begin
if (flow) begin
sr[0] <= in;
for(i=1; i<STAGES; i=i+1) begin
sr[i] <= sr[i-1];
end
end
end
end
always @(*) begin
out <= sr[STAGES-1];
end
endmodule | 98 |
137,442 | data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ack_delay_logic/ack_delay_logic.sv | 78,697,642 | ack_delay_logic.sv | sv | 112 | 71 | [] | [] | [] | [(1, 109)] | null | data/verilator_xmls/df9b326c-d32e-4ae7-bf3b-9c76e97265b4.xml | null | 299,553 | module | module ack_delay_logic (
input wire [31:0] delay_ack_pio,
input wire ack_in,
output wire ack_delay_out,
input wire clk,
input wire reset
);
wire ack_loopback_delay_ver;
reg [1:0] state, next_state;
reg [31:0] ack_delay_counter;
reg start_ack_count;
reg en_ack_loopback;
reg reset_ack_count;
localparam [1:0] IDLE = 2'b00;
localparam [1:0] ACK_DELAY_COUNT = 2'b01;
localparam [1:0] ENABLE_ACK_LOOPBACK = 2'b10;
localparam [1:0] RESET_ACK_DELAY_COUNT = 2'b11;
always @(posedge clk or posedge reset) begin
if (reset) begin
ack_delay_counter <= 32'd0;
end
else begin
if (start_ack_count) begin
ack_delay_counter <= ack_delay_counter + 32'd1;
end
if (reset_ack_count) begin
ack_delay_counter <= 32'd0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always @* begin
case (state)
IDLE: begin
if (ack_in) begin
if (delay_ack_pio == 0) begin
next_state = ENABLE_ACK_LOOPBACK;
end else begin
next_state = ACK_DELAY_COUNT;
end
end
else begin
next_state = IDLE;
end
end
ACK_DELAY_COUNT: begin
if (ack_delay_counter == delay_ack_pio) begin
next_state = ENABLE_ACK_LOOPBACK;
end
else begin
next_state = ACK_DELAY_COUNT;
end
end
ENABLE_ACK_LOOPBACK: begin
if (~ack_in) begin
next_state = RESET_ACK_DELAY_COUNT;
end
else begin
next_state = ENABLE_ACK_LOOPBACK;
end
end
RESET_ACK_DELAY_COUNT: begin
next_state = IDLE;
end
default: begin
next_state = 2'bxx;
end
endcase
end
always @(next_state) begin
if (next_state == ACK_DELAY_COUNT) begin
start_ack_count <= 1'b1;
end else
start_ack_count <= 1'b0;
end
always @(next_state) begin
if (next_state == ENABLE_ACK_LOOPBACK) begin
en_ack_loopback <= 1'b1;
end else
en_ack_loopback <= 1'b0;
end
always @(next_state) begin
if (next_state == RESET_ACK_DELAY_COUNT || next_state == IDLE) begin
reset_ack_count <= 1'b1;
end else
reset_ack_count <= 1'b0;
end
assign ack_delay_out = (en_ack_loopback) ? ack_in : 1'b0;
endmodule | module ack_delay_logic (
input wire [31:0] delay_ack_pio,
input wire ack_in,
output wire ack_delay_out,
input wire clk,
input wire reset
); |
wire ack_loopback_delay_ver;
reg [1:0] state, next_state;
reg [31:0] ack_delay_counter;
reg start_ack_count;
reg en_ack_loopback;
reg reset_ack_count;
localparam [1:0] IDLE = 2'b00;
localparam [1:0] ACK_DELAY_COUNT = 2'b01;
localparam [1:0] ENABLE_ACK_LOOPBACK = 2'b10;
localparam [1:0] RESET_ACK_DELAY_COUNT = 2'b11;
always @(posedge clk or posedge reset) begin
if (reset) begin
ack_delay_counter <= 32'd0;
end
else begin
if (start_ack_count) begin
ack_delay_counter <= ack_delay_counter + 32'd1;
end
if (reset_ack_count) begin
ack_delay_counter <= 32'd0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always @* begin
case (state)
IDLE: begin
if (ack_in) begin
if (delay_ack_pio == 0) begin
next_state = ENABLE_ACK_LOOPBACK;
end else begin
next_state = ACK_DELAY_COUNT;
end
end
else begin
next_state = IDLE;
end
end
ACK_DELAY_COUNT: begin
if (ack_delay_counter == delay_ack_pio) begin
next_state = ENABLE_ACK_LOOPBACK;
end
else begin
next_state = ACK_DELAY_COUNT;
end
end
ENABLE_ACK_LOOPBACK: begin
if (~ack_in) begin
next_state = RESET_ACK_DELAY_COUNT;
end
else begin
next_state = ENABLE_ACK_LOOPBACK;
end
end
RESET_ACK_DELAY_COUNT: begin
next_state = IDLE;
end
default: begin
next_state = 2'bxx;
end
endcase
end
always @(next_state) begin
if (next_state == ACK_DELAY_COUNT) begin
start_ack_count <= 1'b1;
end else
start_ack_count <= 1'b0;
end
always @(next_state) begin
if (next_state == ENABLE_ACK_LOOPBACK) begin
en_ack_loopback <= 1'b1;
end else
en_ack_loopback <= 1'b0;
end
always @(next_state) begin
if (next_state == RESET_ACK_DELAY_COUNT || next_state == IDLE) begin
reset_ack_count <= 1'b1;
end else
reset_ack_count <= 1'b0;
end
assign ack_delay_out = (en_ack_loopback) ? ack_in : 1'b0;
endmodule | 98 |
137,443 | data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds/buslvds.v | 78,697,642 | buslvds.v | v | 79 | 79 | [] | [] | [] | [(19, 78)] | null | null | 1: b"%Error: data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds/buslvds.v:45: Cannot find file containing module: 'pdo'\npdo b2v_inst(\n^~~\n ... Looked in:\n data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds,data/full_repos/permissive/78697642/pdo\n data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds,data/full_repos/permissive/78697642/pdo.v\n data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds,data/full_repos/permissive/78697642/pdo.sv\n pdo\n pdo.v\n pdo.sv\n obj_dir/pdo\n obj_dir/pdo.v\n obj_dir/pdo.sv\n%Error: data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds/buslvds.v:58: Cannot find file containing module: 'twentynm_io_obuf'\ntwentynm_io_obuf b2v_inst3(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds/buslvds.v:65: Cannot find file containing module: 'twentynm_io_obuf'\ntwentynm_io_obuf b2v_inst4(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds/buslvds.v:72: Cannot find file containing module: 'diffin'\ndiffin b2v_inst5(\n^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 299,555 | module | module buslvds(
doutp,
oe,
din,
p,
n
);
input wire doutp;
input wire oe;
output wire din;
inout wire p;
inout wire n;
wire oebout;
wire oeout;
wire [0:0] SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
pdo b2v_inst(
.i(doutp),
.oein(oe),
.o(SYNTHESIZED_WIRE_2),
.obar(SYNTHESIZED_WIRE_3),
.oebout(oebout),
.oeout(oeout));
assign din = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_1 = ~oe;
twentynm_io_obuf b2v_inst3(
.i(SYNTHESIZED_WIRE_2),
.oe(oeout),
.o(p),
.obar());
twentynm_io_obuf b2v_inst4(
.i(SYNTHESIZED_WIRE_3),
.oe(oebout),
.o(n),
.obar());
diffin b2v_inst5(
.datain(p),
.datain_b(n),
.dataout(SYNTHESIZED_WIRE_0));
endmodule | module buslvds(
doutp,
oe,
din,
p,
n
); |
input wire doutp;
input wire oe;
output wire din;
inout wire p;
inout wire n;
wire oebout;
wire oeout;
wire [0:0] SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
pdo b2v_inst(
.i(doutp),
.oein(oe),
.o(SYNTHESIZED_WIRE_2),
.obar(SYNTHESIZED_WIRE_3),
.oebout(oebout),
.oeout(oeout));
assign din = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_1 = ~oe;
twentynm_io_obuf b2v_inst3(
.i(SYNTHESIZED_WIRE_2),
.oe(oeout),
.o(p),
.obar());
twentynm_io_obuf b2v_inst4(
.i(SYNTHESIZED_WIRE_3),
.oe(oebout),
.o(n),
.obar());
diffin b2v_inst5(
.datain(p),
.datain_b(n),
.dataout(SYNTHESIZED_WIRE_0));
endmodule | 98 |
137,444 | data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ILC/ghrd_10as066n2_ILC_bb.v | 78,697,642 | ghrd_10as066n2_ILC_bb.v | v | 13 | 60 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/0ee7204a-fbe8-4215-b3ed-f120c522a2d7.xml | null | 299,558 | module | module ghrd_10as066n2_ILC (
input wire [5:0] avmm_addr,
input wire [31:0] avmm_wrdata,
input wire avmm_write,
input wire avmm_read,
output wire [31:0] avmm_rddata,
input wire clk,
input wire [1:0] irq,
input wire reset_n
);
endmodule | module ghrd_10as066n2_ILC (
input wire [5:0] avmm_addr,
input wire [31:0] avmm_wrdata,
input wire avmm_write,
input wire avmm_read,
output wire [31:0] avmm_rddata,
input wire clk,
input wire [1:0] irq,
input wire reset_n
); |
endmodule | 98 |
137,445 | data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeASIC/build/designware_divmod.v | 78,697,642 | designware_divmod.v | v | 36 | 112 | [] | [] | [] | [(1, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeASIC/build/designware_divmod.v:17: Cannot find file containing module: 'DW_div_pipe'\nDW_div_pipe #(\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeASIC/build,data/full_repos/permissive/78697642/DW_div_pipe\n data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeASIC/build,data/full_repos/permissive/78697642/DW_div_pipe.v\n data/full_repos/permissive/78697642/spatial/core/resources/chiselgen/template-level/fringeASIC/build,data/full_repos/permissive/78697642/DW_div_pipe.sv\n DW_div_pipe\n DW_div_pipe.v\n DW_div_pipe.sv\n obj_dir/DW_div_pipe\n obj_dir/DW_div_pipe.v\n obj_dir/DW_div_pipe.sv\n%Error: Exiting due to 1 error(s)\n" | 299,563 | module | module designware_divmod(clock, reset, dividend, divisor, quot_out, rem_out);
parameter DIVIDEND_BIT_WIDTH = 16;
parameter DIVISOR_BIT_WIDTH = 16;
parameter SIGNED = 0;
parameter IS_DIV = 1;
parameter NUM_STAGES = 2;
input clock, reset;
input [DIVIDEND_BIT_WIDTH-1:0] dividend;
input [DIVISOR_BIT_WIDTH-1:0] divisor;
output [DIVIDEND_BIT_WIDTH-1:0] quot_out, rem_out;
wire divide_by_0;
DW_div_pipe #(
.a_width(DIVIDEND_BIT_WIDTH),
.b_width(DIVISOR_BIT_WIDTH),
.tc_mode(SIGNED),
.rem_mode(IS_DIV),
.num_stages(NUM_STAGES),
.stall_mode(1'b0),
.rst_mode(1)) div_pipe_inst (
.clk(clock),
.rst_n(reset),
.en(1'b1),
.a(dividend),
.b(divisor),
.quotient(quot_out),
.remainder(rem_out),
.divide_by_0(divide_by_0)
);
endmodule | module designware_divmod(clock, reset, dividend, divisor, quot_out, rem_out); |
parameter DIVIDEND_BIT_WIDTH = 16;
parameter DIVISOR_BIT_WIDTH = 16;
parameter SIGNED = 0;
parameter IS_DIV = 1;
parameter NUM_STAGES = 2;
input clock, reset;
input [DIVIDEND_BIT_WIDTH-1:0] dividend;
input [DIVISOR_BIT_WIDTH-1:0] divisor;
output [DIVIDEND_BIT_WIDTH-1:0] quot_out, rem_out;
wire divide_by_0;
DW_div_pipe #(
.a_width(DIVIDEND_BIT_WIDTH),
.b_width(DIVISOR_BIT_WIDTH),
.tc_mode(SIGNED),
.rem_mode(IS_DIV),
.num_stages(NUM_STAGES),
.stall_mode(1'b0),
.rst_mode(1)) div_pipe_inst (
.clk(clock),
.rst_n(reset),
.en(1'b1),
.a(dividend),
.b(divisor),
.quotient(quot_out),
.remainder(rem_out),
.divide_by_0(divide_by_0)
);
endmodule | 98 |
137,451 | data/full_repos/permissive/78777078/test_spmi.v | 78,777,078 | test_spmi.v | v | 83 | 54 | [] | [] | [] | [(3, 82)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:16: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SYSCLK/2) sysclk = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:17: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SYSCLK/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:39: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SYSCLK * 10);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:41: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SYSCLK * 50);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:46: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:48: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:56: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK/2) spmiclk = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:57: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:60: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SYSCLK * 50);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:66: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:74: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK/2) spmiclk = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:75: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SPMICLK/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78777078/test_spmi.v:78: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_SYSCLK * 50);\n ^\n%Error: data/full_repos/permissive/78777078/test_spmi.v:20: Cannot find file containing module: \'spmi\'\n spmi spmi_dut(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/78777078,data/full_repos/permissive/78777078/spmi\n data/full_repos/permissive/78777078,data/full_repos/permissive/78777078/spmi.v\n data/full_repos/permissive/78777078,data/full_repos/permissive/78777078/spmi.sv\n spmi\n spmi.v\n spmi.sv\n obj_dir/spmi\n obj_dir/spmi.v\n obj_dir/spmi.sv\n%Warning-WIDTH: data/full_repos/permissive/78777078/test_spmi.v:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h2f5\' generates 13 bits.\n : ... In instance test_spmi\n dat = 13\'h2F5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/78777078/test_spmi.v:54: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'13\'h1000\' generates 13 bits.\n : ... In instance test_spmi\n spmidat = dat & 13\'b1_0000_0000_0000 ? 1\'b1 : 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/78777078/test_spmi.v:54: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 bits.\n : ... In instance test_spmi\n spmidat = dat & 13\'b1_0000_0000_0000 ? 1\'b1 : 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/78777078/test_spmi.v:69: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h1a05\' generates 13 bits.\n : ... In instance test_spmi\n dat = 13\'h1A05;\n ^\n%Warning-WIDTH: data/full_repos/permissive/78777078/test_spmi.v:72: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'13\'h1000\' generates 13 bits.\n : ... In instance test_spmi\n spmidat = dat & 13\'b1_0000_0000_0000 ? 1\'b1 : 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/78777078/test_spmi.v:72: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 bits.\n : ... In instance test_spmi\n spmidat = dat & 13\'b1_0000_0000_0000 ? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 1 error(s), 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,572 | module | module test_spmi;
reg sysclk;
reg spmiclk;
reg spmidat;
reg reset;
reg fetched;
parameter PERIOD_SYSCLK = 12.5;
parameter PERIOD_SPMICLK = 45;
always begin
sysclk = 1'b0;
#(PERIOD_SYSCLK/2) sysclk = 1'b1;
#(PERIOD_SYSCLK/2);
end
spmi spmi_dut(
.sysclk(sysclk),
.spmiclk(spmiclk),
.spmidat(spmidat),
.reset(reset),
.packet(packet),
.valid(valid),
.fetched(fetched),
.overflow(overflow)
);
integer i;
integer dat;
initial begin
spmidat = 1'b0;
spmiclk = 1'b0;
reset = 1'b1;
#(PERIOD_SYSCLK * 10);
reset = 1'b0;
#(PERIOD_SYSCLK * 50);
spmidat = 1'b1;
#(PERIOD_SPMICLK);
spmidat = 1'b0;
#(PERIOD_SPMICLK);
dat = 13'h2F5;
for( i = 0; i < 13; i = i + 1 ) begin
spmiclk = 1'b0;
spmidat = dat & 13'b1_0000_0000_0000 ? 1'b1 : 1'b0;
dat = dat << 1;
#(PERIOD_SPMICLK/2) spmiclk = 1'b1;
#(PERIOD_SPMICLK/2);
end
#(PERIOD_SYSCLK * 50);
spmidat = 1'b1;
#(PERIOD_SPMICLK);
spmidat = 1'b0;
#(PERIOD_SPMICLK);
dat = 13'h1A05;
for( i = 0; i < 13; i = i + 1 ) begin
spmiclk = 1'b0;
spmidat = dat & 13'b1_0000_0000_0000 ? 1'b1 : 1'b0;
dat = dat << 1;
#(PERIOD_SPMICLK/2) spmiclk = 1'b1;
#(PERIOD_SPMICLK/2);
end
#(PERIOD_SYSCLK * 50);
end
endmodule | module test_spmi; |
reg sysclk;
reg spmiclk;
reg spmidat;
reg reset;
reg fetched;
parameter PERIOD_SYSCLK = 12.5;
parameter PERIOD_SPMICLK = 45;
always begin
sysclk = 1'b0;
#(PERIOD_SYSCLK/2) sysclk = 1'b1;
#(PERIOD_SYSCLK/2);
end
spmi spmi_dut(
.sysclk(sysclk),
.spmiclk(spmiclk),
.spmidat(spmidat),
.reset(reset),
.packet(packet),
.valid(valid),
.fetched(fetched),
.overflow(overflow)
);
integer i;
integer dat;
initial begin
spmidat = 1'b0;
spmiclk = 1'b0;
reset = 1'b1;
#(PERIOD_SYSCLK * 10);
reset = 1'b0;
#(PERIOD_SYSCLK * 50);
spmidat = 1'b1;
#(PERIOD_SPMICLK);
spmidat = 1'b0;
#(PERIOD_SPMICLK);
dat = 13'h2F5;
for( i = 0; i < 13; i = i + 1 ) begin
spmiclk = 1'b0;
spmidat = dat & 13'b1_0000_0000_0000 ? 1'b1 : 1'b0;
dat = dat << 1;
#(PERIOD_SPMICLK/2) spmiclk = 1'b1;
#(PERIOD_SPMICLK/2);
end
#(PERIOD_SYSCLK * 50);
spmidat = 1'b1;
#(PERIOD_SPMICLK);
spmidat = 1'b0;
#(PERIOD_SPMICLK);
dat = 13'h1A05;
for( i = 0; i < 13; i = i + 1 ) begin
spmiclk = 1'b0;
spmidat = dat & 13'b1_0000_0000_0000 ? 1'b1 : 1'b0;
dat = dat << 1;
#(PERIOD_SPMICLK/2) spmiclk = 1'b1;
#(PERIOD_SPMICLK/2);
end
#(PERIOD_SYSCLK * 50);
end
endmodule | 1 |
137,452 | data/full_repos/permissive/78823969/multipliers/src/rtl/mult.v | 78,823,969 | mult.v | v | 181 | 92 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(42, 176)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/78823969/multipliers/src/rtl/mult.v:112: Operator ASSIGNDLY expects 256 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n : ... In instance mult\n opb_reg <= {(OPB_WIDTH){1\'h0}};\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/78823969/multipliers/src/rtl/mult.v:156: Operator LTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'addr\' generates 8 bits.\n : ... In instance mult\n if ((addr >= OPA_BASE_ADDR) && (addr <= OPA_TOP_ADDR))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/78823969/multipliers/src/rtl/mult.v:171: Operator LTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'addr\' generates 8 bits.\n : ... In instance mult\n if ((addr >= PROD_BASE_ADDR) && (addr <= PROD_TOP_ADDR))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/78823969/multipliers/src/rtl/mult.v:156: Comparison is constant due to unsigned arithmetic\n : ... In instance mult\n if ((addr >= OPA_BASE_ADDR) && (addr <= OPA_TOP_ADDR))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 299,573 | module | module mult(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] addr,
input wire [(API_WIDTH - 1) : 0] write_data,
output wire [(API_WIDTH - 1) : 0] read_data
);
parameter API_WIDTH = 16;
parameter OPA_WIDTH = 256;
parameter OPB_WIDTH = 64;
localparam OPA_WORDS = OPA_WIDTH / API_WIDTH;
localparam OPA_BASE_ADDR = 8'h00;
localparam OPA_TOP_ADDR = (OPA_BASE_ADDR + OPA_WORDS - 1);
localparam OPB_WORDS = OPB_WIDTH / API_WIDTH;
localparam OPB_BASE_ADDR = 8'h40;
localparam OPB_TOP_ADDR = (OPB_BASE_ADDR + OPB_WORDS - 1);
localparam PROD_WIDTH = OPA_WIDTH + OPB_WIDTH;
localparam PROD_WORDS = PROD_WIDTH / API_WIDTH;
localparam PROD_BASE_ADDR = 8'h80;
localparam PROD_TOP_ADDR = (PROD_BASE_ADDR + PROD_WORDS - 1);
reg [(OPA_WIDTH - 1) : 0] opa_reg;
reg [(OPA_WIDTH - 1) : 0] opa_new;
reg opa_we;
reg [(OPA_WIDTH - 1) : 0] opb_reg;
reg [(OPA_WIDTH - 1) : 0] opb_new;
reg opb_we;
reg [(PROD_WIDTH - 1) : 0] prod_reg;
reg [(PROD_WIDTH - 1) : 0] prod_new;
reg [(API_WIDTH -1) : 0] tmp_read_data;
assign read_data = tmp_read_data;
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
opa_reg <= {(OPA_WIDTH){1'h0}};
opb_reg <= {(OPB_WIDTH){1'h0}};
prod_reg <= {(PROD_WIDTH){1'h0}};
end
else
begin
prod_reg <= prod_new;
if (opa_we)
opa_reg <= opa_new;
if (opb_we)
opb_reg <= opb_new;
end
end
always @*
begin : mult_logic
prod_new = opa_reg * opb_reg;
end
always @*
begin : api
tmp_read_data = {(API_WIDTH){1'h0}};
opa_new = opa_reg;
opa_we = 0;
opb_new = opb_reg;
opb_we = 0;
if (cs)
begin
if (we)
begin
if ((addr >= OPA_BASE_ADDR) && (addr <= OPA_TOP_ADDR))
begin
opa_new[API_WIDTH * (addr - OPA_BASE_ADDR) +: API_WIDTH] = write_data;
opa_we = 1;
end
if ((addr >= OPB_BASE_ADDR) && (addr <= OPB_TOP_ADDR))
begin
opb_new[API_WIDTH * (addr - OPB_BASE_ADDR) +: API_WIDTH] = write_data;
opb_we = 1;
end
end
else
begin
if ((addr >= PROD_BASE_ADDR) && (addr <= PROD_TOP_ADDR))
tmp_read_data = prod_reg[API_WIDTH * (addr - PROD_BASE_ADDR) +: API_WIDTH];
end
end
end
endmodule | module mult(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] addr,
input wire [(API_WIDTH - 1) : 0] write_data,
output wire [(API_WIDTH - 1) : 0] read_data
); |
parameter API_WIDTH = 16;
parameter OPA_WIDTH = 256;
parameter OPB_WIDTH = 64;
localparam OPA_WORDS = OPA_WIDTH / API_WIDTH;
localparam OPA_BASE_ADDR = 8'h00;
localparam OPA_TOP_ADDR = (OPA_BASE_ADDR + OPA_WORDS - 1);
localparam OPB_WORDS = OPB_WIDTH / API_WIDTH;
localparam OPB_BASE_ADDR = 8'h40;
localparam OPB_TOP_ADDR = (OPB_BASE_ADDR + OPB_WORDS - 1);
localparam PROD_WIDTH = OPA_WIDTH + OPB_WIDTH;
localparam PROD_WORDS = PROD_WIDTH / API_WIDTH;
localparam PROD_BASE_ADDR = 8'h80;
localparam PROD_TOP_ADDR = (PROD_BASE_ADDR + PROD_WORDS - 1);
reg [(OPA_WIDTH - 1) : 0] opa_reg;
reg [(OPA_WIDTH - 1) : 0] opa_new;
reg opa_we;
reg [(OPA_WIDTH - 1) : 0] opb_reg;
reg [(OPA_WIDTH - 1) : 0] opb_new;
reg opb_we;
reg [(PROD_WIDTH - 1) : 0] prod_reg;
reg [(PROD_WIDTH - 1) : 0] prod_new;
reg [(API_WIDTH -1) : 0] tmp_read_data;
assign read_data = tmp_read_data;
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
opa_reg <= {(OPA_WIDTH){1'h0}};
opb_reg <= {(OPB_WIDTH){1'h0}};
prod_reg <= {(PROD_WIDTH){1'h0}};
end
else
begin
prod_reg <= prod_new;
if (opa_we)
opa_reg <= opa_new;
if (opb_we)
opb_reg <= opb_new;
end
end
always @*
begin : mult_logic
prod_new = opa_reg * opb_reg;
end
always @*
begin : api
tmp_read_data = {(API_WIDTH){1'h0}};
opa_new = opa_reg;
opa_we = 0;
opb_new = opb_reg;
opb_we = 0;
if (cs)
begin
if (we)
begin
if ((addr >= OPA_BASE_ADDR) && (addr <= OPA_TOP_ADDR))
begin
opa_new[API_WIDTH * (addr - OPA_BASE_ADDR) +: API_WIDTH] = write_data;
opa_we = 1;
end
if ((addr >= OPB_BASE_ADDR) && (addr <= OPB_TOP_ADDR))
begin
opb_new[API_WIDTH * (addr - OPB_BASE_ADDR) +: API_WIDTH] = write_data;
opb_we = 1;
end
end
else
begin
if ((addr >= PROD_BASE_ADDR) && (addr <= PROD_TOP_ADDR))
tmp_read_data = prod_reg[API_WIDTH * (addr - PROD_BASE_ADDR) +: API_WIDTH];
end
end
end
endmodule | 1 |
137,453 | data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v | 78,823,969 | tb_mult.v | v | 330 | 115 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | null | line:114: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:95: Unsupported: Ignoring delay on this delayed statement.\n #CLK_HALF_PERIOD;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:110: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:145: Unsupported: Ignoring delay on this delayed statement.\n #(2 * CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:226: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:245: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:127: Can\'t find definition of \'addr\' in dotted variable: \'dut.addr\'\n $display("addr: 0x%02x, data = 0x%08x, cs = 0x%01x, we = 0x%01x", dut.addr, dut.write_data, dut.cs, dut.we);\n ^~~~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:127: Can\'t find definition of \'write_data\' in dotted variable: \'dut.write_data\'\n $display("addr: 0x%02x, data = 0x%08x, cs = 0x%01x, we = 0x%01x", dut.addr, dut.write_data, dut.cs, dut.we);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:127: Can\'t find definition of \'cs\' in dotted variable: \'dut.cs\'\n $display("addr: 0x%02x, data = 0x%08x, cs = 0x%01x, we = 0x%01x", dut.addr, dut.write_data, dut.cs, dut.we);\n ^~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:127: Can\'t find definition of \'we\' in dotted variable: \'dut.we\'\n $display("addr: 0x%02x, data = 0x%08x, cs = 0x%01x, we = 0x%01x", dut.addr, dut.write_data, dut.cs, dut.we);\n ^~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:128: Can\'t find definition of \'opa_reg\' in dotted variable: \'dut.opa_reg\'\n $display("operand a: 0x%064x, opa_we: 0x%01x", dut.opa_reg, dut.opa_we);\n ^~~~~~~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:128: Can\'t find definition of \'opa_we\' in dotted variable: \'dut.opa_we\'\n $display("operand a: 0x%064x, opa_we: 0x%01x", dut.opa_reg, dut.opa_we);\n ^~~~~~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:129: Can\'t find definition of \'opb_reg\' in dotted variable: \'dut.opb_reg\'\n $display("operand b: 0x%064x, opb_we: 0x%01x", dut.opb_reg, dut.opb_we);\n ^~~~~~~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:129: Can\'t find definition of \'opb_we\' in dotted variable: \'dut.opb_we\'\n $display("operand b: 0x%064x, opb_we: 0x%01x", dut.opb_reg, dut.opb_we);\n ^~~~~~\n%Error: data/full_repos/permissive/78823969/multipliers/src/tb/tb_mult.v:130: Can\'t find definition of \'prod_reg\' in dotted variable: \'dut.prod_reg\'\n $display("product: 0x%0128x", dut.prod_reg);\n ^~~~~~~~\n%Error: Exiting due to 9 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,574 | module | module tb_mult;
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter API_WIDTH = 16;
localparam OPA_WIDTH = 128;
localparam OPB_WIDTH = 128;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [(API_WIDTH - 1) : 0] tb_write_data;
wire [(API_WIDTH - 1) : 0] tb_read_data;
reg [(API_WIDTH - 1) : 0] read_data;
reg [255 : 0] result_data;
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
mult #(.API_WIDTH(API_WIDTH), .OPA_WIDTH(OPA_WIDTH), .OPB_WIDTH(OPB_WIDTH))
dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.addr(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("addr: 0x%02x, data = 0x%08x, cs = 0x%01x, we = 0x%01x", dut.addr, dut.write_data, dut.cs, dut.we);
$display("operand a: 0x%064x, opa_we: 0x%01x", dut.opa_reg, dut.opa_we);
$display("operand b: 0x%064x, opb_we: 0x%01x", dut.opb_reg, dut.opb_we);
$display("product: 0x%0128x", dut.prod_reg);
$display("");
end
endtask
task reset_dut;
begin
$display("TB: Resetting dut.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask
task display_test_results;
begin
$display("");
if (error_ctr == 0)
begin
$display("%02d test completed. All test cases completed successfully.", tc_ctr);
end
else
begin
$display("%02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h0;
tb_write_data = 16'h0;
end
endtask
task inc_tc_ctr;
tc_ctr = tc_ctr + 1;
endtask
task inc_error_ctr;
error_ctr = error_ctr + 1;
endtask
task write_word(input [7 : 0] address, input [(API_WIDTH - 1) : 0] word);
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask
task read_result;
begin : rd_res
integer i;
for (i = 0; i < 16 ; i = i + 1)
begin
read_word(i + 8'h80);
result_data[API_WIDTH * i +: API_WIDTH] = read_data;
end
end
endtask
task test_case1;
begin : tc1
integer i;
$display("TC1: Writing data into operand registers:");
inc_tc_ctr();
for (i = 0 ; i < 8 ; i = i + 1)
begin
write_word(i, 16'hffff);
write_word(i + 8'h40, 16'hfffd);
end
$display("");
$display("TC1: Reading out data from product registers:");
read_result();
if (result_data == 256'hfffdfffdfffdfffdfffdfffdfffdfffc00020002000200020002000200020003)
$display("TC1: SUCCESS. Multiplication correct.");
else
begin
$display("TC1: FAILURE. Multiplication not correct.");
inc_error_ctr();
end
$display("");
end
endtask
initial
begin : main
$display("*** Testbench for the multiplier started ***");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
test_case1();
dump_dut_state();
display_test_results();
$display("*** Multiplier testbench done. ***");
$finish;
end
endmodule | module tb_mult; |
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter API_WIDTH = 16;
localparam OPA_WIDTH = 128;
localparam OPB_WIDTH = 128;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [(API_WIDTH - 1) : 0] tb_write_data;
wire [(API_WIDTH - 1) : 0] tb_read_data;
reg [(API_WIDTH - 1) : 0] read_data;
reg [255 : 0] result_data;
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
mult #(.API_WIDTH(API_WIDTH), .OPA_WIDTH(OPA_WIDTH), .OPB_WIDTH(OPB_WIDTH))
dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.addr(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("addr: 0x%02x, data = 0x%08x, cs = 0x%01x, we = 0x%01x", dut.addr, dut.write_data, dut.cs, dut.we);
$display("operand a: 0x%064x, opa_we: 0x%01x", dut.opa_reg, dut.opa_we);
$display("operand b: 0x%064x, opb_we: 0x%01x", dut.opb_reg, dut.opb_we);
$display("product: 0x%0128x", dut.prod_reg);
$display("");
end
endtask
task reset_dut;
begin
$display("TB: Resetting dut.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask
task display_test_results;
begin
$display("");
if (error_ctr == 0)
begin
$display("%02d test completed. All test cases completed successfully.", tc_ctr);
end
else
begin
$display("%02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h0;
tb_write_data = 16'h0;
end
endtask
task inc_tc_ctr;
tc_ctr = tc_ctr + 1;
endtask
task inc_error_ctr;
error_ctr = error_ctr + 1;
endtask
task write_word(input [7 : 0] address, input [(API_WIDTH - 1) : 0] word);
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask
task read_result;
begin : rd_res
integer i;
for (i = 0; i < 16 ; i = i + 1)
begin
read_word(i + 8'h80);
result_data[API_WIDTH * i +: API_WIDTH] = read_data;
end
end
endtask
task test_case1;
begin : tc1
integer i;
$display("TC1: Writing data into operand registers:");
inc_tc_ctr();
for (i = 0 ; i < 8 ; i = i + 1)
begin
write_word(i, 16'hffff);
write_word(i + 8'h40, 16'hfffd);
end
$display("");
$display("TC1: Reading out data from product registers:");
read_result();
if (result_data == 256'hfffdfffdfffdfffdfffdfffdfffdfffc00020002000200020002000200020003)
$display("TC1: SUCCESS. Multiplication correct.");
else
begin
$display("TC1: FAILURE. Multiplication not correct.");
inc_error_ctr();
end
$display("");
end
endtask
initial
begin : main
$display("*** Testbench for the multiplier started ***");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
test_case1();
dump_dut_state();
display_test_results();
$display("*** Multiplier testbench done. ***");
$finish;
end
endmodule | 1 |
137,454 | data/full_repos/permissive/78967537/src/Source/32_bit_adder.v | 78,967,537 | 32_bit_adder.v | v | 25 | 68 | [] | [] | [] | [(7, 25)] | null | data/verilator_xmls/2e671c53-f31f-4ceb-adab-de738700f4fd.xml | null | 299,575 | module | module adder_32_bit(clock, en, reset, op1, op2, out);
input clock;
input en;
input reset;
input [31:0] op1;
input [31:0] op2;
output reg [31:0] out;
always @(posedge clock or negedge reset) begin
if(reset == 0) begin
out <= 0;
end else begin
out = op1 + op2;
end
end
endmodule | module adder_32_bit(clock, en, reset, op1, op2, out); |
input clock;
input en;
input reset;
input [31:0] op1;
input [31:0] op2;
output reg [31:0] out;
always @(posedge clock or negedge reset) begin
if(reset == 0) begin
out <= 0;
end else begin
out = op1 + op2;
end
end
endmodule | 0 |
137,455 | data/full_repos/permissive/78967537/src/Source/adder_32_bit.v | 78,967,537 | adder_32_bit.v | v | 16 | 68 | [] | [] | [] | [(7, 16)] | null | data/verilator_xmls/3857c2e4-6619-400b-b233-da28859fc1cf.xml | null | 299,576 | module | module adder_32_bit(op1, op2, out);
input [31:0] op1;
input [31:0] op2;
output [31:0] out;
assign out = op1 + op2;
endmodule | module adder_32_bit(op1, op2, out); |
input [31:0] op1;
input [31:0] op2;
output [31:0] out;
assign out = op1 + op2;
endmodule | 0 |
137,456 | data/full_repos/permissive/78967537/src/Source/clock.v | 78,967,537 | clock.v | v | 23 | 39 | [] | [] | [] | [(9, 22)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Source/clock.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-INFINITELOOP: data/full_repos/permissive/78967537/src/Source/clock.v:15: Infinite loop (condition always true)\n : ... In instance clock\n forever begin\n ^~~~~~~\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,577 | module | module clock(clk);
output reg clk;
initial begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end
endmodule | module clock(clk); |
output reg clk;
initial begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end
endmodule | 0 |
137,457 | data/full_repos/permissive/78967537/src/Source/control.v | 78,967,537 | control.v | v | 45 | 116 | [] | [] | [] | [(8, 45)] | null | data/verilator_xmls/8dcbbd2c-9a9a-4630-8348-7fbc8d2f2ef8.xml | null | 299,578 | module | module memory(clk, reset, instruct, reg_dest, branch, mem_read, mem_to_reg, mem_write, alu_op, alu_src, reg_write);
input wire clk;
input wire reset;
input wire [31:26] instruct;
output reg reg_dest;
output reg branch ;
output reg mem_read;
output reg mem_to_reg;
output reg mem_write;
output reg alu_op;
output reg alu_src;
output reg reg_write;
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
reg_dest = 0;
branch = 0;
mem_read = 0;
mem_to_reg = 0;
mem_write = 0;
alu_op = 0;
alu_src = 0;
reg_write = 0;
end else begin
reg_dest = 0;
branch = 0;
mem_read = 0;
mem_to_reg = 0;
mem_write = 0;
alu_op = 0;
alu_src = 0;
reg_write = 0;
end
end
endmodule | module memory(clk, reset, instruct, reg_dest, branch, mem_read, mem_to_reg, mem_write, alu_op, alu_src, reg_write); |
input wire clk;
input wire reset;
input wire [31:26] instruct;
output reg reg_dest;
output reg branch ;
output reg mem_read;
output reg mem_to_reg;
output reg mem_write;
output reg alu_op;
output reg alu_src;
output reg reg_write;
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
reg_dest = 0;
branch = 0;
mem_read = 0;
mem_to_reg = 0;
mem_write = 0;
alu_op = 0;
alu_src = 0;
reg_write = 0;
end else begin
reg_dest = 0;
branch = 0;
mem_read = 0;
mem_to_reg = 0;
mem_write = 0;
alu_op = 0;
alu_src = 0;
reg_write = 0;
end
end
endmodule | 0 |
137,458 | data/full_repos/permissive/78967537/src/Source/instruction_increment.v | 78,967,537 | instruction_increment.v | v | 13 | 88 | [] | [] | [] | [(7, 13)] | null | data/verilator_xmls/63cc90cd-2f52-47d7-8029-2d738c74728e.xml | null | 299,579 | module | module instruction_increment(instruction, next_instruction);
input [31:0] instruction;
output [31:0] next_instruction;
assign next_instruction = instruction + 1;
endmodule | module instruction_increment(instruction, next_instruction); |
input [31:0] instruction;
output [31:0] next_instruction;
assign next_instruction = instruction + 1;
endmodule | 0 |
137,459 | data/full_repos/permissive/78967537/src/Source/memory.v | 78,967,537 | memory.v | v | 51 | 133 | [] | [] | [] | [(7, 50)] | null | data/verilator_xmls/037b02fd-7250-4297-8bb2-9222c3619da4.xml | null | 299,580 | module | module memory(clk, reset, data_op, instruct_addr, data_addr, write_val, instruct_val, read_val);
parameter mem_size = 511;
input wire clk;
input wire reset;
input wire data_op;
input wire [31:0] instruct_addr;
input wire [31:0] data_addr;
input wire [31:0] write_val;
output reg [31:0] instruct_val;
output reg[31:0] read_val;
reg [31:0] mem [0:mem_size];
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
instruct_val <= 0;
read_val <= 0;
mem[0] = 5;
mem[1] = 5;
mem[2] = 5;
mem[3] = 5;
mem[4] = 5;
mem[5] = 5;
mem[6] = 5;
mem[7] = 5;
mem[8] = 5;
mem[9] = 5;
mem[10] = 5;
end else begin
instruct_val <= mem[instruct_addr];
if(data_op == 1) begin
read_val <= mem[data_addr];
end else begin
mem[data_addr] <= write_val;
end
end
end
endmodule | module memory(clk, reset, data_op, instruct_addr, data_addr, write_val, instruct_val, read_val); |
parameter mem_size = 511;
input wire clk;
input wire reset;
input wire data_op;
input wire [31:0] instruct_addr;
input wire [31:0] data_addr;
input wire [31:0] write_val;
output reg [31:0] instruct_val;
output reg[31:0] read_val;
reg [31:0] mem [0:mem_size];
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
instruct_val <= 0;
read_val <= 0;
mem[0] = 5;
mem[1] = 5;
mem[2] = 5;
mem[3] = 5;
mem[4] = 5;
mem[5] = 5;
mem[6] = 5;
mem[7] = 5;
mem[8] = 5;
mem[9] = 5;
mem[10] = 5;
end else begin
instruct_val <= mem[instruct_addr];
if(data_op == 1) begin
read_val <= mem[data_addr];
end else begin
mem[data_addr] <= write_val;
end
end
end
endmodule | 0 |
137,460 | data/full_repos/permissive/78967537/src/Source/mips.v | 78,967,537 | mips.v | v | 37 | 114 | [] | [] | [] | [(9, 36)] | null | null | 1: b"%Error: data/full_repos/permissive/78967537/src/Source/mips.v:18: Cannot find file containing module: 'clock'\n clock sysclock(clk);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/78967537/src/Source,data/full_repos/permissive/78967537/clock\n data/full_repos/permissive/78967537/src/Source,data/full_repos/permissive/78967537/clock.v\n data/full_repos/permissive/78967537/src/Source,data/full_repos/permissive/78967537/clock.sv\n clock\n clock.v\n clock.sv\n obj_dir/clock\n obj_dir/clock.v\n obj_dir/clock.sv\n%Error: data/full_repos/permissive/78967537/src/Source/mips.v:19: Cannot find file containing module: 'program_counter'\n program_counter pc(clk, reset, next_address, pc_address, next_address);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/78967537/src/Source/mips.v:32: Cannot find file containing module: 'memory'\n memory ram(clk, reset, data_op, pc_address, data_addr, write_val, instruct_val, read_val);\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 299,581 | module | module mips(clk, reset, en, pc_address, next_address, data_op, data_addr, write_val, instruct_val, read_val);
output wire clk;
input wire reset;
output wire en;
output wire [31:0] next_address;
output wire [31:0] pc_address;
clock sysclock(clk);
program_counter pc(clk, reset, next_address, pc_address, next_address);
output wire [31:0] instruct_val;
output wire [31:0] read_val;
output wire [31:0] data_addr;
output wire [31:0] write_val;
assign data_addr = next_address + 1;
assign write_val = data_addr + 4;
output reg data_op = 0;
memory ram(clk, reset, data_op, pc_address, data_addr, write_val, instruct_val, read_val);
endmodule | module mips(clk, reset, en, pc_address, next_address, data_op, data_addr, write_val, instruct_val, read_val); |
output wire clk;
input wire reset;
output wire en;
output wire [31:0] next_address;
output wire [31:0] pc_address;
clock sysclock(clk);
program_counter pc(clk, reset, next_address, pc_address, next_address);
output wire [31:0] instruct_val;
output wire [31:0] read_val;
output wire [31:0] data_addr;
output wire [31:0] write_val;
assign data_addr = next_address + 1;
assign write_val = data_addr + 4;
output reg data_op = 0;
memory ram(clk, reset, data_op, pc_address, data_addr, write_val, instruct_val, read_val);
endmodule | 0 |
137,461 | data/full_repos/permissive/78967537/src/Source/program_counter.v | 78,967,537 | program_counter.v | v | 29 | 122 | [] | [] | [] | [(7, 28)] | null | data/verilator_xmls/12fbd635-3869-4a8b-9c79-fe557ed6426d.xml | null | 299,582 | module | module program_counter(clk, reset, in_addr, cur_addr, next_addr);
input wire clk;
input wire reset;
input wire [31:0] in_addr;
output reg [31:0] cur_addr;
output reg [31:0] next_addr;
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
cur_addr <= 0;
next_addr <= 1;
end else begin
cur_addr <= in_addr;
next_addr <= in_addr + 1;
end
end
endmodule | module program_counter(clk, reset, in_addr, cur_addr, next_addr); |
input wire clk;
input wire reset;
input wire [31:0] in_addr;
output reg [31:0] cur_addr;
output reg [31:0] next_addr;
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
cur_addr <= 0;
next_addr <= 1;
end else begin
cur_addr <= in_addr;
next_addr <= in_addr + 1;
end
end
endmodule | 0 |
137,462 | data/full_repos/permissive/78967537/src/Source/reg_bank.v | 78,967,537 | reg_bank.v | v | 93 | 97 | [] | [] | [] | [(8, 92)] | null | data/verilator_xmls/4e140817-abba-4794-b102-24dcc35ae925.xml | null | 299,583 | module | module reg_bank(clk, reset, read_reg1, read_reg2, write_reg, wire_data, read_data1, read_data2);
input wire clk;
input wire reset;
input wire [25:21] read_reg1;
input wire [20:16] read_reg2;
input wire [31:0] write_reg;
input wire [31:0] wire_data;
output reg [31:0] read_data1;
output reg [31:0] read_data2;
reg [31:0] r0;
reg [31:0] r1;
reg [31:0] r2;
reg [31:0] r3;
reg [31:0] r4;
reg [31:0] r5;
reg [31:0] r6;
reg [31:0] r7;
reg [31:0] r8;
reg [31:0] r9;
reg [31:0] r10;
reg [31:0] r11;
reg [31:0] r12;
reg [31:0] r13;
reg [31:0] r14;
reg [31:0] r15;
reg [31:0] r16;
reg [31:0] r17;
reg [31:0] r18;
reg [31:0] r19;
reg [31:0] r20;
reg [31:0] r21;
reg [31:0] r22;
reg [31:0] r23;
reg [31:0] r24;
reg [31:0] r25;
reg [31:0] r26;
reg [31:0] r27;
reg [31:0] r28;
reg [31:0] r29;
reg [31:0] r30;
reg [31:0] r31;
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
r0 = 0;
r1 = 0;
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
r8 = 0;
r9 = 0;
r10 = 0;
r11 = 0;
r12 = 0;
r13 = 0;
r14 = 0;
r15 = 0;
r16 = 0;
r17 = 0;
r18 = 0;
r19 = 0;
r20 = 0;
r21 = 0;
r22 = 0;
r23 = 0;
r24 = 0;
r25 = 0;
r26 = 0;
r27 = 0;
r28 = 0;
r29 = 0;
r30 = 0;
r31 = 0;
end else begin
end
end
endmodule | module reg_bank(clk, reset, read_reg1, read_reg2, write_reg, wire_data, read_data1, read_data2); |
input wire clk;
input wire reset;
input wire [25:21] read_reg1;
input wire [20:16] read_reg2;
input wire [31:0] write_reg;
input wire [31:0] wire_data;
output reg [31:0] read_data1;
output reg [31:0] read_data2;
reg [31:0] r0;
reg [31:0] r1;
reg [31:0] r2;
reg [31:0] r3;
reg [31:0] r4;
reg [31:0] r5;
reg [31:0] r6;
reg [31:0] r7;
reg [31:0] r8;
reg [31:0] r9;
reg [31:0] r10;
reg [31:0] r11;
reg [31:0] r12;
reg [31:0] r13;
reg [31:0] r14;
reg [31:0] r15;
reg [31:0] r16;
reg [31:0] r17;
reg [31:0] r18;
reg [31:0] r19;
reg [31:0] r20;
reg [31:0] r21;
reg [31:0] r22;
reg [31:0] r23;
reg [31:0] r24;
reg [31:0] r25;
reg [31:0] r26;
reg [31:0] r27;
reg [31:0] r28;
reg [31:0] r29;
reg [31:0] r30;
reg [31:0] r31;
always @(posedge clk or negedge reset) begin
if(reset == 0) begin
r0 = 0;
r1 = 0;
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
r8 = 0;
r9 = 0;
r10 = 0;
r11 = 0;
r12 = 0;
r13 = 0;
r14 = 0;
r15 = 0;
r16 = 0;
r17 = 0;
r18 = 0;
r19 = 0;
r20 = 0;
r21 = 0;
r22 = 0;
r23 = 0;
r24 = 0;
r25 = 0;
r26 = 0;
r27 = 0;
r28 = 0;
r29 = 0;
r30 = 0;
r31 = 0;
end else begin
end
end
endmodule | 0 |
137,463 | data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v | 78,967,537 | tb_adder_32_bit.v.v | v | 63 | 70 | [] | [] | [] | [(12, 63)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:32: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:36: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:50: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:52: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:54: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:56: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:58: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:20: Cannot find file containing module: \'clock\'\n clock sys_clock(clk);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.v\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.sv\n clock\n clock.v\n clock.sv\n obj_dir/clock\n obj_dir/clock.v\n obj_dir/clock.sv\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_adder_32_bit.v.v:21: Cannot find file containing module: \'adder_32_bit\'\n adder_32_bit adder(clk, en, reset, op1, op2, out);\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,584 | module | module tb_adder_32_bit();
wire clk;
reg en;
reg reset;
reg [31:0] op1;
reg [31:0] op2;
wire [31:0] out;
clock sys_clock(clk);
adder_32_bit adder(clk, en, reset, op1, op2, out);
initial begin
reset = 0;
en = 0;
op1 = 0;
op2 = 4;
#5;
reset = 1;
#5;
reset = 0;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
end
endmodule | module tb_adder_32_bit(); |
wire clk;
reg en;
reg reset;
reg [31:0] op1;
reg [31:0] op2;
wire [31:0] out;
clock sys_clock(clk);
adder_32_bit adder(clk, en, reset, op1, op2, out);
initial begin
reset = 0;
en = 0;
op1 = 0;
op2 = 4;
#5;
reset = 1;
#5;
reset = 0;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
#5;
op1 = op1 + 4;
end
endmodule | 0 |
137,464 | data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v | 78,967,537 | tb_instruction_incrementer.v | v | 41 | 71 | [] | [] | [] | [(12, 41)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:32: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:36: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:19: Cannot find file containing module: \'clock\'\n clock sys_clock(clk);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.v\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.sv\n clock\n clock.v\n clock.sv\n obj_dir/clock\n obj_dir/clock.v\n obj_dir/clock.sv\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_instruction_incrementer.v:20: Cannot find file containing module: \'instruction_increment\'\n instruction_increment incrementer(clk, en, reset, instruction, out);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,585 | module | module tb_instruction_incrementer();
wire clk;
reg en;
reg reset;
reg [31:0] instruction;
wire [31:0] out;
clock sys_clock(clk);
instruction_increment incrementer(clk, en, reset, instruction, out);
initial begin
reset = 0;
en = 0;
instruction = 0;
#5;
reset = 1;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
end
endmodule | module tb_instruction_incrementer(); |
wire clk;
reg en;
reg reset;
reg [31:0] instruction;
wire [31:0] out;
clock sys_clock(clk);
instruction_increment incrementer(clk, en, reset, instruction, out);
initial begin
reset = 0;
en = 0;
instruction = 0;
#5;
reset = 1;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
#5;
instruction = out;
end
endmodule | 0 |
137,465 | data/full_repos/permissive/78967537/src/Testbench/tb_memory.v | 78,967,537 | tb_memory.v | v | 51 | 142 | [] | [] | [] | [(12, 52)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_memory.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_memory.v:30: Cannot find file containing module: \'clock\'\n clock sys_clock(clk);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.v\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.sv\n clock\n clock.v\n clock.sv\n obj_dir/clock\n obj_dir/clock.v\n obj_dir/clock.sv\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_memory.v:31: Cannot find file containing module: \'memory\'\n memory ram(clk, reset, read1_sig, read1_address, read1_out, read2_sig, read2_address, read2_out, write2_sig, write2_address, write2_value);\n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,586 | module | module tb_memory();
wire clk;
reg reset;
reg read1_sig;
reg read2_sig;
reg write2_sig;
reg [31:0] read1_address;
reg [31:0] read2_address;
reg [31:0] write2_address;
reg [31:0] write2_value;
wire[31:0] read1_out;
wire[31:0] read2_out;
clock sys_clock(clk);
memory ram(clk, reset, read1_sig, read1_address, read1_out, read2_sig, read2_address, read2_out, write2_sig, write2_address, write2_value);
initial begin
read1_sig = 1;
read2_sig = 1;
write2_sig = 1;
read1_address = 2;
read2_address = 3;
write2_address = 0;
write2_value = 666;
reset = 0;
#10;
reset = 1;
end
endmodule | module tb_memory(); |
wire clk;
reg reset;
reg read1_sig;
reg read2_sig;
reg write2_sig;
reg [31:0] read1_address;
reg [31:0] read2_address;
reg [31:0] write2_address;
reg [31:0] write2_value;
wire[31:0] read1_out;
wire[31:0] read2_out;
clock sys_clock(clk);
memory ram(clk, reset, read1_sig, read1_address, read1_out, read2_sig, read2_address, read2_out, write2_sig, write2_address, write2_value);
initial begin
read1_sig = 1;
read2_sig = 1;
write2_sig = 1;
read1_address = 2;
read2_address = 3;
write2_address = 0;
write2_value = 666;
reset = 0;
#10;
reset = 1;
end
endmodule | 0 |
137,466 | data/full_repos/permissive/78967537/src/Testbench/tb_mips.v | 78,967,537 | tb_mips.v | v | 35 | 112 | [] | [] | [] | [(12, 37)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_mips.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_mips.v:26: Cannot find file containing module: \'mips\'\n mips cpu(clk, reset, en, pc_address, next_address, data_op, data_addr, write_val, instruct_val, read_val); \n ^~~~\n ... Looked in:\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/mips\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/mips.v\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/mips.sv\n mips\n mips.v\n mips.sv\n obj_dir/mips\n obj_dir/mips.v\n obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,587 | module | module tb_mips();
wire clk;
reg reset;
wire en;
wire [31:0] next_address;
wire [31:0] pc_address;
wire data_op;
wire [31:0] data_addr;
wire [31:0] write_val;
wire [31:0] instruct_val;
wire [31:0] read_val;
mips cpu(clk, reset, en, pc_address, next_address, data_op, data_addr, write_val, instruct_val, read_val);
initial begin
reset = 0;
#10;
reset = 1;
end
endmodule | module tb_mips(); |
wire clk;
reg reset;
wire en;
wire [31:0] next_address;
wire [31:0] pc_address;
wire data_op;
wire [31:0] data_addr;
wire [31:0] write_val;
wire [31:0] instruct_val;
wire [31:0] read_val;
mips cpu(clk, reset, en, pc_address, next_address, data_op, data_addr, write_val, instruct_val, read_val);
initial begin
reset = 0;
#10;
reset = 1;
end
endmodule | 0 |
137,467 | data/full_repos/permissive/78967537/src/Testbench/tb_program_counter.v | 78,967,537 | tb_program_counter.v | v | 38 | 81 | [] | [] | [] | [(12, 38)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78967537/src/Testbench/tb_program_counter.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_program_counter.v:16: Cannot find file containing module: \'clock\'\n clock clo(clk);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.v\n data/full_repos/permissive/78967537/src/Testbench,data/full_repos/permissive/78967537/clock.sv\n clock\n clock.v\n clock.sv\n obj_dir/clock\n obj_dir/clock.v\n obj_dir/clock.sv\n%Error: data/full_repos/permissive/78967537/src/Testbench/tb_program_counter.v:22: Cannot find file containing module: \'program_counter\'\n program_counter counter(clk, reset, next_address, pc_address, next_address); \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,588 | module | module tb_program_counter();
wire clk;
clock clo(clk);
reg reset;
wire [31:0] next_address;
wire [31:0] pc_address;
program_counter counter(clk, reset, next_address, pc_address, next_address);
initial begin
reset = 0;
#10;
reset = 1;
end
endmodule | module tb_program_counter(); |
wire clk;
clock clo(clk);
reg reset;
wire [31:0] next_address;
wire [31:0] pc_address;
program_counter counter(clk, reset, next_address, pc_address, next_address);
initial begin
reset = 0;
#10;
reset = 1;
end
endmodule | 0 |
137,468 | data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v | 79,051,628 | ahb_lite_sdram.v | v | 308 | 129 | [] | [] | [] | [(6, 307)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:275: Operator OR expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'AddrColumn\' generates 10 bits.\n : ... In instance ahb_lite_sdram\n S_READ2_READ : begin cmd = CMD_READ; ADDR = AddrColumn | SDRAM_AUTOPRCH_FLAG; BA = AddrBank; end\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:278: Operator OR expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'AddrColumn\' generates 10 bits.\n : ... In instance ahb_lite_sdram\n S_WRITE2_WR0 : begin cmd = CMD_WRITE; ADDR = AddrColumn | SDRAM_AUTOPRCH_FLAG; BA = AddrBank; end\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:293: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b00 } : DQM = 2\'b10;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:293: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b00 } : DQM = 2\'b10;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:294: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b01 } : DQM = 2\'b01;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:294: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b01 } : DQM = 2\'b01;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:295: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b1? } : DQM = 2\'b11;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:295: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b1? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:296: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b0? } : DQM = 2\'b11;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:296: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b0? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:297: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b10 } : DQM = 2\'b10;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:297: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b10 } : DQM = 2\'b10;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:298: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b11 } : DQM = 2\'b01;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:298: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b11 } : DQM = 2\'b01;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:300: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X16, 2\'b0? } : DQM = 2\'b00;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:300: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X16, 2\'b0? } : DQM = 2\'b00;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:301: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X16, 2\'b1? } : DQM = 2\'b11;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:301: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X16, 2\'b1? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:302: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X16, 2\'b0? } : DQM = 2\'b11;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:302: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X16, 2\'b0? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:303: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X16, 2\'b1? } : DQM = 2\'b00;\n ^~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:303: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X16, 2\'b1? } : DQM = 2\'b00;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:293: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b00 } : DQM = 2\'b10;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:294: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b01 } : DQM = 2\'b01;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:295: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X8, 2\'b1? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:296: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b0? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:297: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b10 } : DQM = 2\'b10;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:298: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X8, 2\'b11 } : DQM = 2\'b01;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:300: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X16, 2\'b0? } : DQM = 2\'b00;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:301: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE2_WR0, HSIZE_X16, 2\'b1? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:302: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X16, 2\'b0? } : DQM = 2\'b11;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/79051628/src/ahb_lite_sdram/ahb_lite_sdram.v:303: Unsized numbers/parameters not allowed in replications.\n : ... In instance ahb_lite_sdram\n { S_WRITE3_WR1, HSIZE_X16, 2\'b1? } : DQM = 2\'b00;\n ^\n%Error: Exiting due to 32 warning(s)\n' | 299,590 | module | module ahb_lite_sdram
#(
parameter ADDR_BITS = 13,
ROW_BITS = 13,
COL_BITS = 10,
DQ_BITS = 16,
DM_BITS = 2,
BA_BITS = 2,
SADDR_BITS = (ROW_BITS + COL_BITS + BA_BITS),
parameter DELAY_nCKE = 20,
DELAY_tREF = 390,
DELAY_tRP = 0,
DELAY_tRFC = 2,
DELAY_tMRD = 0,
DELAY_tRCD = 0,
DELAY_tCAS = 0,
DELAY_afterREAD = 0,
DELAY_afterWRITE = 2,
COUNT_initAutoRef = 2
)
(
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK,
input [ 3:0] HPROT,
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
input HREADY,
output reg [ 31 : 0 ] HRDATA,
output HREADYOUT,
output HRESP,
input SI_Endian,
output CKE,
output CSn,
output RASn,
output CASn,
output WEn,
output reg [ ADDR_BITS - 1 : 0 ] ADDR,
output reg [ BA_BITS - 1 : 0 ] BA,
inout [ DQ_BITS - 1 : 0 ] DQ,
output reg [ DM_BITS - 1 : 0 ] DQM
);
parameter S_IDLE = 0,
S_INIT0_nCKE = 1,
S_INIT1_nCKE = 2,
S_INIT2_CKE = 3,
S_INIT3_NOP = 4,
S_INIT4_PRECHALL = 5,
S_INIT5_NOP = 6,
S_INIT6_PREREF = 7,
S_INIT7_AUTOREF = 8,
S_INIT8_NOP = 9,
S_INIT9_LMR = 10,
S_INIT10_NOP = 11,
S_READ0_ACT = 20,
S_READ1_NOP = 21,
S_READ2_READ = 22,
S_READ3_NOP = 23,
S_READ4_RD0 = 24,
S_READ5_RD1 = 25,
S_READ6_NOP = 26,
S_WRITE0_ACT = 30,
S_WRITE1_NOP = 31,
S_WRITE2_WR0 = 32,
S_WRITE3_WR1 = 33,
S_WRITE4_NOP = 34,
S_AREF0_AUTOREF = 40,
S_AREF1_NOP = 41;
reg [ 5 : 0 ] State, Next;
reg [ 24 : 0 ] delay_u;
reg [ 4 : 0 ] delay_n;
reg [ 3 : 0 ] repeat_cnt;
reg [ 2 : 0 ] HSIZE_old;
reg [ 31 : 0 ] HADDR_old;
reg HWRITE_old;
reg [ 1 : 0 ] HTRANS_old;
reg [ 31 : 0 ] DATA;
reg [ DQ_BITS - 1 : 0 ] DQreg;
assign DQ = DQreg;
parameter HTRANS_IDLE = 2'b0;
parameter HSIZE_X8 = 3'b000,
HSIZE_X16 = 3'b001,
HSIZE_X32 = 3'b010;
assign HRESP = 1'b0;
assign HREADYOUT = (State == S_IDLE);
wire NeedAction = HTRANS != HTRANS_IDLE && HSEL && HREADY;
wire NeedRefresh = ~|delay_u;
wire DelayFinished = ~|delay_n;
wire BigDelayFinished = ~|delay_u;
wire RepeatsFinished = ~|repeat_cnt;
always @ (posedge HCLK) begin
if (~HRESETn)
State <= S_INIT0_nCKE;
else
State <= Next;
end
always @ (*) begin
case(State)
S_IDLE : Next = NeedAction ? (HWRITE ? S_WRITE0_ACT : S_READ0_ACT)
: (NeedRefresh ? S_AREF0_AUTOREF : S_IDLE);
S_INIT0_nCKE : Next = S_INIT1_nCKE;
S_INIT1_nCKE : Next = BigDelayFinished ? S_INIT2_CKE : S_INIT1_nCKE;
S_INIT2_CKE : Next = S_INIT3_NOP;
S_INIT3_NOP : Next = S_INIT4_PRECHALL;
S_INIT4_PRECHALL : Next = (DELAY_tRP == 0) ? S_INIT6_PREREF : S_INIT5_NOP;
S_INIT5_NOP : Next = DelayFinished ? S_INIT6_PREREF : S_INIT5_NOP;
S_INIT6_PREREF : Next = S_INIT7_AUTOREF;
S_INIT7_AUTOREF : Next = S_INIT8_NOP;
S_INIT8_NOP : Next = ~DelayFinished ? S_INIT8_NOP : (
RepeatsFinished ? S_INIT9_LMR : S_INIT7_AUTOREF );
S_INIT9_LMR : Next = S_INIT10_NOP;
S_INIT10_NOP : Next = ~DelayFinished ? S_INIT10_NOP : (
~NeedAction ? S_IDLE : (
HWRITE ? S_WRITE0_ACT : S_READ0_ACT));
S_READ0_ACT : Next = (DELAY_tRCD == 0) ? S_READ2_READ : S_READ1_NOP;
S_READ1_NOP : Next = DelayFinished ? S_READ2_READ : S_READ1_NOP;
S_READ2_READ : Next = (DELAY_tCAS == 0) ? S_READ4_RD0 : S_READ3_NOP;
S_READ3_NOP : Next = DelayFinished ? S_READ4_RD0 : S_READ3_NOP;
S_READ4_RD0 : Next = S_READ5_RD1;
S_READ5_RD1 : Next = (DELAY_afterREAD != 0) ? S_READ6_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_READ6_NOP : Next = ~DelayFinished ? S_READ6_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_WRITE0_ACT : Next = (DELAY_tRCD == 0) ? S_WRITE2_WR0 : S_WRITE1_NOP;
S_WRITE1_NOP : Next = DelayFinished ? S_WRITE2_WR0 : S_WRITE1_NOP;
S_WRITE2_WR0 : Next = S_WRITE3_WR1;
S_WRITE3_WR1 : Next = (DELAY_afterWRITE != 0) ? S_WRITE4_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_WRITE4_NOP : Next = ~DelayFinished ? S_WRITE4_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_AREF0_AUTOREF : Next = S_AREF1_NOP;
S_AREF1_NOP : Next = ~DelayFinished ? S_AREF1_NOP : S_IDLE;
endcase
end
always @ (posedge HCLK) begin
case(State)
S_INIT4_PRECHALL : delay_n <= DELAY_tRP - 1;
S_INIT6_PREREF : repeat_cnt <= COUNT_initAutoRef;
S_INIT7_AUTOREF : begin delay_n <= DELAY_tRFC; repeat_cnt <= repeat_cnt - 1; end
S_INIT9_LMR : delay_n <= DELAY_tMRD;
S_READ0_ACT : delay_n <= DELAY_tRCD - 1;
S_READ2_READ : delay_n <= DELAY_tCAS - 1;
S_READ5_RD1 : delay_n <= DELAY_afterREAD - 1;
S_WRITE0_ACT : delay_n <= DELAY_tRCD - 1;
S_WRITE3_WR1 : delay_n <= DELAY_afterWRITE - 1;
S_AREF0_AUTOREF : delay_n <= DELAY_tRFC;
default : if (|delay_n) delay_n <= delay_n - 1;
endcase
case(State)
S_INIT0_nCKE : delay_u <= DELAY_nCKE;
S_INIT7_AUTOREF : delay_u <= DELAY_tREF;
S_AREF0_AUTOREF : delay_u <= DELAY_tREF;
default : if (|delay_u) delay_u <= delay_u - 1;
endcase
case(State)
S_INIT10_NOP,
S_IDLE : if (HSEL) begin
HADDR_old <= HADDR; HWRITE_old <= HWRITE;
HSIZE_old <= HSIZE; HTRANS_old <= HTRANS;
end
S_INIT0_nCKE : { HADDR_old, HWRITE_old, HSIZE_old, HTRANS_old } <= { 38 {1'b0}};
S_READ4_RD0 : DATA [15:0] <= DQ;
S_READ5_RD1 : HRDATA <= { DQ, DATA [15:0] };
S_WRITE0_ACT : DATA <= HWDATA;
default : ;
endcase
end
wire [ 1 : 0 ] ByteNum = HADDR_old [ 1 : 0 ];
wire [ COL_BITS - 1 : 0 ] AddrColumn = { HADDR_old [ COL_BITS : 2 ] , 1'b0 };
wire [ ROW_BITS - 1 : 0 ] AddrRow = HADDR_old [ ROW_BITS + COL_BITS : COL_BITS + 1 ];
wire [ BA_BITS - 1 : 0 ] AddrBank = HADDR_old [ SADDR_BITS : ROW_BITS + COL_BITS + 1 ];
reg [ 4 : 0 ] cmd;
assign { CKE, CSn, RASn, CASn, WEn } = cmd;
parameter CMD_NOP_NCKE = 5'b00111,
CMD_NOP = 5'b10111,
CMD_PRECHARGEALL = 5'b10010,
CMD_AUTOREFRESH = 5'b10001,
CMD_LOADMODEREG = 5'b10000,
CMD_ACTIVE = 5'b10011,
CMD_READ = 5'b10101,
CMD_WRITE = 5'b10100;
parameter SDRAM_CAS = 3'b010;
parameter SDRAM_BURST_TYPE = 1'b0;
parameter SDRAM_BURST_LEN = 3'b001;
parameter SDRAM_MODE_A = { { ADDR_BITS - 7 { 1'b0 } }, SDRAM_CAS, SDRAM_BURST_TYPE, SDRAM_BURST_LEN };
parameter SDRAM_MODE_B = { BA_BITS {1'b0} };
parameter SDRAM_ALL_BANKS = (1 << 10);
parameter SDRAM_AUTOPRCH_FLAG = (1 << 10);
always @ (*) begin
case(State)
default : cmd = CMD_NOP;
S_INIT0_nCKE : cmd = CMD_NOP_NCKE;
S_INIT1_nCKE : cmd = CMD_NOP_NCKE;
S_INIT4_PRECHALL : begin cmd = CMD_PRECHARGEALL; ADDR = SDRAM_ALL_BANKS; end
S_INIT7_AUTOREF : cmd = CMD_AUTOREFRESH;
S_INIT9_LMR : begin cmd = CMD_LOADMODEREG; ADDR = SDRAM_MODE_A; BA = SDRAM_MODE_B; end
S_READ0_ACT : begin cmd = CMD_ACTIVE; ADDR = AddrRow; BA = AddrBank; end
S_READ2_READ : begin cmd = CMD_READ; ADDR = AddrColumn | SDRAM_AUTOPRCH_FLAG; BA = AddrBank; end
S_WRITE0_ACT : begin cmd = CMD_ACTIVE; ADDR = AddrRow; BA = AddrBank; end
S_WRITE2_WR0 : begin cmd = CMD_WRITE; ADDR = AddrColumn | SDRAM_AUTOPRCH_FLAG; BA = AddrBank; end
S_AREF0_AUTOREF : cmd = CMD_AUTOREFRESH;
endcase
case(State)
default : DQreg = { DQ_BITS { 1'bz }};
S_WRITE2_WR0 : DQreg = DATA [ 15:0 ];
S_WRITE3_WR1 : DQreg = DATA [ 31:16 ];
endcase
casez( { State, HSIZE_old, ByteNum } )
default: DQM = 2'b00;
{ S_WRITE2_WR0, HSIZE_X8, 2'b00 } : DQM = 2'b10;
{ S_WRITE2_WR0, HSIZE_X8, 2'b01 } : DQM = 2'b01;
{ S_WRITE2_WR0, HSIZE_X8, 2'b1? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X8, 2'b0? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X8, 2'b10 } : DQM = 2'b10;
{ S_WRITE3_WR1, HSIZE_X8, 2'b11 } : DQM = 2'b01;
{ S_WRITE2_WR0, HSIZE_X16, 2'b0? } : DQM = 2'b00;
{ S_WRITE2_WR0, HSIZE_X16, 2'b1? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X16, 2'b0? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X16, 2'b1? } : DQM = 2'b00;
endcase
end
endmodule | module ahb_lite_sdram
#(
parameter ADDR_BITS = 13,
ROW_BITS = 13,
COL_BITS = 10,
DQ_BITS = 16,
DM_BITS = 2,
BA_BITS = 2,
SADDR_BITS = (ROW_BITS + COL_BITS + BA_BITS),
parameter DELAY_nCKE = 20,
DELAY_tREF = 390,
DELAY_tRP = 0,
DELAY_tRFC = 2,
DELAY_tMRD = 0,
DELAY_tRCD = 0,
DELAY_tCAS = 0,
DELAY_afterREAD = 0,
DELAY_afterWRITE = 2,
COUNT_initAutoRef = 2
)
(
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK,
input [ 3:0] HPROT,
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
input HREADY,
output reg [ 31 : 0 ] HRDATA,
output HREADYOUT,
output HRESP,
input SI_Endian,
output CKE,
output CSn,
output RASn,
output CASn,
output WEn,
output reg [ ADDR_BITS - 1 : 0 ] ADDR,
output reg [ BA_BITS - 1 : 0 ] BA,
inout [ DQ_BITS - 1 : 0 ] DQ,
output reg [ DM_BITS - 1 : 0 ] DQM
); |
parameter S_IDLE = 0,
S_INIT0_nCKE = 1,
S_INIT1_nCKE = 2,
S_INIT2_CKE = 3,
S_INIT3_NOP = 4,
S_INIT4_PRECHALL = 5,
S_INIT5_NOP = 6,
S_INIT6_PREREF = 7,
S_INIT7_AUTOREF = 8,
S_INIT8_NOP = 9,
S_INIT9_LMR = 10,
S_INIT10_NOP = 11,
S_READ0_ACT = 20,
S_READ1_NOP = 21,
S_READ2_READ = 22,
S_READ3_NOP = 23,
S_READ4_RD0 = 24,
S_READ5_RD1 = 25,
S_READ6_NOP = 26,
S_WRITE0_ACT = 30,
S_WRITE1_NOP = 31,
S_WRITE2_WR0 = 32,
S_WRITE3_WR1 = 33,
S_WRITE4_NOP = 34,
S_AREF0_AUTOREF = 40,
S_AREF1_NOP = 41;
reg [ 5 : 0 ] State, Next;
reg [ 24 : 0 ] delay_u;
reg [ 4 : 0 ] delay_n;
reg [ 3 : 0 ] repeat_cnt;
reg [ 2 : 0 ] HSIZE_old;
reg [ 31 : 0 ] HADDR_old;
reg HWRITE_old;
reg [ 1 : 0 ] HTRANS_old;
reg [ 31 : 0 ] DATA;
reg [ DQ_BITS - 1 : 0 ] DQreg;
assign DQ = DQreg;
parameter HTRANS_IDLE = 2'b0;
parameter HSIZE_X8 = 3'b000,
HSIZE_X16 = 3'b001,
HSIZE_X32 = 3'b010;
assign HRESP = 1'b0;
assign HREADYOUT = (State == S_IDLE);
wire NeedAction = HTRANS != HTRANS_IDLE && HSEL && HREADY;
wire NeedRefresh = ~|delay_u;
wire DelayFinished = ~|delay_n;
wire BigDelayFinished = ~|delay_u;
wire RepeatsFinished = ~|repeat_cnt;
always @ (posedge HCLK) begin
if (~HRESETn)
State <= S_INIT0_nCKE;
else
State <= Next;
end
always @ (*) begin
case(State)
S_IDLE : Next = NeedAction ? (HWRITE ? S_WRITE0_ACT : S_READ0_ACT)
: (NeedRefresh ? S_AREF0_AUTOREF : S_IDLE);
S_INIT0_nCKE : Next = S_INIT1_nCKE;
S_INIT1_nCKE : Next = BigDelayFinished ? S_INIT2_CKE : S_INIT1_nCKE;
S_INIT2_CKE : Next = S_INIT3_NOP;
S_INIT3_NOP : Next = S_INIT4_PRECHALL;
S_INIT4_PRECHALL : Next = (DELAY_tRP == 0) ? S_INIT6_PREREF : S_INIT5_NOP;
S_INIT5_NOP : Next = DelayFinished ? S_INIT6_PREREF : S_INIT5_NOP;
S_INIT6_PREREF : Next = S_INIT7_AUTOREF;
S_INIT7_AUTOREF : Next = S_INIT8_NOP;
S_INIT8_NOP : Next = ~DelayFinished ? S_INIT8_NOP : (
RepeatsFinished ? S_INIT9_LMR : S_INIT7_AUTOREF );
S_INIT9_LMR : Next = S_INIT10_NOP;
S_INIT10_NOP : Next = ~DelayFinished ? S_INIT10_NOP : (
~NeedAction ? S_IDLE : (
HWRITE ? S_WRITE0_ACT : S_READ0_ACT));
S_READ0_ACT : Next = (DELAY_tRCD == 0) ? S_READ2_READ : S_READ1_NOP;
S_READ1_NOP : Next = DelayFinished ? S_READ2_READ : S_READ1_NOP;
S_READ2_READ : Next = (DELAY_tCAS == 0) ? S_READ4_RD0 : S_READ3_NOP;
S_READ3_NOP : Next = DelayFinished ? S_READ4_RD0 : S_READ3_NOP;
S_READ4_RD0 : Next = S_READ5_RD1;
S_READ5_RD1 : Next = (DELAY_afterREAD != 0) ? S_READ6_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_READ6_NOP : Next = ~DelayFinished ? S_READ6_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_WRITE0_ACT : Next = (DELAY_tRCD == 0) ? S_WRITE2_WR0 : S_WRITE1_NOP;
S_WRITE1_NOP : Next = DelayFinished ? S_WRITE2_WR0 : S_WRITE1_NOP;
S_WRITE2_WR0 : Next = S_WRITE3_WR1;
S_WRITE3_WR1 : Next = (DELAY_afterWRITE != 0) ? S_WRITE4_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_WRITE4_NOP : Next = ~DelayFinished ? S_WRITE4_NOP : (
NeedRefresh ? S_AREF0_AUTOREF : S_IDLE );
S_AREF0_AUTOREF : Next = S_AREF1_NOP;
S_AREF1_NOP : Next = ~DelayFinished ? S_AREF1_NOP : S_IDLE;
endcase
end
always @ (posedge HCLK) begin
case(State)
S_INIT4_PRECHALL : delay_n <= DELAY_tRP - 1;
S_INIT6_PREREF : repeat_cnt <= COUNT_initAutoRef;
S_INIT7_AUTOREF : begin delay_n <= DELAY_tRFC; repeat_cnt <= repeat_cnt - 1; end
S_INIT9_LMR : delay_n <= DELAY_tMRD;
S_READ0_ACT : delay_n <= DELAY_tRCD - 1;
S_READ2_READ : delay_n <= DELAY_tCAS - 1;
S_READ5_RD1 : delay_n <= DELAY_afterREAD - 1;
S_WRITE0_ACT : delay_n <= DELAY_tRCD - 1;
S_WRITE3_WR1 : delay_n <= DELAY_afterWRITE - 1;
S_AREF0_AUTOREF : delay_n <= DELAY_tRFC;
default : if (|delay_n) delay_n <= delay_n - 1;
endcase
case(State)
S_INIT0_nCKE : delay_u <= DELAY_nCKE;
S_INIT7_AUTOREF : delay_u <= DELAY_tREF;
S_AREF0_AUTOREF : delay_u <= DELAY_tREF;
default : if (|delay_u) delay_u <= delay_u - 1;
endcase
case(State)
S_INIT10_NOP,
S_IDLE : if (HSEL) begin
HADDR_old <= HADDR; HWRITE_old <= HWRITE;
HSIZE_old <= HSIZE; HTRANS_old <= HTRANS;
end
S_INIT0_nCKE : { HADDR_old, HWRITE_old, HSIZE_old, HTRANS_old } <= { 38 {1'b0}};
S_READ4_RD0 : DATA [15:0] <= DQ;
S_READ5_RD1 : HRDATA <= { DQ, DATA [15:0] };
S_WRITE0_ACT : DATA <= HWDATA;
default : ;
endcase
end
wire [ 1 : 0 ] ByteNum = HADDR_old [ 1 : 0 ];
wire [ COL_BITS - 1 : 0 ] AddrColumn = { HADDR_old [ COL_BITS : 2 ] , 1'b0 };
wire [ ROW_BITS - 1 : 0 ] AddrRow = HADDR_old [ ROW_BITS + COL_BITS : COL_BITS + 1 ];
wire [ BA_BITS - 1 : 0 ] AddrBank = HADDR_old [ SADDR_BITS : ROW_BITS + COL_BITS + 1 ];
reg [ 4 : 0 ] cmd;
assign { CKE, CSn, RASn, CASn, WEn } = cmd;
parameter CMD_NOP_NCKE = 5'b00111,
CMD_NOP = 5'b10111,
CMD_PRECHARGEALL = 5'b10010,
CMD_AUTOREFRESH = 5'b10001,
CMD_LOADMODEREG = 5'b10000,
CMD_ACTIVE = 5'b10011,
CMD_READ = 5'b10101,
CMD_WRITE = 5'b10100;
parameter SDRAM_CAS = 3'b010;
parameter SDRAM_BURST_TYPE = 1'b0;
parameter SDRAM_BURST_LEN = 3'b001;
parameter SDRAM_MODE_A = { { ADDR_BITS - 7 { 1'b0 } }, SDRAM_CAS, SDRAM_BURST_TYPE, SDRAM_BURST_LEN };
parameter SDRAM_MODE_B = { BA_BITS {1'b0} };
parameter SDRAM_ALL_BANKS = (1 << 10);
parameter SDRAM_AUTOPRCH_FLAG = (1 << 10);
always @ (*) begin
case(State)
default : cmd = CMD_NOP;
S_INIT0_nCKE : cmd = CMD_NOP_NCKE;
S_INIT1_nCKE : cmd = CMD_NOP_NCKE;
S_INIT4_PRECHALL : begin cmd = CMD_PRECHARGEALL; ADDR = SDRAM_ALL_BANKS; end
S_INIT7_AUTOREF : cmd = CMD_AUTOREFRESH;
S_INIT9_LMR : begin cmd = CMD_LOADMODEREG; ADDR = SDRAM_MODE_A; BA = SDRAM_MODE_B; end
S_READ0_ACT : begin cmd = CMD_ACTIVE; ADDR = AddrRow; BA = AddrBank; end
S_READ2_READ : begin cmd = CMD_READ; ADDR = AddrColumn | SDRAM_AUTOPRCH_FLAG; BA = AddrBank; end
S_WRITE0_ACT : begin cmd = CMD_ACTIVE; ADDR = AddrRow; BA = AddrBank; end
S_WRITE2_WR0 : begin cmd = CMD_WRITE; ADDR = AddrColumn | SDRAM_AUTOPRCH_FLAG; BA = AddrBank; end
S_AREF0_AUTOREF : cmd = CMD_AUTOREFRESH;
endcase
case(State)
default : DQreg = { DQ_BITS { 1'bz }};
S_WRITE2_WR0 : DQreg = DATA [ 15:0 ];
S_WRITE3_WR1 : DQreg = DATA [ 31:16 ];
endcase
casez( { State, HSIZE_old, ByteNum } )
default: DQM = 2'b00;
{ S_WRITE2_WR0, HSIZE_X8, 2'b00 } : DQM = 2'b10;
{ S_WRITE2_WR0, HSIZE_X8, 2'b01 } : DQM = 2'b01;
{ S_WRITE2_WR0, HSIZE_X8, 2'b1? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X8, 2'b0? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X8, 2'b10 } : DQM = 2'b10;
{ S_WRITE3_WR1, HSIZE_X8, 2'b11 } : DQM = 2'b01;
{ S_WRITE2_WR0, HSIZE_X16, 2'b0? } : DQM = 2'b00;
{ S_WRITE2_WR0, HSIZE_X16, 2'b1? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X16, 2'b0? } : DQM = 2'b11;
{ S_WRITE3_WR1, HSIZE_X16, 2'b1? } : DQM = 2'b00;
endcase
end
endmodule | 14 |
137,470 | data/full_repos/permissive/79051628/src/debug/ahb_lite_mem.v | 79,051,628 | ahb_lite_mem.v | v | 96 | 87 | [] | [] | [] | [(7, 95)] | null | data/verilator_xmls/cb3701e7-92ce-4f88-b1fc-e8536678d2e7.xml | null | 299,593 | module | module ahb_lite_mem
#(
parameter ADDR_WIDTH = 6,
parameter DELAY_VAL = 2
)
(
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [ 2:0] HBURST,
input HMASTLOCK,
input [ 3:0] HPROT,
input HSEL,
input [ 2:0] HSIZE,
input [ 1:0] HTRANS,
input [31:0] HWDATA,
input HWRITE,
output reg [31:0] HRDATA,
output HREADY,
output HRESP,
input SI_Endian
);
assign HRESP = 1'b0;
parameter S_INIT = 0,
S_IDLE = 1,
S_READ = 2,
S_WRITE = 3,
S_WAIT = 4;
parameter HTRANS_IDLE = 2'b0;
reg [ 4 : 0 ] State, Next;
reg [ 31 : 0 ] HADDR_old;
reg HWRITE_old;
reg [ 1 : 0 ] HTRANS_old;
reg [ 3 : 0 ] Delay;
assign HREADY = (State == S_IDLE);
wire NeedAction = HTRANS != HTRANS_IDLE && HSEL;
wire DelayFinished = ( ~| Delay );
always @ (posedge HCLK) begin
if (~HRESETn)
State <= S_INIT;
else
State <= Next;
end
always @ (*) begin
Next = State;
case(State)
S_INIT: Next = S_IDLE;
S_IDLE: Next = ~NeedAction ? S_IDLE : (HWRITE ? S_WRITE : S_READ);
S_READ: Next = S_WAIT;
S_WRITE: Next = S_WAIT;
S_WAIT: Next = DelayFinished ? S_IDLE : S_WAIT;
endcase
end
reg [31:0] ram [ (1 << ADDR_WIDTH) - 1 : 0 ];
always @ (posedge HCLK) begin
if(State == S_INIT) begin
HADDR_old <= 32'b0;
HWRITE_old <= 1'b0;
HTRANS_old <= HTRANS_IDLE;
end
if(State == S_IDLE && HSEL) begin
HADDR_old <= HADDR;
HWRITE_old <= HWRITE;
HTRANS_old <= HTRANS;
end
if(State == S_READ)
HRDATA <= ram[HADDR_old [ ADDR_WIDTH - 1 + 2 : 2] ];
if(State == S_WRITE)
ram[HADDR_old [ ADDR_WIDTH - 1 + 2 : 2] ] <= HWDATA;
if(State == S_READ || State == S_WRITE)
Delay <= DELAY_VAL;
if(~DelayFinished)
Delay <= Delay - 1;
end
endmodule | module ahb_lite_mem
#(
parameter ADDR_WIDTH = 6,
parameter DELAY_VAL = 2
)
(
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [ 2:0] HBURST,
input HMASTLOCK,
input [ 3:0] HPROT,
input HSEL,
input [ 2:0] HSIZE,
input [ 1:0] HTRANS,
input [31:0] HWDATA,
input HWRITE,
output reg [31:0] HRDATA,
output HREADY,
output HRESP,
input SI_Endian
); |
assign HRESP = 1'b0;
parameter S_INIT = 0,
S_IDLE = 1,
S_READ = 2,
S_WRITE = 3,
S_WAIT = 4;
parameter HTRANS_IDLE = 2'b0;
reg [ 4 : 0 ] State, Next;
reg [ 31 : 0 ] HADDR_old;
reg HWRITE_old;
reg [ 1 : 0 ] HTRANS_old;
reg [ 3 : 0 ] Delay;
assign HREADY = (State == S_IDLE);
wire NeedAction = HTRANS != HTRANS_IDLE && HSEL;
wire DelayFinished = ( ~| Delay );
always @ (posedge HCLK) begin
if (~HRESETn)
State <= S_INIT;
else
State <= Next;
end
always @ (*) begin
Next = State;
case(State)
S_INIT: Next = S_IDLE;
S_IDLE: Next = ~NeedAction ? S_IDLE : (HWRITE ? S_WRITE : S_READ);
S_READ: Next = S_WAIT;
S_WRITE: Next = S_WAIT;
S_WAIT: Next = DelayFinished ? S_IDLE : S_WAIT;
endcase
end
reg [31:0] ram [ (1 << ADDR_WIDTH) - 1 : 0 ];
always @ (posedge HCLK) begin
if(State == S_INIT) begin
HADDR_old <= 32'b0;
HWRITE_old <= 1'b0;
HTRANS_old <= HTRANS_IDLE;
end
if(State == S_IDLE && HSEL) begin
HADDR_old <= HADDR;
HWRITE_old <= HWRITE;
HTRANS_old <= HTRANS;
end
if(State == S_READ)
HRDATA <= ram[HADDR_old [ ADDR_WIDTH - 1 + 2 : 2] ];
if(State == S_WRITE)
ram[HADDR_old [ ADDR_WIDTH - 1 + 2 : 2] ] <= HWDATA;
if(State == S_READ || State == S_WRITE)
Delay <= DELAY_VAL;
if(~DelayFinished)
Delay <= Delay - 1;
end
endmodule | 14 |
137,471 | data/full_repos/permissive/79051628/src/debug/ahb_lite_rw_master.v | 79,051,628 | ahb_lite_rw_master.v | v | 137 | 98 | [] | [] | [] | [(7, 137)] | null | data/verilator_xmls/feea167b-d229-475e-b34c-6a6cb66eaf46.xml | null | 299,594 | module | module ahb_lite_rw_master
#(
parameter ADDR_INCREMENT = 32'h10004,
DELAY_BITS = 10,
INCREMENT_CNT = 8,
READ_ITER_CNT = 2,
MAX_HADDR = INCREMENT_CNT * ADDR_INCREMENT
)
(
input HCLK,
input HRESETn,
output reg [ 31 : 0 ] HADDR,
output [ 2 : 0 ] HBURST,
output HSEL,
output [ 2 : 0 ] HSIZE,
output reg [ 1 : 0 ] HTRANS,
output [ 31 : 0 ] HWDATA,
output reg HWRITE,
input [ 31 : 0 ] HRDATA,
input HREADY,
input HRESP,
output reg [ 31 : 0 ] ERRCOUNT,
output reg [ 7 : 0 ] CHKCOUNT,
output S_WRITE,
output S_CHECK,
output S_SUCCESS,
output S_FAILED,
input [ 31 : 0 ] STARTADDR
);
assign HBURST = 3'b0;
assign HSEL = 1'b1;
assign HSIZE = 3'b010;
reg [ 31 : 0 ] HADDR_old;
reg [ DELAY_BITS - 1 : 0 ] delay_u;
wire BigDelayFinished = ~|delay_u;
wire [ 31 : 0 ] debugValue = HADDR_old;
assign HWDATA = debugValue;
reg [ 3 : 0 ] status;
assign { S_WRITE, S_CHECK, S_SUCCESS, S_FAILED } = status;
reg [ 3 : 0 ] State;
always @(posedge HCLK) begin
if(!HRESETn)
State <= 0;
else
case(State)
0: begin
HADDR_old <= STARTADDR;
HADDR <= STARTADDR;
HTRANS <= 2'b10;
HWRITE <= 1'b1;
State <= 1;
ERRCOUNT <= 0;
status <= 4'b1000;
CHKCOUNT <= 0;
end
1: if(HREADY) begin
if(HADDR == MAX_HADDR + STARTADDR)
State <= 3;
else begin
HADDR_old <= HADDR;
HADDR <= HADDR + ADDR_INCREMENT;
end
end
3: begin
HWRITE <= 1'b0;
HTRANS <= 2'b00;
delay_u <= 0;
State <= 4;
status <= 4'b0100;
end
4: begin
delay_u <= delay_u + 1;
if( &delay_u )
State <= 5;
end
5: begin
HADDR <= STARTADDR;
HTRANS <= 2'b10;
State <= 6;
end
6: begin
HADDR_old <= HADDR;
State <= 7;
end
7: if(HREADY) begin
if(HRDATA != debugValue)
ERRCOUNT <= ERRCOUNT + 1;
if(HADDR == MAX_HADDR + STARTADDR) begin
if ( CHKCOUNT == READ_ITER_CNT ) begin
HTRANS <= 2'b00;
State <= ( |ERRCOUNT ) ? 8 : 9;
end
else begin
State <= 3;
CHKCOUNT <= CHKCOUNT + 1;
end
end
else begin
HADDR_old <= HADDR;
HADDR <= HADDR + ADDR_INCREMENT;
end
end
8: status <= 4'b0001;
9: status <= 4'b0010;
endcase
end
endmodule | module ahb_lite_rw_master
#(
parameter ADDR_INCREMENT = 32'h10004,
DELAY_BITS = 10,
INCREMENT_CNT = 8,
READ_ITER_CNT = 2,
MAX_HADDR = INCREMENT_CNT * ADDR_INCREMENT
)
(
input HCLK,
input HRESETn,
output reg [ 31 : 0 ] HADDR,
output [ 2 : 0 ] HBURST,
output HSEL,
output [ 2 : 0 ] HSIZE,
output reg [ 1 : 0 ] HTRANS,
output [ 31 : 0 ] HWDATA,
output reg HWRITE,
input [ 31 : 0 ] HRDATA,
input HREADY,
input HRESP,
output reg [ 31 : 0 ] ERRCOUNT,
output reg [ 7 : 0 ] CHKCOUNT,
output S_WRITE,
output S_CHECK,
output S_SUCCESS,
output S_FAILED,
input [ 31 : 0 ] STARTADDR
); |
assign HBURST = 3'b0;
assign HSEL = 1'b1;
assign HSIZE = 3'b010;
reg [ 31 : 0 ] HADDR_old;
reg [ DELAY_BITS - 1 : 0 ] delay_u;
wire BigDelayFinished = ~|delay_u;
wire [ 31 : 0 ] debugValue = HADDR_old;
assign HWDATA = debugValue;
reg [ 3 : 0 ] status;
assign { S_WRITE, S_CHECK, S_SUCCESS, S_FAILED } = status;
reg [ 3 : 0 ] State;
always @(posedge HCLK) begin
if(!HRESETn)
State <= 0;
else
case(State)
0: begin
HADDR_old <= STARTADDR;
HADDR <= STARTADDR;
HTRANS <= 2'b10;
HWRITE <= 1'b1;
State <= 1;
ERRCOUNT <= 0;
status <= 4'b1000;
CHKCOUNT <= 0;
end
1: if(HREADY) begin
if(HADDR == MAX_HADDR + STARTADDR)
State <= 3;
else begin
HADDR_old <= HADDR;
HADDR <= HADDR + ADDR_INCREMENT;
end
end
3: begin
HWRITE <= 1'b0;
HTRANS <= 2'b00;
delay_u <= 0;
State <= 4;
status <= 4'b0100;
end
4: begin
delay_u <= delay_u + 1;
if( &delay_u )
State <= 5;
end
5: begin
HADDR <= STARTADDR;
HTRANS <= 2'b10;
State <= 6;
end
6: begin
HADDR_old <= HADDR;
State <= 7;
end
7: if(HREADY) begin
if(HRDATA != debugValue)
ERRCOUNT <= ERRCOUNT + 1;
if(HADDR == MAX_HADDR + STARTADDR) begin
if ( CHKCOUNT == READ_ITER_CNT ) begin
HTRANS <= 2'b00;
State <= ( |ERRCOUNT ) ? 8 : 9;
end
else begin
State <= 3;
CHKCOUNT <= CHKCOUNT + 1;
end
end
else begin
HADDR_old <= HADDR;
HADDR <= HADDR + ADDR_INCREMENT;
end
end
8: status <= 4'b0001;
9: status <= 4'b0010;
endcase
end
endmodule | 14 |
137,473 | data/full_repos/permissive/79051628/src/testbench/test_ahb_lite_rw_master.v | 79,051,628 | test_ahb_lite_rw_master.v | v | 156 | 92 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/79051628/src/testbench/test_ahb_lite_rw_master.v:11: Cannot find include file: sdr_parameters.vh\n `include "sdr_parameters.vh" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79051628/src/testbench,data/full_repos/permissive/79051628/sdr_parameters.vh\n data/full_repos/permissive/79051628/src/testbench,data/full_repos/permissive/79051628/sdr_parameters.vh.v\n data/full_repos/permissive/79051628/src/testbench,data/full_repos/permissive/79051628/sdr_parameters.vh.sv\n sdr_parameters.vh\n sdr_parameters.vh.v\n sdr_parameters.vh.sv\n obj_dir/sdr_parameters.vh\n obj_dir/sdr_parameters.vh.v\n obj_dir/sdr_parameters.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/test_ahb_lite_rw_master.v:93: Unsupported: Ignoring delay on this delayed statement.\n #(phaseShift) \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/test_ahb_lite_rw_master.v:97: Unsupported: Ignoring delay on this delayed statement.\n always #(tT/2) HCLK = ~HCLK; \n ^\n%Error: data/full_repos/permissive/79051628/src/testbench/test_ahb_lite_rw_master.v:144: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/test_ahb_lite_rw_master.v:150: Unsupported: Ignoring delay on this delayed statement.\n #70000 \n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 299,598 | module | module test_ahb_lite_rw_master;
`include "sdr_parameters.vh"
wire CKE;
wire CSn;
wire RASn;
wire CASn;
wire WEn;
wire [ ADDR_BITS - 1 : 0 ] ADDR;
wire [ BA_BITS - 1 : 0 ] BA;
wire [ DQ_BITS - 1 : 0 ] DQ;
wire [ DM_BITS - 1 : 0 ] DQM;
reg HCLK;
reg HRESETn;
wire [ 31 : 0 ] HADDR;
wire [ 2 : 0 ] HBURST;
wire HSEL;
wire [ 2 : 0 ] HSIZE;
wire [ 1 : 0 ] HTRANS;
wire [ 31 : 0 ] HWDATA;
wire HWRITE;
wire [ 31 : 0 ] HRDATA;
wire HREADY;
wire HRESP;
`define CLOCK_50_MHZ 1
ahb_lite_sdram
#(
.DELAY_nCKE (1000),
.DELAY_tREF (4000)
`ifndef CLOCK_50_MHZ
,
.DELAY_tRP ( 1 ),
.DELAY_tRFC ( 7 ),
.DELAY_tRCD ( 2 ),
.DELAY_tCAS ( 1 ),
.DELAY_afterREAD ( 3 ),
.DELAY_afterWRITE ( 5 )
`endif
)
mem
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.CKE ( CKE ),
.CSn ( CSn ),
.RASn ( RASn ),
.CASn ( CASn ),
.WEn ( WEn ),
.ADDR ( ADDR ),
.BA ( BA ),
.DQ ( DQ ),
.DQM ( DQM )
);
reg MCLK;
`ifdef CLOCK_50_MHZ
parameter tT = 20;
parameter phaseShift = 12;
`else
parameter tT = tCK;
parameter phaseShift = 2;
`endif
initial begin
MCLK = 1;
#(phaseShift)
forever MCLK = #(tT/2) ~MCLK;
end
always #(tT/2) HCLK = ~HCLK;
sdr sdram0 (DQ, ADDR, BA, MCLK, CKE, CSn, RASn, CASn, WEn, DQM);
wire [ 31 : 0 ] ERRCOUNT;
wire [ 7 : 0 ] CHKCOUNT;
wire S_WRITE;
wire S_CHECK;
wire S_SUCCESS;
wire S_FAILED;
ahb_lite_rw_master
#(
)
master
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.ERRCOUNT ( ERRCOUNT ),
.CHKCOUNT ( CHKCOUNT ),
.S_WRITE ( S_WRITE ),
.S_CHECK ( S_CHECK ),
.S_SUCCESS ( S_SUCCESS ),
.S_FAILED ( S_FAILED ),
.STARTADDR ( 1 )
);
initial begin
begin
HCLK = 0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
end
#70000
$stop;
$finish;
end
endmodule | module test_ahb_lite_rw_master; |
`include "sdr_parameters.vh"
wire CKE;
wire CSn;
wire RASn;
wire CASn;
wire WEn;
wire [ ADDR_BITS - 1 : 0 ] ADDR;
wire [ BA_BITS - 1 : 0 ] BA;
wire [ DQ_BITS - 1 : 0 ] DQ;
wire [ DM_BITS - 1 : 0 ] DQM;
reg HCLK;
reg HRESETn;
wire [ 31 : 0 ] HADDR;
wire [ 2 : 0 ] HBURST;
wire HSEL;
wire [ 2 : 0 ] HSIZE;
wire [ 1 : 0 ] HTRANS;
wire [ 31 : 0 ] HWDATA;
wire HWRITE;
wire [ 31 : 0 ] HRDATA;
wire HREADY;
wire HRESP;
`define CLOCK_50_MHZ 1
ahb_lite_sdram
#(
.DELAY_nCKE (1000),
.DELAY_tREF (4000)
`ifndef CLOCK_50_MHZ
,
.DELAY_tRP ( 1 ),
.DELAY_tRFC ( 7 ),
.DELAY_tRCD ( 2 ),
.DELAY_tCAS ( 1 ),
.DELAY_afterREAD ( 3 ),
.DELAY_afterWRITE ( 5 )
`endif
)
mem
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.CKE ( CKE ),
.CSn ( CSn ),
.RASn ( RASn ),
.CASn ( CASn ),
.WEn ( WEn ),
.ADDR ( ADDR ),
.BA ( BA ),
.DQ ( DQ ),
.DQM ( DQM )
);
reg MCLK;
`ifdef CLOCK_50_MHZ
parameter tT = 20;
parameter phaseShift = 12;
`else
parameter tT = tCK;
parameter phaseShift = 2;
`endif
initial begin
MCLK = 1;
#(phaseShift)
forever MCLK = #(tT/2) ~MCLK;
end
always #(tT/2) HCLK = ~HCLK;
sdr sdram0 (DQ, ADDR, BA, MCLK, CKE, CSn, RASn, CASn, WEn, DQM);
wire [ 31 : 0 ] ERRCOUNT;
wire [ 7 : 0 ] CHKCOUNT;
wire S_WRITE;
wire S_CHECK;
wire S_SUCCESS;
wire S_FAILED;
ahb_lite_rw_master
#(
)
master
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.ERRCOUNT ( ERRCOUNT ),
.CHKCOUNT ( CHKCOUNT ),
.S_WRITE ( S_WRITE ),
.S_CHECK ( S_CHECK ),
.S_SUCCESS ( S_SUCCESS ),
.S_FAILED ( S_FAILED ),
.STARTADDR ( 1 )
);
initial begin
begin
HCLK = 0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
end
#70000
$stop;
$finish;
end
endmodule | 14 |
137,476 | data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v | 79,051,628 | test.v | v | 366 | 102 | [] | [] | [] | null | line:434: before: "(" | null | 1: b'%Error: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:7: Cannot find include file: sdr_parameters.vh\n`include "sdr_parameters.vh" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79051628/src/testbench/sdr_sdram,data/full_repos/permissive/79051628/sdr_parameters.vh\n data/full_repos/permissive/79051628/src/testbench/sdr_sdram,data/full_repos/permissive/79051628/sdr_parameters.vh.v\n data/full_repos/permissive/79051628/src/testbench/sdr_sdram,data/full_repos/permissive/79051628/sdr_parameters.vh.sv\n sdr_parameters.vh\n sdr_parameters.vh.v\n sdr_parameters.vh.sv\n obj_dir/sdr_parameters.vh\n obj_dir/sdr_parameters.vh.v\n obj_dir/sdr_parameters.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:33: Unsupported: Ignoring delay on this delayed statement.\nalways #(tCK/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:238: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:239: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:240: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:241: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:242: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:243: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:244: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:245: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:246: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:247: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:248: Unsupported: Ignoring delay on this delayed statement.\n #tCK; precharge_all_bank(0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:249: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:250: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:251: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:252: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:253: Unsupported: Ignoring delay on this delayed statement.\n #tCK; auto_refresh; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:254: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:255: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:256: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:257: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:258: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:259: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:260: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:261: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:262: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:263: Unsupported: Ignoring delay on this delayed statement.\n #tCK; auto_refresh; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:264: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:265: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:266: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:267: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:268: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:269: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:270: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:271: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:272: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:273: Unsupported: Ignoring delay on this delayed statement.\n #tCK; load_mode_reg (50); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:274: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:277: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (0, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:278: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:279: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:280: Unsupported: Ignoring delay on this delayed statement.\n #tCK; write (0, 1024, $random, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:281: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:282: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:283: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:284: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:287: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (1, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:288: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:289: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:290: Unsupported: Ignoring delay on this delayed statement.\n #tCK; write (1, 1024, $random, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:291: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:292: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:293: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:294: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:297: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (2, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:298: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:299: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:300: Unsupported: Ignoring delay on this delayed statement.\n #tCK; write (2, 1024, $random, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:301: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:302: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:303: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:304: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:307: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (3, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:308: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:309: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:310: Unsupported: Ignoring delay on this delayed statement.\n #tCK; write (3, 1024, $random, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:311: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:312: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:313: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, $random); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:314: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:317: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (0, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:318: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:319: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:320: Unsupported: Ignoring delay on this delayed statement.\n #tCK; read (0, 1024, hi_z, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:321: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:322: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:323: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:324: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:327: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (1, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:328: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:329: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:330: Unsupported: Ignoring delay on this delayed statement.\n #tCK; read (1, 1024, hi_z, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:331: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:332: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:333: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:334: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:337: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (2, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:338: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:339: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:340: Unsupported: Ignoring delay on this delayed statement.\n #tCK; read (2, 1024, hi_z, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:341: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:342: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:343: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:344: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:347: Unsupported: Ignoring delay on this delayed statement.\n #tCK; active (3, 0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:348: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:349: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:350: Unsupported: Ignoring delay on this delayed statement.\n #tCK; read (3, 1024, hi_z, 0); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:351: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:352: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:353: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:354: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:356: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:357: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:358: Unsupported: Ignoring delay on this delayed statement.\n #tCK; nop (0, hi_z); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/79051628/src/testbench/sdr_sdram/test.v:359: Unsupported: Ignoring delay on this delayed statement.\n #tCK;\n ^\n%Error: Exiting due to 1 error(s), 106 warning(s)\n' | 299,603 | module | module test;
`include "sdr_parameters.vh"
reg clk;
reg cke;
reg cs_n;
reg ras_n;
reg cas_n;
reg we_n;
reg [ADDR_BITS - 1 : 0] addr;
reg [BA_BITS - 1 : 0] ba;
reg [DQ_BITS - 1 : 0] dq;
reg [DM_BITS - 1 : 0] dqm;
wire [DQ_BITS - 1 : 0] DQ = dq;
parameter hi_z = {DQ_BITS{1'bz}};
sdr sdram0 (DQ, addr, ba, clk, cke, cs_n, ras_n, cas_n, we_n, dqm);
initial begin
clk = 1'b0;
cke = 1'b0;
cs_n = 1'b1;
dq = hi_z;
end
always #(tCK/2) clk = ~clk;
task active;
input [ADDR_BITS - 1 : 0] bank;
input [ROW_BITS - 1 : 0] row;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 1;
dqm = 0;
ba = bank;
addr = row;
dq = dq_in;
end
endtask
task auto_refresh;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 0;
we_n = 1;
dqm = 0;
dq = hi_z;
end
endtask
task burst_term;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 1;
we_n = 0;
dqm = 0;
dq = dq_in;
end
endtask
task load_mode_reg;
input [ADDR_BITS - 1 : 0] op_code;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 0;
we_n = 0;
dqm = 0;
ba = 0;
addr = op_code;
dq = hi_z;
end
endtask
task nop;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 1;
we_n = 1;
dqm = dqm_in;
dq = dq_in;
end
endtask
task precharge_bank_0;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 0;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_1;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 1;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_2;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 2;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_3;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 3;
addr = 0;
dq = dq_in;
end
endtask
task precharge_all_bank;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 0;
addr = 1024;
dq = dq_in;
end
endtask
task read;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] column;
input [DQ_BITS - 1 : 0] dq_in;
input [DM_BITS - 1 : 0] dqm_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 0;
we_n = 1;
dqm = dqm_in;
ba = bank;
addr = column;
dq = dq_in;
end
endtask
task write;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] column;
input [DQ_BITS - 1 : 0] dq_in;
input [DM_BITS - 1 : 0] dqm_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 0;
we_n = 0;
dqm = dqm_in;
ba = bank;
addr = column;
dq = dq_in;
end
endtask
initial begin
begin
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; precharge_all_bank(0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; auto_refresh;
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; auto_refresh;
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; load_mode_reg (50);
#tCK; nop (0, hi_z);
#tCK; active (0, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (0, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (1, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (1, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (2, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (2, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (3, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (3, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (0, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (0, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; active (1, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (1, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; active (2, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (2, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; active (3, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (3, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK;
end
$stop;
$finish;
end
endmodule | module test; |
`include "sdr_parameters.vh"
reg clk;
reg cke;
reg cs_n;
reg ras_n;
reg cas_n;
reg we_n;
reg [ADDR_BITS - 1 : 0] addr;
reg [BA_BITS - 1 : 0] ba;
reg [DQ_BITS - 1 : 0] dq;
reg [DM_BITS - 1 : 0] dqm;
wire [DQ_BITS - 1 : 0] DQ = dq;
parameter hi_z = {DQ_BITS{1'bz}};
sdr sdram0 (DQ, addr, ba, clk, cke, cs_n, ras_n, cas_n, we_n, dqm);
initial begin
clk = 1'b0;
cke = 1'b0;
cs_n = 1'b1;
dq = hi_z;
end
always #(tCK/2) clk = ~clk;
task active;
input [ADDR_BITS - 1 : 0] bank;
input [ROW_BITS - 1 : 0] row;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 1;
dqm = 0;
ba = bank;
addr = row;
dq = dq_in;
end
endtask
task auto_refresh;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 0;
we_n = 1;
dqm = 0;
dq = hi_z;
end
endtask
task burst_term;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 1;
we_n = 0;
dqm = 0;
dq = dq_in;
end
endtask
task load_mode_reg;
input [ADDR_BITS - 1 : 0] op_code;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 0;
we_n = 0;
dqm = 0;
ba = 0;
addr = op_code;
dq = hi_z;
end
endtask
task nop;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 1;
we_n = 1;
dqm = dqm_in;
dq = dq_in;
end
endtask
task precharge_bank_0;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 0;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_1;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 1;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_2;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 2;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_3;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 3;
addr = 0;
dq = dq_in;
end
endtask
task precharge_all_bank;
input [DM_BITS - 1 : 0] dqm_in;
input [DQ_BITS - 1 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 0;
addr = 1024;
dq = dq_in;
end
endtask
task read;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] column;
input [DQ_BITS - 1 : 0] dq_in;
input [DM_BITS - 1 : 0] dqm_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 0;
we_n = 1;
dqm = dqm_in;
ba = bank;
addr = column;
dq = dq_in;
end
endtask
task write;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] column;
input [DQ_BITS - 1 : 0] dq_in;
input [DM_BITS - 1 : 0] dqm_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 0;
we_n = 0;
dqm = dqm_in;
ba = bank;
addr = column;
dq = dq_in;
end
endtask
initial begin
begin
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; precharge_all_bank(0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; auto_refresh;
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; auto_refresh;
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; load_mode_reg (50);
#tCK; nop (0, hi_z);
#tCK; active (0, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (0, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (1, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (1, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (2, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (2, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (3, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; write (3, 1024, $random, 0);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, $random);
#tCK; nop (0, hi_z);
#tCK; active (0, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (0, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; active (1, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (1, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; active (2, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (2, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; active (3, 0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; read (3, 1024, hi_z, 0);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK; nop (0, hi_z);
#tCK;
end
$stop;
$finish;
end
endmodule | 14 |
137,478 | data/full_repos/permissive/79090962/Verilog/Adder_Test.v | 79,090,962 | Adder_Test.v | v | 61 | 79 | [] | [] | [] | null | line:39: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Adder_Test.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Adder_Test.v:43: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Adder_Test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Adder_Test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Adder_Test.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));\n ^\n%Error: data/full_repos/permissive/79090962/Verilog/Adder_Test.v:27: Cannot find file containing module: \'Adder\'\n Adder adder (a,b, sum);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Adder\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Adder.v\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Adder.sv\n Adder\n Adder.v\n Adder.sv\n obj_dir/Adder\n obj_dir/Adder.v\n obj_dir/Adder.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,605 | module | module Comparator_Test();
reg [31:0] a, b;
wire [31:0] sum;
Adder adder (a,b, sum);
initial
begin
$display("Testing Comparator with some selected test cases.");
a = 1;
b = 2;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = 0;
b = -1;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = -100000;
b = 100000;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = 2147483647;
b = 2;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = 2147483647;
b = -2147483647;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
end
endmodule | module Comparator_Test(); |
reg [31:0] a, b;
wire [31:0] sum;
Adder adder (a,b, sum);
initial
begin
$display("Testing Comparator with some selected test cases.");
a = 1;
b = 2;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = 0;
b = -1;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = -100000;
b = 100000;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = 2147483647;
b = 2;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
a = 2147483647;
b = -2147483647;
#5 $display("A: %d | B: %d | Sum: %d", $signed(a), $signed(b), $signed(sum));
end
endmodule | 1 |
137,479 | data/full_repos/permissive/79090962/Verilog/ALU.v | 79,090,962 | ALU.v | v | 71 | 74 | [] | [] | [] | [(24, 71)] | null | data/verilator_xmls/d225088a-0ccc-4944-982d-85b111c4f92d.xml | null | 299,606 | module | module ALU (input signed [31:0] in1,
input signed [31:0] in2,
input [2:0] ALUControl,
input clock,
output reg signed [31:0] result,
output zero);
reg signed [63:0] HiLo;
assign zero = (result == 0);
initial
begin
HiLo = 0;
end
always @(in1 or in2 or ALUControl)
begin
casex (ALUControl)
0:
result = in1;
1:
result = in1 | in2;
2:
result = in1 + in2;
3:
result = HiLo[63:32];
4:
result = HiLo[31:0];
6:
result = in1 - in2;
endcase
end
always @(negedge clock)
begin
if(ALUControl == 5)
HiLo = in1 * in2;
if(ALUControl == 7)
begin
HiLo[31:0] = in1 / in2;
HiLo[63:32] = in1 % in2;
end
end
endmodule | module ALU (input signed [31:0] in1,
input signed [31:0] in2,
input [2:0] ALUControl,
input clock,
output reg signed [31:0] result,
output zero); |
reg signed [63:0] HiLo;
assign zero = (result == 0);
initial
begin
HiLo = 0;
end
always @(in1 or in2 or ALUControl)
begin
casex (ALUControl)
0:
result = in1;
1:
result = in1 | in2;
2:
result = in1 + in2;
3:
result = HiLo[63:32];
4:
result = HiLo[31:0];
6:
result = in1 - in2;
endcase
end
always @(negedge clock)
begin
if(ALUControl == 5)
HiLo = in1 * in2;
if(ALUControl == 7)
begin
HiLo[31:0] = in1 / in2;
HiLo[63:32] = in1 % in2;
end
end
endmodule | 1 |
137,480 | data/full_repos/permissive/79090962/Verilog/ALUControl.v | 79,090,962 | ALUControl.v | v | 76 | 85 | [] | [] | [] | [(25, 76)] | null | data/verilator_xmls/e74ed53c-9a87-4555-83f9-52ec71b3ef4e.xml | null | 299,607 | module | module ALUControl (Funct, ALUOp, ALUCtl);
input [5:0] Funct;
input [1:0] ALUOp;
output reg [2:0] ALUCtl;
localparam FORWARD=3'b000;
localparam OR =3'b001;
localparam ADD =3'b010;
localparam MFHI =3'b011;
localparam MFLO =3'b100;
localparam MUL =3'b101;
localparam SUB =3'b110;
localparam DIV =3'b111;
always @ (*)
begin
if (ALUOp == 2'b01) ALUCtl = SUB;
if (ALUOp == 2'b00) ALUCtl = ADD;
if (ALUOp == 2'b10)
begin
casex (Funct)
6'b101010: ALUCtl = OR;
6'b100000: ALUCtl = ADD;
6'b000000: ALUCtl = FORWARD;
6'b100010: ALUCtl = SUB;
6'b011000: ALUCtl = MUL;
6'b011010: ALUCtl = DIV;
6'b010000: ALUCtl = MFHI;
6'b010010: ALUCtl = MFLO;
6'b001000: ALUCtl = FORWARD;
endcase
end
end
endmodule | module ALUControl (Funct, ALUOp, ALUCtl); |
input [5:0] Funct;
input [1:0] ALUOp;
output reg [2:0] ALUCtl;
localparam FORWARD=3'b000;
localparam OR =3'b001;
localparam ADD =3'b010;
localparam MFHI =3'b011;
localparam MFLO =3'b100;
localparam MUL =3'b101;
localparam SUB =3'b110;
localparam DIV =3'b111;
always @ (*)
begin
if (ALUOp == 2'b01) ALUCtl = SUB;
if (ALUOp == 2'b00) ALUCtl = ADD;
if (ALUOp == 2'b10)
begin
casex (Funct)
6'b101010: ALUCtl = OR;
6'b100000: ALUCtl = ADD;
6'b000000: ALUCtl = FORWARD;
6'b100010: ALUCtl = SUB;
6'b011000: ALUCtl = MUL;
6'b011010: ALUCtl = DIV;
6'b010000: ALUCtl = MFHI;
6'b010010: ALUCtl = MFLO;
6'b001000: ALUCtl = FORWARD;
endcase
end
end
endmodule | 1 |
137,481 | data/full_repos/permissive/79090962/Verilog/BranchControl.v | 79,090,962 | BranchControl.v | v | 18 | 166 | [] | [] | [] | [(1, 18)] | null | data/verilator_xmls/1317f556-264a-42e8-8172-0df20a00db9b.xml | null | 299,608 | module | module BranchControl (input [31:0] PCp4, input [31:0] immediate, input zero, input [31:0] ALUresult, input BEQ, input BNE, input JR, input JUMP, output [31:0] toPC);
wire branch;
assign branch = ((zero && BEQ) || (!zero && BNE));
wire [31:0] branchTar;
assign branchTar = PCp4 + {immediate[29:0], 2'b00};
wire [31:0] branchMuxed;
assign branchMuxed = (branch) ? branchTar : PCp4;
wire [31:0] JRMuxed;
assign JRMuxed = (JR) ? ALUresult : branchMuxed;
assign toPC = (JUMP) ? {PCp4[31:28], immediate [25:0], 2'b00} : JRMuxed;
endmodule | module BranchControl (input [31:0] PCp4, input [31:0] immediate, input zero, input [31:0] ALUresult, input BEQ, input BNE, input JR, input JUMP, output [31:0] toPC); |
wire branch;
assign branch = ((zero && BEQ) || (!zero && BNE));
wire [31:0] branchTar;
assign branchTar = PCp4 + {immediate[29:0], 2'b00};
wire [31:0] branchMuxed;
assign branchMuxed = (branch) ? branchTar : PCp4;
wire [31:0] JRMuxed;
assign JRMuxed = (JR) ? ALUresult : branchMuxed;
assign toPC = (JUMP) ? {PCp4[31:28], immediate [25:0], 2'b00} : JRMuxed;
endmodule | 1 |
137,482 | data/full_repos/permissive/79090962/Verilog/Clock.v | 79,090,962 | Clock.v | v | 39 | 60 | [] | [] | [] | [(26, 39)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Clock.v:36: Unsupported: Ignoring delay on this delayed statement.\n#50 clock = ~clock; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Clock.v:37: Unsupported: Ignoring delay on this delayed statement.\n#50 clock = ~clock; \n^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,609 | module | module Clock(clock);
output reg clock;
initial
clock = 0;
always
begin
#50 clock = ~clock;
#50 clock = ~clock;
end
endmodule | module Clock(clock); |
output reg clock;
initial
clock = 0;
always
begin
#50 clock = ~clock;
#50 clock = ~clock;
end
endmodule | 1 |
137,483 | data/full_repos/permissive/79090962/Verilog/Clock_Test.v | 79,090,962 | Clock_Test.v | v | 36 | 95 | [] | [] | [] | null | line:31: before: "," | null | 1: b'%Error: data/full_repos/permissive/79090962/Verilog/Clock_Test.v:31: Unsupported or unknown PLI call: $monitor\n $monitor( $time,,"clock = %b", clock );\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Clock_Test.v:31: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n $monitor( $time,,"clock = %b", clock );\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Clock_Test.v:32: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,610 | module | module Clock_Test;
wire clock;
Clock c0( clock );
initial
begin
$monitor( $time,,"clock = %b", clock );
#1000 $finish;
end
endmodule | module Clock_Test; |
wire clock;
Clock c0( clock );
initial
begin
$monitor( $time,,"clock = %b", clock );
#1000 $finish;
end
endmodule | 1 |
137,484 | data/full_repos/permissive/79090962/Verilog/Comparator.v | 79,090,962 | Comparator.v | v | 33 | 79 | [] | [] | [] | [(25, 33)] | null | data/verilator_xmls/a2fe7143-189c-415c-b035-12b33dc4e792.xml | null | 299,611 | module | module Comparator (in0, in1, equal);
input [31:0] in0, in1;
output equal;
assign equal = (in0 == in1)? 1 : 0;
endmodule | module Comparator (in0, in1, equal); |
input [31:0] in0, in1;
output equal;
assign equal = (in0 == in1)? 1 : 0;
endmodule | 1 |
137,486 | data/full_repos/permissive/79090962/Verilog/Control.v | 79,090,962 | Control.v | v | 147 | 133 | [] | [] | [] | [(39, 147)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/79090962/Verilog/Control.v:104: Operator EQ expects 6 bits on the LHS, but LHS\'s SEL generates 5 bits.\n : ... In instance Control\n assign JMP = (instr[31:27] == 6\'b00001); \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 299,613 | module | module Control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable, JAL, JR );
input [31:0] instr;
output reg [1:0] ALUOp;
output reg [5:0] func;
output wire RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc,RegWrite, LUI, SysEnable, JAL, JR;
assign SysEnable = (instr == 32'h0000000C);
always @(instr or SysEnable)
begin
if ((SysEnable == 0'b0) && (instr[31:26] == 6'b000000))
begin
func = instr[5:0];
ALUOp = 2'b10;
end
if ((instr[31:26] == 6'b000100) || (instr[31:26] == 6'b000101) )
begin
ALUOp = 2'b01;
end
if ((instr[31:26] == 6'b100011) || (instr[31:26] == 6'b101011))
begin
ALUOp = 2'b00;
end
if (instr[31:26] == 6'b001101)
begin
ALUOp = 2'b10;
func =6'b101010;
end
if (instr[31:26] == 6'b001000)
begin
ALUOp = 2'b10;
func =6'b100000;
end
end
assign RegDST = (instr[31:26] == 6'b000000);
assign BEQ = (instr[31:26] == 6'b000100);
assign BNE = (instr[31:26] == 6'b000101);
assign JMP = (instr[31:27] == 6'b00001);
assign JAL = (instr[31:26] == 6'b000011);
assign JR = ((instr[31:26] == 6'b000000) && (instr[5:0] == 6'b001000));
assign MemRead = (instr[31:26] == 6'b100011);
assign MemtoReg = (instr[31:26] == 6'b100011);
assign MemWrite = (instr[31:26] == 6'b101011);
assign LUI = (instr[31:26] == 6'b001111);
assign ALUSrc = ((instr[31:26] == 6'b100011) ||
(instr[31:26] == 6'b101011) ||
(instr[31:26] == 6'b001101) ||
(instr[31:26] == 6'b001000)
);
assign RegWrite = ((instr[31:26] == 6'b100011) ||
(instr[31:26] == 6'b001111) ||
(instr[31:26] == 6'b001101) ||
(instr[31:26] == 6'b001000) ||
(instr[31:26] == 6'b000011) ||
((instr[31:26] == 6'b000000) && !SysEnable && !JR)
);
endmodule | module Control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable, JAL, JR ); |
input [31:0] instr;
output reg [1:0] ALUOp;
output reg [5:0] func;
output wire RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc,RegWrite, LUI, SysEnable, JAL, JR;
assign SysEnable = (instr == 32'h0000000C);
always @(instr or SysEnable)
begin
if ((SysEnable == 0'b0) && (instr[31:26] == 6'b000000))
begin
func = instr[5:0];
ALUOp = 2'b10;
end
if ((instr[31:26] == 6'b000100) || (instr[31:26] == 6'b000101) )
begin
ALUOp = 2'b01;
end
if ((instr[31:26] == 6'b100011) || (instr[31:26] == 6'b101011))
begin
ALUOp = 2'b00;
end
if (instr[31:26] == 6'b001101)
begin
ALUOp = 2'b10;
func =6'b101010;
end
if (instr[31:26] == 6'b001000)
begin
ALUOp = 2'b10;
func =6'b100000;
end
end
assign RegDST = (instr[31:26] == 6'b000000);
assign BEQ = (instr[31:26] == 6'b000100);
assign BNE = (instr[31:26] == 6'b000101);
assign JMP = (instr[31:27] == 6'b00001);
assign JAL = (instr[31:26] == 6'b000011);
assign JR = ((instr[31:26] == 6'b000000) && (instr[5:0] == 6'b001000));
assign MemRead = (instr[31:26] == 6'b100011);
assign MemtoReg = (instr[31:26] == 6'b100011);
assign MemWrite = (instr[31:26] == 6'b101011);
assign LUI = (instr[31:26] == 6'b001111);
assign ALUSrc = ((instr[31:26] == 6'b100011) ||
(instr[31:26] == 6'b101011) ||
(instr[31:26] == 6'b001101) ||
(instr[31:26] == 6'b001000)
);
assign RegWrite = ((instr[31:26] == 6'b100011) ||
(instr[31:26] == 6'b001111) ||
(instr[31:26] == 6'b001101) ||
(instr[31:26] == 6'b001000) ||
(instr[31:26] == 6'b000011) ||
((instr[31:26] == 6'b000000) && !SysEnable && !JR)
);
endmodule | 1 |
137,487 | data/full_repos/permissive/79090962/Verilog/HelloWorld.v | 79,090,962 | HelloWorld.v | v | 20 | 49 | [] | [] | [] | [(16, 20)] | null | data/verilator_xmls/2aeb8dd2-8adf-40ec-b757-8ef84e230582.xml | null | 299,614 | module | module helloworld;
initial
$display("Hello World \n Thomas Sowders");
endmodule | module helloworld; |
initial
$display("Hello World \n Thomas Sowders");
endmodule | 1 |
137,488 | data/full_repos/permissive/79090962/Verilog/InstructionMemory.v | 79,090,962 | InstructionMemory.v | v | 40 | 71 | [] | [] | [] | [(24, 40)] | null | data/verilator_xmls/0b5a9349-59e1-46e1-857d-8b1d8bb8d0dc.xml | null | 299,615 | module | module InstructionMemory (input [31:0] addr, output reg [31:0] instr);
reg [31:0] memory[0:255];
initial
begin
$readmemh("MIPSinst.txt", memory);
end
always@ (addr)
begin
instr = memory[addr[9:2]];
end
endmodule | module InstructionMemory (input [31:0] addr, output reg [31:0] instr); |
reg [31:0] memory[0:255];
initial
begin
$readmemh("MIPSinst.txt", memory);
end
always@ (addr)
begin
instr = memory[addr[9:2]];
end
endmodule | 1 |
137,489 | data/full_repos/permissive/79090962/Verilog/Left_Shift.v | 79,090,962 | Left_Shift.v | v | 32 | 87 | [] | [] | [] | [(24, 32)] | null | data/verilator_xmls/c50948a4-3ee8-4cc7-991d-77b66bbadcee.xml | null | 299,616 | module | module Left_Shift(in, out);
input wire [31:0] in;
output wire [31:0] out;
assign out = {in[29:0], 2'b0};
endmodule | module Left_Shift(in, out); |
input wire [31:0] in;
output wire [31:0] out;
assign out = {in[29:0], 2'b0};
endmodule | 1 |
137,491 | data/full_repos/permissive/79090962/Verilog/MainMemory.v | 79,090,962 | MainMemory.v | v | 53 | 112 | [] | [] | [] | [(27, 53)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/79090962/Verilog/MainMemory.v:40: Bit extraction of array[512:0] requires 10 bit index, not 8 bits.\n : ... In instance MainMemory\n out = memory[addr[9:2]];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/79090962/Verilog/MainMemory.v:48: Bit extraction of array[512:0] requires 10 bit index, not 8 bits.\n : ... In instance MainMemory\n memory[addr[9:2]] <= writeData;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 299,618 | module | module MainMemory (input [31:0] addr, input write, input clock, input [31:0] writeData, output reg [31:0] out);
reg [31:0] memory[0:512];
initial
begin
$readmemh("MIPSdata.txt", memory);
end
always@ (addr or clock)
begin
out = memory[addr[9:2]];
end
always @(negedge clock)
begin
if (write)
begin
memory[addr[9:2]] <= writeData;
out <= writeData;
end
end
endmodule | module MainMemory (input [31:0] addr, input write, input clock, input [31:0] writeData, output reg [31:0] out); |
reg [31:0] memory[0:512];
initial
begin
$readmemh("MIPSdata.txt", memory);
end
always@ (addr or clock)
begin
out = memory[addr[9:2]];
end
always @(negedge clock)
begin
if (write)
begin
memory[addr[9:2]] <= writeData;
out <= writeData;
end
end
endmodule | 1 |
137,492 | data/full_repos/permissive/79090962/Verilog/Mux_4.v | 79,090,962 | Mux_4.v | v | 51 | 75 | [] | [] | [] | [(26, 51)] | null | data/verilator_xmls/da56fe91-1944-444b-86b5-65d9e2529777.xml | null | 299,620 | module | module Mux_4(in0, in1, in2, in3, select, out);
input [31:0] in0, in1, in2, in3;
input[1:0] select;
output reg [31:0] out;
always @ (in0 or in1 or in2 or in3 or select)
begin
if( select == 0)
out = in0;
if( select == 1)
out = in1;
if( select == 2)
out = in2;
if( select == 3)
out = in3;
end
endmodule | module Mux_4(in0, in1, in2, in3, select, out); |
input [31:0] in0, in1, in2, in3;
input[1:0] select;
output reg [31:0] out;
always @ (in0 or in1 or in2 or in3 or select)
begin
if( select == 0)
out = in0;
if( select == 1)
out = in1;
if( select == 2)
out = in2;
if( select == 3)
out = in3;
end
endmodule | 1 |
137,494 | data/full_repos/permissive/79090962/Verilog/Mux_Test.v | 79,090,962 | Mux_Test.v | v | 53 | 92 | [] | [] | [] | null | line:47: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Mux_Test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("in0 = %d, in1 = %d, select = %b. Output = %d", out0, out1, select, muxout);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/79090962/Verilog/Mux_Test.v:27: Cannot find file containing module: \'Mux\'\n Mux mux (out0,out1,select,muxout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Mux\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Mux.v\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Mux.sv\n Mux\n Mux.v\n Mux.sv\n obj_dir/Mux\n obj_dir/Mux.v\n obj_dir/Mux.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,622 | module | module MuxTest();
reg [31:0] out0, out1;
reg select;
wire [31:0] muxout;
reg [3:0] testvals;
Mux mux (out0,out1,select,muxout);
initial
begin
$display("Testing 2-to-1 Mux:");
testvals = 0;
out0 = 32'b0;
out1 = 32'b0;
for (testvals = 0; testvals < 8; testvals = testvals +1)
begin
{out0[0],out1[1],select} = testvals[2:0];
#5 $display("in0 = %d, in1 = %d, select = %b. Output = %d", out0, out1, select, muxout);
end
end
endmodule | module MuxTest(); |
reg [31:0] out0, out1;
reg select;
wire [31:0] muxout;
reg [3:0] testvals;
Mux mux (out0,out1,select,muxout);
initial
begin
$display("Testing 2-to-1 Mux:");
testvals = 0;
out0 = 32'b0;
out1 = 32'b0;
for (testvals = 0; testvals < 8; testvals = testvals +1)
begin
{out0[0],out1[1],select} = testvals[2:0];
#5 $display("in0 = %d, in1 = %d, select = %b. Output = %d", out0, out1, select, muxout);
end
end
endmodule | 1 |
137,496 | data/full_repos/permissive/79090962/Verilog/PC_Test.v | 79,090,962 | PC_Test.v | v | 46 | 85 | [] | [] | [] | null | line:40: before: "$" | null | 1: b'%Error: data/full_repos/permissive/79090962/Verilog/PC_Test.v:38: Unsupported or unknown PLI call: $monitor\n $monitor("At time: ",$time," | ","PC = %b", pc_val);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/PC_Test.v:40: Unsupported: Ignoring delay on this delayed statement.\n #2000 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,624 | module | module PC_Test();
wire clock_signal;
wire [31:0] pc_val;
Clock clk (clock_signal);
ProgramCounter pc (clock_signal, pc_val);
initial
begin
$display("Testing Program Counter. Monitoring output of PC for 10 clock cycles.");
$monitor("At time: ",$time," | ","PC = %b", pc_val);
#2000 $finish;
end
endmodule | module PC_Test(); |
wire clock_signal;
wire [31:0] pc_val;
Clock clk (clock_signal);
ProgramCounter pc (clock_signal, pc_val);
initial
begin
$display("Testing Program Counter. Monitoring output of PC for 10 clock cycles.");
$monitor("At time: ",$time," | ","PC = %b", pc_val);
#2000 $finish;
end
endmodule | 1 |
137,497 | data/full_repos/permissive/79090962/Verilog/Processor.v | 79,090,962 | Processor.v | v | 111 | 145 | [] | [] | [] | [(2, 111)] | null | null | 1: b"%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:6: Cannot find file containing module: 'Clock'\nClock myClock(clock);\n^~~~~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Clock\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Clock.v\n data/full_repos/permissive/79090962/Verilog,data/full_repos/permissive/79090962/Clock.sv\n Clock\n Clock.v\n Clock.sv\n obj_dir/Clock\n obj_dir/Clock.v\n obj_dir/Clock.sv\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:11: Cannot find file containing module: 'ProgramCounter'\nProgramCounter myPC (clock, to_pc, from_pc);\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:15: Cannot find file containing module: 'Adder'\nAdder pcAdder({32'h00000004}, from_pc, pcPlus4);\n^~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:21: Cannot find file containing module: 'InstructionMemory'\nInstructionMemory myInstructionMemory (from_pc, instruction);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:40: Cannot find file containing module: 'Control'\nControl myControl (instruction, ALUOP, FUNC, REGDST, BEQ, BNE, JMP, MEMREAD, MEMTOREG, MEMWRITE, ALUSRC, CTL_REGWRITE, LUI, SYSENABLE, JAL, JR);\n^~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:45: Cannot find file containing module: 'Syscalls'\nSyscalls mySyscalls(SYSENABLE);\n^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:70: Cannot find file containing module: 'Mux5'\nMux5 regDstMux (instruction[20:16], instruction[15:11], REGDST, writeReg_case0);\n^~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:72: Cannot find file containing module: 'Mux_4'\nMux_4 writeRegMux ({27'h0,writeReg_case0}, {32'h0000001f}, {32'h00000002}, 32'hzzzzzzzz, {SYS_REGWRITE, JAL}, toWriteReg);\n^~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:74: Cannot find file containing module: 'Mux_4'\nMux_4 writeDataMux (from_LUIMux, pcPlus4, SYSDATA, 32'hzzzzzzzz, {SYS_REGWRITE, JAL}, toWriteData);\n^~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:76: Cannot find file containing module: 'Mux'\nMux LUIMux (memToRegData, {instruction[15:0], 16'b0}, LUI, from_LUIMux);\n^~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:81: Cannot find file containing module: 'Registers'\nRegisters myRegisters (instruction[25:21], instruction[20:16], toWriteReg[4:0], clock, toWriteData, data1, data2, REGWRITE);\n^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:84: Cannot find file containing module: 'Sign_Extender'\nSign_Extender mySignExtender (instruction[15:0], signExtImm);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:88: Cannot find file containing module: 'ALUControl'\nALUControl myALUControl(FUNC, ALUOP, ALUCtl);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:92: Cannot find file containing module: 'Mux'\nMux ALUSrcMux (data2, signExtImm, ALUSRC, ALU_in2);\n^~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:96: Cannot find file containing module: 'ALU'\nALU myALU(data1, ALU_in2, ALUCtl, clock, ALUResult, ZERO);\n^~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:100: Cannot find file containing module: 'Mux'\nMux addressMux(ALUResult, SYSADDR, SYSMEM, memAddress);\n^~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:103: Cannot find file containing module: 'MainMemory'\nMainMemory myMemory(memAddress, MEMWRITE, clock, data2, memData);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:105: Cannot find file containing module: 'Mux'\nMux memToRegMux (ALUResult, memData, MEMTOREG, memToRegData);\n^~~\n%Error: data/full_repos/permissive/79090962/Verilog/Processor.v:108: Cannot find file containing module: 'BranchControl'\nBranchControl myBranchControl (pcPlus4, signExtImm, ZERO, ALUResult, BEQ, BNE, JR, JMP, to_pc);\n^~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n" | 299,625 | module | module Processor();
wire clock;
Clock myClock(clock);
wire [31:0] to_pc;
wire [31:0] from_pc;
ProgramCounter myPC (clock, to_pc, from_pc);
wire [31:0] pcPlus4;
Adder pcAdder({32'h00000004}, from_pc, pcPlus4);
wire [31:0] instruction;
InstructionMemory myInstructionMemory (from_pc, instruction);
wire [1:0] ALUOP;
wire [5:0] FUNC;
wire REGDST;
wire BEQ;
wire BNE;
wire JMP;
wire MEMREAD;
wire MEMTOREG;
wire MEMWRITE;
wire ALUSRC;
wire CTL_REGWRITE;
wire LUI;
wire SYSENABLE;
wire JAL;
wire JR;
Control myControl (instruction, ALUOP, FUNC, REGDST, BEQ, BNE, JMP, MEMREAD, MEMTOREG, MEMWRITE, ALUSRC, CTL_REGWRITE, LUI, SYSENABLE, JAL, JR);
Syscalls mySyscalls(SYSENABLE);
wire SYS_REGWRITE;
wire [31:0] SYSDATA;
wire SYSMEM;
wire [31:0] SYSADDR;
assign SYS_REGWRITE = 0;
assign SYSMEM = 0;
assign SYSDATA = 32'hz;
assign SYSADDR = 32'hz;
wire REGWRITE= CTL_REGWRITE || SYS_REGWRITE;
wire [4:0] writeReg_case0;
wire [31:0] toWriteReg;
wire [31:0] toWriteData;
wire [31:0] from_LUIMux;
wire [31:0] memToRegData;
Mux5 regDstMux (instruction[20:16], instruction[15:11], REGDST, writeReg_case0);
Mux_4 writeRegMux ({27'h0,writeReg_case0}, {32'h0000001f}, {32'h00000002}, 32'hzzzzzzzz, {SYS_REGWRITE, JAL}, toWriteReg);
Mux_4 writeDataMux (from_LUIMux, pcPlus4, SYSDATA, 32'hzzzzzzzz, {SYS_REGWRITE, JAL}, toWriteData);
Mux LUIMux (memToRegData, {instruction[15:0], 16'b0}, LUI, from_LUIMux);
wire [31:0] data1;
wire [31:0] data2;
Registers myRegisters (instruction[25:21], instruction[20:16], toWriteReg[4:0], clock, toWriteData, data1, data2, REGWRITE);
wire [31:0] signExtImm;
Sign_Extender mySignExtender (instruction[15:0], signExtImm);
wire [2:0] ALUCtl;
ALUControl myALUControl(FUNC, ALUOP, ALUCtl);
wire [31:0] ALU_in2;
Mux ALUSrcMux (data2, signExtImm, ALUSRC, ALU_in2);
wire [31:0] ALUResult;
wire ZERO;
ALU myALU(data1, ALU_in2, ALUCtl, clock, ALUResult, ZERO);
wire [31:0] memAddress;
Mux addressMux(ALUResult, SYSADDR, SYSMEM, memAddress);
wire [31:0] memData;
MainMemory myMemory(memAddress, MEMWRITE, clock, data2, memData);
Mux memToRegMux (ALUResult, memData, MEMTOREG, memToRegData);
BranchControl myBranchControl (pcPlus4, signExtImm, ZERO, ALUResult, BEQ, BNE, JR, JMP, to_pc);
endmodule | module Processor(); |
wire clock;
Clock myClock(clock);
wire [31:0] to_pc;
wire [31:0] from_pc;
ProgramCounter myPC (clock, to_pc, from_pc);
wire [31:0] pcPlus4;
Adder pcAdder({32'h00000004}, from_pc, pcPlus4);
wire [31:0] instruction;
InstructionMemory myInstructionMemory (from_pc, instruction);
wire [1:0] ALUOP;
wire [5:0] FUNC;
wire REGDST;
wire BEQ;
wire BNE;
wire JMP;
wire MEMREAD;
wire MEMTOREG;
wire MEMWRITE;
wire ALUSRC;
wire CTL_REGWRITE;
wire LUI;
wire SYSENABLE;
wire JAL;
wire JR;
Control myControl (instruction, ALUOP, FUNC, REGDST, BEQ, BNE, JMP, MEMREAD, MEMTOREG, MEMWRITE, ALUSRC, CTL_REGWRITE, LUI, SYSENABLE, JAL, JR);
Syscalls mySyscalls(SYSENABLE);
wire SYS_REGWRITE;
wire [31:0] SYSDATA;
wire SYSMEM;
wire [31:0] SYSADDR;
assign SYS_REGWRITE = 0;
assign SYSMEM = 0;
assign SYSDATA = 32'hz;
assign SYSADDR = 32'hz;
wire REGWRITE= CTL_REGWRITE || SYS_REGWRITE;
wire [4:0] writeReg_case0;
wire [31:0] toWriteReg;
wire [31:0] toWriteData;
wire [31:0] from_LUIMux;
wire [31:0] memToRegData;
Mux5 regDstMux (instruction[20:16], instruction[15:11], REGDST, writeReg_case0);
Mux_4 writeRegMux ({27'h0,writeReg_case0}, {32'h0000001f}, {32'h00000002}, 32'hzzzzzzzz, {SYS_REGWRITE, JAL}, toWriteReg);
Mux_4 writeDataMux (from_LUIMux, pcPlus4, SYSDATA, 32'hzzzzzzzz, {SYS_REGWRITE, JAL}, toWriteData);
Mux LUIMux (memToRegData, {instruction[15:0], 16'b0}, LUI, from_LUIMux);
wire [31:0] data1;
wire [31:0] data2;
Registers myRegisters (instruction[25:21], instruction[20:16], toWriteReg[4:0], clock, toWriteData, data1, data2, REGWRITE);
wire [31:0] signExtImm;
Sign_Extender mySignExtender (instruction[15:0], signExtImm);
wire [2:0] ALUCtl;
ALUControl myALUControl(FUNC, ALUOP, ALUCtl);
wire [31:0] ALU_in2;
Mux ALUSrcMux (data2, signExtImm, ALUSRC, ALU_in2);
wire [31:0] ALUResult;
wire ZERO;
ALU myALU(data1, ALU_in2, ALUCtl, clock, ALUResult, ZERO);
wire [31:0] memAddress;
Mux addressMux(ALUResult, SYSADDR, SYSMEM, memAddress);
wire [31:0] memData;
MainMemory myMemory(memAddress, MEMWRITE, clock, data2, memData);
Mux memToRegMux (ALUResult, memData, MEMTOREG, memToRegData);
BranchControl myBranchControl (pcPlus4, signExtImm, ZERO, ALUResult, BEQ, BNE, JR, JMP, to_pc);
endmodule | 1 |
137,502 | data/full_repos/permissive/79090962/Verilog/Syscalls.v | 79,090,962 | Syscalls.v | v | 67 | 58 | [] | [] | [] | [(1, 66)] | null | null | 1: b'%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:10: Can\'t find definition of scope/variable: \'Processor\'\n case (Processor.myRegisters.registers[2])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:10: Can\'t find definition of scope/variable: \'myRegisters\'\n case (Processor.myRegisters.registers[2])\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:13: Can\'t find definition of scope/variable: \'Processor\'\n $display("%d",Processor.myRegisters.registers[4]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:13: Can\'t find definition of scope/variable: \'myRegisters\'\n $display("%d",Processor.myRegisters.registers[4]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:18: Can\'t find definition of scope/variable: \'Processor\'\n index = Processor.myRegisters.registers[4][10:0];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:18: Can\'t find definition of scope/variable: \'myRegisters\'\n index = Processor.myRegisters.registers[4][10:0];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:21: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][7:0];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:21: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][7:0];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:23: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][15:8];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:23: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][15:8];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:25: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][23:16];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:25: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][23:16];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:27: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][31:24];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:27: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][31:24];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:34: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][7:0];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:34: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][7:0];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:36: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][15:8];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:36: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][15:8];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:38: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][23:16];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:38: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][23:16];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:40: Can\'t find definition of scope/variable: \'Processor\'\n char = Processor.myMemory.memory[index[10:2]][31:24];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:40: Can\'t find definition of scope/variable: \'myMemory\'\n char = Processor.myMemory.memory[index[10:2]][31:24];\n ^~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:52: Can\'t find definition of scope/variable: \'Processor\'\n Processor.myRegisters.registers[2] = data[0];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79090962/Verilog/Syscalls.v:52: Can\'t find definition of scope/variable: \'myRegisters\'\n Processor.myRegisters.registers[2] = data[0];\n ^~~~~~~~~~~\n%Error: Exiting due to 24 error(s)\n' | 299,630 | module | module Syscalls(input sysEnable);
reg [31:0] data [0:1];
reg [7:0] char;
reg [10:0] index;
always @(posedge sysEnable)
begin
case (Processor.myRegisters.registers[2])
1:
begin
$display("%d",Processor.myRegisters.registers[4]);
end
4:
begin
index = Processor.myRegisters.registers[4][10:0];
if (index[1:0] == 2'b00)
char = Processor.myMemory.memory[index[10:2]][7:0];
if (index[1:0] == 2'b01)
char = Processor.myMemory.memory[index[10:2]][15:8];
if (index[1:0] == 2'b10)
char = Processor.myMemory.memory[index[10:2]][23:16];
if (index[1:0] == 2'b11)
char = Processor.myMemory.memory[index[10:2]][31:24];
while (char != 0)
begin
$write("%c", char);
index = index + 1;
if (index[1:0] == 2'b00)
char = Processor.myMemory.memory[index[10:2]][7:0];
if (index[1:0] == 2'b01)
char = Processor.myMemory.memory[index[10:2]][15:8];
if (index[1:0] == 2'b10)
char = Processor.myMemory.memory[index[10:2]][23:16];
if (index[1:0] == 2'b11)
char = Processor.myMemory.memory[index[10:2]][31:24];
end
end
5:
begin
$readmemh("input.txt", data);
Processor.myRegisters.registers[2] = data[0];
$display("Read input value %d", data[0]);
end
10:
begin
$finish;
end
endcase
end
endmodule | module Syscalls(input sysEnable); |
reg [31:0] data [0:1];
reg [7:0] char;
reg [10:0] index;
always @(posedge sysEnable)
begin
case (Processor.myRegisters.registers[2])
1:
begin
$display("%d",Processor.myRegisters.registers[4]);
end
4:
begin
index = Processor.myRegisters.registers[4][10:0];
if (index[1:0] == 2'b00)
char = Processor.myMemory.memory[index[10:2]][7:0];
if (index[1:0] == 2'b01)
char = Processor.myMemory.memory[index[10:2]][15:8];
if (index[1:0] == 2'b10)
char = Processor.myMemory.memory[index[10:2]][23:16];
if (index[1:0] == 2'b11)
char = Processor.myMemory.memory[index[10:2]][31:24];
while (char != 0)
begin
$write("%c", char);
index = index + 1;
if (index[1:0] == 2'b00)
char = Processor.myMemory.memory[index[10:2]][7:0];
if (index[1:0] == 2'b01)
char = Processor.myMemory.memory[index[10:2]][15:8];
if (index[1:0] == 2'b10)
char = Processor.myMemory.memory[index[10:2]][23:16];
if (index[1:0] == 2'b11)
char = Processor.myMemory.memory[index[10:2]][31:24];
end
end
5:
begin
$readmemh("input.txt", data);
Processor.myRegisters.registers[2] = data[0];
$display("Read input value %d", data[0]);
end
10:
begin
$finish;
end
endcase
end
endmodule | 1 |
137,504 | data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v | 79,090,962 | ALUControlTest.v | v | 117 | 126 | [] | [] | [] | null | line:39: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:84: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:88: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:92: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:96: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:104: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:108: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:112: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);\n ^\n%Error: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:28: Cannot find file containing module: \'Control\'\n Control control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable );\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Control\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Control.v\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Control.sv\n Control\n Control.v\n Control.sv\n obj_dir/Control\n obj_dir/Control.v\n obj_dir/Control.sv\n%Error: data/full_repos/permissive/79090962/Verilog/Tests/ALUControlTest.v:32: Cannot find file containing module: \'ALUControl\'\n ALUControl alu(func , ALUOp, ALUCtl);\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 19 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,633 | module | module ALUControlTest();
reg [31:0] instr;
wire [1:0] ALUOp;
wire [5:0] func;
wire RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc,RegWrite, LUI, SysEnable;
Control control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable );
wire [2:0] ALUCtl;
ALUControl alu(func , ALUOp, ALUCtl);
initial
begin
$display ("Testing ALU Control Unit");
$display ("Testing beq");
instr = 32'h10000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing bne");
instr = 32'h14000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing lw");
instr = 32'h8c000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing sw");
instr = 32'h94000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing lui");
instr = 32'h3c000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing ori");
instr = 32'h34000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing addi");
instr = 32'h20000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing jal");
instr = 32'h0c000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing j");
instr = 32'h08000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing syscall");
instr = 32'h0000000c;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing NOP");
instr = 32'h00000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing or");
instr = 32'h0000002a;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing add");
instr = 32'h00000020;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing sub");
instr = 32'h00000022;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing mul");
instr = 32'h00000018;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing div");
instr = 32'h0000001a;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing jr");
instr = 32'h00000008;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing mfhi");
instr = 32'h00000010;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing mflo");
instr = 32'h00000012;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
end
endmodule | module ALUControlTest(); |
reg [31:0] instr;
wire [1:0] ALUOp;
wire [5:0] func;
wire RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc,RegWrite, LUI, SysEnable;
Control control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable );
wire [2:0] ALUCtl;
ALUControl alu(func , ALUOp, ALUCtl);
initial
begin
$display ("Testing ALU Control Unit");
$display ("Testing beq");
instr = 32'h10000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing bne");
instr = 32'h14000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing lw");
instr = 32'h8c000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing sw");
instr = 32'h94000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing lui");
instr = 32'h3c000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing ori");
instr = 32'h34000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing addi");
instr = 32'h20000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing jal");
instr = 32'h0c000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing j");
instr = 32'h08000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing syscall");
instr = 32'h0000000c;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing NOP");
instr = 32'h00000000;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing or");
instr = 32'h0000002a;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing add");
instr = 32'h00000020;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing sub");
instr = 32'h00000022;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing mul");
instr = 32'h00000018;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing div");
instr = 32'h0000001a;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing jr");
instr = 32'h00000008;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing mfhi");
instr = 32'h00000010;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
$display ("Testing mflo");
instr = 32'h00000012;
#10 $display ("instr= %h, ALUOp= %b, func= %b, ALUCtl= %b", instr, ALUOp, func, ALUCtl);
end
endmodule | 1 |
137,506 | data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v | 79,090,962 | ControlTest.v | v | 113 | 302 | [] | [] | [] | null | line:34: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5 $display ("Testing beq");\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:64: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:80: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:84: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:92: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:100: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);\n ^\n%Error: data/full_repos/permissive/79090962/Verilog/Tests/ControlTest.v:27: Cannot find file containing module: \'Control\'\n Control control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable );\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Control\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Control.v\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Control.sv\n Control\n Control.v\n Control.sv\n obj_dir/Control\n obj_dir/Control.v\n obj_dir/Control.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,637 | module | module ControlTest();
reg [31:0] instr;
wire [1:0] ALUOp;
wire [5:0] func;
wire RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc,RegWrite, LUI, SysEnable;
Control control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable );
initial
begin
$display ("Testing Control Unit");
instr = 32'h00000000;
#5 $display ("Testing beq");
instr = 32'h10000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing bne");
instr = 32'h14000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing lw");
instr = 32'h8c000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing sw");
instr = 32'h94000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing lui");
instr = 32'h3c000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing ori");
instr = 32'h34000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing addi");
instr = 32'h20000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing jal");
instr = 32'h0c000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing j");
instr = 32'h08000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing syscall");
instr = 32'h0000000c;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing NOP");
instr = 32'h00000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing or");
instr = 32'h0000002a;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing add");
instr = 32'h00000020;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing sub");
instr = 32'h00000022;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing mul");
instr = 32'h00000018;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing div");
instr = 32'h0000001a;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing jr");
instr = 32'h00000008;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing mfhi");
instr = 32'h00000010;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing mflo");
instr = 32'h00000012;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
end
endmodule | module ControlTest(); |
reg [31:0] instr;
wire [1:0] ALUOp;
wire [5:0] func;
wire RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc,RegWrite, LUI, SysEnable;
Control control (instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable );
initial
begin
$display ("Testing Control Unit");
instr = 32'h00000000;
#5 $display ("Testing beq");
instr = 32'h10000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing bne");
instr = 32'h14000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing lw");
instr = 32'h8c000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing sw");
instr = 32'h94000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing lui");
instr = 32'h3c000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing ori");
instr = 32'h34000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing addi");
instr = 32'h20000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing jal");
instr = 32'h0c000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing j");
instr = 32'h08000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing syscall");
instr = 32'h0000000c;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing NOP");
instr = 32'h00000000;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing or");
instr = 32'h0000002a;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing add");
instr = 32'h00000020;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing sub");
instr = 32'h00000022;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing mul");
instr = 32'h00000018;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing div");
instr = 32'h0000001a;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing jr");
instr = 32'h00000008;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing mfhi");
instr = 32'h00000010;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
$display ("Testing mflo");
instr = 32'h00000012;
#100 $display ("instr = %h, ALUOp = %b, func = %b, RegDST = %b, BEQ = %b, BNE = %b, JMP = %b, MemRead = %b, MemtoReg = %b, MemWrite = %b, ALUSrc = %b, RegWrite = %b, LUI = %b, SysEnable = %b",instr, ALUOp, func, RegDST, BEQ, BNE, JMP, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, LUI, SysEnable);
end
endmodule | 1 |
137,507 | data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v | 79,090,962 | InstructionMemoryTest.v | v | 51 | 57 | [] | [] | [] | null | line:32: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("At address %d, value is: %h",addr,data);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:33: Unsupported: Ignoring delay on this delayed statement.\n #2 addr = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("At address %d, value is: %h",addr,data);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n #2 addr = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("At address %d, value is: %h",addr,data);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:37: Unsupported: Ignoring delay on this delayed statement.\n #2 addr = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("At address %d, value is: %h",addr,data);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:39: Unsupported: Ignoring delay on this delayed statement.\n #2 addr = 7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("At address %d, value is: %h",addr,data);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:41: Unsupported: Ignoring delay on this delayed statement.\n #2 addr = 15;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:42: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("At address %d, value is: %h",addr,data);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:43: Unsupported: Ignoring delay on this delayed statement.\n #2 addr = 31;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("At address %d, value is: %h",addr,data);\n ^\n%Error: data/full_repos/permissive/79090962/Verilog/Tests/InstructionMemoryTest.v:27: Cannot find file containing module: \'InstructionMemory\'\n InstructionMemory mem(addr, data);\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/InstructionMemory\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/InstructionMemory.v\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/InstructionMemory.sv\n InstructionMemory\n InstructionMemory.v\n InstructionMemory.sv\n obj_dir/InstructionMemory\n obj_dir/InstructionMemory.v\n obj_dir/InstructionMemory.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,638 | module | module InstructionMemoryTest();
reg [31:0] addr;
wire [31:0] data;
InstructionMemory mem(addr, data);
initial
begin
addr = 0;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 1;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 2;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 3;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 7;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 15;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 31;
#2 $display("At address %d, value is: %h",addr,data);
end
endmodule | module InstructionMemoryTest(); |
reg [31:0] addr;
wire [31:0] data;
InstructionMemory mem(addr, data);
initial
begin
addr = 0;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 1;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 2;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 3;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 7;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 15;
#2 $display("At address %d, value is: %h",addr,data);
#2 addr = 31;
#2 $display("At address %d, value is: %h",addr,data);
end
endmodule | 1 |
137,509 | data/full_repos/permissive/79090962/Verilog/Tests/OrTest.v | 79,090,962 | OrTest.v | v | 33 | 51 | [] | [] | [] | null | line:31: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/OrTest.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5 $display("a= %b\\nb= %b\\ny= %b", a, b, y);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/79090962/Verilog/Tests/OrTest.v:24: Cannot find file containing module: \'Or\'\n Or myOr(a,b,y);\n ^~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Or\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Or.v\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Or.sv\n Or\n Or.v\n Or.sv\n obj_dir/Or\n obj_dir/Or.v\n obj_dir/Or.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,642 | module | module OrTest();
reg [31:0] a , b;
wire [31:0] y;
Or myOr(a,b,y);
initial
begin
$display ("Testing or module.");
a = 32'b00001111000011110000000000000000;
b = 32'b00111100001000100010101010000001;
#5 $display("a= %b\nb= %b\ny= %b", a, b, y);
end
endmodule | module OrTest(); |
reg [31:0] a , b;
wire [31:0] y;
Or myOr(a,b,y);
initial
begin
$display ("Testing or module.");
a = 32'b00001111000011110000000000000000;
b = 32'b00111100001000100010101010000001;
#5 $display("a= %b\nb= %b\ny= %b", a, b, y);
end
endmodule | 1 |
137,510 | data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v | 79,090,962 | RegistersTest.v | v | 91 | 95 | [] | [] | [] | null | line:49: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:47: Unsupported: Ignoring delay on this delayed statement.\n #2 clock = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:49: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Writing %h to register %d.", writeData, writeReg);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:56: Unsupported: Ignoring delay on this delayed statement.\n #2 clock = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Writing %h to register %d.", writeData, writeReg);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:63: Unsupported: Ignoring delay on this delayed statement.\n #2clock = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:65: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Writing %h to register %d.", writeData, writeReg);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:70: Unsupported: Ignoring delay on this delayed statement.\n #2 clock = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Writing %h to register %d. This should have no effect.", writeData, writeReg);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:74: Unsupported: Ignoring delay on this delayed statement.\n #2 write = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:79: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Testing reads:");\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Content of register %d is: %h", ReadReg1 , out1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:81: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Content of register %d is: %h", ReadReg2 , out2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:83: Unsupported: Ignoring delay on this delayed statement.\n #2 ReadReg1 = 31;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:84: Unsupported: Ignoring delay on this delayed statement.\n #2 ReadReg2 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:85: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Content of register %d is: %h", ReadReg1 , out1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:86: Unsupported: Ignoring delay on this delayed statement.\n #2 $display("Content of register %d is: %h", ReadReg2 , out2);\n ^\n%Error: data/full_repos/permissive/79090962/Verilog/Tests/RegistersTest.v:37: Cannot find file containing module: \'Registers\'\n Registers registers(ReadReg1, ReadReg2, writeReg, clock, writeData, out1, out2 ,write);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Registers\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Registers.v\n data/full_repos/permissive/79090962/Verilog/Tests,data/full_repos/permissive/79090962/Registers.sv\n Registers\n Registers.v\n Registers.sv\n obj_dir/Registers\n obj_dir/Registers.v\n obj_dir/Registers.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 299,644 | module | module RegisterTest();
reg [4:0] ReadReg1;
reg [4:0] ReadReg2;
reg [4:0] writeReg;
reg clock;
reg [31:0] writeData;
wire [31:0] out1;
wire [31:0] out2;
reg write;
Registers registers(ReadReg1, ReadReg2, writeReg, clock, writeData, out1, out2 ,write);
initial
begin
$display("--Testing Register Module--");
clock = 1;
write = 1;
writeReg = 1;
writeData = 32'haaaaaaaa;
#2 clock = 0;
#2 $display("Writing %h to register %d.", writeData, writeReg);
clock = 1;
writeReg = 11;
writeData = 32'hbbbbbbbb;
#2 clock = 0;
#2 $display("Writing %h to register %d.", writeData, writeReg);
clock = 1;
writeReg = 31;
writeData = 32'hcccccccc;
#2clock = 0;
#2 $display("Writing %h to register %d.", writeData, writeReg);
clock = 1;
writeReg = 0;
writeData = 32'hdddddddd;
#2 clock = 0;
#2 $display("Writing %h to register %d. This should have no effect.", writeData, writeReg);
#2 write = 0;
ReadReg1 = 1;
ReadReg2 = 11;
#2 $display("Testing reads:");
#2 $display("Content of register %d is: %h", ReadReg1 , out1);
#2 $display("Content of register %d is: %h", ReadReg2 , out2);
#2 ReadReg1 = 31;
#2 ReadReg2 = 0;
#2 $display("Content of register %d is: %h", ReadReg1 , out1);
#2 $display("Content of register %d is: %h", ReadReg2 , out2);
end
endmodule | module RegisterTest(); |
reg [4:0] ReadReg1;
reg [4:0] ReadReg2;
reg [4:0] writeReg;
reg clock;
reg [31:0] writeData;
wire [31:0] out1;
wire [31:0] out2;
reg write;
Registers registers(ReadReg1, ReadReg2, writeReg, clock, writeData, out1, out2 ,write);
initial
begin
$display("--Testing Register Module--");
clock = 1;
write = 1;
writeReg = 1;
writeData = 32'haaaaaaaa;
#2 clock = 0;
#2 $display("Writing %h to register %d.", writeData, writeReg);
clock = 1;
writeReg = 11;
writeData = 32'hbbbbbbbb;
#2 clock = 0;
#2 $display("Writing %h to register %d.", writeData, writeReg);
clock = 1;
writeReg = 31;
writeData = 32'hcccccccc;
#2clock = 0;
#2 $display("Writing %h to register %d.", writeData, writeReg);
clock = 1;
writeReg = 0;
writeData = 32'hdddddddd;
#2 clock = 0;
#2 $display("Writing %h to register %d. This should have no effect.", writeData, writeReg);
#2 write = 0;
ReadReg1 = 1;
ReadReg2 = 11;
#2 $display("Testing reads:");
#2 $display("Content of register %d is: %h", ReadReg1 , out1);
#2 $display("Content of register %d is: %h", ReadReg2 , out2);
#2 ReadReg1 = 31;
#2 ReadReg2 = 0;
#2 $display("Content of register %d is: %h", ReadReg1 , out1);
#2 $display("Content of register %d is: %h", ReadReg2 , out2);
end
endmodule | 1 |
137,516 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D32.sv | 79,197,809 | CRC32_D32.sv | sv | 74 | 278 | [] | [] | [] | null | line:74: before: "al" | data/verilator_xmls/2e5416fd-b134-4da6-a34a-a9779bca79d4.xml | null | 299,762 | module | module CRC32_D32(input [31:0] data,input [31:0] crc,output [31:0] crc_nxt);
function [31:0] nextCRC32_D32;
input [31:0] Data;
input [31:0] crc;
reg [31:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[9] ^ c[10] ^ c[12] ^ c[16] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[1] = d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[16] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
newcrc[2] = d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[24] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[25] ^ c[27] ^ c[31];
newcrc[4] = d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[8] ^ c[11] ^ c[12] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[29] ^ c[30] ^ c[31];
newcrc[5] = d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[6] = d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[7] = d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[7] ^ c[8] ^ c[10] ^ c[15] ^ c[16] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29];
newcrc[8] = d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[8] ^ c[10] ^ c[11] ^ c[12] ^ c[17] ^ c[22] ^ c[23] ^ c[28] ^ c[31];
newcrc[9] = d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[18] ^ c[23] ^ c[24] ^ c[29];
newcrc[10] = d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[11] = d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
newcrc[12] = d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[12] ^ c[13] ^ c[15] ^ c[17] ^ c[18] ^ c[21] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[13] = d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[25] ^ c[28] ^ c[31];
newcrc[14] = d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[20] ^ c[23] ^ c[26] ^ c[29];
newcrc[15] = d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[15] ^ c[16] ^ c[18] ^ c[20] ^ c[21] ^ c[24] ^ c[27] ^ c[30];
newcrc[16] = d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[4] ^ c[5] ^ c[8] ^ c[12] ^ c[13] ^ c[17] ^ c[19] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[29] ^ c[30];
newcrc[17] = d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[5] ^ c[6] ^ c[9] ^ c[13] ^ c[14] ^ c[18] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[30] ^ c[31];
newcrc[18] = d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[31];
newcrc[19] = d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29];
newcrc[20] = d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[21] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[9] ^ c[10] ^ c[13] ^ c[17] ^ c[18] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[22] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[0] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[23] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[9] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[24] = d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[7] ^ c[10] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[27] ^ c[28] ^ c[30];
newcrc[25] = d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[8] ^ c[11] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[28] ^ c[29] ^ c[31];
newcrc[26] = d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[6] ^ c[10] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[31];
newcrc[27] = d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[1] ^ c[4] ^ c[5] ^ c[7] ^ c[11] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[29];
newcrc[28] = d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[2] ^ c[5] ^ c[6] ^ c[8] ^ c[12] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[29] = d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[3] ^ c[6] ^ c[7] ^ c[9] ^ c[13] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[30] = d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[14] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[31] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[5] ^ c[8] ^ c[9] ^ c[11] ^ c[15] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
nextCRC32_D32 = newcrc;
end
endfunction
assign crc_nxt = nextCRC32_D32(data,crc);
endmodule | module CRC32_D32(input [31:0] data,input [31:0] crc,output [31:0] crc_nxt); |
function [31:0] nextCRC32_D32;
input [31:0] Data;
input [31:0] crc;
reg [31:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[9] ^ c[10] ^ c[12] ^ c[16] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[1] = d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[16] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
newcrc[2] = d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[24] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[25] ^ c[27] ^ c[31];
newcrc[4] = d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[8] ^ c[11] ^ c[12] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[29] ^ c[30] ^ c[31];
newcrc[5] = d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[6] = d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[7] = d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[7] ^ c[8] ^ c[10] ^ c[15] ^ c[16] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29];
newcrc[8] = d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[8] ^ c[10] ^ c[11] ^ c[12] ^ c[17] ^ c[22] ^ c[23] ^ c[28] ^ c[31];
newcrc[9] = d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[18] ^ c[23] ^ c[24] ^ c[29];
newcrc[10] = d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[11] = d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
newcrc[12] = d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[12] ^ c[13] ^ c[15] ^ c[17] ^ c[18] ^ c[21] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[13] = d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[25] ^ c[28] ^ c[31];
newcrc[14] = d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[20] ^ c[23] ^ c[26] ^ c[29];
newcrc[15] = d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[15] ^ c[16] ^ c[18] ^ c[20] ^ c[21] ^ c[24] ^ c[27] ^ c[30];
newcrc[16] = d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[4] ^ c[5] ^ c[8] ^ c[12] ^ c[13] ^ c[17] ^ c[19] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[29] ^ c[30];
newcrc[17] = d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[5] ^ c[6] ^ c[9] ^ c[13] ^ c[14] ^ c[18] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[30] ^ c[31];
newcrc[18] = d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[31];
newcrc[19] = d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29];
newcrc[20] = d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[21] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[9] ^ c[10] ^ c[13] ^ c[17] ^ c[18] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[22] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[0] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[23] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[9] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[24] = d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[7] ^ c[10] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[27] ^ c[28] ^ c[30];
newcrc[25] = d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[8] ^ c[11] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[28] ^ c[29] ^ c[31];
newcrc[26] = d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[6] ^ c[10] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[31];
newcrc[27] = d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[1] ^ c[4] ^ c[5] ^ c[7] ^ c[11] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[29];
newcrc[28] = d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[2] ^ c[5] ^ c[6] ^ c[8] ^ c[12] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[29] = d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[3] ^ c[6] ^ c[7] ^ c[9] ^ c[13] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[30] = d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[14] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[31] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[5] ^ c[8] ^ c[9] ^ c[11] ^ c[15] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
nextCRC32_D32 = newcrc;
end
endfunction
assign crc_nxt = nextCRC32_D32(data,crc);
endmodule | 1 |
137,517 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D32.sv | 79,197,809 | CRC32_D32.sv | sv | 74 | 278 | [] | [] | [] | null | line:74: before: "al" | data/verilator_xmls/2e5416fd-b134-4da6-a34a-a9779bca79d4.xml | null | 299,762 | function | function [31:0] nextCRC32_D32;
input [31:0] Data;
input [31:0] crc;
reg [31:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[9] ^ c[10] ^ c[12] ^ c[16] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[1] = d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[16] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
newcrc[2] = d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[24] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[25] ^ c[27] ^ c[31];
newcrc[4] = d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[8] ^ c[11] ^ c[12] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[29] ^ c[30] ^ c[31];
newcrc[5] = d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[6] = d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[7] = d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[7] ^ c[8] ^ c[10] ^ c[15] ^ c[16] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29];
newcrc[8] = d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[8] ^ c[10] ^ c[11] ^ c[12] ^ c[17] ^ c[22] ^ c[23] ^ c[28] ^ c[31];
newcrc[9] = d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[18] ^ c[23] ^ c[24] ^ c[29];
newcrc[10] = d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[11] = d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
newcrc[12] = d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[12] ^ c[13] ^ c[15] ^ c[17] ^ c[18] ^ c[21] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[13] = d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[25] ^ c[28] ^ c[31];
newcrc[14] = d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[20] ^ c[23] ^ c[26] ^ c[29];
newcrc[15] = d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[15] ^ c[16] ^ c[18] ^ c[20] ^ c[21] ^ c[24] ^ c[27] ^ c[30];
newcrc[16] = d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[4] ^ c[5] ^ c[8] ^ c[12] ^ c[13] ^ c[17] ^ c[19] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[29] ^ c[30];
newcrc[17] = d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[5] ^ c[6] ^ c[9] ^ c[13] ^ c[14] ^ c[18] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[30] ^ c[31];
newcrc[18] = d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[31];
newcrc[19] = d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29];
newcrc[20] = d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[21] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[9] ^ c[10] ^ c[13] ^ c[17] ^ c[18] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[22] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[0] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[23] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[9] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[24] = d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[7] ^ c[10] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[27] ^ c[28] ^ c[30];
newcrc[25] = d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[8] ^ c[11] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[28] ^ c[29] ^ c[31];
newcrc[26] = d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[6] ^ c[10] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[31];
newcrc[27] = d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[1] ^ c[4] ^ c[5] ^ c[7] ^ c[11] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[29];
newcrc[28] = d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[2] ^ c[5] ^ c[6] ^ c[8] ^ c[12] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[29] = d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[3] ^ c[6] ^ c[7] ^ c[9] ^ c[13] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[30] = d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[14] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[31] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[5] ^ c[8] ^ c[9] ^ c[11] ^ c[15] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
nextCRC32_D32 = newcrc;
end
endfunction | function [31:0] nextCRC32_D32; |
input [31:0] Data;
input [31:0] crc;
reg [31:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[16] ^ d[12] ^ d[10] ^ d[9] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[9] ^ c[10] ^ c[12] ^ c[16] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[1] = d[28] ^ d[27] ^ d[24] ^ d[17] ^ d[16] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[7] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[16] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
newcrc[2] = d[31] ^ d[30] ^ d[26] ^ d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[24] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[31] ^ d[27] ^ d[25] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[14] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[25] ^ c[27] ^ c[31];
newcrc[4] = d[31] ^ d[30] ^ d[29] ^ d[25] ^ d[24] ^ d[20] ^ d[19] ^ d[18] ^ d[15] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[8] ^ c[11] ^ c[12] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[24] ^ c[25] ^ c[29] ^ c[30] ^ c[31];
newcrc[5] = d[29] ^ d[28] ^ d[24] ^ d[21] ^ d[20] ^ d[19] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[19] ^ c[20] ^ c[21] ^ c[24] ^ c[28] ^ c[29];
newcrc[6] = d[30] ^ d[29] ^ d[25] ^ d[22] ^ d[21] ^ d[20] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[20] ^ c[21] ^ c[22] ^ c[25] ^ c[29] ^ c[30];
newcrc[7] = d[29] ^ d[28] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[16] ^ d[15] ^ d[10] ^ d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[7] ^ c[8] ^ c[10] ^ c[15] ^ c[16] ^ c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[29];
newcrc[8] = d[31] ^ d[28] ^ d[23] ^ d[22] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[8] ^ c[10] ^ c[11] ^ c[12] ^ c[17] ^ c[22] ^ c[23] ^ c[28] ^ c[31];
newcrc[9] = d[29] ^ d[24] ^ d[23] ^ d[18] ^ d[13] ^ d[12] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[9] ^ c[11] ^ c[12] ^ c[13] ^ c[18] ^ c[23] ^ c[24] ^ c[29];
newcrc[10] = d[31] ^ d[29] ^ d[28] ^ d[26] ^ d[19] ^ d[16] ^ d[14] ^ d[13] ^ d[9] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[9] ^ c[13] ^ c[14] ^ c[16] ^ c[19] ^ c[26] ^ c[28] ^ c[29] ^ c[31];
newcrc[11] = d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[20] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[9] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[12] ^ c[14] ^ c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
newcrc[12] = d[31] ^ d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[9] ^ c[12] ^ c[13] ^ c[15] ^ c[17] ^ c[18] ^ c[21] ^ c[24] ^ c[27] ^ c[30] ^ c[31];
newcrc[13] = d[31] ^ d[28] ^ d[25] ^ d[22] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[13] ^ d[10] ^ d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[7] ^ c[10] ^ c[13] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[22] ^ c[25] ^ c[28] ^ c[31];
newcrc[14] = d[29] ^ d[26] ^ d[23] ^ d[20] ^ d[19] ^ d[17] ^ d[15] ^ d[14] ^ d[11] ^ d[8] ^ d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^ c[8] ^ c[11] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[20] ^ c[23] ^ c[26] ^ c[29];
newcrc[15] = d[30] ^ d[27] ^ d[24] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^ d[15] ^ d[12] ^ d[9] ^ d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[15] ^ c[16] ^ c[18] ^ c[20] ^ c[21] ^ c[24] ^ c[27] ^ c[30];
newcrc[16] = d[30] ^ d[29] ^ d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[13] ^ d[12] ^ d[8] ^ d[5] ^ d[4] ^ d[0] ^ c[0] ^ c[4] ^ c[5] ^ c[8] ^ c[12] ^ c[13] ^ c[17] ^ c[19] ^ c[21] ^ c[22] ^ c[24] ^ c[26] ^ c[29] ^ c[30];
newcrc[17] = d[31] ^ d[30] ^ d[27] ^ d[25] ^ d[23] ^ d[22] ^ d[20] ^ d[18] ^ d[14] ^ d[13] ^ d[9] ^ d[6] ^ d[5] ^ d[1] ^ c[1] ^ c[5] ^ c[6] ^ c[9] ^ c[13] ^ c[14] ^ c[18] ^ c[20] ^ c[22] ^ c[23] ^ c[25] ^ c[27] ^ c[30] ^ c[31];
newcrc[18] = d[31] ^ d[28] ^ d[26] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[15] ^ d[14] ^ d[10] ^ d[7] ^ d[6] ^ d[2] ^ c[2] ^ c[6] ^ c[7] ^ c[10] ^ c[14] ^ c[15] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^ c[28] ^ c[31];
newcrc[19] = d[29] ^ d[27] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[16] ^ d[15] ^ d[11] ^ d[8] ^ d[7] ^ d[3] ^ c[3] ^ c[7] ^ c[8] ^ c[11] ^ c[15] ^ c[16] ^ c[20] ^ c[22] ^ c[24] ^ c[25] ^ c[27] ^ c[29];
newcrc[20] = d[30] ^ d[28] ^ d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[17] ^ d[16] ^ d[12] ^ d[9] ^ d[8] ^ d[4] ^ c[4] ^ c[8] ^ c[9] ^ c[12] ^ c[16] ^ c[17] ^ c[21] ^ c[23] ^ c[25] ^ c[26] ^ c[28] ^ c[30];
newcrc[21] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[22] ^ d[18] ^ d[17] ^ d[13] ^ d[10] ^ d[9] ^ d[5] ^ c[5] ^ c[9] ^ c[10] ^ c[13] ^ c[17] ^ c[18] ^ c[22] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[22] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[19] ^ d[18] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^ d[9] ^ d[0] ^ c[0] ^ c[9] ^ c[11] ^ c[12] ^ c[14] ^ c[16] ^ c[18] ^ c[19] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[23] = d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[20] ^ d[19] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[9] ^ d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6] ^ c[9] ^ c[13] ^ c[15] ^ c[16] ^ c[17] ^ c[19] ^ c[20] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[24] = d[30] ^ d[28] ^ d[27] ^ d[21] ^ d[20] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[10] ^ d[7] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[7] ^ c[10] ^ c[14] ^ c[16] ^ c[17] ^ c[18] ^ c[20] ^ c[21] ^ c[27] ^ c[28] ^ c[30];
newcrc[25] = d[31] ^ d[29] ^ d[28] ^ d[22] ^ d[21] ^ d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[11] ^ d[8] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[8] ^ c[11] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[21] ^ c[22] ^ c[28] ^ c[29] ^ c[31];
newcrc[26] = d[31] ^ d[28] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[18] ^ d[10] ^ d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[0] ^ c[3] ^ c[4] ^ c[6] ^ c[10] ^ c[18] ^ c[19] ^ c[20] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[31];
newcrc[27] = d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[11] ^ d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[1] ^ c[4] ^ c[5] ^ c[7] ^ c[11] ^ c[19] ^ c[20] ^ c[21] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[29];
newcrc[28] = d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[20] ^ d[12] ^ d[8] ^ d[6] ^ d[5] ^ d[2] ^ c[2] ^ c[5] ^ c[6] ^ c[8] ^ c[12] ^ c[20] ^ c[21] ^ c[22] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[29] = d[31] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[23] ^ d[22] ^ d[21] ^ d[13] ^ d[9] ^ d[7] ^ d[6] ^ d[3] ^ c[3] ^ c[6] ^ c[7] ^ c[9] ^ c[13] ^ c[21] ^ c[22] ^ c[23] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[30] = d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[24] ^ d[23] ^ d[22] ^ d[14] ^ d[10] ^ d[8] ^ d[7] ^ d[4] ^ c[4] ^ c[7] ^ c[8] ^ c[10] ^ c[14] ^ c[22] ^ c[23] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
newcrc[31] = d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[27] ^ d[25] ^ d[24] ^ d[23] ^ d[15] ^ d[11] ^ d[9] ^ d[8] ^ d[5] ^ c[5] ^ c[8] ^ c[9] ^ c[11] ^ c[15] ^ c[23] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
nextCRC32_D32 = newcrc;
end
endfunction | 1 |
137,519 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D48.sv | 79,197,809 | CRC32_D48.sv | sv | 8 | 76 | [] | [] | [] | [(1, 7)] | null | null | 1: b"%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D48.sv:4: Cannot find file containing module: 'CRC32_D32'\n CRC32_D32 crc32(data[47:16],crc,crc_temp);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl,data/full_repos/permissive/79197809/CRC32_D32\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl,data/full_repos/permissive/79197809/CRC32_D32.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl,data/full_repos/permissive/79197809/CRC32_D32.sv\n CRC32_D32\n CRC32_D32.v\n CRC32_D32.sv\n obj_dir/CRC32_D32\n obj_dir/CRC32_D32.v\n obj_dir/CRC32_D32.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D48.sv:5: Cannot find file containing module: 'CRC32_D16'\n CRC32_D16 crc16(data[15:0],crc_temp,crc_nxt);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 299,764 | module | module CRC32_D48(input [47:0] data,input [31:0] crc,output [31:0] crc_nxt);
reg [31:0] crc_temp;
CRC32_D32 crc32(data[47:16],crc,crc_temp);
CRC32_D16 crc16(data[15:0],crc_temp,crc_nxt);
endmodule | module CRC32_D48(input [47:0] data,input [31:0] crc,output [31:0] crc_nxt); |
reg [31:0] crc_temp;
CRC32_D32 crc32(data[47:16],crc,crc_temp);
CRC32_D16 crc16(data[15:0],crc_temp,crc_nxt);
endmodule | 1 |
137,520 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D56.sv | 79,197,809 | CRC32_D56.sv | sv | 7 | 77 | [] | [] | [] | [(1, 6)] | null | null | 1: b"%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D56.sv:3: Cannot find file containing module: 'CRC32_D48'\n CRC32_D48 crc48(data[55:8],crc,crc_temp);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl,data/full_repos/permissive/79197809/CRC32_D48\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl,data/full_repos/permissive/79197809/CRC32_D48.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl,data/full_repos/permissive/79197809/CRC32_D48.sv\n CRC32_D48\n CRC32_D48.v\n CRC32_D48.sv\n obj_dir/CRC32_D48\n obj_dir/CRC32_D48.v\n obj_dir/CRC32_D48.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D56.sv:4: Cannot find file containing module: 'CRC32_D8'\n CRC32_D8 crc8 (data[7:0],crc_temp,crc_nxt);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 299,765 | module | module CRC32_D56(input [55:0] data,input [31:0] crc,output [31:0] crc_nxt);
reg [31:0] crc_temp;
CRC32_D48 crc48(data[55:8],crc,crc_temp);
CRC32_D8 crc8 (data[7:0],crc_temp,crc_nxt);
endmodule | module CRC32_D56(input [55:0] data,input [31:0] crc,output [31:0] crc_nxt); |
reg [31:0] crc_temp;
CRC32_D48 crc48(data[55:8],crc,crc_temp);
CRC32_D8 crc8 (data[7:0],crc_temp,crc_nxt);
endmodule | 1 |
137,523 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D8.sv | 79,197,809 | CRC32_D8.sv | sv | 73 | 120 | [] | [] | [] | [(19, 72)] | null | data/verilator_xmls/49276deb-4e7b-45cb-8b3b-6a23c6186b78.xml | null | 299,767 | module | module CRC32_D8(input [7:0] data,input [31:0] crc, output [31:0] crc_nxt);
function [31:0] nextCRC32_D8;
input [7:0] Data;
input [31:0] crc;
reg [7:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[6] ^ d[0] ^ c[24] ^ c[30];
newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[30] ^ c[31];
newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[24] ^ c[26] ^ c[27] ^ c[29];
newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[25] ^ c[26] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[10] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[7] ^ d[3] ^ c[11] ^ c[27] ^ c[31];
newcrc[20] = d[4] ^ c[12] ^ c[28];
newcrc[21] = d[5] ^ c[13] ^ c[29];
newcrc[22] = d[0] ^ c[14] ^ c[24];
newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[15] ^ c[24] ^ c[25] ^ c[30];
newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[16] ^ c[25] ^ c[26] ^ c[31];
newcrc[25] = d[3] ^ d[2] ^ c[17] ^ c[26] ^ c[27];
newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[18] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[19] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[20] ^ c[26] ^ c[29] ^ c[30];
newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[21] ^ c[27] ^ c[30] ^ c[31];
newcrc[30] = d[7] ^ d[4] ^ c[22] ^ c[28] ^ c[31];
newcrc[31] = d[5] ^ c[23] ^ c[29];
nextCRC32_D8 = newcrc;
end
endfunction
assign crc_nxt= nextCRC32_D8(data,crc);
endmodule | module CRC32_D8(input [7:0] data,input [31:0] crc, output [31:0] crc_nxt); |
function [31:0] nextCRC32_D8;
input [7:0] Data;
input [31:0] crc;
reg [7:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[6] ^ d[0] ^ c[24] ^ c[30];
newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[30] ^ c[31];
newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[24] ^ c[26] ^ c[27] ^ c[29];
newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[25] ^ c[26] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[10] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[7] ^ d[3] ^ c[11] ^ c[27] ^ c[31];
newcrc[20] = d[4] ^ c[12] ^ c[28];
newcrc[21] = d[5] ^ c[13] ^ c[29];
newcrc[22] = d[0] ^ c[14] ^ c[24];
newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[15] ^ c[24] ^ c[25] ^ c[30];
newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[16] ^ c[25] ^ c[26] ^ c[31];
newcrc[25] = d[3] ^ d[2] ^ c[17] ^ c[26] ^ c[27];
newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[18] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[19] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[20] ^ c[26] ^ c[29] ^ c[30];
newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[21] ^ c[27] ^ c[30] ^ c[31];
newcrc[30] = d[7] ^ d[4] ^ c[22] ^ c[28] ^ c[31];
newcrc[31] = d[5] ^ c[23] ^ c[29];
nextCRC32_D8 = newcrc;
end
endfunction
assign crc_nxt= nextCRC32_D8(data,crc);
endmodule | 1 |
137,524 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/CRC32_D8.sv | 79,197,809 | CRC32_D8.sv | sv | 73 | 120 | [] | [] | [] | [(19, 72)] | null | data/verilator_xmls/49276deb-4e7b-45cb-8b3b-6a23c6186b78.xml | null | 299,767 | function | function [31:0] nextCRC32_D8;
input [7:0] Data;
input [31:0] crc;
reg [7:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[6] ^ d[0] ^ c[24] ^ c[30];
newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[30] ^ c[31];
newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[24] ^ c[26] ^ c[27] ^ c[29];
newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[25] ^ c[26] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[10] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[7] ^ d[3] ^ c[11] ^ c[27] ^ c[31];
newcrc[20] = d[4] ^ c[12] ^ c[28];
newcrc[21] = d[5] ^ c[13] ^ c[29];
newcrc[22] = d[0] ^ c[14] ^ c[24];
newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[15] ^ c[24] ^ c[25] ^ c[30];
newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[16] ^ c[25] ^ c[26] ^ c[31];
newcrc[25] = d[3] ^ d[2] ^ c[17] ^ c[26] ^ c[27];
newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[18] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[19] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[20] ^ c[26] ^ c[29] ^ c[30];
newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[21] ^ c[27] ^ c[30] ^ c[31];
newcrc[30] = d[7] ^ d[4] ^ c[22] ^ c[28] ^ c[31];
newcrc[31] = d[5] ^ c[23] ^ c[29];
nextCRC32_D8 = newcrc;
end
endfunction | function [31:0] nextCRC32_D8; |
input [7:0] Data;
input [31:0] crc;
reg [7:0] d;
reg [31:0] c;
reg [31:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[6] ^ d[0] ^ c[24] ^ c[30];
newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[30] ^ c[31];
newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31];
newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[27] ^ c[31];
newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30];
newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31];
newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29];
newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[24] ^ c[26] ^ c[27] ^ c[29];
newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[24] ^ c[25] ^ c[27] ^ c[28];
newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30];
newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[25] ^ c[26] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31];
newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[27] ^ c[28] ^ c[29] ^ c[31];
newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[24] ^ c[28] ^ c[29];
newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[25] ^ c[29] ^ c[30];
newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[10] ^ c[26] ^ c[30] ^ c[31];
newcrc[19] = d[7] ^ d[3] ^ c[11] ^ c[27] ^ c[31];
newcrc[20] = d[4] ^ c[12] ^ c[28];
newcrc[21] = d[5] ^ c[13] ^ c[29];
newcrc[22] = d[0] ^ c[14] ^ c[24];
newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[15] ^ c[24] ^ c[25] ^ c[30];
newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[16] ^ c[25] ^ c[26] ^ c[31];
newcrc[25] = d[3] ^ d[2] ^ c[17] ^ c[26] ^ c[27];
newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[18] ^ c[24] ^ c[27] ^ c[28] ^ c[30];
newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[19] ^ c[25] ^ c[28] ^ c[29] ^ c[31];
newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[20] ^ c[26] ^ c[29] ^ c[30];
newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[21] ^ c[27] ^ c[30] ^ c[31];
newcrc[30] = d[7] ^ d[4] ^ c[22] ^ c[28] ^ c[31];
newcrc[31] = d[5] ^ c[23] ^ c[29];
nextCRC32_D8 = newcrc;
end
endfunction | 1 |
137,529 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo.sv | 79,197,809 | dma_fifo.sv | sv | 79 | 100 | [] | [] | [] | null | line:11: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo.sv:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dma_fifo\'\nmodule dma_fifo(clks,push,pull,data_in,data_out,depth_left,full,empty);\n ^~~~~~~~\n : ... Top module \'AXI_clks\'\nAXI_clks.to_rtl clks;\n^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo.sv:11: Unsupported: Interfaced port on top level module\nAXI_clks.to_rtl clks;\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo.sv:11: Cannot find file containing interface: \'AXI_clks\'\nAXI_clks.to_rtl clks;\n^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo.sv:11: ../V3LinkDot.cpp:2055: Unlinked interface\nAXI_clks.to_rtl clks;\n^~~~~~~~\n' | 299,771 | module | module dma_fifo(clks,push,pull,data_in,data_out,depth_left,full,empty);
parameter DWIDTH = 32;
parameter AWIDTH = 32;
parameter FIFO_DEPTH = (1<<AWIDTH);
AXI_clks.to_rtl clks;
input push,pull;
input [DWIDTH-1:0] data_in;
output [DWIDTH-1:0] data_out;
output reg [AWIDTH:0] depth_left;
output full,empty;
reg [AWIDTH-1:0] w_ptr,r_ptr;
reg [DWIDTH-1:0] data_mem[0:FIFO_DEPTH-1];
reg [DWIDTH-1:0] reg_0;
reg [DWIDTH-1:0] reg_1;
reg [DWIDTH-1:0] reg_2;
assign reg_0 = data_mem[0];
assign reg_1 = data_mem[1];
assign reg_2 = data_mem[2];
assign data_out = !clks.rst ? 0:data_mem[r_ptr];
assign full = (depth_left == 0);
assign empty = (depth_left == FIFO_DEPTH);
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
w_ptr <= #0 0;
r_ptr <= #0 0;
depth_left <= #0 FIFO_DEPTH;
end else begin
if(pull && !push && !empty) begin
r_ptr <= #1 r_ptr + 1;
depth_left <= #1 depth_left +1;
end
if(!pull && push && !full) begin
w_ptr <= #1 w_ptr + 1;
depth_left <= #1 depth_left -1;
data_mem[w_ptr] <= #1 data_in;
end
if(push && pull && !empty && !full) begin
r_ptr <= #1 r_ptr + 1;
w_ptr <= #1 w_ptr + 1;
data_mem[w_ptr] <= #1 data_in;
end
end
end
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(full && push)) ) ;
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(empty && pull))) ;
endmodule | module dma_fifo(clks,push,pull,data_in,data_out,depth_left,full,empty); |
parameter DWIDTH = 32;
parameter AWIDTH = 32;
parameter FIFO_DEPTH = (1<<AWIDTH);
AXI_clks.to_rtl clks;
input push,pull;
input [DWIDTH-1:0] data_in;
output [DWIDTH-1:0] data_out;
output reg [AWIDTH:0] depth_left;
output full,empty;
reg [AWIDTH-1:0] w_ptr,r_ptr;
reg [DWIDTH-1:0] data_mem[0:FIFO_DEPTH-1];
reg [DWIDTH-1:0] reg_0;
reg [DWIDTH-1:0] reg_1;
reg [DWIDTH-1:0] reg_2;
assign reg_0 = data_mem[0];
assign reg_1 = data_mem[1];
assign reg_2 = data_mem[2];
assign data_out = !clks.rst ? 0:data_mem[r_ptr];
assign full = (depth_left == 0);
assign empty = (depth_left == FIFO_DEPTH);
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
w_ptr <= #0 0;
r_ptr <= #0 0;
depth_left <= #0 FIFO_DEPTH;
end else begin
if(pull && !push && !empty) begin
r_ptr <= #1 r_ptr + 1;
depth_left <= #1 depth_left +1;
end
if(!pull && push && !full) begin
w_ptr <= #1 w_ptr + 1;
depth_left <= #1 depth_left -1;
data_mem[w_ptr] <= #1 data_in;
end
if(push && pull && !empty && !full) begin
r_ptr <= #1 r_ptr + 1;
w_ptr <= #1 w_ptr + 1;
data_mem[w_ptr] <= #1 data_in;
end
end
end
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(full && push)) ) ;
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(empty && pull))) ;
endmodule | 1 |
137,530 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo_exmem_pktc.sv | 79,197,809 | dma_fifo_exmem_pktc.sv | sv | 81 | 100 | [] | [] | [] | null | line:11: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo_exmem_pktc.sv:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dma_fifo_exmem_pktc\'\nmodule dma_fifo_exmem_pktc(clks,push,pull,data_in,data_out,depth_left,full,empty,memif);\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'AXI_clks\'\nAXI_clks.to_rtl clks;\n^~~~~~~~\n : ... Top module \'MEMIF_PKTC\'\nMEMIF_PKTC.from_fifo memif;\n^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo_exmem_pktc.sv:11: Unsupported: Interfaced port on top level module\nAXI_clks.to_rtl clks;\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo_exmem_pktc.sv:17: Unsupported: Interfaced port on top level module\nMEMIF_PKTC.from_fifo memif;\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo_exmem_pktc.sv:11: Cannot find file containing interface: \'AXI_clks\'\nAXI_clks.to_rtl clks;\n^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo_exmem_pktc.sv:17: Cannot find file containing interface: \'MEMIF_PKTC\'\nMEMIF_PKTC.from_fifo memif;\n^~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/dma_fifo_exmem_pktc.sv:17: ../V3LinkDot.cpp:2055: Unlinked interface\nMEMIF_PKTC.from_fifo memif;\n^~~~~~~~~~\n' | 299,774 | module | module dma_fifo_exmem_pktc(clks,push,pull,data_in,data_out,depth_left,full,empty,memif);
parameter DWIDTH = 64;
parameter AWIDTH = 8;
parameter FIFO_DEPTH = (1<<AWIDTH);
AXI_clks.to_rtl clks;
input push,pull;
input [DWIDTH-1:0] data_in;
output [DWIDTH-1:0] data_out;
output reg [AWIDTH:0] depth_left;
output full,empty;
MEMIF_PKTC.from_fifo memif;
reg [AWIDTH-1:0] w_ptr,r_ptr;
assign memif.f0_waddr = w_ptr;
assign memif.f0_wdata = data_in;
assign memif.f0_write = push;
assign memif.f0_raddr = r_ptr;
assign data_out = !clks.rst ? 0 : memif.f0_rdata;
assign full = (depth_left == 0);
assign empty = (depth_left == FIFO_DEPTH);
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
w_ptr <= #0 0;
r_ptr <= #0 0;
depth_left <= #0 FIFO_DEPTH;
end else begin
if(pull && !push && !empty) begin
r_ptr <= #1 r_ptr + 1;
depth_left <= #1 depth_left +1;
end
if(!pull && push && !full) begin
w_ptr <= #1 w_ptr + 1;
depth_left <= #1 depth_left -1;
end
if(push && pull && !empty && !full) begin
r_ptr <= #1 r_ptr + 1;
w_ptr <= #1 w_ptr + 1;
end
end
end
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(full && push)) ) ;
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(empty && pull))) ;
endmodule | module dma_fifo_exmem_pktc(clks,push,pull,data_in,data_out,depth_left,full,empty,memif); |
parameter DWIDTH = 64;
parameter AWIDTH = 8;
parameter FIFO_DEPTH = (1<<AWIDTH);
AXI_clks.to_rtl clks;
input push,pull;
input [DWIDTH-1:0] data_in;
output [DWIDTH-1:0] data_out;
output reg [AWIDTH:0] depth_left;
output full,empty;
MEMIF_PKTC.from_fifo memif;
reg [AWIDTH-1:0] w_ptr,r_ptr;
assign memif.f0_waddr = w_ptr;
assign memif.f0_wdata = data_in;
assign memif.f0_write = push;
assign memif.f0_raddr = r_ptr;
assign data_out = !clks.rst ? 0 : memif.f0_rdata;
assign full = (depth_left == 0);
assign empty = (depth_left == FIFO_DEPTH);
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
w_ptr <= #0 0;
r_ptr <= #0 0;
depth_left <= #0 FIFO_DEPTH;
end else begin
if(pull && !push && !empty) begin
r_ptr <= #1 r_ptr + 1;
depth_left <= #1 depth_left +1;
end
if(!pull && push && !full) begin
w_ptr <= #1 w_ptr + 1;
depth_left <= #1 depth_left -1;
end
if(push && pull && !empty && !full) begin
r_ptr <= #1 r_ptr + 1;
w_ptr <= #1 w_ptr + 1;
end
end
end
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(full && push)) ) ;
assert property ( @(posedge clks.clk) disable iff (!clks.rst) (!(empty && pull))) ;
endmodule | 1 |
137,531 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv | 79,197,809 | eth_core.sv | sv | 55 | 81 | [] | [] | [] | null | line:1: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:1: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'eth_core\'\nmodule eth_core(AXI_clks.to_rtl clks,\n ^~~~~~~~\n : ... Top module \'AXI_clks\'\nmodule eth_core(AXI_clks.to_rtl clks,\n ^~~~~~~~\n : ... Top module \'AXI_wr_addr_ch\'\n AXI_wr_addr_ch.slave_if w_ach,\n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_wr_data_ch\'\n AXI_wr_data_ch.slave_if w_dch,\n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_wr_resp_ch\'\n AXI_wr_resp_ch.slave_if w_rspch, \n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_rd_addr_ch\'\n AXI_rd_addr_ch.master_if m_r_ach,\n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_rd_data_ch\'\n AXI_rd_data_ch.master_if m_r_dch,\n ^~~~~~~~~~~~~~\n : ... Top module \'tx_xgmii\'\n tx_xgmii.from_rtl xgmii_tx,\n ^~~~~~~~\n : ... Top module \'MEMIF_CRC\'\n MEMIF_CRC.from_fifo memif_crcf0,\n ^~~~~~~~~\n : ... Top module \'MEMIF_PKTD\'\n MEMIF_PKTD.from_fifo memif_pdfifo0,\n ^~~~~~~~~~\n : ... Top module \'MEMIF_PKTC\'\n MEMIF_PKTC.from_fifo memif_pcfifo0,\n ^~~~~~~~~~\n : ... Top module \'MEMIF_SWCHADDR\'\n MEMIF_SWCHADDR.from_fifo memif_swchaddr, \n ^~~~~~~~~~~~~~\n : ... Top module \'MEMIF_SWCHDATA\'\n MEMIF_SWCHDATA.from_fifo memif_swchdata, \n ^~~~~~~~~~~~~~\n : ... Top module \'MEMIF_SWCHRSP\'\n MEMIF_SWCHRSP.from_fifo memif_swchrsp \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:1: Unsupported: Interfaced port on top level module\nmodule eth_core(AXI_clks.to_rtl clks,\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:4: Unsupported: Interfaced port on top level module\n AXI_wr_addr_ch.slave_if w_ach,\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:5: Unsupported: Interfaced port on top level module\n AXI_wr_data_ch.slave_if w_dch,\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:6: Unsupported: Interfaced port on top level module\n AXI_wr_resp_ch.slave_if w_rspch, \n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:7: Unsupported: Interfaced port on top level module\n AXI_rd_addr_ch.master_if m_r_ach,\n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:8: Unsupported: Interfaced port on top level module\n AXI_rd_data_ch.master_if m_r_dch,\n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:9: Unsupported: Interfaced port on top level module\n tx_xgmii.from_rtl xgmii_tx,\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:10: Unsupported: Interfaced port on top level module\n MEMIF_CRC.from_fifo memif_crcf0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:11: Unsupported: Interfaced port on top level module\n MEMIF_CRC.from_fifo memif_crcf1,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:12: Unsupported: Interfaced port on top level module\n MEMIF_CRC.from_fifo memif_crcf2,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:13: Unsupported: Interfaced port on top level module\n MEMIF_PKTD.from_fifo memif_pdfifo0,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:14: Unsupported: Interfaced port on top level module\n MEMIF_PKTD.from_fifo memif_pdfifo1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:15: Unsupported: Interfaced port on top level module\n MEMIF_PKTD.from_fifo memif_pdfifo2, \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:16: Unsupported: Interfaced port on top level module\n MEMIF_PKTC.from_fifo memif_pcfifo0,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:17: Unsupported: Interfaced port on top level module\n MEMIF_PKTC.from_fifo memif_pcfifo1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:18: Unsupported: Interfaced port on top level module\n MEMIF_PKTC.from_fifo memif_pcfifo2, \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:19: Unsupported: Interfaced port on top level module\n MEMIF_SWCHADDR.from_fifo memif_swchaddr, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:20: Unsupported: Interfaced port on top level module\n MEMIF_SWCHDATA.from_fifo memif_swchdata, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:21: Unsupported: Interfaced port on top level module\n MEMIF_SWCHRSP.from_fifo memif_swchrsp \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:1: Cannot find file containing interface: \'AXI_clks\'\nmodule eth_core(AXI_clks.to_rtl clks,\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:4: Cannot find file containing interface: \'AXI_wr_addr_ch\'\n AXI_wr_addr_ch.slave_if w_ach,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:5: Cannot find file containing interface: \'AXI_wr_data_ch\'\n AXI_wr_data_ch.slave_if w_dch,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:6: Cannot find file containing interface: \'AXI_wr_resp_ch\'\n AXI_wr_resp_ch.slave_if w_rspch, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:7: Cannot find file containing interface: \'AXI_rd_addr_ch\'\n AXI_rd_addr_ch.master_if m_r_ach,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:8: Cannot find file containing interface: \'AXI_rd_data_ch\'\n AXI_rd_data_ch.master_if m_r_dch,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:9: Cannot find file containing interface: \'tx_xgmii\'\n tx_xgmii.from_rtl xgmii_tx,\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:10: Cannot find file containing interface: \'MEMIF_CRC\'\n MEMIF_CRC.from_fifo memif_crcf0,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:11: Cannot find file containing interface: \'MEMIF_CRC\'\n MEMIF_CRC.from_fifo memif_crcf1,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:12: Cannot find file containing interface: \'MEMIF_CRC\'\n MEMIF_CRC.from_fifo memif_crcf2,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:13: Cannot find file containing interface: \'MEMIF_PKTD\'\n MEMIF_PKTD.from_fifo memif_pdfifo0,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:14: Cannot find file containing interface: \'MEMIF_PKTD\'\n MEMIF_PKTD.from_fifo memif_pdfifo1,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:15: Cannot find file containing interface: \'MEMIF_PKTD\'\n MEMIF_PKTD.from_fifo memif_pdfifo2, \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:16: Cannot find file containing interface: \'MEMIF_PKTC\'\n MEMIF_PKTC.from_fifo memif_pcfifo0,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:17: Cannot find file containing interface: \'MEMIF_PKTC\'\n MEMIF_PKTC.from_fifo memif_pcfifo1,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:18: Cannot find file containing interface: \'MEMIF_PKTC\'\n MEMIF_PKTC.from_fifo memif_pcfifo2, \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:19: Cannot find file containing interface: \'MEMIF_SWCHADDR\'\n MEMIF_SWCHADDR.from_fifo memif_swchaddr, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:20: Cannot find file containing interface: \'MEMIF_SWCHDATA\'\n MEMIF_SWCHDATA.from_fifo memif_swchdata, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/eth_core.sv:21: Cannot find file containing interface: \'MEMIF_SWCHRSP\'\n MEMIF_SWCHRSP.from_fifo memif_swchrsp \n ^~~~~~~~~~~~~\n%Error: Exiting due to 38 error(s), 1 warning(s)\n' | 299,779 | module | module eth_core(AXI_clks.to_rtl clks,
AXI_wr_addr_ch.slave_if w_ach,
AXI_wr_data_ch.slave_if w_dch,
AXI_wr_resp_ch.slave_if w_rspch,
AXI_rd_addr_ch.master_if m_r_ach,
AXI_rd_data_ch.master_if m_r_dch,
tx_xgmii.from_rtl xgmii_tx,
MEMIF_CRC.from_fifo memif_crcf0,
MEMIF_CRC.from_fifo memif_crcf1,
MEMIF_CRC.from_fifo memif_crcf2,
MEMIF_PKTD.from_fifo memif_pdfifo0,
MEMIF_PKTD.from_fifo memif_pdfifo1,
MEMIF_PKTD.from_fifo memif_pdfifo2,
MEMIF_PKTC.from_fifo memif_pcfifo0,
MEMIF_PKTC.from_fifo memif_pcfifo1,
MEMIF_PKTC.from_fifo memif_pcfifo2,
MEMIF_SWCHADDR.from_fifo memif_swchaddr,
MEMIF_SWCHDATA.from_fifo memif_swchdata,
MEMIF_SWCHRSP.from_fifo memif_swchrsp
);
eth_tx tx_core ( clks,
w_ach,
w_dch,
w_rspch,
m_r_ach,
m_r_dch,
xgmii_tx,
memif_crcf0,
memif_crcf1,
memif_crcf2,
memif_pdfifo0,
memif_pdfifo1,
memif_pdfifo2,
memif_pcfifo0,
memif_pcfifo1,
memif_pcfifo2,
memif_swchaddr,
memif_swchdata,
memif_swchrsp
);
endmodule | module eth_core(AXI_clks.to_rtl clks,
AXI_wr_addr_ch.slave_if w_ach,
AXI_wr_data_ch.slave_if w_dch,
AXI_wr_resp_ch.slave_if w_rspch,
AXI_rd_addr_ch.master_if m_r_ach,
AXI_rd_data_ch.master_if m_r_dch,
tx_xgmii.from_rtl xgmii_tx,
MEMIF_CRC.from_fifo memif_crcf0,
MEMIF_CRC.from_fifo memif_crcf1,
MEMIF_CRC.from_fifo memif_crcf2,
MEMIF_PKTD.from_fifo memif_pdfifo0,
MEMIF_PKTD.from_fifo memif_pdfifo1,
MEMIF_PKTD.from_fifo memif_pdfifo2,
MEMIF_PKTC.from_fifo memif_pcfifo0,
MEMIF_PKTC.from_fifo memif_pcfifo1,
MEMIF_PKTC.from_fifo memif_pcfifo2,
MEMIF_SWCHADDR.from_fifo memif_swchaddr,
MEMIF_SWCHDATA.from_fifo memif_swchdata,
MEMIF_SWCHRSP.from_fifo memif_swchrsp
); |
eth_tx tx_core ( clks,
w_ach,
w_dch,
w_rspch,
m_r_ach,
m_r_dch,
xgmii_tx,
memif_crcf0,
memif_crcf1,
memif_crcf2,
memif_pdfifo0,
memif_pdfifo1,
memif_pdfifo2,
memif_pcfifo0,
memif_pcfifo1,
memif_pcfifo2,
memif_swchaddr,
memif_swchdata,
memif_swchrsp
);
endmodule | 1 |
137,534 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/mem_model_swchdata.sv | 79,197,809 | mem_model_swchdata.sv | sv | 48 | 78 | [] | [] | [] | null | line:10: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/mem_model_swchdata.sv:10: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'mem_model_swchdata\'\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'MEMIF_SWCHDATA\'\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_clks\'\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/mem_model_swchdata.sv:10: Unsupported: Interfaced port on top level module\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/mem_model_swchdata.sv:10: Unsupported: Interfaced port on top level module\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/mem_model_swchdata.sv:10: Cannot find file containing interface: \'MEMIF_SWCHDATA\'\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/mem_model_swchdata.sv:10: Cannot find file containing interface: \'AXI_clks\'\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/mem_model_swchdata.sv:10: ../V3LinkDot.cpp:2055: Unlinked interface\nmodule mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);\n ^~~~~~~~~~~~~~\n' | 299,788 | module | module mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks);
parameter DWIDTH = 32;
parameter AWIDTH = 32;
parameter MEM_DEPTH = (1<<AWIDTH);
logic [AWIDTH-1:0] waddr;
logic [DWIDTH-1:0] wdata;
logic write;
logic [AWIDTH-1:0] raddr;
logic [DWIDTH-1:0] rdata;
assign waddr = memif.f0_waddr;
assign wdata = memif.f0_wdata;
assign write = memif.f0_write;
assign raddr = memif.f0_raddr;
assign memif.f0_rdata = rdata;
reg [DWIDTH-1:0] mem[0:MEM_DEPTH-1];
logic [DWIDTH-1:0] m00,m01,m02,m03;
assign m00=mem[0];
assign m01=mem[1];
assign m02=mem[2];
assign m03=mem[3];
always @(*) begin
rdata <= #1 mem[raddr];
end
always @(posedge(clks.clk)) begin
if(write) begin
mem[waddr]<=#1 wdata;
end
end
endmodule | module mem_model_swchdata(MEMIF_SWCHDATA.to_mem memif,AXI_clks.to_rtl clks); |
parameter DWIDTH = 32;
parameter AWIDTH = 32;
parameter MEM_DEPTH = (1<<AWIDTH);
logic [AWIDTH-1:0] waddr;
logic [DWIDTH-1:0] wdata;
logic write;
logic [AWIDTH-1:0] raddr;
logic [DWIDTH-1:0] rdata;
assign waddr = memif.f0_waddr;
assign wdata = memif.f0_wdata;
assign write = memif.f0_write;
assign raddr = memif.f0_raddr;
assign memif.f0_rdata = rdata;
reg [DWIDTH-1:0] mem[0:MEM_DEPTH-1];
logic [DWIDTH-1:0] m00,m01,m02,m03;
assign m00=mem[0];
assign m01=mem[1];
assign m02=mem[2];
assign m03=mem[3];
always @(*) begin
rdata <= #1 mem[raddr];
end
always @(posedge(clks.clk)) begin
if(write) begin
mem[waddr]<=#1 wdata;
end
end
endmodule | 1 |
137,535 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/Packet_queue.sv | 79,197,809 | Packet_queue.sv | sv | 16 | 57 | [] | [] | [] | null | line:2: before: "." | null | 1: b"%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/Packet_queue.sv:11: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/Packet_queue.sv:15: syntax error, unexpected endmodule\nendmodule \n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 299,790 | module | module Packet_queue_sm(
AXI_clks.to_rtl clks,
input valid,
input [63:0] head_ptr,
output [2:0] channel_id,
output [63:0] head_ptr_to_axi,
);
reg [2:0] req_hptr_vec,gnt_hpt_vec;
reg [2:0] push_ptr_vec,push_ptr_gnt;
endmodule | module Packet_queue_sm(
AXI_clks.to_rtl clks,
input valid,
input [63:0] head_ptr,
output [2:0] channel_id,
output [63:0] head_ptr_to_axi,
); |
reg [2:0] req_hptr_vec,gnt_hpt_vec;
reg [2:0] push_ptr_vec,push_ptr_gnt;
endmodule | 1 |
137,537 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/QOS_arb.sv | 79,197,809 | QOS_arb.sv | sv | 100 | 74 | [] | [] | [] | null | line:9: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/QOS_arb.sv:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'QOS_arb\'\nmodule QOS_arb(\n ^~~~~~~\n : ... Top module \'AXI_clks\'\nAXI_clks.to_rtl clks,\n^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/QOS_arb.sv:9: Unsupported: Interfaced port on top level module\nAXI_clks.to_rtl clks,\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/QOS_arb.sv:9: Cannot find file containing interface: \'AXI_clks\'\nAXI_clks.to_rtl clks,\n^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/QOS_arb.sv:9: ../V3LinkDot.cpp:2055: Unlinked interface\nAXI_clks.to_rtl clks,\n^~~~~~~~\n' | 299,792 | module | module QOS_arb(
AXI_clks.to_rtl clks,
input [2:0] req,
input arb_nxt,
output [2:0] gnt
);
reg en0,en1,en2;
reg en0_d,en1_d,en2_d;
wire [2:0] req0,req1,req2;
wire [2:0] gnt0,gnt1,gnt2;
prienc #(.N(3)) pr0 (en0,req0,gnt0);
prienc #(.N(3)) pr1 (en1,req1,gnt1);
prienc #(.N(3)) pr2 (en2,req2,gnt2);
reg [7:0] srv_cnt0_d,srv_cnt1_d,srv_cnt2_d;
reg [7:0] srv_cnt0_q,srv_cnt1_q,srv_cnt2_q;
reg [2:0] queue_gnt_d,queue_gnt_q;
wire [7:0] add_cnt;
wire q_ovr_all,q_ovr_0,q_ovr_1,q_ovr_2;
wire q_atv_0,q_atv_1,q_atv_2;
wire [2:0] cmp_val;
always @(posedge clks.clk or negedge clks.rst) begin
if(~clks.rst) begin
srv_cnt0_d <= #0 32'h0;
srv_cnt1_d <= #0 32'h0;
srv_cnt2_d <= #0 32'h0;
queue_gnt_d <= #0 3'b000;
en0_d <= #0 1'b0;
en1_d <= #0 1'b0;
en2_d <= #0 1'b0;
end else begin
srv_cnt0_d <= #1 q_ovr_all ? 32'h0 : srv_cnt0_q;
srv_cnt1_d <= #1 q_ovr_all ? 32'h0 : srv_cnt1_q;
srv_cnt2_d <= #1 q_ovr_all ? 32'h0 : srv_cnt2_q;
queue_gnt_d <= #1 queue_gnt_q;
en0_d <= #1 en0;
en1_d <= #1 en1;
en2_d <= #1 en2;
end
end
assign add_cnt = {srv_cnt0_q + srv_cnt1_q + srv_cnt2_q};
assign q_ovr_all = (add_cnt == 7);
assign q_ovr_0 = (srv_cnt0_q == 4);
assign q_ovr_1 = (srv_cnt1_q == 2);
assign q_ovr_2 = (srv_cnt2_q == 1);
assign q_atv_0 = (srv_cnt0_d < 4)? 1'b1 : 1'b0;
assign q_atv_1 = (srv_cnt1_d < 2)? 1'b1 : 1'b0;
assign q_atv_2 = (srv_cnt2_d < 1)? 1'b1 : 1'b0;
assign cmp_val = {q_atv_2,q_atv_1,q_atv_0};
assign req0 = {req[0],req[1],req[2]};
assign req1 = {req[1],req[2],req[0]};
assign req2 = {req[2],req[1],req[0]};
always @(*) begin
en0 = 1'b1;
en1 = 1'b1;
en2 = 1'b1;
queue_gnt_q = queue_gnt_d;
if(arb_nxt) begin
case(1)
cmp_val[0]: begin
queue_gnt_q = {gnt0[0],gnt0[1],gnt0[2]};
end
cmp_val[1]: begin
queue_gnt_q = {gnt1[1],gnt1[2],gnt1[0]};
end
cmp_val[2]: begin
queue_gnt_q = {gnt2[2],gnt2[0],gnt2[1]};
end
endcase
end
srv_cnt0_q = queue_gnt_q[0] & arb_nxt ? (srv_cnt0_d+1):srv_cnt0_d;
srv_cnt1_q = queue_gnt_q[1] & arb_nxt ? (srv_cnt1_d+1):srv_cnt1_d;
srv_cnt2_q = queue_gnt_q[2] & arb_nxt ? (srv_cnt2_d+1):srv_cnt2_d;
end
assign gnt = queue_gnt_d;
endmodule | module QOS_arb(
AXI_clks.to_rtl clks,
input [2:0] req,
input arb_nxt,
output [2:0] gnt
); |
reg en0,en1,en2;
reg en0_d,en1_d,en2_d;
wire [2:0] req0,req1,req2;
wire [2:0] gnt0,gnt1,gnt2;
prienc #(.N(3)) pr0 (en0,req0,gnt0);
prienc #(.N(3)) pr1 (en1,req1,gnt1);
prienc #(.N(3)) pr2 (en2,req2,gnt2);
reg [7:0] srv_cnt0_d,srv_cnt1_d,srv_cnt2_d;
reg [7:0] srv_cnt0_q,srv_cnt1_q,srv_cnt2_q;
reg [2:0] queue_gnt_d,queue_gnt_q;
wire [7:0] add_cnt;
wire q_ovr_all,q_ovr_0,q_ovr_1,q_ovr_2;
wire q_atv_0,q_atv_1,q_atv_2;
wire [2:0] cmp_val;
always @(posedge clks.clk or negedge clks.rst) begin
if(~clks.rst) begin
srv_cnt0_d <= #0 32'h0;
srv_cnt1_d <= #0 32'h0;
srv_cnt2_d <= #0 32'h0;
queue_gnt_d <= #0 3'b000;
en0_d <= #0 1'b0;
en1_d <= #0 1'b0;
en2_d <= #0 1'b0;
end else begin
srv_cnt0_d <= #1 q_ovr_all ? 32'h0 : srv_cnt0_q;
srv_cnt1_d <= #1 q_ovr_all ? 32'h0 : srv_cnt1_q;
srv_cnt2_d <= #1 q_ovr_all ? 32'h0 : srv_cnt2_q;
queue_gnt_d <= #1 queue_gnt_q;
en0_d <= #1 en0;
en1_d <= #1 en1;
en2_d <= #1 en2;
end
end
assign add_cnt = {srv_cnt0_q + srv_cnt1_q + srv_cnt2_q};
assign q_ovr_all = (add_cnt == 7);
assign q_ovr_0 = (srv_cnt0_q == 4);
assign q_ovr_1 = (srv_cnt1_q == 2);
assign q_ovr_2 = (srv_cnt2_q == 1);
assign q_atv_0 = (srv_cnt0_d < 4)? 1'b1 : 1'b0;
assign q_atv_1 = (srv_cnt1_d < 2)? 1'b1 : 1'b0;
assign q_atv_2 = (srv_cnt2_d < 1)? 1'b1 : 1'b0;
assign cmp_val = {q_atv_2,q_atv_1,q_atv_0};
assign req0 = {req[0],req[1],req[2]};
assign req1 = {req[1],req[2],req[0]};
assign req2 = {req[2],req[1],req[0]};
always @(*) begin
en0 = 1'b1;
en1 = 1'b1;
en2 = 1'b1;
queue_gnt_q = queue_gnt_d;
if(arb_nxt) begin
case(1)
cmp_val[0]: begin
queue_gnt_q = {gnt0[0],gnt0[1],gnt0[2]};
end
cmp_val[1]: begin
queue_gnt_q = {gnt1[1],gnt1[2],gnt1[0]};
end
cmp_val[2]: begin
queue_gnt_q = {gnt2[2],gnt2[0],gnt2[1]};
end
endcase
end
srv_cnt0_q = queue_gnt_q[0] & arb_nxt ? (srv_cnt0_d+1):srv_cnt0_d;
srv_cnt1_q = queue_gnt_q[1] & arb_nxt ? (srv_cnt1_d+1):srv_cnt1_d;
srv_cnt2_q = queue_gnt_q[2] & arb_nxt ? (srv_cnt2_d+1):srv_cnt2_d;
end
assign gnt = queue_gnt_d;
endmodule | 1 |
137,540 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/sram_mem.sv | 79,197,809 | sram_mem.sv | sv | 26 | 65 | [] | [] | [] | [(5, 24)] | null | data/verilator_xmls/2b010d60-3dcf-4c74-ad05-6e5c6d62c163.xml | null | 299,796 | module | module sram_mem(
input [63:0] data_in,
input clk,
input write,
input read,
input [31:0] wr_addr,
input [31:0] rd_addr,
output[63:0] data_out);
reg [63:0] mem [0:2047];
assign data_out = read ? mem[rd_addr] : 64'h0000_0000_0000_0000;
always @(posedge clk) begin
if(write) begin
mem[wr_addr] <= #1 data_in;
end
end
endmodule | module sram_mem(
input [63:0] data_in,
input clk,
input write,
input read,
input [31:0] wr_addr,
input [31:0] rd_addr,
output[63:0] data_out); |
reg [63:0] mem [0:2047];
assign data_out = read ? mem[rd_addr] : 64'h0000_0000_0000_0000;
always @(posedge clk) begin
if(write) begin
mem[wr_addr] <= #1 data_in;
end
end
endmodule | 1 |
137,544 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v | 79,197,809 | queue_selection.v | v | 1,079 | 80 | [] | [] | [] | [(8, 1077)] | null | null | 1: b"%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:108: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/queue_gnt_d_reg[2] ( .D(\\qos/queue_gnt_q [2]), .CLK(\\clks.clk ), \n ^~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc,data/full_repos/permissive/79197809/DFFSR\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc,data/full_repos/permissive/79197809/DFFSR.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc,data/full_repos/permissive/79197809/DFFSR.sv\n DFFSR\n DFFSR.v\n DFFSR.sv\n obj_dir/DFFSR\n obj_dir/DFFSR.v\n obj_dir/DFFSR.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:110: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[0] ( .D(\\qos/N26 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:112: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[1] ( .D(\\qos/N27 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:114: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[2] ( .D(\\qos/N28 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:116: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[3] ( .D(\\qos/N29 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:118: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[4] ( .D(\\qos/N30 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:120: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[5] ( .D(\\qos/N31 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:122: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[6] ( .D(\\qos/N32 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:124: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt2_d_reg[7] ( .D(\\qos/N33 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:126: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/queue_gnt_d_reg[1] ( .D(\\qos/queue_gnt_q [1]), .CLK(\\clks.clk ), \n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:128: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[0] ( .D(\\qos/N18 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:130: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[1] ( .D(\\qos/N19 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:132: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[2] ( .D(\\qos/N20 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:134: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[3] ( .D(\\qos/N21 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:136: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[4] ( .D(\\qos/N22 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:138: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[5] ( .D(\\qos/N23 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:140: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[6] ( .D(\\qos/N24 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:142: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt1_d_reg[7] ( .D(\\qos/N25 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:144: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/queue_gnt_d_reg[0] ( .D(\\qos/queue_gnt_q [0]), .CLK(\\clks.clk ), \n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:146: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[0] ( .D(\\qos/N10 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:148: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[1] ( .D(\\qos/N11 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:150: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[2] ( .D(\\qos/N12 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:152: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[3] ( .D(\\qos/N13 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:154: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[4] ( .D(\\qos/N14 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:156: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[5] ( .D(\\qos/N15 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:158: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[6] ( .D(\\qos/N16 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:160: Cannot find file containing module: 'DFFSR'\n DFFSR \\qos/srv_cnt0_d_reg[7] ( .D(\\qos/N17 ), .CLK(\\clks.clk ), .R(\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:162: Cannot find file containing module: 'OR2X1'\n OR2X1 U469 ( .A(n788), .B(n566), .Y(n786) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:163: Cannot find file containing module: 'OR2X1'\n OR2X1 U470 ( .A(n586), .B(n745), .Y(n756) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:164: Cannot find file containing module: 'AND2X1'\n AND2X1 U471 ( .A(n590), .B(n410), .Y(n790) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:165: Cannot find file containing module: 'INVX2'\n INVX2 U472 ( .A(n432), .Y(n1074) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:166: Cannot find file containing module: 'BUFX2'\n BUFX2 U473 ( .A(n1075), .Y(n728) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:167: Cannot find file containing module: 'INVX4'\n INVX4 U474 ( .A(n411), .Y(n822) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:168: Cannot find file containing module: 'AND2X2'\n AND2X2 U475 ( .A(arb_nxt), .B(\\qos/queue_gnt_q [0]), .Y(n565) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:169: Cannot find file containing module: 'AND2X2'\n AND2X2 U476 ( .A(n589), .B(n415), .Y(n779) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:170: Cannot find file containing module: 'INVX2'\n INVX2 U477 ( .A(n782), .Y(n843) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:171: Cannot find file containing module: 'OR2X1'\n OR2X1 U478 ( .A(n423), .B(n766), .Y(n765) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:172: Cannot find file containing module: 'OR2X1'\n OR2X1 U479 ( .A(n559), .B(n578), .Y(n797) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:173: Cannot find file containing module: 'AND2X1'\n AND2X1 U480 ( .A(n710), .B(crcfifo1_empty), .Y(n738) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:174: Cannot find file containing module: 'INVX1'\n INVX1 U481 ( .A(n778), .Y(n835) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:175: Cannot find file containing module: 'INVX1'\n INVX1 U482 ( .A(n780), .Y(n827) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:176: Cannot find file containing module: 'INVX1'\n INVX1 U483 ( .A(n820), .Y(n413) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:177: Cannot find file containing module: 'INVX1'\n INVX1 U484 ( .A(n821), .Y(n412) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:178: Cannot find file containing module: 'AND2X1'\n AND2X1 U485 ( .A(n846), .B(n822), .Y(\\qos/N17 ) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:179: Cannot find file containing module: 'AND2X1'\n AND2X1 U486 ( .A(n845), .B(n822), .Y(\\qos/N16 ) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:180: Cannot find file containing module: 'AND2X1'\n AND2X1 U487 ( .A(n419), .B(n822), .Y(\\qos/N15 ) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:181: Cannot find file containing module: 'AND2X1'\n AND2X1 U488 ( .A(n843), .B(n822), .Y(\\qos/N14 ) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:182: Cannot find file containing module: 'AND2X1'\n AND2X1 U489 ( .A(n575), .B(n822), .Y(\\qos/N13 ) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:183: Cannot find file containing module: 'AND2X1'\n AND2X1 U490 ( .A(n841), .B(n822), .Y(\\qos/N12 ) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_ibloc/queue_selection.v:184: Cannot find file containing module: 'AND2X1'\n AND2X1 U491 ( .A(n568), .B(n822), .Y(\\qos/N11 ) );\n ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 299,824 | module | module queue_selection ( \clks.clk , \clks.rst , arb_nxt, pfifo_datain0,
pfifo_datain1, pfifo_datain2, crcfifo0_dataout, crcfifo1_dataout,
crcfifo2_dataout, pfifo_datain_ctrl_0, pfifo_datain_ctrl_1,
pfifo_datain_ctrl_2, crcfifo0_empty, crcfifo1_empty, crcfifo2_empty,
pfifo_pop, crcfifo_pop, crcfifo0_pull, crcfifo1_pull, crcfifo2_pull,
pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1,
pcfifo_pop_2, pfifo_datain, pfifo_datain_ctrl, crcfifo_dataout,
start_transmit );
input [63:0] pfifo_datain0;
input [63:0] pfifo_datain1;
input [63:0] pfifo_datain2;
input [31:0] crcfifo0_dataout;
input [31:0] crcfifo1_dataout;
input [31:0] crcfifo2_dataout;
input [15:0] pfifo_datain_ctrl_0;
input [15:0] pfifo_datain_ctrl_1;
input [15:0] pfifo_datain_ctrl_2;
output [63:0] pfifo_datain;
output [15:0] pfifo_datain_ctrl;
output [31:0] crcfifo_dataout;
input \clks.clk , \clks.rst , arb_nxt, crcfifo0_empty, crcfifo1_empty,
crcfifo2_empty, pfifo_pop, crcfifo_pop;
output crcfifo0_pull, crcfifo1_pull, crcfifo2_pull, pfifo_pop_0, pfifo_pop_1,
pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1, pcfifo_pop_2, start_transmit;
wire pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, \qos/N33 , \qos/N32 ,
\qos/N31 , \qos/N30 , \qos/N29 , \qos/N28 , \qos/N27 , \qos/N26 ,
\qos/N25 , \qos/N24 , \qos/N23 , \qos/N22 , \qos/N21 , \qos/N20 ,
\qos/N19 , \qos/N18 , \qos/N17 , \qos/N16 , \qos/N15 , \qos/N14 ,
\qos/N13 , \qos/N12 , \qos/N11 , \qos/N10 , n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,
n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534,
n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622,
n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633,
n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644,
n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666,
n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688,
n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077;
wire [2:0] buffer_sel;
wire [2:0] \qos/queue_gnt_q ;
wire [7:0] \qos/srv_cnt2_d ;
wire [7:0] \qos/srv_cnt1_d ;
wire [7:0] \qos/srv_cnt0_d ;
assign pcfifo_pop_0 = pfifo_pop_0;
assign pcfifo_pop_1 = pfifo_pop_1;
assign pcfifo_pop_2 = pfifo_pop_2;
DFFSR \qos/queue_gnt_d_reg[2] ( .D(\qos/queue_gnt_q [2]), .CLK(\clks.clk ),
.R(\clks.rst ), .S(1'b1), .Q(buffer_sel[2]) );
DFFSR \qos/srv_cnt2_d_reg[0] ( .D(\qos/N26 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [0]) );
DFFSR \qos/srv_cnt2_d_reg[1] ( .D(\qos/N27 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [1]) );
DFFSR \qos/srv_cnt2_d_reg[2] ( .D(\qos/N28 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [2]) );
DFFSR \qos/srv_cnt2_d_reg[3] ( .D(\qos/N29 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [3]) );
DFFSR \qos/srv_cnt2_d_reg[4] ( .D(\qos/N30 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [4]) );
DFFSR \qos/srv_cnt2_d_reg[5] ( .D(\qos/N31 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [5]) );
DFFSR \qos/srv_cnt2_d_reg[6] ( .D(\qos/N32 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [6]) );
DFFSR \qos/srv_cnt2_d_reg[7] ( .D(\qos/N33 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [7]) );
DFFSR \qos/queue_gnt_d_reg[1] ( .D(\qos/queue_gnt_q [1]), .CLK(\clks.clk ),
.R(\clks.rst ), .S(1'b1), .Q(buffer_sel[1]) );
DFFSR \qos/srv_cnt1_d_reg[0] ( .D(\qos/N18 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [0]) );
DFFSR \qos/srv_cnt1_d_reg[1] ( .D(\qos/N19 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [1]) );
DFFSR \qos/srv_cnt1_d_reg[2] ( .D(\qos/N20 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [2]) );
DFFSR \qos/srv_cnt1_d_reg[3] ( .D(\qos/N21 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [3]) );
DFFSR \qos/srv_cnt1_d_reg[4] ( .D(\qos/N22 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [4]) );
DFFSR \qos/srv_cnt1_d_reg[5] ( .D(\qos/N23 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [5]) );
DFFSR \qos/srv_cnt1_d_reg[6] ( .D(\qos/N24 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [6]) );
DFFSR \qos/srv_cnt1_d_reg[7] ( .D(\qos/N25 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [7]) );
DFFSR \qos/queue_gnt_d_reg[0] ( .D(\qos/queue_gnt_q [0]), .CLK(\clks.clk ),
.R(\clks.rst ), .S(1'b1), .Q(buffer_sel[0]) );
DFFSR \qos/srv_cnt0_d_reg[0] ( .D(\qos/N10 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [0]) );
DFFSR \qos/srv_cnt0_d_reg[1] ( .D(\qos/N11 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [1]) );
DFFSR \qos/srv_cnt0_d_reg[2] ( .D(\qos/N12 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [2]) );
DFFSR \qos/srv_cnt0_d_reg[3] ( .D(\qos/N13 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [3]) );
DFFSR \qos/srv_cnt0_d_reg[4] ( .D(\qos/N14 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [4]) );
DFFSR \qos/srv_cnt0_d_reg[5] ( .D(\qos/N15 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [5]) );
DFFSR \qos/srv_cnt0_d_reg[6] ( .D(\qos/N16 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [6]) );
DFFSR \qos/srv_cnt0_d_reg[7] ( .D(\qos/N17 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [7]) );
OR2X1 U469 ( .A(n788), .B(n566), .Y(n786) );
OR2X1 U470 ( .A(n586), .B(n745), .Y(n756) );
AND2X1 U471 ( .A(n590), .B(n410), .Y(n790) );
INVX2 U472 ( .A(n432), .Y(n1074) );
BUFX2 U473 ( .A(n1075), .Y(n728) );
INVX4 U474 ( .A(n411), .Y(n822) );
AND2X2 U475 ( .A(arb_nxt), .B(\qos/queue_gnt_q [0]), .Y(n565) );
AND2X2 U476 ( .A(n589), .B(n415), .Y(n779) );
INVX2 U477 ( .A(n782), .Y(n843) );
OR2X1 U478 ( .A(n423), .B(n766), .Y(n765) );
OR2X1 U479 ( .A(n559), .B(n578), .Y(n797) );
AND2X1 U480 ( .A(n710), .B(crcfifo1_empty), .Y(n738) );
INVX1 U481 ( .A(n778), .Y(n835) );
INVX1 U482 ( .A(n780), .Y(n827) );
INVX1 U483 ( .A(n820), .Y(n413) );
INVX1 U484 ( .A(n821), .Y(n412) );
AND2X1 U485 ( .A(n846), .B(n822), .Y(\qos/N17 ) );
AND2X1 U486 ( .A(n845), .B(n822), .Y(\qos/N16 ) );
AND2X1 U487 ( .A(n419), .B(n822), .Y(\qos/N15 ) );
AND2X1 U488 ( .A(n843), .B(n822), .Y(\qos/N14 ) );
AND2X1 U489 ( .A(n575), .B(n822), .Y(\qos/N13 ) );
AND2X1 U490 ( .A(n841), .B(n822), .Y(\qos/N12 ) );
AND2X1 U491 ( .A(n568), .B(n822), .Y(\qos/N11 ) );
AND2X1 U492 ( .A(n717), .B(n822), .Y(\qos/N10 ) );
AND2X1 U493 ( .A(n573), .B(n757), .Y(n747) );
AND2X1 U494 ( .A(n838), .B(n822), .Y(\qos/N25 ) );
AND2X1 U495 ( .A(n837), .B(n822), .Y(\qos/N24 ) );
AND2X1 U496 ( .A(n716), .B(n822), .Y(\qos/N23 ) );
AND2X1 U497 ( .A(n835), .B(n822), .Y(\qos/N22 ) );
AND2X1 U498 ( .A(n715), .B(n822), .Y(\qos/N21 ) );
AND2X1 U499 ( .A(n596), .B(n822), .Y(\qos/N20 ) );
AND2X1 U500 ( .A(n832), .B(n822), .Y(\qos/N19 ) );
AND2X1 U501 ( .A(n831), .B(n822), .Y(\qos/N18 ) );
AND2X1 U502 ( .A(n830), .B(n822), .Y(\qos/N33 ) );
AND2X1 U503 ( .A(n829), .B(n822), .Y(\qos/N32 ) );
AND2X1 U504 ( .A(n592), .B(n822), .Y(\qos/N31 ) );
AND2X1 U505 ( .A(n827), .B(n822), .Y(\qos/N30 ) );
AND2X1 U506 ( .A(n593), .B(n822), .Y(\qos/N29 ) );
AND2X1 U507 ( .A(n825), .B(n822), .Y(\qos/N28 ) );
AND2X1 U508 ( .A(n824), .B(n822), .Y(\qos/N27 ) );
AND2X1 U509 ( .A(n574), .B(n822), .Y(\qos/N26 ) );
OR2X1 U510 ( .A(n556), .B(n579), .Y(n799) );
OR2X1 U511 ( .A(n554), .B(n577), .Y(n792) );
AND2X1 U512 ( .A(n712), .B(n581), .Y(n781) );
AND2X1 U513 ( .A(n553), .B(n760), .Y(n784) );
AND2X1 U514 ( .A(n721), .B(n767), .Y(n760) );
OR2X1 U515 ( .A(n785), .B(n572), .Y(n783) );
OR2X1 U516 ( .A(n791), .B(n576), .Y(n789) );
AND2X1 U517 ( .A(n711), .B(n416), .Y(n767) );
AND2X1 U518 ( .A(n714), .B(n774), .Y(n787) );
AND2X1 U519 ( .A(n718), .B(n763), .Y(n774) );
INVX1 U520 ( .A(n739), .Y(n586) );
INVX1 U521 ( .A(arb_nxt), .Y(n848) );
INVX1 U522 ( .A(n797), .Y(n713) );
INVX1 U523 ( .A(n799), .Y(n595) );
INVX1 U524 ( .A(n789), .Y(n581) );
AND2X1 U525 ( .A(n428), .B(n420), .Y(n410) );
INVX1 U526 ( .A(n819), .Y(n414) );
NOR3X1 U527 ( .A(n412), .B(n413), .C(n414), .Y(n411) );
INVX1 U528 ( .A(n786), .Y(n415) );
BUFX2 U529 ( .A(n564), .Y(n416) );
BUFX2 U530 ( .A(n740), .Y(n417) );
BUFX2 U531 ( .A(n849), .Y(n418) );
BUFX2 U532 ( .A(n844), .Y(n419) );
INVX1 U533 ( .A(n765), .Y(n420) );
BUFX2 U534 ( .A(n744), .Y(n421) );
INVX1 U535 ( .A(n747), .Y(n422) );
INVX1 U536 ( .A(n565), .Y(n423) );
INVX1 U537 ( .A(n738), .Y(n424) );
BUFX2 U538 ( .A(n748), .Y(n425) );
BUFX2 U539 ( .A(n741), .Y(n426) );
BUFX2 U540 ( .A(n749), .Y(n427) );
AND2X1 U541 ( .A(n569), .B(n757), .Y(n847) );
BUFX2 U542 ( .A(\qos/srv_cnt0_d [1]), .Y(n428) );
BUFX2 U543 ( .A(\qos/srv_cnt0_d [0]), .Y(n429) );
BUFX2 U544 ( .A(\qos/srv_cnt1_d [3]), .Y(n430) );
BUFX2 U545 ( .A(\qos/srv_cnt2_d [3]), .Y(n431) );
BUFX2 U546 ( .A(n726), .Y(n432) );
AND2X1 U547 ( .A(n807), .B(n808), .Y(n724) );
INVX1 U548 ( .A(n850), .Y(n433) );
AND2X1 U549 ( .A(n728), .B(pfifo_datain_ctrl_0[0]), .Y(n850) );
INVX1 U550 ( .A(n852), .Y(n434) );
AND2X1 U551 ( .A(n728), .B(pfifo_datain_ctrl_0[1]), .Y(n852) );
INVX1 U552 ( .A(n854), .Y(n435) );
AND2X1 U553 ( .A(n728), .B(pfifo_datain_ctrl_0[2]), .Y(n854) );
INVX1 U554 ( .A(n856), .Y(n436) );
AND2X1 U555 ( .A(n728), .B(pfifo_datain_ctrl_0[3]), .Y(n856) );
INVX1 U556 ( .A(n858), .Y(n437) );
AND2X1 U557 ( .A(n728), .B(pfifo_datain_ctrl_0[4]), .Y(n858) );
INVX1 U558 ( .A(n860), .Y(n438) );
AND2X1 U559 ( .A(n728), .B(pfifo_datain_ctrl_0[5]), .Y(n860) );
INVX1 U560 ( .A(n862), .Y(n439) );
AND2X1 U561 ( .A(n728), .B(pfifo_datain_ctrl_0[6]), .Y(n862) );
INVX1 U562 ( .A(n864), .Y(n440) );
AND2X1 U563 ( .A(n728), .B(pfifo_datain_ctrl_0[7]), .Y(n864) );
INVX1 U564 ( .A(n866), .Y(n441) );
AND2X1 U565 ( .A(n728), .B(pfifo_datain_ctrl_0[8]), .Y(n866) );
INVX1 U566 ( .A(n868), .Y(n442) );
AND2X1 U567 ( .A(n728), .B(pfifo_datain_ctrl_0[9]), .Y(n868) );
INVX1 U568 ( .A(n870), .Y(n443) );
AND2X1 U569 ( .A(n728), .B(pfifo_datain_ctrl_0[10]), .Y(n870) );
INVX1 U570 ( .A(n872), .Y(n444) );
AND2X1 U571 ( .A(n728), .B(pfifo_datain_ctrl_0[11]), .Y(n872) );
INVX1 U572 ( .A(n874), .Y(n445) );
AND2X1 U573 ( .A(n728), .B(pfifo_datain_ctrl_0[12]), .Y(n874) );
INVX1 U574 ( .A(n876), .Y(n446) );
AND2X1 U575 ( .A(n728), .B(pfifo_datain_ctrl_0[13]), .Y(n876) );
INVX1 U576 ( .A(n878), .Y(n447) );
AND2X1 U577 ( .A(n728), .B(pfifo_datain_ctrl_0[14]), .Y(n878) );
INVX1 U578 ( .A(n880), .Y(n448) );
AND2X1 U579 ( .A(n728), .B(pfifo_datain_ctrl_0[15]), .Y(n880) );
INVX1 U580 ( .A(n882), .Y(n449) );
AND2X1 U581 ( .A(n728), .B(crcfifo0_dataout[0]), .Y(n882) );
INVX1 U582 ( .A(n884), .Y(n450) );
AND2X1 U583 ( .A(n728), .B(crcfifo0_dataout[1]), .Y(n884) );
INVX1 U584 ( .A(n886), .Y(n451) );
AND2X1 U585 ( .A(n728), .B(crcfifo0_dataout[2]), .Y(n886) );
INVX1 U586 ( .A(n888), .Y(n452) );
AND2X1 U587 ( .A(n728), .B(crcfifo0_dataout[3]), .Y(n888) );
INVX1 U588 ( .A(n890), .Y(n453) );
AND2X1 U589 ( .A(n728), .B(crcfifo0_dataout[4]), .Y(n890) );
INVX1 U590 ( .A(n892), .Y(n454) );
AND2X1 U591 ( .A(n728), .B(crcfifo0_dataout[5]), .Y(n892) );
INVX1 U592 ( .A(n894), .Y(n455) );
AND2X1 U593 ( .A(n728), .B(crcfifo0_dataout[6]), .Y(n894) );
INVX1 U594 ( .A(n896), .Y(n456) );
AND2X1 U595 ( .A(n728), .B(crcfifo0_dataout[7]), .Y(n896) );
INVX1 U596 ( .A(n898), .Y(n457) );
AND2X1 U597 ( .A(n728), .B(crcfifo0_dataout[8]), .Y(n898) );
AND2X1 U598 ( .A(n1075), .B(crcfifo0_dataout[9]), .Y(n900) );
INVX1 U599 ( .A(n900), .Y(n458) );
AND2X1 U600 ( .A(n1075), .B(crcfifo0_dataout[10]), .Y(n902) );
INVX1 U601 ( .A(n902), .Y(n459) );
AND2X2 U602 ( .A(n1075), .B(crcfifo0_dataout[11]), .Y(n904) );
INVX1 U603 ( .A(n904), .Y(n460) );
AND2X1 U604 ( .A(n1075), .B(crcfifo0_dataout[12]), .Y(n906) );
INVX1 U605 ( .A(n906), .Y(n461) );
AND2X2 U606 ( .A(n1075), .B(crcfifo0_dataout[13]), .Y(n908) );
INVX1 U607 ( .A(n908), .Y(n462) );
AND2X1 U608 ( .A(n1075), .B(crcfifo0_dataout[14]), .Y(n910) );
INVX1 U609 ( .A(n910), .Y(n463) );
AND2X1 U610 ( .A(n1075), .B(crcfifo0_dataout[15]), .Y(n912) );
INVX1 U611 ( .A(n912), .Y(n464) );
AND2X2 U612 ( .A(n1075), .B(crcfifo0_dataout[16]), .Y(n914) );
INVX1 U613 ( .A(n914), .Y(n465) );
AND2X1 U614 ( .A(n1075), .B(crcfifo0_dataout[17]), .Y(n916) );
INVX1 U615 ( .A(n916), .Y(n466) );
AND2X1 U616 ( .A(n1075), .B(crcfifo0_dataout[18]), .Y(n918) );
INVX1 U617 ( .A(n918), .Y(n467) );
AND2X2 U618 ( .A(n1075), .B(crcfifo0_dataout[19]), .Y(n920) );
INVX1 U619 ( .A(n920), .Y(n468) );
INVX1 U620 ( .A(n922), .Y(n469) );
AND2X1 U621 ( .A(n728), .B(crcfifo0_dataout[20]), .Y(n922) );
INVX1 U622 ( .A(n924), .Y(n470) );
AND2X1 U623 ( .A(n728), .B(crcfifo0_dataout[21]), .Y(n924) );
INVX1 U624 ( .A(n926), .Y(n471) );
AND2X1 U625 ( .A(n728), .B(crcfifo0_dataout[22]), .Y(n926) );
AND2X1 U626 ( .A(n1075), .B(crcfifo0_dataout[23]), .Y(n928) );
INVX1 U627 ( .A(n928), .Y(n472) );
AND2X2 U628 ( .A(n1075), .B(crcfifo0_dataout[24]), .Y(n930) );
INVX1 U629 ( .A(n930), .Y(n473) );
AND2X1 U630 ( .A(n1075), .B(crcfifo0_dataout[25]), .Y(n932) );
INVX1 U631 ( .A(n932), .Y(n474) );
AND2X1 U632 ( .A(n1075), .B(crcfifo0_dataout[26]), .Y(n934) );
INVX1 U633 ( .A(n934), .Y(n475) );
AND2X2 U634 ( .A(n1075), .B(crcfifo0_dataout[27]), .Y(n936) );
INVX1 U635 ( .A(n936), .Y(n476) );
AND2X1 U636 ( .A(n1075), .B(crcfifo0_dataout[28]), .Y(n938) );
INVX1 U637 ( .A(n938), .Y(n477) );
AND2X1 U638 ( .A(n1075), .B(crcfifo0_dataout[29]), .Y(n940) );
INVX1 U639 ( .A(n940), .Y(n478) );
AND2X2 U640 ( .A(n1075), .B(crcfifo0_dataout[30]), .Y(n942) );
INVX1 U641 ( .A(n942), .Y(n479) );
AND2X1 U642 ( .A(n1075), .B(crcfifo0_dataout[31]), .Y(n944) );
INVX1 U643 ( .A(n944), .Y(n480) );
AND2X1 U644 ( .A(n1075), .B(pfifo_datain0[0]), .Y(n946) );
INVX1 U645 ( .A(n946), .Y(n481) );
AND2X2 U646 ( .A(n1075), .B(pfifo_datain0[1]), .Y(n948) );
INVX1 U647 ( .A(n948), .Y(n482) );
AND2X1 U648 ( .A(n1075), .B(pfifo_datain0[2]), .Y(n950) );
INVX1 U649 ( .A(n950), .Y(n483) );
AND2X2 U650 ( .A(n1075), .B(pfifo_datain0[3]), .Y(n952) );
INVX1 U651 ( .A(n952), .Y(n484) );
INVX1 U652 ( .A(n954), .Y(n485) );
AND2X1 U653 ( .A(n728), .B(pfifo_datain0[4]), .Y(n954) );
INVX1 U654 ( .A(n956), .Y(n486) );
AND2X1 U655 ( .A(n728), .B(pfifo_datain0[5]), .Y(n956) );
INVX1 U656 ( .A(n958), .Y(n487) );
AND2X1 U657 ( .A(n728), .B(pfifo_datain0[6]), .Y(n958) );
INVX1 U658 ( .A(n960), .Y(n488) );
AND2X1 U659 ( .A(n728), .B(pfifo_datain0[7]), .Y(n960) );
INVX1 U660 ( .A(n962), .Y(n489) );
AND2X1 U661 ( .A(n728), .B(pfifo_datain0[8]), .Y(n962) );
INVX1 U662 ( .A(n964), .Y(n490) );
AND2X1 U663 ( .A(n728), .B(pfifo_datain0[9]), .Y(n964) );
INVX1 U664 ( .A(n966), .Y(n491) );
AND2X1 U665 ( .A(n728), .B(pfifo_datain0[10]), .Y(n966) );
INVX1 U666 ( .A(n968), .Y(n492) );
AND2X1 U667 ( .A(n728), .B(pfifo_datain0[11]), .Y(n968) );
INVX1 U668 ( .A(n970), .Y(n493) );
AND2X1 U669 ( .A(n728), .B(pfifo_datain0[12]), .Y(n970) );
INVX1 U670 ( .A(n972), .Y(n494) );
AND2X1 U671 ( .A(n728), .B(pfifo_datain0[13]), .Y(n972) );
INVX1 U672 ( .A(n974), .Y(n495) );
AND2X1 U673 ( .A(n728), .B(pfifo_datain0[14]), .Y(n974) );
INVX1 U674 ( .A(n976), .Y(n496) );
AND2X1 U675 ( .A(n728), .B(pfifo_datain0[15]), .Y(n976) );
INVX1 U676 ( .A(n978), .Y(n497) );
AND2X1 U677 ( .A(n728), .B(pfifo_datain0[16]), .Y(n978) );
INVX1 U678 ( .A(n980), .Y(n498) );
AND2X1 U679 ( .A(n728), .B(pfifo_datain0[17]), .Y(n980) );
INVX1 U680 ( .A(n982), .Y(n499) );
AND2X1 U681 ( .A(n728), .B(pfifo_datain0[18]), .Y(n982) );
AND2X1 U682 ( .A(n1075), .B(pfifo_datain0[19]), .Y(n984) );
INVX1 U683 ( .A(n984), .Y(n500) );
AND2X1 U684 ( .A(n1075), .B(pfifo_datain0[20]), .Y(n986) );
INVX1 U685 ( .A(n986), .Y(n501) );
AND2X2 U686 ( .A(n1075), .B(pfifo_datain0[21]), .Y(n988) );
INVX1 U687 ( .A(n988), .Y(n502) );
AND2X1 U688 ( .A(n1075), .B(pfifo_datain0[22]), .Y(n990) );
INVX1 U689 ( .A(n990), .Y(n503) );
AND2X1 U690 ( .A(n1075), .B(pfifo_datain0[23]), .Y(n992) );
INVX1 U691 ( .A(n992), .Y(n504) );
AND2X2 U692 ( .A(n1075), .B(pfifo_datain0[24]), .Y(n994) );
INVX1 U693 ( .A(n994), .Y(n505) );
AND2X1 U694 ( .A(n1075), .B(pfifo_datain0[25]), .Y(n996) );
INVX1 U695 ( .A(n996), .Y(n506) );
AND2X1 U696 ( .A(n1075), .B(pfifo_datain0[26]), .Y(n998) );
INVX1 U697 ( .A(n998), .Y(n507) );
AND2X2 U698 ( .A(n1075), .B(pfifo_datain0[27]), .Y(n1000) );
INVX1 U699 ( .A(n1000), .Y(n508) );
AND2X1 U700 ( .A(n1075), .B(pfifo_datain0[28]), .Y(n1002) );
INVX1 U701 ( .A(n1002), .Y(n509) );
AND2X2 U702 ( .A(n1075), .B(pfifo_datain0[29]), .Y(n1004) );
INVX1 U703 ( .A(n1004), .Y(n510) );
AND2X1 U704 ( .A(n1075), .B(pfifo_datain0[30]), .Y(n1006) );
INVX1 U705 ( .A(n1006), .Y(n511) );
AND2X1 U706 ( .A(n1075), .B(pfifo_datain0[31]), .Y(n1008) );
INVX1 U707 ( .A(n1008), .Y(n512) );
AND2X2 U708 ( .A(n1075), .B(pfifo_datain0[32]), .Y(n1010) );
INVX1 U709 ( .A(n1010), .Y(n513) );
AND2X1 U710 ( .A(n1075), .B(pfifo_datain0[33]), .Y(n1012) );
INVX1 U711 ( .A(n1012), .Y(n514) );
AND2X1 U712 ( .A(n1075), .B(pfifo_datain0[34]), .Y(n1014) );
INVX1 U713 ( .A(n1014), .Y(n515) );
AND2X2 U714 ( .A(n1075), .B(pfifo_datain0[35]), .Y(n1016) );
INVX1 U715 ( .A(n1016), .Y(n516) );
AND2X1 U716 ( .A(n1075), .B(pfifo_datain0[36]), .Y(n1018) );
INVX1 U717 ( .A(n1018), .Y(n517) );
INVX1 U718 ( .A(n1020), .Y(n518) );
AND2X1 U719 ( .A(n728), .B(pfifo_datain0[37]), .Y(n1020) );
INVX1 U720 ( .A(n1022), .Y(n519) );
AND2X1 U721 ( .A(n728), .B(pfifo_datain0[38]), .Y(n1022) );
INVX1 U722 ( .A(n1024), .Y(n520) );
AND2X1 U723 ( .A(n728), .B(pfifo_datain0[39]), .Y(n1024) );
INVX1 U724 ( .A(n1026), .Y(n521) );
AND2X1 U725 ( .A(n728), .B(pfifo_datain0[40]), .Y(n1026) );
INVX1 U726 ( .A(n1028), .Y(n522) );
AND2X1 U727 ( .A(n728), .B(pfifo_datain0[41]), .Y(n1028) );
INVX1 U728 ( .A(n1030), .Y(n523) );
AND2X1 U729 ( .A(n728), .B(pfifo_datain0[42]), .Y(n1030) );
INVX1 U730 ( .A(n1032), .Y(n524) );
AND2X1 U731 ( .A(n728), .B(pfifo_datain0[43]), .Y(n1032) );
INVX1 U732 ( .A(n1034), .Y(n525) );
AND2X1 U733 ( .A(n728), .B(pfifo_datain0[44]), .Y(n1034) );
INVX1 U734 ( .A(n1036), .Y(n526) );
AND2X1 U735 ( .A(n728), .B(pfifo_datain0[45]), .Y(n1036) );
INVX1 U736 ( .A(n1038), .Y(n527) );
AND2X1 U737 ( .A(n728), .B(pfifo_datain0[46]), .Y(n1038) );
INVX1 U738 ( .A(n1040), .Y(n528) );
AND2X1 U739 ( .A(n728), .B(pfifo_datain0[47]), .Y(n1040) );
INVX1 U740 ( .A(n1042), .Y(n529) );
AND2X1 U741 ( .A(n728), .B(pfifo_datain0[48]), .Y(n1042) );
INVX1 U742 ( .A(n1044), .Y(n530) );
AND2X1 U743 ( .A(n728), .B(pfifo_datain0[49]), .Y(n1044) );
INVX1 U744 ( .A(n1046), .Y(n531) );
AND2X1 U745 ( .A(n728), .B(pfifo_datain0[50]), .Y(n1046) );
INVX1 U746 ( .A(n1049), .Y(n532) );
AND2X1 U747 ( .A(n728), .B(pfifo_datain0[51]), .Y(n1049) );
INVX1 U748 ( .A(n1051), .Y(n533) );
AND2X1 U749 ( .A(n728), .B(pfifo_datain0[52]), .Y(n1051) );
INVX1 U750 ( .A(n1053), .Y(n534) );
AND2X1 U751 ( .A(n728), .B(pfifo_datain0[53]), .Y(n1053) );
INVX1 U752 ( .A(n1055), .Y(n535) );
AND2X1 U753 ( .A(n728), .B(pfifo_datain0[54]), .Y(n1055) );
INVX1 U754 ( .A(n1057), .Y(n536) );
AND2X1 U755 ( .A(n728), .B(pfifo_datain0[55]), .Y(n1057) );
INVX1 U756 ( .A(n1059), .Y(n537) );
AND2X1 U757 ( .A(n728), .B(pfifo_datain0[56]), .Y(n1059) );
INVX1 U758 ( .A(n1061), .Y(n538) );
AND2X1 U759 ( .A(n728), .B(pfifo_datain0[57]), .Y(n1061) );
INVX1 U760 ( .A(n1063), .Y(n539) );
AND2X1 U761 ( .A(n728), .B(pfifo_datain0[58]), .Y(n1063) );
INVX1 U762 ( .A(n1065), .Y(n540) );
AND2X1 U763 ( .A(n728), .B(pfifo_datain0[59]), .Y(n1065) );
INVX1 U764 ( .A(n1067), .Y(n541) );
AND2X1 U765 ( .A(n728), .B(pfifo_datain0[60]), .Y(n1067) );
AND2X2 U766 ( .A(n1075), .B(pfifo_datain0[61]), .Y(n1069) );
INVX1 U767 ( .A(n1069), .Y(n542) );
AND2X1 U768 ( .A(n1075), .B(pfifo_datain0[62]), .Y(n1071) );
INVX1 U769 ( .A(n1071), .Y(n543) );
AND2X1 U770 ( .A(n1075), .B(pfifo_datain0[63]), .Y(n1076) );
INVX1 U771 ( .A(n1076), .Y(n544) );
INVX1 U772 ( .A(n750), .Y(n545) );
AND2X1 U773 ( .A(arb_nxt), .B(\qos/queue_gnt_q [2]), .Y(n750) );
BUFX2 U774 ( .A(n730), .Y(n546) );
BUFX2 U775 ( .A(n735), .Y(n547) );
INVX1 U776 ( .A(n816), .Y(n548) );
AND2X1 U777 ( .A(n815), .B(n814), .Y(n816) );
INVX1 U778 ( .A(n793), .Y(n549) );
AND2X1 U779 ( .A(n720), .B(n594), .Y(n793) );
INVX1 U780 ( .A(n798), .Y(n550) );
AND2X1 U781 ( .A(n571), .B(n713), .Y(n798) );
INVX1 U782 ( .A(n800), .Y(n551) );
AND2X1 U783 ( .A(n719), .B(n595), .Y(n800) );
INVX1 U784 ( .A(n767), .Y(n552) );
BUFX2 U785 ( .A(\qos/srv_cnt1_d [2]), .Y(n553) );
INVX1 U786 ( .A(n555), .Y(n554) );
BUFX2 U787 ( .A(\qos/srv_cnt1_d [5]), .Y(n555) );
INVX1 U788 ( .A(n557), .Y(n556) );
BUFX2 U789 ( .A(\qos/srv_cnt0_d [5]), .Y(n557) );
BUFX2 U790 ( .A(\qos/srv_cnt0_d [3]), .Y(n558) );
INVX1 U791 ( .A(n560), .Y(n559) );
BUFX2 U792 ( .A(\qos/srv_cnt2_d [5]), .Y(n560) );
BUFX2 U793 ( .A(\qos/srv_cnt2_d [0]), .Y(n561) );
INVX1 U794 ( .A(n760), .Y(n562) );
INVX1 U795 ( .A(n774), .Y(n563) );
AOI21X1 U796 ( .A(n418), .B(n709), .C(n848), .Y(n564) );
INVX1 U797 ( .A(n787), .Y(n566) );
INVX1 U798 ( .A(n752), .Y(n567) );
AND2X1 U799 ( .A(crcfifo1_empty), .B(crcfifo2_empty), .Y(n752) );
BUFX2 U800 ( .A(n840), .Y(n568) );
BUFX2 U801 ( .A(buffer_sel[1]), .Y(n569) );
INVX1 U802 ( .A(n571), .Y(n570) );
BUFX2 U803 ( .A(\qos/srv_cnt2_d [6]), .Y(n571) );
INVX1 U804 ( .A(n784), .Y(n572) );
BUFX2 U805 ( .A(buffer_sel[0]), .Y(n573) );
BUFX2 U806 ( .A(n823), .Y(n574) );
BUFX2 U807 ( .A(n842), .Y(n575) );
INVX1 U808 ( .A(n790), .Y(n576) );
AND2X1 U809 ( .A(n591), .B(n580), .Y(n777) );
INVX1 U810 ( .A(n777), .Y(n577) );
INVX1 U811 ( .A(n779), .Y(n578) );
INVX1 U812 ( .A(n781), .Y(n579) );
INVX1 U813 ( .A(n783), .Y(n580) );
INVX1 U814 ( .A(n583), .Y(n582) );
BUFX2 U815 ( .A(\qos/srv_cnt1_d [7]), .Y(n583) );
INVX1 U816 ( .A(n585), .Y(n584) );
BUFX2 U817 ( .A(\qos/srv_cnt2_d [7]), .Y(n585) );
OR2X1 U818 ( .A(n743), .B(n737), .Y(n739) );
INVX1 U819 ( .A(n588), .Y(n587) );
BUFX2 U820 ( .A(\qos/srv_cnt0_d [7]), .Y(n588) );
BUFX2 U821 ( .A(\qos/srv_cnt2_d [4]), .Y(n589) );
BUFX2 U822 ( .A(\qos/srv_cnt0_d [2]), .Y(n590) );
BUFX2 U823 ( .A(\qos/srv_cnt1_d [4]), .Y(n591) );
BUFX2 U824 ( .A(n828), .Y(n592) );
BUFX2 U825 ( .A(n826), .Y(n593) );
INVX1 U826 ( .A(n792), .Y(n594) );
BUFX2 U827 ( .A(n833), .Y(n596) );
BUFX2 U828 ( .A(n1077), .Y(n597) );
BUFX2 U829 ( .A(n1072), .Y(n598) );
BUFX2 U830 ( .A(n1070), .Y(n599) );
BUFX2 U831 ( .A(n1068), .Y(n600) );
BUFX2 U832 ( .A(n1066), .Y(n601) );
BUFX2 U833 ( .A(n1064), .Y(n602) );
BUFX2 U834 ( .A(n1062), .Y(n603) );
BUFX2 U835 ( .A(n1060), .Y(n604) );
BUFX2 U836 ( .A(n1058), .Y(n605) );
BUFX2 U837 ( .A(n1056), .Y(n606) );
BUFX2 U838 ( .A(n1054), .Y(n607) );
BUFX2 U839 ( .A(n1052), .Y(n608) );
BUFX2 U840 ( .A(n1050), .Y(n609) );
BUFX2 U841 ( .A(n1047), .Y(n610) );
BUFX2 U842 ( .A(n1045), .Y(n611) );
BUFX2 U843 ( .A(n1043), .Y(n612) );
BUFX2 U844 ( .A(n1041), .Y(n613) );
BUFX2 U845 ( .A(n1039), .Y(n614) );
BUFX2 U846 ( .A(n1037), .Y(n615) );
BUFX2 U847 ( .A(n1035), .Y(n616) );
BUFX2 U848 ( .A(n1033), .Y(n617) );
BUFX2 U849 ( .A(n1031), .Y(n618) );
BUFX2 U850 ( .A(n1029), .Y(n619) );
BUFX2 U851 ( .A(n1027), .Y(n620) );
BUFX2 U852 ( .A(n1025), .Y(n621) );
BUFX2 U853 ( .A(n1023), .Y(n622) );
BUFX2 U854 ( .A(n1021), .Y(n623) );
BUFX2 U855 ( .A(n1019), .Y(n624) );
BUFX2 U856 ( .A(n1017), .Y(n625) );
BUFX2 U857 ( .A(n1015), .Y(n626) );
BUFX2 U858 ( .A(n1013), .Y(n627) );
BUFX2 U859 ( .A(n1011), .Y(n628) );
BUFX2 U860 ( .A(n1009), .Y(n629) );
BUFX2 U861 ( .A(n1007), .Y(n630) );
BUFX2 U862 ( .A(n1005), .Y(n631) );
BUFX2 U863 ( .A(n1003), .Y(n632) );
BUFX2 U864 ( .A(n1001), .Y(n633) );
BUFX2 U865 ( .A(n999), .Y(n634) );
BUFX2 U866 ( .A(n997), .Y(n635) );
BUFX2 U867 ( .A(n995), .Y(n636) );
BUFX2 U868 ( .A(n993), .Y(n637) );
BUFX2 U869 ( .A(n991), .Y(n638) );
BUFX2 U870 ( .A(n989), .Y(n639) );
BUFX2 U871 ( .A(n987), .Y(n640) );
BUFX2 U872 ( .A(n985), .Y(n641) );
BUFX2 U873 ( .A(n983), .Y(n642) );
BUFX2 U874 ( .A(n981), .Y(n643) );
BUFX2 U875 ( .A(n979), .Y(n644) );
BUFX2 U876 ( .A(n977), .Y(n645) );
BUFX2 U877 ( .A(n975), .Y(n646) );
BUFX2 U878 ( .A(n973), .Y(n647) );
BUFX2 U879 ( .A(n971), .Y(n648) );
BUFX2 U880 ( .A(n969), .Y(n649) );
BUFX2 U881 ( .A(n967), .Y(n650) );
BUFX2 U882 ( .A(n965), .Y(n651) );
BUFX2 U883 ( .A(n963), .Y(n652) );
BUFX2 U884 ( .A(n961), .Y(n653) );
BUFX2 U885 ( .A(n959), .Y(n654) );
BUFX2 U886 ( .A(n957), .Y(n655) );
BUFX2 U887 ( .A(n955), .Y(n656) );
BUFX2 U888 ( .A(n953), .Y(n657) );
BUFX2 U889 ( .A(n951), .Y(n658) );
BUFX2 U890 ( .A(n949), .Y(n659) );
BUFX2 U891 ( .A(n947), .Y(n660) );
BUFX2 U892 ( .A(n881), .Y(n661) );
BUFX2 U893 ( .A(n879), .Y(n662) );
BUFX2 U894 ( .A(n877), .Y(n663) );
BUFX2 U895 ( .A(n875), .Y(n664) );
BUFX2 U896 ( .A(n873), .Y(n665) );
BUFX2 U897 ( .A(n871), .Y(n666) );
BUFX2 U898 ( .A(n869), .Y(n667) );
BUFX2 U899 ( .A(n867), .Y(n668) );
BUFX2 U900 ( .A(n865), .Y(n669) );
BUFX2 U901 ( .A(n863), .Y(n670) );
BUFX2 U902 ( .A(n861), .Y(n671) );
BUFX2 U903 ( .A(n859), .Y(n672) );
BUFX2 U904 ( .A(n857), .Y(n673) );
BUFX2 U905 ( .A(n855), .Y(n674) );
BUFX2 U906 ( .A(n853), .Y(n675) );
BUFX2 U907 ( .A(n851), .Y(n676) );
BUFX2 U908 ( .A(n945), .Y(n677) );
BUFX2 U909 ( .A(n943), .Y(n678) );
BUFX2 U910 ( .A(n941), .Y(n679) );
BUFX2 U911 ( .A(n939), .Y(n680) );
BUFX2 U912 ( .A(n937), .Y(n681) );
BUFX2 U913 ( .A(n935), .Y(n682) );
BUFX2 U914 ( .A(n933), .Y(n683) );
BUFX2 U915 ( .A(n931), .Y(n684) );
BUFX2 U916 ( .A(n929), .Y(n685) );
BUFX2 U917 ( .A(n927), .Y(n686) );
BUFX2 U918 ( .A(n925), .Y(n687) );
BUFX2 U919 ( .A(n923), .Y(n688) );
BUFX2 U920 ( .A(n921), .Y(n689) );
BUFX2 U921 ( .A(n919), .Y(n690) );
BUFX2 U922 ( .A(n917), .Y(n691) );
BUFX2 U923 ( .A(n915), .Y(n692) );
BUFX2 U924 ( .A(n913), .Y(n693) );
BUFX2 U925 ( .A(n911), .Y(n694) );
BUFX2 U926 ( .A(n909), .Y(n695) );
BUFX2 U927 ( .A(n907), .Y(n696) );
BUFX2 U928 ( .A(n905), .Y(n697) );
BUFX2 U929 ( .A(n903), .Y(n698) );
BUFX2 U930 ( .A(n901), .Y(n699) );
BUFX2 U931 ( .A(n899), .Y(n700) );
BUFX2 U932 ( .A(n897), .Y(n701) );
BUFX2 U933 ( .A(n895), .Y(n702) );
BUFX2 U934 ( .A(n893), .Y(n703) );
BUFX2 U935 ( .A(n891), .Y(n704) );
BUFX2 U936 ( .A(n889), .Y(n705) );
BUFX2 U937 ( .A(n887), .Y(n706) );
BUFX2 U938 ( .A(n885), .Y(n707) );
BUFX2 U939 ( .A(n883), .Y(n708) );
INVX1 U940 ( .A(n847), .Y(n709) );
INVX1 U941 ( .A(n756), .Y(n710) );
BUFX2 U942 ( .A(\qos/srv_cnt1_d [0]), .Y(n711) );
BUFX2 U943 ( .A(\qos/srv_cnt0_d [4]), .Y(n712) );
BUFX2 U944 ( .A(\qos/srv_cnt2_d [2]), .Y(n714) );
BUFX2 U945 ( .A(n834), .Y(n715) );
BUFX2 U946 ( .A(n836), .Y(n716) );
BUFX2 U947 ( .A(n839), .Y(n717) );
BUFX2 U948 ( .A(\qos/srv_cnt2_d [1]), .Y(n718) );
BUFX2 U949 ( .A(\qos/srv_cnt0_d [6]), .Y(n719) );
BUFX2 U950 ( .A(\qos/srv_cnt1_d [6]), .Y(n720) );
BUFX2 U951 ( .A(\qos/srv_cnt1_d [1]), .Y(n721) );
BUFX2 U952 ( .A(n753), .Y(n722) );
BUFX2 U953 ( .A(buffer_sel[2]), .Y(n723) );
XOR2X1 U954 ( .A(n807), .B(n808), .Y(n812) );
INVX1 U955 ( .A(n569), .Y(n725) );
NOR3X1 U956 ( .A(n573), .B(n723), .C(n725), .Y(n1048) );
AND2X1 U957 ( .A(n1048), .B(crcfifo_pop), .Y(crcfifo1_pull) );
AND2X1 U958 ( .A(n1048), .B(pfifo_pop), .Y(pfifo_pop_1) );
INVX1 U959 ( .A(n573), .Y(n727) );
NAND3X1 U960 ( .A(n727), .B(n725), .C(n723), .Y(n726) );
AND2X1 U961 ( .A(n1074), .B(crcfifo_pop), .Y(crcfifo2_pull) );
AND2X1 U962 ( .A(n1074), .B(pfifo_pop), .Y(pfifo_pop_2) );
NOR3X1 U963 ( .A(n723), .B(n569), .C(n727), .Y(n1075) );
AND2X1 U964 ( .A(n728), .B(crcfifo_pop), .Y(crcfifo0_pull) );
AND2X1 U965 ( .A(n728), .B(pfifo_pop), .Y(pfifo_pop_0) );
INVX1 U966 ( .A(crcfifo0_empty), .Y(n742) );
OR2X1 U967 ( .A(n742), .B(n567), .Y(start_transmit) );
NOR3X1 U968 ( .A(n555), .B(n720), .C(n591), .Y(n729) );
INVX1 U969 ( .A(n553), .Y(n761) );
INVX1 U970 ( .A(n430), .Y(n785) );
NAND3X1 U971 ( .A(n729), .B(n761), .C(n785), .Y(n730) );
NOR3X1 U972 ( .A(n583), .B(n721), .C(n546), .Y(n743) );
NOR3X1 U973 ( .A(n712), .B(n558), .C(n588), .Y(n732) );
NOR3X1 U974 ( .A(n719), .B(n557), .C(n590), .Y(n731) );
AND2X1 U975 ( .A(n732), .B(n731), .Y(n737) );
NOR3X1 U976 ( .A(n585), .B(n561), .C(n714), .Y(n734) );
INVX1 U977 ( .A(n718), .Y(n733) );
NAND3X1 U978 ( .A(n586), .B(n734), .C(n733), .Y(n735) );
NOR3X1 U979 ( .A(n589), .B(n560), .C(n547), .Y(n736) );
INVX1 U980 ( .A(n431), .Y(n788) );
NAND3X1 U981 ( .A(n736), .B(n788), .C(n570), .Y(n753) );
AND2X1 U982 ( .A(n742), .B(n737), .Y(n745) );
AOI21X1 U983 ( .A(n722), .B(n424), .C(crcfifo2_empty), .Y(n741) );
AOI21X1 U984 ( .A(n722), .B(n586), .C(n848), .Y(n740) );
INVX1 U985 ( .A(n417), .Y(n757) );
AOI22X1 U986 ( .A(arb_nxt), .B(n426), .C(n723), .D(n757), .Y(n749) );
INVX1 U987 ( .A(n427), .Y(\qos/queue_gnt_q [2]) );
NAND3X1 U988 ( .A(n743), .B(n742), .C(crcfifo1_empty), .Y(n744) );
OAI21X1 U989 ( .A(crcfifo1_empty), .B(n722), .C(n421), .Y(n746) );
AOI21X1 U990 ( .A(n746), .B(crcfifo2_empty), .C(n745), .Y(n748) );
OAI21X1 U991 ( .A(n425), .B(n848), .C(n422), .Y(\qos/queue_gnt_q [0]) );
INVX1 U992 ( .A(n561), .Y(n751) );
NOR3X1 U993 ( .A(n751), .B(n848), .C(n427), .Y(n763) );
AOI21X1 U994 ( .A(n751), .B(n545), .C(n763), .Y(n823) );
INVX1 U995 ( .A(crcfifo1_empty), .Y(n755) );
NOR3X1 U996 ( .A(crcfifo0_empty), .B(n722), .C(n567), .Y(n754) );
AOI21X1 U997 ( .A(n710), .B(n755), .C(n754), .Y(n849) );
OAI21X1 U998 ( .A(n721), .B(n767), .C(n562), .Y(n758) );
INVX1 U999 ( .A(n758), .Y(n832) );
INVX1 U1000 ( .A(n428), .Y(n759) );
INVX1 U1001 ( .A(n429), .Y(n766) );
AOI21X1 U1002 ( .A(n759), .B(n765), .C(n410), .Y(n840) );
AOI21X1 U1003 ( .A(n761), .B(n562), .C(n784), .Y(n833) );
MUX2X1 U1004 ( .B(n563), .A(n774), .S(n714), .Y(n825) );
OAI21X1 U1005 ( .A(n590), .B(n410), .C(n576), .Y(n762) );
INVX1 U1006 ( .A(n762), .Y(n841) );
OAI21X1 U1007 ( .A(n718), .B(n763), .C(n563), .Y(n764) );
INVX1 U1008 ( .A(n764), .Y(n824) );
HAX1 U1009 ( .A(n832), .B(n568), .YC(n771), .YS(n773) );
AOI21X1 U1010 ( .A(n766), .B(n423), .C(n420), .Y(n839) );
OAI21X1 U1011 ( .A(n416), .B(n711), .C(n552), .Y(n768) );
INVX1 U1012 ( .A(n768), .Y(n831) );
FAX1 U1013 ( .A(n771), .B(n770), .C(n769), .YS(n821) );
FAX1 U1014 ( .A(n824), .B(n773), .C(n772), .YC(n769), .YS(n820) );
AOI21X1 U1015 ( .A(n554), .B(n577), .C(n594), .Y(n836) );
AOI21X1 U1016 ( .A(n559), .B(n578), .C(n713), .Y(n828) );
INVX1 U1017 ( .A(n558), .Y(n791) );
AOI21X1 U1018 ( .A(n556), .B(n579), .C(n595), .Y(n844) );
INVX1 U1019 ( .A(n720), .Y(n775) );
MUX2X1 U1020 ( .B(n775), .A(n720), .S(n594), .Y(n837) );
MUX2X1 U1021 ( .B(n570), .A(n571), .S(n713), .Y(n829) );
INVX1 U1022 ( .A(n719), .Y(n776) );
MUX2X1 U1023 ( .B(n776), .A(n719), .S(n595), .Y(n845) );
OAI21X1 U1024 ( .A(n591), .B(n580), .C(n577), .Y(n778) );
OAI21X1 U1025 ( .A(n589), .B(n415), .C(n578), .Y(n780) );
OAI21X1 U1026 ( .A(n712), .B(n581), .C(n579), .Y(n782) );
FAX1 U1027 ( .A(n716), .B(n592), .C(n419), .YC(n796), .YS(n805) );
AOI21X1 U1028 ( .A(n785), .B(n572), .C(n580), .Y(n834) );
AOI21X1 U1029 ( .A(n788), .B(n566), .C(n415), .Y(n826) );
AOI21X1 U1030 ( .A(n791), .B(n576), .C(n581), .Y(n842) );
FAX1 U1031 ( .A(n835), .B(n843), .C(n827), .YC(n806), .YS(n809) );
FAX1 U1032 ( .A(n596), .B(n825), .C(n841), .YC(n808), .YS(n770) );
FAX1 U1033 ( .A(n715), .B(n593), .C(n575), .YC(n810), .YS(n807) );
MUX2X1 U1034 ( .B(n583), .A(n582), .S(n549), .Y(n838) );
FAX1 U1035 ( .A(n796), .B(n795), .C(n794), .YC(n803), .YS(n818) );
FAX1 U1036 ( .A(n837), .B(n829), .C(n845), .YC(n801), .YS(n795) );
MUX2X1 U1037 ( .B(n585), .A(n584), .S(n550), .Y(n830) );
MUX2X1 U1038 ( .B(n588), .A(n587), .S(n551), .Y(n846) );
FAX1 U1039 ( .A(n801), .B(n830), .C(n846), .YS(n802) );
FAX1 U1040 ( .A(n838), .B(n803), .C(n802), .YS(n817) );
FAX1 U1041 ( .A(n717), .B(n831), .C(n574), .YC(n772), .YS(n815) );
FAX1 U1042 ( .A(n806), .B(n805), .C(n804), .YC(n794), .YS(n813) );
FAX1 U1043 ( .A(n810), .B(n809), .C(n724), .YC(n804), .YS(n811) );
NOR3X1 U1044 ( .A(n813), .B(n812), .C(n811), .Y(n814) );
NOR3X1 U1045 ( .A(n818), .B(n817), .C(n548), .Y(n819) );
OAI21X1 U1046 ( .A(n418), .B(n848), .C(n709), .Y(\qos/queue_gnt_q [1]) );
BUFX2 U1047 ( .A(n1048), .Y(n1073) );
AOI22X1 U1048 ( .A(n1074), .B(pfifo_datain_ctrl_2[0]), .C(n1073), .D(
pfifo_datain_ctrl_1[0]), .Y(n851) );
NAND2X1 U1049 ( .A(n676), .B(n433), .Y(pfifo_datain_ctrl[0]) );
AOI22X1 U1050 ( .A(n1074), .B(pfifo_datain_ctrl_2[1]), .C(n1073), .D(
pfifo_datain_ctrl_1[1]), .Y(n853) );
NAND2X1 U1051 ( .A(n675), .B(n434), .Y(pfifo_datain_ctrl[1]) );
AOI22X1 U1052 ( .A(n1074), .B(pfifo_datain_ctrl_2[2]), .C(n1073), .D(
pfifo_datain_ctrl_1[2]), .Y(n855) );
NAND2X1 U1053 ( .A(n674), .B(n435), .Y(pfifo_datain_ctrl[2]) );
AOI22X1 U1054 ( .A(n1074), .B(pfifo_datain_ctrl_2[3]), .C(n1048), .D(
pfifo_datain_ctrl_1[3]), .Y(n857) );
NAND2X1 U1055 ( .A(n673), .B(n436), .Y(pfifo_datain_ctrl[3]) );
AOI22X1 U1056 ( .A(n1074), .B(pfifo_datain_ctrl_2[4]), .C(n1073), .D(
pfifo_datain_ctrl_1[4]), .Y(n859) );
NAND2X1 U1057 ( .A(n672), .B(n437), .Y(pfifo_datain_ctrl[4]) );
AOI22X1 U1058 ( .A(n1074), .B(pfifo_datain_ctrl_2[5]), .C(n1073), .D(
pfifo_datain_ctrl_1[5]), .Y(n861) );
NAND2X1 U1059 ( .A(n671), .B(n438), .Y(pfifo_datain_ctrl[5]) );
AOI22X1 U1060 ( .A(n1074), .B(pfifo_datain_ctrl_2[6]), .C(n1073), .D(
pfifo_datain_ctrl_1[6]), .Y(n863) );
NAND2X1 U1061 ( .A(n670), .B(n439), .Y(pfifo_datain_ctrl[6]) );
AOI22X1 U1062 ( .A(n1074), .B(pfifo_datain_ctrl_2[7]), .C(n1073), .D(
pfifo_datain_ctrl_1[7]), .Y(n865) );
NAND2X1 U1063 ( .A(n669), .B(n440), .Y(pfifo_datain_ctrl[7]) );
AOI22X1 U1064 ( .A(n1074), .B(pfifo_datain_ctrl_2[8]), .C(n1073), .D(
pfifo_datain_ctrl_1[8]), .Y(n867) );
NAND2X1 U1065 ( .A(n668), .B(n441), .Y(pfifo_datain_ctrl[8]) );
AOI22X1 U1066 ( .A(n1074), .B(pfifo_datain_ctrl_2[9]), .C(n1048), .D(
pfifo_datain_ctrl_1[9]), .Y(n869) );
NAND2X1 U1067 ( .A(n667), .B(n442), .Y(pfifo_datain_ctrl[9]) );
AOI22X1 U1068 ( .A(n1074), .B(pfifo_datain_ctrl_2[10]), .C(n1073), .D(
pfifo_datain_ctrl_1[10]), .Y(n871) );
NAND2X1 U1069 ( .A(n666), .B(n443), .Y(pfifo_datain_ctrl[10]) );
AOI22X1 U1070 ( .A(n1074), .B(pfifo_datain_ctrl_2[11]), .C(n1048), .D(
pfifo_datain_ctrl_1[11]), .Y(n873) );
NAND2X1 U1071 ( .A(n665), .B(n444), .Y(pfifo_datain_ctrl[11]) );
AOI22X1 U1072 ( .A(n1074), .B(pfifo_datain_ctrl_2[12]), .C(n1048), .D(
pfifo_datain_ctrl_1[12]), .Y(n875) );
NAND2X1 U1073 ( .A(n664), .B(n445), .Y(pfifo_datain_ctrl[12]) );
AOI22X1 U1074 ( .A(n1074), .B(pfifo_datain_ctrl_2[13]), .C(n1073), .D(
pfifo_datain_ctrl_1[13]), .Y(n877) );
NAND2X1 U1075 ( .A(n663), .B(n446), .Y(pfifo_datain_ctrl[13]) );
AOI22X1 U1076 ( .A(n1074), .B(pfifo_datain_ctrl_2[14]), .C(n1048), .D(
pfifo_datain_ctrl_1[14]), .Y(n879) );
NAND2X1 U1077 ( .A(n662), .B(n447), .Y(pfifo_datain_ctrl[14]) );
AOI22X1 U1078 ( .A(n1074), .B(pfifo_datain_ctrl_2[15]), .C(n1073), .D(
pfifo_datain_ctrl_1[15]), .Y(n881) );
NAND2X1 U1079 ( .A(n661), .B(n448), .Y(pfifo_datain_ctrl[15]) );
AOI22X1 U1080 ( .A(n1074), .B(crcfifo2_dataout[0]), .C(n1048), .D(
crcfifo1_dataout[0]), .Y(n883) );
NAND2X1 U1081 ( .A(n708), .B(n449), .Y(crcfifo_dataout[0]) );
AOI22X1 U1082 ( .A(n1074), .B(crcfifo2_dataout[1]), .C(n1073), .D(
crcfifo1_dataout[1]), .Y(n885) );
NAND2X1 U1083 ( .A(n707), .B(n450), .Y(crcfifo_dataout[1]) );
AOI22X1 U1084 ( .A(n1074), .B(crcfifo2_dataout[2]), .C(n1048), .D(
crcfifo1_dataout[2]), .Y(n887) );
NAND2X1 U1085 ( .A(n706), .B(n451), .Y(crcfifo_dataout[2]) );
AOI22X1 U1086 ( .A(n1074), .B(crcfifo2_dataout[3]), .C(n1048), .D(
crcfifo1_dataout[3]), .Y(n889) );
NAND2X1 U1087 ( .A(n705), .B(n452), .Y(crcfifo_dataout[3]) );
AOI22X1 U1088 ( .A(n1074), .B(crcfifo2_dataout[4]), .C(n1073), .D(
crcfifo1_dataout[4]), .Y(n891) );
NAND2X1 U1089 ( .A(n704), .B(n453), .Y(crcfifo_dataout[4]) );
AOI22X1 U1090 ( .A(n1074), .B(crcfifo2_dataout[5]), .C(n1048), .D(
crcfifo1_dataout[5]), .Y(n893) );
NAND2X1 U1091 ( .A(n703), .B(n454), .Y(crcfifo_dataout[5]) );
AOI22X1 U1092 ( .A(n1074), .B(crcfifo2_dataout[6]), .C(n1073), .D(
crcfifo1_dataout[6]), .Y(n895) );
NAND2X1 U1093 ( .A(n702), .B(n455), .Y(crcfifo_dataout[6]) );
AOI22X1 U1094 ( .A(n1074), .B(crcfifo2_dataout[7]), .C(n1048), .D(
crcfifo1_dataout[7]), .Y(n897) );
NAND2X1 U1095 ( .A(n701), .B(n456), .Y(crcfifo_dataout[7]) );
AOI22X1 U1096 ( .A(n1074), .B(crcfifo2_dataout[8]), .C(n1073), .D(
crcfifo1_dataout[8]), .Y(n899) );
NAND2X1 U1097 ( .A(n700), .B(n457), .Y(crcfifo_dataout[8]) );
AOI22X1 U1098 ( .A(n1074), .B(crcfifo2_dataout[9]), .C(n1048), .D(
crcfifo1_dataout[9]), .Y(n901) );
NAND2X1 U1099 ( .A(n699), .B(n458), .Y(crcfifo_dataout[9]) );
AOI22X1 U1100 ( .A(n1074), .B(crcfifo2_dataout[10]), .C(n1048), .D(
crcfifo1_dataout[10]), .Y(n903) );
NAND2X1 U1101 ( .A(n698), .B(n459), .Y(crcfifo_dataout[10]) );
AOI22X1 U1102 ( .A(n1074), .B(crcfifo2_dataout[11]), .C(n1048), .D(
crcfifo1_dataout[11]), .Y(n905) );
NAND2X1 U1103 ( .A(n697), .B(n460), .Y(crcfifo_dataout[11]) );
AOI22X1 U1104 ( .A(n1074), .B(crcfifo2_dataout[12]), .C(n1048), .D(
crcfifo1_dataout[12]), .Y(n907) );
NAND2X1 U1105 ( .A(n696), .B(n461), .Y(crcfifo_dataout[12]) );
AOI22X1 U1106 ( .A(n1074), .B(crcfifo2_dataout[13]), .C(n1073), .D(
crcfifo1_dataout[13]), .Y(n909) );
NAND2X1 U1107 ( .A(n695), .B(n462), .Y(crcfifo_dataout[13]) );
AOI22X1 U1108 ( .A(n1074), .B(crcfifo2_dataout[14]), .C(n1073), .D(
crcfifo1_dataout[14]), .Y(n911) );
NAND2X1 U1109 ( .A(n694), .B(n463), .Y(crcfifo_dataout[14]) );
AOI22X1 U1110 ( .A(n1074), .B(crcfifo2_dataout[15]), .C(n1073), .D(
crcfifo1_dataout[15]), .Y(n913) );
NAND2X1 U1111 ( .A(n693), .B(n464), .Y(crcfifo_dataout[15]) );
AOI22X1 U1112 ( .A(n1074), .B(crcfifo2_dataout[16]), .C(n1048), .D(
crcfifo1_dataout[16]), .Y(n915) );
NAND2X1 U1113 ( .A(n692), .B(n465), .Y(crcfifo_dataout[16]) );
AOI22X1 U1114 ( .A(n1074), .B(crcfifo2_dataout[17]), .C(n1073), .D(
crcfifo1_dataout[17]), .Y(n917) );
NAND2X1 U1115 ( .A(n691), .B(n466), .Y(crcfifo_dataout[17]) );
AOI22X1 U1116 ( .A(n1074), .B(crcfifo2_dataout[18]), .C(n1048), .D(
crcfifo1_dataout[18]), .Y(n919) );
NAND2X1 U1117 ( .A(n690), .B(n467), .Y(crcfifo_dataout[18]) );
AOI22X1 U1118 ( .A(n1074), .B(crcfifo2_dataout[19]), .C(n1073), .D(
crcfifo1_dataout[19]), .Y(n921) );
NAND2X1 U1119 ( .A(n689), .B(n468), .Y(crcfifo_dataout[19]) );
AOI22X1 U1120 ( .A(n1074), .B(crcfifo2_dataout[20]), .C(n1048), .D(
crcfifo1_dataout[20]), .Y(n923) );
NAND2X1 U1121 ( .A(n688), .B(n469), .Y(crcfifo_dataout[20]) );
AOI22X1 U1122 ( .A(n1074), .B(crcfifo2_dataout[21]), .C(n1048), .D(
crcfifo1_dataout[21]), .Y(n925) );
NAND2X1 U1123 ( .A(n687), .B(n470), .Y(crcfifo_dataout[21]) );
AOI22X1 U1124 ( .A(n1074), .B(crcfifo2_dataout[22]), .C(n1073), .D(
crcfifo1_dataout[22]), .Y(n927) );
NAND2X1 U1125 ( .A(n686), .B(n471), .Y(crcfifo_dataout[22]) );
AOI22X1 U1126 ( .A(n1074), .B(crcfifo2_dataout[23]), .C(n1073), .D(
crcfifo1_dataout[23]), .Y(n929) );
NAND2X1 U1127 ( .A(n685), .B(n472), .Y(crcfifo_dataout[23]) );
AOI22X1 U1128 ( .A(n1074), .B(crcfifo2_dataout[24]), .C(n1073), .D(
crcfifo1_dataout[24]), .Y(n931) );
NAND2X1 U1129 ( .A(n684), .B(n473), .Y(crcfifo_dataout[24]) );
AOI22X1 U1130 ( .A(n1074), .B(crcfifo2_dataout[25]), .C(n1073), .D(
crcfifo1_dataout[25]), .Y(n933) );
NAND2X1 U1131 ( .A(n683), .B(n474), .Y(crcfifo_dataout[25]) );
AOI22X1 U1132 ( .A(n1074), .B(crcfifo2_dataout[26]), .C(n1048), .D(
crcfifo1_dataout[26]), .Y(n935) );
NAND2X1 U1133 ( .A(n682), .B(n475), .Y(crcfifo_dataout[26]) );
AOI22X1 U1134 ( .A(n1074), .B(crcfifo2_dataout[27]), .C(n1073), .D(
crcfifo1_dataout[27]), .Y(n937) );
NAND2X1 U1135 ( .A(n681), .B(n476), .Y(crcfifo_dataout[27]) );
AOI22X1 U1136 ( .A(n1074), .B(crcfifo2_dataout[28]), .C(n1073), .D(
crcfifo1_dataout[28]), .Y(n939) );
NAND2X1 U1137 ( .A(n680), .B(n477), .Y(crcfifo_dataout[28]) );
AOI22X1 U1138 ( .A(n1074), .B(crcfifo2_dataout[29]), .C(n1048), .D(
crcfifo1_dataout[29]), .Y(n941) );
NAND2X1 U1139 ( .A(n679), .B(n478), .Y(crcfifo_dataout[29]) );
AOI22X1 U1140 ( .A(n1074), .B(crcfifo2_dataout[30]), .C(n1073), .D(
crcfifo1_dataout[30]), .Y(n943) );
NAND2X1 U1141 ( .A(n678), .B(n479), .Y(crcfifo_dataout[30]) );
AOI22X1 U1142 ( .A(n1074), .B(crcfifo2_dataout[31]), .C(n1073), .D(
crcfifo1_dataout[31]), .Y(n945) );
NAND2X1 U1143 ( .A(n677), .B(n480), .Y(crcfifo_dataout[31]) );
AOI22X1 U1144 ( .A(n1074), .B(pfifo_datain2[0]), .C(n1073), .D(
pfifo_datain1[0]), .Y(n947) );
NAND2X1 U1145 ( .A(n660), .B(n481), .Y(pfifo_datain[0]) );
AOI22X1 U1146 ( .A(n1074), .B(pfifo_datain2[1]), .C(n1073), .D(
pfifo_datain1[1]), .Y(n949) );
NAND2X1 U1147 ( .A(n659), .B(n482), .Y(pfifo_datain[1]) );
AOI22X1 U1148 ( .A(n1074), .B(pfifo_datain2[2]), .C(n1073), .D(
pfifo_datain1[2]), .Y(n951) );
NAND2X1 U1149 ( .A(n658), .B(n483), .Y(pfifo_datain[2]) );
AOI22X1 U1150 ( .A(n1074), .B(pfifo_datain2[3]), .C(n1073), .D(
pfifo_datain1[3]), .Y(n953) );
NAND2X1 U1151 ( .A(n657), .B(n484), .Y(pfifo_datain[3]) );
AOI22X1 U1152 ( .A(n1074), .B(pfifo_datain2[4]), .C(n1048), .D(
pfifo_datain1[4]), .Y(n955) );
NAND2X1 U1153 ( .A(n656), .B(n485), .Y(pfifo_datain[4]) );
AOI22X1 U1154 ( .A(n1074), .B(pfifo_datain2[5]), .C(n1073), .D(
pfifo_datain1[5]), .Y(n957) );
NAND2X1 U1155 ( .A(n655), .B(n486), .Y(pfifo_datain[5]) );
AOI22X1 U1156 ( .A(n1074), .B(pfifo_datain2[6]), .C(n1073), .D(
pfifo_datain1[6]), .Y(n959) );
NAND2X1 U1157 ( .A(n654), .B(n487), .Y(pfifo_datain[6]) );
AOI22X1 U1158 ( .A(n1074), .B(pfifo_datain2[7]), .C(n1048), .D(
pfifo_datain1[7]), .Y(n961) );
NAND2X1 U1159 ( .A(n653), .B(n488), .Y(pfifo_datain[7]) );
AOI22X1 U1160 ( .A(n1074), .B(pfifo_datain2[8]), .C(n1073), .D(
pfifo_datain1[8]), .Y(n963) );
NAND2X1 U1161 ( .A(n652), .B(n489), .Y(pfifo_datain[8]) );
AOI22X1 U1162 ( .A(n1074), .B(pfifo_datain2[9]), .C(n1073), .D(
pfifo_datain1[9]), .Y(n965) );
NAND2X1 U1163 ( .A(n651), .B(n490), .Y(pfifo_datain[9]) );
AOI22X1 U1164 ( .A(n1074), .B(pfifo_datain2[10]), .C(n1073), .D(
pfifo_datain1[10]), .Y(n967) );
NAND2X1 U1165 ( .A(n650), .B(n491), .Y(pfifo_datain[10]) );
AOI22X1 U1166 ( .A(n1074), .B(pfifo_datain2[11]), .C(n1073), .D(
pfifo_datain1[11]), .Y(n969) );
NAND2X1 U1167 ( .A(n649), .B(n492), .Y(pfifo_datain[11]) );
AOI22X1 U1168 ( .A(n1074), .B(pfifo_datain2[12]), .C(n1073), .D(
pfifo_datain1[12]), .Y(n971) );
NAND2X1 U1169 ( .A(n648), .B(n493), .Y(pfifo_datain[12]) );
AOI22X1 U1170 ( .A(n1074), .B(pfifo_datain2[13]), .C(n1048), .D(
pfifo_datain1[13]), .Y(n973) );
NAND2X1 U1171 ( .A(n647), .B(n494), .Y(pfifo_datain[13]) );
AOI22X1 U1172 ( .A(n1074), .B(pfifo_datain2[14]), .C(n1048), .D(
pfifo_datain1[14]), .Y(n975) );
NAND2X1 U1173 ( .A(n646), .B(n495), .Y(pfifo_datain[14]) );
AOI22X1 U1174 ( .A(n1074), .B(pfifo_datain2[15]), .C(n1048), .D(
pfifo_datain1[15]), .Y(n977) );
NAND2X1 U1175 ( .A(n645), .B(n496), .Y(pfifo_datain[15]) );
AOI22X1 U1176 ( .A(n1074), .B(pfifo_datain2[16]), .C(n1073), .D(
pfifo_datain1[16]), .Y(n979) );
NAND2X1 U1177 ( .A(n644), .B(n497), .Y(pfifo_datain[16]) );
AOI22X1 U1178 ( .A(n1074), .B(pfifo_datain2[17]), .C(n1073), .D(
pfifo_datain1[17]), .Y(n981) );
NAND2X1 U1179 ( .A(n643), .B(n498), .Y(pfifo_datain[17]) );
AOI22X1 U1180 ( .A(n1074), .B(pfifo_datain2[18]), .C(n1073), .D(
pfifo_datain1[18]), .Y(n983) );
NAND2X1 U1181 ( .A(n642), .B(n499), .Y(pfifo_datain[18]) );
AOI22X1 U1182 ( .A(n1074), .B(pfifo_datain2[19]), .C(n1073), .D(
pfifo_datain1[19]), .Y(n985) );
NAND2X1 U1183 ( .A(n641), .B(n500), .Y(pfifo_datain[19]) );
AOI22X1 U1184 ( .A(n1074), .B(pfifo_datain2[20]), .C(n1073), .D(
pfifo_datain1[20]), .Y(n987) );
NAND2X1 U1185 ( .A(n640), .B(n501), .Y(pfifo_datain[20]) );
AOI22X1 U1186 ( .A(n1074), .B(pfifo_datain2[21]), .C(n1073), .D(
pfifo_datain1[21]), .Y(n989) );
NAND2X1 U1187 ( .A(n639), .B(n502), .Y(pfifo_datain[21]) );
AOI22X1 U1188 ( .A(n1074), .B(pfifo_datain2[22]), .C(n1073), .D(
pfifo_datain1[22]), .Y(n991) );
NAND2X1 U1189 ( .A(n638), .B(n503), .Y(pfifo_datain[22]) );
AOI22X1 U1190 ( .A(n1074), .B(pfifo_datain2[23]), .C(n1073), .D(
pfifo_datain1[23]), .Y(n993) );
NAND2X1 U1191 ( .A(n637), .B(n504), .Y(pfifo_datain[23]) );
AOI22X1 U1192 ( .A(n1074), .B(pfifo_datain2[24]), .C(n1073), .D(
pfifo_datain1[24]), .Y(n995) );
NAND2X1 U1193 ( .A(n636), .B(n505), .Y(pfifo_datain[24]) );
AOI22X1 U1194 ( .A(n1074), .B(pfifo_datain2[25]), .C(n1073), .D(
pfifo_datain1[25]), .Y(n997) );
NAND2X1 U1195 ( .A(n635), .B(n506), .Y(pfifo_datain[25]) );
AOI22X1 U1196 ( .A(n1074), .B(pfifo_datain2[26]), .C(n1073), .D(
pfifo_datain1[26]), .Y(n999) );
NAND2X1 U1197 ( .A(n634), .B(n507), .Y(pfifo_datain[26]) );
AOI22X1 U1198 ( .A(n1074), .B(pfifo_datain2[27]), .C(n1073), .D(
pfifo_datain1[27]), .Y(n1001) );
NAND2X1 U1199 ( .A(n633), .B(n508), .Y(pfifo_datain[27]) );
AOI22X1 U1200 ( .A(n1074), .B(pfifo_datain2[28]), .C(n1073), .D(
pfifo_datain1[28]), .Y(n1003) );
NAND2X1 U1201 ( .A(n632), .B(n509), .Y(pfifo_datain[28]) );
AOI22X1 U1202 ( .A(n1074), .B(pfifo_datain2[29]), .C(n1073), .D(
pfifo_datain1[29]), .Y(n1005) );
NAND2X1 U1203 ( .A(n631), .B(n510), .Y(pfifo_datain[29]) );
AOI22X1 U1204 ( .A(n1074), .B(pfifo_datain2[30]), .C(n1073), .D(
pfifo_datain1[30]), .Y(n1007) );
NAND2X1 U1205 ( .A(n630), .B(n511), .Y(pfifo_datain[30]) );
AOI22X1 U1206 ( .A(n1074), .B(pfifo_datain2[31]), .C(n1073), .D(
pfifo_datain1[31]), .Y(n1009) );
NAND2X1 U1207 ( .A(n629), .B(n512), .Y(pfifo_datain[31]) );
AOI22X1 U1208 ( .A(n1074), .B(pfifo_datain2[32]), .C(n1073), .D(
pfifo_datain1[32]), .Y(n1011) );
NAND2X1 U1209 ( .A(n628), .B(n513), .Y(pfifo_datain[32]) );
AOI22X1 U1210 ( .A(n1074), .B(pfifo_datain2[33]), .C(n1073), .D(
pfifo_datain1[33]), .Y(n1013) );
NAND2X1 U1211 ( .A(n627), .B(n514), .Y(pfifo_datain[33]) );
AOI22X1 U1212 ( .A(n1074), .B(pfifo_datain2[34]), .C(n1073), .D(
pfifo_datain1[34]), .Y(n1015) );
NAND2X1 U1213 ( .A(n626), .B(n515), .Y(pfifo_datain[34]) );
AOI22X1 U1214 ( .A(n1074), .B(pfifo_datain2[35]), .C(n1073), .D(
pfifo_datain1[35]), .Y(n1017) );
NAND2X1 U1215 ( .A(n625), .B(n516), .Y(pfifo_datain[35]) );
AOI22X1 U1216 ( .A(n1074), .B(pfifo_datain2[36]), .C(n1048), .D(
pfifo_datain1[36]), .Y(n1019) );
NAND2X1 U1217 ( .A(n624), .B(n517), .Y(pfifo_datain[36]) );
AOI22X1 U1218 ( .A(n1074), .B(pfifo_datain2[37]), .C(n1073), .D(
pfifo_datain1[37]), .Y(n1021) );
NAND2X1 U1219 ( .A(n623), .B(n518), .Y(pfifo_datain[37]) );
AOI22X1 U1220 ( .A(n1074), .B(pfifo_datain2[38]), .C(n1073), .D(
pfifo_datain1[38]), .Y(n1023) );
NAND2X1 U1221 ( .A(n622), .B(n519), .Y(pfifo_datain[38]) );
AOI22X1 U1222 ( .A(n1074), .B(pfifo_datain2[39]), .C(n1073), .D(
pfifo_datain1[39]), .Y(n1025) );
NAND2X1 U1223 ( .A(n621), .B(n520), .Y(pfifo_datain[39]) );
AOI22X1 U1224 ( .A(n1074), .B(pfifo_datain2[40]), .C(n1073), .D(
pfifo_datain1[40]), .Y(n1027) );
NAND2X1 U1225 ( .A(n620), .B(n521), .Y(pfifo_datain[40]) );
AOI22X1 U1226 ( .A(n1074), .B(pfifo_datain2[41]), .C(n1073), .D(
pfifo_datain1[41]), .Y(n1029) );
NAND2X1 U1227 ( .A(n619), .B(n522), .Y(pfifo_datain[41]) );
AOI22X1 U1228 ( .A(n1074), .B(pfifo_datain2[42]), .C(n1073), .D(
pfifo_datain1[42]), .Y(n1031) );
NAND2X1 U1229 ( .A(n618), .B(n523), .Y(pfifo_datain[42]) );
AOI22X1 U1230 ( .A(n1074), .B(pfifo_datain2[43]), .C(n1048), .D(
pfifo_datain1[43]), .Y(n1033) );
NAND2X1 U1231 ( .A(n617), .B(n524), .Y(pfifo_datain[43]) );
AOI22X1 U1232 ( .A(n1074), .B(pfifo_datain2[44]), .C(n1048), .D(
pfifo_datain1[44]), .Y(n1035) );
NAND2X1 U1233 ( .A(n616), .B(n525), .Y(pfifo_datain[44]) );
AOI22X1 U1234 ( .A(n1074), .B(pfifo_datain2[45]), .C(n1048), .D(
pfifo_datain1[45]), .Y(n1037) );
NAND2X1 U1235 ( .A(n615), .B(n526), .Y(pfifo_datain[45]) );
AOI22X1 U1236 ( .A(n1074), .B(pfifo_datain2[46]), .C(n1048), .D(
pfifo_datain1[46]), .Y(n1039) );
NAND2X1 U1237 ( .A(n614), .B(n527), .Y(pfifo_datain[46]) );
AOI22X1 U1238 ( .A(n1074), .B(pfifo_datain2[47]), .C(n1073), .D(
pfifo_datain1[47]), .Y(n1041) );
NAND2X1 U1239 ( .A(n613), .B(n528), .Y(pfifo_datain[47]) );
AOI22X1 U1240 ( .A(n1074), .B(pfifo_datain2[48]), .C(n1073), .D(
pfifo_datain1[48]), .Y(n1043) );
NAND2X1 U1241 ( .A(n612), .B(n529), .Y(pfifo_datain[48]) );
AOI22X1 U1242 ( .A(n1074), .B(pfifo_datain2[49]), .C(n1073), .D(
pfifo_datain1[49]), .Y(n1045) );
NAND2X1 U1243 ( .A(n611), .B(n530), .Y(pfifo_datain[49]) );
AOI22X1 U1244 ( .A(n1074), .B(pfifo_datain2[50]), .C(n1073), .D(
pfifo_datain1[50]), .Y(n1047) );
NAND2X1 U1245 ( .A(n610), .B(n531), .Y(pfifo_datain[50]) );
AOI22X1 U1246 ( .A(n1074), .B(pfifo_datain2[51]), .C(n1048), .D(
pfifo_datain1[51]), .Y(n1050) );
NAND2X1 U1247 ( .A(n609), .B(n532), .Y(pfifo_datain[51]) );
AOI22X1 U1248 ( .A(n1074), .B(pfifo_datain2[52]), .C(n1073), .D(
pfifo_datain1[52]), .Y(n1052) );
NAND2X1 U1249 ( .A(n608), .B(n533), .Y(pfifo_datain[52]) );
AOI22X1 U1250 ( .A(n1074), .B(pfifo_datain2[53]), .C(n1073), .D(
pfifo_datain1[53]), .Y(n1054) );
NAND2X1 U1251 ( .A(n607), .B(n534), .Y(pfifo_datain[53]) );
AOI22X1 U1252 ( .A(n1074), .B(pfifo_datain2[54]), .C(n1073), .D(
pfifo_datain1[54]), .Y(n1056) );
NAND2X1 U1253 ( .A(n606), .B(n535), .Y(pfifo_datain[54]) );
AOI22X1 U1254 ( .A(n1074), .B(pfifo_datain2[55]), .C(n1073), .D(
pfifo_datain1[55]), .Y(n1058) );
NAND2X1 U1255 ( .A(n605), .B(n536), .Y(pfifo_datain[55]) );
AOI22X1 U1256 ( .A(n1074), .B(pfifo_datain2[56]), .C(n1073), .D(
pfifo_datain1[56]), .Y(n1060) );
NAND2X1 U1257 ( .A(n604), .B(n537), .Y(pfifo_datain[56]) );
AOI22X1 U1258 ( .A(n1074), .B(pfifo_datain2[57]), .C(n1073), .D(
pfifo_datain1[57]), .Y(n1062) );
NAND2X1 U1259 ( .A(n603), .B(n538), .Y(pfifo_datain[57]) );
AOI22X1 U1260 ( .A(n1074), .B(pfifo_datain2[58]), .C(n1073), .D(
pfifo_datain1[58]), .Y(n1064) );
NAND2X1 U1261 ( .A(n602), .B(n539), .Y(pfifo_datain[58]) );
AOI22X1 U1262 ( .A(n1074), .B(pfifo_datain2[59]), .C(n1073), .D(
pfifo_datain1[59]), .Y(n1066) );
NAND2X1 U1263 ( .A(n601), .B(n540), .Y(pfifo_datain[59]) );
AOI22X1 U1264 ( .A(n1074), .B(pfifo_datain2[60]), .C(n1073), .D(
pfifo_datain1[60]), .Y(n1068) );
NAND2X1 U1265 ( .A(n600), .B(n541), .Y(pfifo_datain[60]) );
AOI22X1 U1266 ( .A(n1074), .B(pfifo_datain2[61]), .C(n1073), .D(
pfifo_datain1[61]), .Y(n1070) );
NAND2X1 U1267 ( .A(n599), .B(n542), .Y(pfifo_datain[61]) );
AOI22X1 U1268 ( .A(n1074), .B(pfifo_datain2[62]), .C(n1073), .D(
pfifo_datain1[62]), .Y(n1072) );
NAND2X1 U1269 ( .A(n598), .B(n543), .Y(pfifo_datain[62]) );
AOI22X1 U1270 ( .A(n1074), .B(pfifo_datain2[63]), .C(n1073), .D(
pfifo_datain1[63]), .Y(n1077) );
NAND2X1 U1271 ( .A(n597), .B(n544), .Y(pfifo_datain[63]) );
endmodule | module queue_selection ( \clks.clk , \clks.rst , arb_nxt, pfifo_datain0,
pfifo_datain1, pfifo_datain2, crcfifo0_dataout, crcfifo1_dataout,
crcfifo2_dataout, pfifo_datain_ctrl_0, pfifo_datain_ctrl_1,
pfifo_datain_ctrl_2, crcfifo0_empty, crcfifo1_empty, crcfifo2_empty,
pfifo_pop, crcfifo_pop, crcfifo0_pull, crcfifo1_pull, crcfifo2_pull,
pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1,
pcfifo_pop_2, pfifo_datain, pfifo_datain_ctrl, crcfifo_dataout,
start_transmit ); |
input [63:0] pfifo_datain0;
input [63:0] pfifo_datain1;
input [63:0] pfifo_datain2;
input [31:0] crcfifo0_dataout;
input [31:0] crcfifo1_dataout;
input [31:0] crcfifo2_dataout;
input [15:0] pfifo_datain_ctrl_0;
input [15:0] pfifo_datain_ctrl_1;
input [15:0] pfifo_datain_ctrl_2;
output [63:0] pfifo_datain;
output [15:0] pfifo_datain_ctrl;
output [31:0] crcfifo_dataout;
input \clks.clk , \clks.rst , arb_nxt, crcfifo0_empty, crcfifo1_empty,
crcfifo2_empty, pfifo_pop, crcfifo_pop;
output crcfifo0_pull, crcfifo1_pull, crcfifo2_pull, pfifo_pop_0, pfifo_pop_1,
pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1, pcfifo_pop_2, start_transmit;
wire pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, \qos/N33 , \qos/N32 ,
\qos/N31 , \qos/N30 , \qos/N29 , \qos/N28 , \qos/N27 , \qos/N26 ,
\qos/N25 , \qos/N24 , \qos/N23 , \qos/N22 , \qos/N21 , \qos/N20 ,
\qos/N19 , \qos/N18 , \qos/N17 , \qos/N16 , \qos/N15 , \qos/N14 ,
\qos/N13 , \qos/N12 , \qos/N11 , \qos/N10 , n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,
n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534,
n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622,
n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633,
n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644,
n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666,
n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688,
n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077;
wire [2:0] buffer_sel;
wire [2:0] \qos/queue_gnt_q ;
wire [7:0] \qos/srv_cnt2_d ;
wire [7:0] \qos/srv_cnt1_d ;
wire [7:0] \qos/srv_cnt0_d ;
assign pcfifo_pop_0 = pfifo_pop_0;
assign pcfifo_pop_1 = pfifo_pop_1;
assign pcfifo_pop_2 = pfifo_pop_2;
DFFSR \qos/queue_gnt_d_reg[2] ( .D(\qos/queue_gnt_q [2]), .CLK(\clks.clk ),
.R(\clks.rst ), .S(1'b1), .Q(buffer_sel[2]) );
DFFSR \qos/srv_cnt2_d_reg[0] ( .D(\qos/N26 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [0]) );
DFFSR \qos/srv_cnt2_d_reg[1] ( .D(\qos/N27 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [1]) );
DFFSR \qos/srv_cnt2_d_reg[2] ( .D(\qos/N28 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [2]) );
DFFSR \qos/srv_cnt2_d_reg[3] ( .D(\qos/N29 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [3]) );
DFFSR \qos/srv_cnt2_d_reg[4] ( .D(\qos/N30 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [4]) );
DFFSR \qos/srv_cnt2_d_reg[5] ( .D(\qos/N31 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [5]) );
DFFSR \qos/srv_cnt2_d_reg[6] ( .D(\qos/N32 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [6]) );
DFFSR \qos/srv_cnt2_d_reg[7] ( .D(\qos/N33 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt2_d [7]) );
DFFSR \qos/queue_gnt_d_reg[1] ( .D(\qos/queue_gnt_q [1]), .CLK(\clks.clk ),
.R(\clks.rst ), .S(1'b1), .Q(buffer_sel[1]) );
DFFSR \qos/srv_cnt1_d_reg[0] ( .D(\qos/N18 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [0]) );
DFFSR \qos/srv_cnt1_d_reg[1] ( .D(\qos/N19 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [1]) );
DFFSR \qos/srv_cnt1_d_reg[2] ( .D(\qos/N20 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [2]) );
DFFSR \qos/srv_cnt1_d_reg[3] ( .D(\qos/N21 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [3]) );
DFFSR \qos/srv_cnt1_d_reg[4] ( .D(\qos/N22 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [4]) );
DFFSR \qos/srv_cnt1_d_reg[5] ( .D(\qos/N23 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [5]) );
DFFSR \qos/srv_cnt1_d_reg[6] ( .D(\qos/N24 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [6]) );
DFFSR \qos/srv_cnt1_d_reg[7] ( .D(\qos/N25 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt1_d [7]) );
DFFSR \qos/queue_gnt_d_reg[0] ( .D(\qos/queue_gnt_q [0]), .CLK(\clks.clk ),
.R(\clks.rst ), .S(1'b1), .Q(buffer_sel[0]) );
DFFSR \qos/srv_cnt0_d_reg[0] ( .D(\qos/N10 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [0]) );
DFFSR \qos/srv_cnt0_d_reg[1] ( .D(\qos/N11 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [1]) );
DFFSR \qos/srv_cnt0_d_reg[2] ( .D(\qos/N12 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [2]) );
DFFSR \qos/srv_cnt0_d_reg[3] ( .D(\qos/N13 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [3]) );
DFFSR \qos/srv_cnt0_d_reg[4] ( .D(\qos/N14 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [4]) );
DFFSR \qos/srv_cnt0_d_reg[5] ( .D(\qos/N15 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [5]) );
DFFSR \qos/srv_cnt0_d_reg[6] ( .D(\qos/N16 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [6]) );
DFFSR \qos/srv_cnt0_d_reg[7] ( .D(\qos/N17 ), .CLK(\clks.clk ), .R(
\clks.rst ), .S(1'b1), .Q(\qos/srv_cnt0_d [7]) );
OR2X1 U469 ( .A(n788), .B(n566), .Y(n786) );
OR2X1 U470 ( .A(n586), .B(n745), .Y(n756) );
AND2X1 U471 ( .A(n590), .B(n410), .Y(n790) );
INVX2 U472 ( .A(n432), .Y(n1074) );
BUFX2 U473 ( .A(n1075), .Y(n728) );
INVX4 U474 ( .A(n411), .Y(n822) );
AND2X2 U475 ( .A(arb_nxt), .B(\qos/queue_gnt_q [0]), .Y(n565) );
AND2X2 U476 ( .A(n589), .B(n415), .Y(n779) );
INVX2 U477 ( .A(n782), .Y(n843) );
OR2X1 U478 ( .A(n423), .B(n766), .Y(n765) );
OR2X1 U479 ( .A(n559), .B(n578), .Y(n797) );
AND2X1 U480 ( .A(n710), .B(crcfifo1_empty), .Y(n738) );
INVX1 U481 ( .A(n778), .Y(n835) );
INVX1 U482 ( .A(n780), .Y(n827) );
INVX1 U483 ( .A(n820), .Y(n413) );
INVX1 U484 ( .A(n821), .Y(n412) );
AND2X1 U485 ( .A(n846), .B(n822), .Y(\qos/N17 ) );
AND2X1 U486 ( .A(n845), .B(n822), .Y(\qos/N16 ) );
AND2X1 U487 ( .A(n419), .B(n822), .Y(\qos/N15 ) );
AND2X1 U488 ( .A(n843), .B(n822), .Y(\qos/N14 ) );
AND2X1 U489 ( .A(n575), .B(n822), .Y(\qos/N13 ) );
AND2X1 U490 ( .A(n841), .B(n822), .Y(\qos/N12 ) );
AND2X1 U491 ( .A(n568), .B(n822), .Y(\qos/N11 ) );
AND2X1 U492 ( .A(n717), .B(n822), .Y(\qos/N10 ) );
AND2X1 U493 ( .A(n573), .B(n757), .Y(n747) );
AND2X1 U494 ( .A(n838), .B(n822), .Y(\qos/N25 ) );
AND2X1 U495 ( .A(n837), .B(n822), .Y(\qos/N24 ) );
AND2X1 U496 ( .A(n716), .B(n822), .Y(\qos/N23 ) );
AND2X1 U497 ( .A(n835), .B(n822), .Y(\qos/N22 ) );
AND2X1 U498 ( .A(n715), .B(n822), .Y(\qos/N21 ) );
AND2X1 U499 ( .A(n596), .B(n822), .Y(\qos/N20 ) );
AND2X1 U500 ( .A(n832), .B(n822), .Y(\qos/N19 ) );
AND2X1 U501 ( .A(n831), .B(n822), .Y(\qos/N18 ) );
AND2X1 U502 ( .A(n830), .B(n822), .Y(\qos/N33 ) );
AND2X1 U503 ( .A(n829), .B(n822), .Y(\qos/N32 ) );
AND2X1 U504 ( .A(n592), .B(n822), .Y(\qos/N31 ) );
AND2X1 U505 ( .A(n827), .B(n822), .Y(\qos/N30 ) );
AND2X1 U506 ( .A(n593), .B(n822), .Y(\qos/N29 ) );
AND2X1 U507 ( .A(n825), .B(n822), .Y(\qos/N28 ) );
AND2X1 U508 ( .A(n824), .B(n822), .Y(\qos/N27 ) );
AND2X1 U509 ( .A(n574), .B(n822), .Y(\qos/N26 ) );
OR2X1 U510 ( .A(n556), .B(n579), .Y(n799) );
OR2X1 U511 ( .A(n554), .B(n577), .Y(n792) );
AND2X1 U512 ( .A(n712), .B(n581), .Y(n781) );
AND2X1 U513 ( .A(n553), .B(n760), .Y(n784) );
AND2X1 U514 ( .A(n721), .B(n767), .Y(n760) );
OR2X1 U515 ( .A(n785), .B(n572), .Y(n783) );
OR2X1 U516 ( .A(n791), .B(n576), .Y(n789) );
AND2X1 U517 ( .A(n711), .B(n416), .Y(n767) );
AND2X1 U518 ( .A(n714), .B(n774), .Y(n787) );
AND2X1 U519 ( .A(n718), .B(n763), .Y(n774) );
INVX1 U520 ( .A(n739), .Y(n586) );
INVX1 U521 ( .A(arb_nxt), .Y(n848) );
INVX1 U522 ( .A(n797), .Y(n713) );
INVX1 U523 ( .A(n799), .Y(n595) );
INVX1 U524 ( .A(n789), .Y(n581) );
AND2X1 U525 ( .A(n428), .B(n420), .Y(n410) );
INVX1 U526 ( .A(n819), .Y(n414) );
NOR3X1 U527 ( .A(n412), .B(n413), .C(n414), .Y(n411) );
INVX1 U528 ( .A(n786), .Y(n415) );
BUFX2 U529 ( .A(n564), .Y(n416) );
BUFX2 U530 ( .A(n740), .Y(n417) );
BUFX2 U531 ( .A(n849), .Y(n418) );
BUFX2 U532 ( .A(n844), .Y(n419) );
INVX1 U533 ( .A(n765), .Y(n420) );
BUFX2 U534 ( .A(n744), .Y(n421) );
INVX1 U535 ( .A(n747), .Y(n422) );
INVX1 U536 ( .A(n565), .Y(n423) );
INVX1 U537 ( .A(n738), .Y(n424) );
BUFX2 U538 ( .A(n748), .Y(n425) );
BUFX2 U539 ( .A(n741), .Y(n426) );
BUFX2 U540 ( .A(n749), .Y(n427) );
AND2X1 U541 ( .A(n569), .B(n757), .Y(n847) );
BUFX2 U542 ( .A(\qos/srv_cnt0_d [1]), .Y(n428) );
BUFX2 U543 ( .A(\qos/srv_cnt0_d [0]), .Y(n429) );
BUFX2 U544 ( .A(\qos/srv_cnt1_d [3]), .Y(n430) );
BUFX2 U545 ( .A(\qos/srv_cnt2_d [3]), .Y(n431) );
BUFX2 U546 ( .A(n726), .Y(n432) );
AND2X1 U547 ( .A(n807), .B(n808), .Y(n724) );
INVX1 U548 ( .A(n850), .Y(n433) );
AND2X1 U549 ( .A(n728), .B(pfifo_datain_ctrl_0[0]), .Y(n850) );
INVX1 U550 ( .A(n852), .Y(n434) );
AND2X1 U551 ( .A(n728), .B(pfifo_datain_ctrl_0[1]), .Y(n852) );
INVX1 U552 ( .A(n854), .Y(n435) );
AND2X1 U553 ( .A(n728), .B(pfifo_datain_ctrl_0[2]), .Y(n854) );
INVX1 U554 ( .A(n856), .Y(n436) );
AND2X1 U555 ( .A(n728), .B(pfifo_datain_ctrl_0[3]), .Y(n856) );
INVX1 U556 ( .A(n858), .Y(n437) );
AND2X1 U557 ( .A(n728), .B(pfifo_datain_ctrl_0[4]), .Y(n858) );
INVX1 U558 ( .A(n860), .Y(n438) );
AND2X1 U559 ( .A(n728), .B(pfifo_datain_ctrl_0[5]), .Y(n860) );
INVX1 U560 ( .A(n862), .Y(n439) );
AND2X1 U561 ( .A(n728), .B(pfifo_datain_ctrl_0[6]), .Y(n862) );
INVX1 U562 ( .A(n864), .Y(n440) );
AND2X1 U563 ( .A(n728), .B(pfifo_datain_ctrl_0[7]), .Y(n864) );
INVX1 U564 ( .A(n866), .Y(n441) );
AND2X1 U565 ( .A(n728), .B(pfifo_datain_ctrl_0[8]), .Y(n866) );
INVX1 U566 ( .A(n868), .Y(n442) );
AND2X1 U567 ( .A(n728), .B(pfifo_datain_ctrl_0[9]), .Y(n868) );
INVX1 U568 ( .A(n870), .Y(n443) );
AND2X1 U569 ( .A(n728), .B(pfifo_datain_ctrl_0[10]), .Y(n870) );
INVX1 U570 ( .A(n872), .Y(n444) );
AND2X1 U571 ( .A(n728), .B(pfifo_datain_ctrl_0[11]), .Y(n872) );
INVX1 U572 ( .A(n874), .Y(n445) );
AND2X1 U573 ( .A(n728), .B(pfifo_datain_ctrl_0[12]), .Y(n874) );
INVX1 U574 ( .A(n876), .Y(n446) );
AND2X1 U575 ( .A(n728), .B(pfifo_datain_ctrl_0[13]), .Y(n876) );
INVX1 U576 ( .A(n878), .Y(n447) );
AND2X1 U577 ( .A(n728), .B(pfifo_datain_ctrl_0[14]), .Y(n878) );
INVX1 U578 ( .A(n880), .Y(n448) );
AND2X1 U579 ( .A(n728), .B(pfifo_datain_ctrl_0[15]), .Y(n880) );
INVX1 U580 ( .A(n882), .Y(n449) );
AND2X1 U581 ( .A(n728), .B(crcfifo0_dataout[0]), .Y(n882) );
INVX1 U582 ( .A(n884), .Y(n450) );
AND2X1 U583 ( .A(n728), .B(crcfifo0_dataout[1]), .Y(n884) );
INVX1 U584 ( .A(n886), .Y(n451) );
AND2X1 U585 ( .A(n728), .B(crcfifo0_dataout[2]), .Y(n886) );
INVX1 U586 ( .A(n888), .Y(n452) );
AND2X1 U587 ( .A(n728), .B(crcfifo0_dataout[3]), .Y(n888) );
INVX1 U588 ( .A(n890), .Y(n453) );
AND2X1 U589 ( .A(n728), .B(crcfifo0_dataout[4]), .Y(n890) );
INVX1 U590 ( .A(n892), .Y(n454) );
AND2X1 U591 ( .A(n728), .B(crcfifo0_dataout[5]), .Y(n892) );
INVX1 U592 ( .A(n894), .Y(n455) );
AND2X1 U593 ( .A(n728), .B(crcfifo0_dataout[6]), .Y(n894) );
INVX1 U594 ( .A(n896), .Y(n456) );
AND2X1 U595 ( .A(n728), .B(crcfifo0_dataout[7]), .Y(n896) );
INVX1 U596 ( .A(n898), .Y(n457) );
AND2X1 U597 ( .A(n728), .B(crcfifo0_dataout[8]), .Y(n898) );
AND2X1 U598 ( .A(n1075), .B(crcfifo0_dataout[9]), .Y(n900) );
INVX1 U599 ( .A(n900), .Y(n458) );
AND2X1 U600 ( .A(n1075), .B(crcfifo0_dataout[10]), .Y(n902) );
INVX1 U601 ( .A(n902), .Y(n459) );
AND2X2 U602 ( .A(n1075), .B(crcfifo0_dataout[11]), .Y(n904) );
INVX1 U603 ( .A(n904), .Y(n460) );
AND2X1 U604 ( .A(n1075), .B(crcfifo0_dataout[12]), .Y(n906) );
INVX1 U605 ( .A(n906), .Y(n461) );
AND2X2 U606 ( .A(n1075), .B(crcfifo0_dataout[13]), .Y(n908) );
INVX1 U607 ( .A(n908), .Y(n462) );
AND2X1 U608 ( .A(n1075), .B(crcfifo0_dataout[14]), .Y(n910) );
INVX1 U609 ( .A(n910), .Y(n463) );
AND2X1 U610 ( .A(n1075), .B(crcfifo0_dataout[15]), .Y(n912) );
INVX1 U611 ( .A(n912), .Y(n464) );
AND2X2 U612 ( .A(n1075), .B(crcfifo0_dataout[16]), .Y(n914) );
INVX1 U613 ( .A(n914), .Y(n465) );
AND2X1 U614 ( .A(n1075), .B(crcfifo0_dataout[17]), .Y(n916) );
INVX1 U615 ( .A(n916), .Y(n466) );
AND2X1 U616 ( .A(n1075), .B(crcfifo0_dataout[18]), .Y(n918) );
INVX1 U617 ( .A(n918), .Y(n467) );
AND2X2 U618 ( .A(n1075), .B(crcfifo0_dataout[19]), .Y(n920) );
INVX1 U619 ( .A(n920), .Y(n468) );
INVX1 U620 ( .A(n922), .Y(n469) );
AND2X1 U621 ( .A(n728), .B(crcfifo0_dataout[20]), .Y(n922) );
INVX1 U622 ( .A(n924), .Y(n470) );
AND2X1 U623 ( .A(n728), .B(crcfifo0_dataout[21]), .Y(n924) );
INVX1 U624 ( .A(n926), .Y(n471) );
AND2X1 U625 ( .A(n728), .B(crcfifo0_dataout[22]), .Y(n926) );
AND2X1 U626 ( .A(n1075), .B(crcfifo0_dataout[23]), .Y(n928) );
INVX1 U627 ( .A(n928), .Y(n472) );
AND2X2 U628 ( .A(n1075), .B(crcfifo0_dataout[24]), .Y(n930) );
INVX1 U629 ( .A(n930), .Y(n473) );
AND2X1 U630 ( .A(n1075), .B(crcfifo0_dataout[25]), .Y(n932) );
INVX1 U631 ( .A(n932), .Y(n474) );
AND2X1 U632 ( .A(n1075), .B(crcfifo0_dataout[26]), .Y(n934) );
INVX1 U633 ( .A(n934), .Y(n475) );
AND2X2 U634 ( .A(n1075), .B(crcfifo0_dataout[27]), .Y(n936) );
INVX1 U635 ( .A(n936), .Y(n476) );
AND2X1 U636 ( .A(n1075), .B(crcfifo0_dataout[28]), .Y(n938) );
INVX1 U637 ( .A(n938), .Y(n477) );
AND2X1 U638 ( .A(n1075), .B(crcfifo0_dataout[29]), .Y(n940) );
INVX1 U639 ( .A(n940), .Y(n478) );
AND2X2 U640 ( .A(n1075), .B(crcfifo0_dataout[30]), .Y(n942) );
INVX1 U641 ( .A(n942), .Y(n479) );
AND2X1 U642 ( .A(n1075), .B(crcfifo0_dataout[31]), .Y(n944) );
INVX1 U643 ( .A(n944), .Y(n480) );
AND2X1 U644 ( .A(n1075), .B(pfifo_datain0[0]), .Y(n946) );
INVX1 U645 ( .A(n946), .Y(n481) );
AND2X2 U646 ( .A(n1075), .B(pfifo_datain0[1]), .Y(n948) );
INVX1 U647 ( .A(n948), .Y(n482) );
AND2X1 U648 ( .A(n1075), .B(pfifo_datain0[2]), .Y(n950) );
INVX1 U649 ( .A(n950), .Y(n483) );
AND2X2 U650 ( .A(n1075), .B(pfifo_datain0[3]), .Y(n952) );
INVX1 U651 ( .A(n952), .Y(n484) );
INVX1 U652 ( .A(n954), .Y(n485) );
AND2X1 U653 ( .A(n728), .B(pfifo_datain0[4]), .Y(n954) );
INVX1 U654 ( .A(n956), .Y(n486) );
AND2X1 U655 ( .A(n728), .B(pfifo_datain0[5]), .Y(n956) );
INVX1 U656 ( .A(n958), .Y(n487) );
AND2X1 U657 ( .A(n728), .B(pfifo_datain0[6]), .Y(n958) );
INVX1 U658 ( .A(n960), .Y(n488) );
AND2X1 U659 ( .A(n728), .B(pfifo_datain0[7]), .Y(n960) );
INVX1 U660 ( .A(n962), .Y(n489) );
AND2X1 U661 ( .A(n728), .B(pfifo_datain0[8]), .Y(n962) );
INVX1 U662 ( .A(n964), .Y(n490) );
AND2X1 U663 ( .A(n728), .B(pfifo_datain0[9]), .Y(n964) );
INVX1 U664 ( .A(n966), .Y(n491) );
AND2X1 U665 ( .A(n728), .B(pfifo_datain0[10]), .Y(n966) );
INVX1 U666 ( .A(n968), .Y(n492) );
AND2X1 U667 ( .A(n728), .B(pfifo_datain0[11]), .Y(n968) );
INVX1 U668 ( .A(n970), .Y(n493) );
AND2X1 U669 ( .A(n728), .B(pfifo_datain0[12]), .Y(n970) );
INVX1 U670 ( .A(n972), .Y(n494) );
AND2X1 U671 ( .A(n728), .B(pfifo_datain0[13]), .Y(n972) );
INVX1 U672 ( .A(n974), .Y(n495) );
AND2X1 U673 ( .A(n728), .B(pfifo_datain0[14]), .Y(n974) );
INVX1 U674 ( .A(n976), .Y(n496) );
AND2X1 U675 ( .A(n728), .B(pfifo_datain0[15]), .Y(n976) );
INVX1 U676 ( .A(n978), .Y(n497) );
AND2X1 U677 ( .A(n728), .B(pfifo_datain0[16]), .Y(n978) );
INVX1 U678 ( .A(n980), .Y(n498) );
AND2X1 U679 ( .A(n728), .B(pfifo_datain0[17]), .Y(n980) );
INVX1 U680 ( .A(n982), .Y(n499) );
AND2X1 U681 ( .A(n728), .B(pfifo_datain0[18]), .Y(n982) );
AND2X1 U682 ( .A(n1075), .B(pfifo_datain0[19]), .Y(n984) );
INVX1 U683 ( .A(n984), .Y(n500) );
AND2X1 U684 ( .A(n1075), .B(pfifo_datain0[20]), .Y(n986) );
INVX1 U685 ( .A(n986), .Y(n501) );
AND2X2 U686 ( .A(n1075), .B(pfifo_datain0[21]), .Y(n988) );
INVX1 U687 ( .A(n988), .Y(n502) );
AND2X1 U688 ( .A(n1075), .B(pfifo_datain0[22]), .Y(n990) );
INVX1 U689 ( .A(n990), .Y(n503) );
AND2X1 U690 ( .A(n1075), .B(pfifo_datain0[23]), .Y(n992) );
INVX1 U691 ( .A(n992), .Y(n504) );
AND2X2 U692 ( .A(n1075), .B(pfifo_datain0[24]), .Y(n994) );
INVX1 U693 ( .A(n994), .Y(n505) );
AND2X1 U694 ( .A(n1075), .B(pfifo_datain0[25]), .Y(n996) );
INVX1 U695 ( .A(n996), .Y(n506) );
AND2X1 U696 ( .A(n1075), .B(pfifo_datain0[26]), .Y(n998) );
INVX1 U697 ( .A(n998), .Y(n507) );
AND2X2 U698 ( .A(n1075), .B(pfifo_datain0[27]), .Y(n1000) );
INVX1 U699 ( .A(n1000), .Y(n508) );
AND2X1 U700 ( .A(n1075), .B(pfifo_datain0[28]), .Y(n1002) );
INVX1 U701 ( .A(n1002), .Y(n509) );
AND2X2 U702 ( .A(n1075), .B(pfifo_datain0[29]), .Y(n1004) );
INVX1 U703 ( .A(n1004), .Y(n510) );
AND2X1 U704 ( .A(n1075), .B(pfifo_datain0[30]), .Y(n1006) );
INVX1 U705 ( .A(n1006), .Y(n511) );
AND2X1 U706 ( .A(n1075), .B(pfifo_datain0[31]), .Y(n1008) );
INVX1 U707 ( .A(n1008), .Y(n512) );
AND2X2 U708 ( .A(n1075), .B(pfifo_datain0[32]), .Y(n1010) );
INVX1 U709 ( .A(n1010), .Y(n513) );
AND2X1 U710 ( .A(n1075), .B(pfifo_datain0[33]), .Y(n1012) );
INVX1 U711 ( .A(n1012), .Y(n514) );
AND2X1 U712 ( .A(n1075), .B(pfifo_datain0[34]), .Y(n1014) );
INVX1 U713 ( .A(n1014), .Y(n515) );
AND2X2 U714 ( .A(n1075), .B(pfifo_datain0[35]), .Y(n1016) );
INVX1 U715 ( .A(n1016), .Y(n516) );
AND2X1 U716 ( .A(n1075), .B(pfifo_datain0[36]), .Y(n1018) );
INVX1 U717 ( .A(n1018), .Y(n517) );
INVX1 U718 ( .A(n1020), .Y(n518) );
AND2X1 U719 ( .A(n728), .B(pfifo_datain0[37]), .Y(n1020) );
INVX1 U720 ( .A(n1022), .Y(n519) );
AND2X1 U721 ( .A(n728), .B(pfifo_datain0[38]), .Y(n1022) );
INVX1 U722 ( .A(n1024), .Y(n520) );
AND2X1 U723 ( .A(n728), .B(pfifo_datain0[39]), .Y(n1024) );
INVX1 U724 ( .A(n1026), .Y(n521) );
AND2X1 U725 ( .A(n728), .B(pfifo_datain0[40]), .Y(n1026) );
INVX1 U726 ( .A(n1028), .Y(n522) );
AND2X1 U727 ( .A(n728), .B(pfifo_datain0[41]), .Y(n1028) );
INVX1 U728 ( .A(n1030), .Y(n523) );
AND2X1 U729 ( .A(n728), .B(pfifo_datain0[42]), .Y(n1030) );
INVX1 U730 ( .A(n1032), .Y(n524) );
AND2X1 U731 ( .A(n728), .B(pfifo_datain0[43]), .Y(n1032) );
INVX1 U732 ( .A(n1034), .Y(n525) );
AND2X1 U733 ( .A(n728), .B(pfifo_datain0[44]), .Y(n1034) );
INVX1 U734 ( .A(n1036), .Y(n526) );
AND2X1 U735 ( .A(n728), .B(pfifo_datain0[45]), .Y(n1036) );
INVX1 U736 ( .A(n1038), .Y(n527) );
AND2X1 U737 ( .A(n728), .B(pfifo_datain0[46]), .Y(n1038) );
INVX1 U738 ( .A(n1040), .Y(n528) );
AND2X1 U739 ( .A(n728), .B(pfifo_datain0[47]), .Y(n1040) );
INVX1 U740 ( .A(n1042), .Y(n529) );
AND2X1 U741 ( .A(n728), .B(pfifo_datain0[48]), .Y(n1042) );
INVX1 U742 ( .A(n1044), .Y(n530) );
AND2X1 U743 ( .A(n728), .B(pfifo_datain0[49]), .Y(n1044) );
INVX1 U744 ( .A(n1046), .Y(n531) );
AND2X1 U745 ( .A(n728), .B(pfifo_datain0[50]), .Y(n1046) );
INVX1 U746 ( .A(n1049), .Y(n532) );
AND2X1 U747 ( .A(n728), .B(pfifo_datain0[51]), .Y(n1049) );
INVX1 U748 ( .A(n1051), .Y(n533) );
AND2X1 U749 ( .A(n728), .B(pfifo_datain0[52]), .Y(n1051) );
INVX1 U750 ( .A(n1053), .Y(n534) );
AND2X1 U751 ( .A(n728), .B(pfifo_datain0[53]), .Y(n1053) );
INVX1 U752 ( .A(n1055), .Y(n535) );
AND2X1 U753 ( .A(n728), .B(pfifo_datain0[54]), .Y(n1055) );
INVX1 U754 ( .A(n1057), .Y(n536) );
AND2X1 U755 ( .A(n728), .B(pfifo_datain0[55]), .Y(n1057) );
INVX1 U756 ( .A(n1059), .Y(n537) );
AND2X1 U757 ( .A(n728), .B(pfifo_datain0[56]), .Y(n1059) );
INVX1 U758 ( .A(n1061), .Y(n538) );
AND2X1 U759 ( .A(n728), .B(pfifo_datain0[57]), .Y(n1061) );
INVX1 U760 ( .A(n1063), .Y(n539) );
AND2X1 U761 ( .A(n728), .B(pfifo_datain0[58]), .Y(n1063) );
INVX1 U762 ( .A(n1065), .Y(n540) );
AND2X1 U763 ( .A(n728), .B(pfifo_datain0[59]), .Y(n1065) );
INVX1 U764 ( .A(n1067), .Y(n541) );
AND2X1 U765 ( .A(n728), .B(pfifo_datain0[60]), .Y(n1067) );
AND2X2 U766 ( .A(n1075), .B(pfifo_datain0[61]), .Y(n1069) );
INVX1 U767 ( .A(n1069), .Y(n542) );
AND2X1 U768 ( .A(n1075), .B(pfifo_datain0[62]), .Y(n1071) );
INVX1 U769 ( .A(n1071), .Y(n543) );
AND2X1 U770 ( .A(n1075), .B(pfifo_datain0[63]), .Y(n1076) );
INVX1 U771 ( .A(n1076), .Y(n544) );
INVX1 U772 ( .A(n750), .Y(n545) );
AND2X1 U773 ( .A(arb_nxt), .B(\qos/queue_gnt_q [2]), .Y(n750) );
BUFX2 U774 ( .A(n730), .Y(n546) );
BUFX2 U775 ( .A(n735), .Y(n547) );
INVX1 U776 ( .A(n816), .Y(n548) );
AND2X1 U777 ( .A(n815), .B(n814), .Y(n816) );
INVX1 U778 ( .A(n793), .Y(n549) );
AND2X1 U779 ( .A(n720), .B(n594), .Y(n793) );
INVX1 U780 ( .A(n798), .Y(n550) );
AND2X1 U781 ( .A(n571), .B(n713), .Y(n798) );
INVX1 U782 ( .A(n800), .Y(n551) );
AND2X1 U783 ( .A(n719), .B(n595), .Y(n800) );
INVX1 U784 ( .A(n767), .Y(n552) );
BUFX2 U785 ( .A(\qos/srv_cnt1_d [2]), .Y(n553) );
INVX1 U786 ( .A(n555), .Y(n554) );
BUFX2 U787 ( .A(\qos/srv_cnt1_d [5]), .Y(n555) );
INVX1 U788 ( .A(n557), .Y(n556) );
BUFX2 U789 ( .A(\qos/srv_cnt0_d [5]), .Y(n557) );
BUFX2 U790 ( .A(\qos/srv_cnt0_d [3]), .Y(n558) );
INVX1 U791 ( .A(n560), .Y(n559) );
BUFX2 U792 ( .A(\qos/srv_cnt2_d [5]), .Y(n560) );
BUFX2 U793 ( .A(\qos/srv_cnt2_d [0]), .Y(n561) );
INVX1 U794 ( .A(n760), .Y(n562) );
INVX1 U795 ( .A(n774), .Y(n563) );
AOI21X1 U796 ( .A(n418), .B(n709), .C(n848), .Y(n564) );
INVX1 U797 ( .A(n787), .Y(n566) );
INVX1 U798 ( .A(n752), .Y(n567) );
AND2X1 U799 ( .A(crcfifo1_empty), .B(crcfifo2_empty), .Y(n752) );
BUFX2 U800 ( .A(n840), .Y(n568) );
BUFX2 U801 ( .A(buffer_sel[1]), .Y(n569) );
INVX1 U802 ( .A(n571), .Y(n570) );
BUFX2 U803 ( .A(\qos/srv_cnt2_d [6]), .Y(n571) );
INVX1 U804 ( .A(n784), .Y(n572) );
BUFX2 U805 ( .A(buffer_sel[0]), .Y(n573) );
BUFX2 U806 ( .A(n823), .Y(n574) );
BUFX2 U807 ( .A(n842), .Y(n575) );
INVX1 U808 ( .A(n790), .Y(n576) );
AND2X1 U809 ( .A(n591), .B(n580), .Y(n777) );
INVX1 U810 ( .A(n777), .Y(n577) );
INVX1 U811 ( .A(n779), .Y(n578) );
INVX1 U812 ( .A(n781), .Y(n579) );
INVX1 U813 ( .A(n783), .Y(n580) );
INVX1 U814 ( .A(n583), .Y(n582) );
BUFX2 U815 ( .A(\qos/srv_cnt1_d [7]), .Y(n583) );
INVX1 U816 ( .A(n585), .Y(n584) );
BUFX2 U817 ( .A(\qos/srv_cnt2_d [7]), .Y(n585) );
OR2X1 U818 ( .A(n743), .B(n737), .Y(n739) );
INVX1 U819 ( .A(n588), .Y(n587) );
BUFX2 U820 ( .A(\qos/srv_cnt0_d [7]), .Y(n588) );
BUFX2 U821 ( .A(\qos/srv_cnt2_d [4]), .Y(n589) );
BUFX2 U822 ( .A(\qos/srv_cnt0_d [2]), .Y(n590) );
BUFX2 U823 ( .A(\qos/srv_cnt1_d [4]), .Y(n591) );
BUFX2 U824 ( .A(n828), .Y(n592) );
BUFX2 U825 ( .A(n826), .Y(n593) );
INVX1 U826 ( .A(n792), .Y(n594) );
BUFX2 U827 ( .A(n833), .Y(n596) );
BUFX2 U828 ( .A(n1077), .Y(n597) );
BUFX2 U829 ( .A(n1072), .Y(n598) );
BUFX2 U830 ( .A(n1070), .Y(n599) );
BUFX2 U831 ( .A(n1068), .Y(n600) );
BUFX2 U832 ( .A(n1066), .Y(n601) );
BUFX2 U833 ( .A(n1064), .Y(n602) );
BUFX2 U834 ( .A(n1062), .Y(n603) );
BUFX2 U835 ( .A(n1060), .Y(n604) );
BUFX2 U836 ( .A(n1058), .Y(n605) );
BUFX2 U837 ( .A(n1056), .Y(n606) );
BUFX2 U838 ( .A(n1054), .Y(n607) );
BUFX2 U839 ( .A(n1052), .Y(n608) );
BUFX2 U840 ( .A(n1050), .Y(n609) );
BUFX2 U841 ( .A(n1047), .Y(n610) );
BUFX2 U842 ( .A(n1045), .Y(n611) );
BUFX2 U843 ( .A(n1043), .Y(n612) );
BUFX2 U844 ( .A(n1041), .Y(n613) );
BUFX2 U845 ( .A(n1039), .Y(n614) );
BUFX2 U846 ( .A(n1037), .Y(n615) );
BUFX2 U847 ( .A(n1035), .Y(n616) );
BUFX2 U848 ( .A(n1033), .Y(n617) );
BUFX2 U849 ( .A(n1031), .Y(n618) );
BUFX2 U850 ( .A(n1029), .Y(n619) );
BUFX2 U851 ( .A(n1027), .Y(n620) );
BUFX2 U852 ( .A(n1025), .Y(n621) );
BUFX2 U853 ( .A(n1023), .Y(n622) );
BUFX2 U854 ( .A(n1021), .Y(n623) );
BUFX2 U855 ( .A(n1019), .Y(n624) );
BUFX2 U856 ( .A(n1017), .Y(n625) );
BUFX2 U857 ( .A(n1015), .Y(n626) );
BUFX2 U858 ( .A(n1013), .Y(n627) );
BUFX2 U859 ( .A(n1011), .Y(n628) );
BUFX2 U860 ( .A(n1009), .Y(n629) );
BUFX2 U861 ( .A(n1007), .Y(n630) );
BUFX2 U862 ( .A(n1005), .Y(n631) );
BUFX2 U863 ( .A(n1003), .Y(n632) );
BUFX2 U864 ( .A(n1001), .Y(n633) );
BUFX2 U865 ( .A(n999), .Y(n634) );
BUFX2 U866 ( .A(n997), .Y(n635) );
BUFX2 U867 ( .A(n995), .Y(n636) );
BUFX2 U868 ( .A(n993), .Y(n637) );
BUFX2 U869 ( .A(n991), .Y(n638) );
BUFX2 U870 ( .A(n989), .Y(n639) );
BUFX2 U871 ( .A(n987), .Y(n640) );
BUFX2 U872 ( .A(n985), .Y(n641) );
BUFX2 U873 ( .A(n983), .Y(n642) );
BUFX2 U874 ( .A(n981), .Y(n643) );
BUFX2 U875 ( .A(n979), .Y(n644) );
BUFX2 U876 ( .A(n977), .Y(n645) );
BUFX2 U877 ( .A(n975), .Y(n646) );
BUFX2 U878 ( .A(n973), .Y(n647) );
BUFX2 U879 ( .A(n971), .Y(n648) );
BUFX2 U880 ( .A(n969), .Y(n649) );
BUFX2 U881 ( .A(n967), .Y(n650) );
BUFX2 U882 ( .A(n965), .Y(n651) );
BUFX2 U883 ( .A(n963), .Y(n652) );
BUFX2 U884 ( .A(n961), .Y(n653) );
BUFX2 U885 ( .A(n959), .Y(n654) );
BUFX2 U886 ( .A(n957), .Y(n655) );
BUFX2 U887 ( .A(n955), .Y(n656) );
BUFX2 U888 ( .A(n953), .Y(n657) );
BUFX2 U889 ( .A(n951), .Y(n658) );
BUFX2 U890 ( .A(n949), .Y(n659) );
BUFX2 U891 ( .A(n947), .Y(n660) );
BUFX2 U892 ( .A(n881), .Y(n661) );
BUFX2 U893 ( .A(n879), .Y(n662) );
BUFX2 U894 ( .A(n877), .Y(n663) );
BUFX2 U895 ( .A(n875), .Y(n664) );
BUFX2 U896 ( .A(n873), .Y(n665) );
BUFX2 U897 ( .A(n871), .Y(n666) );
BUFX2 U898 ( .A(n869), .Y(n667) );
BUFX2 U899 ( .A(n867), .Y(n668) );
BUFX2 U900 ( .A(n865), .Y(n669) );
BUFX2 U901 ( .A(n863), .Y(n670) );
BUFX2 U902 ( .A(n861), .Y(n671) );
BUFX2 U903 ( .A(n859), .Y(n672) );
BUFX2 U904 ( .A(n857), .Y(n673) );
BUFX2 U905 ( .A(n855), .Y(n674) );
BUFX2 U906 ( .A(n853), .Y(n675) );
BUFX2 U907 ( .A(n851), .Y(n676) );
BUFX2 U908 ( .A(n945), .Y(n677) );
BUFX2 U909 ( .A(n943), .Y(n678) );
BUFX2 U910 ( .A(n941), .Y(n679) );
BUFX2 U911 ( .A(n939), .Y(n680) );
BUFX2 U912 ( .A(n937), .Y(n681) );
BUFX2 U913 ( .A(n935), .Y(n682) );
BUFX2 U914 ( .A(n933), .Y(n683) );
BUFX2 U915 ( .A(n931), .Y(n684) );
BUFX2 U916 ( .A(n929), .Y(n685) );
BUFX2 U917 ( .A(n927), .Y(n686) );
BUFX2 U918 ( .A(n925), .Y(n687) );
BUFX2 U919 ( .A(n923), .Y(n688) );
BUFX2 U920 ( .A(n921), .Y(n689) );
BUFX2 U921 ( .A(n919), .Y(n690) );
BUFX2 U922 ( .A(n917), .Y(n691) );
BUFX2 U923 ( .A(n915), .Y(n692) );
BUFX2 U924 ( .A(n913), .Y(n693) );
BUFX2 U925 ( .A(n911), .Y(n694) );
BUFX2 U926 ( .A(n909), .Y(n695) );
BUFX2 U927 ( .A(n907), .Y(n696) );
BUFX2 U928 ( .A(n905), .Y(n697) );
BUFX2 U929 ( .A(n903), .Y(n698) );
BUFX2 U930 ( .A(n901), .Y(n699) );
BUFX2 U931 ( .A(n899), .Y(n700) );
BUFX2 U932 ( .A(n897), .Y(n701) );
BUFX2 U933 ( .A(n895), .Y(n702) );
BUFX2 U934 ( .A(n893), .Y(n703) );
BUFX2 U935 ( .A(n891), .Y(n704) );
BUFX2 U936 ( .A(n889), .Y(n705) );
BUFX2 U937 ( .A(n887), .Y(n706) );
BUFX2 U938 ( .A(n885), .Y(n707) );
BUFX2 U939 ( .A(n883), .Y(n708) );
INVX1 U940 ( .A(n847), .Y(n709) );
INVX1 U941 ( .A(n756), .Y(n710) );
BUFX2 U942 ( .A(\qos/srv_cnt1_d [0]), .Y(n711) );
BUFX2 U943 ( .A(\qos/srv_cnt0_d [4]), .Y(n712) );
BUFX2 U944 ( .A(\qos/srv_cnt2_d [2]), .Y(n714) );
BUFX2 U945 ( .A(n834), .Y(n715) );
BUFX2 U946 ( .A(n836), .Y(n716) );
BUFX2 U947 ( .A(n839), .Y(n717) );
BUFX2 U948 ( .A(\qos/srv_cnt2_d [1]), .Y(n718) );
BUFX2 U949 ( .A(\qos/srv_cnt0_d [6]), .Y(n719) );
BUFX2 U950 ( .A(\qos/srv_cnt1_d [6]), .Y(n720) );
BUFX2 U951 ( .A(\qos/srv_cnt1_d [1]), .Y(n721) );
BUFX2 U952 ( .A(n753), .Y(n722) );
BUFX2 U953 ( .A(buffer_sel[2]), .Y(n723) );
XOR2X1 U954 ( .A(n807), .B(n808), .Y(n812) );
INVX1 U955 ( .A(n569), .Y(n725) );
NOR3X1 U956 ( .A(n573), .B(n723), .C(n725), .Y(n1048) );
AND2X1 U957 ( .A(n1048), .B(crcfifo_pop), .Y(crcfifo1_pull) );
AND2X1 U958 ( .A(n1048), .B(pfifo_pop), .Y(pfifo_pop_1) );
INVX1 U959 ( .A(n573), .Y(n727) );
NAND3X1 U960 ( .A(n727), .B(n725), .C(n723), .Y(n726) );
AND2X1 U961 ( .A(n1074), .B(crcfifo_pop), .Y(crcfifo2_pull) );
AND2X1 U962 ( .A(n1074), .B(pfifo_pop), .Y(pfifo_pop_2) );
NOR3X1 U963 ( .A(n723), .B(n569), .C(n727), .Y(n1075) );
AND2X1 U964 ( .A(n728), .B(crcfifo_pop), .Y(crcfifo0_pull) );
AND2X1 U965 ( .A(n728), .B(pfifo_pop), .Y(pfifo_pop_0) );
INVX1 U966 ( .A(crcfifo0_empty), .Y(n742) );
OR2X1 U967 ( .A(n742), .B(n567), .Y(start_transmit) );
NOR3X1 U968 ( .A(n555), .B(n720), .C(n591), .Y(n729) );
INVX1 U969 ( .A(n553), .Y(n761) );
INVX1 U970 ( .A(n430), .Y(n785) );
NAND3X1 U971 ( .A(n729), .B(n761), .C(n785), .Y(n730) );
NOR3X1 U972 ( .A(n583), .B(n721), .C(n546), .Y(n743) );
NOR3X1 U973 ( .A(n712), .B(n558), .C(n588), .Y(n732) );
NOR3X1 U974 ( .A(n719), .B(n557), .C(n590), .Y(n731) );
AND2X1 U975 ( .A(n732), .B(n731), .Y(n737) );
NOR3X1 U976 ( .A(n585), .B(n561), .C(n714), .Y(n734) );
INVX1 U977 ( .A(n718), .Y(n733) );
NAND3X1 U978 ( .A(n586), .B(n734), .C(n733), .Y(n735) );
NOR3X1 U979 ( .A(n589), .B(n560), .C(n547), .Y(n736) );
INVX1 U980 ( .A(n431), .Y(n788) );
NAND3X1 U981 ( .A(n736), .B(n788), .C(n570), .Y(n753) );
AND2X1 U982 ( .A(n742), .B(n737), .Y(n745) );
AOI21X1 U983 ( .A(n722), .B(n424), .C(crcfifo2_empty), .Y(n741) );
AOI21X1 U984 ( .A(n722), .B(n586), .C(n848), .Y(n740) );
INVX1 U985 ( .A(n417), .Y(n757) );
AOI22X1 U986 ( .A(arb_nxt), .B(n426), .C(n723), .D(n757), .Y(n749) );
INVX1 U987 ( .A(n427), .Y(\qos/queue_gnt_q [2]) );
NAND3X1 U988 ( .A(n743), .B(n742), .C(crcfifo1_empty), .Y(n744) );
OAI21X1 U989 ( .A(crcfifo1_empty), .B(n722), .C(n421), .Y(n746) );
AOI21X1 U990 ( .A(n746), .B(crcfifo2_empty), .C(n745), .Y(n748) );
OAI21X1 U991 ( .A(n425), .B(n848), .C(n422), .Y(\qos/queue_gnt_q [0]) );
INVX1 U992 ( .A(n561), .Y(n751) );
NOR3X1 U993 ( .A(n751), .B(n848), .C(n427), .Y(n763) );
AOI21X1 U994 ( .A(n751), .B(n545), .C(n763), .Y(n823) );
INVX1 U995 ( .A(crcfifo1_empty), .Y(n755) );
NOR3X1 U996 ( .A(crcfifo0_empty), .B(n722), .C(n567), .Y(n754) );
AOI21X1 U997 ( .A(n710), .B(n755), .C(n754), .Y(n849) );
OAI21X1 U998 ( .A(n721), .B(n767), .C(n562), .Y(n758) );
INVX1 U999 ( .A(n758), .Y(n832) );
INVX1 U1000 ( .A(n428), .Y(n759) );
INVX1 U1001 ( .A(n429), .Y(n766) );
AOI21X1 U1002 ( .A(n759), .B(n765), .C(n410), .Y(n840) );
AOI21X1 U1003 ( .A(n761), .B(n562), .C(n784), .Y(n833) );
MUX2X1 U1004 ( .B(n563), .A(n774), .S(n714), .Y(n825) );
OAI21X1 U1005 ( .A(n590), .B(n410), .C(n576), .Y(n762) );
INVX1 U1006 ( .A(n762), .Y(n841) );
OAI21X1 U1007 ( .A(n718), .B(n763), .C(n563), .Y(n764) );
INVX1 U1008 ( .A(n764), .Y(n824) );
HAX1 U1009 ( .A(n832), .B(n568), .YC(n771), .YS(n773) );
AOI21X1 U1010 ( .A(n766), .B(n423), .C(n420), .Y(n839) );
OAI21X1 U1011 ( .A(n416), .B(n711), .C(n552), .Y(n768) );
INVX1 U1012 ( .A(n768), .Y(n831) );
FAX1 U1013 ( .A(n771), .B(n770), .C(n769), .YS(n821) );
FAX1 U1014 ( .A(n824), .B(n773), .C(n772), .YC(n769), .YS(n820) );
AOI21X1 U1015 ( .A(n554), .B(n577), .C(n594), .Y(n836) );
AOI21X1 U1016 ( .A(n559), .B(n578), .C(n713), .Y(n828) );
INVX1 U1017 ( .A(n558), .Y(n791) );
AOI21X1 U1018 ( .A(n556), .B(n579), .C(n595), .Y(n844) );
INVX1 U1019 ( .A(n720), .Y(n775) );
MUX2X1 U1020 ( .B(n775), .A(n720), .S(n594), .Y(n837) );
MUX2X1 U1021 ( .B(n570), .A(n571), .S(n713), .Y(n829) );
INVX1 U1022 ( .A(n719), .Y(n776) );
MUX2X1 U1023 ( .B(n776), .A(n719), .S(n595), .Y(n845) );
OAI21X1 U1024 ( .A(n591), .B(n580), .C(n577), .Y(n778) );
OAI21X1 U1025 ( .A(n589), .B(n415), .C(n578), .Y(n780) );
OAI21X1 U1026 ( .A(n712), .B(n581), .C(n579), .Y(n782) );
FAX1 U1027 ( .A(n716), .B(n592), .C(n419), .YC(n796), .YS(n805) );
AOI21X1 U1028 ( .A(n785), .B(n572), .C(n580), .Y(n834) );
AOI21X1 U1029 ( .A(n788), .B(n566), .C(n415), .Y(n826) );
AOI21X1 U1030 ( .A(n791), .B(n576), .C(n581), .Y(n842) );
FAX1 U1031 ( .A(n835), .B(n843), .C(n827), .YC(n806), .YS(n809) );
FAX1 U1032 ( .A(n596), .B(n825), .C(n841), .YC(n808), .YS(n770) );
FAX1 U1033 ( .A(n715), .B(n593), .C(n575), .YC(n810), .YS(n807) );
MUX2X1 U1034 ( .B(n583), .A(n582), .S(n549), .Y(n838) );
FAX1 U1035 ( .A(n796), .B(n795), .C(n794), .YC(n803), .YS(n818) );
FAX1 U1036 ( .A(n837), .B(n829), .C(n845), .YC(n801), .YS(n795) );
MUX2X1 U1037 ( .B(n585), .A(n584), .S(n550), .Y(n830) );
MUX2X1 U1038 ( .B(n588), .A(n587), .S(n551), .Y(n846) );
FAX1 U1039 ( .A(n801), .B(n830), .C(n846), .YS(n802) );
FAX1 U1040 ( .A(n838), .B(n803), .C(n802), .YS(n817) );
FAX1 U1041 ( .A(n717), .B(n831), .C(n574), .YC(n772), .YS(n815) );
FAX1 U1042 ( .A(n806), .B(n805), .C(n804), .YC(n794), .YS(n813) );
FAX1 U1043 ( .A(n810), .B(n809), .C(n724), .YC(n804), .YS(n811) );
NOR3X1 U1044 ( .A(n813), .B(n812), .C(n811), .Y(n814) );
NOR3X1 U1045 ( .A(n818), .B(n817), .C(n548), .Y(n819) );
OAI21X1 U1046 ( .A(n418), .B(n848), .C(n709), .Y(\qos/queue_gnt_q [1]) );
BUFX2 U1047 ( .A(n1048), .Y(n1073) );
AOI22X1 U1048 ( .A(n1074), .B(pfifo_datain_ctrl_2[0]), .C(n1073), .D(
pfifo_datain_ctrl_1[0]), .Y(n851) );
NAND2X1 U1049 ( .A(n676), .B(n433), .Y(pfifo_datain_ctrl[0]) );
AOI22X1 U1050 ( .A(n1074), .B(pfifo_datain_ctrl_2[1]), .C(n1073), .D(
pfifo_datain_ctrl_1[1]), .Y(n853) );
NAND2X1 U1051 ( .A(n675), .B(n434), .Y(pfifo_datain_ctrl[1]) );
AOI22X1 U1052 ( .A(n1074), .B(pfifo_datain_ctrl_2[2]), .C(n1073), .D(
pfifo_datain_ctrl_1[2]), .Y(n855) );
NAND2X1 U1053 ( .A(n674), .B(n435), .Y(pfifo_datain_ctrl[2]) );
AOI22X1 U1054 ( .A(n1074), .B(pfifo_datain_ctrl_2[3]), .C(n1048), .D(
pfifo_datain_ctrl_1[3]), .Y(n857) );
NAND2X1 U1055 ( .A(n673), .B(n436), .Y(pfifo_datain_ctrl[3]) );
AOI22X1 U1056 ( .A(n1074), .B(pfifo_datain_ctrl_2[4]), .C(n1073), .D(
pfifo_datain_ctrl_1[4]), .Y(n859) );
NAND2X1 U1057 ( .A(n672), .B(n437), .Y(pfifo_datain_ctrl[4]) );
AOI22X1 U1058 ( .A(n1074), .B(pfifo_datain_ctrl_2[5]), .C(n1073), .D(
pfifo_datain_ctrl_1[5]), .Y(n861) );
NAND2X1 U1059 ( .A(n671), .B(n438), .Y(pfifo_datain_ctrl[5]) );
AOI22X1 U1060 ( .A(n1074), .B(pfifo_datain_ctrl_2[6]), .C(n1073), .D(
pfifo_datain_ctrl_1[6]), .Y(n863) );
NAND2X1 U1061 ( .A(n670), .B(n439), .Y(pfifo_datain_ctrl[6]) );
AOI22X1 U1062 ( .A(n1074), .B(pfifo_datain_ctrl_2[7]), .C(n1073), .D(
pfifo_datain_ctrl_1[7]), .Y(n865) );
NAND2X1 U1063 ( .A(n669), .B(n440), .Y(pfifo_datain_ctrl[7]) );
AOI22X1 U1064 ( .A(n1074), .B(pfifo_datain_ctrl_2[8]), .C(n1073), .D(
pfifo_datain_ctrl_1[8]), .Y(n867) );
NAND2X1 U1065 ( .A(n668), .B(n441), .Y(pfifo_datain_ctrl[8]) );
AOI22X1 U1066 ( .A(n1074), .B(pfifo_datain_ctrl_2[9]), .C(n1048), .D(
pfifo_datain_ctrl_1[9]), .Y(n869) );
NAND2X1 U1067 ( .A(n667), .B(n442), .Y(pfifo_datain_ctrl[9]) );
AOI22X1 U1068 ( .A(n1074), .B(pfifo_datain_ctrl_2[10]), .C(n1073), .D(
pfifo_datain_ctrl_1[10]), .Y(n871) );
NAND2X1 U1069 ( .A(n666), .B(n443), .Y(pfifo_datain_ctrl[10]) );
AOI22X1 U1070 ( .A(n1074), .B(pfifo_datain_ctrl_2[11]), .C(n1048), .D(
pfifo_datain_ctrl_1[11]), .Y(n873) );
NAND2X1 U1071 ( .A(n665), .B(n444), .Y(pfifo_datain_ctrl[11]) );
AOI22X1 U1072 ( .A(n1074), .B(pfifo_datain_ctrl_2[12]), .C(n1048), .D(
pfifo_datain_ctrl_1[12]), .Y(n875) );
NAND2X1 U1073 ( .A(n664), .B(n445), .Y(pfifo_datain_ctrl[12]) );
AOI22X1 U1074 ( .A(n1074), .B(pfifo_datain_ctrl_2[13]), .C(n1073), .D(
pfifo_datain_ctrl_1[13]), .Y(n877) );
NAND2X1 U1075 ( .A(n663), .B(n446), .Y(pfifo_datain_ctrl[13]) );
AOI22X1 U1076 ( .A(n1074), .B(pfifo_datain_ctrl_2[14]), .C(n1048), .D(
pfifo_datain_ctrl_1[14]), .Y(n879) );
NAND2X1 U1077 ( .A(n662), .B(n447), .Y(pfifo_datain_ctrl[14]) );
AOI22X1 U1078 ( .A(n1074), .B(pfifo_datain_ctrl_2[15]), .C(n1073), .D(
pfifo_datain_ctrl_1[15]), .Y(n881) );
NAND2X1 U1079 ( .A(n661), .B(n448), .Y(pfifo_datain_ctrl[15]) );
AOI22X1 U1080 ( .A(n1074), .B(crcfifo2_dataout[0]), .C(n1048), .D(
crcfifo1_dataout[0]), .Y(n883) );
NAND2X1 U1081 ( .A(n708), .B(n449), .Y(crcfifo_dataout[0]) );
AOI22X1 U1082 ( .A(n1074), .B(crcfifo2_dataout[1]), .C(n1073), .D(
crcfifo1_dataout[1]), .Y(n885) );
NAND2X1 U1083 ( .A(n707), .B(n450), .Y(crcfifo_dataout[1]) );
AOI22X1 U1084 ( .A(n1074), .B(crcfifo2_dataout[2]), .C(n1048), .D(
crcfifo1_dataout[2]), .Y(n887) );
NAND2X1 U1085 ( .A(n706), .B(n451), .Y(crcfifo_dataout[2]) );
AOI22X1 U1086 ( .A(n1074), .B(crcfifo2_dataout[3]), .C(n1048), .D(
crcfifo1_dataout[3]), .Y(n889) );
NAND2X1 U1087 ( .A(n705), .B(n452), .Y(crcfifo_dataout[3]) );
AOI22X1 U1088 ( .A(n1074), .B(crcfifo2_dataout[4]), .C(n1073), .D(
crcfifo1_dataout[4]), .Y(n891) );
NAND2X1 U1089 ( .A(n704), .B(n453), .Y(crcfifo_dataout[4]) );
AOI22X1 U1090 ( .A(n1074), .B(crcfifo2_dataout[5]), .C(n1048), .D(
crcfifo1_dataout[5]), .Y(n893) );
NAND2X1 U1091 ( .A(n703), .B(n454), .Y(crcfifo_dataout[5]) );
AOI22X1 U1092 ( .A(n1074), .B(crcfifo2_dataout[6]), .C(n1073), .D(
crcfifo1_dataout[6]), .Y(n895) );
NAND2X1 U1093 ( .A(n702), .B(n455), .Y(crcfifo_dataout[6]) );
AOI22X1 U1094 ( .A(n1074), .B(crcfifo2_dataout[7]), .C(n1048), .D(
crcfifo1_dataout[7]), .Y(n897) );
NAND2X1 U1095 ( .A(n701), .B(n456), .Y(crcfifo_dataout[7]) );
AOI22X1 U1096 ( .A(n1074), .B(crcfifo2_dataout[8]), .C(n1073), .D(
crcfifo1_dataout[8]), .Y(n899) );
NAND2X1 U1097 ( .A(n700), .B(n457), .Y(crcfifo_dataout[8]) );
AOI22X1 U1098 ( .A(n1074), .B(crcfifo2_dataout[9]), .C(n1048), .D(
crcfifo1_dataout[9]), .Y(n901) );
NAND2X1 U1099 ( .A(n699), .B(n458), .Y(crcfifo_dataout[9]) );
AOI22X1 U1100 ( .A(n1074), .B(crcfifo2_dataout[10]), .C(n1048), .D(
crcfifo1_dataout[10]), .Y(n903) );
NAND2X1 U1101 ( .A(n698), .B(n459), .Y(crcfifo_dataout[10]) );
AOI22X1 U1102 ( .A(n1074), .B(crcfifo2_dataout[11]), .C(n1048), .D(
crcfifo1_dataout[11]), .Y(n905) );
NAND2X1 U1103 ( .A(n697), .B(n460), .Y(crcfifo_dataout[11]) );
AOI22X1 U1104 ( .A(n1074), .B(crcfifo2_dataout[12]), .C(n1048), .D(
crcfifo1_dataout[12]), .Y(n907) );
NAND2X1 U1105 ( .A(n696), .B(n461), .Y(crcfifo_dataout[12]) );
AOI22X1 U1106 ( .A(n1074), .B(crcfifo2_dataout[13]), .C(n1073), .D(
crcfifo1_dataout[13]), .Y(n909) );
NAND2X1 U1107 ( .A(n695), .B(n462), .Y(crcfifo_dataout[13]) );
AOI22X1 U1108 ( .A(n1074), .B(crcfifo2_dataout[14]), .C(n1073), .D(
crcfifo1_dataout[14]), .Y(n911) );
NAND2X1 U1109 ( .A(n694), .B(n463), .Y(crcfifo_dataout[14]) );
AOI22X1 U1110 ( .A(n1074), .B(crcfifo2_dataout[15]), .C(n1073), .D(
crcfifo1_dataout[15]), .Y(n913) );
NAND2X1 U1111 ( .A(n693), .B(n464), .Y(crcfifo_dataout[15]) );
AOI22X1 U1112 ( .A(n1074), .B(crcfifo2_dataout[16]), .C(n1048), .D(
crcfifo1_dataout[16]), .Y(n915) );
NAND2X1 U1113 ( .A(n692), .B(n465), .Y(crcfifo_dataout[16]) );
AOI22X1 U1114 ( .A(n1074), .B(crcfifo2_dataout[17]), .C(n1073), .D(
crcfifo1_dataout[17]), .Y(n917) );
NAND2X1 U1115 ( .A(n691), .B(n466), .Y(crcfifo_dataout[17]) );
AOI22X1 U1116 ( .A(n1074), .B(crcfifo2_dataout[18]), .C(n1048), .D(
crcfifo1_dataout[18]), .Y(n919) );
NAND2X1 U1117 ( .A(n690), .B(n467), .Y(crcfifo_dataout[18]) );
AOI22X1 U1118 ( .A(n1074), .B(crcfifo2_dataout[19]), .C(n1073), .D(
crcfifo1_dataout[19]), .Y(n921) );
NAND2X1 U1119 ( .A(n689), .B(n468), .Y(crcfifo_dataout[19]) );
AOI22X1 U1120 ( .A(n1074), .B(crcfifo2_dataout[20]), .C(n1048), .D(
crcfifo1_dataout[20]), .Y(n923) );
NAND2X1 U1121 ( .A(n688), .B(n469), .Y(crcfifo_dataout[20]) );
AOI22X1 U1122 ( .A(n1074), .B(crcfifo2_dataout[21]), .C(n1048), .D(
crcfifo1_dataout[21]), .Y(n925) );
NAND2X1 U1123 ( .A(n687), .B(n470), .Y(crcfifo_dataout[21]) );
AOI22X1 U1124 ( .A(n1074), .B(crcfifo2_dataout[22]), .C(n1073), .D(
crcfifo1_dataout[22]), .Y(n927) );
NAND2X1 U1125 ( .A(n686), .B(n471), .Y(crcfifo_dataout[22]) );
AOI22X1 U1126 ( .A(n1074), .B(crcfifo2_dataout[23]), .C(n1073), .D(
crcfifo1_dataout[23]), .Y(n929) );
NAND2X1 U1127 ( .A(n685), .B(n472), .Y(crcfifo_dataout[23]) );
AOI22X1 U1128 ( .A(n1074), .B(crcfifo2_dataout[24]), .C(n1073), .D(
crcfifo1_dataout[24]), .Y(n931) );
NAND2X1 U1129 ( .A(n684), .B(n473), .Y(crcfifo_dataout[24]) );
AOI22X1 U1130 ( .A(n1074), .B(crcfifo2_dataout[25]), .C(n1073), .D(
crcfifo1_dataout[25]), .Y(n933) );
NAND2X1 U1131 ( .A(n683), .B(n474), .Y(crcfifo_dataout[25]) );
AOI22X1 U1132 ( .A(n1074), .B(crcfifo2_dataout[26]), .C(n1048), .D(
crcfifo1_dataout[26]), .Y(n935) );
NAND2X1 U1133 ( .A(n682), .B(n475), .Y(crcfifo_dataout[26]) );
AOI22X1 U1134 ( .A(n1074), .B(crcfifo2_dataout[27]), .C(n1073), .D(
crcfifo1_dataout[27]), .Y(n937) );
NAND2X1 U1135 ( .A(n681), .B(n476), .Y(crcfifo_dataout[27]) );
AOI22X1 U1136 ( .A(n1074), .B(crcfifo2_dataout[28]), .C(n1073), .D(
crcfifo1_dataout[28]), .Y(n939) );
NAND2X1 U1137 ( .A(n680), .B(n477), .Y(crcfifo_dataout[28]) );
AOI22X1 U1138 ( .A(n1074), .B(crcfifo2_dataout[29]), .C(n1048), .D(
crcfifo1_dataout[29]), .Y(n941) );
NAND2X1 U1139 ( .A(n679), .B(n478), .Y(crcfifo_dataout[29]) );
AOI22X1 U1140 ( .A(n1074), .B(crcfifo2_dataout[30]), .C(n1073), .D(
crcfifo1_dataout[30]), .Y(n943) );
NAND2X1 U1141 ( .A(n678), .B(n479), .Y(crcfifo_dataout[30]) );
AOI22X1 U1142 ( .A(n1074), .B(crcfifo2_dataout[31]), .C(n1073), .D(
crcfifo1_dataout[31]), .Y(n945) );
NAND2X1 U1143 ( .A(n677), .B(n480), .Y(crcfifo_dataout[31]) );
AOI22X1 U1144 ( .A(n1074), .B(pfifo_datain2[0]), .C(n1073), .D(
pfifo_datain1[0]), .Y(n947) );
NAND2X1 U1145 ( .A(n660), .B(n481), .Y(pfifo_datain[0]) );
AOI22X1 U1146 ( .A(n1074), .B(pfifo_datain2[1]), .C(n1073), .D(
pfifo_datain1[1]), .Y(n949) );
NAND2X1 U1147 ( .A(n659), .B(n482), .Y(pfifo_datain[1]) );
AOI22X1 U1148 ( .A(n1074), .B(pfifo_datain2[2]), .C(n1073), .D(
pfifo_datain1[2]), .Y(n951) );
NAND2X1 U1149 ( .A(n658), .B(n483), .Y(pfifo_datain[2]) );
AOI22X1 U1150 ( .A(n1074), .B(pfifo_datain2[3]), .C(n1073), .D(
pfifo_datain1[3]), .Y(n953) );
NAND2X1 U1151 ( .A(n657), .B(n484), .Y(pfifo_datain[3]) );
AOI22X1 U1152 ( .A(n1074), .B(pfifo_datain2[4]), .C(n1048), .D(
pfifo_datain1[4]), .Y(n955) );
NAND2X1 U1153 ( .A(n656), .B(n485), .Y(pfifo_datain[4]) );
AOI22X1 U1154 ( .A(n1074), .B(pfifo_datain2[5]), .C(n1073), .D(
pfifo_datain1[5]), .Y(n957) );
NAND2X1 U1155 ( .A(n655), .B(n486), .Y(pfifo_datain[5]) );
AOI22X1 U1156 ( .A(n1074), .B(pfifo_datain2[6]), .C(n1073), .D(
pfifo_datain1[6]), .Y(n959) );
NAND2X1 U1157 ( .A(n654), .B(n487), .Y(pfifo_datain[6]) );
AOI22X1 U1158 ( .A(n1074), .B(pfifo_datain2[7]), .C(n1048), .D(
pfifo_datain1[7]), .Y(n961) );
NAND2X1 U1159 ( .A(n653), .B(n488), .Y(pfifo_datain[7]) );
AOI22X1 U1160 ( .A(n1074), .B(pfifo_datain2[8]), .C(n1073), .D(
pfifo_datain1[8]), .Y(n963) );
NAND2X1 U1161 ( .A(n652), .B(n489), .Y(pfifo_datain[8]) );
AOI22X1 U1162 ( .A(n1074), .B(pfifo_datain2[9]), .C(n1073), .D(
pfifo_datain1[9]), .Y(n965) );
NAND2X1 U1163 ( .A(n651), .B(n490), .Y(pfifo_datain[9]) );
AOI22X1 U1164 ( .A(n1074), .B(pfifo_datain2[10]), .C(n1073), .D(
pfifo_datain1[10]), .Y(n967) );
NAND2X1 U1165 ( .A(n650), .B(n491), .Y(pfifo_datain[10]) );
AOI22X1 U1166 ( .A(n1074), .B(pfifo_datain2[11]), .C(n1073), .D(
pfifo_datain1[11]), .Y(n969) );
NAND2X1 U1167 ( .A(n649), .B(n492), .Y(pfifo_datain[11]) );
AOI22X1 U1168 ( .A(n1074), .B(pfifo_datain2[12]), .C(n1073), .D(
pfifo_datain1[12]), .Y(n971) );
NAND2X1 U1169 ( .A(n648), .B(n493), .Y(pfifo_datain[12]) );
AOI22X1 U1170 ( .A(n1074), .B(pfifo_datain2[13]), .C(n1048), .D(
pfifo_datain1[13]), .Y(n973) );
NAND2X1 U1171 ( .A(n647), .B(n494), .Y(pfifo_datain[13]) );
AOI22X1 U1172 ( .A(n1074), .B(pfifo_datain2[14]), .C(n1048), .D(
pfifo_datain1[14]), .Y(n975) );
NAND2X1 U1173 ( .A(n646), .B(n495), .Y(pfifo_datain[14]) );
AOI22X1 U1174 ( .A(n1074), .B(pfifo_datain2[15]), .C(n1048), .D(
pfifo_datain1[15]), .Y(n977) );
NAND2X1 U1175 ( .A(n645), .B(n496), .Y(pfifo_datain[15]) );
AOI22X1 U1176 ( .A(n1074), .B(pfifo_datain2[16]), .C(n1073), .D(
pfifo_datain1[16]), .Y(n979) );
NAND2X1 U1177 ( .A(n644), .B(n497), .Y(pfifo_datain[16]) );
AOI22X1 U1178 ( .A(n1074), .B(pfifo_datain2[17]), .C(n1073), .D(
pfifo_datain1[17]), .Y(n981) );
NAND2X1 U1179 ( .A(n643), .B(n498), .Y(pfifo_datain[17]) );
AOI22X1 U1180 ( .A(n1074), .B(pfifo_datain2[18]), .C(n1073), .D(
pfifo_datain1[18]), .Y(n983) );
NAND2X1 U1181 ( .A(n642), .B(n499), .Y(pfifo_datain[18]) );
AOI22X1 U1182 ( .A(n1074), .B(pfifo_datain2[19]), .C(n1073), .D(
pfifo_datain1[19]), .Y(n985) );
NAND2X1 U1183 ( .A(n641), .B(n500), .Y(pfifo_datain[19]) );
AOI22X1 U1184 ( .A(n1074), .B(pfifo_datain2[20]), .C(n1073), .D(
pfifo_datain1[20]), .Y(n987) );
NAND2X1 U1185 ( .A(n640), .B(n501), .Y(pfifo_datain[20]) );
AOI22X1 U1186 ( .A(n1074), .B(pfifo_datain2[21]), .C(n1073), .D(
pfifo_datain1[21]), .Y(n989) );
NAND2X1 U1187 ( .A(n639), .B(n502), .Y(pfifo_datain[21]) );
AOI22X1 U1188 ( .A(n1074), .B(pfifo_datain2[22]), .C(n1073), .D(
pfifo_datain1[22]), .Y(n991) );
NAND2X1 U1189 ( .A(n638), .B(n503), .Y(pfifo_datain[22]) );
AOI22X1 U1190 ( .A(n1074), .B(pfifo_datain2[23]), .C(n1073), .D(
pfifo_datain1[23]), .Y(n993) );
NAND2X1 U1191 ( .A(n637), .B(n504), .Y(pfifo_datain[23]) );
AOI22X1 U1192 ( .A(n1074), .B(pfifo_datain2[24]), .C(n1073), .D(
pfifo_datain1[24]), .Y(n995) );
NAND2X1 U1193 ( .A(n636), .B(n505), .Y(pfifo_datain[24]) );
AOI22X1 U1194 ( .A(n1074), .B(pfifo_datain2[25]), .C(n1073), .D(
pfifo_datain1[25]), .Y(n997) );
NAND2X1 U1195 ( .A(n635), .B(n506), .Y(pfifo_datain[25]) );
AOI22X1 U1196 ( .A(n1074), .B(pfifo_datain2[26]), .C(n1073), .D(
pfifo_datain1[26]), .Y(n999) );
NAND2X1 U1197 ( .A(n634), .B(n507), .Y(pfifo_datain[26]) );
AOI22X1 U1198 ( .A(n1074), .B(pfifo_datain2[27]), .C(n1073), .D(
pfifo_datain1[27]), .Y(n1001) );
NAND2X1 U1199 ( .A(n633), .B(n508), .Y(pfifo_datain[27]) );
AOI22X1 U1200 ( .A(n1074), .B(pfifo_datain2[28]), .C(n1073), .D(
pfifo_datain1[28]), .Y(n1003) );
NAND2X1 U1201 ( .A(n632), .B(n509), .Y(pfifo_datain[28]) );
AOI22X1 U1202 ( .A(n1074), .B(pfifo_datain2[29]), .C(n1073), .D(
pfifo_datain1[29]), .Y(n1005) );
NAND2X1 U1203 ( .A(n631), .B(n510), .Y(pfifo_datain[29]) );
AOI22X1 U1204 ( .A(n1074), .B(pfifo_datain2[30]), .C(n1073), .D(
pfifo_datain1[30]), .Y(n1007) );
NAND2X1 U1205 ( .A(n630), .B(n511), .Y(pfifo_datain[30]) );
AOI22X1 U1206 ( .A(n1074), .B(pfifo_datain2[31]), .C(n1073), .D(
pfifo_datain1[31]), .Y(n1009) );
NAND2X1 U1207 ( .A(n629), .B(n512), .Y(pfifo_datain[31]) );
AOI22X1 U1208 ( .A(n1074), .B(pfifo_datain2[32]), .C(n1073), .D(
pfifo_datain1[32]), .Y(n1011) );
NAND2X1 U1209 ( .A(n628), .B(n513), .Y(pfifo_datain[32]) );
AOI22X1 U1210 ( .A(n1074), .B(pfifo_datain2[33]), .C(n1073), .D(
pfifo_datain1[33]), .Y(n1013) );
NAND2X1 U1211 ( .A(n627), .B(n514), .Y(pfifo_datain[33]) );
AOI22X1 U1212 ( .A(n1074), .B(pfifo_datain2[34]), .C(n1073), .D(
pfifo_datain1[34]), .Y(n1015) );
NAND2X1 U1213 ( .A(n626), .B(n515), .Y(pfifo_datain[34]) );
AOI22X1 U1214 ( .A(n1074), .B(pfifo_datain2[35]), .C(n1073), .D(
pfifo_datain1[35]), .Y(n1017) );
NAND2X1 U1215 ( .A(n625), .B(n516), .Y(pfifo_datain[35]) );
AOI22X1 U1216 ( .A(n1074), .B(pfifo_datain2[36]), .C(n1048), .D(
pfifo_datain1[36]), .Y(n1019) );
NAND2X1 U1217 ( .A(n624), .B(n517), .Y(pfifo_datain[36]) );
AOI22X1 U1218 ( .A(n1074), .B(pfifo_datain2[37]), .C(n1073), .D(
pfifo_datain1[37]), .Y(n1021) );
NAND2X1 U1219 ( .A(n623), .B(n518), .Y(pfifo_datain[37]) );
AOI22X1 U1220 ( .A(n1074), .B(pfifo_datain2[38]), .C(n1073), .D(
pfifo_datain1[38]), .Y(n1023) );
NAND2X1 U1221 ( .A(n622), .B(n519), .Y(pfifo_datain[38]) );
AOI22X1 U1222 ( .A(n1074), .B(pfifo_datain2[39]), .C(n1073), .D(
pfifo_datain1[39]), .Y(n1025) );
NAND2X1 U1223 ( .A(n621), .B(n520), .Y(pfifo_datain[39]) );
AOI22X1 U1224 ( .A(n1074), .B(pfifo_datain2[40]), .C(n1073), .D(
pfifo_datain1[40]), .Y(n1027) );
NAND2X1 U1225 ( .A(n620), .B(n521), .Y(pfifo_datain[40]) );
AOI22X1 U1226 ( .A(n1074), .B(pfifo_datain2[41]), .C(n1073), .D(
pfifo_datain1[41]), .Y(n1029) );
NAND2X1 U1227 ( .A(n619), .B(n522), .Y(pfifo_datain[41]) );
AOI22X1 U1228 ( .A(n1074), .B(pfifo_datain2[42]), .C(n1073), .D(
pfifo_datain1[42]), .Y(n1031) );
NAND2X1 U1229 ( .A(n618), .B(n523), .Y(pfifo_datain[42]) );
AOI22X1 U1230 ( .A(n1074), .B(pfifo_datain2[43]), .C(n1048), .D(
pfifo_datain1[43]), .Y(n1033) );
NAND2X1 U1231 ( .A(n617), .B(n524), .Y(pfifo_datain[43]) );
AOI22X1 U1232 ( .A(n1074), .B(pfifo_datain2[44]), .C(n1048), .D(
pfifo_datain1[44]), .Y(n1035) );
NAND2X1 U1233 ( .A(n616), .B(n525), .Y(pfifo_datain[44]) );
AOI22X1 U1234 ( .A(n1074), .B(pfifo_datain2[45]), .C(n1048), .D(
pfifo_datain1[45]), .Y(n1037) );
NAND2X1 U1235 ( .A(n615), .B(n526), .Y(pfifo_datain[45]) );
AOI22X1 U1236 ( .A(n1074), .B(pfifo_datain2[46]), .C(n1048), .D(
pfifo_datain1[46]), .Y(n1039) );
NAND2X1 U1237 ( .A(n614), .B(n527), .Y(pfifo_datain[46]) );
AOI22X1 U1238 ( .A(n1074), .B(pfifo_datain2[47]), .C(n1073), .D(
pfifo_datain1[47]), .Y(n1041) );
NAND2X1 U1239 ( .A(n613), .B(n528), .Y(pfifo_datain[47]) );
AOI22X1 U1240 ( .A(n1074), .B(pfifo_datain2[48]), .C(n1073), .D(
pfifo_datain1[48]), .Y(n1043) );
NAND2X1 U1241 ( .A(n612), .B(n529), .Y(pfifo_datain[48]) );
AOI22X1 U1242 ( .A(n1074), .B(pfifo_datain2[49]), .C(n1073), .D(
pfifo_datain1[49]), .Y(n1045) );
NAND2X1 U1243 ( .A(n611), .B(n530), .Y(pfifo_datain[49]) );
AOI22X1 U1244 ( .A(n1074), .B(pfifo_datain2[50]), .C(n1073), .D(
pfifo_datain1[50]), .Y(n1047) );
NAND2X1 U1245 ( .A(n610), .B(n531), .Y(pfifo_datain[50]) );
AOI22X1 U1246 ( .A(n1074), .B(pfifo_datain2[51]), .C(n1048), .D(
pfifo_datain1[51]), .Y(n1050) );
NAND2X1 U1247 ( .A(n609), .B(n532), .Y(pfifo_datain[51]) );
AOI22X1 U1248 ( .A(n1074), .B(pfifo_datain2[52]), .C(n1073), .D(
pfifo_datain1[52]), .Y(n1052) );
NAND2X1 U1249 ( .A(n608), .B(n533), .Y(pfifo_datain[52]) );
AOI22X1 U1250 ( .A(n1074), .B(pfifo_datain2[53]), .C(n1073), .D(
pfifo_datain1[53]), .Y(n1054) );
NAND2X1 U1251 ( .A(n607), .B(n534), .Y(pfifo_datain[53]) );
AOI22X1 U1252 ( .A(n1074), .B(pfifo_datain2[54]), .C(n1073), .D(
pfifo_datain1[54]), .Y(n1056) );
NAND2X1 U1253 ( .A(n606), .B(n535), .Y(pfifo_datain[54]) );
AOI22X1 U1254 ( .A(n1074), .B(pfifo_datain2[55]), .C(n1073), .D(
pfifo_datain1[55]), .Y(n1058) );
NAND2X1 U1255 ( .A(n605), .B(n536), .Y(pfifo_datain[55]) );
AOI22X1 U1256 ( .A(n1074), .B(pfifo_datain2[56]), .C(n1073), .D(
pfifo_datain1[56]), .Y(n1060) );
NAND2X1 U1257 ( .A(n604), .B(n537), .Y(pfifo_datain[56]) );
AOI22X1 U1258 ( .A(n1074), .B(pfifo_datain2[57]), .C(n1073), .D(
pfifo_datain1[57]), .Y(n1062) );
NAND2X1 U1259 ( .A(n603), .B(n538), .Y(pfifo_datain[57]) );
AOI22X1 U1260 ( .A(n1074), .B(pfifo_datain2[58]), .C(n1073), .D(
pfifo_datain1[58]), .Y(n1064) );
NAND2X1 U1261 ( .A(n602), .B(n539), .Y(pfifo_datain[58]) );
AOI22X1 U1262 ( .A(n1074), .B(pfifo_datain2[59]), .C(n1073), .D(
pfifo_datain1[59]), .Y(n1066) );
NAND2X1 U1263 ( .A(n601), .B(n540), .Y(pfifo_datain[59]) );
AOI22X1 U1264 ( .A(n1074), .B(pfifo_datain2[60]), .C(n1073), .D(
pfifo_datain1[60]), .Y(n1068) );
NAND2X1 U1265 ( .A(n600), .B(n541), .Y(pfifo_datain[60]) );
AOI22X1 U1266 ( .A(n1074), .B(pfifo_datain2[61]), .C(n1073), .D(
pfifo_datain1[61]), .Y(n1070) );
NAND2X1 U1267 ( .A(n599), .B(n542), .Y(pfifo_datain[61]) );
AOI22X1 U1268 ( .A(n1074), .B(pfifo_datain2[62]), .C(n1073), .D(
pfifo_datain1[62]), .Y(n1072) );
NAND2X1 U1269 ( .A(n598), .B(n543), .Y(pfifo_datain[62]) );
AOI22X1 U1270 ( .A(n1074), .B(pfifo_datain2[63]), .C(n1073), .D(
pfifo_datain1[63]), .Y(n1077) );
NAND2X1 U1271 ( .A(n597), .B(n544), .Y(pfifo_datain[63]) );
endmodule | 1 |
137,578 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v | 79,197,809 | queue_selection_gates.v | v | 897 | 102 | [] | [] | [] | [(8, 895)] | null | null | 1: b"%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:93: Cannot find file containing module: 'CFD2QX1'\n CFD2QX1 \\qos/srv_cnt2_d_reg[5] ( .D(\\qos/N31 ), .CP(\\clks.clk ), .CD(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign,data/full_repos/permissive/79197809/CFD2QX1\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign,data/full_repos/permissive/79197809/CFD2QX1.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign,data/full_repos/permissive/79197809/CFD2QX1.sv\n CFD2QX1\n CFD2QX1.v\n CFD2QX1.sv\n obj_dir/CFD2QX1\n obj_dir/CFD2QX1.v\n obj_dir/CFD2QX1.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:95: Cannot find file containing module: 'CFD2QXL'\n CFD2QXL \\qos/queue_gnt_d_reg[2] ( .D(n481), .CP(\\clks.clk ), .CD(\\clks.rst ), .Q(buffer_sel[2]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:96: Cannot find file containing module: 'CFD2QXL'\n CFD2QXL \\qos/srv_cnt1_d_reg[0] ( .D(n927), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:98: Cannot find file containing module: 'CFD2QX1'\n CFD2QX1 \\qos/srv_cnt2_d_reg[7] ( .D(\\qos/N33 ), .CP(\\clks.clk ), .CD(\n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:100: Cannot find file containing module: 'CFD2QXL'\n CFD2QXL \\qos/srv_cnt0_d_reg[1] ( .D(n920), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:102: Cannot find file containing module: 'CFD2QXL'\n CFD2QXL \\qos/srv_cnt0_d_reg[0] ( .D(n931), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:104: Cannot find file containing module: 'CFD2QX2'\n CFD2QX2 \\qos/srv_cnt2_d_reg[2] ( .D(n935), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:106: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt0_d_reg[5] ( .D(n932), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:108: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt0_d_reg[3] ( .D(n921), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:110: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt2_d_reg[3] ( .D(n925), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:112: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt1_d_reg[7] ( .D(n930), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:114: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt1_d_reg[6] ( .D(n929), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:116: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt0_d_reg[4] ( .D(n938), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:118: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt1_d_reg[5] ( .D(n928), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:120: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt2_d_reg[4] ( .D(n924), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:122: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt2_d_reg[0] ( .D(n939), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:124: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt0_d_reg[7] ( .D(n922), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:126: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt2_d_reg[6] ( .D(n919), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:128: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt1_d_reg[2] ( .D(n918), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:130: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt2_d_reg[1] ( .D(n934), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:132: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt1_d_reg[1] ( .D(n923), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:134: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt0_d_reg[6] ( .D(n933), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:136: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt0_d_reg[2] ( .D(n926), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:138: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt1_d_reg[4] ( .D(n936), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:140: Cannot find file containing module: 'CFD2X2'\n CFD2X2 \\qos/srv_cnt1_d_reg[3] ( .D(n937), .CP(\\clks.clk ), .CD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:142: Cannot find file containing module: 'CFD2QXL'\n CFD2QXL \\qos/queue_gnt_d_reg[1] ( .D(\\qos/queue_gnt_q [1]), .CP(\\clks.clk ), \n ^~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:144: Cannot find file containing module: 'CFD4X1'\n CFD4X1 \\qos/queue_gnt_d_reg[0] ( .D(n917), .CP(\\clks.clk ), .SD(\\clks.rst ), \n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:146: Cannot find file containing module: 'CNIVXL'\n CNIVXL U434 ( .A(n913), .Z(n456) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:147: Cannot find file containing module: 'CND3XL'\n CND3XL U435 ( .A(n659), .B(n658), .C(buffer_sel[0]), .Z(n671) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:148: Cannot find file containing module: 'CENX1'\n CENX1 U436 ( .A(n521), .B(n522), .Z(n520) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:149: Cannot find file containing module: 'CENX1'\n CENX1 U437 ( .A(n623), .B(n650), .Z(n661) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:150: Cannot find file containing module: 'CIVX2'\n CIVX2 U438 ( .A(n403), .Z(n559) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:151: Cannot find file containing module: 'CND2XL'\n CND2XL U439 ( .A(n903), .B(n911), .Z(n494) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:152: Cannot find file containing module: 'CMX2X1'\n CMX2X1 U440 ( .A0(\\qos/srv_cnt0_d [1]), .A1(n619), .S(n650), .Z(n900) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:153: Cannot find file containing module: 'CNIVX1'\n CNIVX1 U441 ( .A(n910), .Z(n453) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:154: Cannot find file containing module: 'CMX2X1'\n CMX2X1 U442 ( .A0(n441), .A1(n636), .S(n517), .Z(n383) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:155: Cannot find file containing module: 'CND2X2'\n CND2X2 U443 ( .A(n495), .B(n498), .Z(n905) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:156: Cannot find file containing module: 'CENX1'\n CENX1 U444 ( .A(n620), .B(n385), .Z(n902) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:157: Cannot find file containing module: 'CND2X1'\n CND2X1 U445 ( .A(n650), .B(n592), .Z(n498) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:158: Cannot find file containing module: 'CND2X1'\n CND2X1 U446 ( .A(n491), .B(n436), .Z(n470) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:159: Cannot find file containing module: 'CND2X1'\n CND2X1 U447 ( .A(n591), .B(n506), .Z(n507) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:160: Cannot find file containing module: 'CND2X2'\n CND2X2 U448 ( .A(n572), .B(n669), .Z(n473) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:161: Cannot find file containing module: 'CND3X2'\n CND3X2 U449 ( .A(n584), .B(n583), .C(n545), .Z(n544) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:162: Cannot find file containing module: 'CND2X1'\n CND2X1 U450 ( .A(n575), .B(n574), .Z(n583) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:163: Cannot find file containing module: 'CND2X2'\n CND2X2 U451 ( .A(n524), .B(n554), .Z(n523) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:164: Cannot find file containing module: 'CNIVXL'\n CNIVXL U452 ( .A(n906), .Z(n375) );\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:165: Cannot find file containing module: 'CIVXL'\n CIVXL U453 ( .A(\\qos/srv_cnt2_d [7]), .Z(n641) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:166: Cannot find file containing module: 'CEOXL'\n CEOXL U454 ( .A(n606), .B(n605), .Z(n608) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:167: Cannot find file containing module: 'CIVX4'\n CIVX4 U455 ( .A(n568), .Z(n569) );\n ^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/rtl/syn_wholedesign/queue_selection_gates.v:168: Cannot find file containing module: 'CIVX4'\n CIVX4 U456 ( .A(n673), .Z(n376) );\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 299,851 | module | module queue_selection ( \clks.clk , \clks.rst , arb_nxt, pfifo_datain0,
pfifo_datain1, pfifo_datain2, crcfifo0_dataout, crcfifo1_dataout,
crcfifo2_dataout, pfifo_datain_ctrl_0, pfifo_datain_ctrl_1,
pfifo_datain_ctrl_2, crcfifo0_empty, crcfifo1_empty, crcfifo2_empty,
pfifo_pop, crcfifo_pop, crcfifo0_pull, crcfifo1_pull, crcfifo2_pull,
pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1,
pcfifo_pop_2, pfifo_datain, pfifo_datain_ctrl, crcfifo_dataout,
start_transmit );
input [63:0] pfifo_datain0;
input [63:0] pfifo_datain1;
input [63:0] pfifo_datain2;
input [31:0] crcfifo0_dataout;
input [31:0] crcfifo1_dataout;
input [31:0] crcfifo2_dataout;
input [15:0] pfifo_datain_ctrl_0;
input [15:0] pfifo_datain_ctrl_1;
input [15:0] pfifo_datain_ctrl_2;
output [63:0] pfifo_datain;
output [15:0] pfifo_datain_ctrl;
output [31:0] crcfifo_dataout;
input \clks.clk , \clks.rst , arb_nxt, crcfifo0_empty, crcfifo1_empty,
crcfifo2_empty, pfifo_pop, crcfifo_pop;
output crcfifo0_pull, crcfifo1_pull, crcfifo2_pull, pfifo_pop_0, pfifo_pop_1,
pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1, pcfifo_pop_2, start_transmit;
wire pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, \qos/N33 , \qos/N31 ,
\qos/srv_cnt1_d[0] , n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940;
wire [2:0] buffer_sel;
wire [2:0] \qos/queue_gnt_q ;
wire [7:0] \qos/srv_cnt2_d ;
wire [7:0] \qos/srv_cnt0_d ;
assign pcfifo_pop_0 = pfifo_pop_0;
assign pcfifo_pop_1 = pfifo_pop_1;
assign pcfifo_pop_2 = pfifo_pop_2;
CFD2QX1 \qos/srv_cnt2_d_reg[5] ( .D(\qos/N31 ), .CP(\clks.clk ), .CD(
\clks.rst ), .Q(\qos/srv_cnt2_d [5]) );
CFD2QXL \qos/queue_gnt_d_reg[2] ( .D(n481), .CP(\clks.clk ), .CD(\clks.rst ), .Q(buffer_sel[2]) );
CFD2QXL \qos/srv_cnt1_d_reg[0] ( .D(n927), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt1_d[0] ) );
CFD2QX1 \qos/srv_cnt2_d_reg[7] ( .D(\qos/N33 ), .CP(\clks.clk ), .CD(
\clks.rst ), .Q(\qos/srv_cnt2_d [7]) );
CFD2QXL \qos/srv_cnt0_d_reg[1] ( .D(n920), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt0_d [1]) );
CFD2QXL \qos/srv_cnt0_d_reg[0] ( .D(n931), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt0_d [0]) );
CFD2QX2 \qos/srv_cnt2_d_reg[2] ( .D(n935), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt2_d [2]) );
CFD2X2 \qos/srv_cnt0_d_reg[5] ( .D(n932), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n449), .QN(n450) );
CFD2X2 \qos/srv_cnt0_d_reg[3] ( .D(n921), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n447), .QN(n446) );
CFD2X2 \qos/srv_cnt2_d_reg[3] ( .D(n925), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n445), .QN(n381) );
CFD2X2 \qos/srv_cnt1_d_reg[7] ( .D(n930), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n443), .QN(n442) );
CFD2X2 \qos/srv_cnt1_d_reg[6] ( .D(n929), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n440), .QN(n439) );
CFD2X2 \qos/srv_cnt0_d_reg[4] ( .D(n938), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n438), .QN(n437) );
CFD2X2 \qos/srv_cnt1_d_reg[5] ( .D(n928), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n435), .QN(n434) );
CFD2X2 \qos/srv_cnt2_d_reg[4] ( .D(n924), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n433) );
CFD2X2 \qos/srv_cnt2_d_reg[0] ( .D(n939), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n432) );
CFD2X2 \qos/srv_cnt0_d_reg[7] ( .D(n922), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n430), .QN(n431) );
CFD2X2 \qos/srv_cnt2_d_reg[6] ( .D(n919), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n428), .QN(n429) );
CFD2X2 \qos/srv_cnt1_d_reg[2] ( .D(n918), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n426), .QN(n425) );
CFD2X2 \qos/srv_cnt2_d_reg[1] ( .D(n934), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n424), .QN(n423) );
CFD2X2 \qos/srv_cnt1_d_reg[1] ( .D(n923), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n421), .QN(n420) );
CFD2X2 \qos/srv_cnt0_d_reg[6] ( .D(n933), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n418), .QN(n419) );
CFD2X2 \qos/srv_cnt0_d_reg[2] ( .D(n926), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n416), .QN(n415) );
CFD2X2 \qos/srv_cnt1_d_reg[4] ( .D(n936), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n413), .QN(n412) );
CFD2X2 \qos/srv_cnt1_d_reg[3] ( .D(n937), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n410), .QN(n409) );
CFD2QXL \qos/queue_gnt_d_reg[1] ( .D(\qos/queue_gnt_q [1]), .CP(\clks.clk ),
.CD(\clks.rst ), .Q(buffer_sel[1]) );
CFD4X1 \qos/queue_gnt_d_reg[0] ( .D(n917), .CP(\clks.clk ), .SD(\clks.rst ),
.Q(n940), .QN(buffer_sel[0]) );
CNIVXL U434 ( .A(n913), .Z(n456) );
CND3XL U435 ( .A(n659), .B(n658), .C(buffer_sel[0]), .Z(n671) );
CENX1 U436 ( .A(n521), .B(n522), .Z(n520) );
CENX1 U437 ( .A(n623), .B(n650), .Z(n661) );
CIVX2 U438 ( .A(n403), .Z(n559) );
CND2XL U439 ( .A(n903), .B(n911), .Z(n494) );
CMX2X1 U440 ( .A0(\qos/srv_cnt0_d [1]), .A1(n619), .S(n650), .Z(n900) );
CNIVX1 U441 ( .A(n910), .Z(n453) );
CMX2X1 U442 ( .A0(n441), .A1(n636), .S(n517), .Z(n383) );
CND2X2 U443 ( .A(n495), .B(n498), .Z(n905) );
CENX1 U444 ( .A(n620), .B(n385), .Z(n902) );
CND2X1 U445 ( .A(n650), .B(n592), .Z(n498) );
CND2X1 U446 ( .A(n491), .B(n436), .Z(n470) );
CND2X1 U447 ( .A(n591), .B(n506), .Z(n507) );
CND2X2 U448 ( .A(n572), .B(n669), .Z(n473) );
CND3X2 U449 ( .A(n584), .B(n583), .C(n545), .Z(n544) );
CND2X1 U450 ( .A(n575), .B(n574), .Z(n583) );
CND2X2 U451 ( .A(n524), .B(n554), .Z(n523) );
CNIVXL U452 ( .A(n906), .Z(n375) );
CIVXL U453 ( .A(\qos/srv_cnt2_d [7]), .Z(n641) );
CEOXL U454 ( .A(n606), .B(n605), .Z(n608) );
CIVX4 U455 ( .A(n568), .Z(n569) );
CIVX4 U456 ( .A(n673), .Z(n376) );
CND2XL U457 ( .A(n657), .B(buffer_sel[1]), .Z(n673) );
CIVX4 U458 ( .A(n672), .Z(n782) );
CEOX1 U459 ( .A(n627), .B(n580), .Z(n377) );
CEOXL U460 ( .A(n611), .B(n425), .Z(n378) );
CENX1 U461 ( .A(n409), .B(n598), .Z(n379) );
CAN2X2 U462 ( .A(n400), .B(n479), .Z(n380) );
CNIVX1 U463 ( .A(crcfifo1_empty), .Z(n916) );
CENX1 U464 ( .A(n434), .B(n582), .Z(n382) );
CIVDX1 U465 ( .A(n642), .Z0(n384), .Z1(n385) );
CIVX2 U466 ( .A(n604), .Z(n521) );
CIVX1 U467 ( .A(n902), .Z(n478) );
CIVX12 U468 ( .A(n671), .Z(n561) );
CND2X1 U469 ( .A(n459), .B(n458), .Z(n457) );
CIVX2 U470 ( .A(n900), .Z(n503) );
CIVX1 U471 ( .A(n389), .Z(n390) );
CND2IX1 U472 ( .B(n480), .A(n481), .Z(n547) );
CIVX1 U473 ( .A(n573), .Z(n917) );
CNR2XL U474 ( .A(n667), .B(n671), .Z(pfifo_pop_0) );
CIVX1 U475 ( .A(buffer_sel[2]), .Z(n658) );
CND2X4 U476 ( .A(n500), .B(n486), .Z(n546) );
CNIVX2 U477 ( .A(n646), .Z(n491) );
CNR2X2 U478 ( .A(n386), .B(n617), .Z(n542) );
CND2X2 U479 ( .A(n386), .B(n617), .Z(n560) );
CENX2 U480 ( .A(n904), .B(n455), .Z(n386) );
CIVX3 U481 ( .A(n552), .Z(n555) );
CND2X2 U482 ( .A(n388), .B(n488), .Z(n552) );
CENX2 U483 ( .A(n489), .B(n387), .Z(n488) );
CENX2 U484 ( .A(n383), .B(n665), .Z(n387) );
CIVX2 U485 ( .A(n527), .Z(n388) );
CND2X2 U486 ( .A(n638), .B(n637), .Z(n527) );
CND2X2 U487 ( .A(n547), .B(n548), .Z(n460) );
CND3X1 U488 ( .A(n940), .B(n659), .C(buffer_sel[2]), .Z(n672) );
CMXI2X2 U489 ( .A0(n630), .A1(n429), .S(n642), .Z(n666) );
CNIVX1 U490 ( .A(\qos/queue_gnt_q [2]), .Z(n481) );
CIVXL U491 ( .A(n668), .Z(n389) );
CMXI2X1 U492 ( .A0(n391), .A1(n381), .S(n642), .Z(n668) );
CENX1 U493 ( .A(n381), .B(n603), .Z(n391) );
CND3X4 U494 ( .A(n394), .B(n393), .C(n392), .Z(n574) );
CNR2X4 U495 ( .A(n438), .B(n430), .Z(n392) );
CND4X4 U496 ( .A(n398), .B(n575), .C(n380), .D(n574), .Z(n576) );
CENX4 U497 ( .A(n905), .B(n482), .Z(n485) );
CND2X2 U498 ( .A(n398), .B(n380), .Z(n566) );
CNR2X2 U499 ( .A(n416), .B(n447), .Z(n393) );
CNR2X2 U500 ( .A(n449), .B(n418), .Z(n394) );
CND4X4 U501 ( .A(n397), .B(n396), .C(n395), .D(n564), .Z(n575) );
CNR2X2 U502 ( .A(n413), .B(n443), .Z(n395) );
CNR2X2 U503 ( .A(n440), .B(n410), .Z(n396) );
CNR2X2 U504 ( .A(n435), .B(n426), .Z(n397) );
CIVX3 U505 ( .A(n399), .Z(n398) );
CND2X2 U506 ( .A(n402), .B(n401), .Z(n399) );
CNR2X2 U507 ( .A(n428), .B(\qos/srv_cnt2_d [2]), .Z(n400) );
CNR2X2 U508 ( .A(n445), .B(n424), .Z(n401) );
CNR2X2 U509 ( .A(n432), .B(n433), .Z(n402) );
CIVX2 U510 ( .A(n421), .Z(n564) );
CND2X2 U511 ( .A(n901), .B(n902), .Z(n403) );
CND2X2 U512 ( .A(n403), .B(n477), .Z(n476) );
CND3X2 U513 ( .A(n513), .B(n511), .C(n520), .Z(n516) );
CNR2X2 U514 ( .A(n597), .B(n581), .Z(n471) );
CEOXL U515 ( .A(n564), .B(\qos/srv_cnt1_d[0] ), .Z(n616) );
CNIVXL U516 ( .A(n664), .Z(n404) );
CNR2X1 U517 ( .A(n408), .B(n531), .Z(n935) );
CNR2X1 U518 ( .A(n408), .B(n458), .Z(n932) );
CIVX3 U519 ( .A(n914), .Z(n408) );
CIVX2 U520 ( .A(n662), .Z(n458) );
CAN3X2 U521 ( .A(n587), .B(n530), .C(n473), .Z(n405) );
CND2X4 U522 ( .A(n589), .B(n569), .Z(n530) );
CMXI2X1 U523 ( .A0(n406), .A1(n423), .S(n642), .Z(n909) );
CEOXL U524 ( .A(n423), .B(n620), .Z(n406) );
CIVX2 U525 ( .A(n914), .Z(n407) );
CIVX2 U526 ( .A(n646), .Z(n517) );
CNR2IX2 U527 ( .B(n460), .A(n407), .Z(\qos/N31 ) );
CND2X2 U528 ( .A(n914), .B(n456), .Z(n915) );
CIVX2 U529 ( .A(n409), .Z(n411) );
CIVX2 U530 ( .A(n412), .Z(n414) );
CIVX2 U531 ( .A(n415), .Z(n417) );
CIVX2 U532 ( .A(n420), .Z(n422) );
CIVX2 U533 ( .A(n425), .Z(n427) );
CIVX2 U534 ( .A(n434), .Z(n436) );
CIVX2 U535 ( .A(n439), .Z(n441) );
CIVX2 U536 ( .A(n442), .Z(n444) );
CIVX2 U537 ( .A(n446), .Z(n448) );
CIVX2 U538 ( .A(n911), .Z(n466) );
CND2X4 U539 ( .A(n509), .B(n508), .Z(n911) );
COND1X2 U540 ( .A(n571), .B(n501), .C(n584), .Z(n572) );
CND2X4 U541 ( .A(n452), .B(n549), .Z(n584) );
CIVDX2 U542 ( .A(crcfifo0_empty), .Z0(n452), .Z1(n451) );
CND2X1 U543 ( .A(n569), .B(n377), .Z(n480) );
CENX4 U544 ( .A(n911), .B(n903), .Z(n482) );
CND2X1 U545 ( .A(n642), .B(n563), .Z(n508) );
CNIVX1 U546 ( .A(n453), .Z(n454) );
CMX2X1 U547 ( .A0(n444), .A1(n647), .S(n506), .Z(n907) );
CND2X1 U548 ( .A(n653), .B(n652), .Z(n654) );
CNR2X4 U549 ( .A(n567), .B(n576), .Z(n486) );
CND3X4 U550 ( .A(n537), .B(n538), .C(n624), .Z(n525) );
COND1X1 U551 ( .A(n532), .B(n904), .C(n453), .Z(n613) );
CNR2IX2 U552 ( .B(n590), .A(n405), .Z(n529) );
CNR2X4 U553 ( .A(n525), .B(n526), .Z(n524) );
CMXI2X2 U554 ( .A0(n379), .A1(n409), .S(n646), .Z(n906) );
CENX2 U555 ( .A(n532), .B(n910), .Z(n455) );
CND2X4 U556 ( .A(n505), .B(buffer_sel[2]), .Z(n557) );
CND3X4 U557 ( .A(n558), .B(n557), .C(n556), .Z(\qos/queue_gnt_q [2]) );
CNIVX4 U558 ( .A(n633), .Z(n650) );
CND2X1 U559 ( .A(n460), .B(n662), .Z(n637) );
CND2X2 U560 ( .A(n457), .B(n908), .Z(n638) );
CIVXL U561 ( .A(n460), .Z(n459) );
CENX2 U562 ( .A(n662), .B(n460), .Z(n469) );
CND3X2 U563 ( .A(n552), .B(n551), .C(n461), .Z(n514) );
CND2X4 U564 ( .A(n468), .B(n463), .Z(n461) );
CIVX2 U565 ( .A(n461), .Z(n553) );
CND2X2 U566 ( .A(n462), .B(n527), .Z(n551) );
CIVX2 U567 ( .A(n488), .Z(n462) );
CIVX2 U568 ( .A(n594), .Z(n463) );
CND2X2 U569 ( .A(n464), .B(n494), .Z(n594) );
CND2X2 U570 ( .A(n465), .B(n905), .Z(n464) );
CND2X2 U571 ( .A(n467), .B(n466), .Z(n465) );
CIVX2 U572 ( .A(n903), .Z(n467) );
CIVX2 U573 ( .A(n595), .Z(n468) );
CENX2 U574 ( .A(n908), .B(n469), .Z(n595) );
COND1X2 U575 ( .A(n382), .B(n491), .C(n470), .Z(n908) );
CND2X2 U576 ( .A(n471), .B(n635), .Z(n644) );
CND2X1 U577 ( .A(n471), .B(n414), .Z(n582) );
CENX1 U578 ( .A(n471), .B(n412), .Z(n591) );
CND2X2 U579 ( .A(n472), .B(n493), .Z(n533) );
CIVX2 U580 ( .A(n615), .Z(n472) );
CND3XL U581 ( .A(n474), .B(n587), .C(n473), .Z(n573) );
CND3X4 U582 ( .A(n473), .B(n530), .C(n587), .Z(n633) );
CIVX2 U583 ( .A(n474), .Z(n589) );
CND2X2 U584 ( .A(n505), .B(buffer_sel[0]), .Z(n474) );
CND2IXL U585 ( .B(n518), .A(n670), .Z(\qos/queue_gnt_q [1]) );
CIVX4 U586 ( .A(n475), .Z(n518) );
CND2X4 U587 ( .A(n505), .B(buffer_sel[1]), .Z(n475) );
CENX2 U588 ( .A(n661), .B(n476), .Z(n624) );
CND2IX1 U589 ( .B(n901), .A(n478), .Z(n477) );
CENX1 U590 ( .A(\qos/srv_cnt1_d[0] ), .B(n491), .Z(n901) );
CNR2X2 U591 ( .A(\qos/srv_cnt2_d [5]), .B(\qos/srv_cnt2_d [7]), .Z(n479) );
CIVX3 U592 ( .A(n621), .Z(n504) );
CND2X4 U593 ( .A(\qos/queue_gnt_q [2]), .B(n669), .Z(n642) );
CENX2 U594 ( .A(n485), .B(n626), .Z(n512) );
CND2X2 U595 ( .A(n484), .B(n483), .Z(n604) );
CIVX2 U596 ( .A(n626), .Z(n483) );
CIVX2 U597 ( .A(n485), .Z(n484) );
CND3X2 U598 ( .A(n569), .B(n486), .C(n545), .Z(n587) );
CND2X2 U599 ( .A(n487), .B(n553), .Z(n515) );
CND2X2 U600 ( .A(n552), .B(n551), .Z(n487) );
CIVX2 U601 ( .A(n666), .Z(n489) );
COND1X2 U602 ( .A(n608), .B(n642), .C(n490), .Z(n532) );
CND2X2 U603 ( .A(n642), .B(n607), .Z(n490) );
CND2X1 U604 ( .A(n492), .B(n569), .Z(n670) );
COND1X4 U605 ( .A(n518), .B(n492), .C(n669), .Z(n646) );
CND2X4 U606 ( .A(n546), .B(n544), .Z(n492) );
CIVX1 U607 ( .A(n614), .Z(n493) );
CND2X2 U608 ( .A(n615), .B(n614), .Z(n625) );
CND2X2 U609 ( .A(n497), .B(n496), .Z(n495) );
CIVX2 U610 ( .A(n437), .Z(n496) );
CIVX2 U611 ( .A(n650), .Z(n497) );
CNR2X4 U612 ( .A(n529), .B(n528), .Z(n662) );
CNIVX1 U613 ( .A(n646), .Z(n499) );
CND2X1 U614 ( .A(n642), .B(\qos/srv_cnt2_d [5]), .Z(n548) );
CIVX2 U615 ( .A(n501), .Z(n500) );
CND2X2 U616 ( .A(n452), .B(crcfifo1_empty), .Z(n501) );
CNR2IX2 U617 ( .B(n622), .A(n502), .Z(n535) );
CND2X2 U618 ( .A(n519), .B(n559), .Z(n502) );
CND2X4 U619 ( .A(n504), .B(n503), .Z(n519) );
CND2X1 U620 ( .A(n621), .B(n900), .Z(n622) );
CND2X4 U621 ( .A(n588), .B(n565), .Z(n505) );
CIVX2 U622 ( .A(n646), .Z(n506) );
CND2X4 U623 ( .A(n510), .B(n507), .Z(n903) );
CND2X2 U624 ( .A(n384), .B(n593), .Z(n509) );
CND2X2 U625 ( .A(n499), .B(n414), .Z(n510) );
CENX2 U626 ( .A(n512), .B(n625), .Z(n511) );
CND2X2 U627 ( .A(n515), .B(n514), .Z(n513) );
CNR2X4 U628 ( .A(n523), .B(n516), .Z(n656) );
CND2X2 U629 ( .A(n519), .B(n559), .Z(n540) );
CANR1X1 U630 ( .A(n622), .B(n519), .C(n559), .Z(n534) );
CND3X2 U631 ( .A(n566), .B(n575), .C(n574), .Z(n565) );
CND2X2 U632 ( .A(n461), .B(n596), .Z(n522) );
CND2X2 U633 ( .A(n543), .B(n539), .Z(n526) );
CNR2IX2 U634 ( .B(n450), .A(n633), .Z(n528) );
CND2X1 U635 ( .A(n904), .B(n532), .Z(n612) );
CIVX1 U636 ( .A(n532), .Z(n531) );
CNR2X4 U637 ( .A(n535), .B(n534), .Z(n537) );
CND2X2 U638 ( .A(n536), .B(n560), .Z(n538) );
CNR2X2 U639 ( .A(n540), .B(n542), .Z(n536) );
COND1X2 U640 ( .A(n542), .B(n541), .C(n540), .Z(n539) );
CIVX2 U641 ( .A(n560), .Z(n541) );
CND2X2 U642 ( .A(n533), .B(n625), .Z(n543) );
CMXI2X2 U643 ( .A0(n419), .A1(n634), .S(n633), .Z(n665) );
CIVX2 U644 ( .A(crcfifo1_empty), .Z(n545) );
CIVX2 U645 ( .A(n575), .Z(n570) );
CIVX2 U646 ( .A(n574), .Z(n549) );
CMXI2X1 U647 ( .A0(n616), .A1(n564), .S(n646), .Z(n664) );
CMXI2X2 U648 ( .A0(n378), .A1(n425), .S(n646), .Z(n910) );
CENX2 U649 ( .A(n550), .B(n555), .Z(n554) );
CENX2 U650 ( .A(n655), .B(n654), .Z(n550) );
CND2X2 U651 ( .A(n578), .B(n577), .Z(n556) );
CND4X2 U652 ( .A(n578), .B(n916), .C(n584), .D(n583), .Z(n558) );
CND2X1 U653 ( .A(n595), .B(n594), .Z(n596) );
CMXI2X2 U654 ( .A0(n643), .A1(n641), .S(n642), .Z(n913) );
CIVX8 U655 ( .A(n656), .Z(n914) );
CNR2IX2 U656 ( .B(arb_nxt), .A(crcfifo2_empty), .Z(n578) );
CNIVX4 U657 ( .A(n432), .Z(n620) );
CIVDX1 U658 ( .A(n433), .Z0(n562), .Z1(n563) );
CNIVX4 U659 ( .A(arb_nxt), .Z(n588) );
CIVX2 U660 ( .A(crcfifo2_empty), .Z(n567) );
CND2X1 U661 ( .A(crcfifo2_empty), .B(n570), .Z(n571) );
CIVDX2 U662 ( .A(n588), .Z0(n568), .Z1(n669) );
CIVX2 U663 ( .A(n576), .Z(n577) );
CIVX2 U664 ( .A(\qos/srv_cnt2_d [5]), .Z(n627) );
CIVX2 U665 ( .A(\qos/srv_cnt2_d [2]), .Z(n605) );
CIVX2 U666 ( .A(n605), .Z(n607) );
CND2X1 U667 ( .A(n607), .B(n445), .Z(n579) );
CND2X1 U668 ( .A(n424), .B(n620), .Z(n602) );
CNR2X2 U669 ( .A(n579), .B(n602), .Z(n629) );
CND2X1 U670 ( .A(n629), .B(n563), .Z(n580) );
CND2X1 U671 ( .A(n427), .B(n411), .Z(n581) );
CND2X2 U672 ( .A(n422), .B(\qos/srv_cnt1_d[0] ), .Z(n597) );
CND2X1 U673 ( .A(n417), .B(n448), .Z(n585) );
CND2X2 U674 ( .A(\qos/srv_cnt0_d [1]), .B(\qos/srv_cnt0_d [0]), .Z(n599) );
CNR2X2 U675 ( .A(n585), .B(n599), .Z(n632) );
CND2X1 U676 ( .A(n632), .B(n496), .Z(n586) );
CENX1 U677 ( .A(n450), .B(n586), .Z(n590) );
CENX1 U678 ( .A(n632), .B(n437), .Z(n592) );
CENX1 U679 ( .A(n629), .B(n562), .Z(n593) );
CIVX2 U680 ( .A(n597), .Z(n611) );
CND2X1 U681 ( .A(n611), .B(n427), .Z(n598) );
CIVX2 U682 ( .A(n599), .Z(n609) );
CND2X1 U683 ( .A(n609), .B(n417), .Z(n600) );
CENX1 U684 ( .A(n446), .B(n600), .Z(n601) );
CMXI2X1 U685 ( .A0(n446), .A1(n601), .S(n633), .Z(n663) );
CIVX1 U686 ( .A(n602), .Z(n606) );
CND2X1 U687 ( .A(n606), .B(\qos/srv_cnt2_d [2]), .Z(n603) );
CFA1X1 U688 ( .A(n906), .B(n663), .CI(n668), .CO(n626), .S(n615) );
CEOX1 U689 ( .A(n415), .B(n609), .Z(n610) );
CMXI2X2 U690 ( .A0(n415), .A1(n610), .S(n633), .Z(n904) );
CND2X1 U691 ( .A(n613), .B(n612), .Z(n614) );
CHA1X1 U692 ( .A(n664), .B(n909), .CO(n617), .S(n621) );
CIVXL U693 ( .A(\qos/srv_cnt0_d [1]), .Z(n618) );
CENXL U694 ( .A(n618), .B(\qos/srv_cnt0_d [0]), .Z(n619) );
CIVX1 U695 ( .A(\qos/srv_cnt0_d [0]), .Z(n623) );
CNR2X1 U696 ( .A(n562), .B(n627), .Z(n628) );
CND2X1 U697 ( .A(n629), .B(n628), .Z(n639) );
CENX1 U698 ( .A(n429), .B(n639), .Z(n630) );
CNR2X1 U699 ( .A(n437), .B(n450), .Z(n631) );
CND2X1 U700 ( .A(n632), .B(n631), .Z(n648) );
CENX1 U701 ( .A(n419), .B(n648), .Z(n634) );
CNR2X1 U702 ( .A(n412), .B(n434), .Z(n635) );
CEOX1 U703 ( .A(n439), .B(n644), .Z(n636) );
CNR2X1 U704 ( .A(n639), .B(n429), .Z(n640) );
CEOX1 U705 ( .A(n640), .B(n641), .Z(n643) );
CNR2X1 U706 ( .A(n644), .B(n439), .Z(n645) );
CENX1 U707 ( .A(n645), .B(n442), .Z(n647) );
CNR2X1 U708 ( .A(n648), .B(n419), .Z(n649) );
CEOX1 U709 ( .A(n649), .B(n431), .Z(n651) );
CMXI2X1 U710 ( .A0(n431), .A1(n651), .S(n650), .Z(n912) );
CEO3X2 U711 ( .A(n913), .B(n907), .C(n912), .Z(n655) );
COND1XL U712 ( .A(n665), .B(n666), .C(n383), .Z(n653) );
CND2XL U713 ( .A(n666), .B(n665), .Z(n652) );
CIVX2 U714 ( .A(crcfifo_pop), .Z(n660) );
CNR2X1 U715 ( .A(buffer_sel[0]), .B(buffer_sel[2]), .Z(n657) );
CNR2XL U716 ( .A(n660), .B(n673), .Z(crcfifo1_pull) );
CIVX2 U717 ( .A(pfifo_pop), .Z(n667) );
CNR2XL U718 ( .A(n667), .B(n673), .Z(pfifo_pop_1) );
CIVX1 U719 ( .A(buffer_sel[1]), .Z(n659) );
CNR2XL U720 ( .A(n660), .B(n671), .Z(crcfifo0_pull) );
CNR2XL U721 ( .A(n660), .B(n672), .Z(crcfifo2_pull) );
CNR2XL U722 ( .A(n667), .B(n672), .Z(pfifo_pop_2) );
CAN2X1 U723 ( .A(n914), .B(n661), .Z(n931) );
CAN2X1 U724 ( .A(n914), .B(n663), .Z(n921) );
CAN2X1 U725 ( .A(n914), .B(n404), .Z(n923) );
CAN2X1 U726 ( .A(n914), .B(n665), .Z(n933) );
CAN2X1 U727 ( .A(n914), .B(n666), .Z(n919) );
CAN2X1 U728 ( .A(n914), .B(n390), .Z(n925) );
CND2X1 U729 ( .A(pfifo_datain0[38]), .B(n561), .Z(n675) );
CANR2X1 U730 ( .A(n782), .B(pfifo_datain2[38]), .C(n376), .D(
pfifo_datain1[38]), .Z(n674) );
CND2X1 U731 ( .A(n675), .B(n674), .Z(pfifo_datain[38]) );
CND2X1 U732 ( .A(pfifo_datain0[27]), .B(n561), .Z(n677) );
CANR2X1 U733 ( .A(n782), .B(pfifo_datain2[27]), .C(n376), .D(
pfifo_datain1[27]), .Z(n676) );
CND2X1 U734 ( .A(n677), .B(n676), .Z(pfifo_datain[27]) );
CND2X1 U735 ( .A(pfifo_datain0[39]), .B(n561), .Z(n679) );
CANR2X1 U736 ( .A(n782), .B(pfifo_datain2[39]), .C(n376), .D(
pfifo_datain1[39]), .Z(n678) );
CND2X1 U737 ( .A(n679), .B(n678), .Z(pfifo_datain[39]) );
CND2X1 U738 ( .A(pfifo_datain0[31]), .B(n561), .Z(n681) );
CANR2X1 U739 ( .A(n782), .B(pfifo_datain2[31]), .C(n376), .D(
pfifo_datain1[31]), .Z(n680) );
CND2X1 U740 ( .A(n681), .B(n680), .Z(pfifo_datain[31]) );
CND2X1 U741 ( .A(pfifo_datain0[40]), .B(n561), .Z(n683) );
CANR2X1 U742 ( .A(n782), .B(pfifo_datain2[40]), .C(n376), .D(
pfifo_datain1[40]), .Z(n682) );
CND2X1 U743 ( .A(n683), .B(n682), .Z(pfifo_datain[40]) );
CND2X1 U744 ( .A(pfifo_datain0[35]), .B(n561), .Z(n685) );
CANR2X1 U745 ( .A(n782), .B(pfifo_datain2[35]), .C(n376), .D(
pfifo_datain1[35]), .Z(n684) );
CND2X1 U746 ( .A(n685), .B(n684), .Z(pfifo_datain[35]) );
CND2X1 U747 ( .A(pfifo_datain0[32]), .B(n561), .Z(n687) );
CANR2X1 U748 ( .A(n782), .B(pfifo_datain2[32]), .C(n376), .D(
pfifo_datain1[32]), .Z(n686) );
CND2X1 U749 ( .A(n687), .B(n686), .Z(pfifo_datain[32]) );
CND2X1 U750 ( .A(pfifo_datain0[28]), .B(n561), .Z(n689) );
CANR2X1 U751 ( .A(n782), .B(pfifo_datain2[28]), .C(n376), .D(
pfifo_datain1[28]), .Z(n688) );
CND2X1 U752 ( .A(n689), .B(n688), .Z(pfifo_datain[28]) );
CND2X1 U753 ( .A(pfifo_datain0[37]), .B(n561), .Z(n691) );
CANR2X1 U754 ( .A(n782), .B(pfifo_datain2[37]), .C(n376), .D(
pfifo_datain1[37]), .Z(n690) );
CND2X1 U755 ( .A(n691), .B(n690), .Z(pfifo_datain[37]) );
CND2X1 U756 ( .A(pfifo_datain0[33]), .B(n561), .Z(n693) );
CANR2X1 U757 ( .A(n782), .B(pfifo_datain2[33]), .C(n376), .D(
pfifo_datain1[33]), .Z(n692) );
CND2X1 U758 ( .A(n693), .B(n692), .Z(pfifo_datain[33]) );
CND2X1 U759 ( .A(pfifo_datain0[34]), .B(n561), .Z(n695) );
CANR2X1 U760 ( .A(n782), .B(pfifo_datain2[34]), .C(n376), .D(
pfifo_datain1[34]), .Z(n694) );
CND2X1 U761 ( .A(n695), .B(n694), .Z(pfifo_datain[34]) );
CND2X1 U762 ( .A(pfifo_datain0[21]), .B(n561), .Z(n697) );
CANR2X1 U763 ( .A(n782), .B(pfifo_datain2[21]), .C(n376), .D(
pfifo_datain1[21]), .Z(n696) );
CND2X1 U764 ( .A(n697), .B(n696), .Z(pfifo_datain[21]) );
CND2X1 U765 ( .A(pfifo_datain0[23]), .B(n561), .Z(n699) );
CANR2X1 U766 ( .A(n782), .B(pfifo_datain2[23]), .C(n376), .D(
pfifo_datain1[23]), .Z(n698) );
CND2X1 U767 ( .A(n699), .B(n698), .Z(pfifo_datain[23]) );
CND2X1 U768 ( .A(pfifo_datain0[16]), .B(n561), .Z(n701) );
CANR2X1 U769 ( .A(n782), .B(pfifo_datain2[16]), .C(n376), .D(
pfifo_datain1[16]), .Z(n700) );
CND2X1 U770 ( .A(n701), .B(n700), .Z(pfifo_datain[16]) );
CND2X1 U771 ( .A(pfifo_datain0[26]), .B(n561), .Z(n703) );
CANR2X1 U772 ( .A(n782), .B(pfifo_datain2[26]), .C(n376), .D(
pfifo_datain1[26]), .Z(n702) );
CND2X1 U773 ( .A(n703), .B(n702), .Z(pfifo_datain[26]) );
CND2X1 U774 ( .A(pfifo_datain0[14]), .B(n561), .Z(n705) );
CANR2X1 U775 ( .A(n782), .B(pfifo_datain2[14]), .C(n376), .D(
pfifo_datain1[14]), .Z(n704) );
CND2X1 U776 ( .A(n705), .B(n704), .Z(pfifo_datain[14]) );
CND2X1 U777 ( .A(pfifo_datain0[13]), .B(n561), .Z(n707) );
CANR2X1 U778 ( .A(n782), .B(pfifo_datain2[13]), .C(n376), .D(
pfifo_datain1[13]), .Z(n706) );
CND2X1 U779 ( .A(n707), .B(n706), .Z(pfifo_datain[13]) );
CND2X1 U780 ( .A(pfifo_datain0[18]), .B(n561), .Z(n709) );
CANR2X1 U781 ( .A(n782), .B(pfifo_datain2[18]), .C(n376), .D(
pfifo_datain1[18]), .Z(n708) );
CND2X1 U782 ( .A(n709), .B(n708), .Z(pfifo_datain[18]) );
CND2X1 U783 ( .A(pfifo_datain0[22]), .B(n561), .Z(n711) );
CANR2X1 U784 ( .A(n782), .B(pfifo_datain2[22]), .C(n376), .D(
pfifo_datain1[22]), .Z(n710) );
CND2X1 U785 ( .A(n711), .B(n710), .Z(pfifo_datain[22]) );
CND2X1 U786 ( .A(pfifo_datain0[20]), .B(n561), .Z(n713) );
CANR2X1 U787 ( .A(n782), .B(pfifo_datain2[20]), .C(n376), .D(
pfifo_datain1[20]), .Z(n712) );
CND2X1 U788 ( .A(n713), .B(n712), .Z(pfifo_datain[20]) );
CND2X1 U789 ( .A(pfifo_datain0[15]), .B(n561), .Z(n715) );
CANR2X1 U790 ( .A(n782), .B(pfifo_datain2[15]), .C(n376), .D(
pfifo_datain1[15]), .Z(n714) );
CND2X1 U791 ( .A(n715), .B(n714), .Z(pfifo_datain[15]) );
CND2X1 U792 ( .A(pfifo_datain0[12]), .B(n561), .Z(n717) );
CANR2X1 U793 ( .A(n782), .B(pfifo_datain2[12]), .C(n376), .D(
pfifo_datain1[12]), .Z(n716) );
CND2X1 U794 ( .A(n717), .B(n716), .Z(pfifo_datain[12]) );
CND2X1 U795 ( .A(pfifo_datain0[17]), .B(n561), .Z(n719) );
CANR2X1 U796 ( .A(n782), .B(pfifo_datain2[17]), .C(n376), .D(
pfifo_datain1[17]), .Z(n718) );
CND2X1 U797 ( .A(n719), .B(n718), .Z(pfifo_datain[17]) );
CND2X1 U798 ( .A(pfifo_datain_ctrl_0[5]), .B(n561), .Z(n721) );
CANR2X1 U799 ( .A(n782), .B(pfifo_datain_ctrl_2[5]), .C(n376), .D(
pfifo_datain_ctrl_1[5]), .Z(n720) );
CND2X1 U800 ( .A(n721), .B(n720), .Z(pfifo_datain_ctrl[5]) );
CND2X1 U801 ( .A(pfifo_datain_ctrl_0[10]), .B(n561), .Z(n723) );
CANR2X1 U802 ( .A(n782), .B(pfifo_datain_ctrl_2[10]), .C(n376), .D(
pfifo_datain_ctrl_1[10]), .Z(n722) );
CND2X1 U803 ( .A(n723), .B(n722), .Z(pfifo_datain_ctrl[10]) );
CND2X1 U804 ( .A(pfifo_datain_ctrl_0[7]), .B(n561), .Z(n725) );
CANR2X1 U805 ( .A(n782), .B(pfifo_datain_ctrl_2[7]), .C(n376), .D(
pfifo_datain_ctrl_1[7]), .Z(n724) );
CND2X1 U806 ( .A(n725), .B(n724), .Z(pfifo_datain_ctrl[7]) );
CND2X1 U807 ( .A(pfifo_datain_ctrl_0[8]), .B(n561), .Z(n727) );
CANR2X1 U808 ( .A(n782), .B(pfifo_datain_ctrl_2[8]), .C(n376), .D(
pfifo_datain_ctrl_1[8]), .Z(n726) );
CND2X1 U809 ( .A(n727), .B(n726), .Z(pfifo_datain_ctrl[8]) );
CND2X1 U810 ( .A(pfifo_datain_ctrl_0[9]), .B(n561), .Z(n729) );
CANR2X1 U811 ( .A(n782), .B(pfifo_datain_ctrl_2[9]), .C(n376), .D(
pfifo_datain_ctrl_1[9]), .Z(n728) );
CND2X1 U812 ( .A(n729), .B(n728), .Z(pfifo_datain_ctrl[9]) );
CND2X1 U813 ( .A(pfifo_datain_ctrl_0[3]), .B(n561), .Z(n731) );
CANR2X1 U814 ( .A(n782), .B(pfifo_datain_ctrl_2[3]), .C(n376), .D(
pfifo_datain_ctrl_1[3]), .Z(n730) );
CND2X1 U815 ( .A(n731), .B(n730), .Z(pfifo_datain_ctrl[3]) );
CND2X1 U816 ( .A(pfifo_datain0[25]), .B(n561), .Z(n733) );
CANR2X1 U817 ( .A(n782), .B(pfifo_datain2[25]), .C(n376), .D(
pfifo_datain1[25]), .Z(n732) );
CND2X1 U818 ( .A(n733), .B(n732), .Z(pfifo_datain[25]) );
CND2X1 U819 ( .A(pfifo_datain_ctrl_0[1]), .B(n561), .Z(n735) );
CANR2X1 U820 ( .A(n782), .B(pfifo_datain_ctrl_2[1]), .C(n376), .D(
pfifo_datain_ctrl_1[1]), .Z(n734) );
CND2X1 U821 ( .A(n735), .B(n734), .Z(pfifo_datain_ctrl[1]) );
CND2X1 U822 ( .A(pfifo_datain0[63]), .B(n561), .Z(n737) );
CANR2X1 U823 ( .A(n782), .B(pfifo_datain2[63]), .C(n376), .D(
pfifo_datain1[63]), .Z(n736) );
CND2X1 U824 ( .A(n737), .B(n736), .Z(pfifo_datain[63]) );
CND2X1 U825 ( .A(pfifo_datain_ctrl_0[4]), .B(n561), .Z(n739) );
CANR2X1 U826 ( .A(n782), .B(pfifo_datain_ctrl_2[4]), .C(n376), .D(
pfifo_datain_ctrl_1[4]), .Z(n738) );
CND2X1 U827 ( .A(n739), .B(n738), .Z(pfifo_datain_ctrl[4]) );
CND2X1 U828 ( .A(pfifo_datain_ctrl_0[2]), .B(n561), .Z(n741) );
CANR2X1 U829 ( .A(n782), .B(pfifo_datain_ctrl_2[2]), .C(n376), .D(
pfifo_datain_ctrl_1[2]), .Z(n740) );
CND2X1 U830 ( .A(n741), .B(n740), .Z(pfifo_datain_ctrl[2]) );
CND2X1 U831 ( .A(pfifo_datain0[47]), .B(n561), .Z(n743) );
CANR2X1 U832 ( .A(n782), .B(pfifo_datain2[47]), .C(n376), .D(
pfifo_datain1[47]), .Z(n742) );
CND2X1 U833 ( .A(n743), .B(n742), .Z(pfifo_datain[47]) );
CND2X1 U834 ( .A(pfifo_datain_ctrl_0[6]), .B(n561), .Z(n745) );
CANR2X1 U835 ( .A(n782), .B(pfifo_datain_ctrl_2[6]), .C(n376), .D(
pfifo_datain_ctrl_1[6]), .Z(n744) );
CND2X1 U836 ( .A(n745), .B(n744), .Z(pfifo_datain_ctrl[6]) );
CND2X1 U837 ( .A(pfifo_datain_ctrl_0[0]), .B(n561), .Z(n747) );
CANR2X1 U838 ( .A(n782), .B(pfifo_datain_ctrl_2[0]), .C(n376), .D(
pfifo_datain_ctrl_1[0]), .Z(n746) );
CND2X1 U839 ( .A(n747), .B(n746), .Z(pfifo_datain_ctrl[0]) );
CND2X1 U840 ( .A(pfifo_datain_ctrl_0[11]), .B(n561), .Z(n749) );
CANR2X1 U841 ( .A(n782), .B(pfifo_datain_ctrl_2[11]), .C(n376), .D(
pfifo_datain_ctrl_1[11]), .Z(n748) );
CND2X1 U842 ( .A(n749), .B(n748), .Z(pfifo_datain_ctrl[11]) );
CND2X1 U843 ( .A(pfifo_datain0[41]), .B(n561), .Z(n751) );
CANR2X1 U844 ( .A(n782), .B(pfifo_datain2[41]), .C(n376), .D(
pfifo_datain1[41]), .Z(n750) );
CND2X1 U845 ( .A(n751), .B(n750), .Z(pfifo_datain[41]) );
CND2X1 U846 ( .A(pfifo_datain0[30]), .B(n561), .Z(n753) );
CANR2X1 U847 ( .A(n782), .B(pfifo_datain2[30]), .C(n376), .D(
pfifo_datain1[30]), .Z(n752) );
CND2X1 U848 ( .A(n753), .B(n752), .Z(pfifo_datain[30]) );
CND2X1 U849 ( .A(pfifo_datain0[19]), .B(n561), .Z(n755) );
CANR2X1 U850 ( .A(n782), .B(pfifo_datain2[19]), .C(n376), .D(
pfifo_datain1[19]), .Z(n754) );
CND2X1 U851 ( .A(n755), .B(n754), .Z(pfifo_datain[19]) );
CND2X1 U852 ( .A(pfifo_datain0[42]), .B(n561), .Z(n757) );
CANR2X1 U853 ( .A(n782), .B(pfifo_datain2[42]), .C(n376), .D(
pfifo_datain1[42]), .Z(n756) );
CND2X1 U854 ( .A(n757), .B(n756), .Z(pfifo_datain[42]) );
CND2X1 U855 ( .A(pfifo_datain0[36]), .B(n561), .Z(n759) );
CANR2X1 U856 ( .A(n782), .B(pfifo_datain2[36]), .C(n376), .D(
pfifo_datain1[36]), .Z(n758) );
CND2X1 U857 ( .A(n759), .B(n758), .Z(pfifo_datain[36]) );
CND2X1 U858 ( .A(pfifo_datain0[29]), .B(n561), .Z(n761) );
CANR2X1 U859 ( .A(n782), .B(pfifo_datain2[29]), .C(n376), .D(
pfifo_datain1[29]), .Z(n760) );
CND2X1 U860 ( .A(n761), .B(n760), .Z(pfifo_datain[29]) );
CND2X1 U861 ( .A(pfifo_datain0[59]), .B(n561), .Z(n763) );
CANR2X1 U862 ( .A(n782), .B(pfifo_datain2[59]), .C(n376), .D(
pfifo_datain1[59]), .Z(n762) );
CND2X1 U863 ( .A(n763), .B(n762), .Z(pfifo_datain[59]) );
CND2X1 U864 ( .A(pfifo_datain0[57]), .B(n561), .Z(n765) );
CANR2X1 U865 ( .A(n782), .B(pfifo_datain2[57]), .C(n376), .D(
pfifo_datain1[57]), .Z(n764) );
CND2X1 U866 ( .A(n765), .B(n764), .Z(pfifo_datain[57]) );
CND2X1 U867 ( .A(pfifo_datain0[56]), .B(n561), .Z(n767) );
CANR2X1 U868 ( .A(n782), .B(pfifo_datain2[56]), .C(n376), .D(
pfifo_datain1[56]), .Z(n766) );
CND2X1 U869 ( .A(n767), .B(n766), .Z(pfifo_datain[56]) );
CND2X1 U870 ( .A(pfifo_datain0[58]), .B(n561), .Z(n769) );
CANR2X1 U871 ( .A(n782), .B(pfifo_datain2[58]), .C(n376), .D(
pfifo_datain1[58]), .Z(n768) );
CND2X1 U872 ( .A(n769), .B(n768), .Z(pfifo_datain[58]) );
CND2X1 U873 ( .A(pfifo_datain0[24]), .B(n561), .Z(n771) );
CANR2X1 U874 ( .A(n782), .B(pfifo_datain2[24]), .C(n376), .D(
pfifo_datain1[24]), .Z(n770) );
CND2X1 U875 ( .A(n771), .B(n770), .Z(pfifo_datain[24]) );
CND2X1 U876 ( .A(pfifo_datain0[62]), .B(n561), .Z(n773) );
CANR2X1 U877 ( .A(n782), .B(pfifo_datain2[62]), .C(n376), .D(
pfifo_datain1[62]), .Z(n772) );
CND2X1 U878 ( .A(n773), .B(n772), .Z(pfifo_datain[62]) );
CND2X1 U879 ( .A(pfifo_datain0[61]), .B(n561), .Z(n775) );
CANR2X1 U880 ( .A(n782), .B(pfifo_datain2[61]), .C(n376), .D(
pfifo_datain1[61]), .Z(n774) );
CND2X1 U881 ( .A(n775), .B(n774), .Z(pfifo_datain[61]) );
CND2X1 U882 ( .A(pfifo_datain0[48]), .B(n561), .Z(n777) );
CANR2X1 U883 ( .A(n782), .B(pfifo_datain2[48]), .C(n376), .D(
pfifo_datain1[48]), .Z(n776) );
CND2X1 U884 ( .A(n777), .B(n776), .Z(pfifo_datain[48]) );
CND2X1 U885 ( .A(pfifo_datain0[46]), .B(n561), .Z(n779) );
CANR2X1 U886 ( .A(n782), .B(pfifo_datain2[46]), .C(n376), .D(
pfifo_datain1[46]), .Z(n778) );
CND2X1 U887 ( .A(n779), .B(n778), .Z(pfifo_datain[46]) );
CND2X1 U888 ( .A(pfifo_datain0[45]), .B(n561), .Z(n781) );
CANR2X1 U889 ( .A(n782), .B(pfifo_datain2[45]), .C(n376), .D(
pfifo_datain1[45]), .Z(n780) );
CND2X1 U890 ( .A(n781), .B(n780), .Z(pfifo_datain[45]) );
CND2X1 U891 ( .A(pfifo_datain0[60]), .B(n561), .Z(n784) );
CANR2X1 U892 ( .A(n782), .B(pfifo_datain2[60]), .C(n376), .D(
pfifo_datain1[60]), .Z(n783) );
CND2X1 U893 ( .A(n784), .B(n783), .Z(pfifo_datain[60]) );
CND2X1 U894 ( .A(pfifo_datain0[43]), .B(n561), .Z(n786) );
CANR2X1 U895 ( .A(n782), .B(pfifo_datain2[43]), .C(n376), .D(
pfifo_datain1[43]), .Z(n785) );
CND2X1 U896 ( .A(n786), .B(n785), .Z(pfifo_datain[43]) );
CND2X1 U897 ( .A(pfifo_datain0[55]), .B(n561), .Z(n788) );
CANR2X1 U898 ( .A(n782), .B(pfifo_datain2[55]), .C(n376), .D(
pfifo_datain1[55]), .Z(n787) );
CND2X1 U899 ( .A(n788), .B(n787), .Z(pfifo_datain[55]) );
CND2X1 U900 ( .A(pfifo_datain0[54]), .B(n561), .Z(n790) );
CANR2X1 U901 ( .A(n782), .B(pfifo_datain2[54]), .C(n376), .D(
pfifo_datain1[54]), .Z(n789) );
CND2X1 U902 ( .A(n790), .B(n789), .Z(pfifo_datain[54]) );
CND2X1 U903 ( .A(pfifo_datain0[53]), .B(n561), .Z(n792) );
CANR2X1 U904 ( .A(n782), .B(pfifo_datain2[53]), .C(n376), .D(
pfifo_datain1[53]), .Z(n791) );
CND2X1 U905 ( .A(n792), .B(n791), .Z(pfifo_datain[53]) );
CND2X1 U906 ( .A(pfifo_datain0[52]), .B(n561), .Z(n794) );
CANR2X1 U907 ( .A(n782), .B(pfifo_datain2[52]), .C(n376), .D(
pfifo_datain1[52]), .Z(n793) );
CND2X1 U908 ( .A(n794), .B(n793), .Z(pfifo_datain[52]) );
CND2X1 U909 ( .A(pfifo_datain0[51]), .B(n561), .Z(n796) );
CANR2X1 U910 ( .A(n782), .B(pfifo_datain2[51]), .C(n376), .D(
pfifo_datain1[51]), .Z(n795) );
CND2X1 U911 ( .A(n796), .B(n795), .Z(pfifo_datain[51]) );
CND2X1 U912 ( .A(pfifo_datain0[44]), .B(n561), .Z(n798) );
CANR2X1 U913 ( .A(n782), .B(pfifo_datain2[44]), .C(n376), .D(
pfifo_datain1[44]), .Z(n797) );
CND2X1 U914 ( .A(n798), .B(n797), .Z(pfifo_datain[44]) );
CND2X1 U915 ( .A(pfifo_datain0[50]), .B(n561), .Z(n800) );
CANR2X1 U916 ( .A(n782), .B(pfifo_datain2[50]), .C(n376), .D(
pfifo_datain1[50]), .Z(n799) );
CND2X1 U917 ( .A(n800), .B(n799), .Z(pfifo_datain[50]) );
CND2X1 U918 ( .A(pfifo_datain0[49]), .B(n561), .Z(n802) );
CANR2X1 U919 ( .A(n782), .B(pfifo_datain2[49]), .C(n376), .D(
pfifo_datain1[49]), .Z(n801) );
CND2X1 U920 ( .A(n802), .B(n801), .Z(pfifo_datain[49]) );
CND2X1 U921 ( .A(pfifo_datain0[11]), .B(n561), .Z(n804) );
CANR2X1 U922 ( .A(n782), .B(pfifo_datain2[11]), .C(n376), .D(
pfifo_datain1[11]), .Z(n803) );
CND2X1 U923 ( .A(n804), .B(n803), .Z(pfifo_datain[11]) );
CND2X1 U924 ( .A(pfifo_datain0[10]), .B(n561), .Z(n806) );
CANR2X1 U925 ( .A(n782), .B(pfifo_datain2[10]), .C(n376), .D(
pfifo_datain1[10]), .Z(n805) );
CND2X1 U926 ( .A(n806), .B(n805), .Z(pfifo_datain[10]) );
CND2X1 U927 ( .A(pfifo_datain0[9]), .B(n561), .Z(n808) );
CANR2X1 U928 ( .A(n782), .B(pfifo_datain2[9]), .C(n376), .D(pfifo_datain1[9]), .Z(n807) );
CND2X1 U929 ( .A(n808), .B(n807), .Z(pfifo_datain[9]) );
CND2X1 U930 ( .A(pfifo_datain0[8]), .B(n561), .Z(n810) );
CANR2X1 U931 ( .A(n782), .B(pfifo_datain2[8]), .C(n376), .D(pfifo_datain1[8]), .Z(n809) );
CND2X1 U932 ( .A(n810), .B(n809), .Z(pfifo_datain[8]) );
CND2X1 U933 ( .A(pfifo_datain0[7]), .B(n561), .Z(n812) );
CANR2X1 U934 ( .A(n782), .B(pfifo_datain2[7]), .C(n376), .D(pfifo_datain1[7]), .Z(n811) );
CND2X1 U935 ( .A(n812), .B(n811), .Z(pfifo_datain[7]) );
CND2X1 U936 ( .A(pfifo_datain0[6]), .B(n561), .Z(n814) );
CANR2X1 U937 ( .A(n782), .B(pfifo_datain2[6]), .C(n376), .D(pfifo_datain1[6]), .Z(n813) );
CND2X1 U938 ( .A(n814), .B(n813), .Z(pfifo_datain[6]) );
CND2X1 U939 ( .A(pfifo_datain_ctrl_0[14]), .B(n561), .Z(n816) );
CANR2X1 U940 ( .A(n782), .B(pfifo_datain_ctrl_2[14]), .C(n376), .D(
pfifo_datain_ctrl_1[14]), .Z(n815) );
CND2X1 U941 ( .A(n816), .B(n815), .Z(pfifo_datain_ctrl[14]) );
CND2X1 U942 ( .A(pfifo_datain0[5]), .B(n561), .Z(n818) );
CANR2X1 U943 ( .A(n782), .B(pfifo_datain2[5]), .C(n376), .D(pfifo_datain1[5]), .Z(n817) );
CND2X1 U944 ( .A(n818), .B(n817), .Z(pfifo_datain[5]) );
CND2X1 U945 ( .A(pfifo_datain0[4]), .B(n561), .Z(n820) );
CANR2X1 U946 ( .A(n782), .B(pfifo_datain2[4]), .C(n376), .D(pfifo_datain1[4]), .Z(n819) );
CND2X1 U947 ( .A(n820), .B(n819), .Z(pfifo_datain[4]) );
CND2X1 U948 ( .A(pfifo_datain0[3]), .B(n561), .Z(n822) );
CANR2X1 U949 ( .A(n782), .B(pfifo_datain2[3]), .C(n376), .D(pfifo_datain1[3]), .Z(n821) );
CND2X1 U950 ( .A(n822), .B(n821), .Z(pfifo_datain[3]) );
CND2X1 U951 ( .A(pfifo_datain0[2]), .B(n561), .Z(n824) );
CANR2X1 U952 ( .A(n782), .B(pfifo_datain2[2]), .C(n376), .D(pfifo_datain1[2]), .Z(n823) );
CND2X1 U953 ( .A(n824), .B(n823), .Z(pfifo_datain[2]) );
CND2X1 U954 ( .A(pfifo_datain0[1]), .B(n561), .Z(n826) );
CANR2X1 U955 ( .A(n782), .B(pfifo_datain2[1]), .C(n376), .D(pfifo_datain1[1]), .Z(n825) );
CND2X1 U956 ( .A(n826), .B(n825), .Z(pfifo_datain[1]) );
CND2X1 U957 ( .A(pfifo_datain0[0]), .B(n561), .Z(n828) );
CANR2X1 U958 ( .A(n782), .B(pfifo_datain2[0]), .C(n376), .D(pfifo_datain1[0]), .Z(n827) );
CND2X1 U959 ( .A(n828), .B(n827), .Z(pfifo_datain[0]) );
CND2X1 U960 ( .A(pfifo_datain_ctrl_0[15]), .B(n561), .Z(n830) );
CANR2X1 U961 ( .A(n782), .B(pfifo_datain_ctrl_2[15]), .C(n376), .D(
pfifo_datain_ctrl_1[15]), .Z(n829) );
CND2X1 U962 ( .A(n830), .B(n829), .Z(pfifo_datain_ctrl[15]) );
CND2X1 U963 ( .A(pfifo_datain_ctrl_0[13]), .B(n561), .Z(n832) );
CANR2X1 U964 ( .A(n782), .B(pfifo_datain_ctrl_2[13]), .C(n376), .D(
pfifo_datain_ctrl_1[13]), .Z(n831) );
CND2X1 U965 ( .A(n832), .B(n831), .Z(pfifo_datain_ctrl[13]) );
CND2X1 U966 ( .A(pfifo_datain_ctrl_0[12]), .B(n561), .Z(n834) );
CANR2X1 U967 ( .A(n782), .B(pfifo_datain_ctrl_2[12]), .C(n376), .D(
pfifo_datain_ctrl_1[12]), .Z(n833) );
CND2X1 U968 ( .A(n834), .B(n833), .Z(pfifo_datain_ctrl[12]) );
CND2X1 U969 ( .A(crcfifo0_dataout[31]), .B(n561), .Z(n836) );
CANR2X1 U970 ( .A(n782), .B(crcfifo2_dataout[31]), .C(n376), .D(
crcfifo1_dataout[31]), .Z(n835) );
CND2X1 U971 ( .A(n836), .B(n835), .Z(crcfifo_dataout[31]) );
CND2X1 U972 ( .A(crcfifo0_dataout[30]), .B(n561), .Z(n838) );
CANR2X1 U973 ( .A(n782), .B(crcfifo2_dataout[30]), .C(n376), .D(
crcfifo1_dataout[30]), .Z(n837) );
CND2X1 U974 ( .A(n838), .B(n837), .Z(crcfifo_dataout[30]) );
CND2X1 U975 ( .A(crcfifo0_dataout[29]), .B(n561), .Z(n840) );
CANR2X1 U976 ( .A(n782), .B(crcfifo2_dataout[29]), .C(n376), .D(
crcfifo1_dataout[29]), .Z(n839) );
CND2X1 U977 ( .A(n840), .B(n839), .Z(crcfifo_dataout[29]) );
CND2X1 U978 ( .A(crcfifo0_dataout[28]), .B(n561), .Z(n842) );
CANR2X1 U979 ( .A(n782), .B(crcfifo2_dataout[28]), .C(n376), .D(
crcfifo1_dataout[28]), .Z(n841) );
CND2X1 U980 ( .A(n842), .B(n841), .Z(crcfifo_dataout[28]) );
CND2X1 U981 ( .A(crcfifo0_dataout[27]), .B(n561), .Z(n844) );
CANR2X1 U982 ( .A(n782), .B(crcfifo2_dataout[27]), .C(n376), .D(
crcfifo1_dataout[27]), .Z(n843) );
CND2X1 U983 ( .A(n844), .B(n843), .Z(crcfifo_dataout[27]) );
CND2X1 U984 ( .A(crcfifo0_dataout[26]), .B(n561), .Z(n846) );
CANR2X1 U985 ( .A(n782), .B(crcfifo2_dataout[26]), .C(n376), .D(
crcfifo1_dataout[26]), .Z(n845) );
CND2X1 U986 ( .A(n846), .B(n845), .Z(crcfifo_dataout[26]) );
CND2X1 U987 ( .A(crcfifo0_dataout[25]), .B(n561), .Z(n848) );
CANR2X1 U988 ( .A(n782), .B(crcfifo2_dataout[25]), .C(n376), .D(
crcfifo1_dataout[25]), .Z(n847) );
CND2X1 U989 ( .A(n848), .B(n847), .Z(crcfifo_dataout[25]) );
CND2X1 U990 ( .A(crcfifo0_dataout[24]), .B(n561), .Z(n850) );
CANR2X1 U991 ( .A(n782), .B(crcfifo2_dataout[24]), .C(n376), .D(
crcfifo1_dataout[24]), .Z(n849) );
CND2X1 U992 ( .A(n850), .B(n849), .Z(crcfifo_dataout[24]) );
CND2X1 U993 ( .A(crcfifo0_dataout[23]), .B(n561), .Z(n852) );
CANR2X1 U994 ( .A(n782), .B(crcfifo2_dataout[23]), .C(n376), .D(
crcfifo1_dataout[23]), .Z(n851) );
CND2X1 U995 ( .A(n852), .B(n851), .Z(crcfifo_dataout[23]) );
CND2X1 U996 ( .A(crcfifo0_dataout[22]), .B(n561), .Z(n854) );
CANR2X1 U997 ( .A(n782), .B(crcfifo2_dataout[22]), .C(n376), .D(
crcfifo1_dataout[22]), .Z(n853) );
CND2X1 U998 ( .A(n854), .B(n853), .Z(crcfifo_dataout[22]) );
CND2X1 U999 ( .A(crcfifo0_dataout[21]), .B(n561), .Z(n856) );
CANR2X1 U1000 ( .A(n782), .B(crcfifo2_dataout[21]), .C(n376), .D(
crcfifo1_dataout[21]), .Z(n855) );
CND2X1 U1001 ( .A(n856), .B(n855), .Z(crcfifo_dataout[21]) );
CND2X1 U1002 ( .A(crcfifo0_dataout[20]), .B(n561), .Z(n858) );
CANR2X1 U1003 ( .A(n782), .B(crcfifo2_dataout[20]), .C(n376), .D(
crcfifo1_dataout[20]), .Z(n857) );
CND2X1 U1004 ( .A(n858), .B(n857), .Z(crcfifo_dataout[20]) );
CND2X1 U1005 ( .A(crcfifo0_dataout[19]), .B(n561), .Z(n860) );
CANR2X1 U1006 ( .A(n782), .B(crcfifo2_dataout[19]), .C(n376), .D(
crcfifo1_dataout[19]), .Z(n859) );
CND2X1 U1007 ( .A(n860), .B(n859), .Z(crcfifo_dataout[19]) );
CND2X1 U1008 ( .A(crcfifo0_dataout[18]), .B(n561), .Z(n862) );
CANR2X1 U1009 ( .A(n782), .B(crcfifo2_dataout[18]), .C(n376), .D(
crcfifo1_dataout[18]), .Z(n861) );
CND2X1 U1010 ( .A(n862), .B(n861), .Z(crcfifo_dataout[18]) );
CND2X1 U1011 ( .A(crcfifo0_dataout[17]), .B(n561), .Z(n864) );
CANR2X1 U1012 ( .A(n782), .B(crcfifo2_dataout[17]), .C(n376), .D(
crcfifo1_dataout[17]), .Z(n863) );
CND2X1 U1013 ( .A(n864), .B(n863), .Z(crcfifo_dataout[17]) );
CND2X1 U1014 ( .A(crcfifo0_dataout[16]), .B(n561), .Z(n866) );
CANR2X1 U1015 ( .A(n782), .B(crcfifo2_dataout[16]), .C(n376), .D(
crcfifo1_dataout[16]), .Z(n865) );
CND2X1 U1016 ( .A(n866), .B(n865), .Z(crcfifo_dataout[16]) );
CND2X1 U1017 ( .A(crcfifo0_dataout[15]), .B(n561), .Z(n868) );
CANR2X1 U1018 ( .A(n782), .B(crcfifo2_dataout[15]), .C(n376), .D(
crcfifo1_dataout[15]), .Z(n867) );
CND2X1 U1019 ( .A(n868), .B(n867), .Z(crcfifo_dataout[15]) );
CND2X1 U1020 ( .A(crcfifo0_dataout[14]), .B(n561), .Z(n870) );
CANR2X1 U1021 ( .A(n782), .B(crcfifo2_dataout[14]), .C(n376), .D(
crcfifo1_dataout[14]), .Z(n869) );
CND2X1 U1022 ( .A(n870), .B(n869), .Z(crcfifo_dataout[14]) );
CND2X1 U1023 ( .A(crcfifo0_dataout[13]), .B(n561), .Z(n872) );
CANR2X1 U1024 ( .A(n782), .B(crcfifo2_dataout[13]), .C(n376), .D(
crcfifo1_dataout[13]), .Z(n871) );
CND2X1 U1025 ( .A(n872), .B(n871), .Z(crcfifo_dataout[13]) );
CND2X1 U1026 ( .A(crcfifo0_dataout[12]), .B(n561), .Z(n874) );
CANR2X1 U1027 ( .A(n782), .B(crcfifo2_dataout[12]), .C(n376), .D(
crcfifo1_dataout[12]), .Z(n873) );
CND2X1 U1028 ( .A(n874), .B(n873), .Z(crcfifo_dataout[12]) );
CND2X1 U1029 ( .A(crcfifo0_dataout[11]), .B(n561), .Z(n876) );
CANR2X1 U1030 ( .A(n782), .B(crcfifo2_dataout[11]), .C(n376), .D(
crcfifo1_dataout[11]), .Z(n875) );
CND2X1 U1031 ( .A(n876), .B(n875), .Z(crcfifo_dataout[11]) );
CND2X1 U1032 ( .A(crcfifo0_dataout[10]), .B(n561), .Z(n878) );
CANR2X1 U1033 ( .A(n782), .B(crcfifo2_dataout[10]), .C(n376), .D(
crcfifo1_dataout[10]), .Z(n877) );
CND2X1 U1034 ( .A(n878), .B(n877), .Z(crcfifo_dataout[10]) );
CND2X1 U1035 ( .A(crcfifo0_dataout[9]), .B(n561), .Z(n880) );
CANR2X1 U1036 ( .A(n782), .B(crcfifo2_dataout[9]), .C(n376), .D(
crcfifo1_dataout[9]), .Z(n879) );
CND2X1 U1037 ( .A(n880), .B(n879), .Z(crcfifo_dataout[9]) );
CND2X1 U1038 ( .A(crcfifo0_dataout[8]), .B(n561), .Z(n883) );
CANR2X1 U1039 ( .A(n782), .B(crcfifo2_dataout[8]), .C(n376), .D(
crcfifo1_dataout[8]), .Z(n882) );
CND2X1 U1040 ( .A(n883), .B(n882), .Z(crcfifo_dataout[8]) );
CND2X1 U1041 ( .A(crcfifo0_dataout[7]), .B(n561), .Z(n885) );
CANR2X1 U1042 ( .A(n782), .B(crcfifo2_dataout[7]), .C(n376), .D(
crcfifo1_dataout[7]), .Z(n884) );
CND2X1 U1043 ( .A(n885), .B(n884), .Z(crcfifo_dataout[7]) );
CND2X1 U1044 ( .A(crcfifo0_dataout[6]), .B(n561), .Z(n887) );
CANR2X1 U1045 ( .A(n782), .B(crcfifo2_dataout[6]), .C(n376), .D(
crcfifo1_dataout[6]), .Z(n886) );
CND2X1 U1046 ( .A(n887), .B(n886), .Z(crcfifo_dataout[6]) );
CND2X1 U1047 ( .A(crcfifo0_dataout[5]), .B(n561), .Z(n889) );
CANR2X1 U1048 ( .A(n782), .B(crcfifo2_dataout[5]), .C(n376), .D(
crcfifo1_dataout[5]), .Z(n888) );
CND2X1 U1049 ( .A(n889), .B(n888), .Z(crcfifo_dataout[5]) );
CND2X1 U1050 ( .A(crcfifo0_dataout[4]), .B(n561), .Z(n891) );
CANR2X1 U1051 ( .A(n782), .B(crcfifo2_dataout[4]), .C(n376), .D(
crcfifo1_dataout[4]), .Z(n890) );
CND2X1 U1052 ( .A(n891), .B(n890), .Z(crcfifo_dataout[4]) );
CND2X1 U1053 ( .A(crcfifo0_dataout[3]), .B(n561), .Z(n893) );
CANR2X1 U1054 ( .A(n782), .B(crcfifo2_dataout[3]), .C(n376), .D(
crcfifo1_dataout[3]), .Z(n892) );
CND2X1 U1055 ( .A(n893), .B(n892), .Z(crcfifo_dataout[3]) );
CND2X1 U1056 ( .A(crcfifo0_dataout[2]), .B(n561), .Z(n895) );
CANR2X1 U1057 ( .A(n782), .B(crcfifo2_dataout[2]), .C(n376), .D(
crcfifo1_dataout[2]), .Z(n894) );
CND2X1 U1058 ( .A(n895), .B(n894), .Z(crcfifo_dataout[2]) );
CND2X1 U1059 ( .A(crcfifo0_dataout[1]), .B(n561), .Z(n897) );
CANR2X1 U1060 ( .A(n782), .B(crcfifo2_dataout[1]), .C(n376), .D(
crcfifo1_dataout[1]), .Z(n896) );
CND2X1 U1061 ( .A(n897), .B(n896), .Z(crcfifo_dataout[1]) );
CND2X1 U1062 ( .A(crcfifo0_dataout[0]), .B(n561), .Z(n899) );
CANR2X1 U1063 ( .A(n782), .B(crcfifo2_dataout[0]), .C(n376), .D(
crcfifo1_dataout[0]), .Z(n898) );
CND2X1 U1064 ( .A(n899), .B(n898), .Z(crcfifo_dataout[0]) );
CAN2X1 U1065 ( .A(n914), .B(n900), .Z(n920) );
CAN2X1 U1066 ( .A(n914), .B(n901), .Z(n927) );
CAN2X1 U1067 ( .A(n914), .B(n902), .Z(n939) );
CAN2X1 U1068 ( .A(n914), .B(n903), .Z(n936) );
CAN2X1 U1069 ( .A(n914), .B(n904), .Z(n926) );
CAN2X1 U1070 ( .A(n914), .B(n905), .Z(n938) );
CAN2X1 U1071 ( .A(n914), .B(n375), .Z(n937) );
CAN2X1 U1072 ( .A(n914), .B(n907), .Z(n930) );
CAN2X1 U1073 ( .A(n914), .B(n383), .Z(n929) );
CAN2X1 U1074 ( .A(n914), .B(n908), .Z(n928) );
CAN2X1 U1075 ( .A(n914), .B(n909), .Z(n934) );
CAN2X1 U1076 ( .A(n914), .B(n454), .Z(n918) );
CAN2X1 U1077 ( .A(n914), .B(n911), .Z(n924) );
CAN2X1 U1078 ( .A(n914), .B(n912), .Z(n922) );
CIVX2 U1079 ( .A(n915), .Z(\qos/N33 ) );
CND3XL U1080 ( .A(n451), .B(n916), .C(crcfifo2_empty), .Z(start_transmit) );
endmodule | module queue_selection ( \clks.clk , \clks.rst , arb_nxt, pfifo_datain0,
pfifo_datain1, pfifo_datain2, crcfifo0_dataout, crcfifo1_dataout,
crcfifo2_dataout, pfifo_datain_ctrl_0, pfifo_datain_ctrl_1,
pfifo_datain_ctrl_2, crcfifo0_empty, crcfifo1_empty, crcfifo2_empty,
pfifo_pop, crcfifo_pop, crcfifo0_pull, crcfifo1_pull, crcfifo2_pull,
pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1,
pcfifo_pop_2, pfifo_datain, pfifo_datain_ctrl, crcfifo_dataout,
start_transmit ); |
input [63:0] pfifo_datain0;
input [63:0] pfifo_datain1;
input [63:0] pfifo_datain2;
input [31:0] crcfifo0_dataout;
input [31:0] crcfifo1_dataout;
input [31:0] crcfifo2_dataout;
input [15:0] pfifo_datain_ctrl_0;
input [15:0] pfifo_datain_ctrl_1;
input [15:0] pfifo_datain_ctrl_2;
output [63:0] pfifo_datain;
output [15:0] pfifo_datain_ctrl;
output [31:0] crcfifo_dataout;
input \clks.clk , \clks.rst , arb_nxt, crcfifo0_empty, crcfifo1_empty,
crcfifo2_empty, pfifo_pop, crcfifo_pop;
output crcfifo0_pull, crcfifo1_pull, crcfifo2_pull, pfifo_pop_0, pfifo_pop_1,
pfifo_pop_2, pcfifo_pop_0, pcfifo_pop_1, pcfifo_pop_2, start_transmit;
wire pfifo_pop_0, pfifo_pop_1, pfifo_pop_2, \qos/N33 , \qos/N31 ,
\qos/srv_cnt1_d[0] , n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940;
wire [2:0] buffer_sel;
wire [2:0] \qos/queue_gnt_q ;
wire [7:0] \qos/srv_cnt2_d ;
wire [7:0] \qos/srv_cnt0_d ;
assign pcfifo_pop_0 = pfifo_pop_0;
assign pcfifo_pop_1 = pfifo_pop_1;
assign pcfifo_pop_2 = pfifo_pop_2;
CFD2QX1 \qos/srv_cnt2_d_reg[5] ( .D(\qos/N31 ), .CP(\clks.clk ), .CD(
\clks.rst ), .Q(\qos/srv_cnt2_d [5]) );
CFD2QXL \qos/queue_gnt_d_reg[2] ( .D(n481), .CP(\clks.clk ), .CD(\clks.rst ), .Q(buffer_sel[2]) );
CFD2QXL \qos/srv_cnt1_d_reg[0] ( .D(n927), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt1_d[0] ) );
CFD2QX1 \qos/srv_cnt2_d_reg[7] ( .D(\qos/N33 ), .CP(\clks.clk ), .CD(
\clks.rst ), .Q(\qos/srv_cnt2_d [7]) );
CFD2QXL \qos/srv_cnt0_d_reg[1] ( .D(n920), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt0_d [1]) );
CFD2QXL \qos/srv_cnt0_d_reg[0] ( .D(n931), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt0_d [0]) );
CFD2QX2 \qos/srv_cnt2_d_reg[2] ( .D(n935), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(\qos/srv_cnt2_d [2]) );
CFD2X2 \qos/srv_cnt0_d_reg[5] ( .D(n932), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n449), .QN(n450) );
CFD2X2 \qos/srv_cnt0_d_reg[3] ( .D(n921), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n447), .QN(n446) );
CFD2X2 \qos/srv_cnt2_d_reg[3] ( .D(n925), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n445), .QN(n381) );
CFD2X2 \qos/srv_cnt1_d_reg[7] ( .D(n930), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n443), .QN(n442) );
CFD2X2 \qos/srv_cnt1_d_reg[6] ( .D(n929), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n440), .QN(n439) );
CFD2X2 \qos/srv_cnt0_d_reg[4] ( .D(n938), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n438), .QN(n437) );
CFD2X2 \qos/srv_cnt1_d_reg[5] ( .D(n928), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n435), .QN(n434) );
CFD2X2 \qos/srv_cnt2_d_reg[4] ( .D(n924), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n433) );
CFD2X2 \qos/srv_cnt2_d_reg[0] ( .D(n939), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n432) );
CFD2X2 \qos/srv_cnt0_d_reg[7] ( .D(n922), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n430), .QN(n431) );
CFD2X2 \qos/srv_cnt2_d_reg[6] ( .D(n919), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n428), .QN(n429) );
CFD2X2 \qos/srv_cnt1_d_reg[2] ( .D(n918), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n426), .QN(n425) );
CFD2X2 \qos/srv_cnt2_d_reg[1] ( .D(n934), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n424), .QN(n423) );
CFD2X2 \qos/srv_cnt1_d_reg[1] ( .D(n923), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n421), .QN(n420) );
CFD2X2 \qos/srv_cnt0_d_reg[6] ( .D(n933), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n418), .QN(n419) );
CFD2X2 \qos/srv_cnt0_d_reg[2] ( .D(n926), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n416), .QN(n415) );
CFD2X2 \qos/srv_cnt1_d_reg[4] ( .D(n936), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n413), .QN(n412) );
CFD2X2 \qos/srv_cnt1_d_reg[3] ( .D(n937), .CP(\clks.clk ), .CD(\clks.rst ),
.Q(n410), .QN(n409) );
CFD2QXL \qos/queue_gnt_d_reg[1] ( .D(\qos/queue_gnt_q [1]), .CP(\clks.clk ),
.CD(\clks.rst ), .Q(buffer_sel[1]) );
CFD4X1 \qos/queue_gnt_d_reg[0] ( .D(n917), .CP(\clks.clk ), .SD(\clks.rst ),
.Q(n940), .QN(buffer_sel[0]) );
CNIVXL U434 ( .A(n913), .Z(n456) );
CND3XL U435 ( .A(n659), .B(n658), .C(buffer_sel[0]), .Z(n671) );
CENX1 U436 ( .A(n521), .B(n522), .Z(n520) );
CENX1 U437 ( .A(n623), .B(n650), .Z(n661) );
CIVX2 U438 ( .A(n403), .Z(n559) );
CND2XL U439 ( .A(n903), .B(n911), .Z(n494) );
CMX2X1 U440 ( .A0(\qos/srv_cnt0_d [1]), .A1(n619), .S(n650), .Z(n900) );
CNIVX1 U441 ( .A(n910), .Z(n453) );
CMX2X1 U442 ( .A0(n441), .A1(n636), .S(n517), .Z(n383) );
CND2X2 U443 ( .A(n495), .B(n498), .Z(n905) );
CENX1 U444 ( .A(n620), .B(n385), .Z(n902) );
CND2X1 U445 ( .A(n650), .B(n592), .Z(n498) );
CND2X1 U446 ( .A(n491), .B(n436), .Z(n470) );
CND2X1 U447 ( .A(n591), .B(n506), .Z(n507) );
CND2X2 U448 ( .A(n572), .B(n669), .Z(n473) );
CND3X2 U449 ( .A(n584), .B(n583), .C(n545), .Z(n544) );
CND2X1 U450 ( .A(n575), .B(n574), .Z(n583) );
CND2X2 U451 ( .A(n524), .B(n554), .Z(n523) );
CNIVXL U452 ( .A(n906), .Z(n375) );
CIVXL U453 ( .A(\qos/srv_cnt2_d [7]), .Z(n641) );
CEOXL U454 ( .A(n606), .B(n605), .Z(n608) );
CIVX4 U455 ( .A(n568), .Z(n569) );
CIVX4 U456 ( .A(n673), .Z(n376) );
CND2XL U457 ( .A(n657), .B(buffer_sel[1]), .Z(n673) );
CIVX4 U458 ( .A(n672), .Z(n782) );
CEOX1 U459 ( .A(n627), .B(n580), .Z(n377) );
CEOXL U460 ( .A(n611), .B(n425), .Z(n378) );
CENX1 U461 ( .A(n409), .B(n598), .Z(n379) );
CAN2X2 U462 ( .A(n400), .B(n479), .Z(n380) );
CNIVX1 U463 ( .A(crcfifo1_empty), .Z(n916) );
CENX1 U464 ( .A(n434), .B(n582), .Z(n382) );
CIVDX1 U465 ( .A(n642), .Z0(n384), .Z1(n385) );
CIVX2 U466 ( .A(n604), .Z(n521) );
CIVX1 U467 ( .A(n902), .Z(n478) );
CIVX12 U468 ( .A(n671), .Z(n561) );
CND2X1 U469 ( .A(n459), .B(n458), .Z(n457) );
CIVX2 U470 ( .A(n900), .Z(n503) );
CIVX1 U471 ( .A(n389), .Z(n390) );
CND2IX1 U472 ( .B(n480), .A(n481), .Z(n547) );
CIVX1 U473 ( .A(n573), .Z(n917) );
CNR2XL U474 ( .A(n667), .B(n671), .Z(pfifo_pop_0) );
CIVX1 U475 ( .A(buffer_sel[2]), .Z(n658) );
CND2X4 U476 ( .A(n500), .B(n486), .Z(n546) );
CNIVX2 U477 ( .A(n646), .Z(n491) );
CNR2X2 U478 ( .A(n386), .B(n617), .Z(n542) );
CND2X2 U479 ( .A(n386), .B(n617), .Z(n560) );
CENX2 U480 ( .A(n904), .B(n455), .Z(n386) );
CIVX3 U481 ( .A(n552), .Z(n555) );
CND2X2 U482 ( .A(n388), .B(n488), .Z(n552) );
CENX2 U483 ( .A(n489), .B(n387), .Z(n488) );
CENX2 U484 ( .A(n383), .B(n665), .Z(n387) );
CIVX2 U485 ( .A(n527), .Z(n388) );
CND2X2 U486 ( .A(n638), .B(n637), .Z(n527) );
CND2X2 U487 ( .A(n547), .B(n548), .Z(n460) );
CND3X1 U488 ( .A(n940), .B(n659), .C(buffer_sel[2]), .Z(n672) );
CMXI2X2 U489 ( .A0(n630), .A1(n429), .S(n642), .Z(n666) );
CNIVX1 U490 ( .A(\qos/queue_gnt_q [2]), .Z(n481) );
CIVXL U491 ( .A(n668), .Z(n389) );
CMXI2X1 U492 ( .A0(n391), .A1(n381), .S(n642), .Z(n668) );
CENX1 U493 ( .A(n381), .B(n603), .Z(n391) );
CND3X4 U494 ( .A(n394), .B(n393), .C(n392), .Z(n574) );
CNR2X4 U495 ( .A(n438), .B(n430), .Z(n392) );
CND4X4 U496 ( .A(n398), .B(n575), .C(n380), .D(n574), .Z(n576) );
CENX4 U497 ( .A(n905), .B(n482), .Z(n485) );
CND2X2 U498 ( .A(n398), .B(n380), .Z(n566) );
CNR2X2 U499 ( .A(n416), .B(n447), .Z(n393) );
CNR2X2 U500 ( .A(n449), .B(n418), .Z(n394) );
CND4X4 U501 ( .A(n397), .B(n396), .C(n395), .D(n564), .Z(n575) );
CNR2X2 U502 ( .A(n413), .B(n443), .Z(n395) );
CNR2X2 U503 ( .A(n440), .B(n410), .Z(n396) );
CNR2X2 U504 ( .A(n435), .B(n426), .Z(n397) );
CIVX3 U505 ( .A(n399), .Z(n398) );
CND2X2 U506 ( .A(n402), .B(n401), .Z(n399) );
CNR2X2 U507 ( .A(n428), .B(\qos/srv_cnt2_d [2]), .Z(n400) );
CNR2X2 U508 ( .A(n445), .B(n424), .Z(n401) );
CNR2X2 U509 ( .A(n432), .B(n433), .Z(n402) );
CIVX2 U510 ( .A(n421), .Z(n564) );
CND2X2 U511 ( .A(n901), .B(n902), .Z(n403) );
CND2X2 U512 ( .A(n403), .B(n477), .Z(n476) );
CND3X2 U513 ( .A(n513), .B(n511), .C(n520), .Z(n516) );
CNR2X2 U514 ( .A(n597), .B(n581), .Z(n471) );
CEOXL U515 ( .A(n564), .B(\qos/srv_cnt1_d[0] ), .Z(n616) );
CNIVXL U516 ( .A(n664), .Z(n404) );
CNR2X1 U517 ( .A(n408), .B(n531), .Z(n935) );
CNR2X1 U518 ( .A(n408), .B(n458), .Z(n932) );
CIVX3 U519 ( .A(n914), .Z(n408) );
CIVX2 U520 ( .A(n662), .Z(n458) );
CAN3X2 U521 ( .A(n587), .B(n530), .C(n473), .Z(n405) );
CND2X4 U522 ( .A(n589), .B(n569), .Z(n530) );
CMXI2X1 U523 ( .A0(n406), .A1(n423), .S(n642), .Z(n909) );
CEOXL U524 ( .A(n423), .B(n620), .Z(n406) );
CIVX2 U525 ( .A(n914), .Z(n407) );
CIVX2 U526 ( .A(n646), .Z(n517) );
CNR2IX2 U527 ( .B(n460), .A(n407), .Z(\qos/N31 ) );
CND2X2 U528 ( .A(n914), .B(n456), .Z(n915) );
CIVX2 U529 ( .A(n409), .Z(n411) );
CIVX2 U530 ( .A(n412), .Z(n414) );
CIVX2 U531 ( .A(n415), .Z(n417) );
CIVX2 U532 ( .A(n420), .Z(n422) );
CIVX2 U533 ( .A(n425), .Z(n427) );
CIVX2 U534 ( .A(n434), .Z(n436) );
CIVX2 U535 ( .A(n439), .Z(n441) );
CIVX2 U536 ( .A(n442), .Z(n444) );
CIVX2 U537 ( .A(n446), .Z(n448) );
CIVX2 U538 ( .A(n911), .Z(n466) );
CND2X4 U539 ( .A(n509), .B(n508), .Z(n911) );
COND1X2 U540 ( .A(n571), .B(n501), .C(n584), .Z(n572) );
CND2X4 U541 ( .A(n452), .B(n549), .Z(n584) );
CIVDX2 U542 ( .A(crcfifo0_empty), .Z0(n452), .Z1(n451) );
CND2X1 U543 ( .A(n569), .B(n377), .Z(n480) );
CENX4 U544 ( .A(n911), .B(n903), .Z(n482) );
CND2X1 U545 ( .A(n642), .B(n563), .Z(n508) );
CNIVX1 U546 ( .A(n453), .Z(n454) );
CMX2X1 U547 ( .A0(n444), .A1(n647), .S(n506), .Z(n907) );
CND2X1 U548 ( .A(n653), .B(n652), .Z(n654) );
CNR2X4 U549 ( .A(n567), .B(n576), .Z(n486) );
CND3X4 U550 ( .A(n537), .B(n538), .C(n624), .Z(n525) );
COND1X1 U551 ( .A(n532), .B(n904), .C(n453), .Z(n613) );
CNR2IX2 U552 ( .B(n590), .A(n405), .Z(n529) );
CNR2X4 U553 ( .A(n525), .B(n526), .Z(n524) );
CMXI2X2 U554 ( .A0(n379), .A1(n409), .S(n646), .Z(n906) );
CENX2 U555 ( .A(n532), .B(n910), .Z(n455) );
CND2X4 U556 ( .A(n505), .B(buffer_sel[2]), .Z(n557) );
CND3X4 U557 ( .A(n558), .B(n557), .C(n556), .Z(\qos/queue_gnt_q [2]) );
CNIVX4 U558 ( .A(n633), .Z(n650) );
CND2X1 U559 ( .A(n460), .B(n662), .Z(n637) );
CND2X2 U560 ( .A(n457), .B(n908), .Z(n638) );
CIVXL U561 ( .A(n460), .Z(n459) );
CENX2 U562 ( .A(n662), .B(n460), .Z(n469) );
CND3X2 U563 ( .A(n552), .B(n551), .C(n461), .Z(n514) );
CND2X4 U564 ( .A(n468), .B(n463), .Z(n461) );
CIVX2 U565 ( .A(n461), .Z(n553) );
CND2X2 U566 ( .A(n462), .B(n527), .Z(n551) );
CIVX2 U567 ( .A(n488), .Z(n462) );
CIVX2 U568 ( .A(n594), .Z(n463) );
CND2X2 U569 ( .A(n464), .B(n494), .Z(n594) );
CND2X2 U570 ( .A(n465), .B(n905), .Z(n464) );
CND2X2 U571 ( .A(n467), .B(n466), .Z(n465) );
CIVX2 U572 ( .A(n903), .Z(n467) );
CIVX2 U573 ( .A(n595), .Z(n468) );
CENX2 U574 ( .A(n908), .B(n469), .Z(n595) );
COND1X2 U575 ( .A(n382), .B(n491), .C(n470), .Z(n908) );
CND2X2 U576 ( .A(n471), .B(n635), .Z(n644) );
CND2X1 U577 ( .A(n471), .B(n414), .Z(n582) );
CENX1 U578 ( .A(n471), .B(n412), .Z(n591) );
CND2X2 U579 ( .A(n472), .B(n493), .Z(n533) );
CIVX2 U580 ( .A(n615), .Z(n472) );
CND3XL U581 ( .A(n474), .B(n587), .C(n473), .Z(n573) );
CND3X4 U582 ( .A(n473), .B(n530), .C(n587), .Z(n633) );
CIVX2 U583 ( .A(n474), .Z(n589) );
CND2X2 U584 ( .A(n505), .B(buffer_sel[0]), .Z(n474) );
CND2IXL U585 ( .B(n518), .A(n670), .Z(\qos/queue_gnt_q [1]) );
CIVX4 U586 ( .A(n475), .Z(n518) );
CND2X4 U587 ( .A(n505), .B(buffer_sel[1]), .Z(n475) );
CENX2 U588 ( .A(n661), .B(n476), .Z(n624) );
CND2IX1 U589 ( .B(n901), .A(n478), .Z(n477) );
CENX1 U590 ( .A(\qos/srv_cnt1_d[0] ), .B(n491), .Z(n901) );
CNR2X2 U591 ( .A(\qos/srv_cnt2_d [5]), .B(\qos/srv_cnt2_d [7]), .Z(n479) );
CIVX3 U592 ( .A(n621), .Z(n504) );
CND2X4 U593 ( .A(\qos/queue_gnt_q [2]), .B(n669), .Z(n642) );
CENX2 U594 ( .A(n485), .B(n626), .Z(n512) );
CND2X2 U595 ( .A(n484), .B(n483), .Z(n604) );
CIVX2 U596 ( .A(n626), .Z(n483) );
CIVX2 U597 ( .A(n485), .Z(n484) );
CND3X2 U598 ( .A(n569), .B(n486), .C(n545), .Z(n587) );
CND2X2 U599 ( .A(n487), .B(n553), .Z(n515) );
CND2X2 U600 ( .A(n552), .B(n551), .Z(n487) );
CIVX2 U601 ( .A(n666), .Z(n489) );
COND1X2 U602 ( .A(n608), .B(n642), .C(n490), .Z(n532) );
CND2X2 U603 ( .A(n642), .B(n607), .Z(n490) );
CND2X1 U604 ( .A(n492), .B(n569), .Z(n670) );
COND1X4 U605 ( .A(n518), .B(n492), .C(n669), .Z(n646) );
CND2X4 U606 ( .A(n546), .B(n544), .Z(n492) );
CIVX1 U607 ( .A(n614), .Z(n493) );
CND2X2 U608 ( .A(n615), .B(n614), .Z(n625) );
CND2X2 U609 ( .A(n497), .B(n496), .Z(n495) );
CIVX2 U610 ( .A(n437), .Z(n496) );
CIVX2 U611 ( .A(n650), .Z(n497) );
CNR2X4 U612 ( .A(n529), .B(n528), .Z(n662) );
CNIVX1 U613 ( .A(n646), .Z(n499) );
CND2X1 U614 ( .A(n642), .B(\qos/srv_cnt2_d [5]), .Z(n548) );
CIVX2 U615 ( .A(n501), .Z(n500) );
CND2X2 U616 ( .A(n452), .B(crcfifo1_empty), .Z(n501) );
CNR2IX2 U617 ( .B(n622), .A(n502), .Z(n535) );
CND2X2 U618 ( .A(n519), .B(n559), .Z(n502) );
CND2X4 U619 ( .A(n504), .B(n503), .Z(n519) );
CND2X1 U620 ( .A(n621), .B(n900), .Z(n622) );
CND2X4 U621 ( .A(n588), .B(n565), .Z(n505) );
CIVX2 U622 ( .A(n646), .Z(n506) );
CND2X4 U623 ( .A(n510), .B(n507), .Z(n903) );
CND2X2 U624 ( .A(n384), .B(n593), .Z(n509) );
CND2X2 U625 ( .A(n499), .B(n414), .Z(n510) );
CENX2 U626 ( .A(n512), .B(n625), .Z(n511) );
CND2X2 U627 ( .A(n515), .B(n514), .Z(n513) );
CNR2X4 U628 ( .A(n523), .B(n516), .Z(n656) );
CND2X2 U629 ( .A(n519), .B(n559), .Z(n540) );
CANR1X1 U630 ( .A(n622), .B(n519), .C(n559), .Z(n534) );
CND3X2 U631 ( .A(n566), .B(n575), .C(n574), .Z(n565) );
CND2X2 U632 ( .A(n461), .B(n596), .Z(n522) );
CND2X2 U633 ( .A(n543), .B(n539), .Z(n526) );
CNR2IX2 U634 ( .B(n450), .A(n633), .Z(n528) );
CND2X1 U635 ( .A(n904), .B(n532), .Z(n612) );
CIVX1 U636 ( .A(n532), .Z(n531) );
CNR2X4 U637 ( .A(n535), .B(n534), .Z(n537) );
CND2X2 U638 ( .A(n536), .B(n560), .Z(n538) );
CNR2X2 U639 ( .A(n540), .B(n542), .Z(n536) );
COND1X2 U640 ( .A(n542), .B(n541), .C(n540), .Z(n539) );
CIVX2 U641 ( .A(n560), .Z(n541) );
CND2X2 U642 ( .A(n533), .B(n625), .Z(n543) );
CMXI2X2 U643 ( .A0(n419), .A1(n634), .S(n633), .Z(n665) );
CIVX2 U644 ( .A(crcfifo1_empty), .Z(n545) );
CIVX2 U645 ( .A(n575), .Z(n570) );
CIVX2 U646 ( .A(n574), .Z(n549) );
CMXI2X1 U647 ( .A0(n616), .A1(n564), .S(n646), .Z(n664) );
CMXI2X2 U648 ( .A0(n378), .A1(n425), .S(n646), .Z(n910) );
CENX2 U649 ( .A(n550), .B(n555), .Z(n554) );
CENX2 U650 ( .A(n655), .B(n654), .Z(n550) );
CND2X2 U651 ( .A(n578), .B(n577), .Z(n556) );
CND4X2 U652 ( .A(n578), .B(n916), .C(n584), .D(n583), .Z(n558) );
CND2X1 U653 ( .A(n595), .B(n594), .Z(n596) );
CMXI2X2 U654 ( .A0(n643), .A1(n641), .S(n642), .Z(n913) );
CIVX8 U655 ( .A(n656), .Z(n914) );
CNR2IX2 U656 ( .B(arb_nxt), .A(crcfifo2_empty), .Z(n578) );
CNIVX4 U657 ( .A(n432), .Z(n620) );
CIVDX1 U658 ( .A(n433), .Z0(n562), .Z1(n563) );
CNIVX4 U659 ( .A(arb_nxt), .Z(n588) );
CIVX2 U660 ( .A(crcfifo2_empty), .Z(n567) );
CND2X1 U661 ( .A(crcfifo2_empty), .B(n570), .Z(n571) );
CIVDX2 U662 ( .A(n588), .Z0(n568), .Z1(n669) );
CIVX2 U663 ( .A(n576), .Z(n577) );
CIVX2 U664 ( .A(\qos/srv_cnt2_d [5]), .Z(n627) );
CIVX2 U665 ( .A(\qos/srv_cnt2_d [2]), .Z(n605) );
CIVX2 U666 ( .A(n605), .Z(n607) );
CND2X1 U667 ( .A(n607), .B(n445), .Z(n579) );
CND2X1 U668 ( .A(n424), .B(n620), .Z(n602) );
CNR2X2 U669 ( .A(n579), .B(n602), .Z(n629) );
CND2X1 U670 ( .A(n629), .B(n563), .Z(n580) );
CND2X1 U671 ( .A(n427), .B(n411), .Z(n581) );
CND2X2 U672 ( .A(n422), .B(\qos/srv_cnt1_d[0] ), .Z(n597) );
CND2X1 U673 ( .A(n417), .B(n448), .Z(n585) );
CND2X2 U674 ( .A(\qos/srv_cnt0_d [1]), .B(\qos/srv_cnt0_d [0]), .Z(n599) );
CNR2X2 U675 ( .A(n585), .B(n599), .Z(n632) );
CND2X1 U676 ( .A(n632), .B(n496), .Z(n586) );
CENX1 U677 ( .A(n450), .B(n586), .Z(n590) );
CENX1 U678 ( .A(n632), .B(n437), .Z(n592) );
CENX1 U679 ( .A(n629), .B(n562), .Z(n593) );
CIVX2 U680 ( .A(n597), .Z(n611) );
CND2X1 U681 ( .A(n611), .B(n427), .Z(n598) );
CIVX2 U682 ( .A(n599), .Z(n609) );
CND2X1 U683 ( .A(n609), .B(n417), .Z(n600) );
CENX1 U684 ( .A(n446), .B(n600), .Z(n601) );
CMXI2X1 U685 ( .A0(n446), .A1(n601), .S(n633), .Z(n663) );
CIVX1 U686 ( .A(n602), .Z(n606) );
CND2X1 U687 ( .A(n606), .B(\qos/srv_cnt2_d [2]), .Z(n603) );
CFA1X1 U688 ( .A(n906), .B(n663), .CI(n668), .CO(n626), .S(n615) );
CEOX1 U689 ( .A(n415), .B(n609), .Z(n610) );
CMXI2X2 U690 ( .A0(n415), .A1(n610), .S(n633), .Z(n904) );
CND2X1 U691 ( .A(n613), .B(n612), .Z(n614) );
CHA1X1 U692 ( .A(n664), .B(n909), .CO(n617), .S(n621) );
CIVXL U693 ( .A(\qos/srv_cnt0_d [1]), .Z(n618) );
CENXL U694 ( .A(n618), .B(\qos/srv_cnt0_d [0]), .Z(n619) );
CIVX1 U695 ( .A(\qos/srv_cnt0_d [0]), .Z(n623) );
CNR2X1 U696 ( .A(n562), .B(n627), .Z(n628) );
CND2X1 U697 ( .A(n629), .B(n628), .Z(n639) );
CENX1 U698 ( .A(n429), .B(n639), .Z(n630) );
CNR2X1 U699 ( .A(n437), .B(n450), .Z(n631) );
CND2X1 U700 ( .A(n632), .B(n631), .Z(n648) );
CENX1 U701 ( .A(n419), .B(n648), .Z(n634) );
CNR2X1 U702 ( .A(n412), .B(n434), .Z(n635) );
CEOX1 U703 ( .A(n439), .B(n644), .Z(n636) );
CNR2X1 U704 ( .A(n639), .B(n429), .Z(n640) );
CEOX1 U705 ( .A(n640), .B(n641), .Z(n643) );
CNR2X1 U706 ( .A(n644), .B(n439), .Z(n645) );
CENX1 U707 ( .A(n645), .B(n442), .Z(n647) );
CNR2X1 U708 ( .A(n648), .B(n419), .Z(n649) );
CEOX1 U709 ( .A(n649), .B(n431), .Z(n651) );
CMXI2X1 U710 ( .A0(n431), .A1(n651), .S(n650), .Z(n912) );
CEO3X2 U711 ( .A(n913), .B(n907), .C(n912), .Z(n655) );
COND1XL U712 ( .A(n665), .B(n666), .C(n383), .Z(n653) );
CND2XL U713 ( .A(n666), .B(n665), .Z(n652) );
CIVX2 U714 ( .A(crcfifo_pop), .Z(n660) );
CNR2X1 U715 ( .A(buffer_sel[0]), .B(buffer_sel[2]), .Z(n657) );
CNR2XL U716 ( .A(n660), .B(n673), .Z(crcfifo1_pull) );
CIVX2 U717 ( .A(pfifo_pop), .Z(n667) );
CNR2XL U718 ( .A(n667), .B(n673), .Z(pfifo_pop_1) );
CIVX1 U719 ( .A(buffer_sel[1]), .Z(n659) );
CNR2XL U720 ( .A(n660), .B(n671), .Z(crcfifo0_pull) );
CNR2XL U721 ( .A(n660), .B(n672), .Z(crcfifo2_pull) );
CNR2XL U722 ( .A(n667), .B(n672), .Z(pfifo_pop_2) );
CAN2X1 U723 ( .A(n914), .B(n661), .Z(n931) );
CAN2X1 U724 ( .A(n914), .B(n663), .Z(n921) );
CAN2X1 U725 ( .A(n914), .B(n404), .Z(n923) );
CAN2X1 U726 ( .A(n914), .B(n665), .Z(n933) );
CAN2X1 U727 ( .A(n914), .B(n666), .Z(n919) );
CAN2X1 U728 ( .A(n914), .B(n390), .Z(n925) );
CND2X1 U729 ( .A(pfifo_datain0[38]), .B(n561), .Z(n675) );
CANR2X1 U730 ( .A(n782), .B(pfifo_datain2[38]), .C(n376), .D(
pfifo_datain1[38]), .Z(n674) );
CND2X1 U731 ( .A(n675), .B(n674), .Z(pfifo_datain[38]) );
CND2X1 U732 ( .A(pfifo_datain0[27]), .B(n561), .Z(n677) );
CANR2X1 U733 ( .A(n782), .B(pfifo_datain2[27]), .C(n376), .D(
pfifo_datain1[27]), .Z(n676) );
CND2X1 U734 ( .A(n677), .B(n676), .Z(pfifo_datain[27]) );
CND2X1 U735 ( .A(pfifo_datain0[39]), .B(n561), .Z(n679) );
CANR2X1 U736 ( .A(n782), .B(pfifo_datain2[39]), .C(n376), .D(
pfifo_datain1[39]), .Z(n678) );
CND2X1 U737 ( .A(n679), .B(n678), .Z(pfifo_datain[39]) );
CND2X1 U738 ( .A(pfifo_datain0[31]), .B(n561), .Z(n681) );
CANR2X1 U739 ( .A(n782), .B(pfifo_datain2[31]), .C(n376), .D(
pfifo_datain1[31]), .Z(n680) );
CND2X1 U740 ( .A(n681), .B(n680), .Z(pfifo_datain[31]) );
CND2X1 U741 ( .A(pfifo_datain0[40]), .B(n561), .Z(n683) );
CANR2X1 U742 ( .A(n782), .B(pfifo_datain2[40]), .C(n376), .D(
pfifo_datain1[40]), .Z(n682) );
CND2X1 U743 ( .A(n683), .B(n682), .Z(pfifo_datain[40]) );
CND2X1 U744 ( .A(pfifo_datain0[35]), .B(n561), .Z(n685) );
CANR2X1 U745 ( .A(n782), .B(pfifo_datain2[35]), .C(n376), .D(
pfifo_datain1[35]), .Z(n684) );
CND2X1 U746 ( .A(n685), .B(n684), .Z(pfifo_datain[35]) );
CND2X1 U747 ( .A(pfifo_datain0[32]), .B(n561), .Z(n687) );
CANR2X1 U748 ( .A(n782), .B(pfifo_datain2[32]), .C(n376), .D(
pfifo_datain1[32]), .Z(n686) );
CND2X1 U749 ( .A(n687), .B(n686), .Z(pfifo_datain[32]) );
CND2X1 U750 ( .A(pfifo_datain0[28]), .B(n561), .Z(n689) );
CANR2X1 U751 ( .A(n782), .B(pfifo_datain2[28]), .C(n376), .D(
pfifo_datain1[28]), .Z(n688) );
CND2X1 U752 ( .A(n689), .B(n688), .Z(pfifo_datain[28]) );
CND2X1 U753 ( .A(pfifo_datain0[37]), .B(n561), .Z(n691) );
CANR2X1 U754 ( .A(n782), .B(pfifo_datain2[37]), .C(n376), .D(
pfifo_datain1[37]), .Z(n690) );
CND2X1 U755 ( .A(n691), .B(n690), .Z(pfifo_datain[37]) );
CND2X1 U756 ( .A(pfifo_datain0[33]), .B(n561), .Z(n693) );
CANR2X1 U757 ( .A(n782), .B(pfifo_datain2[33]), .C(n376), .D(
pfifo_datain1[33]), .Z(n692) );
CND2X1 U758 ( .A(n693), .B(n692), .Z(pfifo_datain[33]) );
CND2X1 U759 ( .A(pfifo_datain0[34]), .B(n561), .Z(n695) );
CANR2X1 U760 ( .A(n782), .B(pfifo_datain2[34]), .C(n376), .D(
pfifo_datain1[34]), .Z(n694) );
CND2X1 U761 ( .A(n695), .B(n694), .Z(pfifo_datain[34]) );
CND2X1 U762 ( .A(pfifo_datain0[21]), .B(n561), .Z(n697) );
CANR2X1 U763 ( .A(n782), .B(pfifo_datain2[21]), .C(n376), .D(
pfifo_datain1[21]), .Z(n696) );
CND2X1 U764 ( .A(n697), .B(n696), .Z(pfifo_datain[21]) );
CND2X1 U765 ( .A(pfifo_datain0[23]), .B(n561), .Z(n699) );
CANR2X1 U766 ( .A(n782), .B(pfifo_datain2[23]), .C(n376), .D(
pfifo_datain1[23]), .Z(n698) );
CND2X1 U767 ( .A(n699), .B(n698), .Z(pfifo_datain[23]) );
CND2X1 U768 ( .A(pfifo_datain0[16]), .B(n561), .Z(n701) );
CANR2X1 U769 ( .A(n782), .B(pfifo_datain2[16]), .C(n376), .D(
pfifo_datain1[16]), .Z(n700) );
CND2X1 U770 ( .A(n701), .B(n700), .Z(pfifo_datain[16]) );
CND2X1 U771 ( .A(pfifo_datain0[26]), .B(n561), .Z(n703) );
CANR2X1 U772 ( .A(n782), .B(pfifo_datain2[26]), .C(n376), .D(
pfifo_datain1[26]), .Z(n702) );
CND2X1 U773 ( .A(n703), .B(n702), .Z(pfifo_datain[26]) );
CND2X1 U774 ( .A(pfifo_datain0[14]), .B(n561), .Z(n705) );
CANR2X1 U775 ( .A(n782), .B(pfifo_datain2[14]), .C(n376), .D(
pfifo_datain1[14]), .Z(n704) );
CND2X1 U776 ( .A(n705), .B(n704), .Z(pfifo_datain[14]) );
CND2X1 U777 ( .A(pfifo_datain0[13]), .B(n561), .Z(n707) );
CANR2X1 U778 ( .A(n782), .B(pfifo_datain2[13]), .C(n376), .D(
pfifo_datain1[13]), .Z(n706) );
CND2X1 U779 ( .A(n707), .B(n706), .Z(pfifo_datain[13]) );
CND2X1 U780 ( .A(pfifo_datain0[18]), .B(n561), .Z(n709) );
CANR2X1 U781 ( .A(n782), .B(pfifo_datain2[18]), .C(n376), .D(
pfifo_datain1[18]), .Z(n708) );
CND2X1 U782 ( .A(n709), .B(n708), .Z(pfifo_datain[18]) );
CND2X1 U783 ( .A(pfifo_datain0[22]), .B(n561), .Z(n711) );
CANR2X1 U784 ( .A(n782), .B(pfifo_datain2[22]), .C(n376), .D(
pfifo_datain1[22]), .Z(n710) );
CND2X1 U785 ( .A(n711), .B(n710), .Z(pfifo_datain[22]) );
CND2X1 U786 ( .A(pfifo_datain0[20]), .B(n561), .Z(n713) );
CANR2X1 U787 ( .A(n782), .B(pfifo_datain2[20]), .C(n376), .D(
pfifo_datain1[20]), .Z(n712) );
CND2X1 U788 ( .A(n713), .B(n712), .Z(pfifo_datain[20]) );
CND2X1 U789 ( .A(pfifo_datain0[15]), .B(n561), .Z(n715) );
CANR2X1 U790 ( .A(n782), .B(pfifo_datain2[15]), .C(n376), .D(
pfifo_datain1[15]), .Z(n714) );
CND2X1 U791 ( .A(n715), .B(n714), .Z(pfifo_datain[15]) );
CND2X1 U792 ( .A(pfifo_datain0[12]), .B(n561), .Z(n717) );
CANR2X1 U793 ( .A(n782), .B(pfifo_datain2[12]), .C(n376), .D(
pfifo_datain1[12]), .Z(n716) );
CND2X1 U794 ( .A(n717), .B(n716), .Z(pfifo_datain[12]) );
CND2X1 U795 ( .A(pfifo_datain0[17]), .B(n561), .Z(n719) );
CANR2X1 U796 ( .A(n782), .B(pfifo_datain2[17]), .C(n376), .D(
pfifo_datain1[17]), .Z(n718) );
CND2X1 U797 ( .A(n719), .B(n718), .Z(pfifo_datain[17]) );
CND2X1 U798 ( .A(pfifo_datain_ctrl_0[5]), .B(n561), .Z(n721) );
CANR2X1 U799 ( .A(n782), .B(pfifo_datain_ctrl_2[5]), .C(n376), .D(
pfifo_datain_ctrl_1[5]), .Z(n720) );
CND2X1 U800 ( .A(n721), .B(n720), .Z(pfifo_datain_ctrl[5]) );
CND2X1 U801 ( .A(pfifo_datain_ctrl_0[10]), .B(n561), .Z(n723) );
CANR2X1 U802 ( .A(n782), .B(pfifo_datain_ctrl_2[10]), .C(n376), .D(
pfifo_datain_ctrl_1[10]), .Z(n722) );
CND2X1 U803 ( .A(n723), .B(n722), .Z(pfifo_datain_ctrl[10]) );
CND2X1 U804 ( .A(pfifo_datain_ctrl_0[7]), .B(n561), .Z(n725) );
CANR2X1 U805 ( .A(n782), .B(pfifo_datain_ctrl_2[7]), .C(n376), .D(
pfifo_datain_ctrl_1[7]), .Z(n724) );
CND2X1 U806 ( .A(n725), .B(n724), .Z(pfifo_datain_ctrl[7]) );
CND2X1 U807 ( .A(pfifo_datain_ctrl_0[8]), .B(n561), .Z(n727) );
CANR2X1 U808 ( .A(n782), .B(pfifo_datain_ctrl_2[8]), .C(n376), .D(
pfifo_datain_ctrl_1[8]), .Z(n726) );
CND2X1 U809 ( .A(n727), .B(n726), .Z(pfifo_datain_ctrl[8]) );
CND2X1 U810 ( .A(pfifo_datain_ctrl_0[9]), .B(n561), .Z(n729) );
CANR2X1 U811 ( .A(n782), .B(pfifo_datain_ctrl_2[9]), .C(n376), .D(
pfifo_datain_ctrl_1[9]), .Z(n728) );
CND2X1 U812 ( .A(n729), .B(n728), .Z(pfifo_datain_ctrl[9]) );
CND2X1 U813 ( .A(pfifo_datain_ctrl_0[3]), .B(n561), .Z(n731) );
CANR2X1 U814 ( .A(n782), .B(pfifo_datain_ctrl_2[3]), .C(n376), .D(
pfifo_datain_ctrl_1[3]), .Z(n730) );
CND2X1 U815 ( .A(n731), .B(n730), .Z(pfifo_datain_ctrl[3]) );
CND2X1 U816 ( .A(pfifo_datain0[25]), .B(n561), .Z(n733) );
CANR2X1 U817 ( .A(n782), .B(pfifo_datain2[25]), .C(n376), .D(
pfifo_datain1[25]), .Z(n732) );
CND2X1 U818 ( .A(n733), .B(n732), .Z(pfifo_datain[25]) );
CND2X1 U819 ( .A(pfifo_datain_ctrl_0[1]), .B(n561), .Z(n735) );
CANR2X1 U820 ( .A(n782), .B(pfifo_datain_ctrl_2[1]), .C(n376), .D(
pfifo_datain_ctrl_1[1]), .Z(n734) );
CND2X1 U821 ( .A(n735), .B(n734), .Z(pfifo_datain_ctrl[1]) );
CND2X1 U822 ( .A(pfifo_datain0[63]), .B(n561), .Z(n737) );
CANR2X1 U823 ( .A(n782), .B(pfifo_datain2[63]), .C(n376), .D(
pfifo_datain1[63]), .Z(n736) );
CND2X1 U824 ( .A(n737), .B(n736), .Z(pfifo_datain[63]) );
CND2X1 U825 ( .A(pfifo_datain_ctrl_0[4]), .B(n561), .Z(n739) );
CANR2X1 U826 ( .A(n782), .B(pfifo_datain_ctrl_2[4]), .C(n376), .D(
pfifo_datain_ctrl_1[4]), .Z(n738) );
CND2X1 U827 ( .A(n739), .B(n738), .Z(pfifo_datain_ctrl[4]) );
CND2X1 U828 ( .A(pfifo_datain_ctrl_0[2]), .B(n561), .Z(n741) );
CANR2X1 U829 ( .A(n782), .B(pfifo_datain_ctrl_2[2]), .C(n376), .D(
pfifo_datain_ctrl_1[2]), .Z(n740) );
CND2X1 U830 ( .A(n741), .B(n740), .Z(pfifo_datain_ctrl[2]) );
CND2X1 U831 ( .A(pfifo_datain0[47]), .B(n561), .Z(n743) );
CANR2X1 U832 ( .A(n782), .B(pfifo_datain2[47]), .C(n376), .D(
pfifo_datain1[47]), .Z(n742) );
CND2X1 U833 ( .A(n743), .B(n742), .Z(pfifo_datain[47]) );
CND2X1 U834 ( .A(pfifo_datain_ctrl_0[6]), .B(n561), .Z(n745) );
CANR2X1 U835 ( .A(n782), .B(pfifo_datain_ctrl_2[6]), .C(n376), .D(
pfifo_datain_ctrl_1[6]), .Z(n744) );
CND2X1 U836 ( .A(n745), .B(n744), .Z(pfifo_datain_ctrl[6]) );
CND2X1 U837 ( .A(pfifo_datain_ctrl_0[0]), .B(n561), .Z(n747) );
CANR2X1 U838 ( .A(n782), .B(pfifo_datain_ctrl_2[0]), .C(n376), .D(
pfifo_datain_ctrl_1[0]), .Z(n746) );
CND2X1 U839 ( .A(n747), .B(n746), .Z(pfifo_datain_ctrl[0]) );
CND2X1 U840 ( .A(pfifo_datain_ctrl_0[11]), .B(n561), .Z(n749) );
CANR2X1 U841 ( .A(n782), .B(pfifo_datain_ctrl_2[11]), .C(n376), .D(
pfifo_datain_ctrl_1[11]), .Z(n748) );
CND2X1 U842 ( .A(n749), .B(n748), .Z(pfifo_datain_ctrl[11]) );
CND2X1 U843 ( .A(pfifo_datain0[41]), .B(n561), .Z(n751) );
CANR2X1 U844 ( .A(n782), .B(pfifo_datain2[41]), .C(n376), .D(
pfifo_datain1[41]), .Z(n750) );
CND2X1 U845 ( .A(n751), .B(n750), .Z(pfifo_datain[41]) );
CND2X1 U846 ( .A(pfifo_datain0[30]), .B(n561), .Z(n753) );
CANR2X1 U847 ( .A(n782), .B(pfifo_datain2[30]), .C(n376), .D(
pfifo_datain1[30]), .Z(n752) );
CND2X1 U848 ( .A(n753), .B(n752), .Z(pfifo_datain[30]) );
CND2X1 U849 ( .A(pfifo_datain0[19]), .B(n561), .Z(n755) );
CANR2X1 U850 ( .A(n782), .B(pfifo_datain2[19]), .C(n376), .D(
pfifo_datain1[19]), .Z(n754) );
CND2X1 U851 ( .A(n755), .B(n754), .Z(pfifo_datain[19]) );
CND2X1 U852 ( .A(pfifo_datain0[42]), .B(n561), .Z(n757) );
CANR2X1 U853 ( .A(n782), .B(pfifo_datain2[42]), .C(n376), .D(
pfifo_datain1[42]), .Z(n756) );
CND2X1 U854 ( .A(n757), .B(n756), .Z(pfifo_datain[42]) );
CND2X1 U855 ( .A(pfifo_datain0[36]), .B(n561), .Z(n759) );
CANR2X1 U856 ( .A(n782), .B(pfifo_datain2[36]), .C(n376), .D(
pfifo_datain1[36]), .Z(n758) );
CND2X1 U857 ( .A(n759), .B(n758), .Z(pfifo_datain[36]) );
CND2X1 U858 ( .A(pfifo_datain0[29]), .B(n561), .Z(n761) );
CANR2X1 U859 ( .A(n782), .B(pfifo_datain2[29]), .C(n376), .D(
pfifo_datain1[29]), .Z(n760) );
CND2X1 U860 ( .A(n761), .B(n760), .Z(pfifo_datain[29]) );
CND2X1 U861 ( .A(pfifo_datain0[59]), .B(n561), .Z(n763) );
CANR2X1 U862 ( .A(n782), .B(pfifo_datain2[59]), .C(n376), .D(
pfifo_datain1[59]), .Z(n762) );
CND2X1 U863 ( .A(n763), .B(n762), .Z(pfifo_datain[59]) );
CND2X1 U864 ( .A(pfifo_datain0[57]), .B(n561), .Z(n765) );
CANR2X1 U865 ( .A(n782), .B(pfifo_datain2[57]), .C(n376), .D(
pfifo_datain1[57]), .Z(n764) );
CND2X1 U866 ( .A(n765), .B(n764), .Z(pfifo_datain[57]) );
CND2X1 U867 ( .A(pfifo_datain0[56]), .B(n561), .Z(n767) );
CANR2X1 U868 ( .A(n782), .B(pfifo_datain2[56]), .C(n376), .D(
pfifo_datain1[56]), .Z(n766) );
CND2X1 U869 ( .A(n767), .B(n766), .Z(pfifo_datain[56]) );
CND2X1 U870 ( .A(pfifo_datain0[58]), .B(n561), .Z(n769) );
CANR2X1 U871 ( .A(n782), .B(pfifo_datain2[58]), .C(n376), .D(
pfifo_datain1[58]), .Z(n768) );
CND2X1 U872 ( .A(n769), .B(n768), .Z(pfifo_datain[58]) );
CND2X1 U873 ( .A(pfifo_datain0[24]), .B(n561), .Z(n771) );
CANR2X1 U874 ( .A(n782), .B(pfifo_datain2[24]), .C(n376), .D(
pfifo_datain1[24]), .Z(n770) );
CND2X1 U875 ( .A(n771), .B(n770), .Z(pfifo_datain[24]) );
CND2X1 U876 ( .A(pfifo_datain0[62]), .B(n561), .Z(n773) );
CANR2X1 U877 ( .A(n782), .B(pfifo_datain2[62]), .C(n376), .D(
pfifo_datain1[62]), .Z(n772) );
CND2X1 U878 ( .A(n773), .B(n772), .Z(pfifo_datain[62]) );
CND2X1 U879 ( .A(pfifo_datain0[61]), .B(n561), .Z(n775) );
CANR2X1 U880 ( .A(n782), .B(pfifo_datain2[61]), .C(n376), .D(
pfifo_datain1[61]), .Z(n774) );
CND2X1 U881 ( .A(n775), .B(n774), .Z(pfifo_datain[61]) );
CND2X1 U882 ( .A(pfifo_datain0[48]), .B(n561), .Z(n777) );
CANR2X1 U883 ( .A(n782), .B(pfifo_datain2[48]), .C(n376), .D(
pfifo_datain1[48]), .Z(n776) );
CND2X1 U884 ( .A(n777), .B(n776), .Z(pfifo_datain[48]) );
CND2X1 U885 ( .A(pfifo_datain0[46]), .B(n561), .Z(n779) );
CANR2X1 U886 ( .A(n782), .B(pfifo_datain2[46]), .C(n376), .D(
pfifo_datain1[46]), .Z(n778) );
CND2X1 U887 ( .A(n779), .B(n778), .Z(pfifo_datain[46]) );
CND2X1 U888 ( .A(pfifo_datain0[45]), .B(n561), .Z(n781) );
CANR2X1 U889 ( .A(n782), .B(pfifo_datain2[45]), .C(n376), .D(
pfifo_datain1[45]), .Z(n780) );
CND2X1 U890 ( .A(n781), .B(n780), .Z(pfifo_datain[45]) );
CND2X1 U891 ( .A(pfifo_datain0[60]), .B(n561), .Z(n784) );
CANR2X1 U892 ( .A(n782), .B(pfifo_datain2[60]), .C(n376), .D(
pfifo_datain1[60]), .Z(n783) );
CND2X1 U893 ( .A(n784), .B(n783), .Z(pfifo_datain[60]) );
CND2X1 U894 ( .A(pfifo_datain0[43]), .B(n561), .Z(n786) );
CANR2X1 U895 ( .A(n782), .B(pfifo_datain2[43]), .C(n376), .D(
pfifo_datain1[43]), .Z(n785) );
CND2X1 U896 ( .A(n786), .B(n785), .Z(pfifo_datain[43]) );
CND2X1 U897 ( .A(pfifo_datain0[55]), .B(n561), .Z(n788) );
CANR2X1 U898 ( .A(n782), .B(pfifo_datain2[55]), .C(n376), .D(
pfifo_datain1[55]), .Z(n787) );
CND2X1 U899 ( .A(n788), .B(n787), .Z(pfifo_datain[55]) );
CND2X1 U900 ( .A(pfifo_datain0[54]), .B(n561), .Z(n790) );
CANR2X1 U901 ( .A(n782), .B(pfifo_datain2[54]), .C(n376), .D(
pfifo_datain1[54]), .Z(n789) );
CND2X1 U902 ( .A(n790), .B(n789), .Z(pfifo_datain[54]) );
CND2X1 U903 ( .A(pfifo_datain0[53]), .B(n561), .Z(n792) );
CANR2X1 U904 ( .A(n782), .B(pfifo_datain2[53]), .C(n376), .D(
pfifo_datain1[53]), .Z(n791) );
CND2X1 U905 ( .A(n792), .B(n791), .Z(pfifo_datain[53]) );
CND2X1 U906 ( .A(pfifo_datain0[52]), .B(n561), .Z(n794) );
CANR2X1 U907 ( .A(n782), .B(pfifo_datain2[52]), .C(n376), .D(
pfifo_datain1[52]), .Z(n793) );
CND2X1 U908 ( .A(n794), .B(n793), .Z(pfifo_datain[52]) );
CND2X1 U909 ( .A(pfifo_datain0[51]), .B(n561), .Z(n796) );
CANR2X1 U910 ( .A(n782), .B(pfifo_datain2[51]), .C(n376), .D(
pfifo_datain1[51]), .Z(n795) );
CND2X1 U911 ( .A(n796), .B(n795), .Z(pfifo_datain[51]) );
CND2X1 U912 ( .A(pfifo_datain0[44]), .B(n561), .Z(n798) );
CANR2X1 U913 ( .A(n782), .B(pfifo_datain2[44]), .C(n376), .D(
pfifo_datain1[44]), .Z(n797) );
CND2X1 U914 ( .A(n798), .B(n797), .Z(pfifo_datain[44]) );
CND2X1 U915 ( .A(pfifo_datain0[50]), .B(n561), .Z(n800) );
CANR2X1 U916 ( .A(n782), .B(pfifo_datain2[50]), .C(n376), .D(
pfifo_datain1[50]), .Z(n799) );
CND2X1 U917 ( .A(n800), .B(n799), .Z(pfifo_datain[50]) );
CND2X1 U918 ( .A(pfifo_datain0[49]), .B(n561), .Z(n802) );
CANR2X1 U919 ( .A(n782), .B(pfifo_datain2[49]), .C(n376), .D(
pfifo_datain1[49]), .Z(n801) );
CND2X1 U920 ( .A(n802), .B(n801), .Z(pfifo_datain[49]) );
CND2X1 U921 ( .A(pfifo_datain0[11]), .B(n561), .Z(n804) );
CANR2X1 U922 ( .A(n782), .B(pfifo_datain2[11]), .C(n376), .D(
pfifo_datain1[11]), .Z(n803) );
CND2X1 U923 ( .A(n804), .B(n803), .Z(pfifo_datain[11]) );
CND2X1 U924 ( .A(pfifo_datain0[10]), .B(n561), .Z(n806) );
CANR2X1 U925 ( .A(n782), .B(pfifo_datain2[10]), .C(n376), .D(
pfifo_datain1[10]), .Z(n805) );
CND2X1 U926 ( .A(n806), .B(n805), .Z(pfifo_datain[10]) );
CND2X1 U927 ( .A(pfifo_datain0[9]), .B(n561), .Z(n808) );
CANR2X1 U928 ( .A(n782), .B(pfifo_datain2[9]), .C(n376), .D(pfifo_datain1[9]), .Z(n807) );
CND2X1 U929 ( .A(n808), .B(n807), .Z(pfifo_datain[9]) );
CND2X1 U930 ( .A(pfifo_datain0[8]), .B(n561), .Z(n810) );
CANR2X1 U931 ( .A(n782), .B(pfifo_datain2[8]), .C(n376), .D(pfifo_datain1[8]), .Z(n809) );
CND2X1 U932 ( .A(n810), .B(n809), .Z(pfifo_datain[8]) );
CND2X1 U933 ( .A(pfifo_datain0[7]), .B(n561), .Z(n812) );
CANR2X1 U934 ( .A(n782), .B(pfifo_datain2[7]), .C(n376), .D(pfifo_datain1[7]), .Z(n811) );
CND2X1 U935 ( .A(n812), .B(n811), .Z(pfifo_datain[7]) );
CND2X1 U936 ( .A(pfifo_datain0[6]), .B(n561), .Z(n814) );
CANR2X1 U937 ( .A(n782), .B(pfifo_datain2[6]), .C(n376), .D(pfifo_datain1[6]), .Z(n813) );
CND2X1 U938 ( .A(n814), .B(n813), .Z(pfifo_datain[6]) );
CND2X1 U939 ( .A(pfifo_datain_ctrl_0[14]), .B(n561), .Z(n816) );
CANR2X1 U940 ( .A(n782), .B(pfifo_datain_ctrl_2[14]), .C(n376), .D(
pfifo_datain_ctrl_1[14]), .Z(n815) );
CND2X1 U941 ( .A(n816), .B(n815), .Z(pfifo_datain_ctrl[14]) );
CND2X1 U942 ( .A(pfifo_datain0[5]), .B(n561), .Z(n818) );
CANR2X1 U943 ( .A(n782), .B(pfifo_datain2[5]), .C(n376), .D(pfifo_datain1[5]), .Z(n817) );
CND2X1 U944 ( .A(n818), .B(n817), .Z(pfifo_datain[5]) );
CND2X1 U945 ( .A(pfifo_datain0[4]), .B(n561), .Z(n820) );
CANR2X1 U946 ( .A(n782), .B(pfifo_datain2[4]), .C(n376), .D(pfifo_datain1[4]), .Z(n819) );
CND2X1 U947 ( .A(n820), .B(n819), .Z(pfifo_datain[4]) );
CND2X1 U948 ( .A(pfifo_datain0[3]), .B(n561), .Z(n822) );
CANR2X1 U949 ( .A(n782), .B(pfifo_datain2[3]), .C(n376), .D(pfifo_datain1[3]), .Z(n821) );
CND2X1 U950 ( .A(n822), .B(n821), .Z(pfifo_datain[3]) );
CND2X1 U951 ( .A(pfifo_datain0[2]), .B(n561), .Z(n824) );
CANR2X1 U952 ( .A(n782), .B(pfifo_datain2[2]), .C(n376), .D(pfifo_datain1[2]), .Z(n823) );
CND2X1 U953 ( .A(n824), .B(n823), .Z(pfifo_datain[2]) );
CND2X1 U954 ( .A(pfifo_datain0[1]), .B(n561), .Z(n826) );
CANR2X1 U955 ( .A(n782), .B(pfifo_datain2[1]), .C(n376), .D(pfifo_datain1[1]), .Z(n825) );
CND2X1 U956 ( .A(n826), .B(n825), .Z(pfifo_datain[1]) );
CND2X1 U957 ( .A(pfifo_datain0[0]), .B(n561), .Z(n828) );
CANR2X1 U958 ( .A(n782), .B(pfifo_datain2[0]), .C(n376), .D(pfifo_datain1[0]), .Z(n827) );
CND2X1 U959 ( .A(n828), .B(n827), .Z(pfifo_datain[0]) );
CND2X1 U960 ( .A(pfifo_datain_ctrl_0[15]), .B(n561), .Z(n830) );
CANR2X1 U961 ( .A(n782), .B(pfifo_datain_ctrl_2[15]), .C(n376), .D(
pfifo_datain_ctrl_1[15]), .Z(n829) );
CND2X1 U962 ( .A(n830), .B(n829), .Z(pfifo_datain_ctrl[15]) );
CND2X1 U963 ( .A(pfifo_datain_ctrl_0[13]), .B(n561), .Z(n832) );
CANR2X1 U964 ( .A(n782), .B(pfifo_datain_ctrl_2[13]), .C(n376), .D(
pfifo_datain_ctrl_1[13]), .Z(n831) );
CND2X1 U965 ( .A(n832), .B(n831), .Z(pfifo_datain_ctrl[13]) );
CND2X1 U966 ( .A(pfifo_datain_ctrl_0[12]), .B(n561), .Z(n834) );
CANR2X1 U967 ( .A(n782), .B(pfifo_datain_ctrl_2[12]), .C(n376), .D(
pfifo_datain_ctrl_1[12]), .Z(n833) );
CND2X1 U968 ( .A(n834), .B(n833), .Z(pfifo_datain_ctrl[12]) );
CND2X1 U969 ( .A(crcfifo0_dataout[31]), .B(n561), .Z(n836) );
CANR2X1 U970 ( .A(n782), .B(crcfifo2_dataout[31]), .C(n376), .D(
crcfifo1_dataout[31]), .Z(n835) );
CND2X1 U971 ( .A(n836), .B(n835), .Z(crcfifo_dataout[31]) );
CND2X1 U972 ( .A(crcfifo0_dataout[30]), .B(n561), .Z(n838) );
CANR2X1 U973 ( .A(n782), .B(crcfifo2_dataout[30]), .C(n376), .D(
crcfifo1_dataout[30]), .Z(n837) );
CND2X1 U974 ( .A(n838), .B(n837), .Z(crcfifo_dataout[30]) );
CND2X1 U975 ( .A(crcfifo0_dataout[29]), .B(n561), .Z(n840) );
CANR2X1 U976 ( .A(n782), .B(crcfifo2_dataout[29]), .C(n376), .D(
crcfifo1_dataout[29]), .Z(n839) );
CND2X1 U977 ( .A(n840), .B(n839), .Z(crcfifo_dataout[29]) );
CND2X1 U978 ( .A(crcfifo0_dataout[28]), .B(n561), .Z(n842) );
CANR2X1 U979 ( .A(n782), .B(crcfifo2_dataout[28]), .C(n376), .D(
crcfifo1_dataout[28]), .Z(n841) );
CND2X1 U980 ( .A(n842), .B(n841), .Z(crcfifo_dataout[28]) );
CND2X1 U981 ( .A(crcfifo0_dataout[27]), .B(n561), .Z(n844) );
CANR2X1 U982 ( .A(n782), .B(crcfifo2_dataout[27]), .C(n376), .D(
crcfifo1_dataout[27]), .Z(n843) );
CND2X1 U983 ( .A(n844), .B(n843), .Z(crcfifo_dataout[27]) );
CND2X1 U984 ( .A(crcfifo0_dataout[26]), .B(n561), .Z(n846) );
CANR2X1 U985 ( .A(n782), .B(crcfifo2_dataout[26]), .C(n376), .D(
crcfifo1_dataout[26]), .Z(n845) );
CND2X1 U986 ( .A(n846), .B(n845), .Z(crcfifo_dataout[26]) );
CND2X1 U987 ( .A(crcfifo0_dataout[25]), .B(n561), .Z(n848) );
CANR2X1 U988 ( .A(n782), .B(crcfifo2_dataout[25]), .C(n376), .D(
crcfifo1_dataout[25]), .Z(n847) );
CND2X1 U989 ( .A(n848), .B(n847), .Z(crcfifo_dataout[25]) );
CND2X1 U990 ( .A(crcfifo0_dataout[24]), .B(n561), .Z(n850) );
CANR2X1 U991 ( .A(n782), .B(crcfifo2_dataout[24]), .C(n376), .D(
crcfifo1_dataout[24]), .Z(n849) );
CND2X1 U992 ( .A(n850), .B(n849), .Z(crcfifo_dataout[24]) );
CND2X1 U993 ( .A(crcfifo0_dataout[23]), .B(n561), .Z(n852) );
CANR2X1 U994 ( .A(n782), .B(crcfifo2_dataout[23]), .C(n376), .D(
crcfifo1_dataout[23]), .Z(n851) );
CND2X1 U995 ( .A(n852), .B(n851), .Z(crcfifo_dataout[23]) );
CND2X1 U996 ( .A(crcfifo0_dataout[22]), .B(n561), .Z(n854) );
CANR2X1 U997 ( .A(n782), .B(crcfifo2_dataout[22]), .C(n376), .D(
crcfifo1_dataout[22]), .Z(n853) );
CND2X1 U998 ( .A(n854), .B(n853), .Z(crcfifo_dataout[22]) );
CND2X1 U999 ( .A(crcfifo0_dataout[21]), .B(n561), .Z(n856) );
CANR2X1 U1000 ( .A(n782), .B(crcfifo2_dataout[21]), .C(n376), .D(
crcfifo1_dataout[21]), .Z(n855) );
CND2X1 U1001 ( .A(n856), .B(n855), .Z(crcfifo_dataout[21]) );
CND2X1 U1002 ( .A(crcfifo0_dataout[20]), .B(n561), .Z(n858) );
CANR2X1 U1003 ( .A(n782), .B(crcfifo2_dataout[20]), .C(n376), .D(
crcfifo1_dataout[20]), .Z(n857) );
CND2X1 U1004 ( .A(n858), .B(n857), .Z(crcfifo_dataout[20]) );
CND2X1 U1005 ( .A(crcfifo0_dataout[19]), .B(n561), .Z(n860) );
CANR2X1 U1006 ( .A(n782), .B(crcfifo2_dataout[19]), .C(n376), .D(
crcfifo1_dataout[19]), .Z(n859) );
CND2X1 U1007 ( .A(n860), .B(n859), .Z(crcfifo_dataout[19]) );
CND2X1 U1008 ( .A(crcfifo0_dataout[18]), .B(n561), .Z(n862) );
CANR2X1 U1009 ( .A(n782), .B(crcfifo2_dataout[18]), .C(n376), .D(
crcfifo1_dataout[18]), .Z(n861) );
CND2X1 U1010 ( .A(n862), .B(n861), .Z(crcfifo_dataout[18]) );
CND2X1 U1011 ( .A(crcfifo0_dataout[17]), .B(n561), .Z(n864) );
CANR2X1 U1012 ( .A(n782), .B(crcfifo2_dataout[17]), .C(n376), .D(
crcfifo1_dataout[17]), .Z(n863) );
CND2X1 U1013 ( .A(n864), .B(n863), .Z(crcfifo_dataout[17]) );
CND2X1 U1014 ( .A(crcfifo0_dataout[16]), .B(n561), .Z(n866) );
CANR2X1 U1015 ( .A(n782), .B(crcfifo2_dataout[16]), .C(n376), .D(
crcfifo1_dataout[16]), .Z(n865) );
CND2X1 U1016 ( .A(n866), .B(n865), .Z(crcfifo_dataout[16]) );
CND2X1 U1017 ( .A(crcfifo0_dataout[15]), .B(n561), .Z(n868) );
CANR2X1 U1018 ( .A(n782), .B(crcfifo2_dataout[15]), .C(n376), .D(
crcfifo1_dataout[15]), .Z(n867) );
CND2X1 U1019 ( .A(n868), .B(n867), .Z(crcfifo_dataout[15]) );
CND2X1 U1020 ( .A(crcfifo0_dataout[14]), .B(n561), .Z(n870) );
CANR2X1 U1021 ( .A(n782), .B(crcfifo2_dataout[14]), .C(n376), .D(
crcfifo1_dataout[14]), .Z(n869) );
CND2X1 U1022 ( .A(n870), .B(n869), .Z(crcfifo_dataout[14]) );
CND2X1 U1023 ( .A(crcfifo0_dataout[13]), .B(n561), .Z(n872) );
CANR2X1 U1024 ( .A(n782), .B(crcfifo2_dataout[13]), .C(n376), .D(
crcfifo1_dataout[13]), .Z(n871) );
CND2X1 U1025 ( .A(n872), .B(n871), .Z(crcfifo_dataout[13]) );
CND2X1 U1026 ( .A(crcfifo0_dataout[12]), .B(n561), .Z(n874) );
CANR2X1 U1027 ( .A(n782), .B(crcfifo2_dataout[12]), .C(n376), .D(
crcfifo1_dataout[12]), .Z(n873) );
CND2X1 U1028 ( .A(n874), .B(n873), .Z(crcfifo_dataout[12]) );
CND2X1 U1029 ( .A(crcfifo0_dataout[11]), .B(n561), .Z(n876) );
CANR2X1 U1030 ( .A(n782), .B(crcfifo2_dataout[11]), .C(n376), .D(
crcfifo1_dataout[11]), .Z(n875) );
CND2X1 U1031 ( .A(n876), .B(n875), .Z(crcfifo_dataout[11]) );
CND2X1 U1032 ( .A(crcfifo0_dataout[10]), .B(n561), .Z(n878) );
CANR2X1 U1033 ( .A(n782), .B(crcfifo2_dataout[10]), .C(n376), .D(
crcfifo1_dataout[10]), .Z(n877) );
CND2X1 U1034 ( .A(n878), .B(n877), .Z(crcfifo_dataout[10]) );
CND2X1 U1035 ( .A(crcfifo0_dataout[9]), .B(n561), .Z(n880) );
CANR2X1 U1036 ( .A(n782), .B(crcfifo2_dataout[9]), .C(n376), .D(
crcfifo1_dataout[9]), .Z(n879) );
CND2X1 U1037 ( .A(n880), .B(n879), .Z(crcfifo_dataout[9]) );
CND2X1 U1038 ( .A(crcfifo0_dataout[8]), .B(n561), .Z(n883) );
CANR2X1 U1039 ( .A(n782), .B(crcfifo2_dataout[8]), .C(n376), .D(
crcfifo1_dataout[8]), .Z(n882) );
CND2X1 U1040 ( .A(n883), .B(n882), .Z(crcfifo_dataout[8]) );
CND2X1 U1041 ( .A(crcfifo0_dataout[7]), .B(n561), .Z(n885) );
CANR2X1 U1042 ( .A(n782), .B(crcfifo2_dataout[7]), .C(n376), .D(
crcfifo1_dataout[7]), .Z(n884) );
CND2X1 U1043 ( .A(n885), .B(n884), .Z(crcfifo_dataout[7]) );
CND2X1 U1044 ( .A(crcfifo0_dataout[6]), .B(n561), .Z(n887) );
CANR2X1 U1045 ( .A(n782), .B(crcfifo2_dataout[6]), .C(n376), .D(
crcfifo1_dataout[6]), .Z(n886) );
CND2X1 U1046 ( .A(n887), .B(n886), .Z(crcfifo_dataout[6]) );
CND2X1 U1047 ( .A(crcfifo0_dataout[5]), .B(n561), .Z(n889) );
CANR2X1 U1048 ( .A(n782), .B(crcfifo2_dataout[5]), .C(n376), .D(
crcfifo1_dataout[5]), .Z(n888) );
CND2X1 U1049 ( .A(n889), .B(n888), .Z(crcfifo_dataout[5]) );
CND2X1 U1050 ( .A(crcfifo0_dataout[4]), .B(n561), .Z(n891) );
CANR2X1 U1051 ( .A(n782), .B(crcfifo2_dataout[4]), .C(n376), .D(
crcfifo1_dataout[4]), .Z(n890) );
CND2X1 U1052 ( .A(n891), .B(n890), .Z(crcfifo_dataout[4]) );
CND2X1 U1053 ( .A(crcfifo0_dataout[3]), .B(n561), .Z(n893) );
CANR2X1 U1054 ( .A(n782), .B(crcfifo2_dataout[3]), .C(n376), .D(
crcfifo1_dataout[3]), .Z(n892) );
CND2X1 U1055 ( .A(n893), .B(n892), .Z(crcfifo_dataout[3]) );
CND2X1 U1056 ( .A(crcfifo0_dataout[2]), .B(n561), .Z(n895) );
CANR2X1 U1057 ( .A(n782), .B(crcfifo2_dataout[2]), .C(n376), .D(
crcfifo1_dataout[2]), .Z(n894) );
CND2X1 U1058 ( .A(n895), .B(n894), .Z(crcfifo_dataout[2]) );
CND2X1 U1059 ( .A(crcfifo0_dataout[1]), .B(n561), .Z(n897) );
CANR2X1 U1060 ( .A(n782), .B(crcfifo2_dataout[1]), .C(n376), .D(
crcfifo1_dataout[1]), .Z(n896) );
CND2X1 U1061 ( .A(n897), .B(n896), .Z(crcfifo_dataout[1]) );
CND2X1 U1062 ( .A(crcfifo0_dataout[0]), .B(n561), .Z(n899) );
CANR2X1 U1063 ( .A(n782), .B(crcfifo2_dataout[0]), .C(n376), .D(
crcfifo1_dataout[0]), .Z(n898) );
CND2X1 U1064 ( .A(n899), .B(n898), .Z(crcfifo_dataout[0]) );
CAN2X1 U1065 ( .A(n914), .B(n900), .Z(n920) );
CAN2X1 U1066 ( .A(n914), .B(n901), .Z(n927) );
CAN2X1 U1067 ( .A(n914), .B(n902), .Z(n939) );
CAN2X1 U1068 ( .A(n914), .B(n903), .Z(n936) );
CAN2X1 U1069 ( .A(n914), .B(n904), .Z(n926) );
CAN2X1 U1070 ( .A(n914), .B(n905), .Z(n938) );
CAN2X1 U1071 ( .A(n914), .B(n375), .Z(n937) );
CAN2X1 U1072 ( .A(n914), .B(n907), .Z(n930) );
CAN2X1 U1073 ( .A(n914), .B(n383), .Z(n929) );
CAN2X1 U1074 ( .A(n914), .B(n908), .Z(n928) );
CAN2X1 U1075 ( .A(n914), .B(n909), .Z(n934) );
CAN2X1 U1076 ( .A(n914), .B(n454), .Z(n918) );
CAN2X1 U1077 ( .A(n914), .B(n911), .Z(n924) );
CAN2X1 U1078 ( .A(n914), .B(n912), .Z(n922) );
CIVX2 U1079 ( .A(n915), .Z(\qos/N33 ) );
CND3XL U1080 ( .A(n451), .B(n916), .C(crcfifo2_empty), .Z(start_transmit) );
endmodule | 1 |
137,579 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv | 79,197,809 | axi_master_model.sv | sv | 211 | 96 | [] | [] | [] | null | line:3: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:3: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'axi_master_model\'\nmodule axi_master_model(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'AXI_wr_addr_ch\'\n AXI_wr_addr_ch.master_if wr_ach,\n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_wr_data_ch\'\n AXI_wr_data_ch.master_if wr_dch,\n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_wr_resp_ch\'\n AXI_wr_resp_ch.master_if wr_rspch,\n ^~~~~~~~~~~~~~\n : ... Top module \'AXI_clks\'\n AXI_clks.to_rtl clks\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:3: Unsupported: Interfaced port on top level module\n AXI_wr_addr_ch.master_if wr_ach,\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:4: Unsupported: Interfaced port on top level module\n AXI_wr_data_ch.master_if wr_dch,\n ^~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:5: Unsupported: Interfaced port on top level module\n AXI_wr_resp_ch.master_if wr_rspch,\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:6: Unsupported: Interfaced port on top level module\n AXI_clks.to_rtl clks\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:3: Cannot find file containing interface: \'AXI_wr_addr_ch\'\n AXI_wr_addr_ch.master_if wr_ach,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:4: Cannot find file containing interface: \'AXI_wr_data_ch\'\n AXI_wr_data_ch.master_if wr_dch,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:5: Cannot find file containing interface: \'AXI_wr_resp_ch\'\n AXI_wr_resp_ch.master_if wr_rspch,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:6: Cannot find file containing interface: \'AXI_clks\'\n AXI_clks.to_rtl clks\n ^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_master_model.sv:3: ../V3LinkDot.cpp:2055: Unlinked interface\n AXI_wr_addr_ch.master_if wr_ach,\n ^~~~~~~~~~~~~~\n' | 299,853 | module | module axi_master_model(
AXI_wr_addr_ch.master_if wr_ach,
AXI_wr_data_ch.master_if wr_dch,
AXI_wr_resp_ch.master_if wr_rspch,
AXI_clks.to_rtl clks
);
logic [32:0] axi_waddr[$];
logic [63:0] axi_wdata[$];
logic [4:0] axi_rsp_cnt_d,axi_rsp_cnt_nxt,axi_rsp_cnt_tmp;
reg waddr_empty;
reg wdata_empty;
integer wdata_depth;
typedef enum logic [2:0] {RST_WA=3'h0,WAD=3'h1,WA=3'h2,WA_HOLD=3'h3} axi_wr_state;
typedef enum logic [2:0] {RST_WRSP=3'h0,WVRSP=3'h1} axi_wrsp_state;
axi_wr_state wra_cur_state,wra_nxt_state;
axi_wr_state wrd_cur_state,wrd_nxt_state;
axi_wrsp_state wrsp_cur_state,wrsp_nxt_state;
reg awvalid_d,awvalid_nxt;
reg awburst_d,awburst_nxt;
reg bready_d,bready_nxt;
reg [3:0] awlen_d,awlen_nxt;
reg [2:0] awsize_d,awsize_nxt;
reg wvalid_d,wvalid_nxt;
reg [31:0] awaddr_d,awaddr_nxt;
reg [63:0] wdata_d,wdata_nxt;
reg [3:0] awid_d,wid_d;
reg pop;
assign wr_ach.AWVALID = awvalid_d;
assign wr_ach.AWADDR = awaddr_d;
assign wr_ach.AWBURST = awburst_d;
assign wr_ach.AWLEN = awlen_d;
assign wr_ach.AWSIZE = awsize_d;
assign wr_ach.AWID = awid_d;
assign wr_dch.WDATA = wdata_d;
assign wr_dch.WLAST = 0;
assign wr_dch.WID = wid_d;
assign wr_dch.WVALID = wvalid_d & ~wdata_empty;
assign wr_rspch.BREADY = bready_d;
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
wra_cur_state <= #0 RST_WA;
wrd_cur_state <= #0 RST_WA;
awvalid_d <= #0 0;
wvalid_d <= #0 0;
awaddr_d <= #0 0;
wdata_d <= #0 0;
awid_d <= #0 0;
wid_d <= #0 0;
waddr_empty <= #0 1;
wdata_empty <= #0 1;
awburst_d <= #0 0;
awlen_d <= #0 0;
awsize_d <= #0 3'b011;
axi_rsp_cnt_d <= #0 0;
bready_d <= #0 0;
wrsp_cur_state <= #0 RST_WRSP;
end else begin
wra_cur_state <= #1 wra_nxt_state;
wrd_cur_state <= #1 wrd_nxt_state;
awvalid_d <= #1 awvalid_nxt;
wvalid_d <= #1 wvalid_nxt;
awaddr_d <= #1 awaddr_nxt;
awid_d <= #1 3;
wid_d <= #1 3;
waddr_empty <= #1 (axi_waddr.size()==0);
wdata_empty <= #1 (axi_wdata.size()==0);
awburst_d <= #1 awburst_nxt;
awlen_d <= #1 awlen_nxt;
awsize_d <= #1 awsize_nxt;
wdata_d <= #1 pop ?axi_wdata.pop_front() :wdata_d;
axi_rsp_cnt_d <= #1 axi_rsp_cnt_nxt;
bready_d <= #1 bready_nxt;
wrsp_cur_state <= #1 wrsp_nxt_state;
end
end
always @(*) begin
wra_nxt_state = wra_cur_state;
awvalid_nxt = awvalid_d;
awaddr_nxt = awaddr_d;
awsize_nxt = awsize_d;
awburst_nxt = 0;
awlen_nxt = 0;
case(wra_cur_state)
RST_WA: begin
awvalid_nxt = 0;
if(!clks.rst) wra_nxt_state = RST_WA;
else wra_nxt_state = WAD;
end
WAD: begin
if(waddr_empty) begin
wra_nxt_state = WAD;
awvalid_nxt = 0;
end else begin
awvalid_nxt = 1;
awaddr_nxt = axi_waddr.pop_front();
wra_nxt_state = WA;
end
end
WA: begin
if(wr_ach.AWREADY) begin
if(!waddr_empty) begin
wra_nxt_state = WA;
awaddr_nxt = axi_waddr.pop_front();
awvalid_nxt = 1;
end else begin
awvalid_nxt = 0;
wra_nxt_state = WAD;
end
end
end
endcase
end
always @(*) begin
wrd_nxt_state = wrd_cur_state;
wvalid_nxt = wvalid_d;
pop = 0;
wdata_depth = axi_wdata.size();
case(wrd_cur_state)
RST_WA: begin
wvalid_nxt = 0;
if(!clks.rst) wrd_nxt_state = RST_WA;
else wrd_nxt_state = WAD;
end
WAD: begin
if(wdata_empty) begin
wrd_nxt_state = WAD;
wvalid_nxt = 0;
end else begin
wvalid_nxt = 1;
pop = 1;
wrd_nxt_state = WA;
wdata_depth = axi_wdata.size();
end
end
WA: begin
if(wr_dch.WREADY) begin
if(!wdata_empty) begin
wrd_nxt_state = WA;
pop = 1;
wvalid_nxt = 1;
wdata_depth = axi_wdata.size();
end else begin
wvalid_nxt = 0;
wrd_nxt_state = WAD;
end
end
end
endcase
end
always @(*) begin
axi_rsp_cnt_tmp = (wr_dch.WVALID & wr_dch.WREADY) ? (axi_rsp_cnt_d + 1):axi_rsp_cnt_d;
axi_rsp_cnt_nxt = (wr_rspch.BVALID & wr_rspch.BREADY) ? (axi_rsp_cnt_tmp-1):axi_rsp_cnt_tmp;
wrsp_nxt_state = wrsp_cur_state;
bready_nxt = 0;
case(wrsp_cur_state)
RST_WRSP: begin
if(!clks.rst) begin
wrsp_nxt_state = RST_WRSP;
end else begin
wrsp_nxt_state = WVRSP;
end
end
WVRSP: begin
if(wr_rspch.BVALID) begin
bready_nxt = 1;
end else begin
bready_nxt = 0;
end
wrsp_nxt_state = WVRSP;
end
endcase
end
always @(posedge clks.clk or negedge clks.rst) begin
if(clks.rst) begin
if(axi_rsp_cnt_d[4] == 1) begin
$display("%t RUN ABORTED:stale rsp received !!!!!!!!!",$time);
$finish;
end
end
end
endmodule | module axi_master_model(
AXI_wr_addr_ch.master_if wr_ach,
AXI_wr_data_ch.master_if wr_dch,
AXI_wr_resp_ch.master_if wr_rspch,
AXI_clks.to_rtl clks
); |
logic [32:0] axi_waddr[$];
logic [63:0] axi_wdata[$];
logic [4:0] axi_rsp_cnt_d,axi_rsp_cnt_nxt,axi_rsp_cnt_tmp;
reg waddr_empty;
reg wdata_empty;
integer wdata_depth;
typedef enum logic [2:0] {RST_WA=3'h0,WAD=3'h1,WA=3'h2,WA_HOLD=3'h3} axi_wr_state;
typedef enum logic [2:0] {RST_WRSP=3'h0,WVRSP=3'h1} axi_wrsp_state;
axi_wr_state wra_cur_state,wra_nxt_state;
axi_wr_state wrd_cur_state,wrd_nxt_state;
axi_wrsp_state wrsp_cur_state,wrsp_nxt_state;
reg awvalid_d,awvalid_nxt;
reg awburst_d,awburst_nxt;
reg bready_d,bready_nxt;
reg [3:0] awlen_d,awlen_nxt;
reg [2:0] awsize_d,awsize_nxt;
reg wvalid_d,wvalid_nxt;
reg [31:0] awaddr_d,awaddr_nxt;
reg [63:0] wdata_d,wdata_nxt;
reg [3:0] awid_d,wid_d;
reg pop;
assign wr_ach.AWVALID = awvalid_d;
assign wr_ach.AWADDR = awaddr_d;
assign wr_ach.AWBURST = awburst_d;
assign wr_ach.AWLEN = awlen_d;
assign wr_ach.AWSIZE = awsize_d;
assign wr_ach.AWID = awid_d;
assign wr_dch.WDATA = wdata_d;
assign wr_dch.WLAST = 0;
assign wr_dch.WID = wid_d;
assign wr_dch.WVALID = wvalid_d & ~wdata_empty;
assign wr_rspch.BREADY = bready_d;
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
wra_cur_state <= #0 RST_WA;
wrd_cur_state <= #0 RST_WA;
awvalid_d <= #0 0;
wvalid_d <= #0 0;
awaddr_d <= #0 0;
wdata_d <= #0 0;
awid_d <= #0 0;
wid_d <= #0 0;
waddr_empty <= #0 1;
wdata_empty <= #0 1;
awburst_d <= #0 0;
awlen_d <= #0 0;
awsize_d <= #0 3'b011;
axi_rsp_cnt_d <= #0 0;
bready_d <= #0 0;
wrsp_cur_state <= #0 RST_WRSP;
end else begin
wra_cur_state <= #1 wra_nxt_state;
wrd_cur_state <= #1 wrd_nxt_state;
awvalid_d <= #1 awvalid_nxt;
wvalid_d <= #1 wvalid_nxt;
awaddr_d <= #1 awaddr_nxt;
awid_d <= #1 3;
wid_d <= #1 3;
waddr_empty <= #1 (axi_waddr.size()==0);
wdata_empty <= #1 (axi_wdata.size()==0);
awburst_d <= #1 awburst_nxt;
awlen_d <= #1 awlen_nxt;
awsize_d <= #1 awsize_nxt;
wdata_d <= #1 pop ?axi_wdata.pop_front() :wdata_d;
axi_rsp_cnt_d <= #1 axi_rsp_cnt_nxt;
bready_d <= #1 bready_nxt;
wrsp_cur_state <= #1 wrsp_nxt_state;
end
end
always @(*) begin
wra_nxt_state = wra_cur_state;
awvalid_nxt = awvalid_d;
awaddr_nxt = awaddr_d;
awsize_nxt = awsize_d;
awburst_nxt = 0;
awlen_nxt = 0;
case(wra_cur_state)
RST_WA: begin
awvalid_nxt = 0;
if(!clks.rst) wra_nxt_state = RST_WA;
else wra_nxt_state = WAD;
end
WAD: begin
if(waddr_empty) begin
wra_nxt_state = WAD;
awvalid_nxt = 0;
end else begin
awvalid_nxt = 1;
awaddr_nxt = axi_waddr.pop_front();
wra_nxt_state = WA;
end
end
WA: begin
if(wr_ach.AWREADY) begin
if(!waddr_empty) begin
wra_nxt_state = WA;
awaddr_nxt = axi_waddr.pop_front();
awvalid_nxt = 1;
end else begin
awvalid_nxt = 0;
wra_nxt_state = WAD;
end
end
end
endcase
end
always @(*) begin
wrd_nxt_state = wrd_cur_state;
wvalid_nxt = wvalid_d;
pop = 0;
wdata_depth = axi_wdata.size();
case(wrd_cur_state)
RST_WA: begin
wvalid_nxt = 0;
if(!clks.rst) wrd_nxt_state = RST_WA;
else wrd_nxt_state = WAD;
end
WAD: begin
if(wdata_empty) begin
wrd_nxt_state = WAD;
wvalid_nxt = 0;
end else begin
wvalid_nxt = 1;
pop = 1;
wrd_nxt_state = WA;
wdata_depth = axi_wdata.size();
end
end
WA: begin
if(wr_dch.WREADY) begin
if(!wdata_empty) begin
wrd_nxt_state = WA;
pop = 1;
wvalid_nxt = 1;
wdata_depth = axi_wdata.size();
end else begin
wvalid_nxt = 0;
wrd_nxt_state = WAD;
end
end
end
endcase
end
always @(*) begin
axi_rsp_cnt_tmp = (wr_dch.WVALID & wr_dch.WREADY) ? (axi_rsp_cnt_d + 1):axi_rsp_cnt_d;
axi_rsp_cnt_nxt = (wr_rspch.BVALID & wr_rspch.BREADY) ? (axi_rsp_cnt_tmp-1):axi_rsp_cnt_tmp;
wrsp_nxt_state = wrsp_cur_state;
bready_nxt = 0;
case(wrsp_cur_state)
RST_WRSP: begin
if(!clks.rst) begin
wrsp_nxt_state = RST_WRSP;
end else begin
wrsp_nxt_state = WVRSP;
end
end
WVRSP: begin
if(wr_rspch.BVALID) begin
bready_nxt = 1;
end else begin
bready_nxt = 0;
end
wrsp_nxt_state = WVRSP;
end
endcase
end
always @(posedge clks.clk or negedge clks.rst) begin
if(clks.rst) begin
if(axi_rsp_cnt_d[4] == 1) begin
$display("%t RUN ABORTED:stale rsp received !!!!!!!!!",$time);
$finish;
end
end
end
endmodule | 1 |
137,580 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv | 79,197,809 | axi_slave_model.sv | sv | 275 | 148 | [] | [] | [] | null | line:2: before: "." | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:153: syntax error, unexpected ::\n if(!ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)) begin\n ^~\n%Warning-STMTDLY: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:155: Unsupported: Ignoring delay on this delayed statement.\n #100; $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:157: syntax error, unexpected ::\n ethernet_frame_pkg::ethernet_mem_data.delete(mem_addr_d);\n ^~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:170: syntax error, unexpected end\nend \n^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:175: syntax error, unexpected ::\n if(ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)) begin\n ^~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:184: syntax error, unexpected ::, expecting \';\'\n rresp = ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)?2\'b00:2\'b10; \n ^~\n : ... Perhaps \'ethernet_frame_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = VALID_ASSERT; \n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:206: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = RST_DR; \n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:211: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = WAIT_FOR_READY;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:221: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = VALID_ASSERT;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:232: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = WAIT_FOR_READY;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:242: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = VALID_ASSERT;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = WAIT_FOR_READY;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:255: syntax error, unexpected \'=\', expecting IDENTIFIER\n nxt_rd_state = WAIT_FOR_READY;\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/axi_slave_model.sv:262: syntax error, unexpected end\nend \n^~~\n%Error: Exiting due to 14 error(s), 1 warning(s)\n' | 299,854 | module | module axi_slave_model(
AXI_clks.to_rtl clks,
AXI_rd_addr_ch.slave_if rd_ach,
AXI_rd_data_ch.slave_if rd_dch
);
reg [35:0] ra_fifo [3][$];
reg [31:0] rd_fifo [3][$];
integer ra_size0,ra_size1,ra_size2;
reg [3:0] rdid_d,rdid_nxt;
reg arready_d,arready_nxt,push_addr,pop;
reg empty_ra_fifo0,empty_ra_fifo1,empty_ra_fifo2;
typedef enum reg [2:0] {RST_AR= 3'b000,WAIT_FOR_VALID=3'h1,READY_ASSERTED=3'h3} ra_state;
typedef enum reg [2:0] {RST_DR= 3'b000,VALID_ASSERT =3'b001,WAIT_FOR_READY=3'b011} rd_state;
ra_state cur_ra_state,nxt_ra_state;
rd_state cur_rd_state,nxt_rd_state;
reg [2:0] gnt_vector_d,gnt_vector_nxt;
reg [2:0] req_vector;
reg [1:0] r_vector[3],r_vector_nxt[3];
reg [1:0] r_v0,r_v1,r_v2;
reg pop_addr,arb_nxt;
reg [1:0] ch_tdm_d,ch_tdm_nxt;
assign {r_v0,r_v1,r_v2} = {r_vector[0],r_vector[1],r_vector[2]};
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
cur_ra_state <= #0 RST_AR;
arready_d <= #0 0;
empty_ra_fifo0 <= #0 1;
empty_ra_fifo1 <= #0 1;
empty_ra_fifo2 <= #0 1;
ra_size0 <= #0 0;
ra_size1 <= #0 0;
ra_size2 <= #0 0;
end else begin
cur_ra_state <= #1 nxt_ra_state;
arready_d <= #1 arready_nxt;
if(push_addr) begin
ra_fifo[rd_ach.ARID].push_back({rd_ach.ARLEN,rd_ach.ARADDR});
$display("%0t tb_axi_slave_model::===========ADDR pushed into FIFO[%d]:%0h==========",$realtime,rd_ach.ARID,{rd_ach.ARLEN,rd_ach.ARADDR});
end
empty_ra_fifo0 <= #1 (ra_fifo[0].size()==0);
empty_ra_fifo1 <= #1 (ra_fifo[1].size()==0);
empty_ra_fifo2 <= #1 (ra_fifo[2].size()==0);
ra_size0 <= #1 ra_fifo[0].size();
ra_size1 <= #1 ra_fifo[1].size();
ra_size2 <= #1 ra_fifo[2].size();
end
end
reg empty_ra_fifo;
always @(*) begin
nxt_ra_state = cur_ra_state;
push_addr = rd_ach.ARVALID & rd_ach.ARREADY;
arready_nxt = 0;
empty_ra_fifo = (empty_ra_fifo0 & empty_ra_fifo1 & empty_ra_fifo2);
case(cur_ra_state)
RST_AR: begin
if(clks.rst) begin
nxt_ra_state = WAIT_FOR_VALID;
end else begin
nxt_ra_state = RST_AR;
end
end
WAIT_FOR_VALID: begin
if(rd_ach.ARVALID) begin
nxt_ra_state = READY_ASSERTED;
arready_nxt = 1;
end
end
READY_ASSERTED: begin
if(rd_ach.ARVALID) begin
nxt_ra_state = READY_ASSERTED;
arready_nxt = 1;
end else begin
nxt_ra_state = WAIT_FOR_VALID;
arready_nxt = 0;
end
end
endcase
end
reg net_arb;
always @(*) begin
req_vector = {~empty_ra_fifo2,~empty_ra_fifo1,~empty_ra_fifo0};
r_vector_nxt[0] = r_vector[0];
for(integer i=0;i<3;i=i+1) begin
gnt_vector_nxt[i] = gnt_vector_d[i];
r_vector_nxt[i] = r_vector[i];
end
net_arb = arb_nxt || (gnt_vector_d==0);
if(net_arb) begin
gnt_vector_nxt[r_vector[0]] = 0;
for(integer i=1;i<3;i=i+1) begin
gnt_vector_nxt[r_vector[i]] = req_vector[r_vector[i]] & ~gnt_vector_nxt[r_vector[i-1]];
if(gnt_vector_nxt[r_vector[i]]) begin
r_vector_nxt[0] = r_vector[i];
end
end
for(integer i=1;i<3;i=i+1) begin
r_vector_nxt[i] = ((r_vector_nxt[i-1]+1)==3)?0:(r_vector_nxt[i-1]+1);
end
end
end
reg rvalid_d,rvalid_nxt;
reg [1:0] rresp;
reg rlast_d,rlast_nxt;
reg [31:0] mem_addr_d;
reg [35:0] mem_addr_nxt;
reg [3:0] rburst_cnt_d,rburst_cnt_nxt;
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
cur_rd_state <=#0 RST_DR;
rvalid_d <=#0 0;
gnt_vector_d <=#0 1;
for (integer i=0;i<3;i=i+1) begin
r_vector[i] <=#0 i;
end
rlast_d <=#0 0;
mem_addr_d <=#0 0;
rburst_cnt_d <=#0 4'hF;
rdid_d <= #0 0;
end else begin
cur_rd_state <= #1 nxt_rd_state;
rvalid_d <= #1 rvalid_nxt;
gnt_vector_d <= #1 gnt_vector_nxt;
rlast_d <= #1 rlast_nxt;
mem_addr_d <= #1 mem_addr_nxt[31:0];
for (integer i=0;i<3;i=i+1) begin
r_vector[i] <=#1 r_vector_nxt[i];
end
if(pop) begin
if(!ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)) begin
$display("tb_axi_slave_model::============Data does not exits @ location:%h======",mem_addr_d);
#100; $finish;
end else begin
ethernet_frame_pkg::ethernet_mem_data.delete(mem_addr_d);
$display("%0t tb_axi_slave_model::==========Memory freed @ location:%h=============",$realtime,mem_addr_d);
end
end
if(pop_addr) begin
$display("%tWAIT_FOR_READY====tb_axi_slave_model=====rd_addr_poped:%h",$time,ra_fifo[(gnt_vector_d>>1)][0]);
ra_fifo[(gnt_vector_d>>1)].pop_front();
end
rburst_cnt_d <= #1 rburst_cnt_nxt;
rdid_d <= #1 rdid_nxt;
end
end
reg [63:0] rdata;
always @(mem_addr_d) begin
if(clks.rst) begin
if(ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)) begin
rdata = ethernet_frame_pkg::ethernet_mem_data[mem_addr_d];
end else begin
$display("tb_axi_slave_model::+++++++++Memory read TB Fatal error+++++++++++");
$display("time:%t tb_axi_slave_model::+++++++++Data does not exits @ location:%h+++++++++++",$time,mem_addr_d);
rdata = 'hx;
end
rresp = ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)?2'b00:2'b10;
end else begin
rdata = 'hx;
end
end
always @(*) begin
nxt_rd_state = cur_rd_state;
rlast_nxt = (rburst_cnt_d==0);
mem_addr_nxt = {4'h0,mem_addr_d};
pop = rd_dch.RREADY & rd_dch.RVALID;
rburst_cnt_nxt = rburst_cnt_d;
rvalid_nxt = 0;
pop_addr = 0;
arb_nxt = 0;
rdid_nxt = rdid_d;
case(cur_rd_state)
RST_DR: begin
if(clks.rst) begin
nxt_rd_state = VALID_ASSERT;
end else begin
nxt_rd_state = RST_DR;
end
end
VALID_ASSERT: begin
if(!empty_ra_fifo & !(gnt_vector_d==0)) begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
mem_addr_nxt = ra_fifo[(gnt_vector_d>>1)][0];
rdid_nxt = (gnt_vector_d>>1);
arb_nxt = 1;
rburst_cnt_nxt = mem_addr_nxt[35:32]-1;
pop_addr = 1;
end else begin
nxt_rd_state = VALID_ASSERT;
rvalid_nxt = 0;
rburst_cnt_nxt = 4'hF;
end
end
WAIT_FOR_READY: begin
if(rd_dch.RREADY) begin
if(rburst_cnt_d==0) begin
if(!empty_ra_fifo & !(gnt_vector_d==0)) begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
mem_addr_nxt = ra_fifo[(gnt_vector_d>>1)][0];
rdid_nxt = (gnt_vector_d>>1);
rburst_cnt_nxt = mem_addr_nxt[35:32]-1;
pop_addr = 1;
arb_nxt = 1;
end else begin
nxt_rd_state = VALID_ASSERT;
rvalid_nxt = 0;
rburst_cnt_nxt = 4'hF;
end
end else begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
mem_addr_nxt = mem_addr_d + 8;
rburst_cnt_nxt = rburst_cnt_d-1;
end
end else begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
end
end
endcase
end
assign rd_ach.ARREADY = arready_d;
assign rd_dch.RDATA = rdata;
assign rd_dch.RRESP = rresp;
assign rd_dch.RLAST = (rburst_cnt_d == 0);
assign rd_dch.RUSER = 0;
assign rd_dch.RVALID = rvalid_d;
assign rd_dch.RID = rdid_d;
endmodule | module axi_slave_model(
AXI_clks.to_rtl clks,
AXI_rd_addr_ch.slave_if rd_ach,
AXI_rd_data_ch.slave_if rd_dch
); |
reg [35:0] ra_fifo [3][$];
reg [31:0] rd_fifo [3][$];
integer ra_size0,ra_size1,ra_size2;
reg [3:0] rdid_d,rdid_nxt;
reg arready_d,arready_nxt,push_addr,pop;
reg empty_ra_fifo0,empty_ra_fifo1,empty_ra_fifo2;
typedef enum reg [2:0] {RST_AR= 3'b000,WAIT_FOR_VALID=3'h1,READY_ASSERTED=3'h3} ra_state;
typedef enum reg [2:0] {RST_DR= 3'b000,VALID_ASSERT =3'b001,WAIT_FOR_READY=3'b011} rd_state;
ra_state cur_ra_state,nxt_ra_state;
rd_state cur_rd_state,nxt_rd_state;
reg [2:0] gnt_vector_d,gnt_vector_nxt;
reg [2:0] req_vector;
reg [1:0] r_vector[3],r_vector_nxt[3];
reg [1:0] r_v0,r_v1,r_v2;
reg pop_addr,arb_nxt;
reg [1:0] ch_tdm_d,ch_tdm_nxt;
assign {r_v0,r_v1,r_v2} = {r_vector[0],r_vector[1],r_vector[2]};
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
cur_ra_state <= #0 RST_AR;
arready_d <= #0 0;
empty_ra_fifo0 <= #0 1;
empty_ra_fifo1 <= #0 1;
empty_ra_fifo2 <= #0 1;
ra_size0 <= #0 0;
ra_size1 <= #0 0;
ra_size2 <= #0 0;
end else begin
cur_ra_state <= #1 nxt_ra_state;
arready_d <= #1 arready_nxt;
if(push_addr) begin
ra_fifo[rd_ach.ARID].push_back({rd_ach.ARLEN,rd_ach.ARADDR});
$display("%0t tb_axi_slave_model::===========ADDR pushed into FIFO[%d]:%0h==========",$realtime,rd_ach.ARID,{rd_ach.ARLEN,rd_ach.ARADDR});
end
empty_ra_fifo0 <= #1 (ra_fifo[0].size()==0);
empty_ra_fifo1 <= #1 (ra_fifo[1].size()==0);
empty_ra_fifo2 <= #1 (ra_fifo[2].size()==0);
ra_size0 <= #1 ra_fifo[0].size();
ra_size1 <= #1 ra_fifo[1].size();
ra_size2 <= #1 ra_fifo[2].size();
end
end
reg empty_ra_fifo;
always @(*) begin
nxt_ra_state = cur_ra_state;
push_addr = rd_ach.ARVALID & rd_ach.ARREADY;
arready_nxt = 0;
empty_ra_fifo = (empty_ra_fifo0 & empty_ra_fifo1 & empty_ra_fifo2);
case(cur_ra_state)
RST_AR: begin
if(clks.rst) begin
nxt_ra_state = WAIT_FOR_VALID;
end else begin
nxt_ra_state = RST_AR;
end
end
WAIT_FOR_VALID: begin
if(rd_ach.ARVALID) begin
nxt_ra_state = READY_ASSERTED;
arready_nxt = 1;
end
end
READY_ASSERTED: begin
if(rd_ach.ARVALID) begin
nxt_ra_state = READY_ASSERTED;
arready_nxt = 1;
end else begin
nxt_ra_state = WAIT_FOR_VALID;
arready_nxt = 0;
end
end
endcase
end
reg net_arb;
always @(*) begin
req_vector = {~empty_ra_fifo2,~empty_ra_fifo1,~empty_ra_fifo0};
r_vector_nxt[0] = r_vector[0];
for(integer i=0;i<3;i=i+1) begin
gnt_vector_nxt[i] = gnt_vector_d[i];
r_vector_nxt[i] = r_vector[i];
end
net_arb = arb_nxt || (gnt_vector_d==0);
if(net_arb) begin
gnt_vector_nxt[r_vector[0]] = 0;
for(integer i=1;i<3;i=i+1) begin
gnt_vector_nxt[r_vector[i]] = req_vector[r_vector[i]] & ~gnt_vector_nxt[r_vector[i-1]];
if(gnt_vector_nxt[r_vector[i]]) begin
r_vector_nxt[0] = r_vector[i];
end
end
for(integer i=1;i<3;i=i+1) begin
r_vector_nxt[i] = ((r_vector_nxt[i-1]+1)==3)?0:(r_vector_nxt[i-1]+1);
end
end
end
reg rvalid_d,rvalid_nxt;
reg [1:0] rresp;
reg rlast_d,rlast_nxt;
reg [31:0] mem_addr_d;
reg [35:0] mem_addr_nxt;
reg [3:0] rburst_cnt_d,rburst_cnt_nxt;
always @(posedge clks.clk or negedge clks.rst) begin
if(!clks.rst) begin
cur_rd_state <=#0 RST_DR;
rvalid_d <=#0 0;
gnt_vector_d <=#0 1;
for (integer i=0;i<3;i=i+1) begin
r_vector[i] <=#0 i;
end
rlast_d <=#0 0;
mem_addr_d <=#0 0;
rburst_cnt_d <=#0 4'hF;
rdid_d <= #0 0;
end else begin
cur_rd_state <= #1 nxt_rd_state;
rvalid_d <= #1 rvalid_nxt;
gnt_vector_d <= #1 gnt_vector_nxt;
rlast_d <= #1 rlast_nxt;
mem_addr_d <= #1 mem_addr_nxt[31:0];
for (integer i=0;i<3;i=i+1) begin
r_vector[i] <=#1 r_vector_nxt[i];
end
if(pop) begin
if(!ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)) begin
$display("tb_axi_slave_model::============Data does not exits @ location:%h======",mem_addr_d);
#100; $finish;
end else begin
ethernet_frame_pkg::ethernet_mem_data.delete(mem_addr_d);
$display("%0t tb_axi_slave_model::==========Memory freed @ location:%h=============",$realtime,mem_addr_d);
end
end
if(pop_addr) begin
$display("%tWAIT_FOR_READY====tb_axi_slave_model=====rd_addr_poped:%h",$time,ra_fifo[(gnt_vector_d>>1)][0]);
ra_fifo[(gnt_vector_d>>1)].pop_front();
end
rburst_cnt_d <= #1 rburst_cnt_nxt;
rdid_d <= #1 rdid_nxt;
end
end
reg [63:0] rdata;
always @(mem_addr_d) begin
if(clks.rst) begin
if(ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)) begin
rdata = ethernet_frame_pkg::ethernet_mem_data[mem_addr_d];
end else begin
$display("tb_axi_slave_model::+++++++++Memory read TB Fatal error+++++++++++");
$display("time:%t tb_axi_slave_model::+++++++++Data does not exits @ location:%h+++++++++++",$time,mem_addr_d);
rdata = 'hx;
end
rresp = ethernet_frame_pkg::ethernet_mem_data.exists(mem_addr_d)?2'b00:2'b10;
end else begin
rdata = 'hx;
end
end
always @(*) begin
nxt_rd_state = cur_rd_state;
rlast_nxt = (rburst_cnt_d==0);
mem_addr_nxt = {4'h0,mem_addr_d};
pop = rd_dch.RREADY & rd_dch.RVALID;
rburst_cnt_nxt = rburst_cnt_d;
rvalid_nxt = 0;
pop_addr = 0;
arb_nxt = 0;
rdid_nxt = rdid_d;
case(cur_rd_state)
RST_DR: begin
if(clks.rst) begin
nxt_rd_state = VALID_ASSERT;
end else begin
nxt_rd_state = RST_DR;
end
end
VALID_ASSERT: begin
if(!empty_ra_fifo & !(gnt_vector_d==0)) begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
mem_addr_nxt = ra_fifo[(gnt_vector_d>>1)][0];
rdid_nxt = (gnt_vector_d>>1);
arb_nxt = 1;
rburst_cnt_nxt = mem_addr_nxt[35:32]-1;
pop_addr = 1;
end else begin
nxt_rd_state = VALID_ASSERT;
rvalid_nxt = 0;
rburst_cnt_nxt = 4'hF;
end
end
WAIT_FOR_READY: begin
if(rd_dch.RREADY) begin
if(rburst_cnt_d==0) begin
if(!empty_ra_fifo & !(gnt_vector_d==0)) begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
mem_addr_nxt = ra_fifo[(gnt_vector_d>>1)][0];
rdid_nxt = (gnt_vector_d>>1);
rburst_cnt_nxt = mem_addr_nxt[35:32]-1;
pop_addr = 1;
arb_nxt = 1;
end else begin
nxt_rd_state = VALID_ASSERT;
rvalid_nxt = 0;
rburst_cnt_nxt = 4'hF;
end
end else begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
mem_addr_nxt = mem_addr_d + 8;
rburst_cnt_nxt = rburst_cnt_d-1;
end
end else begin
nxt_rd_state = WAIT_FOR_READY;
rvalid_nxt = 1;
end
end
endcase
end
assign rd_ach.ARREADY = arready_d;
assign rd_dch.RDATA = rdata;
assign rd_dch.RRESP = rresp;
assign rd_dch.RLAST = (rburst_cnt_d == 0);
assign rd_dch.RUSER = 0;
assign rd_dch.RVALID = rvalid_d;
assign rd_dch.RID = rdid_d;
endmodule | 1 |
137,601 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function new ();
ethernet_poly = 32'hedb88320;
endfunction | function new (); |
ethernet_poly = 32'hedb88320;
endfunction | 1 |
137,602 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function logic[31:0] clc_CRC(input integer net_size);
integer rem,div,i,j;
div = net_size/64;
rem = (net_size%64)/8;
clc_CRC = 32'hFFFFFFFF;
for(i=0,j=net_size-1;i<div;i=i+1,j=j-64) begin
clc_CRC=nextCRC32_D64(raw_pkt[j-:64],clc_CRC);
end
case(rem)
1:begin
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
2:begin
clc_CRC=nextCRC32_D16(raw_pkt[15:0],clc_CRC);
end
3:begin
clc_CRC=nextCRC32_D16(raw_pkt[23:8],clc_CRC);
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
4:begin
clc_CRC=nextCRC32_D32(raw_pkt[31:0],clc_CRC);
end
5:begin
clc_CRC=nextCRC32_D32(raw_pkt[39:8],clc_CRC);
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
6:begin
clc_CRC=nextCRC32_D32(raw_pkt[47:16],clc_CRC);
clc_CRC=nextCRC32_D16(raw_pkt[15:0],clc_CRC);
end
7:begin
clc_CRC=nextCRC32_D32(raw_pkt[55:24],clc_CRC);
clc_CRC=nextCRC32_D16(raw_pkt[23:8],clc_CRC);
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
endcase
endfunction | function logic[31:0] clc_CRC(input integer net_size); |
integer rem,div,i,j;
div = net_size/64;
rem = (net_size%64)/8;
clc_CRC = 32'hFFFFFFFF;
for(i=0,j=net_size-1;i<div;i=i+1,j=j-64) begin
clc_CRC=nextCRC32_D64(raw_pkt[j-:64],clc_CRC);
end
case(rem)
1:begin
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
2:begin
clc_CRC=nextCRC32_D16(raw_pkt[15:0],clc_CRC);
end
3:begin
clc_CRC=nextCRC32_D16(raw_pkt[23:8],clc_CRC);
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
4:begin
clc_CRC=nextCRC32_D32(raw_pkt[31:0],clc_CRC);
end
5:begin
clc_CRC=nextCRC32_D32(raw_pkt[39:8],clc_CRC);
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
6:begin
clc_CRC=nextCRC32_D32(raw_pkt[47:16],clc_CRC);
clc_CRC=nextCRC32_D16(raw_pkt[15:0],clc_CRC);
end
7:begin
clc_CRC=nextCRC32_D32(raw_pkt[55:24],clc_CRC);
clc_CRC=nextCRC32_D16(raw_pkt[23:8],clc_CRC);
clc_CRC=nextCRC32_D8(raw_pkt[7:0],clc_CRC);
end
endcase
endfunction | 1 |
137,603 | data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv | 79,197,809 | ethernet_frame_pkg.sv | sv | 383 | 108 | [] | [] | [] | null | line:1: before: "package" | null | 1: b'%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:2: Cannot find include file: TB_CRC_block.sv\n`include "TB_CRC_block.sv" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.v\n data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb,data/full_repos/permissive/79197809/TB_CRC_block.sv.sv\n TB_CRC_block.sv\n TB_CRC_block.sv.v\n TB_CRC_block.sv.sv\n obj_dir/TB_CRC_block.sv\n obj_dir/TB_CRC_block.sv.v\n obj_dir/TB_CRC_block.sv.sv\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:19: Unsupported: classes\nclass ethernet_frame;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:38: syntax error, unexpected IDENTIFIER\n constraint on_payload_size {payload_size > 63 && payload_size < 1523;}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_payload {PAYLOAD.size()==payload_size;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_QoS {QoS inside {8\'h01,8\'h02,8\'h04,8\'h08,8\'h10,8\'h20,8\'h40,8\'h80};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:50: syntax error, unexpected IDENTIFIER\n div = net_size/64; \n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:144: syntax error, unexpected IDENTIFIER\n net_size = (48*2)+16+(payload_size*8);\n ^~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:181: syntax error, unexpected IDENTIFIER\n rem = net_size%64;\n ^~~\n%Error: Unsupported: [*] wildcard associative arrays\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: classes\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:248: syntax error, unexpected IDENTIFIER\n constraint on_mem_addr { mem_addr % 16 ==0;}\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:249: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint on_mem_addr_start_end { mem_addr>= 32\'hFF000000; & mem_addr<= 32\'hFF0FFFFF;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:255: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n randomize(mem_addr);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:271: Unsupported: new constructor\n function new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:272: Unsupported: new with arguments\n eth_frame = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:273: Unsupported: new with arguments\n addr_gen_obj = new();\n ^~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: syntax error, unexpected \'(\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:283: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n assert(eth_frame.randomize() with {payload_size==64;});\n ^~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n assert(addr_gen_obj.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:289: syntax error, unexpected \'(\'\n assert(addr_gen_obj.randomize());\n ^\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:243: Unsupported: class within class\nclass mem_addr_gen;\n^~~~~\n%Error: data/full_repos/permissive/79197809/MS_PROJECT_MEM_SEP/tb/ethernet_frame_pkg.sv:381: syntax error, unexpected endpackage\nendpackage \n^~~~~~~~~~\n%Error: Cannot continue\n' | 299,857 | function | function void print();
$display("=-=-=-=-=-=-=-=-=-=-=-=ETHERNET FRAME=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
$display("DA:%0h",
this.DA[47:40],"::%0h",
this.DA[39:32],"::%0h",
this.DA[31:24],"::%0h",
this.DA[23:16],"::%0h",
this.DA[15:8] ,"::%0h",
this.DA[7:0] );
$display("SA:%0h",
this.SA[47:40],"::%0h",
this.SA[39:32],"::%0h",
this.SA[31:24],"::%0h",
this.SA[23:16],"::%0h",
this.SA[15:8] ,"::%0h",
this.SA[7:0] );
$display("ETHER_TYPE:%0h",this.ETHER_TYPE);
$display("PAYLOAD:");
for(integer i=0;i<payload_size;i++) begin
$write("%0h",this.PAYLOAD[i],":");
end
$display("\nCRC:%0h",this.CRC);
$display("\n-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
endfunction | function void print(); |
$display("=-=-=-=-=-=-=-=-=-=-=-=ETHERNET FRAME=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
$display("DA:%0h",
this.DA[47:40],"::%0h",
this.DA[39:32],"::%0h",
this.DA[31:24],"::%0h",
this.DA[23:16],"::%0h",
this.DA[15:8] ,"::%0h",
this.DA[7:0] );
$display("SA:%0h",
this.SA[47:40],"::%0h",
this.SA[39:32],"::%0h",
this.SA[31:24],"::%0h",
this.SA[23:16],"::%0h",
this.SA[15:8] ,"::%0h",
this.SA[7:0] );
$display("ETHER_TYPE:%0h",this.ETHER_TYPE);
$display("PAYLOAD:");
for(integer i=0;i<payload_size;i++) begin
$write("%0h",this.PAYLOAD[i],":");
end
$display("\nCRC:%0h",this.CRC);
$display("\n-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-");
endfunction | 1 |
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