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137,256 | data/full_repos/permissive/77022825/Example/rtl/ud_counter.v | 77,022,825 | ud_counter.v | v | 20 | 41 | [] | [] | [] | [(1, 19)] | null | data/verilator_xmls/62cff443-5ab1-4e97-adbd-9aaf9ea9d6e1.xml | null | 295,679 | module | module ud_counter
#(
parameter WIDTH = 8
)
(
input clk,
input arst_n,
input en,
input up,
output reg [WIDTH-1:0] cnt
);
always @ (posedge clk or negedge arst_n)
if (!arst_n)
cnt <= 0;
else if (en)
cnt <= up ? cnt + 1 : cnt - 1;
endmodule | module ud_counter
#(
parameter WIDTH = 8
)
(
input clk,
input arst_n,
input en,
input up,
output reg [WIDTH-1:0] cnt
); |
always @ (posedge clk or negedge arst_n)
if (!arst_n)
cnt <= 0;
else if (en)
cnt <= up ? cnt + 1 : cnt - 1;
endmodule | 0 |
137,257 | data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v | 77,469,627 | alorium_lfsr_tb.v | v | 49 | 47 | [] | [] | [] | null | line:90: before: "$" | null | 1: b'%Error: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:1: Cannot find include file: alorium_lfsr.v\n`include "alorium_lfsr.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77469627/extras/rtl,data/full_repos/permissive/77469627/alorium_lfsr.v\n data/full_repos/permissive/77469627/extras/rtl,data/full_repos/permissive/77469627/alorium_lfsr.v.v\n data/full_repos/permissive/77469627/extras/rtl,data/full_repos/permissive/77469627/alorium_lfsr.v.sv\n alorium_lfsr.v\n alorium_lfsr.v.v\n alorium_lfsr.v.sv\n obj_dir/alorium_lfsr.v\n obj_dir/alorium_lfsr.v.v\n obj_dir/alorium_lfsr.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10 in = 8\'b10101010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #15 new_seed = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #5 new_seed = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #25 enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #25 enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #5 $stop;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77469627/extras/rtl/alorium_lfsr_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock;\n ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n' | 295,684 | module | module alorium_lfsr_tb();
reg clock, reset, new_seed, enable, long_hb;
reg [7:0] in;
wire heartbeat;
wire [7:0] out;
initial begin
clock = 1;
reset = 1;
new_seed = 0;
enable = 0;
long_hb = 1;
#5 reset = 0;
#10 reset = 1;
#10 in = 8'b10101010;
#15 new_seed = 1;
#5 new_seed = 0;
#5 enable = 1;
#5 enable = 0;
#25 enable = 1;
#5 enable = 0;
#25 enable = 1;
#200;
#5 $stop;
end
always begin
#5 clock = ~clock;
end
alorium_lfsr lfsr_inst (
.clk (clock),
.reset_n (reset),
.new_seed (new_seed),
.enable (enable),
.seed (in),
.long_hb (long_hb),
.heartbeat (heartbeat),
.lfsr_data (out));
endmodule | module alorium_lfsr_tb(); |
reg clock, reset, new_seed, enable, long_hb;
reg [7:0] in;
wire heartbeat;
wire [7:0] out;
initial begin
clock = 1;
reset = 1;
new_seed = 0;
enable = 0;
long_hb = 1;
#5 reset = 0;
#10 reset = 1;
#10 in = 8'b10101010;
#15 new_seed = 1;
#5 new_seed = 0;
#5 enable = 1;
#5 enable = 0;
#25 enable = 1;
#5 enable = 0;
#25 enable = 1;
#200;
#5 $stop;
end
always begin
#5 clock = ~clock;
end
alorium_lfsr lfsr_inst (
.clk (clock),
.reset_n (reset),
.new_seed (new_seed),
.enable (enable),
.seed (in),
.long_hb (long_hb),
.heartbeat (heartbeat),
.lfsr_data (out));
endmodule | 2 |
137,258 | data/full_repos/permissive/77662186/bomb.v | 77,662,186 | bomb.v | v | 1,015 | 252 | [] | [] | [] | null | line:799 column:5: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/77662186/bomb.v:35: syntax error, unexpected type, expecting IDENTIFIER or '=' or do or final\nreg [2:0]type;\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:111: syntax error, unexpected '(', expecting IDENTIFIER\nkey(.clk(clock), .rst(reset), .Data(index), .keypadRow(keypadR), .keypadCol(keypadC), .KEY(K));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:131: syntax error, unexpected <=, expecting '('\n type <= 0;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:157: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:164: syntax error, unexpected <=, expecting '('\n type <= 4;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:173: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:181: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:188: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:194: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:201: syntax error, unexpected <=, expecting '('\n type <= 5;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:544: syntax error, unexpected '(', expecting IDENTIFIER\nmove(.clk(clock), .rst(reset), .button(button[0]), .LED(isMove[0]));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:713: syntax error, unexpected ==, expecting '('\n else if(type == 1)\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:728: syntax error, unexpected else\n else if(type == 3)\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:736: syntax error, unexpected else\n else\n ^~~~\n%Error: Exiting due to 14 error(s)\n" | 295,748 | module | module bomb(reset, clock, button, stop, iwanttostep, isBomb, cancel, led, verf, verf1, keypadC, keypadR, dotC, dotR, hex1, hex2, hex3, hex4, hex5, hex6, vga_hs, vga_vs, vga_r, vga_g, vga_b);
`define fre 32'd50000000
input clock, reset, stop, cancel, isBomb, iwanttostep;
input [3:0]button;
input [3:0]keypadC;
output [3:0]keypadR;
output [15:0]dotC;
output [7:0]dotR;
output [6:0]hex1, hex2, hex3, hex4, hex5, hex6;
output [7:0]led;
output verf, verf1;
reg [15:0]dotC;
reg [7:0]dotR;
reg [31:0]cnt1, cnt2, cnt3;
reg [7:0]led;
reg [3:0]tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
reg div_clk_1s, div_clk_10k;
reg twinkle;
reg [3:0]area;
reg [3:0]State,NextState;
reg [3:0]times;
reg [127:0]pos, twink;
reg second;
reg gameover;
reg verf;
reg win;
wire verf1;
wire [3:0]isMove;
wire [3:0]index;
wire K;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9;
reg [2:0]type;
reg typeGameover;
output vga_hs, vga_vs;
output [3:0] vga_r, vga_g, vga_b;
reg vga_hs, vga_vs;
reg [3:0] vga_r, vga_g, vga_b;
reg [10:0] counths;
reg [9:0] countvs;
reg [9:0] p_h, p_v;
reg valid;
reg [31:0]c1,c3;
reg [1:0]c2;
reg [2:0]c4;
reg [31:0]c5,c7;
reg c6;
reg [2:0]c8;
always @(posedge clock)
begin
if(c5 == `fre/4)
begin
c5 = 0;
c6 = c6 + 1;
end
else
begin
c5 = c5 + 1;
end
end
always @(posedge clock)
begin
if(c7 == 5000)
begin
c7 = 0;
c8 = c8 + 1;
end
else
c7 = c7 + 1;
end
always @(posedge clock)
begin
if(c1 == `fre/2)
begin
c1 = 0;
c2 = c2 + 1;
if(c2 == 4)
begin
c2 = 0;
end
end
else
begin
c1 = c1 + 1;
end
end
always @(posedge clock)
begin
if(c3 == 5000)
begin
c3 = 0;
c4 = c4 + 1;
end
else
begin
c3 = c3 + 1;
end
end
assign verf1 = verf;
key(.clk(clock), .rst(reset), .Data(index), .keypadRow(keypadR), .keypadCol(keypadC), .KEY(K));
always @(negedge reset or posedge div_clk_10k)
begin
if(!reset)
times=4'b0000;
else
begin
if(times == 8)
times=0;
else
times=times+1;
end
end
always @(negedge reset or posedge K or posedge cancel)
begin
if(!reset)
begin
type <= 0;
pos[127:0] <= 0;
twink[127:0] <= 0 ;
second <= 0;
verf <= 1;
end
else
begin
if(cancel == 1)
begin
if(stop == 1)
begin
second <= 0;
verf <= 1;
end
end
else if(stop == 1)
begin
if(second == 0)
begin
second <= 1;
verf <= ~verf;
end
else if(isBomb == 1 && pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] != 1 && twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0)
begin
type <= 3;
twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
second <= 0;
verf <= ~verf;
end
else if(isBomb == 1 && pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] != 1 && twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 4;
twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 0;
second <= 0;
verf <= ~verf;
end
else
begin
if(iwanttostep == 1 && twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 1;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 0;
verf <= ~verf;
second <= 0;
end
else if(twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0 && pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0)
begin
type <= 1;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
verf <= ~verf;
second <= 0;
end
else if(twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 3;
verf <= ~verf;
second <= 0;
end
else if(pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0)
begin
type <= 1;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
verf <= ~verf;
second <= 0;
end
else if(pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 5;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
verf <= ~verf;
second <= 0;
end
else
begin
second <= 0;
verf <= ~verf;
end
end
end
else
verf <= 1;
end
end
always @(times)
begin
if(!reset)
begin
dotC = 16'b0000000000000000;
dotR = 8'b11111111;
end
else if(win)
begin
begin
if(c2 == 0)
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b1110_1110_1110_1110;
2:dotC=16'b0010_0010_0010_0010;
3:dotC=16'b1110_1110_1110_1110;
4:dotC=16'b1010_1010_1010_1010;
5:dotC=16'b1110_1110_1110_1110;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
else if(c2 == 3)
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b1101110_1110_11101;
2:dotC=16'b0100010001000100;
3:dotC=16'b1101110_1110_11101;
4:dotC=16'b0101010_1010_10101;
5:dotC=16'b1101110_1110_11101;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
else if(c2 == 2)
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b10_1110_1110_111011;
2:dotC=16'b1000100010001000;
3:dotC=16'b10_1110_1110_111011;
4:dotC=16'b10_1010_1010_101010;
5:dotC=16'b10_1110_1110_111011;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
else
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b0_1110_1110_1110111;
2:dotC=16'b0001000100010001;
3:dotC=16'b0_1110_1110_1110111;
4:dotC=16'b0_1010_1010_1010101;
5:dotC=16'b0_1110_1110_1110111;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
end
end
else if(!gameover)
begin
case(times)
0:
begin
dotR = 8'b01111111;
dotC = twinkle ? pos[15:0] + twink[15:0] : pos[15:0];
end
1:
begin
dotR = 8'b10111111;
dotC = twinkle ? pos[31:16] + twink[31:16] : pos[31:16];
end
2:
begin
dotR = 8'b11011111;
dotC = twinkle ? pos[47:32] + twink[47:32] : pos[47:32];
end
3:
begin
dotR = 8'b11101111;
dotC = twinkle ? pos[63:48] + twink[63:48] : pos[63:48];
end
4:
begin
dotR = 8'b11110111;
dotC = twinkle ? pos[79:64] + twink[79:64] : pos[79:64];
end
5:
begin
dotR = 8'b11111011;
dotC = twinkle ? pos[95:80] + twink[95:80] : pos[95:80];
end
6:
begin
dotR = 8'b11111101;
dotC = twinkle ? pos[111:96] + twink[111:96] : pos[111:96];
end
7:
begin
dotR = 8'b11111110;
dotC = twinkle ? pos[127:112] + twink[127:112] : pos[127:112];
end
endcase
end
else
begin
if(c6 == 1)
begin
case(c8)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c8)
0:dotC=16'b0111111001111110;
1:dotC=16'b0111111001111110;
2:dotC=16'b0000011000000110;
3:dotC=16'b0111011001110110;
4:dotC=16'b0111011001110110;
5:dotC=16'b0110011001100110;
6:dotC=16'b0111111001111110;
7:dotC=16'b0111111001111110;
endcase
end
else
begin
dotR = 8'b11111111;
dotC = 0;
end
end
end
always @(negedge reset or posedge clock or posedge pos[87])
begin
if(!reset)
begin
gameover = 0;
State = S0;
typeGameover = 0;
win = 0;
end
else
begin
if(pos[87] == 1)
begin
gameover = 1;
State = S8;
typeGameover = 1;
end
else if(pos == -1-(1<<87))
begin
win = 1;
State = S9;
end
else
begin
State = NextState;
typeGameover = 0;
gameover = 0;
end
end
end
always @(negedge reset or posedge clock)
begin
if( !reset )
begin
cnt2 <= 32'd0;
div_clk_10k <= 1'b0;
end
else
begin
if( cnt2 == 32'd2500)
begin
cnt2 <= 32'd0;
div_clk_10k <= ~div_clk_10k;
end
else
begin
cnt2 <= cnt2 + 32'd1;
end
end
end
always @(negedge reset or posedge clock)
begin
if( !reset )
begin
cnt1 <=32'd0;
div_clk_1s <= 1'b0;
cnt3 <=32'd0;
twinkle <= 1'b0;
end
else
begin
if( cnt3 == 32'd12500000)
begin
twinkle <= ~twinkle;
cnt3 <= 32'd0;
end
else
cnt3 <= cnt3 + 32'd1;
if(cnt1 == 32'd25000000)
begin
cnt1 <= 32'd0;
div_clk_1s <= ~div_clk_1s;
end
else
begin
cnt1 <= cnt1 + 32'd1;
end
end
end
always @(negedge reset or posedge div_clk_1s)
begin
if(!reset)
begin
tmp1 = 0;
tmp2 = 0;
tmp3 = 0;
tmp4 = 0;
tmp5 = 0;
tmp6 = 0;
end
else
begin
if(stop == 1 && gameover != 1 && win != 1)
begin
tmp1 = tmp1+1;
if(tmp1 == 10)
begin
tmp1 = 0;
tmp2 = tmp2+1;
end
if(tmp2 == 6)
begin
tmp2 = 0;
tmp3 = tmp3+1;
end
if(tmp3 == 10)
begin
tmp3 = 0;
tmp4 = tmp4+1;
end
if(tmp4 == 6)
begin
tmp4 = 0;
tmp5 = tmp5+1;
end
if(tmp5 == 10)
begin
tmp5 = 0;
tmp6 = tmp6+1;
end
end
else
begin
tmp1 = tmp1;
end
end
end
Seven s1(.sin(tmp1), .sout(hex1));
Seven s2(.sin(tmp2), .sout(hex2));
Seven s3(.sin(tmp3), .sout(hex3));
Seven s4(.sin(tmp4), .sout(hex4));
Seven s5(.sin(tmp5), .sout(hex5));
Seven s6(.sin(tmp6), .sout(hex6));
move(.clk(clock), .rst(reset), .button(button[0]), .LED(isMove[0]));
move(.clk(clock), .rst(reset), .button(button[1]), .LED(isMove[1]));
move(.clk(clock), .rst(reset), .button(button[2]), .LED(isMove[2]));
move(.clk(clock), .rst(reset), .button(button[3]), .LED(isMove[3]));
always@(posedge isMove[0] or posedge isMove[1] or posedge isMove[2] or posedge isMove[3])
begin
case(State)
S0:
begin
if(isMove[0] == 1)
NextState = S1;
else if(isMove[2] == 1)
NextState = S4;
else
NextState = S0;
end
S1:
begin
if(isMove[0] == 1)
NextState = S2;
else if(isMove[2] == 1)
NextState = S5;
else if(isMove[1] == 1)
NextState = S0;
else
NextState = S1;
end
S2:
begin
if(isMove[0] == 1)
NextState = S3;
else if(isMove[2] == 1)
NextState = S6;
else if(isMove[1] == 1)
NextState = S1;
else
NextState = S2;
end
S3:
begin
if(isMove[2] == 1)
NextState = S7;
else if(isMove[1] == 1)
NextState = S2;
else
NextState = S3;
end
S4:
begin
if(isMove[0] == 1)
NextState = S5;
else if(isMove[3] == 1)
NextState = S0;
else
NextState = S4;
end
S5:
begin
if(isMove[0] == 1)
NextState = S6;
else if(isMove[3] == 1)
NextState = S1;
else if(isMove[1] == 1)
NextState = S4;
else
NextState = S5;
end
S6:
begin
if(isMove[0] == 1)
NextState = S7;
else if(isMove[3] == 1)
NextState = S2;
else if(isMove[1] == 1)
NextState = S5;
else
NextState = S6;
end
S7:
begin
if(isMove[1] == 1)
NextState = S6;
else if(isMove[3] == 1)
NextState = S3;
else
NextState = S7;
end
default:
NextState = S0;
endcase
end
always@(State)
begin
case(State)
S7:led = 8'b00000001;
S6:led = 8'b00000010;
S5:led = 8'b00000100;
S4:led = 8'b00001000;
S3:led = 8'b00010000;
S2:led = 8'b00100000;
S1:led = 8'b01000000;
S0:led = 8'b10000000;
default:led = 8'b11111111;
endcase
end
always@(negedge reset or posedge clock)
begin
if(!reset)
begin
counths <= 11'd0;
countvs <= 10'd0;
end
else
begin
counths <= (counths == 11'd1600) ? 11'd0 : counths + 16'd1;
countvs <= (countvs == 10'd525) ? 10'd0 : (counths == 11'd1600) ? countvs + 10'd1 : countvs;
end
end
always@(negedge reset or posedge clock)
begin
if(!reset)
begin
vga_hs <= 1'b0;
vga_vs <= 1'b0;
valid <= 1'b0;
end
else
begin
vga_hs <= (counths < 11'd192 || counths > 11'd1568) ? 1'b0 : 1'b1;
vga_vs <= (countvs < 10'd2 || countvs > 10'd515) ? 1'b0 : 1'b1;
valid <= (countvs > 10'd35 && countvs < 10'd516 && counths > 11'd288 && counths < 11'd1568) ? 1'b1 : 1'b0;
end
end
always@(negedge reset or posedge clock)
begin
if(!reset)
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
else
begin
if(valid)
begin
if(typeGameover == 1)
begin
if((countvs - counths + 683 + 928 > 928) && (countvs - counths + 623 + 928 < 928) || (countvs + counths - 1173 + 928 > 928) && (countvs + counths - 1233 + 928 < 928))
begin
vga_r <= 4'd15;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else if(type == 1)
begin
if(8*(countvs-35-240)*(countvs-275) + 3*(counths-288-640)*(counths-288-640) < 432900 && 8*(countvs-35-240)*(countvs-275) + 3*(counths-288-640)*(counths-288-640) > 156300)
begin
vga_r <= 4'd0;
vga_g <= 4'd15;
vga_b <= 4'd0;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else if(type == 3)
begin
if(8*17*(countvs-275)*(countvs-275)-5*16*(countvs-275)*(counths<928? (counths-928) :928-counths)+3*17*(counths-928)*(counths-928) < 1000000)
begin
vga_r <= 4'd15;
vga_g <= 4'd8;
vga_b <= 4'd11;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else if(type == 4)
begin
if(8*17*(countvs-275)*(countvs-275)-5*16*(countvs-275)*(counths<928? (counths-928) :928-counths)+3*17*(counths-928)*(counths-928) < 1000000)
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
else
begin
vga_r <= 4'd15;
vga_g <= 4'd15;
vga_b <= 4'd15;
end
end
else if(type == 5)
begin
if((counths < 668 || counths > 1188 || countvs < 95 || countvs > 455) && counths > 578 && counths < 1278)
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd15;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
end
endmodule | module bomb(reset, clock, button, stop, iwanttostep, isBomb, cancel, led, verf, verf1, keypadC, keypadR, dotC, dotR, hex1, hex2, hex3, hex4, hex5, hex6, vga_hs, vga_vs, vga_r, vga_g, vga_b); |
`define fre 32'd50000000
input clock, reset, stop, cancel, isBomb, iwanttostep;
input [3:0]button;
input [3:0]keypadC;
output [3:0]keypadR;
output [15:0]dotC;
output [7:0]dotR;
output [6:0]hex1, hex2, hex3, hex4, hex5, hex6;
output [7:0]led;
output verf, verf1;
reg [15:0]dotC;
reg [7:0]dotR;
reg [31:0]cnt1, cnt2, cnt3;
reg [7:0]led;
reg [3:0]tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
reg div_clk_1s, div_clk_10k;
reg twinkle;
reg [3:0]area;
reg [3:0]State,NextState;
reg [3:0]times;
reg [127:0]pos, twink;
reg second;
reg gameover;
reg verf;
reg win;
wire verf1;
wire [3:0]isMove;
wire [3:0]index;
wire K;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9;
reg [2:0]type;
reg typeGameover;
output vga_hs, vga_vs;
output [3:0] vga_r, vga_g, vga_b;
reg vga_hs, vga_vs;
reg [3:0] vga_r, vga_g, vga_b;
reg [10:0] counths;
reg [9:0] countvs;
reg [9:0] p_h, p_v;
reg valid;
reg [31:0]c1,c3;
reg [1:0]c2;
reg [2:0]c4;
reg [31:0]c5,c7;
reg c6;
reg [2:0]c8;
always @(posedge clock)
begin
if(c5 == `fre/4)
begin
c5 = 0;
c6 = c6 + 1;
end
else
begin
c5 = c5 + 1;
end
end
always @(posedge clock)
begin
if(c7 == 5000)
begin
c7 = 0;
c8 = c8 + 1;
end
else
c7 = c7 + 1;
end
always @(posedge clock)
begin
if(c1 == `fre/2)
begin
c1 = 0;
c2 = c2 + 1;
if(c2 == 4)
begin
c2 = 0;
end
end
else
begin
c1 = c1 + 1;
end
end
always @(posedge clock)
begin
if(c3 == 5000)
begin
c3 = 0;
c4 = c4 + 1;
end
else
begin
c3 = c3 + 1;
end
end
assign verf1 = verf;
key(.clk(clock), .rst(reset), .Data(index), .keypadRow(keypadR), .keypadCol(keypadC), .KEY(K));
always @(negedge reset or posedge div_clk_10k)
begin
if(!reset)
times=4'b0000;
else
begin
if(times == 8)
times=0;
else
times=times+1;
end
end
always @(negedge reset or posedge K or posedge cancel)
begin
if(!reset)
begin
type <= 0;
pos[127:0] <= 0;
twink[127:0] <= 0 ;
second <= 0;
verf <= 1;
end
else
begin
if(cancel == 1)
begin
if(stop == 1)
begin
second <= 0;
verf <= 1;
end
end
else if(stop == 1)
begin
if(second == 0)
begin
second <= 1;
verf <= ~verf;
end
else if(isBomb == 1 && pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] != 1 && twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0)
begin
type <= 3;
twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
second <= 0;
verf <= ~verf;
end
else if(isBomb == 1 && pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] != 1 && twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 4;
twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 0;
second <= 0;
verf <= ~verf;
end
else
begin
if(iwanttostep == 1 && twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 1;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 0;
verf <= ~verf;
second <= 0;
end
else if(twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0 && pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0)
begin
type <= 1;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
verf <= ~verf;
second <= 0;
end
else if(twink[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 3;
verf <= ~verf;
second <= 0;
end
else if(pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 0)
begin
type <= 1;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
verf <= ~verf;
second <= 0;
end
else if(pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] == 1)
begin
type <= 5;
pos[16*((index/4)+(State/4)*4)+4*(State%4)+index%4] <= 1;
verf <= ~verf;
second <= 0;
end
else
begin
second <= 0;
verf <= ~verf;
end
end
end
else
verf <= 1;
end
end
always @(times)
begin
if(!reset)
begin
dotC = 16'b0000000000000000;
dotR = 8'b11111111;
end
else if(win)
begin
begin
if(c2 == 0)
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b1110_1110_1110_1110;
2:dotC=16'b0010_0010_0010_0010;
3:dotC=16'b1110_1110_1110_1110;
4:dotC=16'b1010_1010_1010_1010;
5:dotC=16'b1110_1110_1110_1110;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
else if(c2 == 3)
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b1101110_1110_11101;
2:dotC=16'b0100010001000100;
3:dotC=16'b1101110_1110_11101;
4:dotC=16'b0101010_1010_10101;
5:dotC=16'b1101110_1110_11101;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
else if(c2 == 2)
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b10_1110_1110_111011;
2:dotC=16'b1000100010001000;
3:dotC=16'b10_1110_1110_111011;
4:dotC=16'b10_1010_1010_101010;
5:dotC=16'b10_1110_1110_111011;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
else
begin
case(c4)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c4)
0:dotC=16'b0000_0000_0000_0000;
1:dotC=16'b0_1110_1110_1110111;
2:dotC=16'b0001000100010001;
3:dotC=16'b0_1110_1110_1110111;
4:dotC=16'b0_1010_1010_1010101;
5:dotC=16'b0_1110_1110_1110111;
6:dotC=16'b0000_0000_0000_0000;
7:dotC=16'b0000_0000_0000_0000;
endcase
end
end
end
else if(!gameover)
begin
case(times)
0:
begin
dotR = 8'b01111111;
dotC = twinkle ? pos[15:0] + twink[15:0] : pos[15:0];
end
1:
begin
dotR = 8'b10111111;
dotC = twinkle ? pos[31:16] + twink[31:16] : pos[31:16];
end
2:
begin
dotR = 8'b11011111;
dotC = twinkle ? pos[47:32] + twink[47:32] : pos[47:32];
end
3:
begin
dotR = 8'b11101111;
dotC = twinkle ? pos[63:48] + twink[63:48] : pos[63:48];
end
4:
begin
dotR = 8'b11110111;
dotC = twinkle ? pos[79:64] + twink[79:64] : pos[79:64];
end
5:
begin
dotR = 8'b11111011;
dotC = twinkle ? pos[95:80] + twink[95:80] : pos[95:80];
end
6:
begin
dotR = 8'b11111101;
dotC = twinkle ? pos[111:96] + twink[111:96] : pos[111:96];
end
7:
begin
dotR = 8'b11111110;
dotC = twinkle ? pos[127:112] + twink[127:112] : pos[127:112];
end
endcase
end
else
begin
if(c6 == 1)
begin
case(c8)
0:dotR=8'b01111111;
1:dotR=8'b10111111;
2:dotR=8'b11011111;
3:dotR=8'b11101111;
4:dotR=8'b11110111;
5:dotR=8'b11111011;
6:dotR=8'b11111101;
7:dotR=8'b11111110;
endcase
case(c8)
0:dotC=16'b0111111001111110;
1:dotC=16'b0111111001111110;
2:dotC=16'b0000011000000110;
3:dotC=16'b0111011001110110;
4:dotC=16'b0111011001110110;
5:dotC=16'b0110011001100110;
6:dotC=16'b0111111001111110;
7:dotC=16'b0111111001111110;
endcase
end
else
begin
dotR = 8'b11111111;
dotC = 0;
end
end
end
always @(negedge reset or posedge clock or posedge pos[87])
begin
if(!reset)
begin
gameover = 0;
State = S0;
typeGameover = 0;
win = 0;
end
else
begin
if(pos[87] == 1)
begin
gameover = 1;
State = S8;
typeGameover = 1;
end
else if(pos == -1-(1<<87))
begin
win = 1;
State = S9;
end
else
begin
State = NextState;
typeGameover = 0;
gameover = 0;
end
end
end
always @(negedge reset or posedge clock)
begin
if( !reset )
begin
cnt2 <= 32'd0;
div_clk_10k <= 1'b0;
end
else
begin
if( cnt2 == 32'd2500)
begin
cnt2 <= 32'd0;
div_clk_10k <= ~div_clk_10k;
end
else
begin
cnt2 <= cnt2 + 32'd1;
end
end
end
always @(negedge reset or posedge clock)
begin
if( !reset )
begin
cnt1 <=32'd0;
div_clk_1s <= 1'b0;
cnt3 <=32'd0;
twinkle <= 1'b0;
end
else
begin
if( cnt3 == 32'd12500000)
begin
twinkle <= ~twinkle;
cnt3 <= 32'd0;
end
else
cnt3 <= cnt3 + 32'd1;
if(cnt1 == 32'd25000000)
begin
cnt1 <= 32'd0;
div_clk_1s <= ~div_clk_1s;
end
else
begin
cnt1 <= cnt1 + 32'd1;
end
end
end
always @(negedge reset or posedge div_clk_1s)
begin
if(!reset)
begin
tmp1 = 0;
tmp2 = 0;
tmp3 = 0;
tmp4 = 0;
tmp5 = 0;
tmp6 = 0;
end
else
begin
if(stop == 1 && gameover != 1 && win != 1)
begin
tmp1 = tmp1+1;
if(tmp1 == 10)
begin
tmp1 = 0;
tmp2 = tmp2+1;
end
if(tmp2 == 6)
begin
tmp2 = 0;
tmp3 = tmp3+1;
end
if(tmp3 == 10)
begin
tmp3 = 0;
tmp4 = tmp4+1;
end
if(tmp4 == 6)
begin
tmp4 = 0;
tmp5 = tmp5+1;
end
if(tmp5 == 10)
begin
tmp5 = 0;
tmp6 = tmp6+1;
end
end
else
begin
tmp1 = tmp1;
end
end
end
Seven s1(.sin(tmp1), .sout(hex1));
Seven s2(.sin(tmp2), .sout(hex2));
Seven s3(.sin(tmp3), .sout(hex3));
Seven s4(.sin(tmp4), .sout(hex4));
Seven s5(.sin(tmp5), .sout(hex5));
Seven s6(.sin(tmp6), .sout(hex6));
move(.clk(clock), .rst(reset), .button(button[0]), .LED(isMove[0]));
move(.clk(clock), .rst(reset), .button(button[1]), .LED(isMove[1]));
move(.clk(clock), .rst(reset), .button(button[2]), .LED(isMove[2]));
move(.clk(clock), .rst(reset), .button(button[3]), .LED(isMove[3]));
always@(posedge isMove[0] or posedge isMove[1] or posedge isMove[2] or posedge isMove[3])
begin
case(State)
S0:
begin
if(isMove[0] == 1)
NextState = S1;
else if(isMove[2] == 1)
NextState = S4;
else
NextState = S0;
end
S1:
begin
if(isMove[0] == 1)
NextState = S2;
else if(isMove[2] == 1)
NextState = S5;
else if(isMove[1] == 1)
NextState = S0;
else
NextState = S1;
end
S2:
begin
if(isMove[0] == 1)
NextState = S3;
else if(isMove[2] == 1)
NextState = S6;
else if(isMove[1] == 1)
NextState = S1;
else
NextState = S2;
end
S3:
begin
if(isMove[2] == 1)
NextState = S7;
else if(isMove[1] == 1)
NextState = S2;
else
NextState = S3;
end
S4:
begin
if(isMove[0] == 1)
NextState = S5;
else if(isMove[3] == 1)
NextState = S0;
else
NextState = S4;
end
S5:
begin
if(isMove[0] == 1)
NextState = S6;
else if(isMove[3] == 1)
NextState = S1;
else if(isMove[1] == 1)
NextState = S4;
else
NextState = S5;
end
S6:
begin
if(isMove[0] == 1)
NextState = S7;
else if(isMove[3] == 1)
NextState = S2;
else if(isMove[1] == 1)
NextState = S5;
else
NextState = S6;
end
S7:
begin
if(isMove[1] == 1)
NextState = S6;
else if(isMove[3] == 1)
NextState = S3;
else
NextState = S7;
end
default:
NextState = S0;
endcase
end
always@(State)
begin
case(State)
S7:led = 8'b00000001;
S6:led = 8'b00000010;
S5:led = 8'b00000100;
S4:led = 8'b00001000;
S3:led = 8'b00010000;
S2:led = 8'b00100000;
S1:led = 8'b01000000;
S0:led = 8'b10000000;
default:led = 8'b11111111;
endcase
end
always@(negedge reset or posedge clock)
begin
if(!reset)
begin
counths <= 11'd0;
countvs <= 10'd0;
end
else
begin
counths <= (counths == 11'd1600) ? 11'd0 : counths + 16'd1;
countvs <= (countvs == 10'd525) ? 10'd0 : (counths == 11'd1600) ? countvs + 10'd1 : countvs;
end
end
always@(negedge reset or posedge clock)
begin
if(!reset)
begin
vga_hs <= 1'b0;
vga_vs <= 1'b0;
valid <= 1'b0;
end
else
begin
vga_hs <= (counths < 11'd192 || counths > 11'd1568) ? 1'b0 : 1'b1;
vga_vs <= (countvs < 10'd2 || countvs > 10'd515) ? 1'b0 : 1'b1;
valid <= (countvs > 10'd35 && countvs < 10'd516 && counths > 11'd288 && counths < 11'd1568) ? 1'b1 : 1'b0;
end
end
always@(negedge reset or posedge clock)
begin
if(!reset)
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
else
begin
if(valid)
begin
if(typeGameover == 1)
begin
if((countvs - counths + 683 + 928 > 928) && (countvs - counths + 623 + 928 < 928) || (countvs + counths - 1173 + 928 > 928) && (countvs + counths - 1233 + 928 < 928))
begin
vga_r <= 4'd15;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else if(type == 1)
begin
if(8*(countvs-35-240)*(countvs-275) + 3*(counths-288-640)*(counths-288-640) < 432900 && 8*(countvs-35-240)*(countvs-275) + 3*(counths-288-640)*(counths-288-640) > 156300)
begin
vga_r <= 4'd0;
vga_g <= 4'd15;
vga_b <= 4'd0;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else if(type == 3)
begin
if(8*17*(countvs-275)*(countvs-275)-5*16*(countvs-275)*(counths<928? (counths-928) :928-counths)+3*17*(counths-928)*(counths-928) < 1000000)
begin
vga_r <= 4'd15;
vga_g <= 4'd8;
vga_b <= 4'd11;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else if(type == 4)
begin
if(8*17*(countvs-275)*(countvs-275)-5*16*(countvs-275)*(counths<928? (counths-928) :928-counths)+3*17*(counths-928)*(counths-928) < 1000000)
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
else
begin
vga_r <= 4'd15;
vga_g <= 4'd15;
vga_b <= 4'd15;
end
end
else if(type == 5)
begin
if((counths < 668 || counths > 1188 || countvs < 95 || countvs > 455) && counths > 578 && counths < 1278)
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd15;
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
else
begin
vga_r <= 4'd0;
vga_g <= 4'd0;
vga_b <= 4'd0;
end
end
end
endmodule | 0 |
137,259 | data/full_repos/permissive/77662186/bomb.v | 77,662,186 | bomb.v | v | 1,015 | 252 | [] | [] | [] | null | line:799 column:5: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/77662186/bomb.v:35: syntax error, unexpected type, expecting IDENTIFIER or '=' or do or final\nreg [2:0]type;\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:111: syntax error, unexpected '(', expecting IDENTIFIER\nkey(.clk(clock), .rst(reset), .Data(index), .keypadRow(keypadR), .keypadCol(keypadC), .KEY(K));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:131: syntax error, unexpected <=, expecting '('\n type <= 0;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:157: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:164: syntax error, unexpected <=, expecting '('\n type <= 4;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:173: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:181: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:188: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:194: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:201: syntax error, unexpected <=, expecting '('\n type <= 5;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:544: syntax error, unexpected '(', expecting IDENTIFIER\nmove(.clk(clock), .rst(reset), .button(button[0]), .LED(isMove[0]));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:713: syntax error, unexpected ==, expecting '('\n else if(type == 1)\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:728: syntax error, unexpected else\n else if(type == 3)\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:736: syntax error, unexpected else\n else\n ^~~~\n%Error: Exiting due to 14 error(s)\n" | 295,748 | module | module Seven(sin, sout);
input [3:0]sin;
output [6:0]sout;
reg [6:0]sout;
always@(sin)
begin
case(sin)
4'b 0000:sout=7'b 1000000;
4'b 0001:sout=7'b 1111001;
4'b 0010:sout=7'b 0100100;
4'b 0011:sout=7'b 0110000;
4'b 0100:sout=7'b 0011001;
4'b 0101:sout=7'b 0010010;
4'b 0110:sout=7'b 0000010;
4'b 0111:sout=7'b 1111000;
4'b 1000:sout=7'b 0000000;
4'b 1001:sout=7'b 0010000;
4'b 1010:sout=7'b 0001000;
4'b 1011:sout=7'b 0000011;
4'b 1100:sout=7'b 1000110;
4'b 1101:sout=7'b 0100001;
4'b 1110:sout=7'b 0000110;
4'b 1111:sout=7'b 0001110;
endcase
end
endmodule | module Seven(sin, sout); |
input [3:0]sin;
output [6:0]sout;
reg [6:0]sout;
always@(sin)
begin
case(sin)
4'b 0000:sout=7'b 1000000;
4'b 0001:sout=7'b 1111001;
4'b 0010:sout=7'b 0100100;
4'b 0011:sout=7'b 0110000;
4'b 0100:sout=7'b 0011001;
4'b 0101:sout=7'b 0010010;
4'b 0110:sout=7'b 0000010;
4'b 0111:sout=7'b 1111000;
4'b 1000:sout=7'b 0000000;
4'b 1001:sout=7'b 0010000;
4'b 1010:sout=7'b 0001000;
4'b 1011:sout=7'b 0000011;
4'b 1100:sout=7'b 1000110;
4'b 1101:sout=7'b 0100001;
4'b 1110:sout=7'b 0000110;
4'b 1111:sout=7'b 0001110;
endcase
end
endmodule | 0 |
137,260 | data/full_repos/permissive/77662186/bomb.v | 77,662,186 | bomb.v | v | 1,015 | 252 | [] | [] | [] | null | line:799 column:5: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/77662186/bomb.v:35: syntax error, unexpected type, expecting IDENTIFIER or '=' or do or final\nreg [2:0]type;\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:111: syntax error, unexpected '(', expecting IDENTIFIER\nkey(.clk(clock), .rst(reset), .Data(index), .keypadRow(keypadR), .keypadCol(keypadC), .KEY(K));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:131: syntax error, unexpected <=, expecting '('\n type <= 0;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:157: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:164: syntax error, unexpected <=, expecting '('\n type <= 4;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:173: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:181: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:188: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:194: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:201: syntax error, unexpected <=, expecting '('\n type <= 5;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:544: syntax error, unexpected '(', expecting IDENTIFIER\nmove(.clk(clock), .rst(reset), .button(button[0]), .LED(isMove[0]));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:713: syntax error, unexpected ==, expecting '('\n else if(type == 1)\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:728: syntax error, unexpected else\n else if(type == 3)\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:736: syntax error, unexpected else\n else\n ^~~~\n%Error: Exiting due to 14 error(s)\n" | 295,748 | module | module move(clk, rst, button, LED);
input clk, rst, button;
output LED;
reg flagButton;
reg LED;
reg [24:0]delayButton;
always@(posedge clk)
begin
if(!rst)
begin
LED = 1'b0;
flagButton = 1'b0;
delayButton = 25'd0;
end
else
begin
if((!button)&&(!flagButton)) flagButton = 1'b1;
else if(flagButton)
begin
delayButton = delayButton + 1'b1;
if(delayButton == 25'b1000000000000000000000000)
begin
flagButton = 1'b0;
delayButton = 25'd0;
LED = 1'b1;
end
end
else LED = 1'b0;
end
end
endmodule | module move(clk, rst, button, LED); |
input clk, rst, button;
output LED;
reg flagButton;
reg LED;
reg [24:0]delayButton;
always@(posedge clk)
begin
if(!rst)
begin
LED = 1'b0;
flagButton = 1'b0;
delayButton = 25'd0;
end
else
begin
if((!button)&&(!flagButton)) flagButton = 1'b1;
else if(flagButton)
begin
delayButton = delayButton + 1'b1;
if(delayButton == 25'b1000000000000000000000000)
begin
flagButton = 1'b0;
delayButton = 25'd0;
LED = 1'b1;
end
end
else LED = 1'b0;
end
end
endmodule | 0 |
137,261 | data/full_repos/permissive/77662186/bomb.v | 77,662,186 | bomb.v | v | 1,015 | 252 | [] | [] | [] | null | line:799 column:5: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/77662186/bomb.v:35: syntax error, unexpected type, expecting IDENTIFIER or '=' or do or final\nreg [2:0]type;\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:111: syntax error, unexpected '(', expecting IDENTIFIER\nkey(.clk(clock), .rst(reset), .Data(index), .keypadRow(keypadR), .keypadCol(keypadC), .KEY(K));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:131: syntax error, unexpected <=, expecting '('\n type <= 0;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:157: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:164: syntax error, unexpected <=, expecting '('\n type <= 4;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:173: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:181: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:188: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:194: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:201: syntax error, unexpected <=, expecting '('\n type <= 5;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:544: syntax error, unexpected '(', expecting IDENTIFIER\nmove(.clk(clock), .rst(reset), .button(button[0]), .LED(isMove[0]));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:713: syntax error, unexpected ==, expecting '('\n else if(type == 1)\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:728: syntax error, unexpected else\n else if(type == 3)\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:736: syntax error, unexpected else\n else\n ^~~~\n%Error: Exiting due to 14 error(s)\n" | 295,748 | module | module key(clk, rst, Data, keypadRow, keypadCol, KEY);
input clk, rst;
input [3:0]keypadCol;
output [3:0]keypadRow;
output [3:0]Data;
output KEY;
reg KEY;
reg [3:0]keypadRow;
reg [3:0]keypadBuf;
reg [24:0]keypadDelay;
SevenSegment seven(.in(keypadBuf), .out(Data));
always@(posedge clk)
begin
if(!rst)
begin
keypadRow = 4'b1110;
keypadBuf = 4'b0000;
keypadDelay = 25'd0;
KEY = 0;
end
else
begin
if(keypadDelay == `TimeExpire_KEY)
begin
keypadDelay = 25'd0;
case({keypadRow, keypadCol})
8'b1110_1110 :
begin
keypadBuf = 4'h7;
KEY = 1;
end
8'b1110_1101 :
begin
keypadBuf = 4'h4;
KEY = 1;
end
8'b1110_1011 :
begin
keypadBuf = 4'h1;
KEY = 1;
end
8'b1110_0111 :
begin
keypadBuf = 4'h0;
KEY = 1;
end
8'b1101_1110 :
begin
keypadBuf = 4'h9;
KEY = 1;
end
8'b1101_1101 :
begin
keypadBuf = 4'h6;
KEY = 1;
end
8'b1101_1011 :
begin
keypadBuf = 4'h3;
KEY = 1;
end
8'b1101_0111 :
begin
keypadBuf = 4'hb;
KEY = 1;
end
8'b1011_1110 :
begin
keypadBuf = 4'h8;
KEY = 1;
end
8'b1011_1101 :
begin
keypadBuf = 4'h5;
KEY = 1;
end
8'b1011_1011 :
begin
keypadBuf = 4'h2;
KEY = 1;
end
8'b1011_0111 :
begin
keypadBuf = 4'ha;
KEY = 1;
end
8'b0111_1110 :
begin
keypadBuf = 4'hc;
KEY = 1;
end
8'b0111_1101 :
begin
keypadBuf = 4'hd;
KEY = 1;
end
8'b0111_1011 :
begin
keypadBuf = 4'he;
KEY = 1;
end
8'b0111_0111 :
begin
keypadBuf = 4'hf;
KEY = 1;
end
default :
begin
keypadBuf = keypadBuf;
KEY = 0;
end
endcase
case(keypadRow)
4'b1110 : keypadRow = 4'b1101;
4'b1101 : keypadRow = 4'b1011;
4'b1011 : keypadRow = 4'b0111;
4'b0111 : keypadRow = 4'b1110;
default: keypadRow = 4'b1110;
endcase
end
else
begin
KEY = 0;
keypadDelay = keypadDelay + 1'b1;
end
end
end
endmodule | module key(clk, rst, Data, keypadRow, keypadCol, KEY); |
input clk, rst;
input [3:0]keypadCol;
output [3:0]keypadRow;
output [3:0]Data;
output KEY;
reg KEY;
reg [3:0]keypadRow;
reg [3:0]keypadBuf;
reg [24:0]keypadDelay;
SevenSegment seven(.in(keypadBuf), .out(Data));
always@(posedge clk)
begin
if(!rst)
begin
keypadRow = 4'b1110;
keypadBuf = 4'b0000;
keypadDelay = 25'd0;
KEY = 0;
end
else
begin
if(keypadDelay == `TimeExpire_KEY)
begin
keypadDelay = 25'd0;
case({keypadRow, keypadCol})
8'b1110_1110 :
begin
keypadBuf = 4'h7;
KEY = 1;
end
8'b1110_1101 :
begin
keypadBuf = 4'h4;
KEY = 1;
end
8'b1110_1011 :
begin
keypadBuf = 4'h1;
KEY = 1;
end
8'b1110_0111 :
begin
keypadBuf = 4'h0;
KEY = 1;
end
8'b1101_1110 :
begin
keypadBuf = 4'h9;
KEY = 1;
end
8'b1101_1101 :
begin
keypadBuf = 4'h6;
KEY = 1;
end
8'b1101_1011 :
begin
keypadBuf = 4'h3;
KEY = 1;
end
8'b1101_0111 :
begin
keypadBuf = 4'hb;
KEY = 1;
end
8'b1011_1110 :
begin
keypadBuf = 4'h8;
KEY = 1;
end
8'b1011_1101 :
begin
keypadBuf = 4'h5;
KEY = 1;
end
8'b1011_1011 :
begin
keypadBuf = 4'h2;
KEY = 1;
end
8'b1011_0111 :
begin
keypadBuf = 4'ha;
KEY = 1;
end
8'b0111_1110 :
begin
keypadBuf = 4'hc;
KEY = 1;
end
8'b0111_1101 :
begin
keypadBuf = 4'hd;
KEY = 1;
end
8'b0111_1011 :
begin
keypadBuf = 4'he;
KEY = 1;
end
8'b0111_0111 :
begin
keypadBuf = 4'hf;
KEY = 1;
end
default :
begin
keypadBuf = keypadBuf;
KEY = 0;
end
endcase
case(keypadRow)
4'b1110 : keypadRow = 4'b1101;
4'b1101 : keypadRow = 4'b1011;
4'b1011 : keypadRow = 4'b0111;
4'b0111 : keypadRow = 4'b1110;
default: keypadRow = 4'b1110;
endcase
end
else
begin
KEY = 0;
keypadDelay = keypadDelay + 1'b1;
end
end
end
endmodule | 0 |
137,262 | data/full_repos/permissive/77662186/bomb.v | 77,662,186 | bomb.v | v | 1,015 | 252 | [] | [] | [] | null | line:799 column:5: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/77662186/bomb.v:35: syntax error, unexpected type, expecting IDENTIFIER or '=' or do or final\nreg [2:0]type;\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:111: syntax error, unexpected '(', expecting IDENTIFIER\nkey(.clk(clock), .rst(reset), .Data(index), .keypadRow(keypadR), .keypadCol(keypadC), .KEY(K));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:131: syntax error, unexpected <=, expecting '('\n type <= 0;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:157: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:164: syntax error, unexpected <=, expecting '('\n type <= 4;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:173: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:181: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:188: syntax error, unexpected <=, expecting '('\n type <= 3;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:194: syntax error, unexpected <=, expecting '('\n type <= 1;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:201: syntax error, unexpected <=, expecting '('\n type <= 5;\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:544: syntax error, unexpected '(', expecting IDENTIFIER\nmove(.clk(clock), .rst(reset), .button(button[0]), .LED(isMove[0]));\n ^\n%Error: data/full_repos/permissive/77662186/bomb.v:713: syntax error, unexpected ==, expecting '('\n else if(type == 1)\n ^~\n%Error: data/full_repos/permissive/77662186/bomb.v:728: syntax error, unexpected else\n else if(type == 3)\n ^~~~\n%Error: data/full_repos/permissive/77662186/bomb.v:736: syntax error, unexpected else\n else\n ^~~~\n%Error: Exiting due to 14 error(s)\n" | 295,748 | module | module SevenSegment(in,out);
input [3:0]in;
output [3:0]out;
reg [3:0]out;
always@(*)
begin
case(in)
4'h0: out = 12;
4'h1: out = 13;
4'h2: out = 9;
4'h3: out = 5;
4'h4: out = 14;
4'h5: out = 10;
4'h6: out = 6;
4'h7: out = 15;
4'h8: out = 11;
4'h9: out = 7;
4'ha: out = 8;
4'hb: out = 4;
4'hc: out = 3;
4'hd: out = 2;
4'he: out = 1;
4'hf: out = 0;
endcase
end
endmodule | module SevenSegment(in,out); |
input [3:0]in;
output [3:0]out;
reg [3:0]out;
always@(*)
begin
case(in)
4'h0: out = 12;
4'h1: out = 13;
4'h2: out = 9;
4'h3: out = 5;
4'h4: out = 14;
4'h5: out = 10;
4'h6: out = 6;
4'h7: out = 15;
4'h8: out = 11;
4'h9: out = 7;
4'ha: out = 8;
4'hb: out = 4;
4'hc: out = 3;
4'hd: out = 2;
4'he: out = 1;
4'hf: out = 0;
endcase
end
endmodule | 0 |
137,264 | data/full_repos/permissive/77681453/n64.v | 77,681,453 | n64.v | v | 35 | 47 | [] | [] | [] | [(1, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/77681453/n64.v:21: Cannot find file containing module: 'divM'\ndivM #(.M(3)) div3 (\n^~~~\n ... Looked in:\n data/full_repos/permissive/77681453,data/full_repos/permissive/77681453/divM\n data/full_repos/permissive/77681453,data/full_repos/permissive/77681453/divM.v\n data/full_repos/permissive/77681453,data/full_repos/permissive/77681453/divM.sv\n divM\n divM.v\n divM.sv\n obj_dir/divM\n obj_dir/divM.v\n obj_dir/divM.sv\n%Error: data/full_repos/permissive/77681453/n64.v:27: Cannot find file containing module: 'n64_readcmd'\nn64_readcmd n64 (\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 295,751 | module | module n64_top(
input wire clk,
inout data,
output led_middle,
output led_up,
output led_down,
output led_left,
output led_right);
wire [31:0] ctrl_state;
wire ctrl_clk;
assign led_middle = ctrl_state[31];
assign led_up = ctrl_state[27];
assign led_down = ctrl_state[26];
assign led_left = ctrl_state[25];
assign led_right = ctrl_state[24];
wire clk_4M;
divM #(.M(3)) div3 (
.clk_in(clk),
.clk_out(clk_4M)
);
n64_readcmd n64 (
.clk_4M(clk_4M),
.data(data),
.ctrl_state(ctrl_state),
.ctrl_clk(ctrl_clk)
);
endmodule | module n64_top(
input wire clk,
inout data,
output led_middle,
output led_up,
output led_down,
output led_left,
output led_right); |
wire [31:0] ctrl_state;
wire ctrl_clk;
assign led_middle = ctrl_state[31];
assign led_up = ctrl_state[27];
assign led_down = ctrl_state[26];
assign led_left = ctrl_state[25];
assign led_right = ctrl_state[24];
wire clk_4M;
divM #(.M(3)) div3 (
.clk_in(clk),
.clk_out(clk_4M)
);
n64_readcmd n64 (
.clk_4M(clk_4M),
.data(data),
.ctrl_state(ctrl_state),
.ctrl_clk(ctrl_clk)
);
endmodule | 6 |
137,270 | data/full_repos/permissive/77681453/trigger_gen.v | 77,681,453 | trigger_gen.v | v | 29 | 75 | [] | [] | [] | [(7, 28)] | null | null | 1: b"%Error: data/full_repos/permissive/77681453/trigger_gen.v:11: Duplicate declaration of signal: 'trigger'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg trigger = 0;\n ^~~~~~~\n data/full_repos/permissive/77681453/trigger_gen.v:7: ... Location of original declaration\nmodule triggerM(input wire clk, output trigger);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 295,757 | module | module triggerM(input wire clk, output trigger);
parameter M = 512;
reg trigger = 0;
localparam N = $clog2(M);
reg [N-1:0] divcounter = M;
always @(posedge clk)
begin
divcounter <= divcounter - 1;
if (divcounter == 0)
trigger <= 1;
else
trigger <= 0;
end
endmodule | module triggerM(input wire clk, output trigger); |
parameter M = 512;
reg trigger = 0;
localparam N = $clog2(M);
reg [N-1:0] divcounter = M;
always @(posedge clk)
begin
divcounter <= divcounter - 1;
if (divcounter == 0)
trigger <= 1;
else
trigger <= 0;
end
endmodule | 6 |
137,271 | data/full_repos/permissive/77750427/display/top.v | 77,750,427 | top.v | v | 42 | 50 | [] | [] | [] | null | line:11: before: ")" | null | 1: b"%Error: data/full_repos/permissive/77750427/display/top.v:11: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/77750427/display/top.v:18: syntax error, unexpected assign\nassign ucSEL_ = PMOD0;\n^~~~~~\n%Error: data/full_repos/permissive/77750427/display/top.v:26: syntax error, unexpected assign\nassign spiin = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 295,759 | module | module main (
input clk,
input PMOD0,
input PMOD1,
output PMOD2,
input PMOD3,
output [6:0] digit1,
output [6:0] digit2,
);
wire ucSEL_;
wire ucSCLK;
wire ucMOSI;
wire ucMISO;
assign ucSEL_ = PMOD0;
assign ucMOSI = PMOD1;
assign PMOD2 = ucMISO;
assign ucSCLK = PMOD3;
wire [`N-1:0] spiin;
wire [`N-1:0] spiout;
assign spiin = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
SPISlave #(.WIDTH(`N)) spi (
.clk(clk),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(spiin),
.data_out(spiout)
);
assign digit1 = spiout[6:0];
assign digit2 = spiout[14:8];
endmodule | module main (
input clk,
input PMOD0,
input PMOD1,
output PMOD2,
input PMOD3,
output [6:0] digit1,
output [6:0] digit2,
); |
wire ucSEL_;
wire ucSCLK;
wire ucMOSI;
wire ucMISO;
assign ucSEL_ = PMOD0;
assign ucMOSI = PMOD1;
assign PMOD2 = ucMISO;
assign ucSCLK = PMOD3;
wire [`N-1:0] spiin;
wire [`N-1:0] spiout;
assign spiin = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
SPISlave #(.WIDTH(`N)) spi (
.clk(clk),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(spiin),
.data_out(spiout)
);
assign digit1 = spiout[6:0];
assign digit2 = spiout[14:8];
endmodule | 0 |
137,272 | data/full_repos/permissive/77750427/leds/top.v | 77,750,427 | top.v | v | 41 | 33 | [] | [] | [] | [(3, 40)] | null | null | 1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/77750427/leds/top.v:26: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance main\nassign spiin = {0,0,0,0,switch};\n ^\n ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/77750427/leds/top.v:26: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance main\nassign spiin = {0,0,0,0,switch};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/77750427/leds/top.v:26: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance main\nassign spiin = {0,0,0,0,switch};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/77750427/leds/top.v:26: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance main\nassign spiin = {0,0,0,0,switch};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/77750427/leds/top.v:26: Unsized numbers/parameters not allowed in replications.\n : ... In instance main\nassign spiin = {0,0,0,0,switch};\n ^\n%Error: data/full_repos/permissive/77750427/leds/top.v:28: Cannot find file containing module: \'SPISlave\'\nSPISlave #(.WIDTH(8)) spi (\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77750427/leds,data/full_repos/permissive/77750427/SPISlave\n data/full_repos/permissive/77750427/leds,data/full_repos/permissive/77750427/SPISlave.v\n data/full_repos/permissive/77750427/leds,data/full_repos/permissive/77750427/SPISlave.sv\n SPISlave\n SPISlave.v\n SPISlave.sv\n obj_dir/SPISlave\n obj_dir/SPISlave.v\n obj_dir/SPISlave.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 295,761 | module | module main (
input clk,
input PMOD0,
input PMOD1,
output PMOD2,
input PMOD3,
input [3:0] switch,
output [3:0] led
);
wire ucSEL_;
wire ucSCLK;
wire ucMOSI;
wire ucMISO;
assign ucSEL_ = PMOD0;
assign ucMOSI = PMOD1;
assign PMOD2 = ucMISO;
assign ucSCLK = PMOD3;
wire [`N-1:0] spiin;
wire [`N-1:0] spiout;
assign spiin = {0,0,0,0,switch};
SPISlave #(.WIDTH(`N)) spi (
.clk(clk),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(spiin),
.data_out(spiout)
);
assign led = spiout[3:0];
endmodule | module main (
input clk,
input PMOD0,
input PMOD1,
output PMOD2,
input PMOD3,
input [3:0] switch,
output [3:0] led
); |
wire ucSEL_;
wire ucSCLK;
wire ucMOSI;
wire ucMISO;
assign ucSEL_ = PMOD0;
assign ucMOSI = PMOD1;
assign PMOD2 = ucMISO;
assign ucSCLK = PMOD3;
wire [`N-1:0] spiin;
wire [`N-1:0] spiout;
assign spiin = {0,0,0,0,switch};
SPISlave #(.WIDTH(`N)) spi (
.clk(clk),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(spiin),
.data_out(spiout)
);
assign led = spiout[3:0];
endmodule | 0 |
137,273 | data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_Chroma_Resampler.v | 77,756,631 | top_level_Chroma_Resampler.v | v | 249 | 81 | [] | [] | [] | [(48, 247)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_Chroma_Resampler.v:239: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'empty\' generates 1 bits.\n : ... In instance top_level_Chroma_Resampler\nassign converted_empty = empty;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 295,818 | module | module top_level_Chroma_Resampler (
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
parameter IDW = 15;
parameter ODW = 23;
parameter IEW = 0;
parameter OEW = 1;
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
reg [ 7: 0] saved_CrCb;
reg cur_is_Cr_or_Cb;
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
saved_CrCb <= 8'h00;
else if (stream_in_ready & stream_in_startofpacket)
saved_CrCb <= 8'h00;
else if (transfer_data & valid)
saved_CrCb <= data[15: 8];
end
always @(posedge clk)
begin
if (reset)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready & stream_in_startofpacket)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready)
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb ^ 1'b1;
end
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = (cur_is_Cr_or_Cb) ? data[15: 8] : saved_CrCb;
assign converted_data[15: 8] = (cur_is_Cr_or_Cb) ? saved_CrCb : data[15: 8];
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
endmodule | module top_level_Chroma_Resampler (
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
); |
parameter IDW = 15;
parameter ODW = 23;
parameter IEW = 0;
parameter OEW = 1;
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
reg [ 7: 0] saved_CrCb;
reg cur_is_Cr_or_Cb;
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
saved_CrCb <= 8'h00;
else if (stream_in_ready & stream_in_startofpacket)
saved_CrCb <= 8'h00;
else if (transfer_data & valid)
saved_CrCb <= data[15: 8];
end
always @(posedge clk)
begin
if (reset)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready & stream_in_startofpacket)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready)
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb ^ 1'b1;
end
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = (cur_is_Cr_or_Cb) ? data[15: 8] : saved_CrCb;
assign converted_data[15: 8] = (cur_is_Cr_or_Cb) ? saved_CrCb : data[15: 8];
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
endmodule | 1 |
137,274 | data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_clocks.v | 77,756,631 | top_level_clocks.v | v | 233 | 81 | [] | [] | [] | null | line:165: before: "." | null | 1: b"%Error: data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_clocks.v:132: Cannot find file containing module: 'altpll'\naltpll DE_Clock_Generator_System (\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altpll\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altpll.v\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altpll.sv\n altpll\n altpll.v\n altpll.sv\n obj_dir/altpll\n obj_dir/altpll.v\n obj_dir/altpll.sv\n%Error: Exiting due to 1 error(s)\n" | 295,819 | module | module top_level_clocks (
CLOCK_50,
reset,
SDRAM_CLK,
VGA_CLK,
sys_clk,
sys_reset_n
);
input CLOCK_50;
input reset;
output SDRAM_CLK;
output VGA_CLK;
output sys_clk;
output sys_reset_n;
localparam SYS_CLK_MULT = 1;
localparam SYS_CLK_DIV = 1;
wire [ 2: 0] sys_mem_clks;
wire clk_locked;
wire video_in_clk;
assign sys_reset_n = clk_locked;
assign sys_clk = sys_mem_clks[0];
assign SDRAM_CLK = sys_mem_clks[1];
assign VGA_CLK = sys_mem_clks[2];
altpll DE_Clock_Generator_System (
.inclk ({1'b0, CLOCK_50}),
.clk (sys_mem_clks),
.locked (clk_locked),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone II",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
endmodule | module top_level_clocks (
CLOCK_50,
reset,
SDRAM_CLK,
VGA_CLK,
sys_clk,
sys_reset_n
); |
input CLOCK_50;
input reset;
output SDRAM_CLK;
output VGA_CLK;
output sys_clk;
output sys_reset_n;
localparam SYS_CLK_MULT = 1;
localparam SYS_CLK_DIV = 1;
wire [ 2: 0] sys_mem_clks;
wire clk_locked;
wire video_in_clk;
assign sys_reset_n = clk_locked;
assign sys_clk = sys_mem_clks[0];
assign SDRAM_CLK = sys_mem_clks[1];
assign VGA_CLK = sys_mem_clks[2];
altpll DE_Clock_Generator_System (
.inclk ({1'b0, CLOCK_50}),
.clk (sys_mem_clks),
.locked (clk_locked),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone II",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
endmodule | 1 |
137,275 | data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_RGB_Resampler.v | 77,756,631 | top_level_RGB_Resampler.v | v | 193 | 81 | [] | [] | [] | [(47, 191)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_RGB_Resampler.v:161: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'stream_in_empty\' generates 2 bits.\n : ... In instance top_level_RGB_Resampler\n stream_out_empty <= stream_in_empty;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 295,853 | module | module top_level_RGB_Resampler (
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
parameter IDW = 23;
parameter ODW = 15;
parameter IEW = 1;
parameter OEW = 0;
parameter ALPHA = 10'h3FF;
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = ALPHA;
assign converted_data[15:11] = r[ 9: 5];
assign converted_data[10: 5] = g[ 9: 4];
assign converted_data[ 4: 0] = b[ 9: 5];
endmodule | module top_level_RGB_Resampler (
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
); |
parameter IDW = 23;
parameter ODW = 15;
parameter IEW = 1;
parameter OEW = 0;
parameter ALPHA = 10'h3FF;
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = ALPHA;
assign converted_data[15:11] = r[ 9: 5];
assign converted_data[10: 5] = g[ 9: 4];
assign converted_data[ 4: 0] = b[ 9: 5];
endmodule | 1 |
137,276 | data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_Video_Clipper.v | 77,756,631 | top_level_Video_Clipper.v | v | 261 | 81 | [] | [] | [] | null | line:204: before: "." | null | 1: b"%Error: data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_Video_Clipper.v:178: Cannot find file containing module: 'altera_up_video_clipper_drop'\naltera_up_video_clipper_drop Clipper_Drop (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altera_up_video_clipper_drop\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altera_up_video_clipper_drop.v\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altera_up_video_clipper_drop.sv\n altera_up_video_clipper_drop\n altera_up_video_clipper_drop.v\n altera_up_video_clipper_drop.sv\n obj_dir/altera_up_video_clipper_drop\n obj_dir/altera_up_video_clipper_drop.v\n obj_dir/altera_up_video_clipper_drop.sv\n%Error: data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_Video_Clipper.v:219: Cannot find file containing module: 'altera_up_video_clipper_add'\naltera_up_video_clipper_add Clipper_Add (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 295,866 | module | module top_level_Video_Clipper (
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
parameter DW = 15;
parameter EW = 0;
parameter WIDTH_IN = 720;
parameter HEIGHT_IN = 244;
parameter WW_IN = 9;
parameter HW_IN = 7;
parameter DROP_PIXELS_AT_START = 40;
parameter DROP_PIXELS_AT_END = 40;
parameter DROP_LINES_AT_START = 2;
parameter DROP_LINES_AT_END = 2;
parameter WIDTH_OUT = 640;
parameter HEIGHT_OUT = 240;
parameter WW_OUT = 9;
parameter HW_OUT = 7;
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 16'd0;
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire [EW: 0] internal_empty;
wire internal_valid;
wire internal_ready;
altera_up_video_clipper_drop Clipper_Drop (
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_empty (stream_in_empty),
.stream_in_valid (stream_in_valid),
.stream_out_ready (internal_ready),
.stream_in_ready (stream_in_ready),
.stream_out_data (internal_data),
.stream_out_startofpacket (internal_startofpacket),
.stream_out_endofpacket (internal_endofpacket),
.stream_out_empty (internal_empty),
.stream_out_valid (internal_valid)
);
defparam
Clipper_Drop.DW = DW,
Clipper_Drop.EW = EW,
Clipper_Drop.IMAGE_WIDTH = WIDTH_IN,
Clipper_Drop.IMAGE_HEIGHT = HEIGHT_IN,
Clipper_Drop.WW = WW_IN,
Clipper_Drop.HW = HW_IN,
Clipper_Drop.DROP_PIXELS_AT_START = DROP_PIXELS_AT_START,
Clipper_Drop.DROP_PIXELS_AT_END = DROP_PIXELS_AT_END,
Clipper_Drop.DROP_LINES_AT_START = DROP_LINES_AT_START,
Clipper_Drop.DROP_LINES_AT_END = DROP_LINES_AT_END,
Clipper_Drop.ADD_DATA = ADD_DATA;
altera_up_video_clipper_add Clipper_Add (
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (internal_endofpacket),
.stream_in_empty (internal_empty),
.stream_in_valid (internal_valid),
.stream_out_ready (stream_out_ready),
.stream_in_ready (internal_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_empty (stream_out_empty),
.stream_out_valid (stream_out_valid)
);
defparam
Clipper_Add.DW = DW,
Clipper_Add.EW = EW,
Clipper_Add.IMAGE_WIDTH = WIDTH_OUT,
Clipper_Add.IMAGE_HEIGHT = HEIGHT_OUT,
Clipper_Add.WW = WW_OUT,
Clipper_Add.HW = HW_OUT,
Clipper_Add.ADD_PIXELS_AT_START = ADD_PIXELS_AT_START,
Clipper_Add.ADD_PIXELS_AT_END = ADD_PIXELS_AT_END,
Clipper_Add.ADD_LINES_AT_START = ADD_LINES_AT_START,
Clipper_Add.ADD_LINES_AT_END = ADD_LINES_AT_END,
Clipper_Add.ADD_DATA = ADD_DATA;
endmodule | module top_level_Video_Clipper (
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
); |
parameter DW = 15;
parameter EW = 0;
parameter WIDTH_IN = 720;
parameter HEIGHT_IN = 244;
parameter WW_IN = 9;
parameter HW_IN = 7;
parameter DROP_PIXELS_AT_START = 40;
parameter DROP_PIXELS_AT_END = 40;
parameter DROP_LINES_AT_START = 2;
parameter DROP_LINES_AT_END = 2;
parameter WIDTH_OUT = 640;
parameter HEIGHT_OUT = 240;
parameter WW_OUT = 9;
parameter HW_OUT = 7;
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 16'd0;
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire [EW: 0] internal_empty;
wire internal_valid;
wire internal_ready;
altera_up_video_clipper_drop Clipper_Drop (
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_empty (stream_in_empty),
.stream_in_valid (stream_in_valid),
.stream_out_ready (internal_ready),
.stream_in_ready (stream_in_ready),
.stream_out_data (internal_data),
.stream_out_startofpacket (internal_startofpacket),
.stream_out_endofpacket (internal_endofpacket),
.stream_out_empty (internal_empty),
.stream_out_valid (internal_valid)
);
defparam
Clipper_Drop.DW = DW,
Clipper_Drop.EW = EW,
Clipper_Drop.IMAGE_WIDTH = WIDTH_IN,
Clipper_Drop.IMAGE_HEIGHT = HEIGHT_IN,
Clipper_Drop.WW = WW_IN,
Clipper_Drop.HW = HW_IN,
Clipper_Drop.DROP_PIXELS_AT_START = DROP_PIXELS_AT_START,
Clipper_Drop.DROP_PIXELS_AT_END = DROP_PIXELS_AT_END,
Clipper_Drop.DROP_LINES_AT_START = DROP_LINES_AT_START,
Clipper_Drop.DROP_LINES_AT_END = DROP_LINES_AT_END,
Clipper_Drop.ADD_DATA = ADD_DATA;
altera_up_video_clipper_add Clipper_Add (
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (internal_endofpacket),
.stream_in_empty (internal_empty),
.stream_in_valid (internal_valid),
.stream_out_ready (stream_out_ready),
.stream_in_ready (internal_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_empty (stream_out_empty),
.stream_out_valid (stream_out_valid)
);
defparam
Clipper_Add.DW = DW,
Clipper_Add.EW = EW,
Clipper_Add.IMAGE_WIDTH = WIDTH_OUT,
Clipper_Add.IMAGE_HEIGHT = HEIGHT_OUT,
Clipper_Add.WW = WW_OUT,
Clipper_Add.HW = HW_OUT,
Clipper_Add.ADD_PIXELS_AT_START = ADD_PIXELS_AT_START,
Clipper_Add.ADD_PIXELS_AT_END = ADD_PIXELS_AT_END,
Clipper_Add.ADD_LINES_AT_START = ADD_LINES_AT_START,
Clipper_Add.ADD_LINES_AT_END = ADD_LINES_AT_END,
Clipper_Add.ADD_DATA = ADD_DATA;
endmodule | 1 |
137,277 | data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_video_decoder_0.v | 77,756,631 | top_level_video_decoder_0.v | v | 236 | 81 | [] | [] | [] | null | line:232: before: "." | null | 1: b"%Error: data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_video_decoder_0.v:193: Cannot find file containing module: 'altera_up_video_itu_656_decoder'\naltera_up_video_itu_656_decoder ITU_R_656_Decoder (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altera_up_video_itu_656_decoder\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altera_up_video_itu_656_decoder.v\n data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules,data/full_repos/permissive/77756631/altera_up_video_itu_656_decoder.sv\n altera_up_video_itu_656_decoder\n altera_up_video_itu_656_decoder.v\n altera_up_video_itu_656_decoder.sv\n obj_dir/altera_up_video_itu_656_decoder\n obj_dir/altera_up_video_itu_656_decoder.v\n obj_dir/altera_up_video_itu_656_decoder.sv\n%Error: data/full_repos/permissive/77756631/DE2/top_level/synthesis/submodules/top_level_video_decoder_0.v:211: Cannot find file containing module: 'altera_up_video_dual_clock_fifo'\naltera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 295,867 | module | module top_level_video_decoder_0 (
clk,
reset,
TD_CLK27,
TD_DATA,
TD_HS,
TD_VS,
clk27_reset,
stream_out_ready,
TD_RESET,
overflow_flag,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
parameter IW = 7;
parameter OW = 15;
parameter FW = 17;
parameter PIXELS = 1280;
input clk;
input reset;
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
input TD_VS;
input clk27_reset;
input stream_out_ready;
output TD_RESET;
output reg overflow_flag;
output [OW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output stream_out_empty;
output stream_out_valid;
wire video_clk;
wire video_clk_reset;
wire [OW: 0] decoded_pixel;
wire decoded_startofpacket;
wire decoded_endofpacket;
wire decoded_valid;
wire [FW: 0] data_from_fifo;
wire [ 6: 0] fifo_used_words;
wire [ 6: 0] wrusedw;
wire wrfull;
wire rdempty;
reg reached_start_of_frame;
always @(posedge video_clk)
begin
if (video_clk_reset)
overflow_flag <= 1'b0;
else if (decoded_valid & reached_start_of_frame & wrfull)
overflow_flag <= 1'b1;
end
always @(posedge video_clk)
begin
if (video_clk_reset)
reached_start_of_frame <= 1'b0;
else if (decoded_valid & decoded_startofpacket)
reached_start_of_frame <= 1'b1;
end
assign TD_RESET = 1'b1;
assign stream_out_data = data_from_fifo[OW: 0];
assign stream_out_startofpacket = data_from_fifo[(FW - 1)];
assign stream_out_endofpacket = data_from_fifo[FW];
assign stream_out_empty = 1'b0;
assign stream_out_valid = ~rdempty;
assign video_clk = TD_CLK27;
assign video_clk_reset = clk27_reset;
altera_up_video_itu_656_decoder ITU_R_656_Decoder (
.clk (video_clk),
.reset (video_clk_reset),
.TD_DATA (TD_DATA),
.ready (decoded_valid & ~wrfull),
.data (decoded_pixel),
.startofpacket (decoded_startofpacket),
.endofpacket (decoded_endofpacket),
.valid (decoded_valid)
);
altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (
.wrclk (video_clk),
.wrreq (decoded_valid & reached_start_of_frame & ~wrfull),
.data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}),
.rdclk (clk),
.rdreq (stream_out_valid & stream_out_ready),
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (data_from_fifo),
.rdusedw (fifo_used_words),
.rdempty (rdempty)
);
defparam
Video_In_Dual_Clock_FIFO.DW = (FW + 1);
endmodule | module top_level_video_decoder_0 (
clk,
reset,
TD_CLK27,
TD_DATA,
TD_HS,
TD_VS,
clk27_reset,
stream_out_ready,
TD_RESET,
overflow_flag,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
); |
parameter IW = 7;
parameter OW = 15;
parameter FW = 17;
parameter PIXELS = 1280;
input clk;
input reset;
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
input TD_VS;
input clk27_reset;
input stream_out_ready;
output TD_RESET;
output reg overflow_flag;
output [OW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output stream_out_empty;
output stream_out_valid;
wire video_clk;
wire video_clk_reset;
wire [OW: 0] decoded_pixel;
wire decoded_startofpacket;
wire decoded_endofpacket;
wire decoded_valid;
wire [FW: 0] data_from_fifo;
wire [ 6: 0] fifo_used_words;
wire [ 6: 0] wrusedw;
wire wrfull;
wire rdempty;
reg reached_start_of_frame;
always @(posedge video_clk)
begin
if (video_clk_reset)
overflow_flag <= 1'b0;
else if (decoded_valid & reached_start_of_frame & wrfull)
overflow_flag <= 1'b1;
end
always @(posedge video_clk)
begin
if (video_clk_reset)
reached_start_of_frame <= 1'b0;
else if (decoded_valid & decoded_startofpacket)
reached_start_of_frame <= 1'b1;
end
assign TD_RESET = 1'b1;
assign stream_out_data = data_from_fifo[OW: 0];
assign stream_out_startofpacket = data_from_fifo[(FW - 1)];
assign stream_out_endofpacket = data_from_fifo[FW];
assign stream_out_empty = 1'b0;
assign stream_out_valid = ~rdempty;
assign video_clk = TD_CLK27;
assign video_clk_reset = clk27_reset;
altera_up_video_itu_656_decoder ITU_R_656_Decoder (
.clk (video_clk),
.reset (video_clk_reset),
.TD_DATA (TD_DATA),
.ready (decoded_valid & ~wrfull),
.data (decoded_pixel),
.startofpacket (decoded_startofpacket),
.endofpacket (decoded_endofpacket),
.valid (decoded_valid)
);
altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (
.wrclk (video_clk),
.wrreq (decoded_valid & reached_start_of_frame & ~wrfull),
.data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}),
.rdclk (clk),
.rdreq (stream_out_valid & stream_out_ready),
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (data_from_fifo),
.rdusedw (fifo_used_words),
.rdempty (rdempty)
);
defparam
Video_In_Dual_Clock_FIFO.DW = (FW + 1);
endmodule | 1 |
137,279 | data/full_repos/permissive/77767059/CPU.v | 77,767,059 | CPU.v | v | 467 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/CPU.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,870 | module | module CPU #(
parameter INSTR_MEM_SIZE = 1024,
parameter DATA_MEM_SIZE = 4096
) (
input wire clock,
input wire reset
);
wire [31:0] pc_next;
wire [31:0] pc;
ProgramCounter ProgramCounter_0 (
.clock(clock),
.reset(reset),
.Stall(Stall),
.pc_next(pc_next),
.pc(pc)
);
wire [31:0] pc_plus_four;
PCPlus4 PCPlus4_0 (
.pc(pc),
.pc_plus_four(pc_plus_four)
);
wire [31:0] instruction;
InstructionMemory #(
.SIZE(INSTR_MEM_SIZE)
) InstructionMemory_0 (
.Address(pc),
.Instruction(instruction)
);
wire [31:0] ID_pc_plus_four;
wire [31:0] ID_instruction;
IF_ID IF_ID_0 (
.clock(clock),
.WriteEnable(~Stall),
.Flush(0),
.pc_plus_four(pc_plus_four),
.ID_pc_plus_four(ID_pc_plus_four),
.instruction(instruction),
.ID_instruction(ID_instruction)
);
wire [5:0] opcode;
assign opcode = ID_instruction[31:26];
wire [4:0] rs;
assign rs = ID_instruction[25:21];
wire [4:0] rt;
assign rt = ID_instruction[20:16];
wire [4:0] rd;
assign rd = ID_instruction[15:11];
wire [5:0] funct;
assign funct = ID_instruction[5:0];
wire [15:0] immediate;
assign immediate = ID_instruction[15:0];
wire Stall;
HazardDetection HazardDetection_0 (
.EX_MemRead(EX_MemRead),
.rs(rs),
.rt(rt),
.EX_rt(EX_rt),
.Stall(Stall)
);
wire RegWrite;
wire RegDst;
wire MemRead;
wire MemWrite;
wire MemToReg;
wire Branch;
wire ALUSrc;
wire [1:0] ALUOp;
Control Control_0 (
.Opcode(opcode),
.RegWrite(RegWrite),
.RegDst(RegDst),
.MemRead(MemRead),
.MemWrite(MemWrite),
.MemToReg(MemToReg),
.Branch(Branch),
.ALUSrc(ALUSrc),
.ALUOp(ALUOp)
);
wire [8:0] BufferedControl;
mux2to1 #(
.WIDTH(9)
) MuxControlStall (
.inA( {RegWrite, RegDst, MemRead, MemWrite, MemToReg, Branch, ALUSrc,
ALUOp} ),
.inB(9'b0),
.select(Stall),
.out(BufferedControl)
);
wire [31:0] RegReadDataA;
wire [31:0] RegReadDataB;
wire [31:0] RegWriteData;
Registers Registers_0 (
.clock(clock),
.reset(reset),
.ReadAddressA(rs),
.ReadDataA(RegReadDataA),
.ReadAddressB(rt),
.ReadDataB(RegReadDataB),
.WriteEnable(WB_RegWrite),
.WriteAddress(WB_RegWriteAddress),
.WriteData(RegWriteData)
);
wire [31:0] extended;
SignExtender SignExtender_0 (
.immediate(immediate),
.extended(extended)
);
wire [31:0] EX_instruction;
wire [31:0] EX_pc_plus_four;
wire [31:0] EX_RegReadDataA;
wire [31:0] EX_RegReadDataB;
wire [31:0] EX_extended;
wire EX_RegWrite;
wire EX_RegDst;
wire EX_MemRead;
wire EX_MemWrite;
wire EX_MemToReg;
wire EX_Branch;
wire EX_ALUSrc;
wire [1:0] EX_ALUOp;
wire [4:0] EX_rs;
wire [4:0] EX_rt;
wire [4:0] EX_rd;
ID_EX ID_EX_0 (
.clock(clock),
.ID_instruction(ID_instruction),
.EX_instruction(EX_instruction),
.ID_pc_plus_four(ID_pc_plus_four),
.EX_pc_plus_four(EX_pc_plus_four),
.RegReadDataA(RegReadDataA),
.EX_RegReadDataA(EX_RegReadDataA),
.RegReadDataB(RegReadDataB),
.EX_RegReadDataB(EX_RegReadDataB),
.extended(extended),
.EX_extended(EX_extended),
.RegWrite(BufferedControl[8]),
.EX_RegWrite(EX_RegWrite),
.RegDst(BufferedControl[7]),
.EX_RegDst(EX_RegDst),
.MemRead(BufferedControl[6]),
.EX_MemRead(EX_MemRead),
.MemWrite(BufferedControl[5]),
.EX_MemWrite(EX_MemWrite),
.MemToReg(BufferedControl[4]),
.EX_MemToReg(EX_MemToReg),
.Branch(BufferedControl[3]),
.EX_Branch(EX_Branch),
.ALUSrc(BufferedControl[2]),
.EX_ALUSrc(EX_ALUSrc),
.ALUOp(BufferedControl[1:0]),
.EX_ALUOp(EX_ALUOp),
.rs(rs),
.EX_rs(EX_rs),
.rt(rt),
.EX_rt(EX_rt),
.rd(rd),
.EX_rd(EX_rd)
);
wire [1:0] ForwardA;
wire [31:0] ALUArgA;
mux4to1 #(
.WIDTH(32)
) MuxForwardA (
.inA(EX_RegReadDataA),
.inB(RegWriteData),
.inC(MEM_ALUResult),
.inD(32'b0),
.select(ForwardA),
.out(ALUArgA)
);
wire [1:0] ForwardB;
wire [31:0] ForwardBOut;
mux4to1 #(
.WIDTH(32)
) MuxForwardB (
.inA(EX_RegReadDataB),
.inB(RegWriteData),
.inC(MEM_ALUResult),
.inD(32'b0),
.select(ForwardB),
.out(ForwardBOut)
);
wire [31:0] ALUArgB;
mux2to1 #(
.WIDTH(32)
) MuxALUSrc (
.inA(ForwardBOut),
.inB(EX_extended),
.select(EX_ALUSrc),
.out(ALUArgB)
);
wire [31:0] ALUResult;
wire Zero;
ALU #(
.WIDTH(32)
) ALU_0 (
.op(ALUCtrl),
.inA(ALUArgA),
.inB(ALUArgB),
.out(ALUResult),
.zero(Zero)
);
wire [5:0] EX_funct;
assign EX_funct = EX_extended[5:0];
wire [3:0] ALUCtrl;
ALUControl ALUControl_0 (
.Funct(EX_funct),
.ALUOp(EX_ALUOp),
.ALUCtrl(ALUCtrl)
);
wire [4:0] RegWriteAddress;
mux2to1 #(
.WIDTH(5)
) MuxRegDst (
.inA(EX_rt),
.inB(EX_rd),
.select(EX_RegDst),
.out(RegWriteAddress)
);
wire [31:0] branch_address;
BranchAdder BranchAdder_0 (
.pc_plus_four(EX_pc_plus_four),
.extended_times_four(EX_extended << 2),
.branch_address(branch_address)
);
wire bneOne;
assign bneOne = ID_instruction[26];
wire [31:0] MEM_instruction;
wire [31:0] MEM_branch_address;
wire MEM_Zero;
wire [31:0] MEM_ALUResult;
wire [31:0] MEM_ForwardBOut;
wire [4:0] MEM_RegWriteAddress;
wire MEM_RegWrite;
wire MEM_MemRead;
wire MEM_MemWrite;
wire MEM_MemToReg;
wire MEM_Branch;
wire MEM_bneOne;
Forwarding Forwarding_0 (
.EX_rs(EX_rs),
.EX_rt(EX_rt),
.MEM_rd(MEM_rd),
.WB_rd(WB_rd),
.MEM_RegWrite(MEM_RegWrite),
.WB_RegWrite(WB_RegWrite),
.ForwardA(ForwardA),
.ForwardB(ForwardB)
);
EX_MEM EX_MEM_0 (
.clock(clock),
.EX_instruction(EX_instruction),
.MEM_instruction(MEM_instruction),
.branch_address(branch_address),
.MEM_branch_address(MEM_branch_address),
.Zero(Zero),
.MEM_Zero(MEM_Zero),
.ALUResult(ALUResult),
.MEM_ALUResult(MEM_ALUResult),
.ForwardBOut(ForwardBOut),
.MEM_ForwardBOut(MEM_ForwardBOut),
.RegWriteAddress(RegWriteAddress),
.MEM_RegWriteAddress(MEM_RegWriteAddress),
.EX_RegWrite(EX_RegWrite),
.MEM_RegWrite(MEM_RegWrite),
.EX_MemRead(EX_MemRead),
.MEM_MemRead(MEM_MemRead),
.EX_MemWrite(EX_MemWrite),
.MEM_MemWrite(MEM_MemWrite),
.EX_MemToReg(EX_MemToReg),
.MEM_MemToReg(MEM_MemToReg),
.EX_Branch(EX_Branch),
.MEM_Branch(MEM_Branch),
.bneOne(bneOne),
.MEM_bneOne(MEM_bneOne)
);
wire pc_chooser;
mux2to1 #(
.WIDTH(1)
) MuxBeqBne (
.inA(MEM_Zero),
.inB(~MEM_Zero),
.select(MEM_bneOne),
.out(pc_chooser)
);
mux2to1 #(
.WIDTH(32)
) MuxPCNext (
.inA(pc_plus_four),
.inB(MEM_branch_address),
.select(MEM_Branch && pc_chooser),
.out(pc_next)
);
wire [31:0] MemReadData;
Memory #(
.SIZE(DATA_MEM_SIZE)
) DataMemory_0 (
.clock(clock),
.Address(MEM_ALUResult),
.ReadEnable(MEM_MemRead),
.ReadData(MemReadData),
.WriteEnable(MEM_MemWrite),
.WriteData(MEM_ForwardBOut)
);
wire [4:0] MEM_rd;
assign MEM_rd = MEM_RegWriteAddress;
wire [31:0] WB_instruction;
wire [31:0] WB_MemReadData;
wire [31:0] WB_ALUResult;
wire [4:0] WB_RegWriteAddress;
wire WB_RegWrite;
wire WB_MemToReg;
MEM_WB MEM_WB_0 (
.clock(clock),
.MEM_instruction(MEM_instruction),
.WB_instruction(WB_instruction),
.MemReadData(MemReadData),
.WB_MemReadData(WB_MemReadData),
.MEM_ALUResult(MEM_ALUResult),
.WB_ALUResult(WB_ALUResult),
.MEM_RegWriteAddress(MEM_RegWriteAddress),
.WB_RegWriteAddress(WB_RegWriteAddress),
.MEM_RegWrite(MEM_RegWrite),
.WB_RegWrite(WB_RegWrite),
.MEM_MemToReg(MEM_MemToReg),
.WB_MemToReg(WB_MemToReg)
);
mux2to1 #(
.WIDTH(32)
) MuxMemtoReg (
.inA(WB_ALUResult),
.inB(WB_MemReadData),
.select(WB_MemToReg),
.out(RegWriteData)
);
wire [4:0] WB_rd;
assign WB_rd = WB_RegWriteAddress;
endmodule | module CPU #(
parameter INSTR_MEM_SIZE = 1024,
parameter DATA_MEM_SIZE = 4096
) (
input wire clock,
input wire reset
); |
wire [31:0] pc_next;
wire [31:0] pc;
ProgramCounter ProgramCounter_0 (
.clock(clock),
.reset(reset),
.Stall(Stall),
.pc_next(pc_next),
.pc(pc)
);
wire [31:0] pc_plus_four;
PCPlus4 PCPlus4_0 (
.pc(pc),
.pc_plus_four(pc_plus_four)
);
wire [31:0] instruction;
InstructionMemory #(
.SIZE(INSTR_MEM_SIZE)
) InstructionMemory_0 (
.Address(pc),
.Instruction(instruction)
);
wire [31:0] ID_pc_plus_four;
wire [31:0] ID_instruction;
IF_ID IF_ID_0 (
.clock(clock),
.WriteEnable(~Stall),
.Flush(0),
.pc_plus_four(pc_plus_four),
.ID_pc_plus_four(ID_pc_plus_four),
.instruction(instruction),
.ID_instruction(ID_instruction)
);
wire [5:0] opcode;
assign opcode = ID_instruction[31:26];
wire [4:0] rs;
assign rs = ID_instruction[25:21];
wire [4:0] rt;
assign rt = ID_instruction[20:16];
wire [4:0] rd;
assign rd = ID_instruction[15:11];
wire [5:0] funct;
assign funct = ID_instruction[5:0];
wire [15:0] immediate;
assign immediate = ID_instruction[15:0];
wire Stall;
HazardDetection HazardDetection_0 (
.EX_MemRead(EX_MemRead),
.rs(rs),
.rt(rt),
.EX_rt(EX_rt),
.Stall(Stall)
);
wire RegWrite;
wire RegDst;
wire MemRead;
wire MemWrite;
wire MemToReg;
wire Branch;
wire ALUSrc;
wire [1:0] ALUOp;
Control Control_0 (
.Opcode(opcode),
.RegWrite(RegWrite),
.RegDst(RegDst),
.MemRead(MemRead),
.MemWrite(MemWrite),
.MemToReg(MemToReg),
.Branch(Branch),
.ALUSrc(ALUSrc),
.ALUOp(ALUOp)
);
wire [8:0] BufferedControl;
mux2to1 #(
.WIDTH(9)
) MuxControlStall (
.inA( {RegWrite, RegDst, MemRead, MemWrite, MemToReg, Branch, ALUSrc,
ALUOp} ),
.inB(9'b0),
.select(Stall),
.out(BufferedControl)
);
wire [31:0] RegReadDataA;
wire [31:0] RegReadDataB;
wire [31:0] RegWriteData;
Registers Registers_0 (
.clock(clock),
.reset(reset),
.ReadAddressA(rs),
.ReadDataA(RegReadDataA),
.ReadAddressB(rt),
.ReadDataB(RegReadDataB),
.WriteEnable(WB_RegWrite),
.WriteAddress(WB_RegWriteAddress),
.WriteData(RegWriteData)
);
wire [31:0] extended;
SignExtender SignExtender_0 (
.immediate(immediate),
.extended(extended)
);
wire [31:0] EX_instruction;
wire [31:0] EX_pc_plus_four;
wire [31:0] EX_RegReadDataA;
wire [31:0] EX_RegReadDataB;
wire [31:0] EX_extended;
wire EX_RegWrite;
wire EX_RegDst;
wire EX_MemRead;
wire EX_MemWrite;
wire EX_MemToReg;
wire EX_Branch;
wire EX_ALUSrc;
wire [1:0] EX_ALUOp;
wire [4:0] EX_rs;
wire [4:0] EX_rt;
wire [4:0] EX_rd;
ID_EX ID_EX_0 (
.clock(clock),
.ID_instruction(ID_instruction),
.EX_instruction(EX_instruction),
.ID_pc_plus_four(ID_pc_plus_four),
.EX_pc_plus_four(EX_pc_plus_four),
.RegReadDataA(RegReadDataA),
.EX_RegReadDataA(EX_RegReadDataA),
.RegReadDataB(RegReadDataB),
.EX_RegReadDataB(EX_RegReadDataB),
.extended(extended),
.EX_extended(EX_extended),
.RegWrite(BufferedControl[8]),
.EX_RegWrite(EX_RegWrite),
.RegDst(BufferedControl[7]),
.EX_RegDst(EX_RegDst),
.MemRead(BufferedControl[6]),
.EX_MemRead(EX_MemRead),
.MemWrite(BufferedControl[5]),
.EX_MemWrite(EX_MemWrite),
.MemToReg(BufferedControl[4]),
.EX_MemToReg(EX_MemToReg),
.Branch(BufferedControl[3]),
.EX_Branch(EX_Branch),
.ALUSrc(BufferedControl[2]),
.EX_ALUSrc(EX_ALUSrc),
.ALUOp(BufferedControl[1:0]),
.EX_ALUOp(EX_ALUOp),
.rs(rs),
.EX_rs(EX_rs),
.rt(rt),
.EX_rt(EX_rt),
.rd(rd),
.EX_rd(EX_rd)
);
wire [1:0] ForwardA;
wire [31:0] ALUArgA;
mux4to1 #(
.WIDTH(32)
) MuxForwardA (
.inA(EX_RegReadDataA),
.inB(RegWriteData),
.inC(MEM_ALUResult),
.inD(32'b0),
.select(ForwardA),
.out(ALUArgA)
);
wire [1:0] ForwardB;
wire [31:0] ForwardBOut;
mux4to1 #(
.WIDTH(32)
) MuxForwardB (
.inA(EX_RegReadDataB),
.inB(RegWriteData),
.inC(MEM_ALUResult),
.inD(32'b0),
.select(ForwardB),
.out(ForwardBOut)
);
wire [31:0] ALUArgB;
mux2to1 #(
.WIDTH(32)
) MuxALUSrc (
.inA(ForwardBOut),
.inB(EX_extended),
.select(EX_ALUSrc),
.out(ALUArgB)
);
wire [31:0] ALUResult;
wire Zero;
ALU #(
.WIDTH(32)
) ALU_0 (
.op(ALUCtrl),
.inA(ALUArgA),
.inB(ALUArgB),
.out(ALUResult),
.zero(Zero)
);
wire [5:0] EX_funct;
assign EX_funct = EX_extended[5:0];
wire [3:0] ALUCtrl;
ALUControl ALUControl_0 (
.Funct(EX_funct),
.ALUOp(EX_ALUOp),
.ALUCtrl(ALUCtrl)
);
wire [4:0] RegWriteAddress;
mux2to1 #(
.WIDTH(5)
) MuxRegDst (
.inA(EX_rt),
.inB(EX_rd),
.select(EX_RegDst),
.out(RegWriteAddress)
);
wire [31:0] branch_address;
BranchAdder BranchAdder_0 (
.pc_plus_four(EX_pc_plus_four),
.extended_times_four(EX_extended << 2),
.branch_address(branch_address)
);
wire bneOne;
assign bneOne = ID_instruction[26];
wire [31:0] MEM_instruction;
wire [31:0] MEM_branch_address;
wire MEM_Zero;
wire [31:0] MEM_ALUResult;
wire [31:0] MEM_ForwardBOut;
wire [4:0] MEM_RegWriteAddress;
wire MEM_RegWrite;
wire MEM_MemRead;
wire MEM_MemWrite;
wire MEM_MemToReg;
wire MEM_Branch;
wire MEM_bneOne;
Forwarding Forwarding_0 (
.EX_rs(EX_rs),
.EX_rt(EX_rt),
.MEM_rd(MEM_rd),
.WB_rd(WB_rd),
.MEM_RegWrite(MEM_RegWrite),
.WB_RegWrite(WB_RegWrite),
.ForwardA(ForwardA),
.ForwardB(ForwardB)
);
EX_MEM EX_MEM_0 (
.clock(clock),
.EX_instruction(EX_instruction),
.MEM_instruction(MEM_instruction),
.branch_address(branch_address),
.MEM_branch_address(MEM_branch_address),
.Zero(Zero),
.MEM_Zero(MEM_Zero),
.ALUResult(ALUResult),
.MEM_ALUResult(MEM_ALUResult),
.ForwardBOut(ForwardBOut),
.MEM_ForwardBOut(MEM_ForwardBOut),
.RegWriteAddress(RegWriteAddress),
.MEM_RegWriteAddress(MEM_RegWriteAddress),
.EX_RegWrite(EX_RegWrite),
.MEM_RegWrite(MEM_RegWrite),
.EX_MemRead(EX_MemRead),
.MEM_MemRead(MEM_MemRead),
.EX_MemWrite(EX_MemWrite),
.MEM_MemWrite(MEM_MemWrite),
.EX_MemToReg(EX_MemToReg),
.MEM_MemToReg(MEM_MemToReg),
.EX_Branch(EX_Branch),
.MEM_Branch(MEM_Branch),
.bneOne(bneOne),
.MEM_bneOne(MEM_bneOne)
);
wire pc_chooser;
mux2to1 #(
.WIDTH(1)
) MuxBeqBne (
.inA(MEM_Zero),
.inB(~MEM_Zero),
.select(MEM_bneOne),
.out(pc_chooser)
);
mux2to1 #(
.WIDTH(32)
) MuxPCNext (
.inA(pc_plus_four),
.inB(MEM_branch_address),
.select(MEM_Branch && pc_chooser),
.out(pc_next)
);
wire [31:0] MemReadData;
Memory #(
.SIZE(DATA_MEM_SIZE)
) DataMemory_0 (
.clock(clock),
.Address(MEM_ALUResult),
.ReadEnable(MEM_MemRead),
.ReadData(MemReadData),
.WriteEnable(MEM_MemWrite),
.WriteData(MEM_ForwardBOut)
);
wire [4:0] MEM_rd;
assign MEM_rd = MEM_RegWriteAddress;
wire [31:0] WB_instruction;
wire [31:0] WB_MemReadData;
wire [31:0] WB_ALUResult;
wire [4:0] WB_RegWriteAddress;
wire WB_RegWrite;
wire WB_MemToReg;
MEM_WB MEM_WB_0 (
.clock(clock),
.MEM_instruction(MEM_instruction),
.WB_instruction(WB_instruction),
.MemReadData(MemReadData),
.WB_MemReadData(WB_MemReadData),
.MEM_ALUResult(MEM_ALUResult),
.WB_ALUResult(WB_ALUResult),
.MEM_RegWriteAddress(MEM_RegWriteAddress),
.WB_RegWriteAddress(WB_RegWriteAddress),
.MEM_RegWrite(MEM_RegWrite),
.WB_RegWrite(WB_RegWrite),
.MEM_MemToReg(MEM_MemToReg),
.WB_MemToReg(WB_MemToReg)
);
mux2to1 #(
.WIDTH(32)
) MuxMemtoReg (
.inA(WB_ALUResult),
.inB(WB_MemReadData),
.select(WB_MemToReg),
.out(RegWriteData)
);
wire [4:0] WB_rd;
assign WB_rd = WB_RegWriteAddress;
endmodule | 0 |
137,280 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module ALU #(
parameter WIDTH = 32
) (
input wire [3:0] op,
input wire [WIDTH - 1:0] inA,
input wire [WIDTH - 1:0] inB,
output reg [WIDTH - 1:0] out,
output wire zero
);
always @(op, inA, inB) begin
case(op)
0 : out = inA & inB;
1 : out = inA | inB;
2 : out = inA + inB;
6 : out = inA - inB;
7 : out = (inA < inB) ? 1 : 0;
12 : out = ~(inA | inB);
default: out = 32'bx;
endcase
end
assign zero = (out == 0);
endmodule | module ALU #(
parameter WIDTH = 32
) (
input wire [3:0] op,
input wire [WIDTH - 1:0] inA,
input wire [WIDTH - 1:0] inB,
output reg [WIDTH - 1:0] out,
output wire zero
); |
always @(op, inA, inB) begin
case(op)
0 : out = inA & inB;
1 : out = inA | inB;
2 : out = inA + inB;
6 : out = inA - inB;
7 : out = (inA < inB) ? 1 : 0;
12 : out = ~(inA | inB);
default: out = 32'bx;
endcase
end
assign zero = (out == 0);
endmodule | 0 |
137,281 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module ALUControl (
input wire [5:0] Funct,
input wire [1:0] ALUOp,
output reg [3:0] ALUCtrl
);
always @ (Funct, ALUOp) begin
case(ALUOp)
0 : ALUCtrl = 4'b0010;
1 : ALUCtrl = 4'b0110;
2 : case(Funct)
32 : ALUCtrl = 4'b0010;
34 : ALUCtrl = 4'b0110;
36 : ALUCtrl = 4'b0000;
37 : ALUCtrl = 4'b0001;
42 : ALUCtrl = 4'b0111;
default: ALUCtrl = 4'bx;
endcase
default: ALUCtrl = 4'bx;
endcase
end
endmodule | module ALUControl (
input wire [5:0] Funct,
input wire [1:0] ALUOp,
output reg [3:0] ALUCtrl
); |
always @ (Funct, ALUOp) begin
case(ALUOp)
0 : ALUCtrl = 4'b0010;
1 : ALUCtrl = 4'b0110;
2 : case(Funct)
32 : ALUCtrl = 4'b0010;
34 : ALUCtrl = 4'b0110;
36 : ALUCtrl = 4'b0000;
37 : ALUCtrl = 4'b0001;
42 : ALUCtrl = 4'b0111;
default: ALUCtrl = 4'bx;
endcase
default: ALUCtrl = 4'bx;
endcase
end
endmodule | 0 |
137,282 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module BranchAdder (
input wire [31:0] pc_plus_four,
input wire [31:0] extended_times_four,
output wire [31:0] branch_address
);
assign branch_address = pc_plus_four + extended_times_four;
endmodule | module BranchAdder (
input wire [31:0] pc_plus_four,
input wire [31:0] extended_times_four,
output wire [31:0] branch_address
); |
assign branch_address = pc_plus_four + extended_times_four;
endmodule | 0 |
137,283 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module Control (
input wire [5:0] Opcode,
output reg RegWrite,
output reg RegDst,
output reg MemRead,
output reg MemWrite,
output reg MemToReg,
output reg Branch,
output reg ALUSrc,
output reg [1:0] ALUOp
);
always @ (Opcode) begin
case(Opcode)
0 : begin
RegDst = 1'b1;
Branch = 1'b0;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b10;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b1;
end
4 : begin
RegDst = 1'b0;
Branch = 1'b1;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b01;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
end
5 : begin
RegDst = 1'b0;
Branch = 1'b1;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b11;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
end
35 : begin
RegDst = 1'b0;
Branch = 1'b0;
MemRead = 1'b1;
MemToReg = 1'b1;
ALUOp = 2'b00;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
end
43 : begin
RegDst = 1'b0;
Branch = 1'b0;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b00;
MemWrite = 1'b1;
ALUSrc = 1'b1;
RegWrite = 1'b0;
end
default : begin
RegDst = 1'b0;
Branch = 1'b0;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b11;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
end
endcase
end
endmodule | module Control (
input wire [5:0] Opcode,
output reg RegWrite,
output reg RegDst,
output reg MemRead,
output reg MemWrite,
output reg MemToReg,
output reg Branch,
output reg ALUSrc,
output reg [1:0] ALUOp
); |
always @ (Opcode) begin
case(Opcode)
0 : begin
RegDst = 1'b1;
Branch = 1'b0;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b10;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b1;
end
4 : begin
RegDst = 1'b0;
Branch = 1'b1;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b01;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
end
5 : begin
RegDst = 1'b0;
Branch = 1'b1;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b11;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
end
35 : begin
RegDst = 1'b0;
Branch = 1'b0;
MemRead = 1'b1;
MemToReg = 1'b1;
ALUOp = 2'b00;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
end
43 : begin
RegDst = 1'b0;
Branch = 1'b0;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b00;
MemWrite = 1'b1;
ALUSrc = 1'b1;
RegWrite = 1'b0;
end
default : begin
RegDst = 1'b0;
Branch = 1'b0;
MemRead = 1'b0;
MemToReg = 1'b0;
ALUOp = 2'b11;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
end
endcase
end
endmodule | 0 |
137,284 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module InstructionMemory #(
parameter SIZE = 1024
) (
input wire [31:0] Address,
output reg [31:0] Instruction
);
reg [31:0] data[SIZE - 1:0];
always @(Address) begin
if (Address[31:12]) begin
$display("\nInstructionMemory WARNING (time %0d):", $time);
$display("unused address MSBs not zero\n");
end
Instruction = data[Address[11:0]];
end
endmodule | module InstructionMemory #(
parameter SIZE = 1024
) (
input wire [31:0] Address,
output reg [31:0] Instruction
); |
reg [31:0] data[SIZE - 1:0];
always @(Address) begin
if (Address[31:12]) begin
$display("\nInstructionMemory WARNING (time %0d):", $time);
$display("unused address MSBs not zero\n");
end
Instruction = data[Address[11:0]];
end
endmodule | 0 |
137,285 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module mux2to1 #(
parameter WIDTH = 1
) (
input wire [WIDTH - 1:0] inA,
input wire [WIDTH - 1:0] inB,
input wire select,
output reg [WIDTH - 1:0] out
);
always @(inA, inB, select) begin
case(select)
0 : out = inA;
1 : out = inB;
default: out = inA;
endcase
end
endmodule | module mux2to1 #(
parameter WIDTH = 1
) (
input wire [WIDTH - 1:0] inA,
input wire [WIDTH - 1:0] inB,
input wire select,
output reg [WIDTH - 1:0] out
); |
always @(inA, inB, select) begin
case(select)
0 : out = inA;
1 : out = inB;
default: out = inA;
endcase
end
endmodule | 0 |
137,286 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module mux4to1 #(
parameter WIDTH = 1
) (
input wire [WIDTH - 1:0] inA,
input wire [WIDTH - 1:0] inB,
input wire [WIDTH - 1:0] inC,
input wire [WIDTH - 1:0] inD,
input wire [1:0] select,
output reg [WIDTH - 1:0] out
);
always @(inA, inB, inC, inD, select) begin
case(select)
0 : out = inA;
1 : out = inB;
2 : out = inC;
3 : out = inD;
default: out = inA;
endcase
end
endmodule | module mux4to1 #(
parameter WIDTH = 1
) (
input wire [WIDTH - 1:0] inA,
input wire [WIDTH - 1:0] inB,
input wire [WIDTH - 1:0] inC,
input wire [WIDTH - 1:0] inD,
input wire [1:0] select,
output reg [WIDTH - 1:0] out
); |
always @(inA, inB, inC, inD, select) begin
case(select)
0 : out = inA;
1 : out = inB;
2 : out = inC;
3 : out = inD;
default: out = inA;
endcase
end
endmodule | 0 |
137,287 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module Memory #(
parameter SIZE = 4096
) (
input wire clock,
input wire [31:0] Address,
input wire ReadEnable,
output wire [31:0] ReadData,
input wire WriteEnable,
input wire [31:0] WriteData
);
reg [31:0] data[SIZE - 1:0];
always @(ReadEnable, WriteEnable)
if (ReadEnable && WriteEnable) begin
$display ("\nDataMemory ERROR (time %0d):", $time);
$display ("ReadEnable and WriteEnable both active\n");
end
always @(posedge ReadEnable, posedge WriteEnable)
if (Address[31:12]) begin
$display("\nDataMemory WARNING (time %0d):", $time);
$display("unused address MSBs not zero\n");
end
assign ReadData = (~WriteEnable && ReadEnable) ? data[Address[11:0]] : 32'bx;
always @(negedge clock)
if (~ReadEnable && WriteEnable) begin
data[Address[11:0]] <= WriteData;
$display("DataMemory:");
$display("\twrote data %2d to address %2d at time %3d\n",
WriteData, Address[11:0], $time);
end
endmodule | module Memory #(
parameter SIZE = 4096
) (
input wire clock,
input wire [31:0] Address,
input wire ReadEnable,
output wire [31:0] ReadData,
input wire WriteEnable,
input wire [31:0] WriteData
); |
reg [31:0] data[SIZE - 1:0];
always @(ReadEnable, WriteEnable)
if (ReadEnable && WriteEnable) begin
$display ("\nDataMemory ERROR (time %0d):", $time);
$display ("ReadEnable and WriteEnable both active\n");
end
always @(posedge ReadEnable, posedge WriteEnable)
if (Address[31:12]) begin
$display("\nDataMemory WARNING (time %0d):", $time);
$display("unused address MSBs not zero\n");
end
assign ReadData = (~WriteEnable && ReadEnable) ? data[Address[11:0]] : 32'bx;
always @(negedge clock)
if (~ReadEnable && WriteEnable) begin
data[Address[11:0]] <= WriteData;
$display("DataMemory:");
$display("\twrote data %2d to address %2d at time %3d\n",
WriteData, Address[11:0], $time);
end
endmodule | 0 |
137,288 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module ProgramCounter (
input wire clock,
input wire reset,
input wire Stall,
input wire [31:0] pc_next,
output reg [31:0] pc
);
always @(posedge clock, negedge reset) begin
if (~reset)
pc = 0;
else if (~Stall)
pc = pc_next;
end
endmodule | module ProgramCounter (
input wire clock,
input wire reset,
input wire Stall,
input wire [31:0] pc_next,
output reg [31:0] pc
); |
always @(posedge clock, negedge reset) begin
if (~reset)
pc = 0;
else if (~Stall)
pc = pc_next;
end
endmodule | 0 |
137,289 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module PCPlus4 (
input wire [31:0] pc,
output wire [31:0] pc_plus_four
);
assign pc_plus_four = pc + 4;
endmodule | module PCPlus4 (
input wire [31:0] pc,
output wire [31:0] pc_plus_four
); |
assign pc_plus_four = pc + 4;
endmodule | 0 |
137,290 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module Registers (
input wire clock,
input wire reset,
input wire [4:0] ReadAddressA,
output reg [31:0] ReadDataA,
input wire [4:0] ReadAddressB,
output reg [31:0] ReadDataB,
input wire WriteEnable,
input wire [4:0] WriteAddress,
input wire [31:0] WriteData
);
reg [31:0] data[0:31];
integer k;
always @(posedge clock, ReadAddressA, ReadAddressB) begin
ReadDataA = data[ReadAddressA];
ReadDataB = data[ReadAddressB];
end
always @(negedge reset)
for (k = 0; k < 32; k = k + 1)
data[k] = 0;
always @(negedge clock)
if (reset && WriteEnable) begin
data[WriteAddress] <= WriteData;
$display("Registers:");
$display("\twrote data %2d to register %2d at time %3d\n",
WriteData, WriteAddress, $time);
end
endmodule | module Registers (
input wire clock,
input wire reset,
input wire [4:0] ReadAddressA,
output reg [31:0] ReadDataA,
input wire [4:0] ReadAddressB,
output reg [31:0] ReadDataB,
input wire WriteEnable,
input wire [4:0] WriteAddress,
input wire [31:0] WriteData
); |
reg [31:0] data[0:31];
integer k;
always @(posedge clock, ReadAddressA, ReadAddressB) begin
ReadDataA = data[ReadAddressA];
ReadDataB = data[ReadAddressB];
end
always @(negedge reset)
for (k = 0; k < 32; k = k + 1)
data[k] = 0;
always @(negedge clock)
if (reset && WriteEnable) begin
data[WriteAddress] <= WriteData;
$display("Registers:");
$display("\twrote data %2d to register %2d at time %3d\n",
WriteData, WriteAddress, $time);
end
endmodule | 0 |
137,291 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module SignExtender (
input wire [15:0] immediate,
output reg [31:0] extended
);
always @(immediate) begin
extended[31:0] = {{16{immediate[15]}}, immediate[15:0]};
end
endmodule | module SignExtender (
input wire [15:0] immediate,
output reg [31:0] extended
); |
always @(immediate) begin
extended[31:0] = {{16{immediate[15]}}, immediate[15:0]};
end
endmodule | 0 |
137,292 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module IF_ID (
input wire clock,
input wire WriteEnable,
input wire Flush,
input wire [31:0] pc_plus_four,
output reg [31:0] ID_pc_plus_four,
input wire [31:0] instruction,
output reg [31:0] ID_instruction
);
always @(negedge clock) begin
if (Flush) begin
ID_pc_plus_four <= 0;
ID_instruction <= 0;
end
else if (WriteEnable) begin
ID_pc_plus_four <= pc_plus_four;
ID_instruction <= instruction;
end
end
endmodule | module IF_ID (
input wire clock,
input wire WriteEnable,
input wire Flush,
input wire [31:0] pc_plus_four,
output reg [31:0] ID_pc_plus_four,
input wire [31:0] instruction,
output reg [31:0] ID_instruction
); |
always @(negedge clock) begin
if (Flush) begin
ID_pc_plus_four <= 0;
ID_instruction <= 0;
end
else if (WriteEnable) begin
ID_pc_plus_four <= pc_plus_four;
ID_instruction <= instruction;
end
end
endmodule | 0 |
137,293 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module ID_EX (
input wire clock,
input wire [31:0] ID_instruction,
output reg [31:0] EX_instruction,
input wire [31:0] ID_pc_plus_four,
output reg [31:0] EX_pc_plus_four,
input wire [31:0] RegReadDataA,
output reg [31:0] EX_RegReadDataA,
input wire [31:0] RegReadDataB,
output reg [31:0] EX_RegReadDataB,
input wire [31:0] extended,
output reg [31:0] EX_extended,
input wire RegWrite,
output reg EX_RegWrite,
input wire RegDst,
output reg EX_RegDst,
input wire MemRead,
output reg EX_MemRead,
input wire MemWrite,
output reg EX_MemWrite,
input wire MemToReg,
output reg EX_MemToReg,
input wire Branch,
output reg EX_Branch,
input wire ALUSrc,
output reg EX_ALUSrc,
input wire [1:0] ALUOp,
output reg [1:0] EX_ALUOp,
input wire [4:0] rs,
output reg [4:0] EX_rs,
input wire [4:0] rt,
output reg [4:0] EX_rt,
input wire [4:0] rd,
output reg [4:0] EX_rd
);
always @(negedge clock) begin
EX_instruction <= ID_instruction;
EX_pc_plus_four <= ID_pc_plus_four;
EX_RegReadDataA <= RegReadDataA;
EX_RegReadDataB <= RegReadDataB;
EX_extended <= extended;
EX_RegWrite <= RegWrite;
EX_RegDst <= RegDst;
EX_MemRead <= MemRead;
EX_MemWrite <= MemWrite;
EX_MemToReg <= MemToReg;
EX_Branch <= Branch;
EX_ALUSrc <= ALUSrc;
EX_ALUOp <= ALUOp;
EX_rs <= rs;
EX_rt <= rt;
EX_rd <= rd;
end
endmodule | module ID_EX (
input wire clock,
input wire [31:0] ID_instruction,
output reg [31:0] EX_instruction,
input wire [31:0] ID_pc_plus_four,
output reg [31:0] EX_pc_plus_four,
input wire [31:0] RegReadDataA,
output reg [31:0] EX_RegReadDataA,
input wire [31:0] RegReadDataB,
output reg [31:0] EX_RegReadDataB,
input wire [31:0] extended,
output reg [31:0] EX_extended,
input wire RegWrite,
output reg EX_RegWrite,
input wire RegDst,
output reg EX_RegDst,
input wire MemRead,
output reg EX_MemRead,
input wire MemWrite,
output reg EX_MemWrite,
input wire MemToReg,
output reg EX_MemToReg,
input wire Branch,
output reg EX_Branch,
input wire ALUSrc,
output reg EX_ALUSrc,
input wire [1:0] ALUOp,
output reg [1:0] EX_ALUOp,
input wire [4:0] rs,
output reg [4:0] EX_rs,
input wire [4:0] rt,
output reg [4:0] EX_rt,
input wire [4:0] rd,
output reg [4:0] EX_rd
); |
always @(negedge clock) begin
EX_instruction <= ID_instruction;
EX_pc_plus_four <= ID_pc_plus_four;
EX_RegReadDataA <= RegReadDataA;
EX_RegReadDataB <= RegReadDataB;
EX_extended <= extended;
EX_RegWrite <= RegWrite;
EX_RegDst <= RegDst;
EX_MemRead <= MemRead;
EX_MemWrite <= MemWrite;
EX_MemToReg <= MemToReg;
EX_Branch <= Branch;
EX_ALUSrc <= ALUSrc;
EX_ALUOp <= ALUOp;
EX_rs <= rs;
EX_rt <= rt;
EX_rd <= rd;
end
endmodule | 0 |
137,294 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module EX_MEM (
input wire clock,
input wire [31:0] EX_instruction,
output reg [31:0] MEM_instruction,
input wire [31:0] branch_address,
output reg [31:0] MEM_branch_address,
input wire Zero,
output reg MEM_Zero,
input wire [31:0] ALUResult,
output reg [31:0] MEM_ALUResult,
input wire [31:0] ForwardBOut,
output reg [31:0] MEM_ForwardBOut,
input wire [4:0] RegWriteAddress,
output reg [4:0] MEM_RegWriteAddress,
input wire EX_RegWrite,
output reg MEM_RegWrite,
input wire EX_MemRead,
output reg MEM_MemRead,
input wire EX_MemWrite,
output reg MEM_MemWrite,
input wire EX_MemToReg,
output reg MEM_MemToReg,
input wire EX_Branch,
output reg MEM_Branch,
input wire bneOne,
output reg MEM_bneOne
);
always @(negedge clock) begin
MEM_instruction <= EX_instruction;
MEM_branch_address <= branch_address;
MEM_Zero <= Zero;
MEM_ALUResult <= ALUResult;
MEM_ForwardBOut <= ForwardBOut;
MEM_RegWriteAddress <= RegWriteAddress;
MEM_RegWrite <= EX_RegWrite;
MEM_MemRead <= EX_MemRead;
MEM_MemWrite <= EX_MemWrite;
MEM_MemToReg <= EX_MemToReg;
MEM_Branch <= EX_Branch;
MEM_bneOne <= bneOne;
end
endmodule | module EX_MEM (
input wire clock,
input wire [31:0] EX_instruction,
output reg [31:0] MEM_instruction,
input wire [31:0] branch_address,
output reg [31:0] MEM_branch_address,
input wire Zero,
output reg MEM_Zero,
input wire [31:0] ALUResult,
output reg [31:0] MEM_ALUResult,
input wire [31:0] ForwardBOut,
output reg [31:0] MEM_ForwardBOut,
input wire [4:0] RegWriteAddress,
output reg [4:0] MEM_RegWriteAddress,
input wire EX_RegWrite,
output reg MEM_RegWrite,
input wire EX_MemRead,
output reg MEM_MemRead,
input wire EX_MemWrite,
output reg MEM_MemWrite,
input wire EX_MemToReg,
output reg MEM_MemToReg,
input wire EX_Branch,
output reg MEM_Branch,
input wire bneOne,
output reg MEM_bneOne
); |
always @(negedge clock) begin
MEM_instruction <= EX_instruction;
MEM_branch_address <= branch_address;
MEM_Zero <= Zero;
MEM_ALUResult <= ALUResult;
MEM_ForwardBOut <= ForwardBOut;
MEM_RegWriteAddress <= RegWriteAddress;
MEM_RegWrite <= EX_RegWrite;
MEM_MemRead <= EX_MemRead;
MEM_MemWrite <= EX_MemWrite;
MEM_MemToReg <= EX_MemToReg;
MEM_Branch <= EX_Branch;
MEM_bneOne <= bneOne;
end
endmodule | 0 |
137,295 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module MEM_WB (
input wire clock,
input wire [31:0] MEM_instruction,
output reg [31:0] WB_instruction,
input wire [31:0] MemReadData,
output reg [31:0] WB_MemReadData,
input wire [31:0] MEM_ALUResult,
output reg [31:0] WB_ALUResult,
input wire [4:0] MEM_RegWriteAddress,
output reg [4:0] WB_RegWriteAddress,
input wire MEM_RegWrite,
output reg WB_RegWrite,
input wire MEM_MemToReg,
output reg WB_MemToReg
);
always @(negedge clock) begin
WB_instruction <= MEM_instruction;
WB_MemReadData <= MemReadData;
WB_ALUResult <= MEM_ALUResult;
WB_RegWriteAddress <= MEM_RegWriteAddress;
WB_RegWrite <= MEM_RegWrite;
WB_MemToReg <= MEM_MemToReg;
end
endmodule | module MEM_WB (
input wire clock,
input wire [31:0] MEM_instruction,
output reg [31:0] WB_instruction,
input wire [31:0] MemReadData,
output reg [31:0] WB_MemReadData,
input wire [31:0] MEM_ALUResult,
output reg [31:0] WB_ALUResult,
input wire [4:0] MEM_RegWriteAddress,
output reg [4:0] WB_RegWriteAddress,
input wire MEM_RegWrite,
output reg WB_RegWrite,
input wire MEM_MemToReg,
output reg WB_MemToReg
); |
always @(negedge clock) begin
WB_instruction <= MEM_instruction;
WB_MemReadData <= MemReadData;
WB_ALUResult <= MEM_ALUResult;
WB_RegWriteAddress <= MEM_RegWriteAddress;
WB_RegWrite <= MEM_RegWrite;
WB_MemToReg <= MEM_MemToReg;
end
endmodule | 0 |
137,296 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module Forwarding (
input wire [4:0] EX_rs,
input wire [4:0] EX_rt,
input wire [4:0] MEM_rd,
input wire [4:0] WB_rd,
input wire MEM_RegWrite,
input wire WB_RegWrite,
output reg [1:0] ForwardA,
output reg [1:0] ForwardB
);
always @*
if (WB_RegWrite && WB_rd && (WB_rd == EX_rs) &&
((MEM_rd != EX_rs) || (~MEM_RegWrite)))
ForwardA = 2'b01;
else if (MEM_RegWrite && MEM_rd && (MEM_rd == EX_rs))
ForwardA = 2'b10;
else
ForwardA = 2'b00;
always @*
if (WB_RegWrite && WB_rd && (WB_rd == EX_rt) &&
((MEM_rd != EX_rt) || (~MEM_RegWrite)))
ForwardB = 2'b01;
else if (MEM_RegWrite && MEM_rd && (MEM_rd == EX_rt))
ForwardB = 2'b10;
else
ForwardB = 2'b00;
endmodule | module Forwarding (
input wire [4:0] EX_rs,
input wire [4:0] EX_rt,
input wire [4:0] MEM_rd,
input wire [4:0] WB_rd,
input wire MEM_RegWrite,
input wire WB_RegWrite,
output reg [1:0] ForwardA,
output reg [1:0] ForwardB
); |
always @*
if (WB_RegWrite && WB_rd && (WB_rd == EX_rs) &&
((MEM_rd != EX_rs) || (~MEM_RegWrite)))
ForwardA = 2'b01;
else if (MEM_RegWrite && MEM_rd && (MEM_rd == EX_rs))
ForwardA = 2'b10;
else
ForwardA = 2'b00;
always @*
if (WB_RegWrite && WB_rd && (WB_rd == EX_rt) &&
((MEM_rd != EX_rt) || (~MEM_RegWrite)))
ForwardB = 2'b01;
else if (MEM_RegWrite && MEM_rd && (MEM_rd == EX_rt))
ForwardB = 2'b10;
else
ForwardB = 2'b00;
endmodule | 0 |
137,297 | data/full_repos/permissive/77767059/library.v | 77,767,059 | library.v | v | 723 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/library.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Error: Exiting due to 1 error(s)\n' | 295,871 | module | module HazardDetection (
input wire EX_MemRead,
input wire [4:0] rs,
input wire [4:0] rt,
input wire [4:0] EX_rt,
output reg Stall
);
always @*
if (EX_MemRead && ((EX_rt == rs) || (EX_rt == rt))) begin
Stall = 1;
end
else begin
Stall = 0;
end
endmodule | module HazardDetection (
input wire EX_MemRead,
input wire [4:0] rs,
input wire [4:0] rt,
input wire [4:0] EX_rt,
output reg Stall
); |
always @*
if (EX_MemRead && ((EX_rt == rs) || (EX_rt == rt))) begin
Stall = 1;
end
else begin
Stall = 0;
end
endmodule | 0 |
137,298 | data/full_repos/permissive/77767059/testbench_8.v | 77,767,059 | testbench_8.v | v | 130 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/testbench_8.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_8.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/77767059/testbench_8.v:44: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dumpfile_8.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_8.v:45: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, cpu_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_8.v:47: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, CPU_0.Registers_0.data[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_8.v:49: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, CPU_0.InstructionMemory_0.data[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_8.v:51: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, CPU_0.DataMemory_0.data[i]);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_8.v:64: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_8.v:71: Unsupported: Ignoring delay on this delayed statement.\n #55;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_8.v:72: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n' | 295,873 | module | module cpu_tb;
localparam N_REGISTERS = 32;
localparam IMS = 32;
localparam DMS = 32;
reg clock, reset;
integer i;
CPU #(.INSTR_MEM_SIZE(IMS), .DATA_MEM_SIZE(DMS)) CPU_0 (clock, reset);
always begin
#5;
clock = ~clock;
end
initial begin
$dumpfile("dumpfile_8.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
clock = 1;
reset = 0;
$readmemb("program_8.mbin", CPU_0.InstructionMemory_0.data);
#5;
reset = 1;
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#55;
#30;
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 2) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 4) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 8) &&
(CPU_0.Registers_0.data[9] == 1) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 13) &&
(CPU_0.Registers_0.data[14] == 14) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 17) &&
(CPU_0.Registers_0.data[18] == 12) &&
(CPU_0.Registers_0.data[19] == 19) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 29) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31) &&
(CPU_0.DataMemory_0.data[16] == 12) &&
(CPU_0.ProgramCounter_0.pc == 32)) begin
$display("\n");
$display("program 8 completed successfully");
$display("\n");
end
else begin
$display("\n");
$display("program 8 failed");
$display("\n");
end
$finish;
end
endmodule | module cpu_tb; |
localparam N_REGISTERS = 32;
localparam IMS = 32;
localparam DMS = 32;
reg clock, reset;
integer i;
CPU #(.INSTR_MEM_SIZE(IMS), .DATA_MEM_SIZE(DMS)) CPU_0 (clock, reset);
always begin
#5;
clock = ~clock;
end
initial begin
$dumpfile("dumpfile_8.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
clock = 1;
reset = 0;
$readmemb("program_8.mbin", CPU_0.InstructionMemory_0.data);
#5;
reset = 1;
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#55;
#30;
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 2) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 4) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 8) &&
(CPU_0.Registers_0.data[9] == 1) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 13) &&
(CPU_0.Registers_0.data[14] == 14) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 17) &&
(CPU_0.Registers_0.data[18] == 12) &&
(CPU_0.Registers_0.data[19] == 19) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 29) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31) &&
(CPU_0.DataMemory_0.data[16] == 12) &&
(CPU_0.ProgramCounter_0.pc == 32)) begin
$display("\n");
$display("program 8 completed successfully");
$display("\n");
end
else begin
$display("\n");
$display("program 8 failed");
$display("\n");
end
$finish;
end
endmodule | 0 |
137,299 | data/full_repos/permissive/77767059/testbench_9.v | 77,767,059 | testbench_9.v | v | 204 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/77767059/testbench_9.v:18: Cannot find include file: constants.h\n`include "constants.h" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.v\n data/full_repos/permissive/77767059,data/full_repos/permissive/77767059/constants.h.sv\n constants.h\n constants.h.v\n constants.h.sv\n obj_dir/constants.h\n obj_dir/constants.h.v\n obj_dir/constants.h.sv\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/77767059/testbench_9.v:53: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dumpfile_9.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_9.v:54: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, cpu_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_9.v:56: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, CPU_0.Registers_0.data[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_9.v:58: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, CPU_0.InstructionMemory_0.data[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77767059/testbench_9.v:60: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, CPU_0.DataMemory_0.data[i]);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:80: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:87: Unsupported: Ignoring delay on this delayed statement.\n #65;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:88: Unsupported: Ignoring delay on this delayed statement.\n #65;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:89: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:90: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:91: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77767059/testbench_9.v:92: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: Exiting due to 6 error(s), 8 warning(s)\n' | 295,874 | module | module cpu_tb;
localparam N_REGISTERS = 32;
localparam IMS = 64;
localparam DMS = 32;
reg clock, reset;
integer i;
integer tests_passed;
CPU #(
.INSTR_MEM_SIZE(IMS),
.DATA_MEM_SIZE(DMS)
) CPU_0 (
.clock(clock),
.reset(reset)
);
always begin
#5;
clock = ~clock;
end
initial begin
$dumpfile("dumpfile_9.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
clock = 1;
reset = 0;
for (i = 0; i < DMS; i = i + 1)
CPU_0.DataMemory_0.data[i] = i;
$readmemb("program_9.mbin", CPU_0.InstructionMemory_0.data);
$display("\n");
$display("Program 9 loaded and running.\n");
#5;
reset = 1;
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#65;
#65;
#5;
#30;
#10;
#20;
tests_passed = 0;
$display("\n");
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 28) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 30) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 24) &&
(CPU_0.Registers_0.data[9] == 58) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 31) &&
(CPU_0.Registers_0.data[14] == 31) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 17) &&
(CPU_0.Registers_0.data[18] == 18) &&
(CPU_0.Registers_0.data[19] == 16) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 1) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31)) begin
tests_passed = tests_passed + 1;
$display("Registers OK. All values are correct.");
end
else begin
$display("Registers mismatch. Wrong values.");
end
$display("\n");
if ((CPU_0.DataMemory_0.data[0] == 0) &&
(CPU_0.DataMemory_0.data[1] == 1) &&
(CPU_0.DataMemory_0.data[2] == 2) &&
(CPU_0.DataMemory_0.data[3] == 3) &&
(CPU_0.DataMemory_0.data[4] == 4) &&
(CPU_0.DataMemory_0.data[5] == 5) &&
(CPU_0.DataMemory_0.data[6] == 6) &&
(CPU_0.DataMemory_0.data[7] == 7) &&
(CPU_0.DataMemory_0.data[8] == 28) &&
(CPU_0.DataMemory_0.data[9] == 9) &&
(CPU_0.DataMemory_0.data[10] == 10) &&
(CPU_0.DataMemory_0.data[11] == 11) &&
(CPU_0.DataMemory_0.data[12] == 31) &&
(CPU_0.DataMemory_0.data[13] == 13) &&
(CPU_0.DataMemory_0.data[14] == 14) &&
(CPU_0.DataMemory_0.data[15] == 15) &&
(CPU_0.DataMemory_0.data[16] == 16) &&
(CPU_0.DataMemory_0.data[17] == 17) &&
(CPU_0.DataMemory_0.data[18] == 18) &&
(CPU_0.DataMemory_0.data[19] == 19) &&
(CPU_0.DataMemory_0.data[20] == 20) &&
(CPU_0.DataMemory_0.data[21] == 21) &&
(CPU_0.DataMemory_0.data[22] == 22) &&
(CPU_0.DataMemory_0.data[23] == 23) &&
(CPU_0.DataMemory_0.data[24] == 24) &&
(CPU_0.DataMemory_0.data[25] == 25) &&
(CPU_0.DataMemory_0.data[26] == 26) &&
(CPU_0.DataMemory_0.data[27] == 27) &&
(CPU_0.DataMemory_0.data[28] == 28) &&
(CPU_0.DataMemory_0.data[29] == 29) &&
(CPU_0.DataMemory_0.data[30] == 30) &&
(CPU_0.DataMemory_0.data[31] == 31)) begin
tests_passed = tests_passed + 1;
$display("DataMemory OK. All values are correct.");
end
else begin
$display("DataMemory mismatch. Wrong values.");
end
$display("\n");
if (tests_passed == 2)
$display("Program 9 successfully run.");
else
$display("Program 9 has failed.");
$display("\n");
$finish;
end
endmodule | module cpu_tb; |
localparam N_REGISTERS = 32;
localparam IMS = 64;
localparam DMS = 32;
reg clock, reset;
integer i;
integer tests_passed;
CPU #(
.INSTR_MEM_SIZE(IMS),
.DATA_MEM_SIZE(DMS)
) CPU_0 (
.clock(clock),
.reset(reset)
);
always begin
#5;
clock = ~clock;
end
initial begin
$dumpfile("dumpfile_9.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
clock = 1;
reset = 0;
for (i = 0; i < DMS; i = i + 1)
CPU_0.DataMemory_0.data[i] = i;
$readmemb("program_9.mbin", CPU_0.InstructionMemory_0.data);
$display("\n");
$display("Program 9 loaded and running.\n");
#5;
reset = 1;
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#65;
#65;
#5;
#30;
#10;
#20;
tests_passed = 0;
$display("\n");
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 28) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 30) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 24) &&
(CPU_0.Registers_0.data[9] == 58) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 31) &&
(CPU_0.Registers_0.data[14] == 31) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 17) &&
(CPU_0.Registers_0.data[18] == 18) &&
(CPU_0.Registers_0.data[19] == 16) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 1) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31)) begin
tests_passed = tests_passed + 1;
$display("Registers OK. All values are correct.");
end
else begin
$display("Registers mismatch. Wrong values.");
end
$display("\n");
if ((CPU_0.DataMemory_0.data[0] == 0) &&
(CPU_0.DataMemory_0.data[1] == 1) &&
(CPU_0.DataMemory_0.data[2] == 2) &&
(CPU_0.DataMemory_0.data[3] == 3) &&
(CPU_0.DataMemory_0.data[4] == 4) &&
(CPU_0.DataMemory_0.data[5] == 5) &&
(CPU_0.DataMemory_0.data[6] == 6) &&
(CPU_0.DataMemory_0.data[7] == 7) &&
(CPU_0.DataMemory_0.data[8] == 28) &&
(CPU_0.DataMemory_0.data[9] == 9) &&
(CPU_0.DataMemory_0.data[10] == 10) &&
(CPU_0.DataMemory_0.data[11] == 11) &&
(CPU_0.DataMemory_0.data[12] == 31) &&
(CPU_0.DataMemory_0.data[13] == 13) &&
(CPU_0.DataMemory_0.data[14] == 14) &&
(CPU_0.DataMemory_0.data[15] == 15) &&
(CPU_0.DataMemory_0.data[16] == 16) &&
(CPU_0.DataMemory_0.data[17] == 17) &&
(CPU_0.DataMemory_0.data[18] == 18) &&
(CPU_0.DataMemory_0.data[19] == 19) &&
(CPU_0.DataMemory_0.data[20] == 20) &&
(CPU_0.DataMemory_0.data[21] == 21) &&
(CPU_0.DataMemory_0.data[22] == 22) &&
(CPU_0.DataMemory_0.data[23] == 23) &&
(CPU_0.DataMemory_0.data[24] == 24) &&
(CPU_0.DataMemory_0.data[25] == 25) &&
(CPU_0.DataMemory_0.data[26] == 26) &&
(CPU_0.DataMemory_0.data[27] == 27) &&
(CPU_0.DataMemory_0.data[28] == 28) &&
(CPU_0.DataMemory_0.data[29] == 29) &&
(CPU_0.DataMemory_0.data[30] == 30) &&
(CPU_0.DataMemory_0.data[31] == 31)) begin
tests_passed = tests_passed + 1;
$display("DataMemory OK. All values are correct.");
end
else begin
$display("DataMemory mismatch. Wrong values.");
end
$display("\n");
if (tests_passed == 2)
$display("Program 9 successfully run.");
else
$display("Program 9 has failed.");
$display("\n");
$finish;
end
endmodule | 0 |
137,300 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/pcie_status_check_v1_00_a/hdl/verilog/user_logic.v | 77,907,036 | user_logic.v | v | 86 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(48, 85)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/pcie_status_check_v1_00_a/hdl/verilog/user_logic.v:59: Little bit endian vector: MSB < LSB of bit range: 0:31\n input [0 : 31] Bus2IP_Addr,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/pcie_status_check_v1_00_a/hdl/verilog/user_logic.v:80: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'sig\' generates 1 bits.\n : ... In instance user_logic\n assign IP2Bus_Data = sig;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 295,875 | module | module user_logic
#
(
parameter C_NUM_REG = 1,
parameter C_SLV_DWIDTH = 32
)
(
input pcie_mmcm_lock,
input Bus2IP_Clk,
input Bus2IP_Resetn,
input [0 : 31] Bus2IP_Addr,
input Bus2IP_CS,
input Bus2IP_RNW,
input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data,
input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE,
input [C_NUM_REG-1 : 0] Bus2IP_RdCE,
input [C_NUM_REG-1 : 0] Bus2IP_WrCE,
output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data,
output IP2Bus_RdAck,
output IP2Bus_WrAck,
output IP2Bus_Error
);
reg sig;
always @ (posedge Bus2IP_Clk, negedge Bus2IP_Resetn)
if (!Bus2IP_Resetn)
sig <= 1'b0;
else
sig <= pcie_mmcm_lock;
assign IP2Bus_Data = sig;
assign IP2Bus_WrAck = 1'b1;
assign IP2Bus_RdAck = 1'b1;
assign IP2Bus_Error = 0;
endmodule | module user_logic
#
(
parameter C_NUM_REG = 1,
parameter C_SLV_DWIDTH = 32
)
(
input pcie_mmcm_lock,
input Bus2IP_Clk,
input Bus2IP_Resetn,
input [0 : 31] Bus2IP_Addr,
input Bus2IP_CS,
input Bus2IP_RNW,
input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data,
input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE,
input [C_NUM_REG-1 : 0] Bus2IP_RdCE,
input [C_NUM_REG-1 : 0] Bus2IP_WrCE,
output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data,
output IP2Bus_RdAck,
output IP2Bus_WrAck,
output IP2Bus_Error
); |
reg sig;
always @ (posedge Bus2IP_Clk, negedge Bus2IP_Resetn)
if (!Bus2IP_Resetn)
sig <= 1'b0;
else
sig <= pcie_mmcm_lock;
assign IP2Bus_Data = sig;
assign IP2Bus_WrAck = 1'b1;
assign IP2Bus_RdAck = 1'b1;
assign IP2Bus_Error = 0;
endmodule | 25 |
137,302 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v | 77,907,036 | performance_ch_prog_counter.v | v | 170 | 137 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbc in position 875: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v:1: Cannot find include file: p_parameter.vh\n`include "p_parameter.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.sv\n p_parameter.vh\n p_parameter.vh.v\n p_parameter.vh.sv\n obj_dir/p_parameter.vh\n obj_dir/p_parameter.vh.v\n obj_dir/p_parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v:10: Define or directive not defined: \'`SLV_DATA_WD\'\n input wire [`SLV_DATA_WD-1:0] i_config,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v:12: Define or directive not defined: \'`SLV_DATA_WD\'\n output wire [`SLV_DATA_WD-1:0] o_prog_cnt,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v:16: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v:17: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_end,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v:18: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_op_fail, \n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_ch_prog_counter.v:26: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_config;\n ^~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n' | 295,877 | module | module performance_ch_prog_counter
(
input wire i_bus_clk,
input wire i_bus_rst,
input wire [`SLV_DATA_WD-1:0] i_config,
input wire i_prog_cnt_cp_cmplt,
output wire [`SLV_DATA_WD-1:0] o_prog_cnt,
output wire [9:0] o_prog_req_cnt,
input wire [`WAY-1:0] i_prog_start,
input wire [`WAY-1:0] i_prog_end,
input wire [`WAY-1:0] i_op_fail,
output reg o_prog_ready
);
wire [`SLV_DATA_WD-1:0] w_config;
wire w_prog_start;
wire w_prog_end;
assign w_prog_start = |{i_prog_start};
assign w_prog_end = |{i_prog_end };
reg [31:0] r_prog_cnt;
reg [31:0] r_prog_cnt_sum;
reg r_prog_sum_end;
reg r_prog_sum_end_ack_1;
reg r_prog_sum_end_ack_2;
wire [9:0] w_prog_config;
reg [9:0] r_prog_req_cnt;
reg r_prog_end;
reg r_prog_end_ack;
reg [1:0] r_prog_cur_state;
reg [1:0] r_prog_next_state;
parameter PROG_IDLE = 2'b00;
parameter PROG_REQ_CNT = 2'b01;
parameter CP_CMPLT = 2'b11;
parameter PROG_SUM_END = 2'b10;
assign w_config = i_config;
assign w_prog_config = w_config[31:22];
assign o_prog_cnt = r_prog_cnt_sum;
assign o_prog_req_cnt = r_prog_req_cnt;
always @ (posedge i_bus_clk)
begin
r_prog_end <= w_prog_end;
r_prog_end_ack <= ~w_prog_end & r_prog_end;
end
always @ (posedge i_bus_clk)
begin
r_prog_sum_end_ack_1 <= r_prog_sum_end;
r_prog_sum_end_ack_2 <= ~r_prog_sum_end & r_prog_sum_end_ack_1;
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst)
begin
r_prog_cnt <= 'b0;
end
else
begin
if (w_prog_start && w_prog_end) r_prog_cnt <= 'b0;
else if(w_prog_start) r_prog_cnt <= r_prog_cnt + 'b1;
else if(w_prog_end) r_prog_cnt <= r_prog_cnt;
else if(r_prog_end_ack) r_prog_cnt <= 'b0;
else r_prog_cnt <= r_prog_cnt;
end
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) r_prog_cnt_sum <= 'b0;
else
begin
if(w_prog_start && w_prog_end) r_prog_cnt_sum <= r_prog_cnt + r_prog_cnt_sum;
else if(w_prog_end) r_prog_cnt_sum <= (i_op_fail) ? r_prog_cnt_sum : r_prog_cnt + r_prog_cnt_sum;
else if(r_prog_sum_end_ack_2) r_prog_cnt_sum <= 'b0;
else r_prog_cnt_sum <= r_prog_cnt_sum;
end
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) r_prog_req_cnt <= 'b0;
else if(w_prog_end) r_prog_req_cnt <= (i_op_fail) ? r_prog_req_cnt : r_prog_req_cnt + 'b1;
else if (r_prog_sum_end_ack_2) r_prog_req_cnt <= 'b0;
else r_prog_req_cnt <= r_prog_req_cnt;
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) r_prog_cur_state <= PROG_IDLE;
else r_prog_cur_state <= r_prog_next_state;
end
always @ (*)
begin
case(r_prog_cur_state)
PROG_IDLE:
begin
r_prog_next_state <= (w_prog_start) ? PROG_REQ_CNT : PROG_IDLE;
r_prog_sum_end <= 'b0;
end
PROG_REQ_CNT:
begin
r_prog_next_state <= (r_prog_req_cnt == w_prog_config) ? CP_CMPLT : (i_prog_cnt_cp_cmplt) ? PROG_SUM_END : PROG_REQ_CNT;
r_prog_sum_end <= 'b0;
end
CP_CMPLT:
begin
r_prog_next_state <= (i_prog_cnt_cp_cmplt) ? PROG_SUM_END : CP_CMPLT;
r_prog_sum_end <= 'b0;
end
PROG_SUM_END:
begin
r_prog_next_state <= PROG_IDLE;
r_prog_sum_end <= 'b1;
end
default:
begin
r_prog_next_state <= PROG_IDLE;
r_prog_sum_end <= 'b0;
end
endcase
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) o_prog_ready <= 'b0;
else
begin
case(r_prog_cur_state)
CP_CMPLT : o_prog_ready <= 'b1;
default: o_prog_ready <= 'b0;
endcase
end
end
endmodule | module performance_ch_prog_counter
(
input wire i_bus_clk,
input wire i_bus_rst,
input wire [`SLV_DATA_WD-1:0] i_config,
input wire i_prog_cnt_cp_cmplt,
output wire [`SLV_DATA_WD-1:0] o_prog_cnt,
output wire [9:0] o_prog_req_cnt,
input wire [`WAY-1:0] i_prog_start,
input wire [`WAY-1:0] i_prog_end,
input wire [`WAY-1:0] i_op_fail,
output reg o_prog_ready
); |
wire [`SLV_DATA_WD-1:0] w_config;
wire w_prog_start;
wire w_prog_end;
assign w_prog_start = |{i_prog_start};
assign w_prog_end = |{i_prog_end };
reg [31:0] r_prog_cnt;
reg [31:0] r_prog_cnt_sum;
reg r_prog_sum_end;
reg r_prog_sum_end_ack_1;
reg r_prog_sum_end_ack_2;
wire [9:0] w_prog_config;
reg [9:0] r_prog_req_cnt;
reg r_prog_end;
reg r_prog_end_ack;
reg [1:0] r_prog_cur_state;
reg [1:0] r_prog_next_state;
parameter PROG_IDLE = 2'b00;
parameter PROG_REQ_CNT = 2'b01;
parameter CP_CMPLT = 2'b11;
parameter PROG_SUM_END = 2'b10;
assign w_config = i_config;
assign w_prog_config = w_config[31:22];
assign o_prog_cnt = r_prog_cnt_sum;
assign o_prog_req_cnt = r_prog_req_cnt;
always @ (posedge i_bus_clk)
begin
r_prog_end <= w_prog_end;
r_prog_end_ack <= ~w_prog_end & r_prog_end;
end
always @ (posedge i_bus_clk)
begin
r_prog_sum_end_ack_1 <= r_prog_sum_end;
r_prog_sum_end_ack_2 <= ~r_prog_sum_end & r_prog_sum_end_ack_1;
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst)
begin
r_prog_cnt <= 'b0;
end
else
begin
if (w_prog_start && w_prog_end) r_prog_cnt <= 'b0;
else if(w_prog_start) r_prog_cnt <= r_prog_cnt + 'b1;
else if(w_prog_end) r_prog_cnt <= r_prog_cnt;
else if(r_prog_end_ack) r_prog_cnt <= 'b0;
else r_prog_cnt <= r_prog_cnt;
end
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) r_prog_cnt_sum <= 'b0;
else
begin
if(w_prog_start && w_prog_end) r_prog_cnt_sum <= r_prog_cnt + r_prog_cnt_sum;
else if(w_prog_end) r_prog_cnt_sum <= (i_op_fail) ? r_prog_cnt_sum : r_prog_cnt + r_prog_cnt_sum;
else if(r_prog_sum_end_ack_2) r_prog_cnt_sum <= 'b0;
else r_prog_cnt_sum <= r_prog_cnt_sum;
end
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) r_prog_req_cnt <= 'b0;
else if(w_prog_end) r_prog_req_cnt <= (i_op_fail) ? r_prog_req_cnt : r_prog_req_cnt + 'b1;
else if (r_prog_sum_end_ack_2) r_prog_req_cnt <= 'b0;
else r_prog_req_cnt <= r_prog_req_cnt;
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) r_prog_cur_state <= PROG_IDLE;
else r_prog_cur_state <= r_prog_next_state;
end
always @ (*)
begin
case(r_prog_cur_state)
PROG_IDLE:
begin
r_prog_next_state <= (w_prog_start) ? PROG_REQ_CNT : PROG_IDLE;
r_prog_sum_end <= 'b0;
end
PROG_REQ_CNT:
begin
r_prog_next_state <= (r_prog_req_cnt == w_prog_config) ? CP_CMPLT : (i_prog_cnt_cp_cmplt) ? PROG_SUM_END : PROG_REQ_CNT;
r_prog_sum_end <= 'b0;
end
CP_CMPLT:
begin
r_prog_next_state <= (i_prog_cnt_cp_cmplt) ? PROG_SUM_END : CP_CMPLT;
r_prog_sum_end <= 'b0;
end
PROG_SUM_END:
begin
r_prog_next_state <= PROG_IDLE;
r_prog_sum_end <= 'b1;
end
default:
begin
r_prog_next_state <= PROG_IDLE;
r_prog_sum_end <= 'b0;
end
endcase
end
always @ (posedge i_bus_clk or posedge i_bus_rst)
begin
if(i_bus_rst) o_prog_ready <= 'b0;
else
begin
case(r_prog_cur_state)
CP_CMPLT : o_prog_ready <= 'b1;
default: o_prog_ready <= 'b0;
endcase
end
end
endmodule | 25 |
137,304 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v | 77,907,036 | performance_monitor_reg.v | v | 467 | 199 | [] | [] | [] | [(39, 502)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:1: Cannot find include file: p_parameter.vh\n`include "p_parameter.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.sv\n p_parameter.vh\n p_parameter.vh.v\n p_parameter.vh.sv\n obj_dir/p_parameter.vh\n obj_dir/p_parameter.vh.v\n obj_dir/p_parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:10: Define or directive not defined: \'`SLV_DATA_WD\'\n input wire [`SLV_DATA_WD-1:0] i_slv_data,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:11: Define or directive not defined: \'`SLV_DATA_WD\'\n output reg [`SLV_DATA_WD-1:0] o_slv_data,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:12: Define or directive not defined: \'`SLV_ADDR_WD\'\n input wire [`SLV_ADDR_WD-1:0] i_slv_addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:20: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:21: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_end,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:22: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_read_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:23: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_read_end,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:24: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_erase_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:25: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_erase_end,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:26: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_op_fail\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:30: Define or directive not defined: \'`SLV_DATA_WD\'\n reg [`SLV_DATA_WD-1:0] r_ch_monitor_confi ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:31: Define or directive not defined: \'`SLV_DATA_WD\'\n reg [`SLV_DATA_WD-1:0] r_way_monitor_confi ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:32: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_way_monitor_status;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:33: Define or directive not defined: \'`SLV_DATA_WD\'\n reg [`SLV_DATA_WD-1:0] r_reserved ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:36: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_req_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:37: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_monitor_status;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:39: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_prog_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:44: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_read_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:49: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_erase_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:55: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:55: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:55: Define or directive not defined: \'`WAY\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:56: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:56: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:56: Define or directive not defined: \'`WAY\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:57: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:57: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:57: Define or directive not defined: \'`WAY\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:110: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_req_cnt [0:7];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:116: Define or directive not defined: \'`WAY\'\n wire [`WAY-1:0] w_prog_ready;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:117: Define or directive not defined: \'`WAY\'\n wire [`WAY-1:0] w_read_ready;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:118: Define or directive not defined: \'`WAY\'\n wire [`WAY-1:0] w_erase_ready;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:385: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:385: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for(i=0;i<`WAY;i=i+1)\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:392: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:399: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:407: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_prog_cnt (w_prog_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:407: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_prog_cnt (w_prog_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:418: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:426: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_read_cnt (w_read_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:426: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_read_cnt (w_read_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:437: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:445: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_erase_cnt (w_erase_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:445: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_erase_cnt (w_erase_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:460: syntax error, unexpected \'=\', expecting IDENTIFIER\n clogb2 = 0;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:462: syntax error, unexpected \'=\', expecting IDENTIFIER\n clogb2 = i + 1;\n ^\n%Error: Cannot continue\n' | 295,882 | module | module performance_monitor_reg
(
input wire i_bus_clk,
input wire i_bus_rstn,
input wire [`SLV_DATA_WD-1:0] i_slv_data,
output reg [`SLV_DATA_WD-1:0] o_slv_data,
input wire [`SLV_ADDR_WD-1:0] i_slv_addr,
input wire i_slv_rnw,
output wire o_slv_write_ack,
output reg o_slv_read_ack,
input wire i_slv_wr_ack,
input wire i_slv_rd_ack,
input wire [`WAY-1:0] i_prog_start,
input wire [`WAY-1:0] i_prog_end,
input wire [`WAY-1:0] i_read_start,
input wire [`WAY-1:0] i_read_end,
input wire [`WAY-1:0] i_erase_start,
input wire [`WAY-1:0] i_erase_end,
input wire [`WAY-1:0] i_op_fail
);
reg [`SLV_DATA_WD-1:0] r_ch_monitor_confi ;
reg [`SLV_DATA_WD-1:0] r_way_monitor_confi ;
wire [`SLV_DATA_WD-1:0] w_way_monitor_status;
reg [`SLV_DATA_WD-1:0] r_reserved ;
wire [`SLV_DATA_WD-1:0] w_ch_req_cnt;
wire [`SLV_DATA_WD-1:0] w_ch_monitor_status;
wire [`SLV_DATA_WD-1:0] w_ch_prog_cnt;
wire [9:0] w_ch_prog_req_cnt;
wire w_ch_prog_ready;
reg r_ch_prog_cnt_cp_cmplt;
wire [`SLV_DATA_WD-1:0] w_ch_read_cnt;
wire [11:0] w_ch_read_req_cnt;
wire w_ch_read_ready;
reg r_ch_read_cnt_cp_cmplt;
wire [`SLV_DATA_WD-1:0] w_ch_erase_cnt;
wire [9:0] w_ch_erase_req_cnt;
wire w_ch_erase_ready;
reg r_ch_erase_cnt_cp_cmplt;
wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;
wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;
wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;
`ifdef WAY8
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
wire [`SLV_DATA_WD-1:0] w1_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w1_read_cnt ;
wire [`SLV_DATA_WD-1:0] w1_erase_cnt;
wire [`SLV_DATA_WD-1:0] w2_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w2_read_cnt ;
wire [`SLV_DATA_WD-1:0] w2_erase_cnt;
wire [`SLV_DATA_WD-1:0] w3_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w3_read_cnt ;
wire [`SLV_DATA_WD-1:0] w3_erase_cnt;
wire [`SLV_DATA_WD-1:0] w4_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w4_read_cnt ;
wire [`SLV_DATA_WD-1:0] w4_erase_cnt;
wire [`SLV_DATA_WD-1:0] w5_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w5_read_cnt ;
wire [`SLV_DATA_WD-1:0] w5_erase_cnt;
wire [`SLV_DATA_WD-1:0] w6_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w6_read_cnt ;
wire [`SLV_DATA_WD-1:0] w6_erase_cnt;
wire [`SLV_DATA_WD-1:0] w7_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w7_read_cnt ;
wire [`SLV_DATA_WD-1:0] w7_erase_cnt;
`else `ifdef WAY4
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
wire [`SLV_DATA_WD-1:0] w1_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w1_read_cnt ;
wire [`SLV_DATA_WD-1:0] w1_erase_cnt;
wire [`SLV_DATA_WD-1:0] w2_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w2_read_cnt ;
wire [`SLV_DATA_WD-1:0] w2_erase_cnt;
wire [`SLV_DATA_WD-1:0] w3_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w3_read_cnt ;
wire [`SLV_DATA_WD-1:0] w3_erase_cnt;
`else `ifdef WAY2
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
wire [`SLV_DATA_WD-1:0] w1_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w1_read_cnt ;
wire [`SLV_DATA_WD-1:0] w1_erase_cnt;
`else `ifdef WAY1
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
`endif `endif `endif `endif
wire [`SLV_DATA_WD-1:0] w_req_cnt [0:7];
wire [9:0] w_prog_req_cnt [0:7];
wire [11:0] w_read_req_cnt [0:7];
wire [9:0] w_erase_req_cnt[0:7];
wire [`WAY-1:0] w_prog_ready;
wire [`WAY-1:0] w_read_ready;
wire [`WAY-1:0] w_erase_ready;
reg [7:0] r_prog_cnt_cp_cmplt;
reg [7:0] r_read_cnt_cp_cmplt;
reg [7:0] r_erase_cnt_cp_cmplt;
assign o_slv_write_ack = i_slv_wr_ack;
always @ (posedge i_bus_clk)
begin
o_slv_read_ack <= i_slv_rd_ack;
end
always @ (posedge i_bus_clk or negedge i_bus_rstn)
begin
if(!i_bus_rstn)
begin
r_way_monitor_confi <= 'b0;
r_reserved <= 'b0;
end
else
begin
if(i_slv_wr_ack)
begin
case(i_slv_addr[7:0])
8'h0_0: r_ch_monitor_confi <= i_slv_data;
8'h0_4: r_way_monitor_confi <= i_slv_data;
8'h0_8: r_reserved <= i_slv_data;
8'h0_c: r_reserved <= i_slv_data;
default: ;
endcase
end
end
end
always @ (posedge i_bus_clk)
begin
if(i_slv_rd_ack)
case(i_slv_addr[7:0])
8'h0_0: o_slv_data <= r_ch_monitor_confi;
8'h0_4: o_slv_data <= r_way_monitor_confi;
8'h0_8: o_slv_data <= w_ch_monitor_status;
8'h0_c: o_slv_data <= w_way_monitor_status;
`ifdef WAY8
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
8'h2_0: o_slv_data <= w1_prog_cnt ;
8'h2_4: o_slv_data <= w1_read_cnt ;
8'h2_8: o_slv_data <= w1_erase_cnt;
8'h2_c: o_slv_data <= r_reserved;
8'h3_0: o_slv_data <= w2_prog_cnt ;
8'h3_4: o_slv_data <= w2_read_cnt ;
8'h3_8: o_slv_data <= w2_erase_cnt;
8'h3_c: o_slv_data <= r_reserved;
8'h4_0: o_slv_data <= w3_prog_cnt ;
8'h4_4: o_slv_data <= w3_read_cnt ;
8'h4_8: o_slv_data <= w3_erase_cnt;
8'h4_c: o_slv_data <= r_reserved;
8'h5_0: o_slv_data <= w4_prog_cnt ;
8'h5_4: o_slv_data <= w4_read_cnt ;
8'h5_8: o_slv_data <= w4_erase_cnt;
8'h5_c: o_slv_data <= r_reserved;
8'h6_0: o_slv_data <= w5_prog_cnt ;
8'h6_4: o_slv_data <= w5_read_cnt ;
8'h6_8: o_slv_data <= w5_erase_cnt;
8'h6_c: o_slv_data <= r_reserved;
8'h7_0: o_slv_data <= w6_prog_cnt ;
8'h7_4: o_slv_data <= w6_read_cnt ;
8'h7_8: o_slv_data <= w6_erase_cnt;
8'h7_c: o_slv_data <= r_reserved;
8'h8_0: o_slv_data <= w7_prog_cnt ;
8'h8_4: o_slv_data <= w7_read_cnt ;
8'h8_8: o_slv_data <= w7_erase_cnt;
8'h8_c: o_slv_data <= r_reserved;
8'h9_0: o_slv_data <= w_req_cnt[0];
8'h9_4: o_slv_data <= w_req_cnt[1];
8'h9_8: o_slv_data <= w_req_cnt[2];
8'h9_c: o_slv_data <= w_req_cnt[3];
8'ha_0: o_slv_data <= w_req_cnt[4];
8'ha_4: o_slv_data <= w_req_cnt[5];
8'ha_8: o_slv_data <= w_req_cnt[6];
8'ha_c: o_slv_data <= w_req_cnt[7];
8'hb_0: o_slv_data <= w_ch_prog_cnt;
8'hb_4: o_slv_data <= w_ch_read_cnt;
8'hb_8: o_slv_data <= w_ch_erase_cnt;
8'hb_c: o_slv_data <= r_reserved;
8'hc_0: o_slv_data <= w_ch_req_cnt;
8'hc_4: o_slv_data <= r_reserved;
8'hc_8: o_slv_data <= r_reserved;
8'hc_c: o_slv_data <= r_reserved;
8'hd_0: o_slv_data <= r_reserved;
8'hd_4: o_slv_data <= r_reserved;
8'hd_8: o_slv_data <= r_reserved;
8'hd_c: o_slv_data <= r_reserved;
8'he_0: o_slv_data <= r_reserved;
8'he_4: o_slv_data <= r_reserved;
8'he_8: o_slv_data <= r_reserved;
8'he_c: o_slv_data <= r_reserved;
8'hf_0: o_slv_data <= r_reserved;
8'hf_4: o_slv_data <= r_reserved;
8'hf_8: o_slv_data <= r_reserved;
8'hf_c: o_slv_data <= r_reserved;
`else `ifdef WAY4
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
8'h2_0: o_slv_data <= w1_prog_cnt ;
8'h2_4: o_slv_data <= w1_read_cnt ;
8'h2_8: o_slv_data <= w1_erase_cnt;
8'h2_c: o_slv_data <= r_reserved;
8'h3_0: o_slv_data <= w2_prog_cnt ;
8'h3_4: o_slv_data <= w2_read_cnt ;
8'h3_8: o_slv_data <= w2_erase_cnt;
8'h3_c: o_slv_data <= r_reserved;
8'h4_0: o_slv_data <= w3_prog_cnt ;
8'h4_4: o_slv_data <= w3_read_cnt ;
8'h4_8: o_slv_data <= w3_erase_cnt;
8'h4_c: o_slv_data <= r_reserved;
`else `ifdef WAY2
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
8'h2_0: o_slv_data <= w1_prog_cnt ;
8'h2_4: o_slv_data <= w1_read_cnt ;
8'h2_8: o_slv_data <= w1_erase_cnt;
8'h2_c: o_slv_data <= r_reserved;
`else `ifdef WAY1
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
`endif `endif `endif `endif
default: o_slv_data <= 'b0;
endcase
end
always @ (posedge i_bus_clk)
begin
r_prog_cnt_cp_cmplt[0] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[1] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[2] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[3] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[4] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[5] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[6] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[7] <= i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
always @ (posedge i_bus_clk)
begin
r_read_cnt_cp_cmplt[0] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[1] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[2] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[3] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[4] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[5] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[6] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[7] <= i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
always @ (posedge i_bus_clk)
begin
r_erase_cnt_cp_cmplt[0] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & (!i_slv_addr[5]) & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[1] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[2] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[3] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[4] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[5] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[6] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[7] <= i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & (!i_slv_addr[5]) & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
always @ (posedge i_bus_clk)
begin
r_ch_prog_cnt_cp_cmplt = i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_ch_read_cnt_cp_cmplt = i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_ch_erase_cnt_cp_cmplt = i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
assign w0_prog_cnt = w_prog_cnt[31:0] ;
assign w0_read_cnt = w_read_cnt[31:0] ;
assign w0_erase_cnt = w_erase_cnt[31:0];
assign w1_prog_cnt = w_prog_cnt[63:32] ;
assign w1_read_cnt = w_read_cnt[63:32] ;
assign w1_erase_cnt = w_erase_cnt[63:32];
assign w2_prog_cnt = w_prog_cnt[95:64] ;
assign w2_read_cnt = w_read_cnt[95:64] ;
assign w2_erase_cnt = w_erase_cnt[95:64];
assign w3_prog_cnt = w_prog_cnt[127:96] ;
assign w3_read_cnt = w_read_cnt[127:96] ;
assign w3_erase_cnt = w_erase_cnt[127:96];
assign w4_prog_cnt = w_prog_cnt[159:128] ;
assign w4_read_cnt = w_read_cnt[159:128] ;
assign w4_erase_cnt = w_erase_cnt[159:128];
assign w5_prog_cnt = w_prog_cnt[191:160] ;
assign w5_read_cnt = w_read_cnt[191:160] ;
assign w5_erase_cnt = w_erase_cnt[191:160];
assign w6_prog_cnt = w_prog_cnt[223:192] ;
assign w6_read_cnt = w_read_cnt[223:192] ;
assign w6_erase_cnt = w_erase_cnt[223:192];
assign w7_prog_cnt = w_prog_cnt[255:224] ;
assign w7_read_cnt = w_read_cnt[255:224] ;
assign w7_erase_cnt = w_erase_cnt[255:224];
assign w_ch_req_cnt = {w_ch_prog_req_cnt, w_ch_read_req_cnt, w_ch_erase_req_cnt};
assign w_ch_monitor_status = {w_ch_prog_ready, w_ch_read_ready, w_ch_erase_ready};
performance_ch_prog_counter performance_ch_prog_counter0(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_ch_monitor_confi),
.i_prog_cnt_cp_cmplt(r_ch_prog_cnt_cp_cmplt),
.o_prog_cnt (w_ch_prog_cnt),
.o_prog_req_cnt (w_ch_prog_req_cnt),
.i_prog_start (i_prog_start),
.i_prog_end (i_prog_end),
.i_op_fail (i_op_fail),
.o_prog_ready (w_ch_prog_ready)
);
performance_ch_read_counter performance_ch_read_counter0(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_ch_monitor_confi),
.i_read_cnt_cp_cmplt(r_ch_read_cnt_cp_cmplt),
.o_read_cnt (w_ch_read_cnt),
.o_read_req_cnt (w_ch_read_req_cnt),
.i_read_start (i_read_start),
.i_read_end (i_read_end),
.i_op_fail (i_op_fail),
.o_read_ready (w_ch_read_ready)
);
performance_ch_erase_counter performance_ch_erase_counter0(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_ch_monitor_confi),
.i_erase_cnt_cp_cmplt(r_ch_erase_cnt_cp_cmplt),
.o_erase_cnt (w_ch_erase_cnt),
.o_erase_req_cnt (w_ch_erase_req_cnt),
.i_erase_start (i_erase_start),
.i_erase_end (i_erase_end),
.i_op_fail (i_op_fail),
.o_erase_ready (w_ch_erase_ready)
);
genvar i;
generate
for(i=0;i<`WAY;i=i+1)
begin : performance_status
assign w_way_monitor_status[(i+1)*4-1:i*4] = {w_prog_ready[i], w_read_ready[i], w_erase_ready[i], 1'b0};
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : req_cnt
assign w_req_cnt[i] = {w_prog_req_cnt[i], w_read_req_cnt[i], w_erase_req_cnt[i]};
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : prog_monitoring_module_generate
performance_counter_prog prog_counter(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_way_monitor_confi),
.i_prog_cnt_cp_cmplt (r_prog_cnt_cp_cmplt[i]),
.o_prog_cnt (w_prog_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.o_prog_req_cnt (w_prog_req_cnt[i]),
.i_prog_start (i_prog_start[i]),
.i_prog_end (i_prog_end[i]),
.i_op_fail (i_op_fail[i]),
.o_prog_ready (w_prog_ready[i])
);
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : read_monitoring_module_generate
performance_counter_read read_counter(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_way_monitor_confi),
.i_read_cnt_cp_cmplt (r_read_cnt_cp_cmplt[i]),
.o_read_cnt (w_read_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.o_read_req_cnt (w_read_req_cnt[i]),
.i_read_start (i_read_start[i]),
.i_read_end (i_read_end[i]),
.i_op_fail (i_op_fail[i]),
.o_read_ready (w_read_ready[i])
);
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : erase_monitoring_module_generate
performance_counter_erase erase_counter(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_way_monitor_confi),
.i_erase_cnt_cp_cmplt (r_erase_cnt_cp_cmplt[i]),
.o_erase_cnt (w_erase_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.o_erase_req_cnt (w_erase_req_cnt[i]),
.i_erase_start (i_erase_start[i]),
.i_erase_end (i_erase_end[i]),
.i_op_fail (i_op_fail[i]),
.o_erase_ready (w_erase_ready[i])
);
end
endgenerate
function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
endmodule | module performance_monitor_reg
(
input wire i_bus_clk,
input wire i_bus_rstn,
input wire [`SLV_DATA_WD-1:0] i_slv_data,
output reg [`SLV_DATA_WD-1:0] o_slv_data,
input wire [`SLV_ADDR_WD-1:0] i_slv_addr,
input wire i_slv_rnw,
output wire o_slv_write_ack,
output reg o_slv_read_ack,
input wire i_slv_wr_ack,
input wire i_slv_rd_ack,
input wire [`WAY-1:0] i_prog_start,
input wire [`WAY-1:0] i_prog_end,
input wire [`WAY-1:0] i_read_start,
input wire [`WAY-1:0] i_read_end,
input wire [`WAY-1:0] i_erase_start,
input wire [`WAY-1:0] i_erase_end,
input wire [`WAY-1:0] i_op_fail
); |
reg [`SLV_DATA_WD-1:0] r_ch_monitor_confi ;
reg [`SLV_DATA_WD-1:0] r_way_monitor_confi ;
wire [`SLV_DATA_WD-1:0] w_way_monitor_status;
reg [`SLV_DATA_WD-1:0] r_reserved ;
wire [`SLV_DATA_WD-1:0] w_ch_req_cnt;
wire [`SLV_DATA_WD-1:0] w_ch_monitor_status;
wire [`SLV_DATA_WD-1:0] w_ch_prog_cnt;
wire [9:0] w_ch_prog_req_cnt;
wire w_ch_prog_ready;
reg r_ch_prog_cnt_cp_cmplt;
wire [`SLV_DATA_WD-1:0] w_ch_read_cnt;
wire [11:0] w_ch_read_req_cnt;
wire w_ch_read_ready;
reg r_ch_read_cnt_cp_cmplt;
wire [`SLV_DATA_WD-1:0] w_ch_erase_cnt;
wire [9:0] w_ch_erase_req_cnt;
wire w_ch_erase_ready;
reg r_ch_erase_cnt_cp_cmplt;
wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;
wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;
wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;
`ifdef WAY8
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
wire [`SLV_DATA_WD-1:0] w1_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w1_read_cnt ;
wire [`SLV_DATA_WD-1:0] w1_erase_cnt;
wire [`SLV_DATA_WD-1:0] w2_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w2_read_cnt ;
wire [`SLV_DATA_WD-1:0] w2_erase_cnt;
wire [`SLV_DATA_WD-1:0] w3_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w3_read_cnt ;
wire [`SLV_DATA_WD-1:0] w3_erase_cnt;
wire [`SLV_DATA_WD-1:0] w4_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w4_read_cnt ;
wire [`SLV_DATA_WD-1:0] w4_erase_cnt;
wire [`SLV_DATA_WD-1:0] w5_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w5_read_cnt ;
wire [`SLV_DATA_WD-1:0] w5_erase_cnt;
wire [`SLV_DATA_WD-1:0] w6_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w6_read_cnt ;
wire [`SLV_DATA_WD-1:0] w6_erase_cnt;
wire [`SLV_DATA_WD-1:0] w7_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w7_read_cnt ;
wire [`SLV_DATA_WD-1:0] w7_erase_cnt;
`else `ifdef WAY4
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
wire [`SLV_DATA_WD-1:0] w1_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w1_read_cnt ;
wire [`SLV_DATA_WD-1:0] w1_erase_cnt;
wire [`SLV_DATA_WD-1:0] w2_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w2_read_cnt ;
wire [`SLV_DATA_WD-1:0] w2_erase_cnt;
wire [`SLV_DATA_WD-1:0] w3_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w3_read_cnt ;
wire [`SLV_DATA_WD-1:0] w3_erase_cnt;
`else `ifdef WAY2
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
wire [`SLV_DATA_WD-1:0] w1_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w1_read_cnt ;
wire [`SLV_DATA_WD-1:0] w1_erase_cnt;
`else `ifdef WAY1
wire [`SLV_DATA_WD-1:0] w0_prog_cnt ;
wire [`SLV_DATA_WD-1:0] w0_read_cnt ;
wire [`SLV_DATA_WD-1:0] w0_erase_cnt;
`endif `endif `endif `endif
wire [`SLV_DATA_WD-1:0] w_req_cnt [0:7];
wire [9:0] w_prog_req_cnt [0:7];
wire [11:0] w_read_req_cnt [0:7];
wire [9:0] w_erase_req_cnt[0:7];
wire [`WAY-1:0] w_prog_ready;
wire [`WAY-1:0] w_read_ready;
wire [`WAY-1:0] w_erase_ready;
reg [7:0] r_prog_cnt_cp_cmplt;
reg [7:0] r_read_cnt_cp_cmplt;
reg [7:0] r_erase_cnt_cp_cmplt;
assign o_slv_write_ack = i_slv_wr_ack;
always @ (posedge i_bus_clk)
begin
o_slv_read_ack <= i_slv_rd_ack;
end
always @ (posedge i_bus_clk or negedge i_bus_rstn)
begin
if(!i_bus_rstn)
begin
r_way_monitor_confi <= 'b0;
r_reserved <= 'b0;
end
else
begin
if(i_slv_wr_ack)
begin
case(i_slv_addr[7:0])
8'h0_0: r_ch_monitor_confi <= i_slv_data;
8'h0_4: r_way_monitor_confi <= i_slv_data;
8'h0_8: r_reserved <= i_slv_data;
8'h0_c: r_reserved <= i_slv_data;
default: ;
endcase
end
end
end
always @ (posedge i_bus_clk)
begin
if(i_slv_rd_ack)
case(i_slv_addr[7:0])
8'h0_0: o_slv_data <= r_ch_monitor_confi;
8'h0_4: o_slv_data <= r_way_monitor_confi;
8'h0_8: o_slv_data <= w_ch_monitor_status;
8'h0_c: o_slv_data <= w_way_monitor_status;
`ifdef WAY8
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
8'h2_0: o_slv_data <= w1_prog_cnt ;
8'h2_4: o_slv_data <= w1_read_cnt ;
8'h2_8: o_slv_data <= w1_erase_cnt;
8'h2_c: o_slv_data <= r_reserved;
8'h3_0: o_slv_data <= w2_prog_cnt ;
8'h3_4: o_slv_data <= w2_read_cnt ;
8'h3_8: o_slv_data <= w2_erase_cnt;
8'h3_c: o_slv_data <= r_reserved;
8'h4_0: o_slv_data <= w3_prog_cnt ;
8'h4_4: o_slv_data <= w3_read_cnt ;
8'h4_8: o_slv_data <= w3_erase_cnt;
8'h4_c: o_slv_data <= r_reserved;
8'h5_0: o_slv_data <= w4_prog_cnt ;
8'h5_4: o_slv_data <= w4_read_cnt ;
8'h5_8: o_slv_data <= w4_erase_cnt;
8'h5_c: o_slv_data <= r_reserved;
8'h6_0: o_slv_data <= w5_prog_cnt ;
8'h6_4: o_slv_data <= w5_read_cnt ;
8'h6_8: o_slv_data <= w5_erase_cnt;
8'h6_c: o_slv_data <= r_reserved;
8'h7_0: o_slv_data <= w6_prog_cnt ;
8'h7_4: o_slv_data <= w6_read_cnt ;
8'h7_8: o_slv_data <= w6_erase_cnt;
8'h7_c: o_slv_data <= r_reserved;
8'h8_0: o_slv_data <= w7_prog_cnt ;
8'h8_4: o_slv_data <= w7_read_cnt ;
8'h8_8: o_slv_data <= w7_erase_cnt;
8'h8_c: o_slv_data <= r_reserved;
8'h9_0: o_slv_data <= w_req_cnt[0];
8'h9_4: o_slv_data <= w_req_cnt[1];
8'h9_8: o_slv_data <= w_req_cnt[2];
8'h9_c: o_slv_data <= w_req_cnt[3];
8'ha_0: o_slv_data <= w_req_cnt[4];
8'ha_4: o_slv_data <= w_req_cnt[5];
8'ha_8: o_slv_data <= w_req_cnt[6];
8'ha_c: o_slv_data <= w_req_cnt[7];
8'hb_0: o_slv_data <= w_ch_prog_cnt;
8'hb_4: o_slv_data <= w_ch_read_cnt;
8'hb_8: o_slv_data <= w_ch_erase_cnt;
8'hb_c: o_slv_data <= r_reserved;
8'hc_0: o_slv_data <= w_ch_req_cnt;
8'hc_4: o_slv_data <= r_reserved;
8'hc_8: o_slv_data <= r_reserved;
8'hc_c: o_slv_data <= r_reserved;
8'hd_0: o_slv_data <= r_reserved;
8'hd_4: o_slv_data <= r_reserved;
8'hd_8: o_slv_data <= r_reserved;
8'hd_c: o_slv_data <= r_reserved;
8'he_0: o_slv_data <= r_reserved;
8'he_4: o_slv_data <= r_reserved;
8'he_8: o_slv_data <= r_reserved;
8'he_c: o_slv_data <= r_reserved;
8'hf_0: o_slv_data <= r_reserved;
8'hf_4: o_slv_data <= r_reserved;
8'hf_8: o_slv_data <= r_reserved;
8'hf_c: o_slv_data <= r_reserved;
`else `ifdef WAY4
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
8'h2_0: o_slv_data <= w1_prog_cnt ;
8'h2_4: o_slv_data <= w1_read_cnt ;
8'h2_8: o_slv_data <= w1_erase_cnt;
8'h2_c: o_slv_data <= r_reserved;
8'h3_0: o_slv_data <= w2_prog_cnt ;
8'h3_4: o_slv_data <= w2_read_cnt ;
8'h3_8: o_slv_data <= w2_erase_cnt;
8'h3_c: o_slv_data <= r_reserved;
8'h4_0: o_slv_data <= w3_prog_cnt ;
8'h4_4: o_slv_data <= w3_read_cnt ;
8'h4_8: o_slv_data <= w3_erase_cnt;
8'h4_c: o_slv_data <= r_reserved;
`else `ifdef WAY2
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
8'h2_0: o_slv_data <= w1_prog_cnt ;
8'h2_4: o_slv_data <= w1_read_cnt ;
8'h2_8: o_slv_data <= w1_erase_cnt;
8'h2_c: o_slv_data <= r_reserved;
`else `ifdef WAY1
8'h1_0: o_slv_data <= w0_prog_cnt ;
8'h1_4: o_slv_data <= w0_read_cnt ;
8'h1_8: o_slv_data <= w0_erase_cnt;
8'h1_c: o_slv_data <= r_reserved;
`endif `endif `endif `endif
default: o_slv_data <= 'b0;
endcase
end
always @ (posedge i_bus_clk)
begin
r_prog_cnt_cp_cmplt[0] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[1] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[2] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[3] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[4] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[5] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[6] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_prog_cnt_cp_cmplt[7] <= i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
always @ (posedge i_bus_clk)
begin
r_read_cnt_cp_cmplt[0] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[1] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[2] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[3] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[4] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[5] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[6] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_read_cnt_cp_cmplt[7] <= i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & (!i_slv_addr[5]) & (!i_slv_addr[4]) & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
always @ (posedge i_bus_clk)
begin
r_erase_cnt_cp_cmplt[0] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & (!i_slv_addr[5]) & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[1] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[2] <= i_slv_rd_ack & (!i_slv_addr[7]) & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[3] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[4] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & (!i_slv_addr[5]) & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[5] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[6] <= i_slv_rd_ack & (!i_slv_addr[7]) & i_slv_addr[6] & i_slv_addr[5] & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_erase_cnt_cp_cmplt[7] <= i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & (!i_slv_addr[5]) & (!i_slv_addr[4]) & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
always @ (posedge i_bus_clk)
begin
r_ch_prog_cnt_cp_cmplt = i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_ch_read_cnt_cp_cmplt = i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & (!i_slv_addr[3]) & i_slv_addr[2] & (!i_slv_addr[1]) & (!i_slv_addr[0]);
r_ch_erase_cnt_cp_cmplt = i_slv_rd_ack & i_slv_addr[7] & (!i_slv_addr[6]) & i_slv_addr[5] & i_slv_addr[4] & i_slv_addr[3] & (!i_slv_addr[2]) & (!i_slv_addr[1]) & (!i_slv_addr[0]);
end
assign w0_prog_cnt = w_prog_cnt[31:0] ;
assign w0_read_cnt = w_read_cnt[31:0] ;
assign w0_erase_cnt = w_erase_cnt[31:0];
assign w1_prog_cnt = w_prog_cnt[63:32] ;
assign w1_read_cnt = w_read_cnt[63:32] ;
assign w1_erase_cnt = w_erase_cnt[63:32];
assign w2_prog_cnt = w_prog_cnt[95:64] ;
assign w2_read_cnt = w_read_cnt[95:64] ;
assign w2_erase_cnt = w_erase_cnt[95:64];
assign w3_prog_cnt = w_prog_cnt[127:96] ;
assign w3_read_cnt = w_read_cnt[127:96] ;
assign w3_erase_cnt = w_erase_cnt[127:96];
assign w4_prog_cnt = w_prog_cnt[159:128] ;
assign w4_read_cnt = w_read_cnt[159:128] ;
assign w4_erase_cnt = w_erase_cnt[159:128];
assign w5_prog_cnt = w_prog_cnt[191:160] ;
assign w5_read_cnt = w_read_cnt[191:160] ;
assign w5_erase_cnt = w_erase_cnt[191:160];
assign w6_prog_cnt = w_prog_cnt[223:192] ;
assign w6_read_cnt = w_read_cnt[223:192] ;
assign w6_erase_cnt = w_erase_cnt[223:192];
assign w7_prog_cnt = w_prog_cnt[255:224] ;
assign w7_read_cnt = w_read_cnt[255:224] ;
assign w7_erase_cnt = w_erase_cnt[255:224];
assign w_ch_req_cnt = {w_ch_prog_req_cnt, w_ch_read_req_cnt, w_ch_erase_req_cnt};
assign w_ch_monitor_status = {w_ch_prog_ready, w_ch_read_ready, w_ch_erase_ready};
performance_ch_prog_counter performance_ch_prog_counter0(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_ch_monitor_confi),
.i_prog_cnt_cp_cmplt(r_ch_prog_cnt_cp_cmplt),
.o_prog_cnt (w_ch_prog_cnt),
.o_prog_req_cnt (w_ch_prog_req_cnt),
.i_prog_start (i_prog_start),
.i_prog_end (i_prog_end),
.i_op_fail (i_op_fail),
.o_prog_ready (w_ch_prog_ready)
);
performance_ch_read_counter performance_ch_read_counter0(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_ch_monitor_confi),
.i_read_cnt_cp_cmplt(r_ch_read_cnt_cp_cmplt),
.o_read_cnt (w_ch_read_cnt),
.o_read_req_cnt (w_ch_read_req_cnt),
.i_read_start (i_read_start),
.i_read_end (i_read_end),
.i_op_fail (i_op_fail),
.o_read_ready (w_ch_read_ready)
);
performance_ch_erase_counter performance_ch_erase_counter0(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_ch_monitor_confi),
.i_erase_cnt_cp_cmplt(r_ch_erase_cnt_cp_cmplt),
.o_erase_cnt (w_ch_erase_cnt),
.o_erase_req_cnt (w_ch_erase_req_cnt),
.i_erase_start (i_erase_start),
.i_erase_end (i_erase_end),
.i_op_fail (i_op_fail),
.o_erase_ready (w_ch_erase_ready)
);
genvar i;
generate
for(i=0;i<`WAY;i=i+1)
begin : performance_status
assign w_way_monitor_status[(i+1)*4-1:i*4] = {w_prog_ready[i], w_read_ready[i], w_erase_ready[i], 1'b0};
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : req_cnt
assign w_req_cnt[i] = {w_prog_req_cnt[i], w_read_req_cnt[i], w_erase_req_cnt[i]};
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : prog_monitoring_module_generate
performance_counter_prog prog_counter(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_way_monitor_confi),
.i_prog_cnt_cp_cmplt (r_prog_cnt_cp_cmplt[i]),
.o_prog_cnt (w_prog_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.o_prog_req_cnt (w_prog_req_cnt[i]),
.i_prog_start (i_prog_start[i]),
.i_prog_end (i_prog_end[i]),
.i_op_fail (i_op_fail[i]),
.o_prog_ready (w_prog_ready[i])
);
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : read_monitoring_module_generate
performance_counter_read read_counter(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_way_monitor_confi),
.i_read_cnt_cp_cmplt (r_read_cnt_cp_cmplt[i]),
.o_read_cnt (w_read_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.o_read_req_cnt (w_read_req_cnt[i]),
.i_read_start (i_read_start[i]),
.i_read_end (i_read_end[i]),
.i_op_fail (i_op_fail[i]),
.o_read_ready (w_read_ready[i])
);
end
endgenerate
generate
for(i=0;i<`WAY;i=i+1)
begin : erase_monitoring_module_generate
performance_counter_erase erase_counter(
.i_bus_clk (i_bus_clk),
.i_bus_rst (!i_bus_rstn),
.i_config (r_way_monitor_confi),
.i_erase_cnt_cp_cmplt (r_erase_cnt_cp_cmplt[i]),
.o_erase_cnt (w_erase_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.o_erase_req_cnt (w_erase_req_cnt[i]),
.i_erase_start (i_erase_start[i]),
.i_erase_end (i_erase_end[i]),
.i_op_fail (i_op_fail[i]),
.o_erase_ready (w_erase_ready[i])
);
end
endgenerate
function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
endmodule | 25 |
137,305 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v | 77,907,036 | performance_monitor_reg.v | v | 467 | 199 | [] | [] | [] | [(39, 502)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:1: Cannot find include file: p_parameter.vh\n`include "p_parameter.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.sv\n p_parameter.vh\n p_parameter.vh.v\n p_parameter.vh.sv\n obj_dir/p_parameter.vh\n obj_dir/p_parameter.vh.v\n obj_dir/p_parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:10: Define or directive not defined: \'`SLV_DATA_WD\'\n input wire [`SLV_DATA_WD-1:0] i_slv_data,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:11: Define or directive not defined: \'`SLV_DATA_WD\'\n output reg [`SLV_DATA_WD-1:0] o_slv_data,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:12: Define or directive not defined: \'`SLV_ADDR_WD\'\n input wire [`SLV_ADDR_WD-1:0] i_slv_addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:20: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:21: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_end,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:22: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_read_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:23: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_read_end,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:24: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_erase_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:25: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_erase_end,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:26: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_op_fail\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:30: Define or directive not defined: \'`SLV_DATA_WD\'\n reg [`SLV_DATA_WD-1:0] r_ch_monitor_confi ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:31: Define or directive not defined: \'`SLV_DATA_WD\'\n reg [`SLV_DATA_WD-1:0] r_way_monitor_confi ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:32: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_way_monitor_status;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:33: Define or directive not defined: \'`SLV_DATA_WD\'\n reg [`SLV_DATA_WD-1:0] r_reserved ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:36: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_req_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:37: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_monitor_status;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:39: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_prog_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:44: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_read_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:49: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_ch_erase_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:55: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:55: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:55: Define or directive not defined: \'`WAY\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_prog_cnt;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:56: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:56: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:56: Define or directive not defined: \'`WAY\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_read_cnt;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:57: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:57: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:57: Define or directive not defined: \'`WAY\'\n wire [`SLV_DATA_WD*`WAY-1:0] w_erase_cnt;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:110: Define or directive not defined: \'`SLV_DATA_WD\'\n wire [`SLV_DATA_WD-1:0] w_req_cnt [0:7];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:116: Define or directive not defined: \'`WAY\'\n wire [`WAY-1:0] w_prog_ready;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:117: Define or directive not defined: \'`WAY\'\n wire [`WAY-1:0] w_read_ready;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:118: Define or directive not defined: \'`WAY\'\n wire [`WAY-1:0] w_erase_ready;\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:385: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:385: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for(i=0;i<`WAY;i=i+1)\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:392: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:399: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:407: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_prog_cnt (w_prog_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:407: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_prog_cnt (w_prog_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:418: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:426: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_read_cnt (w_read_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:426: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_read_cnt (w_read_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:437: Define or directive not defined: \'`WAY\'\n for(i=0;i<`WAY;i=i+1)\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:445: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_erase_cnt (w_erase_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:445: Define or directive not defined: \'`SLV_DATA_WD\'\n .o_erase_cnt (w_erase_cnt[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:460: syntax error, unexpected \'=\', expecting IDENTIFIER\n clogb2 = 0;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_reg.v:462: syntax error, unexpected \'=\', expecting IDENTIFIER\n clogb2 = i + 1;\n ^\n%Error: Cannot continue\n' | 295,882 | function | function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction | function integer clogb2; |
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction | 25 |
137,306 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v | 77,907,036 | performance_monitor_top.v | v | 56 | 54 | [] | [] | [] | [(39, 91)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:1: Cannot find include file: p_parameter.vh\n`include "p_parameter.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/p_parameter.vh.sv\n p_parameter.vh\n p_parameter.vh.v\n p_parameter.vh.sv\n obj_dir/p_parameter.vh\n obj_dir/p_parameter.vh.v\n obj_dir/p_parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:7: Define or directive not defined: \'`SLV_DATA_WD\'\n input wire [`SLV_DATA_WD-1:0] Bus2IP_Addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:9: Define or directive not defined: \'`SLV_DATA_WD\'\n input wire [`SLV_DATA_WD-1:0] Bus2IP_Data,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:10: Define or directive not defined: \'`SLV_DATA_WD\'\n input wire [`SLV_DATA_WD/8-1 : 0] Bus2IP_BE,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:10: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n input wire [`SLV_DATA_WD/8-1 : 0] Bus2IP_BE,\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [0:0] Bus2IP_WrCE,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [`SLV_ADDR_WD-1:0] IP2Bus_Data,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:13: Define or directive not defined: \'`SLV_ADDR_WD\'\n output wire [`SLV_ADDR_WD-1:0] IP2Bus_Data,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_RdAck,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_WrAck,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_Error,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`WAY-1:0] i_prog_start ,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:19: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_start ,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`WAY-1:0] i_prog_end ,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:20: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_prog_end ,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`WAY-1:0] i_read_start ,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:21: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_read_start ,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`WAY-1:0] i_read_end ,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:22: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_read_end ,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`WAY-1:0] i_erase_start,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:23: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_erase_start,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`WAY-1:0] i_erase_end ,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:24: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_erase_end ,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`WAY-1:0] i_op_fail\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:25: Define or directive not defined: \'`WAY\'\n input wire [`WAY-1:0] i_op_fail\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:26: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/performance_monitor_v1_00_a/hdl/verilog/performance_monitor_top.v:31: syntax error, unexpected assign\n assign IP2Bus_WrAck = w_slv_write_ack;\n ^~~~~~\n%Error: Exiting due to 27 error(s)\n' | 295,883 | module | module performance_monitor_top
(
input wire Bus2IP_Clk,
input wire Bus2IP_Resetn,
input wire [`SLV_DATA_WD-1:0] Bus2IP_Addr,
input wire Bus2IP_RNW,
input wire [`SLV_DATA_WD-1:0] Bus2IP_Data,
input wire [`SLV_DATA_WD/8-1 : 0] Bus2IP_BE,
input wire [0:0] Bus2IP_RdCE,
input wire [0:0] Bus2IP_WrCE,
output wire [`SLV_ADDR_WD-1:0] IP2Bus_Data,
output wire IP2Bus_RdAck,
output wire IP2Bus_WrAck,
output wire IP2Bus_Error,
input wire [`WAY-1:0] i_prog_start ,
input wire [`WAY-1:0] i_prog_end ,
input wire [`WAY-1:0] i_read_start ,
input wire [`WAY-1:0] i_read_end ,
input wire [`WAY-1:0] i_erase_start,
input wire [`WAY-1:0] i_erase_end ,
input wire [`WAY-1:0] i_op_fail
);
wire w_slv_read_ack;
wire w_slv_write_ack;
assign IP2Bus_WrAck = w_slv_write_ack;
assign IP2Bus_RdAck = w_slv_read_ack;
assign IP2Bus_Error = 0;
performance_monitor_reg performance_monitor_reg0(
.i_bus_clk (Bus2IP_Clk) ,
.i_bus_rstn (Bus2IP_Resetn) ,
.i_slv_data (Bus2IP_Data) ,
.o_slv_data (IP2Bus_Data) ,
.i_slv_addr (Bus2IP_Addr) ,
.i_slv_rnw (Bus2IP_RNW) ,
.o_slv_write_ack(w_slv_write_ack),
.o_slv_read_ack (w_slv_read_ack) ,
.i_slv_wr_ack (|{Bus2IP_WrCE}) ,
.i_slv_rd_ack (|{Bus2IP_RdCE}) ,
.i_prog_start (i_prog_start) ,
.i_prog_end (i_prog_end) ,
.i_read_start (i_read_start) ,
.i_read_end (i_read_end) ,
.i_erase_start (i_erase_start) ,
.i_erase_end (i_erase_end) ,
.i_op_fail (i_op_fail)
);
endmodule | module performance_monitor_top
(
input wire Bus2IP_Clk,
input wire Bus2IP_Resetn,
input wire [`SLV_DATA_WD-1:0] Bus2IP_Addr,
input wire Bus2IP_RNW,
input wire [`SLV_DATA_WD-1:0] Bus2IP_Data,
input wire [`SLV_DATA_WD/8-1 : 0] Bus2IP_BE,
input wire [0:0] Bus2IP_RdCE,
input wire [0:0] Bus2IP_WrCE,
output wire [`SLV_ADDR_WD-1:0] IP2Bus_Data,
output wire IP2Bus_RdAck,
output wire IP2Bus_WrAck,
output wire IP2Bus_Error,
input wire [`WAY-1:0] i_prog_start ,
input wire [`WAY-1:0] i_prog_end ,
input wire [`WAY-1:0] i_read_start ,
input wire [`WAY-1:0] i_read_end ,
input wire [`WAY-1:0] i_erase_start,
input wire [`WAY-1:0] i_erase_end ,
input wire [`WAY-1:0] i_op_fail
); |
wire w_slv_read_ack;
wire w_slv_write_ack;
assign IP2Bus_WrAck = w_slv_write_ack;
assign IP2Bus_RdAck = w_slv_read_ack;
assign IP2Bus_Error = 0;
performance_monitor_reg performance_monitor_reg0(
.i_bus_clk (Bus2IP_Clk) ,
.i_bus_rstn (Bus2IP_Resetn) ,
.i_slv_data (Bus2IP_Data) ,
.o_slv_data (IP2Bus_Data) ,
.i_slv_addr (Bus2IP_Addr) ,
.i_slv_rnw (Bus2IP_RNW) ,
.o_slv_write_ack(w_slv_write_ack),
.o_slv_read_ack (w_slv_read_ack) ,
.i_slv_wr_ack (|{Bus2IP_WrCE}) ,
.i_slv_rd_ack (|{Bus2IP_RdCE}) ,
.i_prog_start (i_prog_start) ,
.i_prog_end (i_prog_end) ,
.i_read_start (i_read_start) ,
.i_read_end (i_read_end) ,
.i_erase_start (i_erase_start) ,
.i_erase_end (i_erase_end) ,
.i_op_fail (i_op_fail)
);
endmodule | 25 |
137,307 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ch_abt.v | 77,907,036 | ch_abt.v | v | 225 | 91 | [] | ['general public license', 'free software foundation'] | [] | [(215, 388)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ch_abt.v:49: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ch_abt.v:55: Define or directive not defined: \'`WAY\'\ninput [`WAY-1:0] i_ch_req,\n ^~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ch_abt.v:56: Define or directive not defined: \'`WAY\'\noutput [`WAY-1:0] o_ch_grt\n ^~~~\n%Error: Exiting due to 3 error(s)\n' | 295,886 | module | module ch_arbiter (
input i_nc_clk,
input i_nc_rstn,
input [`WAY-1:0] i_ch_req,
output [`WAY-1:0] o_ch_grt
);
reg [7:0] o_ch_grt;
parameter IDLE = 4'b0000;
parameter GNT_0 = 4'b0001;
parameter GNT_1 = 4'b0011;
parameter GNT_2 = 4'b0010;
parameter GNT_3 = 4'b0110;
parameter GNT_4 = 4'b0111;
parameter GNT_5 = 4'b0101;
parameter GNT_6 = 4'b0100;
parameter GNT_7 = 4'b1100;
reg [3:0] cur_state;
reg [3:0] next_state;
reg [7:0] arbiter_ptr;
always @ (posedge i_nc_clk, negedge i_nc_rstn) begin
if (!i_nc_rstn)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case (cur_state)
IDLE : begin
casex (i_ch_req)
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_0 : begin
casex (i_ch_req)
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_1 : begin
casex (i_ch_req)
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_2 : begin
casex (i_ch_req)
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_3 : begin
casex (i_ch_req)
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_4 : begin
casex (i_ch_req)
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_5 : begin
casex (i_ch_req)
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_6 : begin
casex (i_ch_req)
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_7 : begin
casex (i_ch_req)
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b0000_0000 : next_state <= IDLE;
endcase
end
default:
next_state <= IDLE;
endcase
end
always @ (*) begin
case (cur_state)
GNT_0 : o_ch_grt <= 8'b0000_0001;
GNT_1 : o_ch_grt <= 8'b0000_0010;
GNT_2 : o_ch_grt <= 8'b0000_0100;
GNT_3 : o_ch_grt <= 8'b0000_1000;
GNT_4 : o_ch_grt <= 8'b0001_0000;
GNT_5 : o_ch_grt <= 8'b0010_0000;
GNT_6 : o_ch_grt <= 8'b0100_0000;
GNT_7 : o_ch_grt <= 8'b1000_0000;
default : o_ch_grt <= 8'b0;
endcase
end
endmodule | module ch_arbiter (
input i_nc_clk,
input i_nc_rstn,
input [`WAY-1:0] i_ch_req,
output [`WAY-1:0] o_ch_grt
); |
reg [7:0] o_ch_grt;
parameter IDLE = 4'b0000;
parameter GNT_0 = 4'b0001;
parameter GNT_1 = 4'b0011;
parameter GNT_2 = 4'b0010;
parameter GNT_3 = 4'b0110;
parameter GNT_4 = 4'b0111;
parameter GNT_5 = 4'b0101;
parameter GNT_6 = 4'b0100;
parameter GNT_7 = 4'b1100;
reg [3:0] cur_state;
reg [3:0] next_state;
reg [7:0] arbiter_ptr;
always @ (posedge i_nc_clk, negedge i_nc_rstn) begin
if (!i_nc_rstn)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case (cur_state)
IDLE : begin
casex (i_ch_req)
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_0 : begin
casex (i_ch_req)
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_1 : begin
casex (i_ch_req)
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_2 : begin
casex (i_ch_req)
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_3 : begin
casex (i_ch_req)
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_4 : begin
casex (i_ch_req)
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_5 : begin
casex (i_ch_req)
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_6 : begin
casex (i_ch_req)
8'bx1xx_xxxx : next_state <= GNT_6;
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'b0000_0000 : next_state <= IDLE;
endcase
end
GNT_7 : begin
casex (i_ch_req)
8'b1xxx_xxxx : next_state <= GNT_7;
8'bxxxx_xxx1 : next_state <= GNT_0;
8'bxxxx_xx1x : next_state <= GNT_1;
8'bxxxx_x1xx : next_state <= GNT_2;
8'bxxxx_1xxx : next_state <= GNT_3;
8'bxxx1_xxxx : next_state <= GNT_4;
8'bxx1x_xxxx : next_state <= GNT_5;
8'bx1xx_xxxx : next_state <= GNT_6;
8'b0000_0000 : next_state <= IDLE;
endcase
end
default:
next_state <= IDLE;
endcase
end
always @ (*) begin
case (cur_state)
GNT_0 : o_ch_grt <= 8'b0000_0001;
GNT_1 : o_ch_grt <= 8'b0000_0010;
GNT_2 : o_ch_grt <= 8'b0000_0100;
GNT_3 : o_ch_grt <= 8'b0000_1000;
GNT_4 : o_ch_grt <= 8'b0001_0000;
GNT_5 : o_ch_grt <= 8'b0010_0000;
GNT_6 : o_ch_grt <= 8'b0100_0000;
GNT_7 : o_ch_grt <= 8'b1000_0000;
default : o_ch_grt <= 8'b0;
endcase
end
endmodule | 25 |
137,311 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder_ctl.v | 77,907,036 | decoder_ctl.v | v | 347 | 179 | [] | ['general public license', 'free software foundation'] | [] | [(214, 510)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder_ctl.v:48: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder_ctl.v:60: Define or directive not defined: \'`NAND_PBAWIDTH\'\n output reg [`NAND_PBAWIDTH-1:0] o_dec_addr,\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 295,891 | module | module decoder_ctl
(
input wire i_nc_clk,
input wire i_nc_rstn,
input wire i_dec_gen_start,
output reg o_dec_gen_cmplt,
output reg o_dec_en,
output reg o_dec_we,
output reg [`NAND_PBAWIDTH-1:0] o_dec_addr,
input wire [7:0] i_dec_data,
output reg [7:0] o_dec_data,
output reg o_dec_fail
);
reg [2:0] r_cur_state;
reg [2:0] r_next_state;
wire w_dec_available;
wire w_err_detection_end;
reg r_err_detection_end;
wire w_err_detection_end_1;
wire w_err_detected;
reg r_err_detected;
wire w_err_detected_1;
wire w_kes_end;
reg r_kes_end;
wire w_kes_end_1;
wire w_kes_fail;
wire w_dec_data_strobe;
wire w_cor_data_end;
reg r_cor_data_end;
wire w_cor_data_end_1;
wire [7:0] w_dec_data_o;
reg [1:0] r_dec_end_cnt;
reg [11:0] r_det_data_cnt;
reg r_execute_decoding;
reg r_code_BUS_valid ;
parameter DEC_IDLE = 3'b000;
parameter DEC_INIT = 3'b001;
parameter ERR_DETECTION = 3'b011;
parameter ERR_CORRECTION = 3'b010;
parameter DEC_DATA_TRANS = 3'b110;
parameter DEC_END = 3'b100;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_cur_state <= DEC_IDLE;
else r_cur_state <= r_next_state;
end
always @ (*)
begin
case(r_cur_state)
DEC_IDLE:
begin
r_next_state <= (i_dec_gen_start && w_dec_available) ? DEC_INIT : DEC_IDLE;
end
DEC_INIT:
begin
r_next_state <= ERR_DETECTION;
end
ERR_DETECTION:
begin
r_next_state <= (w_err_detection_end_1) ? (w_err_detected_1) ? ERR_CORRECTION : DEC_END : ERR_DETECTION;
end
ERR_CORRECTION:
begin
r_next_state <= (!w_kes_fail) ? (w_kes_end_1) ? DEC_DATA_TRANS : ERR_CORRECTION : DEC_END;
end
DEC_DATA_TRANS:
begin
r_next_state <= (!w_cor_data_end_1) ? DEC_DATA_TRANS : DEC_END;
end
DEC_END:
begin
r_next_state <= (r_dec_end_cnt) ? DEC_END : DEC_IDLE;
end
default:
begin
r_next_state <= DEC_IDLE;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
ERR_DETECTION:
begin
r_execute_decoding <= (r_det_data_cnt==0) ? 'b1 : 'b0;
r_code_BUS_valid <= (r_det_data_cnt!=2198)? 'b1 : 'b0;
end
default:
begin
r_execute_decoding <= 'b0;
r_code_BUS_valid <= 'b0;
end
endcase
end
reg r_execute_decoding_1;
wire r_execute_decoding_2;
always @ (posedge i_nc_clk)
begin
r_execute_decoding_1 <= r_execute_decoding;
end
assign r_execute_decoding_2 = |{r_execute_decoding, r_execute_decoding_1};
always @ (*)
begin
case(r_cur_state)
DEC_INIT:
begin
o_dec_en <= 'b1;
o_dec_we <= 'b0;
end
ERR_DETECTION:
begin
o_dec_en <= 'b1;
o_dec_we <= 'b0;
end
DEC_DATA_TRANS:
begin
o_dec_en <= (w_dec_data_strobe)? 'b1 : 'b0;
o_dec_we <= (w_dec_data_strobe)? 'b1 : 'b0;
end
default:
begin
o_dec_en <= 'b0;
o_dec_we <= 'b0;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
DEC_INIT:
begin
o_dec_addr <= o_dec_addr + 'b1;
end
ERR_DETECTION:
begin
o_dec_addr <= (&{o_dec_addr[11], o_dec_addr[7],o_dec_addr[4],o_dec_addr[2],o_dec_addr[0]}) ? o_dec_addr : o_dec_addr + 'b1;
end
DEC_DATA_TRANS:
begin
o_dec_addr <= (w_dec_data_strobe) ? o_dec_addr + 'b1 : o_dec_addr;
end
default:
begin
o_dec_addr <= 'b0;
end
endcase
end
always @ (*)
begin
case(r_cur_state)
DEC_DATA_TRANS: o_dec_data <= w_dec_data_o;
default: o_dec_data <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
ERR_DETECTION:
begin
r_det_data_cnt <= (&{r_det_data_cnt[11], r_det_data_cnt[7],r_det_data_cnt[4],r_det_data_cnt[2],r_det_data_cnt[1]}) ? r_det_data_cnt : r_det_data_cnt + 'b1;
r_dec_end_cnt <= 'h3;
end
DEC_END:
begin
r_det_data_cnt <= 'b0;
r_dec_end_cnt <= (r_dec_end_cnt) ? r_dec_end_cnt - 'b1 : r_dec_end_cnt;
end
default:
begin
r_det_data_cnt <= 'b0;
r_dec_end_cnt <= 'h3;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
DEC_END: o_dec_gen_cmplt <= 'b1;
default: o_dec_gen_cmplt <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) o_dec_fail <= 'b0;
else
begin
case(r_cur_state)
ERR_CORRECTION: o_dec_fail <= w_kes_fail;
default : o_dec_fail <= o_dec_fail;
endcase
end
end
always @ (posedge i_nc_clk)
begin
r_err_detection_end <= w_err_detection_end;
end
assign w_err_detection_end_1 = |{w_err_detection_end, r_err_detection_end};
always @ (posedge i_nc_clk)
begin
r_err_detected <= w_err_detected;
end
assign w_err_detected_1 = |{w_err_detected, r_err_detected};
always @ (posedge i_nc_clk)
begin
r_kes_end <= w_kes_end;
end
assign w_kes_end_1 = |{w_kes_end, r_kes_end};
always @ (posedge i_nc_clk)
begin
r_cor_data_end <= w_cor_data_end;
end
assign w_cor_data_end_1 = |{w_cor_data_end, r_cor_data_end};
decoder decoder0(
.clk_100 (i_nc_clk),
.nRESET (i_nc_rstn),
.decoder_state (),
.decoder_available (w_dec_available),
.execute_decoding (r_execute_decoding_2),
.code_BUS_valid (r_code_BUS_valid),
.code (i_dec_data),
.decoding_start (),
.last_code_block_received (),
.decoding_end (),
.error_detection_stage_end (w_err_detection_end),
.error_detected (w_err_detected),
.ELP_search_stage_end (w_kes_end),
.correction_fail (w_kes_fail),
.corrected_message_strobe (w_dec_data_strobe),
.corrected_message_output_start(),
.corrected_message_output_end (w_cor_data_end),
.corrected_message_out (w_dec_data_o)
);
function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
endmodule | module decoder_ctl
(
input wire i_nc_clk,
input wire i_nc_rstn,
input wire i_dec_gen_start,
output reg o_dec_gen_cmplt,
output reg o_dec_en,
output reg o_dec_we,
output reg [`NAND_PBAWIDTH-1:0] o_dec_addr,
input wire [7:0] i_dec_data,
output reg [7:0] o_dec_data,
output reg o_dec_fail
); |
reg [2:0] r_cur_state;
reg [2:0] r_next_state;
wire w_dec_available;
wire w_err_detection_end;
reg r_err_detection_end;
wire w_err_detection_end_1;
wire w_err_detected;
reg r_err_detected;
wire w_err_detected_1;
wire w_kes_end;
reg r_kes_end;
wire w_kes_end_1;
wire w_kes_fail;
wire w_dec_data_strobe;
wire w_cor_data_end;
reg r_cor_data_end;
wire w_cor_data_end_1;
wire [7:0] w_dec_data_o;
reg [1:0] r_dec_end_cnt;
reg [11:0] r_det_data_cnt;
reg r_execute_decoding;
reg r_code_BUS_valid ;
parameter DEC_IDLE = 3'b000;
parameter DEC_INIT = 3'b001;
parameter ERR_DETECTION = 3'b011;
parameter ERR_CORRECTION = 3'b010;
parameter DEC_DATA_TRANS = 3'b110;
parameter DEC_END = 3'b100;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_cur_state <= DEC_IDLE;
else r_cur_state <= r_next_state;
end
always @ (*)
begin
case(r_cur_state)
DEC_IDLE:
begin
r_next_state <= (i_dec_gen_start && w_dec_available) ? DEC_INIT : DEC_IDLE;
end
DEC_INIT:
begin
r_next_state <= ERR_DETECTION;
end
ERR_DETECTION:
begin
r_next_state <= (w_err_detection_end_1) ? (w_err_detected_1) ? ERR_CORRECTION : DEC_END : ERR_DETECTION;
end
ERR_CORRECTION:
begin
r_next_state <= (!w_kes_fail) ? (w_kes_end_1) ? DEC_DATA_TRANS : ERR_CORRECTION : DEC_END;
end
DEC_DATA_TRANS:
begin
r_next_state <= (!w_cor_data_end_1) ? DEC_DATA_TRANS : DEC_END;
end
DEC_END:
begin
r_next_state <= (r_dec_end_cnt) ? DEC_END : DEC_IDLE;
end
default:
begin
r_next_state <= DEC_IDLE;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
ERR_DETECTION:
begin
r_execute_decoding <= (r_det_data_cnt==0) ? 'b1 : 'b0;
r_code_BUS_valid <= (r_det_data_cnt!=2198)? 'b1 : 'b0;
end
default:
begin
r_execute_decoding <= 'b0;
r_code_BUS_valid <= 'b0;
end
endcase
end
reg r_execute_decoding_1;
wire r_execute_decoding_2;
always @ (posedge i_nc_clk)
begin
r_execute_decoding_1 <= r_execute_decoding;
end
assign r_execute_decoding_2 = |{r_execute_decoding, r_execute_decoding_1};
always @ (*)
begin
case(r_cur_state)
DEC_INIT:
begin
o_dec_en <= 'b1;
o_dec_we <= 'b0;
end
ERR_DETECTION:
begin
o_dec_en <= 'b1;
o_dec_we <= 'b0;
end
DEC_DATA_TRANS:
begin
o_dec_en <= (w_dec_data_strobe)? 'b1 : 'b0;
o_dec_we <= (w_dec_data_strobe)? 'b1 : 'b0;
end
default:
begin
o_dec_en <= 'b0;
o_dec_we <= 'b0;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
DEC_INIT:
begin
o_dec_addr <= o_dec_addr + 'b1;
end
ERR_DETECTION:
begin
o_dec_addr <= (&{o_dec_addr[11], o_dec_addr[7],o_dec_addr[4],o_dec_addr[2],o_dec_addr[0]}) ? o_dec_addr : o_dec_addr + 'b1;
end
DEC_DATA_TRANS:
begin
o_dec_addr <= (w_dec_data_strobe) ? o_dec_addr + 'b1 : o_dec_addr;
end
default:
begin
o_dec_addr <= 'b0;
end
endcase
end
always @ (*)
begin
case(r_cur_state)
DEC_DATA_TRANS: o_dec_data <= w_dec_data_o;
default: o_dec_data <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
ERR_DETECTION:
begin
r_det_data_cnt <= (&{r_det_data_cnt[11], r_det_data_cnt[7],r_det_data_cnt[4],r_det_data_cnt[2],r_det_data_cnt[1]}) ? r_det_data_cnt : r_det_data_cnt + 'b1;
r_dec_end_cnt <= 'h3;
end
DEC_END:
begin
r_det_data_cnt <= 'b0;
r_dec_end_cnt <= (r_dec_end_cnt) ? r_dec_end_cnt - 'b1 : r_dec_end_cnt;
end
default:
begin
r_det_data_cnt <= 'b0;
r_dec_end_cnt <= 'h3;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_cur_state)
DEC_END: o_dec_gen_cmplt <= 'b1;
default: o_dec_gen_cmplt <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) o_dec_fail <= 'b0;
else
begin
case(r_cur_state)
ERR_CORRECTION: o_dec_fail <= w_kes_fail;
default : o_dec_fail <= o_dec_fail;
endcase
end
end
always @ (posedge i_nc_clk)
begin
r_err_detection_end <= w_err_detection_end;
end
assign w_err_detection_end_1 = |{w_err_detection_end, r_err_detection_end};
always @ (posedge i_nc_clk)
begin
r_err_detected <= w_err_detected;
end
assign w_err_detected_1 = |{w_err_detected, r_err_detected};
always @ (posedge i_nc_clk)
begin
r_kes_end <= w_kes_end;
end
assign w_kes_end_1 = |{w_kes_end, r_kes_end};
always @ (posedge i_nc_clk)
begin
r_cor_data_end <= w_cor_data_end;
end
assign w_cor_data_end_1 = |{w_cor_data_end, r_cor_data_end};
decoder decoder0(
.clk_100 (i_nc_clk),
.nRESET (i_nc_rstn),
.decoder_state (),
.decoder_available (w_dec_available),
.execute_decoding (r_execute_decoding_2),
.code_BUS_valid (r_code_BUS_valid),
.code (i_dec_data),
.decoding_start (),
.last_code_block_received (),
.decoding_end (),
.error_detection_stage_end (w_err_detection_end),
.error_detected (w_err_detected),
.ELP_search_stage_end (w_kes_end),
.correction_fail (w_kes_fail),
.corrected_message_strobe (w_dec_data_strobe),
.corrected_message_output_start(),
.corrected_message_output_end (w_cor_data_end),
.corrected_message_out (w_dec_data_o)
);
function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
endmodule | 25 |
137,312 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder_ctl.v | 77,907,036 | decoder_ctl.v | v | 347 | 179 | [] | ['general public license', 'free software foundation'] | [] | [(214, 510)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder_ctl.v:48: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder_ctl.v:60: Define or directive not defined: \'`NAND_PBAWIDTH\'\n output reg [`NAND_PBAWIDTH-1:0] o_dec_addr,\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 295,891 | function | function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction | function integer clogb2; |
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction | 25 |
137,316 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v | 77,907,036 | ipif_burst.v | v | 468 | 105 | [] | ['general public license', 'free software foundation'] | [] | [(222, 631)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:56: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:60: Define or directive not defined: \'`SLV_DATA_WD\'\n parameter C_SLV_DWIDTH = `SLV_DATA_WD,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:60: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n parameter C_SLV_DWIDTH = `SLV_DATA_WD,\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:61: Define or directive not defined: \'`MST_ADDR_WD\'\n parameter C_MST_AWIDTH = `MST_ADDR_WD,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:61: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n parameter C_MST_AWIDTH = `MST_ADDR_WD,\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:62: Define or directive not defined: \'`MST_DATA_WD\'\n parameter C_MST_DWIDTH = `MST_DATA_WD,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:62: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n parameter C_MST_DWIDTH = `MST_DATA_WD,\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:63: Define or directive not defined: \'`NUM_REG\'\n parameter C_NUM_REG = `NUM_REG+2, \n ^~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:64: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter C_NUM_INTR = 1\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:65: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:68: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_Resetn,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:69: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`SLV_ADDR_WD -1:0] Bus2IP_Addr,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:69: Define or directive not defined: \'`SLV_ADDR_WD\'\n input wire [`SLV_ADDR_WD -1:0] Bus2IP_Addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:70: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [C_SLV_DWIDTH -1:0] Bus2IP_Data,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:71: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_RNW,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:72: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [C_SLV_DWIDTH/8 -1:0] Bus2IP_BE,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:73: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [C_NUM_REG -1:0] Bus2IP_RdCE,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:74: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [C_NUM_REG -1:0] Bus2IP_WrCE,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:75: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [C_SLV_DWIDTH -1:0] IP2Bus_Data,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:76: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_RdAck,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:77: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_WrAck,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:78: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_Error, \n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:81: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstRd_Req,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:82: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstWr_Req,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:83: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [C_MST_AWIDTH -1:0] IP2Bus_Mst_Addr,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:84: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [C_MST_DWIDTH/8 -1:0] IP2Bus_Mst_BE, \n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:85: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [`DMA_LEN-1 :0] IP2Bus_Mst_Length,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:85: Define or directive not defined: \'`DMA_LEN\'\n output wire [`DMA_LEN-1 :0] IP2Bus_Mst_Length,\n ^~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:86: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_Mst_Type,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:87: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_Mst_Lock,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:88: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_Mst_Reset,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:89: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_Mst_CmdAck,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:90: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_Mst_Cmplt,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:91: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_Mst_Error,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:92: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_Mst_Rearbitrate,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:93: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_Mst_Cmd_Timeout,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:94: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [C_MST_DWIDTH -1:0] Bus2IP_MstRd_d,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:95: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [C_MST_DWIDTH/8 -1:0] Bus2IP_MstRd_rem,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:96: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_MstRd_sof_n,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:97: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_MstRd_eof_n,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:98: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_MstRd_src_rdy_n,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:99: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire Bus2IP_MstRd_src_dsc_n,\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:100: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstRd_dst_rdy_n,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:101: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstRd_dst_dsc_n,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:102: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [C_MST_DWIDTH -1:0] IP2Bus_MstWr_d,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:103: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [C_MST_DWIDTH/8 -1:0] IP2Bus_MstWr_rem,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:104: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstWr_sof_n,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:105: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstWr_eof_n,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:106: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstWr_src_rdy_n,\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v:107: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire IP2Bus_MstWr_src_dsc_n,\n ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 295,896 | module | module ipif #(
parameter C_SLV_DWIDTH = `SLV_DATA_WD,
parameter C_MST_AWIDTH = `MST_ADDR_WD,
parameter C_MST_DWIDTH = `MST_DATA_WD,
parameter C_NUM_REG = `NUM_REG+2,
parameter C_NUM_INTR = 1
)(
input wire Bus2IP_Clk,
input wire Bus2IP_Resetn,
input wire [`SLV_ADDR_WD -1:0] Bus2IP_Addr,
input wire [C_SLV_DWIDTH -1:0] Bus2IP_Data,
input wire Bus2IP_RNW,
input wire [C_SLV_DWIDTH/8 -1:0] Bus2IP_BE,
input wire [C_NUM_REG -1:0] Bus2IP_RdCE,
input wire [C_NUM_REG -1:0] Bus2IP_WrCE,
output wire [C_SLV_DWIDTH -1:0] IP2Bus_Data,
output wire IP2Bus_RdAck,
output wire IP2Bus_WrAck,
output wire IP2Bus_Error,
output wire IP2Bus_MstRd_Req,
output wire IP2Bus_MstWr_Req,
output wire [C_MST_AWIDTH -1:0] IP2Bus_Mst_Addr,
output wire [C_MST_DWIDTH/8 -1:0] IP2Bus_Mst_BE,
output wire [`DMA_LEN-1 :0] IP2Bus_Mst_Length,
output wire IP2Bus_Mst_Type,
output wire IP2Bus_Mst_Lock,
output wire IP2Bus_Mst_Reset,
input wire Bus2IP_Mst_CmdAck,
input wire Bus2IP_Mst_Cmplt,
input wire Bus2IP_Mst_Error,
input wire Bus2IP_Mst_Rearbitrate,
input wire Bus2IP_Mst_Cmd_Timeout,
input wire [C_MST_DWIDTH -1:0] Bus2IP_MstRd_d,
input wire [C_MST_DWIDTH/8 -1:0] Bus2IP_MstRd_rem,
input wire Bus2IP_MstRd_sof_n,
input wire Bus2IP_MstRd_eof_n,
input wire Bus2IP_MstRd_src_rdy_n,
input wire Bus2IP_MstRd_src_dsc_n,
output wire IP2Bus_MstRd_dst_rdy_n,
output wire IP2Bus_MstRd_dst_dsc_n,
output wire [C_MST_DWIDTH -1:0] IP2Bus_MstWr_d,
output wire [C_MST_DWIDTH/8 -1:0] IP2Bus_MstWr_rem,
output wire IP2Bus_MstWr_sof_n,
output wire IP2Bus_MstWr_eof_n,
output wire IP2Bus_MstWr_src_rdy_n,
output wire IP2Bus_MstWr_src_dsc_n,
input wire Bus2IP_MstWr_dst_rdy_n,
input wire Bus2IP_MstWr_dst_dsc_n,
input wire i_clk ,
input wire i_clk_200 ,
input wire i_rstn ,
input wire [`CIO_WD*`CH-1:0] i_nand_dq_i ,
output reg [`CIO_WD*`CH-1:0] o_nand_dq_o ,
output reg [`CIO_WD*`CH-1:0] o_nand_dq_t ,
output reg o_nand_cle ,
output reg o_nand_ale ,
output reg [`CLST*`CH*`WAY-1:0] o_nand_ce_n ,
output wire o_nand_clk ,
output reg o_nand_wr_n ,
output reg o_nand_wp_n ,
input wire [`CLST*`CH*`WAY-1:0] i_nand_rb ,
input wire i_nand_dqs ,
output wire o_nand_dqs ,
output reg o_nand_dqs_t,
output wire [`WAY-1:0] o_prog_start ,
output wire [`WAY-1:0] o_prog_end ,
output wire [`WAY-1:0] o_read_start ,
output wire [`WAY-1:0] o_read_end ,
output wire [`WAY-1:0] o_erase_start,
output wire [`WAY-1:0] o_erase_end ,
output wire [`WAY-1:0] o_op_fail
);
wire [`SLV_DATA_WD-1 :0] w_slv_i_data;
wire [`SLV_DATA_WD-1:0] w_slv_o_data;
wire [`SLV_ADDR_WD-1:0] w_slv_addr;
wire [`MST_ADDR_WD-1:0] w_dma_addr;
wire [`DMA_LEN-1:0] w_dma_length;
wire [`MST_DATA_WD-1:0] w_dma_i_data;
wire [`MST_DATA_WD-1:0] w_dma_o_data;
wire [`CIO_WD*`CH-1:0] l_nand_dq_o;
wire [`CIO_WD*`CH-1:0] l_nand_dq_t;
wire [`CLST*`CH-1:0] l_nand_cle;
wire [`CLST*`CH-1:0] l_nand_ale;
wire [`CLST*`CH*`WAY-1:0] l_nand_ce_n;
wire [`CLST*`CH-1:0] l_nand_we_n;
wire [`CLST*`CH-1:0] l_nand_wr_n;
wire [`CLST*`CH-1:0] l_nand_wp_n;
wire [`CIO_WD*`CH-1:0] w_nand_dq_i;
wire [`CIO_WD*`CH-1:0] w_nand_dq_o;
wire [`CIO_WD*`CH-1:0] b_nand_dq_o;
wire [`CH-1:0] w_nand_dq_t;
wire [`CH-1:0] w_nand_cle ;
wire [`CH-1:0] w_nand_ale ;
wire [`CH*`WAY-1:0] w_nand_ce_n;
wire [`CH-1:0] w_nand_we_n;
wire [`CH-1:0] w_nand_wr_n;
wire [`CH-1:0] w_nand_wp_n;
wire [`CH*`WAY-1:0] w_nand_rb;
reg [`CH*`WAY-1:0] r_nand_rb;
reg [`CIO_WD*`CH-1:0] r_nand_dq_o;
reg [`CH-1:0] r_nand_we_n;
wire w_nand_dqs_i;
wire l_nand_dqs_t;
wire [`CH-1:0] w_nand_dqs_t;
wire b_nand_dqs;
wire w_clk_o;
wire [`CH-1:0] w_m_ch_cmplt;
wire w_dqs_ce;
reg r_dqs_ce;
wire w_read_sp_ack;
wire w_prog_sp_ack;
wire w_slv_wr_ack;
wire w_slv_rd_ack;
reg r_b2ip_cmd_ack;
wire w_b2ip_cmd_ack;
reg r_b2ip_cmplt;
wire w_b2ip_cmplt;
wire [`NUM_REG-1:0] w_reg_rd_sel;
wire [`NUM_REG-1:0] w_reg_wr_sel;
reg [`NUM_REG-1:0] f_reg_rd_sel;
reg [`NUM_REG-1:0] f_reg_wr_sel;
assign IP2Bus_WrAck = |{f_reg_wr_sel, w_prog_sp_ack};
assign IP2Bus_RdAck = |{f_reg_rd_sel, w_read_sp_ack};
assign IP2Bus_Error = 0;
assign w_slv_wr_ack = |{w_reg_wr_sel};
assign w_slv_rd_ack = |{w_reg_rd_sel};
assign w_b2ip_cmd_ack = |{Bus2IP_Mst_CmdAck, r_b2ip_cmd_ack};
assign w_b2ip_cmplt = |{Bus2IP_Mst_Cmplt, r_b2ip_cmplt};
always @ (posedge i_clk)
begin
r_b2ip_cmd_ack <= Bus2IP_Mst_CmdAck;
end
always @ (posedge i_clk)
begin
r_b2ip_cmplt <= Bus2IP_Mst_Cmplt;
end
assign IP2Bus_Data = w_slv_o_data;
genvar i;
generate
for ( i=0; i<`NUM_REG; i=i+1 ) begin : reg_select
assign w_reg_rd_sel[i] = Bus2IP_RdCE[i];
assign w_reg_wr_sel[i] = Bus2IP_WrCE[i];
end
endgenerate
always @ (*)
begin
if(Bus2IP_Addr[7])
begin
f_reg_wr_sel <= 'b0;
f_reg_rd_sel <= 'b0;
end
else
begin
f_reg_wr_sel <= w_reg_wr_sel;
f_reg_rd_sel <= w_reg_rd_sel;
end
end
generate
for ( i=0; i<`SLV_DATA_WD; i=i+1 ) begin : system_bus_d
assign w_slv_i_data[i] = Bus2IP_Data[i];
end
endgenerate
generate
for ( i=0; i<`SLV_ADDR_WD; i=i+1 ) begin : slv_addr
assign w_slv_addr[i] = Bus2IP_Addr[i];
end
endgenerate
generate
for ( i=0; i<`CIO_WD*`CH; i=i+1 ) begin : nand_dq
assign w_nand_dq_i[i] = i_nand_dq_i[i];
assign l_nand_dq_o[i] = w_nand_dq_o[i];
assign l_nand_dq_t[i] = w_nand_dq_t;
end
endgenerate
generate
for (i=0; i<(`CLST*`CH*`WAY); i=i+1) begin : nand_a
assign l_nand_ce_n[i] = w_nand_ce_n[i/`CLST];
end
for (i=0; i<(`CLST*`CH); i=i+1) begin : nand_b
assign l_nand_cle[i] = w_nand_cle;
assign l_nand_ale[i] = w_nand_ale;
assign l_nand_wp_n[i] = w_nand_wp_n;
end
endgenerate
assign l_nand_we_n = w_nand_we_n;
assign l_nand_wr_n = w_nand_wr_n;
assign w_nand_rb = i_nand_rb;
assign l_nand_dqs_t = w_nand_dqs_t;
generate
for ( i=0; i<`MST_DATA_WD; i=i+1 ) begin : data_bus_read_d
assign w_dma_i_data[i] = Bus2IP_MstRd_d [i];
end
endgenerate
generate
for(i=0;i<`MST_ADDR_WD;i=i+1)
begin : data_bus_a
assign IP2Bus_Mst_Addr[i] = w_dma_addr[i];
end
endgenerate
generate
for ( i=0; i<`DMA_LEN; i=i+1 ) begin : dma_length
assign IP2Bus_Mst_Length[i] = w_dma_length[i];
end
endgenerate
assign IP2Bus_Mst_BE = 8'hff ;
assign IP2Bus_Mst_Type = IP2Bus_MstRd_Req|IP2Bus_MstWr_Req;
assign IP2Bus_Mst_Lock = 0;
assign IP2Bus_Mst_Reset = 0;
assign IP2Bus_MstWr_d = w_dma_o_data;
assign IP2Bus_MstWr_rem = 0;
always@ (posedge i_clk) begin
r_nand_dq_o <= l_nand_dq_o;
o_nand_dq_t <= l_nand_dq_t;
o_nand_cle <= l_nand_cle;
o_nand_ale <= l_nand_ale;
o_nand_ce_n <= l_nand_ce_n;
r_nand_we_n <= l_nand_we_n;
o_nand_wr_n <= l_nand_wr_n;
o_nand_wp_n <= l_nand_wp_n;
o_nand_dqs_t <= l_nand_dqs_t;
end
assign b_nand_dq_o = r_nand_dq_o ;
always @ (posedge i_clk_200)
begin
o_nand_dq_o <= b_nand_dq_o;
end
assign o_nand_clk = (w_m_ch_cmplt) ? w_clk_o : r_nand_we_n ;
always @ (posedge i_clk)
begin
r_dqs_ce <= w_dqs_ce;
end
always@(posedge i_clk) begin
r_nand_rb <= w_nand_rb;
end
IDELAYCTRL IDELAYCTRL_INST (
.REFCLK(i_clk_200),
.RST(~i_rstn),
.RDY()
);
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (31),
.PIPE_SEL ("FALSE"),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA")
)IODELAY_INST (
.CNTVALUEOUT(),
.DATAOUT (w_nand_dqs_i),
.C (1'b0),
.CE (1'b0),
.CINVCTRL (1'b0),
.CNTVALUEIN (5'b0),
.DATAIN (1'b0),
.IDATAIN (i_nand_dqs),
.INC (1'b0),
.LD (1'b0),
.LDPIPEEN (1'b0),
.REGRST (1'b0)
);
pll_50M pll(
.CLK_IN1(i_clk),
.CLK_OUT1(w_clk_o),
.RESET(!i_rstn),
.LOCKED());
BUFGCE dqs_buf(
.O(b_nand_dqs),
.CE(!r_dqs_ce),
.I(w_clk_o));
buf buf_dqs(o_nand_dqs, b_nand_dqs);
generate
for (i=0; i<`CH; i=i+1) begin : ch_controller
ch_controller ch (
.i_bus_clk (Bus2IP_Clk ),
.i_bus_rst (~Bus2IP_Resetn),
.i_slv_rd_sel (f_reg_rd_sel[(`CH_REG+`WAY_REG*`WAY)*(i+1)-1:(`CH_REG+`WAY_REG*`WAY)*i]),
.i_slv_wr_sel (f_reg_wr_sel[(`CH_REG+`WAY_REG*`WAY)*(i+1)-1:(`CH_REG+`WAY_REG*`WAY)*i]),
.i_slv_data (w_slv_i_data),
.o_slv_data (w_slv_o_data[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.i_slv_addr (w_slv_addr),
.i_slv_rnw (Bus2IP_RNW),
.o_sp_write_ack (w_prog_sp_ack),
.o_sp_read_ack (w_read_sp_ack),
.i_slv_sp_wr_ack (w_slv_wr_ack),
.i_slv_sp_rd_ack (w_slv_rd_ack),
.i_data_clk (i_clk ),
.i_data_rst (~Bus2IP_Resetn ),
.o_dma_addr (w_dma_addr ),
.i_dma_data (w_dma_i_data ),
.o_dma_data (w_dma_o_data ),
.o_dma_length (w_dma_length ),
.o_dma_rd_req (IP2Bus_MstRd_Req ),
.o_dma_wr_req (IP2Bus_MstWr_Req ),
.i_dma_cmd_ack (w_b2ip_cmd_ack ),
.i_dma_cmplt (w_b2ip_cmplt ),
.i_dma_rd_sof_n (Bus2IP_MstRd_sof_n ),
.i_dma_rd_eof_n (Bus2IP_MstRd_eof_n ),
.i_dma_rd_src_rdy_n (Bus2IP_MstRd_src_rdy_n),
.i_dma_rd_src_dsc_n (Bus2IP_MstRd_src_dsc_n),
.o_dma_rd_dst_rdy_n (IP2Bus_MstRd_dst_rdy_n),
.o_dma_rd_dst_dsc_n (IP2Bus_MstRd_dst_dsc_n),
.o_dma_wr_sof_n (IP2Bus_MstWr_sof_n ),
.o_dma_wr_eof_n (IP2Bus_MstWr_eof_n ),
.o_dma_wr_src_rdy_n (IP2Bus_MstWr_src_rdy_n),
.o_dma_wr_src_dsc_n (IP2Bus_MstWr_src_dsc_n),
.i_dma_wr_dst_rdy_n (Bus2IP_MstWr_dst_rdy_n),
.i_dma_wr_dst_dsc_n (Bus2IP_MstWr_dst_dsc_n),
.i_nc_clk (i_clk ),
.i_nc_rstn (i_rstn),
.i_nand_dq (w_nand_dq_i[`CIO_WD*(i+1)-1:`CIO_WD*i]),
.o_nand_dq (w_nand_dq_o[`CIO_WD*(i+1)-1:`CIO_WD*i]),
.o_nand_dq_t (w_nand_dq_t[i] ),
.o_nand_cle (w_nand_cle[i] ),
.o_nand_ale (w_nand_ale[i] ),
.o_nand_ce_n (w_nand_ce_n[`WAY*(i+1)-1:`WAY*i] ),
.o_nand_we_n (w_nand_we_n[i] ),
.o_nand_wr_n (w_nand_wr_n[i] ),
.o_nand_wp_n (w_nand_wp_n[i] ),
.i_nand_rb (r_nand_rb[`WAY*(i+1)-1:`WAY*i] ),
.i_nand_dqs (w_nand_dqs_i ),
.o_nand_dqs_t (w_nand_dqs_t ),
.i_clk_o (w_clk_o ),
.o_m_ch_cmplt (w_m_ch_cmplt ),
.o_dqs_ce (w_dqs_ce ),
.o_prog_start (o_prog_start ),
.o_prog_end (o_prog_end ),
.o_read_start (o_read_start ),
.o_read_end (o_read_end ),
.o_erase_start (o_erase_start ),
.o_erase_end (o_erase_end ),
.o_op_fail (o_op_fail )
);
end
endgenerate
endmodule | module ipif #(
parameter C_SLV_DWIDTH = `SLV_DATA_WD,
parameter C_MST_AWIDTH = `MST_ADDR_WD,
parameter C_MST_DWIDTH = `MST_DATA_WD,
parameter C_NUM_REG = `NUM_REG+2,
parameter C_NUM_INTR = 1
)(
input wire Bus2IP_Clk,
input wire Bus2IP_Resetn,
input wire [`SLV_ADDR_WD -1:0] Bus2IP_Addr,
input wire [C_SLV_DWIDTH -1:0] Bus2IP_Data,
input wire Bus2IP_RNW,
input wire [C_SLV_DWIDTH/8 -1:0] Bus2IP_BE,
input wire [C_NUM_REG -1:0] Bus2IP_RdCE,
input wire [C_NUM_REG -1:0] Bus2IP_WrCE,
output wire [C_SLV_DWIDTH -1:0] IP2Bus_Data,
output wire IP2Bus_RdAck,
output wire IP2Bus_WrAck,
output wire IP2Bus_Error,
output wire IP2Bus_MstRd_Req,
output wire IP2Bus_MstWr_Req,
output wire [C_MST_AWIDTH -1:0] IP2Bus_Mst_Addr,
output wire [C_MST_DWIDTH/8 -1:0] IP2Bus_Mst_BE,
output wire [`DMA_LEN-1 :0] IP2Bus_Mst_Length,
output wire IP2Bus_Mst_Type,
output wire IP2Bus_Mst_Lock,
output wire IP2Bus_Mst_Reset,
input wire Bus2IP_Mst_CmdAck,
input wire Bus2IP_Mst_Cmplt,
input wire Bus2IP_Mst_Error,
input wire Bus2IP_Mst_Rearbitrate,
input wire Bus2IP_Mst_Cmd_Timeout,
input wire [C_MST_DWIDTH -1:0] Bus2IP_MstRd_d,
input wire [C_MST_DWIDTH/8 -1:0] Bus2IP_MstRd_rem,
input wire Bus2IP_MstRd_sof_n,
input wire Bus2IP_MstRd_eof_n,
input wire Bus2IP_MstRd_src_rdy_n,
input wire Bus2IP_MstRd_src_dsc_n,
output wire IP2Bus_MstRd_dst_rdy_n,
output wire IP2Bus_MstRd_dst_dsc_n,
output wire [C_MST_DWIDTH -1:0] IP2Bus_MstWr_d,
output wire [C_MST_DWIDTH/8 -1:0] IP2Bus_MstWr_rem,
output wire IP2Bus_MstWr_sof_n,
output wire IP2Bus_MstWr_eof_n,
output wire IP2Bus_MstWr_src_rdy_n,
output wire IP2Bus_MstWr_src_dsc_n,
input wire Bus2IP_MstWr_dst_rdy_n,
input wire Bus2IP_MstWr_dst_dsc_n,
input wire i_clk ,
input wire i_clk_200 ,
input wire i_rstn ,
input wire [`CIO_WD*`CH-1:0] i_nand_dq_i ,
output reg [`CIO_WD*`CH-1:0] o_nand_dq_o ,
output reg [`CIO_WD*`CH-1:0] o_nand_dq_t ,
output reg o_nand_cle ,
output reg o_nand_ale ,
output reg [`CLST*`CH*`WAY-1:0] o_nand_ce_n ,
output wire o_nand_clk ,
output reg o_nand_wr_n ,
output reg o_nand_wp_n ,
input wire [`CLST*`CH*`WAY-1:0] i_nand_rb ,
input wire i_nand_dqs ,
output wire o_nand_dqs ,
output reg o_nand_dqs_t,
output wire [`WAY-1:0] o_prog_start ,
output wire [`WAY-1:0] o_prog_end ,
output wire [`WAY-1:0] o_read_start ,
output wire [`WAY-1:0] o_read_end ,
output wire [`WAY-1:0] o_erase_start,
output wire [`WAY-1:0] o_erase_end ,
output wire [`WAY-1:0] o_op_fail
); |
wire [`SLV_DATA_WD-1 :0] w_slv_i_data;
wire [`SLV_DATA_WD-1:0] w_slv_o_data;
wire [`SLV_ADDR_WD-1:0] w_slv_addr;
wire [`MST_ADDR_WD-1:0] w_dma_addr;
wire [`DMA_LEN-1:0] w_dma_length;
wire [`MST_DATA_WD-1:0] w_dma_i_data;
wire [`MST_DATA_WD-1:0] w_dma_o_data;
wire [`CIO_WD*`CH-1:0] l_nand_dq_o;
wire [`CIO_WD*`CH-1:0] l_nand_dq_t;
wire [`CLST*`CH-1:0] l_nand_cle;
wire [`CLST*`CH-1:0] l_nand_ale;
wire [`CLST*`CH*`WAY-1:0] l_nand_ce_n;
wire [`CLST*`CH-1:0] l_nand_we_n;
wire [`CLST*`CH-1:0] l_nand_wr_n;
wire [`CLST*`CH-1:0] l_nand_wp_n;
wire [`CIO_WD*`CH-1:0] w_nand_dq_i;
wire [`CIO_WD*`CH-1:0] w_nand_dq_o;
wire [`CIO_WD*`CH-1:0] b_nand_dq_o;
wire [`CH-1:0] w_nand_dq_t;
wire [`CH-1:0] w_nand_cle ;
wire [`CH-1:0] w_nand_ale ;
wire [`CH*`WAY-1:0] w_nand_ce_n;
wire [`CH-1:0] w_nand_we_n;
wire [`CH-1:0] w_nand_wr_n;
wire [`CH-1:0] w_nand_wp_n;
wire [`CH*`WAY-1:0] w_nand_rb;
reg [`CH*`WAY-1:0] r_nand_rb;
reg [`CIO_WD*`CH-1:0] r_nand_dq_o;
reg [`CH-1:0] r_nand_we_n;
wire w_nand_dqs_i;
wire l_nand_dqs_t;
wire [`CH-1:0] w_nand_dqs_t;
wire b_nand_dqs;
wire w_clk_o;
wire [`CH-1:0] w_m_ch_cmplt;
wire w_dqs_ce;
reg r_dqs_ce;
wire w_read_sp_ack;
wire w_prog_sp_ack;
wire w_slv_wr_ack;
wire w_slv_rd_ack;
reg r_b2ip_cmd_ack;
wire w_b2ip_cmd_ack;
reg r_b2ip_cmplt;
wire w_b2ip_cmplt;
wire [`NUM_REG-1:0] w_reg_rd_sel;
wire [`NUM_REG-1:0] w_reg_wr_sel;
reg [`NUM_REG-1:0] f_reg_rd_sel;
reg [`NUM_REG-1:0] f_reg_wr_sel;
assign IP2Bus_WrAck = |{f_reg_wr_sel, w_prog_sp_ack};
assign IP2Bus_RdAck = |{f_reg_rd_sel, w_read_sp_ack};
assign IP2Bus_Error = 0;
assign w_slv_wr_ack = |{w_reg_wr_sel};
assign w_slv_rd_ack = |{w_reg_rd_sel};
assign w_b2ip_cmd_ack = |{Bus2IP_Mst_CmdAck, r_b2ip_cmd_ack};
assign w_b2ip_cmplt = |{Bus2IP_Mst_Cmplt, r_b2ip_cmplt};
always @ (posedge i_clk)
begin
r_b2ip_cmd_ack <= Bus2IP_Mst_CmdAck;
end
always @ (posedge i_clk)
begin
r_b2ip_cmplt <= Bus2IP_Mst_Cmplt;
end
assign IP2Bus_Data = w_slv_o_data;
genvar i;
generate
for ( i=0; i<`NUM_REG; i=i+1 ) begin : reg_select
assign w_reg_rd_sel[i] = Bus2IP_RdCE[i];
assign w_reg_wr_sel[i] = Bus2IP_WrCE[i];
end
endgenerate
always @ (*)
begin
if(Bus2IP_Addr[7])
begin
f_reg_wr_sel <= 'b0;
f_reg_rd_sel <= 'b0;
end
else
begin
f_reg_wr_sel <= w_reg_wr_sel;
f_reg_rd_sel <= w_reg_rd_sel;
end
end
generate
for ( i=0; i<`SLV_DATA_WD; i=i+1 ) begin : system_bus_d
assign w_slv_i_data[i] = Bus2IP_Data[i];
end
endgenerate
generate
for ( i=0; i<`SLV_ADDR_WD; i=i+1 ) begin : slv_addr
assign w_slv_addr[i] = Bus2IP_Addr[i];
end
endgenerate
generate
for ( i=0; i<`CIO_WD*`CH; i=i+1 ) begin : nand_dq
assign w_nand_dq_i[i] = i_nand_dq_i[i];
assign l_nand_dq_o[i] = w_nand_dq_o[i];
assign l_nand_dq_t[i] = w_nand_dq_t;
end
endgenerate
generate
for (i=0; i<(`CLST*`CH*`WAY); i=i+1) begin : nand_a
assign l_nand_ce_n[i] = w_nand_ce_n[i/`CLST];
end
for (i=0; i<(`CLST*`CH); i=i+1) begin : nand_b
assign l_nand_cle[i] = w_nand_cle;
assign l_nand_ale[i] = w_nand_ale;
assign l_nand_wp_n[i] = w_nand_wp_n;
end
endgenerate
assign l_nand_we_n = w_nand_we_n;
assign l_nand_wr_n = w_nand_wr_n;
assign w_nand_rb = i_nand_rb;
assign l_nand_dqs_t = w_nand_dqs_t;
generate
for ( i=0; i<`MST_DATA_WD; i=i+1 ) begin : data_bus_read_d
assign w_dma_i_data[i] = Bus2IP_MstRd_d [i];
end
endgenerate
generate
for(i=0;i<`MST_ADDR_WD;i=i+1)
begin : data_bus_a
assign IP2Bus_Mst_Addr[i] = w_dma_addr[i];
end
endgenerate
generate
for ( i=0; i<`DMA_LEN; i=i+1 ) begin : dma_length
assign IP2Bus_Mst_Length[i] = w_dma_length[i];
end
endgenerate
assign IP2Bus_Mst_BE = 8'hff ;
assign IP2Bus_Mst_Type = IP2Bus_MstRd_Req|IP2Bus_MstWr_Req;
assign IP2Bus_Mst_Lock = 0;
assign IP2Bus_Mst_Reset = 0;
assign IP2Bus_MstWr_d = w_dma_o_data;
assign IP2Bus_MstWr_rem = 0;
always@ (posedge i_clk) begin
r_nand_dq_o <= l_nand_dq_o;
o_nand_dq_t <= l_nand_dq_t;
o_nand_cle <= l_nand_cle;
o_nand_ale <= l_nand_ale;
o_nand_ce_n <= l_nand_ce_n;
r_nand_we_n <= l_nand_we_n;
o_nand_wr_n <= l_nand_wr_n;
o_nand_wp_n <= l_nand_wp_n;
o_nand_dqs_t <= l_nand_dqs_t;
end
assign b_nand_dq_o = r_nand_dq_o ;
always @ (posedge i_clk_200)
begin
o_nand_dq_o <= b_nand_dq_o;
end
assign o_nand_clk = (w_m_ch_cmplt) ? w_clk_o : r_nand_we_n ;
always @ (posedge i_clk)
begin
r_dqs_ce <= w_dqs_ce;
end
always@(posedge i_clk) begin
r_nand_rb <= w_nand_rb;
end
IDELAYCTRL IDELAYCTRL_INST (
.REFCLK(i_clk_200),
.RST(~i_rstn),
.RDY()
);
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (31),
.PIPE_SEL ("FALSE"),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA")
)IODELAY_INST (
.CNTVALUEOUT(),
.DATAOUT (w_nand_dqs_i),
.C (1'b0),
.CE (1'b0),
.CINVCTRL (1'b0),
.CNTVALUEIN (5'b0),
.DATAIN (1'b0),
.IDATAIN (i_nand_dqs),
.INC (1'b0),
.LD (1'b0),
.LDPIPEEN (1'b0),
.REGRST (1'b0)
);
pll_50M pll(
.CLK_IN1(i_clk),
.CLK_OUT1(w_clk_o),
.RESET(!i_rstn),
.LOCKED());
BUFGCE dqs_buf(
.O(b_nand_dqs),
.CE(!r_dqs_ce),
.I(w_clk_o));
buf buf_dqs(o_nand_dqs, b_nand_dqs);
generate
for (i=0; i<`CH; i=i+1) begin : ch_controller
ch_controller ch (
.i_bus_clk (Bus2IP_Clk ),
.i_bus_rst (~Bus2IP_Resetn),
.i_slv_rd_sel (f_reg_rd_sel[(`CH_REG+`WAY_REG*`WAY)*(i+1)-1:(`CH_REG+`WAY_REG*`WAY)*i]),
.i_slv_wr_sel (f_reg_wr_sel[(`CH_REG+`WAY_REG*`WAY)*(i+1)-1:(`CH_REG+`WAY_REG*`WAY)*i]),
.i_slv_data (w_slv_i_data),
.o_slv_data (w_slv_o_data[`SLV_DATA_WD*(i+1)-1:`SLV_DATA_WD*i]),
.i_slv_addr (w_slv_addr),
.i_slv_rnw (Bus2IP_RNW),
.o_sp_write_ack (w_prog_sp_ack),
.o_sp_read_ack (w_read_sp_ack),
.i_slv_sp_wr_ack (w_slv_wr_ack),
.i_slv_sp_rd_ack (w_slv_rd_ack),
.i_data_clk (i_clk ),
.i_data_rst (~Bus2IP_Resetn ),
.o_dma_addr (w_dma_addr ),
.i_dma_data (w_dma_i_data ),
.o_dma_data (w_dma_o_data ),
.o_dma_length (w_dma_length ),
.o_dma_rd_req (IP2Bus_MstRd_Req ),
.o_dma_wr_req (IP2Bus_MstWr_Req ),
.i_dma_cmd_ack (w_b2ip_cmd_ack ),
.i_dma_cmplt (w_b2ip_cmplt ),
.i_dma_rd_sof_n (Bus2IP_MstRd_sof_n ),
.i_dma_rd_eof_n (Bus2IP_MstRd_eof_n ),
.i_dma_rd_src_rdy_n (Bus2IP_MstRd_src_rdy_n),
.i_dma_rd_src_dsc_n (Bus2IP_MstRd_src_dsc_n),
.o_dma_rd_dst_rdy_n (IP2Bus_MstRd_dst_rdy_n),
.o_dma_rd_dst_dsc_n (IP2Bus_MstRd_dst_dsc_n),
.o_dma_wr_sof_n (IP2Bus_MstWr_sof_n ),
.o_dma_wr_eof_n (IP2Bus_MstWr_eof_n ),
.o_dma_wr_src_rdy_n (IP2Bus_MstWr_src_rdy_n),
.o_dma_wr_src_dsc_n (IP2Bus_MstWr_src_dsc_n),
.i_dma_wr_dst_rdy_n (Bus2IP_MstWr_dst_rdy_n),
.i_dma_wr_dst_dsc_n (Bus2IP_MstWr_dst_dsc_n),
.i_nc_clk (i_clk ),
.i_nc_rstn (i_rstn),
.i_nand_dq (w_nand_dq_i[`CIO_WD*(i+1)-1:`CIO_WD*i]),
.o_nand_dq (w_nand_dq_o[`CIO_WD*(i+1)-1:`CIO_WD*i]),
.o_nand_dq_t (w_nand_dq_t[i] ),
.o_nand_cle (w_nand_cle[i] ),
.o_nand_ale (w_nand_ale[i] ),
.o_nand_ce_n (w_nand_ce_n[`WAY*(i+1)-1:`WAY*i] ),
.o_nand_we_n (w_nand_we_n[i] ),
.o_nand_wr_n (w_nand_wr_n[i] ),
.o_nand_wp_n (w_nand_wp_n[i] ),
.i_nand_rb (r_nand_rb[`WAY*(i+1)-1:`WAY*i] ),
.i_nand_dqs (w_nand_dqs_i ),
.o_nand_dqs_t (w_nand_dqs_t ),
.i_clk_o (w_clk_o ),
.o_m_ch_cmplt (w_m_ch_cmplt ),
.o_dqs_ce (w_dqs_ce ),
.o_prog_start (o_prog_start ),
.o_prog_end (o_prog_end ),
.o_read_start (o_read_start ),
.o_read_end (o_read_end ),
.o_erase_start (o_erase_start ),
.o_erase_end (o_erase_end ),
.o_op_fail (o_op_fail )
);
end
endgenerate
endmodule | 25 |
137,325 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/partial_FFM_gate.v | 77,907,036 | partial_FFM_gate.v | v | 88 | 84 | [] | ['general public license', 'free software foundation'] | [] | [(56, 87)] | null | data/verilator_xmls/eb4ddd62-de2e-4660-a253-839686a899c2.xml | null | 295,905 | module | module partial_FFM_gate(
a,
b,
r
);
input wire [4:0] a;
input wire [4:0] b;
output wire [8:0] r;
assign r[8] = (a[4]&b[4]);
assign r[7] = (a[3]&b[4]) ^ (a[4]&b[3]);
assign r[6] = (a[2]&b[4]) ^ (a[3]&b[3]) ^ (a[4]&b[2]);
assign r[5] = (a[1]&b[4]) ^ (a[2]&b[3]) ^ (a[3]&b[2]) ^ (a[4]&b[1]);
assign r[4] = (a[0]&b[4]) ^ (a[1]&b[3]) ^ (a[2]&b[2]) ^ (a[3]&b[1]) ^ (a[4]&b[0]);
assign r[3] = (a[0]&b[3]) ^ (a[1]&b[2]) ^ (a[2]&b[1]) ^ (a[3]&b[0]);
assign r[2] = (a[0]&b[2]) ^ (a[1]&b[1]) ^ (a[2]&b[0]);
assign r[1] = (a[0]&b[1]) ^ (a[1]&b[0]);
assign r[0] = (a[0]&b[0]);
endmodule | module partial_FFM_gate(
a,
b,
r
); |
input wire [4:0] a;
input wire [4:0] b;
output wire [8:0] r;
assign r[8] = (a[4]&b[4]);
assign r[7] = (a[3]&b[4]) ^ (a[4]&b[3]);
assign r[6] = (a[2]&b[4]) ^ (a[3]&b[3]) ^ (a[4]&b[2]);
assign r[5] = (a[1]&b[4]) ^ (a[2]&b[3]) ^ (a[3]&b[2]) ^ (a[4]&b[1]);
assign r[4] = (a[0]&b[4]) ^ (a[1]&b[3]) ^ (a[2]&b[2]) ^ (a[3]&b[1]) ^ (a[4]&b[0]);
assign r[3] = (a[0]&b[3]) ^ (a[1]&b[2]) ^ (a[2]&b[1]) ^ (a[3]&b[0]);
assign r[2] = (a[0]&b[2]) ^ (a[1]&b[1]) ^ (a[2]&b[0]);
assign r[1] = (a[0]&b[1]) ^ (a[1]&b[0]);
assign r[0] = (a[0]&b[0]);
endmodule | 25 |
137,326 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_DC_NMLodr.v | 77,907,036 | PE_DC_NMLodr.v | v | 197 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(62, 196)] | null | null | 1: b"%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_DC_NMLodr.v:186: Cannot find file containing module: 'parallel_FFM_gate'\n parallel_FFM_gate S_in_FFM_v_2i_X (\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parallel_FFM_gate\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parallel_FFM_gate.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parallel_FFM_gate.sv\n parallel_FFM_gate\n parallel_FFM_gate.v\n parallel_FFM_gate.sv\n obj_dir/parallel_FFM_gate\n obj_dir/parallel_FFM_gate.v\n obj_dir/parallel_FFM_gate.sv\n%Error: Exiting due to 1 error(s)\n" | 295,907 | module | module PE_DC_NMLodr(
clk,
nRESET_KES,
EXECUTE_PE_DC,
S_in,
v_2i_X,
S_out,
coef_2ip1
);
parameter GF_ORDER = 15;
parameter [14:0] VALUE_ZERO = 15'b00000_00000_00000;
parameter [14:0] VALUE_ONE = 15'b00000_00000_00001;
input wire clk;
input wire nRESET_KES;
input wire EXECUTE_PE_DC;
input wire [GF_ORDER-1:0] S_in;
input wire [GF_ORDER-1:0] v_2i_X;
output wire [GF_ORDER-1:0] S_out;
output reg [GF_ORDER-1:0] coef_2ip1;
reg [GF_ORDER-1:0] S_in_b;
reg [GF_ORDER-1:0] v_2i_X_b;
wire [GF_ORDER-1:0] coef_term;
parameter PE_DC_RST = 3'b001;
parameter PE_DC_INP = 3'b010;
parameter PE_DC_OUT = 3'b100;
reg [2:0] cur_state;
reg [2:0] nxt_state;
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
cur_state <= PE_DC_RST;
end else begin
cur_state <= nxt_state;
end
end
always @ ( * )
begin
case (cur_state)
PE_DC_RST: begin
nxt_state <= (EXECUTE_PE_DC)? (PE_DC_INP):(PE_DC_RST);
end
PE_DC_INP: begin
nxt_state <= PE_DC_OUT;
end
PE_DC_OUT: begin
nxt_state <= PE_DC_RST;
end
default: begin
nxt_state <= PE_DC_RST;
end
endcase
end
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
S_in_b <= 0;
v_2i_X_b <= 0;
coef_2ip1[GF_ORDER-1:0] <= VALUE_ZERO[GF_ORDER-1:0];
end
else begin
case (nxt_state)
PE_DC_RST: begin
S_in_b <= S_in_b;
v_2i_X_b <= v_2i_X_b;
coef_2ip1[GF_ORDER-1:0] <= coef_2ip1[GF_ORDER-1:0];
end
PE_DC_INP: begin
S_in_b <= S_in;
v_2i_X_b <= v_2i_X;
coef_2ip1[GF_ORDER-1:0] <= coef_2ip1[GF_ORDER-1:0];
end
PE_DC_OUT: begin
S_in_b <= S_in_b;
v_2i_X_b <= v_2i_X_b;
coef_2ip1[GF_ORDER-1:0] <= coef_term[GF_ORDER-1:0];
end
default: begin
S_in_b <= S_in_b;
v_2i_X_b <= v_2i_X_b;
coef_2ip1[GF_ORDER-1:0] <= coef_2ip1[GF_ORDER-1:0];
end
endcase
end
end
parallel_FFM_gate S_in_FFM_v_2i_X (
.poly_form_A(S_in_b[GF_ORDER-1:0]),
.poly_form_B(v_2i_X_b[GF_ORDER-1:0]),
.poly_form_result(coef_term[GF_ORDER-1:0]));
assign S_out[GF_ORDER-1:0] = S_in_b[GF_ORDER-1:0];
endmodule | module PE_DC_NMLodr(
clk,
nRESET_KES,
EXECUTE_PE_DC,
S_in,
v_2i_X,
S_out,
coef_2ip1
); |
parameter GF_ORDER = 15;
parameter [14:0] VALUE_ZERO = 15'b00000_00000_00000;
parameter [14:0] VALUE_ONE = 15'b00000_00000_00001;
input wire clk;
input wire nRESET_KES;
input wire EXECUTE_PE_DC;
input wire [GF_ORDER-1:0] S_in;
input wire [GF_ORDER-1:0] v_2i_X;
output wire [GF_ORDER-1:0] S_out;
output reg [GF_ORDER-1:0] coef_2ip1;
reg [GF_ORDER-1:0] S_in_b;
reg [GF_ORDER-1:0] v_2i_X_b;
wire [GF_ORDER-1:0] coef_term;
parameter PE_DC_RST = 3'b001;
parameter PE_DC_INP = 3'b010;
parameter PE_DC_OUT = 3'b100;
reg [2:0] cur_state;
reg [2:0] nxt_state;
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
cur_state <= PE_DC_RST;
end else begin
cur_state <= nxt_state;
end
end
always @ ( * )
begin
case (cur_state)
PE_DC_RST: begin
nxt_state <= (EXECUTE_PE_DC)? (PE_DC_INP):(PE_DC_RST);
end
PE_DC_INP: begin
nxt_state <= PE_DC_OUT;
end
PE_DC_OUT: begin
nxt_state <= PE_DC_RST;
end
default: begin
nxt_state <= PE_DC_RST;
end
endcase
end
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
S_in_b <= 0;
v_2i_X_b <= 0;
coef_2ip1[GF_ORDER-1:0] <= VALUE_ZERO[GF_ORDER-1:0];
end
else begin
case (nxt_state)
PE_DC_RST: begin
S_in_b <= S_in_b;
v_2i_X_b <= v_2i_X_b;
coef_2ip1[GF_ORDER-1:0] <= coef_2ip1[GF_ORDER-1:0];
end
PE_DC_INP: begin
S_in_b <= S_in;
v_2i_X_b <= v_2i_X;
coef_2ip1[GF_ORDER-1:0] <= coef_2ip1[GF_ORDER-1:0];
end
PE_DC_OUT: begin
S_in_b <= S_in_b;
v_2i_X_b <= v_2i_X_b;
coef_2ip1[GF_ORDER-1:0] <= coef_term[GF_ORDER-1:0];
end
default: begin
S_in_b <= S_in_b;
v_2i_X_b <= v_2i_X_b;
coef_2ip1[GF_ORDER-1:0] <= coef_2ip1[GF_ORDER-1:0];
end
endcase
end
end
parallel_FFM_gate S_in_FFM_v_2i_X (
.poly_form_A(S_in_b[GF_ORDER-1:0]),
.poly_form_B(v_2i_X_b[GF_ORDER-1:0]),
.poly_form_result(coef_term[GF_ORDER-1:0]));
assign S_out[GF_ORDER-1:0] = S_in_b[GF_ORDER-1:0];
endmodule | 25 |
137,327 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_ELU_MINodr.v | 77,907,036 | PE_ELU_MINodr.v | v | 257 | 108 | [] | ['general public license', 'free software foundation'] | [] | [(62, 256)] | null | null | 1: b"%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_ELU_MINodr.v:239: Cannot find file containing module: 'parallel_FFM_gate'\n parallel_FFM_gate delta_2im2_FFM_v_2i_X (\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parallel_FFM_gate\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parallel_FFM_gate.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parallel_FFM_gate.sv\n parallel_FFM_gate\n parallel_FFM_gate.v\n parallel_FFM_gate.sv\n obj_dir/parallel_FFM_gate\n obj_dir/parallel_FFM_gate.v\n obj_dir/parallel_FFM_gate.sv\n%Error: Exiting due to 1 error(s)\n" | 295,909 | module | module PE_ELU_MINodr(
clk,
nRESET_KES,
EXECUTE_PE_ELU,
delta_2im2,
v_2i_X,
v_2i_X_deg_chk_bit,
k_2i_X
);
parameter GF_ORDER = 15;
parameter [14:0] VALUE_ZERO = 15'b00000_00000_00000;
parameter [14:0] VALUE_ONE = 15'b00000_00000_00001;
input wire clk;
input wire nRESET_KES;
input wire EXECUTE_PE_ELU;
input wire [GF_ORDER-1:0] delta_2im2;
output reg [GF_ORDER-1:0] v_2i_X;
output reg v_2i_X_deg_chk_bit;
output reg [GF_ORDER-1:0] k_2i_X;
reg [GF_ORDER-1:0] delta_2im2_b;
wire [GF_ORDER-1:0] v_2ip2_X_term_A;
wire [GF_ORDER-1:0] v_2ip2_X;
wire [GF_ORDER-1:0] k_2ip2_X;
parameter PE_ELU_RST = 3'b001;
parameter PE_ELU_INP = 3'b010;
parameter PE_ELU_OUT = 3'b100;
reg [2:0] cur_state;
reg [2:0] nxt_state;
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
cur_state <= PE_ELU_RST;
end else begin
cur_state <= nxt_state;
end
end
always @ ( * )
begin
case (cur_state)
PE_ELU_RST: begin
nxt_state <= (EXECUTE_PE_ELU)? (PE_ELU_INP):(PE_ELU_RST);
end
PE_ELU_INP: begin
nxt_state <= PE_ELU_OUT;
end
PE_ELU_OUT: begin
nxt_state <= PE_ELU_RST;
end
default: begin
nxt_state <= PE_ELU_RST;
end
endcase
end
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
delta_2im2_b <= 0;
v_2i_X[GF_ORDER-1:0] <= VALUE_ONE[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= 1;
k_2i_X[GF_ORDER-1:0] <= VALUE_ONE[GF_ORDER-1:0];
end
else begin
case (nxt_state)
PE_ELU_RST: begin
delta_2im2_b <= delta_2im2_b;
v_2i_X[GF_ORDER-1:0] <= v_2i_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= v_2i_X_deg_chk_bit;
k_2i_X[GF_ORDER-1:0] <= k_2i_X[GF_ORDER-1:0];
end
PE_ELU_INP: begin
delta_2im2_b <= delta_2im2;
v_2i_X[GF_ORDER-1:0] <= v_2i_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= v_2i_X_deg_chk_bit;
k_2i_X[GF_ORDER-1:0] <= k_2i_X[GF_ORDER-1:0];
end
PE_ELU_OUT: begin
delta_2im2_b <= delta_2im2_b;
v_2i_X[GF_ORDER-1:0] <= v_2ip2_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= |(v_2ip2_X[GF_ORDER-1:0]);
k_2i_X[GF_ORDER-1:0] <= k_2ip2_X[GF_ORDER-1:0];
end
default: begin
delta_2im2_b <= delta_2im2_b;
v_2i_X[GF_ORDER-1:0] <= v_2i_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= v_2i_X_deg_chk_bit;
k_2i_X[GF_ORDER-1:0] <= k_2i_X[GF_ORDER-1:0];
end
endcase
end
end
parallel_FFM_gate delta_2im2_FFM_v_2i_X (
.poly_form_A(delta_2im2_b[GF_ORDER-1:0]),
.poly_form_B(v_2i_X[GF_ORDER-1:0]),
.poly_form_result(v_2ip2_X_term_A[GF_ORDER-1:0]));
assign v_2ip2_X[GF_ORDER-1:0] = v_2ip2_X_term_A[GF_ORDER-1:0];
assign k_2ip2_X[GF_ORDER-1:0] = VALUE_ZERO[GF_ORDER-1:0];
endmodule | module PE_ELU_MINodr(
clk,
nRESET_KES,
EXECUTE_PE_ELU,
delta_2im2,
v_2i_X,
v_2i_X_deg_chk_bit,
k_2i_X
); |
parameter GF_ORDER = 15;
parameter [14:0] VALUE_ZERO = 15'b00000_00000_00000;
parameter [14:0] VALUE_ONE = 15'b00000_00000_00001;
input wire clk;
input wire nRESET_KES;
input wire EXECUTE_PE_ELU;
input wire [GF_ORDER-1:0] delta_2im2;
output reg [GF_ORDER-1:0] v_2i_X;
output reg v_2i_X_deg_chk_bit;
output reg [GF_ORDER-1:0] k_2i_X;
reg [GF_ORDER-1:0] delta_2im2_b;
wire [GF_ORDER-1:0] v_2ip2_X_term_A;
wire [GF_ORDER-1:0] v_2ip2_X;
wire [GF_ORDER-1:0] k_2ip2_X;
parameter PE_ELU_RST = 3'b001;
parameter PE_ELU_INP = 3'b010;
parameter PE_ELU_OUT = 3'b100;
reg [2:0] cur_state;
reg [2:0] nxt_state;
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
cur_state <= PE_ELU_RST;
end else begin
cur_state <= nxt_state;
end
end
always @ ( * )
begin
case (cur_state)
PE_ELU_RST: begin
nxt_state <= (EXECUTE_PE_ELU)? (PE_ELU_INP):(PE_ELU_RST);
end
PE_ELU_INP: begin
nxt_state <= PE_ELU_OUT;
end
PE_ELU_OUT: begin
nxt_state <= PE_ELU_RST;
end
default: begin
nxt_state <= PE_ELU_RST;
end
endcase
end
always @ (posedge clk, negedge nRESET_KES)
begin
if (!nRESET_KES) begin
delta_2im2_b <= 0;
v_2i_X[GF_ORDER-1:0] <= VALUE_ONE[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= 1;
k_2i_X[GF_ORDER-1:0] <= VALUE_ONE[GF_ORDER-1:0];
end
else begin
case (nxt_state)
PE_ELU_RST: begin
delta_2im2_b <= delta_2im2_b;
v_2i_X[GF_ORDER-1:0] <= v_2i_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= v_2i_X_deg_chk_bit;
k_2i_X[GF_ORDER-1:0] <= k_2i_X[GF_ORDER-1:0];
end
PE_ELU_INP: begin
delta_2im2_b <= delta_2im2;
v_2i_X[GF_ORDER-1:0] <= v_2i_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= v_2i_X_deg_chk_bit;
k_2i_X[GF_ORDER-1:0] <= k_2i_X[GF_ORDER-1:0];
end
PE_ELU_OUT: begin
delta_2im2_b <= delta_2im2_b;
v_2i_X[GF_ORDER-1:0] <= v_2ip2_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= |(v_2ip2_X[GF_ORDER-1:0]);
k_2i_X[GF_ORDER-1:0] <= k_2ip2_X[GF_ORDER-1:0];
end
default: begin
delta_2im2_b <= delta_2im2_b;
v_2i_X[GF_ORDER-1:0] <= v_2i_X[GF_ORDER-1:0];
v_2i_X_deg_chk_bit <= v_2i_X_deg_chk_bit;
k_2i_X[GF_ORDER-1:0] <= k_2i_X[GF_ORDER-1:0];
end
endcase
end
end
parallel_FFM_gate delta_2im2_FFM_v_2i_X (
.poly_form_A(delta_2im2_b[GF_ORDER-1:0]),
.poly_form_B(v_2i_X[GF_ORDER-1:0]),
.poly_form_result(v_2ip2_X_term_A[GF_ORDER-1:0]));
assign v_2ip2_X[GF_ORDER-1:0] = v_2ip2_X_term_A[GF_ORDER-1:0];
assign k_2ip2_X[GF_ORDER-1:0] = VALUE_ZERO[GF_ORDER-1:0];
endmodule | 25 |
137,328 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/serial_m_lfs_XOR.v | 77,907,036 | serial_m_lfs_XOR.v | v | 104 | 518 | [] | ['general public license', 'free software foundation'] | [] | [(56, 103)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/serial_m_lfs_XOR.v:64: Little bit endian vector: MSB < LSB of bit range: 0:480\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 295,918 | module | module serial_m_lfs_XOR(
message,
cur_parity,
nxt_parity
);
parameter PARITY_LENGTH = 480;
parameter [0:480] GEN_POLY = 481'b1101110100111011110100011101111000110111110010101100101011111101110111010100110000000000010111101011010011101011011100000101000100101001101111111111011000010010011111000111110001110101101011100111000011010000110000010000110001010001000100101101100110011011000000011110110011111101010010010000001011110001110101110100100000100101010101011110111111000110111011001100111100101110000111000011000011010100110000001100001101111100101111000111001101001100111100001001001100011111010011101;
input wire message;
input wire [PARITY_LENGTH-1:0] cur_parity;
output wire [PARITY_LENGTH-1:0] nxt_parity;
wire FB_term;
assign FB_term = message ^ cur_parity[PARITY_LENGTH-1];
assign nxt_parity[0] = FB_term;
genvar i;
generate
for (i=1; i<PARITY_LENGTH; i=i+1)
begin: linear_function
if (GEN_POLY[i] == 1)
begin
assign nxt_parity[i] = cur_parity[i-1] ^ FB_term;
end
else
begin
assign nxt_parity[i] = cur_parity[i-1];
end
end
endgenerate
endmodule | module serial_m_lfs_XOR(
message,
cur_parity,
nxt_parity
); |
parameter PARITY_LENGTH = 480;
parameter [0:480] GEN_POLY = 481'b1101110100111011110100011101111000110111110010101100101011111101110111010100110000000000010111101011010011101011011100000101000100101001101111111111011000010010011111000111110001110101101011100111000011010000110000010000110001010001000100101101100110011011000000011110110011111101010010010000001011110001110101110100100000100101010101011110111111000110111011001100111100101110000111000011000011010100110000001100001101111100101111000111001101001100111100001001001100011111010011101;
input wire message;
input wire [PARITY_LENGTH-1:0] cur_parity;
output wire [PARITY_LENGTH-1:0] nxt_parity;
wire FB_term;
assign FB_term = message ^ cur_parity[PARITY_LENGTH-1];
assign nxt_parity[0] = FB_term;
genvar i;
generate
for (i=1; i<PARITY_LENGTH; i=i+1)
begin: linear_function
if (GEN_POLY[i] == 1)
begin
assign nxt_parity[i] = cur_parity[i-1] ^ FB_term;
end
else
begin
assign nxt_parity[i] = cur_parity[i-1];
end
end
endgenerate
endmodule | 25 |
137,329 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v | 77,907,036 | sync_op.v | v | 901 | 144 | [] | ['general public license', 'free software foundation'] | [] | [(219, 1064)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:53: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:63: Define or directive not defined: \'`CMD_WD\'\n input wire [`CMD_WD-1:0] i_command ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:64: Define or directive not defined: \'`NADDR_WD\'\n input wire [`NADDR_WD-1:0] i_nand_addr ,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:84: Define or directive not defined: \'`CIO_WD\'\n output wire [`CIO_WD-1:0] o_op_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:120: Define or directive not defined: \'`CMD_WD\'\n wire [`CMD_WD-1:0] t_CMD ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:121: Define or directive not defined: \'`NADDR_WD\'\n wire [`NADDR_WD-1:0] t_ADDR ;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:122: Define or directive not defined: \'`IO_WD\'\n reg [`IO_WD-1 :0] r_op_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:126: Define or directive not defined: \'`CLST\'\n for (i=0 ; i<`CLST ; i=i+1) \n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:126: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0 ; i<`CLST ; i=i+1) \n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:128: Define or directive not defined: \'`IO_WD\'\n assign o_op_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_op_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:128: Define or directive not defined: \'`IO_WD\'\n assign o_op_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_op_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v:900: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n' | 295,919 | module | module sync_op(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_enable ,
input wire [`CMD_WD-1:0] i_command ,
input wire [`NADDR_WD-1:0] i_nand_addr ,
input wire i_read_end ,
input wire i_prog_end ,
input wire i_status_read_end ,
output reg o_read_begin ,
output reg o_prog_begin ,
output reg o_status_read_begin ,
output reg o_prog_start ,
output reg o_prog_end ,
output reg o_read_start ,
output reg o_read_end ,
output reg o_erase_start,
output reg o_erase_end ,
output reg o_op_dq_t ,
output reg o_op_dqs_t ,
output wire [`CIO_WD-1:0] o_op_dq ,
output reg o_op_ce_n ,
output reg o_op_cle ,
output reg o_op_ale ,
output reg o_op_wr_n ,
input wire i_sta_rdy ,
input wire i_ch_gnt ,
output reg o_ch_req ,
output wire o_maddr_ack ,
output reg o_ready
);
reg [3:0] r_op_current_state;
reg [3:0] r_op_next_state ;
reg count_comm_i ;
reg [2:0] count_ADD_i ;
reg count_comm ;
reg [2:0] count_ADD ;
reg [1:0] count_wait_i ;
reg [1:0] count_wait ;
reg [4:0] r_return_grt_cnt ;
reg [2:0] r_cnt_wait ;
reg [2:0] r_cnt_wait_i ;
reg r_maddr_ack ;
reg r_maddr_ack_1 ;
reg r_cmd_cycle_i ;
reg r_cmd_cycle ;
reg r_addr_wait_cnt_i;
reg r_addr_wait_cnt ;
reg r_addr_cycle_i ;
reg r_addr_cycle ;
wire t_enable ;
wire [`CMD_WD-1:0] t_CMD ;
wire [`NADDR_WD-1:0] t_ADDR ;
reg [`IO_WD-1 :0] r_op_dq ;
genvar i ;
generate
for (i=0 ; i<`CLST ; i=i+1)
begin : nand_io
assign o_op_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_op_dq ;
end
endgenerate
parameter ST_op_IDLE = 4'b0000;
parameter ST_op_wait_grt = 4'b0001;
parameter ST_op_READY = 4'b0011;
parameter ST_op_CMD_wait = 4'b0010;
parameter ST_op_CMD = 4'b0110;
parameter ST_op_ADDR_wait = 4'b0111;
parameter ST_op_ADDR = 4'b0101;
parameter ST_op_datain_wait = 4'b0100;
parameter ST_op_datain = 4'b1100;
parameter ST_op_prog_wait = 4'b1101;
parameter ST_op_status_wait = 4'b1111;
parameter ST_op_status = 4'b1110;
parameter ST_op_return_grt = 4'b1010;
parameter ST_op_end = 4'b1011;
parameter ST_op_dataout = 4'b1001;
parameter READ = 8'h01 ;
parameter PROGRAM = 8'h02 ;
parameter ERASE = 8'h03 ;
parameter RETURN_GNT_CNT = 5'b1_0100 ;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
assign t_enable = i_enable ;
assign t_ADDR = i_nand_addr ;
assign t_CMD = i_command ;
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_IDLE:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
ST_op_CMD_wait:
begin
case(t_CMD)
PROGRAM:
begin
o_prog_start <= 'b1;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
READ:
begin
o_prog_start <= 'b0;
o_read_start <= 'b1;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
ERASE:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b1;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
default:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
endcase
end
ST_op_end:
begin
case(t_CMD)
PROGRAM:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b1;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
READ:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b1;
o_erase_end <= 'b0;
end
ERASE:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b1;
end
default:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
endcase
end
default:
begin
o_prog_start <= o_prog_start ;
o_read_start <= o_read_start ;
o_erase_start<= o_erase_start;
o_prog_end <= o_prog_end ;
o_read_end <= o_read_end ;
o_erase_end <= o_erase_end ;
end
endcase
end
assign o_maddr_ack = r_maddr_ack || r_maddr_ack_1;
always @ (posedge i_nc_clk)
begin
r_maddr_ack_1 <= r_maddr_ack;
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_op_current_state <= ST_op_IDLE ;
end
else
begin
r_op_current_state <= r_op_next_state ;
end
end
always @ (*)
begin
case(r_op_current_state)
ST_op_IDLE :
begin
if(t_enable)
begin
r_op_next_state <= ST_op_wait_grt ;
end
else
begin
r_op_next_state <= ST_op_IDLE ;
end
end
ST_op_wait_grt :
begin
if(i_ch_gnt)
begin
r_op_next_state <= ST_op_READY ;
end
else
begin
r_op_next_state <= ST_op_wait_grt ;
end
end
ST_op_READY :
begin
r_op_next_state <= (i_clk_o) ? ST_op_CMD_wait : ST_op_READY ;
end
ST_op_CMD_wait :
begin
r_op_next_state <= (count_wait_i) ? ST_op_CMD_wait : ST_op_CMD;
end
ST_op_CMD :
begin
r_op_next_state <= (!r_cmd_cycle_i) ? ST_op_CMD : (!count_comm_i) ? ST_op_ADDR_wait : ST_op_status_wait ;
end
ST_op_ADDR_wait :
begin
r_op_next_state <= (r_addr_wait_cnt_i) ? ST_op_ADDR_wait: ST_op_ADDR ;
end
ST_op_ADDR :
begin
case(t_CMD)
READ :
begin
r_op_next_state <= (r_addr_cycle_i) ? ST_op_ADDR : (count_ADD_i == 4) ? ST_op_CMD_wait: ST_op_ADDR_wait ;
end
PROGRAM :
begin
r_op_next_state <= (r_addr_cycle_i) ? ST_op_ADDR : (count_ADD_i == 4) ? ST_op_datain_wait : ST_op_ADDR_wait ;
end
ERASE :
begin
r_op_next_state <= (r_addr_cycle_i) ? ST_op_ADDR : (count_ADD_i == 2) ? ST_op_CMD_wait : ST_op_ADDR_wait ;
end
default :
begin
r_op_next_state <= ST_op_IDLE ;
end
endcase
end
ST_op_dataout :
begin
r_op_next_state <= (i_read_end) ? ST_op_end : ST_op_dataout ;
end
ST_op_datain_wait :
begin
r_op_next_state <= ST_op_datain ;
end
ST_op_datain :
begin
r_op_next_state <= (i_prog_end) ? ST_op_prog_wait : ST_op_datain ;
end
ST_op_status_wait :
begin
r_op_next_state <= (r_cnt_wait_i) ? ST_op_status_wait : ST_op_status ;
end
ST_op_status :
begin
if(i_status_read_end)
begin
if (i_sta_rdy)
begin
case(t_CMD)
READ :
begin
r_op_next_state <= ST_op_dataout;
end
default :
begin
r_op_next_state <= ST_op_end;
end
endcase
end
else
begin
r_op_next_state <= ST_op_return_grt ;
end
end
else
begin
r_op_next_state <= ST_op_status ;
end
end
ST_op_return_grt :
begin
r_op_next_state <= (r_return_grt_cnt)? ST_op_return_grt : ST_op_status ;
end
ST_op_prog_wait :
begin
r_op_next_state <= ST_op_READY ;
end
ST_op_end :
begin
r_op_next_state <= ST_op_IDLE;
end
default :
begin
r_op_next_state <= ST_op_IDLE ;
end
endcase
end
always @ (*)
begin
case(r_op_current_state)
ST_op_IDLE :
begin
if(t_enable)
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
end
else
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
end
r_maddr_ack <= 'b0 ;
end
ST_op_wait_grt :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_READY :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_CMD_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_CMD :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_ADDR_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_ADDR :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_dataout :
begin
o_read_begin <= 1 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_datain_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b1 ;
end
ST_op_datain :
begin
o_read_begin <= 0 ;
o_prog_begin <= 1 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_status_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_status :
begin
if(i_status_read_end)
begin
if (i_sta_rdy)
begin
case(t_CMD)
READ :
begin
o_ch_req <= 'b1;
r_maddr_ack <= 'b1;
end
default :
begin
o_ch_req <= 'b0;
r_maddr_ack <= 'b0;
end
endcase
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
end
else
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
end
else
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= (i_ch_gnt) ? 'b1 : 'b0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
end
ST_op_return_grt :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
ST_op_prog_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_end :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
default :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
count_comm_i <= 'b0;
r_cmd_cycle_i <= 'b0;
r_addr_wait_cnt_i <= 'b1;
r_addr_cycle_i <= 'b1;
count_ADD_i <= 'b0;
count_wait_i <= 'h3;
r_cnt_wait_i <= 'h4;
end
else
begin
count_comm_i <= count_comm ;
r_cmd_cycle_i <= r_cmd_cycle ;
r_addr_wait_cnt_i <= r_addr_wait_cnt;
r_addr_cycle_i <= r_addr_cycle;
count_ADD_i <= count_ADD ;
count_wait_i <= count_wait ;
r_cnt_wait_i <= r_cnt_wait ;
end
end
always @ (*)
begin
case(r_op_current_state)
ST_op_IDLE:
begin
count_comm <= 'b0;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= 'b0;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_CMD_wait :
begin
count_comm <= count_comm_i ;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i ;
count_wait <= count_wait_i-'b1 ;
r_cnt_wait <= 'h4;
end
ST_op_CMD :
begin
count_comm <= (r_cmd_cycle_i) ? count_comm_i+'b1 : count_comm_i;
r_cmd_cycle <= r_cmd_cycle_i+'b1;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i ;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_ADDR_wait:
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= r_addr_wait_cnt_i-'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i ;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_ADDR :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= r_addr_cycle_i-'b1;
count_ADD <= (r_addr_cycle_i) ? count_ADD_i : count_ADD_i + 1;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_datain_wait :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_status_wait :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i;
count_wait <= 'h3;
r_cnt_wait <= r_cnt_wait_i-'b1;
end
default :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_return_grt : r_return_grt_cnt <= r_return_grt_cnt - 'b1;
default : r_return_grt_cnt <= RETURN_GNT_CNT;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_IDLE, ST_op_wait_grt, ST_op_end:
begin
o_op_ce_n <= hi ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
ST_op_CMD :
begin
o_op_ce_n <= lo ;
o_op_cle <= hi ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
o_op_dq_t <= lo ;
o_op_dqs_t <= hi ;
case(t_CMD)
READ :
begin
r_op_dq <= (!count_comm_i) ? 8'h00 : 8'h30 ;
end
PROGRAM :
begin
r_op_dq <= (!count_comm_i) ? 8'h80 : 8'h10 ;
end
ERASE :
begin
r_op_dq <= (!count_comm_i) ? 8'h60 : 8'hd0 ;
end
default :
begin
r_op_dq <= 8'h00 ;
end
endcase
end
ST_op_ADDR :
begin
o_op_ce_n <= lo ;
o_op_cle <= lo ;
o_op_ale <= hi ;
o_op_wr_n <= hi ;
o_op_dq_t <= lo ;
o_op_dqs_t <= hi ;
case(t_CMD)
READ, PROGRAM :
begin
case(count_ADD_i)
0: r_op_dq <= t_ADDR[7:0] ;
1: r_op_dq <= {2'h0, t_ADDR[13:8]} ;
2: r_op_dq <= t_ADDR[21:14] ;
3: r_op_dq <= t_ADDR[29:22] ;
4: r_op_dq <= {4'b0000,t_ADDR[33:30]} ;
default: r_op_dq <= 0 ;
endcase
end
ERASE :
begin
case(count_ADD_i)
0: r_op_dq <=t_ADDR[21:14] ;
1: r_op_dq <=t_ADDR[29:22] ;
2: r_op_dq <={4'b0000,t_ADDR[33:30]} ;
default: r_op_dq <=0 ;
endcase
end
default :
begin
r_op_dq <= 0 ;
end
endcase
end
ST_op_datain :
begin
o_op_ce_n <= lo ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
ST_op_status, ST_op_return_grt, ST_op_dataout :
begin
o_op_ce_n <= hi ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
default :
begin
o_op_ce_n <= lo ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_IDLE: o_ready <= 'b1;
default : o_ready <= 'b0;
endcase
end
endmodule | module sync_op(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_enable ,
input wire [`CMD_WD-1:0] i_command ,
input wire [`NADDR_WD-1:0] i_nand_addr ,
input wire i_read_end ,
input wire i_prog_end ,
input wire i_status_read_end ,
output reg o_read_begin ,
output reg o_prog_begin ,
output reg o_status_read_begin ,
output reg o_prog_start ,
output reg o_prog_end ,
output reg o_read_start ,
output reg o_read_end ,
output reg o_erase_start,
output reg o_erase_end ,
output reg o_op_dq_t ,
output reg o_op_dqs_t ,
output wire [`CIO_WD-1:0] o_op_dq ,
output reg o_op_ce_n ,
output reg o_op_cle ,
output reg o_op_ale ,
output reg o_op_wr_n ,
input wire i_sta_rdy ,
input wire i_ch_gnt ,
output reg o_ch_req ,
output wire o_maddr_ack ,
output reg o_ready
); |
reg [3:0] r_op_current_state;
reg [3:0] r_op_next_state ;
reg count_comm_i ;
reg [2:0] count_ADD_i ;
reg count_comm ;
reg [2:0] count_ADD ;
reg [1:0] count_wait_i ;
reg [1:0] count_wait ;
reg [4:0] r_return_grt_cnt ;
reg [2:0] r_cnt_wait ;
reg [2:0] r_cnt_wait_i ;
reg r_maddr_ack ;
reg r_maddr_ack_1 ;
reg r_cmd_cycle_i ;
reg r_cmd_cycle ;
reg r_addr_wait_cnt_i;
reg r_addr_wait_cnt ;
reg r_addr_cycle_i ;
reg r_addr_cycle ;
wire t_enable ;
wire [`CMD_WD-1:0] t_CMD ;
wire [`NADDR_WD-1:0] t_ADDR ;
reg [`IO_WD-1 :0] r_op_dq ;
genvar i ;
generate
for (i=0 ; i<`CLST ; i=i+1)
begin : nand_io
assign o_op_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_op_dq ;
end
endgenerate
parameter ST_op_IDLE = 4'b0000;
parameter ST_op_wait_grt = 4'b0001;
parameter ST_op_READY = 4'b0011;
parameter ST_op_CMD_wait = 4'b0010;
parameter ST_op_CMD = 4'b0110;
parameter ST_op_ADDR_wait = 4'b0111;
parameter ST_op_ADDR = 4'b0101;
parameter ST_op_datain_wait = 4'b0100;
parameter ST_op_datain = 4'b1100;
parameter ST_op_prog_wait = 4'b1101;
parameter ST_op_status_wait = 4'b1111;
parameter ST_op_status = 4'b1110;
parameter ST_op_return_grt = 4'b1010;
parameter ST_op_end = 4'b1011;
parameter ST_op_dataout = 4'b1001;
parameter READ = 8'h01 ;
parameter PROGRAM = 8'h02 ;
parameter ERASE = 8'h03 ;
parameter RETURN_GNT_CNT = 5'b1_0100 ;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
assign t_enable = i_enable ;
assign t_ADDR = i_nand_addr ;
assign t_CMD = i_command ;
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_IDLE:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
ST_op_CMD_wait:
begin
case(t_CMD)
PROGRAM:
begin
o_prog_start <= 'b1;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
READ:
begin
o_prog_start <= 'b0;
o_read_start <= 'b1;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
ERASE:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b1;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
default:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
endcase
end
ST_op_end:
begin
case(t_CMD)
PROGRAM:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b1;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
READ:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b1;
o_erase_end <= 'b0;
end
ERASE:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b1;
end
default:
begin
o_prog_start <= 'b0;
o_read_start <= 'b0;
o_erase_start<= 'b0;
o_prog_end <= 'b0;
o_read_end <= 'b0;
o_erase_end <= 'b0;
end
endcase
end
default:
begin
o_prog_start <= o_prog_start ;
o_read_start <= o_read_start ;
o_erase_start<= o_erase_start;
o_prog_end <= o_prog_end ;
o_read_end <= o_read_end ;
o_erase_end <= o_erase_end ;
end
endcase
end
assign o_maddr_ack = r_maddr_ack || r_maddr_ack_1;
always @ (posedge i_nc_clk)
begin
r_maddr_ack_1 <= r_maddr_ack;
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_op_current_state <= ST_op_IDLE ;
end
else
begin
r_op_current_state <= r_op_next_state ;
end
end
always @ (*)
begin
case(r_op_current_state)
ST_op_IDLE :
begin
if(t_enable)
begin
r_op_next_state <= ST_op_wait_grt ;
end
else
begin
r_op_next_state <= ST_op_IDLE ;
end
end
ST_op_wait_grt :
begin
if(i_ch_gnt)
begin
r_op_next_state <= ST_op_READY ;
end
else
begin
r_op_next_state <= ST_op_wait_grt ;
end
end
ST_op_READY :
begin
r_op_next_state <= (i_clk_o) ? ST_op_CMD_wait : ST_op_READY ;
end
ST_op_CMD_wait :
begin
r_op_next_state <= (count_wait_i) ? ST_op_CMD_wait : ST_op_CMD;
end
ST_op_CMD :
begin
r_op_next_state <= (!r_cmd_cycle_i) ? ST_op_CMD : (!count_comm_i) ? ST_op_ADDR_wait : ST_op_status_wait ;
end
ST_op_ADDR_wait :
begin
r_op_next_state <= (r_addr_wait_cnt_i) ? ST_op_ADDR_wait: ST_op_ADDR ;
end
ST_op_ADDR :
begin
case(t_CMD)
READ :
begin
r_op_next_state <= (r_addr_cycle_i) ? ST_op_ADDR : (count_ADD_i == 4) ? ST_op_CMD_wait: ST_op_ADDR_wait ;
end
PROGRAM :
begin
r_op_next_state <= (r_addr_cycle_i) ? ST_op_ADDR : (count_ADD_i == 4) ? ST_op_datain_wait : ST_op_ADDR_wait ;
end
ERASE :
begin
r_op_next_state <= (r_addr_cycle_i) ? ST_op_ADDR : (count_ADD_i == 2) ? ST_op_CMD_wait : ST_op_ADDR_wait ;
end
default :
begin
r_op_next_state <= ST_op_IDLE ;
end
endcase
end
ST_op_dataout :
begin
r_op_next_state <= (i_read_end) ? ST_op_end : ST_op_dataout ;
end
ST_op_datain_wait :
begin
r_op_next_state <= ST_op_datain ;
end
ST_op_datain :
begin
r_op_next_state <= (i_prog_end) ? ST_op_prog_wait : ST_op_datain ;
end
ST_op_status_wait :
begin
r_op_next_state <= (r_cnt_wait_i) ? ST_op_status_wait : ST_op_status ;
end
ST_op_status :
begin
if(i_status_read_end)
begin
if (i_sta_rdy)
begin
case(t_CMD)
READ :
begin
r_op_next_state <= ST_op_dataout;
end
default :
begin
r_op_next_state <= ST_op_end;
end
endcase
end
else
begin
r_op_next_state <= ST_op_return_grt ;
end
end
else
begin
r_op_next_state <= ST_op_status ;
end
end
ST_op_return_grt :
begin
r_op_next_state <= (r_return_grt_cnt)? ST_op_return_grt : ST_op_status ;
end
ST_op_prog_wait :
begin
r_op_next_state <= ST_op_READY ;
end
ST_op_end :
begin
r_op_next_state <= ST_op_IDLE;
end
default :
begin
r_op_next_state <= ST_op_IDLE ;
end
endcase
end
always @ (*)
begin
case(r_op_current_state)
ST_op_IDLE :
begin
if(t_enable)
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
end
else
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
end
r_maddr_ack <= 'b0 ;
end
ST_op_wait_grt :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_READY :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_CMD_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_CMD :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_ADDR_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_ADDR :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_dataout :
begin
o_read_begin <= 1 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_datain_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b1 ;
end
ST_op_datain :
begin
o_read_begin <= 0 ;
o_prog_begin <= 1 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_status_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_status :
begin
if(i_status_read_end)
begin
if (i_sta_rdy)
begin
case(t_CMD)
READ :
begin
o_ch_req <= 'b1;
r_maddr_ack <= 'b1;
end
default :
begin
o_ch_req <= 'b0;
r_maddr_ack <= 'b0;
end
endcase
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
end
else
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
end
else
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= (i_ch_gnt) ? 'b1 : 'b0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
end
ST_op_return_grt :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
ST_op_prog_wait :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b1 ;
r_maddr_ack <= 'b0 ;
end
ST_op_end :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
default :
begin
o_read_begin <= 0 ;
o_prog_begin <= 0 ;
o_status_read_begin <= 0 ;
o_ch_req <= 'b0 ;
r_maddr_ack <= 'b0 ;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
count_comm_i <= 'b0;
r_cmd_cycle_i <= 'b0;
r_addr_wait_cnt_i <= 'b1;
r_addr_cycle_i <= 'b1;
count_ADD_i <= 'b0;
count_wait_i <= 'h3;
r_cnt_wait_i <= 'h4;
end
else
begin
count_comm_i <= count_comm ;
r_cmd_cycle_i <= r_cmd_cycle ;
r_addr_wait_cnt_i <= r_addr_wait_cnt;
r_addr_cycle_i <= r_addr_cycle;
count_ADD_i <= count_ADD ;
count_wait_i <= count_wait ;
r_cnt_wait_i <= r_cnt_wait ;
end
end
always @ (*)
begin
case(r_op_current_state)
ST_op_IDLE:
begin
count_comm <= 'b0;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= 'b0;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_CMD_wait :
begin
count_comm <= count_comm_i ;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i ;
count_wait <= count_wait_i-'b1 ;
r_cnt_wait <= 'h4;
end
ST_op_CMD :
begin
count_comm <= (r_cmd_cycle_i) ? count_comm_i+'b1 : count_comm_i;
r_cmd_cycle <= r_cmd_cycle_i+'b1;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i ;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_ADDR_wait:
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= r_addr_wait_cnt_i-'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i ;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_ADDR :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= r_addr_cycle_i-'b1;
count_ADD <= (r_addr_cycle_i) ? count_ADD_i : count_ADD_i + 1;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_datain_wait :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
ST_op_status_wait :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i;
count_wait <= 'h3;
r_cnt_wait <= r_cnt_wait_i-'b1;
end
default :
begin
count_comm <= count_comm_i;
r_cmd_cycle <= 'b0;
r_addr_wait_cnt <= 'b1;
r_addr_cycle <= 'b1;
count_ADD <= count_ADD_i;
count_wait <= 'h3;
r_cnt_wait <= 'h4;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_return_grt : r_return_grt_cnt <= r_return_grt_cnt - 'b1;
default : r_return_grt_cnt <= RETURN_GNT_CNT;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_IDLE, ST_op_wait_grt, ST_op_end:
begin
o_op_ce_n <= hi ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
ST_op_CMD :
begin
o_op_ce_n <= lo ;
o_op_cle <= hi ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
o_op_dq_t <= lo ;
o_op_dqs_t <= hi ;
case(t_CMD)
READ :
begin
r_op_dq <= (!count_comm_i) ? 8'h00 : 8'h30 ;
end
PROGRAM :
begin
r_op_dq <= (!count_comm_i) ? 8'h80 : 8'h10 ;
end
ERASE :
begin
r_op_dq <= (!count_comm_i) ? 8'h60 : 8'hd0 ;
end
default :
begin
r_op_dq <= 8'h00 ;
end
endcase
end
ST_op_ADDR :
begin
o_op_ce_n <= lo ;
o_op_cle <= lo ;
o_op_ale <= hi ;
o_op_wr_n <= hi ;
o_op_dq_t <= lo ;
o_op_dqs_t <= hi ;
case(t_CMD)
READ, PROGRAM :
begin
case(count_ADD_i)
0: r_op_dq <= t_ADDR[7:0] ;
1: r_op_dq <= {2'h0, t_ADDR[13:8]} ;
2: r_op_dq <= t_ADDR[21:14] ;
3: r_op_dq <= t_ADDR[29:22] ;
4: r_op_dq <= {4'b0000,t_ADDR[33:30]} ;
default: r_op_dq <= 0 ;
endcase
end
ERASE :
begin
case(count_ADD_i)
0: r_op_dq <=t_ADDR[21:14] ;
1: r_op_dq <=t_ADDR[29:22] ;
2: r_op_dq <={4'b0000,t_ADDR[33:30]} ;
default: r_op_dq <=0 ;
endcase
end
default :
begin
r_op_dq <= 0 ;
end
endcase
end
ST_op_datain :
begin
o_op_ce_n <= lo ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
ST_op_status, ST_op_return_grt, ST_op_dataout :
begin
o_op_ce_n <= hi ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
default :
begin
o_op_ce_n <= lo ;
o_op_cle <= lo ;
o_op_ale <= lo ;
o_op_wr_n <= hi ;
r_op_dq <= 8'h0 ;
o_op_dq_t <= hi ;
o_op_dqs_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_op_current_state)
ST_op_IDLE: o_ready <= 'b1;
default : o_ready <= 'b0;
endcase
end
endmodule | 25 |
137,330 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v | 77,907,036 | sync_prog.v | v | 501 | 137 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xb0 in position 15087: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:52: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:70: Define or directive not defined: \'`CIO_WD\'\n output reg [`CIO_WD-1:0] o_prog_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:79: Define or directive not defined: \'`CIO_WD\'\n input wire [`CIO_WD-1:0] i_b2n_data , \n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:80: Define or directive not defined: \'`NAND_PBAWIDTH\'\n output reg [`NAND_PBAWIDTH-1:0] o_b2n_addr ,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:90: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] count_datain_i ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:91: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] count_datain ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:96: Define or directive not defined: \'`CIO_WD\'\n reg [`CIO_WD-1:0] r_prog_dq ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:99: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] r_cnt_para ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:119: Define or directive not defined: \'`PBDEPTH\'\n parameter DATA_COUNT = (`PBDEPTH)/2-1; \n ^~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:119: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n parameter DATA_COUNT = (`PBDEPTH)/2-1; \n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:120: Define or directive not defined: \'`SBDEPTH\'\n parameter SDATA_COUNT = (`SBDEPTH)/2-1; \n ^~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:120: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n parameter SDATA_COUNT = (`SBDEPTH)/2-1; \n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:391: Define or directive not defined: \'`CIO_WD\'\n r_prog_dq <= `CIO_WD\'h0 ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:403: Define or directive not defined: \'`CIO_WD\'\n r_prog_dq <= `CIO_WD\'h0 ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:409: Define or directive not defined: \'`CIO_WD\'\n r_prog_dq <= `CIO_WD\'h0 ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:422: Define or directive not defined: \'`INIT_PBDEPTH\'\n o_b2n_addr <= (r_begin_cnt) ? `INIT_PBDEPTH - \'b1 : o_b2n_addr - \'b1;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v:450: Define or directive not defined: \'`INIT_PBDEPTH\'\n o_b2n_addr <= `INIT_PBDEPTH - \'b1 ;\n ^~~~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n' | 295,920 | module | module sync_prog(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_prog_begin ,
output reg o_prog_end ,
output reg o_m2b_req ,
input wire i_m2b_cmplt ,
output wire o_sp_en ,
output reg o_dqs_ce ,
output reg [`CIO_WD-1:0] o_prog_dq ,
output reg o_prog_ce_n ,
output reg o_prog_cle ,
output reg o_prog_ale ,
output reg o_prog_wr_n ,
output reg o_prog_dqs_t ,
output reg o_prog_dq_t ,
input wire [`CIO_WD-1:0] i_b2n_data ,
output reg [`NAND_PBAWIDTH-1:0] o_b2n_addr ,
output reg o_b2n_en ,
output reg o_b2n_we
);
reg [3:0] current_datain_state ;
reg [3:0] next_datain_state ;
reg [`NAND_PBAWIDTH-1:0] count_datain_i ;
reg [`NAND_PBAWIDTH-1:0] count_datain ;
reg [2:0] r_begin_cnt ;
reg [1:0] r_datain_ready_cnt;
reg r_datain_end_cnt;
reg [`CIO_WD-1:0] r_prog_dq ;
reg [1 : 0] r_trf_cnt ;
reg r_spare_done;
reg [`NAND_PBAWIDTH-1:0] r_cnt_para ;
parameter ST_datain_idle = 4'b0000;
parameter ST_datain_m2b = 4'b0001;
parameter ST_clk_syn = 4'b0011;
parameter ST_datain_begin = 4'b0010;
parameter ST_datain_ready_1 = 4'b0110;
parameter ST_datain_ready_2 = 4'b0111;
parameter ST_datain1 = 4'b0101;
parameter ST_datain2 = 4'b0100;
parameter ST_datain3 = 4'b1100;
parameter ST_datain_end_1 = 4'b1101;
parameter ST_datain_end_2 = 4'b1111;
parameter ST_datain_end_3 = 4'b1110;
parameter ST_datain_end_4 = 4'b1010;
parameter ST_sddatain_end = 4'b1011;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
parameter DATA_COUNT = (`PBDEPTH)/2-1;
parameter SDATA_COUNT = (`SBDEPTH)/2-1;
assign o_sp_en = !r_spare_done;
always @ (*)
begin
case(r_spare_done)
1'b0 : r_cnt_para <= SDATA_COUNT;
default : r_cnt_para <= DATA_COUNT;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
current_datain_state <= ST_datain_idle ;
end
else
begin
current_datain_state <= next_datain_state ;
end
end
always @ (*)
begin
case(current_datain_state)
ST_datain_idle :
begin
next_datain_state <= (i_prog_begin) ? (r_spare_done) ? ST_datain_m2b : ST_clk_syn : ST_datain_idle ;
end
ST_datain_m2b :
begin
if(i_m2b_cmplt)
begin
next_datain_state <= ST_clk_syn ;
end
else
begin
next_datain_state <= ST_datain_m2b ;
end
end
ST_clk_syn :
begin
next_datain_state <= (i_clk_o) ? ST_clk_syn : ST_datain_begin ;
end
ST_datain_begin :
begin
next_datain_state <= (r_begin_cnt) ? ST_datain_begin : ST_datain_ready_1 ;
end
ST_datain_ready_1 :
begin
next_datain_state <= ST_datain_ready_2 ;
end
ST_datain_ready_2 :
begin
next_datain_state <= (r_datain_ready_cnt) ? ST_datain_ready_2 : ST_datain1 ;
end
ST_datain1 :
begin
next_datain_state <= ST_datain2 ;
end
ST_datain2 :
begin
next_datain_state <= (count_datain_i == r_cnt_para-'h1) ? ST_datain3 : ST_datain1 ;
end
ST_datain3 :
begin
next_datain_state <= (r_datain_end_cnt) ? ST_datain3 : ST_datain_end_1 ;
end
ST_datain_end_1 :
begin
next_datain_state <= ST_datain_end_2 ;
end
ST_datain_end_2 :
begin
next_datain_state <= (r_spare_done) ? ST_datain_end_3 : ST_sddatain_end ;
end
ST_datain_end_3 :
begin
next_datain_state <= ST_datain_end_4 ;
end
ST_datain_end_4:
begin
next_datain_state <= ST_datain_idle ;
end
ST_sddatain_end :
begin
next_datain_state <= ST_datain_idle ;
end
default :
begin
next_datain_state <= ST_datain_idle ;
end
endcase
end
always @ (*)
begin
case(current_datain_state)
ST_datain_m2b: o_m2b_req <= (i_m2b_cmplt) ? 'b0 : 'b1;
default: o_m2b_req <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_end_3: o_prog_end <= (!r_trf_cnt) ? 'b1 : 'b0 ;
ST_datain_end_4: o_prog_end <= o_prog_end;
default: o_prog_end <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_ready_2 :
begin
r_datain_ready_cnt <= r_datain_ready_cnt-'b1;
r_datain_end_cnt <= 'b1;
end
ST_datain3 :
begin
r_datain_ready_cnt <= 'h2;
r_datain_end_cnt <= r_datain_end_cnt-'b1;
end
default :
begin
r_datain_ready_cnt <= 'h2;
r_datain_end_cnt <= 'b1;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
count_datain_i <= 0 ;
end
else
begin
count_datain_i <= count_datain ;
end
end
always @ (*)
begin
case(current_datain_state)
ST_datain1 :
begin
count_datain <= count_datain_i ;
end
ST_datain2 :
begin
count_datain <= count_datain_i + 1 ;
end
default :
begin
count_datain <= 0 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_idle, ST_datain_m2b, ST_clk_syn :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= lo ;
o_prog_ale <= lo ;
o_prog_wr_n <= hi ;
end
ST_datain_begin, ST_datain_ready_1 :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= lo ;
o_prog_ale <= lo ;
o_prog_wr_n <= hi ;
end
ST_datain_ready_2, ST_datain1 :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= hi ;
o_prog_ale <= hi ;
o_prog_wr_n <= hi ;
end
ST_datain2 :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= (count_datain_i == r_cnt_para-'h1) ? lo : hi ;
o_prog_ale <= (count_datain_i == r_cnt_para-'h1) ? lo : hi ;
o_prog_wr_n <= hi ;
end
default :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= lo ;
o_prog_ale <= lo ;
o_prog_wr_n <= hi ;
end
endcase
end
always @ (*)
begin
case(current_datain_state)
ST_datain_ready_1, ST_datain_ready_2, ST_datain_end_1, ST_datain_end_2, ST_datain_end_3, ST_datain_end_4, ST_sddatain_end:
begin
o_prog_dqs_t <= lo;
o_dqs_ce <= 'b1;
end
ST_datain1, ST_datain2, ST_datain3 :
begin
o_prog_dqs_t <= lo;
o_dqs_ce <= 'b0;
end
default :
begin
o_prog_dqs_t <= hi;
o_dqs_ce <= 'b1;
end
endcase
end
always @ (posedge i_nc_clk)
begin
o_prog_dq <= r_prog_dq ;
end
always @ (*)
begin
case(current_datain_state)
ST_datain_begin :
begin
r_prog_dq <= `CIO_WD'h0 ;
o_prog_dq_t <= hi ;
end
ST_datain_ready_2, ST_datain1, ST_datain2, ST_datain3 :
begin
r_prog_dq <= i_b2n_data ;
o_prog_dq_t <= lo ;
end
ST_datain_end_1 :
begin
r_prog_dq <= `CIO_WD'h0 ;
o_prog_dq_t <= lo ;
end
default :
begin
r_prog_dq <= `CIO_WD'h0 ;
o_prog_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_begin :
begin
o_b2n_addr <= (r_begin_cnt) ? `INIT_PBDEPTH - 'b1 : o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
ST_datain_ready_1 :
begin
o_b2n_addr <= o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
ST_datain_ready_2 :
begin
o_b2n_addr <= o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
ST_datain1, ST_datain2 :
begin
o_b2n_addr <= o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
default :
begin
o_b2n_addr <= `INIT_PBDEPTH - 'b1 ;
o_b2n_en <= lo ;
o_b2n_we <= lo ;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_trf_cnt <= 'b0 ;
end
else
begin
case(current_datain_state)
ST_datain_end_1 : r_trf_cnt <= (r_spare_done) ? r_trf_cnt + 'b1 : r_trf_cnt ;
default : r_trf_cnt <= r_trf_cnt ;
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_spare_done <= 'b0 ;
else
begin
case(current_datain_state)
ST_datain_end_2: r_spare_done <= (r_trf_cnt) ? 'b1 : 'b0;
ST_sddatain_end: r_spare_done <= 'b1;
default: r_spare_done <= r_spare_done;
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_begin_cnt <= 3'b101;
else
begin
case(current_datain_state)
ST_datain_begin : r_begin_cnt <= r_begin_cnt - 'b1 ;
default : r_begin_cnt <= 3'b101;
endcase
end
end
endmodule | module sync_prog(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_prog_begin ,
output reg o_prog_end ,
output reg o_m2b_req ,
input wire i_m2b_cmplt ,
output wire o_sp_en ,
output reg o_dqs_ce ,
output reg [`CIO_WD-1:0] o_prog_dq ,
output reg o_prog_ce_n ,
output reg o_prog_cle ,
output reg o_prog_ale ,
output reg o_prog_wr_n ,
output reg o_prog_dqs_t ,
output reg o_prog_dq_t ,
input wire [`CIO_WD-1:0] i_b2n_data ,
output reg [`NAND_PBAWIDTH-1:0] o_b2n_addr ,
output reg o_b2n_en ,
output reg o_b2n_we
); |
reg [3:0] current_datain_state ;
reg [3:0] next_datain_state ;
reg [`NAND_PBAWIDTH-1:0] count_datain_i ;
reg [`NAND_PBAWIDTH-1:0] count_datain ;
reg [2:0] r_begin_cnt ;
reg [1:0] r_datain_ready_cnt;
reg r_datain_end_cnt;
reg [`CIO_WD-1:0] r_prog_dq ;
reg [1 : 0] r_trf_cnt ;
reg r_spare_done;
reg [`NAND_PBAWIDTH-1:0] r_cnt_para ;
parameter ST_datain_idle = 4'b0000;
parameter ST_datain_m2b = 4'b0001;
parameter ST_clk_syn = 4'b0011;
parameter ST_datain_begin = 4'b0010;
parameter ST_datain_ready_1 = 4'b0110;
parameter ST_datain_ready_2 = 4'b0111;
parameter ST_datain1 = 4'b0101;
parameter ST_datain2 = 4'b0100;
parameter ST_datain3 = 4'b1100;
parameter ST_datain_end_1 = 4'b1101;
parameter ST_datain_end_2 = 4'b1111;
parameter ST_datain_end_3 = 4'b1110;
parameter ST_datain_end_4 = 4'b1010;
parameter ST_sddatain_end = 4'b1011;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
parameter DATA_COUNT = (`PBDEPTH)/2-1;
parameter SDATA_COUNT = (`SBDEPTH)/2-1;
assign o_sp_en = !r_spare_done;
always @ (*)
begin
case(r_spare_done)
1'b0 : r_cnt_para <= SDATA_COUNT;
default : r_cnt_para <= DATA_COUNT;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
current_datain_state <= ST_datain_idle ;
end
else
begin
current_datain_state <= next_datain_state ;
end
end
always @ (*)
begin
case(current_datain_state)
ST_datain_idle :
begin
next_datain_state <= (i_prog_begin) ? (r_spare_done) ? ST_datain_m2b : ST_clk_syn : ST_datain_idle ;
end
ST_datain_m2b :
begin
if(i_m2b_cmplt)
begin
next_datain_state <= ST_clk_syn ;
end
else
begin
next_datain_state <= ST_datain_m2b ;
end
end
ST_clk_syn :
begin
next_datain_state <= (i_clk_o) ? ST_clk_syn : ST_datain_begin ;
end
ST_datain_begin :
begin
next_datain_state <= (r_begin_cnt) ? ST_datain_begin : ST_datain_ready_1 ;
end
ST_datain_ready_1 :
begin
next_datain_state <= ST_datain_ready_2 ;
end
ST_datain_ready_2 :
begin
next_datain_state <= (r_datain_ready_cnt) ? ST_datain_ready_2 : ST_datain1 ;
end
ST_datain1 :
begin
next_datain_state <= ST_datain2 ;
end
ST_datain2 :
begin
next_datain_state <= (count_datain_i == r_cnt_para-'h1) ? ST_datain3 : ST_datain1 ;
end
ST_datain3 :
begin
next_datain_state <= (r_datain_end_cnt) ? ST_datain3 : ST_datain_end_1 ;
end
ST_datain_end_1 :
begin
next_datain_state <= ST_datain_end_2 ;
end
ST_datain_end_2 :
begin
next_datain_state <= (r_spare_done) ? ST_datain_end_3 : ST_sddatain_end ;
end
ST_datain_end_3 :
begin
next_datain_state <= ST_datain_end_4 ;
end
ST_datain_end_4:
begin
next_datain_state <= ST_datain_idle ;
end
ST_sddatain_end :
begin
next_datain_state <= ST_datain_idle ;
end
default :
begin
next_datain_state <= ST_datain_idle ;
end
endcase
end
always @ (*)
begin
case(current_datain_state)
ST_datain_m2b: o_m2b_req <= (i_m2b_cmplt) ? 'b0 : 'b1;
default: o_m2b_req <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_end_3: o_prog_end <= (!r_trf_cnt) ? 'b1 : 'b0 ;
ST_datain_end_4: o_prog_end <= o_prog_end;
default: o_prog_end <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_ready_2 :
begin
r_datain_ready_cnt <= r_datain_ready_cnt-'b1;
r_datain_end_cnt <= 'b1;
end
ST_datain3 :
begin
r_datain_ready_cnt <= 'h2;
r_datain_end_cnt <= r_datain_end_cnt-'b1;
end
default :
begin
r_datain_ready_cnt <= 'h2;
r_datain_end_cnt <= 'b1;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
count_datain_i <= 0 ;
end
else
begin
count_datain_i <= count_datain ;
end
end
always @ (*)
begin
case(current_datain_state)
ST_datain1 :
begin
count_datain <= count_datain_i ;
end
ST_datain2 :
begin
count_datain <= count_datain_i + 1 ;
end
default :
begin
count_datain <= 0 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_idle, ST_datain_m2b, ST_clk_syn :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= lo ;
o_prog_ale <= lo ;
o_prog_wr_n <= hi ;
end
ST_datain_begin, ST_datain_ready_1 :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= lo ;
o_prog_ale <= lo ;
o_prog_wr_n <= hi ;
end
ST_datain_ready_2, ST_datain1 :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= hi ;
o_prog_ale <= hi ;
o_prog_wr_n <= hi ;
end
ST_datain2 :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= (count_datain_i == r_cnt_para-'h1) ? lo : hi ;
o_prog_ale <= (count_datain_i == r_cnt_para-'h1) ? lo : hi ;
o_prog_wr_n <= hi ;
end
default :
begin
o_prog_ce_n <= lo ;
o_prog_cle <= lo ;
o_prog_ale <= lo ;
o_prog_wr_n <= hi ;
end
endcase
end
always @ (*)
begin
case(current_datain_state)
ST_datain_ready_1, ST_datain_ready_2, ST_datain_end_1, ST_datain_end_2, ST_datain_end_3, ST_datain_end_4, ST_sddatain_end:
begin
o_prog_dqs_t <= lo;
o_dqs_ce <= 'b1;
end
ST_datain1, ST_datain2, ST_datain3 :
begin
o_prog_dqs_t <= lo;
o_dqs_ce <= 'b0;
end
default :
begin
o_prog_dqs_t <= hi;
o_dqs_ce <= 'b1;
end
endcase
end
always @ (posedge i_nc_clk)
begin
o_prog_dq <= r_prog_dq ;
end
always @ (*)
begin
case(current_datain_state)
ST_datain_begin :
begin
r_prog_dq <= `CIO_WD'h0 ;
o_prog_dq_t <= hi ;
end
ST_datain_ready_2, ST_datain1, ST_datain2, ST_datain3 :
begin
r_prog_dq <= i_b2n_data ;
o_prog_dq_t <= lo ;
end
ST_datain_end_1 :
begin
r_prog_dq <= `CIO_WD'h0 ;
o_prog_dq_t <= lo ;
end
default :
begin
r_prog_dq <= `CIO_WD'h0 ;
o_prog_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_datain_state)
ST_datain_begin :
begin
o_b2n_addr <= (r_begin_cnt) ? `INIT_PBDEPTH - 'b1 : o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
ST_datain_ready_1 :
begin
o_b2n_addr <= o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
ST_datain_ready_2 :
begin
o_b2n_addr <= o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
ST_datain1, ST_datain2 :
begin
o_b2n_addr <= o_b2n_addr - 'b1;
o_b2n_en <= hi ;
o_b2n_we <= lo ;
end
default :
begin
o_b2n_addr <= `INIT_PBDEPTH - 'b1 ;
o_b2n_en <= lo ;
o_b2n_we <= lo ;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_trf_cnt <= 'b0 ;
end
else
begin
case(current_datain_state)
ST_datain_end_1 : r_trf_cnt <= (r_spare_done) ? r_trf_cnt + 'b1 : r_trf_cnt ;
default : r_trf_cnt <= r_trf_cnt ;
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_spare_done <= 'b0 ;
else
begin
case(current_datain_state)
ST_datain_end_2: r_spare_done <= (r_trf_cnt) ? 'b1 : 'b0;
ST_sddatain_end: r_spare_done <= 'b1;
default: r_spare_done <= r_spare_done;
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_begin_cnt <= 3'b101;
else
begin
case(current_datain_state)
ST_datain_begin : r_begin_cnt <= r_begin_cnt - 'b1 ;
default : r_begin_cnt <= 3'b101;
endcase
end
end
endmodule | 25 |
137,331 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v | 77,907,036 | sync_read_dt.v | v | 581 | 97 | [] | ['general public license', 'free software foundation'] | [] | [(217, 744)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:51: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:64: Define or directive not defined: \'`CIO_WD\'\n input wire [`CIO_WD-1:0] i_read_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:69: Define or directive not defined: \'`CIO_WD\'\n output reg [`CIO_WD-1:0] o_n2b_data ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:70: Define or directive not defined: \'`NAND_PBAWIDTH\'\n output reg [`NAND_PBAWIDTH-1:0] o_n2b_addr ,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:83: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] r_n2b_addr ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:84: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] s_n2b_addr_1 ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:85: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] s_n2b_addr_2 ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:94: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] r_clk_cnt ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:103: Define or directive not defined: \'`NAND_PBAWIDTH\'\n reg [`NAND_PBAWIDTH-1:0] r_cnt_para ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:131: Define or directive not defined: \'`PBDEPTH\'\n parameter DATA_COUNT = (`PBDEPTH)/2-1;\n ^~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:131: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n parameter DATA_COUNT = (`PBDEPTH)/2-1;\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:512: Define or directive not defined: \'`IO_WD\'\n reg [`IO_WD-1 :0] r_p_data;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:513: Define or directive not defined: \'`IO_WD\'\n reg [`IO_WD-1 :0] r_n_data;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v:548: Define or directive not defined: \'`INIT_PBDEPTH\'\n r_n2b_addr <= `INIT_PBDEPTH - \'b1 ;\n ^~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n' | 295,921 | module | module sync_read_dt(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
output reg o_read_cle ,
output reg o_read_ale ,
output reg o_read_wr_n ,
output reg o_read_dq_t ,
input wire [`CIO_WD-1:0] i_read_dq ,
input wire i_read_dqs ,
output reg o_b2m_req ,
input wire i_b2m_cmplt ,
output reg [`CIO_WD-1:0] o_n2b_data ,
output reg [`NAND_PBAWIDTH-1:0] o_n2b_addr ,
output reg o_n2b_en ,
output reg o_n2b_we ,
output reg o_dt_start ,
input wire i_dt_start ,
output reg o_dt_read_end
);
reg [3:0] r_current_read_state ;
reg [3:0] r_next_read_state ;
reg [`NAND_PBAWIDTH-1:0] r_n2b_addr ;
reg [`NAND_PBAWIDTH-1:0] s_n2b_addr_1 ;
reg [`NAND_PBAWIDTH-1:0] s_n2b_addr_2 ;
reg s_n2b_en_1;
reg s_n2b_en_2;
reg s_n2b_we_1;
reg s_n2b_we_2;
reg [1 : 0] r_trf_cnt ;
reg [`NAND_PBAWIDTH-1:0] r_clk_cnt ;
reg [2:0] r_cmd_wait_cnt ;
reg r_cmd_cnt ;
reg [1:0] r_begin1_cnt ;
reg [2:0] r_begin2_cnt ;
reg [1:0] r_ready_cnt ;
reg r_end_cnt ;
reg r_end2_cnt ;
reg r_end3_4_cnt ;
reg [`NAND_PBAWIDTH-1:0] r_cnt_para ;
wire w_read_dqs_n;
assign w_read_dqs_n = !i_read_dqs;
parameter ST_dataout_idle = 4'b0000;
parameter ST_clk_syn = 4'b0001;
parameter ST_dataout_CMD_wait = 4'b0011;
parameter ST_dataout_CMD = 4'b0010;
parameter ST_dataout_begin1 = 4'b0110;
parameter ST_dataout_begin2 = 4'b0111;
parameter ST_dataout_ready = 4'b0101;
parameter ST_dataout = 4'b0100;
parameter ST_dataout_end1 = 4'b1100;
parameter ST_dataout_end2 = 4'b1101;
parameter ST_dataout_end3_1 = 4'b1111;
parameter ST_dataout_end3_2 = 4'b1110;
parameter ST_dataout_end3_3 = 4'b1010;
parameter ST_dataout_end3_4 = 4'b1011;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
parameter DATA_COUNT = (`PBDEPTH)/2-1;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_current_read_state <= ST_dataout_idle ;
end
else
begin
r_current_read_state <= r_next_read_state ;
end
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_idle :
begin
r_next_read_state <= (i_dt_start) ? ST_clk_syn : ST_dataout_idle ;
end
ST_clk_syn :
begin
r_next_read_state <= (i_clk_o) ? ST_clk_syn : ST_dataout_CMD_wait ;
end
ST_dataout_CMD_wait :
begin
r_next_read_state <= (r_cmd_wait_cnt) ? ST_dataout_CMD_wait : ST_dataout_CMD ;
end
ST_dataout_CMD :
begin
r_next_read_state <= (r_cmd_cnt) ? ST_dataout_CMD : ST_dataout_begin1 ;
end
ST_dataout_begin1 :
begin
r_next_read_state <= (r_begin1_cnt) ? ST_dataout_begin1 : ST_dataout_begin2 ;
end
ST_dataout_begin2 :
begin
r_next_read_state <= (r_begin2_cnt) ? ST_dataout_begin2 : ST_dataout_ready ;
end
ST_dataout_ready :
begin
r_next_read_state <= (r_ready_cnt) ? ST_dataout_ready : ST_dataout ;
end
ST_dataout :
begin
r_next_read_state <= (r_clk_cnt==DATA_COUNT) ? ST_dataout_end1 : ST_dataout;
end
ST_dataout_end1 :
begin
r_next_read_state <= (r_end_cnt) ? ST_dataout_end1 : ST_dataout_end2 ;
end
ST_dataout_end2 :
begin
r_next_read_state <= (r_end2_cnt) ? ST_dataout_end2 : ST_dataout_end3_1;
end
ST_dataout_end3_1 :
begin
r_next_read_state <= ST_dataout_end3_2 ;
end
ST_dataout_end3_2 :
begin
r_next_read_state <= (i_b2m_cmplt) ? ST_dataout_end3_3 : ST_dataout_end3_2 ;
end
ST_dataout_end3_3 :
begin
r_next_read_state <= (r_trf_cnt) ? ST_clk_syn : ST_dataout_end3_4 ;
end
ST_dataout_end3_4:
begin
r_next_read_state <= (r_end3_4_cnt) ? ST_dataout_end3_4 : ST_dataout_idle ;
end
default :
begin
r_next_read_state <= ST_dataout_idle ;
end
endcase
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_idle: o_dt_start <= 'b0;
default: o_dt_start <= 'b1;
endcase
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_end3_4: o_dt_read_end <= 'b1;
default: o_dt_read_end <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
else
begin
case(r_current_read_state)
ST_dataout_CMD_wait :
begin
r_cmd_wait_cnt <= r_cmd_wait_cnt - 'b1 ;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_CMD :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= r_cmd_cnt - 'b1 ;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_begin1 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= r_begin1_cnt - 'b1 ;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_begin2 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= r_begin2_cnt - 'b1 ;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_ready :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= r_ready_cnt - 'b1 ;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_end1 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= r_end_cnt - 'b1 ;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_end2 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= r_end2_cnt - 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_end3_4:
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= r_end3_4_cnt - 'h1;
end
default :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_trf_cnt <= 'b0;
end
else
begin
case(r_current_read_state)
ST_dataout_end3_1 : r_trf_cnt <= r_trf_cnt + 'b1;
default : r_trf_cnt <= r_trf_cnt;
endcase
end
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_idle, ST_clk_syn :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
ST_dataout_CMD_wait :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
ST_dataout_CMD :
begin
o_read_cle <= hi ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= lo ;
end
ST_dataout_begin1 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
ST_dataout_begin2 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_ready :
begin
o_read_cle <= hi ;
o_read_ale <= hi ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout :
begin
o_read_cle <= (r_clk_cnt == DATA_COUNT) ? lo : hi ;
o_read_ale <= (r_clk_cnt == DATA_COUNT) ? lo : hi ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_end1 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_end2 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_end3_1, ST_dataout_end3_2 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
default :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_read_state)
ST_dataout_end3_2: o_b2m_req <= 'b1;
default: o_b2m_req <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if (!i_nc_rstn) r_clk_cnt <= 'b0;
else
begin
case(r_current_read_state)
ST_dataout :
begin
if (!i_clk_o) r_clk_cnt <= r_clk_cnt + 'b1;
else r_clk_cnt <= r_clk_cnt;
end
default : r_clk_cnt <= 'b0;
endcase
end
end
reg [`IO_WD-1 :0] r_p_data;
reg [`IO_WD-1 :0] r_n_data;
always @ (posedge i_read_dqs)
begin
r_p_data <= i_read_dq;
end
always @ (posedge w_read_dqs_n)
begin
r_n_data <= i_read_dq;
end
always @(posedge i_nc_clk)
begin
o_n2b_data <= (i_read_dqs) ? r_p_data : r_n_data;
end
always @ (posedge i_nc_clk)
begin
s_n2b_addr_1 <= r_n2b_addr;
s_n2b_addr_2 <= s_n2b_addr_1;
o_n2b_addr <= s_n2b_addr_2;
end
always @ (posedge i_nc_clk)
begin
case(r_current_read_state)
ST_dataout, ST_dataout_end1 :
begin
r_n2b_addr <= (!r_n2b_addr) ? r_n2b_addr : r_n2b_addr - 'b1;
end
default :
begin
r_n2b_addr <= `INIT_PBDEPTH - 'b1 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
s_n2b_en_2 <= s_n2b_en_1;
o_n2b_en <= s_n2b_en_2;
s_n2b_we_2 <= s_n2b_we_1;
o_n2b_we <= s_n2b_we_2;
end
always @ (posedge i_nc_clk)
begin
case(r_current_read_state)
ST_dataout, ST_dataout_end1 :
begin
s_n2b_en_1 <= (r_end_cnt) ? hi : lo;
s_n2b_we_1 <= (r_end_cnt) ? hi : lo;
end
default :
begin
s_n2b_en_1 <= lo ;
s_n2b_we_1 <= lo ;
end
endcase
end
endmodule | module sync_read_dt(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
output reg o_read_cle ,
output reg o_read_ale ,
output reg o_read_wr_n ,
output reg o_read_dq_t ,
input wire [`CIO_WD-1:0] i_read_dq ,
input wire i_read_dqs ,
output reg o_b2m_req ,
input wire i_b2m_cmplt ,
output reg [`CIO_WD-1:0] o_n2b_data ,
output reg [`NAND_PBAWIDTH-1:0] o_n2b_addr ,
output reg o_n2b_en ,
output reg o_n2b_we ,
output reg o_dt_start ,
input wire i_dt_start ,
output reg o_dt_read_end
); |
reg [3:0] r_current_read_state ;
reg [3:0] r_next_read_state ;
reg [`NAND_PBAWIDTH-1:0] r_n2b_addr ;
reg [`NAND_PBAWIDTH-1:0] s_n2b_addr_1 ;
reg [`NAND_PBAWIDTH-1:0] s_n2b_addr_2 ;
reg s_n2b_en_1;
reg s_n2b_en_2;
reg s_n2b_we_1;
reg s_n2b_we_2;
reg [1 : 0] r_trf_cnt ;
reg [`NAND_PBAWIDTH-1:0] r_clk_cnt ;
reg [2:0] r_cmd_wait_cnt ;
reg r_cmd_cnt ;
reg [1:0] r_begin1_cnt ;
reg [2:0] r_begin2_cnt ;
reg [1:0] r_ready_cnt ;
reg r_end_cnt ;
reg r_end2_cnt ;
reg r_end3_4_cnt ;
reg [`NAND_PBAWIDTH-1:0] r_cnt_para ;
wire w_read_dqs_n;
assign w_read_dqs_n = !i_read_dqs;
parameter ST_dataout_idle = 4'b0000;
parameter ST_clk_syn = 4'b0001;
parameter ST_dataout_CMD_wait = 4'b0011;
parameter ST_dataout_CMD = 4'b0010;
parameter ST_dataout_begin1 = 4'b0110;
parameter ST_dataout_begin2 = 4'b0111;
parameter ST_dataout_ready = 4'b0101;
parameter ST_dataout = 4'b0100;
parameter ST_dataout_end1 = 4'b1100;
parameter ST_dataout_end2 = 4'b1101;
parameter ST_dataout_end3_1 = 4'b1111;
parameter ST_dataout_end3_2 = 4'b1110;
parameter ST_dataout_end3_3 = 4'b1010;
parameter ST_dataout_end3_4 = 4'b1011;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
parameter DATA_COUNT = (`PBDEPTH)/2-1;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_current_read_state <= ST_dataout_idle ;
end
else
begin
r_current_read_state <= r_next_read_state ;
end
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_idle :
begin
r_next_read_state <= (i_dt_start) ? ST_clk_syn : ST_dataout_idle ;
end
ST_clk_syn :
begin
r_next_read_state <= (i_clk_o) ? ST_clk_syn : ST_dataout_CMD_wait ;
end
ST_dataout_CMD_wait :
begin
r_next_read_state <= (r_cmd_wait_cnt) ? ST_dataout_CMD_wait : ST_dataout_CMD ;
end
ST_dataout_CMD :
begin
r_next_read_state <= (r_cmd_cnt) ? ST_dataout_CMD : ST_dataout_begin1 ;
end
ST_dataout_begin1 :
begin
r_next_read_state <= (r_begin1_cnt) ? ST_dataout_begin1 : ST_dataout_begin2 ;
end
ST_dataout_begin2 :
begin
r_next_read_state <= (r_begin2_cnt) ? ST_dataout_begin2 : ST_dataout_ready ;
end
ST_dataout_ready :
begin
r_next_read_state <= (r_ready_cnt) ? ST_dataout_ready : ST_dataout ;
end
ST_dataout :
begin
r_next_read_state <= (r_clk_cnt==DATA_COUNT) ? ST_dataout_end1 : ST_dataout;
end
ST_dataout_end1 :
begin
r_next_read_state <= (r_end_cnt) ? ST_dataout_end1 : ST_dataout_end2 ;
end
ST_dataout_end2 :
begin
r_next_read_state <= (r_end2_cnt) ? ST_dataout_end2 : ST_dataout_end3_1;
end
ST_dataout_end3_1 :
begin
r_next_read_state <= ST_dataout_end3_2 ;
end
ST_dataout_end3_2 :
begin
r_next_read_state <= (i_b2m_cmplt) ? ST_dataout_end3_3 : ST_dataout_end3_2 ;
end
ST_dataout_end3_3 :
begin
r_next_read_state <= (r_trf_cnt) ? ST_clk_syn : ST_dataout_end3_4 ;
end
ST_dataout_end3_4:
begin
r_next_read_state <= (r_end3_4_cnt) ? ST_dataout_end3_4 : ST_dataout_idle ;
end
default :
begin
r_next_read_state <= ST_dataout_idle ;
end
endcase
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_idle: o_dt_start <= 'b0;
default: o_dt_start <= 'b1;
endcase
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_end3_4: o_dt_read_end <= 'b1;
default: o_dt_read_end <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
else
begin
case(r_current_read_state)
ST_dataout_CMD_wait :
begin
r_cmd_wait_cnt <= r_cmd_wait_cnt - 'b1 ;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_CMD :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= r_cmd_cnt - 'b1 ;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_begin1 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= r_begin1_cnt - 'b1 ;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_begin2 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= r_begin2_cnt - 'b1 ;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_ready :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= r_ready_cnt - 'b1 ;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_end1 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= r_end_cnt - 'b1 ;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_end2 :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= r_end2_cnt - 'h1;
r_end3_4_cnt <= 'h1;
end
ST_dataout_end3_4:
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= r_end3_4_cnt - 'h1;
end
default :
begin
r_cmd_wait_cnt <= 3'h4;
r_cmd_cnt <= 'b1;
r_begin1_cnt <= 2'h3;
r_begin2_cnt <= 3'h5;
r_ready_cnt <= 2'h2;
r_end_cnt <= 'h1;
r_end2_cnt <= 'h1;
r_end3_4_cnt <= 'h1;
end
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_trf_cnt <= 'b0;
end
else
begin
case(r_current_read_state)
ST_dataout_end3_1 : r_trf_cnt <= r_trf_cnt + 'b1;
default : r_trf_cnt <= r_trf_cnt;
endcase
end
end
always @ (*)
begin
case(r_current_read_state)
ST_dataout_idle, ST_clk_syn :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
ST_dataout_CMD_wait :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
ST_dataout_CMD :
begin
o_read_cle <= hi ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= lo ;
end
ST_dataout_begin1 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
ST_dataout_begin2 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_ready :
begin
o_read_cle <= hi ;
o_read_ale <= hi ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout :
begin
o_read_cle <= (r_clk_cnt == DATA_COUNT) ? lo : hi ;
o_read_ale <= (r_clk_cnt == DATA_COUNT) ? lo : hi ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_end1 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_end2 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= lo ;
o_read_dq_t <= hi ;
end
ST_dataout_end3_1, ST_dataout_end3_2 :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
default :
begin
o_read_cle <= lo ;
o_read_ale <= lo ;
o_read_wr_n <= hi ;
o_read_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_read_state)
ST_dataout_end3_2: o_b2m_req <= 'b1;
default: o_b2m_req <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if (!i_nc_rstn) r_clk_cnt <= 'b0;
else
begin
case(r_current_read_state)
ST_dataout :
begin
if (!i_clk_o) r_clk_cnt <= r_clk_cnt + 'b1;
else r_clk_cnt <= r_clk_cnt;
end
default : r_clk_cnt <= 'b0;
endcase
end
end
reg [`IO_WD-1 :0] r_p_data;
reg [`IO_WD-1 :0] r_n_data;
always @ (posedge i_read_dqs)
begin
r_p_data <= i_read_dq;
end
always @ (posedge w_read_dqs_n)
begin
r_n_data <= i_read_dq;
end
always @(posedge i_nc_clk)
begin
o_n2b_data <= (i_read_dqs) ? r_p_data : r_n_data;
end
always @ (posedge i_nc_clk)
begin
s_n2b_addr_1 <= r_n2b_addr;
s_n2b_addr_2 <= s_n2b_addr_1;
o_n2b_addr <= s_n2b_addr_2;
end
always @ (posedge i_nc_clk)
begin
case(r_current_read_state)
ST_dataout, ST_dataout_end1 :
begin
r_n2b_addr <= (!r_n2b_addr) ? r_n2b_addr : r_n2b_addr - 'b1;
end
default :
begin
r_n2b_addr <= `INIT_PBDEPTH - 'b1 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
s_n2b_en_2 <= s_n2b_en_1;
o_n2b_en <= s_n2b_en_2;
s_n2b_we_2 <= s_n2b_we_1;
o_n2b_we <= s_n2b_we_2;
end
always @ (posedge i_nc_clk)
begin
case(r_current_read_state)
ST_dataout, ST_dataout_end1 :
begin
s_n2b_en_1 <= (r_end_cnt) ? hi : lo;
s_n2b_we_1 <= (r_end_cnt) ? hi : lo;
end
default :
begin
s_n2b_en_1 <= lo ;
s_n2b_we_1 <= lo ;
end
endcase
end
endmodule | 25 |
137,333 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v | 77,907,036 | sync_read_top.v | v | 294 | 95 | [] | ['general public license', 'free software foundation'] | [] | [(211, 457)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:45: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:65: Define or directive not defined: \'`CIO_WD\'\n input wire [`CIO_WD-1:0] i_read_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:67: Define or directive not defined: \'`CIO_WD\'\n output wire [`CIO_WD-1:0] o_read_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:73: Define or directive not defined: \'`CIO_WD\'\n output reg [`CIO_WD-1:0] o_n2b_data ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:74: Define or directive not defined: \'`NAND_PBAWIDTH\'\n output reg [`NAND_PBAWIDTH-1:0] o_n2b_addr ,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:108: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_n2b_sp_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:109: Define or directive not defined: \'`NAND_PBAWIDTH\'\n wire [`NAND_PBAWIDTH-1:0] w_n2b_sp_addr;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:114: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_n2b_dt_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v:115: Define or directive not defined: \'`NAND_PBAWIDTH\'\n wire [`NAND_PBAWIDTH-1:0] w_n2b_dt_addr;\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 295,923 | module | module sync_read_top(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_read_begin ,
output reg o_read_end ,
output wire o_read_ce_n ,
output reg o_read_cle ,
output reg o_read_ale ,
output reg o_read_wr_n ,
input wire [`CIO_WD-1:0] i_read_dq ,
input wire i_read_dqs ,
output wire [`CIO_WD-1:0] o_read_dq ,
output reg o_read_dq_t ,
output wire o_b2m_req ,
input wire i_b2m_cmplt ,
output reg o_sp_en ,
output reg [`CIO_WD-1:0] o_n2b_data ,
output reg [`NAND_PBAWIDTH-1:0] o_n2b_addr ,
output reg o_n2b_en ,
output reg o_n2b_we
);
reg [2:0] r_current_state;
reg [2:0] r_next_state;
reg r_rd_end_cnt;
wire w_sp_read_end;
wire w_dt_read_end;
reg r_sp_start;
reg r_dt_start;
wire w_sp_start;
wire w_sp_read_cle ;
wire w_sp_read_ale ;
wire w_sp_read_wr_n;
wire w_sp_read_dq_t;
wire w_dt_start;
wire w_dt_read_cle ;
wire w_dt_read_ale ;
wire w_dt_read_wr_n;
wire w_dt_read_dq_t;
wire w_sp_n2b_en;
wire w_sp_n2b_we;
wire [`CIO_WD-1:0] w_n2b_sp_data;
wire [`NAND_PBAWIDTH-1:0] w_n2b_sp_addr;
wire w_dt_n2b_en;
wire w_dt_n2b_we;
wire [`CIO_WD-1:0] w_n2b_dt_data;
wire [`NAND_PBAWIDTH-1:0] w_n2b_dt_addr;
parameter IDLE = 3'b000;
parameter SP_READ_EXECUTE = 3'b001;
parameter SP_READ_END = 3'b011;
parameter DT_READ_EXECUTE = 3'b010;
parameter DT_READ_END = 3'b110;
parameter READ_END = 3'b100;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_current_state <= IDLE;
else r_current_state <= r_next_state;
end
always @ (*)
begin
case(r_current_state)
IDLE: r_next_state <= (i_read_begin) ? SP_READ_EXECUTE : IDLE;
SP_READ_EXECUTE: r_next_state <= (w_sp_read_end) ? SP_READ_END : SP_READ_EXECUTE;
SP_READ_END: r_next_state <= DT_READ_EXECUTE;
DT_READ_EXECUTE: r_next_state <= (w_dt_read_end) ? DT_READ_END : DT_READ_EXECUTE;
DT_READ_END: r_next_state <= READ_END;
READ_END: r_next_state <= (r_rd_end_cnt) ? READ_END : IDLE;
default: r_next_state <= IDLE;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_state)
READ_END:r_rd_end_cnt <= (r_rd_end_cnt) ? r_rd_end_cnt - 'b1 : r_rd_end_cnt;
default: r_rd_end_cnt <= 'b1;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_state)
READ_END: o_read_end <= 'b1;
default: o_read_end <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_state)
IDLE, SP_READ_EXECUTE, SP_READ_END: o_sp_en <= 'b1;
default: o_sp_en <= 'b0;
endcase
end
always @ (*)
begin
case(r_current_state)
SP_READ_EXECUTE:
begin
r_sp_start <= 'b1;
r_dt_start <= 'b0;
end
DT_READ_EXECUTE:
begin
r_sp_start <= 'b0;
r_dt_start <= 'b1;
end
default:
begin
r_sp_start <= 'b0;
r_dt_start <= 'b0;
end
endcase
end
assign o_read_ce_n = 'b0;
assign o_read_dq = 'b0;
always @ (posedge i_nc_clk)
begin
case({w_sp_start, w_dt_start})
2'b10:
begin
o_read_cle <= w_sp_read_cle ;
o_read_ale <= w_sp_read_ale ;
o_read_wr_n <= w_sp_read_wr_n;
o_read_dq_t <= w_sp_read_dq_t;
end
2'b01:
begin
o_read_cle <= w_dt_read_cle ;
o_read_ale <= w_dt_read_ale ;
o_read_wr_n <= w_dt_read_wr_n;
o_read_dq_t <= w_dt_read_dq_t;
end
default:
begin
o_read_cle <= 'b0;
o_read_ale <= 'b0;
o_read_wr_n <= 'b1;
o_read_dq_t <= 'b1;
end
endcase
end
always @ (posedge i_nc_clk)
begin
o_n2b_en <= |{w_sp_n2b_en, w_dt_n2b_en};
o_n2b_we <= |{w_sp_n2b_we, w_dt_n2b_we};
end
always @ (posedge i_nc_clk)
begin
case({w_sp_start, w_dt_start})
2'b10:
begin
o_n2b_data <= w_n2b_sp_data;
o_n2b_addr <= w_n2b_sp_addr;
end
2'b01:
begin
o_n2b_data <= w_n2b_dt_data;
o_n2b_addr <= w_n2b_dt_addr;
end
default:
begin
o_n2b_data <= 'b0;
o_n2b_addr <= 'b0;
end
endcase
end
sync_read_sp sync_read_sp0(
.i_nc_clk (i_nc_clk ),
.i_clk_o (i_clk_o ),
.i_nc_rstn (i_nc_rstn),
.o_read_cle (w_sp_read_cle ),
.o_read_ale (w_sp_read_ale ),
.o_read_wr_n (w_sp_read_wr_n),
.o_read_dq_t (w_sp_read_dq_t),
.i_read_dq (i_read_dq),
.i_read_dqs (i_read_dqs),
.o_n2b_data (w_n2b_sp_data),
.o_n2b_addr (w_n2b_sp_addr),
.o_n2b_en (w_sp_n2b_en),
.o_n2b_we (w_sp_n2b_we),
.o_sp_start (w_sp_start),
.i_sp_start (r_sp_start),
.o_sp_read_end (w_sp_read_end)
);
sync_read_dt sync_read_dt0(
.i_nc_clk (i_nc_clk ),
.i_clk_o (i_clk_o ),
.i_nc_rstn (i_nc_rstn),
.o_read_cle (w_dt_read_cle ),
.o_read_ale (w_dt_read_ale ),
.o_read_wr_n (w_dt_read_wr_n),
.o_read_dq_t (w_dt_read_dq_t),
.i_read_dq (i_read_dq),
.i_read_dqs (i_read_dqs),
.o_b2m_req (o_b2m_req ),
.i_b2m_cmplt (i_b2m_cmplt),
.o_n2b_data (w_n2b_dt_data),
.o_n2b_addr (w_n2b_dt_addr),
.o_n2b_en (w_dt_n2b_en),
.o_n2b_we (w_dt_n2b_we),
.o_dt_start (w_dt_start),
.i_dt_start (r_dt_start),
.o_dt_read_end (w_dt_read_end)
);
endmodule | module sync_read_top(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_read_begin ,
output reg o_read_end ,
output wire o_read_ce_n ,
output reg o_read_cle ,
output reg o_read_ale ,
output reg o_read_wr_n ,
input wire [`CIO_WD-1:0] i_read_dq ,
input wire i_read_dqs ,
output wire [`CIO_WD-1:0] o_read_dq ,
output reg o_read_dq_t ,
output wire o_b2m_req ,
input wire i_b2m_cmplt ,
output reg o_sp_en ,
output reg [`CIO_WD-1:0] o_n2b_data ,
output reg [`NAND_PBAWIDTH-1:0] o_n2b_addr ,
output reg o_n2b_en ,
output reg o_n2b_we
); |
reg [2:0] r_current_state;
reg [2:0] r_next_state;
reg r_rd_end_cnt;
wire w_sp_read_end;
wire w_dt_read_end;
reg r_sp_start;
reg r_dt_start;
wire w_sp_start;
wire w_sp_read_cle ;
wire w_sp_read_ale ;
wire w_sp_read_wr_n;
wire w_sp_read_dq_t;
wire w_dt_start;
wire w_dt_read_cle ;
wire w_dt_read_ale ;
wire w_dt_read_wr_n;
wire w_dt_read_dq_t;
wire w_sp_n2b_en;
wire w_sp_n2b_we;
wire [`CIO_WD-1:0] w_n2b_sp_data;
wire [`NAND_PBAWIDTH-1:0] w_n2b_sp_addr;
wire w_dt_n2b_en;
wire w_dt_n2b_we;
wire [`CIO_WD-1:0] w_n2b_dt_data;
wire [`NAND_PBAWIDTH-1:0] w_n2b_dt_addr;
parameter IDLE = 3'b000;
parameter SP_READ_EXECUTE = 3'b001;
parameter SP_READ_END = 3'b011;
parameter DT_READ_EXECUTE = 3'b010;
parameter DT_READ_END = 3'b110;
parameter READ_END = 3'b100;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_current_state <= IDLE;
else r_current_state <= r_next_state;
end
always @ (*)
begin
case(r_current_state)
IDLE: r_next_state <= (i_read_begin) ? SP_READ_EXECUTE : IDLE;
SP_READ_EXECUTE: r_next_state <= (w_sp_read_end) ? SP_READ_END : SP_READ_EXECUTE;
SP_READ_END: r_next_state <= DT_READ_EXECUTE;
DT_READ_EXECUTE: r_next_state <= (w_dt_read_end) ? DT_READ_END : DT_READ_EXECUTE;
DT_READ_END: r_next_state <= READ_END;
READ_END: r_next_state <= (r_rd_end_cnt) ? READ_END : IDLE;
default: r_next_state <= IDLE;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_state)
READ_END:r_rd_end_cnt <= (r_rd_end_cnt) ? r_rd_end_cnt - 'b1 : r_rd_end_cnt;
default: r_rd_end_cnt <= 'b1;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_state)
READ_END: o_read_end <= 'b1;
default: o_read_end <= 'b0;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_state)
IDLE, SP_READ_EXECUTE, SP_READ_END: o_sp_en <= 'b1;
default: o_sp_en <= 'b0;
endcase
end
always @ (*)
begin
case(r_current_state)
SP_READ_EXECUTE:
begin
r_sp_start <= 'b1;
r_dt_start <= 'b0;
end
DT_READ_EXECUTE:
begin
r_sp_start <= 'b0;
r_dt_start <= 'b1;
end
default:
begin
r_sp_start <= 'b0;
r_dt_start <= 'b0;
end
endcase
end
assign o_read_ce_n = 'b0;
assign o_read_dq = 'b0;
always @ (posedge i_nc_clk)
begin
case({w_sp_start, w_dt_start})
2'b10:
begin
o_read_cle <= w_sp_read_cle ;
o_read_ale <= w_sp_read_ale ;
o_read_wr_n <= w_sp_read_wr_n;
o_read_dq_t <= w_sp_read_dq_t;
end
2'b01:
begin
o_read_cle <= w_dt_read_cle ;
o_read_ale <= w_dt_read_ale ;
o_read_wr_n <= w_dt_read_wr_n;
o_read_dq_t <= w_dt_read_dq_t;
end
default:
begin
o_read_cle <= 'b0;
o_read_ale <= 'b0;
o_read_wr_n <= 'b1;
o_read_dq_t <= 'b1;
end
endcase
end
always @ (posedge i_nc_clk)
begin
o_n2b_en <= |{w_sp_n2b_en, w_dt_n2b_en};
o_n2b_we <= |{w_sp_n2b_we, w_dt_n2b_we};
end
always @ (posedge i_nc_clk)
begin
case({w_sp_start, w_dt_start})
2'b10:
begin
o_n2b_data <= w_n2b_sp_data;
o_n2b_addr <= w_n2b_sp_addr;
end
2'b01:
begin
o_n2b_data <= w_n2b_dt_data;
o_n2b_addr <= w_n2b_dt_addr;
end
default:
begin
o_n2b_data <= 'b0;
o_n2b_addr <= 'b0;
end
endcase
end
sync_read_sp sync_read_sp0(
.i_nc_clk (i_nc_clk ),
.i_clk_o (i_clk_o ),
.i_nc_rstn (i_nc_rstn),
.o_read_cle (w_sp_read_cle ),
.o_read_ale (w_sp_read_ale ),
.o_read_wr_n (w_sp_read_wr_n),
.o_read_dq_t (w_sp_read_dq_t),
.i_read_dq (i_read_dq),
.i_read_dqs (i_read_dqs),
.o_n2b_data (w_n2b_sp_data),
.o_n2b_addr (w_n2b_sp_addr),
.o_n2b_en (w_sp_n2b_en),
.o_n2b_we (w_sp_n2b_we),
.o_sp_start (w_sp_start),
.i_sp_start (r_sp_start),
.o_sp_read_end (w_sp_read_end)
);
sync_read_dt sync_read_dt0(
.i_nc_clk (i_nc_clk ),
.i_clk_o (i_clk_o ),
.i_nc_rstn (i_nc_rstn),
.o_read_cle (w_dt_read_cle ),
.o_read_ale (w_dt_read_ale ),
.o_read_wr_n (w_dt_read_wr_n),
.o_read_dq_t (w_dt_read_dq_t),
.i_read_dq (i_read_dq),
.i_read_dqs (i_read_dqs),
.o_b2m_req (o_b2m_req ),
.i_b2m_cmplt (i_b2m_cmplt),
.o_n2b_data (w_n2b_dt_data),
.o_n2b_addr (w_n2b_dt_addr),
.o_n2b_en (w_dt_n2b_en),
.o_n2b_we (w_dt_n2b_we),
.o_dt_start (w_dt_start),
.i_dt_start (r_dt_start),
.o_dt_read_end (w_dt_read_end)
);
endmodule | 25 |
137,334 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v | 77,907,036 | sync_setting.v | v | 520 | 176 | [] | ['general public license', 'free software foundation'] | [] | [(217, 683)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:51: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:69: Define or directive not defined: \'`CIO_WD\'\n output wire [`CIO_WD-1:0] o_set_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:96: Define or directive not defined: \'`IO_WD\'\n reg [`IO_WD-1 :0] r_set_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:105: Define or directive not defined: \'`CLST\'\n for (i=0 ; i<`CLST ; i=i+1) \n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0 ; i<`CLST ; i=i+1) \n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:107: Define or directive not defined: \'`IO_WD\'\n assign o_set_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_set_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:107: Define or directive not defined: \'`IO_WD\'\n assign o_set_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_set_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v:519: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n' | 295,924 | module | module sync_setting(
input wire i_nc_clk ,
input wire i_nc_rstn ,
input wire i_mode_ch_en_n ,
output reg o_mode_ch_ready ,
output reg o_mode_ch_begin ,
input wire i_ch_gnt ,
output reg o_ch_req ,
output reg o_m_ch_cmplt ,
input wire i_set_rb_n ,
output wire [`CIO_WD-1:0] o_set_dq ,
output reg o_set_ce_n ,
output reg o_set_cle ,
output reg o_set_ale ,
output reg o_set_wr_n ,
output reg o_set_clk ,
output reg o_set_dq_t
);
reg [3:0] r_current_st_state;
reg [3:0] r_next_st_state ;
reg [3:0] cnt_mode_cmd ;
reg [3:0] cnt_mode_addr ;
reg [4:0] cnt_mode_wait ;
reg [2:0] cnt_mode_datain1 ;
reg [1:0] cnt_mode_datain2 ;
reg [3:0] cnt_mode_data ;
reg [3:0] i_cnt_mode_cmd ;
reg [3:0] i_cnt_mode_addr ;
reg [4:0] i_cnt_mode_wait ;
reg [2:0] i_cnt_mode_datain1 ;
reg [1:0] i_cnt_mode_datain2 ;
reg [3:0] i_cnt_mode_data ;
reg [`IO_WD-1 :0] r_set_dq ;
reg r_set_drive_done ;
wire w_set_slc_mode_begin ;
reg r_set_slc_mode_done ;
genvar i ;
generate
for (i=0 ; i<`CLST ; i=i+1)
begin : nand_io
assign o_set_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_set_dq ;
end
endgenerate
parameter ST_setting_idle = 4'b0000;
parameter ST_mode_select_wait_grt = 4'b0001;
parameter ST_mode_select_cmd1 = 4'b0011;
parameter ST_mode_select_cmd2 = 4'b0010;
parameter ST_mode_select_addr1 = 4'b0110;
parameter ST_mode_select_addr2 = 4'b0111;
parameter ST_mode_select_wait = 4'b0101;
parameter ST_mode_select_datain1 = 4'b0100;
parameter ST_mode_select_datain2 = 4'b1100;
parameter ST_mode_ch_wait = 4'b1000;
parameter ST_mode_ch_wait_n = 4'b1010;
parameter ST_mode_ch_end = 4'b1011;
parameter ST_mode_ch_cmpt = 4'b1001;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
parameter set_features = 8'hef;
parameter ch_slc_mode = 8'hbe;
parameter timing_mode_addr = 8'h01;
parameter io_drive_addr = 8'h10;
parameter timing_mode = 8'h12;
parameter io_drive = 8'h00;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_current_st_state <= ST_setting_idle ;
end
else
begin
r_current_st_state <= r_next_st_state ;
end
end
always @ (*)
begin
case(r_current_st_state)
ST_setting_idle :
begin
r_next_st_state <= (!i_mode_ch_en_n) ? ST_mode_select_wait_grt : ST_setting_idle ;
o_ch_req <= 'b0;
end
ST_mode_select_wait_grt:
begin
r_next_st_state <= (i_ch_gnt) ? ST_mode_select_cmd1 : ST_mode_select_wait_grt ;
o_ch_req <= 'b1 ;
end
ST_mode_select_cmd1 :
begin
r_next_st_state <= (i_cnt_mode_cmd == 8) ? ST_mode_select_cmd2 : ST_mode_select_cmd1 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_cmd2 :
begin
r_next_st_state <= (i_cnt_mode_cmd == 12) ? (w_set_slc_mode_begin & (!r_set_slc_mode_done)) ? ST_mode_ch_wait_n : ST_mode_select_addr1 : ST_mode_select_cmd2;
o_ch_req <= 'b1 ;
end
ST_mode_select_addr1 :
begin
r_next_st_state <= (i_cnt_mode_addr == 7) ? ST_mode_select_addr2 : ST_mode_select_addr1 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_addr2 :
begin
r_next_st_state <= (i_cnt_mode_addr == 11) ? ST_mode_select_wait : ST_mode_select_addr2 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_wait :
begin
r_next_st_state <= (i_cnt_mode_wait == 19) ? ST_mode_select_datain1 : ST_mode_select_wait ;
o_ch_req <= 'b1 ;
end
ST_mode_select_datain1 :
begin
r_next_st_state <= (i_cnt_mode_datain1 == 5) ? ST_mode_select_datain2 : ST_mode_select_datain1 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_datain2 :
begin
if(i_cnt_mode_data == 15)
begin
r_next_st_state <= ST_mode_ch_wait ;
end
else
begin
r_next_st_state <= (i_cnt_mode_datain2 == 3) ? ST_mode_select_datain1 : ST_mode_select_datain2 ;
end
o_ch_req <= 'b1 ;
end
ST_mode_ch_wait :
begin
r_next_st_state <= (i_set_rb_n) ? ST_mode_ch_wait : ST_mode_ch_wait_n ;
o_ch_req <= 'b1 ;
end
ST_mode_ch_wait_n :
begin
r_next_st_state <= (!i_set_rb_n) ? ST_mode_ch_wait_n : ST_mode_ch_end ;
o_ch_req <= 'b1 ;
end
ST_mode_ch_end :
begin
r_next_st_state <= (r_set_drive_done & r_set_slc_mode_done) ? ST_mode_ch_cmpt : ST_mode_select_cmd1;
o_ch_req <= 'b1;
end
ST_mode_ch_cmpt :
begin
r_next_st_state <= ST_mode_ch_cmpt;
o_ch_req <= 'b0;
end
default :
begin
r_next_st_state <= ST_setting_idle ;
o_ch_req <= 'b0 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_st_state)
ST_mode_ch_cmpt: o_m_ch_cmplt <= 'b1;
default : o_m_ch_cmplt <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
i_cnt_mode_cmd <= 0 ;
i_cnt_mode_addr <= 0 ;
i_cnt_mode_wait <= 0 ;
i_cnt_mode_datain1<= 0 ;
i_cnt_mode_datain2<= 0 ;
i_cnt_mode_data <= 0 ;
end
else
begin
i_cnt_mode_cmd <= cnt_mode_cmd ;
i_cnt_mode_addr <= cnt_mode_addr ;
i_cnt_mode_wait <= cnt_mode_wait ;
i_cnt_mode_datain1<= cnt_mode_datain1 ;
i_cnt_mode_datain2<= cnt_mode_datain2 ;
i_cnt_mode_data <= cnt_mode_data ;
end
end
always @ (*)
begin
case(r_current_st_state)
ST_mode_select_cmd1, ST_mode_select_cmd2 :
begin
cnt_mode_cmd <= i_cnt_mode_cmd + 1 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_addr1 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= i_cnt_mode_addr + 1 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_addr2 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= i_cnt_mode_addr + 1 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_wait :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= i_cnt_mode_wait + 1 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_datain1 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= (i_cnt_mode_datain1 == 5) ? 0 : i_cnt_mode_datain1 + 1 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= i_cnt_mode_data ;
end
ST_mode_select_datain2 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= (i_cnt_mode_datain2 == 3) ? 0 : i_cnt_mode_datain2 + 1 ;
cnt_mode_data <= i_cnt_mode_data + 1 ;
end
default :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_st_state)
ST_setting_idle, ST_mode_ch_cmpt :
begin
o_set_ce_n <= hi ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
ST_mode_select_cmd1 :
begin
o_set_ce_n <= lo ;
o_set_cle <= hi ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= lo ;
r_set_dq <= (w_set_slc_mode_begin & (!r_set_slc_mode_done)) ? ch_slc_mode : set_features;
o_set_dq_t <= lo ;
end
ST_mode_select_cmd2 :
begin
o_set_ce_n <= lo ;
o_set_cle <= hi ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= (w_set_slc_mode_begin & (!r_set_slc_mode_done)) ? ch_slc_mode : set_features;
o_set_dq_t <= lo ;
end
ST_mode_select_addr1 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= hi ;
o_set_wr_n <= hi ;
o_set_clk <= lo ;
r_set_dq <= (r_set_drive_done) ? timing_mode_addr : io_drive_addr;
o_set_dq_t <= lo ;
end
ST_mode_select_addr2 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= hi ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= (r_set_drive_done) ? timing_mode_addr : io_drive_addr;
o_set_dq_t <= lo ;
end
ST_mode_select_wait :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
ST_mode_select_datain1 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= lo ;
r_set_dq <= (i_cnt_mode_data == 0) ? (r_set_drive_done) ? timing_mode : io_drive : 8'h00 ;
o_set_dq_t <= lo ;
end
ST_mode_select_datain2 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= (i_cnt_mode_data == 0 || i_cnt_mode_data == 1) ? (r_set_drive_done) ? timing_mode : io_drive : 8'h00 ;
o_set_dq_t <= lo ;
end
ST_mode_ch_end :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
default :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_set_drive_done <= 'b0;
else
begin
case(r_current_st_state)
ST_mode_ch_end : r_set_drive_done <= 'b1;
default : r_set_drive_done <= r_set_drive_done;
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_set_slc_mode_done <= 'b0;
else
begin
case(r_current_st_state)
ST_mode_ch_end : r_set_slc_mode_done <= (!r_set_drive_done) ? 'b0 : 'b1;
default : r_set_slc_mode_done <= r_set_slc_mode_done;
endcase
end
end
assign w_set_slc_mode_begin = r_set_drive_done;
always @ (*)
begin
case(r_current_st_state)
ST_setting_idle, ST_mode_select_wait_grt, ST_mode_ch_end, ST_mode_ch_cmpt : o_mode_ch_begin <= 'b0 ;
default : o_mode_ch_begin <= 'b1 ;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_st_state)
ST_setting_idle, ST_mode_ch_cmpt: o_mode_ch_ready <= 'b1 ;
default: o_mode_ch_ready <= 'b0 ;
endcase
end
endmodule | module sync_setting(
input wire i_nc_clk ,
input wire i_nc_rstn ,
input wire i_mode_ch_en_n ,
output reg o_mode_ch_ready ,
output reg o_mode_ch_begin ,
input wire i_ch_gnt ,
output reg o_ch_req ,
output reg o_m_ch_cmplt ,
input wire i_set_rb_n ,
output wire [`CIO_WD-1:0] o_set_dq ,
output reg o_set_ce_n ,
output reg o_set_cle ,
output reg o_set_ale ,
output reg o_set_wr_n ,
output reg o_set_clk ,
output reg o_set_dq_t
); |
reg [3:0] r_current_st_state;
reg [3:0] r_next_st_state ;
reg [3:0] cnt_mode_cmd ;
reg [3:0] cnt_mode_addr ;
reg [4:0] cnt_mode_wait ;
reg [2:0] cnt_mode_datain1 ;
reg [1:0] cnt_mode_datain2 ;
reg [3:0] cnt_mode_data ;
reg [3:0] i_cnt_mode_cmd ;
reg [3:0] i_cnt_mode_addr ;
reg [4:0] i_cnt_mode_wait ;
reg [2:0] i_cnt_mode_datain1 ;
reg [1:0] i_cnt_mode_datain2 ;
reg [3:0] i_cnt_mode_data ;
reg [`IO_WD-1 :0] r_set_dq ;
reg r_set_drive_done ;
wire w_set_slc_mode_begin ;
reg r_set_slc_mode_done ;
genvar i ;
generate
for (i=0 ; i<`CLST ; i=i+1)
begin : nand_io
assign o_set_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_set_dq ;
end
endgenerate
parameter ST_setting_idle = 4'b0000;
parameter ST_mode_select_wait_grt = 4'b0001;
parameter ST_mode_select_cmd1 = 4'b0011;
parameter ST_mode_select_cmd2 = 4'b0010;
parameter ST_mode_select_addr1 = 4'b0110;
parameter ST_mode_select_addr2 = 4'b0111;
parameter ST_mode_select_wait = 4'b0101;
parameter ST_mode_select_datain1 = 4'b0100;
parameter ST_mode_select_datain2 = 4'b1100;
parameter ST_mode_ch_wait = 4'b1000;
parameter ST_mode_ch_wait_n = 4'b1010;
parameter ST_mode_ch_end = 4'b1011;
parameter ST_mode_ch_cmpt = 4'b1001;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
parameter set_features = 8'hef;
parameter ch_slc_mode = 8'hbe;
parameter timing_mode_addr = 8'h01;
parameter io_drive_addr = 8'h10;
parameter timing_mode = 8'h12;
parameter io_drive = 8'h00;
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
r_current_st_state <= ST_setting_idle ;
end
else
begin
r_current_st_state <= r_next_st_state ;
end
end
always @ (*)
begin
case(r_current_st_state)
ST_setting_idle :
begin
r_next_st_state <= (!i_mode_ch_en_n) ? ST_mode_select_wait_grt : ST_setting_idle ;
o_ch_req <= 'b0;
end
ST_mode_select_wait_grt:
begin
r_next_st_state <= (i_ch_gnt) ? ST_mode_select_cmd1 : ST_mode_select_wait_grt ;
o_ch_req <= 'b1 ;
end
ST_mode_select_cmd1 :
begin
r_next_st_state <= (i_cnt_mode_cmd == 8) ? ST_mode_select_cmd2 : ST_mode_select_cmd1 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_cmd2 :
begin
r_next_st_state <= (i_cnt_mode_cmd == 12) ? (w_set_slc_mode_begin & (!r_set_slc_mode_done)) ? ST_mode_ch_wait_n : ST_mode_select_addr1 : ST_mode_select_cmd2;
o_ch_req <= 'b1 ;
end
ST_mode_select_addr1 :
begin
r_next_st_state <= (i_cnt_mode_addr == 7) ? ST_mode_select_addr2 : ST_mode_select_addr1 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_addr2 :
begin
r_next_st_state <= (i_cnt_mode_addr == 11) ? ST_mode_select_wait : ST_mode_select_addr2 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_wait :
begin
r_next_st_state <= (i_cnt_mode_wait == 19) ? ST_mode_select_datain1 : ST_mode_select_wait ;
o_ch_req <= 'b1 ;
end
ST_mode_select_datain1 :
begin
r_next_st_state <= (i_cnt_mode_datain1 == 5) ? ST_mode_select_datain2 : ST_mode_select_datain1 ;
o_ch_req <= 'b1 ;
end
ST_mode_select_datain2 :
begin
if(i_cnt_mode_data == 15)
begin
r_next_st_state <= ST_mode_ch_wait ;
end
else
begin
r_next_st_state <= (i_cnt_mode_datain2 == 3) ? ST_mode_select_datain1 : ST_mode_select_datain2 ;
end
o_ch_req <= 'b1 ;
end
ST_mode_ch_wait :
begin
r_next_st_state <= (i_set_rb_n) ? ST_mode_ch_wait : ST_mode_ch_wait_n ;
o_ch_req <= 'b1 ;
end
ST_mode_ch_wait_n :
begin
r_next_st_state <= (!i_set_rb_n) ? ST_mode_ch_wait_n : ST_mode_ch_end ;
o_ch_req <= 'b1 ;
end
ST_mode_ch_end :
begin
r_next_st_state <= (r_set_drive_done & r_set_slc_mode_done) ? ST_mode_ch_cmpt : ST_mode_select_cmd1;
o_ch_req <= 'b1;
end
ST_mode_ch_cmpt :
begin
r_next_st_state <= ST_mode_ch_cmpt;
o_ch_req <= 'b0;
end
default :
begin
r_next_st_state <= ST_setting_idle ;
o_ch_req <= 'b0 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_st_state)
ST_mode_ch_cmpt: o_m_ch_cmplt <= 'b1;
default : o_m_ch_cmplt <= 'b0;
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
i_cnt_mode_cmd <= 0 ;
i_cnt_mode_addr <= 0 ;
i_cnt_mode_wait <= 0 ;
i_cnt_mode_datain1<= 0 ;
i_cnt_mode_datain2<= 0 ;
i_cnt_mode_data <= 0 ;
end
else
begin
i_cnt_mode_cmd <= cnt_mode_cmd ;
i_cnt_mode_addr <= cnt_mode_addr ;
i_cnt_mode_wait <= cnt_mode_wait ;
i_cnt_mode_datain1<= cnt_mode_datain1 ;
i_cnt_mode_datain2<= cnt_mode_datain2 ;
i_cnt_mode_data <= cnt_mode_data ;
end
end
always @ (*)
begin
case(r_current_st_state)
ST_mode_select_cmd1, ST_mode_select_cmd2 :
begin
cnt_mode_cmd <= i_cnt_mode_cmd + 1 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_addr1 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= i_cnt_mode_addr + 1 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_addr2 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= i_cnt_mode_addr + 1 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_wait :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= i_cnt_mode_wait + 1 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
ST_mode_select_datain1 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= (i_cnt_mode_datain1 == 5) ? 0 : i_cnt_mode_datain1 + 1 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= i_cnt_mode_data ;
end
ST_mode_select_datain2 :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= (i_cnt_mode_datain2 == 3) ? 0 : i_cnt_mode_datain2 + 1 ;
cnt_mode_data <= i_cnt_mode_data + 1 ;
end
default :
begin
cnt_mode_cmd <= 0 ;
cnt_mode_addr <= 0 ;
cnt_mode_wait <= 0 ;
cnt_mode_datain1 <= 0 ;
cnt_mode_datain2 <= 0 ;
cnt_mode_data <= 0 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_st_state)
ST_setting_idle, ST_mode_ch_cmpt :
begin
o_set_ce_n <= hi ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
ST_mode_select_cmd1 :
begin
o_set_ce_n <= lo ;
o_set_cle <= hi ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= lo ;
r_set_dq <= (w_set_slc_mode_begin & (!r_set_slc_mode_done)) ? ch_slc_mode : set_features;
o_set_dq_t <= lo ;
end
ST_mode_select_cmd2 :
begin
o_set_ce_n <= lo ;
o_set_cle <= hi ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= (w_set_slc_mode_begin & (!r_set_slc_mode_done)) ? ch_slc_mode : set_features;
o_set_dq_t <= lo ;
end
ST_mode_select_addr1 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= hi ;
o_set_wr_n <= hi ;
o_set_clk <= lo ;
r_set_dq <= (r_set_drive_done) ? timing_mode_addr : io_drive_addr;
o_set_dq_t <= lo ;
end
ST_mode_select_addr2 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= hi ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= (r_set_drive_done) ? timing_mode_addr : io_drive_addr;
o_set_dq_t <= lo ;
end
ST_mode_select_wait :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
ST_mode_select_datain1 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= lo ;
r_set_dq <= (i_cnt_mode_data == 0) ? (r_set_drive_done) ? timing_mode : io_drive : 8'h00 ;
o_set_dq_t <= lo ;
end
ST_mode_select_datain2 :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= (i_cnt_mode_data == 0 || i_cnt_mode_data == 1) ? (r_set_drive_done) ? timing_mode : io_drive : 8'h00 ;
o_set_dq_t <= lo ;
end
ST_mode_ch_end :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
default :
begin
o_set_ce_n <= lo ;
o_set_cle <= lo ;
o_set_ale <= lo ;
o_set_wr_n <= hi ;
o_set_clk <= hi ;
r_set_dq <= 8'h0 ;
o_set_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_set_drive_done <= 'b0;
else
begin
case(r_current_st_state)
ST_mode_ch_end : r_set_drive_done <= 'b1;
default : r_set_drive_done <= r_set_drive_done;
endcase
end
end
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn) r_set_slc_mode_done <= 'b0;
else
begin
case(r_current_st_state)
ST_mode_ch_end : r_set_slc_mode_done <= (!r_set_drive_done) ? 'b0 : 'b1;
default : r_set_slc_mode_done <= r_set_slc_mode_done;
endcase
end
end
assign w_set_slc_mode_begin = r_set_drive_done;
always @ (*)
begin
case(r_current_st_state)
ST_setting_idle, ST_mode_select_wait_grt, ST_mode_ch_end, ST_mode_ch_cmpt : o_mode_ch_begin <= 'b0 ;
default : o_mode_ch_begin <= 'b1 ;
endcase
end
always @ (posedge i_nc_clk)
begin
case(r_current_st_state)
ST_setting_idle, ST_mode_ch_cmpt: o_mode_ch_ready <= 'b1 ;
default: o_mode_ch_ready <= 'b0 ;
endcase
end
endmodule | 25 |
137,335 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v | 77,907,036 | sync_status.v | v | 431 | 115 | [] | ['general public license', 'free software foundation'] | [] | [(214, 595)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:48: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:63: Define or directive not defined: \'`CIO_WD\'\n output reg [`CIO_WD-1:0] o_st_data ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:72: Define or directive not defined: \'`CIO_WD\'\n input wire [`CIO_WD-1:0] i_st_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:75: Define or directive not defined: \'`CIO_WD\'\n output wire [`CIO_WD-1:0] o_st_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:92: Define or directive not defined: \'`IO_WD\'\n reg [`IO_WD-1 :0] r_status_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:96: Define or directive not defined: \'`CLST\'\n for (i=0 ; i<`CLST ; i=i+1) \n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0 ; i<`CLST ; i=i+1) \n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:98: Define or directive not defined: \'`IO_WD\'\n assign o_st_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_status_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:98: Define or directive not defined: \'`IO_WD\'\n assign o_st_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_status_dq ;\n ^~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:398: Define or directive not defined: \'`CIO_WD\'\n o_st_data <= `CIO_WD\'b0 ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v:431: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n' | 295,925 | module | module sync_status(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_status_read_begin ,
output reg o_status_read_end ,
output reg o_st_begin ,
output reg o_st_data_cp ,
output reg [`CIO_WD-1:0] o_st_data ,
output reg o_st_ce_n ,
output reg o_st_cle ,
output reg o_st_ale ,
output reg o_st_wr_n ,
input wire [`CIO_WD-1:0] i_st_dq ,
input wire i_st_dqs ,
output wire o_sta_rdy ,
output wire [`CIO_WD-1:0] o_st_dq ,
output reg o_st_dq_t
);
reg [3:0] current_status_state ;
reg [3:0] next_status_state ;
reg [1:0] r_ready_cnt ;
reg [2:0] r_cnt_setup_ce ;
reg r_cnt_cmd_input ;
reg r_begin_cnt;
reg r_st_begin_cnt;
reg [1:0] r_st_data_ready_cnt;
reg [1:0] r_st_data_cp_cnt;
reg [`IO_WD-1 :0] r_status_dq ;
genvar i ;
generate
for (i=0 ; i<`CLST ; i=i+1)
begin : nand_io
assign o_st_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_status_dq ;
end
endgenerate
parameter ST_status_idle = 4'b0000;
parameter ST_status_setup_ce = 4'b0001;
parameter ST_status_cmd_input = 4'b0011;
parameter ST_status_begin = 4'b0010;
parameter ST_status_ready = 4'b0110;
parameter ST_status = 4'b0111;
parameter ST_status_out = 4'b0101;
parameter ST_status_cp = 4'b0100;
parameter ST_status_cp_end = 4'b1100;
parameter ST_status_end = 4'b1000;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
assign o_sta_rdy = o_st_data[5];
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
current_status_state <= ST_status_idle ;
end
else
begin
current_status_state <= next_status_state ;
end
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_setup_ce :
begin
r_cnt_setup_ce <= r_cnt_setup_ce-'b1 ;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_cmd_input :
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= r_cnt_cmd_input-'b1 ;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_begin :
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= r_begin_cnt-'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_ready:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= r_ready_cnt-'b1;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= r_st_begin_cnt-'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_out:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <= r_st_data_ready_cnt-'b1;
r_st_data_cp_cnt <= 'h3;
end
ST_status_cp_end:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <= 'h2;
r_st_data_cp_cnt <= r_st_data_cp_cnt-'b1;
end
default :
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
endcase
end
always @ (*)
begin
case(current_status_state)
ST_status_idle :
begin
next_status_state <= (i_status_read_begin&&(!i_clk_o)) ? ST_status_setup_ce : ST_status_idle ;
o_st_begin <= 'b0;
end
ST_status_setup_ce :
begin
next_status_state <= (r_cnt_setup_ce) ? ST_status_setup_ce : ST_status_cmd_input ;
o_st_begin <= 'b1;
end
ST_status_cmd_input :
begin
next_status_state <= (r_cnt_cmd_input) ? ST_status_cmd_input : ST_status_begin ;
o_st_begin <= 'b1;
end
ST_status_begin :
begin
next_status_state <= (r_begin_cnt) ? ST_status_begin : ST_status_ready ;
o_st_begin <= 'b1;
end
ST_status_ready :
begin
next_status_state <= (r_ready_cnt) ? ST_status_ready : ST_status;
o_st_begin <= 'b1;
end
ST_status :
begin
next_status_state <= (r_st_begin_cnt) ? ST_status : ST_status_out ;
o_st_begin <= 'b1;
end
ST_status_out :
begin
next_status_state <= (r_st_data_ready_cnt) ? ST_status_out : ST_status_cp ;
o_st_begin <= 'b1;
end
ST_status_cp :
begin
next_status_state <= ST_status_cp_end ;
o_st_begin <= 'b1;
end
ST_status_cp_end :
begin
next_status_state <= (r_st_data_cp_cnt) ? ST_status_cp_end : ST_status_end ;
o_st_begin <= 'b1;
end
ST_status_end :
begin
next_status_state <= ST_status_idle ;
o_st_begin <= 'b1;
end
default :
begin
next_status_state <= ST_status_idle ;
o_st_begin <= 'b0;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_idle :
begin
o_st_ce_n <= hi ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_setup_ce :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_cmd_input :
begin
o_st_ce_n <= lo ;
o_st_cle <= hi ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 8'h70 ;
o_st_dq_t <= lo ;
end
ST_status_begin :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_ready :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= lo ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status :
begin
o_st_ce_n <= lo ;
o_st_cle <= hi ;
o_st_ale <= hi ;
o_st_wr_n <= lo ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_out, ST_status_cp :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= lo ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_cp_end :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
default :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_idle:
begin
o_st_data <= `CIO_WD'b0 ;
o_st_data_cp <= 'b0 ;
end
ST_status_cp, ST_status_cp_end:
begin
o_st_data <= (i_st_dqs) ? i_st_dq : o_st_data;
o_st_data_cp <= 'b1 ;
end
ST_status_end:
begin
o_st_data <= o_st_data ;
o_st_data_cp <= 'b1 ;
end
default:
begin
o_st_data <= o_st_data ;
o_st_data_cp <= 'b1 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_cp_end, ST_status_end: o_status_read_end <= 'b1;
default: o_status_read_end <= 'b0;
endcase
end
endmodule | module sync_status(
input wire i_nc_clk ,
input wire i_clk_o ,
input wire i_nc_rstn ,
input wire i_status_read_begin ,
output reg o_status_read_end ,
output reg o_st_begin ,
output reg o_st_data_cp ,
output reg [`CIO_WD-1:0] o_st_data ,
output reg o_st_ce_n ,
output reg o_st_cle ,
output reg o_st_ale ,
output reg o_st_wr_n ,
input wire [`CIO_WD-1:0] i_st_dq ,
input wire i_st_dqs ,
output wire o_sta_rdy ,
output wire [`CIO_WD-1:0] o_st_dq ,
output reg o_st_dq_t
); |
reg [3:0] current_status_state ;
reg [3:0] next_status_state ;
reg [1:0] r_ready_cnt ;
reg [2:0] r_cnt_setup_ce ;
reg r_cnt_cmd_input ;
reg r_begin_cnt;
reg r_st_begin_cnt;
reg [1:0] r_st_data_ready_cnt;
reg [1:0] r_st_data_cp_cnt;
reg [`IO_WD-1 :0] r_status_dq ;
genvar i ;
generate
for (i=0 ; i<`CLST ; i=i+1)
begin : nand_io
assign o_st_dq[(`IO_WD*(i+1))-1 : `IO_WD*i] = r_status_dq ;
end
endgenerate
parameter ST_status_idle = 4'b0000;
parameter ST_status_setup_ce = 4'b0001;
parameter ST_status_cmd_input = 4'b0011;
parameter ST_status_begin = 4'b0010;
parameter ST_status_ready = 4'b0110;
parameter ST_status = 4'b0111;
parameter ST_status_out = 4'b0101;
parameter ST_status_cp = 4'b0100;
parameter ST_status_cp_end = 4'b1100;
parameter ST_status_end = 4'b1000;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
assign o_sta_rdy = o_st_data[5];
always @ (posedge i_nc_clk or negedge i_nc_rstn)
begin
if(!i_nc_rstn)
begin
current_status_state <= ST_status_idle ;
end
else
begin
current_status_state <= next_status_state ;
end
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_setup_ce :
begin
r_cnt_setup_ce <= r_cnt_setup_ce-'b1 ;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_cmd_input :
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= r_cnt_cmd_input-'b1 ;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_begin :
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= r_begin_cnt-'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_ready:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= r_ready_cnt-'b1;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= r_st_begin_cnt-'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
ST_status_out:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <= r_st_data_ready_cnt-'b1;
r_st_data_cp_cnt <= 'h3;
end
ST_status_cp_end:
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <= 'h2;
r_st_data_cp_cnt <= r_st_data_cp_cnt-'b1;
end
default :
begin
r_cnt_setup_ce <= 'h4;
r_cnt_cmd_input <= 'b1;
r_begin_cnt <= 'b1;
r_ready_cnt <= 'h3;
r_st_begin_cnt <= 'b1;
r_st_data_ready_cnt <='h2;
r_st_data_cp_cnt <= 'h3;
end
endcase
end
always @ (*)
begin
case(current_status_state)
ST_status_idle :
begin
next_status_state <= (i_status_read_begin&&(!i_clk_o)) ? ST_status_setup_ce : ST_status_idle ;
o_st_begin <= 'b0;
end
ST_status_setup_ce :
begin
next_status_state <= (r_cnt_setup_ce) ? ST_status_setup_ce : ST_status_cmd_input ;
o_st_begin <= 'b1;
end
ST_status_cmd_input :
begin
next_status_state <= (r_cnt_cmd_input) ? ST_status_cmd_input : ST_status_begin ;
o_st_begin <= 'b1;
end
ST_status_begin :
begin
next_status_state <= (r_begin_cnt) ? ST_status_begin : ST_status_ready ;
o_st_begin <= 'b1;
end
ST_status_ready :
begin
next_status_state <= (r_ready_cnt) ? ST_status_ready : ST_status;
o_st_begin <= 'b1;
end
ST_status :
begin
next_status_state <= (r_st_begin_cnt) ? ST_status : ST_status_out ;
o_st_begin <= 'b1;
end
ST_status_out :
begin
next_status_state <= (r_st_data_ready_cnt) ? ST_status_out : ST_status_cp ;
o_st_begin <= 'b1;
end
ST_status_cp :
begin
next_status_state <= ST_status_cp_end ;
o_st_begin <= 'b1;
end
ST_status_cp_end :
begin
next_status_state <= (r_st_data_cp_cnt) ? ST_status_cp_end : ST_status_end ;
o_st_begin <= 'b1;
end
ST_status_end :
begin
next_status_state <= ST_status_idle ;
o_st_begin <= 'b1;
end
default :
begin
next_status_state <= ST_status_idle ;
o_st_begin <= 'b0;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_idle :
begin
o_st_ce_n <= hi ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_setup_ce :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_cmd_input :
begin
o_st_ce_n <= lo ;
o_st_cle <= hi ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 8'h70 ;
o_st_dq_t <= lo ;
end
ST_status_begin :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_ready :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= lo ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status :
begin
o_st_ce_n <= lo ;
o_st_cle <= hi ;
o_st_ale <= hi ;
o_st_wr_n <= lo ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_out, ST_status_cp :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= lo ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
ST_status_cp_end :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
default :
begin
o_st_ce_n <= lo ;
o_st_cle <= lo ;
o_st_ale <= lo ;
o_st_wr_n <= hi ;
r_status_dq <= 0 ;
o_st_dq_t <= hi ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_idle:
begin
o_st_data <= `CIO_WD'b0 ;
o_st_data_cp <= 'b0 ;
end
ST_status_cp, ST_status_cp_end:
begin
o_st_data <= (i_st_dqs) ? i_st_dq : o_st_data;
o_st_data_cp <= 'b1 ;
end
ST_status_end:
begin
o_st_data <= o_st_data ;
o_st_data_cp <= 'b1 ;
end
default:
begin
o_st_data <= o_st_data ;
o_st_data_cp <= 'b1 ;
end
endcase
end
always @ (posedge i_nc_clk)
begin
case(current_status_state)
ST_status_cp_end, ST_status_end: o_status_read_end <= 'b1;
default: o_status_read_end <= 'b0;
endcase
end
endmodule | 25 |
137,336 | data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v | 77,907,036 | sync_top.v | v | 464 | 128 | [] | ['general public license', 'free software foundation'] | [] | [(215, 627)] | null | null | 1: b'%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:49: Cannot find include file: parameter.vh\n`include "parameter.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.v\n data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog,data/full_repos/permissive/77907036/parameter.vh.sv\n parameter.vh\n parameter.vh.v\n parameter.vh.sv\n obj_dir/parameter.vh\n obj_dir/parameter.vh.v\n obj_dir/parameter.vh.sv\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:56: Define or directive not defined: \'`CMD_WD\'\n input wire [`CMD_WD-1:0] i_command,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:64: Define or directive not defined: \'`CIO_WD\'\n output reg [`CIO_WD-1:0] o_status,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:71: Define or directive not defined: \'`NAND_PBAWIDTH\'\n output reg [`NAND_PBAWIDTH-1:0] o_pb_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:72: Define or directive not defined: \'`CIO_WD\'\n input wire [`CIO_WD-1:0] i_pb_data, \n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:73: Define or directive not defined: \'`CIO_WD\'\n output wire [`CIO_WD-1:0] o_pb_data, \n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:79: Define or directive not defined: \'`NADDR_WD\'\n input wire [`NADDR_WD-1:0] i_nand_addr ,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:80: Define or directive not defined: \'`CIO_WD\'\n input wire [`CIO_WD-1:0] i_nand_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:81: Define or directive not defined: \'`CIO_WD\'\n output reg [`CIO_WD-1:0] o_nand_dq ,\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:107: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_set_dq_o ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:133: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_rst_status ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:135: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_rst_io_o ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:145: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_op_dq_o ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:156: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_read_dq_o ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:161: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_prog_dq_o ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:173: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_st_dq_o ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:176: Define or directive not defined: \'`CIO_WD\'\n wire [`CIO_WD-1:0] w_st_data ;\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:192: Define or directive not defined: \'`NAND_PBAWIDTH\'\n wire [`NAND_PBAWIDTH-1:0] w_n2b_addr ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:196: Define or directive not defined: \'`NAND_PBAWIDTH\'\n wire [`NAND_PBAWIDTH-1:0] w_b2n_addr ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:247: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n `CMD_RESET :\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:247: syntax error, unexpected \':\', expecting endcase\n `CMD_RESET :\n ^\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:254: Define or directive not defined: \'`CMD_MODE_CHANGE\'\n `CMD_MODE_CHANGE :\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:255: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:261: syntax error, unexpected default\n default :\n ^~~~~~~\n%Error: data/full_repos/permissive/77907036/Source/Predefined_Project/OpenSSD2_4Ch4Way/pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v:267: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: Exiting due to 25 error(s)\n' | 295,926 | module | module sync_top(
input wire i_nc_clk ,
input wire i_nc_rstn,
input wire [`CMD_WD-1:0] i_command,
input wire i_cmd_ack,
output wire o_maddr_ack,
output wire o_b2m_req,
input wire i_b2m_cmplt,
output wire o_m2b_req,
input wire i_m2b_cmplt,
output wire o_ready,
output reg [`CIO_WD-1:0] o_status,
output wire o_ch_req,
input wire i_ch_gnt,
output reg [`NAND_PBAWIDTH-1:0] o_pb_addr,
input wire [`CIO_WD-1:0] i_pb_data,
output wire [`CIO_WD-1:0] o_pb_data,
output wire o_pb_en,
output wire o_pb_we,
input wire i_clk_o ,
input wire [`NADDR_WD-1:0] i_nand_addr ,
input wire [`CIO_WD-1:0] i_nand_dq ,
output reg [`CIO_WD-1:0] o_nand_dq ,
output wire o_nand_dq_t ,
output wire o_nand_cle ,
output wire o_nand_ale ,
output reg o_nand_ce_n ,
output wire o_nand_we_n ,
output wire o_nand_wr_n ,
output wire o_nand_wp_n ,
input wire i_nand_rb ,
input wire i_nand_dqs ,
output wire o_nand_dqs_t,
output wire o_m_ch_cmplt ,
output wire o_dqs_ce ,
output wire o_sp_en ,
output wire o_prog_start ,
output wire o_prog_end ,
output wire o_read_start ,
output wire o_read_end ,
output wire o_erase_start ,
output wire o_erase_end
);
wire [`CIO_WD-1:0] w_set_dq_o ;
wire w_set_ce_n ;
wire s_CLE ;
wire s_ALE ;
wire s_W_R_n ;
wire s_CLK_out ;
wire w_mode_ch_ready ;
wire w_mode_ch_req ;
reg r_mode_ch_en_n ;
wire flag_dataout_end ;
wire flag_datain_end ;
wire w_status_read_end ;
wire w_read_begin ;
wire w_prog_begin ;
wire flag_status_begin ;
wire w_op_ready ;
reg r_reset_en_n ;
reg r_op_en_n ;
wire w_rst_ready ;
wire w_rst_ch_req ;
wire w_op_ch_req ;
wire [`CIO_WD-1:0] w_rst_status ;
wire [`CIO_WD-1:0] w_rst_io_o ;
wire w_rst_io_t ;
wire w_rst_cle ;
wire w_rst_ce_n ;
wire w_rst_we_n ;
wire w_rst_re_n ;
wire w_rst_begin;
wire w_asyn_st_cp;
wire [`CIO_WD-1:0] w_op_dq_o ;
wire w_op_ce_n ;
wire op_CLE ;
wire op_ALE ;
wire op_W_R_n ;
wire w_read_ce_n ;
wire do_CLE ;
wire do_ALE ;
wire do_W_R_n ;
wire [`CIO_WD-1:0] w_read_dq_o ;
wire w_read_dq_t ;
wire w_r_sp_en ;
wire [`CIO_WD-1:0] w_prog_dq_o ;
wire w_prog_ce_n ;
wire di_CLE ;
wire di_ALE ;
wire di_W_R_n ;
wire w_p_sp_en ;
wire w_st_ce_n ;
wire st_CLE ;
wire st_ALE ;
wire st_W_R_n ;
wire [`CIO_WD-1:0] w_st_dq_o ;
wire w_st_dq_t ;
wire w_st_begin ;
wire [`CIO_WD-1:0] w_st_data ;
wire w_sync_st_cp;
wire w_op_dq_t ;
wire w_op_dqs_t ;
wire w_prog_dqs_t ;
wire w_prog_dq_t ;
wire w_set_dq_t ;
wire w_sta_rdy ;
wire w_mode_ch_begin ;
wire [`NAND_PBAWIDTH-1:0] w_n2b_addr ;
wire w_n2b_en ;
wire w_n2b_we ;
wire [`NAND_PBAWIDTH-1:0] w_b2n_addr ;
wire w_b2n_en ;
wire w_b2n_we ;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
assign o_nand_dq_t = &{w_op_dq_t, w_set_dq_t, w_read_dq_t, w_prog_dq_t, w_st_dq_t, w_rst_io_t} ;
assign o_nand_dqs_t = &{w_op_dqs_t, w_prog_dqs_t} ;
assign o_pb_en = |{w_n2b_en, w_b2n_en} ;
assign o_pb_we = |{w_n2b_we, w_b2n_we} ;
assign o_ch_req =|{w_rst_ch_req, w_mode_ch_req, w_op_ch_req};
assign o_ready = &{w_rst_ready, w_mode_ch_ready, w_op_ready};
assign o_sp_en = &{w_r_sp_en, w_p_sp_en};
assign o_nand_wp_n = 'b1;
assign o_nand_cle = |{w_rst_cle, s_CLE, do_CLE, di_CLE, st_CLE, op_CLE};
assign o_nand_ale = |{s_ALE, do_ALE, di_ALE, st_ALE, op_ALE};
assign o_nand_wr_n = &{w_rst_re_n, s_W_R_n, do_W_R_n, di_W_R_n, st_W_R_n, op_W_R_n};
assign o_nand_we_n = &{w_rst_we_n, s_CLK_out};
always @ (posedge i_nc_clk)
begin
case({w_asyn_st_cp, w_sync_st_cp})
2'b10 : o_status <= w_rst_status;
2'b01 : o_status <= w_st_data ;
default : o_status <= o_status ;
endcase
end
always @ (*)
begin
case({w_read_begin, w_prog_begin})
2'b10 : o_pb_addr <= w_n2b_addr ;
2'b01 : o_pb_addr <= w_b2n_addr ;
default : o_pb_addr <= 'hfff ;
endcase
end
always @ (*)
begin
if (i_cmd_ack)
begin
case (i_command)
`CMD_RESET :
begin
r_reset_en_n <= 'b0;
r_op_en_n <= 'b1;
r_mode_ch_en_n <= 'b1 ;
end
`CMD_MODE_CHANGE :
begin
r_reset_en_n <= 'b1;
r_op_en_n <= 'b1;
r_mode_ch_en_n <= 'b0 ;
end
default :
begin
r_reset_en_n <= 'b1;
r_op_en_n <= 'b0;
r_mode_ch_en_n <= 'b1 ;
end
endcase
end
else
begin
r_reset_en_n <= 'b1;
r_op_en_n <= 'b1;
r_mode_ch_en_n <= 'b1 ;
end
end
reset reset0(
.i_nc_clk (i_nc_clk),
.i_nc_rstn (i_nc_rstn),
.i_en_n (r_reset_en_n),
.o_ready (w_rst_ready),
.o_rst_begin (w_rst_begin),
.o_status (w_rst_status),
.o_st_data_cp (w_asyn_st_cp),
.o_ch_req (w_rst_ch_req),
.i_ch_gnt (i_ch_gnt),
.i_nand_io (i_nand_dq ),
.o_nand_io (w_rst_io_o),
.o_nand_io_t (w_rst_io_t),
.o_nand_cle (w_rst_cle ),
.o_nand_ce_n (w_rst_ce_n),
.o_nand_we_n (w_rst_we_n),
.o_nand_re_n (w_rst_re_n),
.i_nand_rb (i_nand_rb )
);
sync_setting sync_setting0(
.i_nc_clk (i_nc_clk),
.i_nc_rstn (i_nc_rstn),
.i_mode_ch_en_n (r_mode_ch_en_n),
.o_mode_ch_ready (w_mode_ch_ready),
.o_mode_ch_begin (w_mode_ch_begin),
.i_ch_gnt (i_ch_gnt),
.o_ch_req (w_mode_ch_req),
.o_m_ch_cmplt (o_m_ch_cmplt),
.i_set_rb_n (i_nand_rb),
.o_set_dq (w_set_dq_o),
.o_set_ce_n (w_set_ce_n),
.o_set_cle (s_CLE),
.o_set_ale (s_ALE),
.o_set_wr_n (s_W_R_n),
.o_set_clk (s_CLK_out),
.o_set_dq_t (w_set_dq_t)
);
sync_op sync_op0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn),
.i_enable (!r_op_en_n),
.i_command (i_command),
.i_nand_addr (i_nand_addr),
.i_read_end (flag_dataout_end),
.i_prog_end (flag_datain_end),
.i_status_read_end (w_status_read_end),
.o_read_begin (w_read_begin),
.o_prog_begin (w_prog_begin),
.o_status_read_begin (flag_status_begin),
.o_prog_start (o_prog_start ),
.o_prog_end (o_prog_end ),
.o_read_start (o_read_start ),
.o_read_end (o_read_end ),
.o_erase_start (o_erase_start),
.o_erase_end (o_erase_end ),
.o_op_dq_t (w_op_dq_t),
.o_op_dqs_t (w_op_dqs_t),
.o_op_dq (w_op_dq_o),
.o_op_ce_n (w_op_ce_n),
.o_op_cle (op_CLE),
.o_op_ale (op_ALE),
.o_op_wr_n (op_W_R_n),
.i_sta_rdy (w_sta_rdy),
.i_ch_gnt (i_ch_gnt),
.o_ch_req (w_op_ch_req),
.o_maddr_ack (o_maddr_ack),
.o_ready (w_op_ready)
);
sync_read_top sync_read_top0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn) ,
.i_read_begin (w_read_begin),
.o_read_end (flag_dataout_end),
.o_read_ce_n (w_read_ce_n),
.o_read_cle (do_CLE),
.o_read_ale (do_ALE),
.o_read_wr_n (do_W_R_n),
.i_read_dq (i_nand_dq),
.i_read_dqs (i_nand_dqs),
.o_read_dq (w_read_dq_o),
.o_read_dq_t (w_read_dq_t),
.o_b2m_req (o_b2m_req),
.i_b2m_cmplt (i_b2m_cmplt),
.o_sp_en (w_r_sp_en),
.o_n2b_data (o_pb_data),
.o_n2b_addr (w_n2b_addr),
.o_n2b_en (w_n2b_en ),
.o_n2b_we (w_n2b_we )
);
sync_prog sync_prog0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn) ,
.i_prog_begin (w_prog_begin),
.o_prog_end (flag_datain_end),
.o_m2b_req (o_m2b_req ),
.i_m2b_cmplt (i_m2b_cmplt),
.o_sp_en (w_p_sp_en),
.o_dqs_ce (o_dqs_ce),
.o_prog_dq (w_prog_dq_o),
.o_prog_ce_n (w_prog_ce_n),
.o_prog_cle (di_CLE),
.o_prog_ale (di_ALE),
.o_prog_wr_n (di_W_R_n),
.o_prog_dqs_t (w_prog_dqs_t),
.o_prog_dq_t (w_prog_dq_t),
.i_b2n_data (i_pb_data),
.o_b2n_addr (w_b2n_addr),
.o_b2n_en (w_b2n_en ),
.o_b2n_we (w_b2n_we )
);
sync_status sync_status0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn) ,
.i_status_read_begin (flag_status_begin),
.o_status_read_end (w_status_read_end),
.o_st_begin (w_st_begin),
.o_st_data_cp (w_sync_st_cp),
.o_st_data (w_st_data),
.o_st_ce_n (w_st_ce_n),
.o_st_cle (st_CLE),
.o_st_ale (st_ALE),
.o_st_wr_n (st_W_R_n),
.i_st_dq (i_nand_dq),
.i_st_dqs (i_nand_dqs),
.o_sta_rdy (w_sta_rdy),
.o_st_dq (w_st_dq_o),
.o_st_dq_t (w_st_dq_t)
);
always @ (*)
begin
case ({w_rst_begin, w_mode_ch_begin, w_read_begin, w_prog_begin, w_st_begin})
5'b1_0000 :
begin
o_nand_dq <= w_rst_io_o;
o_nand_ce_n <= w_rst_ce_n;
end
5'b0_1000 :
begin
o_nand_dq <= w_set_dq_o;
o_nand_ce_n <= w_set_ce_n;
end
5'b0_0100 :
begin
o_nand_dq <= w_read_dq_o;
o_nand_ce_n <= w_read_ce_n;
end
5'b0_0010 :
begin
o_nand_dq <= w_prog_dq_o;
o_nand_ce_n <= w_prog_ce_n;
end
5'b0_0001 :
begin
o_nand_dq <= w_st_dq_o;
o_nand_ce_n <= w_st_ce_n;
end
default :
begin
o_nand_dq <= w_op_dq_o;
o_nand_ce_n <= w_op_ce_n;
end
endcase
end
endmodule | module sync_top(
input wire i_nc_clk ,
input wire i_nc_rstn,
input wire [`CMD_WD-1:0] i_command,
input wire i_cmd_ack,
output wire o_maddr_ack,
output wire o_b2m_req,
input wire i_b2m_cmplt,
output wire o_m2b_req,
input wire i_m2b_cmplt,
output wire o_ready,
output reg [`CIO_WD-1:0] o_status,
output wire o_ch_req,
input wire i_ch_gnt,
output reg [`NAND_PBAWIDTH-1:0] o_pb_addr,
input wire [`CIO_WD-1:0] i_pb_data,
output wire [`CIO_WD-1:0] o_pb_data,
output wire o_pb_en,
output wire o_pb_we,
input wire i_clk_o ,
input wire [`NADDR_WD-1:0] i_nand_addr ,
input wire [`CIO_WD-1:0] i_nand_dq ,
output reg [`CIO_WD-1:0] o_nand_dq ,
output wire o_nand_dq_t ,
output wire o_nand_cle ,
output wire o_nand_ale ,
output reg o_nand_ce_n ,
output wire o_nand_we_n ,
output wire o_nand_wr_n ,
output wire o_nand_wp_n ,
input wire i_nand_rb ,
input wire i_nand_dqs ,
output wire o_nand_dqs_t,
output wire o_m_ch_cmplt ,
output wire o_dqs_ce ,
output wire o_sp_en ,
output wire o_prog_start ,
output wire o_prog_end ,
output wire o_read_start ,
output wire o_read_end ,
output wire o_erase_start ,
output wire o_erase_end
); |
wire [`CIO_WD-1:0] w_set_dq_o ;
wire w_set_ce_n ;
wire s_CLE ;
wire s_ALE ;
wire s_W_R_n ;
wire s_CLK_out ;
wire w_mode_ch_ready ;
wire w_mode_ch_req ;
reg r_mode_ch_en_n ;
wire flag_dataout_end ;
wire flag_datain_end ;
wire w_status_read_end ;
wire w_read_begin ;
wire w_prog_begin ;
wire flag_status_begin ;
wire w_op_ready ;
reg r_reset_en_n ;
reg r_op_en_n ;
wire w_rst_ready ;
wire w_rst_ch_req ;
wire w_op_ch_req ;
wire [`CIO_WD-1:0] w_rst_status ;
wire [`CIO_WD-1:0] w_rst_io_o ;
wire w_rst_io_t ;
wire w_rst_cle ;
wire w_rst_ce_n ;
wire w_rst_we_n ;
wire w_rst_re_n ;
wire w_rst_begin;
wire w_asyn_st_cp;
wire [`CIO_WD-1:0] w_op_dq_o ;
wire w_op_ce_n ;
wire op_CLE ;
wire op_ALE ;
wire op_W_R_n ;
wire w_read_ce_n ;
wire do_CLE ;
wire do_ALE ;
wire do_W_R_n ;
wire [`CIO_WD-1:0] w_read_dq_o ;
wire w_read_dq_t ;
wire w_r_sp_en ;
wire [`CIO_WD-1:0] w_prog_dq_o ;
wire w_prog_ce_n ;
wire di_CLE ;
wire di_ALE ;
wire di_W_R_n ;
wire w_p_sp_en ;
wire w_st_ce_n ;
wire st_CLE ;
wire st_ALE ;
wire st_W_R_n ;
wire [`CIO_WD-1:0] w_st_dq_o ;
wire w_st_dq_t ;
wire w_st_begin ;
wire [`CIO_WD-1:0] w_st_data ;
wire w_sync_st_cp;
wire w_op_dq_t ;
wire w_op_dqs_t ;
wire w_prog_dqs_t ;
wire w_prog_dq_t ;
wire w_set_dq_t ;
wire w_sta_rdy ;
wire w_mode_ch_begin ;
wire [`NAND_PBAWIDTH-1:0] w_n2b_addr ;
wire w_n2b_en ;
wire w_n2b_we ;
wire [`NAND_PBAWIDTH-1:0] w_b2n_addr ;
wire w_b2n_en ;
wire w_b2n_we ;
parameter hi = 1'b1 ;
parameter lo = 1'b0 ;
assign o_nand_dq_t = &{w_op_dq_t, w_set_dq_t, w_read_dq_t, w_prog_dq_t, w_st_dq_t, w_rst_io_t} ;
assign o_nand_dqs_t = &{w_op_dqs_t, w_prog_dqs_t} ;
assign o_pb_en = |{w_n2b_en, w_b2n_en} ;
assign o_pb_we = |{w_n2b_we, w_b2n_we} ;
assign o_ch_req =|{w_rst_ch_req, w_mode_ch_req, w_op_ch_req};
assign o_ready = &{w_rst_ready, w_mode_ch_ready, w_op_ready};
assign o_sp_en = &{w_r_sp_en, w_p_sp_en};
assign o_nand_wp_n = 'b1;
assign o_nand_cle = |{w_rst_cle, s_CLE, do_CLE, di_CLE, st_CLE, op_CLE};
assign o_nand_ale = |{s_ALE, do_ALE, di_ALE, st_ALE, op_ALE};
assign o_nand_wr_n = &{w_rst_re_n, s_W_R_n, do_W_R_n, di_W_R_n, st_W_R_n, op_W_R_n};
assign o_nand_we_n = &{w_rst_we_n, s_CLK_out};
always @ (posedge i_nc_clk)
begin
case({w_asyn_st_cp, w_sync_st_cp})
2'b10 : o_status <= w_rst_status;
2'b01 : o_status <= w_st_data ;
default : o_status <= o_status ;
endcase
end
always @ (*)
begin
case({w_read_begin, w_prog_begin})
2'b10 : o_pb_addr <= w_n2b_addr ;
2'b01 : o_pb_addr <= w_b2n_addr ;
default : o_pb_addr <= 'hfff ;
endcase
end
always @ (*)
begin
if (i_cmd_ack)
begin
case (i_command)
`CMD_RESET :
begin
r_reset_en_n <= 'b0;
r_op_en_n <= 'b1;
r_mode_ch_en_n <= 'b1 ;
end
`CMD_MODE_CHANGE :
begin
r_reset_en_n <= 'b1;
r_op_en_n <= 'b1;
r_mode_ch_en_n <= 'b0 ;
end
default :
begin
r_reset_en_n <= 'b1;
r_op_en_n <= 'b0;
r_mode_ch_en_n <= 'b1 ;
end
endcase
end
else
begin
r_reset_en_n <= 'b1;
r_op_en_n <= 'b1;
r_mode_ch_en_n <= 'b1 ;
end
end
reset reset0(
.i_nc_clk (i_nc_clk),
.i_nc_rstn (i_nc_rstn),
.i_en_n (r_reset_en_n),
.o_ready (w_rst_ready),
.o_rst_begin (w_rst_begin),
.o_status (w_rst_status),
.o_st_data_cp (w_asyn_st_cp),
.o_ch_req (w_rst_ch_req),
.i_ch_gnt (i_ch_gnt),
.i_nand_io (i_nand_dq ),
.o_nand_io (w_rst_io_o),
.o_nand_io_t (w_rst_io_t),
.o_nand_cle (w_rst_cle ),
.o_nand_ce_n (w_rst_ce_n),
.o_nand_we_n (w_rst_we_n),
.o_nand_re_n (w_rst_re_n),
.i_nand_rb (i_nand_rb )
);
sync_setting sync_setting0(
.i_nc_clk (i_nc_clk),
.i_nc_rstn (i_nc_rstn),
.i_mode_ch_en_n (r_mode_ch_en_n),
.o_mode_ch_ready (w_mode_ch_ready),
.o_mode_ch_begin (w_mode_ch_begin),
.i_ch_gnt (i_ch_gnt),
.o_ch_req (w_mode_ch_req),
.o_m_ch_cmplt (o_m_ch_cmplt),
.i_set_rb_n (i_nand_rb),
.o_set_dq (w_set_dq_o),
.o_set_ce_n (w_set_ce_n),
.o_set_cle (s_CLE),
.o_set_ale (s_ALE),
.o_set_wr_n (s_W_R_n),
.o_set_clk (s_CLK_out),
.o_set_dq_t (w_set_dq_t)
);
sync_op sync_op0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn),
.i_enable (!r_op_en_n),
.i_command (i_command),
.i_nand_addr (i_nand_addr),
.i_read_end (flag_dataout_end),
.i_prog_end (flag_datain_end),
.i_status_read_end (w_status_read_end),
.o_read_begin (w_read_begin),
.o_prog_begin (w_prog_begin),
.o_status_read_begin (flag_status_begin),
.o_prog_start (o_prog_start ),
.o_prog_end (o_prog_end ),
.o_read_start (o_read_start ),
.o_read_end (o_read_end ),
.o_erase_start (o_erase_start),
.o_erase_end (o_erase_end ),
.o_op_dq_t (w_op_dq_t),
.o_op_dqs_t (w_op_dqs_t),
.o_op_dq (w_op_dq_o),
.o_op_ce_n (w_op_ce_n),
.o_op_cle (op_CLE),
.o_op_ale (op_ALE),
.o_op_wr_n (op_W_R_n),
.i_sta_rdy (w_sta_rdy),
.i_ch_gnt (i_ch_gnt),
.o_ch_req (w_op_ch_req),
.o_maddr_ack (o_maddr_ack),
.o_ready (w_op_ready)
);
sync_read_top sync_read_top0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn) ,
.i_read_begin (w_read_begin),
.o_read_end (flag_dataout_end),
.o_read_ce_n (w_read_ce_n),
.o_read_cle (do_CLE),
.o_read_ale (do_ALE),
.o_read_wr_n (do_W_R_n),
.i_read_dq (i_nand_dq),
.i_read_dqs (i_nand_dqs),
.o_read_dq (w_read_dq_o),
.o_read_dq_t (w_read_dq_t),
.o_b2m_req (o_b2m_req),
.i_b2m_cmplt (i_b2m_cmplt),
.o_sp_en (w_r_sp_en),
.o_n2b_data (o_pb_data),
.o_n2b_addr (w_n2b_addr),
.o_n2b_en (w_n2b_en ),
.o_n2b_we (w_n2b_we )
);
sync_prog sync_prog0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn) ,
.i_prog_begin (w_prog_begin),
.o_prog_end (flag_datain_end),
.o_m2b_req (o_m2b_req ),
.i_m2b_cmplt (i_m2b_cmplt),
.o_sp_en (w_p_sp_en),
.o_dqs_ce (o_dqs_ce),
.o_prog_dq (w_prog_dq_o),
.o_prog_ce_n (w_prog_ce_n),
.o_prog_cle (di_CLE),
.o_prog_ale (di_ALE),
.o_prog_wr_n (di_W_R_n),
.o_prog_dqs_t (w_prog_dqs_t),
.o_prog_dq_t (w_prog_dq_t),
.i_b2n_data (i_pb_data),
.o_b2n_addr (w_b2n_addr),
.o_b2n_en (w_b2n_en ),
.o_b2n_we (w_b2n_we )
);
sync_status sync_status0(
.i_nc_clk (i_nc_clk),
.i_clk_o (i_clk_o),
.i_nc_rstn (i_nc_rstn) ,
.i_status_read_begin (flag_status_begin),
.o_status_read_end (w_status_read_end),
.o_st_begin (w_st_begin),
.o_st_data_cp (w_sync_st_cp),
.o_st_data (w_st_data),
.o_st_ce_n (w_st_ce_n),
.o_st_cle (st_CLE),
.o_st_ale (st_ALE),
.o_st_wr_n (st_W_R_n),
.i_st_dq (i_nand_dq),
.i_st_dqs (i_nand_dqs),
.o_sta_rdy (w_sta_rdy),
.o_st_dq (w_st_dq_o),
.o_st_dq_t (w_st_dq_t)
);
always @ (*)
begin
case ({w_rst_begin, w_mode_ch_begin, w_read_begin, w_prog_begin, w_st_begin})
5'b1_0000 :
begin
o_nand_dq <= w_rst_io_o;
o_nand_ce_n <= w_rst_ce_n;
end
5'b0_1000 :
begin
o_nand_dq <= w_set_dq_o;
o_nand_ce_n <= w_set_ce_n;
end
5'b0_0100 :
begin
o_nand_dq <= w_read_dq_o;
o_nand_ce_n <= w_read_ce_n;
end
5'b0_0010 :
begin
o_nand_dq <= w_prog_dq_o;
o_nand_ce_n <= w_prog_ce_n;
end
5'b0_0001 :
begin
o_nand_dq <= w_st_dq_o;
o_nand_ce_n <= w_st_ce_n;
end
default :
begin
o_nand_dq <= w_op_dq_o;
o_nand_ce_n <= w_op_ce_n;
end
endcase
end
endmodule | 25 |
137,343 | data/full_repos/permissive/77915656/Jump.v | 77,915,656 | Jump.v | v | 295 | 136 | [] | [] | [] | [(3, 294)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/77915656/Jump.v:17: Little bit endian vector: MSB < LSB of bit range: 0:82\n reg [0:82] body_run [0:73];\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/77915656/Jump.v:18: Little bit endian vector: MSB < LSB of bit range: 0:82\n reg [0:82] body_stop [0:73];\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/77915656/Jump.v:19: Little bit endian vector: MSB < LSB of bit range: 0:82\n reg [0:82] feet_stop [0:13];\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/77915656/Jump.v:20: Little bit endian vector: MSB < LSB of bit range: 0:82\n reg [0:82] feet_run_a [0:13];\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/77915656/Jump.v:21: Little bit endian vector: MSB < LSB of bit range: 0:82\n reg [0:82] feet_run_b [0:13];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:27: Operator DIV expects 12 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance Jump\n assign height = (jump_time*12\'d40 - jump_time*jump_time) / 2\'d2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:62: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n px <= body_run[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:62: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'h13a\' generates 10 bits.\n : ... In instance Jump\n px <= body_run[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:62: Bit extraction of array[73:0] requires 7 bit index, not 12 bits.\n : ... In instance Jump\n px <= body_run[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:62: Operator SUB expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'col_addr\' generates 10 bits.\n : ... In instance Jump\n px <= body_run[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:64: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n px <= body_stop[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:64: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'h13a\' generates 10 bits.\n : ... In instance Jump\n px <= body_stop[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:64: Bit extraction of array[73:0] requires 7 bit index, not 12 bits.\n : ... In instance Jump\n px <= body_stop[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:64: Operator SUB expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'col_addr\' generates 10 bits.\n : ... In instance Jump\n px <= body_stop[row_addr+height-10\'d314][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:60: Operator GTE expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d88 && row_addr < 10\'d402 - height -10\'d14 && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:60: Operator SUB expects 12 bits on the LHS, but LHS\'s CONST \'10\'h192\' generates 10 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d88 && row_addr < 10\'d402 - height -10\'d14 && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:60: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'h58\' generates 10 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d88 && row_addr < 10\'d402 - height -10\'d14 && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:60: Operator LT expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d88 && row_addr < 10\'d402 - height -10\'d14 && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:60: Operator SUB expects 12 bits on the LHS, but LHS\'s CONST \'10\'h192\' generates 10 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d88 && row_addr < 10\'d402 - height -10\'d14 && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:60: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'he\' generates 10 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d88 && row_addr < 10\'d402 - height -10\'d14 && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:76: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n px<=feet_run_a[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:76: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'h184\' generates 10 bits.\n : ... In instance Jump\n px<=feet_run_a[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:76: Bit extraction of array[13:0] requires 4 bit index, not 12 bits.\n : ... In instance Jump\n px<=feet_run_a[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:76: Operator SUB expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'col_addr\' generates 10 bits.\n : ... In instance Jump\n px<=feet_run_a[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:78: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n px<=feet_run_b[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:78: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'h184\' generates 10 bits.\n : ... In instance Jump\n px<=feet_run_b[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:78: Bit extraction of array[13:0] requires 4 bit index, not 12 bits.\n : ... In instance Jump\n px<=feet_run_b[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:78: Operator SUB expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'col_addr\' generates 10 bits.\n : ... In instance Jump\n px<=feet_run_b[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:82: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n px<=feet_stop[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:82: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'h184\' generates 10 bits.\n : ... In instance Jump\n px<=feet_stop[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:82: Bit extraction of array[13:0] requires 4 bit index, not 12 bits.\n : ... In instance Jump\n px<=feet_stop[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:82: Operator SUB expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'col_addr\' generates 10 bits.\n : ... In instance Jump\n px<=feet_stop[row_addr+height-10\'d388][col_addr-12\'d80];\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:72: Operator GTE expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d14 && row_addr < 10\'d402 - height && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:72: Operator SUB expects 12 bits on the LHS, but LHS\'s CONST \'10\'h192\' generates 10 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d14 && row_addr < 10\'d402 - height && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:72: Operator SUB expects 12 bits on the RHS, but RHS\'s CONST \'10\'he\' generates 10 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d14 && row_addr < 10\'d402 - height && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:72: Operator LT expects 12 bits on the LHS, but LHS\'s VARREF \'row_addr\' generates 9 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d14 && row_addr < 10\'d402 - height && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:72: Operator SUB expects 12 bits on the LHS, but LHS\'s CONST \'10\'h192\' generates 10 bits.\n : ... In instance Jump\n if (row_addr >= 10\'d402 - height - 10\'d14 && row_addr < 10\'d402 - height && col_addr>=10\'d80 && col_addr<10\'d162) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:91: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_run[0]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:92: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_run[1]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:93: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_run[2]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:94: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_run[3]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:95: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[4]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:96: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[5]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:97: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[6]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:98: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[7]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:99: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc7ffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[8]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:100: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc7ffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[9]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:101: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc7ffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[10]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:102: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[11]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:103: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[12]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:104: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[13]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:105: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[14]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:106: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[15]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:107: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[16]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:108: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[17]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:109: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[18]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:110: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[19]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:111: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[20]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:112: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[21]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:113: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_run[22]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:114: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffff80000\' generates 82 bits.\n : ... In instance Jump\n body_run[23]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:115: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffff80000\' generates 82 bits.\n : ... In instance Jump\n body_run[24]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:116: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffff80000\' generates 82 bits.\n : ... In instance Jump\n body_run[25]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:117: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000003fffffffff0\' generates 82 bits.\n : ... In instance Jump\n body_run[26]<=82\'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:118: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000003fffffffff0\' generates 82 bits.\n : ... In instance Jump\n body_run[27]<=82\'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:119: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000003ffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[28]<=82\'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:120: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000003ffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[29]<=82\'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:121: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0000000fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[30]<=82\'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:122: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0000000fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[31]<=82\'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:123: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f0000003fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[32]<=82\'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:124: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f0000003fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[33]<=82\'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:125: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000ffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[34]<=82\'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:126: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000ffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[35]<=82\'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:127: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ff0000fffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[36]<=82\'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:128: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ff0000fffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[37]<=82\'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:129: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc003fffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_run[38]<=82\'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:130: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc003fffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_run[39]<=82\'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:131: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fff03ffffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_run[40]<=82\'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:132: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fff03ffffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_run[41]<=82\'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:133: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_run[42]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:134: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_run[43]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:135: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_run[44]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:136: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_run[45]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:137: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[46]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:138: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[47]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:139: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[48]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:140: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[49]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:141: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[50]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:142: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[51]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:143: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[52]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:144: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[53]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:145: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[54]<=82\'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:146: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[55]<=82\'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:147: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[56]<=82\'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:148: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[57]<=82\'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:149: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[58]<=82\'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:150: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[59]<=82\'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:151: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[60]<=82\'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:152: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_run[61]<=82\'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:153: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffff0000000\' generates 82 bits.\n : ... In instance Jump\n body_run[62]<=82\'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:154: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffff0000000\' generates 82 bits.\n : ... In instance Jump\n body_run[63]<=82\'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:155: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffc0000000\' generates 82 bits.\n : ... In instance Jump\n body_run[64]<=82\'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:156: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffc0000000\' generates 82 bits.\n : ... In instance Jump\n body_run[65]<=82\'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:157: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffff00000000\' generates 82 bits.\n : ... In instance Jump\n body_run[66]<=82\'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:158: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffff00000000\' generates 82 bits.\n : ... In instance Jump\n body_run[67]<=82\'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:159: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffc00000000\' generates 82 bits.\n : ... In instance Jump\n body_run[68]<=82\'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:160: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffc00000000\' generates 82 bits.\n : ... In instance Jump\n body_run[69]<=82\'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:161: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffff000000000\' generates 82 bits.\n : ... In instance Jump\n body_run[70]<=82\'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:162: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffff000000000\' generates 82 bits.\n : ... In instance Jump\n body_run[71]<=82\'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:163: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffc000000000\' generates 82 bits.\n : ... In instance Jump\n body_run[72]<=82\'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:164: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffc000000000\' generates 82 bits.\n : ... In instance Jump\n body_run[73]<=82\'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:167: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc3fc000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[0]<=82\'b0000000000_0000000000_1111111111_1100001111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:168: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc3fc000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[1]<=82\'b0000000000_0000000000_1111111111_1100001111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:169: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[2]<=82\'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:170: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[3]<=82\'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:171: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[4]<=82\'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:172: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f0003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[5]<=82\'b0000000000_0000000000_1111110000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:173: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[6]<=82\'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:174: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[7]<=82\'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:175: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[8]<=82\'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:176: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[9]<=82\'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:177: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[10]<=82\'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:178: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[11]<=82\'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:179: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[12]<=82\'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:180: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_stop[13]<=82\'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:183: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc03fc000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[0]<=82\'b0000000000_0000000000_1111111100_0000001111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:184: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc03fc000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[1]<=82\'b0000000000_0000000000_1111111100_0000001111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:185: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[2]<=82\'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:186: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfff03c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[3]<=82\'b0000000000_0000000000_0011111111_1111000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:187: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfff03c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[4]<=82\'b0000000000_0000000000_0011111111_1111000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:188: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[5]<=82\'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:189: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[6]<=82\'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:190: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[7]<=82\'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:191: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[8]<=82\'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:192: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[9]<=82\'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:193: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[10]<=82\'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:194: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[11]<=82\'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:195: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[12]<=82\'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:196: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_a[13]<=82\'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:199: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc03c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[0]<=82\'b0000000000_0000000000_1111111111_1100000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:200: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc03c000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[1]<=82\'b0000000000_0000000000_1111111111_1100000000_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:201: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003ff00000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[2]<=82\'b0000000000_0000000000_1111111100_0000000000_1111111111_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:202: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc003ff00000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[3]<=82\'b0000000000_0000000000_1111111100_0000000000_1111111111_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:203: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc0000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[4]<=82\'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:204: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f00000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[5]<=82\'b0000000000_0000000000_1111110000_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:205: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[6]<=82\'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:206: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[7]<=82\'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:207: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[8]<=82\'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:208: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[9]<=82\'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:209: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc0000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[10]<=82\'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:210: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc0000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[11]<=82\'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:211: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc0000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[12]<=82\'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:212: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc0000000000000\' generates 82 bits.\n : ... In instance Jump\n feet_run_b[13]<=82\'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:216: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[0]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:217: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[1]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:218: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[2]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:219: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[3]<=82\'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:220: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[4]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:221: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[5]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:222: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f03ffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[6]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:223: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f03ffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[7]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:224: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f33ffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[8]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_0011001111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:225: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f33ffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[9]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_0011001111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:226: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f03ffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[10]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:227: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f03ffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[11]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:228: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[12]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:229: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[13]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:230: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[14]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:231: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[15]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:232: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[16]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:233: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[17]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:234: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[18]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:235: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[19]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:236: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[20]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:237: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[21]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:238: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[22]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:239: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffff\' generates 82 bits.\n : ... In instance Jump\n body_stop[23]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:240: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[24]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:241: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[25]<=82\'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:242: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000003fffffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[26]<=82\'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:243: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c000000003fffffffff0\' generates 82 bits.\n : ... In instance Jump\n body_stop[27]<=82\'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:244: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000003ffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[28]<=82\'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:245: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c00000003ffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[29]<=82\'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:246: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0000000fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[30]<=82\'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:247: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3c0000000fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[31]<=82\'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:248: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f0000003fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[32]<=82\'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:249: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3f0000003fffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[33]<=82\'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:250: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000ffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[34]<=82\'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:251: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fc00000ffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[35]<=82\'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:252: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ff0000fffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[36]<=82\'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:253: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ff0000fffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[37]<=82\'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:254: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc003fffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[38]<=82\'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:255: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffc003fffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[39]<=82\'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:256: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fff03ffffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[40]<=82\'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:257: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fff03ffffffffffc0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[41]<=82\'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:258: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[42]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:259: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[43]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:260: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[44]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:261: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc3c0000\' generates 82 bits.\n : ... In instance Jump\n body_stop[45]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:262: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[46]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:263: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[47]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:264: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[48]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:265: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[49]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:266: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[50]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:267: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[51]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:268: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[52]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:269: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[53]<=82\'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:270: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[54]<=82\'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:271: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[55]<=82\'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:272: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[56]<=82\'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:273: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3ffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[57]<=82\'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:274: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[58]<=82\'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:275: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hffffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[59]<=82\'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:276: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[60]<=82\'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:277: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffffc000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[61]<=82\'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:278: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffff0000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[62]<=82\'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:279: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffffff0000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[63]<=82\'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:280: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffc0000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[64]<=82\'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:281: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffffc0000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[65]<=82\'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:282: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffff00000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[66]<=82\'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:283: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffffff00000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[67]<=82\'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:284: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffc00000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[68]<=82\'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:285: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffffc00000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[69]<=82\'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:286: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffff000000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[70]<=82\'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:287: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'hfffffff000000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[71]<=82\'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:288: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffc000000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[72]<=82\'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/77915656/Jump.v:289: Operator ASSIGNDLY expects 83 bits on the Assign RHS, but Assign RHS\'s CONST \'82\'h3fffffc000000000\' generates 82 bits.\n : ... In instance Jump\n body_stop[73]<=82\'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;\n ^~\n%Error: Exiting due to 227 warning(s)\n' | 295,933 | module | module Jump (
input wire fresh,
input wire [31:0] clkdiv,
input wire button_jump,
input wire RESET,
input wire START,
input wire [8:0] row_addr,
input wire [9:0] col_addr,
output reg px,
input wire game_status
);
reg [11:0] jump_time;
wire [11:0] height;
reg [0:82] body_run [0:73];
reg [0:82] body_stop [0:73];
reg [0:82] feet_stop [0:13];
reg [0:82] feet_run_a [0:13];
reg [0:82] feet_run_b [0:13];
reg jumping;
reg [3:0] counter;
assign height = (jump_time*12'd40 - jump_time*jump_time) / 2'd2;
always @(negedge fresh) begin
counter<=counter+1;
if (game_status) begin
if (button_jump && jumping==1'b0) begin
jumping<=1'b1;
end
if (jumping) begin
if (jump_time>=12'd40) begin
jump_time<=12'b0;
jumping<=1'b0;
end else begin
jump_time<=jump_time+1'b1;
end
end
end else begin
if (RESET || START) begin
jump_time<=12'b0;
jumping<=1'b0;
counter<=4'b0;
end
end
end
always @(posedge clkdiv[0]) begin
if (row_addr >= 10'd402 - height - 10'd88 && row_addr < 10'd402 - height -10'd14 && col_addr>=10'd80 && col_addr<10'd162) begin
if (game_status) begin
px <= body_run[row_addr+height-10'd314][col_addr-12'd80];
end else begin
px <= body_stop[row_addr+height-10'd314][col_addr-12'd80];
end
end else begin
px <= 1'b0;
end
if (row_addr >= 10'd402 - height - 10'd14 && row_addr < 10'd402 - height && col_addr>=10'd80 && col_addr<10'd162) begin
if (game_status && height==0) begin
if (counter[3]) begin
px<=feet_run_a[row_addr+height-10'd388][col_addr-12'd80];
end else begin
px<=feet_run_b[row_addr+height-10'd388][col_addr-12'd80];
end
end else begin
px<=feet_stop[row_addr+height-10'd388][col_addr-12'd80];
end
end
end
always @(posedge RESET) begin
body_run[0]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[1]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[2]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[3]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[4]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[5]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[6]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[7]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[8]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;
body_run[9]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;
body_run[10]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;
body_run[11]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[12]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[13]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[14]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[15]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[16]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[17]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[18]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[19]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[20]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[21]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[22]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[23]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;
body_run[24]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;
body_run[25]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;
body_run[26]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_run[27]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_run[28]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_run[29]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_run[30]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[31]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[32]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[33]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[34]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[35]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[36]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[37]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[38]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[39]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[40]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[41]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[42]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[43]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[44]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[45]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[46]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[47]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[48]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[49]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[50]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[51]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[52]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[53]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[54]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[55]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[56]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[57]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[58]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[59]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[60]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[61]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[62]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_run[63]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_run[64]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_run[65]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_run[66]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_run[67]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_run[68]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_run[69]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_run[70]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_run[71]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_run[72]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
body_run[73]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[0]<=82'b0000000000_0000000000_1111111111_1100001111_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[1]<=82'b0000000000_0000000000_1111111111_1100001111_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[2]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[3]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[4]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[5]<=82'b0000000000_0000000000_1111110000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[6]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[7]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[8]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[9]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[10]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_stop[11]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_stop[12]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_stop[13]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[0]<=82'b0000000000_0000000000_1111111100_0000001111_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[1]<=82'b0000000000_0000000000_1111111100_0000001111_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[2]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[3]<=82'b0000000000_0000000000_0011111111_1111000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[4]<=82'b0000000000_0000000000_0011111111_1111000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[5]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[6]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[7]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[8]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[9]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[10]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[11]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[12]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[13]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_b[0]<=82'b0000000000_0000000000_1111111111_1100000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_b[1]<=82'b0000000000_0000000000_1111111111_1100000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_b[2]<=82'b0000000000_0000000000_1111111100_0000000000_1111111111_0000000000_0000000000_0000000000_00;
feet_run_b[3]<=82'b0000000000_0000000000_1111111100_0000000000_1111111111_0000000000_0000000000_0000000000_00;
feet_run_b[4]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[5]<=82'b0000000000_0000000000_1111110000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[6]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[7]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[8]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[9]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[10]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[11]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[12]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[13]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
body_stop[0]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[1]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[2]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[3]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[4]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[5]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[6]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[7]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[8]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0011001111_1111111111_1111111111_11;
body_stop[9]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0011001111_1111111111_1111111111_11;
body_stop[10]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[11]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[12]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[13]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[14]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[15]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[16]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[17]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[18]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[19]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[20]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[21]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[22]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[23]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[24]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111100_00;
body_stop[25]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111100_00;
body_stop[26]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_stop[27]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_stop[28]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[29]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[30]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[31]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[32]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[33]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[34]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[35]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[36]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[37]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[38]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[39]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[40]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[41]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[42]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[43]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[44]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[45]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[46]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[47]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[48]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[49]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[50]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[51]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[52]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[53]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[54]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[55]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[56]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[57]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[58]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[59]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[60]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[61]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[62]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_stop[63]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_stop[64]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_stop[65]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_stop[66]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_stop[67]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_stop[68]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_stop[69]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_stop[70]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_stop[71]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_stop[72]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
body_stop[73]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
end
endmodule | module Jump (
input wire fresh,
input wire [31:0] clkdiv,
input wire button_jump,
input wire RESET,
input wire START,
input wire [8:0] row_addr,
input wire [9:0] col_addr,
output reg px,
input wire game_status
); |
reg [11:0] jump_time;
wire [11:0] height;
reg [0:82] body_run [0:73];
reg [0:82] body_stop [0:73];
reg [0:82] feet_stop [0:13];
reg [0:82] feet_run_a [0:13];
reg [0:82] feet_run_b [0:13];
reg jumping;
reg [3:0] counter;
assign height = (jump_time*12'd40 - jump_time*jump_time) / 2'd2;
always @(negedge fresh) begin
counter<=counter+1;
if (game_status) begin
if (button_jump && jumping==1'b0) begin
jumping<=1'b1;
end
if (jumping) begin
if (jump_time>=12'd40) begin
jump_time<=12'b0;
jumping<=1'b0;
end else begin
jump_time<=jump_time+1'b1;
end
end
end else begin
if (RESET || START) begin
jump_time<=12'b0;
jumping<=1'b0;
counter<=4'b0;
end
end
end
always @(posedge clkdiv[0]) begin
if (row_addr >= 10'd402 - height - 10'd88 && row_addr < 10'd402 - height -10'd14 && col_addr>=10'd80 && col_addr<10'd162) begin
if (game_status) begin
px <= body_run[row_addr+height-10'd314][col_addr-12'd80];
end else begin
px <= body_stop[row_addr+height-10'd314][col_addr-12'd80];
end
end else begin
px <= 1'b0;
end
if (row_addr >= 10'd402 - height - 10'd14 && row_addr < 10'd402 - height && col_addr>=10'd80 && col_addr<10'd162) begin
if (game_status && height==0) begin
if (counter[3]) begin
px<=feet_run_a[row_addr+height-10'd388][col_addr-12'd80];
end else begin
px<=feet_run_b[row_addr+height-10'd388][col_addr-12'd80];
end
end else begin
px<=feet_stop[row_addr+height-10'd388][col_addr-12'd80];
end
end
end
always @(posedge RESET) begin
body_run[0]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[1]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[2]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[3]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_run[4]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[5]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[6]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[7]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[8]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;
body_run[9]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;
body_run[10]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1100011111_1111111111_1111111111_11;
body_run[11]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[12]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[13]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[14]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[15]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[16]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[17]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[18]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[19]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[20]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[21]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[22]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_run[23]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;
body_run[24]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;
body_run[25]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1110000000_0000000000_00;
body_run[26]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_run[27]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_run[28]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_run[29]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_run[30]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[31]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[32]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[33]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[34]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[35]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[36]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[37]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[38]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[39]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[40]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[41]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_run[42]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[43]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[44]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[45]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_run[46]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[47]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[48]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[49]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[50]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[51]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[52]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[53]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[54]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[55]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[56]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[57]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[58]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[59]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[60]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[61]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_run[62]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_run[63]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_run[64]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_run[65]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_run[66]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_run[67]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_run[68]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_run[69]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_run[70]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_run[71]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_run[72]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
body_run[73]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[0]<=82'b0000000000_0000000000_1111111111_1100001111_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[1]<=82'b0000000000_0000000000_1111111111_1100001111_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[2]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[3]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[4]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[5]<=82'b0000000000_0000000000_1111110000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[6]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[7]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[8]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[9]<=82'b0000000000_0000000000_1111000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_stop[10]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_stop[11]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_stop[12]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_stop[13]<=82'b0000000000_0000000000_1111111100_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[0]<=82'b0000000000_0000000000_1111111100_0000001111_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[1]<=82'b0000000000_0000000000_1111111100_0000001111_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[2]<=82'b0000000000_0000000000_1111111100_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[3]<=82'b0000000000_0000000000_0011111111_1111000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[4]<=82'b0000000000_0000000000_0011111111_1111000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[5]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[6]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[7]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[8]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[9]<=82'b0000000000_0000000000_0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_a[10]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[11]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[12]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_a[13]<=82'b0000000000_0000000000_0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_00;
feet_run_b[0]<=82'b0000000000_0000000000_1111111111_1100000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_b[1]<=82'b0000000000_0000000000_1111111111_1100000000_1111000000_0000000000_0000000000_0000000000_00;
feet_run_b[2]<=82'b0000000000_0000000000_1111111100_0000000000_1111111111_0000000000_0000000000_0000000000_00;
feet_run_b[3]<=82'b0000000000_0000000000_1111111100_0000000000_1111111111_0000000000_0000000000_0000000000_00;
feet_run_b[4]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[5]<=82'b0000000000_0000000000_1111110000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[6]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[7]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[8]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[9]<=82'b0000000000_0000000000_1111000000_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[10]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[11]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[12]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
feet_run_b[13]<=82'b0000000000_0000000000_1111111100_0000000000_0000000000_0000000000_0000000000_0000000000_00;
body_stop[0]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[1]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[2]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[3]<=82'b0000000000_0000000000_0000000000_0000000000_0000000011_1111111111_1111111111_1111111100_00;
body_stop[4]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[5]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[6]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[7]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[8]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0011001111_1111111111_1111111111_11;
body_stop[9]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0011001111_1111111111_1111111111_11;
body_stop[10]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[11]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_0000001111_1111111111_1111111111_11;
body_stop[12]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[13]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[14]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[15]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[16]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[17]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[18]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[19]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[20]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[21]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[22]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[23]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111111_11;
body_stop[24]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111100_00;
body_stop[25]<=82'b0000000000_0000000000_0000000000_0000000000_0000111111_1111111111_1111111111_1111111100_00;
body_stop[26]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_stop[27]<=82'b1111000000_0000000000_0000000000_0000000000_1111111111_1111111111_1111111111_1111111100_00;
body_stop[28]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[29]<=82'b1111000000_0000000000_0000000000_0000001111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[30]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[31]<=82'b1111000000_0000000000_0000000000_0000111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[32]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[33]<=82'b1111110000_0000000000_0000000000_0011111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[34]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[35]<=82'b1111111100_0000000000_0000000000_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[36]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[37]<=82'b1111111111_0000000000_0000001111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[38]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[39]<=82'b1111111111_1100000000_0000111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[40]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[41]<=82'b1111111111_1111000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_00;
body_stop[42]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[43]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[44]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[45]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_1111000000_0000000000_00;
body_stop[46]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[47]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[48]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[49]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[50]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[51]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[52]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[53]<=82'b1111111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[54]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[55]<=82'b0011111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[56]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[57]<=82'b0000111111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[58]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[59]<=82'b0000001111_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[60]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[61]<=82'b0000000011_1111111111_1111111111_1111111111_1111111111_1111110000_0000000000_0000000000_00;
body_stop[62]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_stop[63]<=82'b0000000000_1111111111_1111111111_1111111111_1111111111_1111000000_0000000000_0000000000_00;
body_stop[64]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_stop[65]<=82'b0000000000_0011111111_1111111111_1111111111_1111111111_1100000000_0000000000_0000000000_00;
body_stop[66]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_stop[67]<=82'b0000000000_0000111111_1111111111_1111111111_1111111111_0000000000_0000000000_0000000000_00;
body_stop[68]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_stop[69]<=82'b0000000000_0000001111_1111111111_1111111111_1111111100_0000000000_0000000000_0000000000_00;
body_stop[70]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_stop[71]<=82'b0000000000_0000000011_1111111111_1111111111_1111110000_0000000000_0000000000_0000000000_00;
body_stop[72]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
body_stop[73]<=82'b0000000000_0000000000_1111111111_1111111111_1111000000_0000000000_0000000000_0000000000_00;
end
endmodule | 3 |
137,345 | data/full_repos/permissive/77915656/Random.v | 77,915,656 | Random.v | v | 25 | 45 | [] | [] | [] | [(2, 24)] | null | data/verilator_xmls/6b75626e-4eee-438a-a9e6-0922d20f55f2.xml | null | 295,935 | module | module Random(
input clk,
input RESET,
output reg [4:0] data
);
reg [4:0] data_next;
always @(posedge clk) begin
data_next[4] = data[4]^data[1];
data_next[3] = data[3]^data[0];
data_next[2] = data[2]^data_next[4];
data_next[1] = data[1]^data_next[3];
data_next[0] = data[0]^data_next[2];
end
always @(posedge clk)
if(RESET)
data <= 5'h1f;
else
data <= data_next;
endmodule | module Random(
input clk,
input RESET,
output reg [4:0] data
); |
reg [4:0] data_next;
always @(posedge clk) begin
data_next[4] = data[4]^data[1];
data_next[3] = data[3]^data[0];
data_next[2] = data[2]^data_next[4];
data_next[1] = data[1]^data_next[3];
data_next[0] = data[0]^data_next[2];
end
always @(posedge clk)
if(RESET)
data <= 5'h1f;
else
data <= data_next;
endmodule | 3 |
137,346 | data/full_repos/permissive/77915656/random_sim.v | 77,915,656 | random_sim.v | v | 64 | 81 | [] | [] | [] | [(25, 62)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/77915656/random_sim.v:47: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77915656/random_sim.v:50: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77915656/random_sim.v:58: Unsupported: Ignoring delay on this delayed statement.\n clk = 0; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77915656/random_sim.v:59: Unsupported: Ignoring delay on this delayed statement.\n clk = 1; #10;\n ^\n%Error: data/full_repos/permissive/77915656/random_sim.v:35: Cannot find file containing module: \'Random\'\n Random uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/Random\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/Random.v\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/Random.sv\n Random\n Random.v\n Random.sv\n obj_dir/Random\n obj_dir/Random.v\n obj_dir/Random.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,936 | module | module random_sim;
reg clk;
reg RESET;
wire [4:0] data;
Random uut (
.clk(clk),
.RESET(RESET),
.data(data)
);
initial begin
clk = 0;
RESET = 0;
#30;
RESET=1;
#30;
RESET=0;
end
always begin
clk = 0; #10;
clk = 1; #10;
end
endmodule | module random_sim; |
reg clk;
reg RESET;
wire [4:0] data;
Random uut (
.clk(clk),
.RESET(RESET),
.data(data)
);
initial begin
clk = 0;
RESET = 0;
#30;
RESET=1;
#30;
RESET=0;
end
always begin
clk = 0; #10;
clk = 1; #10;
end
endmodule | 3 |
137,348 | data/full_repos/permissive/77915656/Top.v | 77,915,656 | Top.v | v | 155 | 117 | [] | [] | [] | [(3, 154)] | null | null | 1: b"%Error: data/full_repos/permissive/77915656/Top.v:30: Cannot find file containing module: 'AntiJitter'\n AntiJitter #(4) a0[15:0](.clk(clkdiv[0]), .I(SW), .O(SW_OK));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/AntiJitter\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/AntiJitter.v\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/AntiJitter.sv\n AntiJitter\n AntiJitter.v\n AntiJitter.sv\n obj_dir/AntiJitter\n obj_dir/AntiJitter.v\n obj_dir/AntiJitter.sv\n%Error: data/full_repos/permissive/77915656/Top.v:42: Cannot find file containing module: 'Jump'\n Jump jump (\n ^~~~\n%Error: data/full_repos/permissive/77915656/Top.v:58: Cannot find file containing module: 'Ground'\n Ground ground (\n ^~~~~~\n%Error: data/full_repos/permissive/77915656/Top.v:71: Cannot find file containing module: 'Cactus'\n Cactus cactus (\n ^~~~~~\n%Error: data/full_repos/permissive/77915656/Top.v:84: Cannot find file containing module: 'Score'\n Score score(\n ^~~~~\n%Error: data/full_repos/permissive/77915656/Top.v:96: Cannot find file containing module: 'Vga'\n Vga vga (\n ^~~\n%Error: Exiting due to 6 error(s)\n" | 295,938 | module | module Top(
input wire CLK,
input wire START_N,
input wire JUMP_N,
input [15:0]SW,
output hs,
output vs,
output [3:0] r,
output [3:0] g,
output [3:0] b
);
reg game_status;
reg trigger_start;
wire [8:0] row_addr;
wire [9:0] col_addr;
reg [31:0]clkdiv;
always@(posedge CLK) begin
clkdiv <= clkdiv + 1'b1;
end
wire [15:0] SW_OK;
AntiJitter #(4) a0[15:0](.clk(clkdiv[0]), .I(SW), .O(SW_OK));
wire RESET;
assign RESET = SW_OK[2];
wire START;
assign START = ~START_N;
wire JUMP;
assign JUMP = ~JUMP_N;
wire px_dinosaur;
Jump jump (
.fresh(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.clkdiv(clkdiv),
.button_jump(JUMP),
.RESET(RESET),
.START(START),
.game_status(game_status),
.px(px_dinosaur)
);
wire px_ground;
wire [3:0] speed;
Ground ground (
.clkdiv(clkdiv),
.fresh(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.game_status(game_status),
.speed(speed),
.px(px_ground)
);
wire px_cactus;
Cactus cactus (
.clkdiv(clkdiv),
.RESET(RESET),
.START(START),
.fresh(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.game_status(game_status),
.speed(speed),
.px(px_cactus)
);
wire px_score;
Score score(
.clkdiv(clkdiv),
.RESET(RESET),
.row_addr(row_addr),
.col_addr(col_addr),
.START(START),
.game_status(game_status),
.px(px_score)
);
wire px;
Vga vga (
.vga_clk(clkdiv[1]),
.clrn(SW_OK[0]),
.r(r),
.g(g),
.b(b),
.hs(hs),
.vs(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.px_dinosaur(px_dinosaur),
.px_ground(px_ground),
.px_cactus(px_cactus),
.px_score(px_score),
.px(px)
);
wire trigger_stop;
assign trigger_stop = px_dinosaur && px_cactus;
always @(posedge CLK) begin
if (START) begin
if(game_status==1'b0)begin
trigger_start<=1'b1;
end
end
if (trigger_stop) begin
game_status<=1'b0;
end
if (vs==1'b0) begin
if (trigger_start==1'b1) begin
if (game_status==1'b0) begin
game_status<=1'b1;
end else begin
trigger_start<=1'b0;
end
end
end
if (RESET) begin
game_status<=1'b0;
trigger_start<=1'b0;
end
end
endmodule | module Top(
input wire CLK,
input wire START_N,
input wire JUMP_N,
input [15:0]SW,
output hs,
output vs,
output [3:0] r,
output [3:0] g,
output [3:0] b
); |
reg game_status;
reg trigger_start;
wire [8:0] row_addr;
wire [9:0] col_addr;
reg [31:0]clkdiv;
always@(posedge CLK) begin
clkdiv <= clkdiv + 1'b1;
end
wire [15:0] SW_OK;
AntiJitter #(4) a0[15:0](.clk(clkdiv[0]), .I(SW), .O(SW_OK));
wire RESET;
assign RESET = SW_OK[2];
wire START;
assign START = ~START_N;
wire JUMP;
assign JUMP = ~JUMP_N;
wire px_dinosaur;
Jump jump (
.fresh(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.clkdiv(clkdiv),
.button_jump(JUMP),
.RESET(RESET),
.START(START),
.game_status(game_status),
.px(px_dinosaur)
);
wire px_ground;
wire [3:0] speed;
Ground ground (
.clkdiv(clkdiv),
.fresh(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.game_status(game_status),
.speed(speed),
.px(px_ground)
);
wire px_cactus;
Cactus cactus (
.clkdiv(clkdiv),
.RESET(RESET),
.START(START),
.fresh(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.game_status(game_status),
.speed(speed),
.px(px_cactus)
);
wire px_score;
Score score(
.clkdiv(clkdiv),
.RESET(RESET),
.row_addr(row_addr),
.col_addr(col_addr),
.START(START),
.game_status(game_status),
.px(px_score)
);
wire px;
Vga vga (
.vga_clk(clkdiv[1]),
.clrn(SW_OK[0]),
.r(r),
.g(g),
.b(b),
.hs(hs),
.vs(vs),
.row_addr(row_addr),
.col_addr(col_addr),
.px_dinosaur(px_dinosaur),
.px_ground(px_ground),
.px_cactus(px_cactus),
.px_score(px_score),
.px(px)
);
wire trigger_stop;
assign trigger_stop = px_dinosaur && px_cactus;
always @(posedge CLK) begin
if (START) begin
if(game_status==1'b0)begin
trigger_start<=1'b1;
end
end
if (trigger_stop) begin
game_status<=1'b0;
end
if (vs==1'b0) begin
if (trigger_start==1'b1) begin
if (game_status==1'b0) begin
game_status<=1'b1;
end else begin
trigger_start<=1'b0;
end
end
end
if (RESET) begin
game_status<=1'b0;
trigger_start<=1'b0;
end
end
endmodule | 3 |
137,349 | data/full_repos/permissive/77915656/top_sim.v | 77,915,656 | top_sim.v | v | 88 | 81 | [] | [] | [] | [(25, 86)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/77915656/top_sim.v:67: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77915656/top_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77915656/top_sim.v:72: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77915656/top_sim.v:82: Unsupported: Ignoring delay on this delayed statement.\n CLK = 0; #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77915656/top_sim.v:83: Unsupported: Ignoring delay on this delayed statement.\n CLK = 1; #10;\n ^\n%Error: data/full_repos/permissive/77915656/top_sim.v:44: Cannot find file containing module: \'Top\'\n Top uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/Top\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/Top.v\n data/full_repos/permissive/77915656,data/full_repos/permissive/77915656/Top.sv\n Top\n Top.v\n Top.sv\n obj_dir/Top\n obj_dir/Top.v\n obj_dir/Top.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,939 | module | module top_sim;
reg CLK;
reg START;
reg RESET;
reg [15:0] SW;
wire hs;
wire vs;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;
wire px;
wire px_dinosaur;
wire px_ground;
Top uut (
.CLK(CLK),
.START(START),
.RESET(RESET),
.SW(SW),
.hs(hs),
.vs(vs),
.r(r),
.g(g),
.px(px),
.px_dinosaur(px_dinosaur),
.px_ground(px_ground),
.b(b)
);
initial begin
CLK = 0;
SW = 0;
RESET=0;
START=0;
#30;
SW[0]=1;
#50;
SW[2]=1;
#50;
SW[2]=0;
end
always begin
CLK = 0; #10;
CLK = 1; #10;
end
endmodule | module top_sim; |
reg CLK;
reg START;
reg RESET;
reg [15:0] SW;
wire hs;
wire vs;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;
wire px;
wire px_dinosaur;
wire px_ground;
Top uut (
.CLK(CLK),
.START(START),
.RESET(RESET),
.SW(SW),
.hs(hs),
.vs(vs),
.r(r),
.g(g),
.px(px),
.px_dinosaur(px_dinosaur),
.px_ground(px_ground),
.b(b)
);
initial begin
CLK = 0;
SW = 0;
RESET=0;
START=0;
#30;
SW[0]=1;
#50;
SW[2]=1;
#50;
SW[2]=0;
end
always begin
CLK = 0; #10;
CLK = 1; #10;
end
endmodule | 3 |
137,351 | data/full_repos/permissive/77923266/verilog/Absorb.v | 77,923,266 | Absorb.v | v | 109 | 85 | [] | [] | [] | [(23, 109)] | null | null | 1: b"%Error: data/full_repos/permissive/77923266/verilog/Absorb.v:47: Cannot find file containing module: 'Permute'\n Permute permute_instance (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/Permute\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/Permute.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/Permute.sv\n Permute\n Permute.v\n Permute.sv\n obj_dir/Permute\n obj_dir/Permute.v\n obj_dir/Permute.sv\n%Error: Exiting due to 1 error(s)\n" | 295,942 | module | module Absorb(state_in, state_out, clk, rst, en, rdy);
input [263:0] state_in;
input rst;
input clk;
input en;
output reg[263:0] state_out;
output reg rdy;
reg wr_en;
reg [15:0] IV, INV_IV;
reg [31:0] iteration;
reg [263:0] temp_state;
reg permute_enable;
reg [15:0] permute_IV_in;
reg [263:0] permute_state_in;
reg permute_rst;
wire [263:0] permute_state_out;
wire [15:0] permute_IV_out;
wire permute_out_rdy;
Permute permute_instance (
.state_in(permute_state_in),
.IV_in(permute_IV_in),
.state_out(permute_state_out),
.IV_out(permute_IV_out),
.clk(clk),
.rst(permute_rst),
.en(permute_enable),
.rdy(permute_out_rdy)
);
always @ (posedge clk or posedge rst) begin
if (rst) begin
permute_rst = rst;
state_out = 0;
temp_state = 0;
permute_state_in = 0;
permute_enable = 0;
IV = 16'hc6;
INV_IV = 16'h0;
wr_en = 1;
rdy = 0;
iteration = 0;
end else if (en) begin
permute_rst = 0;
if (temp_state == 0) begin
temp_state = state_in;
end
if (wr_en) begin
wr_en = 0;
permute_IV_in = IV;
permute_state_in = temp_state;
permute_enable = 1;
end
if (permute_out_rdy) begin
temp_state = permute_state_out;
IV = permute_IV_out;
iteration = iteration + 1;
if (iteration === 135) begin
state_out = permute_state_out;
rdy = 1;
end else begin
wr_en = 1;
permute_rst = 1;
rdy = 0;
end
end else begin
rdy = 0;
end
end
end
endmodule | module Absorb(state_in, state_out, clk, rst, en, rdy); |
input [263:0] state_in;
input rst;
input clk;
input en;
output reg[263:0] state_out;
output reg rdy;
reg wr_en;
reg [15:0] IV, INV_IV;
reg [31:0] iteration;
reg [263:0] temp_state;
reg permute_enable;
reg [15:0] permute_IV_in;
reg [263:0] permute_state_in;
reg permute_rst;
wire [263:0] permute_state_out;
wire [15:0] permute_IV_out;
wire permute_out_rdy;
Permute permute_instance (
.state_in(permute_state_in),
.IV_in(permute_IV_in),
.state_out(permute_state_out),
.IV_out(permute_IV_out),
.clk(clk),
.rst(permute_rst),
.en(permute_enable),
.rdy(permute_out_rdy)
);
always @ (posedge clk or posedge rst) begin
if (rst) begin
permute_rst = rst;
state_out = 0;
temp_state = 0;
permute_state_in = 0;
permute_enable = 0;
IV = 16'hc6;
INV_IV = 16'h0;
wr_en = 1;
rdy = 0;
iteration = 0;
end else if (en) begin
permute_rst = 0;
if (temp_state == 0) begin
temp_state = state_in;
end
if (wr_en) begin
wr_en = 0;
permute_IV_in = IV;
permute_state_in = temp_state;
permute_enable = 1;
end
if (permute_out_rdy) begin
temp_state = permute_state_out;
IV = permute_IV_out;
iteration = iteration + 1;
if (iteration === 135) begin
state_out = permute_state_out;
rdy = 1;
end else begin
wr_en = 1;
permute_rst = 1;
rdy = 0;
end
end else begin
rdy = 0;
end
end
end
endmodule | 0 |
137,352 | data/full_repos/permissive/77923266/verilog/lCounter.v | 77,923,266 | lCounter.v | v | 17 | 46 | [] | [] | [] | [(4, 14)] | null | data/verilator_xmls/af6739e1-1f84-409c-8b0c-35df2a7a2dd2.xml | null | 295,944 | module | module lCounter (input [15:0] lfsr,
output [15:0] out);
assign out = ((lfsr << 1) |
(((16'h80 & lfsr) >> 7) ^
((16'h08 & lfsr) >> 3) ^
((16'h04 & lfsr) >> 2) ^
((16'h02 & lfsr) >> 1) )
)
& 16'hff;
endmodule | module lCounter (input [15:0] lfsr,
output [15:0] out); |
assign out = ((lfsr << 1) |
(((16'h80 & lfsr) >> 7) ^
((16'h08 & lfsr) >> 3) ^
((16'h04 & lfsr) >> 2) ^
((16'h02 & lfsr) >> 1) )
)
& 16'hff;
endmodule | 0 |
137,353 | data/full_repos/permissive/77923266/verilog/Permute.v | 77,923,266 | Permute.v | v | 99 | 112 | [] | [] | [] | [(287, 620)] | null | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/Permute.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:57: Define or directive not defined: \'`INIT_SBOX_LAYER\'\n `INIT_SBOX_LAYER;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:77: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:77: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8\'hff;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:77: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:77: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:77: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:78: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:78: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8\'hff;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:78: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:78: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:78: Define or directive not defined: \'`nSBox\'\n tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8\'hff;\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:81: Define or directive not defined: \'`nSBox\'\n for (j=0; j<`nSBox*8; j=j+8) begin\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:81: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n for (j=0; j<`nSBox*8; j=j+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:81: syntax error, unexpected \')\', expecting \';\'\n for (j=0; j<`nSBox*8; j=j+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/Permute.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 295,945 | module | module Permute(state_in, IV_in, INV_IV_in, state_out, IV_out, INV_IV_out, clk, rst, en, rdy);
input [263:0] state_in;
input [ 15:0] IV_in;
input [ 15:0] INV_IV_in;
input rst;
input clk;
input en;
output reg[263:0] state_out;
output reg[ 15:0] IV_out;
output reg[ 15:0] INV_IV_out;
output reg rdy;
reg [ 15:0] i;
reg [ 263:0] tmp_state;
reg [2048:0] sBoxLayer;
reg wr_en;
wire [ 15:0] lCounter_out, retnuoCl_out;
lCounter lCounter_instance(.lfsr(IV_in), .out(lCounter_out));
retnuoCl retnuoCl_instance(.lfsr(IV_in), .out(retnuoCl_out));
reg pLayer_enable;
reg [ 263:0] pLayer_state_in;
wire [ 263:0] pLayer_state_out;
wire pLayer_out_rdy;
pLayer pLayer_instance (.clk(clk),
.rst(rst),
.state_in(pLayer_state_in),
.state_out(pLayer_state_out),
.out_rdy(pLayer_out_rdy),
.en(pLayer_enable)
);
initial begin
`INIT_SBOX_LAYER;
end
integer j;
always @ (posedge clk or posedge rst) begin
if (rst) begin
state_out = 0;
tmp_state = 0;
pLayer_state_in = 0;
pLayer_enable = 0;
wr_en = 1;
rdy = 0;
end else if (en) begin
IV_out = 0;
INV_IV_out = 0;
state_out = 0;
tmp_state = state_in;
tmp_state[ 7:0] = tmp_state[ 7:0] ^ (IV_in & 16'hff);
tmp_state[15:8] = tmp_state[15:8] ^ ((IV_in >> 8) & 16'hff);
INV_IV_out = retnuoCl_out;
tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8'hff;
tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8'hff;
IV_out = lCounter_out;
for (j=0; j<`nSBox*8; j=j+8) begin
tmp_state[j+:8] = sBoxLayer[(tmp_state[j+:8]*8)+:8];
end
if (wr_en) begin
wr_en = 0;
pLayer_state_in = tmp_state;
pLayer_enable = 1;
end
if (pLayer_out_rdy) begin
state_out = pLayer_state_out;
rdy = 1;
end else begin
rdy = 0;
end
end
end
endmodule | module Permute(state_in, IV_in, INV_IV_in, state_out, IV_out, INV_IV_out, clk, rst, en, rdy); |
input [263:0] state_in;
input [ 15:0] IV_in;
input [ 15:0] INV_IV_in;
input rst;
input clk;
input en;
output reg[263:0] state_out;
output reg[ 15:0] IV_out;
output reg[ 15:0] INV_IV_out;
output reg rdy;
reg [ 15:0] i;
reg [ 263:0] tmp_state;
reg [2048:0] sBoxLayer;
reg wr_en;
wire [ 15:0] lCounter_out, retnuoCl_out;
lCounter lCounter_instance(.lfsr(IV_in), .out(lCounter_out));
retnuoCl retnuoCl_instance(.lfsr(IV_in), .out(retnuoCl_out));
reg pLayer_enable;
reg [ 263:0] pLayer_state_in;
wire [ 263:0] pLayer_state_out;
wire pLayer_out_rdy;
pLayer pLayer_instance (.clk(clk),
.rst(rst),
.state_in(pLayer_state_in),
.state_out(pLayer_state_out),
.out_rdy(pLayer_out_rdy),
.en(pLayer_enable)
);
initial begin
`INIT_SBOX_LAYER;
end
integer j;
always @ (posedge clk or posedge rst) begin
if (rst) begin
state_out = 0;
tmp_state = 0;
pLayer_state_in = 0;
pLayer_enable = 0;
wr_en = 1;
rdy = 0;
end else if (en) begin
IV_out = 0;
INV_IV_out = 0;
state_out = 0;
tmp_state = state_in;
tmp_state[ 7:0] = tmp_state[ 7:0] ^ (IV_in & 16'hff);
tmp_state[15:8] = tmp_state[15:8] ^ ((IV_in >> 8) & 16'hff);
INV_IV_out = retnuoCl_out;
tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8'hff;
tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8'hff;
IV_out = lCounter_out;
for (j=0; j<`nSBox*8; j=j+8) begin
tmp_state[j+:8] = sBoxLayer[(tmp_state[j+:8]*8)+:8];
end
if (wr_en) begin
wr_en = 0;
pLayer_state_in = tmp_state;
pLayer_enable = 1;
end
if (pLayer_out_rdy) begin
state_out = pLayer_state_out;
rdy = 1;
end else begin
rdy = 0;
end
end
end
endmodule | 0 |
137,354 | data/full_repos/permissive/77923266/verilog/Pi.v | 77,923,266 | Pi.v | v | 18 | 42 | [] | [] | [] | [(268, 282)] | null | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/Pi.v:1: Cannot find include file: constants.vh\n`include "constants.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/77923266/verilog/Pi.v:10: Define or directive not defined: \'`nBits\'\n wire [8:0] out_comb = (in != `nBits-1) ?\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Pi.v:11: Define or directive not defined: \'`nBits\'\n (in*`nBits/4)%(`nBits-1) :\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Pi.v:11: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n (in*`nBits/4)%(`nBits-1) :\n ^\n%Error: data/full_repos/permissive/77923266/verilog/Pi.v:11: Define or directive not defined: \'`nBits\'\n (in*`nBits/4)%(`nBits-1) :\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/Pi.v:12: Define or directive not defined: \'`nBits\'\n `nBits-1;\n ^~~~~~\n%Error: Exiting due to 6 error(s)\n' | 295,946 | module | module Pi_mod(in, out, clk, rst);
input clk;
input rst;
input [31:0] in;
output reg [8:0] out;
wire [8:0] out_comb = (in != `nBits-1) ?
(in*`nBits/4)%(`nBits-1) :
`nBits-1;
always@(posedge clk)
out <= out_comb;
endmodule | module Pi_mod(in, out, clk, rst); |
input clk;
input rst;
input [31:0] in;
output reg [8:0] out;
wire [8:0] out_comb = (in != `nBits-1) ?
(in*`nBits/4)%(`nBits-1) :
`nBits-1;
always@(posedge clk)
out <= out_comb;
endmodule | 0 |
137,355 | data/full_repos/permissive/77923266/verilog/pLayer.v | 77,923,266 | pLayer.v | v | 66 | 98 | [] | [] | [] | null | line:297: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:1: Cannot find include file: constants.vh\n`include "constants.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:27: Define or directive not defined: \'`nSBox\'\n for (k=0; k<`nSBox; k=k+1)\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (k=0; k<`nSBox; k=k+1)\n ^\n%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:27: syntax error, unexpected \')\', expecting \';\'\n for (k=0; k<`nSBox; k=k+1)\n ^\n%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:33: Define or directive not defined: \'`nSBox\'\n for (itr_i = 0; itr_i<`nSBox; itr_i=itr_i+1) begin : Pi_i\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (itr_i = 0; itr_i<`nSBox; itr_i=itr_i+1) begin : Pi_i\n ^\n%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:46: Define or directive not defined: \'`nSBox\'\n for (k=0; k<`nSBox; k=k+1)\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/pLayer.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (k=0; k<`nSBox; k=k+1)\n ^\n%Error: Cannot continue\n' | 295,947 | module | module pLayer(state_in, state_out, clk, rst, out_rdy, en);
input clk;
input rst;
input [263:0] state_in;
input en;
output reg [263:0] state_out;
output reg out_rdy;
wire [7:0] out_comb;
reg [7:0] permute [0:32];
reg [263:0] state_comb;
reg [7:0] x, y;
reg [31:0] j, PermutedBitNo;
wire [8:0] pi_out_field [8:0][32:0];
reg [31:0] idx;
integer k;
initial begin
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end
genvar itr_i, itr_j;
generate begin
for (itr_i = 0; itr_i<`nSBox; itr_i=itr_i+1) begin : Pi_i
for (itr_j = 0; itr_j<8; itr_j=itr_j+1) begin : Pi_j
Pi_mod pi(.in ((itr_i<<3)+itr_j), .out (pi_out_field[itr_j][itr_i]), .clk (clk), .rst (rst));
end
end
end endgenerate
always @ (posedge clk or posedge rst) begin
if (rst) begin
state_out = 0;
state_comb = 0;
idx = 0;
out_rdy = 0;
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end else if(en) begin
for (j=0; j<8; j=j+1) begin
x = (state_in[(idx*8)+:8]>>j) & 8'b00000001;
PermutedBitNo = pi_out_field[j][idx];
y = PermutedBitNo>>3;
permute[y] = permute[y] ^ (x << (PermutedBitNo - 8*y));
state_comb = state_comb | permute[y] << (y*8);
end
if (idx==32) begin
state_out = state_comb;
out_rdy = 1'b1;
end else begin
out_rdy = 1'b0;
end
idx = idx + 1;
end
end
endmodule | module pLayer(state_in, state_out, clk, rst, out_rdy, en); |
input clk;
input rst;
input [263:0] state_in;
input en;
output reg [263:0] state_out;
output reg out_rdy;
wire [7:0] out_comb;
reg [7:0] permute [0:32];
reg [263:0] state_comb;
reg [7:0] x, y;
reg [31:0] j, PermutedBitNo;
wire [8:0] pi_out_field [8:0][32:0];
reg [31:0] idx;
integer k;
initial begin
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end
genvar itr_i, itr_j;
generate begin
for (itr_i = 0; itr_i<`nSBox; itr_i=itr_i+1) begin : Pi_i
for (itr_j = 0; itr_j<8; itr_j=itr_j+1) begin : Pi_j
Pi_mod pi(.in ((itr_i<<3)+itr_j), .out (pi_out_field[itr_j][itr_i]), .clk (clk), .rst (rst));
end
end
end endgenerate
always @ (posedge clk or posedge rst) begin
if (rst) begin
state_out = 0;
state_comb = 0;
idx = 0;
out_rdy = 0;
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end else if(en) begin
for (j=0; j<8; j=j+1) begin
x = (state_in[(idx*8)+:8]>>j) & 8'b00000001;
PermutedBitNo = pi_out_field[j][idx];
y = PermutedBitNo>>3;
permute[y] = permute[y] ^ (x << (PermutedBitNo - 8*y));
state_comb = state_comb | permute[y] << (y*8);
end
if (idx==32) begin
state_out = state_comb;
out_rdy = 1'b1;
end else begin
out_rdy = 1'b0;
end
idx = idx + 1;
end
end
endmodule | 0 |
137,356 | data/full_repos/permissive/77923266/verilog/retnuoCl.v | 77,923,266 | retnuoCl.v | v | 18 | 47 | [] | [] | [] | [(4, 16)] | null | data/verilator_xmls/2a4b23e5-494c-466f-bd88-37a3ee50f96d.xml | null | 295,948 | module | module retnuoCl (input [15:0] lfsr,
output [15:0] out);
assign out = ((((lfsr & 16'h01) << 7) |
((lfsr & 16'h02) << 5) |
((lfsr & 16'h04) << 3) |
((lfsr & 16'h08) << 1) |
((lfsr & 16'h10) >> 1) |
((lfsr & 16'h20) >> 3) |
((lfsr & 16'h40) >> 5) |
((lfsr & 16'h80) >> 7) )
<< 8);
endmodule | module retnuoCl (input [15:0] lfsr,
output [15:0] out); |
assign out = ((((lfsr & 16'h01) << 7) |
((lfsr & 16'h02) << 5) |
((lfsr & 16'h04) << 3) |
((lfsr & 16'h08) << 1) |
((lfsr & 16'h10) >> 1) |
((lfsr & 16'h20) >> 3) |
((lfsr & 16'h40) >> 5) |
((lfsr & 16'h80) >> 7) )
<< 8);
endmodule | 0 |
137,357 | data/full_repos/permissive/77923266/verilog/SpongentHash.v | 77,923,266 | SpongentHash.v | v | 111 | 115 | [] | [] | [] | [(290, 375)] | null | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:79: Define or directive not defined: \'`R_SizeInBytes\'\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:79: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:79: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:87: Define or directive not defined: \'`R_SizeInBytes\'\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:87: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:87: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:99: syntax error, unexpected \'=\', expecting IDENTIFIER\n state = absorb_state_out;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:103: syntax error, unexpected \'=\', expecting IDENTIFIER\n count = count - 1;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/SpongentHash.v:107: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 295,949 | module | module SpongentHash(clk, rst, en, rdy, hash_out);
input rst;
input clk;
input en;
output reg rdy;
output reg [87:0] hash_out;
reg [263:0] state;
reg [512:0] data;
reg [ 87:0] hash;
reg [ 31:0] i, count;
reg wr_en;
reg [263:0] absorb_state_in;
reg absorb_enable;
reg absorb_rst;
wire absorb_out_rdy;
wire [263:0] absorb_state_out;
Absorb absorb_instance (
.state_in(absorb_state_in),
.state_out(absorb_state_out),
.clk(clk),
.rst(absorb_rst),
.en(absorb_enable),
.rdy(absorb_out_rdy)
);
always @ (posedge clk or posedge rst) begin
if (rst) begin
rdy = 0;
state = 0;
data = {"Spongent is a lightweight Hashfunction", 8'h80, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00};
count = 4;
wr_en = 1;
absorb_rst = rst;
absorb_state_in = 0;
absorb_enable = 0;
hash = 0;
end else if (en) begin
absorb_rst = 0;
if (wr_en) begin
wr_en = 0;
if (count > 0) begin
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state[i+:8] = state[i+:8] ^ data[count * 88 - (i+8) +:8];
end
absorb_state_in = state;
absorb_enable = 1;
end else begin
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
hash[i+:8] = hash[i+:8] ^ state[i +:8];
end
hash_out = hash;
rdy = 1;
end
end
if (absorb_out_rdy) begin
state = absorb_state_out;
absorb_rst = 1;
if (count > 0) begin
count = count - 1;
wr_en = 1;
end
end
end
end
endmodule | module SpongentHash(clk, rst, en, rdy, hash_out); |
input rst;
input clk;
input en;
output reg rdy;
output reg [87:0] hash_out;
reg [263:0] state;
reg [512:0] data;
reg [ 87:0] hash;
reg [ 31:0] i, count;
reg wr_en;
reg [263:0] absorb_state_in;
reg absorb_enable;
reg absorb_rst;
wire absorb_out_rdy;
wire [263:0] absorb_state_out;
Absorb absorb_instance (
.state_in(absorb_state_in),
.state_out(absorb_state_out),
.clk(clk),
.rst(absorb_rst),
.en(absorb_enable),
.rdy(absorb_out_rdy)
);
always @ (posedge clk or posedge rst) begin
if (rst) begin
rdy = 0;
state = 0;
data = {"Spongent is a lightweight Hashfunction", 8'h80, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00};
count = 4;
wr_en = 1;
absorb_rst = rst;
absorb_state_in = 0;
absorb_enable = 0;
hash = 0;
end else if (en) begin
absorb_rst = 0;
if (wr_en) begin
wr_en = 0;
if (count > 0) begin
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state[i+:8] = state[i+:8] ^ data[count * 88 - (i+8) +:8];
end
absorb_state_in = state;
absorb_enable = 1;
end else begin
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
hash[i+:8] = hash[i+:8] ^ state[i +:8];
end
hash_out = hash;
rdy = 1;
end
end
if (absorb_out_rdy) begin
state = absorb_state_out;
absorb_rst = 1;
if (count > 0) begin
count = count - 1;
wr_en = 1;
end
end
end
end
endmodule | 0 |
137,358 | data/full_repos/permissive/77923266/verilog/tb_Absorb.v | 77,923,266 | tb_Absorb.v | v | 85 | 79 | [] | [] | [] | null | line:325: before: "(" | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:49: Define or directive not defined: \'`rate\'\n while (databitlen >= `rate) begin\n ^~~~~\n%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n while (databitlen >= `rate) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:52: Define or directive not defined: \'`R_SizeInBytes\'\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:52: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:52: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:57: syntax error, unexpected $display\n $display("state in: %h", state_in);\n ^~~~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/tb_Absorb.v:68: Define or directive not defined: \'`rate\'\n databitlen = databitlen - `rate;\n ^~~~~\n%Error: Cannot continue\n' | 295,950 | module | module tb_Absorb;
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
reg [175:0] data;
wire [263:0] state_out;
wire rdy;
Absorb uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
integer i;
integer databitlen;
integer counter;
initial begin
databitlen = 176;
data = "Hello WorldHello World";
counter = 0;
state_in = 0;
clk = 0;
rst = 1;
en = 0;
#100;
rst = 0;
$display("[INITIALIZING]");
state_in = 0;
en = 1;
while (databitlen >= `rate) begin
$display("counter %d", counter);
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state_in[i+:8] = state_in[i+:8] ^ data[databitlen - (i+8) +:8];
$display("data: %d %h", databitlen - (i+8), data[databitlen - (i+8) +:8]);
end
$display("state in: %h", state_in);
$display("data: %h", data);
repeat(70*135) begin
#5;
end
if (rdy) begin
state_in = state_out;
$display("state_out: %h", state_out);
counter = counter + 1;
databitlen = databitlen - `rate;
end
end
end
always begin
#5; clk = !clk;
end
always @ (rdy) begin
if (rdy == 1) begin
state_in = state_out;
$display("state_out: %h", state_out);
end
end
endmodule | module tb_Absorb; |
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
reg [175:0] data;
wire [263:0] state_out;
wire rdy;
Absorb uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
integer i;
integer databitlen;
integer counter;
initial begin
databitlen = 176;
data = "Hello WorldHello World";
counter = 0;
state_in = 0;
clk = 0;
rst = 1;
en = 0;
#100;
rst = 0;
$display("[INITIALIZING]");
state_in = 0;
en = 1;
while (databitlen >= `rate) begin
$display("counter %d", counter);
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state_in[i+:8] = state_in[i+:8] ^ data[databitlen - (i+8) +:8];
$display("data: %d %h", databitlen - (i+8), data[databitlen - (i+8) +:8]);
end
$display("state in: %h", state_in);
$display("data: %h", data);
repeat(70*135) begin
#5;
end
if (rdy) begin
state_in = state_out;
$display("state_out: %h", state_out);
counter = counter + 1;
databitlen = databitlen - `rate;
end
end
end
always begin
#5; clk = !clk;
end
always @ (rdy) begin
if (rdy == 1) begin
state_in = state_out;
$display("state_out: %h", state_out);
end
end
endmodule | 0 |
137,359 | data/full_repos/permissive/77923266/verilog/tb_lCounter.v | 77,923,266 | tb_lCounter.v | v | 57 | 81 | [] | [] | [] | [(25, 55)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_lCounter.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_lCounter.v:49: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_lCounter.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_lCounter.v:34: Cannot find file containing module: \'lCounter\'\n lCounter uut (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/lCounter\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/lCounter.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/lCounter.sv\n lCounter\n lCounter.v\n lCounter.sv\n obj_dir/lCounter\n obj_dir/lCounter.v\n obj_dir/lCounter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,951 | module | module tb_lCounter;
reg [15:0] lfsr;
wire [15:0] out;
lCounter uut (
.lfsr(lfsr),
.out(out)
);
initial begin
lfsr = 16'b0000000000000000;
#100;
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, (hex): %h", lfsr, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule | module tb_lCounter; |
reg [15:0] lfsr;
wire [15:0] out;
lCounter uut (
.lfsr(lfsr),
.out(out)
);
initial begin
lfsr = 16'b0000000000000000;
#100;
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, (hex): %h", lfsr, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule | 0 |
137,360 | data/full_repos/permissive/77923266/verilog/tb_Permute.v | 77,923,266 | tb_Permute.v | v | 101 | 81 | [] | [] | [] | null | line:341: before: "(" | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/tb_Permute.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Permute.v:64: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/77923266/verilog/tb_Permute.v:70: Define or directive not defined: \'`nSBox\'\n for (i=0; i<`nSBox; i=i+1) begin\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/tb_Permute.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0; i<`nSBox; i=i+1) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_Permute.v:70: syntax error, unexpected \')\', expecting \';\'\n for (i=0; i<`nSBox; i=i+1) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_Permute.v:73: syntax error, unexpected \'=\', expecting IDENTIFIER\n j = 0;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_Permute.v:90: syntax error, unexpected $display\n $display("state_out: %h", state_out);\n ^~~~~~~~\n%Error: Cannot continue\n' | 295,952 | module | module tb_Permute;
reg [263:0] state_in;
reg [15:0] IV_in, INV_IV_in;
reg clk;
reg rst;
reg en;
wire [263:0] state_out;
wire [15:0] IV_out, INV_IV_out;
wire rdy;
Permute uut (
.state_in(state_in),
.IV_in(IV_in),
.INV_IV_in(INV_IV_in),
.state_out(state_out),
.IV_out(IV_out),
.INV_IV_out(INV_IV_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
reg [31:0] iteration;
integer i, j;
initial begin
state_in = 0;
clk = 0;
rst = 1;
en = 0;
iteration = 0;
#100;
rst = 0;
IV_in = 16'hc6;
INV_IV_in = 16'h0;
$display("[INITIALIZING]");
for (i=0; i<`nSBox; i=i+1) begin
state_in = state_in | i<<(i*8);
end
j = 0;
$display("state in: %h", state_in);
en = 1;
repeat (135) begin
rst = 0;
repeat (70) begin
#5;
end
if (rdy) begin
state_in = state_out;
IV_in = IV_out;
INV_IV_in = INV_IV_out;
end
rst = 1;
j = j+1;
if (j == 135)
$display("state_out: %h", state_out);
#5;
end
end
always begin
#5; clk = !clk;
end
endmodule | module tb_Permute; |
reg [263:0] state_in;
reg [15:0] IV_in, INV_IV_in;
reg clk;
reg rst;
reg en;
wire [263:0] state_out;
wire [15:0] IV_out, INV_IV_out;
wire rdy;
Permute uut (
.state_in(state_in),
.IV_in(IV_in),
.INV_IV_in(INV_IV_in),
.state_out(state_out),
.IV_out(IV_out),
.INV_IV_out(INV_IV_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
reg [31:0] iteration;
integer i, j;
initial begin
state_in = 0;
clk = 0;
rst = 1;
en = 0;
iteration = 0;
#100;
rst = 0;
IV_in = 16'hc6;
INV_IV_in = 16'h0;
$display("[INITIALIZING]");
for (i=0; i<`nSBox; i=i+1) begin
state_in = state_in | i<<(i*8);
end
j = 0;
$display("state in: %h", state_in);
en = 1;
repeat (135) begin
rst = 0;
repeat (70) begin
#5;
end
if (rdy) begin
state_in = state_out;
IV_in = IV_out;
INV_IV_in = INV_IV_out;
end
rst = 1;
j = j+1;
if (j == 135)
$display("state_out: %h", state_out);
#5;
end
end
always begin
#5; clk = !clk;
end
endmodule | 0 |
137,361 | data/full_repos/permissive/77923266/verilog/tb_Pi.v | 77,923,266 | tb_Pi.v | v | 75 | 80 | [] | [] | [] | [(25, 73)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:51: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:53: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:56: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:60: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:63: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:66: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_Pi.v:71: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_Pi.v:36: Cannot find file containing module: \'Pi_mod\'\n Pi_mod uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/Pi_mod\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/Pi_mod.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/Pi_mod.sv\n Pi_mod\n Pi_mod.v\n Pi_mod.sv\n obj_dir/Pi_mod\n obj_dir/Pi_mod.v\n obj_dir/Pi_mod.sv\n%Warning-WIDTH: data/full_repos/permissive/77923266/verilog/tb_Pi.v:59: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'hfe\' generates 31 bits.\n : ... In instance tb_Pi\n in = 31\'h000000FE;\n ^\n%Warning-WIDTH: data/full_repos/permissive/77923266/verilog/tb_Pi.v:62: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'hfd\' generates 31 bits.\n : ... In instance tb_Pi\n in = 31\'h000000FD;\n ^\n%Warning-WIDTH: data/full_repos/permissive/77923266/verilog/tb_Pi.v:65: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h100\' generates 31 bits.\n : ... In instance tb_Pi\n in = 31\'h00000100;\n ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,953 | module | module tb_Pi;
reg [31:0] in;
reg clk;
reg rst;
wire [8:0] out;
Pi_mod uut (
.in(in),
.out(out),
.clk(clk),
.rst(rst)
);
initial begin
in = 0;
clk = 0;
#5;
rst = 1;
#5;
rst = 0;
#5;
while ( in < 10) begin
#5;
$display ("i = %d, Pi=%h", in, out);
in = in + 1;
#5;
end
in = 31'h000000FE;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
in = 31'h000000FD;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
in = 31'h00000100;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
end
always begin
#5 clk = !clk;
end
endmodule | module tb_Pi; |
reg [31:0] in;
reg clk;
reg rst;
wire [8:0] out;
Pi_mod uut (
.in(in),
.out(out),
.clk(clk),
.rst(rst)
);
initial begin
in = 0;
clk = 0;
#5;
rst = 1;
#5;
rst = 0;
#5;
while ( in < 10) begin
#5;
$display ("i = %d, Pi=%h", in, out);
in = in + 1;
#5;
end
in = 31'h000000FE;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
in = 31'h000000FD;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
in = 31'h00000100;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
end
always begin
#5 clk = !clk;
end
endmodule | 0 |
137,362 | data/full_repos/permissive/77923266/verilog/tb_pLayer.v | 77,923,266 | tb_pLayer.v | v | 89 | 86 | [] | [] | [] | null | line:327: before: "(" | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_pLayer.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_pLayer.v:63: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_pLayer.v:70: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_pLayer.v:76: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_pLayer.v:85: Unsupported: Ignoring delay on this delayed statement.\n #5; clk = !clk;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 295,954 | module | module tb_pLayer;
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
wire [263:0] state_out;
wire out_rdy;
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.out_rdy(out_rdy)
);
initial begin
state_in = 0;
clk = 0;
rst = 1;
#100;
rst = 0;
$display("[INITIALIZING]");
en = 1;
state_in = 264'h20d6d3dcd9d5d8dad7dfd4d1d2d0dbdddee6e3ece9e5e8eae7efe4e1e2e0ebed94;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
rst = 1; en = 0;
#5;
en = 1; rst = 0;
state_in = 264'ha8365886353658867333568863335688ca2ed1e22f3856833e55353353dd2d22a5;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
end
always begin
#5; clk = !clk;
end
endmodule | module tb_pLayer; |
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
wire [263:0] state_out;
wire out_rdy;
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.out_rdy(out_rdy)
);
initial begin
state_in = 0;
clk = 0;
rst = 1;
#100;
rst = 0;
$display("[INITIALIZING]");
en = 1;
state_in = 264'h20d6d3dcd9d5d8dad7dfd4d1d2d0dbdddee6e3ece9e5e8eae7efe4e1e2e0ebed94;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
rst = 1; en = 0;
#5;
en = 1; rst = 0;
state_in = 264'ha8365886353658867333568863335688ca2ed1e22f3856833e55353353dd2d22a5;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
end
always begin
#5; clk = !clk;
end
endmodule | 0 |
137,363 | data/full_repos/permissive/77923266/verilog/tb_pLayer2.v | 77,923,266 | tb_pLayer2.v | v | 91 | 80 | [] | [] | [] | [(290, 354)] | null | null | 1: b'%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer2.v:2: Cannot find include file: constants.vh\n`include "constants.vh"\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/constants.vh.sv\n constants.vh\n constants.vh.v\n constants.vh.sv\n obj_dir/constants.vh\n obj_dir/constants.vh.v\n obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer2.v:62: Define or directive not defined: \'`nSBox\'\n for (i=0; i<`nSBox; i=i+1) begin\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer2.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0; i<`nSBox; i=i+1) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer2.v:62: syntax error, unexpected \')\', expecting \';\'\n for (i=0; i<`nSBox; i=i+1) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer2.v:65: Define or directive not defined: \'`nSBox\'\n for (i=0; i < `nSBox ; i = i+1) begin\n ^~~~~~\n%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer2.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0; i < `nSBox ; i = i+1) begin\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_pLayer2.v:66: Define or directive not defined: \'`nSBox\'\n temp_state_in[((`nSBox-1)*8)-(8*i) +: 8] = i;\n ^~~~~~\n%Error: Cannot continue\n' | 295,955 | module | module tb_pLayer2;
reg [263:0] state_in;
reg [31:0] index;
reg clk;
reg rst;
reg enable;
wire [263:0] state_out;
wire output_rdy;
reg [7:0] state [0:32];
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.index(index),
.clk(clk),
.rst(rst),
.enable(enable),
.output_rdy(output_rdy)
);
reg [263:0] temp_state_in;
integer i;
initial begin
state_in = 0;
index = 0;
clk = 0;
rst = 0;
enable = 0;
for (i=0; i<`nSBox; i=i+1) begin
state [i] = i;
end
for (i=0; i < `nSBox ; i = i+1) begin
temp_state_in[((`nSBox-1)*8)-(8*i) +: 8] = i;
end
$display("input state: %h", state);
#100;
enable = 1;
state_in = temp_state_in;
$display("out: %h", state_out);
#5;
$display("out: %h", state_out);
#5;
$display("out: %h", state_out);
end
always begin
#5; clk = !clk;
end
endmodule | module tb_pLayer2; |
reg [263:0] state_in;
reg [31:0] index;
reg clk;
reg rst;
reg enable;
wire [263:0] state_out;
wire output_rdy;
reg [7:0] state [0:32];
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.index(index),
.clk(clk),
.rst(rst),
.enable(enable),
.output_rdy(output_rdy)
);
reg [263:0] temp_state_in;
integer i;
initial begin
state_in = 0;
index = 0;
clk = 0;
rst = 0;
enable = 0;
for (i=0; i<`nSBox; i=i+1) begin
state [i] = i;
end
for (i=0; i < `nSBox ; i = i+1) begin
temp_state_in[((`nSBox-1)*8)-(8*i) +: 8] = i;
end
$display("input state: %h", state);
#100;
enable = 1;
state_in = temp_state_in;
$display("out: %h", state_out);
#5;
$display("out: %h", state_out);
#5;
$display("out: %h", state_out);
end
always begin
#5; clk = !clk;
end
endmodule | 0 |
137,364 | data/full_repos/permissive/77923266/verilog/tb_retnuoCl.v | 77,923,266 | tb_retnuoCl.v | v | 58 | 81 | [] | [] | [] | [(25, 56)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_retnuoCl.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_retnuoCl.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_retnuoCl.v:52: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_retnuoCl.v:34: Cannot find file containing module: \'retnuoCl\'\n retnuoCl uut (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/retnuoCl\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/retnuoCl.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/retnuoCl.sv\n retnuoCl\n retnuoCl.v\n retnuoCl.sv\n obj_dir/retnuoCl\n obj_dir/retnuoCl.v\n obj_dir/retnuoCl.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,956 | module | module tb_retnuoCl;
reg [15:0] lfsr;
wire [15:0] out;
retnuoCl uut (
.lfsr(lfsr),
.out(out)
);
initial begin
lfsr = 16'b0000000000000000;
$display("set lsfr to : %d", lfsr);
#100;
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, out=%b, (hex): %h", lfsr, out, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule | module tb_retnuoCl; |
reg [15:0] lfsr;
wire [15:0] out;
retnuoCl uut (
.lfsr(lfsr),
.out(out)
);
initial begin
lfsr = 16'b0000000000000000;
$display("set lsfr to : %d", lfsr);
#100;
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, out=%b, (hex): %h", lfsr, out, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule | 0 |
137,365 | data/full_repos/permissive/77923266/verilog/tb_SpongentHash.v | 77,923,266 | tb_SpongentHash.v | v | 68 | 83 | [] | [] | [] | [(21, 68)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_SpongentHash.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/77923266/verilog/tb_SpongentHash.v:57: Unsupported: Ignoring delay on this delayed statement.\n #5; clk = !clk;\n ^\n%Error: data/full_repos/permissive/77923266/verilog/tb_SpongentHash.v:31: Cannot find file containing module: \'SpongentHash\'\n SpongentHash uut (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/SpongentHash\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/SpongentHash.v\n data/full_repos/permissive/77923266/verilog,data/full_repos/permissive/77923266/SpongentHash.sv\n SpongentHash\n SpongentHash.v\n SpongentHash.sv\n obj_dir/SpongentHash\n obj_dir/SpongentHash.v\n obj_dir/SpongentHash.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,957 | module | module tb_SpongentHash;
wire [87:0] hash;
reg [87:0] reference_hash;
reg clk;
reg rst;
reg en;
wire rdy;
SpongentHash uut (
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy),
.hash_out(hash)
);
initial begin
clk = 0;
rst = 1;
en = 0;
reference_hash = 88'h06846ff7186c0cfa5dfd32;
#100;
rst = 0;
en = 1;
end
always begin
#5; clk = !clk;
end
always @ rdy begin
if (rdy == 1) begin
$display("hash %h", hash);
if (hash === reference_hash) begin
$display("SUCCESS");
end
end
end
endmodule | module tb_SpongentHash; |
wire [87:0] hash;
reg [87:0] reference_hash;
reg clk;
reg rst;
reg en;
wire rdy;
SpongentHash uut (
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy),
.hash_out(hash)
);
initial begin
clk = 0;
rst = 1;
en = 0;
reference_hash = 88'h06846ff7186c0cfa5dfd32;
#100;
rst = 0;
en = 1;
end
always begin
#5; clk = !clk;
end
always @ rdy begin
if (rdy == 1) begin
$display("hash %h", hash);
if (hash === reference_hash) begin
$display("SUCCESS");
end
end
end
endmodule | 0 |
137,368 | data/full_repos/permissive/779589/src/gb/joypad.v | 779,589 | joypad.v | v | 45 | 75 | [] | [] | [] | [(4, 44)] | null | data/verilator_xmls/9af32afe-9174-4947-ade5-7b6a650187bb.xml | null | 295,960 | module | module joypad_controller(
input wire clock,
input wire reset,
input wire int_ack,
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire rd_n,
input wire wr_n,
input wire cs,
output reg [1:0] button_sel,
input wire [3:0] button_data
);
always @(posedge clock) begin
if (reset)
int_req <= 0;
else begin
if (!wr_n) begin
if (A == 16'hFF00)
button_sel <= Di[5:4];
end
end
end
assign Do = (cs) ? { 2'b11, button_sel[1:0], button_data[3:0] } : 8'hFF;
endmodule | module joypad_controller(
input wire clock,
input wire reset,
input wire int_ack,
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire rd_n,
input wire wr_n,
input wire cs,
output reg [1:0] button_sel,
input wire [3:0] button_data
); |
always @(posedge clock) begin
if (reset)
int_req <= 0;
else begin
if (!wr_n) begin
if (A == 16'hFF00)
button_sel <= Di[5:4];
end
end
end
assign Do = (cs) ? { 2'b11, button_sel[1:0], button_data[3:0] } : 8'hFF;
endmodule | 83 |
137,369 | data/full_repos/permissive/779589/src/gb/mmu.v | 779,589 | mmu.v | v | 142 | 85 | [] | [] | [] | [(4, 141)] | null | null | 1: b'%Error: data/full_repos/permissive/779589/src/gb/mmu.v:67: Cannot find file containing module: \'async_mem\'\n async_mem #(.asz(8), .depth(127)) high_ram (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/779589/src/gb,data/full_repos/permissive/779589/async_mem\n data/full_repos/permissive/779589/src/gb,data/full_repos/permissive/779589/async_mem.v\n data/full_repos/permissive/779589/src/gb,data/full_repos/permissive/779589/async_mem.sv\n async_mem\n async_mem.v\n async_mem.sv\n obj_dir/async_mem\n obj_dir/async_mem.v\n obj_dir/async_mem.sv\n%Warning-WIDTH: data/full_repos/permissive/779589/src/gb/mmu.v:115: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 16 bits.\n : ... In instance mmu\n assign A_jump_rom = A - 16\'hFEA0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/779589/src/gb/mmu.v:116: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 16 bits.\n : ... In instance mmu\n assign A_high_ram = A - 16\'hFF80;\n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/gb/mmu.v:131: Bit extraction of array[255:0] requires 8 bit index, not 16 bits.\n : ... In instance mmu\n (cs_boot_rom) ? boot_rom[A_cpu] :\n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/gb/mmu.v:133: Bit extraction of array[9:0] requires 4 bit index, not 7 bits.\n : ... In instance mmu\n (cs_jump_rom) ? jump_rom[A_jump_rom] :\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n' | 295,961 | module | module mmu(
input wire clock,
input wire reset,
input wire [15:0] A_cpu,
input wire [7:0] Di_cpu,
output wire [7:0] Do_cpu,
input wire rd_cpu_n,
input wire wr_cpu_n,
output wire [15:0] A,
output wire [7:0] Do,
input wire [7:0] Di,
output wire wr_n,
output wire rd_n,
output wire cs_n,
output wire [15:0] A_ppu,
output wire [7:0] Do_ppu,
input wire [7:0] Di_ppu,
output wire rd_ppu_n,
output wire wr_ppu_n,
output wire cs_ppu,
input wire [7:0] Do_interrupt,
input wire [7:0] Do_timer,
input wire [7:0] Do_sound,
input wire [7:0] Do_joypad,
output wire cs_interrupt,
output wire cs_timer,
output wire cs_sound,
output wire cs_joypad
);
wire [7:0] Do_high_ram;
wire cs_boot_rom;
wire cs_jump_rom;
wire cs_high_ram;
wire [6:0] A_jump_rom;
wire [6:0] A_high_ram;
reg boot_rom_enable;
reg [7:0] boot_rom [0:255];
reg [7:0] jump_rom [0:9];
initial begin
$readmemh("data/boot.hex", boot_rom, 0, 255);
$readmemh("data/jump.hex", jump_rom, 0, 9);
end
async_mem #(.asz(8), .depth(127)) high_ram (
.rd_data(Do_high_ram),
.wr_clk(clock),
.wr_data(Di_cpu),
.wr_cs(cs_high_ram && !wr_n),
.addr(A_high_ram),
.rd_cs(cs_high_ram)
);
always @ (posedge clock)
begin
if (reset)
begin
boot_rom_enable <= 1;
end
else
begin
if (!wr_n)
begin
case(A)
16'hFF46:
begin
end
16'hFF50: if (Di == 8'h01) boot_rom_enable <= 1'b0;
endcase
end
end
end
assign cs_n = (A < 16'hFE00) ? 1'b0 : 1'b1;
assign cs_ppu =
(A >= 16'h8000 && A < 16'hA000) ||
(A >= 16'hFE00 && A < 16'hFEA0) ||
(A >= 16'hFF40 && A <= 16'hFF4B && A != 16'hFF46);
assign cs_boot_rom = boot_rom_enable && A < 16'h0100;
assign cs_jump_rom = A >= 16'hFEA0 && A < 16'hFF00;
assign cs_high_ram = A >= 16'hFF80 && A < 16'hFFFF;
assign cs_interrupt = A == 16'hFF0F || A == 16'hFFFF;
assign cs_sound = A >= 16'hFF10 && A <= 16'hFF3F;
assign cs_timer = A >= 16'hFF04 && A <= 16'hFF07;
assign cs_joypad = A == 16'hFF00;
assign A_jump_rom = A - 16'hFEA0;
assign A_high_ram = A - 16'hFF80;
assign A = A_cpu;
assign Do = Di_cpu;
assign wr_n = wr_cpu_n;
assign rd_n = rd_cpu_n;
assign A_ppu = A_cpu;
assign Do_ppu = Di_cpu;
assign wr_ppu_n = wr_cpu_n;
assign rd_ppu_n = rd_cpu_n;
assign Do_cpu =
(cs_boot_rom) ? boot_rom[A_cpu] :
(cs_high_ram) ? Do_high_ram :
(cs_jump_rom) ? jump_rom[A_jump_rom] :
(cs_interrupt) ? Do_interrupt :
(cs_timer) ? Do_timer :
(cs_sound) ? Do_sound :
(cs_joypad) ? Do_joypad :
(cs_ppu) ? Do_ppu :
(!cs_n) ? Di : 8'hFF;
endmodule | module mmu(
input wire clock,
input wire reset,
input wire [15:0] A_cpu,
input wire [7:0] Di_cpu,
output wire [7:0] Do_cpu,
input wire rd_cpu_n,
input wire wr_cpu_n,
output wire [15:0] A,
output wire [7:0] Do,
input wire [7:0] Di,
output wire wr_n,
output wire rd_n,
output wire cs_n,
output wire [15:0] A_ppu,
output wire [7:0] Do_ppu,
input wire [7:0] Di_ppu,
output wire rd_ppu_n,
output wire wr_ppu_n,
output wire cs_ppu,
input wire [7:0] Do_interrupt,
input wire [7:0] Do_timer,
input wire [7:0] Do_sound,
input wire [7:0] Do_joypad,
output wire cs_interrupt,
output wire cs_timer,
output wire cs_sound,
output wire cs_joypad
); |
wire [7:0] Do_high_ram;
wire cs_boot_rom;
wire cs_jump_rom;
wire cs_high_ram;
wire [6:0] A_jump_rom;
wire [6:0] A_high_ram;
reg boot_rom_enable;
reg [7:0] boot_rom [0:255];
reg [7:0] jump_rom [0:9];
initial begin
$readmemh("data/boot.hex", boot_rom, 0, 255);
$readmemh("data/jump.hex", jump_rom, 0, 9);
end
async_mem #(.asz(8), .depth(127)) high_ram (
.rd_data(Do_high_ram),
.wr_clk(clock),
.wr_data(Di_cpu),
.wr_cs(cs_high_ram && !wr_n),
.addr(A_high_ram),
.rd_cs(cs_high_ram)
);
always @ (posedge clock)
begin
if (reset)
begin
boot_rom_enable <= 1;
end
else
begin
if (!wr_n)
begin
case(A)
16'hFF46:
begin
end
16'hFF50: if (Di == 8'h01) boot_rom_enable <= 1'b0;
endcase
end
end
end
assign cs_n = (A < 16'hFE00) ? 1'b0 : 1'b1;
assign cs_ppu =
(A >= 16'h8000 && A < 16'hA000) ||
(A >= 16'hFE00 && A < 16'hFEA0) ||
(A >= 16'hFF40 && A <= 16'hFF4B && A != 16'hFF46);
assign cs_boot_rom = boot_rom_enable && A < 16'h0100;
assign cs_jump_rom = A >= 16'hFEA0 && A < 16'hFF00;
assign cs_high_ram = A >= 16'hFF80 && A < 16'hFFFF;
assign cs_interrupt = A == 16'hFF0F || A == 16'hFFFF;
assign cs_sound = A >= 16'hFF10 && A <= 16'hFF3F;
assign cs_timer = A >= 16'hFF04 && A <= 16'hFF07;
assign cs_joypad = A == 16'hFF00;
assign A_jump_rom = A - 16'hFEA0;
assign A_high_ram = A - 16'hFF80;
assign A = A_cpu;
assign Do = Di_cpu;
assign wr_n = wr_cpu_n;
assign rd_n = rd_cpu_n;
assign A_ppu = A_cpu;
assign Do_ppu = Di_cpu;
assign wr_ppu_n = wr_cpu_n;
assign rd_ppu_n = rd_cpu_n;
assign Do_cpu =
(cs_boot_rom) ? boot_rom[A_cpu] :
(cs_high_ram) ? Do_high_ram :
(cs_jump_rom) ? jump_rom[A_jump_rom] :
(cs_interrupt) ? Do_interrupt :
(cs_timer) ? Do_timer :
(cs_sound) ? Do_sound :
(cs_joypad) ? Do_joypad :
(cs_ppu) ? Do_ppu :
(!cs_n) ? Di : 8'hFF;
endmodule | 83 |
137,373 | data/full_repos/permissive/779589/src/io/debug/cls_spi.v | 779,589 | cls_spi.v | v | 345 | 76 | [] | [] | [] | null | line:104: before: "state" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:152: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance cls_spi\n send_buf <= glyph_rom[(data >> ({hex_idx, 2\'b00})) & 4\'hF];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:152: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance cls_spi\n send_buf <= glyph_rom[(data >> ({hex_idx, 2\'b00})) & 4\'hF];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:166: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 0: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h42; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:166: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h42\' generates 8 bits.\n : ... In instance cls_spi\n 0: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h42; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:167: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 1: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h59; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:167: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h59\' generates 8 bits.\n : ... In instance cls_spi\n 1: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h59; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:168: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 2: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h73; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:168: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h73\' generates 8 bits.\n : ... In instance cls_spi\n 2: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h73; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:169: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 3: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h53; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:169: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h53\' generates 8 bits.\n : ... In instance cls_spi\n 3: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h53; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:170: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 4: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h5E; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:170: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h5e\' generates 8 bits.\n : ... In instance cls_spi\n 4: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h5E; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:171: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 5: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h64; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:171: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h64\' generates 8 bits.\n : ... In instance cls_spi\n 5: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h64; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:172: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 6: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h3C; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:172: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h3c\' generates 8 bits.\n : ... In instance cls_spi\n 6: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h3C; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:173: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 7: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h3E; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:173: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h3e\' generates 8 bits.\n : ... In instance cls_spi\n 7: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h3E; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:174: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 8: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h41; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:174: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h41\' generates 8 bits.\n : ... In instance cls_spi\n 8: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h41; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:175: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 9: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h58; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:175: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h58\' generates 8 bits.\n : ... In instance cls_spi\n 9: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h58; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:176: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 10: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h4C; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:176: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h4c\' generates 8 bits.\n : ... In instance cls_spi\n 10: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h4C; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:177: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n 11: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h52; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:177: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'8\'h52\' generates 8 bits.\n : ... In instance cls_spi\n 11: send_buf <= joypad_state[btn_idx] ? 8\'h20 : 8\'h52; \n ^\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:178: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance cls_spi\n default: send_buf <= 8\'h20;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:203: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h65335b1b\' generates 32 bits.\n : ... In instance cls_spi\n send_buf <= 32\'h65335B1B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:211: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h6a305b1b\' generates 32 bits.\n : ... In instance cls_spi\n send_buf <= 32\'h6A305B1B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:219: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h63305b1b\' generates 32 bits.\n : ... In instance cls_spi\n send_buf <= 32\'h63305B1B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:227: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h68305b1b\' generates 32 bits.\n : ... In instance cls_spi\n send_buf <= 32\'h68305B1B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:235: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'48\'h48303b305b1b\' generates 48 bits.\n : ... In instance cls_spi\n send_buf <= 48\'h48303B305B1B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:243: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h3a4120\' generates 24 bits.\n : ... In instance cls_spi\n send_buf <= 24\'h3A4120; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:250: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 16 bits.\n : ... In instance cls_spi\n data <= A;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:257: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3a4f4920\' generates 32 bits.\n : ... In instance cls_spi\n send_buf <= 32\'h3A4f4920; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:264: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n : ... In instance cls_spi\n data <= { Di, Do };\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:271: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'48\'h48303b315b1b\' generates 48 bits.\n : ... In instance cls_spi\n send_buf <= 48\'h48303B315B1B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:279: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h3a4350\' generates 24 bits.\n : ... In instance cls_spi\n 2\'b00: send_buf <= 24\'h3A4350; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:280: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h3a4641\' generates 24 bits.\n : ... In instance cls_spi\n 2\'b01: send_buf <= 24\'h3A4641; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:281: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h3a4544\' generates 24 bits.\n : ... In instance cls_spi\n 2\'b10: send_buf <= 24\'h3A4544; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:290: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC\' generates 16 bits.\n : ... In instance cls_spi\n 2\'b00: data <= PC;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:291: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'AF\' generates 16 bits.\n : ... In instance cls_spi\n 2\'b01: data <= AF;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:292: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'DE\' generates 16 bits.\n : ... In instance cls_spi\n 2\'b10: data <= DE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:301: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3a505320\' generates 32 bits.\n : ... In instance cls_spi\n 2\'b00: send_buf <= 32\'h3A505320; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:302: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3a434220\' generates 32 bits.\n : ... In instance cls_spi\n 2\'b01: send_buf <= 32\'h3A434220; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:303: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3a4c4820\' generates 32 bits.\n : ... In instance cls_spi\n 2\'b10: send_buf <= 32\'h3A4C4820; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:312: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'SP\' generates 16 bits.\n : ... In instance cls_spi\n 2\'b00: data <= SP;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:313: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'BC\' generates 16 bits.\n : ... In instance cls_spi\n 2\'b01: data <= BC;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:314: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'HL\' generates 16 bits.\n : ... In instance cls_spi\n 2\'b10: data <= HL;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/debug/cls_spi.v:322: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2020\' generates 16 bits.\n : ... In instance cls_spi\n send_buf <= 16\'h2020;\n ^~\n%Error: Exiting due to 50 warning(s)\n' | 295,965 | module | module cls_spi(
input wire clock,
input wire reset,
input wire [15:0] A,
input wire [7:0] Di,
input wire [7:0] Do,
input wire [15:0] PC,
input wire [15:0] SP,
input wire [15:0] AF,
input wire [15:0] BC,
input wire [15:0] DE,
input wire [15:0] HL,
input wire [15:0] joypad_state,
input wire [1:0] mode,
output wire ss,
output reg mosi,
input wire miso,
output wire sclk
);
parameter WAIT = 1;
parameter SEND = 2;
parameter SEND_2 = 3;
parameter SEND_3 = 4;
parameter SEND_4 = 5;
parameter SEND_5 = 6;
parameter SENDHEX = 7;
parameter SENDJOYPAD = 8;
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter LOOP_1 = 20;
parameter LOOP_2 = 21;
parameter LOOP_3 = 22;
parameter LOOP_4 = 23;
parameter LOOP_5 = 24;
parameter LOOP_6 = 25;
parameter LOOP_7 = 26;
parameter LOOP_8 = 27;
parameter LOOP_9 = 28;
parameter LOOP_10 = 29;
parameter LOOP_11 = 30;
parameter LOOP_7b = 31;
parameter LOOP_8b = 32;
reg [63:0] send_buf;
reg [2:0] send_idx;
reg [2:0] send_ctr;
reg [2:0] send_max;
reg [31:0] wait_ctr;
reg [31:0] wait_max;
reg [2:0] hex_idx;
reg [3:0] btn_idx;
reg [1:0] mode_latch;
reg [7:0] state;
reg [7:0] next_state;
reg [7:0] next_state_hex;
reg [7:0] next_state_btn;
reg ss_enable;
reg sclk_enable;
reg [7:0] glyph_rom [15:0];
reg [31:0] data;
reg [1:0] data_idx;
initial begin
$readmemh("data/hexascii.hex", glyph_rom, 0, 15);
end
always @(posedge clock) begin
if (reset) begin
send_buf <= 64'b0;
send_idx <= 3'b0;
send_ctr <= 3'b0;
send_max <= 3'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 8'b0;
next_state_hex <= 8'b0;
next_state_btn <= 8'b0;
mode_latch <= 2'b0;
hex_idx <= 3'b0;
btn_idx <= 4'b0;
data <= 32'b0;
data_idx <= 2'b0;
ss_enable <= 0;
sclk_enable <= 0;
mosi <= 1'b0;
end
else begin
if (state == SEND) begin
ss_enable <= 1;
state <= SEND_2;
end
else if (state == SEND_2) begin
state <= SEND_3;
end
else if (state == SEND_3) begin
mosi <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7) begin
send_idx <= 0;
state <= SEND_4;
end else begin
sclk_enable <= 1;
send_idx <= send_idx + 1;
end
end
else if (state == SEND_4) begin
mosi <= 0;
state <= SEND_5;
end
else if (state == SEND_5) begin
sclk_enable <= 0;
ss_enable <= 0;
if (send_ctr == send_max) begin
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else begin
send_ctr <= send_ctr + 1;
state <= SEND;
end
end
else if (state == SENDHEX) begin
send_buf <= glyph_rom[(data >> ({hex_idx, 2'b00})) & 4'hF];
send_max <= 0;
if (hex_idx == 0) begin
next_state <= next_state_hex;
end else begin
next_state <= SENDHEX;
hex_idx <= hex_idx - 1;
end
state <= SEND;
end
else if (state == SENDJOYPAD) begin
case (btn_idx)
0: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h42;
1: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h59;
2: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h73;
3: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h53;
4: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h5E;
5: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h64;
6: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3C;
7: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3E;
8: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h41;
9: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h58;
10: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h4C;
11: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h52;
default: send_buf <= 8'h20;
endcase
send_max <= 0;
if (btn_idx == 15) begin
btn_idx <= 4'b0;
next_state <= next_state_btn;
end else begin
next_state <= SENDJOYPAD;
btn_idx <= btn_idx + 1;
end
state <= SEND;
end
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
else if (state == STARTUP_1) begin
send_buf <= 32'h65335B1B;
send_max <= 3;
state <= SEND;
next_state <= STARTUP_2;
end
else if (state == STARTUP_2) begin
send_buf <= 32'h6A305B1B;
send_max <= 3;
state <= SEND;
next_state <= STARTUP_3;
end
else if (state == STARTUP_3) begin
send_buf <= 32'h63305B1B;
send_max <= 3;
state <= SEND;
next_state <= STARTUP_4;
end
else if (state == STARTUP_4) begin
send_buf <= 32'h68305B1B;
send_max <= 3;
state <= SEND;
next_state <= LOOP_1;
end
else if (state == LOOP_1) begin
send_buf <= 48'h48303B305B1B;
send_max <= 5;
state <= SEND;
next_state <= LOOP_2;
mode_latch <= mode;
end
else if (state == LOOP_2) begin
send_buf <= 24'h3A4120;
send_max <= 2;
state <= SEND;
next_state <= LOOP_3;
end
else if (state == LOOP_3) begin
data <= A;
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_4;
end
else if (state == LOOP_4) begin
send_buf <= 32'h3A4f4920;
send_max <= 3;
state <= SEND;
next_state <= LOOP_5;
end
else if (state == LOOP_5) begin
data <= { Di, Do };
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_6;
end
else if (state == LOOP_6) begin
send_buf <= 48'h48303B315B1B;
send_max <= 5;
state <= SEND;
next_state <= mode_latch == 2'b11 ? LOOP_7b : LOOP_7;
end
else if (state == LOOP_7) begin
case (mode_latch)
2'b00: send_buf <= 24'h3A4350;
2'b01: send_buf <= 24'h3A4641;
2'b10: send_buf <= 24'h3A4544;
endcase
send_max <= 2;
state <= SEND;
next_state <= LOOP_8;
end
else if (state == LOOP_8) begin
case (mode_latch)
2'b00: data <= PC;
2'b01: data <= AF;
2'b10: data <= DE;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_9;
end
else if (state == LOOP_9) begin
case (mode_latch)
2'b00: send_buf <= 32'h3A505320;
2'b01: send_buf <= 32'h3A434220;
2'b10: send_buf <= 32'h3A4C4820;
endcase
send_max <= 3;
state <= SEND;
next_state <= LOOP_10;
end
else if (state == LOOP_10) begin
case (mode_latch)
2'b00: data <= SP;
2'b01: data <= BC;
2'b10: data <= HL;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_11;
end
else if (state == LOOP_7b) begin
send_buf <= 16'h2020;
send_max <= 1;
state <= SEND;
next_state <= LOOP_8b;
end
else if (state == LOOP_8b) begin
state <= SENDJOYPAD;
next_state_btn <= LOOP_11;
end
else if (state == LOOP_11) begin
wait_max <= 10;
state <= WAIT;
next_state <= LOOP_1;
end
end
end
assign ss = (ss_enable) ? 1'b0 : 1'b1;
assign sclk = (sclk_enable) ? !clock : 1'b1;
endmodule | module cls_spi(
input wire clock,
input wire reset,
input wire [15:0] A,
input wire [7:0] Di,
input wire [7:0] Do,
input wire [15:0] PC,
input wire [15:0] SP,
input wire [15:0] AF,
input wire [15:0] BC,
input wire [15:0] DE,
input wire [15:0] HL,
input wire [15:0] joypad_state,
input wire [1:0] mode,
output wire ss,
output reg mosi,
input wire miso,
output wire sclk
); |
parameter WAIT = 1;
parameter SEND = 2;
parameter SEND_2 = 3;
parameter SEND_3 = 4;
parameter SEND_4 = 5;
parameter SEND_5 = 6;
parameter SENDHEX = 7;
parameter SENDJOYPAD = 8;
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter LOOP_1 = 20;
parameter LOOP_2 = 21;
parameter LOOP_3 = 22;
parameter LOOP_4 = 23;
parameter LOOP_5 = 24;
parameter LOOP_6 = 25;
parameter LOOP_7 = 26;
parameter LOOP_8 = 27;
parameter LOOP_9 = 28;
parameter LOOP_10 = 29;
parameter LOOP_11 = 30;
parameter LOOP_7b = 31;
parameter LOOP_8b = 32;
reg [63:0] send_buf;
reg [2:0] send_idx;
reg [2:0] send_ctr;
reg [2:0] send_max;
reg [31:0] wait_ctr;
reg [31:0] wait_max;
reg [2:0] hex_idx;
reg [3:0] btn_idx;
reg [1:0] mode_latch;
reg [7:0] state;
reg [7:0] next_state;
reg [7:0] next_state_hex;
reg [7:0] next_state_btn;
reg ss_enable;
reg sclk_enable;
reg [7:0] glyph_rom [15:0];
reg [31:0] data;
reg [1:0] data_idx;
initial begin
$readmemh("data/hexascii.hex", glyph_rom, 0, 15);
end
always @(posedge clock) begin
if (reset) begin
send_buf <= 64'b0;
send_idx <= 3'b0;
send_ctr <= 3'b0;
send_max <= 3'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 8'b0;
next_state_hex <= 8'b0;
next_state_btn <= 8'b0;
mode_latch <= 2'b0;
hex_idx <= 3'b0;
btn_idx <= 4'b0;
data <= 32'b0;
data_idx <= 2'b0;
ss_enable <= 0;
sclk_enable <= 0;
mosi <= 1'b0;
end
else begin
if (state == SEND) begin
ss_enable <= 1;
state <= SEND_2;
end
else if (state == SEND_2) begin
state <= SEND_3;
end
else if (state == SEND_3) begin
mosi <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7) begin
send_idx <= 0;
state <= SEND_4;
end else begin
sclk_enable <= 1;
send_idx <= send_idx + 1;
end
end
else if (state == SEND_4) begin
mosi <= 0;
state <= SEND_5;
end
else if (state == SEND_5) begin
sclk_enable <= 0;
ss_enable <= 0;
if (send_ctr == send_max) begin
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else begin
send_ctr <= send_ctr + 1;
state <= SEND;
end
end
else if (state == SENDHEX) begin
send_buf <= glyph_rom[(data >> ({hex_idx, 2'b00})) & 4'hF];
send_max <= 0;
if (hex_idx == 0) begin
next_state <= next_state_hex;
end else begin
next_state <= SENDHEX;
hex_idx <= hex_idx - 1;
end
state <= SEND;
end
else if (state == SENDJOYPAD) begin
case (btn_idx)
0: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h42;
1: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h59;
2: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h73;
3: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h53;
4: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h5E;
5: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h64;
6: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3C;
7: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3E;
8: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h41;
9: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h58;
10: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h4C;
11: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h52;
default: send_buf <= 8'h20;
endcase
send_max <= 0;
if (btn_idx == 15) begin
btn_idx <= 4'b0;
next_state <= next_state_btn;
end else begin
next_state <= SENDJOYPAD;
btn_idx <= btn_idx + 1;
end
state <= SEND;
end
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
else if (state == STARTUP_1) begin
send_buf <= 32'h65335B1B;
send_max <= 3;
state <= SEND;
next_state <= STARTUP_2;
end
else if (state == STARTUP_2) begin
send_buf <= 32'h6A305B1B;
send_max <= 3;
state <= SEND;
next_state <= STARTUP_3;
end
else if (state == STARTUP_3) begin
send_buf <= 32'h63305B1B;
send_max <= 3;
state <= SEND;
next_state <= STARTUP_4;
end
else if (state == STARTUP_4) begin
send_buf <= 32'h68305B1B;
send_max <= 3;
state <= SEND;
next_state <= LOOP_1;
end
else if (state == LOOP_1) begin
send_buf <= 48'h48303B305B1B;
send_max <= 5;
state <= SEND;
next_state <= LOOP_2;
mode_latch <= mode;
end
else if (state == LOOP_2) begin
send_buf <= 24'h3A4120;
send_max <= 2;
state <= SEND;
next_state <= LOOP_3;
end
else if (state == LOOP_3) begin
data <= A;
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_4;
end
else if (state == LOOP_4) begin
send_buf <= 32'h3A4f4920;
send_max <= 3;
state <= SEND;
next_state <= LOOP_5;
end
else if (state == LOOP_5) begin
data <= { Di, Do };
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_6;
end
else if (state == LOOP_6) begin
send_buf <= 48'h48303B315B1B;
send_max <= 5;
state <= SEND;
next_state <= mode_latch == 2'b11 ? LOOP_7b : LOOP_7;
end
else if (state == LOOP_7) begin
case (mode_latch)
2'b00: send_buf <= 24'h3A4350;
2'b01: send_buf <= 24'h3A4641;
2'b10: send_buf <= 24'h3A4544;
endcase
send_max <= 2;
state <= SEND;
next_state <= LOOP_8;
end
else if (state == LOOP_8) begin
case (mode_latch)
2'b00: data <= PC;
2'b01: data <= AF;
2'b10: data <= DE;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_9;
end
else if (state == LOOP_9) begin
case (mode_latch)
2'b00: send_buf <= 32'h3A505320;
2'b01: send_buf <= 32'h3A434220;
2'b10: send_buf <= 32'h3A4C4820;
endcase
send_max <= 3;
state <= SEND;
next_state <= LOOP_10;
end
else if (state == LOOP_10) begin
case (mode_latch)
2'b00: data <= SP;
2'b01: data <= BC;
2'b10: data <= HL;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_11;
end
else if (state == LOOP_7b) begin
send_buf <= 16'h2020;
send_max <= 1;
state <= SEND;
next_state <= LOOP_8b;
end
else if (state == LOOP_8b) begin
state <= SENDJOYPAD;
next_state_btn <= LOOP_11;
end
else if (state == LOOP_11) begin
wait_max <= 10;
state <= WAIT;
next_state <= LOOP_1;
end
end
end
assign ss = (ss_enable) ? 1'b0 : 1'b1;
assign sclk = (sclk_enable) ? !clock : 1'b1;
endmodule | 83 |
137,377 | data/full_repos/permissive/779589/src/io/input/joypad_snes_adapter.v | 779,589 | joypad_snes_adapter.v | v | 89 | 110 | [] | [] | [] | [(4, 88)] | null | data/verilator_xmls/f4049e04-3929-4081-8a8b-5b07454ddf5a.xml | null | 295,969 | module | module joypad_snes_adapter(
input wire clock,
input wire reset,
input wire [1:0] button_sel,
output wire [3:0] button_data,
output reg [15:0] button_state,
input wire controller_data,
output wire controller_latch,
output wire controller_clock
);
parameter WAIT_STATE = 0;
parameter LATCH_STATE = 1;
parameter READ_STATE = 2;
reg [1:0] state;
reg [3:0] button_index;
always @(posedge clock) begin
if (reset)
state <= WAIT_STATE;
else begin
if (state == WAIT_STATE)
state <= LATCH_STATE;
else if (state == LATCH_STATE)
state <= READ_STATE;
else if (state == READ_STATE) begin
if (button_index == 15)
state <= WAIT_STATE;
end
end
end
always @(negedge clock) begin
if (reset) begin
button_index <= 4'b0;
button_state <= 16'hFFFF;
end else begin
if (state == WAIT_STATE)
button_index <= 4'b0;
else if (state == READ_STATE) begin
button_state[button_index] <= controller_data;
button_index <= button_index + 1;
end
end
end
assign controller_latch = (state == LATCH_STATE) ? 1'b1 : 1'b0;
assign controller_clock = (state == READ_STATE) ? clock : 1'b1;
assign button_data =
button_sel[0] == 1'b0 ? { button_state[7], button_state[6], button_state[4], button_state[5] } :
button_sel[1] == 1'b0 ? { button_state[8], button_state[0], button_state[2], button_state[3] } : 4'b1111;
endmodule | module joypad_snes_adapter(
input wire clock,
input wire reset,
input wire [1:0] button_sel,
output wire [3:0] button_data,
output reg [15:0] button_state,
input wire controller_data,
output wire controller_latch,
output wire controller_clock
); |
parameter WAIT_STATE = 0;
parameter LATCH_STATE = 1;
parameter READ_STATE = 2;
reg [1:0] state;
reg [3:0] button_index;
always @(posedge clock) begin
if (reset)
state <= WAIT_STATE;
else begin
if (state == WAIT_STATE)
state <= LATCH_STATE;
else if (state == LATCH_STATE)
state <= READ_STATE;
else if (state == READ_STATE) begin
if (button_index == 15)
state <= WAIT_STATE;
end
end
end
always @(negedge clock) begin
if (reset) begin
button_index <= 4'b0;
button_state <= 16'hFFFF;
end else begin
if (state == WAIT_STATE)
button_index <= 4'b0;
else if (state == READ_STATE) begin
button_state[button_index] <= controller_data;
button_index <= button_index + 1;
end
end
end
assign controller_latch = (state == LATCH_STATE) ? 1'b1 : 1'b0;
assign controller_clock = (state == READ_STATE) ? clock : 1'b1;
assign button_data =
button_sel[0] == 1'b0 ? { button_state[7], button_state[6], button_state[4], button_state[5] } :
button_sel[1] == 1'b0 ? { button_state[8], button_state[0], button_state[2], button_state[3] } : 4'b1111;
endmodule | 83 |
137,378 | data/full_repos/permissive/779589/src/io/input/joypad_snes_adapter_tb.v | 779,589 | joypad_snes_adapter_tb.v | v | 68 | 81 | [] | [] | [] | [(25, 66)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/779589/src/io/input/joypad_snes_adapter_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/779589/src/io/input/joypad_snes_adapter_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10 clock = !clock;\n ^\n%Error: data/full_repos/permissive/779589/src/io/input/joypad_snes_adapter_tb.v:40: Cannot find file containing module: \'joypad_snes_adapter\'\n joypad_snes_adapter uut (\n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/779589/src/io/input,data/full_repos/permissive/779589/joypad_snes_adapter\n data/full_repos/permissive/779589/src/io/input,data/full_repos/permissive/779589/joypad_snes_adapter.v\n data/full_repos/permissive/779589/src/io/input,data/full_repos/permissive/779589/joypad_snes_adapter.sv\n joypad_snes_adapter\n joypad_snes_adapter.v\n joypad_snes_adapter.sv\n obj_dir/joypad_snes_adapter\n obj_dir/joypad_snes_adapter.v\n obj_dir/joypad_snes_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,970 | module | module joypad_snes_adapter_tb;
reg clock;
reg reset;
wire [1:0] button_sel;
wire controller_data;
wire [3:0] button_data;
wire controller_latch;
wire controller_clock;
joypad_snes_adapter uut (
.clock(clock),
.reset(reset),
.button_sel(button_sel),
.button_data(button_data),
.controller_data(controller_data),
.controller_latch(controller_latch),
.controller_clock(controller_clock)
);
assign button_sel = 2'b0;
assign controller_data = 1'b0;
initial begin
clock = 0;
reset = 1;
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule | module joypad_snes_adapter_tb; |
reg clock;
reg reset;
wire [1:0] button_sel;
wire controller_data;
wire [3:0] button_data;
wire controller_latch;
wire controller_clock;
joypad_snes_adapter uut (
.clock(clock),
.reset(reset),
.button_sel(button_sel),
.button_data(button_data),
.controller_data(controller_data),
.controller_latch(controller_latch),
.controller_clock(controller_clock)
);
assign button_sel = 2'b0;
assign controller_data = 1'b0;
initial begin
clock = 0;
reset = 1;
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule | 83 |
137,379 | data/full_repos/permissive/779589/src/io/video/vga_controller.v | 779,589 | vga_controller.v | v | 63 | 87 | [] | [] | [] | [(5, 62)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/779589/src/io/video/vga_controller.v:56: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_controller\n assign next_pixel = (pixel_count >= NUM_PIXELS - 1) ? 1\'b0 : pixel_count + 1\'b1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/779589/src/io/video/vga_controller.v:58: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_controller\n ((line_count >= NUM_LINES - 1) ? 1\'b0 : line_count + 1\'b1) : line_count;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 295,971 | module | module vga_controller(pixel_clock, reset, hsync, vsync, pixel_count, line_count);
input pixel_clock;
input reset;
output hsync;
output vsync;
output [9:0] pixel_count;
output [9:0] line_count;
reg hsync, vsync;
reg [9:0] pixel_count, line_count;
wire [9:0] next_pixel, next_line;
parameter NUM_LINES = 525;
parameter NUM_PIXELS = 800;
parameter WIDTH = 640;
parameter HEIGHT = 480;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter V_FRONT_PORCH = 11;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 32;
always @(posedge pixel_clock) begin
if(reset) begin
pixel_count <= 10'b0;
line_count <= 10'b0;
hsync <= 1;
vsync <= 1;
end else begin
pixel_count <= next_pixel;
line_count <= next_line;
hsync <= ~((next_pixel >= WIDTH + H_FRONT_PORCH) &
(next_pixel < WIDTH + H_FRONT_PORCH + H_SYNC));
vsync <= ~((next_line >= HEIGHT + V_FRONT_PORCH) &
(next_line < HEIGHT + V_FRONT_PORCH + V_SYNC));
end
end
assign next_pixel = (pixel_count >= NUM_PIXELS - 1) ? 1'b0 : pixel_count + 1'b1;
assign next_line = (pixel_count >= NUM_PIXELS - 1) ?
((line_count >= NUM_LINES - 1) ? 1'b0 : line_count + 1'b1) : line_count;
endmodule | module vga_controller(pixel_clock, reset, hsync, vsync, pixel_count, line_count); |
input pixel_clock;
input reset;
output hsync;
output vsync;
output [9:0] pixel_count;
output [9:0] line_count;
reg hsync, vsync;
reg [9:0] pixel_count, line_count;
wire [9:0] next_pixel, next_line;
parameter NUM_LINES = 525;
parameter NUM_PIXELS = 800;
parameter WIDTH = 640;
parameter HEIGHT = 480;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter V_FRONT_PORCH = 11;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 32;
always @(posedge pixel_clock) begin
if(reset) begin
pixel_count <= 10'b0;
line_count <= 10'b0;
hsync <= 1;
vsync <= 1;
end else begin
pixel_count <= next_pixel;
line_count <= next_line;
hsync <= ~((next_pixel >= WIDTH + H_FRONT_PORCH) &
(next_pixel < WIDTH + H_FRONT_PORCH + H_SYNC));
vsync <= ~((next_line >= HEIGHT + V_FRONT_PORCH) &
(next_line < HEIGHT + V_FRONT_PORCH + V_SYNC));
end
end
assign next_pixel = (pixel_count >= NUM_PIXELS - 1) ? 1'b0 : pixel_count + 1'b1;
assign next_line = (pixel_count >= NUM_PIXELS - 1) ?
((line_count >= NUM_LINES - 1) ? 1'b0 : line_count + 1'b1) : line_count;
endmodule | 83 |
137,381 | data/full_repos/permissive/779589/src/tv80/env/env_io.v | 779,589 | env_io.v | v | 152 | 79 | [] | [] | [] | null | line:76: before: ";" | null | 1: b"%Error: data/full_repos/permissive/779589/src/tv80/env/env_io.v:76: Can't find definition of scope/variable: 'tb_top'\n 1 : tb_top.test_pass;\n ^~~~~~\n%Error: data/full_repos/permissive/779589/src/tv80/env/env_io.v:78: Can't find definition of scope/variable: 'tb_top'\n 2 : tb_top.test_fail;\n ^~~~~~\n%Error: data/full_repos/permissive/779589/src/tv80/env/env_io.v:80: Can't find definition of scope/variable: 'tb_top'\n 3 : tb_top.dumpon;\n ^~~~~~\n%Error: data/full_repos/permissive/779589/src/tv80/env/env_io.v:82: Can't find definition of scope/variable: 'tb_top'\n 4 : tb_top.dumpoff;\n ^~~~~~\n%Error: data/full_repos/permissive/779589/src/tv80/env/env_io.v:133: Can't find definition of scope/variable: 'tb_top'\n tb_top.test_fail;\n ^~~~~~\n%Error: data/full_repos/permissive/779589/src/tv80/env/env_io.v:141: Can't find definition of scope/variable: 'tb_top'\n tb_top.int_n <= #1 1'b0;\n ^~~~~~\n%Error: data/full_repos/permissive/779589/src/tv80/env/env_io.v:147: Can't find definition of scope/variable: 'tb_top'\n tb_top.int_n <= #1 1'b1;\n ^~~~~~\n%Error: Exiting due to 7 error(s)\n" | 295,973 | module | module env_io (
DI,
clk, iorq_n, rd_n, wr_n, addr, DO
);
input clk;
input iorq_n;
input rd_n;
input wr_n;
input [7:0] addr;
input [7:0] DO;
inout [7:0] DI;
reg [7:0] io_data;
reg [7:0] str_buf [0:255];
reg io_cs;
integer buf_ptr, i;
reg [7:0] timeout_ctl;
reg [15:0] cur_timeout;
reg [15:0] max_timeout;
reg [7:0] int_countdown;
reg [7:0] checksum;
reg [7:0] ior_value;
assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
initial
begin
io_cs = 0;
buf_ptr = 0;
cur_timeout = 0;
max_timeout = 10000;
timeout_ctl = 1;
int_countdown = 0;
end
always @*
begin
if (!iorq_n & !rd_n)
begin
io_cs = (addr[7:5] == 3'b100);
case (addr)
8'h82 : io_data = timeout_ctl;
8'h83 : io_data = max_timeout[7:0];
8'h84 : io_data = max_timeout[15:8];
8'h90 : io_data = int_countdown;
8'h91 : io_data = checksum;
8'h93 : io_data = ior_value;
8'h94 : io_data = {$random};
default : io_data = 8'hzz;
endcase
end
end
wire wr_stb;
reg last_iowrite;
assign wr_stb = (!iorq_n & !wr_n);
always @(posedge clk)
begin
last_iowrite <= #1 wr_stb;
if (!wr_stb & last_iowrite)
case (addr)
8'h80 :
begin
case (DO)
1 : tb_top.test_pass;
2 : tb_top.test_fail;
3 : tb_top.dumpon;
4 : tb_top.dumpoff;
default :
begin
$display ("%t: ERROR : Unknown I/O command %x", $time, DO);
end
endcase
end
8'h81 :
begin
str_buf[buf_ptr] = DO;
buf_ptr = buf_ptr + 1;
if (DO == 8'h0A)
begin
$write ("%t: PROGRAM : ", $time);
for (i=0; i<buf_ptr; i=i+1)
$write ("%s", str_buf[i]);
buf_ptr = 0;
end
end
8'h82 :
begin
timeout_ctl = DO;
end
8'h83 : max_timeout[7:0] = DO;
8'h84 : max_timeout[15:8] = DO;
8'h90 : int_countdown = DO;
8'h91 : checksum = DO;
8'h92 : checksum = checksum + DO;
8'h93 : ior_value = DO;
endcase
end
always @(posedge clk)
begin
if (timeout_ctl[1])
cur_timeout = 0;
else if (timeout_ctl[0])
cur_timeout = cur_timeout + 1;
if (cur_timeout >= max_timeout)
begin
$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);
tb_top.test_fail;
end
end
always @(posedge clk)
begin
if (int_countdown == 1)
begin
tb_top.int_n <= #1 1'b0;
int_countdown = 0;
end
else if (int_countdown > 1)
begin
int_countdown = int_countdown - 1;
tb_top.int_n <= #1 1'b1;
end
end
endmodule | module env_io (
DI,
clk, iorq_n, rd_n, wr_n, addr, DO
); |
input clk;
input iorq_n;
input rd_n;
input wr_n;
input [7:0] addr;
input [7:0] DO;
inout [7:0] DI;
reg [7:0] io_data;
reg [7:0] str_buf [0:255];
reg io_cs;
integer buf_ptr, i;
reg [7:0] timeout_ctl;
reg [15:0] cur_timeout;
reg [15:0] max_timeout;
reg [7:0] int_countdown;
reg [7:0] checksum;
reg [7:0] ior_value;
assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
initial
begin
io_cs = 0;
buf_ptr = 0;
cur_timeout = 0;
max_timeout = 10000;
timeout_ctl = 1;
int_countdown = 0;
end
always @*
begin
if (!iorq_n & !rd_n)
begin
io_cs = (addr[7:5] == 3'b100);
case (addr)
8'h82 : io_data = timeout_ctl;
8'h83 : io_data = max_timeout[7:0];
8'h84 : io_data = max_timeout[15:8];
8'h90 : io_data = int_countdown;
8'h91 : io_data = checksum;
8'h93 : io_data = ior_value;
8'h94 : io_data = {$random};
default : io_data = 8'hzz;
endcase
end
end
wire wr_stb;
reg last_iowrite;
assign wr_stb = (!iorq_n & !wr_n);
always @(posedge clk)
begin
last_iowrite <= #1 wr_stb;
if (!wr_stb & last_iowrite)
case (addr)
8'h80 :
begin
case (DO)
1 : tb_top.test_pass;
2 : tb_top.test_fail;
3 : tb_top.dumpon;
4 : tb_top.dumpoff;
default :
begin
$display ("%t: ERROR : Unknown I/O command %x", $time, DO);
end
endcase
end
8'h81 :
begin
str_buf[buf_ptr] = DO;
buf_ptr = buf_ptr + 1;
if (DO == 8'h0A)
begin
$write ("%t: PROGRAM : ", $time);
for (i=0; i<buf_ptr; i=i+1)
$write ("%s", str_buf[i]);
buf_ptr = 0;
end
end
8'h82 :
begin
timeout_ctl = DO;
end
8'h83 : max_timeout[7:0] = DO;
8'h84 : max_timeout[15:8] = DO;
8'h90 : int_countdown = DO;
8'h91 : checksum = DO;
8'h92 : checksum = checksum + DO;
8'h93 : ior_value = DO;
endcase
end
always @(posedge clk)
begin
if (timeout_ctl[1])
cur_timeout = 0;
else if (timeout_ctl[0])
cur_timeout = cur_timeout + 1;
if (cur_timeout >= max_timeout)
begin
$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);
tb_top.test_fail;
end
end
always @(posedge clk)
begin
if (int_countdown == 1)
begin
tb_top.int_n <= #1 1'b0;
int_countdown = 0;
end
else if (int_countdown > 1)
begin
int_countdown = int_countdown - 1;
tb_top.int_n <= #1 1'b1;
end
end
endmodule | 83 |
137,383 | data/full_repos/permissive/779589/src/tv80/rtl/core/tv80s.v | 779,589 | tv80s.v | v | 184 | 100 | [] | [] | [] | [(25, 182)] | null | null | 1: b"%Error: data/full_repos/permissive/779589/src/tv80/rtl/core/tv80s.v:27: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do,\n ^~\n%Error: data/full_repos/permissive/779589/src/tv80/rtl/core/tv80s.v:54: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n output [7:0] do;\n ^~\n%Error: data/full_repos/permissive/779589/src/tv80/rtl/core/tv80s.v:103: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n .do (do),\n ^~\n%Error: data/full_repos/permissive/779589/src/tv80/rtl/core/tv80s.v:103: syntax error, unexpected '(', expecting ')'\n .do (do),\n ^~\n%Error: Exiting due to 4 error(s)\n" | 295,978 | module | module tv80s (
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do,
BC, DE, HL, ACC, F, PC, SP, IntE_FF1, IntE_FF2, INT_s,
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 3;
parameter T2Write = 1;
parameter IOWait = 1;
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] do;
output [15:0] BC;
output [15:0] DE;
output [15:0] HL;
output [7:0] F;
output [7:0] ACC;
output [15:0] PC;
output [15:0] SP;
output IntE_FF1;
output IntE_FF2;
output INT_s;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.do (do),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n),
.BC (BC),
.DE (DE),
.HL (HL),
.F (F),
.ACC (ACC),
.PC (PC),
.SP (SP),
.IntE_FF1(IntE_FF1),
.IntE_FF2(IntE_FF2),
.INT_s(INT_s)
);
always @(posedge clk)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
di_reg <= #1 0;
end
else
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
if (mcycle[0])
begin
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
begin
rd_n <= #1 ~ intcycle_n;
mreq_n <= #1 ~ intcycle_n;
iorq_n <= #1 intcycle_n;
end
`ifdef TV80_REFRESH
if (tstate[3])
mreq_n <= #1 1'b0;
`endif
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
begin
rd_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
end
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end
end
endmodule | module tv80s (
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do,
BC, DE, HL, ACC, F, PC, SP, IntE_FF1, IntE_FF2, INT_s,
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
); |
parameter Mode = 3;
parameter T2Write = 1;
parameter IOWait = 1;
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] do;
output [15:0] BC;
output [15:0] DE;
output [15:0] HL;
output [7:0] F;
output [7:0] ACC;
output [15:0] PC;
output [15:0] SP;
output IntE_FF1;
output IntE_FF2;
output INT_s;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.do (do),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n),
.BC (BC),
.DE (DE),
.HL (HL),
.F (F),
.ACC (ACC),
.PC (PC),
.SP (SP),
.IntE_FF1(IntE_FF1),
.IntE_FF2(IntE_FF2),
.INT_s(INT_s)
);
always @(posedge clk)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
di_reg <= #1 0;
end
else
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
if (mcycle[0])
begin
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
begin
rd_n <= #1 ~ intcycle_n;
mreq_n <= #1 ~ intcycle_n;
iorq_n <= #1 intcycle_n;
end
`ifdef TV80_REFRESH
if (tstate[3])
mreq_n <= #1 1'b0;
`endif
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
begin
rd_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
end
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end
end
endmodule | 83 |
137,384 | data/full_repos/permissive/779589/src/tv80/rtl/core/tv80_reg.v | 779,589 | tv80_reg.v | v | 80 | 122 | [] | [] | [] | [(25, 78)] | null | data/verilator_xmls/97a7fef8-6b20-4f85-a380-1099c25dd393.xml | null | 295,982 | module | module tv80_reg (
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, BC, DE, HL,
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
output [15:0] BC;
output [15:0] DE;
output [15:0] HL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
assign BC = { RegsH[0], RegsL[0] };
assign DE = { RegsH[1], RegsL[1] };
assign HL = { RegsH[2], RegsL[2] };
endmodule | module tv80_reg (
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, BC, DE, HL,
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
); |
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
output [15:0] BC;
output [15:0] DE;
output [15:0] HL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
assign BC = { RegsH[0], RegsL[0] };
assign DE = { RegsH[1], RegsL[1] };
assign HL = { RegsH[2], RegsL[2] };
endmodule | 83 |
137,386 | data/full_repos/permissive/779589/src/util/debounce.v | 779,589 | debounce.v | v | 27 | 65 | [] | [] | [] | [(1, 26)] | null | null | 1: b"%Error: data/full_repos/permissive/779589/src/util/debounce.v:7: syntax error, unexpected new, expecting IDENTIFIER or '=' or do or final\n reg new, clean;\n ^\n%Error: data/full_repos/permissive/779589/src/util/debounce.v:13: syntax error, unexpected new\n new <= noisy;\n ^~\n%Error: data/full_repos/permissive/779589/src/util/debounce.v:16: syntax error, unexpected new, expecting TYPE-IDENTIFIER\n else if (noisy != new)\n ^\n%Error: Exiting due to 3 error(s)\n" | 295,985 | module | module debounce (reset, clock, noisy, clean);
parameter DELAY = 333333;
input reset, clock, noisy;
output clean;
reg [18:0] count;
reg new, clean;
always @(posedge clock)
if (reset)
begin
count <= 0;
new <= noisy;
clean <= noisy;
end
else if (noisy != new)
begin
new <= noisy;
count <= 0;
end
else if (count == DELAY)
clean <= new;
else
count <= count+1;
endmodule | module debounce (reset, clock, noisy, clean); |
parameter DELAY = 333333;
input reset, clock, noisy;
output clean;
reg [18:0] count;
reg new, clean;
always @(posedge clock)
if (reset)
begin
count <= 0;
new <= noisy;
clean <= noisy;
end
else if (noisy != new)
begin
new <= noisy;
count <= 0;
end
else if (count == DELAY)
clean <= new;
else
count <= count+1;
endmodule | 83 |
137,388 | data/full_repos/permissive/78069562/basic_and.v | 78,069,562 | basic_and.v | v | 30 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/b4bd9c51-957a-4e78-8c0f-533cb0f2c794.xml | null | 295,987 | module | module basic_and#(parameter WIDTH = 1)(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] out
);
assign out = a&b;
endmodule | module basic_and#(parameter WIDTH = 1)(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] out
); |
assign out = a&b;
endmodule | 0 |
137,389 | data/full_repos/permissive/78069562/basic_and_tb.v | 78,069,562 | basic_and_tb.v | v | 49 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78069562/basic_and_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78069562/basic_and_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78069562/basic_and_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/78069562/basic_and_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/78069562/basic_and_tb.v:26: Cannot find file containing module: \'basic_and\'\n basic_and #(.WIDTH(4)) DUT (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/basic_and\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/basic_and.v\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/basic_and.sv\n basic_and\n basic_and.v\n basic_and.sv\n obj_dir/basic_and\n obj_dir/basic_and.v\n obj_dir/basic_and.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,988 | module | module basic_and_tb();
reg [3:0] a,b;
wire [3:0] out;
basic_and #(.WIDTH(4)) DUT (
.a(a),
.b(b),
.out(out)
);
initial begin
a = 4'b0000;
b = 4'b0000;
#20
a = 4'b1111;
b = 4'b0101;
#20
a = 4'b0110;
b = 4'b1100;
#20
a = 4'b1110;
b = 4'b0111;
#20
$finish;
end
endmodule | module basic_and_tb(); |
reg [3:0] a,b;
wire [3:0] out;
basic_and #(.WIDTH(4)) DUT (
.a(a),
.b(b),
.out(out)
);
initial begin
a = 4'b0000;
b = 4'b0000;
#20
a = 4'b1111;
b = 4'b0101;
#20
a = 4'b0110;
b = 4'b1100;
#20
a = 4'b1110;
b = 4'b0111;
#20
$finish;
end
endmodule | 0 |
137,390 | data/full_repos/permissive/78069562/button_conditioner.v | 78,069,562 | button_conditioner.v | v | 52 | 83 | [] | [] | [] | [(21, 51)] | null | null | 1: b"%Error: data/full_repos/permissive/78069562/button_conditioner.v:47: Can't find definition of variable: 'ctr'\n : ... Suggested alternative: 'ctr_d'\n ctr_q <= ctr+d;\n ^~~\n%Error: data/full_repos/permissive/78069562/button_conditioner.v:47: Can't find definition of variable: 'd'\n ctr_q <= ctr+d;\n ^\n%Error: Exiting due to 2 error(s)\n" | 295,990 | module | module button_conditioner(
input clk,
input btn,
output out
);
reg [19:0] ctr_d, ctr_q;
reg [1:0] sync_d, sync_q;
assign out = ctr_q == {20{1'b1}};
always @(*) begin
sync_d[0] = btn;
sync_d[1] = sync_q[0];
ctr_d = ctr_q + 1'b1;
if (ctr_q == {20{1'b1}}) begin
ctr_d = ctr_q;
end
if (!sync_q[1])
ctr_d = 20'd0;
end
always @(posedge clk) begin
ctr_q <= ctr+d;
sync_q <= sync_d;
end
endmodule | module button_conditioner(
input clk,
input btn,
output out
); |
reg [19:0] ctr_d, ctr_q;
reg [1:0] sync_d, sync_q;
assign out = ctr_q == {20{1'b1}};
always @(*) begin
sync_d[0] = btn;
sync_d[1] = sync_q[0];
ctr_d = ctr_q + 1'b1;
if (ctr_q == {20{1'b1}}) begin
ctr_d = ctr_q;
end
if (!sync_q[1])
ctr_d = 20'd0;
end
always @(posedge clk) begin
ctr_q <= ctr+d;
sync_q <= sync_d;
end
endmodule | 0 |
137,391 | data/full_repos/permissive/78069562/counter.v | 78,069,562 | counter.v | v | 47 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/78069562/counter.v:40: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance counter\n ctr_q <= 1\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 295,991 | module | module counter#(parameter CTR_LEN = 27)(
input clk,
input rst,
output reg [7:0] value
);
reg[CTR_LEN-1:0] ctr_d, ctr_q;
always @(ctr_q) begin
ctr_d = ctr_q + 1'b1;
if (ctr_q[CTR_LEN-1])
value = ~ctr_q[CTR_LEN-2:CTR_LEN-9];
else
value = ctr_q[CTR_LEN-2:CTR_LEN-9];
end
always @(posedge clk) begin
if(rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
end
endmodule | module counter#(parameter CTR_LEN = 27)(
input clk,
input rst,
output reg [7:0] value
); |
reg[CTR_LEN-1:0] ctr_d, ctr_q;
always @(ctr_q) begin
ctr_d = ctr_q + 1'b1;
if (ctr_q[CTR_LEN-1])
value = ~ctr_q[CTR_LEN-2:CTR_LEN-9];
else
value = ctr_q[CTR_LEN-2:CTR_LEN-9];
end
always @(posedge clk) begin
if(rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
end
endmodule | 0 |
137,392 | data/full_repos/permissive/78069562/input_capture.v | 78,069,562 | input_capture.v | v | 61 | 83 | [] | [] | [] | [(21, 60)] | null | null | 1: b"%Error: data/full_repos/permissive/78069562/input_capture.v:36: Cannot find file containing module: 'pwm'\n pwm #(.CTR_LEN(10)) ped_pwm( \n ^~~\n ... Looked in:\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/pwm\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/pwm.v\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/pwm.sv\n pwm\n pwm.v\n pwm.sv\n obj_dir/pwm\n obj_dir/pwm.v\n obj_dir/pwm.sv\n%Error: Exiting due to 1 error(s)\n" | 295,992 | module | module input_capture(
input clk,
input rst,
output [3:0] channel,
input new_sample,
input [9:0] sample,
input [3:0] sample_channel,
output [7:0] led
);
assign channel = 4'd0;
reg [9:0] sample_d, sample_q;
wire pwm;
pwm #(.CTR_LEN(10)) ped_pwm(
.clk(clk),
.rst(rst),
.compare(sample_q),
.pwm(pwm)
);
assign led = {8{pwm}};
always @(*) begin
sample_d = sample_q;
if (new_sample && sample_channel == 4'd0)
sample_d = sample;
end
always @(posedge clk) begin
if (rst) begin
sample_q = 10'd0;
end else begin
sample_q = sample_d;
end
end
endmodule | module input_capture(
input clk,
input rst,
output [3:0] channel,
input new_sample,
input [9:0] sample,
input [3:0] sample_channel,
output [7:0] led
); |
assign channel = 4'd0;
reg [9:0] sample_d, sample_q;
wire pwm;
pwm #(.CTR_LEN(10)) ped_pwm(
.clk(clk),
.rst(rst),
.compare(sample_q),
.pwm(pwm)
);
assign led = {8{pwm}};
always @(*) begin
sample_d = sample_q;
if (new_sample && sample_channel == 4'd0)
sample_d = sample;
end
always @(posedge clk) begin
if (rst) begin
sample_q = 10'd0;
end else begin
sample_q = sample_d;
end
end
endmodule | 0 |
137,393 | data/full_repos/permissive/78069562/message_printer.v | 78,069,562 | message_printer.v | v | 79 | 83 | [] | [] | [] | [(21, 78)] | null | null | 1: b"%Error: data/full_repos/permissive/78069562/message_printer.v:39: Cannot find file containing module: 'message_rom'\n message_rom message_rom(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/message_rom\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/message_rom.v\n data/full_repos/permissive/78069562,data/full_repos/permissive/78069562/message_rom.sv\n message_rom\n message_rom.v\n message_rom.sv\n obj_dir/message_rom\n obj_dir/message_rom.v\n obj_dir/message_rom.sv\n%Error: Exiting due to 1 error(s)\n" | 295,994 | module | module message_printer(
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data
);
localparam STATE_SIZE = 1;
localparam IDLE = 0, PRINT_MESSAGE = 1;
localparam MESSAGE_LEN = 14;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [3:0] addr_d, addr_q;
message_rom message_rom(
.clk(clk),
.addr(addr_q),
.data(tx_data)
);
always @(*) begin
state_d = state_q;
addr_d = addr_q;
new_tx_data = 1'b0;
case (state_q)
IDLE: begin
addr_d = 4'b0;
if (new_rx_data && rx_data == "h")
state_d = PRINT_MESSAGE;
end
PRINT_MESSAGE: begin
if(!tx_busy) begin
new_tx_data = 1'b1;
addr_d = addr_q + 1'b1;
if (addr_q == MESSAGE_LEN-1)
state_d = IDLE;
end
end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if(rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
addr_q <= addr_d;
end
endmodule | module message_printer(
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data
); |
localparam STATE_SIZE = 1;
localparam IDLE = 0, PRINT_MESSAGE = 1;
localparam MESSAGE_LEN = 14;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [3:0] addr_d, addr_q;
message_rom message_rom(
.clk(clk),
.addr(addr_q),
.data(tx_data)
);
always @(*) begin
state_d = state_q;
addr_d = addr_q;
new_tx_data = 1'b0;
case (state_q)
IDLE: begin
addr_d = 4'b0;
if (new_rx_data && rx_data == "h")
state_d = PRINT_MESSAGE;
end
PRINT_MESSAGE: begin
if(!tx_busy) begin
new_tx_data = 1'b1;
addr_d = addr_q + 1'b1;
if (addr_q == MESSAGE_LEN-1)
state_d = IDLE;
end
end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if(rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
addr_q <= addr_d;
end
endmodule | 0 |
137,394 | data/full_repos/permissive/78069562/message_rom.v | 78,069,562 | message_rom.v | v | 61 | 83 | [] | [] | [] | [(21, 60)] | null | data/verilator_xmls/af78be36-5aee-4ec5-8d06-67445cd6ccd6.xml | null | 295,995 | module | module message_rom(
input clk,
input [3:0] addr,
output [7:0] data
);
wire [7:0] rom_data [13:0];
assign rom_data[0] = "H";
assign rom_data[1] = "E";
assign rom_data[2] = "L";
assign rom_data[3] = "L";
assign rom_data[4] = "O";
assign rom_data[5] = " ";
assign rom_data[6] = "W";
assign rom_data[7] = "O";
assign rom_data[8] = "R";
assign rom_data[9] = "L";
assign rom_data[10] = "D";
assign rom_data[11] = "!";
assign rom_data[12] = "\n";
assign rom_data[13] = "\r";
reg [7:0] data_d, data_q;
assign data = data_q;
always @(*) begin
if (addr > 4'd13)
data_d = " ";
else
data_d = rom_data[addr];
end
always @(posedge clk) begin
data_q = data_d;
end
endmodule | module message_rom(
input clk,
input [3:0] addr,
output [7:0] data
); |
wire [7:0] rom_data [13:0];
assign rom_data[0] = "H";
assign rom_data[1] = "E";
assign rom_data[2] = "L";
assign rom_data[3] = "L";
assign rom_data[4] = "O";
assign rom_data[5] = " ";
assign rom_data[6] = "W";
assign rom_data[7] = "O";
assign rom_data[8] = "R";
assign rom_data[9] = "L";
assign rom_data[10] = "D";
assign rom_data[11] = "!";
assign rom_data[12] = "\n";
assign rom_data[13] = "\r";
reg [7:0] data_d, data_q;
assign data = data_q;
always @(*) begin
if (addr > 4'd13)
data_d = " ";
else
data_d = rom_data[addr];
end
always @(posedge clk) begin
data_q = data_d;
end
endmodule | 0 |
137,395 | data/full_repos/permissive/78069562/pwm_tb.v | 78,069,562 | pwm_tb.v | v | 53 | 83 | [] | [] | [] | null | line:37: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/78069562/pwm_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n repeat(4) #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/78069562/pwm_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk; \n ^\n%Error: data/full_repos/permissive/78069562/pwm_tb.v:44: syntax error, unexpected \'@\'\n @(negedge rst); \n ^\n%Error: data/full_repos/permissive/78069562/pwm_tb.v:46: syntax error, unexpected \'@\'\n repeat(256) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/78069562/pwm_tb.v:48: syntax error, unexpected \'@\'\n repeat(256) @(posedge clk);\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 295,997 | module | module pwm_tb();
reg clk, rst;
reg [7:0] compare;
wire pwm;
pwm #(.CTR_LEN(8)) DUT(
.clk(clk),
.rst(rst),
.compare(compare),
.pwm(pwm)
);
initial begin
clk = 1'b0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk;
end
initial begin
compare = 8'd0;
@(negedge rst);
compare = 8'd128;
repeat(256) @(posedge clk);
compare = 8'd30;
repeat(256) @(posedge clk);
$finish;
end
endmodule | module pwm_tb(); |
reg clk, rst;
reg [7:0] compare;
wire pwm;
pwm #(.CTR_LEN(8)) DUT(
.clk(clk),
.rst(rst),
.compare(compare),
.pwm(pwm)
);
initial begin
clk = 1'b0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk;
end
initial begin
compare = 8'd0;
@(negedge rst);
compare = 8'd128;
repeat(256) @(posedge clk);
compare = 8'd30;
repeat(256) @(posedge clk);
$finish;
end
endmodule | 0 |
137,396 | data/full_repos/permissive/78069562/servo.v | 78,069,562 | servo.v | v | 54 | 83 | [] | [] | [] | [(21, 53)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/78069562/servo.v:37: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'position\' generates 8 bits.\n : ... In instance servo\n if (position + 8\'d255 > ctr_q[19:8])\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/78069562/servo.v:37: Operator ADD expects 12 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n : ... In instance servo\n if (position + 8\'d255 > ctr_q[19:8])\n ^\n%Warning-WIDTH: data/full_repos/permissive/78069562/servo.v:45: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance servo\n ctr_q <= 1\'b0;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 295,998 | module | module servo(
input clk,
input rst,
input [7:0] position,
output servo
);
reg pwm_d, pwm_q;
reg [19:0] ctr_d, ctr_q;
assign servo = pwm_q;
always @(*) begin
ctr_d = ctr_q + 1'b1;
if (position + 8'd255 > ctr_q[19:8])
pwm_d = 1'b1;
else
pwm_d = 1'b0;
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
pwm_q <= pwm_d;
end
endmodule | module servo(
input clk,
input rst,
input [7:0] position,
output servo
); |
reg pwm_d, pwm_q;
reg [19:0] ctr_d, ctr_q;
assign servo = pwm_q;
always @(*) begin
ctr_d = ctr_q + 1'b1;
if (position + 8'd255 > ctr_q[19:8])
pwm_d = 1'b1;
else
pwm_d = 1'b0;
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
pwm_q <= pwm_d;
end
endmodule | 0 |
137,397 | data/full_repos/permissive/78069562/src/mojo_top.v | 78,069,562 | mojo_top.v | v | 67 | 51 | [] | [] | [] | [(1, 67)] | null | null | 1: b"%Error: data/full_repos/permissive/78069562/src/mojo_top.v:34: Cannot find file containing module: 'avr_interface'\navr_interface avr_interface (\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/78069562/src,data/full_repos/permissive/78069562/avr_interface\n data/full_repos/permissive/78069562/src,data/full_repos/permissive/78069562/avr_interface.v\n data/full_repos/permissive/78069562/src,data/full_repos/permissive/78069562/avr_interface.sv\n avr_interface\n avr_interface.v\n avr_interface.sv\n obj_dir/avr_interface\n obj_dir/avr_interface.v\n obj_dir/avr_interface.sv\n%Error: data/full_repos/permissive/78069562/src/mojo_top.v:57: Cannot find file containing module: 'message_printer'\nmessage_printer helloWorldPrinter (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 296,001 | module | module mojo_top(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy
);
wire rst = ~rst_n;
assign led = 8'b0;
wire [7:0] tx_data;
wire new_tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx),
.rx(avr_tx),
.channel(4'd15),
.new_sample(),
.sample(),
.sample_channel(),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.tx_block(avr_rx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
message_printer helloWorldPrinter (
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
endmodule | module mojo_top(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy
); |
wire rst = ~rst_n;
assign led = 8'b0;
wire [7:0] tx_data;
wire new_tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx),
.rx(avr_tx),
.channel(4'd15),
.new_sample(),
.sample(),
.sample_channel(),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.tx_block(avr_rx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
message_printer helloWorldPrinter (
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
endmodule | 0 |
137,398 | data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c17-abcmap-fmt.v | 78,109,264 | c17-abcmap-fmt.v | v | 15 | 42 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c17-abcmap-fmt.v:7: Cannot find file containing module: 'nand2'\nnand2 gate1( .a(N1), .b(N3), .O(N10) );\n^~~~~\n ... Looked in:\n data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR,data/full_repos/permissive/78109264/nand2\n data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR,data/full_repos/permissive/78109264/nand2.v\n data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR,data/full_repos/permissive/78109264/nand2.sv\n nand2\n nand2.v\n nand2.sv\n obj_dir/nand2\n obj_dir/nand2.v\n obj_dir/nand2.sv\n%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c17-abcmap-fmt.v:8: Cannot find file containing module: 'nand2'\nnand2 gate2( .a(N3), .b(N6), .O(N11) );\n^~~~~\n%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c17-abcmap-fmt.v:9: Cannot find file containing module: 'nand2'\nnand2 gate3( .a(N2), .b(N11), .O(N16) );\n^~~~~\n%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c17-abcmap-fmt.v:10: Cannot find file containing module: 'nand2'\nnand2 gate4( .a(N11), .b(N7), .O(N19) );\n^~~~~\n%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c17-abcmap-fmt.v:11: Cannot find file containing module: 'nand2'\nnand2 gate5( .a(N10), .b(N16), .O(N22) );\n^~~~~\n%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c17-abcmap-fmt.v:12: Cannot find file containing module: 'nand2'\nnand2 gate6( .a(N16), .b(N19), .O(N23) );\n^~~~~\n%Error: Exiting due to 6 error(s)\n" | 296,006 | module | module c17 (N1,N2,N3,N6,N7,N22,N23);
input N1,N2,N3,N6,N7;
output N22,N23;
wire N10,N11,N16,N19;
nand2 gate1( .a(N1), .b(N3), .O(N10) );
nand2 gate2( .a(N3), .b(N6), .O(N11) );
nand2 gate3( .a(N2), .b(N11), .O(N16) );
nand2 gate4( .a(N11), .b(N7), .O(N19) );
nand2 gate5( .a(N10), .b(N16), .O(N22) );
nand2 gate6( .a(N16), .b(N19), .O(N23) );
endmodule | module c17 (N1,N2,N3,N6,N7,N22,N23); |
input N1,N2,N3,N6,N7;
output N22,N23;
wire N10,N11,N16,N19;
nand2 gate1( .a(N1), .b(N3), .O(N10) );
nand2 gate2( .a(N3), .b(N6), .O(N11) );
nand2 gate3( .a(N2), .b(N11), .O(N16) );
nand2 gate4( .a(N11), .b(N7), .O(N19) );
nand2 gate5( .a(N10), .b(N16), .O(N22) );
nand2 gate6( .a(N16), .b(N19), .O(N23) );
endmodule | 8 |
137,401 | data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c2670/c2670-abcmap-fmt-4-randCam1-STD.v | 78,109,264 | c2670-abcmap-fmt-4-randCam1-STD.v | v | 1,481 | 271 | [] | [] | [] | [(1, 1481)] | null | null | 1: b"%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c2670/c2670-abcmap-fmt-4-randCam1-STD.v:65: Input/output/inout does not appear in port list: 's_0'\ninput s_0,s_1; \n ^~~\n%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c2670/c2670-abcmap-fmt-4-randCam1-STD.v:65: Input/output/inout does not appear in port list: 's_1'\ninput s_0,s_1; \n ^~~\n%Error: Exiting due to 2 error(s)\n" | 297,410 | module | module c2670 (N1,N2,N3,N4,N5,N6,N7,N8,N11,N14,
N15,N16,N19,N20,N21,N22,N23,N24,N25,N26,
N27,N28,N29,N32,N33,N34,N35,N36,N37,N40,
N43,N44,N47,N48,N49,N50,N51,N52,N53,N54,
N55,N56,N57,N60,N61,N62,N63,N64,N65,N66,
N67,N68,N69,N72,N73,N74,N75,N76,N77,N78,
N79,N80,N81,N82,N85,N86,N87,N88,N89,N90,
N91,N92,N93,N94,N95,N96,N99,N100,N101,N102,
N103,N104,N105,N106,N107,N108,N111,N112,N113,N114,
N115,N116,N117,N118,N119,N120,N123,N124,N125,N126,
N127,N128,N129,N130,N131,N132,N135,N136,N137,N138,
N139,N140,N141,N142,N219,N224,N227,N230,N231,N234,
N237,N241,N246,N253,N256,N259,N262,N263,N266,N269,
N272,N275,N278,N281,N284,N287,N290,N294,N297,N301,
N305,N309,N313,N316,N319,N322,N325,N328,N331,N334,
N337,N340,N343,N346,N349,N352,N355,N143_I,N144_I,N145_I,
N146_I,N147_I,N148_I,N149_I,N150_I,N151_I,N152_I,N153_I,N154_I,N155_I,
N156_I,N157_I,N158_I,N159_I,N160_I,N161_I,N162_I,N163_I,N164_I,N165_I,
N166_I,N167_I,N168_I,N169_I,N170_I,N171_I,N172_I,N173_I,N174_I,N175_I,
N176_I,N177_I,N178_I,N179_I,N180_I,N181_I,N182_I,N183_I,N184_I,N185_I,
N186_I,N187_I,N188_I,N189_I,N190_I,N191_I,N192_I,N193_I,N194_I,N195_I,
N196_I,N197_I,N198_I,N199_I,N200_I,N201_I,N202_I,N203_I,N204_I,N205_I,
N206_I,N207_I,N208_I,N209_I,N210_I,N211_I,N212_I,N213_I,N214_I,N215_I,
N216_I,N217_I,N218_I,N398,N400,N401,N419,N420,N456,N457,
N458,N487,N488,N489,N490,N491,N492,N493,N494,N792,
N799,N805,N1026,N1028,N1029,N1269,N1277,N1448,N1726,N1816,
N1817,N1818,N1819,N1820,N1821,N1969,N1970,N1971,N2010,N2012,
N2014,N2016,N2018,N2020,N2022,N2387,N2388,N2389,N2390,N2496,
N2643,N2644,N2891,N2925,N2970,N2971,N3038,N3079,N3546,N3671,
N3803,N3804,N3809,N3851,N3875,N3881,N3882,N143_O,N144_O,N145_O,
N146_O,N147_O,N148_O,N149_O,N150_O,N151_O,N152_O,N153_O,N154_O,N155_O,
N156_O,N157_O,N158_O,N159_O,N160_O,N161_O,N162_O,N163_O,N164_O,N165_O,
N166_O,N167_O,N168_O,N169_O,N170_O,N171_O,N172_O,N173_O,N174_O,N175_O,
N176_O,N177_O,N178_O,N179_O,N180_O,N181_O,N182_O,N183_O,N184_O,N185_O,
N186_O,N187_O,N188_O,N189_O,N190_O,N191_O,N192_O,N193_O,N194_O,N195_O,
N196_O,N197_O,N198_O,N199_O,N200_O,N201_O,N202_O,N203_O,N204_O,N205_O,
N206_O,N207_O,N208_O,N209_O,N210_O,N211_O,N212_O,N213_O,N214_O,N215_O,
N216_O,N217_O,N218_O);
input N1,N2,N3,N4,N5,N6,N7,N8,N11,N14,
N15,N16,N19,N20,N21,N22,N23,N24,N25,N26,
N27,N28,N29,N32,N33,N34,N35,N36,N37,N40,
N43,N44,N47,N48,N49,N50,N51,N52,N53,N54,
N55,N56,N57,N60,N61,N62,N63,N64,N65,N66,
N67,N68,N69,N72,N73,N74,N75,N76,N77,N78,
N79,N80,N81,N82,N85,N86,N87,N88,N89,N90,
N91,N92,N93,N94,N95,N96,N99,N100,N101,N102,
N103,N104,N105,N106,N107,N108,N111,N112,N113,N114,
N115,N116,N117,N118,N119,N120,N123,N124,N125,N126,
N127,N128,N129,N130,N131,N132,N135,N136,N137,N138,
N139,N140,N141,N142,N219,N224,N227,N230,N231,N234,
N237,N241,N246,N253,N256,N259,N262,N263,N266,N269,
N272,N275,N278,N281,N284,N287,N290,N294,N297,N301,
N305,N309,N313,N316,N319,N322,N325,N328,N331,N334,
N337,N340,N343,N346,N349,N352,N355,N143_I,N144_I,N145_I,
N146_I,N147_I,N148_I,N149_I,N150_I,N151_I,N152_I,N153_I,N154_I,N155_I,
N156_I,N157_I,N158_I,N159_I,N160_I,N161_I,N162_I,N163_I,N164_I,N165_I,
N166_I,N167_I,N168_I,N169_I,N170_I,N171_I,N172_I,N173_I,N174_I,N175_I,
N176_I,N177_I,N178_I,N179_I,N180_I,N181_I,N182_I,N183_I,N184_I,N185_I,
N186_I,N187_I,N188_I,N189_I,N190_I,N191_I,N192_I,N193_I,N194_I,N195_I,
N196_I,N197_I,N198_I,N199_I,N200_I,N201_I,N202_I,N203_I,N204_I,N205_I,
N206_I,N207_I,N208_I,N209_I,N210_I,N211_I,N212_I,N213_I,N214_I,N215_I,
N216_I,N217_I,N218_I;
input s_0,s_1;
output N398,N400,N401,N419,N420,N456,N457,N458,N487,N488,
N489,N490,N491,N492,N493,N494,N792,N799,N805,N1026,
N1028,N1029,N1269,N1277,N1448,N1726,N1816,N1817,N1818,N1819,
N1820,N1821,N1969,N1970,N1971,N2010,N2012,N2014,N2016,N2018,
N2020,N2022,N2387,N2388,N2389,N2390,N2496,N2643,N2644,N2891,
N2925,N2970,N2971,N3038,N3079,N3546,N3671,N3803,N3804,N3809,
N3851,N3875,N3881,N3882,N143_O,N144_O,N145_O,N146_O,N147_O,N148_O,
N149_O,N150_O,N151_O,N152_O,N153_O,N154_O,N155_O,N156_O,N157_O,N158_O,
N159_O,N160_O,N161_O,N162_O,N163_O,N164_O,N165_O,N166_O,N167_O,N168_O,
N169_O,N170_O,N171_O,N172_O,N173_O,N174_O,N175_O,N176_O,N177_O,N178_O,
N179_O,N180_O,N181_O,N182_O,N183_O,N184_O,N185_O,N186_O,N187_O,N188_O,
N189_O,N190_O,N191_O,N192_O,N193_O,N194_O,N195_O,N196_O,N197_O,N198_O,
N199_O,N200_O,N201_O,N202_O,N203_O,N204_O,N205_O,N206_O,N207_O,N208_O,
N209_O,N210_O,N211_O,N212_O,N213_O,N214_O,N215_O,N216_O,N217_O,N218_O;
wire N405,N408,N425,N485,N486,N495,N496,N499,N500,N503,
N506,N509,N521,N533,N537,N543,N544,N547,N550,N562,
N574,N578,N582,N594,N606,N607,N608,N609,N610,N611,
N612,N613,N625,N637,N643,N650,N651,N655,N659,N663,
N667,N671,N675,N679,N683,N687,N693,N699,N705,N711,
N715,N719,N723,N727,N730,N733,N734,N735,N738,N741,
N744,N747,N750,N753,N756,N759,N762,N765,N768,N771,
N774,N777,N780,N783,N786,N800,N900,N901,N902,N903,
N904,N905,N998,N999,N1027,N1032,N1033,N1034,N1037,N1042,
N1053,N1064,N1065,N1066,N1067,N1068,N1069,N1070,N1075,N1086,
N1097,N1098,N1099,N1100,N1101,N1102,N1113,N1124,N1125,N1126,
N1127,N1128,N1129,N1133,N1137,N1140,N1141,N1142,N1143,N1144,
N1145,N1146,N1157,N1168,N1169,N1170,N1171,N1172,N1173,N1178,
N1184,N1185,N1186,N1187,N1188,N1189,N1190,N1195,N1200,N1205,
N1210,N1211,N1212,N1213,N1214,N1215,N1216,N1219,N1222,N1225,
N1228,N1231,N1234,N1237,N1240,N1243,N1246,N1249,N1250,N1251,
N1254,N1257,N1260,N1263,N1266,N1275,N1276,N1302,N1351,N1352,
N1353,N1354,N1355,N1395,N1396,N1397,N1398,N1399,N1422,N1423,
N1424,N1425,N1426,N1427,N1440,N1441,N1449,N1450,N1451,N1452,
N1453,N1454,N1455,N1456,N1457,N1458,N1459,N1460,N1461,N1462,
N1463,N1464,N1465,N1466,N1467,N1468,N1469,N1470,N1471,N1472,
N1473,N1474,N1475,N1476,N1477,N1478,N1479,N1480,N1481,N1482,
N1483,N1484,N1485,N1486,N1487,N1488,N1489,N1490,N1491,N1492,
N1493,N1494,N1495,N1496,N1499,N1502,N1506,N1510,N1513,N1516,
N1519,N1520,N1521,N1522,N1523,N1524,N1525,N1526,N1527,N1528,
N1529,N1530,N1531,N1532,N1533,N1534,N1535,N1536,N1537,N1538,
N1539,N1540,N1541,N1542,N1543,N1544,N1545,N1546,N1547,N1548,
N1549,N1550,N1551,N1552,N1553,N1557,N1561,N1564,N1565,N1566,
N1567,N1568,N1569,N1570,N1571,N1572,N1573,N1574,N1575,N1576,
N1577,N1578,N1581,N1582,N1585,N1588,N1591,N1596,N1600,N1606,
N1612,N1615,N1619,N1624,N1628,N1631,N1634,N1637,N1642,N1647,
N1651,N1656,N1676,N1681,N1686,N1690,N1708,N1770,N1773,N1776,
N1777,N1778,N1781,N1784,N1785,N1795,N1798,N1801,N1804,N1807,
N1808,N1809,N1810,N1811,N1813,N1814,N1815,N1822,N1823,N1824,
N1827,N1830,N1831,N1832,N1833,N1836,N1841,N1848,N1852,N1856,
N1863,N1870,N1875,N1880,N1885,N1888,N1891,N1894,N1897,N1908,
N1909,N1910,N1911,N1912,N1913,N1914,N1915,N1916,N1917,N1918,
N1919,N1928,N1929,N1930,N1931,N1932,N1933,N1934,N1935,N1936,
N1939,N1940,N1941,N1942,N1945,N1948,N1951,N1954,N1957,N1960,
N1963,N1966,N2028,N2029,N2030,N2031,N2032,N2033,N2034,N2040,
N2041,N2042,N2043,N2046,N2049,N2052,N2055,N2058,N2061,N2064,
N2067,N2070,N2073,N2076,N2079,N2095,N2098,N2101,N2104,N2107,
N2110,N2113,N2119,N2120,N2125,N2126,N2127,N2128,N2135,N2141,
N2144,N2147,N2150,N2153,N2154,N2155,N2156,N2157,N2158,N2171,
N2172,N2173,N2174,N2175,N2176,N2177,N2178,N2185,N2188,N2191,
N2194,N2197,N2200,N2201,N2204,N2207,N2210,N2213,N2216,N2219,
N2234,N2235,N2236,N2237,N2250,N2266,N2269,N2291,N2294,N2297,
N2298,N2300,N2301,N2302,N2303,N2304,N2305,N2306,N2307,N2308,
N2309,N2310,N2311,N2312,N2313,N2314,N2315,N2316,N2317,N2318,
N2319,N2320,N2321,N2322,N2323,N2324,N2325,N2326,N2327,N2328,
N2329,N2330,N2331,N2332,N2333,N2334,N2335,N2336,N2337,N2338,
N2339,N2340,N2354,N2355,N2356,N2357,N2358,N2359,N2364,N2365,
N2366,N2367,N2368,N2372,N2373,N2374,N2375,N2376,N2377,N2382,
N2386,N2391,N2395,N2400,N2403,N2406,N2407,N2408,N2409,N2410,
N2411,N2412,N2413,N2414,N2415,N2416,N2417,N2421,N2425,N2428,
N2429,N2430,N2431,N2432,N2433,N2434,N2437,N2440,N2443,N2446,
N2449,N2452,N2453,N2454,N2457,N2460,N2463,N2466,N2469,N2472,
N2475,N2478,N2481,N2484,N2487,N2490,N2493,N2503,N2504,N2510,
N2511,N2521,N2528,N2531,N2534,N2537,N2540,N2544,N2545,N2546,
N2547,N2548,N2549,N2550,N2551,N2552,N2553,N2563,N2564,N2565,
N2566,N2567,N2568,N2579,N2603,N2607,N2608,N2609,N2610,N2611,
N2612,N2613,N2617,N2618,N2619,N2620,N2621,N2624,N2628,N2629,
N2630,N2631,N2632,N2633,N2634,N2635,N2636,N2638,N2645,N2646,
N2652,N2655,N2656,N2659,N2663,N2664,N2665,N2666,N2667,N2668,
N2669,N2670,N2671,N2672,N2673,N2674,N2675,N2676,N2677,N2678,
N2679,N2680,N2681,N2684,N2687,N2690,N2693,N2694,N2695,N2696,
N2697,N2698,N2699,N2700,N2701,N2702,N2703,N2706,N2707,N2708,
N2709,N2710,N2719,N2720,N2726,N2729,N2738,N2743,N2747,N2748,
N2749,N2750,N2751,N2760,N2761,N2766,N2771,N2772,N2773,N2774,
N2775,N2776,N2777,N2778,N2781,N2782,N2783,N2784,N2789,N2790,
N2791,N2792,N2793,N2796,N2800,N2803,N2806,N2809,N2810,N2811,
N2812,N2817,N2820,N2826,N2829,N2830,N2831,N2837,N2838,N2839,
N2840,N2841,N2844,N2854,N2859,N2869,N2874,N2877,N2880,N2881,
N2882,N2885,N2888,N2894,N2895,N2896,N2897,N2898,N2899,N2900,
N2901,N2914,N2915,N2916,N2917,N2918,N2919,N2920,N2921,N2931,
N2938,N2939,N2963,N2972,N2975,N2978,N2981,N2984,N2985,N2986,
N2989,N2992,N2995,N2998,N3001,N3004,N3007,N3008,N3009,N3010,
N3013,N3016,N3019,N3022,N3025,N3028,N3029,N3030,N3035,N3036,
N3037,N3039,N3044,N3045,N3046,N3047,N3048,N3049,N3050,N3053,
N3054,N3055,N3056,N3057,N3058,N3059,N3060,N3061,N3064,N3065,
N3066,N3067,N3068,N3069,N3070,N3071,N3072,N3073,N3074,N3075,
N3076,N3088,N3091,N3110,N3113,N3137,N3140,N3143,N3146,N3149,
N3152,N3157,N3160,N3163,N3166,N3169,N3172,N3175,N3176,N3177,
N3178,N3180,N3187,N3188,N3189,N3190,N3191,N3192,N3193,N3194,
N3195,N3196,N3197,N3208,N3215,N3216,N3217,N3218,N3219,N3220,
N3222,N3223,N3230,N3231,N3238,N3241,N3244,N3247,N3250,N3253,
N3256,N3259,N3262,N3265,N3268,N3271,N3274,N3277,N3281,N3282,
N3283,N3284,N3286,N3288,N3289,N3291,N3293,N3295,N3296,N3299,
N3301,N3302,N3304,N3306,N3308,N3309,N3312,N3314,N3315,N3318,
N3321,N3324,N3327,N3330,N3333,N3334,N3335,N3336,N3337,N3340,
N3344,N3348,N3352,N3356,N3360,N3364,N3367,N3370,N3374,N3378,
N3382,N3386,N3390,N3394,N3397,N3400,N3401,N3402,N3403,N3404,
N3405,N3406,N3409,N3410,N3412,N3414,N3416,N3418,N3420,N3422,
N3428,N3430,N3432,N3434,N3436,N3438,N3440,N3450,N3453,N3456,
N3459,N3478,N3479,N3480,N3481,N3482,N3483,N3484,N3485,N3486,
N3487,N3488,N3489,N3490,N3491,N3492,N3493,N3494,N3496,N3498,
N3499,N3500,N3501,N3502,N3503,N3504,N3505,N3506,N3507,N3508,
N3509,N3510,N3511,N3512,N3513,N3515,N3517,N3522,N3525,N3528,
N3531,N3534,N3537,N3540,N3543,N3551,N3552,N3553,N3554,N3555,
N3556,N3557,N3558,N3559,N3563,N3564,N3565,N3566,N3567,N3568,
N3569,N3570,N3576,N3579,N3585,N3588,N3592,N3593,N3594,N3595,
N3596,N3597,N3598,N3599,N3600,N3603,N3608,N3612,N3615,N3616,
N3622,N3629,N3630,N3631,N3632,N3633,N3634,N3635,N3640,N3644,
N3647,N3648,N3654,N3661,N3662,N3667,N3668,N3669,N3670,N3691,
N3692,N3693,N3694,N3695,N3696,N3697,N3716,N3717,N3718,N3719,
N3720,N3721,N3722,N3723,N3726,N3727,N3728,N3729,N3730,N3731,
N3732,N3733,N3734,N3735,N3736,N3737,N3740,N3741,N3742,N3743,
N3744,N3745,N3746,N3747,N3748,N3749,N3750,N3753,N3754,N3758,
N3761,N3762,N3767,N3771,N3774,N3775,N3778,N3779,N3780,N3790,
N3793,N3794,N3802,N3805,N3806,N3807,N3808,N3811,N3812,N3813,
N3814,N3815,N3816,N3817,N3818,N3819,N3820,N3821,N3822,N3823,
N3826,N3827,N3834,N3835,N3836,N3837,N3838,N3839,N3840,N3843,
N3852,N3857,N3858,N3859,N3864,N3869,N3870,N3876,N3877, gate1046inter0, gate1046inter1, gate1046inter2, gate1046inter3, gate1046inter4, gate1046inter5, gate1046inter6, gate1046inter7, gate1046inter8, gate1046inter9, gate1046inter10, gate1046inter11, gate1046inter12;
buf1 gate1( .a(N219), .O(N398) );
buf1 gate2( .a(N219), .O(N400) );
buf1 gate3( .a(N219), .O(N401) );
and2 gate4( .a(N1), .b(N3), .O(N405) );
inv1 gate5( .a(N230), .O(N408) );
buf1 gate6( .a(N253), .O(N419) );
buf1 gate7( .a(N253), .O(N420) );
inv1 gate8( .a(N262), .O(N425) );
buf1 gate9( .a(N290), .O(N456) );
buf1 gate10( .a(N290), .O(N457) );
buf1 gate11( .a(N290), .O(N458) );
and4 gate12( .a(N309), .b(N305), .c(N301), .d(N297), .O(N485) );
inv1 gate13( .a(N405), .O(N486) );
inv1 gate14( .a(N44), .O(N487) );
inv1 gate15( .a(N132), .O(N488) );
inv1 gate16( .a(N82), .O(N489) );
inv1 gate17( .a(N96), .O(N490) );
inv1 gate18( .a(N69), .O(N491) );
inv1 gate19( .a(N120), .O(N492) );
inv1 gate20( .a(N57), .O(N493) );
inv1 gate21( .a(N108), .O(N494) );
and3 gate22( .a(N2), .b(N15), .c(N237), .O(N495) );
buf1 gate23( .a(N237), .O(N496) );
and2 gate24( .a(N37), .b(N37), .O(N499) );
buf1 gate25( .a(N219), .O(N500) );
buf1 gate26( .a(N8), .O(N503) );
buf1 gate27( .a(N8), .O(N506) );
buf1 gate28( .a(N227), .O(N509) );
buf1 gate29( .a(N234), .O(N521) );
inv1 gate30( .a(N241), .O(N533) );
inv1 gate31( .a(N246), .O(N537) );
and2 gate32( .a(N11), .b(N246), .O(N543) );
and4 gate33( .a(N132), .b(N82), .c(N96), .d(N44), .O(N544) );
and4 gate34( .a(N120), .b(N57), .c(N108), .d(N69), .O(N547) );
buf1 gate35( .a(N227), .O(N550) );
buf1 gate36( .a(N234), .O(N562) );
inv1 gate37( .a(N256), .O(N574) );
inv1 gate38( .a(N259), .O(N578) );
buf1 gate39( .a(N319), .O(N582) );
buf1 gate40( .a(N322), .O(N594) );
inv1 gate41( .a(N328), .O(N606) );
inv1 gate42( .a(N331), .O(N607) );
inv1 gate43( .a(N334), .O(N608) );
inv1 gate44( .a(N337), .O(N609) );
inv1 gate45( .a(N340), .O(N610) );
inv1 gate46( .a(N343), .O(N611) );
inv1 gate47( .a(N352), .O(N612) );
buf1 gate48( .a(N319), .O(N613) );
buf1 gate49( .a(N322), .O(N625) );
buf1 gate50( .a(N16), .O(N637) );
buf1 gate51( .a(N16), .O(N643) );
inv1 gate52( .a(N355), .O(N650) );
and2 gate53( .a(N7), .b(N237), .O(N651) );
inv1 gate54( .a(N263), .O(N655) );
inv1 gate55( .a(N266), .O(N659) );
inv1 gate56( .a(N269), .O(N663) );
inv1 gate57( .a(N272), .O(N667) );
inv1 gate58( .a(N275), .O(N671) );
inv1 gate59( .a(N278), .O(N675) );
inv1 gate60( .a(N281), .O(N679) );
inv1 gate61( .a(N284), .O(N683) );
inv1 gate62( .a(N287), .O(N687) );
buf1 gate63( .a(N29), .O(N693) );
buf1 gate64( .a(N29), .O(N699) );
inv1 gate65( .a(N294), .O(N705) );
inv1 gate66( .a(N297), .O(N711) );
inv1 gate67( .a(N301), .O(N715) );
inv1 gate68( .a(N305), .O(N719) );
inv1 gate69( .a(N309), .O(N723) );
inv1 gate70( .a(N313), .O(N727) );
inv1 gate71( .a(N316), .O(N730) );
inv1 gate72( .a(N346), .O(N733) );
inv1 gate73( .a(N349), .O(N734) );
buf1 gate74( .a(N259), .O(N735) );
buf1 gate75( .a(N256), .O(N738) );
buf1 gate76( .a(N263), .O(N741) );
buf1 gate77( .a(N269), .O(N744) );
buf1 gate78( .a(N266), .O(N747) );
buf1 gate79( .a(N275), .O(N750) );
buf1 gate80( .a(N272), .O(N753) );
buf1 gate81( .a(N281), .O(N756) );
buf1 gate82( .a(N278), .O(N759) );
buf1 gate83( .a(N287), .O(N762) );
buf1 gate84( .a(N284), .O(N765) );
buf1 gate85( .a(N294), .O(N768) );
buf1 gate86( .a(N301), .O(N771) );
buf1 gate87( .a(N297), .O(N774) );
buf1 gate88( .a(N309), .O(N777) );
buf1 gate89( .a(N305), .O(N780) );
buf1 gate90( .a(N316), .O(N783) );
buf1 gate91( .a(N313), .O(N786) );
inv1 gate92( .a(N485), .O(N792) );
inv1 gate93( .a(N495), .O(N799) );
inv1 gate94( .a(N499), .O(N800) );
buf1 gate95( .a(N500), .O(N805) );
nand2 gate96( .a(N331), .b(N606), .O(N900) );
nand2 gate97( .a(N328), .b(N607), .O(N901) );
nand2 gate98( .a(N337), .b(N608), .O(N902) );
nand2 gate99( .a(N334), .b(N609), .O(N903) );
nand2 gate100( .a(N343), .b(N610), .O(N904) );
nand2 gate101( .a(N340), .b(N611), .O(N905) );
nand2 gate102( .a(N349), .b(N733), .O(N998) );
nand2 gate103( .a(N346), .b(N734), .O(N999) );
and2 gate104( .a(N94), .b(N500), .O(N1026) );
and2 gate105( .a(N325), .b(N651), .O(N1027) );
inv1 gate106( .a(N651), .O(N1028) );
nand2 gate107( .a(N231), .b(N651), .O(N1029) );
inv1 gate108( .a(N544), .O(N1032) );
inv1 gate109( .a(N547), .O(N1033) );
and2 gate110( .a(N547), .b(N544), .O(N1034) );
buf1 gate111( .a(N503), .O(N1037) );
inv1 gate112( .a(N509), .O(N1042) );
inv1 gate113( .a(N521), .O(N1053) );
and3 gate114( .a(N80), .b(N509), .c(N521), .O(N1064) );
and3 gate115( .a(N68), .b(N509), .c(N521), .O(N1065) );
and3 gate116( .a(N79), .b(N509), .c(N521), .O(N1066) );
and3 gate117( .a(N78), .b(N509), .c(N521), .O(N1067) );
and3 gate118( .a(N77), .b(N509), .c(N521), .O(N1068) );
and2 gate119( .a(N11), .b(N537), .O(N1069) );
buf1 gate120( .a(N503), .O(N1070) );
inv1 gate121( .a(N550), .O(N1075) );
inv1 gate122( .a(N562), .O(N1086) );
and3 gate123( .a(N76), .b(N550), .c(N562), .O(N1097) );
and3 gate124( .a(N75), .b(N550), .c(N562), .O(N1098) );
and3 gate125( .a(N74), .b(N550), .c(N562), .O(N1099) );
and3 gate126( .a(N73), .b(N550), .c(N562), .O(N1100) );
and3 gate127( .a(N72), .b(N550), .c(N562), .O(N1101) );
inv1 gate128( .a(N582), .O(N1102) );
inv1 gate129( .a(N594), .O(N1113) );
and3 gate130( .a(N114), .b(N582), .c(N594), .O(N1124) );
and3 gate131( .a(N113), .b(N582), .c(N594), .O(N1125) );
and3 gate132( .a(N112), .b(N582), .c(N594), .O(N1126) );
and3 gate133( .a(N111), .b(N582), .c(N594), .O(N1127) );
and2 gate134( .a(N582), .b(N594), .O(N1128) );
nand2 gate135( .a(N900), .b(N901), .O(N1129) );
nand2 gate136( .a(N902), .b(N903), .O(N1133) );
nand2 gate137( .a(N904), .b(N905), .O(N1137) );
inv1 gate138( .a(N741), .O(N1140) );
nand2 gate139( .a(N741), .b(N612), .O(N1141) );
inv1 gate140( .a(N744), .O(N1142) );
inv1 gate141( .a(N747), .O(N1143) );
inv1 gate142( .a(N750), .O(N1144) );
inv1 gate143( .a(N753), .O(N1145) );
inv1 gate144( .a(N613), .O(N1146) );
inv1 gate145( .a(N625), .O(N1157) );
and3 gate146( .a(N118), .b(N613), .c(N625), .O(N1168) );
and3 gate147( .a(N107), .b(N613), .c(N625), .O(N1169) );
and3 gate148( .a(N117), .b(N613), .c(N625), .O(N1170) );
and3 gate149( .a(N116), .b(N613), .c(N625), .O(N1171) );
and3 gate150( .a(N115), .b(N613), .c(N625), .O(N1172) );
inv1 gate151( .a(N637), .O(N1173) );
inv1 gate152( .a(N643), .O(N1178) );
inv1 gate153( .a(N768), .O(N1184) );
nand2 gate154( .a(N768), .b(N650), .O(N1185) );
inv1 gate155( .a(N771), .O(N1186) );
inv1 gate156( .a(N774), .O(N1187) );
inv1 gate157( .a(N777), .O(N1188) );
inv1 gate158( .a(N780), .O(N1189) );
buf1 gate159( .a(N506), .O(N1190) );
buf1 gate160( .a(N506), .O(N1195) );
inv1 gate161( .a(N693), .O(N1200) );
inv1 gate162( .a(N699), .O(N1205) );
inv1 gate163( .a(N735), .O(N1210) );
inv1 gate164( .a(N738), .O(N1211) );
inv1 gate165( .a(N756), .O(N1212) );
inv1 gate166( .a(N759), .O(N1213) );
inv1 gate167( .a(N762), .O(N1214) );
inv1 gate168( .a(N765), .O(N1215) );
nand2 gate169( .a(N998), .b(N999), .O(N1216) );
buf1 gate170( .a(N574), .O(N1219) );
buf1 gate171( .a(N578), .O(N1222) );
buf1 gate172( .a(N655), .O(N1225) );
buf1 gate173( .a(N659), .O(N1228) );
buf1 gate174( .a(N663), .O(N1231) );
buf1 gate175( .a(N667), .O(N1234) );
buf1 gate176( .a(N671), .O(N1237) );
buf1 gate177( .a(N675), .O(N1240) );
buf1 gate178( .a(N679), .O(N1243) );
buf1 gate179( .a(N683), .O(N1246) );
inv1 gate180( .a(N783), .O(N1249) );
inv1 gate181( .a(N786), .O(N1250) );
buf1 gate182( .a(N687), .O(N1251) );
buf1 gate183( .a(N705), .O(N1254) );
buf1 gate184( .a(N711), .O(N1257) );
buf1 gate185( .a(N715), .O(N1260) );
buf1 gate186( .a(N719), .O(N1263) );
buf1 gate187( .a(N723), .O(N1266) );
inv1 gate188( .a(N1027), .O(N1269) );
and2 gate189( .a(N325), .b(N1032), .O(N1275) );
and2 gate190( .a(N231), .b(N1033), .O(N1276) );
buf1 gate191( .a(N1034), .O(N1277) );
or2 gate192( .a(N1069), .b(N543), .O(N1302) );
nand2 gate193( .a(N352), .b(N1140), .O(N1351) );
nand2 gate194( .a(N747), .b(N1142), .O(N1352) );
nand2 gate195( .a(N744), .b(N1143), .O(N1353) );
nand2 gate196( .a(N753), .b(N1144), .O(N1354) );
nand2 gate197( .a(N750), .b(N1145), .O(N1355) );
nand2 gate198( .a(N355), .b(N1184), .O(N1395) );
nand2 gate199( .a(N774), .b(N1186), .O(N1396) );
nand2 gate200( .a(N771), .b(N1187), .O(N1397) );
nand2 gate201( .a(N780), .b(N1188), .O(N1398) );
nand2 gate202( .a(N777), .b(N1189), .O(N1399) );
nand2 gate203( .a(N738), .b(N1210), .O(N1422) );
nand2 gate204( .a(N735), .b(N1211), .O(N1423) );
nand2 gate205( .a(N759), .b(N1212), .O(N1424) );
nand2 gate206( .a(N756), .b(N1213), .O(N1425) );
nand2 gate207( .a(N765), .b(N1214), .O(N1426) );
nand2 gate208( .a(N762), .b(N1215), .O(N1427) );
nand2 gate209( .a(N786), .b(N1249), .O(N1440) );
nand2 gate210( .a(N783), .b(N1250), .O(N1441) );
inv1 gate211( .a(N1034), .O(N1448) );
inv1 gate212( .a(N1275), .O(N1449) );
inv1 gate213( .a(N1276), .O(N1450) );
and3 gate214( .a(N93), .b(N1042), .c(N1053), .O(N1451) );
and3 gate215( .a(N55), .b(N509), .c(N1053), .O(N1452) );
and3 gate216( .a(N67), .b(N1042), .c(N521), .O(N1453) );
and3 gate217( .a(N81), .b(N1042), .c(N1053), .O(N1454) );
and3 gate218( .a(N43), .b(N509), .c(N1053), .O(N1455) );
and3 gate219( .a(N56), .b(N1042), .c(N521), .O(N1456) );
and3 gate220( .a(N92), .b(N1042), .c(N1053), .O(N1457) );
and3 gate221( .a(N54), .b(N509), .c(N1053), .O(N1458) );
and3 gate222( .a(N66), .b(N1042), .c(N521), .O(N1459) );
and3 gate223( .a(N91), .b(N1042), .c(N1053), .O(N1460) );
and3 gate224( .a(N53), .b(N509), .c(N1053), .O(N1461) );
and3 gate225( .a(N65), .b(N1042), .c(N521), .O(N1462) );
and3 gate226( .a(N90), .b(N1042), .c(N1053), .O(N1463) );
and3 gate227( .a(N52), .b(N509), .c(N1053), .O(N1464) );
and3 gate228( .a(N64), .b(N1042), .c(N521), .O(N1465) );
and3 gate229( .a(N89), .b(N1075), .c(N1086), .O(N1466) );
and3 gate230( .a(N51), .b(N550), .c(N1086), .O(N1467) );
and3 gate231( .a(N63), .b(N1075), .c(N562), .O(N1468) );
and3 gate232( .a(N88), .b(N1075), .c(N1086), .O(N1469) );
and3 gate233( .a(N50), .b(N550), .c(N1086), .O(N1470) );
and3 gate234( .a(N62), .b(N1075), .c(N562), .O(N1471) );
and3 gate235( .a(N87), .b(N1075), .c(N1086), .O(N1472) );
and3 gate236( .a(N49), .b(N550), .c(N1086), .O(N1473) );
and2 gate237( .a(N1075), .b(N562), .O(N1474) );
and3 gate238( .a(N86), .b(N1075), .c(N1086), .O(N1475) );
and3 gate239( .a(N48), .b(N550), .c(N1086), .O(N1476) );
and3 gate240( .a(N61), .b(N1075), .c(N562), .O(N1477) );
and3 gate241( .a(N85), .b(N1075), .c(N1086), .O(N1478) );
and3 gate242( .a(N47), .b(N550), .c(N1086), .O(N1479) );
and3 gate243( .a(N60), .b(N1075), .c(N562), .O(N1480) );
and3 gate244( .a(N138), .b(N1102), .c(N1113), .O(N1481) );
and3 gate245( .a(N102), .b(N582), .c(N1113), .O(N1482) );
and3 gate246( .a(N126), .b(N1102), .c(N594), .O(N1483) );
and3 gate247( .a(N137), .b(N1102), .c(N1113), .O(N1484) );
and3 gate248( .a(N101), .b(N582), .c(N1113), .O(N1485) );
and3 gate249( .a(N125), .b(N1102), .c(N594), .O(N1486) );
and3 gate250( .a(N136), .b(N1102), .c(N1113), .O(N1487) );
and3 gate251( .a(N100), .b(N582), .c(N1113), .O(N1488) );
and3 gate252( .a(N124), .b(N1102), .c(N594), .O(N1489) );
and3 gate253( .a(N135), .b(N1102), .c(N1113), .O(N1490) );
and3 gate254( .a(N99), .b(N582), .c(N1113), .O(N1491) );
and3 gate255( .a(N123), .b(N1102), .c(N594), .O(N1492) );
and2 gate256( .a(N1102), .b(N1113), .O(N1493) );
and2 gate257( .a(N582), .b(N1113), .O(N1494) );
and2 gate258( .a(N1102), .b(N594), .O(N1495) );
inv1 gate259( .a(N1129), .O(N1496) );
inv1 gate260( .a(N1133), .O(N1499) );
nand2 gate261( .a(N1351), .b(N1141), .O(N1502) );
nand2 gate262( .a(N1352), .b(N1353), .O(N1506) );
nand2 gate263( .a(N1354), .b(N1355), .O(N1510) );
buf1 gate264( .a(N1137), .O(N1513) );
buf1 gate265( .a(N1137), .O(N1516) );
inv1 gate266( .a(N1219), .O(N1519) );
inv1 gate267( .a(N1222), .O(N1520) );
inv1 gate268( .a(N1225), .O(N1521) );
inv1 gate269( .a(N1228), .O(N1522) );
inv1 gate270( .a(N1231), .O(N1523) );
inv1 gate271( .a(N1234), .O(N1524) );
inv1 gate272( .a(N1237), .O(N1525) );
inv1 gate273( .a(N1240), .O(N1526) );
inv1 gate274( .a(N1243), .O(N1527) );
inv1 gate275( .a(N1246), .O(N1528) );
and3 gate276( .a(N142), .b(N1146), .c(N1157), .O(N1529) );
and3 gate277( .a(N106), .b(N613), .c(N1157), .O(N1530) );
and3 gate278( .a(N130), .b(N1146), .c(N625), .O(N1531) );
and3 gate279( .a(N131), .b(N1146), .c(N1157), .O(N1532) );
and3 gate280( .a(N95), .b(N613), .c(N1157), .O(N1533) );
and3 gate281( .a(N119), .b(N1146), .c(N625), .O(N1534) );
and3 gate282( .a(N141), .b(N1146), .c(N1157), .O(N1535) );
and3 gate283( .a(N105), .b(N613), .c(N1157), .O(N1536) );
and3 gate284( .a(N129), .b(N1146), .c(N625), .O(N1537) );
and3 gate285( .a(N140), .b(N1146), .c(N1157), .O(N1538) );
and3 gate286( .a(N104), .b(N613), .c(N1157), .O(N1539) );
and3 gate287( .a(N128), .b(N1146), .c(N625), .O(N1540) );
and3 gate288( .a(N139), .b(N1146), .c(N1157), .O(N1541) );
and3 gate289( .a(N103), .b(N613), .c(N1157), .O(N1542) );
and3 gate290( .a(N127), .b(N1146), .c(N625), .O(N1543) );
and2 gate291( .a(N19), .b(N1173), .O(N1544) );
and2 gate292( .a(N4), .b(N1173), .O(N1545) );
and2 gate293( .a(N20), .b(N1173), .O(N1546) );
and2 gate294( .a(N5), .b(N1173), .O(N1547) );
and2 gate295( .a(N21), .b(N1178), .O(N1548) );
and2 gate296( .a(N22), .b(N1178), .O(N1549) );
and2 gate297( .a(N23), .b(N1178), .O(N1550) );
and2 gate298( .a(N6), .b(N1178), .O(N1551) );
and2 gate299( .a(N24), .b(N1178), .O(N1552) );
nand2 gate300( .a(N1395), .b(N1185), .O(N1553) );
nand2 gate301( .a(N1396), .b(N1397), .O(N1557) );
nand2 gate302( .a(N1398), .b(N1399), .O(N1561) );
and2 gate303( .a(N25), .b(N1200), .O(N1564) );
and2 gate304( .a(N32), .b(N1200), .O(N1565) );
and2 gate305( .a(N26), .b(N1200), .O(N1566) );
and2 gate306( .a(N33), .b(N1200), .O(N1567) );
and2 gate307( .a(N27), .b(N1205), .O(N1568) );
and2 gate308( .a(N34), .b(N1205), .O(N1569) );
and2 gate309( .a(N35), .b(N1205), .O(N1570) );
and2 gate310( .a(N28), .b(N1205), .O(N1571) );
inv1 gate311( .a(N1251), .O(N1572) );
inv1 gate312( .a(N1254), .O(N1573) );
inv1 gate313( .a(N1257), .O(N1574) );
inv1 gate314( .a(N1260), .O(N1575) );
inv1 gate315( .a(N1263), .O(N1576) );
inv1 gate316( .a(N1266), .O(N1577) );
nand2 gate317( .a(N1422), .b(N1423), .O(N1578) );
inv1 gate318( .a(N1216), .O(N1581) );
nand2 gate319( .a(N1426), .b(N1427), .O(N1582) );
nand2 gate320( .a(N1424), .b(N1425), .O(N1585) );
nand2 gate321( .a(N1440), .b(N1441), .O(N1588) );
and2 gate322( .a(N1449), .b(N1450), .O(N1591) );
or4 gate323( .a(N1451), .b(N1452), .c(N1453), .d(N1064), .O(N1596) );
or4 gate324( .a(N1454), .b(N1455), .c(N1456), .d(N1065), .O(N1600) );
or4 gate325( .a(N1457), .b(N1458), .c(N1459), .d(N1066), .O(N1606) );
or4 gate326( .a(N1460), .b(N1461), .c(N1462), .d(N1067), .O(N1612) );
or4 gate327( .a(N1463), .b(N1464), .c(N1465), .d(N1068), .O(N1615) );
or4 gate328( .a(N1466), .b(N1467), .c(N1468), .d(N1097), .O(N1619) );
or4 gate329( .a(N1469), .b(N1470), .c(N1471), .d(N1098), .O(N1624) );
or4 gate330( .a(N1472), .b(N1473), .c(N1474), .d(N1099), .O(N1628) );
or4 gate331( .a(N1475), .b(N1476), .c(N1477), .d(N1100), .O(N1631) );
or4 gate332( .a(N1478), .b(N1479), .c(N1480), .d(N1101), .O(N1634) );
or4 gate333( .a(N1481), .b(N1482), .c(N1483), .d(N1124), .O(N1637) );
or4 gate334( .a(N1484), .b(N1485), .c(N1486), .d(N1125), .O(N1642) );
or4 gate335( .a(N1487), .b(N1488), .c(N1489), .d(N1126), .O(N1647) );
or4 gate336( .a(N1490), .b(N1491), .c(N1492), .d(N1127), .O(N1651) );
or4 gate337( .a(N1493), .b(N1494), .c(N1495), .d(N1128), .O(N1656) );
or4 gate338( .a(N1532), .b(N1533), .c(N1534), .d(N1169), .O(N1676) );
or4 gate339( .a(N1535), .b(N1536), .c(N1537), .d(N1170), .O(N1681) );
or4 gate340( .a(N1538), .b(N1539), .c(N1540), .d(N1171), .O(N1686) );
or4 gate341( .a(N1541), .b(N1542), .c(N1543), .d(N1172), .O(N1690) );
or4 gate342( .a(N1529), .b(N1530), .c(N1531), .d(N1168), .O(N1708) );
buf1 gate343( .a(N1591), .O(N1726) );
inv1 gate344( .a(N1502), .O(N1770) );
inv1 gate345( .a(N1506), .O(N1773) );
inv1 gate346( .a(N1513), .O(N1776) );
inv1 gate347( .a(N1516), .O(N1777) );
buf1 gate348( .a(N1510), .O(N1778) );
buf1 gate349( .a(N1510), .O(N1781) );
and3 gate350( .a(N1133), .b(N1129), .c(N1513), .O(N1784) );
and3 gate351( .a(N1499), .b(N1496), .c(N1516), .O(N1785) );
inv1 gate352( .a(N1553), .O(N1795) );
inv1 gate353( .a(N1557), .O(N1798) );
buf1 gate354( .a(N1561), .O(N1801) );
buf1 gate355( .a(N1561), .O(N1804) );
inv1 gate356( .a(N1588), .O(N1807) );
inv1 gate357( .a(N1578), .O(N1808) );
nand2 gate358( .a(N1578), .b(N1581), .O(N1809) );
inv1 gate359( .a(N1582), .O(N1810) );
inv1 gate360( .a(N1585), .O(N1811) );
and2 gate361( .a(N1596), .b(N241), .O(N1813) );
and2 gate362( .a(N1606), .b(N241), .O(N1814) );
and2 gate363( .a(N1600), .b(N241), .O(N1815) );
inv1 gate364( .a(N1642), .O(N1816) );
inv1 gate365( .a(N1647), .O(N1817) );
inv1 gate366( .a(N1637), .O(N1818) );
inv1 gate367( .a(N1624), .O(N1819) );
inv1 gate368( .a(N1619), .O(N1820) );
inv1 gate369( .a(N1615), .O(N1821) );
and4 gate370( .a(N496), .b(N224), .c(N36), .d(N1591), .O(N1822) );
and4 gate371( .a(N496), .b(N224), .c(N1591), .d(N486), .O(N1823) );
buf1 gate372( .a(N1596), .O(N1824) );
inv1 gate373( .a(N1606), .O(N1827) );
and2 gate374( .a(N1600), .b(N537), .O(N1830) );
and2 gate375( .a(N1606), .b(N537), .O(N1831) );
and2 gate376( .a(N1619), .b(N246), .O(N1832) );
inv1 gate377( .a(N1596), .O(N1833) );
inv1 gate378( .a(N1600), .O(N1836) );
inv1 gate379( .a(N1606), .O(N1841) );
buf1 gate380( .a(N1612), .O(N1848) );
buf1 gate381( .a(N1615), .O(N1852) );
buf1 gate382( .a(N1619), .O(N1856) );
buf1 gate383( .a(N1624), .O(N1863) );
buf1 gate384( .a(N1628), .O(N1870) );
buf1 gate385( .a(N1631), .O(N1875) );
buf1 gate386( .a(N1634), .O(N1880) );
nand2 gate387( .a(N727), .b(N1651), .O(N1885) );
nand2 gate388( .a(N730), .b(N1656), .O(N1888) );
buf1 gate389( .a(N1686), .O(N1891) );
and2 gate390( .a(N1637), .b(N425), .O(N1894) );
inv1 gate391( .a(N1642), .O(N1897) );
and3 gate392( .a(N1496), .b(N1133), .c(N1776), .O(N1908) );
and3 gate393( .a(N1129), .b(N1499), .c(N1777), .O(N1909) );
and2 gate394( .a(N1600), .b(N637), .O(N1910) );
and2 gate395( .a(N1606), .b(N637), .O(N1911) );
and2 gate396( .a(N1612), .b(N637), .O(N1912) );
and2 gate397( .a(N1615), .b(N637), .O(N1913) );
and2 gate398( .a(N1619), .b(N643), .O(N1914) );
and2 gate399( .a(N1624), .b(N643), .O(N1915) );
and2 gate400( .a(N1628), .b(N643), .O(N1916) );
and2 gate401( .a(N1631), .b(N643), .O(N1917) );
and2 gate402( .a(N1634), .b(N643), .O(N1918) );
inv1 gate403( .a(N1708), .O(N1919) );
and2 gate404( .a(N1676), .b(N693), .O(N1928) );
and2 gate405( .a(N1681), .b(N693), .O(N1929) );
and2 gate406( .a(N1686), .b(N693), .O(N1930) );
and2 gate407( .a(N1690), .b(N693), .O(N1931) );
and2 gate408( .a(N1637), .b(N699), .O(N1932) );
and2 gate409( .a(N1642), .b(N699), .O(N1933) );
and2 gate410( .a(N1647), .b(N699), .O(N1934) );
and2 gate411( .a(N1651), .b(N699), .O(N1935) );
buf1 gate412( .a(N1600), .O(N1936) );
nand2 gate413( .a(N1216), .b(N1808), .O(N1939) );
nand2 gate414( .a(N1585), .b(N1810), .O(N1940) );
nand2 gate415( .a(N1582), .b(N1811), .O(N1941) );
buf1 gate416( .a(N1676), .O(N1942) );
buf1 gate417( .a(N1686), .O(N1945) );
buf1 gate418( .a(N1681), .O(N1948) );
buf1 gate419( .a(N1637), .O(N1951) );
buf1 gate420( .a(N1690), .O(N1954) );
buf1 gate421( .a(N1647), .O(N1957) );
buf1 gate422( .a(N1642), .O(N1960) );
buf1 gate423( .a(N1656), .O(N1963) );
buf1 gate424( .a(N1651), .O(N1966) );
or2 gate425( .a(N533), .b(N1815), .O(N1969) );
inv1 gate426( .a(N1822), .O(N1970) );
inv1 gate427( .a(N1823), .O(N1971) );
buf1 gate428( .a(N1848), .O(N2010) );
buf1 gate429( .a(N1852), .O(N2012) );
buf1 gate430( .a(N1856), .O(N2014) );
buf1 gate431( .a(N1863), .O(N2016) );
buf1 gate432( .a(N1870), .O(N2018) );
buf1 gate433( .a(N1875), .O(N2020) );
buf1 gate434( .a(N1880), .O(N2022) );
inv1 gate435( .a(N1778), .O(N2028) );
inv1 gate436( .a(N1781), .O(N2029) );
nor2 gate437( .a(N1908), .b(N1784), .O(N2030) );
nor2 gate438( .a(N1909), .b(N1785), .O(N2031) );
and3 gate439( .a(N1506), .b(N1502), .c(N1778), .O(N2032) );
and3 gate440( .a(N1773), .b(N1770), .c(N1781), .O(N2033) );
or2 gate441( .a(N1571), .b(N1935), .O(N2034) );
inv1 gate442( .a(N1801), .O(N2040) );
inv1 gate443( .a(N1804), .O(N2041) );
and3 gate444( .a(N1557), .b(N1553), .c(N1801), .O(N2042) );
and3 gate445( .a(N1798), .b(N1795), .c(N1804), .O(N2043) );
nand2 gate446( .a(N1939), .b(N1809), .O(N2046) );
nand2 gate447( .a(N1940), .b(N1941), .O(N2049) );
or2 gate448( .a(N1544), .b(N1910), .O(N2052) );
or2 gate449( .a(N1545), .b(N1911), .O(N2055) );
or2 gate450( .a(N1546), .b(N1912), .O(N2058) );
or2 gate451( .a(N1547), .b(N1913), .O(N2061) );
or2 gate452( .a(N1548), .b(N1914), .O(N2064) );
or2 gate453( .a(N1549), .b(N1915), .O(N2067) );
or2 gate454( .a(N1550), .b(N1916), .O(N2070) );
or2 gate455( .a(N1551), .b(N1917), .O(N2073) );
or2 gate456( .a(N1552), .b(N1918), .O(N2076) );
or2 gate457( .a(N1564), .b(N1928), .O(N2079) );
or2 gate458( .a(N1565), .b(N1929), .O(N2095) );
or2 gate459( .a(N1566), .b(N1930), .O(N2098) );
or2 gate460( .a(N1567), .b(N1931), .O(N2101) );
or2 gate461( .a(N1568), .b(N1932), .O(N2104) );
or2 gate462( .a(N1569), .b(N1933), .O(N2107) );
or2 gate463( .a(N1570), .b(N1934), .O(N2110) );
and3 gate464( .a(N1897), .b(N1894), .c(N40), .O(N2113) );
inv1 gate465( .a(N1894), .O(N2119) );
nand2 gate466( .a(N408), .b(N1827), .O(N2120) );
and2 gate467( .a(N1824), .b(N537), .O(N2125) );
and2 gate468( .a(N1852), .b(N246), .O(N2126) );
and2 gate469( .a(N1848), .b(N537), .O(N2127) );
inv1 gate470( .a(N1848), .O(N2128) );
inv1 gate471( .a(N1852), .O(N2135) );
inv1 gate472( .a(N1863), .O(N2141) );
inv1 gate473( .a(N1870), .O(N2144) );
inv1 gate474( .a(N1875), .O(N2147) );
inv1 gate475( .a(N1880), .O(N2150) );
and2 gate476( .a(N727), .b(N1885), .O(N2153) );
and2 gate477( .a(N1885), .b(N1651), .O(N2154) );
and2 gate478( .a(N730), .b(N1888), .O(N2155) );
and2 gate479( .a(N1888), .b(N1656), .O(N2156) );
and3 gate480( .a(N1770), .b(N1506), .c(N2028), .O(N2157) );
and3 gate481( .a(N1502), .b(N1773), .c(N2029), .O(N2158) );
inv1 gate482( .a(N1942), .O(N2171) );
nand2 gate483( .a(N1942), .b(N1919), .O(N2172) );
inv1 gate484( .a(N1945), .O(N2173) );
inv1 gate485( .a(N1948), .O(N2174) );
inv1 gate486( .a(N1951), .O(N2175) );
inv1 gate487( .a(N1954), .O(N2176) );
and3 gate488( .a(N1795), .b(N1557), .c(N2040), .O(N2177) );
and3 gate489( .a(N1553), .b(N1798), .c(N2041), .O(N2178) );
buf1 gate490( .a(N1836), .O(N2185) );
buf1 gate491( .a(N1833), .O(N2188) );
buf1 gate492( .a(N1841), .O(N2191) );
inv1 gate493( .a(N1856), .O(N2194) );
inv1 gate494( .a(N1827), .O(N2197) );
inv1 gate495( .a(N1936), .O(N2200) );
buf1 gate496( .a(N1836), .O(N2201) );
buf1 gate497( .a(N1833), .O(N2204) );
buf1 gate498( .a(N1841), .O(N2207) );
buf1 gate499( .a(N1824), .O(N2210) );
buf1 gate500( .a(N1841), .O(N2213) );
buf1 gate501( .a(N1841), .O(N2216) );
nand2 gate502( .a(N2031), .b(N2030), .O(N2219) );
inv1 gate503( .a(N1957), .O(N2234) );
inv1 gate504( .a(N1960), .O(N2235) );
inv1 gate505( .a(N1963), .O(N2236) );
inv1 gate506( .a(N1966), .O(N2237) );
and3 gate507( .a(N40), .b(N1897), .c(N2119), .O(N2250) );
or2 gate508( .a(N1831), .b(N2126), .O(N2266) );
or2 gate509( .a(N2127), .b(N1832), .O(N2269) );
or2 gate510( .a(N2153), .b(N2154), .O(N2291) );
or2 gate511( .a(N2155), .b(N2156), .O(N2294) );
nor2 gate512( .a(N2157), .b(N2032), .O(N2297) );
nor2 gate513( .a(N2158), .b(N2033), .O(N2298) );
inv1 gate514( .a(N2046), .O(N2300) );
inv1 gate515( .a(N2049), .O(N2301) );
nand2 gate516( .a(N2052), .b(N1519), .O(N2302) );
inv1 gate517( .a(N2052), .O(N2303) );
nand2 gate518( .a(N2055), .b(N1520), .O(N2304) );
inv1 gate519( .a(N2055), .O(N2305) );
nand2 gate520( .a(N2058), .b(N1521), .O(N2306) );
inv1 gate521( .a(N2058), .O(N2307) );
nand2 gate522( .a(N2061), .b(N1522), .O(N2308) );
inv1 gate523( .a(N2061), .O(N2309) );
nand2 gate524( .a(N2064), .b(N1523), .O(N2310) );
inv1 gate525( .a(N2064), .O(N2311) );
nand2 gate526( .a(N2067), .b(N1524), .O(N2312) );
inv1 gate527( .a(N2067), .O(N2313) );
nand2 gate528( .a(N2070), .b(N1525), .O(N2314) );
inv1 gate529( .a(N2070), .O(N2315) );
nand2 gate530( .a(N2073), .b(N1526), .O(N2316) );
inv1 gate531( .a(N2073), .O(N2317) );
nand2 gate532( .a(N2076), .b(N1527), .O(N2318) );
inv1 gate533( .a(N2076), .O(N2319) );
nand2 gate534( .a(N2079), .b(N1528), .O(N2320) );
inv1 gate535( .a(N2079), .O(N2321) );
nand2 gate536( .a(N1708), .b(N2171), .O(N2322) );
nand2 gate537( .a(N1948), .b(N2173), .O(N2323) );
nand2 gate538( .a(N1945), .b(N2174), .O(N2324) );
nand2 gate539( .a(N1954), .b(N2175), .O(N2325) );
nand2 gate540( .a(N1951), .b(N2176), .O(N2326) );
nor2 gate541( .a(N2177), .b(N2042), .O(N2327) );
nor2 gate542( .a(N2178), .b(N2043), .O(N2328) );
nand2 gate543( .a(N2095), .b(N1572), .O(N2329) );
inv1 gate544( .a(N2095), .O(N2330) );
nand2 gate545( .a(N2098), .b(N1573), .O(N2331) );
inv1 gate546( .a(N2098), .O(N2332) );
nand2 gate547( .a(N2101), .b(N1574), .O(N2333) );
inv1 gate548( .a(N2101), .O(N2334) );
nand2 gate549( .a(N2104), .b(N1575), .O(N2335) );
inv1 gate550( .a(N2104), .O(N2336) );
nand2 gate551( .a(N2107), .b(N1576), .O(N2337) );
inv1 gate552( .a(N2107), .O(N2338) );
nand2 gate553( .a(N2110), .b(N1577), .O(N2339) );
inv1 gate554( .a(N2110), .O(N2340) );
nand2 gate555( .a(N1960), .b(N2234), .O(N2354) );
nand2 gate556( .a(N1957), .b(N2235), .O(N2355) );
nand2 gate557( .a(N1966), .b(N2236), .O(N2356) );
nand2 gate558( .a(N1963), .b(N2237), .O(N2357) );
and2 gate559( .a(N2120), .b(N533), .O(N2358) );
inv1 gate560( .a(N2113), .O(N2359) );
inv1 gate561( .a(N2185), .O(N2364) );
inv1 gate562( .a(N2188), .O(N2365) );
inv1 gate563( .a(N2191), .O(N2366) );
inv1 gate564( .a(N2194), .O(N2367) );
buf1 gate565( .a(N2120), .O(N2368) );
inv1 gate566( .a(N2201), .O(N2372) );
inv1 gate567( .a(N2204), .O(N2373) );
inv1 gate568( .a(N2207), .O(N2374) );
inv1 gate569( .a(N2210), .O(N2375) );
inv1 gate570( .a(N2213), .O(N2376) );
inv1 gate571( .a(N2113), .O(N2377) );
buf1 gate572( .a(N2113), .O(N2382) );
and2 gate573( .a(N2120), .b(N246), .O(N2386) );
buf1 gate574( .a(N2266), .O(N2387) );
buf1 gate575( .a(N2266), .O(N2388) );
buf1 gate576( .a(N2269), .O(N2389) );
buf1 gate577( .a(N2269), .O(N2390) );
buf1 gate578( .a(N2113), .O(N2391) );
inv1 gate579( .a(N2113), .O(N2395) );
nand2 gate580( .a(N2219), .b(N2300), .O(N2400) );
inv1 gate581( .a(N2216), .O(N2403) );
inv1 gate582( .a(N2219), .O(N2406) );
nand2 gate583( .a(N1219), .b(N2303), .O(N2407) );
nand2 gate584( .a(N1222), .b(N2305), .O(N2408) );
nand2 gate585( .a(N1225), .b(N2307), .O(N2409) );
nand2 gate586( .a(N1228), .b(N2309), .O(N2410) );
nand2 gate587( .a(N1231), .b(N2311), .O(N2411) );
nand2 gate588( .a(N1234), .b(N2313), .O(N2412) );
nand2 gate589( .a(N1237), .b(N2315), .O(N2413) );
nand2 gate590( .a(N1240), .b(N2317), .O(N2414) );
nand2 gate591( .a(N1243), .b(N2319), .O(N2415) );
nand2 gate592( .a(N1246), .b(N2321), .O(N2416) );
nand2 gate593( .a(N2322), .b(N2172), .O(N2417) );
nand2 gate594( .a(N2323), .b(N2324), .O(N2421) );
nand2 gate595( .a(N2325), .b(N2326), .O(N2425) );
nand2 gate596( .a(N1251), .b(N2330), .O(N2428) );
nand2 gate597( .a(N1254), .b(N2332), .O(N2429) );
nand2 gate598( .a(N1257), .b(N2334), .O(N2430) );
nand2 gate599( .a(N1260), .b(N2336), .O(N2431) );
nand2 gate600( .a(N1263), .b(N2338), .O(N2432) );
nand2 gate601( .a(N1266), .b(N2340), .O(N2433) );
buf1 gate602( .a(N2128), .O(N2434) );
buf1 gate603( .a(N2135), .O(N2437) );
buf1 gate604( .a(N2144), .O(N2440) );
buf1 gate605( .a(N2141), .O(N2443) );
buf1 gate606( .a(N2150), .O(N2446) );
buf1 gate607( .a(N2147), .O(N2449) );
inv1 gate608( .a(N2197), .O(N2452) );
nand2 gate609( .a(N2197), .b(N2200), .O(N2453) );
buf1 gate610( .a(N2128), .O(N2454) );
buf1 gate611( .a(N2144), .O(N2457) );
buf1 gate612( .a(N2141), .O(N2460) );
buf1 gate613( .a(N2150), .O(N2463) );
buf1 gate614( .a(N2147), .O(N2466) );
inv1 gate615( .a(N2120), .O(N2469) );
buf1 gate616( .a(N2128), .O(N2472) );
buf1 gate617( .a(N2135), .O(N2475) );
buf1 gate618( .a(N2128), .O(N2478) );
buf1 gate619( .a(N2135), .O(N2481) );
nand2 gate620( .a(N2298), .b(N2297), .O(N2484) );
nand2 gate621( .a(N2356), .b(N2357), .O(N2487) );
nand2 gate622( .a(N2354), .b(N2355), .O(N2490) );
nand2 gate623( .a(N2328), .b(N2327), .O(N2493) );
or2 gate624( .a(N2358), .b(N1814), .O(N2496) );
nand2 gate625( .a(N2188), .b(N2364), .O(N2503) );
nand2 gate626( .a(N2185), .b(N2365), .O(N2504) );
nand2 gate627( .a(N2204), .b(N2372), .O(N2510) );
nand2 gate628( .a(N2201), .b(N2373), .O(N2511) );
or2 gate629( .a(N1830), .b(N2386), .O(N2521) );
nand2 gate630( .a(N2046), .b(N2406), .O(N2528) );
inv1 gate631( .a(N2291), .O(N2531) );
inv1 gate632( .a(N2294), .O(N2534) );
buf1 gate633( .a(N2250), .O(N2537) );
buf1 gate634( .a(N2250), .O(N2540) );
nand2 gate635( .a(N2302), .b(N2407), .O(N2544) );
nand2 gate636( .a(N2304), .b(N2408), .O(N2545) );
nand2 gate637( .a(N2306), .b(N2409), .O(N2546) );
nand2 gate638( .a(N2308), .b(N2410), .O(N2547) );
nand2 gate639( .a(N2310), .b(N2411), .O(N2548) );
nand2 gate640( .a(N2312), .b(N2412), .O(N2549) );
nand2 gate641( .a(N2314), .b(N2413), .O(N2550) );
nand2 gate642( .a(N2316), .b(N2414), .O(N2551) );
nand2 gate643( .a(N2318), .b(N2415), .O(N2552) );
nand2 gate644( .a(N2320), .b(N2416), .O(N2553) );
nand2 gate645( .a(N2329), .b(N2428), .O(N2563) );
nand2 gate646( .a(N2331), .b(N2429), .O(N2564) );
nand2 gate647( .a(N2333), .b(N2430), .O(N2565) );
nand2 gate648( .a(N2335), .b(N2431), .O(N2566) );
nand2 gate649( .a(N2337), .b(N2432), .O(N2567) );
nand2 gate650( .a(N2339), .b(N2433), .O(N2568) );
nand2 gate651( .a(N1936), .b(N2452), .O(N2579) );
buf1 gate652( .a(N2359), .O(N2603) );
and2 gate653( .a(N1880), .b(N2377), .O(N2607) );
and2 gate654( .a(N1676), .b(N2377), .O(N2608) );
and2 gate655( .a(N1681), .b(N2377), .O(N2609) );
and2 gate656( .a(N1891), .b(N2377), .O(N2610) );
and2 gate657( .a(N1856), .b(N2382), .O(N2611) );
and2 gate658( .a(N1863), .b(N2382), .O(N2612) );
nand2 gate659( .a(N2503), .b(N2504), .O(N2613) );
inv1 gate660( .a(N2434), .O(N2617) );
nand2 gate661( .a(N2434), .b(N2366), .O(N2618) );
nand2 gate662( .a(N2437), .b(N2367), .O(N2619) );
inv1 gate663( .a(N2437), .O(N2620) );
inv1 gate664( .a(N2368), .O(N2621) );
nand2 gate665( .a(N2510), .b(N2511), .O(N2624) );
inv1 gate666( .a(N2454), .O(N2628) );
nand2 gate667( .a(N2454), .b(N2374), .O(N2629) );
inv1 gate668( .a(N2472), .O(N2630) );
and2 gate669( .a(N1856), .b(N2391), .O(N2631) );
and2 gate670( .a(N1863), .b(N2391), .O(N2632) );
and2 gate671( .a(N1880), .b(N2395), .O(N2633) );
and2 gate672( .a(N1676), .b(N2395), .O(N2634) );
and2 gate673( .a(N1681), .b(N2395), .O(N2635) );
and2 gate674( .a(N1891), .b(N2395), .O(N2636) );
inv1 gate675( .a(N2382), .O(N2638) );
buf1 gate676( .a(N2521), .O(N2643) );
buf1 gate677( .a(N2521), .O(N2644) );
inv1 gate678( .a(N2475), .O(N2645) );
inv1 gate679( .a(N2391), .O(N2646) );
nand2 gate680( .a(N2528), .b(N2400), .O(N2652) );
inv1 gate681( .a(N2478), .O(N2655) );
inv1 gate682( .a(N2481), .O(N2656) );
buf1 gate683( .a(N2359), .O(N2659) );
inv1 gate684( .a(N2484), .O(N2663) );
nand2 gate685( .a(N2484), .b(N2301), .O(N2664) );
inv1 gate686( .a(N2553), .O(N2665) );
inv1 gate687( .a(N2552), .O(N2666) );
inv1 gate688( .a(N2551), .O(N2667) );
inv1 gate689( .a(N2550), .O(N2668) );
inv1 gate690( .a(N2549), .O(N2669) );
inv1 gate691( .a(N2548), .O(N2670) );
inv1 gate692( .a(N2547), .O(N2671) );
inv1 gate693( .a(N2546), .O(N2672) );
inv1 gate694( .a(N2545), .O(N2673) );
inv1 gate695( .a(N2544), .O(N2674) );
inv1 gate696( .a(N2568), .O(N2675) );
inv1 gate697( .a(N2567), .O(N2676) );
inv1 gate698( .a(N2566), .O(N2677) );
inv1 gate699( .a(N2565), .O(N2678) );
inv1 gate700( .a(N2564), .O(N2679) );
inv1 gate701( .a(N2563), .O(N2680) );
inv1 gate702( .a(N2417), .O(N2681) );
inv1 gate703( .a(N2421), .O(N2684) );
buf1 gate704( .a(N2425), .O(N2687) );
buf1 gate705( .a(N2425), .O(N2690) );
inv1 gate706( .a(N2493), .O(N2693) );
nand2 gate707( .a(N2493), .b(N1807), .O(N2694) );
inv1 gate708( .a(N2440), .O(N2695) );
inv1 gate709( .a(N2443), .O(N2696) );
inv1 gate710( .a(N2446), .O(N2697) );
inv1 gate711( .a(N2449), .O(N2698) );
inv1 gate712( .a(N2457), .O(N2699) );
inv1 gate713( .a(N2460), .O(N2700) );
inv1 gate714( .a(N2463), .O(N2701) );
inv1 gate715( .a(N2466), .O(N2702) );
nand2 gate716( .a(N2579), .b(N2453), .O(N2703) );
inv1 gate717( .a(N2469), .O(N2706) );
inv1 gate718( .a(N2487), .O(N2707) );
inv1 gate719( .a(N2490), .O(N2708) );
and2 gate720( .a(N2294), .b(N2534), .O(N2709) );
and2 gate721( .a(N2291), .b(N2531), .O(N2710) );
nand2 gate722( .a(N2191), .b(N2617), .O(N2719) );
nand2 gate723( .a(N2194), .b(N2620), .O(N2720) );
nand2 gate724( .a(N2207), .b(N2628), .O(N2726) );
buf1 gate725( .a(N2537), .O(N2729) );
buf1 gate726( .a(N2537), .O(N2738) );
inv1 gate727( .a(N2652), .O(N2743) );
nand2 gate728( .a(N2049), .b(N2663), .O(N2747) );
and5 gate729( .a(N2665), .b(N2666), .c(N2667), .d(N2668), .e(N2669), .O(N2748) );
and5 gate730( .a(N2670), .b(N2671), .c(N2672), .d(N2673), .e(N2674), .O(N2749) );
and2 gate731( .a(N2034), .b(N2675), .O(N2750) );
and5 gate732( .a(N2676), .b(N2677), .c(N2678), .d(N2679), .e(N2680), .O(N2751) );
nand2 gate733( .a(N1588), .b(N2693), .O(N2760) );
buf1 gate734( .a(N2540), .O(N2761) );
buf1 gate735( .a(N2540), .O(N2766) );
nand2 gate736( .a(N2443), .b(N2695), .O(N2771) );
nand2 gate737( .a(N2440), .b(N2696), .O(N2772) );
nand2 gate738( .a(N2449), .b(N2697), .O(N2773) );
nand2 gate739( .a(N2446), .b(N2698), .O(N2774) );
nand2 gate740( .a(N2460), .b(N2699), .O(N2775) );
nand2 gate741( .a(N2457), .b(N2700), .O(N2776) );
nand2 gate742( .a(N2466), .b(N2701), .O(N2777) );
nand2 gate743( .a(N2463), .b(N2702), .O(N2778) );
nand2 gate744( .a(N2490), .b(N2707), .O(N2781) );
nand2 gate745( .a(N2487), .b(N2708), .O(N2782) );
or2 gate746( .a(N2709), .b(N2534), .O(N2783) );
or2 gate747( .a(N2710), .b(N2531), .O(N2784) );
and2 gate748( .a(N1856), .b(N2638), .O(N2789) );
and2 gate749( .a(N1863), .b(N2638), .O(N2790) );
and2 gate750( .a(N1870), .b(N2638), .O(N2791) );
and2 gate751( .a(N1875), .b(N2638), .O(N2792) );
inv1 gate752( .a(N2613), .O(N2793) );
nand2 gate753( .a(N2719), .b(N2618), .O(N2796) );
nand2 gate754( .a(N2619), .b(N2720), .O(N2800) );
inv1 gate755( .a(N2624), .O(N2803) );
nand2 gate756( .a(N2726), .b(N2629), .O(N2806) );
and2 gate757( .a(N1856), .b(N2646), .O(N2809) );
and2 gate758( .a(N1863), .b(N2646), .O(N2810) );
and2 gate759( .a(N1870), .b(N2646), .O(N2811) );
and2 gate760( .a(N1875), .b(N2646), .O(N2812) );
and2 gate761( .a(N2743), .b(N14), .O(N2817) );
buf1 gate762( .a(N2603), .O(N2820) );
nand2 gate763( .a(N2747), .b(N2664), .O(N2826) );
and2 gate764( .a(N2748), .b(N2749), .O(N2829) );
and2 gate765( .a(N2750), .b(N2751), .O(N2830) );
buf1 gate766( .a(N2659), .O(N2831) );
inv1 gate767( .a(N2687), .O(N2837) );
inv1 gate768( .a(N2690), .O(N2838) );
and3 gate769( .a(N2421), .b(N2417), .c(N2687), .O(N2839) );
and3 gate770( .a(N2684), .b(N2681), .c(N2690), .O(N2840) );
nand2 gate771( .a(N2760), .b(N2694), .O(N2841) );
buf1 gate772( .a(N2603), .O(N2844) );
buf1 gate773( .a(N2603), .O(N2854) );
buf1 gate774( .a(N2659), .O(N2859) );
buf1 gate775( .a(N2659), .O(N2869) );
nand2 gate776( .a(N2773), .b(N2774), .O(N2874) );
nand2 gate777( .a(N2771), .b(N2772), .O(N2877) );
inv1 gate778( .a(N2703), .O(N2880) );
nand2 gate779( .a(N2703), .b(N2706), .O(N2881) );
nand2 gate780( .a(N2777), .b(N2778), .O(N2882) );
nand2 gate781( .a(N2775), .b(N2776), .O(N2885) );
nand2 gate782( .a(N2781), .b(N2782), .O(N2888) );
nand2 gate783( .a(N2783), .b(N2784), .O(N2891) );
and2 gate784( .a(N2607), .b(N2729), .O(N2894) );
and2 gate785( .a(N2608), .b(N2729), .O(N2895) );
and2 gate786( .a(N2609), .b(N2729), .O(N2896) );
and2 gate787( .a(N2610), .b(N2729), .O(N2897) );
or2 gate788( .a(N2789), .b(N2611), .O(N2898) );
or2 gate789( .a(N2790), .b(N2612), .O(N2899) );
and2 gate790( .a(N2791), .b(N1037), .O(N2900) );
and2 gate791( .a(N2792), .b(N1037), .O(N2901) );
or2 gate792( .a(N2809), .b(N2631), .O(N2914) );
or2 gate793( .a(N2810), .b(N2632), .O(N2915) );
and2 gate794( .a(N2811), .b(N1070), .O(N2916) );
and2 gate795( .a(N2812), .b(N1070), .O(N2917) );
and2 gate796( .a(N2633), .b(N2738), .O(N2918) );
and2 gate797( .a(N2634), .b(N2738), .O(N2919) );
and2 gate798( .a(N2635), .b(N2738), .O(N2920) );
and2 gate799( .a(N2636), .b(N2738), .O(N2921) );
buf1 gate800( .a(N2817), .O(N2925) );
and3 gate801( .a(N2829), .b(N2830), .c(N1302), .O(N2931) );
and3 gate802( .a(N2681), .b(N2421), .c(N2837), .O(N2938) );
and3 gate803( .a(N2417), .b(N2684), .c(N2838), .O(N2939) );
nand2 gate804( .a(N2469), .b(N2880), .O(N2963) );
inv1 gate805( .a(N2841), .O(N2970) );
inv1 gate806( .a(N2826), .O(N2971) );
inv1 gate807( .a(N2894), .O(N2972) );
inv1 gate808( .a(N2895), .O(N2975) );
inv1 gate809( .a(N2896), .O(N2978) );
inv1 gate810( .a(N2897), .O(N2981) );
and2 gate811( .a(N2898), .b(N1037), .O(N2984) );
and2 gate812( .a(N2899), .b(N1037), .O(N2985) );
inv1 gate813( .a(N2900), .O(N2986) );
inv1 gate814( .a(N2901), .O(N2989) );
inv1 gate815( .a(N2796), .O(N2992) );
buf1 gate816( .a(N2800), .O(N2995) );
buf1 gate817( .a(N2800), .O(N2998) );
buf1 gate818( .a(N2806), .O(N3001) );
buf1 gate819( .a(N2806), .O(N3004) );
and2 gate820( .a(N574), .b(N2820), .O(N3007) );
and2 gate821( .a(N2914), .b(N1070), .O(N3008) );
and2 gate822( .a(N2915), .b(N1070), .O(N3009) );
inv1 gate823( .a(N2916), .O(N3010) );
inv1 gate824( .a(N2917), .O(N3013) );
inv1 gate825( .a(N2918), .O(N3016) );
inv1 gate826( .a(N2919), .O(N3019) );
inv1 gate827( .a(N2920), .O(N3022) );
inv1 gate828( .a(N2921), .O(N3025) );
inv1 gate829( .a(N2817), .O(N3028) );
and2 gate830( .a(N574), .b(N2831), .O(N3029) );
inv1 gate831( .a(N2820), .O(N3030) );
and2 gate832( .a(N578), .b(N2820), .O(N3035) );
and2 gate833( .a(N655), .b(N2820), .O(N3036) );
and2 gate834( .a(N659), .b(N2820), .O(N3037) );
buf1 gate835( .a(N2931), .O(N3038) );
inv1 gate836( .a(N2831), .O(N3039) );
and2 gate837( .a(N578), .b(N2831), .O(N3044) );
and2 gate838( .a(N655), .b(N2831), .O(N3045) );
and2 gate839( .a(N659), .b(N2831), .O(N3046) );
nor2 gate840( .a(N2938), .b(N2839), .O(N3047) );
nor2 gate841( .a(N2939), .b(N2840), .O(N3048) );
inv1 gate842( .a(N2888), .O(N3049) );
inv1 gate843( .a(N2844), .O(N3050) );
and2 gate844( .a(N663), .b(N2844), .O(N3053) );
and2 gate845( .a(N667), .b(N2844), .O(N3054) );
and2 gate846( .a(N671), .b(N2844), .O(N3055) );
and2 gate847( .a(N675), .b(N2844), .O(N3056) );
and2 gate848( .a(N679), .b(N2854), .O(N3057) );
and2 gate849( .a(N683), .b(N2854), .O(N3058) );
and2 gate850( .a(N687), .b(N2854), .O(N3059) );
and2 gate851( .a(N705), .b(N2854), .O(N3060) );
inv1 gate852( .a(N2859), .O(N3061) );
and2 gate853( .a(N663), .b(N2859), .O(N3064) );
and2 gate854( .a(N667), .b(N2859), .O(N3065) );
and2 gate855( .a(N671), .b(N2859), .O(N3066) );
and2 gate856( .a(N675), .b(N2859), .O(N3067) );
and2 gate857( .a(N679), .b(N2869), .O(N3068) );
and2 gate858( .a(N683), .b(N2869), .O(N3069) );
and2 gate859( .a(N687), .b(N2869), .O(N3070) );
and2 gate860( .a(N705), .b(N2869), .O(N3071) );
inv1 gate861( .a(N2874), .O(N3072) );
inv1 gate862( .a(N2877), .O(N3073) );
inv1 gate863( .a(N2882), .O(N3074) );
inv1 gate864( .a(N2885), .O(N3075) );
nand2 gate865( .a(N2881), .b(N2963), .O(N3076) );
inv1 gate866( .a(N2931), .O(N3079) );
inv1 gate867( .a(N2984), .O(N3088) );
inv1 gate868( .a(N2985), .O(N3091) );
inv1 gate869( .a(N3008), .O(N3110) );
inv1 gate870( .a(N3009), .O(N3113) );
and2 gate871( .a(N3055), .b(N1190), .O(N3137) );
and2 gate872( .a(N3056), .b(N1190), .O(N3140) );
and2 gate873( .a(N3057), .b(N2761), .O(N3143) );
and2 gate874( .a(N3058), .b(N2761), .O(N3146) );
and2 gate875( .a(N3059), .b(N2761), .O(N3149) );
and2 gate876( .a(N3060), .b(N2761), .O(N3152) );
and2 gate877( .a(N3066), .b(N1195), .O(N3157) );
and2 gate878( .a(N3067), .b(N1195), .O(N3160) );
and2 gate879( .a(N3068), .b(N2766), .O(N3163) );
and2 gate880( .a(N3069), .b(N2766), .O(N3166) );
and2 gate881( .a(N3070), .b(N2766), .O(N3169) );
and2 gate882( .a(N3071), .b(N2766), .O(N3172) );
nand2 gate883( .a(N2877), .b(N3072), .O(N3175) );
nand2 gate884( .a(N2874), .b(N3073), .O(N3176) );
nand2 gate885( .a(N2885), .b(N3074), .O(N3177) );
nand2 gate886( .a(N2882), .b(N3075), .O(N3178) );
nand2 gate887( .a(N3048), .b(N3047), .O(N3180) );
inv1 gate888( .a(N2995), .O(N3187) );
inv1 gate889( .a(N2998), .O(N3188) );
inv1 gate890( .a(N3001), .O(N3189) );
inv1 gate891( .a(N3004), .O(N3190) );
and3 gate892( .a(N2796), .b(N2613), .c(N2995), .O(N3191) );
and3 gate893( .a(N2992), .b(N2793), .c(N2998), .O(N3192) );
and3 gate894( .a(N2624), .b(N2368), .c(N3001), .O(N3193) );
and3 gate895( .a(N2803), .b(N2621), .c(N3004), .O(N3194) );
nand2 gate896( .a(N3076), .b(N2375), .O(N3195) );
inv1 gate897( .a(N3076), .O(N3196) );
and2 gate898( .a(N687), .b(N3030), .O(N3197) );
and2 gate899( .a(N687), .b(N3039), .O(N3208) );
and2 gate900( .a(N705), .b(N3030), .O(N3215) );
and2 gate901( .a(N711), .b(N3030), .O(N3216) );
and2 gate902( .a(N715), .b(N3030), .O(N3217) );
and2 gate903( .a(N705), .b(N3039), .O(N3218) );
and2 gate904( .a(N711), .b(N3039), .O(N3219) );
and2 gate905( .a(N715), .b(N3039), .O(N3220) );
and2 gate906( .a(N719), .b(N3050), .O(N3222) );
and2 gate907( .a(N723), .b(N3050), .O(N3223) );
and2 gate908( .a(N719), .b(N3061), .O(N3230) );
and2 gate909( .a(N723), .b(N3061), .O(N3231) );
nand2 gate910( .a(N3175), .b(N3176), .O(N3238) );
nand2 gate911( .a(N3177), .b(N3178), .O(N3241) );
buf1 gate912( .a(N2981), .O(N3244) );
buf1 gate913( .a(N2978), .O(N3247) );
buf1 gate914( .a(N2975), .O(N3250) );
buf1 gate915( .a(N2972), .O(N3253) );
buf1 gate916( .a(N2989), .O(N3256) );
buf1 gate917( .a(N2986), .O(N3259) );
buf1 gate918( .a(N3025), .O(N3262) );
buf1 gate919( .a(N3022), .O(N3265) );
buf1 gate920( .a(N3019), .O(N3268) );
buf1 gate921( .a(N3016), .O(N3271) );
buf1 gate922( .a(N3013), .O(N3274) );
buf1 gate923( .a(N3010), .O(N3277) );
and3 gate924( .a(N2793), .b(N2796), .c(N3187), .O(N3281) );
and3 gate925( .a(N2613), .b(N2992), .c(N3188), .O(N3282) );
and3 gate926( .a(N2621), .b(N2624), .c(N3189), .O(N3283) );
and3 gate927( .a(N2368), .b(N2803), .c(N3190), .O(N3284) );
nand2 gate928( .a(N2210), .b(N3196), .O(N3286) );
or2 gate929( .a(N3197), .b(N3007), .O(N3288) );
nand2 gate930( .a(N3180), .b(N3049), .O(N3289) );
and2 gate931( .a(N3152), .b(N2981), .O(N3291) );
and2 gate932( .a(N3149), .b(N2978), .O(N3293) );
and2 gate933( .a(N3146), .b(N2975), .O(N3295) );
and2 gate934( .a(N2972), .b(N3143), .O(N3296) );
and2 gate935( .a(N3140), .b(N2989), .O(N3299) );
and2 gate936( .a(N3137), .b(N2986), .O(N3301) );
or2 gate937( .a(N3208), .b(N3029), .O(N3302) );
and2 gate938( .a(N3172), .b(N3025), .O(N3304) );
and2 gate939( .a(N3169), .b(N3022), .O(N3306) );
and2 gate940( .a(N3166), .b(N3019), .O(N3308) );
and2 gate941( .a(N3016), .b(N3163), .O(N3309) );
and2 gate942( .a(N3160), .b(N3013), .O(N3312) );
and2 gate943( .a(N3157), .b(N3010), .O(N3314) );
or2 gate944( .a(N3215), .b(N3035), .O(N3315) );
or2 gate945( .a(N3216), .b(N3036), .O(N3318) );
or2 gate946( .a(N3217), .b(N3037), .O(N3321) );
or2 gate947( .a(N3218), .b(N3044), .O(N3324) );
or2 gate948( .a(N3219), .b(N3045), .O(N3327) );
or2 gate949( .a(N3220), .b(N3046), .O(N3330) );
inv1 gate950( .a(N3180), .O(N3333) );
or2 gate951( .a(N3222), .b(N3053), .O(N3334) );
or2 gate952( .a(N3223), .b(N3054), .O(N3335) );
or2 gate953( .a(N3230), .b(N3064), .O(N3336) );
or2 gate954( .a(N3231), .b(N3065), .O(N3337) );
buf1 gate955( .a(N3152), .O(N3340) );
buf1 gate956( .a(N3149), .O(N3344) );
buf1 gate957( .a(N3146), .O(N3348) );
buf1 gate958( .a(N3143), .O(N3352) );
buf1 gate959( .a(N3140), .O(N3356) );
buf1 gate960( .a(N3137), .O(N3360) );
buf1 gate961( .a(N3091), .O(N3364) );
buf1 gate962( .a(N3088), .O(N3367) );
buf1 gate963( .a(N3172), .O(N3370) );
buf1 gate964( .a(N3169), .O(N3374) );
buf1 gate965( .a(N3166), .O(N3378) );
buf1 gate966( .a(N3163), .O(N3382) );
buf1 gate967( .a(N3160), .O(N3386) );
buf1 gate968( .a(N3157), .O(N3390) );
buf1 gate969( .a(N3113), .O(N3394) );
buf1 gate970( .a(N3110), .O(N3397) );
nand2 gate971( .a(N3195), .b(N3286), .O(N3400) );
nor2 gate972( .a(N3281), .b(N3191), .O(N3401) );
nor2 gate973( .a(N3282), .b(N3192), .O(N3402) );
nor2 gate974( .a(N3283), .b(N3193), .O(N3403) );
nor2 gate975( .a(N3284), .b(N3194), .O(N3404) );
inv1 gate976( .a(N3238), .O(N3405) );
inv1 gate977( .a(N3241), .O(N3406) );
and2 gate978( .a(N3288), .b(N1836), .O(N3409) );
nand2 gate979( .a(N2888), .b(N3333), .O(N3410) );
inv1 gate980( .a(N3244), .O(N3412) );
inv1 gate981( .a(N3247), .O(N3414) );
inv1 gate982( .a(N3250), .O(N3416) );
inv1 gate983( .a(N3253), .O(N3418) );
inv1 gate984( .a(N3256), .O(N3420) );
inv1 gate985( .a(N3259), .O(N3422) );
and2 gate986( .a(N3302), .b(N1836), .O(N3428) );
inv1 gate987( .a(N3262), .O(N3430) );
inv1 gate988( .a(N3265), .O(N3432) );
inv1 gate989( .a(N3268), .O(N3434) );
inv1 gate990( .a(N3271), .O(N3436) );
inv1 gate991( .a(N3274), .O(N3438) );
inv1 gate992( .a(N3277), .O(N3440) );
and2 gate993( .a(N3334), .b(N1190), .O(N3450) );
and2 gate994( .a(N3335), .b(N1190), .O(N3453) );
and2 gate995( .a(N3336), .b(N1195), .O(N3456) );
and2 gate996( .a(N3337), .b(N1195), .O(N3459) );
and2 gate997( .a(N3400), .b(N533), .O(N3478) );
and2 gate998( .a(N3318), .b(N2128), .O(N3479) );
and2 gate999( .a(N3315), .b(N1841), .O(N3480) );
nand2 gate1000( .a(N3410), .b(N3289), .O(N3481) );
inv1 gate1001( .a(N3340), .O(N3482) );
nand2 gate1002( .a(N3340), .b(N3412), .O(N3483) );
inv1 gate1003( .a(N3344), .O(N3484) );
nand2 gate1004( .a(N3344), .b(N3414), .O(N3485) );
inv1 gate1005( .a(N3348), .O(N3486) );
nand2 gate1006( .a(N3348), .b(N3416), .O(N3487) );
inv1 gate1007( .a(N3352), .O(N3488) );
nand2 gate1008( .a(N3352), .b(N3418), .O(N3489) );
inv1 gate1009( .a(N3356), .O(N3490) );
nand2 gate1010( .a(N3356), .b(N3420), .O(N3491) );
inv1 gate1011( .a(N3360), .O(N3492) );
nand2 gate1012( .a(N3360), .b(N3422), .O(N3493) );
inv1 gate1013( .a(N3364), .O(N3494) );
inv1 gate1014( .a(N3367), .O(N3496) );
and2 gate1015( .a(N3321), .b(N2135), .O(N3498) );
and2 gate1016( .a(N3327), .b(N2128), .O(N3499) );
and2 gate1017( .a(N3324), .b(N1841), .O(N3500) );
inv1 gate1018( .a(N3370), .O(N3501) );
nand2 gate1019( .a(N3370), .b(N3430), .O(N3502) );
inv1 gate1020( .a(N3374), .O(N3503) );
nand2 gate1021( .a(N3374), .b(N3432), .O(N3504) );
inv1 gate1022( .a(N3378), .O(N3505) );
nand2 gate1023( .a(N3378), .b(N3434), .O(N3506) );
inv1 gate1024( .a(N3382), .O(N3507) );
nand2 gate1025( .a(N3382), .b(N3436), .O(N3508) );
inv1 gate1026( .a(N3386), .O(N3509) );
nand2 gate1027( .a(N3386), .b(N3438), .O(N3510) );
inv1 gate1028( .a(N3390), .O(N3511) );
nand2 gate1029( .a(N3390), .b(N3440), .O(N3512) );
inv1 gate1030( .a(N3394), .O(N3513) );
inv1 gate1031( .a(N3397), .O(N3515) );
and2 gate1032( .a(N3330), .b(N2135), .O(N3517) );
nand2 gate1033( .a(N3402), .b(N3401), .O(N3522) );
nand2 gate1034( .a(N3404), .b(N3403), .O(N3525) );
buf1 gate1035( .a(N3318), .O(N3528) );
buf1 gate1036( .a(N3315), .O(N3531) );
buf1 gate1037( .a(N3321), .O(N3534) );
buf1 gate1038( .a(N3327), .O(N3537) );
buf1 gate1039( .a(N3324), .O(N3540) );
buf1 gate1040( .a(N3330), .O(N3543) );
or2 gate1041( .a(N3478), .b(N1813), .O(N3546) );
inv1 gate1042( .a(N3481), .O(N3551) );
nand2 gate1043( .a(N3244), .b(N3482), .O(N3552) );
nand2 gate1044( .a(N3247), .b(N3484), .O(N3553) );
nand2 gate1045( .a(N3250), .b(N3486), .O(N3554) );
xor2 gate1270(.a(N3488), .b(N3253), .O(gate1046inter0));
nand2 gate1271(.a(gate1046inter0), .b(s_0), .O(gate1046inter1));
and2 gate1272(.a(N3488), .b(N3253), .O(gate1046inter2));
inv1 gate1273(.a(s_0), .O(gate1046inter3));
inv1 gate1274(.a(s_1), .O(gate1046inter4));
nand2 gate1275(.a(gate1046inter4), .b(gate1046inter3), .O(gate1046inter5));
nor2 gate1276(.a(gate1046inter5), .b(gate1046inter2), .O(gate1046inter6));
inv1 gate1277(.a(N3253), .O(gate1046inter7));
inv1 gate1278(.a(N3488), .O(gate1046inter8));
nand2 gate1279(.a(gate1046inter8), .b(gate1046inter7), .O(gate1046inter9));
nand2 gate1280(.a(s_1), .b(gate1046inter3), .O(gate1046inter10));
nor2 gate1281(.a(gate1046inter10), .b(gate1046inter9), .O(gate1046inter11));
nor2 gate1282(.a(gate1046inter11), .b(gate1046inter6), .O(gate1046inter12));
nand2 gate1283(.a(gate1046inter12), .b(gate1046inter1), .O(N3555));
nand2 gate1047( .a(N3256), .b(N3490), .O(N3556) );
nand2 gate1048( .a(N3259), .b(N3492), .O(N3557) );
and2 gate1049( .a(N3453), .b(N3091), .O(N3558) );
and2 gate1050( .a(N3450), .b(N3088), .O(N3559) );
nand2 gate1051( .a(N3262), .b(N3501), .O(N3563) );
nand2 gate1052( .a(N3265), .b(N3503), .O(N3564) );
nand2 gate1053( .a(N3268), .b(N3505), .O(N3565) );
nand2 gate1054( .a(N3271), .b(N3507), .O(N3566) );
nand2 gate1055( .a(N3274), .b(N3509), .O(N3567) );
nand2 gate1056( .a(N3277), .b(N3511), .O(N3568) );
and2 gate1057( .a(N3459), .b(N3113), .O(N3569) );
and2 gate1058( .a(N3456), .b(N3110), .O(N3570) );
buf1 gate1059( .a(N3453), .O(N3576) );
buf1 gate1060( .a(N3450), .O(N3579) );
buf1 gate1061( .a(N3459), .O(N3585) );
buf1 gate1062( .a(N3456), .O(N3588) );
inv1 gate1063( .a(N3522), .O(N3592) );
nand2 gate1064( .a(N3522), .b(N3405), .O(N3593) );
inv1 gate1065( .a(N3525), .O(N3594) );
nand2 gate1066( .a(N3525), .b(N3406), .O(N3595) );
inv1 gate1067( .a(N3528), .O(N3596) );
nand2 gate1068( .a(N3528), .b(N2630), .O(N3597) );
nand2 gate1069( .a(N3531), .b(N2376), .O(N3598) );
inv1 gate1070( .a(N3531), .O(N3599) );
and2 gate1071( .a(N3551), .b(N800), .O(N3600) );
nand2 gate1072( .a(N3552), .b(N3483), .O(N3603) );
nand2 gate1073( .a(N3553), .b(N3485), .O(N3608) );
nand2 gate1074( .a(N3554), .b(N3487), .O(N3612) );
nand2 gate1075( .a(N3555), .b(N3489), .O(N3615) );
nand2 gate1076( .a(N3556), .b(N3491), .O(N3616) );
nand2 gate1077( .a(N3557), .b(N3493), .O(N3622) );
inv1 gate1078( .a(N3534), .O(N3629) );
nand2 gate1079( .a(N3534), .b(N2645), .O(N3630) );
inv1 gate1080( .a(N3537), .O(N3631) );
nand2 gate1081( .a(N3537), .b(N2655), .O(N3632) );
nand2 gate1082( .a(N3540), .b(N2403), .O(N3633) );
inv1 gate1083( .a(N3540), .O(N3634) );
nand2 gate1084( .a(N3563), .b(N3502), .O(N3635) );
nand2 gate1085( .a(N3564), .b(N3504), .O(N3640) );
nand2 gate1086( .a(N3565), .b(N3506), .O(N3644) );
nand2 gate1087( .a(N3566), .b(N3508), .O(N3647) );
nand2 gate1088( .a(N3567), .b(N3510), .O(N3648) );
nand2 gate1089( .a(N3568), .b(N3512), .O(N3654) );
inv1 gate1090( .a(N3543), .O(N3661) );
nand2 gate1091( .a(N3543), .b(N2656), .O(N3662) );
nand2 gate1092( .a(N3238), .b(N3592), .O(N3667) );
nand2 gate1093( .a(N3241), .b(N3594), .O(N3668) );
nand2 gate1094( .a(N2472), .b(N3596), .O(N3669) );
nand2 gate1095( .a(N2213), .b(N3599), .O(N3670) );
buf1 gate1096( .a(N3600), .O(N3671) );
inv1 gate1097( .a(N3576), .O(N3691) );
nand2 gate1098( .a(N3576), .b(N3494), .O(N3692) );
inv1 gate1099( .a(N3579), .O(N3693) );
nand2 gate1100( .a(N3579), .b(N3496), .O(N3694) );
nand2 gate1101( .a(N2475), .b(N3629), .O(N3695) );
nand2 gate1102( .a(N2478), .b(N3631), .O(N3696) );
nand2 gate1103( .a(N2216), .b(N3634), .O(N3697) );
inv1 gate1104( .a(N3585), .O(N3716) );
nand2 gate1105( .a(N3585), .b(N3513), .O(N3717) );
inv1 gate1106( .a(N3588), .O(N3718) );
nand2 gate1107( .a(N3588), .b(N3515), .O(N3719) );
nand2 gate1108( .a(N2481), .b(N3661), .O(N3720) );
nand2 gate1109( .a(N3667), .b(N3593), .O(N3721) );
nand2 gate1110( .a(N3668), .b(N3595), .O(N3722) );
nand2 gate1111( .a(N3669), .b(N3597), .O(N3723) );
nand2 gate1112( .a(N3670), .b(N3598), .O(N3726) );
inv1 gate1113( .a(N3600), .O(N3727) );
nand2 gate1114( .a(N3364), .b(N3691), .O(N3728) );
nand2 gate1115( .a(N3367), .b(N3693), .O(N3729) );
nand2 gate1116( .a(N3695), .b(N3630), .O(N3730) );
and4 gate1117( .a(N3608), .b(N3615), .c(N3612), .d(N3603), .O(N3731) );
and2 gate1118( .a(N3603), .b(N3293), .O(N3732) );
and3 gate1119( .a(N3608), .b(N3603), .c(N3295), .O(N3733) );
and4 gate1120( .a(N3612), .b(N3603), .c(N3296), .d(N3608), .O(N3734) );
and2 gate1121( .a(N3616), .b(N3301), .O(N3735) );
and3 gate1122( .a(N3622), .b(N3616), .c(N3558), .O(N3736) );
nand2 gate1123( .a(N3696), .b(N3632), .O(N3737) );
nand2 gate1124( .a(N3697), .b(N3633), .O(N3740) );
nand2 gate1125( .a(N3394), .b(N3716), .O(N3741) );
nand2 gate1126( .a(N3397), .b(N3718), .O(N3742) );
nand2 gate1127( .a(N3720), .b(N3662), .O(N3743) );
and4 gate1128( .a(N3640), .b(N3647), .c(N3644), .d(N3635), .O(N3744) );
and2 gate1129( .a(N3635), .b(N3306), .O(N3745) );
and3 gate1130( .a(N3640), .b(N3635), .c(N3308), .O(N3746) );
and4 gate1131( .a(N3644), .b(N3635), .c(N3309), .d(N3640), .O(N3747) );
and2 gate1132( .a(N3648), .b(N3314), .O(N3748) );
and3 gate1133( .a(N3654), .b(N3648), .c(N3569), .O(N3749) );
inv1 gate1134( .a(N3721), .O(N3750) );
and2 gate1135( .a(N3722), .b(N246), .O(N3753) );
nand2 gate1136( .a(N3728), .b(N3692), .O(N3754) );
nand2 gate1137( .a(N3729), .b(N3694), .O(N3758) );
inv1 gate1138( .a(N3731), .O(N3761) );
or4 gate1139( .a(N3291), .b(N3732), .c(N3733), .d(N3734), .O(N3762) );
nand2 gate1140( .a(N3741), .b(N3717), .O(N3767) );
nand2 gate1141( .a(N3742), .b(N3719), .O(N3771) );
inv1 gate1142( .a(N3744), .O(N3774) );
or4 gate1143( .a(N3304), .b(N3745), .c(N3746), .d(N3747), .O(N3775) );
and2 gate1144( .a(N3723), .b(N3480), .O(N3778) );
and3 gate1145( .a(N3726), .b(N3723), .c(N3409), .O(N3779) );
or2 gate1146( .a(N2125), .b(N3753), .O(N3780) );
and2 gate1147( .a(N3750), .b(N800), .O(N3790) );
and2 gate1148( .a(N3737), .b(N3500), .O(N3793) );
and3 gate1149( .a(N3740), .b(N3737), .c(N3428), .O(N3794) );
or3 gate1150( .a(N3479), .b(N3778), .c(N3779), .O(N3802) );
buf1 gate1151( .a(N3780), .O(N3803) );
buf1 gate1152( .a(N3780), .O(N3804) );
inv1 gate1153( .a(N3762), .O(N3805) );
and5 gate1154( .a(N3622), .b(N3730), .c(N3754), .d(N3616), .e(N3758), .O(N3806) );
and4 gate1155( .a(N3754), .b(N3616), .c(N3559), .d(N3622), .O(N3807) );
and5 gate1156( .a(N3758), .b(N3754), .c(N3616), .d(N3498), .e(N3622), .O(N3808) );
buf1 gate1157( .a(N3790), .O(N3809) );
or3 gate1158( .a(N3499), .b(N3793), .c(N3794), .O(N3811) );
inv1 gate1159( .a(N3775), .O(N3812) );
and5 gate1160( .a(N3654), .b(N3743), .c(N3767), .d(N3648), .e(N3771), .O(N3813) );
and4 gate1161( .a(N3767), .b(N3648), .c(N3570), .d(N3654), .O(N3814) );
and5 gate1162( .a(N3771), .b(N3767), .c(N3648), .d(N3517), .e(N3654), .O(N3815) );
or5 gate1163( .a(N3299), .b(N3735), .c(N3736), .d(N3807), .e(N3808), .O(N3816) );
and2 gate1164( .a(N3806), .b(N3802), .O(N3817) );
nand2 gate1165( .a(N3805), .b(N3761), .O(N3818) );
inv1 gate1166( .a(N3790), .O(N3819) );
or5 gate1167( .a(N3312), .b(N3748), .c(N3749), .d(N3814), .e(N3815), .O(N3820) );
and2 gate1168( .a(N3813), .b(N3811), .O(N3821) );
nand2 gate1169( .a(N3812), .b(N3774), .O(N3822) );
or2 gate1170( .a(N3816), .b(N3817), .O(N3823) );
and3 gate1171( .a(N3727), .b(N3819), .c(N2841), .O(N3826) );
or2 gate1172( .a(N3820), .b(N3821), .O(N3827) );
inv1 gate1173( .a(N3823), .O(N3834) );
and2 gate1174( .a(N3818), .b(N3823), .O(N3835) );
inv1 gate1175( .a(N3827), .O(N3836) );
and2 gate1176( .a(N3822), .b(N3827), .O(N3837) );
and2 gate1177( .a(N3762), .b(N3834), .O(N3838) );
and2 gate1178( .a(N3775), .b(N3836), .O(N3839) );
or2 gate1179( .a(N3838), .b(N3835), .O(N3840) );
or2 gate1180( .a(N3839), .b(N3837), .O(N3843) );
buf1 gate1181( .a(N3843), .O(N3851) );
nand2 gate1182( .a(N3843), .b(N3840), .O(N3852) );
and2 gate1183( .a(N3843), .b(N3852), .O(N3857) );
and2 gate1184( .a(N3852), .b(N3840), .O(N3858) );
or2 gate1185( .a(N3857), .b(N3858), .O(N3859) );
inv1 gate1186( .a(N3859), .O(N3864) );
and2 gate1187( .a(N3859), .b(N3864), .O(N3869) );
or2 gate1188( .a(N3869), .b(N3864), .O(N3870) );
inv1 gate1189( .a(N3870), .O(N3875) );
and3 gate1190( .a(N2826), .b(N3028), .c(N3870), .O(N3876) );
and3 gate1191( .a(N3826), .b(N3876), .c(N1591), .O(N3877) );
buf1 gate1192( .a(N3877), .O(N3881) );
inv1 gate1193( .a(N3877), .O(N3882) );
buf1 gate1194( .a(N143_I), .O(N143_O) );
buf1 gate1195( .a(N144_I), .O(N144_O) );
buf1 gate1196( .a(N145_I), .O(N145_O) );
buf1 gate1197( .a(N146_I), .O(N146_O) );
buf1 gate1198( .a(N147_I), .O(N147_O) );
buf1 gate1199( .a(N148_I), .O(N148_O) );
buf1 gate1200( .a(N149_I), .O(N149_O) );
buf1 gate1201( .a(N150_I), .O(N150_O) );
buf1 gate1202( .a(N151_I), .O(N151_O) );
buf1 gate1203( .a(N152_I), .O(N152_O) );
buf1 gate1204( .a(N153_I), .O(N153_O) );
buf1 gate1205( .a(N154_I), .O(N154_O) );
buf1 gate1206( .a(N155_I), .O(N155_O) );
buf1 gate1207( .a(N156_I), .O(N156_O) );
buf1 gate1208( .a(N157_I), .O(N157_O) );
buf1 gate1209( .a(N158_I), .O(N158_O) );
buf1 gate1210( .a(N159_I), .O(N159_O) );
buf1 gate1211( .a(N160_I), .O(N160_O) );
buf1 gate1212( .a(N161_I), .O(N161_O) );
buf1 gate1213( .a(N162_I), .O(N162_O) );
buf1 gate1214( .a(N163_I), .O(N163_O) );
buf1 gate1215( .a(N164_I), .O(N164_O) );
buf1 gate1216( .a(N165_I), .O(N165_O) );
buf1 gate1217( .a(N166_I), .O(N166_O) );
buf1 gate1218( .a(N167_I), .O(N167_O) );
buf1 gate1219( .a(N168_I), .O(N168_O) );
buf1 gate1220( .a(N169_I), .O(N169_O) );
buf1 gate1221( .a(N170_I), .O(N170_O) );
buf1 gate1222( .a(N171_I), .O(N171_O) );
buf1 gate1223( .a(N172_I), .O(N172_O) );
buf1 gate1224( .a(N173_I), .O(N173_O) );
buf1 gate1225( .a(N174_I), .O(N174_O) );
buf1 gate1226( .a(N175_I), .O(N175_O) );
buf1 gate1227( .a(N176_I), .O(N176_O) );
buf1 gate1228( .a(N177_I), .O(N177_O) );
buf1 gate1229( .a(N178_I), .O(N178_O) );
buf1 gate1230( .a(N179_I), .O(N179_O) );
buf1 gate1231( .a(N180_I), .O(N180_O) );
buf1 gate1232( .a(N181_I), .O(N181_O) );
buf1 gate1233( .a(N182_I), .O(N182_O) );
buf1 gate1234( .a(N183_I), .O(N183_O) );
buf1 gate1235( .a(N184_I), .O(N184_O) );
buf1 gate1236( .a(N185_I), .O(N185_O) );
buf1 gate1237( .a(N186_I), .O(N186_O) );
buf1 gate1238( .a(N187_I), .O(N187_O) );
buf1 gate1239( .a(N188_I), .O(N188_O) );
buf1 gate1240( .a(N189_I), .O(N189_O) );
buf1 gate1241( .a(N190_I), .O(N190_O) );
buf1 gate1242( .a(N191_I), .O(N191_O) );
buf1 gate1243( .a(N192_I), .O(N192_O) );
buf1 gate1244( .a(N193_I), .O(N193_O) );
buf1 gate1245( .a(N194_I), .O(N194_O) );
buf1 gate1246( .a(N195_I), .O(N195_O) );
buf1 gate1247( .a(N196_I), .O(N196_O) );
buf1 gate1248( .a(N197_I), .O(N197_O) );
buf1 gate1249( .a(N198_I), .O(N198_O) );
buf1 gate1250( .a(N199_I), .O(N199_O) );
buf1 gate1251( .a(N200_I), .O(N200_O) );
buf1 gate1252( .a(N201_I), .O(N201_O) );
buf1 gate1253( .a(N202_I), .O(N202_O) );
buf1 gate1254( .a(N203_I), .O(N203_O) );
buf1 gate1255( .a(N204_I), .O(N204_O) );
buf1 gate1256( .a(N205_I), .O(N205_O) );
buf1 gate1257( .a(N206_I), .O(N206_O) );
buf1 gate1258( .a(N207_I), .O(N207_O) );
buf1 gate1259( .a(N208_I), .O(N208_O) );
buf1 gate1260( .a(N209_I), .O(N209_O) );
buf1 gate1261( .a(N210_I), .O(N210_O) );
buf1 gate1262( .a(N211_I), .O(N211_O) );
buf1 gate1263( .a(N212_I), .O(N212_O) );
buf1 gate1264( .a(N213_I), .O(N213_O) );
buf1 gate1265( .a(N214_I), .O(N214_O) );
buf1 gate1266( .a(N215_I), .O(N215_O) );
buf1 gate1267( .a(N216_I), .O(N216_O) );
buf1 gate1268( .a(N217_I), .O(N217_O) );
buf1 gate1269( .a(N218_I), .O(N218_O) );
endmodule | module c2670 (N1,N2,N3,N4,N5,N6,N7,N8,N11,N14,
N15,N16,N19,N20,N21,N22,N23,N24,N25,N26,
N27,N28,N29,N32,N33,N34,N35,N36,N37,N40,
N43,N44,N47,N48,N49,N50,N51,N52,N53,N54,
N55,N56,N57,N60,N61,N62,N63,N64,N65,N66,
N67,N68,N69,N72,N73,N74,N75,N76,N77,N78,
N79,N80,N81,N82,N85,N86,N87,N88,N89,N90,
N91,N92,N93,N94,N95,N96,N99,N100,N101,N102,
N103,N104,N105,N106,N107,N108,N111,N112,N113,N114,
N115,N116,N117,N118,N119,N120,N123,N124,N125,N126,
N127,N128,N129,N130,N131,N132,N135,N136,N137,N138,
N139,N140,N141,N142,N219,N224,N227,N230,N231,N234,
N237,N241,N246,N253,N256,N259,N262,N263,N266,N269,
N272,N275,N278,N281,N284,N287,N290,N294,N297,N301,
N305,N309,N313,N316,N319,N322,N325,N328,N331,N334,
N337,N340,N343,N346,N349,N352,N355,N143_I,N144_I,N145_I,
N146_I,N147_I,N148_I,N149_I,N150_I,N151_I,N152_I,N153_I,N154_I,N155_I,
N156_I,N157_I,N158_I,N159_I,N160_I,N161_I,N162_I,N163_I,N164_I,N165_I,
N166_I,N167_I,N168_I,N169_I,N170_I,N171_I,N172_I,N173_I,N174_I,N175_I,
N176_I,N177_I,N178_I,N179_I,N180_I,N181_I,N182_I,N183_I,N184_I,N185_I,
N186_I,N187_I,N188_I,N189_I,N190_I,N191_I,N192_I,N193_I,N194_I,N195_I,
N196_I,N197_I,N198_I,N199_I,N200_I,N201_I,N202_I,N203_I,N204_I,N205_I,
N206_I,N207_I,N208_I,N209_I,N210_I,N211_I,N212_I,N213_I,N214_I,N215_I,
N216_I,N217_I,N218_I,N398,N400,N401,N419,N420,N456,N457,
N458,N487,N488,N489,N490,N491,N492,N493,N494,N792,
N799,N805,N1026,N1028,N1029,N1269,N1277,N1448,N1726,N1816,
N1817,N1818,N1819,N1820,N1821,N1969,N1970,N1971,N2010,N2012,
N2014,N2016,N2018,N2020,N2022,N2387,N2388,N2389,N2390,N2496,
N2643,N2644,N2891,N2925,N2970,N2971,N3038,N3079,N3546,N3671,
N3803,N3804,N3809,N3851,N3875,N3881,N3882,N143_O,N144_O,N145_O,
N146_O,N147_O,N148_O,N149_O,N150_O,N151_O,N152_O,N153_O,N154_O,N155_O,
N156_O,N157_O,N158_O,N159_O,N160_O,N161_O,N162_O,N163_O,N164_O,N165_O,
N166_O,N167_O,N168_O,N169_O,N170_O,N171_O,N172_O,N173_O,N174_O,N175_O,
N176_O,N177_O,N178_O,N179_O,N180_O,N181_O,N182_O,N183_O,N184_O,N185_O,
N186_O,N187_O,N188_O,N189_O,N190_O,N191_O,N192_O,N193_O,N194_O,N195_O,
N196_O,N197_O,N198_O,N199_O,N200_O,N201_O,N202_O,N203_O,N204_O,N205_O,
N206_O,N207_O,N208_O,N209_O,N210_O,N211_O,N212_O,N213_O,N214_O,N215_O,
N216_O,N217_O,N218_O); |
input N1,N2,N3,N4,N5,N6,N7,N8,N11,N14,
N15,N16,N19,N20,N21,N22,N23,N24,N25,N26,
N27,N28,N29,N32,N33,N34,N35,N36,N37,N40,
N43,N44,N47,N48,N49,N50,N51,N52,N53,N54,
N55,N56,N57,N60,N61,N62,N63,N64,N65,N66,
N67,N68,N69,N72,N73,N74,N75,N76,N77,N78,
N79,N80,N81,N82,N85,N86,N87,N88,N89,N90,
N91,N92,N93,N94,N95,N96,N99,N100,N101,N102,
N103,N104,N105,N106,N107,N108,N111,N112,N113,N114,
N115,N116,N117,N118,N119,N120,N123,N124,N125,N126,
N127,N128,N129,N130,N131,N132,N135,N136,N137,N138,
N139,N140,N141,N142,N219,N224,N227,N230,N231,N234,
N237,N241,N246,N253,N256,N259,N262,N263,N266,N269,
N272,N275,N278,N281,N284,N287,N290,N294,N297,N301,
N305,N309,N313,N316,N319,N322,N325,N328,N331,N334,
N337,N340,N343,N346,N349,N352,N355,N143_I,N144_I,N145_I,
N146_I,N147_I,N148_I,N149_I,N150_I,N151_I,N152_I,N153_I,N154_I,N155_I,
N156_I,N157_I,N158_I,N159_I,N160_I,N161_I,N162_I,N163_I,N164_I,N165_I,
N166_I,N167_I,N168_I,N169_I,N170_I,N171_I,N172_I,N173_I,N174_I,N175_I,
N176_I,N177_I,N178_I,N179_I,N180_I,N181_I,N182_I,N183_I,N184_I,N185_I,
N186_I,N187_I,N188_I,N189_I,N190_I,N191_I,N192_I,N193_I,N194_I,N195_I,
N196_I,N197_I,N198_I,N199_I,N200_I,N201_I,N202_I,N203_I,N204_I,N205_I,
N206_I,N207_I,N208_I,N209_I,N210_I,N211_I,N212_I,N213_I,N214_I,N215_I,
N216_I,N217_I,N218_I;
input s_0,s_1;
output N398,N400,N401,N419,N420,N456,N457,N458,N487,N488,
N489,N490,N491,N492,N493,N494,N792,N799,N805,N1026,
N1028,N1029,N1269,N1277,N1448,N1726,N1816,N1817,N1818,N1819,
N1820,N1821,N1969,N1970,N1971,N2010,N2012,N2014,N2016,N2018,
N2020,N2022,N2387,N2388,N2389,N2390,N2496,N2643,N2644,N2891,
N2925,N2970,N2971,N3038,N3079,N3546,N3671,N3803,N3804,N3809,
N3851,N3875,N3881,N3882,N143_O,N144_O,N145_O,N146_O,N147_O,N148_O,
N149_O,N150_O,N151_O,N152_O,N153_O,N154_O,N155_O,N156_O,N157_O,N158_O,
N159_O,N160_O,N161_O,N162_O,N163_O,N164_O,N165_O,N166_O,N167_O,N168_O,
N169_O,N170_O,N171_O,N172_O,N173_O,N174_O,N175_O,N176_O,N177_O,N178_O,
N179_O,N180_O,N181_O,N182_O,N183_O,N184_O,N185_O,N186_O,N187_O,N188_O,
N189_O,N190_O,N191_O,N192_O,N193_O,N194_O,N195_O,N196_O,N197_O,N198_O,
N199_O,N200_O,N201_O,N202_O,N203_O,N204_O,N205_O,N206_O,N207_O,N208_O,
N209_O,N210_O,N211_O,N212_O,N213_O,N214_O,N215_O,N216_O,N217_O,N218_O;
wire N405,N408,N425,N485,N486,N495,N496,N499,N500,N503,
N506,N509,N521,N533,N537,N543,N544,N547,N550,N562,
N574,N578,N582,N594,N606,N607,N608,N609,N610,N611,
N612,N613,N625,N637,N643,N650,N651,N655,N659,N663,
N667,N671,N675,N679,N683,N687,N693,N699,N705,N711,
N715,N719,N723,N727,N730,N733,N734,N735,N738,N741,
N744,N747,N750,N753,N756,N759,N762,N765,N768,N771,
N774,N777,N780,N783,N786,N800,N900,N901,N902,N903,
N904,N905,N998,N999,N1027,N1032,N1033,N1034,N1037,N1042,
N1053,N1064,N1065,N1066,N1067,N1068,N1069,N1070,N1075,N1086,
N1097,N1098,N1099,N1100,N1101,N1102,N1113,N1124,N1125,N1126,
N1127,N1128,N1129,N1133,N1137,N1140,N1141,N1142,N1143,N1144,
N1145,N1146,N1157,N1168,N1169,N1170,N1171,N1172,N1173,N1178,
N1184,N1185,N1186,N1187,N1188,N1189,N1190,N1195,N1200,N1205,
N1210,N1211,N1212,N1213,N1214,N1215,N1216,N1219,N1222,N1225,
N1228,N1231,N1234,N1237,N1240,N1243,N1246,N1249,N1250,N1251,
N1254,N1257,N1260,N1263,N1266,N1275,N1276,N1302,N1351,N1352,
N1353,N1354,N1355,N1395,N1396,N1397,N1398,N1399,N1422,N1423,
N1424,N1425,N1426,N1427,N1440,N1441,N1449,N1450,N1451,N1452,
N1453,N1454,N1455,N1456,N1457,N1458,N1459,N1460,N1461,N1462,
N1463,N1464,N1465,N1466,N1467,N1468,N1469,N1470,N1471,N1472,
N1473,N1474,N1475,N1476,N1477,N1478,N1479,N1480,N1481,N1482,
N1483,N1484,N1485,N1486,N1487,N1488,N1489,N1490,N1491,N1492,
N1493,N1494,N1495,N1496,N1499,N1502,N1506,N1510,N1513,N1516,
N1519,N1520,N1521,N1522,N1523,N1524,N1525,N1526,N1527,N1528,
N1529,N1530,N1531,N1532,N1533,N1534,N1535,N1536,N1537,N1538,
N1539,N1540,N1541,N1542,N1543,N1544,N1545,N1546,N1547,N1548,
N1549,N1550,N1551,N1552,N1553,N1557,N1561,N1564,N1565,N1566,
N1567,N1568,N1569,N1570,N1571,N1572,N1573,N1574,N1575,N1576,
N1577,N1578,N1581,N1582,N1585,N1588,N1591,N1596,N1600,N1606,
N1612,N1615,N1619,N1624,N1628,N1631,N1634,N1637,N1642,N1647,
N1651,N1656,N1676,N1681,N1686,N1690,N1708,N1770,N1773,N1776,
N1777,N1778,N1781,N1784,N1785,N1795,N1798,N1801,N1804,N1807,
N1808,N1809,N1810,N1811,N1813,N1814,N1815,N1822,N1823,N1824,
N1827,N1830,N1831,N1832,N1833,N1836,N1841,N1848,N1852,N1856,
N1863,N1870,N1875,N1880,N1885,N1888,N1891,N1894,N1897,N1908,
N1909,N1910,N1911,N1912,N1913,N1914,N1915,N1916,N1917,N1918,
N1919,N1928,N1929,N1930,N1931,N1932,N1933,N1934,N1935,N1936,
N1939,N1940,N1941,N1942,N1945,N1948,N1951,N1954,N1957,N1960,
N1963,N1966,N2028,N2029,N2030,N2031,N2032,N2033,N2034,N2040,
N2041,N2042,N2043,N2046,N2049,N2052,N2055,N2058,N2061,N2064,
N2067,N2070,N2073,N2076,N2079,N2095,N2098,N2101,N2104,N2107,
N2110,N2113,N2119,N2120,N2125,N2126,N2127,N2128,N2135,N2141,
N2144,N2147,N2150,N2153,N2154,N2155,N2156,N2157,N2158,N2171,
N2172,N2173,N2174,N2175,N2176,N2177,N2178,N2185,N2188,N2191,
N2194,N2197,N2200,N2201,N2204,N2207,N2210,N2213,N2216,N2219,
N2234,N2235,N2236,N2237,N2250,N2266,N2269,N2291,N2294,N2297,
N2298,N2300,N2301,N2302,N2303,N2304,N2305,N2306,N2307,N2308,
N2309,N2310,N2311,N2312,N2313,N2314,N2315,N2316,N2317,N2318,
N2319,N2320,N2321,N2322,N2323,N2324,N2325,N2326,N2327,N2328,
N2329,N2330,N2331,N2332,N2333,N2334,N2335,N2336,N2337,N2338,
N2339,N2340,N2354,N2355,N2356,N2357,N2358,N2359,N2364,N2365,
N2366,N2367,N2368,N2372,N2373,N2374,N2375,N2376,N2377,N2382,
N2386,N2391,N2395,N2400,N2403,N2406,N2407,N2408,N2409,N2410,
N2411,N2412,N2413,N2414,N2415,N2416,N2417,N2421,N2425,N2428,
N2429,N2430,N2431,N2432,N2433,N2434,N2437,N2440,N2443,N2446,
N2449,N2452,N2453,N2454,N2457,N2460,N2463,N2466,N2469,N2472,
N2475,N2478,N2481,N2484,N2487,N2490,N2493,N2503,N2504,N2510,
N2511,N2521,N2528,N2531,N2534,N2537,N2540,N2544,N2545,N2546,
N2547,N2548,N2549,N2550,N2551,N2552,N2553,N2563,N2564,N2565,
N2566,N2567,N2568,N2579,N2603,N2607,N2608,N2609,N2610,N2611,
N2612,N2613,N2617,N2618,N2619,N2620,N2621,N2624,N2628,N2629,
N2630,N2631,N2632,N2633,N2634,N2635,N2636,N2638,N2645,N2646,
N2652,N2655,N2656,N2659,N2663,N2664,N2665,N2666,N2667,N2668,
N2669,N2670,N2671,N2672,N2673,N2674,N2675,N2676,N2677,N2678,
N2679,N2680,N2681,N2684,N2687,N2690,N2693,N2694,N2695,N2696,
N2697,N2698,N2699,N2700,N2701,N2702,N2703,N2706,N2707,N2708,
N2709,N2710,N2719,N2720,N2726,N2729,N2738,N2743,N2747,N2748,
N2749,N2750,N2751,N2760,N2761,N2766,N2771,N2772,N2773,N2774,
N2775,N2776,N2777,N2778,N2781,N2782,N2783,N2784,N2789,N2790,
N2791,N2792,N2793,N2796,N2800,N2803,N2806,N2809,N2810,N2811,
N2812,N2817,N2820,N2826,N2829,N2830,N2831,N2837,N2838,N2839,
N2840,N2841,N2844,N2854,N2859,N2869,N2874,N2877,N2880,N2881,
N2882,N2885,N2888,N2894,N2895,N2896,N2897,N2898,N2899,N2900,
N2901,N2914,N2915,N2916,N2917,N2918,N2919,N2920,N2921,N2931,
N2938,N2939,N2963,N2972,N2975,N2978,N2981,N2984,N2985,N2986,
N2989,N2992,N2995,N2998,N3001,N3004,N3007,N3008,N3009,N3010,
N3013,N3016,N3019,N3022,N3025,N3028,N3029,N3030,N3035,N3036,
N3037,N3039,N3044,N3045,N3046,N3047,N3048,N3049,N3050,N3053,
N3054,N3055,N3056,N3057,N3058,N3059,N3060,N3061,N3064,N3065,
N3066,N3067,N3068,N3069,N3070,N3071,N3072,N3073,N3074,N3075,
N3076,N3088,N3091,N3110,N3113,N3137,N3140,N3143,N3146,N3149,
N3152,N3157,N3160,N3163,N3166,N3169,N3172,N3175,N3176,N3177,
N3178,N3180,N3187,N3188,N3189,N3190,N3191,N3192,N3193,N3194,
N3195,N3196,N3197,N3208,N3215,N3216,N3217,N3218,N3219,N3220,
N3222,N3223,N3230,N3231,N3238,N3241,N3244,N3247,N3250,N3253,
N3256,N3259,N3262,N3265,N3268,N3271,N3274,N3277,N3281,N3282,
N3283,N3284,N3286,N3288,N3289,N3291,N3293,N3295,N3296,N3299,
N3301,N3302,N3304,N3306,N3308,N3309,N3312,N3314,N3315,N3318,
N3321,N3324,N3327,N3330,N3333,N3334,N3335,N3336,N3337,N3340,
N3344,N3348,N3352,N3356,N3360,N3364,N3367,N3370,N3374,N3378,
N3382,N3386,N3390,N3394,N3397,N3400,N3401,N3402,N3403,N3404,
N3405,N3406,N3409,N3410,N3412,N3414,N3416,N3418,N3420,N3422,
N3428,N3430,N3432,N3434,N3436,N3438,N3440,N3450,N3453,N3456,
N3459,N3478,N3479,N3480,N3481,N3482,N3483,N3484,N3485,N3486,
N3487,N3488,N3489,N3490,N3491,N3492,N3493,N3494,N3496,N3498,
N3499,N3500,N3501,N3502,N3503,N3504,N3505,N3506,N3507,N3508,
N3509,N3510,N3511,N3512,N3513,N3515,N3517,N3522,N3525,N3528,
N3531,N3534,N3537,N3540,N3543,N3551,N3552,N3553,N3554,N3555,
N3556,N3557,N3558,N3559,N3563,N3564,N3565,N3566,N3567,N3568,
N3569,N3570,N3576,N3579,N3585,N3588,N3592,N3593,N3594,N3595,
N3596,N3597,N3598,N3599,N3600,N3603,N3608,N3612,N3615,N3616,
N3622,N3629,N3630,N3631,N3632,N3633,N3634,N3635,N3640,N3644,
N3647,N3648,N3654,N3661,N3662,N3667,N3668,N3669,N3670,N3691,
N3692,N3693,N3694,N3695,N3696,N3697,N3716,N3717,N3718,N3719,
N3720,N3721,N3722,N3723,N3726,N3727,N3728,N3729,N3730,N3731,
N3732,N3733,N3734,N3735,N3736,N3737,N3740,N3741,N3742,N3743,
N3744,N3745,N3746,N3747,N3748,N3749,N3750,N3753,N3754,N3758,
N3761,N3762,N3767,N3771,N3774,N3775,N3778,N3779,N3780,N3790,
N3793,N3794,N3802,N3805,N3806,N3807,N3808,N3811,N3812,N3813,
N3814,N3815,N3816,N3817,N3818,N3819,N3820,N3821,N3822,N3823,
N3826,N3827,N3834,N3835,N3836,N3837,N3838,N3839,N3840,N3843,
N3852,N3857,N3858,N3859,N3864,N3869,N3870,N3876,N3877, gate1046inter0, gate1046inter1, gate1046inter2, gate1046inter3, gate1046inter4, gate1046inter5, gate1046inter6, gate1046inter7, gate1046inter8, gate1046inter9, gate1046inter10, gate1046inter11, gate1046inter12;
buf1 gate1( .a(N219), .O(N398) );
buf1 gate2( .a(N219), .O(N400) );
buf1 gate3( .a(N219), .O(N401) );
and2 gate4( .a(N1), .b(N3), .O(N405) );
inv1 gate5( .a(N230), .O(N408) );
buf1 gate6( .a(N253), .O(N419) );
buf1 gate7( .a(N253), .O(N420) );
inv1 gate8( .a(N262), .O(N425) );
buf1 gate9( .a(N290), .O(N456) );
buf1 gate10( .a(N290), .O(N457) );
buf1 gate11( .a(N290), .O(N458) );
and4 gate12( .a(N309), .b(N305), .c(N301), .d(N297), .O(N485) );
inv1 gate13( .a(N405), .O(N486) );
inv1 gate14( .a(N44), .O(N487) );
inv1 gate15( .a(N132), .O(N488) );
inv1 gate16( .a(N82), .O(N489) );
inv1 gate17( .a(N96), .O(N490) );
inv1 gate18( .a(N69), .O(N491) );
inv1 gate19( .a(N120), .O(N492) );
inv1 gate20( .a(N57), .O(N493) );
inv1 gate21( .a(N108), .O(N494) );
and3 gate22( .a(N2), .b(N15), .c(N237), .O(N495) );
buf1 gate23( .a(N237), .O(N496) );
and2 gate24( .a(N37), .b(N37), .O(N499) );
buf1 gate25( .a(N219), .O(N500) );
buf1 gate26( .a(N8), .O(N503) );
buf1 gate27( .a(N8), .O(N506) );
buf1 gate28( .a(N227), .O(N509) );
buf1 gate29( .a(N234), .O(N521) );
inv1 gate30( .a(N241), .O(N533) );
inv1 gate31( .a(N246), .O(N537) );
and2 gate32( .a(N11), .b(N246), .O(N543) );
and4 gate33( .a(N132), .b(N82), .c(N96), .d(N44), .O(N544) );
and4 gate34( .a(N120), .b(N57), .c(N108), .d(N69), .O(N547) );
buf1 gate35( .a(N227), .O(N550) );
buf1 gate36( .a(N234), .O(N562) );
inv1 gate37( .a(N256), .O(N574) );
inv1 gate38( .a(N259), .O(N578) );
buf1 gate39( .a(N319), .O(N582) );
buf1 gate40( .a(N322), .O(N594) );
inv1 gate41( .a(N328), .O(N606) );
inv1 gate42( .a(N331), .O(N607) );
inv1 gate43( .a(N334), .O(N608) );
inv1 gate44( .a(N337), .O(N609) );
inv1 gate45( .a(N340), .O(N610) );
inv1 gate46( .a(N343), .O(N611) );
inv1 gate47( .a(N352), .O(N612) );
buf1 gate48( .a(N319), .O(N613) );
buf1 gate49( .a(N322), .O(N625) );
buf1 gate50( .a(N16), .O(N637) );
buf1 gate51( .a(N16), .O(N643) );
inv1 gate52( .a(N355), .O(N650) );
and2 gate53( .a(N7), .b(N237), .O(N651) );
inv1 gate54( .a(N263), .O(N655) );
inv1 gate55( .a(N266), .O(N659) );
inv1 gate56( .a(N269), .O(N663) );
inv1 gate57( .a(N272), .O(N667) );
inv1 gate58( .a(N275), .O(N671) );
inv1 gate59( .a(N278), .O(N675) );
inv1 gate60( .a(N281), .O(N679) );
inv1 gate61( .a(N284), .O(N683) );
inv1 gate62( .a(N287), .O(N687) );
buf1 gate63( .a(N29), .O(N693) );
buf1 gate64( .a(N29), .O(N699) );
inv1 gate65( .a(N294), .O(N705) );
inv1 gate66( .a(N297), .O(N711) );
inv1 gate67( .a(N301), .O(N715) );
inv1 gate68( .a(N305), .O(N719) );
inv1 gate69( .a(N309), .O(N723) );
inv1 gate70( .a(N313), .O(N727) );
inv1 gate71( .a(N316), .O(N730) );
inv1 gate72( .a(N346), .O(N733) );
inv1 gate73( .a(N349), .O(N734) );
buf1 gate74( .a(N259), .O(N735) );
buf1 gate75( .a(N256), .O(N738) );
buf1 gate76( .a(N263), .O(N741) );
buf1 gate77( .a(N269), .O(N744) );
buf1 gate78( .a(N266), .O(N747) );
buf1 gate79( .a(N275), .O(N750) );
buf1 gate80( .a(N272), .O(N753) );
buf1 gate81( .a(N281), .O(N756) );
buf1 gate82( .a(N278), .O(N759) );
buf1 gate83( .a(N287), .O(N762) );
buf1 gate84( .a(N284), .O(N765) );
buf1 gate85( .a(N294), .O(N768) );
buf1 gate86( .a(N301), .O(N771) );
buf1 gate87( .a(N297), .O(N774) );
buf1 gate88( .a(N309), .O(N777) );
buf1 gate89( .a(N305), .O(N780) );
buf1 gate90( .a(N316), .O(N783) );
buf1 gate91( .a(N313), .O(N786) );
inv1 gate92( .a(N485), .O(N792) );
inv1 gate93( .a(N495), .O(N799) );
inv1 gate94( .a(N499), .O(N800) );
buf1 gate95( .a(N500), .O(N805) );
nand2 gate96( .a(N331), .b(N606), .O(N900) );
nand2 gate97( .a(N328), .b(N607), .O(N901) );
nand2 gate98( .a(N337), .b(N608), .O(N902) );
nand2 gate99( .a(N334), .b(N609), .O(N903) );
nand2 gate100( .a(N343), .b(N610), .O(N904) );
nand2 gate101( .a(N340), .b(N611), .O(N905) );
nand2 gate102( .a(N349), .b(N733), .O(N998) );
nand2 gate103( .a(N346), .b(N734), .O(N999) );
and2 gate104( .a(N94), .b(N500), .O(N1026) );
and2 gate105( .a(N325), .b(N651), .O(N1027) );
inv1 gate106( .a(N651), .O(N1028) );
nand2 gate107( .a(N231), .b(N651), .O(N1029) );
inv1 gate108( .a(N544), .O(N1032) );
inv1 gate109( .a(N547), .O(N1033) );
and2 gate110( .a(N547), .b(N544), .O(N1034) );
buf1 gate111( .a(N503), .O(N1037) );
inv1 gate112( .a(N509), .O(N1042) );
inv1 gate113( .a(N521), .O(N1053) );
and3 gate114( .a(N80), .b(N509), .c(N521), .O(N1064) );
and3 gate115( .a(N68), .b(N509), .c(N521), .O(N1065) );
and3 gate116( .a(N79), .b(N509), .c(N521), .O(N1066) );
and3 gate117( .a(N78), .b(N509), .c(N521), .O(N1067) );
and3 gate118( .a(N77), .b(N509), .c(N521), .O(N1068) );
and2 gate119( .a(N11), .b(N537), .O(N1069) );
buf1 gate120( .a(N503), .O(N1070) );
inv1 gate121( .a(N550), .O(N1075) );
inv1 gate122( .a(N562), .O(N1086) );
and3 gate123( .a(N76), .b(N550), .c(N562), .O(N1097) );
and3 gate124( .a(N75), .b(N550), .c(N562), .O(N1098) );
and3 gate125( .a(N74), .b(N550), .c(N562), .O(N1099) );
and3 gate126( .a(N73), .b(N550), .c(N562), .O(N1100) );
and3 gate127( .a(N72), .b(N550), .c(N562), .O(N1101) );
inv1 gate128( .a(N582), .O(N1102) );
inv1 gate129( .a(N594), .O(N1113) );
and3 gate130( .a(N114), .b(N582), .c(N594), .O(N1124) );
and3 gate131( .a(N113), .b(N582), .c(N594), .O(N1125) );
and3 gate132( .a(N112), .b(N582), .c(N594), .O(N1126) );
and3 gate133( .a(N111), .b(N582), .c(N594), .O(N1127) );
and2 gate134( .a(N582), .b(N594), .O(N1128) );
nand2 gate135( .a(N900), .b(N901), .O(N1129) );
nand2 gate136( .a(N902), .b(N903), .O(N1133) );
nand2 gate137( .a(N904), .b(N905), .O(N1137) );
inv1 gate138( .a(N741), .O(N1140) );
nand2 gate139( .a(N741), .b(N612), .O(N1141) );
inv1 gate140( .a(N744), .O(N1142) );
inv1 gate141( .a(N747), .O(N1143) );
inv1 gate142( .a(N750), .O(N1144) );
inv1 gate143( .a(N753), .O(N1145) );
inv1 gate144( .a(N613), .O(N1146) );
inv1 gate145( .a(N625), .O(N1157) );
and3 gate146( .a(N118), .b(N613), .c(N625), .O(N1168) );
and3 gate147( .a(N107), .b(N613), .c(N625), .O(N1169) );
and3 gate148( .a(N117), .b(N613), .c(N625), .O(N1170) );
and3 gate149( .a(N116), .b(N613), .c(N625), .O(N1171) );
and3 gate150( .a(N115), .b(N613), .c(N625), .O(N1172) );
inv1 gate151( .a(N637), .O(N1173) );
inv1 gate152( .a(N643), .O(N1178) );
inv1 gate153( .a(N768), .O(N1184) );
nand2 gate154( .a(N768), .b(N650), .O(N1185) );
inv1 gate155( .a(N771), .O(N1186) );
inv1 gate156( .a(N774), .O(N1187) );
inv1 gate157( .a(N777), .O(N1188) );
inv1 gate158( .a(N780), .O(N1189) );
buf1 gate159( .a(N506), .O(N1190) );
buf1 gate160( .a(N506), .O(N1195) );
inv1 gate161( .a(N693), .O(N1200) );
inv1 gate162( .a(N699), .O(N1205) );
inv1 gate163( .a(N735), .O(N1210) );
inv1 gate164( .a(N738), .O(N1211) );
inv1 gate165( .a(N756), .O(N1212) );
inv1 gate166( .a(N759), .O(N1213) );
inv1 gate167( .a(N762), .O(N1214) );
inv1 gate168( .a(N765), .O(N1215) );
nand2 gate169( .a(N998), .b(N999), .O(N1216) );
buf1 gate170( .a(N574), .O(N1219) );
buf1 gate171( .a(N578), .O(N1222) );
buf1 gate172( .a(N655), .O(N1225) );
buf1 gate173( .a(N659), .O(N1228) );
buf1 gate174( .a(N663), .O(N1231) );
buf1 gate175( .a(N667), .O(N1234) );
buf1 gate176( .a(N671), .O(N1237) );
buf1 gate177( .a(N675), .O(N1240) );
buf1 gate178( .a(N679), .O(N1243) );
buf1 gate179( .a(N683), .O(N1246) );
inv1 gate180( .a(N783), .O(N1249) );
inv1 gate181( .a(N786), .O(N1250) );
buf1 gate182( .a(N687), .O(N1251) );
buf1 gate183( .a(N705), .O(N1254) );
buf1 gate184( .a(N711), .O(N1257) );
buf1 gate185( .a(N715), .O(N1260) );
buf1 gate186( .a(N719), .O(N1263) );
buf1 gate187( .a(N723), .O(N1266) );
inv1 gate188( .a(N1027), .O(N1269) );
and2 gate189( .a(N325), .b(N1032), .O(N1275) );
and2 gate190( .a(N231), .b(N1033), .O(N1276) );
buf1 gate191( .a(N1034), .O(N1277) );
or2 gate192( .a(N1069), .b(N543), .O(N1302) );
nand2 gate193( .a(N352), .b(N1140), .O(N1351) );
nand2 gate194( .a(N747), .b(N1142), .O(N1352) );
nand2 gate195( .a(N744), .b(N1143), .O(N1353) );
nand2 gate196( .a(N753), .b(N1144), .O(N1354) );
nand2 gate197( .a(N750), .b(N1145), .O(N1355) );
nand2 gate198( .a(N355), .b(N1184), .O(N1395) );
nand2 gate199( .a(N774), .b(N1186), .O(N1396) );
nand2 gate200( .a(N771), .b(N1187), .O(N1397) );
nand2 gate201( .a(N780), .b(N1188), .O(N1398) );
nand2 gate202( .a(N777), .b(N1189), .O(N1399) );
nand2 gate203( .a(N738), .b(N1210), .O(N1422) );
nand2 gate204( .a(N735), .b(N1211), .O(N1423) );
nand2 gate205( .a(N759), .b(N1212), .O(N1424) );
nand2 gate206( .a(N756), .b(N1213), .O(N1425) );
nand2 gate207( .a(N765), .b(N1214), .O(N1426) );
nand2 gate208( .a(N762), .b(N1215), .O(N1427) );
nand2 gate209( .a(N786), .b(N1249), .O(N1440) );
nand2 gate210( .a(N783), .b(N1250), .O(N1441) );
inv1 gate211( .a(N1034), .O(N1448) );
inv1 gate212( .a(N1275), .O(N1449) );
inv1 gate213( .a(N1276), .O(N1450) );
and3 gate214( .a(N93), .b(N1042), .c(N1053), .O(N1451) );
and3 gate215( .a(N55), .b(N509), .c(N1053), .O(N1452) );
and3 gate216( .a(N67), .b(N1042), .c(N521), .O(N1453) );
and3 gate217( .a(N81), .b(N1042), .c(N1053), .O(N1454) );
and3 gate218( .a(N43), .b(N509), .c(N1053), .O(N1455) );
and3 gate219( .a(N56), .b(N1042), .c(N521), .O(N1456) );
and3 gate220( .a(N92), .b(N1042), .c(N1053), .O(N1457) );
and3 gate221( .a(N54), .b(N509), .c(N1053), .O(N1458) );
and3 gate222( .a(N66), .b(N1042), .c(N521), .O(N1459) );
and3 gate223( .a(N91), .b(N1042), .c(N1053), .O(N1460) );
and3 gate224( .a(N53), .b(N509), .c(N1053), .O(N1461) );
and3 gate225( .a(N65), .b(N1042), .c(N521), .O(N1462) );
and3 gate226( .a(N90), .b(N1042), .c(N1053), .O(N1463) );
and3 gate227( .a(N52), .b(N509), .c(N1053), .O(N1464) );
and3 gate228( .a(N64), .b(N1042), .c(N521), .O(N1465) );
and3 gate229( .a(N89), .b(N1075), .c(N1086), .O(N1466) );
and3 gate230( .a(N51), .b(N550), .c(N1086), .O(N1467) );
and3 gate231( .a(N63), .b(N1075), .c(N562), .O(N1468) );
and3 gate232( .a(N88), .b(N1075), .c(N1086), .O(N1469) );
and3 gate233( .a(N50), .b(N550), .c(N1086), .O(N1470) );
and3 gate234( .a(N62), .b(N1075), .c(N562), .O(N1471) );
and3 gate235( .a(N87), .b(N1075), .c(N1086), .O(N1472) );
and3 gate236( .a(N49), .b(N550), .c(N1086), .O(N1473) );
and2 gate237( .a(N1075), .b(N562), .O(N1474) );
and3 gate238( .a(N86), .b(N1075), .c(N1086), .O(N1475) );
and3 gate239( .a(N48), .b(N550), .c(N1086), .O(N1476) );
and3 gate240( .a(N61), .b(N1075), .c(N562), .O(N1477) );
and3 gate241( .a(N85), .b(N1075), .c(N1086), .O(N1478) );
and3 gate242( .a(N47), .b(N550), .c(N1086), .O(N1479) );
and3 gate243( .a(N60), .b(N1075), .c(N562), .O(N1480) );
and3 gate244( .a(N138), .b(N1102), .c(N1113), .O(N1481) );
and3 gate245( .a(N102), .b(N582), .c(N1113), .O(N1482) );
and3 gate246( .a(N126), .b(N1102), .c(N594), .O(N1483) );
and3 gate247( .a(N137), .b(N1102), .c(N1113), .O(N1484) );
and3 gate248( .a(N101), .b(N582), .c(N1113), .O(N1485) );
and3 gate249( .a(N125), .b(N1102), .c(N594), .O(N1486) );
and3 gate250( .a(N136), .b(N1102), .c(N1113), .O(N1487) );
and3 gate251( .a(N100), .b(N582), .c(N1113), .O(N1488) );
and3 gate252( .a(N124), .b(N1102), .c(N594), .O(N1489) );
and3 gate253( .a(N135), .b(N1102), .c(N1113), .O(N1490) );
and3 gate254( .a(N99), .b(N582), .c(N1113), .O(N1491) );
and3 gate255( .a(N123), .b(N1102), .c(N594), .O(N1492) );
and2 gate256( .a(N1102), .b(N1113), .O(N1493) );
and2 gate257( .a(N582), .b(N1113), .O(N1494) );
and2 gate258( .a(N1102), .b(N594), .O(N1495) );
inv1 gate259( .a(N1129), .O(N1496) );
inv1 gate260( .a(N1133), .O(N1499) );
nand2 gate261( .a(N1351), .b(N1141), .O(N1502) );
nand2 gate262( .a(N1352), .b(N1353), .O(N1506) );
nand2 gate263( .a(N1354), .b(N1355), .O(N1510) );
buf1 gate264( .a(N1137), .O(N1513) );
buf1 gate265( .a(N1137), .O(N1516) );
inv1 gate266( .a(N1219), .O(N1519) );
inv1 gate267( .a(N1222), .O(N1520) );
inv1 gate268( .a(N1225), .O(N1521) );
inv1 gate269( .a(N1228), .O(N1522) );
inv1 gate270( .a(N1231), .O(N1523) );
inv1 gate271( .a(N1234), .O(N1524) );
inv1 gate272( .a(N1237), .O(N1525) );
inv1 gate273( .a(N1240), .O(N1526) );
inv1 gate274( .a(N1243), .O(N1527) );
inv1 gate275( .a(N1246), .O(N1528) );
and3 gate276( .a(N142), .b(N1146), .c(N1157), .O(N1529) );
and3 gate277( .a(N106), .b(N613), .c(N1157), .O(N1530) );
and3 gate278( .a(N130), .b(N1146), .c(N625), .O(N1531) );
and3 gate279( .a(N131), .b(N1146), .c(N1157), .O(N1532) );
and3 gate280( .a(N95), .b(N613), .c(N1157), .O(N1533) );
and3 gate281( .a(N119), .b(N1146), .c(N625), .O(N1534) );
and3 gate282( .a(N141), .b(N1146), .c(N1157), .O(N1535) );
and3 gate283( .a(N105), .b(N613), .c(N1157), .O(N1536) );
and3 gate284( .a(N129), .b(N1146), .c(N625), .O(N1537) );
and3 gate285( .a(N140), .b(N1146), .c(N1157), .O(N1538) );
and3 gate286( .a(N104), .b(N613), .c(N1157), .O(N1539) );
and3 gate287( .a(N128), .b(N1146), .c(N625), .O(N1540) );
and3 gate288( .a(N139), .b(N1146), .c(N1157), .O(N1541) );
and3 gate289( .a(N103), .b(N613), .c(N1157), .O(N1542) );
and3 gate290( .a(N127), .b(N1146), .c(N625), .O(N1543) );
and2 gate291( .a(N19), .b(N1173), .O(N1544) );
and2 gate292( .a(N4), .b(N1173), .O(N1545) );
and2 gate293( .a(N20), .b(N1173), .O(N1546) );
and2 gate294( .a(N5), .b(N1173), .O(N1547) );
and2 gate295( .a(N21), .b(N1178), .O(N1548) );
and2 gate296( .a(N22), .b(N1178), .O(N1549) );
and2 gate297( .a(N23), .b(N1178), .O(N1550) );
and2 gate298( .a(N6), .b(N1178), .O(N1551) );
and2 gate299( .a(N24), .b(N1178), .O(N1552) );
nand2 gate300( .a(N1395), .b(N1185), .O(N1553) );
nand2 gate301( .a(N1396), .b(N1397), .O(N1557) );
nand2 gate302( .a(N1398), .b(N1399), .O(N1561) );
and2 gate303( .a(N25), .b(N1200), .O(N1564) );
and2 gate304( .a(N32), .b(N1200), .O(N1565) );
and2 gate305( .a(N26), .b(N1200), .O(N1566) );
and2 gate306( .a(N33), .b(N1200), .O(N1567) );
and2 gate307( .a(N27), .b(N1205), .O(N1568) );
and2 gate308( .a(N34), .b(N1205), .O(N1569) );
and2 gate309( .a(N35), .b(N1205), .O(N1570) );
and2 gate310( .a(N28), .b(N1205), .O(N1571) );
inv1 gate311( .a(N1251), .O(N1572) );
inv1 gate312( .a(N1254), .O(N1573) );
inv1 gate313( .a(N1257), .O(N1574) );
inv1 gate314( .a(N1260), .O(N1575) );
inv1 gate315( .a(N1263), .O(N1576) );
inv1 gate316( .a(N1266), .O(N1577) );
nand2 gate317( .a(N1422), .b(N1423), .O(N1578) );
inv1 gate318( .a(N1216), .O(N1581) );
nand2 gate319( .a(N1426), .b(N1427), .O(N1582) );
nand2 gate320( .a(N1424), .b(N1425), .O(N1585) );
nand2 gate321( .a(N1440), .b(N1441), .O(N1588) );
and2 gate322( .a(N1449), .b(N1450), .O(N1591) );
or4 gate323( .a(N1451), .b(N1452), .c(N1453), .d(N1064), .O(N1596) );
or4 gate324( .a(N1454), .b(N1455), .c(N1456), .d(N1065), .O(N1600) );
or4 gate325( .a(N1457), .b(N1458), .c(N1459), .d(N1066), .O(N1606) );
or4 gate326( .a(N1460), .b(N1461), .c(N1462), .d(N1067), .O(N1612) );
or4 gate327( .a(N1463), .b(N1464), .c(N1465), .d(N1068), .O(N1615) );
or4 gate328( .a(N1466), .b(N1467), .c(N1468), .d(N1097), .O(N1619) );
or4 gate329( .a(N1469), .b(N1470), .c(N1471), .d(N1098), .O(N1624) );
or4 gate330( .a(N1472), .b(N1473), .c(N1474), .d(N1099), .O(N1628) );
or4 gate331( .a(N1475), .b(N1476), .c(N1477), .d(N1100), .O(N1631) );
or4 gate332( .a(N1478), .b(N1479), .c(N1480), .d(N1101), .O(N1634) );
or4 gate333( .a(N1481), .b(N1482), .c(N1483), .d(N1124), .O(N1637) );
or4 gate334( .a(N1484), .b(N1485), .c(N1486), .d(N1125), .O(N1642) );
or4 gate335( .a(N1487), .b(N1488), .c(N1489), .d(N1126), .O(N1647) );
or4 gate336( .a(N1490), .b(N1491), .c(N1492), .d(N1127), .O(N1651) );
or4 gate337( .a(N1493), .b(N1494), .c(N1495), .d(N1128), .O(N1656) );
or4 gate338( .a(N1532), .b(N1533), .c(N1534), .d(N1169), .O(N1676) );
or4 gate339( .a(N1535), .b(N1536), .c(N1537), .d(N1170), .O(N1681) );
or4 gate340( .a(N1538), .b(N1539), .c(N1540), .d(N1171), .O(N1686) );
or4 gate341( .a(N1541), .b(N1542), .c(N1543), .d(N1172), .O(N1690) );
or4 gate342( .a(N1529), .b(N1530), .c(N1531), .d(N1168), .O(N1708) );
buf1 gate343( .a(N1591), .O(N1726) );
inv1 gate344( .a(N1502), .O(N1770) );
inv1 gate345( .a(N1506), .O(N1773) );
inv1 gate346( .a(N1513), .O(N1776) );
inv1 gate347( .a(N1516), .O(N1777) );
buf1 gate348( .a(N1510), .O(N1778) );
buf1 gate349( .a(N1510), .O(N1781) );
and3 gate350( .a(N1133), .b(N1129), .c(N1513), .O(N1784) );
and3 gate351( .a(N1499), .b(N1496), .c(N1516), .O(N1785) );
inv1 gate352( .a(N1553), .O(N1795) );
inv1 gate353( .a(N1557), .O(N1798) );
buf1 gate354( .a(N1561), .O(N1801) );
buf1 gate355( .a(N1561), .O(N1804) );
inv1 gate356( .a(N1588), .O(N1807) );
inv1 gate357( .a(N1578), .O(N1808) );
nand2 gate358( .a(N1578), .b(N1581), .O(N1809) );
inv1 gate359( .a(N1582), .O(N1810) );
inv1 gate360( .a(N1585), .O(N1811) );
and2 gate361( .a(N1596), .b(N241), .O(N1813) );
and2 gate362( .a(N1606), .b(N241), .O(N1814) );
and2 gate363( .a(N1600), .b(N241), .O(N1815) );
inv1 gate364( .a(N1642), .O(N1816) );
inv1 gate365( .a(N1647), .O(N1817) );
inv1 gate366( .a(N1637), .O(N1818) );
inv1 gate367( .a(N1624), .O(N1819) );
inv1 gate368( .a(N1619), .O(N1820) );
inv1 gate369( .a(N1615), .O(N1821) );
and4 gate370( .a(N496), .b(N224), .c(N36), .d(N1591), .O(N1822) );
and4 gate371( .a(N496), .b(N224), .c(N1591), .d(N486), .O(N1823) );
buf1 gate372( .a(N1596), .O(N1824) );
inv1 gate373( .a(N1606), .O(N1827) );
and2 gate374( .a(N1600), .b(N537), .O(N1830) );
and2 gate375( .a(N1606), .b(N537), .O(N1831) );
and2 gate376( .a(N1619), .b(N246), .O(N1832) );
inv1 gate377( .a(N1596), .O(N1833) );
inv1 gate378( .a(N1600), .O(N1836) );
inv1 gate379( .a(N1606), .O(N1841) );
buf1 gate380( .a(N1612), .O(N1848) );
buf1 gate381( .a(N1615), .O(N1852) );
buf1 gate382( .a(N1619), .O(N1856) );
buf1 gate383( .a(N1624), .O(N1863) );
buf1 gate384( .a(N1628), .O(N1870) );
buf1 gate385( .a(N1631), .O(N1875) );
buf1 gate386( .a(N1634), .O(N1880) );
nand2 gate387( .a(N727), .b(N1651), .O(N1885) );
nand2 gate388( .a(N730), .b(N1656), .O(N1888) );
buf1 gate389( .a(N1686), .O(N1891) );
and2 gate390( .a(N1637), .b(N425), .O(N1894) );
inv1 gate391( .a(N1642), .O(N1897) );
and3 gate392( .a(N1496), .b(N1133), .c(N1776), .O(N1908) );
and3 gate393( .a(N1129), .b(N1499), .c(N1777), .O(N1909) );
and2 gate394( .a(N1600), .b(N637), .O(N1910) );
and2 gate395( .a(N1606), .b(N637), .O(N1911) );
and2 gate396( .a(N1612), .b(N637), .O(N1912) );
and2 gate397( .a(N1615), .b(N637), .O(N1913) );
and2 gate398( .a(N1619), .b(N643), .O(N1914) );
and2 gate399( .a(N1624), .b(N643), .O(N1915) );
and2 gate400( .a(N1628), .b(N643), .O(N1916) );
and2 gate401( .a(N1631), .b(N643), .O(N1917) );
and2 gate402( .a(N1634), .b(N643), .O(N1918) );
inv1 gate403( .a(N1708), .O(N1919) );
and2 gate404( .a(N1676), .b(N693), .O(N1928) );
and2 gate405( .a(N1681), .b(N693), .O(N1929) );
and2 gate406( .a(N1686), .b(N693), .O(N1930) );
and2 gate407( .a(N1690), .b(N693), .O(N1931) );
and2 gate408( .a(N1637), .b(N699), .O(N1932) );
and2 gate409( .a(N1642), .b(N699), .O(N1933) );
and2 gate410( .a(N1647), .b(N699), .O(N1934) );
and2 gate411( .a(N1651), .b(N699), .O(N1935) );
buf1 gate412( .a(N1600), .O(N1936) );
nand2 gate413( .a(N1216), .b(N1808), .O(N1939) );
nand2 gate414( .a(N1585), .b(N1810), .O(N1940) );
nand2 gate415( .a(N1582), .b(N1811), .O(N1941) );
buf1 gate416( .a(N1676), .O(N1942) );
buf1 gate417( .a(N1686), .O(N1945) );
buf1 gate418( .a(N1681), .O(N1948) );
buf1 gate419( .a(N1637), .O(N1951) );
buf1 gate420( .a(N1690), .O(N1954) );
buf1 gate421( .a(N1647), .O(N1957) );
buf1 gate422( .a(N1642), .O(N1960) );
buf1 gate423( .a(N1656), .O(N1963) );
buf1 gate424( .a(N1651), .O(N1966) );
or2 gate425( .a(N533), .b(N1815), .O(N1969) );
inv1 gate426( .a(N1822), .O(N1970) );
inv1 gate427( .a(N1823), .O(N1971) );
buf1 gate428( .a(N1848), .O(N2010) );
buf1 gate429( .a(N1852), .O(N2012) );
buf1 gate430( .a(N1856), .O(N2014) );
buf1 gate431( .a(N1863), .O(N2016) );
buf1 gate432( .a(N1870), .O(N2018) );
buf1 gate433( .a(N1875), .O(N2020) );
buf1 gate434( .a(N1880), .O(N2022) );
inv1 gate435( .a(N1778), .O(N2028) );
inv1 gate436( .a(N1781), .O(N2029) );
nor2 gate437( .a(N1908), .b(N1784), .O(N2030) );
nor2 gate438( .a(N1909), .b(N1785), .O(N2031) );
and3 gate439( .a(N1506), .b(N1502), .c(N1778), .O(N2032) );
and3 gate440( .a(N1773), .b(N1770), .c(N1781), .O(N2033) );
or2 gate441( .a(N1571), .b(N1935), .O(N2034) );
inv1 gate442( .a(N1801), .O(N2040) );
inv1 gate443( .a(N1804), .O(N2041) );
and3 gate444( .a(N1557), .b(N1553), .c(N1801), .O(N2042) );
and3 gate445( .a(N1798), .b(N1795), .c(N1804), .O(N2043) );
nand2 gate446( .a(N1939), .b(N1809), .O(N2046) );
nand2 gate447( .a(N1940), .b(N1941), .O(N2049) );
or2 gate448( .a(N1544), .b(N1910), .O(N2052) );
or2 gate449( .a(N1545), .b(N1911), .O(N2055) );
or2 gate450( .a(N1546), .b(N1912), .O(N2058) );
or2 gate451( .a(N1547), .b(N1913), .O(N2061) );
or2 gate452( .a(N1548), .b(N1914), .O(N2064) );
or2 gate453( .a(N1549), .b(N1915), .O(N2067) );
or2 gate454( .a(N1550), .b(N1916), .O(N2070) );
or2 gate455( .a(N1551), .b(N1917), .O(N2073) );
or2 gate456( .a(N1552), .b(N1918), .O(N2076) );
or2 gate457( .a(N1564), .b(N1928), .O(N2079) );
or2 gate458( .a(N1565), .b(N1929), .O(N2095) );
or2 gate459( .a(N1566), .b(N1930), .O(N2098) );
or2 gate460( .a(N1567), .b(N1931), .O(N2101) );
or2 gate461( .a(N1568), .b(N1932), .O(N2104) );
or2 gate462( .a(N1569), .b(N1933), .O(N2107) );
or2 gate463( .a(N1570), .b(N1934), .O(N2110) );
and3 gate464( .a(N1897), .b(N1894), .c(N40), .O(N2113) );
inv1 gate465( .a(N1894), .O(N2119) );
nand2 gate466( .a(N408), .b(N1827), .O(N2120) );
and2 gate467( .a(N1824), .b(N537), .O(N2125) );
and2 gate468( .a(N1852), .b(N246), .O(N2126) );
and2 gate469( .a(N1848), .b(N537), .O(N2127) );
inv1 gate470( .a(N1848), .O(N2128) );
inv1 gate471( .a(N1852), .O(N2135) );
inv1 gate472( .a(N1863), .O(N2141) );
inv1 gate473( .a(N1870), .O(N2144) );
inv1 gate474( .a(N1875), .O(N2147) );
inv1 gate475( .a(N1880), .O(N2150) );
and2 gate476( .a(N727), .b(N1885), .O(N2153) );
and2 gate477( .a(N1885), .b(N1651), .O(N2154) );
and2 gate478( .a(N730), .b(N1888), .O(N2155) );
and2 gate479( .a(N1888), .b(N1656), .O(N2156) );
and3 gate480( .a(N1770), .b(N1506), .c(N2028), .O(N2157) );
and3 gate481( .a(N1502), .b(N1773), .c(N2029), .O(N2158) );
inv1 gate482( .a(N1942), .O(N2171) );
nand2 gate483( .a(N1942), .b(N1919), .O(N2172) );
inv1 gate484( .a(N1945), .O(N2173) );
inv1 gate485( .a(N1948), .O(N2174) );
inv1 gate486( .a(N1951), .O(N2175) );
inv1 gate487( .a(N1954), .O(N2176) );
and3 gate488( .a(N1795), .b(N1557), .c(N2040), .O(N2177) );
and3 gate489( .a(N1553), .b(N1798), .c(N2041), .O(N2178) );
buf1 gate490( .a(N1836), .O(N2185) );
buf1 gate491( .a(N1833), .O(N2188) );
buf1 gate492( .a(N1841), .O(N2191) );
inv1 gate493( .a(N1856), .O(N2194) );
inv1 gate494( .a(N1827), .O(N2197) );
inv1 gate495( .a(N1936), .O(N2200) );
buf1 gate496( .a(N1836), .O(N2201) );
buf1 gate497( .a(N1833), .O(N2204) );
buf1 gate498( .a(N1841), .O(N2207) );
buf1 gate499( .a(N1824), .O(N2210) );
buf1 gate500( .a(N1841), .O(N2213) );
buf1 gate501( .a(N1841), .O(N2216) );
nand2 gate502( .a(N2031), .b(N2030), .O(N2219) );
inv1 gate503( .a(N1957), .O(N2234) );
inv1 gate504( .a(N1960), .O(N2235) );
inv1 gate505( .a(N1963), .O(N2236) );
inv1 gate506( .a(N1966), .O(N2237) );
and3 gate507( .a(N40), .b(N1897), .c(N2119), .O(N2250) );
or2 gate508( .a(N1831), .b(N2126), .O(N2266) );
or2 gate509( .a(N2127), .b(N1832), .O(N2269) );
or2 gate510( .a(N2153), .b(N2154), .O(N2291) );
or2 gate511( .a(N2155), .b(N2156), .O(N2294) );
nor2 gate512( .a(N2157), .b(N2032), .O(N2297) );
nor2 gate513( .a(N2158), .b(N2033), .O(N2298) );
inv1 gate514( .a(N2046), .O(N2300) );
inv1 gate515( .a(N2049), .O(N2301) );
nand2 gate516( .a(N2052), .b(N1519), .O(N2302) );
inv1 gate517( .a(N2052), .O(N2303) );
nand2 gate518( .a(N2055), .b(N1520), .O(N2304) );
inv1 gate519( .a(N2055), .O(N2305) );
nand2 gate520( .a(N2058), .b(N1521), .O(N2306) );
inv1 gate521( .a(N2058), .O(N2307) );
nand2 gate522( .a(N2061), .b(N1522), .O(N2308) );
inv1 gate523( .a(N2061), .O(N2309) );
nand2 gate524( .a(N2064), .b(N1523), .O(N2310) );
inv1 gate525( .a(N2064), .O(N2311) );
nand2 gate526( .a(N2067), .b(N1524), .O(N2312) );
inv1 gate527( .a(N2067), .O(N2313) );
nand2 gate528( .a(N2070), .b(N1525), .O(N2314) );
inv1 gate529( .a(N2070), .O(N2315) );
nand2 gate530( .a(N2073), .b(N1526), .O(N2316) );
inv1 gate531( .a(N2073), .O(N2317) );
nand2 gate532( .a(N2076), .b(N1527), .O(N2318) );
inv1 gate533( .a(N2076), .O(N2319) );
nand2 gate534( .a(N2079), .b(N1528), .O(N2320) );
inv1 gate535( .a(N2079), .O(N2321) );
nand2 gate536( .a(N1708), .b(N2171), .O(N2322) );
nand2 gate537( .a(N1948), .b(N2173), .O(N2323) );
nand2 gate538( .a(N1945), .b(N2174), .O(N2324) );
nand2 gate539( .a(N1954), .b(N2175), .O(N2325) );
nand2 gate540( .a(N1951), .b(N2176), .O(N2326) );
nor2 gate541( .a(N2177), .b(N2042), .O(N2327) );
nor2 gate542( .a(N2178), .b(N2043), .O(N2328) );
nand2 gate543( .a(N2095), .b(N1572), .O(N2329) );
inv1 gate544( .a(N2095), .O(N2330) );
nand2 gate545( .a(N2098), .b(N1573), .O(N2331) );
inv1 gate546( .a(N2098), .O(N2332) );
nand2 gate547( .a(N2101), .b(N1574), .O(N2333) );
inv1 gate548( .a(N2101), .O(N2334) );
nand2 gate549( .a(N2104), .b(N1575), .O(N2335) );
inv1 gate550( .a(N2104), .O(N2336) );
nand2 gate551( .a(N2107), .b(N1576), .O(N2337) );
inv1 gate552( .a(N2107), .O(N2338) );
nand2 gate553( .a(N2110), .b(N1577), .O(N2339) );
inv1 gate554( .a(N2110), .O(N2340) );
nand2 gate555( .a(N1960), .b(N2234), .O(N2354) );
nand2 gate556( .a(N1957), .b(N2235), .O(N2355) );
nand2 gate557( .a(N1966), .b(N2236), .O(N2356) );
nand2 gate558( .a(N1963), .b(N2237), .O(N2357) );
and2 gate559( .a(N2120), .b(N533), .O(N2358) );
inv1 gate560( .a(N2113), .O(N2359) );
inv1 gate561( .a(N2185), .O(N2364) );
inv1 gate562( .a(N2188), .O(N2365) );
inv1 gate563( .a(N2191), .O(N2366) );
inv1 gate564( .a(N2194), .O(N2367) );
buf1 gate565( .a(N2120), .O(N2368) );
inv1 gate566( .a(N2201), .O(N2372) );
inv1 gate567( .a(N2204), .O(N2373) );
inv1 gate568( .a(N2207), .O(N2374) );
inv1 gate569( .a(N2210), .O(N2375) );
inv1 gate570( .a(N2213), .O(N2376) );
inv1 gate571( .a(N2113), .O(N2377) );
buf1 gate572( .a(N2113), .O(N2382) );
and2 gate573( .a(N2120), .b(N246), .O(N2386) );
buf1 gate574( .a(N2266), .O(N2387) );
buf1 gate575( .a(N2266), .O(N2388) );
buf1 gate576( .a(N2269), .O(N2389) );
buf1 gate577( .a(N2269), .O(N2390) );
buf1 gate578( .a(N2113), .O(N2391) );
inv1 gate579( .a(N2113), .O(N2395) );
nand2 gate580( .a(N2219), .b(N2300), .O(N2400) );
inv1 gate581( .a(N2216), .O(N2403) );
inv1 gate582( .a(N2219), .O(N2406) );
nand2 gate583( .a(N1219), .b(N2303), .O(N2407) );
nand2 gate584( .a(N1222), .b(N2305), .O(N2408) );
nand2 gate585( .a(N1225), .b(N2307), .O(N2409) );
nand2 gate586( .a(N1228), .b(N2309), .O(N2410) );
nand2 gate587( .a(N1231), .b(N2311), .O(N2411) );
nand2 gate588( .a(N1234), .b(N2313), .O(N2412) );
nand2 gate589( .a(N1237), .b(N2315), .O(N2413) );
nand2 gate590( .a(N1240), .b(N2317), .O(N2414) );
nand2 gate591( .a(N1243), .b(N2319), .O(N2415) );
nand2 gate592( .a(N1246), .b(N2321), .O(N2416) );
nand2 gate593( .a(N2322), .b(N2172), .O(N2417) );
nand2 gate594( .a(N2323), .b(N2324), .O(N2421) );
nand2 gate595( .a(N2325), .b(N2326), .O(N2425) );
nand2 gate596( .a(N1251), .b(N2330), .O(N2428) );
nand2 gate597( .a(N1254), .b(N2332), .O(N2429) );
nand2 gate598( .a(N1257), .b(N2334), .O(N2430) );
nand2 gate599( .a(N1260), .b(N2336), .O(N2431) );
nand2 gate600( .a(N1263), .b(N2338), .O(N2432) );
nand2 gate601( .a(N1266), .b(N2340), .O(N2433) );
buf1 gate602( .a(N2128), .O(N2434) );
buf1 gate603( .a(N2135), .O(N2437) );
buf1 gate604( .a(N2144), .O(N2440) );
buf1 gate605( .a(N2141), .O(N2443) );
buf1 gate606( .a(N2150), .O(N2446) );
buf1 gate607( .a(N2147), .O(N2449) );
inv1 gate608( .a(N2197), .O(N2452) );
nand2 gate609( .a(N2197), .b(N2200), .O(N2453) );
buf1 gate610( .a(N2128), .O(N2454) );
buf1 gate611( .a(N2144), .O(N2457) );
buf1 gate612( .a(N2141), .O(N2460) );
buf1 gate613( .a(N2150), .O(N2463) );
buf1 gate614( .a(N2147), .O(N2466) );
inv1 gate615( .a(N2120), .O(N2469) );
buf1 gate616( .a(N2128), .O(N2472) );
buf1 gate617( .a(N2135), .O(N2475) );
buf1 gate618( .a(N2128), .O(N2478) );
buf1 gate619( .a(N2135), .O(N2481) );
nand2 gate620( .a(N2298), .b(N2297), .O(N2484) );
nand2 gate621( .a(N2356), .b(N2357), .O(N2487) );
nand2 gate622( .a(N2354), .b(N2355), .O(N2490) );
nand2 gate623( .a(N2328), .b(N2327), .O(N2493) );
or2 gate624( .a(N2358), .b(N1814), .O(N2496) );
nand2 gate625( .a(N2188), .b(N2364), .O(N2503) );
nand2 gate626( .a(N2185), .b(N2365), .O(N2504) );
nand2 gate627( .a(N2204), .b(N2372), .O(N2510) );
nand2 gate628( .a(N2201), .b(N2373), .O(N2511) );
or2 gate629( .a(N1830), .b(N2386), .O(N2521) );
nand2 gate630( .a(N2046), .b(N2406), .O(N2528) );
inv1 gate631( .a(N2291), .O(N2531) );
inv1 gate632( .a(N2294), .O(N2534) );
buf1 gate633( .a(N2250), .O(N2537) );
buf1 gate634( .a(N2250), .O(N2540) );
nand2 gate635( .a(N2302), .b(N2407), .O(N2544) );
nand2 gate636( .a(N2304), .b(N2408), .O(N2545) );
nand2 gate637( .a(N2306), .b(N2409), .O(N2546) );
nand2 gate638( .a(N2308), .b(N2410), .O(N2547) );
nand2 gate639( .a(N2310), .b(N2411), .O(N2548) );
nand2 gate640( .a(N2312), .b(N2412), .O(N2549) );
nand2 gate641( .a(N2314), .b(N2413), .O(N2550) );
nand2 gate642( .a(N2316), .b(N2414), .O(N2551) );
nand2 gate643( .a(N2318), .b(N2415), .O(N2552) );
nand2 gate644( .a(N2320), .b(N2416), .O(N2553) );
nand2 gate645( .a(N2329), .b(N2428), .O(N2563) );
nand2 gate646( .a(N2331), .b(N2429), .O(N2564) );
nand2 gate647( .a(N2333), .b(N2430), .O(N2565) );
nand2 gate648( .a(N2335), .b(N2431), .O(N2566) );
nand2 gate649( .a(N2337), .b(N2432), .O(N2567) );
nand2 gate650( .a(N2339), .b(N2433), .O(N2568) );
nand2 gate651( .a(N1936), .b(N2452), .O(N2579) );
buf1 gate652( .a(N2359), .O(N2603) );
and2 gate653( .a(N1880), .b(N2377), .O(N2607) );
and2 gate654( .a(N1676), .b(N2377), .O(N2608) );
and2 gate655( .a(N1681), .b(N2377), .O(N2609) );
and2 gate656( .a(N1891), .b(N2377), .O(N2610) );
and2 gate657( .a(N1856), .b(N2382), .O(N2611) );
and2 gate658( .a(N1863), .b(N2382), .O(N2612) );
nand2 gate659( .a(N2503), .b(N2504), .O(N2613) );
inv1 gate660( .a(N2434), .O(N2617) );
nand2 gate661( .a(N2434), .b(N2366), .O(N2618) );
nand2 gate662( .a(N2437), .b(N2367), .O(N2619) );
inv1 gate663( .a(N2437), .O(N2620) );
inv1 gate664( .a(N2368), .O(N2621) );
nand2 gate665( .a(N2510), .b(N2511), .O(N2624) );
inv1 gate666( .a(N2454), .O(N2628) );
nand2 gate667( .a(N2454), .b(N2374), .O(N2629) );
inv1 gate668( .a(N2472), .O(N2630) );
and2 gate669( .a(N1856), .b(N2391), .O(N2631) );
and2 gate670( .a(N1863), .b(N2391), .O(N2632) );
and2 gate671( .a(N1880), .b(N2395), .O(N2633) );
and2 gate672( .a(N1676), .b(N2395), .O(N2634) );
and2 gate673( .a(N1681), .b(N2395), .O(N2635) );
and2 gate674( .a(N1891), .b(N2395), .O(N2636) );
inv1 gate675( .a(N2382), .O(N2638) );
buf1 gate676( .a(N2521), .O(N2643) );
buf1 gate677( .a(N2521), .O(N2644) );
inv1 gate678( .a(N2475), .O(N2645) );
inv1 gate679( .a(N2391), .O(N2646) );
nand2 gate680( .a(N2528), .b(N2400), .O(N2652) );
inv1 gate681( .a(N2478), .O(N2655) );
inv1 gate682( .a(N2481), .O(N2656) );
buf1 gate683( .a(N2359), .O(N2659) );
inv1 gate684( .a(N2484), .O(N2663) );
nand2 gate685( .a(N2484), .b(N2301), .O(N2664) );
inv1 gate686( .a(N2553), .O(N2665) );
inv1 gate687( .a(N2552), .O(N2666) );
inv1 gate688( .a(N2551), .O(N2667) );
inv1 gate689( .a(N2550), .O(N2668) );
inv1 gate690( .a(N2549), .O(N2669) );
inv1 gate691( .a(N2548), .O(N2670) );
inv1 gate692( .a(N2547), .O(N2671) );
inv1 gate693( .a(N2546), .O(N2672) );
inv1 gate694( .a(N2545), .O(N2673) );
inv1 gate695( .a(N2544), .O(N2674) );
inv1 gate696( .a(N2568), .O(N2675) );
inv1 gate697( .a(N2567), .O(N2676) );
inv1 gate698( .a(N2566), .O(N2677) );
inv1 gate699( .a(N2565), .O(N2678) );
inv1 gate700( .a(N2564), .O(N2679) );
inv1 gate701( .a(N2563), .O(N2680) );
inv1 gate702( .a(N2417), .O(N2681) );
inv1 gate703( .a(N2421), .O(N2684) );
buf1 gate704( .a(N2425), .O(N2687) );
buf1 gate705( .a(N2425), .O(N2690) );
inv1 gate706( .a(N2493), .O(N2693) );
nand2 gate707( .a(N2493), .b(N1807), .O(N2694) );
inv1 gate708( .a(N2440), .O(N2695) );
inv1 gate709( .a(N2443), .O(N2696) );
inv1 gate710( .a(N2446), .O(N2697) );
inv1 gate711( .a(N2449), .O(N2698) );
inv1 gate712( .a(N2457), .O(N2699) );
inv1 gate713( .a(N2460), .O(N2700) );
inv1 gate714( .a(N2463), .O(N2701) );
inv1 gate715( .a(N2466), .O(N2702) );
nand2 gate716( .a(N2579), .b(N2453), .O(N2703) );
inv1 gate717( .a(N2469), .O(N2706) );
inv1 gate718( .a(N2487), .O(N2707) );
inv1 gate719( .a(N2490), .O(N2708) );
and2 gate720( .a(N2294), .b(N2534), .O(N2709) );
and2 gate721( .a(N2291), .b(N2531), .O(N2710) );
nand2 gate722( .a(N2191), .b(N2617), .O(N2719) );
nand2 gate723( .a(N2194), .b(N2620), .O(N2720) );
nand2 gate724( .a(N2207), .b(N2628), .O(N2726) );
buf1 gate725( .a(N2537), .O(N2729) );
buf1 gate726( .a(N2537), .O(N2738) );
inv1 gate727( .a(N2652), .O(N2743) );
nand2 gate728( .a(N2049), .b(N2663), .O(N2747) );
and5 gate729( .a(N2665), .b(N2666), .c(N2667), .d(N2668), .e(N2669), .O(N2748) );
and5 gate730( .a(N2670), .b(N2671), .c(N2672), .d(N2673), .e(N2674), .O(N2749) );
and2 gate731( .a(N2034), .b(N2675), .O(N2750) );
and5 gate732( .a(N2676), .b(N2677), .c(N2678), .d(N2679), .e(N2680), .O(N2751) );
nand2 gate733( .a(N1588), .b(N2693), .O(N2760) );
buf1 gate734( .a(N2540), .O(N2761) );
buf1 gate735( .a(N2540), .O(N2766) );
nand2 gate736( .a(N2443), .b(N2695), .O(N2771) );
nand2 gate737( .a(N2440), .b(N2696), .O(N2772) );
nand2 gate738( .a(N2449), .b(N2697), .O(N2773) );
nand2 gate739( .a(N2446), .b(N2698), .O(N2774) );
nand2 gate740( .a(N2460), .b(N2699), .O(N2775) );
nand2 gate741( .a(N2457), .b(N2700), .O(N2776) );
nand2 gate742( .a(N2466), .b(N2701), .O(N2777) );
nand2 gate743( .a(N2463), .b(N2702), .O(N2778) );
nand2 gate744( .a(N2490), .b(N2707), .O(N2781) );
nand2 gate745( .a(N2487), .b(N2708), .O(N2782) );
or2 gate746( .a(N2709), .b(N2534), .O(N2783) );
or2 gate747( .a(N2710), .b(N2531), .O(N2784) );
and2 gate748( .a(N1856), .b(N2638), .O(N2789) );
and2 gate749( .a(N1863), .b(N2638), .O(N2790) );
and2 gate750( .a(N1870), .b(N2638), .O(N2791) );
and2 gate751( .a(N1875), .b(N2638), .O(N2792) );
inv1 gate752( .a(N2613), .O(N2793) );
nand2 gate753( .a(N2719), .b(N2618), .O(N2796) );
nand2 gate754( .a(N2619), .b(N2720), .O(N2800) );
inv1 gate755( .a(N2624), .O(N2803) );
nand2 gate756( .a(N2726), .b(N2629), .O(N2806) );
and2 gate757( .a(N1856), .b(N2646), .O(N2809) );
and2 gate758( .a(N1863), .b(N2646), .O(N2810) );
and2 gate759( .a(N1870), .b(N2646), .O(N2811) );
and2 gate760( .a(N1875), .b(N2646), .O(N2812) );
and2 gate761( .a(N2743), .b(N14), .O(N2817) );
buf1 gate762( .a(N2603), .O(N2820) );
nand2 gate763( .a(N2747), .b(N2664), .O(N2826) );
and2 gate764( .a(N2748), .b(N2749), .O(N2829) );
and2 gate765( .a(N2750), .b(N2751), .O(N2830) );
buf1 gate766( .a(N2659), .O(N2831) );
inv1 gate767( .a(N2687), .O(N2837) );
inv1 gate768( .a(N2690), .O(N2838) );
and3 gate769( .a(N2421), .b(N2417), .c(N2687), .O(N2839) );
and3 gate770( .a(N2684), .b(N2681), .c(N2690), .O(N2840) );
nand2 gate771( .a(N2760), .b(N2694), .O(N2841) );
buf1 gate772( .a(N2603), .O(N2844) );
buf1 gate773( .a(N2603), .O(N2854) );
buf1 gate774( .a(N2659), .O(N2859) );
buf1 gate775( .a(N2659), .O(N2869) );
nand2 gate776( .a(N2773), .b(N2774), .O(N2874) );
nand2 gate777( .a(N2771), .b(N2772), .O(N2877) );
inv1 gate778( .a(N2703), .O(N2880) );
nand2 gate779( .a(N2703), .b(N2706), .O(N2881) );
nand2 gate780( .a(N2777), .b(N2778), .O(N2882) );
nand2 gate781( .a(N2775), .b(N2776), .O(N2885) );
nand2 gate782( .a(N2781), .b(N2782), .O(N2888) );
nand2 gate783( .a(N2783), .b(N2784), .O(N2891) );
and2 gate784( .a(N2607), .b(N2729), .O(N2894) );
and2 gate785( .a(N2608), .b(N2729), .O(N2895) );
and2 gate786( .a(N2609), .b(N2729), .O(N2896) );
and2 gate787( .a(N2610), .b(N2729), .O(N2897) );
or2 gate788( .a(N2789), .b(N2611), .O(N2898) );
or2 gate789( .a(N2790), .b(N2612), .O(N2899) );
and2 gate790( .a(N2791), .b(N1037), .O(N2900) );
and2 gate791( .a(N2792), .b(N1037), .O(N2901) );
or2 gate792( .a(N2809), .b(N2631), .O(N2914) );
or2 gate793( .a(N2810), .b(N2632), .O(N2915) );
and2 gate794( .a(N2811), .b(N1070), .O(N2916) );
and2 gate795( .a(N2812), .b(N1070), .O(N2917) );
and2 gate796( .a(N2633), .b(N2738), .O(N2918) );
and2 gate797( .a(N2634), .b(N2738), .O(N2919) );
and2 gate798( .a(N2635), .b(N2738), .O(N2920) );
and2 gate799( .a(N2636), .b(N2738), .O(N2921) );
buf1 gate800( .a(N2817), .O(N2925) );
and3 gate801( .a(N2829), .b(N2830), .c(N1302), .O(N2931) );
and3 gate802( .a(N2681), .b(N2421), .c(N2837), .O(N2938) );
and3 gate803( .a(N2417), .b(N2684), .c(N2838), .O(N2939) );
nand2 gate804( .a(N2469), .b(N2880), .O(N2963) );
inv1 gate805( .a(N2841), .O(N2970) );
inv1 gate806( .a(N2826), .O(N2971) );
inv1 gate807( .a(N2894), .O(N2972) );
inv1 gate808( .a(N2895), .O(N2975) );
inv1 gate809( .a(N2896), .O(N2978) );
inv1 gate810( .a(N2897), .O(N2981) );
and2 gate811( .a(N2898), .b(N1037), .O(N2984) );
and2 gate812( .a(N2899), .b(N1037), .O(N2985) );
inv1 gate813( .a(N2900), .O(N2986) );
inv1 gate814( .a(N2901), .O(N2989) );
inv1 gate815( .a(N2796), .O(N2992) );
buf1 gate816( .a(N2800), .O(N2995) );
buf1 gate817( .a(N2800), .O(N2998) );
buf1 gate818( .a(N2806), .O(N3001) );
buf1 gate819( .a(N2806), .O(N3004) );
and2 gate820( .a(N574), .b(N2820), .O(N3007) );
and2 gate821( .a(N2914), .b(N1070), .O(N3008) );
and2 gate822( .a(N2915), .b(N1070), .O(N3009) );
inv1 gate823( .a(N2916), .O(N3010) );
inv1 gate824( .a(N2917), .O(N3013) );
inv1 gate825( .a(N2918), .O(N3016) );
inv1 gate826( .a(N2919), .O(N3019) );
inv1 gate827( .a(N2920), .O(N3022) );
inv1 gate828( .a(N2921), .O(N3025) );
inv1 gate829( .a(N2817), .O(N3028) );
and2 gate830( .a(N574), .b(N2831), .O(N3029) );
inv1 gate831( .a(N2820), .O(N3030) );
and2 gate832( .a(N578), .b(N2820), .O(N3035) );
and2 gate833( .a(N655), .b(N2820), .O(N3036) );
and2 gate834( .a(N659), .b(N2820), .O(N3037) );
buf1 gate835( .a(N2931), .O(N3038) );
inv1 gate836( .a(N2831), .O(N3039) );
and2 gate837( .a(N578), .b(N2831), .O(N3044) );
and2 gate838( .a(N655), .b(N2831), .O(N3045) );
and2 gate839( .a(N659), .b(N2831), .O(N3046) );
nor2 gate840( .a(N2938), .b(N2839), .O(N3047) );
nor2 gate841( .a(N2939), .b(N2840), .O(N3048) );
inv1 gate842( .a(N2888), .O(N3049) );
inv1 gate843( .a(N2844), .O(N3050) );
and2 gate844( .a(N663), .b(N2844), .O(N3053) );
and2 gate845( .a(N667), .b(N2844), .O(N3054) );
and2 gate846( .a(N671), .b(N2844), .O(N3055) );
and2 gate847( .a(N675), .b(N2844), .O(N3056) );
and2 gate848( .a(N679), .b(N2854), .O(N3057) );
and2 gate849( .a(N683), .b(N2854), .O(N3058) );
and2 gate850( .a(N687), .b(N2854), .O(N3059) );
and2 gate851( .a(N705), .b(N2854), .O(N3060) );
inv1 gate852( .a(N2859), .O(N3061) );
and2 gate853( .a(N663), .b(N2859), .O(N3064) );
and2 gate854( .a(N667), .b(N2859), .O(N3065) );
and2 gate855( .a(N671), .b(N2859), .O(N3066) );
and2 gate856( .a(N675), .b(N2859), .O(N3067) );
and2 gate857( .a(N679), .b(N2869), .O(N3068) );
and2 gate858( .a(N683), .b(N2869), .O(N3069) );
and2 gate859( .a(N687), .b(N2869), .O(N3070) );
and2 gate860( .a(N705), .b(N2869), .O(N3071) );
inv1 gate861( .a(N2874), .O(N3072) );
inv1 gate862( .a(N2877), .O(N3073) );
inv1 gate863( .a(N2882), .O(N3074) );
inv1 gate864( .a(N2885), .O(N3075) );
nand2 gate865( .a(N2881), .b(N2963), .O(N3076) );
inv1 gate866( .a(N2931), .O(N3079) );
inv1 gate867( .a(N2984), .O(N3088) );
inv1 gate868( .a(N2985), .O(N3091) );
inv1 gate869( .a(N3008), .O(N3110) );
inv1 gate870( .a(N3009), .O(N3113) );
and2 gate871( .a(N3055), .b(N1190), .O(N3137) );
and2 gate872( .a(N3056), .b(N1190), .O(N3140) );
and2 gate873( .a(N3057), .b(N2761), .O(N3143) );
and2 gate874( .a(N3058), .b(N2761), .O(N3146) );
and2 gate875( .a(N3059), .b(N2761), .O(N3149) );
and2 gate876( .a(N3060), .b(N2761), .O(N3152) );
and2 gate877( .a(N3066), .b(N1195), .O(N3157) );
and2 gate878( .a(N3067), .b(N1195), .O(N3160) );
and2 gate879( .a(N3068), .b(N2766), .O(N3163) );
and2 gate880( .a(N3069), .b(N2766), .O(N3166) );
and2 gate881( .a(N3070), .b(N2766), .O(N3169) );
and2 gate882( .a(N3071), .b(N2766), .O(N3172) );
nand2 gate883( .a(N2877), .b(N3072), .O(N3175) );
nand2 gate884( .a(N2874), .b(N3073), .O(N3176) );
nand2 gate885( .a(N2885), .b(N3074), .O(N3177) );
nand2 gate886( .a(N2882), .b(N3075), .O(N3178) );
nand2 gate887( .a(N3048), .b(N3047), .O(N3180) );
inv1 gate888( .a(N2995), .O(N3187) );
inv1 gate889( .a(N2998), .O(N3188) );
inv1 gate890( .a(N3001), .O(N3189) );
inv1 gate891( .a(N3004), .O(N3190) );
and3 gate892( .a(N2796), .b(N2613), .c(N2995), .O(N3191) );
and3 gate893( .a(N2992), .b(N2793), .c(N2998), .O(N3192) );
and3 gate894( .a(N2624), .b(N2368), .c(N3001), .O(N3193) );
and3 gate895( .a(N2803), .b(N2621), .c(N3004), .O(N3194) );
nand2 gate896( .a(N3076), .b(N2375), .O(N3195) );
inv1 gate897( .a(N3076), .O(N3196) );
and2 gate898( .a(N687), .b(N3030), .O(N3197) );
and2 gate899( .a(N687), .b(N3039), .O(N3208) );
and2 gate900( .a(N705), .b(N3030), .O(N3215) );
and2 gate901( .a(N711), .b(N3030), .O(N3216) );
and2 gate902( .a(N715), .b(N3030), .O(N3217) );
and2 gate903( .a(N705), .b(N3039), .O(N3218) );
and2 gate904( .a(N711), .b(N3039), .O(N3219) );
and2 gate905( .a(N715), .b(N3039), .O(N3220) );
and2 gate906( .a(N719), .b(N3050), .O(N3222) );
and2 gate907( .a(N723), .b(N3050), .O(N3223) );
and2 gate908( .a(N719), .b(N3061), .O(N3230) );
and2 gate909( .a(N723), .b(N3061), .O(N3231) );
nand2 gate910( .a(N3175), .b(N3176), .O(N3238) );
nand2 gate911( .a(N3177), .b(N3178), .O(N3241) );
buf1 gate912( .a(N2981), .O(N3244) );
buf1 gate913( .a(N2978), .O(N3247) );
buf1 gate914( .a(N2975), .O(N3250) );
buf1 gate915( .a(N2972), .O(N3253) );
buf1 gate916( .a(N2989), .O(N3256) );
buf1 gate917( .a(N2986), .O(N3259) );
buf1 gate918( .a(N3025), .O(N3262) );
buf1 gate919( .a(N3022), .O(N3265) );
buf1 gate920( .a(N3019), .O(N3268) );
buf1 gate921( .a(N3016), .O(N3271) );
buf1 gate922( .a(N3013), .O(N3274) );
buf1 gate923( .a(N3010), .O(N3277) );
and3 gate924( .a(N2793), .b(N2796), .c(N3187), .O(N3281) );
and3 gate925( .a(N2613), .b(N2992), .c(N3188), .O(N3282) );
and3 gate926( .a(N2621), .b(N2624), .c(N3189), .O(N3283) );
and3 gate927( .a(N2368), .b(N2803), .c(N3190), .O(N3284) );
nand2 gate928( .a(N2210), .b(N3196), .O(N3286) );
or2 gate929( .a(N3197), .b(N3007), .O(N3288) );
nand2 gate930( .a(N3180), .b(N3049), .O(N3289) );
and2 gate931( .a(N3152), .b(N2981), .O(N3291) );
and2 gate932( .a(N3149), .b(N2978), .O(N3293) );
and2 gate933( .a(N3146), .b(N2975), .O(N3295) );
and2 gate934( .a(N2972), .b(N3143), .O(N3296) );
and2 gate935( .a(N3140), .b(N2989), .O(N3299) );
and2 gate936( .a(N3137), .b(N2986), .O(N3301) );
or2 gate937( .a(N3208), .b(N3029), .O(N3302) );
and2 gate938( .a(N3172), .b(N3025), .O(N3304) );
and2 gate939( .a(N3169), .b(N3022), .O(N3306) );
and2 gate940( .a(N3166), .b(N3019), .O(N3308) );
and2 gate941( .a(N3016), .b(N3163), .O(N3309) );
and2 gate942( .a(N3160), .b(N3013), .O(N3312) );
and2 gate943( .a(N3157), .b(N3010), .O(N3314) );
or2 gate944( .a(N3215), .b(N3035), .O(N3315) );
or2 gate945( .a(N3216), .b(N3036), .O(N3318) );
or2 gate946( .a(N3217), .b(N3037), .O(N3321) );
or2 gate947( .a(N3218), .b(N3044), .O(N3324) );
or2 gate948( .a(N3219), .b(N3045), .O(N3327) );
or2 gate949( .a(N3220), .b(N3046), .O(N3330) );
inv1 gate950( .a(N3180), .O(N3333) );
or2 gate951( .a(N3222), .b(N3053), .O(N3334) );
or2 gate952( .a(N3223), .b(N3054), .O(N3335) );
or2 gate953( .a(N3230), .b(N3064), .O(N3336) );
or2 gate954( .a(N3231), .b(N3065), .O(N3337) );
buf1 gate955( .a(N3152), .O(N3340) );
buf1 gate956( .a(N3149), .O(N3344) );
buf1 gate957( .a(N3146), .O(N3348) );
buf1 gate958( .a(N3143), .O(N3352) );
buf1 gate959( .a(N3140), .O(N3356) );
buf1 gate960( .a(N3137), .O(N3360) );
buf1 gate961( .a(N3091), .O(N3364) );
buf1 gate962( .a(N3088), .O(N3367) );
buf1 gate963( .a(N3172), .O(N3370) );
buf1 gate964( .a(N3169), .O(N3374) );
buf1 gate965( .a(N3166), .O(N3378) );
buf1 gate966( .a(N3163), .O(N3382) );
buf1 gate967( .a(N3160), .O(N3386) );
buf1 gate968( .a(N3157), .O(N3390) );
buf1 gate969( .a(N3113), .O(N3394) );
buf1 gate970( .a(N3110), .O(N3397) );
nand2 gate971( .a(N3195), .b(N3286), .O(N3400) );
nor2 gate972( .a(N3281), .b(N3191), .O(N3401) );
nor2 gate973( .a(N3282), .b(N3192), .O(N3402) );
nor2 gate974( .a(N3283), .b(N3193), .O(N3403) );
nor2 gate975( .a(N3284), .b(N3194), .O(N3404) );
inv1 gate976( .a(N3238), .O(N3405) );
inv1 gate977( .a(N3241), .O(N3406) );
and2 gate978( .a(N3288), .b(N1836), .O(N3409) );
nand2 gate979( .a(N2888), .b(N3333), .O(N3410) );
inv1 gate980( .a(N3244), .O(N3412) );
inv1 gate981( .a(N3247), .O(N3414) );
inv1 gate982( .a(N3250), .O(N3416) );
inv1 gate983( .a(N3253), .O(N3418) );
inv1 gate984( .a(N3256), .O(N3420) );
inv1 gate985( .a(N3259), .O(N3422) );
and2 gate986( .a(N3302), .b(N1836), .O(N3428) );
inv1 gate987( .a(N3262), .O(N3430) );
inv1 gate988( .a(N3265), .O(N3432) );
inv1 gate989( .a(N3268), .O(N3434) );
inv1 gate990( .a(N3271), .O(N3436) );
inv1 gate991( .a(N3274), .O(N3438) );
inv1 gate992( .a(N3277), .O(N3440) );
and2 gate993( .a(N3334), .b(N1190), .O(N3450) );
and2 gate994( .a(N3335), .b(N1190), .O(N3453) );
and2 gate995( .a(N3336), .b(N1195), .O(N3456) );
and2 gate996( .a(N3337), .b(N1195), .O(N3459) );
and2 gate997( .a(N3400), .b(N533), .O(N3478) );
and2 gate998( .a(N3318), .b(N2128), .O(N3479) );
and2 gate999( .a(N3315), .b(N1841), .O(N3480) );
nand2 gate1000( .a(N3410), .b(N3289), .O(N3481) );
inv1 gate1001( .a(N3340), .O(N3482) );
nand2 gate1002( .a(N3340), .b(N3412), .O(N3483) );
inv1 gate1003( .a(N3344), .O(N3484) );
nand2 gate1004( .a(N3344), .b(N3414), .O(N3485) );
inv1 gate1005( .a(N3348), .O(N3486) );
nand2 gate1006( .a(N3348), .b(N3416), .O(N3487) );
inv1 gate1007( .a(N3352), .O(N3488) );
nand2 gate1008( .a(N3352), .b(N3418), .O(N3489) );
inv1 gate1009( .a(N3356), .O(N3490) );
nand2 gate1010( .a(N3356), .b(N3420), .O(N3491) );
inv1 gate1011( .a(N3360), .O(N3492) );
nand2 gate1012( .a(N3360), .b(N3422), .O(N3493) );
inv1 gate1013( .a(N3364), .O(N3494) );
inv1 gate1014( .a(N3367), .O(N3496) );
and2 gate1015( .a(N3321), .b(N2135), .O(N3498) );
and2 gate1016( .a(N3327), .b(N2128), .O(N3499) );
and2 gate1017( .a(N3324), .b(N1841), .O(N3500) );
inv1 gate1018( .a(N3370), .O(N3501) );
nand2 gate1019( .a(N3370), .b(N3430), .O(N3502) );
inv1 gate1020( .a(N3374), .O(N3503) );
nand2 gate1021( .a(N3374), .b(N3432), .O(N3504) );
inv1 gate1022( .a(N3378), .O(N3505) );
nand2 gate1023( .a(N3378), .b(N3434), .O(N3506) );
inv1 gate1024( .a(N3382), .O(N3507) );
nand2 gate1025( .a(N3382), .b(N3436), .O(N3508) );
inv1 gate1026( .a(N3386), .O(N3509) );
nand2 gate1027( .a(N3386), .b(N3438), .O(N3510) );
inv1 gate1028( .a(N3390), .O(N3511) );
nand2 gate1029( .a(N3390), .b(N3440), .O(N3512) );
inv1 gate1030( .a(N3394), .O(N3513) );
inv1 gate1031( .a(N3397), .O(N3515) );
and2 gate1032( .a(N3330), .b(N2135), .O(N3517) );
nand2 gate1033( .a(N3402), .b(N3401), .O(N3522) );
nand2 gate1034( .a(N3404), .b(N3403), .O(N3525) );
buf1 gate1035( .a(N3318), .O(N3528) );
buf1 gate1036( .a(N3315), .O(N3531) );
buf1 gate1037( .a(N3321), .O(N3534) );
buf1 gate1038( .a(N3327), .O(N3537) );
buf1 gate1039( .a(N3324), .O(N3540) );
buf1 gate1040( .a(N3330), .O(N3543) );
or2 gate1041( .a(N3478), .b(N1813), .O(N3546) );
inv1 gate1042( .a(N3481), .O(N3551) );
nand2 gate1043( .a(N3244), .b(N3482), .O(N3552) );
nand2 gate1044( .a(N3247), .b(N3484), .O(N3553) );
nand2 gate1045( .a(N3250), .b(N3486), .O(N3554) );
xor2 gate1270(.a(N3488), .b(N3253), .O(gate1046inter0));
nand2 gate1271(.a(gate1046inter0), .b(s_0), .O(gate1046inter1));
and2 gate1272(.a(N3488), .b(N3253), .O(gate1046inter2));
inv1 gate1273(.a(s_0), .O(gate1046inter3));
inv1 gate1274(.a(s_1), .O(gate1046inter4));
nand2 gate1275(.a(gate1046inter4), .b(gate1046inter3), .O(gate1046inter5));
nor2 gate1276(.a(gate1046inter5), .b(gate1046inter2), .O(gate1046inter6));
inv1 gate1277(.a(N3253), .O(gate1046inter7));
inv1 gate1278(.a(N3488), .O(gate1046inter8));
nand2 gate1279(.a(gate1046inter8), .b(gate1046inter7), .O(gate1046inter9));
nand2 gate1280(.a(s_1), .b(gate1046inter3), .O(gate1046inter10));
nor2 gate1281(.a(gate1046inter10), .b(gate1046inter9), .O(gate1046inter11));
nor2 gate1282(.a(gate1046inter11), .b(gate1046inter6), .O(gate1046inter12));
nand2 gate1283(.a(gate1046inter12), .b(gate1046inter1), .O(N3555));
nand2 gate1047( .a(N3256), .b(N3490), .O(N3556) );
nand2 gate1048( .a(N3259), .b(N3492), .O(N3557) );
and2 gate1049( .a(N3453), .b(N3091), .O(N3558) );
and2 gate1050( .a(N3450), .b(N3088), .O(N3559) );
nand2 gate1051( .a(N3262), .b(N3501), .O(N3563) );
nand2 gate1052( .a(N3265), .b(N3503), .O(N3564) );
nand2 gate1053( .a(N3268), .b(N3505), .O(N3565) );
nand2 gate1054( .a(N3271), .b(N3507), .O(N3566) );
nand2 gate1055( .a(N3274), .b(N3509), .O(N3567) );
nand2 gate1056( .a(N3277), .b(N3511), .O(N3568) );
and2 gate1057( .a(N3459), .b(N3113), .O(N3569) );
and2 gate1058( .a(N3456), .b(N3110), .O(N3570) );
buf1 gate1059( .a(N3453), .O(N3576) );
buf1 gate1060( .a(N3450), .O(N3579) );
buf1 gate1061( .a(N3459), .O(N3585) );
buf1 gate1062( .a(N3456), .O(N3588) );
inv1 gate1063( .a(N3522), .O(N3592) );
nand2 gate1064( .a(N3522), .b(N3405), .O(N3593) );
inv1 gate1065( .a(N3525), .O(N3594) );
nand2 gate1066( .a(N3525), .b(N3406), .O(N3595) );
inv1 gate1067( .a(N3528), .O(N3596) );
nand2 gate1068( .a(N3528), .b(N2630), .O(N3597) );
nand2 gate1069( .a(N3531), .b(N2376), .O(N3598) );
inv1 gate1070( .a(N3531), .O(N3599) );
and2 gate1071( .a(N3551), .b(N800), .O(N3600) );
nand2 gate1072( .a(N3552), .b(N3483), .O(N3603) );
nand2 gate1073( .a(N3553), .b(N3485), .O(N3608) );
nand2 gate1074( .a(N3554), .b(N3487), .O(N3612) );
nand2 gate1075( .a(N3555), .b(N3489), .O(N3615) );
nand2 gate1076( .a(N3556), .b(N3491), .O(N3616) );
nand2 gate1077( .a(N3557), .b(N3493), .O(N3622) );
inv1 gate1078( .a(N3534), .O(N3629) );
nand2 gate1079( .a(N3534), .b(N2645), .O(N3630) );
inv1 gate1080( .a(N3537), .O(N3631) );
nand2 gate1081( .a(N3537), .b(N2655), .O(N3632) );
nand2 gate1082( .a(N3540), .b(N2403), .O(N3633) );
inv1 gate1083( .a(N3540), .O(N3634) );
nand2 gate1084( .a(N3563), .b(N3502), .O(N3635) );
nand2 gate1085( .a(N3564), .b(N3504), .O(N3640) );
nand2 gate1086( .a(N3565), .b(N3506), .O(N3644) );
nand2 gate1087( .a(N3566), .b(N3508), .O(N3647) );
nand2 gate1088( .a(N3567), .b(N3510), .O(N3648) );
nand2 gate1089( .a(N3568), .b(N3512), .O(N3654) );
inv1 gate1090( .a(N3543), .O(N3661) );
nand2 gate1091( .a(N3543), .b(N2656), .O(N3662) );
nand2 gate1092( .a(N3238), .b(N3592), .O(N3667) );
nand2 gate1093( .a(N3241), .b(N3594), .O(N3668) );
nand2 gate1094( .a(N2472), .b(N3596), .O(N3669) );
nand2 gate1095( .a(N2213), .b(N3599), .O(N3670) );
buf1 gate1096( .a(N3600), .O(N3671) );
inv1 gate1097( .a(N3576), .O(N3691) );
nand2 gate1098( .a(N3576), .b(N3494), .O(N3692) );
inv1 gate1099( .a(N3579), .O(N3693) );
nand2 gate1100( .a(N3579), .b(N3496), .O(N3694) );
nand2 gate1101( .a(N2475), .b(N3629), .O(N3695) );
nand2 gate1102( .a(N2478), .b(N3631), .O(N3696) );
nand2 gate1103( .a(N2216), .b(N3634), .O(N3697) );
inv1 gate1104( .a(N3585), .O(N3716) );
nand2 gate1105( .a(N3585), .b(N3513), .O(N3717) );
inv1 gate1106( .a(N3588), .O(N3718) );
nand2 gate1107( .a(N3588), .b(N3515), .O(N3719) );
nand2 gate1108( .a(N2481), .b(N3661), .O(N3720) );
nand2 gate1109( .a(N3667), .b(N3593), .O(N3721) );
nand2 gate1110( .a(N3668), .b(N3595), .O(N3722) );
nand2 gate1111( .a(N3669), .b(N3597), .O(N3723) );
nand2 gate1112( .a(N3670), .b(N3598), .O(N3726) );
inv1 gate1113( .a(N3600), .O(N3727) );
nand2 gate1114( .a(N3364), .b(N3691), .O(N3728) );
nand2 gate1115( .a(N3367), .b(N3693), .O(N3729) );
nand2 gate1116( .a(N3695), .b(N3630), .O(N3730) );
and4 gate1117( .a(N3608), .b(N3615), .c(N3612), .d(N3603), .O(N3731) );
and2 gate1118( .a(N3603), .b(N3293), .O(N3732) );
and3 gate1119( .a(N3608), .b(N3603), .c(N3295), .O(N3733) );
and4 gate1120( .a(N3612), .b(N3603), .c(N3296), .d(N3608), .O(N3734) );
and2 gate1121( .a(N3616), .b(N3301), .O(N3735) );
and3 gate1122( .a(N3622), .b(N3616), .c(N3558), .O(N3736) );
nand2 gate1123( .a(N3696), .b(N3632), .O(N3737) );
nand2 gate1124( .a(N3697), .b(N3633), .O(N3740) );
nand2 gate1125( .a(N3394), .b(N3716), .O(N3741) );
nand2 gate1126( .a(N3397), .b(N3718), .O(N3742) );
nand2 gate1127( .a(N3720), .b(N3662), .O(N3743) );
and4 gate1128( .a(N3640), .b(N3647), .c(N3644), .d(N3635), .O(N3744) );
and2 gate1129( .a(N3635), .b(N3306), .O(N3745) );
and3 gate1130( .a(N3640), .b(N3635), .c(N3308), .O(N3746) );
and4 gate1131( .a(N3644), .b(N3635), .c(N3309), .d(N3640), .O(N3747) );
and2 gate1132( .a(N3648), .b(N3314), .O(N3748) );
and3 gate1133( .a(N3654), .b(N3648), .c(N3569), .O(N3749) );
inv1 gate1134( .a(N3721), .O(N3750) );
and2 gate1135( .a(N3722), .b(N246), .O(N3753) );
nand2 gate1136( .a(N3728), .b(N3692), .O(N3754) );
nand2 gate1137( .a(N3729), .b(N3694), .O(N3758) );
inv1 gate1138( .a(N3731), .O(N3761) );
or4 gate1139( .a(N3291), .b(N3732), .c(N3733), .d(N3734), .O(N3762) );
nand2 gate1140( .a(N3741), .b(N3717), .O(N3767) );
nand2 gate1141( .a(N3742), .b(N3719), .O(N3771) );
inv1 gate1142( .a(N3744), .O(N3774) );
or4 gate1143( .a(N3304), .b(N3745), .c(N3746), .d(N3747), .O(N3775) );
and2 gate1144( .a(N3723), .b(N3480), .O(N3778) );
and3 gate1145( .a(N3726), .b(N3723), .c(N3409), .O(N3779) );
or2 gate1146( .a(N2125), .b(N3753), .O(N3780) );
and2 gate1147( .a(N3750), .b(N800), .O(N3790) );
and2 gate1148( .a(N3737), .b(N3500), .O(N3793) );
and3 gate1149( .a(N3740), .b(N3737), .c(N3428), .O(N3794) );
or3 gate1150( .a(N3479), .b(N3778), .c(N3779), .O(N3802) );
buf1 gate1151( .a(N3780), .O(N3803) );
buf1 gate1152( .a(N3780), .O(N3804) );
inv1 gate1153( .a(N3762), .O(N3805) );
and5 gate1154( .a(N3622), .b(N3730), .c(N3754), .d(N3616), .e(N3758), .O(N3806) );
and4 gate1155( .a(N3754), .b(N3616), .c(N3559), .d(N3622), .O(N3807) );
and5 gate1156( .a(N3758), .b(N3754), .c(N3616), .d(N3498), .e(N3622), .O(N3808) );
buf1 gate1157( .a(N3790), .O(N3809) );
or3 gate1158( .a(N3499), .b(N3793), .c(N3794), .O(N3811) );
inv1 gate1159( .a(N3775), .O(N3812) );
and5 gate1160( .a(N3654), .b(N3743), .c(N3767), .d(N3648), .e(N3771), .O(N3813) );
and4 gate1161( .a(N3767), .b(N3648), .c(N3570), .d(N3654), .O(N3814) );
and5 gate1162( .a(N3771), .b(N3767), .c(N3648), .d(N3517), .e(N3654), .O(N3815) );
or5 gate1163( .a(N3299), .b(N3735), .c(N3736), .d(N3807), .e(N3808), .O(N3816) );
and2 gate1164( .a(N3806), .b(N3802), .O(N3817) );
nand2 gate1165( .a(N3805), .b(N3761), .O(N3818) );
inv1 gate1166( .a(N3790), .O(N3819) );
or5 gate1167( .a(N3312), .b(N3748), .c(N3749), .d(N3814), .e(N3815), .O(N3820) );
and2 gate1168( .a(N3813), .b(N3811), .O(N3821) );
nand2 gate1169( .a(N3812), .b(N3774), .O(N3822) );
or2 gate1170( .a(N3816), .b(N3817), .O(N3823) );
and3 gate1171( .a(N3727), .b(N3819), .c(N2841), .O(N3826) );
or2 gate1172( .a(N3820), .b(N3821), .O(N3827) );
inv1 gate1173( .a(N3823), .O(N3834) );
and2 gate1174( .a(N3818), .b(N3823), .O(N3835) );
inv1 gate1175( .a(N3827), .O(N3836) );
and2 gate1176( .a(N3822), .b(N3827), .O(N3837) );
and2 gate1177( .a(N3762), .b(N3834), .O(N3838) );
and2 gate1178( .a(N3775), .b(N3836), .O(N3839) );
or2 gate1179( .a(N3838), .b(N3835), .O(N3840) );
or2 gate1180( .a(N3839), .b(N3837), .O(N3843) );
buf1 gate1181( .a(N3843), .O(N3851) );
nand2 gate1182( .a(N3843), .b(N3840), .O(N3852) );
and2 gate1183( .a(N3843), .b(N3852), .O(N3857) );
and2 gate1184( .a(N3852), .b(N3840), .O(N3858) );
or2 gate1185( .a(N3857), .b(N3858), .O(N3859) );
inv1 gate1186( .a(N3859), .O(N3864) );
and2 gate1187( .a(N3859), .b(N3864), .O(N3869) );
or2 gate1188( .a(N3869), .b(N3864), .O(N3870) );
inv1 gate1189( .a(N3870), .O(N3875) );
and3 gate1190( .a(N2826), .b(N3028), .c(N3870), .O(N3876) );
and3 gate1191( .a(N3826), .b(N3876), .c(N1591), .O(N3877) );
buf1 gate1192( .a(N3877), .O(N3881) );
inv1 gate1193( .a(N3877), .O(N3882) );
buf1 gate1194( .a(N143_I), .O(N143_O) );
buf1 gate1195( .a(N144_I), .O(N144_O) );
buf1 gate1196( .a(N145_I), .O(N145_O) );
buf1 gate1197( .a(N146_I), .O(N146_O) );
buf1 gate1198( .a(N147_I), .O(N147_O) );
buf1 gate1199( .a(N148_I), .O(N148_O) );
buf1 gate1200( .a(N149_I), .O(N149_O) );
buf1 gate1201( .a(N150_I), .O(N150_O) );
buf1 gate1202( .a(N151_I), .O(N151_O) );
buf1 gate1203( .a(N152_I), .O(N152_O) );
buf1 gate1204( .a(N153_I), .O(N153_O) );
buf1 gate1205( .a(N154_I), .O(N154_O) );
buf1 gate1206( .a(N155_I), .O(N155_O) );
buf1 gate1207( .a(N156_I), .O(N156_O) );
buf1 gate1208( .a(N157_I), .O(N157_O) );
buf1 gate1209( .a(N158_I), .O(N158_O) );
buf1 gate1210( .a(N159_I), .O(N159_O) );
buf1 gate1211( .a(N160_I), .O(N160_O) );
buf1 gate1212( .a(N161_I), .O(N161_O) );
buf1 gate1213( .a(N162_I), .O(N162_O) );
buf1 gate1214( .a(N163_I), .O(N163_O) );
buf1 gate1215( .a(N164_I), .O(N164_O) );
buf1 gate1216( .a(N165_I), .O(N165_O) );
buf1 gate1217( .a(N166_I), .O(N166_O) );
buf1 gate1218( .a(N167_I), .O(N167_O) );
buf1 gate1219( .a(N168_I), .O(N168_O) );
buf1 gate1220( .a(N169_I), .O(N169_O) );
buf1 gate1221( .a(N170_I), .O(N170_O) );
buf1 gate1222( .a(N171_I), .O(N171_O) );
buf1 gate1223( .a(N172_I), .O(N172_O) );
buf1 gate1224( .a(N173_I), .O(N173_O) );
buf1 gate1225( .a(N174_I), .O(N174_O) );
buf1 gate1226( .a(N175_I), .O(N175_O) );
buf1 gate1227( .a(N176_I), .O(N176_O) );
buf1 gate1228( .a(N177_I), .O(N177_O) );
buf1 gate1229( .a(N178_I), .O(N178_O) );
buf1 gate1230( .a(N179_I), .O(N179_O) );
buf1 gate1231( .a(N180_I), .O(N180_O) );
buf1 gate1232( .a(N181_I), .O(N181_O) );
buf1 gate1233( .a(N182_I), .O(N182_O) );
buf1 gate1234( .a(N183_I), .O(N183_O) );
buf1 gate1235( .a(N184_I), .O(N184_O) );
buf1 gate1236( .a(N185_I), .O(N185_O) );
buf1 gate1237( .a(N186_I), .O(N186_O) );
buf1 gate1238( .a(N187_I), .O(N187_O) );
buf1 gate1239( .a(N188_I), .O(N188_O) );
buf1 gate1240( .a(N189_I), .O(N189_O) );
buf1 gate1241( .a(N190_I), .O(N190_O) );
buf1 gate1242( .a(N191_I), .O(N191_O) );
buf1 gate1243( .a(N192_I), .O(N192_O) );
buf1 gate1244( .a(N193_I), .O(N193_O) );
buf1 gate1245( .a(N194_I), .O(N194_O) );
buf1 gate1246( .a(N195_I), .O(N195_O) );
buf1 gate1247( .a(N196_I), .O(N196_O) );
buf1 gate1248( .a(N197_I), .O(N197_O) );
buf1 gate1249( .a(N198_I), .O(N198_O) );
buf1 gate1250( .a(N199_I), .O(N199_O) );
buf1 gate1251( .a(N200_I), .O(N200_O) );
buf1 gate1252( .a(N201_I), .O(N201_O) );
buf1 gate1253( .a(N202_I), .O(N202_O) );
buf1 gate1254( .a(N203_I), .O(N203_O) );
buf1 gate1255( .a(N204_I), .O(N204_O) );
buf1 gate1256( .a(N205_I), .O(N205_O) );
buf1 gate1257( .a(N206_I), .O(N206_O) );
buf1 gate1258( .a(N207_I), .O(N207_O) );
buf1 gate1259( .a(N208_I), .O(N208_O) );
buf1 gate1260( .a(N209_I), .O(N209_O) );
buf1 gate1261( .a(N210_I), .O(N210_O) );
buf1 gate1262( .a(N211_I), .O(N211_O) );
buf1 gate1263( .a(N212_I), .O(N212_O) );
buf1 gate1264( .a(N213_I), .O(N213_O) );
buf1 gate1265( .a(N214_I), .O(N214_O) );
buf1 gate1266( .a(N215_I), .O(N215_O) );
buf1 gate1267( .a(N216_I), .O(N216_O) );
buf1 gate1268( .a(N217_I), .O(N217_O) );
buf1 gate1269( .a(N218_I), .O(N218_O) );
endmodule | 8 |
137,402 | data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c432/c432-abcmap-fmt-4-randCam1-STD.v | 78,109,264 | c432-abcmap-fmt-4-randCam1-STD.v | v | 209 | 219 | [] | [] | [] | [(1, 209)] | null | null | 1: b"%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c432/c432-abcmap-fmt-4-randCam1-STD.v:12: Input/output/inout does not appear in port list: 's_0'\ninput s_0,s_1; \n ^~~\n%Error: data/full_repos/permissive/78109264/DeCam-Benchmarks-ISCAS-NAND-NOR-XOR/c432/c432-abcmap-fmt-4-randCam1-STD.v:12: Input/output/inout does not appear in port list: 's_1'\ninput s_0,s_1; \n ^~~\n%Error: Exiting due to 2 error(s)\n" | 298,127 | module | module c432 (N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115,N223,N329,N370,N421,
N430,N431,N432);
input N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115;
input s_0,s_1;
output N223,N329,N370,N421,N430,N431,N432;
wire N118,N119,N122,N123,N126,N127,N130,N131,N134,N135,
N138,N139,N142,N143,N146,N147,N150,N151,N154,N157,
N158,N159,N162,N165,N168,N171,N174,N177,N180,N183,
N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,
N194,N195,N196,N197,N198,N199,N203,N213,N224,N227,
N230,N233,N236,N239,N242,N243,N246,N247,N250,N251,
N254,N255,N256,N257,N258,N259,N260,N263,N264,N267,
N270,N273,N276,N279,N282,N285,N288,N289,N290,N291,
N292,N293,N294,N295,N296,N300,N301,N302,N303,N304,
N305,N306,N307,N308,N309,N319,N330,N331,N332,N333,
N334,N335,N336,N337,N338,N339,N340,N341,N342,N343,
N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,
N354,N355,N356,N357,N360,N371,N372,N373,N374,N375,
N376,N377,N378,N379,N380,N381,N386,N393,N399,N404,
N407,N411,N414,N415,N416,N417,N418,N419,N420,N422,
N425,N428,N429, gate110inter0, gate110inter1, gate110inter2, gate110inter3, gate110inter4, gate110inter5, gate110inter6, gate110inter7, gate110inter8, gate110inter9, gate110inter10, gate110inter11, gate110inter12;
inv1 gate1( .a(N1), .O(N118) );
inv1 gate2( .a(N4), .O(N119) );
inv1 gate3( .a(N11), .O(N122) );
inv1 gate4( .a(N17), .O(N123) );
inv1 gate5( .a(N24), .O(N126) );
inv1 gate6( .a(N30), .O(N127) );
inv1 gate7( .a(N37), .O(N130) );
inv1 gate8( .a(N43), .O(N131) );
inv1 gate9( .a(N50), .O(N134) );
inv1 gate10( .a(N56), .O(N135) );
inv1 gate11( .a(N63), .O(N138) );
inv1 gate12( .a(N69), .O(N139) );
inv1 gate13( .a(N76), .O(N142) );
inv1 gate14( .a(N82), .O(N143) );
inv1 gate15( .a(N89), .O(N146) );
inv1 gate16( .a(N95), .O(N147) );
inv1 gate17( .a(N102), .O(N150) );
inv1 gate18( .a(N108), .O(N151) );
nand2 gate19( .a(N118), .b(N4), .O(N154) );
nor2 gate20( .a(N8), .b(N119), .O(N157) );
nor2 gate21( .a(N14), .b(N119), .O(N158) );
nand2 gate22( .a(N122), .b(N17), .O(N159) );
nand2 gate23( .a(N126), .b(N30), .O(N162) );
nand2 gate24( .a(N130), .b(N43), .O(N165) );
nand2 gate25( .a(N134), .b(N56), .O(N168) );
nand2 gate26( .a(N138), .b(N69), .O(N171) );
nand2 gate27( .a(N142), .b(N82), .O(N174) );
nand2 gate28( .a(N146), .b(N95), .O(N177) );
nand2 gate29( .a(N150), .b(N108), .O(N180) );
nor2 gate30( .a(N21), .b(N123), .O(N183) );
nor2 gate31( .a(N27), .b(N123), .O(N184) );
nor2 gate32( .a(N34), .b(N127), .O(N185) );
nor2 gate33( .a(N40), .b(N127), .O(N186) );
nor2 gate34( .a(N47), .b(N131), .O(N187) );
nor2 gate35( .a(N53), .b(N131), .O(N188) );
nor2 gate36( .a(N60), .b(N135), .O(N189) );
nor2 gate37( .a(N66), .b(N135), .O(N190) );
nor2 gate38( .a(N73), .b(N139), .O(N191) );
nor2 gate39( .a(N79), .b(N139), .O(N192) );
nor2 gate40( .a(N86), .b(N143), .O(N193) );
nor2 gate41( .a(N92), .b(N143), .O(N194) );
nor2 gate42( .a(N99), .b(N147), .O(N195) );
nor2 gate43( .a(N105), .b(N147), .O(N196) );
nor2 gate44( .a(N112), .b(N151), .O(N197) );
nor2 gate45( .a(N115), .b(N151), .O(N198) );
and9 gate46( .a(N154), .b(N159), .c(N162), .d(N165), .e(N168), .f(N171), .g(N174), .h(N177), .i(N180), .O(N199) );
inv1 gate47( .a(N199), .O(N203) );
inv1 gate48( .a(N199), .O(N213) );
inv1 gate49( .a(N199), .O(N223) );
xor2 gate50( .a(N203), .b(N154), .O(N224) );
xor2 gate51( .a(N203), .b(N159), .O(N227) );
xor2 gate52( .a(N203), .b(N162), .O(N230) );
xor2 gate53( .a(N203), .b(N165), .O(N233) );
xor2 gate54( .a(N203), .b(N168), .O(N236) );
xor2 gate55( .a(N203), .b(N171), .O(N239) );
nand2 gate56( .a(N1), .b(N213), .O(N242) );
xor2 gate57( .a(N203), .b(N174), .O(N243) );
nand2 gate58( .a(N213), .b(N11), .O(N246) );
xor2 gate59( .a(N203), .b(N177), .O(N247) );
nand2 gate60( .a(N213), .b(N24), .O(N250) );
xor2 gate61( .a(N203), .b(N180), .O(N251) );
nand2 gate62( .a(N213), .b(N37), .O(N254) );
nand2 gate63( .a(N213), .b(N50), .O(N255) );
nand2 gate64( .a(N213), .b(N63), .O(N256) );
nand2 gate65( .a(N213), .b(N76), .O(N257) );
nand2 gate66( .a(N213), .b(N89), .O(N258) );
nand2 gate67( .a(N213), .b(N102), .O(N259) );
nand2 gate68( .a(N224), .b(N157), .O(N260) );
nand2 gate69( .a(N224), .b(N158), .O(N263) );
nand2 gate70( .a(N227), .b(N183), .O(N264) );
nand2 gate71( .a(N230), .b(N185), .O(N267) );
nand2 gate72( .a(N233), .b(N187), .O(N270) );
nand2 gate73( .a(N236), .b(N189), .O(N273) );
nand2 gate74( .a(N239), .b(N191), .O(N276) );
nand2 gate75( .a(N243), .b(N193), .O(N279) );
nand2 gate76( .a(N247), .b(N195), .O(N282) );
nand2 gate77( .a(N251), .b(N197), .O(N285) );
nand2 gate78( .a(N227), .b(N184), .O(N288) );
nand2 gate79( .a(N230), .b(N186), .O(N289) );
nand2 gate80( .a(N233), .b(N188), .O(N290) );
nand2 gate81( .a(N236), .b(N190), .O(N291) );
nand2 gate82( .a(N239), .b(N192), .O(N292) );
nand2 gate83( .a(N243), .b(N194), .O(N293) );
nand2 gate84( .a(N247), .b(N196), .O(N294) );
nand2 gate85( .a(N251), .b(N198), .O(N295) );
and9 gate86( .a(N260), .b(N264), .c(N267), .d(N270), .e(N273), .f(N276), .g(N279), .h(N282), .i(N285), .O(N296) );
inv1 gate87( .a(N263), .O(N300) );
inv1 gate88( .a(N288), .O(N301) );
inv1 gate89( .a(N289), .O(N302) );
inv1 gate90( .a(N290), .O(N303) );
inv1 gate91( .a(N291), .O(N304) );
inv1 gate92( .a(N292), .O(N305) );
inv1 gate93( .a(N293), .O(N306) );
inv1 gate94( .a(N294), .O(N307) );
inv1 gate95( .a(N295), .O(N308) );
inv1 gate96( .a(N296), .O(N309) );
inv1 gate97( .a(N296), .O(N319) );
inv1 gate98( .a(N296), .O(N329) );
xor2 gate99( .a(N309), .b(N260), .O(N330) );
xor2 gate100( .a(N309), .b(N264), .O(N331) );
xor2 gate101( .a(N309), .b(N267), .O(N332) );
xor2 gate102( .a(N309), .b(N270), .O(N333) );
nand2 gate103( .a(N8), .b(N319), .O(N334) );
xor2 gate104( .a(N309), .b(N273), .O(N335) );
nand2 gate105( .a(N319), .b(N21), .O(N336) );
xor2 gate106( .a(N309), .b(N276), .O(N337) );
nand2 gate107( .a(N319), .b(N34), .O(N338) );
xor2 gate108( .a(N309), .b(N279), .O(N339) );
nand2 gate109( .a(N319), .b(N47), .O(N340) );
xor2 gate161(.a(N282), .b(N309), .O(gate110inter0));
nand2 gate162(.a(gate110inter0), .b(s_0), .O(gate110inter1));
and2 gate163(.a(N282), .b(N309), .O(gate110inter2));
inv1 gate164(.a(s_0), .O(gate110inter3));
inv1 gate165(.a(s_1), .O(gate110inter4));
nand2 gate166(.a(gate110inter4), .b(gate110inter3), .O(gate110inter5));
nor2 gate167(.a(gate110inter5), .b(gate110inter2), .O(gate110inter6));
inv1 gate168(.a(N309), .O(gate110inter7));
inv1 gate169(.a(N282), .O(gate110inter8));
nand2 gate170(.a(gate110inter8), .b(gate110inter7), .O(gate110inter9));
nand2 gate171(.a(s_1), .b(gate110inter3), .O(gate110inter10));
nor2 gate172(.a(gate110inter10), .b(gate110inter9), .O(gate110inter11));
nor2 gate173(.a(gate110inter11), .b(gate110inter6), .O(gate110inter12));
nand2 gate174(.a(gate110inter12), .b(gate110inter1), .O(N341));
nand2 gate111( .a(N319), .b(N60), .O(N342) );
xor2 gate112( .a(N309), .b(N285), .O(N343) );
nand2 gate113( .a(N319), .b(N73), .O(N344) );
nand2 gate114( .a(N319), .b(N86), .O(N345) );
nand2 gate115( .a(N319), .b(N99), .O(N346) );
nand2 gate116( .a(N319), .b(N112), .O(N347) );
nand2 gate117( .a(N330), .b(N300), .O(N348) );
nand2 gate118( .a(N331), .b(N301), .O(N349) );
nand2 gate119( .a(N332), .b(N302), .O(N350) );
nand2 gate120( .a(N333), .b(N303), .O(N351) );
nand2 gate121( .a(N335), .b(N304), .O(N352) );
nand2 gate122( .a(N337), .b(N305), .O(N353) );
nand2 gate123( .a(N339), .b(N306), .O(N354) );
nand2 gate124( .a(N341), .b(N307), .O(N355) );
nand2 gate125( .a(N343), .b(N308), .O(N356) );
and9 gate126( .a(N348), .b(N349), .c(N350), .d(N351), .e(N352), .f(N353), .g(N354), .h(N355), .i(N356), .O(N357) );
inv1 gate127( .a(N357), .O(N360) );
inv1 gate128( .a(N357), .O(N370) );
nand2 gate129( .a(N14), .b(N360), .O(N371) );
nand2 gate130( .a(N360), .b(N27), .O(N372) );
nand2 gate131( .a(N360), .b(N40), .O(N373) );
nand2 gate132( .a(N360), .b(N53), .O(N374) );
nand2 gate133( .a(N360), .b(N66), .O(N375) );
nand2 gate134( .a(N360), .b(N79), .O(N376) );
nand2 gate135( .a(N360), .b(N92), .O(N377) );
nand2 gate136( .a(N360), .b(N105), .O(N378) );
nand2 gate137( .a(N360), .b(N115), .O(N379) );
nand4 gate138( .a(N4), .b(N242), .c(N334), .d(N371), .O(N380) );
nand4 gate139( .a(N246), .b(N336), .c(N372), .d(N17), .O(N381) );
nand4 gate140( .a(N250), .b(N338), .c(N373), .d(N30), .O(N386) );
nand4 gate141( .a(N254), .b(N340), .c(N374), .d(N43), .O(N393) );
nand4 gate142( .a(N255), .b(N342), .c(N375), .d(N56), .O(N399) );
nand4 gate143( .a(N256), .b(N344), .c(N376), .d(N69), .O(N404) );
nand4 gate144( .a(N257), .b(N345), .c(N377), .d(N82), .O(N407) );
nand4 gate145( .a(N258), .b(N346), .c(N378), .d(N95), .O(N411) );
nand4 gate146( .a(N259), .b(N347), .c(N379), .d(N108), .O(N414) );
inv1 gate147( .a(N380), .O(N415) );
and8 gate148( .a(N381), .b(N386), .c(N393), .d(N399), .e(N404), .f(N407), .g(N411), .h(N414), .O(N416) );
inv1 gate149( .a(N393), .O(N417) );
inv1 gate150( .a(N404), .O(N418) );
inv1 gate151( .a(N407), .O(N419) );
inv1 gate152( .a(N411), .O(N420) );
nor2 gate153( .a(N415), .b(N416), .O(N421) );
nand2 gate154( .a(N386), .b(N417), .O(N422) );
nand4 gate155( .a(N386), .b(N393), .c(N418), .d(N399), .O(N425) );
nand3 gate156( .a(N399), .b(N393), .c(N419), .O(N428) );
nand4 gate157( .a(N386), .b(N393), .c(N407), .d(N420), .O(N429) );
nand4 gate158( .a(N381), .b(N386), .c(N422), .d(N399), .O(N430) );
nand4 gate159( .a(N381), .b(N386), .c(N425), .d(N428), .O(N431) );
nand4 gate160( .a(N381), .b(N422), .c(N425), .d(N429), .O(N432) );
endmodule | module c432 (N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115,N223,N329,N370,N421,
N430,N431,N432); |
input N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115;
input s_0,s_1;
output N223,N329,N370,N421,N430,N431,N432;
wire N118,N119,N122,N123,N126,N127,N130,N131,N134,N135,
N138,N139,N142,N143,N146,N147,N150,N151,N154,N157,
N158,N159,N162,N165,N168,N171,N174,N177,N180,N183,
N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,
N194,N195,N196,N197,N198,N199,N203,N213,N224,N227,
N230,N233,N236,N239,N242,N243,N246,N247,N250,N251,
N254,N255,N256,N257,N258,N259,N260,N263,N264,N267,
N270,N273,N276,N279,N282,N285,N288,N289,N290,N291,
N292,N293,N294,N295,N296,N300,N301,N302,N303,N304,
N305,N306,N307,N308,N309,N319,N330,N331,N332,N333,
N334,N335,N336,N337,N338,N339,N340,N341,N342,N343,
N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,
N354,N355,N356,N357,N360,N371,N372,N373,N374,N375,
N376,N377,N378,N379,N380,N381,N386,N393,N399,N404,
N407,N411,N414,N415,N416,N417,N418,N419,N420,N422,
N425,N428,N429, gate110inter0, gate110inter1, gate110inter2, gate110inter3, gate110inter4, gate110inter5, gate110inter6, gate110inter7, gate110inter8, gate110inter9, gate110inter10, gate110inter11, gate110inter12;
inv1 gate1( .a(N1), .O(N118) );
inv1 gate2( .a(N4), .O(N119) );
inv1 gate3( .a(N11), .O(N122) );
inv1 gate4( .a(N17), .O(N123) );
inv1 gate5( .a(N24), .O(N126) );
inv1 gate6( .a(N30), .O(N127) );
inv1 gate7( .a(N37), .O(N130) );
inv1 gate8( .a(N43), .O(N131) );
inv1 gate9( .a(N50), .O(N134) );
inv1 gate10( .a(N56), .O(N135) );
inv1 gate11( .a(N63), .O(N138) );
inv1 gate12( .a(N69), .O(N139) );
inv1 gate13( .a(N76), .O(N142) );
inv1 gate14( .a(N82), .O(N143) );
inv1 gate15( .a(N89), .O(N146) );
inv1 gate16( .a(N95), .O(N147) );
inv1 gate17( .a(N102), .O(N150) );
inv1 gate18( .a(N108), .O(N151) );
nand2 gate19( .a(N118), .b(N4), .O(N154) );
nor2 gate20( .a(N8), .b(N119), .O(N157) );
nor2 gate21( .a(N14), .b(N119), .O(N158) );
nand2 gate22( .a(N122), .b(N17), .O(N159) );
nand2 gate23( .a(N126), .b(N30), .O(N162) );
nand2 gate24( .a(N130), .b(N43), .O(N165) );
nand2 gate25( .a(N134), .b(N56), .O(N168) );
nand2 gate26( .a(N138), .b(N69), .O(N171) );
nand2 gate27( .a(N142), .b(N82), .O(N174) );
nand2 gate28( .a(N146), .b(N95), .O(N177) );
nand2 gate29( .a(N150), .b(N108), .O(N180) );
nor2 gate30( .a(N21), .b(N123), .O(N183) );
nor2 gate31( .a(N27), .b(N123), .O(N184) );
nor2 gate32( .a(N34), .b(N127), .O(N185) );
nor2 gate33( .a(N40), .b(N127), .O(N186) );
nor2 gate34( .a(N47), .b(N131), .O(N187) );
nor2 gate35( .a(N53), .b(N131), .O(N188) );
nor2 gate36( .a(N60), .b(N135), .O(N189) );
nor2 gate37( .a(N66), .b(N135), .O(N190) );
nor2 gate38( .a(N73), .b(N139), .O(N191) );
nor2 gate39( .a(N79), .b(N139), .O(N192) );
nor2 gate40( .a(N86), .b(N143), .O(N193) );
nor2 gate41( .a(N92), .b(N143), .O(N194) );
nor2 gate42( .a(N99), .b(N147), .O(N195) );
nor2 gate43( .a(N105), .b(N147), .O(N196) );
nor2 gate44( .a(N112), .b(N151), .O(N197) );
nor2 gate45( .a(N115), .b(N151), .O(N198) );
and9 gate46( .a(N154), .b(N159), .c(N162), .d(N165), .e(N168), .f(N171), .g(N174), .h(N177), .i(N180), .O(N199) );
inv1 gate47( .a(N199), .O(N203) );
inv1 gate48( .a(N199), .O(N213) );
inv1 gate49( .a(N199), .O(N223) );
xor2 gate50( .a(N203), .b(N154), .O(N224) );
xor2 gate51( .a(N203), .b(N159), .O(N227) );
xor2 gate52( .a(N203), .b(N162), .O(N230) );
xor2 gate53( .a(N203), .b(N165), .O(N233) );
xor2 gate54( .a(N203), .b(N168), .O(N236) );
xor2 gate55( .a(N203), .b(N171), .O(N239) );
nand2 gate56( .a(N1), .b(N213), .O(N242) );
xor2 gate57( .a(N203), .b(N174), .O(N243) );
nand2 gate58( .a(N213), .b(N11), .O(N246) );
xor2 gate59( .a(N203), .b(N177), .O(N247) );
nand2 gate60( .a(N213), .b(N24), .O(N250) );
xor2 gate61( .a(N203), .b(N180), .O(N251) );
nand2 gate62( .a(N213), .b(N37), .O(N254) );
nand2 gate63( .a(N213), .b(N50), .O(N255) );
nand2 gate64( .a(N213), .b(N63), .O(N256) );
nand2 gate65( .a(N213), .b(N76), .O(N257) );
nand2 gate66( .a(N213), .b(N89), .O(N258) );
nand2 gate67( .a(N213), .b(N102), .O(N259) );
nand2 gate68( .a(N224), .b(N157), .O(N260) );
nand2 gate69( .a(N224), .b(N158), .O(N263) );
nand2 gate70( .a(N227), .b(N183), .O(N264) );
nand2 gate71( .a(N230), .b(N185), .O(N267) );
nand2 gate72( .a(N233), .b(N187), .O(N270) );
nand2 gate73( .a(N236), .b(N189), .O(N273) );
nand2 gate74( .a(N239), .b(N191), .O(N276) );
nand2 gate75( .a(N243), .b(N193), .O(N279) );
nand2 gate76( .a(N247), .b(N195), .O(N282) );
nand2 gate77( .a(N251), .b(N197), .O(N285) );
nand2 gate78( .a(N227), .b(N184), .O(N288) );
nand2 gate79( .a(N230), .b(N186), .O(N289) );
nand2 gate80( .a(N233), .b(N188), .O(N290) );
nand2 gate81( .a(N236), .b(N190), .O(N291) );
nand2 gate82( .a(N239), .b(N192), .O(N292) );
nand2 gate83( .a(N243), .b(N194), .O(N293) );
nand2 gate84( .a(N247), .b(N196), .O(N294) );
nand2 gate85( .a(N251), .b(N198), .O(N295) );
and9 gate86( .a(N260), .b(N264), .c(N267), .d(N270), .e(N273), .f(N276), .g(N279), .h(N282), .i(N285), .O(N296) );
inv1 gate87( .a(N263), .O(N300) );
inv1 gate88( .a(N288), .O(N301) );
inv1 gate89( .a(N289), .O(N302) );
inv1 gate90( .a(N290), .O(N303) );
inv1 gate91( .a(N291), .O(N304) );
inv1 gate92( .a(N292), .O(N305) );
inv1 gate93( .a(N293), .O(N306) );
inv1 gate94( .a(N294), .O(N307) );
inv1 gate95( .a(N295), .O(N308) );
inv1 gate96( .a(N296), .O(N309) );
inv1 gate97( .a(N296), .O(N319) );
inv1 gate98( .a(N296), .O(N329) );
xor2 gate99( .a(N309), .b(N260), .O(N330) );
xor2 gate100( .a(N309), .b(N264), .O(N331) );
xor2 gate101( .a(N309), .b(N267), .O(N332) );
xor2 gate102( .a(N309), .b(N270), .O(N333) );
nand2 gate103( .a(N8), .b(N319), .O(N334) );
xor2 gate104( .a(N309), .b(N273), .O(N335) );
nand2 gate105( .a(N319), .b(N21), .O(N336) );
xor2 gate106( .a(N309), .b(N276), .O(N337) );
nand2 gate107( .a(N319), .b(N34), .O(N338) );
xor2 gate108( .a(N309), .b(N279), .O(N339) );
nand2 gate109( .a(N319), .b(N47), .O(N340) );
xor2 gate161(.a(N282), .b(N309), .O(gate110inter0));
nand2 gate162(.a(gate110inter0), .b(s_0), .O(gate110inter1));
and2 gate163(.a(N282), .b(N309), .O(gate110inter2));
inv1 gate164(.a(s_0), .O(gate110inter3));
inv1 gate165(.a(s_1), .O(gate110inter4));
nand2 gate166(.a(gate110inter4), .b(gate110inter3), .O(gate110inter5));
nor2 gate167(.a(gate110inter5), .b(gate110inter2), .O(gate110inter6));
inv1 gate168(.a(N309), .O(gate110inter7));
inv1 gate169(.a(N282), .O(gate110inter8));
nand2 gate170(.a(gate110inter8), .b(gate110inter7), .O(gate110inter9));
nand2 gate171(.a(s_1), .b(gate110inter3), .O(gate110inter10));
nor2 gate172(.a(gate110inter10), .b(gate110inter9), .O(gate110inter11));
nor2 gate173(.a(gate110inter11), .b(gate110inter6), .O(gate110inter12));
nand2 gate174(.a(gate110inter12), .b(gate110inter1), .O(N341));
nand2 gate111( .a(N319), .b(N60), .O(N342) );
xor2 gate112( .a(N309), .b(N285), .O(N343) );
nand2 gate113( .a(N319), .b(N73), .O(N344) );
nand2 gate114( .a(N319), .b(N86), .O(N345) );
nand2 gate115( .a(N319), .b(N99), .O(N346) );
nand2 gate116( .a(N319), .b(N112), .O(N347) );
nand2 gate117( .a(N330), .b(N300), .O(N348) );
nand2 gate118( .a(N331), .b(N301), .O(N349) );
nand2 gate119( .a(N332), .b(N302), .O(N350) );
nand2 gate120( .a(N333), .b(N303), .O(N351) );
nand2 gate121( .a(N335), .b(N304), .O(N352) );
nand2 gate122( .a(N337), .b(N305), .O(N353) );
nand2 gate123( .a(N339), .b(N306), .O(N354) );
nand2 gate124( .a(N341), .b(N307), .O(N355) );
nand2 gate125( .a(N343), .b(N308), .O(N356) );
and9 gate126( .a(N348), .b(N349), .c(N350), .d(N351), .e(N352), .f(N353), .g(N354), .h(N355), .i(N356), .O(N357) );
inv1 gate127( .a(N357), .O(N360) );
inv1 gate128( .a(N357), .O(N370) );
nand2 gate129( .a(N14), .b(N360), .O(N371) );
nand2 gate130( .a(N360), .b(N27), .O(N372) );
nand2 gate131( .a(N360), .b(N40), .O(N373) );
nand2 gate132( .a(N360), .b(N53), .O(N374) );
nand2 gate133( .a(N360), .b(N66), .O(N375) );
nand2 gate134( .a(N360), .b(N79), .O(N376) );
nand2 gate135( .a(N360), .b(N92), .O(N377) );
nand2 gate136( .a(N360), .b(N105), .O(N378) );
nand2 gate137( .a(N360), .b(N115), .O(N379) );
nand4 gate138( .a(N4), .b(N242), .c(N334), .d(N371), .O(N380) );
nand4 gate139( .a(N246), .b(N336), .c(N372), .d(N17), .O(N381) );
nand4 gate140( .a(N250), .b(N338), .c(N373), .d(N30), .O(N386) );
nand4 gate141( .a(N254), .b(N340), .c(N374), .d(N43), .O(N393) );
nand4 gate142( .a(N255), .b(N342), .c(N375), .d(N56), .O(N399) );
nand4 gate143( .a(N256), .b(N344), .c(N376), .d(N69), .O(N404) );
nand4 gate144( .a(N257), .b(N345), .c(N377), .d(N82), .O(N407) );
nand4 gate145( .a(N258), .b(N346), .c(N378), .d(N95), .O(N411) );
nand4 gate146( .a(N259), .b(N347), .c(N379), .d(N108), .O(N414) );
inv1 gate147( .a(N380), .O(N415) );
and8 gate148( .a(N381), .b(N386), .c(N393), .d(N399), .e(N404), .f(N407), .g(N411), .h(N414), .O(N416) );
inv1 gate149( .a(N393), .O(N417) );
inv1 gate150( .a(N404), .O(N418) );
inv1 gate151( .a(N407), .O(N419) );
inv1 gate152( .a(N411), .O(N420) );
nor2 gate153( .a(N415), .b(N416), .O(N421) );
nand2 gate154( .a(N386), .b(N417), .O(N422) );
nand4 gate155( .a(N386), .b(N393), .c(N418), .d(N399), .O(N425) );
nand3 gate156( .a(N399), .b(N393), .c(N419), .O(N428) );
nand4 gate157( .a(N386), .b(N393), .c(N407), .d(N420), .O(N429) );
nand4 gate158( .a(N381), .b(N386), .c(N422), .d(N399), .O(N430) );
nand4 gate159( .a(N381), .b(N386), .c(N425), .d(N428), .O(N431) );
nand4 gate160( .a(N381), .b(N422), .c(N425), .d(N429), .O(N432) );
endmodule | 8 |
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