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137,781 | data/full_repos/permissive/80257330/dataMemory.v | 80,257,330 | dataMemory.v | v | 24 | 58 | [] | [] | [] | null | line:12: before: "assign" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80257330/dataMemory.v:17: Bit extraction of array[9:0] requires 4 bit index, not 10 bits.\n : ... In instance dataMemory\n dataMem[extaddr]<= datain;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80257330/dataMemory.v:21: Bit extraction of array[9:0] requires 4 bit index, not 10 bits.\n : ... In instance dataMemory\n assign dataout = dataMem[extaddr];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,595 | module | module dataMemory(address,datain,dataout,load,store,clk);
input [7:0] address;
input [15:0] datain;
input load,store,clk;
output [15:0] dataout;
reg [9:0] extaddr;
reg [15:0] dataMem[9:0];
integer i;
initial begin
for(i=0;i<10;i=i+1)
dataMem[i] = 16'h0111;
assign extaddr = { {2{address[7]}}, address };
end
always @(posedge clk) begin
if (store) begin
dataMem[extaddr]<= datain;
end
end
assign dataout = dataMem[extaddr];
endmodule | module dataMemory(address,datain,dataout,load,store,clk); |
input [7:0] address;
input [15:0] datain;
input load,store,clk;
output [15:0] dataout;
reg [9:0] extaddr;
reg [15:0] dataMem[9:0];
integer i;
initial begin
for(i=0;i<10;i=i+1)
dataMem[i] = 16'h0111;
assign extaddr = { {2{address[7]}}, address };
end
always @(posedge clk) begin
if (store) begin
dataMem[extaddr]<= datain;
end
end
assign dataout = dataMem[extaddr];
endmodule | 0 |
137,782 | data/full_repos/permissive/80257330/decode.v | 80,257,330 | decode.v | v | 14 | 62 | [] | [] | [] | [(1, 12)] | null | data/verilator_xmls/b756de1b-2925-4605-8c79-38e867c1a84f.xml | null | 300,596 | module | module decode(datain,opcode,reg0,src1,src2,jmpaddr,dataaddr);
input [15:0] datain;
output [3:0] opcode,reg0,src1,src2;
output [11:0] jmpaddr;
output [7:0] dataaddr;
assign opcode = datain[15:12];
assign reg0 = datain[11:8];
assign src1 = datain[7:4];
assign src2 = datain[3:0];
assign jmpaddr = datain[11:0];
assign dataaddr = datain[7:0];
endmodule | module decode(datain,opcode,reg0,src1,src2,jmpaddr,dataaddr); |
input [15:0] datain;
output [3:0] opcode,reg0,src1,src2;
output [11:0] jmpaddr;
output [7:0] dataaddr;
assign opcode = datain[15:12];
assign reg0 = datain[11:8];
assign src1 = datain[7:4];
assign src2 = datain[3:0];
assign jmpaddr = datain[11:0];
assign dataaddr = datain[7:0];
endmodule | 0 |
137,783 | data/full_repos/permissive/80257330/instructionMemory.v | 80,257,330 | instructionMemory.v | v | 10 | 56 | [] | [] | [] | [(1, 9)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80257330/instructionMemory.v:5: Bit extraction of array[15:0] requires 4 bit index, not 16 bits.\n : ... In instance instructionMemory\n assign data = instructionMem[address];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 300,597 | module | module instructionMemory(address,data);
input [15:0] address;
output [15:0] data;
reg [15:0] instructionMem[15:0];
assign data = instructionMem[address];
initial begin
$readmemh("verilog_instructions.hex",instructionMem);
end
endmodule | module instructionMemory(address,data); |
input [15:0] address;
output [15:0] data;
reg [15:0] instructionMem[15:0];
assign data = instructionMem[address];
initial begin
$readmemh("verilog_instructions.hex",instructionMem);
end
endmodule | 0 |
137,784 | data/full_repos/permissive/80257330/mainCpu.v | 80,257,330 | mainCpu.v | v | 44 | 95 | [] | [] | [] | null | line:147: before: "assign" | null | 1: b'%Error: data/full_repos/permissive/80257330/mainCpu.v:1: Cannot find include file: instructionMemory.v\n`include "instructionMemory.v" \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80257330,data/full_repos/permissive/80257330/instructionMemory.v\n data/full_repos/permissive/80257330,data/full_repos/permissive/80257330/instructionMemory.v.v\n data/full_repos/permissive/80257330,data/full_repos/permissive/80257330/instructionMemory.v.sv\n instructionMemory.v\n instructionMemory.v.v\n instructionMemory.v.sv\n obj_dir/instructionMemory.v\n obj_dir/instructionMemory.v.v\n obj_dir/instructionMemory.v.sv\n%Error: data/full_repos/permissive/80257330/mainCpu.v:2: Cannot find include file: decode.v\n`include "decode.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:3: Cannot find include file: controlUnit.v\n`include "controlUnit.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:4: Cannot find include file: alu.v\n`include "alu.v" \n ^~~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:5: Cannot find include file: registerFile.v\n`include "registerFile.v" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:6: Cannot find include file: pc.v\n`include "pc.v" \n ^~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:7: Cannot find include file: muxReg.v\n`include "muxReg.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:8: Cannot find include file: mux2.v\n`include "mux2.v" \n ^~~~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:9: Cannot find include file: dataMemory.v\n`include "dataMemory.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80257330/mainCpu.v:10: Cannot find include file: pushpop.v\n`include "pushpop.v" \n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/80257330/mainCpu.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80257330/mainCpu.v:27: Unsupported: Ignoring delay on this delayed statement.\n #99 clk = 0;\n ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 300,598 | module | module mainCpu;
wire[15:0] outaddress,regOut1,regOut2;
wire [15:0] registerIn,memout;
wire [11:0] jmpaddr;
reg clk;
wire[15:0] data,muxout1,muxout2,popout;
wire [3:0] opcode,reg0,src1,src2,muxsrc1out,muxreg0;
wire [1:0] aluselect;
wire [7:0] dataaddr;
wire isImmediate,writeEnable,writeMem,jmp,readMem,push,pop;
initial begin
clk=0;
end
always begin
#1 clk = 1;
#99 clk = 0;
end
pc p(jmpaddr,clk,jmp,outaddress);
instructionMemory i(outaddress,data);
decode d(data,opcode,reg0,src1,src2,jmpaddr,dataaddr);
controlunit cu(opcode,aluselect,isImmediate,writeEnable,readMem,writeMem,jmp,push,pop);
muxReg muxsrc1(src1,reg0,writeMem,muxsrc1out);
muxReg muxr0(reg0,src2,pop,muxreg0);
registerFile rf(muxreg0,writeEnable,clk,muxout2,regOut1,regOut2,muxsrc1out,src2,isImmediate);
pushpop pp(regOut2,push,pop,popout);
dataMemory m (dataaddr,regOut1,memout,readMem,writeMem,clk);
alu a(regOut1, regOut2, aluselect, registerIn);
mux2 mux(registerIn,memout,readMem,muxout1);
mux2 mux1(muxout1,popout,pop,muxout2);
endmodule | module mainCpu; |
wire[15:0] outaddress,regOut1,regOut2;
wire [15:0] registerIn,memout;
wire [11:0] jmpaddr;
reg clk;
wire[15:0] data,muxout1,muxout2,popout;
wire [3:0] opcode,reg0,src1,src2,muxsrc1out,muxreg0;
wire [1:0] aluselect;
wire [7:0] dataaddr;
wire isImmediate,writeEnable,writeMem,jmp,readMem,push,pop;
initial begin
clk=0;
end
always begin
#1 clk = 1;
#99 clk = 0;
end
pc p(jmpaddr,clk,jmp,outaddress);
instructionMemory i(outaddress,data);
decode d(data,opcode,reg0,src1,src2,jmpaddr,dataaddr);
controlunit cu(opcode,aluselect,isImmediate,writeEnable,readMem,writeMem,jmp,push,pop);
muxReg muxsrc1(src1,reg0,writeMem,muxsrc1out);
muxReg muxr0(reg0,src2,pop,muxreg0);
registerFile rf(muxreg0,writeEnable,clk,muxout2,regOut1,regOut2,muxsrc1out,src2,isImmediate);
pushpop pp(regOut2,push,pop,popout);
dataMemory m (dataaddr,regOut1,memout,readMem,writeMem,clk);
alu a(regOut1, regOut2, aluselect, registerIn);
mux2 mux(registerIn,memout,readMem,muxout1);
mux2 mux1(muxout1,popout,pop,muxout2);
endmodule | 0 |
137,785 | data/full_repos/permissive/80257330/mux2.v | 80,257,330 | mux2.v | v | 8 | 42 | [] | [] | [] | [(1, 7)] | null | data/verilator_xmls/430d6a87-6027-4505-9969-6e9be89416a5.xml | null | 300,599 | module | module mux2(input1,input2,enable,muxout);
input[15:0] input1,input2;
input enable;
output wire[15:0] muxout;
assign muxout=(enable)?input2:input1;
endmodule | module mux2(input1,input2,enable,muxout); |
input[15:0] input1,input2;
input enable;
output wire[15:0] muxout;
assign muxout=(enable)?input2:input1;
endmodule | 0 |
137,786 | data/full_repos/permissive/80257330/muxReg.v | 80,257,330 | muxReg.v | v | 11 | 43 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/0c9b1fa3-d55c-4d9e-a5b6-cf591c0c89b8.xml | null | 300,600 | module | module muxReg(input1,input2,writeMem,out);
input[3:0] input1;
input[3:0] input2;
input writeMem;
output wire[3:0] out;
assign out=(writeMem)?input2:input1;
endmodule | module muxReg(input1,input2,writeMem,out); |
input[3:0] input1;
input[3:0] input2;
input writeMem;
output wire[3:0] out;
assign out=(writeMem)?input2:input1;
endmodule | 0 |
137,787 | data/full_repos/permissive/80257330/pc.v | 80,257,330 | pc.v | v | 21 | 44 | [] | [] | [] | null | line:10: before: "assign" | data/verilator_xmls/484aacb9-e2f0-4224-a8b5-b836d926b96f.xml | null | 300,601 | module | module pc (addr,clk,jmp,out);
input [11:0] addr;
input clk,jmp;
output reg [15:0]out;
reg [15:0] keepaddr;
reg [15:0] signext;
integer i;
initial begin
out=16'hffff;
assign signext = { {4{addr[11]}}, addr };
end
always @(posedge clk) begin
if(jmp==0) begin
out=out+16'h0001;
end else begin
out=out+signext;
end
end
endmodule | module pc (addr,clk,jmp,out); |
input [11:0] addr;
input clk,jmp;
output reg [15:0]out;
reg [15:0] keepaddr;
reg [15:0] signext;
integer i;
initial begin
out=16'hffff;
assign signext = { {4{addr[11]}}, addr };
end
always @(posedge clk) begin
if(jmp==0) begin
out=out+16'h0001;
end else begin
out=out+signext;
end
end
endmodule | 0 |
137,788 | data/full_repos/permissive/80257330/pushpop.v | 80,257,330 | pushpop.v | v | 23 | 37 | [] | [] | [] | [(1, 22)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80257330/pushpop.v:16: Bit extraction of array[15:0] requires 4 bit index, not 16 bits.\n : ... In instance pushpop\n stack[addrin] = input1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80257330/pushpop.v:18: Bit extraction of array[15:0] requires 4 bit index, not 16 bits.\n : ... In instance pushpop\n out = stack[addrin];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,602 | module | module pushpop(input1,push,pop,out);
input[15:0] input1;
input push,pop;
output reg[15:0] out;
reg[15:0] stack[15:0];
reg [15:0] addrin,adddrout;
integer i;
initial begin
for(i=0;i<16;i=i+1)
stack[i] = 16'h0000;
addrin = 16'h0010;
end
always @(push or pop) begin
if(push) begin
addrin = addrin - 16'h0001;
stack[addrin] = input1;
end if(pop) begin
out = stack[addrin];
addrin = addrin + 16'h0001;
end
end
endmodule | module pushpop(input1,push,pop,out); |
input[15:0] input1;
input push,pop;
output reg[15:0] out;
reg[15:0] stack[15:0];
reg [15:0] addrin,adddrout;
integer i;
initial begin
for(i=0;i<16;i=i+1)
stack[i] = 16'h0000;
addrin = 16'h0010;
end
always @(push or pop) begin
if(push) begin
addrin = addrin - 16'h0001;
stack[addrin] = input1;
end if(pop) begin
out = stack[addrin];
addrin = addrin + 16'h0001;
end
end
endmodule | 0 |
137,789 | data/full_repos/permissive/80257330/registerFile.v | 80,257,330 | registerFile.v | v | 31 | 86 | [] | [] | [] | [(1, 30)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80257330/registerFile.v:24: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg2\' generates 4 bits.\n : ... In instance registerFile\n output2=reg2;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 300,603 | module | module registerFile(wR,writeEnable,clk,datain,output1,output2,reg1,reg2,isImmediate);
input [3:0] wR,reg1,reg2;
input writeEnable,clk;
input [15:0] datain;
output reg [15:0] output1,output2;
input isImmediate;
reg [15:0] register[0:15];
reg [15:0] extImm;
integer i;
initial begin
for(i=0;i<16;i=i+1)
register[i] = 16'h0000;
end
always @(posedge clk)
begin
if(writeEnable) begin
register[wR] <=datain;
end
end
always @(*)begin
output1 = register[reg1];
if (isImmediate==1)
output2=reg2;
else
output2=register[reg2];
end
endmodule | module registerFile(wR,writeEnable,clk,datain,output1,output2,reg1,reg2,isImmediate); |
input [3:0] wR,reg1,reg2;
input writeEnable,clk;
input [15:0] datain;
output reg [15:0] output1,output2;
input isImmediate;
reg [15:0] register[0:15];
reg [15:0] extImm;
integer i;
initial begin
for(i=0;i<16;i=i+1)
register[i] = 16'h0000;
end
always @(posedge clk)
begin
if(writeEnable) begin
register[wR] <=datain;
end
end
always @(*)begin
output1 = register[reg1];
if (isImmediate==1)
output2=reg2;
else
output2=register[reg2];
end
endmodule | 0 |
137,790 | data/full_repos/permissive/80302247/CE2704_HW10/5248021_HW10/CE2704_HW10/piggy.v | 80,302,247 | piggy.v | v | 394 | 81 | [] | [] | [] | null | line:196: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/80302247/CE2704_HW10/5248021_HW10/CE2704_HW10/piggy.v:196: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: Cannot continue\n' | 300,604 | module | module piggy(clk, reset, b1_in, b5_in, b10_in,
segment1, segment0, full_led);
input clk, reset;
input b1_in, b5_in, b10_in;
output [6:0]segment1;
output [6:0]segment0;
output full_led;
reg [6:0]segment1;
reg [6:0]segment0;
reg full_led;
reg tenths, ones, ntenths, nones, sum0, sum1;
always @ (posedge clk)
begin
if (reset)
begin
ntenths <=#1 0;
nones <=#1 0;
end
else
begin
ntenths <=#1 tenths;
nones <=#1 ones;
end
end
always @ (b1_in or b5_in or b10_in or ntenths or nones)
begin
if (b1_in==1)
if ((ntenths==9)&&(nones==9))
begin
tenths = ntenths;
nones = nones;
end
else if ((nones==9)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 0;
end
else
begin
tenths = ntenths;
nones = nones+1;
end
else if (b5_in==1)
if ((ntenths==9)&&(nones==9))
begin
tenths = ntenths;
nones = nones;
end
else if ((nones==5)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 0;
end
else if ((nones==6)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 1;
end
else if ((nones==7)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 2;
end
else if ((nones==8)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 3;
end
else if ((nones==9)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 4;
end
else
begin
tenths = ntenths;
nones = nones+5;
end
else if (b10_in==1)
if (ntenths==9)
begin
tenths = ntenths;
nones = nones;
end
else
begin
tenths = ntenths+1;
nones = nones;
end
else
begin
tenths = ntenths;
nones = nones;
end
end
always @ (b1_in or b5_in or b10_in or ntenths or nones)
begin
if (b1_in==1)
if ((ntenths==9)&&(nones==9))
begin
sum1 = ntenths;
sum0 = nones;
end
else if ((nones==9)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 0;
end
else
begin
sum1 = ntenths;
sum0 = nones+1;
end
else if (b5_in==1)
if ((ntenths==9)&&(nones==9))
begin
sum1 = ntenths;
sum0 = nones;
end
else if ((nones==5)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 0;
end
else if ((nones==6)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 1;
end
else if ((nones==7)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 2;
end
else if ((nones==8)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 3;
end
else if ((nones==9)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 4;
end
else
begin
sum1 = ntenths;
sum0 = nones+5;
end
else if (b10_in==1)
if (ntenths==9)
begin
sum1 = ntenths;
sum0 = nones;
end
else
begin
sum1 = ntenths+1;
sum0 = nones;
end
else
begin
sum1 = ntenths;
sum0 = nones;
end
end
begin
if ((sum1==9)&&(sum0==9))
full_led=1;
else
full_led=0;
end
begin
case (sum1)
0: begin
segment1[6]=0;
segment1[5]=1;
segment1[4]=1;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
1: begin
segment1[6]=0;
segment1[5]=0;
segment1[4]=0;
segment1[3]=0;
segment1[2]=1;
segment1[1]=1;
segment1[0]=0;
end
2: begin
segment1[6]=1;
segment1[5]=0;
segment1[4]=1;
segment1[3]=1;
segment1[2]=0;
segment1[1]=1;
segment1[0]=1;
end
3: begin
segment1[6]=1;
segment1[5]=0;
segment1[4]=0;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
4: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=0;
segment1[3]=0;
segment1[2]=1;
segment1[1]=1;
segment1[0]=0;
end
5: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=0;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
6: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=1;
segment1[3]=1;
segment1[2]=1;
segment1[1]=0;
segment1[0]=0;
end
7: begin
segment1[6]=0;
segment1[5]=0;
segment1[4]=0;
segment1[3]=0;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
8: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=1;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
9: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=0;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
endcase
end
begin
case (sum0)
0: begin
segment0[6]=0;
segment0[5]=1;
segment0[4]=1;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
1: begin
segment0[6]=0;
segment0[5]=0;
segment0[4]=0;
segment0[3]=0;
segment0[2]=1;
segment0[1]=1;
segment0[0]=0;
end
2: begin
segment0[6]=1;
segment0[5]=0;
segment0[4]=1;
segment0[3]=1;
segment0[2]=0;
segment0[1]=1;
segment0[0]=1;
end
3: begin
segment0[6]=1;
segment0[5]=0;
segment0[4]=0;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
4: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=0;
segment0[3]=0;
segment0[2]=1;
segment0[1]=1;
segment0[0]=0;
end
5: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=0;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
6: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=1;
segment0[3]=1;
segment0[2]=1;
segment0[1]=0;
segment0[0]=0;
end
7: begin
segment0[6]=0;
segment0[5]=0;
segment0[4]=0;
segment0[3]=0;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
8: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=1;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
9: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=0;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
endcase
end
endmodule | module piggy(clk, reset, b1_in, b5_in, b10_in,
segment1, segment0, full_led); |
input clk, reset;
input b1_in, b5_in, b10_in;
output [6:0]segment1;
output [6:0]segment0;
output full_led;
reg [6:0]segment1;
reg [6:0]segment0;
reg full_led;
reg tenths, ones, ntenths, nones, sum0, sum1;
always @ (posedge clk)
begin
if (reset)
begin
ntenths <=#1 0;
nones <=#1 0;
end
else
begin
ntenths <=#1 tenths;
nones <=#1 ones;
end
end
always @ (b1_in or b5_in or b10_in or ntenths or nones)
begin
if (b1_in==1)
if ((ntenths==9)&&(nones==9))
begin
tenths = ntenths;
nones = nones;
end
else if ((nones==9)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 0;
end
else
begin
tenths = ntenths;
nones = nones+1;
end
else if (b5_in==1)
if ((ntenths==9)&&(nones==9))
begin
tenths = ntenths;
nones = nones;
end
else if ((nones==5)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 0;
end
else if ((nones==6)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 1;
end
else if ((nones==7)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 2;
end
else if ((nones==8)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 3;
end
else if ((nones==9)&&(ntenths!=9))
begin
tenths = ntenths+1;
nones = 4;
end
else
begin
tenths = ntenths;
nones = nones+5;
end
else if (b10_in==1)
if (ntenths==9)
begin
tenths = ntenths;
nones = nones;
end
else
begin
tenths = ntenths+1;
nones = nones;
end
else
begin
tenths = ntenths;
nones = nones;
end
end
always @ (b1_in or b5_in or b10_in or ntenths or nones)
begin
if (b1_in==1)
if ((ntenths==9)&&(nones==9))
begin
sum1 = ntenths;
sum0 = nones;
end
else if ((nones==9)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 0;
end
else
begin
sum1 = ntenths;
sum0 = nones+1;
end
else if (b5_in==1)
if ((ntenths==9)&&(nones==9))
begin
sum1 = ntenths;
sum0 = nones;
end
else if ((nones==5)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 0;
end
else if ((nones==6)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 1;
end
else if ((nones==7)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 2;
end
else if ((nones==8)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 3;
end
else if ((nones==9)&&(ntenths!=9))
begin
sum1 = ntenths+1;
sum0 = 4;
end
else
begin
sum1 = ntenths;
sum0 = nones+5;
end
else if (b10_in==1)
if (ntenths==9)
begin
sum1 = ntenths;
sum0 = nones;
end
else
begin
sum1 = ntenths+1;
sum0 = nones;
end
else
begin
sum1 = ntenths;
sum0 = nones;
end
end
begin
if ((sum1==9)&&(sum0==9))
full_led=1;
else
full_led=0;
end
begin
case (sum1)
0: begin
segment1[6]=0;
segment1[5]=1;
segment1[4]=1;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
1: begin
segment1[6]=0;
segment1[5]=0;
segment1[4]=0;
segment1[3]=0;
segment1[2]=1;
segment1[1]=1;
segment1[0]=0;
end
2: begin
segment1[6]=1;
segment1[5]=0;
segment1[4]=1;
segment1[3]=1;
segment1[2]=0;
segment1[1]=1;
segment1[0]=1;
end
3: begin
segment1[6]=1;
segment1[5]=0;
segment1[4]=0;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
4: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=0;
segment1[3]=0;
segment1[2]=1;
segment1[1]=1;
segment1[0]=0;
end
5: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=0;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
6: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=1;
segment1[3]=1;
segment1[2]=1;
segment1[1]=0;
segment1[0]=0;
end
7: begin
segment1[6]=0;
segment1[5]=0;
segment1[4]=0;
segment1[3]=0;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
8: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=1;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
9: begin
segment1[6]=1;
segment1[5]=1;
segment1[4]=0;
segment1[3]=1;
segment1[2]=1;
segment1[1]=1;
segment1[0]=1;
end
endcase
end
begin
case (sum0)
0: begin
segment0[6]=0;
segment0[5]=1;
segment0[4]=1;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
1: begin
segment0[6]=0;
segment0[5]=0;
segment0[4]=0;
segment0[3]=0;
segment0[2]=1;
segment0[1]=1;
segment0[0]=0;
end
2: begin
segment0[6]=1;
segment0[5]=0;
segment0[4]=1;
segment0[3]=1;
segment0[2]=0;
segment0[1]=1;
segment0[0]=1;
end
3: begin
segment0[6]=1;
segment0[5]=0;
segment0[4]=0;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
4: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=0;
segment0[3]=0;
segment0[2]=1;
segment0[1]=1;
segment0[0]=0;
end
5: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=0;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
6: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=1;
segment0[3]=1;
segment0[2]=1;
segment0[1]=0;
segment0[0]=0;
end
7: begin
segment0[6]=0;
segment0[5]=0;
segment0[4]=0;
segment0[3]=0;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
8: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=1;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
9: begin
segment0[6]=1;
segment0[5]=1;
segment0[4]=0;
segment0[3]=1;
segment0[2]=1;
segment0[1]=1;
segment0[0]=1;
end
endcase
end
endmodule | 0 |
137,791 | data/full_repos/permissive/80302247/CE2704_HW10/hw10/signedmul.v | 80,302,247 | signedmul.v | v | 73 | 64 | [] | [] | [] | [(1, 72)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80302247/CE2704_HW10/hw10/signedmul.v:52: Operator NEGATE expects 15 bits on the LHS, but LHS\'s VARREF \'mc\' generates 14 bits.\n : ... In instance signedmul\n assign minus_mc = -mc;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 300,605 | module | module signedmul(clk, a_in, b_in, c);
parameter n = 8;
input clk;
input [n-1:0] a_in, b_in;
output [2*n-1:0] c;
reg [n-1:0] a, b;
always @(posedge clk) begin
a <= #100000 a_in;
b <= #100000 b_in;
end
wire a_min, b_min;
assign a_min = (a == {1'b1, {(n-1){1'b0}} } );
assign b_min = (b == {1'b1, {(n-1){1'b0}} } );
wire [n-1:0] minus_a, minus_b;
assign minus_a = -a;
assign minus_b = -b;
wire sa, sb;
wire [n-2:0] ma, mb;
assign sa = a[n-1];
assign ma = sa ? minus_a[n-2:0] : a[n-2:0];
assign sb = b[n-1];
assign mb = sb ? minus_b[n-2:0] : b[n-2:0];
wire sc;
assign sc = ( (a == 0)||(b == 0) )? 1'b0 : a[n-1] ^ b[n-1];
wire [2*(n-1)-1:0] mc;
assign mc = ma * mb;
wire [2*n-1:0] mul;
wire [2*(n-1):0] minus_mc;
assign minus_mc = -mc;
assign mul = sc ? {sc, minus_mc} : {sc, 1'b0, mc};
reg [2*n-1:0] cc;
always @(a_min or b_min or mul or minus_a or minus_b) begin
case({a_min, b_min})
2'b00: cc = mul;
2'b10: cc = {minus_b[n-1], minus_b, {(n-1){1'b0}} };
2'b01: cc = {minus_a[n-1], minus_a, {(n-1){1'b0}} };
default: cc = {2'b01, {(2*n-2){1'b0}} };
endcase
end
reg [2*n-1:0] c;
always @(posedge clk) begin
c <= #100000 cc;
end
endmodule | module signedmul(clk, a_in, b_in, c); |
parameter n = 8;
input clk;
input [n-1:0] a_in, b_in;
output [2*n-1:0] c;
reg [n-1:0] a, b;
always @(posedge clk) begin
a <= #100000 a_in;
b <= #100000 b_in;
end
wire a_min, b_min;
assign a_min = (a == {1'b1, {(n-1){1'b0}} } );
assign b_min = (b == {1'b1, {(n-1){1'b0}} } );
wire [n-1:0] minus_a, minus_b;
assign minus_a = -a;
assign minus_b = -b;
wire sa, sb;
wire [n-2:0] ma, mb;
assign sa = a[n-1];
assign ma = sa ? minus_a[n-2:0] : a[n-2:0];
assign sb = b[n-1];
assign mb = sb ? minus_b[n-2:0] : b[n-2:0];
wire sc;
assign sc = ( (a == 0)||(b == 0) )? 1'b0 : a[n-1] ^ b[n-1];
wire [2*(n-1)-1:0] mc;
assign mc = ma * mb;
wire [2*n-1:0] mul;
wire [2*(n-1):0] minus_mc;
assign minus_mc = -mc;
assign mul = sc ? {sc, minus_mc} : {sc, 1'b0, mc};
reg [2*n-1:0] cc;
always @(a_min or b_min or mul or minus_a or minus_b) begin
case({a_min, b_min})
2'b00: cc = mul;
2'b10: cc = {minus_b[n-1], minus_b, {(n-1){1'b0}} };
2'b01: cc = {minus_a[n-1], minus_a, {(n-1){1'b0}} };
default: cc = {2'b01, {(2*n-2){1'b0}} };
endcase
end
reg [2*n-1:0] c;
always @(posedge clk) begin
c <= #100000 cc;
end
endmodule | 0 |
137,793 | data/full_repos/permissive/80423202/cmd_buf.v | 80,423,202 | cmd_buf.v | v | 96 | 121 | [] | [] | [] | [(21, 95)] | null | data/verilator_xmls/f3de6bf4-7992-4b84-9d4a-03195e3e4a9a.xml | null | 300,608 | module | module cmd_buf
(
output reg [7:0]cmd,
output [51:0]param,
output package_complete,
output en_crc5,
output en_crc16,
input clk_cmd,
input rst_for_new_package,
input bits_in,
input sync
);
parameter QueryRep = 8'b0000_1100;
parameter ACK = 8'b0000_1101;
parameter Query = 8'b0011_1000;
parameter QueryAdjust = 8'b0011_1001;
parameter Select = 8'b0011_1010;
parameter NAK = 8'b1100_0000;
parameter Req_RN = 8'b1100_0001;
parameter Read = 8'b1100_0010;
parameter Kill = 8'b1100_0100;
parameter Lock = 8'b1100_0101;
reg cmd_complete;
reg [52:0]param_tmp;
assign param = param_tmp[51:0];
assign en_crc5 = (cmd_complete & cmd != Query)? 1'b0 : 1'b1;
assign en_crc16 = (cmd_complete & cmd != Select & cmd != Req_RN & cmd != Read & cmd != Kill & cmd != Lock)? 1'b0 : 1'b1;
assign package_complete = (cmd == QueryRep & param_tmp[2])? 1'b1 :
(cmd == ACK & param_tmp[16])? 1'b1 :
(cmd == Query & param_tmp[18])? 1'b1 :
(cmd == QueryAdjust & param_tmp[5])? 1'b1 :
(cmd == Select & param_tmp[52])? 1'b1 :
(cmd == NAK)? 1'b1 :
(cmd == Req_RN & param_tmp[32])? 1'b1 :
(cmd == Read & param_tmp[50])? 1'b1 :
(cmd == Kill & param_tmp[51])? 1'b1 :
(cmd == Lock & param_tmp[52])? 1'b1 : 1'b0;
always@(*) begin
if(cmd == QueryRep | cmd == ACK | cmd == Query |
cmd == QueryAdjust | cmd == Select | cmd == NAK |
cmd == Req_RN | cmd == Read | cmd == Kill | cmd == Lock) cmd_complete = 1'b1;
else cmd_complete = 1'b0;
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) cmd <= 8'b0000_0011;
else begin
if(sync & ~cmd_complete) cmd <= {cmd[6:0], bits_in};
end
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) param_tmp <= 53'b1;
else begin
if(cmd_complete & ~package_complete) param_tmp <= {param_tmp[51:0], bits_in};
end
end
endmodule | module cmd_buf
(
output reg [7:0]cmd,
output [51:0]param,
output package_complete,
output en_crc5,
output en_crc16,
input clk_cmd,
input rst_for_new_package,
input bits_in,
input sync
); |
parameter QueryRep = 8'b0000_1100;
parameter ACK = 8'b0000_1101;
parameter Query = 8'b0011_1000;
parameter QueryAdjust = 8'b0011_1001;
parameter Select = 8'b0011_1010;
parameter NAK = 8'b1100_0000;
parameter Req_RN = 8'b1100_0001;
parameter Read = 8'b1100_0010;
parameter Kill = 8'b1100_0100;
parameter Lock = 8'b1100_0101;
reg cmd_complete;
reg [52:0]param_tmp;
assign param = param_tmp[51:0];
assign en_crc5 = (cmd_complete & cmd != Query)? 1'b0 : 1'b1;
assign en_crc16 = (cmd_complete & cmd != Select & cmd != Req_RN & cmd != Read & cmd != Kill & cmd != Lock)? 1'b0 : 1'b1;
assign package_complete = (cmd == QueryRep & param_tmp[2])? 1'b1 :
(cmd == ACK & param_tmp[16])? 1'b1 :
(cmd == Query & param_tmp[18])? 1'b1 :
(cmd == QueryAdjust & param_tmp[5])? 1'b1 :
(cmd == Select & param_tmp[52])? 1'b1 :
(cmd == NAK)? 1'b1 :
(cmd == Req_RN & param_tmp[32])? 1'b1 :
(cmd == Read & param_tmp[50])? 1'b1 :
(cmd == Kill & param_tmp[51])? 1'b1 :
(cmd == Lock & param_tmp[52])? 1'b1 : 1'b0;
always@(*) begin
if(cmd == QueryRep | cmd == ACK | cmd == Query |
cmd == QueryAdjust | cmd == Select | cmd == NAK |
cmd == Req_RN | cmd == Read | cmd == Kill | cmd == Lock) cmd_complete = 1'b1;
else cmd_complete = 1'b0;
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) cmd <= 8'b0000_0011;
else begin
if(sync & ~cmd_complete) cmd <= {cmd[6:0], bits_in};
end
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) param_tmp <= 53'b1;
else begin
if(cmd_complete & ~package_complete) param_tmp <= {param_tmp[51:0], bits_in};
end
end
endmodule | 11 |
137,794 | data/full_repos/permissive/80423202/cmd_proc.v | 80,423,202 | cmd_proc.v | v | 1,091 | 263 | [] | [] | [] | [(21, 1090)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1049: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n bs_new_rn16 : reply_data = rn16[r_cnt - 5\'h08];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1055: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n bs_new_rn16_tran_if : reply_data = rn16[r_cnt - 5\'h08];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1056: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n gen_and_bs_new_handle : reply_data = handle[r_cnt - 5\'h08];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1057: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n bs_new_rn16_crc16 : reply_data = rn16[r_cnt - 5\'h08];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1060: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n else if(r_cnt < 5\'h16 & r_cnt > 5\'h5) reply_data = handle[r_cnt - 5\'h6];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1062: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n bs_handle : reply_data = handle[r_cnt - 5\'h08];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1064: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n else if(r_cnt < 5\'h17 & r_cnt > 5\'h6) reply_data = handle[r_cnt - 5\'h07];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1067: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n else if(r_cnt < 5\'h17 & r_cnt > 5\'h6) reply_data = handle[r_cnt - 5\'h07];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/cmd_proc.v:1071: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n : ... In instance cmd_proc\n else reply_data = handle[r_cnt];\n ^\n%Error: Exiting due to 9 warning(s)\n' | 300,609 | module | module cmd_proc
(
output reg reply_data,
output reg reply_complete,
output reg dr,
output reg [1:0]m,
output reg trext,
output reg en_2nd_clk_cp,
output reg en_tx,
output reg en_prng_idol,
output reg en_prng_act,
output reg en_crc16_for_rpy,
output reg en_if,
output reg [18:0]addr,
input clk_cp,
input clk_frm,
input rst_n,
input rst_for_new_package,
input [7:0]cmd,
input [51:0]param,
input crc_check_pass,
input [15:0]prn,
input pre_p_complete,
input p_complete,
input rd_data,
input rd_complete
);
parameter QueryRep = 8'b0000_1100;
parameter ACK = 8'b0000_1101;
parameter Query = 8'b0011_1000;
parameter QueryAdjust = 8'b0011_1001;
parameter Select = 8'b0011_1010;
parameter NAK = 8'b1100_0000;
parameter Req_RN = 8'b1100_0001;
parameter Read = 8'b1100_0010;
parameter Kill = 8'b1100_0100;
parameter Lock = 8'b1100_0101;
parameter Ready = 4'h0;
parameter Sloting = 4'h1;
parameter Arbitrate = 4'h2;
parameter Reply = 4'h3;
parameter Acknowledged = 4'h4;
parameter SlotTran = 4'h5;
parameter Open = 4'h6;
parameter Secured = 4'h7;
parameter Killing = 4'h8;
parameter Killed = 4'h9;
parameter do_nothing = 5'h00;
parameter set_sl_or_if = 5'h01;
parameter init_inventory = 5'h02;
parameter adj_q = 5'h03;
parameter dec_slot = 5'h04;
parameter bs_new_rn16 = 5'h05;
parameter reply_ack = 5'h06;
parameter bs_new_rn16_tran_if = 5'h07;
parameter adj_q_tran_if = 5'h08;
parameter dec_slot_tran_if = 5'h09;
parameter tran_if = 5'h0a;
parameter gen_and_bs_new_handle = 5'h0b;
parameter bs_new_rn16_crc16 = 5'h0c;
parameter bs_read_data = 5'h0d;
parameter bs_handle = 5'h0e;
parameter bs_header_kill = 5'h0f;
parameter bs_header_lock = 5'h10;
parameter bs_error_code = 5'h11;
wire clk_cp_n;
reg [7:0]cmd_checked;
reg [3:0]ps;
reg [3:0]ns;
reg [4:0]act;
reg mch;
reg [7:0]ptr;
reg trct;
reg [1:0]sl;
reg if_s0;
reg if_s1;
reg if_s2;
reg if_s3;
reg [1:0]session;
reg [3:0]q;
reg [14:0]slot;
reg [9:0]lock_act;
reg tid_lock;
reg epc_lock;
reg accs_lock;
reg kill_lock;
reg [4:0]act_reg;
reg [15:0]rn16;
reg [15:0]handle;
reg en_if_d;
reg [4:0]r_cnt;
reg [4:0]r_end;
always@(*) begin
if(cmd == Query | cmd == Select | cmd == Req_RN | cmd == Read | cmd == Kill | cmd == Lock) begin
if(crc_check_pass) cmd_checked = cmd;
else cmd_checked = 8'h00;
end
else cmd_checked = cmd;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) ps <= Ready;
else ps <= ns;
end
always@(*) begin
case(ps)
Ready : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else ns = Ready;
Sloting : if(slot == 15'b0) ns = Reply;
else ns = Arbitrate;
Arbitrate : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Sloting;
else ns = Arbitrate;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Sloting;
else ns = Arbitrate;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Arbitrate;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Arbitrate;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Arbitrate;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Arbitrate;
else ns = Ready;
end
else ns = Arbitrate;
Reply : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Arbitrate;
else ns = Reply;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Sloting;
else ns = Reply;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) ns = Acknowledged;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Arbitrate;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Reply;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Reply;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Reply;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Reply;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Arbitrate;
else if(cmd_checked == Kill) ns = Arbitrate;
else if(cmd_checked == Lock) ns = Arbitrate;
else ns = Reply;
Acknowledged : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Acknowledged;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Acknowledged;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) ns = Acknowledged;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) begin
if(param[31:16] == rn16) ns = Secured;
else ns = Acknowledged;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Acknowledged;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Acknowledged;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Acknowledged;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Acknowledged;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Arbitrate;
else if(cmd_checked == Kill) ns = Arbitrate;
else if(cmd_checked == Lock) ns = Arbitrate;
else ns = Acknowledged;
SlotTran : if(slot == 15'b0) ns = Reply;
else ns = Arbitrate;
Open : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Open;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Open;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == handle) ns = Open;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Open;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Open;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Open;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Open;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Open;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Open;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) ns = Killing;
else ns = Arbitrate;
end
else if(cmd_checked == Lock) ns = Open;
else ns = Open;
Secured : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Secured;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Secured;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == handle) ns = Secured;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Secured;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Secured;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Secured;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Secured;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Secured;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Secured;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) ns = Killing;
else ns = Arbitrate;
end
else if(cmd_checked == Lock) ns = Secured;
else ns = Secured;
Killing : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == Req_RN) ns = Killing;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'h06cc & param[31:16] == handle) ns = Killed;
else ns = Arbitrate;
end
else ns = Arbitrate;
Killed : ns = Killed;
default : ns = Arbitrate;
endcase
end
always@(*) begin
case(ps)
Ready : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Sloting : if(slot == 15'b0) act = bs_new_rn16;
else act = do_nothing;
Arbitrate : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Reply : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Acknowledged : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == rn16) act = gen_and_bs_new_handle;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
SlotTran : if(param[11:10] == session) begin
if(slot == 15'b0) act = bs_new_rn16_tran_if;
else act = tran_if;
end
else act = do_nothing;
Open : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else if(cmd_checked == Read) begin
case(param[49:48])
2'b00 : if(param[39:32] == 8'h0) begin
if(~kill_lock & ~accs_lock & param[47:40] < 8'h3) act = bs_read_data;
else act = bs_error_code;
end
else begin
if((~kill_lock & param[47:40] < 8'h2 & (param[47:40] + param[39:32] < 8'h3)) |
(~accs_lock & param[47:40] < 8'h4 & param[47:40] > 8'h1 & (param[47:40] + param[39:32] < 8'h5)) |
(~kill_lock & ~accs_lock & (param[47:40] + param[39:32] < 8'h5))) act = bs_read_data;
else act = bs_error_code;
end
2'b01 : if(param[39:32] == 8'h0) begin
if(~epc_lock & (param[47:40] < 8'h15)) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~epc_lock & ((param[47:40] + param[39:32]) < 8'hf)) act = bs_read_data;
else act = bs_error_code;
end
2'b10 : if(param[39:32] == 8'h0) begin
if(~tid_lock & param[47:40] < 8'h2) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~tid_lock & ((param[47:40] + param[39:32]) < 8'h3)) act = bs_read_data;
else act = bs_error_code;
end
2'b11 : act = bs_error_code;
endcase
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) act = bs_handle;
else act = do_nothing;
end
else act = do_nothing;
Secured : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else if(cmd_checked == Read) begin
case(param[49:48])
2'b00 : if(param[39:32] == 8'h0) begin
if(~kill_lock & ~accs_lock & param[47:40] < 8'h3) act = bs_read_data;
else act = bs_error_code;
end
else begin
if((~kill_lock & param[47:40] < 8'h2 & (param[47:40] + param[39:32] < 8'h3)) |
(~accs_lock & param[47:40] < 8'h4 & param[47:40] > 8'h1 & (param[47:40] + param[39:32] < 8'h5)) |
(~kill_lock & ~accs_lock & (param[47:40] + param[39:32] < 8'h5))) act = bs_read_data;
else act = bs_error_code;
end
2'b01 : if(param[39:32] == 8'h0) begin
if(~epc_lock & (param[47:40] < 8'h15)) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~epc_lock & ((param[47:40] + param[39:32]) < 8'hf)) act = bs_read_data;
else act = bs_error_code;
end
2'b10 : if(param[39:32] == 8'h0) begin
if(~tid_lock & param[47:40] < 8'h2) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~tid_lock & ((param[47:40] + param[39:32]) < 8'h3)) act = bs_read_data;
else act = bs_error_code;
end
2'b11 : act = bs_error_code;
endcase
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) act = bs_handle;
else act = do_nothing;
end
else if(cmd_checked == Lock) begin
if(param[43:42] != 2'b00 | (({param[50], param[40]} == 2'b10) & lock_act[8]) | (({param[48], param[38]} == 2'b10) & lock_act[6]) | (({param[46], param[36]} == 2'b10) & lock_act[4]) | (({param[44], param[34]} == 2'b10) & lock_act[2])) act = bs_error_code;
else act = bs_header_lock;
end
else act = do_nothing;
Killing : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'h06cc & param[31:16] == handle) act = bs_header_kill;
else act = do_nothing;
end
else act = do_nothing;
Killed : act = do_nothing;
default : act = do_nothing;
endcase
end
always@(*) begin
if(act == set_sl_or_if) begin
if(param[45:44] == 2'b01 & param[43:36] < 8'b1100_0000 & ((param[43:36] - param[35:28]) > 8'b0)) mch = 1'b1;
else if(param[45:44] == 2'b10 & param[43:36] < 8'b0010_0000 & ((param[43:36] - param[35:28]) > 8'b0)) mch = 1'b1;
end
else mch = 1'b0;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) ptr <= 8'b0;
else if(act == set_sl_or_if) ptr <= param[43:36] - param[35:28];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) trct <= 1'b0;
else if(act == set_sl_or_if) trct <= param[16];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) sl <= 2'b10;
else if(act == set_sl_or_if & param[51:49] == 3'b100) begin
if(mch) begin
case(param[48:46])
3'b000 : sl <= 2'b11;
3'b001 : sl <= 2'b11;
3'b011 : sl <= ~sl;
3'b100 : sl <= 2'b10;
3'b101 : sl <= 2'b10;
endcase
end
else begin
case(param[48:46])
3'b000 : sl <= 2'b10;
3'b010 : sl <= 2'b10;
3'b100 : sl <= 2'b11;
3'b110 : sl <= 2'b11;
3'b111 : sl <= ~sl;
endcase
end
end
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s0 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b000) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s0 <= 1'b0;
3'b001 : if_s0 <= 1'b0;
3'b011 : if_s0 <= ~if_s0;
3'b100 : if_s0 <= 1'b0;
3'b101 : if_s0 <= 1'b0;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s0 <= 1'b1;
3'b010 : if_s0 <= 1'b1;
3'b100 : if_s0 <= 1'b0;
3'b110 : if_s0 <= 1'b0;
3'b111 : if_s0 <= ~if_s0;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == dec_slot_tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == adj_q_tran_if & session == 2'b00) if_s0 <= ~if_s0;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s1 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b001) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s1 <= 1'b0;
3'b001 : if_s1 <= 1'b0;
3'b011 : if_s1 <= ~if_s1;
3'b100 : if_s1 <= 1'b1;
3'b101 : if_s1 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s1 <= 1'b1;
3'b010 : if_s1 <= 1'b1;
3'b100 : if_s1 <= 1'b0;
3'b110 : if_s1 <= 1'b0;
3'b111 : if_s1 <= ~if_s1;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == dec_slot_tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == adj_q_tran_if & session == 2'b01) if_s1 <= ~if_s1;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s2 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b010) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s2 <= 1'b0;
3'b001 : if_s2 <= 1'b0;
3'b011 : if_s2 <= ~if_s2;
3'b100 : if_s2 <= 1'b1;
3'b101 : if_s2 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s2 <= 1'b1;
3'b010 : if_s2 <= 1'b1;
3'b100 : if_s2 <= 1'b0;
3'b110 : if_s2 <= 1'b0;
3'b111 : if_s2 <= ~if_s2;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == dec_slot_tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == adj_q_tran_if & session == 2'b10) if_s2 <= ~if_s2;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s3 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b011) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s3 <= 1'b0;
3'b001 : if_s3 <= 1'b0;
3'b011 : if_s3 <= ~if_s3;
3'b100 : if_s3 <= 1'b1;
3'b101 : if_s3 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s3 <= 1'b1;
3'b010 : if_s3 <= 1'b1;
3'b100 : if_s3 <= 1'b0;
3'b110 : if_s3 <= 1'b0;
3'b111 : if_s3 <= ~if_s3;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == dec_slot_tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == adj_q_tran_if & session == 2'b11) if_s3 <= ~if_s3;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) dr <= 1'b0;
else if(act == init_inventory) dr <= param[17];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) m <= 2'b00;
else if(act == init_inventory) m <= param[16:15];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) trext <= 1'b0;
else if(act == init_inventory) trext <= param[14];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) session <= 2'b00;
else if(act == init_inventory) session <= param[11:10];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) q <= 4'b0;
else if(act == init_inventory) q <= param[8:5];
else if(act == adj_q | act == adj_q_tran_if) begin
if(param[2:0] == 3'b110) q <= q + 4'b1;
else if(param[2:0] == 3'b011) q <= q - 4'b1;
end
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) slot <= 15'h2ac7;
else if(act == init_inventory) begin
case(param[8:5])
4'h0 : slot <= 15'b0;
4'h1 : slot <= {14'b0, prn[0]};
4'h2 : slot <= {13'b0, prn[1:0]};
4'h3 : slot <= {12'b0, prn[2:0]};
4'h4 : slot <= {11'b0, prn[3:0]};
4'h5 : slot <= {10'b0, prn[4:0]};
4'h6 : slot <= {9'b0, prn[5:0]};
4'h7 : slot <= {8'b0, prn[6:0]};
4'h8 : slot <= {7'b0, prn[7:0]};
4'h9 : slot <= {6'b0, prn[8:0]};
4'ha : slot <= {5'b0, prn[9:0]};
4'hb : slot <= {4'b0, prn[10:0]};
4'hc : slot <= {3'b0, prn[11:0]};
4'hd : slot <= {2'b0, prn[12:0]};
4'he : slot <= {1'b0, prn[13:0]};
4'hf : slot <= prn[14:0];
endcase
end
else if(act == adj_q | act == adj_q_tran_if) begin
if(param[2:0] == 3'b110) begin
case(q)
4'hf : slot <= 15'b0;
4'h0 : slot <= {14'b0, prn[0]};
4'h1 : slot <= {13'b0, prn[1:0]};
4'h2 : slot <= {12'b0, prn[2:0]};
4'h3 : slot <= {11'b0, prn[3:0]};
4'h4 : slot <= {10'b0, prn[4:0]};
4'h5 : slot <= {9'b0, prn[5:0]};
4'h6 : slot <= {8'b0, prn[6:0]};
4'h7 : slot <= {7'b0, prn[7:0]};
4'h8 : slot <= {6'b0, prn[8:0]};
4'h9 : slot <= {5'b0, prn[9:0]};
4'ha : slot <= {4'b0, prn[10:0]};
4'hb : slot <= {3'b0, prn[11:0]};
4'hc : slot <= {2'b0, prn[12:0]};
4'hd : slot <= {1'b0, prn[13:0]};
4'he : slot <= prn[14:0];
endcase
end
else if(param[2:0] == 3'b011) begin
case(q)
4'h1 : slot <= 15'b0;
4'h2 : slot <= {14'b0, prn[0]};
4'h3 : slot <= {13'b0, prn[1:0]};
4'h4 : slot <= {12'b0, prn[2:0]};
4'h5 : slot <= {11'b0, prn[3:0]};
4'h6 : slot <= {10'b0, prn[4:0]};
4'h7 : slot <= {9'b0, prn[5:0]};
4'h8 : slot <= {8'b0, prn[6:0]};
4'h9 : slot <= {7'b0, prn[7:0]};
4'ha : slot <= {6'b0, prn[8:0]};
4'hb : slot <= {5'b0, prn[9:0]};
4'hc : slot <= {4'b0, prn[10:0]};
4'hd : slot <= {3'b0, prn[11:0]};
4'he : slot <= {2'b0, prn[12:0]};
4'hf : slot <= {1'b0, prn[13:0]};
4'h0 : slot <= prn[14:0];
endcase
end
end
else if(act == dec_slot | act == dec_slot_tran_if) slot <= slot - 15'b1;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) lock_act <= 10'b00_0000_0011;
else begin
if(act == bs_header_lock) begin
if(param[43:42] != 2'b00) lock_act <= lock_act;
else if(({param[50], param[40]} == 2'b10) & lock_act[8]) lock_act <= lock_act;
else if(({param[48], param[38]} == 2'b10) & lock_act[6]) lock_act <= lock_act;
else if(({param[46], param[36]} == 2'b10) & lock_act[4]) lock_act <= lock_act;
else if(({param[44], param[34]} == 2'b10) & lock_act[2]) lock_act <= lock_act;
else begin
if(param[51]) lock_act[9] <= param[41];
if(param[50]) lock_act[8] <= param[40];
if(param[49]) lock_act[7] <= param[39];
if(param[48]) lock_act[6] <= param[38];
if(param[47]) lock_act[5] <= param[37];
if(param[46]) lock_act[4] <= param[36];
if(param[45]) lock_act[3] <= param[35];
if(param[44]) lock_act[2] <= param[34];
end
end
end
end
always@(*) begin
case(lock_act[3:2])
2'b00 : if((ps == Open) | (ps == Secured)) tid_lock = 0;
else tid_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) tid_lock = 0;
else tid_lock = 1;
2'b10 : if(ps == Secured) tid_lock = 0;
else tid_lock = 1;
2'b11 : tid_lock = 1;
endcase
end
always@(*) begin
case(lock_act[5:4])
2'b00 : if((ps == Open) | (ps == Secured)) epc_lock = 0;
else epc_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) epc_lock = 0;
else epc_lock = 1;
2'b10 : if(ps == Secured) epc_lock = 0;
else epc_lock = 1;
2'b11 : epc_lock = 1;
endcase
end
always@(*) begin
case(lock_act[7:6])
2'b00 : if((ps == Open) | (ps == Secured)) accs_lock = 0;
else accs_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) accs_lock = 0;
else accs_lock = 1;
2'b10 : if(ps == Secured) accs_lock = 0;
else accs_lock = 1;
2'b11 : accs_lock = 1;
endcase
end
always@(*) begin
case(lock_act[9:8])
2'b00 : if((ps == Open) | (ps == Secured)) kill_lock = 0;
else kill_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) kill_lock = 0;
else kill_lock = 1;
2'b10 : if(ps == Secured) kill_lock = 0;
else kill_lock = 1;
2'b11 : kill_lock = 1;
endcase
end
always@(posedge clk_cp or negedge rst_for_new_package) begin
if(~rst_for_new_package) act_reg <= 5'h0;
else act_reg <= act;
end
always@(*) begin
if(act_reg == init_inventory | act_reg == adj_q | act_reg == dec_slot | act_reg == adj_q_tran_if | act_reg == dec_slot_tran_if) en_2nd_clk_cp = 1'b1;
else en_2nd_clk_cp = 1'b0;
end
always@(*) begin
if(ps == Ready) en_prng_idol = 1'b1;
else en_prng_idol = 1'b0;
end
always@(*) begin
if(act_reg == bs_new_rn16 | act_reg == bs_new_rn16_tran_if | act_reg == gen_and_bs_new_handle | act_reg == bs_new_rn16_crc16) en_prng_act = 1'b1;
else en_prng_act = 1'b0;
end
always@(*) begin
case(act_reg)
bs_new_rn16 : en_tx = 1'b1;
reply_ack : en_tx = 1'b1;
bs_new_rn16_tran_if : en_tx = 1'b1;
gen_and_bs_new_handle : en_tx = 1'b1;
bs_new_rn16_crc16 : en_tx = 1'b1;
bs_read_data : en_tx = 1'b1;
bs_handle : en_tx = 1'b1;
bs_header_kill : en_tx = 1'b1;
bs_header_lock : en_tx = 1'b1;
bs_error_code : en_tx = 1'b1;
default : en_tx = 1'b0;
endcase
end
always@(*) begin
if(act_reg == reply_ack) begin
if(~trct & pre_p_complete) en_if = 1'b1;
else if(trct & p_complete & (r_cnt < r_end + 5'h02)) en_if = 1'b1;
else en_if = 1'b0;
end
else if(act_reg == bs_read_data) begin
if(p_complete) en_if = 1'b1;
else en_if = 1'b0;
end
else en_if = 1'b0;
end
always@(*) begin
if(p_complete & (act_reg == reply_ack | act_reg == gen_and_bs_new_handle | act_reg == bs_new_rn16_crc16 | act_reg == bs_read_data |
act_reg == bs_handle | act_reg == bs_header_kill | act_reg == bs_header_lock)) en_crc16_for_rpy = 1'b1;
else en_crc16_for_rpy = 1'b0;
end
always@(*) begin
if(act_reg == reply_ack) begin
if(~trct) addr = {1'b0, 2'b01, 8'b0, 8'b0};
else addr = {1'b0, 2'b01, ptr, 8'b0};
end
else if(act_reg == bs_read_data) addr = {1'b1, param[49:32]};
else addr = 19'b0;
end
assign clk_cp_n = ~clk_cp;
always@(posedge clk_cp_n or negedge rst_n) begin
if(~rst_n) rn16 <= 16'hac70;
else if(act_reg == bs_new_rn16 | act_reg == bs_new_rn16_tran_if | act_reg == bs_new_rn16_crc16) rn16 <= prn[15:0];
end
always@(posedge clk_cp_n or negedge rst_n) begin
if(~rst_n) handle <= 16'hff31;
else if(act_reg == gen_and_bs_new_handle) handle <= prn[15:0];
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) en_if_d <= 1'b0;
else en_if_d <= en_if;
end
wire en_r_cnt;
assign en_r_cnt = ~en_if_d | rd_complete;
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) r_cnt <= 5'h17;
else if(p_complete & en_r_cnt) begin
if(r_cnt != r_end) r_cnt <= r_cnt - 1;
else r_cnt <= r_cnt;
end
end
always@(*) begin
case(act_reg)
bs_new_rn16 : r_end = 5'h08;
reply_ack : if(~trct) r_end = 5'h17;
else r_end = 5'h12;
bs_new_rn16_tran_if : r_end = 5'h08;
gen_and_bs_new_handle : r_end = 5'h08;
bs_new_rn16_crc16 : r_end = 5'h08;
bs_read_data : r_end = 5'h06;
bs_handle : r_end = 5'h08;
bs_header_kill : r_end = 5'h07;
bs_header_lock : r_end = 5'h07;
bs_error_code : r_end = 5'h00;
default : r_end = 5'h00;
endcase
end
always@(*) begin
case(act_reg)
bs_new_rn16 : reply_data = rn16[r_cnt - 5'h08];
reply_ack : if(~trct) reply_data = rd_data;
else begin
if(r_cnt > 5'h12) reply_data = 1'b0;
else reply_data = rd_data;
end
bs_new_rn16_tran_if : reply_data = rn16[r_cnt - 5'h08];
gen_and_bs_new_handle : reply_data = handle[r_cnt - 5'h08];
bs_new_rn16_crc16 : reply_data = rn16[r_cnt - 5'h08];
bs_read_data : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt == 5'h16) reply_data = rd_data;
else if(r_cnt < 5'h16 & r_cnt > 5'h5) reply_data = handle[r_cnt - 5'h6];
else reply_data = 1'b0;
bs_handle : reply_data = handle[r_cnt - 5'h08];
bs_header_kill : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt < 5'h17 & r_cnt > 5'h6) reply_data = handle[r_cnt - 5'h07];
else reply_data = 1'b0;
bs_header_lock : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt < 5'h17 & r_cnt > 5'h6) reply_data = handle[r_cnt - 5'h07];
else reply_data = 1'b0;
bs_error_code : if(r_cnt > 5'h13) reply_data = 1'b0;
else if(r_cnt < 5'h14 & r_cnt > 5'h0f) reply_data = 1'b1;
else reply_data = handle[r_cnt];
default : reply_data = 1'b0;
endcase
end
always@(*) begin
if(act_reg == reply_ack) begin
if(rd_complete) reply_complete = 1'b1;
else reply_complete = 1'b0;
end
else begin
if(r_cnt == r_end) reply_complete = 1'b1;
else reply_complete = 1'b0;
end
end
endmodule | module cmd_proc
(
output reg reply_data,
output reg reply_complete,
output reg dr,
output reg [1:0]m,
output reg trext,
output reg en_2nd_clk_cp,
output reg en_tx,
output reg en_prng_idol,
output reg en_prng_act,
output reg en_crc16_for_rpy,
output reg en_if,
output reg [18:0]addr,
input clk_cp,
input clk_frm,
input rst_n,
input rst_for_new_package,
input [7:0]cmd,
input [51:0]param,
input crc_check_pass,
input [15:0]prn,
input pre_p_complete,
input p_complete,
input rd_data,
input rd_complete
); |
parameter QueryRep = 8'b0000_1100;
parameter ACK = 8'b0000_1101;
parameter Query = 8'b0011_1000;
parameter QueryAdjust = 8'b0011_1001;
parameter Select = 8'b0011_1010;
parameter NAK = 8'b1100_0000;
parameter Req_RN = 8'b1100_0001;
parameter Read = 8'b1100_0010;
parameter Kill = 8'b1100_0100;
parameter Lock = 8'b1100_0101;
parameter Ready = 4'h0;
parameter Sloting = 4'h1;
parameter Arbitrate = 4'h2;
parameter Reply = 4'h3;
parameter Acknowledged = 4'h4;
parameter SlotTran = 4'h5;
parameter Open = 4'h6;
parameter Secured = 4'h7;
parameter Killing = 4'h8;
parameter Killed = 4'h9;
parameter do_nothing = 5'h00;
parameter set_sl_or_if = 5'h01;
parameter init_inventory = 5'h02;
parameter adj_q = 5'h03;
parameter dec_slot = 5'h04;
parameter bs_new_rn16 = 5'h05;
parameter reply_ack = 5'h06;
parameter bs_new_rn16_tran_if = 5'h07;
parameter adj_q_tran_if = 5'h08;
parameter dec_slot_tran_if = 5'h09;
parameter tran_if = 5'h0a;
parameter gen_and_bs_new_handle = 5'h0b;
parameter bs_new_rn16_crc16 = 5'h0c;
parameter bs_read_data = 5'h0d;
parameter bs_handle = 5'h0e;
parameter bs_header_kill = 5'h0f;
parameter bs_header_lock = 5'h10;
parameter bs_error_code = 5'h11;
wire clk_cp_n;
reg [7:0]cmd_checked;
reg [3:0]ps;
reg [3:0]ns;
reg [4:0]act;
reg mch;
reg [7:0]ptr;
reg trct;
reg [1:0]sl;
reg if_s0;
reg if_s1;
reg if_s2;
reg if_s3;
reg [1:0]session;
reg [3:0]q;
reg [14:0]slot;
reg [9:0]lock_act;
reg tid_lock;
reg epc_lock;
reg accs_lock;
reg kill_lock;
reg [4:0]act_reg;
reg [15:0]rn16;
reg [15:0]handle;
reg en_if_d;
reg [4:0]r_cnt;
reg [4:0]r_end;
always@(*) begin
if(cmd == Query | cmd == Select | cmd == Req_RN | cmd == Read | cmd == Kill | cmd == Lock) begin
if(crc_check_pass) cmd_checked = cmd;
else cmd_checked = 8'h00;
end
else cmd_checked = cmd;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) ps <= Ready;
else ps <= ns;
end
always@(*) begin
case(ps)
Ready : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else ns = Ready;
Sloting : if(slot == 15'b0) ns = Reply;
else ns = Arbitrate;
Arbitrate : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Sloting;
else ns = Arbitrate;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Sloting;
else ns = Arbitrate;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Arbitrate;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Arbitrate;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Arbitrate;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Arbitrate;
else ns = Ready;
end
else ns = Arbitrate;
Reply : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = Sloting;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Arbitrate;
else ns = Reply;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Sloting;
else ns = Reply;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) ns = Acknowledged;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Arbitrate;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Reply;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Reply;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Reply;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Reply;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Arbitrate;
else if(cmd_checked == Kill) ns = Arbitrate;
else if(cmd_checked == Lock) ns = Arbitrate;
else ns = Reply;
Acknowledged : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Acknowledged;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Acknowledged;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) ns = Acknowledged;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) begin
if(param[31:16] == rn16) ns = Secured;
else ns = Acknowledged;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Acknowledged;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Acknowledged;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Acknowledged;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Acknowledged;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Arbitrate;
else if(cmd_checked == Kill) ns = Arbitrate;
else if(cmd_checked == Lock) ns = Arbitrate;
else ns = Acknowledged;
SlotTran : if(slot == 15'b0) ns = Reply;
else ns = Arbitrate;
Open : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Open;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Open;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == handle) ns = Open;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Open;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Open;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Open;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Open;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Open;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Open;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) ns = Killing;
else ns = Arbitrate;
end
else if(cmd_checked == Lock) ns = Open;
else ns = Open;
Secured : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) ns = Ready;
else ns = Secured;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) ns = Ready;
else ns = Secured;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == handle) ns = Secured;
else ns = Arbitrate;
end
else if(cmd_checked == NAK) ns = Arbitrate;
else if(cmd_checked == Req_RN) ns = Secured;
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) ns = Secured;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) ns = Secured;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) ns = Secured;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) ns = Secured;
else ns = Ready;
end
else if(cmd_checked == Read) ns = Secured;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) ns = Killing;
else ns = Arbitrate;
end
else if(cmd_checked == Lock) ns = Secured;
else ns = Secured;
Killing : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) ns = SlotTran;
else ns = Ready;
end
else if(cmd_checked == Req_RN) ns = Killing;
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'h06cc & param[31:16] == handle) ns = Killed;
else ns = Arbitrate;
end
else ns = Arbitrate;
Killed : ns = Killed;
default : ns = Arbitrate;
endcase
end
always@(*) begin
case(ps)
Ready : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Sloting : if(slot == 15'b0) act = bs_new_rn16;
else act = do_nothing;
Arbitrate : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Reply : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
Acknowledged : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == rn16) act = gen_and_bs_new_handle;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else act = do_nothing;
SlotTran : if(param[11:10] == session) begin
if(slot == 15'b0) act = bs_new_rn16_tran_if;
else act = tran_if;
end
else act = do_nothing;
Open : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else if(cmd_checked == Read) begin
case(param[49:48])
2'b00 : if(param[39:32] == 8'h0) begin
if(~kill_lock & ~accs_lock & param[47:40] < 8'h3) act = bs_read_data;
else act = bs_error_code;
end
else begin
if((~kill_lock & param[47:40] < 8'h2 & (param[47:40] + param[39:32] < 8'h3)) |
(~accs_lock & param[47:40] < 8'h4 & param[47:40] > 8'h1 & (param[47:40] + param[39:32] < 8'h5)) |
(~kill_lock & ~accs_lock & (param[47:40] + param[39:32] < 8'h5))) act = bs_read_data;
else act = bs_error_code;
end
2'b01 : if(param[39:32] == 8'h0) begin
if(~epc_lock & (param[47:40] < 8'h15)) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~epc_lock & ((param[47:40] + param[39:32]) < 8'hf)) act = bs_read_data;
else act = bs_error_code;
end
2'b10 : if(param[39:32] == 8'h0) begin
if(~tid_lock & param[47:40] < 8'h2) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~tid_lock & ((param[47:40] + param[39:32]) < 8'h3)) act = bs_read_data;
else act = bs_error_code;
end
2'b11 : act = bs_error_code;
endcase
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) act = bs_handle;
else act = do_nothing;
end
else act = do_nothing;
Secured : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == QueryRep) begin
if(param[1:0] == session) act = dec_slot_tran_if;
else act = do_nothing;
end
else if(cmd_checked == QueryAdjust) begin
if(param[4:3] == session) act = adj_q_tran_if;
else act = do_nothing;
end
else if(cmd_checked == ACK) begin
if(param[15:0] == rn16) act = reply_ack;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Select) begin
if(param[51:49] == 3'b101 | param[51:49] == 3'b110 | param[51:49] == 3'b111) act = do_nothing;
else if(param[45:44] == 2'b00 & param[43:36] != 8'b0) act = do_nothing;
else if(param[45:44] == 2'b00 & param[35:28] != 8'b0000_1000) act = do_nothing;
else if(param[16] & (param[51:49] != 3'b100 | param[45:44] != 2'b01)) act = do_nothing;
else act = set_sl_or_if;
end
else if(cmd_checked == Read) begin
case(param[49:48])
2'b00 : if(param[39:32] == 8'h0) begin
if(~kill_lock & ~accs_lock & param[47:40] < 8'h3) act = bs_read_data;
else act = bs_error_code;
end
else begin
if((~kill_lock & param[47:40] < 8'h2 & (param[47:40] + param[39:32] < 8'h3)) |
(~accs_lock & param[47:40] < 8'h4 & param[47:40] > 8'h1 & (param[47:40] + param[39:32] < 8'h5)) |
(~kill_lock & ~accs_lock & (param[47:40] + param[39:32] < 8'h5))) act = bs_read_data;
else act = bs_error_code;
end
2'b01 : if(param[39:32] == 8'h0) begin
if(~epc_lock & (param[47:40] < 8'h15)) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~epc_lock & ((param[47:40] + param[39:32]) < 8'hf)) act = bs_read_data;
else act = bs_error_code;
end
2'b10 : if(param[39:32] == 8'h0) begin
if(~tid_lock & param[47:40] < 8'h2) act = bs_read_data;
else act = bs_error_code;
end
else begin
if(~tid_lock & ((param[47:40] + param[39:32]) < 8'h3)) act = bs_read_data;
else act = bs_error_code;
end
2'b11 : act = bs_error_code;
endcase
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'hd357 & param[31:16] == handle) act = bs_handle;
else act = do_nothing;
end
else if(cmd_checked == Lock) begin
if(param[43:42] != 2'b00 | (({param[50], param[40]} == 2'b10) & lock_act[8]) | (({param[48], param[38]} == 2'b10) & lock_act[6]) | (({param[46], param[36]} == 2'b10) & lock_act[4]) | (({param[44], param[34]} == 2'b10) & lock_act[2])) act = bs_error_code;
else act = bs_header_lock;
end
else act = do_nothing;
Killing : if(cmd_checked == Query) begin
if((param[11:9] == {2'b00, if_s0} | param[11:9] == {2'b01, if_s1} | param[11:9] == {2'b10, if_s2} | param[11:9] == {2'b11, if_s3}) & (~param[13] | param[13:12] == sl)) act = init_inventory;
else act = do_nothing;
end
else if(cmd_checked == Req_RN) begin
if(param[31:16] == handle) act = bs_new_rn16_crc16;
else act = do_nothing;
end
else if(cmd_checked == Kill) begin
if((param[50:35] ^ rn16) == 16'h06cc & param[31:16] == handle) act = bs_header_kill;
else act = do_nothing;
end
else act = do_nothing;
Killed : act = do_nothing;
default : act = do_nothing;
endcase
end
always@(*) begin
if(act == set_sl_or_if) begin
if(param[45:44] == 2'b01 & param[43:36] < 8'b1100_0000 & ((param[43:36] - param[35:28]) > 8'b0)) mch = 1'b1;
else if(param[45:44] == 2'b10 & param[43:36] < 8'b0010_0000 & ((param[43:36] - param[35:28]) > 8'b0)) mch = 1'b1;
end
else mch = 1'b0;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) ptr <= 8'b0;
else if(act == set_sl_or_if) ptr <= param[43:36] - param[35:28];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) trct <= 1'b0;
else if(act == set_sl_or_if) trct <= param[16];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) sl <= 2'b10;
else if(act == set_sl_or_if & param[51:49] == 3'b100) begin
if(mch) begin
case(param[48:46])
3'b000 : sl <= 2'b11;
3'b001 : sl <= 2'b11;
3'b011 : sl <= ~sl;
3'b100 : sl <= 2'b10;
3'b101 : sl <= 2'b10;
endcase
end
else begin
case(param[48:46])
3'b000 : sl <= 2'b10;
3'b010 : sl <= 2'b10;
3'b100 : sl <= 2'b11;
3'b110 : sl <= 2'b11;
3'b111 : sl <= ~sl;
endcase
end
end
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s0 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b000) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s0 <= 1'b0;
3'b001 : if_s0 <= 1'b0;
3'b011 : if_s0 <= ~if_s0;
3'b100 : if_s0 <= 1'b0;
3'b101 : if_s0 <= 1'b0;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s0 <= 1'b1;
3'b010 : if_s0 <= 1'b1;
3'b100 : if_s0 <= 1'b0;
3'b110 : if_s0 <= 1'b0;
3'b111 : if_s0 <= ~if_s0;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == dec_slot_tran_if & session == 2'b00) if_s0 <= ~if_s0;
else if(act == adj_q_tran_if & session == 2'b00) if_s0 <= ~if_s0;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s1 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b001) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s1 <= 1'b0;
3'b001 : if_s1 <= 1'b0;
3'b011 : if_s1 <= ~if_s1;
3'b100 : if_s1 <= 1'b1;
3'b101 : if_s1 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s1 <= 1'b1;
3'b010 : if_s1 <= 1'b1;
3'b100 : if_s1 <= 1'b0;
3'b110 : if_s1 <= 1'b0;
3'b111 : if_s1 <= ~if_s1;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == dec_slot_tran_if & session == 2'b01) if_s1 <= ~if_s1;
else if(act == adj_q_tran_if & session == 2'b01) if_s1 <= ~if_s1;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s2 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b010) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s2 <= 1'b0;
3'b001 : if_s2 <= 1'b0;
3'b011 : if_s2 <= ~if_s2;
3'b100 : if_s2 <= 1'b1;
3'b101 : if_s2 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s2 <= 1'b1;
3'b010 : if_s2 <= 1'b1;
3'b100 : if_s2 <= 1'b0;
3'b110 : if_s2 <= 1'b0;
3'b111 : if_s2 <= ~if_s2;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == dec_slot_tran_if & session == 2'b10) if_s2 <= ~if_s2;
else if(act == adj_q_tran_if & session == 2'b10) if_s2 <= ~if_s2;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) if_s3 <= 1'b0;
else if(act == set_sl_or_if & param[51:49] == 3'b011) begin
if(mch) begin
case(param[48:46])
3'b000 : if_s3 <= 1'b0;
3'b001 : if_s3 <= 1'b0;
3'b011 : if_s3 <= ~if_s3;
3'b100 : if_s3 <= 1'b1;
3'b101 : if_s3 <= 1'b1;
endcase
end
else begin
case(param[48:46])
3'b000 : if_s3 <= 1'b1;
3'b010 : if_s3 <= 1'b1;
3'b100 : if_s3 <= 1'b0;
3'b110 : if_s3 <= 1'b0;
3'b111 : if_s3 <= ~if_s3;
endcase
end
end
else if(act == bs_new_rn16_tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == dec_slot_tran_if & session == 2'b11) if_s3 <= ~if_s3;
else if(act == adj_q_tran_if & session == 2'b11) if_s3 <= ~if_s3;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) dr <= 1'b0;
else if(act == init_inventory) dr <= param[17];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) m <= 2'b00;
else if(act == init_inventory) m <= param[16:15];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) trext <= 1'b0;
else if(act == init_inventory) trext <= param[14];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) session <= 2'b00;
else if(act == init_inventory) session <= param[11:10];
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) q <= 4'b0;
else if(act == init_inventory) q <= param[8:5];
else if(act == adj_q | act == adj_q_tran_if) begin
if(param[2:0] == 3'b110) q <= q + 4'b1;
else if(param[2:0] == 3'b011) q <= q - 4'b1;
end
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) slot <= 15'h2ac7;
else if(act == init_inventory) begin
case(param[8:5])
4'h0 : slot <= 15'b0;
4'h1 : slot <= {14'b0, prn[0]};
4'h2 : slot <= {13'b0, prn[1:0]};
4'h3 : slot <= {12'b0, prn[2:0]};
4'h4 : slot <= {11'b0, prn[3:0]};
4'h5 : slot <= {10'b0, prn[4:0]};
4'h6 : slot <= {9'b0, prn[5:0]};
4'h7 : slot <= {8'b0, prn[6:0]};
4'h8 : slot <= {7'b0, prn[7:0]};
4'h9 : slot <= {6'b0, prn[8:0]};
4'ha : slot <= {5'b0, prn[9:0]};
4'hb : slot <= {4'b0, prn[10:0]};
4'hc : slot <= {3'b0, prn[11:0]};
4'hd : slot <= {2'b0, prn[12:0]};
4'he : slot <= {1'b0, prn[13:0]};
4'hf : slot <= prn[14:0];
endcase
end
else if(act == adj_q | act == adj_q_tran_if) begin
if(param[2:0] == 3'b110) begin
case(q)
4'hf : slot <= 15'b0;
4'h0 : slot <= {14'b0, prn[0]};
4'h1 : slot <= {13'b0, prn[1:0]};
4'h2 : slot <= {12'b0, prn[2:0]};
4'h3 : slot <= {11'b0, prn[3:0]};
4'h4 : slot <= {10'b0, prn[4:0]};
4'h5 : slot <= {9'b0, prn[5:0]};
4'h6 : slot <= {8'b0, prn[6:0]};
4'h7 : slot <= {7'b0, prn[7:0]};
4'h8 : slot <= {6'b0, prn[8:0]};
4'h9 : slot <= {5'b0, prn[9:0]};
4'ha : slot <= {4'b0, prn[10:0]};
4'hb : slot <= {3'b0, prn[11:0]};
4'hc : slot <= {2'b0, prn[12:0]};
4'hd : slot <= {1'b0, prn[13:0]};
4'he : slot <= prn[14:0];
endcase
end
else if(param[2:0] == 3'b011) begin
case(q)
4'h1 : slot <= 15'b0;
4'h2 : slot <= {14'b0, prn[0]};
4'h3 : slot <= {13'b0, prn[1:0]};
4'h4 : slot <= {12'b0, prn[2:0]};
4'h5 : slot <= {11'b0, prn[3:0]};
4'h6 : slot <= {10'b0, prn[4:0]};
4'h7 : slot <= {9'b0, prn[5:0]};
4'h8 : slot <= {8'b0, prn[6:0]};
4'h9 : slot <= {7'b0, prn[7:0]};
4'ha : slot <= {6'b0, prn[8:0]};
4'hb : slot <= {5'b0, prn[9:0]};
4'hc : slot <= {4'b0, prn[10:0]};
4'hd : slot <= {3'b0, prn[11:0]};
4'he : slot <= {2'b0, prn[12:0]};
4'hf : slot <= {1'b0, prn[13:0]};
4'h0 : slot <= prn[14:0];
endcase
end
end
else if(act == dec_slot | act == dec_slot_tran_if) slot <= slot - 15'b1;
end
always@(posedge clk_cp or negedge rst_n) begin
if(~rst_n) lock_act <= 10'b00_0000_0011;
else begin
if(act == bs_header_lock) begin
if(param[43:42] != 2'b00) lock_act <= lock_act;
else if(({param[50], param[40]} == 2'b10) & lock_act[8]) lock_act <= lock_act;
else if(({param[48], param[38]} == 2'b10) & lock_act[6]) lock_act <= lock_act;
else if(({param[46], param[36]} == 2'b10) & lock_act[4]) lock_act <= lock_act;
else if(({param[44], param[34]} == 2'b10) & lock_act[2]) lock_act <= lock_act;
else begin
if(param[51]) lock_act[9] <= param[41];
if(param[50]) lock_act[8] <= param[40];
if(param[49]) lock_act[7] <= param[39];
if(param[48]) lock_act[6] <= param[38];
if(param[47]) lock_act[5] <= param[37];
if(param[46]) lock_act[4] <= param[36];
if(param[45]) lock_act[3] <= param[35];
if(param[44]) lock_act[2] <= param[34];
end
end
end
end
always@(*) begin
case(lock_act[3:2])
2'b00 : if((ps == Open) | (ps == Secured)) tid_lock = 0;
else tid_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) tid_lock = 0;
else tid_lock = 1;
2'b10 : if(ps == Secured) tid_lock = 0;
else tid_lock = 1;
2'b11 : tid_lock = 1;
endcase
end
always@(*) begin
case(lock_act[5:4])
2'b00 : if((ps == Open) | (ps == Secured)) epc_lock = 0;
else epc_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) epc_lock = 0;
else epc_lock = 1;
2'b10 : if(ps == Secured) epc_lock = 0;
else epc_lock = 1;
2'b11 : epc_lock = 1;
endcase
end
always@(*) begin
case(lock_act[7:6])
2'b00 : if((ps == Open) | (ps == Secured)) accs_lock = 0;
else accs_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) accs_lock = 0;
else accs_lock = 1;
2'b10 : if(ps == Secured) accs_lock = 0;
else accs_lock = 1;
2'b11 : accs_lock = 1;
endcase
end
always@(*) begin
case(lock_act[9:8])
2'b00 : if((ps == Open) | (ps == Secured)) kill_lock = 0;
else kill_lock = 1;
2'b01 : if((ps == Open) | (ps == Secured)) kill_lock = 0;
else kill_lock = 1;
2'b10 : if(ps == Secured) kill_lock = 0;
else kill_lock = 1;
2'b11 : kill_lock = 1;
endcase
end
always@(posedge clk_cp or negedge rst_for_new_package) begin
if(~rst_for_new_package) act_reg <= 5'h0;
else act_reg <= act;
end
always@(*) begin
if(act_reg == init_inventory | act_reg == adj_q | act_reg == dec_slot | act_reg == adj_q_tran_if | act_reg == dec_slot_tran_if) en_2nd_clk_cp = 1'b1;
else en_2nd_clk_cp = 1'b0;
end
always@(*) begin
if(ps == Ready) en_prng_idol = 1'b1;
else en_prng_idol = 1'b0;
end
always@(*) begin
if(act_reg == bs_new_rn16 | act_reg == bs_new_rn16_tran_if | act_reg == gen_and_bs_new_handle | act_reg == bs_new_rn16_crc16) en_prng_act = 1'b1;
else en_prng_act = 1'b0;
end
always@(*) begin
case(act_reg)
bs_new_rn16 : en_tx = 1'b1;
reply_ack : en_tx = 1'b1;
bs_new_rn16_tran_if : en_tx = 1'b1;
gen_and_bs_new_handle : en_tx = 1'b1;
bs_new_rn16_crc16 : en_tx = 1'b1;
bs_read_data : en_tx = 1'b1;
bs_handle : en_tx = 1'b1;
bs_header_kill : en_tx = 1'b1;
bs_header_lock : en_tx = 1'b1;
bs_error_code : en_tx = 1'b1;
default : en_tx = 1'b0;
endcase
end
always@(*) begin
if(act_reg == reply_ack) begin
if(~trct & pre_p_complete) en_if = 1'b1;
else if(trct & p_complete & (r_cnt < r_end + 5'h02)) en_if = 1'b1;
else en_if = 1'b0;
end
else if(act_reg == bs_read_data) begin
if(p_complete) en_if = 1'b1;
else en_if = 1'b0;
end
else en_if = 1'b0;
end
always@(*) begin
if(p_complete & (act_reg == reply_ack | act_reg == gen_and_bs_new_handle | act_reg == bs_new_rn16_crc16 | act_reg == bs_read_data |
act_reg == bs_handle | act_reg == bs_header_kill | act_reg == bs_header_lock)) en_crc16_for_rpy = 1'b1;
else en_crc16_for_rpy = 1'b0;
end
always@(*) begin
if(act_reg == reply_ack) begin
if(~trct) addr = {1'b0, 2'b01, 8'b0, 8'b0};
else addr = {1'b0, 2'b01, ptr, 8'b0};
end
else if(act_reg == bs_read_data) addr = {1'b1, param[49:32]};
else addr = 19'b0;
end
assign clk_cp_n = ~clk_cp;
always@(posedge clk_cp_n or negedge rst_n) begin
if(~rst_n) rn16 <= 16'hac70;
else if(act_reg == bs_new_rn16 | act_reg == bs_new_rn16_tran_if | act_reg == bs_new_rn16_crc16) rn16 <= prn[15:0];
end
always@(posedge clk_cp_n or negedge rst_n) begin
if(~rst_n) handle <= 16'hff31;
else if(act_reg == gen_and_bs_new_handle) handle <= prn[15:0];
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) en_if_d <= 1'b0;
else en_if_d <= en_if;
end
wire en_r_cnt;
assign en_r_cnt = ~en_if_d | rd_complete;
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) r_cnt <= 5'h17;
else if(p_complete & en_r_cnt) begin
if(r_cnt != r_end) r_cnt <= r_cnt - 1;
else r_cnt <= r_cnt;
end
end
always@(*) begin
case(act_reg)
bs_new_rn16 : r_end = 5'h08;
reply_ack : if(~trct) r_end = 5'h17;
else r_end = 5'h12;
bs_new_rn16_tran_if : r_end = 5'h08;
gen_and_bs_new_handle : r_end = 5'h08;
bs_new_rn16_crc16 : r_end = 5'h08;
bs_read_data : r_end = 5'h06;
bs_handle : r_end = 5'h08;
bs_header_kill : r_end = 5'h07;
bs_header_lock : r_end = 5'h07;
bs_error_code : r_end = 5'h00;
default : r_end = 5'h00;
endcase
end
always@(*) begin
case(act_reg)
bs_new_rn16 : reply_data = rn16[r_cnt - 5'h08];
reply_ack : if(~trct) reply_data = rd_data;
else begin
if(r_cnt > 5'h12) reply_data = 1'b0;
else reply_data = rd_data;
end
bs_new_rn16_tran_if : reply_data = rn16[r_cnt - 5'h08];
gen_and_bs_new_handle : reply_data = handle[r_cnt - 5'h08];
bs_new_rn16_crc16 : reply_data = rn16[r_cnt - 5'h08];
bs_read_data : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt == 5'h16) reply_data = rd_data;
else if(r_cnt < 5'h16 & r_cnt > 5'h5) reply_data = handle[r_cnt - 5'h6];
else reply_data = 1'b0;
bs_handle : reply_data = handle[r_cnt - 5'h08];
bs_header_kill : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt < 5'h17 & r_cnt > 5'h6) reply_data = handle[r_cnt - 5'h07];
else reply_data = 1'b0;
bs_header_lock : if(r_cnt == 5'h17) reply_data = 1'b0;
else if(r_cnt < 5'h17 & r_cnt > 5'h6) reply_data = handle[r_cnt - 5'h07];
else reply_data = 1'b0;
bs_error_code : if(r_cnt > 5'h13) reply_data = 1'b0;
else if(r_cnt < 5'h14 & r_cnt > 5'h0f) reply_data = 1'b1;
else reply_data = handle[r_cnt];
default : reply_data = 1'b0;
endcase
end
always@(*) begin
if(act_reg == reply_ack) begin
if(rd_complete) reply_complete = 1'b1;
else reply_complete = 1'b0;
end
else begin
if(r_cnt == r_end) reply_complete = 1'b1;
else reply_complete = 1'b0;
end
end
endmodule | 11 |
137,796 | data/full_repos/permissive/80423202/crc5.v | 80,423,202 | crc5.v | v | 43 | 92 | [] | [] | [] | [(13, 42)] | null | data/verilator_xmls/bc02101b-c257-4db8-b7a6-1580f122207a.xml | null | 300,611 | module | module crc5
(
output crc5_check_pass,
input clk_crc5,
input rst_for_new_package,
input data,
input sync,
input package_complete
);
reg [4:0]reg_crc;
assign crc5_check_pass = ~(|reg_crc);
always@(posedge clk_crc5 or negedge rst_for_new_package) begin
if(~rst_for_new_package) reg_crc <= 5'b01001;
else if(sync & ~package_complete) begin
reg_crc[4] <= reg_crc[3];
reg_crc[3] <= reg_crc[2] ^ (data ^ reg_crc[4]);
reg_crc[2] <= reg_crc[1];
reg_crc[1] <= reg_crc[0];
reg_crc[0] <= data ^ reg_crc[4];
end
end
endmodule | module crc5
(
output crc5_check_pass,
input clk_crc5,
input rst_for_new_package,
input data,
input sync,
input package_complete
); |
reg [4:0]reg_crc;
assign crc5_check_pass = ~(|reg_crc);
always@(posedge clk_crc5 or negedge rst_for_new_package) begin
if(~rst_for_new_package) reg_crc <= 5'b01001;
else if(sync & ~package_complete) begin
reg_crc[4] <= reg_crc[3];
reg_crc[3] <= reg_crc[2] ^ (data ^ reg_crc[4]);
reg_crc[2] <= reg_crc[1];
reg_crc[1] <= reg_crc[0];
reg_crc[0] <= data ^ reg_crc[4];
end
end
endmodule | 11 |
137,797 | data/full_repos/permissive/80423202/fm0_enc.v | 80,423,202 | fm0_enc.v | v | 130 | 106 | [] | [] | [] | [(19, 129)] | null | data/verilator_xmls/3f0e8648-c7b8-4479-92bf-70d807803e8b.xml | null | 300,613 | module | module fm0_enc
(
output fm0_data,
output fm0_complete,
input clk_fm0,
input rst_for_new_package,
input send_data,
input en_fm0,
input trext,
input st_enc,
input fg_complete
);
parameter GetData = 3'b000;
parameter Data0p = 3'b001;
parameter Data0n = 3'b010;
parameter Data1p = 3'b011;
parameter Data1n = 3'b100;
reg [2:0]ps;
reg [2:0]ns;
wire clk_fm0_n;
wire en_vcnt;
wire start_enc;
wire send_v;
wire m2o;
reg [1:0]data_select;
reg m1o;
reg [4:0]v_cnt;
reg [1:0]fg_comp_cnt;
assign clk_fm0_n = ~clk_fm0;
assign start_enc = (ps != GetData)? 1'b1 : 1'b0;
assign en_vcnt = (start_enc & (v_cnt != 5'h11))? 1'b1 : 1'b0;
assign send_v = (~trext & (v_cnt == 5'h04))? 1'b1 :
(trext & (v_cnt == 5'h10))? 1'b1 : 1'b0;
assign m2o = send_v? 1'b0 : m1o;
assign fm0_data = (en_fm0 & ~fm0_complete)? m2o : 1'b0;
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) ps <= GetData;
else if(st_enc) ps <= ns;
end
always@(*) begin
case(ps)
GetData : if(~en_fm0) ns = GetData;
else if(en_fm0 & (~send_data)) ns = Data0p;
else ns = Data1p;
Data0p : if(~send_data) ns = Data0p;
else ns = Data1p;
Data0n : if(~send_data) ns = Data0n;
else ns = Data1n;
Data1p : if(~send_data) ns = Data0n;
else ns = Data1n;
Data1n : if(~send_data) ns = Data0p;
else ns = Data1p;
default : ns = GetData;
endcase
end
always@(*) begin
case(ps)
GetData : data_select = 2'h0;
Data0p : data_select = 2'h3;
Data0n : data_select = 2'h2;
Data1p : data_select = 2'h1;
Data1n : data_select = 2'h0;
default : data_select = 2'h0;
endcase
end
always@(*) begin
case(data_select)
2'h0 : m1o = 1'b0;
2'h1 : m1o = 1'b1;
2'h2 : m1o = clk_fm0_n;
2'h3 : m1o = clk_fm0;
endcase
end
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) v_cnt <= 5'h00;
else begin
if(st_enc & en_vcnt) v_cnt <= v_cnt + 5'h01;
end
end
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_comp_cnt <= 2'b0;
else begin
if(fg_comp_cnt == 2'b10) fg_comp_cnt <= fg_comp_cnt;
else if(en_fm0 & fg_complete) fg_comp_cnt <= fg_comp_cnt + 2'b1;
end
end
assign fm0_complete = (fg_comp_cnt == 2'b10)? 1'b1 : 1'b0;
endmodule | module fm0_enc
(
output fm0_data,
output fm0_complete,
input clk_fm0,
input rst_for_new_package,
input send_data,
input en_fm0,
input trext,
input st_enc,
input fg_complete
); |
parameter GetData = 3'b000;
parameter Data0p = 3'b001;
parameter Data0n = 3'b010;
parameter Data1p = 3'b011;
parameter Data1n = 3'b100;
reg [2:0]ps;
reg [2:0]ns;
wire clk_fm0_n;
wire en_vcnt;
wire start_enc;
wire send_v;
wire m2o;
reg [1:0]data_select;
reg m1o;
reg [4:0]v_cnt;
reg [1:0]fg_comp_cnt;
assign clk_fm0_n = ~clk_fm0;
assign start_enc = (ps != GetData)? 1'b1 : 1'b0;
assign en_vcnt = (start_enc & (v_cnt != 5'h11))? 1'b1 : 1'b0;
assign send_v = (~trext & (v_cnt == 5'h04))? 1'b1 :
(trext & (v_cnt == 5'h10))? 1'b1 : 1'b0;
assign m2o = send_v? 1'b0 : m1o;
assign fm0_data = (en_fm0 & ~fm0_complete)? m2o : 1'b0;
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) ps <= GetData;
else if(st_enc) ps <= ns;
end
always@(*) begin
case(ps)
GetData : if(~en_fm0) ns = GetData;
else if(en_fm0 & (~send_data)) ns = Data0p;
else ns = Data1p;
Data0p : if(~send_data) ns = Data0p;
else ns = Data1p;
Data0n : if(~send_data) ns = Data0n;
else ns = Data1n;
Data1p : if(~send_data) ns = Data0n;
else ns = Data1n;
Data1n : if(~send_data) ns = Data0p;
else ns = Data1p;
default : ns = GetData;
endcase
end
always@(*) begin
case(ps)
GetData : data_select = 2'h0;
Data0p : data_select = 2'h3;
Data0n : data_select = 2'h2;
Data1p : data_select = 2'h1;
Data1n : data_select = 2'h0;
default : data_select = 2'h0;
endcase
end
always@(*) begin
case(data_select)
2'h0 : m1o = 1'b0;
2'h1 : m1o = 1'b1;
2'h2 : m1o = clk_fm0_n;
2'h3 : m1o = clk_fm0;
endcase
end
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) v_cnt <= 5'h00;
else begin
if(st_enc & en_vcnt) v_cnt <= v_cnt + 5'h01;
end
end
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_comp_cnt <= 2'b0;
else begin
if(fg_comp_cnt == 2'b10) fg_comp_cnt <= fg_comp_cnt;
else if(en_fm0 & fg_complete) fg_comp_cnt <= fg_comp_cnt + 2'b1;
end
end
assign fm0_complete = (fg_comp_cnt == 2'b10)? 1'b1 : 1'b0;
endmodule | 11 |
137,799 | data/full_repos/permissive/80423202/fs_detector.v | 80,423,202 | fs_detector.v | v | 61 | 80 | [] | [] | [] | [(14, 60)] | null | data/verilator_xmls/b2ad1d4f-ec8b-4b0c-abab-bd1546dde8ca.xml | null | 300,615 | module | module fs_detector
(
output reg sync,
input pie_code,
input clk_fsd,
input rst_n,
input package_complete
);
parameter idle = 2'b00;
parameter got0 = 2'b01;
parameter got1 = 2'b10;
reg [1:0]ps;
reg [1:0]ns;
always@(posedge clk_fsd or negedge rst_n) begin
if(~rst_n) ps <= idle;
else ps <= ns;
end
always@(*) begin
case(ps)
idle : if(~pie_code) ns = got0;
else ns = idle;
got0 : if(~pie_code) ns = got0;
else ns = got1;
got1 : if(package_complete) ns = idle;
else ns = got1;
default : ns = idle;
endcase
end
always@(*) begin
case(ps)
idle : sync = 1'b0;
got0 : sync = 1'b0;
got1 : sync = 1'b1;
default : sync = 1'b0;
endcase
end
endmodule | module fs_detector
(
output reg sync,
input pie_code,
input clk_fsd,
input rst_n,
input package_complete
); |
parameter idle = 2'b00;
parameter got0 = 2'b01;
parameter got1 = 2'b10;
reg [1:0]ps;
reg [1:0]ns;
always@(posedge clk_fsd or negedge rst_n) begin
if(~rst_n) ps <= idle;
else ps <= ns;
end
always@(*) begin
case(ps)
idle : if(~pie_code) ns = got0;
else ns = idle;
got0 : if(~pie_code) ns = got0;
else ns = got1;
got1 : if(package_complete) ns = idle;
else ns = got1;
default : ns = idle;
endcase
end
always@(*) begin
case(ps)
idle : sync = 1'b0;
got0 : sync = 1'b0;
got1 : sync = 1'b1;
default : sync = 1'b0;
endcase
end
endmodule | 11 |
137,800 | data/full_repos/permissive/80423202/mem_if.v | 80,423,202 | mem_if.v | v | 104 | 128 | [] | [] | [] | [(18, 103)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:55: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'A_cnt\' generates 6 bits.\n : ... In instance mem_if\n 2\'b00 : A = addr[15:8] + A_cnt;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:55: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s ADD generates 8 bits.\n : ... In instance mem_if\n 2\'b00 : A = addr[15:8] + A_cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:56: Operator ADD expects 8 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance mem_if\n 2\'b01 : A = addr[15:8] + 6\'h4 + A_cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:56: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'A_cnt\' generates 6 bits.\n : ... In instance mem_if\n 2\'b01 : A = addr[15:8] + 6\'h4 + A_cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:56: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s ADD generates 8 bits.\n : ... In instance mem_if\n 2\'b01 : A = addr[15:8] + 6\'h4 + A_cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:57: Operator ADD expects 8 bits on the RHS, but RHS\'s CONST \'6\'h27\' generates 6 bits.\n : ... In instance mem_if\n 2\'b10 : A = addr[15:8] + 6\'h27 + A_cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:57: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'A_cnt\' generates 6 bits.\n : ... In instance mem_if\n 2\'b10 : A = addr[15:8] + 6\'h27 + A_cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:57: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s ADD generates 8 bits.\n : ... In instance mem_if\n 2\'b10 : A = addr[15:8] + 6\'h27 + A_cnt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/80423202/mem_if.v:97: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'A_cnt\' generates 6 bits.\n : ... In instance mem_if\n else if(addr[7:0] != 0 & A_cnt == addr[7:0]) rd_complete <= 1\'b1;\n ^~\n%Error: Exiting due to 9 warning(s)\n' | 300,616 | module | module mem_if
(
output reg rd_data,
output reg rd_complete,
output reg [5:0]A,
output CEN,
input [18:0]addr,
input [15:0]Q,
input clk_if,
input rst_for_new_package
);
wire clk_if_n;
reg d_1clk;
reg d_flag;
reg [3:0]d_cnt;
reg [5:0]A_cnt;
assign CEN = (addr == 19'h0)? 1'b1 : 1'b0;
assign clk_if_n = ~clk_if;
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) rd_data <= 1'b0;
else rd_data <= Q[d_cnt];
end
always@(*) begin
if(~addr[18]) begin
if(addr[15:8] == 8'b0000_0000) A = 6'h5 + A_cnt;
else A = 6'h11 - {2'b0, addr[15:12]} + A_cnt;
end
else begin
case(addr[17:16])
2'b00 : A = addr[15:8] + A_cnt;
2'b01 : A = addr[15:8] + 6'h4 + A_cnt;
2'b10 : A = addr[15:8] + 6'h27 + A_cnt;
2'b11 : A = 6'h29;
endcase
end
end
always@(posedge clk_if_n or negedge rst_for_new_package) begin
if(~rst_for_new_package) A_cnt <= 6'h0;
else if(d_cnt == 4'h0) A_cnt <= A_cnt + 6'h1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_1clk <= 1'b0;
else d_1clk <= 1'b1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_flag <= 1'b0;
else if(~addr[18] & addr[15:8] != 8'h0) d_flag <= 1'b1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_cnt <= 4'hf;
else begin
if(~addr[18] & addr[15:8] != 8'h0 & ~d_flag) d_cnt <= addr[11:8];
else if(d_1clk) d_cnt <= d_cnt - 4'h1;
end
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) rd_complete <= 1'b0;
else begin
if(~addr[18]) begin
if(A == 6'h12) rd_complete <= 1'b1;
end
else begin
if(addr[17:16] == 2'b00 & addr[7:0] == 8'h0 & addr[15:8] < 8'h4 & A == 6'h4) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b01 & addr[7:0] == 8'h0 & addr[15:8] < 8'he & A == 6'h12) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b01 & addr[7:0] == 8'h0 & addr[15:8] > 8'hd & addr[15:8] < 8'h23 & A == 6'h27) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b10 & addr[7:0] == 8'h0 & addr[15:8] < 8'h2 & A == 6'h29) rd_complete <= 1'b1;
else if(addr[7:0] != 0 & A_cnt == addr[7:0]) rd_complete <= 1'b1;
end
end
end
endmodule | module mem_if
(
output reg rd_data,
output reg rd_complete,
output reg [5:0]A,
output CEN,
input [18:0]addr,
input [15:0]Q,
input clk_if,
input rst_for_new_package
); |
wire clk_if_n;
reg d_1clk;
reg d_flag;
reg [3:0]d_cnt;
reg [5:0]A_cnt;
assign CEN = (addr == 19'h0)? 1'b1 : 1'b0;
assign clk_if_n = ~clk_if;
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) rd_data <= 1'b0;
else rd_data <= Q[d_cnt];
end
always@(*) begin
if(~addr[18]) begin
if(addr[15:8] == 8'b0000_0000) A = 6'h5 + A_cnt;
else A = 6'h11 - {2'b0, addr[15:12]} + A_cnt;
end
else begin
case(addr[17:16])
2'b00 : A = addr[15:8] + A_cnt;
2'b01 : A = addr[15:8] + 6'h4 + A_cnt;
2'b10 : A = addr[15:8] + 6'h27 + A_cnt;
2'b11 : A = 6'h29;
endcase
end
end
always@(posedge clk_if_n or negedge rst_for_new_package) begin
if(~rst_for_new_package) A_cnt <= 6'h0;
else if(d_cnt == 4'h0) A_cnt <= A_cnt + 6'h1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_1clk <= 1'b0;
else d_1clk <= 1'b1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_flag <= 1'b0;
else if(~addr[18] & addr[15:8] != 8'h0) d_flag <= 1'b1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_cnt <= 4'hf;
else begin
if(~addr[18] & addr[15:8] != 8'h0 & ~d_flag) d_cnt <= addr[11:8];
else if(d_1clk) d_cnt <= d_cnt - 4'h1;
end
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) rd_complete <= 1'b0;
else begin
if(~addr[18]) begin
if(A == 6'h12) rd_complete <= 1'b1;
end
else begin
if(addr[17:16] == 2'b00 & addr[7:0] == 8'h0 & addr[15:8] < 8'h4 & A == 6'h4) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b01 & addr[7:0] == 8'h0 & addr[15:8] < 8'he & A == 6'h12) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b01 & addr[7:0] == 8'h0 & addr[15:8] > 8'hd & addr[15:8] < 8'h23 & A == 6'h27) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b10 & addr[7:0] == 8'h0 & addr[15:8] < 8'h2 & A == 6'h29) rd_complete <= 1'b1;
else if(addr[7:0] != 0 & A_cnt == addr[7:0]) rd_complete <= 1'b1;
end
end
end
endmodule | 11 |
137,806 | data/full_repos/permissive/80489408/alu2.v | 80,489,408 | alu2.v | v | 49 | 126 | [] | [] | [] | [(29, 49)] | null | data/verilator_xmls/3deae424-24e2-430e-b1bb-306617af5b36.xml | null | 300,622 | module | module alu2(input wire [31:0] srca,input wire [31:0]srcb,
input wire [1:0] alucontrol,
output reg[31:0] aluresult,output wire[3:0]aluflags);
reg [31:0]sum;
reg cout;
wire [31:0]srcbc=~srcb;
always@(*) begin
if(alucontrol[0]) {cout,sum}=srca+srcbc+1;
else {cout,sum}=srca+srcb;
case (alucontrol)
2'b00: aluresult=sum;
2'b01: aluresult=sum;
2'b10: aluresult=srca & srcb;
2'b11: aluresult=srca | srcb;
endcase
end
assign aluflags[3:2]={aluresult[31],aluresult==0};
assign aluflags[1]= cout & ~alucontrol[1];
assign aluflags[0]= (~(alucontrol[0]^srca[31]^srca[31])) & (~alucontrol[1]) & (aluresult[31] ^ srca[31]) ;
endmodule | module alu2(input wire [31:0] srca,input wire [31:0]srcb,
input wire [1:0] alucontrol,
output reg[31:0] aluresult,output wire[3:0]aluflags); |
reg [31:0]sum;
reg cout;
wire [31:0]srcbc=~srcb;
always@(*) begin
if(alucontrol[0]) {cout,sum}=srca+srcbc+1;
else {cout,sum}=srca+srcb;
case (alucontrol)
2'b00: aluresult=sum;
2'b01: aluresult=sum;
2'b10: aluresult=srca & srcb;
2'b11: aluresult=srca | srcb;
endcase
end
assign aluflags[3:2]={aluresult[31],aluresult==0};
assign aluflags[1]= cout & ~alucontrol[1];
assign aluflags[0]= (~(alucontrol[0]^srca[31]^srca[31])) & (~alucontrol[1]) & (aluresult[31] ^ srca[31]) ;
endmodule | 0 |
137,807 | data/full_repos/permissive/80489408/ARM.v | 80,489,408 | ARM.v | v | 49 | 97 | [] | [] | [] | [(1, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/80489408/ARM.v:26: Cannot find file containing module: 'control_unit'\n control_unit Cu(clk,reset,inst[31:28],inst[27:26],inst[25:20],inst[15:12],ALUFlags,PCSrc,\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/control_unit\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/control_unit.v\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/control_unit.sv\n control_unit\n control_unit.v\n control_unit.sv\n obj_dir/control_unit\n obj_dir/control_unit.v\n obj_dir/control_unit.sv\n%Error: data/full_repos/permissive/80489408/ARM.v:42: Cannot find file containing module: 'register_file'\n register_file R_F(clk,RegWrite,RA1,RA2,RA3,Result,PCPlus8,RD1,RD2);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80489408/ARM.v:46: Cannot find file containing module: 'alu2'\n alu2 alu(SrcA,SrcB,ALUControl,ALUResult,ALUFlags);\n ^~~~\n%Error: data/full_repos/permissive/80489408/ARM.v:47: Cannot find file containing module: 'extend'\n extend ex(ImmSrc,inst[23:0],ExtImm);\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 300,623 | module | module ARM(input clk,input reset,input [31:0] inst,input [31:0]ReadData,output [31:0] DataAdr ,
output [31:0] WriteData,
output Write_Enable,output reg [31:0] PC);
wire[3:0] ALUFlags;
wire PCSrc,MemtoReg,MemWrite;
wire [1:0]ALUControl;
wire ALUSrc;
wire [1:0]ImmSrc;
wire RegWrite;
wire [1:0]RegSrc;
initial
PC=32'b0;
wire [31:0] PCPlus4,PCPlus8,PC_dash;
assign PCPlus4=PC+4;
assign PCPlus8=PCPlus4+4;
wire [31:0] Result;
assign PC_dash=(PCSrc==1)?Result:PCPlus4;
always @(posedge clk,posedge reset)begin
if(reset)
PC=32'b0;
else
PC<=PC_dash;
end
control_unit Cu(clk,reset,inst[31:28],inst[27:26],inst[25:20],inst[15:12],ALUFlags,PCSrc,
MemtoReg,MemWrite,
ALUControl,ALUSrc,ImmSrc,RegWrite,RegSrc);
wire [3:0] RA1;
assign RA1=(RegSrc[0]==1)?4'd15:inst[19:16];
wire [3:0] RA2;
assign RA2=(RegSrc[1]==1)? inst[15:12]:inst[3:0];
wire [3:0] RA3;
assign RA3=inst[15:12];
wire [31:0] ALUResult;
wire [31:0] RD1,RD2;
assign DataAdr = ALUResult;
assign WriteData=RD2;
assign Result=(MemtoReg==1)?ReadData:ALUResult;
register_file R_F(clk,RegWrite,RA1,RA2,RA3,Result,PCPlus8,RD1,RD2);
wire [31:0] SrcA,SrcB,ExtImm;
assign SrcA=RD1;
assign SrcB=(ALUSrc==1)?ExtImm:RD2;
alu2 alu(SrcA,SrcB,ALUControl,ALUResult,ALUFlags);
extend ex(ImmSrc,inst[23:0],ExtImm);
assign Write_Enable=MemWrite;
endmodule | module ARM(input clk,input reset,input [31:0] inst,input [31:0]ReadData,output [31:0] DataAdr ,
output [31:0] WriteData,
output Write_Enable,output reg [31:0] PC); |
wire[3:0] ALUFlags;
wire PCSrc,MemtoReg,MemWrite;
wire [1:0]ALUControl;
wire ALUSrc;
wire [1:0]ImmSrc;
wire RegWrite;
wire [1:0]RegSrc;
initial
PC=32'b0;
wire [31:0] PCPlus4,PCPlus8,PC_dash;
assign PCPlus4=PC+4;
assign PCPlus8=PCPlus4+4;
wire [31:0] Result;
assign PC_dash=(PCSrc==1)?Result:PCPlus4;
always @(posedge clk,posedge reset)begin
if(reset)
PC=32'b0;
else
PC<=PC_dash;
end
control_unit Cu(clk,reset,inst[31:28],inst[27:26],inst[25:20],inst[15:12],ALUFlags,PCSrc,
MemtoReg,MemWrite,
ALUControl,ALUSrc,ImmSrc,RegWrite,RegSrc);
wire [3:0] RA1;
assign RA1=(RegSrc[0]==1)?4'd15:inst[19:16];
wire [3:0] RA2;
assign RA2=(RegSrc[1]==1)? inst[15:12]:inst[3:0];
wire [3:0] RA3;
assign RA3=inst[15:12];
wire [31:0] ALUResult;
wire [31:0] RD1,RD2;
assign DataAdr = ALUResult;
assign WriteData=RD2;
assign Result=(MemtoReg==1)?ReadData:ALUResult;
register_file R_F(clk,RegWrite,RA1,RA2,RA3,Result,PCPlus8,RD1,RD2);
wire [31:0] SrcA,SrcB,ExtImm;
assign SrcA=RD1;
assign SrcB=(ALUSrc==1)?ExtImm:RD2;
alu2 alu(SrcA,SrcB,ALUControl,ALUResult,ALUFlags);
extend ex(ImmSrc,inst[23:0],ExtImm);
assign Write_Enable=MemWrite;
endmodule | 0 |
137,808 | data/full_repos/permissive/80489408/Control.v | 80,489,408 | Control.v | v | 109 | 102 | [] | [] | [] | [(6, 109)] | null | data/verilator_xmls/2d1effa1-6d97-4346-ad53-1a51a995152f.xml | null | 300,624 | module | module CU(input wire [31:0] instruction, input wire [3:0] flags, input wire clock,
output reg PCSrc, output reg MemToReg, output reg MemWrite,
output reg [1:0] ALUControl, output reg ALUSrc, output reg [1:0] ImmSrc,
output reg RegWrite, output reg NoWrite);
reg [3:0] interalflags;
reg exec;
always @* begin
exec = 0;
case (instruction[31:28])
4'b0000: if(interalflags[`Z]) exec = 1;
4'b0001: if(~interalflags[`Z]) exec = 1;
4'b0010: if(interalflags[`C]) exec = 1;
4'b0011: if(~interalflags[`C]) exec = 1;
4'b0100: if(interalflags[`N]) exec = 1;
4'b0101: if(~interalflags[`N]) exec = 1;
4'b0110: if(interalflags[`V]) exec = 1;
4'b0111: if(~interalflags[`V]) exec = 1;
4'b1000: if(~interalflags[`Z] & interalflags[`C]) exec = 1;
4'b1001: if(interalflags[`Z] | ~interalflags[`C]) exec = 1;
4'b1010: if(~(interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1011: if(interalflags[`N] ^ interalflags[`V]) exec = 1;
4'b1100: if(~interalflags[`Z] & ~(interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1101: if(interalflags[`Z] | (interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1110: exec = 1;
4'b1111: exec = 1'bx;
endcase
NoWrite = 0;
ALUControl = 0;
ALUSrc = 1;
MemToReg = 0;
MemWrite = 0;
RegWrite = 0;
case (instruction[27:26])
2'b00: begin
if (exec) begin
RegWrite = 1;
end
if (instruction[25]) begin
ImmSrc = 0;
end else begin
ALUSrc = 0;
ImmSrc = 2'bxx;
end
case(instruction[24:21])
4'b0100: ALUControl = 0;
4'b0010: ALUControl = 1;
4'b0000: ALUControl = 2;
4'b1100: ALUControl = 3;
4'b1010: begin
ALUControl = 1;
NoWrite = 1;
end
default : ALUControl = 2'bxx;
endcase
if ((instruction[15:12] == 4'b1111) && RegWrite && exec)
PCSrc = 1;
else
PCSrc = 0;
end
2'b01: begin
if(instruction[20])
MemToReg = 1;
if(exec)
RegWrite = 1;
else begin
MemToReg = 1'bx;
if(exec)
MemWrite = 1;
end
ImmSrc = 1;
if ((instruction[15:12] == 4'b1111) && RegWrite && exec)
PCSrc = 1;
else
PCSrc = 0;
end
2'b10: begin
ImmSrc = 2;
RegWrite = 0;
if (exec)
PCSrc = 1;
else
PCSrc = 0;
end
default: begin
PCSrc = 1'bx;
MemToReg = 1'bx;
MemWrite = 1'bx;
ALUControl = 2'bxx;
ALUSrc = 1'bx;
ImmSrc = 2'bxx;
RegWrite = 1'bx;
NoWrite = 1'bx;
end
endcase
end
always @(posedge clock)
if(!(|instruction[27:26]) & (instruction[20]))
interalflags = flags;
endmodule | module CU(input wire [31:0] instruction, input wire [3:0] flags, input wire clock,
output reg PCSrc, output reg MemToReg, output reg MemWrite,
output reg [1:0] ALUControl, output reg ALUSrc, output reg [1:0] ImmSrc,
output reg RegWrite, output reg NoWrite); |
reg [3:0] interalflags;
reg exec;
always @* begin
exec = 0;
case (instruction[31:28])
4'b0000: if(interalflags[`Z]) exec = 1;
4'b0001: if(~interalflags[`Z]) exec = 1;
4'b0010: if(interalflags[`C]) exec = 1;
4'b0011: if(~interalflags[`C]) exec = 1;
4'b0100: if(interalflags[`N]) exec = 1;
4'b0101: if(~interalflags[`N]) exec = 1;
4'b0110: if(interalflags[`V]) exec = 1;
4'b0111: if(~interalflags[`V]) exec = 1;
4'b1000: if(~interalflags[`Z] & interalflags[`C]) exec = 1;
4'b1001: if(interalflags[`Z] | ~interalflags[`C]) exec = 1;
4'b1010: if(~(interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1011: if(interalflags[`N] ^ interalflags[`V]) exec = 1;
4'b1100: if(~interalflags[`Z] & ~(interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1101: if(interalflags[`Z] | (interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1110: exec = 1;
4'b1111: exec = 1'bx;
endcase
NoWrite = 0;
ALUControl = 0;
ALUSrc = 1;
MemToReg = 0;
MemWrite = 0;
RegWrite = 0;
case (instruction[27:26])
2'b00: begin
if (exec) begin
RegWrite = 1;
end
if (instruction[25]) begin
ImmSrc = 0;
end else begin
ALUSrc = 0;
ImmSrc = 2'bxx;
end
case(instruction[24:21])
4'b0100: ALUControl = 0;
4'b0010: ALUControl = 1;
4'b0000: ALUControl = 2;
4'b1100: ALUControl = 3;
4'b1010: begin
ALUControl = 1;
NoWrite = 1;
end
default : ALUControl = 2'bxx;
endcase
if ((instruction[15:12] == 4'b1111) && RegWrite && exec)
PCSrc = 1;
else
PCSrc = 0;
end
2'b01: begin
if(instruction[20])
MemToReg = 1;
if(exec)
RegWrite = 1;
else begin
MemToReg = 1'bx;
if(exec)
MemWrite = 1;
end
ImmSrc = 1;
if ((instruction[15:12] == 4'b1111) && RegWrite && exec)
PCSrc = 1;
else
PCSrc = 0;
end
2'b10: begin
ImmSrc = 2;
RegWrite = 0;
if (exec)
PCSrc = 1;
else
PCSrc = 0;
end
default: begin
PCSrc = 1'bx;
MemToReg = 1'bx;
MemWrite = 1'bx;
ALUControl = 2'bxx;
ALUSrc = 1'bx;
ImmSrc = 2'bxx;
RegWrite = 1'bx;
NoWrite = 1'bx;
end
endcase
end
always @(posedge clock)
if(!(|instruction[27:26]) & (instruction[20]))
interalflags = flags;
endmodule | 0 |
137,809 | data/full_repos/permissive/80489408/control_unit.v | 80,489,408 | control_unit.v | v | 93 | 128 | [] | [] | [] | [(1, 38), (40, 73), (75, 82), (84, 93)] | null | data/verilator_xmls/2149d471-479d-4166-ac70-d85909b4731a.xml | null | 300,625 | module | module decoder(input [1:0] op,input [5:0] funct,input [3:0]rd,
output reg [1:0] flagw,output wire pcs,output wire regw,
output wire memw,output wire memtoreg,output wire alusrc,
output wire [1:0] immsrc,output wire [1:0] regsrc,output reg[1:0] alucontrol ,output wire nowrite
);
reg [9:0] control;
wire aluop;
wire branch;
always @*
case(op)
2'b00: if(funct[5]) control=10'b0001001001;
else control=10'b0000001001;
2'b01: if(funct[0]) control=10'b0101011000;
else control=10'b0011010100;
2'b10: control=10'b1001100010;
default:control=10'bxxxxxxxxxx;
endcase
assign {branch,memtoreg,memw,alusrc,immsrc,regw,regsrc,aluop} = control;
always @*
if(aluop)begin
case(funct[4:1])
4'd4 : alucontrol=0;
4'd2 : alucontrol=1;
4'd0 : alucontrol=2;
4'd12: alucontrol=3;
4'd10: alucontrol=1;
default:alucontrol=2'bxx;
endcase
flagw[1]=funct[0];
flagw[0] = funct[0] & (alucontrol == 0 | alucontrol == 1);
end
else begin
flagw=0;
alucontrol=0;
end
assign pcs =((rd == 15) & regw) | branch ;
assign nowrite = (funct[4:1]==10);
endmodule | module decoder(input [1:0] op,input [5:0] funct,input [3:0]rd,
output reg [1:0] flagw,output wire pcs,output wire regw,
output wire memw,output wire memtoreg,output wire alusrc,
output wire [1:0] immsrc,output wire [1:0] regsrc,output reg[1:0] alucontrol ,output wire nowrite
); |
reg [9:0] control;
wire aluop;
wire branch;
always @*
case(op)
2'b00: if(funct[5]) control=10'b0001001001;
else control=10'b0000001001;
2'b01: if(funct[0]) control=10'b0101011000;
else control=10'b0011010100;
2'b10: control=10'b1001100010;
default:control=10'bxxxxxxxxxx;
endcase
assign {branch,memtoreg,memw,alusrc,immsrc,regw,regsrc,aluop} = control;
always @*
if(aluop)begin
case(funct[4:1])
4'd4 : alucontrol=0;
4'd2 : alucontrol=1;
4'd0 : alucontrol=2;
4'd12: alucontrol=3;
4'd10: alucontrol=1;
default:alucontrol=2'bxx;
endcase
flagw[1]=funct[0];
flagw[0] = funct[0] & (alucontrol == 0 | alucontrol == 1);
end
else begin
flagw=0;
alucontrol=0;
end
assign pcs =((rd == 15) & regw) | branch ;
assign nowrite = (funct[4:1]==10);
endmodule | 0 |
137,810 | data/full_repos/permissive/80489408/control_unit.v | 80,489,408 | control_unit.v | v | 93 | 128 | [] | [] | [] | [(1, 38), (40, 73), (75, 82), (84, 93)] | null | data/verilator_xmls/2149d471-479d-4166-ac70-d85909b4731a.xml | null | 300,625 | module | module conditional_logic(input clk,input reset,input [3:0] cond,input [3:0]aluflags,input [1:0] flagw ,input pcs,
input wire regsw,input memw,input nowrite,output reg condex,
output wire PCSrc,output wire RegWrite ,output wire MemWrite);
wire [3:0] flags;
wire n,z,c,v;
wire [1:0]flagwrite;
assign flagwrite= flagw & {2{condex}};
flip_flop f1 (clk,reset,flagwrite[0],aluflags[1:0],flags[1:0]);
flip_flop f2 (clk,reset,flagwrite[1],aluflags[3:2],flags[3:2]);
assign {n,z,c,v} = flags;
always@(*)
case(cond)
4'b0000: condex=z;
4'b0001: condex=~z;
4'b0010: condex=c;
4'b0011: condex=~c;
4'b0100: condex=n;
4'b0101: condex=~n;
4'b0110: condex=v;
4'b0111: condex=~v;
4'b1000: condex= ~z & c;
4'b1001: condex= ~c | z;
4'b1010: condex=~(n^v);
4'b1011: condex=n^v;
4'b1100: condex=~z & ~(n ^ v);
4'b1101: condex=~z & ~(n ^ v);
4'b1110: condex=1'b1;
default: condex=1'bx;
endcase
assign PCSrc = pcs & condex;
assign RegWrite = regsw & condex & (~ nowrite);
assign MemWrite = memw & condex;
endmodule | module conditional_logic(input clk,input reset,input [3:0] cond,input [3:0]aluflags,input [1:0] flagw ,input pcs,
input wire regsw,input memw,input nowrite,output reg condex,
output wire PCSrc,output wire RegWrite ,output wire MemWrite); |
wire [3:0] flags;
wire n,z,c,v;
wire [1:0]flagwrite;
assign flagwrite= flagw & {2{condex}};
flip_flop f1 (clk,reset,flagwrite[0],aluflags[1:0],flags[1:0]);
flip_flop f2 (clk,reset,flagwrite[1],aluflags[3:2],flags[3:2]);
assign {n,z,c,v} = flags;
always@(*)
case(cond)
4'b0000: condex=z;
4'b0001: condex=~z;
4'b0010: condex=c;
4'b0011: condex=~c;
4'b0100: condex=n;
4'b0101: condex=~n;
4'b0110: condex=v;
4'b0111: condex=~v;
4'b1000: condex= ~z & c;
4'b1001: condex= ~c | z;
4'b1010: condex=~(n^v);
4'b1011: condex=n^v;
4'b1100: condex=~z & ~(n ^ v);
4'b1101: condex=~z & ~(n ^ v);
4'b1110: condex=1'b1;
default: condex=1'bx;
endcase
assign PCSrc = pcs & condex;
assign RegWrite = regsw & condex & (~ nowrite);
assign MemWrite = memw & condex;
endmodule | 0 |
137,811 | data/full_repos/permissive/80489408/control_unit.v | 80,489,408 | control_unit.v | v | 93 | 128 | [] | [] | [] | [(1, 38), (40, 73), (75, 82), (84, 93)] | null | data/verilator_xmls/2149d471-479d-4166-ac70-d85909b4731a.xml | null | 300,625 | module | module flip_flop(input clk,input reset,input en,input [1:0] d,output reg [1:0] q);
always @(posedge clk) begin
if(reset) q<=0;
else begin
if(en) q <= d;
end
end
endmodule | module flip_flop(input clk,input reset,input en,input [1:0] d,output reg [1:0] q); |
always @(posedge clk) begin
if(reset) q<=0;
else begin
if(en) q <= d;
end
end
endmodule | 0 |
137,812 | data/full_repos/permissive/80489408/control_unit.v | 80,489,408 | control_unit.v | v | 93 | 128 | [] | [] | [] | [(1, 38), (40, 73), (75, 82), (84, 93)] | null | data/verilator_xmls/2149d471-479d-4166-ac70-d85909b4731a.xml | null | 300,625 | module | module control_unit(input Clk,input reset,input [3:0] Cond,input [1:0] Op,input [5:0] Funct,input [3:0] Rd,input [3:0]ALUFlags,
output wire PCSrc,output wire MemtoReg,output wire MemWrite,output wire [1:0]ALUControl,
output wire ALUSrc,output wire [1:0]ImmSrc,output wire RegWrite,output wire [1:0]RegSrc);
wire [1:0]Flagw;
wire PCS,RegW,MemW;
wire nowrite;
wire condex;
decoder d1(Op,Funct,Rd,Flagw,PCS,RegW,MemW,MemtoReg,ALUSrc,ImmSrc,RegSrc,ALUControl,nowrite);
conditional_logic c1(Clk,reset,Cond,ALUFlags,Flagw,PCS,RegW,MemW,nowrite,condex,PCSrc,RegWrite,MemWrite);
endmodule | module control_unit(input Clk,input reset,input [3:0] Cond,input [1:0] Op,input [5:0] Funct,input [3:0] Rd,input [3:0]ALUFlags,
output wire PCSrc,output wire MemtoReg,output wire MemWrite,output wire [1:0]ALUControl,
output wire ALUSrc,output wire [1:0]ImmSrc,output wire RegWrite,output wire [1:0]RegSrc); |
wire [1:0]Flagw;
wire PCS,RegW,MemW;
wire nowrite;
wire condex;
decoder d1(Op,Funct,Rd,Flagw,PCS,RegW,MemW,MemtoReg,ALUSrc,ImmSrc,RegSrc,ALUControl,nowrite);
conditional_logic c1(Clk,reset,Cond,ALUFlags,Flagw,PCS,RegW,MemW,nowrite,condex,PCSrc,RegWrite,MemWrite);
endmodule | 0 |
137,813 | data/full_repos/permissive/80489408/DataMem.v | 80,489,408 | DataMem.v | v | 71 | 62 | [] | [] | [] | [(8, 46)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80489408/DataMem.v:35: Bit extraction of array[127:0] requires 7 bit index, not 30 bits.\n : ... In instance DataMem\n assign RD = (A[31:2]<Depth) ? Data[A[31:2]]: {Width{1\'bz}};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80489408/DataMem.v:41: Bit extraction of array[127:0] requires 7 bit index, not 30 bits.\n : ... In instance DataMem\n Data[A[31:2]]=WD;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,626 | module | module DataMem(A,RD,WD,WE,Clk);
parameter Width = 32,
Depth = 128;
input [Width-1:0] A;
input [Width-1:0] WD;
input WE,Clk;
output [Width-1:0]RD;
reg [Width-1:0] Data [0:Depth-1];
integer i;
initial begin
for(i=0;i<Depth;i=i+1)
Data[i]={Width{1'b0}};
end
assign RD = (A[31:2]<Depth) ? Data[A[31:2]]: {Width{1'bz}};
always @ (posedge Clk) begin
if(WE)
begin
Data[A[31:2]]=WD;
end
end
endmodule | module DataMem(A,RD,WD,WE,Clk); |
parameter Width = 32,
Depth = 128;
input [Width-1:0] A;
input [Width-1:0] WD;
input WE,Clk;
output [Width-1:0]RD;
reg [Width-1:0] Data [0:Depth-1];
integer i;
initial begin
for(i=0;i<Depth;i=i+1)
Data[i]={Width{1'b0}};
end
assign RD = (A[31:2]<Depth) ? Data[A[31:2]]: {Width{1'bz}};
always @ (posedge Clk) begin
if(WE)
begin
Data[A[31:2]]=WD;
end
end
endmodule | 0 |
137,814 | data/full_repos/permissive/80489408/extend.v | 80,489,408 | extend.v | v | 10 | 78 | [] | [] | [] | [(1, 9)] | null | data/verilator_xmls/da51c044-895b-4d7f-827f-f5b638e72232.xml | null | 300,627 | module | module extend(input [1:0] ImmSrc,input [23:0] Instr,output reg[31:0] ExtImm);
always @*
case(ImmSrc)
2'b00: ExtImm = { { 24{1'b0}},Instr[7:0]};
2'b01: ExtImm = { { 20{1'b0}},Instr[11:0]};
2'b10: ExtImm = { { 6{Instr[23]}},Instr[23:0],2'b00};
default: ExtImm = {32{1'bx}};
endcase
endmodule | module extend(input [1:0] ImmSrc,input [23:0] Instr,output reg[31:0] ExtImm); |
always @*
case(ImmSrc)
2'b00: ExtImm = { { 24{1'b0}},Instr[7:0]};
2'b01: ExtImm = { { 20{1'b0}},Instr[11:0]};
2'b10: ExtImm = { { 6{Instr[23]}},Instr[23:0],2'b00};
default: ExtImm = {32{1'bx}};
endcase
endmodule | 0 |
137,815 | data/full_repos/permissive/80489408/InstMem.v | 80,489,408 | InstMem.v | v | 27 | 50 | [] | [] | [] | [(5, 27)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80489408/InstMem.v:25: Operator LT expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n : ... In instance InstMem\n assign RD = (A<Depth) ? Data[A]: {Width{1\'bz}};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 300,629 | module | module InstMem(A,RD);
parameter Width = 32,
Depth = 256;
input [7:0] A;
output [Width-1:0]RD;
reg [Width-1:0] Data [0:Depth-1];
initial
$readmemh("InstructionMemory.txt", Data);
assign RD = (A<Depth) ? Data[A]: {Width{1'bz}};
endmodule | module InstMem(A,RD); |
parameter Width = 32,
Depth = 256;
input [7:0] A;
output [Width-1:0]RD;
reg [Width-1:0] Data [0:Depth-1];
initial
$readmemh("InstructionMemory.txt", Data);
assign RD = (A<Depth) ? Data[A]: {Width{1'bz}};
endmodule | 0 |
137,816 | data/full_repos/permissive/80489408/memory.v | 80,489,408 | memory.v | v | 132 | 62 | [] | [] | [] | [(4, 16), (50, 76)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80489408/memory.v:50: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'memory\'\nmodule memory(input [31:0] A,output reg [31:0] RD);\n ^~~~~~\n : ... Top module \'datamem\'\nmodule datamem\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/80489408/memory.v:14: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance memory\n RD = mem[A[31:2]];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,630 | module | module memory(input [31:0] A,output reg [31:0] RD);
reg [31:0]mem[0:31];
integer i;
initial begin
for(i=0;i<31;i=i+1)
mem[i]={32{1'b0}};
$readmemh("inst.txt",mem);
end
always@(A) begin
RD = mem[A[31:2]];
end
endmodule | module memory(input [31:0] A,output reg [31:0] RD); |
reg [31:0]mem[0:31];
integer i;
initial begin
for(i=0;i<31;i=i+1)
mem[i]={32{1'b0}};
$readmemh("inst.txt",mem);
end
always@(A) begin
RD = mem[A[31:2]];
end
endmodule | 0 |
137,817 | data/full_repos/permissive/80489408/memory.v | 80,489,408 | memory.v | v | 132 | 62 | [] | [] | [] | [(4, 16), (50, 76)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80489408/memory.v:50: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'memory\'\nmodule memory(input [31:0] A,output reg [31:0] RD);\n ^~~~~~\n : ... Top module \'datamem\'\nmodule datamem\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/80489408/memory.v:14: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance memory\n RD = mem[A[31:2]];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,630 | module | module datamem
(input [31:0] A,
input [31:0] WD,
input WE,
output [31:0] RD,
input clk);
reg [31:0] mem [0:31];
assign RD = mem[A[6:2]];
always @(posedge clk) begin
if(WE)begin
mem[A[6:2]] <= WD;
end
end
endmodule | module datamem
(input [31:0] A,
input [31:0] WD,
input WE,
output [31:0] RD,
input clk); |
reg [31:0] mem [0:31];
assign RD = mem[A[6:2]];
always @(posedge clk) begin
if(WE)begin
mem[A[6:2]] <= WD;
end
end
endmodule | 0 |
137,818 | data/full_repos/permissive/80489408/register_file.v | 80,489,408 | register_file.v | v | 36 | 69 | [] | [] | [] | [(2, 21)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80489408/register_file.v:10: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'r15\' generates 32 bits.\n : ... In instance register_file\n if(r15) mem[15]=r15;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 300,631 | module | module register_file(input clk,input we3,
input [3:0]a1,input [3:0]a2,input [3:0]a3,
input [31:0] wd3,input [31:0] r15,
output [31:0]rd1 ,output[31:0] rd2
);
reg[31:0] mem[0:15];
always@(posedge clk)begin
if(we3) mem[a3]=wd3;
if(r15) mem[15]=r15;
end
assign rd1 = (a1 == 4'b1111) ? r15 : mem[a1];
assign rd2 = (a2 == 4'b1111) ? r15 : mem[a2];
endmodule | module register_file(input clk,input we3,
input [3:0]a1,input [3:0]a2,input [3:0]a3,
input [31:0] wd3,input [31:0] r15,
output [31:0]rd1 ,output[31:0] rd2
); |
reg[31:0] mem[0:15];
always@(posedge clk)begin
if(we3) mem[a3]=wd3;
if(r15) mem[15]=r15;
end
assign rd1 = (a1 == 4'b1111) ? r15 : mem[a1];
assign rd2 = (a2 == 4'b1111) ? r15 : mem[a2];
endmodule | 0 |
137,819 | data/full_repos/permissive/80489408/shift2.v | 80,489,408 | shift2.v | v | 29 | 67 | [] | [] | [] | [(2, 29)] | null | data/verilator_xmls/7de9a9ea-4e02-4ca0-9238-99261906b5f0.xml | null | 300,633 | module | module shift2(Inst,Enable,RD2_input,ALUSrc2_output);
input [7:0] Inst;
input Enable;
input [31:0] RD2_input;
output [31:0] ALUSrc2_output;
wire [4:0] shamt5;
assign shamt5[4:0]=(Inst[0]==0)? Inst[7:3] :5'b00000;
wire [1:0] sh;
assign sh[1:0]=Inst[2:1];
wire [31:0] internal_output;
assign internal_output= (sh[1]==1) ?
( (sh[0]==1)? ( (RD2_input>>shamt5)|(RD2_input<<32-shamt5) ):
( (RD2_input>>shamt5)|({32{1'b1}}<<32-shamt5) ) ) :
( (sh[0]==1)? (RD2_input>>shamt5):(RD2_input<<shamt5) );
assign ALUSrc2_output = (Enable==1)? internal_output : RD2_input;
endmodule | module shift2(Inst,Enable,RD2_input,ALUSrc2_output); |
input [7:0] Inst;
input Enable;
input [31:0] RD2_input;
output [31:0] ALUSrc2_output;
wire [4:0] shamt5;
assign shamt5[4:0]=(Inst[0]==0)? Inst[7:3] :5'b00000;
wire [1:0] sh;
assign sh[1:0]=Inst[2:1];
wire [31:0] internal_output;
assign internal_output= (sh[1]==1) ?
( (sh[0]==1)? ( (RD2_input>>shamt5)|(RD2_input<<32-shamt5) ):
( (RD2_input>>shamt5)|({32{1'b1}}<<32-shamt5) ) ) :
( (sh[0]==1)? (RD2_input>>shamt5):(RD2_input<<shamt5) );
assign ALUSrc2_output = (Enable==1)? internal_output : RD2_input;
endmodule | 0 |
137,820 | data/full_repos/permissive/80489408/shifter.v | 80,489,408 | shifter.v | v | 21 | 105 | [] | [] | [] | null | line:7: before: "reg" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80489408/shifter.v:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 64 bits.\n : ... In instance shifter\n 2\'b10: b = {{32{a[31]}}, a} >> shift[6:2]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80489408/shifter.v:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 64 bits.\n : ... In instance shifter\n 2\'b11: b = {a, a} >> (shift[6:2]); \n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,634 | module | module shifter(input wire[`BUSWIDTH - 1:0] a, input wire [6:0] shift,
output reg [`BUSWIDTH - 1:0] b);
always @* begin
reg [2 * `BUSWIDTH - 1:0] c;
case(shift[1:0])
2'b00: b = a << shift[6:2];
2'b01: b = a >> shift[6:2];
2'b10: b = {{`BUSWIDTH{a[31]}}, a} >> shift[6:2];
2'b11: b = {a, a} >> (shift[6:2]);
endcase
end
endmodule | module shifter(input wire[`BUSWIDTH - 1:0] a, input wire [6:0] shift,
output reg [`BUSWIDTH - 1:0] b); |
always @* begin
reg [2 * `BUSWIDTH - 1:0] c;
case(shift[1:0])
2'b00: b = a << shift[6:2];
2'b01: b = a >> shift[6:2];
2'b10: b = {{`BUSWIDTH{a[31]}}, a} >> shift[6:2];
2'b11: b = {a, a} >> (shift[6:2]);
endcase
end
endmodule | 0 |
137,821 | data/full_repos/permissive/80489408/single_cycle.v | 80,489,408 | single_cycle.v | v | 84 | 80 | [] | [] | [] | [(1, 48), (50, 60), (62, 84)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80489408/single_cycle.v:50: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'single_cycle\'\nmodule single_cycle(input clk,input enable,output LED1,output reg LED2,LED3);\n ^~~~~~~~~~~~\n : ... Top module \'single_cycle_tp\'\nmodule single_cycle_tp(input clk,reset,output y,z);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80489408/single_cycle.v:69: Cannot find file containing module: \'memory\'\n memory im(PC,instruction);\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory.v\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory.sv\n memory\n memory.v\n memory.sv\n obj_dir/memory\n obj_dir/memory.v\n obj_dir/memory.sv\n%Error: data/full_repos/permissive/80489408/single_cycle.v:70: Cannot find file containing module: \'datamem\'\n datamem dm(DataAdr,WriteData,Write_Enable,ReadData,clk);\n ^~~~~~~\n%Error: data/full_repos/permissive/80489408/single_cycle.v:71: Cannot find file containing module: \'ARM\'\n ARM proc(clk,reset,instruction,ReadData,DataAdr,WriteData,Write_Enable,PC);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:78: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h7\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h00000014))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:78: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h14\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h00000014))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:80: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h7\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h0000001A))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:80: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1a\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h0000001A))\n ^~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n' | 300,635 | module | module single_cycle(input clk,input enable,output LED1,output reg LED2,LED3);
reg [32:0] cnt = 0;
reg number=0;
reg start=0;
reg stop=0;
reg reset=0;
wire debug1,debug2;
single_cycle_top sc(number,reset,debug1,debug2);
always @(negedge enable,posedge stop)begin
if(stop)
start=0;
else begin
if(!enable)
start=1;
else
start=0;
end
end
always @(posedge clk)begin
cnt <= cnt + 1'b1;
end
always @(posedge cnt[4]) begin
if(!start) begin
number=0;
stop=0;
reset=1;
end else begin
reset=0;
number = ~number;
if(debug1&&debug2)
stop=1;
end
end
always @(debug1, debug2,start) begin
if(start) begin
LED2=~debug1;
LED3=~debug2;
end
end
assign LED1 = !number;
endmodule | module single_cycle(input clk,input enable,output LED1,output reg LED2,LED3); |
reg [32:0] cnt = 0;
reg number=0;
reg start=0;
reg stop=0;
reg reset=0;
wire debug1,debug2;
single_cycle_top sc(number,reset,debug1,debug2);
always @(negedge enable,posedge stop)begin
if(stop)
start=0;
else begin
if(!enable)
start=1;
else
start=0;
end
end
always @(posedge clk)begin
cnt <= cnt + 1'b1;
end
always @(posedge cnt[4]) begin
if(!start) begin
number=0;
stop=0;
reset=1;
end else begin
reset=0;
number = ~number;
if(debug1&&debug2)
stop=1;
end
end
always @(debug1, debug2,start) begin
if(start) begin
LED2=~debug1;
LED3=~debug2;
end
end
assign LED1 = !number;
endmodule | 0 |
137,822 | data/full_repos/permissive/80489408/single_cycle.v | 80,489,408 | single_cycle.v | v | 84 | 80 | [] | [] | [] | [(1, 48), (50, 60), (62, 84)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80489408/single_cycle.v:50: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'single_cycle\'\nmodule single_cycle(input clk,input enable,output LED1,output reg LED2,LED3);\n ^~~~~~~~~~~~\n : ... Top module \'single_cycle_tp\'\nmodule single_cycle_tp(input clk,reset,output y,z);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80489408/single_cycle.v:69: Cannot find file containing module: \'memory\'\n memory im(PC,instruction);\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory.v\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory.sv\n memory\n memory.v\n memory.sv\n obj_dir/memory\n obj_dir/memory.v\n obj_dir/memory.sv\n%Error: data/full_repos/permissive/80489408/single_cycle.v:70: Cannot find file containing module: \'datamem\'\n datamem dm(DataAdr,WriteData,Write_Enable,ReadData,clk);\n ^~~~~~~\n%Error: data/full_repos/permissive/80489408/single_cycle.v:71: Cannot find file containing module: \'ARM\'\n ARM proc(clk,reset,instruction,ReadData,DataAdr,WriteData,Write_Enable,PC);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:78: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h7\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h00000014))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:78: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h14\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h00000014))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:80: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h7\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h0000001A))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:80: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1a\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h0000001A))\n ^~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n' | 300,635 | module | module single_cycle_tp(input clk,reset,output y,z);
reg [3:0]cnt;
assign y=cnt[2];
assign z=cnt[3];
always@(negedge clk,posedge reset) begin
if(reset)
cnt<=0;
else
cnt<=cnt+1'b1;
end
endmodule | module single_cycle_tp(input clk,reset,output y,z); |
reg [3:0]cnt;
assign y=cnt[2];
assign z=cnt[3];
always@(negedge clk,posedge reset) begin
if(reset)
cnt<=0;
else
cnt<=cnt+1'b1;
end
endmodule | 0 |
137,823 | data/full_repos/permissive/80489408/single_cycle.v | 80,489,408 | single_cycle.v | v | 84 | 80 | [] | [] | [] | [(1, 48), (50, 60), (62, 84)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80489408/single_cycle.v:50: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'single_cycle\'\nmodule single_cycle(input clk,input enable,output LED1,output reg LED2,LED3);\n ^~~~~~~~~~~~\n : ... Top module \'single_cycle_tp\'\nmodule single_cycle_tp(input clk,reset,output y,z);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80489408/single_cycle.v:69: Cannot find file containing module: \'memory\'\n memory im(PC,instruction);\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory.v\n data/full_repos/permissive/80489408,data/full_repos/permissive/80489408/memory.sv\n memory\n memory.v\n memory.sv\n obj_dir/memory\n obj_dir/memory.v\n obj_dir/memory.sv\n%Error: data/full_repos/permissive/80489408/single_cycle.v:70: Cannot find file containing module: \'datamem\'\n datamem dm(DataAdr,WriteData,Write_Enable,ReadData,clk);\n ^~~~~~~\n%Error: data/full_repos/permissive/80489408/single_cycle.v:71: Cannot find file containing module: \'ARM\'\n ARM proc(clk,reset,instruction,ReadData,DataAdr,WriteData,Write_Enable,PC);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:78: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h7\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h00000014))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:78: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h14\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h00000014))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:80: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h7\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h0000001A))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/80489408/single_cycle.v:80: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1a\' generates 8 bits.\n : ... In instance single_cycle.sc\n if((WriteData==8\'h00000007)&(DataAdr==8\'h0000001A))\n ^~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n' | 300,635 | module | module single_cycle_top(clk,reset,debug1,debug2);
input clk;
input reset;
output reg debug1,debug2;
wire [31:0] instruction,PC;
wire [31:0] DataAdr,WriteData,ReadData;
wire Write_Enable;
memory im(PC,instruction);
datamem dm(DataAdr,WriteData,Write_Enable,ReadData,clk);
ARM proc(clk,reset,instruction,ReadData,DataAdr,WriteData,Write_Enable,PC);
always@(negedge clk,posedge reset) begin
if(reset) begin
debug1=0;
debug2=0;
end else begin
if((WriteData==8'h00000007)&(DataAdr==8'h00000014))
debug1=1;
if((WriteData==8'h00000007)&(DataAdr==8'h0000001A))
debug2=1;
end
end
endmodule | module single_cycle_top(clk,reset,debug1,debug2); |
input clk;
input reset;
output reg debug1,debug2;
wire [31:0] instruction,PC;
wire [31:0] DataAdr,WriteData,ReadData;
wire Write_Enable;
memory im(PC,instruction);
datamem dm(DataAdr,WriteData,Write_Enable,ReadData,clk);
ARM proc(clk,reset,instruction,ReadData,DataAdr,WriteData,Write_Enable,PC);
always@(negedge clk,posedge reset) begin
if(reset) begin
debug1=0;
debug2=0;
end else begin
if((WriteData==8'h00000007)&(DataAdr==8'h00000014))
debug1=1;
if((WriteData==8'h00000007)&(DataAdr==8'h0000001A))
debug2=1;
end
end
endmodule | 0 |
137,824 | data/full_repos/permissive/80510879/btn.v | 80,510,879 | btn.v | v | 43 | 83 | [] | [] | [] | [(21, 42)] | null | data/verilator_xmls/bbf4c996-2aef-4822-b581-02e0709a01e2.xml | null | 300,636 | module | module btn_module(
input clk,
input wire[4:0] btn,
output reg [31:0] wdata
);
always @ (posedge clk) begin
if(btn == 1) begin
wdata <= 1;
end else if (btn == 2) begin
wdata <= 2;
end else if (btn == 4) begin
wdata <= 3;
end else if (btn == 8) begin
wdata <= 4;
end else if (btn == 16) begin
wdata <= 5;
end else begin
wdata <= 0;
end
end
endmodule | module btn_module(
input clk,
input wire[4:0] btn,
output reg [31:0] wdata
); |
always @ (posedge clk) begin
if(btn == 1) begin
wdata <= 1;
end else if (btn == 2) begin
wdata <= 2;
end else if (btn == 4) begin
wdata <= 3;
end else if (btn == 8) begin
wdata <= 4;
end else if (btn == 16) begin
wdata <= 5;
end else begin
wdata <= 0;
end
end
endmodule | 1 |
137,825 | data/full_repos/permissive/80510879/btn_tb.v | 80,510,879 | btn_tb.v | v | 70 | 81 | [] | [] | [] | [(25, 68)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/80510879/btn_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #100 btn = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80510879/btn_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100 btn = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80510879/btn_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100 btn = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80510879/btn_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100 btn = 8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80510879/btn_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100 btn = 16;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80510879/btn_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100 btn = 7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80510879/btn_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/80510879/btn_tb.v:39: Cannot find file containing module: \'btn_module\'\n btn_module uut (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/btn_module\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/btn_module.v\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/btn_module.sv\n btn_module\n btn_module.v\n btn_module.sv\n obj_dir/btn_module\n obj_dir/btn_module.v\n obj_dir/btn_module.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,637 | module | module btn_tb;
reg clk;
reg [4:0] btn;
wire we;
wire enabler;
wire [31:0] waddr;
wire [31:0] wdata;
wire [3:0] select;
btn_module uut (
.clk(clk),
.btn(btn),
.we(we),
.enabler(enabler),
.waddr(waddr),
.wdata(wdata),
.select(select)
);
initial begin
clk = 0;
btn = 0;
#100 btn = 1;
#100 btn = 2;
#100 btn = 4;
#100 btn = 8;
#100 btn = 16;
#100 btn = 7;
end
always #10 clk = ~clk;
endmodule | module btn_tb; |
reg clk;
reg [4:0] btn;
wire we;
wire enabler;
wire [31:0] waddr;
wire [31:0] wdata;
wire [3:0] select;
btn_module uut (
.clk(clk),
.btn(btn),
.we(we),
.enabler(enabler),
.waddr(waddr),
.wdata(wdata),
.select(select)
);
initial begin
clk = 0;
btn = 0;
#100 btn = 1;
#100 btn = 2;
#100 btn = 4;
#100 btn = 8;
#100 btn = 16;
#100 btn = 7;
end
always #10 clk = ~clk;
endmodule | 1 |
137,829 | data/full_repos/permissive/80510879/execute.v | 80,510,879 | execute.v | v | 302 | 203 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 525: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/80510879/execute.v:2: Cannot find include file: defineOperator.v\n`include "defineOperator.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/defineOperator.v\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/defineOperator.v.v\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/defineOperator.v.sv\n defineOperator.v\n defineOperator.v.v\n defineOperator.v.sv\n obj_dir/defineOperator.v\n obj_dir/defineOperator.v.v\n obj_dir/defineOperator.v.sv\n%Error: data/full_repos/permissive/80510879/execute.v:78: Define or directive not defined: \'`ALUOP_SUB\'\n assign regOp2_mux = ((aluop_input == `ALUOP_SUB) || (aluop_input == `ALUOP_SUBU) || (aluop_input == `ALUOP_SLT)) ? (~regOp2) + 1 : regOp2;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:78: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign regOp2_mux = ((aluop_input == `ALUOP_SUB) || (aluop_input == `ALUOP_SUBU) || (aluop_input == `ALUOP_SLT)) ? (~regOp2) + 1 : regOp2;\n ^\n%Error: data/full_repos/permissive/80510879/execute.v:78: Define or directive not defined: \'`ALUOP_SUBU\'\n assign regOp2_mux = ((aluop_input == `ALUOP_SUB) || (aluop_input == `ALUOP_SUBU) || (aluop_input == `ALUOP_SLT)) ? (~regOp2) + 1 : regOp2;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:78: Define or directive not defined: \'`ALUOP_SLT\'\n assign regOp2_mux = ((aluop_input == `ALUOP_SUB) || (aluop_input == `ALUOP_SUBU) || (aluop_input == `ALUOP_SLT)) ? (~regOp2) + 1 : regOp2;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:84: Define or directive not defined: \'`ALUOP_SLT\'\n assign reg1_lt_reg2 = (aluop_input == `ALUOP_SLT) ? ((regOp1[31] && !regOp2[31]) || (!regOp1[31] && !regOp2[31] && sum_result[31]) || (regOp1[31] && regOp2[31] && sum_result[31])):(regOp1 < regOp2);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign reg1_lt_reg2 = (aluop_input == `ALUOP_SLT) ? ((regOp1[31] && !regOp2[31]) || (!regOp1[31] && !regOp2[31] && sum_result[31]) || (regOp1[31] && regOp2[31] && sum_result[31])):(regOp1 < regOp2);\n ^\n%Error: data/full_repos/permissive/80510879/execute.v:88: Define or directive not defined: \'`ALUOP_MUL\'\n assign mulOp1 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp1[31] == 1)) ? (~regOp1) + 1 : regOp1;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:88: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign mulOp1 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp1[31] == 1)) ? (~regOp1) + 1 : regOp1;\n ^\n%Error: data/full_repos/permissive/80510879/execute.v:88: Define or directive not defined: \'`ALUOP_MULT\'\n assign mulOp1 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp1[31] == 1)) ? (~regOp1) + 1 : regOp1;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:90: Define or directive not defined: \'`ALUOP_MUL\'\n assign mulOp2 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp2[31] == 1)) ? (~regOp2) + 1 : regOp2;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:90: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign mulOp2 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp2[31] == 1)) ? (~regOp2) + 1 : regOp2;\n ^\n%Error: data/full_repos/permissive/80510879/execute.v:90: Define or directive not defined: \'`ALUOP_MULT\'\n assign mulOp2 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp2[31] == 1)) ? (~regOp2) + 1 : regOp2;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:107: Define or directive not defined: \'`ALUOP_SLT\'\n `ALUOP_SLT:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:107: syntax error, unexpected \':\', expecting endcase\n `ALUOP_SLT:\n ^\n%Error: data/full_repos/permissive/80510879/execute.v:109: Define or directive not defined: \'`ALUOP_SLTU\'\n `ALUOP_SLTU: \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:112: Define or directive not defined: \'`ALUOP_ADD\'\n `ALUOP_ADD:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:114: Define or directive not defined: \'`ALUOP_ADDU\'\n `ALUOP_ADDU:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:116: Define or directive not defined: \'`ALUOP_ADDI\'\n `ALUOP_ADDI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:118: Define or directive not defined: \'`ALUOP_ADDIU\'\n `ALUOP_ADDIU:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:121: Define or directive not defined: \'`ALUOP_SUB\'\n `ALUOP_SUB:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:123: Define or directive not defined: \'`ALUOP_SUBU\'\n `ALUOP_SUBU:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:125: Define or directive not defined: \'`ALUOP_CLZ\'\n `ALUOP_CLZ: \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:137: Define or directive not defined: \'`ALUOP_CLO\'\n `ALUOP_CLO:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:158: Define or directive not defined: \'`ALUOP_MULT\'\n end else if((aluop_input == `ALUOP_MULT) || (aluop_input == `ALUOP_MUL)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:158: Define or directive not defined: \'`ALUOP_MUL\'\n end else if((aluop_input == `ALUOP_MULT) || (aluop_input == `ALUOP_MUL)) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:177: Define or directive not defined: \'`ALUOP_AND\'\n `ALUOP_AND: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:180: Define or directive not defined: \'`ALUOP_OR\'\n `ALUOP_OR: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:183: Define or directive not defined: \'`ALUOP_XOR\'\n `ALUOP_XOR: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:186: Define or directive not defined: \'`ALUOP_NOR\'\n `ALUOP_NOR: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:189: Define or directive not defined: \'`ALUOP_ANDI\'\n `ALUOP_ANDI: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:192: Define or directive not defined: \'`ALUOP_ORI\'\n `ALUOP_ORI: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:195: Define or directive not defined: \'`ALUOP_XORI\'\n `ALUOP_XORI: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:198: Define or directive not defined: \'`ALUOP_LUI\'\n `ALUOP_LUI: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:201: Define or directive not defined: \'`ALUOP_SLL\'\n `ALUOP_SLL: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:204: Define or directive not defined: \'`ALUOP_SLLV\'\n `ALUOP_SLLV: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:207: Define or directive not defined: \'`ALUOP_SRL\'\n `ALUOP_SRL: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:210: Define or directive not defined: \'`ALUOP_SRLV\'\n `ALUOP_SRLV: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:213: Define or directive not defined: \'`ALUOP_SRA\'\n `ALUOP_SRA: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:216: Define or directive not defined: \'`ALUOP_SRAV\'\n `ALUOP_SRAV: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:219: Define or directive not defined: \'`ALUOP_MOVN\'\n `ALUOP_MOVN: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:222: Define or directive not defined: \'`ALUOP_MOVZ\'\n `ALUOP_MOVZ: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:225: Define or directive not defined: \'`ALUOP_MFHI\'\n `ALUOP_MFHI: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:228: Define or directive not defined: \'`ALUOP_MFLO\'\n `ALUOP_MFLO: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:231: Define or directive not defined: \'`ALUOP_MTHI\'\n `ALUOP_MTHI: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:235: Define or directive not defined: \'`ALUOP_MTLO\'\n `ALUOP_MTLO: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:239: Define or directive not defined: \'`ALUOP_MULT\'\n `ALUOP_MULT, `ALUOP_MULTU: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:239: Define or directive not defined: \'`ALUOP_MULTU\'\n `ALUOP_MULT, `ALUOP_MULTU: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:244: Define or directive not defined: \'`ALUOP_MTHI\'\n `ALUOP_MTHI: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/execute.v:249: Define or directive not defined: \'`ALUOP_MTLO\'\n `ALUOP_MTLO: begin\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 300,642 | module | module execute(
input rst,
input wire[7:0] aluop_input,
input wire[2:0] alusel_input,
input wire[31:0] regOp1,
input wire[31:0] regOp2,
input wire[4:0] dest_addr,
input write_or_not,
input wire memory_HILO_enabler,
input wire[31:0] memory_HILO_HI,
input wire[31:0] memory_HILO_LO,
input wire memory2writeback_HILO_enabler,
input wire[31:0] memory2writeback_HILO_HI,
input wire[31:0] memory2writeback_HILO_LO,
input wire [31:0] hilo0_HILO_HI,
input wire [31:0] hilo0_HILO_LO,
input wire[31:0] ret_addr,
input wire in_delayslot,
output reg[4:0] dest_addr_output,
output reg write_or_not_output,
output reg[31:0] wdata_output,
output reg execute_HILO_enabler,
output reg[31:0] execute_HILO_HI,
output reg[31:0] execute_HILO_LO,
input wire[31:0] insDecode2execute_ins,
output wire[7:0] aluop_output,
output wire[31:0] mem_addr_output,
output wire[31:0] regOp2_output,
output execute_pause_output
);
reg [31:0] opOut;
reg [31:0] hi;
reg [31:0] lo;
wire overflow;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
reg[31:0] arch_answer;
wire[31:0] regOp2_mux;
wire[31:0] regOp1_not;
wire[31:0] sum_result;
wire[31:0] mulOp1;
wire[31:0] mulOp2;
wire[63:0] mul_temp;
reg[63:0] mul_result;
assign regOp2_mux = ((aluop_input == `ALUOP_SUB) || (aluop_input == `ALUOP_SUBU) || (aluop_input == `ALUOP_SLT)) ? (~regOp2) + 1 : regOp2;
assign sum_result = regOp1 + regOp2_mux;
assign overflow = (!regOp1[31] && !regOp2[31] && sum_result[31]) || (regOp1[31] && regOp2[31] && !sum_result[31]);
assign reg1_lt_reg2 = (aluop_input == `ALUOP_SLT) ? ((regOp1[31] && !regOp2[31]) || (!regOp1[31] && !regOp2[31] && sum_result[31]) || (regOp1[31] && regOp2[31] && sum_result[31])):(regOp1 < regOp2);
assign regOp1_not = ~regOp1;
assign mulOp1 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp1[31] == 1)) ? (~regOp1) + 1 : regOp1;
assign mulOp2 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp2[31] == 1)) ? (~regOp2) + 1 : regOp2;
assign mul_temp = mulOp1 * mulOp2;
assign aluop_output = aluop_input;
assign mem_addr_output = regOp1 + {{16{insDecode2execute_ins[15]}}, insDecode2execute_ins[15:0]};
assign regOp2_output = regOp2;
assign execute_pause_output = 0;
always @ (*) begin
if (rst == 1'b1) begin
arch_answer <= 0;
end else begin
case (aluop_input)
`ALUOP_SLT:
arch_answer <= reg1_lt_reg2;
`ALUOP_SLTU:
arch_answer <= reg1_lt_reg2;
`ALUOP_ADD:
arch_answer <= sum_result;
`ALUOP_ADDU:
arch_answer <= sum_result;
`ALUOP_ADDI:
arch_answer <= sum_result;
`ALUOP_ADDIU:
arch_answer <= sum_result;
`ALUOP_SUB:
arch_answer <= sum_result;
`ALUOP_SUBU:
arch_answer <= sum_result;
`ALUOP_CLZ:
arch_answer <= regOp1[31] ? 0 : regOp1[30] ? 1 : regOp1[29] ? 2 :
regOp1[28] ? 3 : regOp1[27] ? 4 : regOp1[26] ? 5 :
regOp1[25] ? 6 : regOp1[24] ? 7 : regOp1[23] ? 8 :
regOp1[22] ? 9 : regOp1[21] ? 10 : regOp1[20] ? 11 :
regOp1[19] ? 12 : regOp1[18] ? 13 : regOp1[17] ? 14 :
regOp1[16] ? 15 : regOp1[15] ? 16 : regOp1[14] ? 17 :
regOp1[13] ? 18 : regOp1[12] ? 19 : regOp1[11] ? 20 :
regOp1[10] ? 21 : regOp1[9] ? 22 : regOp1[8] ? 23 :
regOp1[7] ? 24 : regOp1[6] ? 25 : regOp1[5] ? 26 :
regOp1[4] ? 27 : regOp1[3] ? 28 : regOp1[2] ? 29 :
regOp1[1] ? 30 : regOp1[0] ? 31 : 32 ;
`ALUOP_CLO:
arch_answer <= regOp1_not[31] ? 0 : regOp1_not[30] ? 1 : regOp1_not[29] ? 2 :
regOp1_not[28] ? 3 : regOp1_not[27] ? 4 : regOp1_not[26] ? 5 :
regOp1_not[25] ? 6 : regOp1_not[24] ? 7 : regOp1_not[23] ? 8 :
regOp1_not[22] ? 9 : regOp1_not[21] ? 10 : regOp1_not[20] ? 11 :
regOp1_not[19] ? 12 : regOp1_not[18] ? 13 : regOp1_not[17] ? 14 :
regOp1_not[16] ? 15 : regOp1_not[15] ? 16 : regOp1_not[14] ? 17 :
regOp1_not[13] ? 18 : regOp1_not[12] ? 19 : regOp1_not[11] ? 20 :
regOp1_not[10] ? 21 : regOp1_not[9] ? 22 : regOp1_not[8] ? 23 :
regOp1_not[7] ? 24 : regOp1_not[6] ? 25 : regOp1_not[5] ? 26 :
regOp1_not[4] ? 27 : regOp1_not[3] ? 28 : regOp1_not[2] ? 29 :
regOp1_not[1] ? 30 : regOp1_not[0] ? 31 : 32 ;
default:
arch_answer <= 0;
endcase
end
end
always @ (*) begin
if (rst == 1) begin
mul_result <= 0;
end else if((aluop_input == `ALUOP_MULT) || (aluop_input == `ALUOP_MUL)) begin
if (regOp1[31] ^ regOp2[31] == 1) begin
mul_result <= ~mul_temp + 1;
end else begin
mul_result <= mul_temp;
end
end else begin
mul_result <= mul_temp;
end
end
always @ (*) begin
if(rst == 1) begin
opOut <= 0;
execute_HILO_enabler <= 0;
execute_HILO_HI <= 0;
execute_HILO_LO <= 0;
end else begin
case (aluop_input)
`ALUOP_AND: begin
opOut <= regOp1 & regOp2;
end
`ALUOP_OR: begin
opOut <= regOp1 | regOp2;
end
`ALUOP_XOR: begin
opOut <= regOp1 ^ regOp2;
end
`ALUOP_NOR: begin
opOut <= ~(regOp1 | regOp2);
end
`ALUOP_ANDI: begin
opOut <= regOp1 & regOp2;
end
`ALUOP_ORI: begin
opOut <= regOp1 | regOp2;
end
`ALUOP_XORI: begin
opOut <= regOp1 ^ regOp2;
end
`ALUOP_LUI: begin
opOut <= regOp2;
end
`ALUOP_SLL: begin
opOut <= regOp2 << regOp1;
end
`ALUOP_SLLV: begin
opOut <= regOp2 << regOp1;
end
`ALUOP_SRL: begin
opOut <= regOp2 >> regOp1;
end
`ALUOP_SRLV: begin
opOut <= regOp2 >> regOp1;
end
`ALUOP_SRA: begin
opOut <= $signed(regOp2) >>> regOp1;
end
`ALUOP_SRAV: begin
opOut <= $signed(regOp2) >>> regOp1;
end
`ALUOP_MOVN: begin
opOut <= regOp1;
end
`ALUOP_MOVZ: begin
opOut <= regOp1;
end
`ALUOP_MFHI: begin
opOut <= hi;
end
`ALUOP_MFLO: begin
opOut <= lo;
end
`ALUOP_MTHI: begin
execute_HILO_enabler <= 1'b1;
execute_HILO_HI <= regOp1;
end
`ALUOP_MTLO: begin
execute_HILO_enabler <= 1'b1;
execute_HILO_LO <= regOp1;
end
`ALUOP_MULT, `ALUOP_MULTU: begin
execute_HILO_enabler <= 1;
execute_HILO_HI <= mul_result[63:32];
execute_HILO_LO <= mul_result[31:0];
end
`ALUOP_MTHI: begin
execute_HILO_enabler <= 1;
execute_HILO_HI <= regOp1;
execute_HILO_LO <= lo;
end
`ALUOP_MTLO: begin
execute_HILO_enabler <= 1;
execute_HILO_HI <= hi;
execute_HILO_LO <= regOp1;
end
default:begin
opOut <= 0;
execute_HILO_enabler <= 0;
end
endcase
end
end
always @ (*) begin
dest_addr_output <= dest_addr;
if((aluop_input == `ALUOP_ADD || aluop_input == `ALUOP_ADDI || aluop_input == `ALUOP_SUB) && overflow == 1)
write_or_not_output <= 0;
else
write_or_not_output <= write_or_not;
case (alusel_input)
`ALUSEL_LOGIC:
wdata_output <= opOut;
`ALUSEL_SHIFT:
wdata_output <= opOut;
`ALUSEL_MOVE:
wdata_output <= opOut;
`ALUSEL_ARCH:
wdata_output <= arch_answer;
`ALUSEL_MUL:
wdata_output <= mul_result[31:0];
`ALUSEL_JUMP_BRANCH:
wdata_output <= ret_addr;
default:
wdata_output <= 0;
endcase
end
always @ (*) begin
if (memory_HILO_enabler == 1) begin
hi = memory_HILO_HI;
lo = memory_HILO_LO;
end else if (memory2writeback_HILO_enabler == 1) begin
hi = memory2writeback_HILO_HI;
lo = memory2writeback_HILO_LO;
end else begin
hi = hilo0_HILO_HI;
lo = hilo0_HILO_LO;
end
end
endmodule | module execute(
input rst,
input wire[7:0] aluop_input,
input wire[2:0] alusel_input,
input wire[31:0] regOp1,
input wire[31:0] regOp2,
input wire[4:0] dest_addr,
input write_or_not,
input wire memory_HILO_enabler,
input wire[31:0] memory_HILO_HI,
input wire[31:0] memory_HILO_LO,
input wire memory2writeback_HILO_enabler,
input wire[31:0] memory2writeback_HILO_HI,
input wire[31:0] memory2writeback_HILO_LO,
input wire [31:0] hilo0_HILO_HI,
input wire [31:0] hilo0_HILO_LO,
input wire[31:0] ret_addr,
input wire in_delayslot,
output reg[4:0] dest_addr_output,
output reg write_or_not_output,
output reg[31:0] wdata_output,
output reg execute_HILO_enabler,
output reg[31:0] execute_HILO_HI,
output reg[31:0] execute_HILO_LO,
input wire[31:0] insDecode2execute_ins,
output wire[7:0] aluop_output,
output wire[31:0] mem_addr_output,
output wire[31:0] regOp2_output,
output execute_pause_output
); |
reg [31:0] opOut;
reg [31:0] hi;
reg [31:0] lo;
wire overflow;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
reg[31:0] arch_answer;
wire[31:0] regOp2_mux;
wire[31:0] regOp1_not;
wire[31:0] sum_result;
wire[31:0] mulOp1;
wire[31:0] mulOp2;
wire[63:0] mul_temp;
reg[63:0] mul_result;
assign regOp2_mux = ((aluop_input == `ALUOP_SUB) || (aluop_input == `ALUOP_SUBU) || (aluop_input == `ALUOP_SLT)) ? (~regOp2) + 1 : regOp2;
assign sum_result = regOp1 + regOp2_mux;
assign overflow = (!regOp1[31] && !regOp2[31] && sum_result[31]) || (regOp1[31] && regOp2[31] && !sum_result[31]);
assign reg1_lt_reg2 = (aluop_input == `ALUOP_SLT) ? ((regOp1[31] && !regOp2[31]) || (!regOp1[31] && !regOp2[31] && sum_result[31]) || (regOp1[31] && regOp2[31] && sum_result[31])):(regOp1 < regOp2);
assign regOp1_not = ~regOp1;
assign mulOp1 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp1[31] == 1)) ? (~regOp1) + 1 : regOp1;
assign mulOp2 = ((( aluop_input == `ALUOP_MUL) || (aluop_input == `ALUOP_MULT)) && (regOp2[31] == 1)) ? (~regOp2) + 1 : regOp2;
assign mul_temp = mulOp1 * mulOp2;
assign aluop_output = aluop_input;
assign mem_addr_output = regOp1 + {{16{insDecode2execute_ins[15]}}, insDecode2execute_ins[15:0]};
assign regOp2_output = regOp2;
assign execute_pause_output = 0;
always @ (*) begin
if (rst == 1'b1) begin
arch_answer <= 0;
end else begin
case (aluop_input)
`ALUOP_SLT:
arch_answer <= reg1_lt_reg2;
`ALUOP_SLTU:
arch_answer <= reg1_lt_reg2;
`ALUOP_ADD:
arch_answer <= sum_result;
`ALUOP_ADDU:
arch_answer <= sum_result;
`ALUOP_ADDI:
arch_answer <= sum_result;
`ALUOP_ADDIU:
arch_answer <= sum_result;
`ALUOP_SUB:
arch_answer <= sum_result;
`ALUOP_SUBU:
arch_answer <= sum_result;
`ALUOP_CLZ:
arch_answer <= regOp1[31] ? 0 : regOp1[30] ? 1 : regOp1[29] ? 2 :
regOp1[28] ? 3 : regOp1[27] ? 4 : regOp1[26] ? 5 :
regOp1[25] ? 6 : regOp1[24] ? 7 : regOp1[23] ? 8 :
regOp1[22] ? 9 : regOp1[21] ? 10 : regOp1[20] ? 11 :
regOp1[19] ? 12 : regOp1[18] ? 13 : regOp1[17] ? 14 :
regOp1[16] ? 15 : regOp1[15] ? 16 : regOp1[14] ? 17 :
regOp1[13] ? 18 : regOp1[12] ? 19 : regOp1[11] ? 20 :
regOp1[10] ? 21 : regOp1[9] ? 22 : regOp1[8] ? 23 :
regOp1[7] ? 24 : regOp1[6] ? 25 : regOp1[5] ? 26 :
regOp1[4] ? 27 : regOp1[3] ? 28 : regOp1[2] ? 29 :
regOp1[1] ? 30 : regOp1[0] ? 31 : 32 ;
`ALUOP_CLO:
arch_answer <= regOp1_not[31] ? 0 : regOp1_not[30] ? 1 : regOp1_not[29] ? 2 :
regOp1_not[28] ? 3 : regOp1_not[27] ? 4 : regOp1_not[26] ? 5 :
regOp1_not[25] ? 6 : regOp1_not[24] ? 7 : regOp1_not[23] ? 8 :
regOp1_not[22] ? 9 : regOp1_not[21] ? 10 : regOp1_not[20] ? 11 :
regOp1_not[19] ? 12 : regOp1_not[18] ? 13 : regOp1_not[17] ? 14 :
regOp1_not[16] ? 15 : regOp1_not[15] ? 16 : regOp1_not[14] ? 17 :
regOp1_not[13] ? 18 : regOp1_not[12] ? 19 : regOp1_not[11] ? 20 :
regOp1_not[10] ? 21 : regOp1_not[9] ? 22 : regOp1_not[8] ? 23 :
regOp1_not[7] ? 24 : regOp1_not[6] ? 25 : regOp1_not[5] ? 26 :
regOp1_not[4] ? 27 : regOp1_not[3] ? 28 : regOp1_not[2] ? 29 :
regOp1_not[1] ? 30 : regOp1_not[0] ? 31 : 32 ;
default:
arch_answer <= 0;
endcase
end
end
always @ (*) begin
if (rst == 1) begin
mul_result <= 0;
end else if((aluop_input == `ALUOP_MULT) || (aluop_input == `ALUOP_MUL)) begin
if (regOp1[31] ^ regOp2[31] == 1) begin
mul_result <= ~mul_temp + 1;
end else begin
mul_result <= mul_temp;
end
end else begin
mul_result <= mul_temp;
end
end
always @ (*) begin
if(rst == 1) begin
opOut <= 0;
execute_HILO_enabler <= 0;
execute_HILO_HI <= 0;
execute_HILO_LO <= 0;
end else begin
case (aluop_input)
`ALUOP_AND: begin
opOut <= regOp1 & regOp2;
end
`ALUOP_OR: begin
opOut <= regOp1 | regOp2;
end
`ALUOP_XOR: begin
opOut <= regOp1 ^ regOp2;
end
`ALUOP_NOR: begin
opOut <= ~(regOp1 | regOp2);
end
`ALUOP_ANDI: begin
opOut <= regOp1 & regOp2;
end
`ALUOP_ORI: begin
opOut <= regOp1 | regOp2;
end
`ALUOP_XORI: begin
opOut <= regOp1 ^ regOp2;
end
`ALUOP_LUI: begin
opOut <= regOp2;
end
`ALUOP_SLL: begin
opOut <= regOp2 << regOp1;
end
`ALUOP_SLLV: begin
opOut <= regOp2 << regOp1;
end
`ALUOP_SRL: begin
opOut <= regOp2 >> regOp1;
end
`ALUOP_SRLV: begin
opOut <= regOp2 >> regOp1;
end
`ALUOP_SRA: begin
opOut <= $signed(regOp2) >>> regOp1;
end
`ALUOP_SRAV: begin
opOut <= $signed(regOp2) >>> regOp1;
end
`ALUOP_MOVN: begin
opOut <= regOp1;
end
`ALUOP_MOVZ: begin
opOut <= regOp1;
end
`ALUOP_MFHI: begin
opOut <= hi;
end
`ALUOP_MFLO: begin
opOut <= lo;
end
`ALUOP_MTHI: begin
execute_HILO_enabler <= 1'b1;
execute_HILO_HI <= regOp1;
end
`ALUOP_MTLO: begin
execute_HILO_enabler <= 1'b1;
execute_HILO_LO <= regOp1;
end
`ALUOP_MULT, `ALUOP_MULTU: begin
execute_HILO_enabler <= 1;
execute_HILO_HI <= mul_result[63:32];
execute_HILO_LO <= mul_result[31:0];
end
`ALUOP_MTHI: begin
execute_HILO_enabler <= 1;
execute_HILO_HI <= regOp1;
execute_HILO_LO <= lo;
end
`ALUOP_MTLO: begin
execute_HILO_enabler <= 1;
execute_HILO_HI <= hi;
execute_HILO_LO <= regOp1;
end
default:begin
opOut <= 0;
execute_HILO_enabler <= 0;
end
endcase
end
end
always @ (*) begin
dest_addr_output <= dest_addr;
if((aluop_input == `ALUOP_ADD || aluop_input == `ALUOP_ADDI || aluop_input == `ALUOP_SUB) && overflow == 1)
write_or_not_output <= 0;
else
write_or_not_output <= write_or_not;
case (alusel_input)
`ALUSEL_LOGIC:
wdata_output <= opOut;
`ALUSEL_SHIFT:
wdata_output <= opOut;
`ALUSEL_MOVE:
wdata_output <= opOut;
`ALUSEL_ARCH:
wdata_output <= arch_answer;
`ALUSEL_MUL:
wdata_output <= mul_result[31:0];
`ALUSEL_JUMP_BRANCH:
wdata_output <= ret_addr;
default:
wdata_output <= 0;
endcase
end
always @ (*) begin
if (memory_HILO_enabler == 1) begin
hi = memory_HILO_HI;
lo = memory_HILO_LO;
end else if (memory2writeback_HILO_enabler == 1) begin
hi = memory2writeback_HILO_HI;
lo = memory2writeback_HILO_LO;
end else begin
hi = hilo0_HILO_HI;
lo = hilo0_HILO_LO;
end
end
endmodule | 1 |
137,833 | data/full_repos/permissive/80510879/insDecode2execute.v | 80,510,879 | insDecode2execute.v | v | 76 | 83 | [] | [] | [] | [(21, 75)] | null | data/verilator_xmls/053b4820-c453-4885-9fca-95de7b533fc6.xml | null | 300,646 | module | module insDecode2execute(
input clk,
input rst,
input wire[7:0] aluop_input,
input wire[2:0] alusel_input,
input wire[31:0] regOp1,
input wire[31:0] regOp2,
input wire[4:0] dest_addr,
input write_or_not,
output reg[7:0] aluop_output,
output reg[2:0] alusel_output,
output reg[31:0] regOp1_output,
output reg[31:0] regOp2_output,
output reg[4:0] dest_addr_output,
output reg write_or_not_output,
input in_delayslot,
input wire[31:0] ret_addr,
input next_delay,
output reg execute_in_delayslot,
output reg[31:0] ret_addr_output,
output reg insDecode_in_delayslot,
input wire[31:0] insDecode_ins,
output reg[31:0] insDecode2execute_ins,
input wire[5:0] control
);
always @ (posedge clk) begin
if(rst == 1) begin
aluop_output <= 0;
alusel_output <= 0;
regOp1_output <= 0;
regOp2_output <= 0;
dest_addr_output <= 0;
write_or_not_output <= 0;
end else if(control[2] == 0) begin
aluop_output <= aluop_input;
alusel_output <= alusel_input;
regOp1_output <= regOp1;
regOp2_output <= regOp2;
dest_addr_output <= dest_addr;
write_or_not_output <= write_or_not;
ret_addr_output <= ret_addr;
execute_in_delayslot <= in_delayslot;
insDecode_in_delayslot <= next_delay;
insDecode2execute_ins <= insDecode_ins;
end
end
endmodule | module insDecode2execute(
input clk,
input rst,
input wire[7:0] aluop_input,
input wire[2:0] alusel_input,
input wire[31:0] regOp1,
input wire[31:0] regOp2,
input wire[4:0] dest_addr,
input write_or_not,
output reg[7:0] aluop_output,
output reg[2:0] alusel_output,
output reg[31:0] regOp1_output,
output reg[31:0] regOp2_output,
output reg[4:0] dest_addr_output,
output reg write_or_not_output,
input in_delayslot,
input wire[31:0] ret_addr,
input next_delay,
output reg execute_in_delayslot,
output reg[31:0] ret_addr_output,
output reg insDecode_in_delayslot,
input wire[31:0] insDecode_ins,
output reg[31:0] insDecode2execute_ins,
input wire[5:0] control
); |
always @ (posedge clk) begin
if(rst == 1) begin
aluop_output <= 0;
alusel_output <= 0;
regOp1_output <= 0;
regOp2_output <= 0;
dest_addr_output <= 0;
write_or_not_output <= 0;
end else if(control[2] == 0) begin
aluop_output <= aluop_input;
alusel_output <= alusel_input;
regOp1_output <= regOp1;
regOp2_output <= regOp2;
dest_addr_output <= dest_addr;
write_or_not_output <= write_or_not;
ret_addr_output <= ret_addr;
execute_in_delayslot <= in_delayslot;
insDecode_in_delayslot <= next_delay;
insDecode2execute_ins <= insDecode_ins;
end
end
endmodule | 1 |
137,834 | data/full_repos/permissive/80510879/insFetch2insDecode.v | 80,510,879 | insFetch2insDecode.v | v | 45 | 83 | [] | [] | [] | [(22, 44)] | null | data/verilator_xmls/2bce5902-247f-4f69-a1b6-79e561190acf.xml | null | 300,647 | module | module insFetch2insDecode(
input clk,
input rst,
input wire[31:0] insFetchPC,
input wire[31:0] insFetchInst,
output reg[31:0] insDecodePC,
output reg[31:0] insDecodeInst,
input wire[5:0] control
);
always @ (posedge clk) begin
if (rst == 1) begin
insDecodePC <= 0;
insDecodeInst <= 0;
end
else if(control[1] == 0) begin
insDecodePC <= insFetchPC;
insDecodeInst <= insFetchInst;
end
end
endmodule | module insFetch2insDecode(
input clk,
input rst,
input wire[31:0] insFetchPC,
input wire[31:0] insFetchInst,
output reg[31:0] insDecodePC,
output reg[31:0] insDecodeInst,
input wire[5:0] control
); |
always @ (posedge clk) begin
if (rst == 1) begin
insDecodePC <= 0;
insDecodeInst <= 0;
end
else if(control[1] == 0) begin
insDecodePC <= insFetchPC;
insDecodeInst <= insFetchInst;
end
end
endmodule | 1 |
137,835 | data/full_repos/permissive/80510879/insRom.v | 80,510,879 | insRom.v | v | 39 | 83 | [] | [] | [] | [(21, 38)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80510879/insRom.v:35: Bit extraction of array[255:0] requires 8 bit index, not 17 bits.\n : ... In instance instRom\n spo <= instMem[a[18:2]];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 300,648 | module | module instRom(
input enabler,
input wire[31:0] a,
output reg[31:0] spo
);
reg[31:0] instMem[0:255];
initial $readmemh( "instRom.data", instMem );
always @ (*) begin
if (enabler == 0)
spo <= 0;
else
spo <= instMem[a[18:2]];
end
endmodule | module instRom(
input enabler,
input wire[31:0] a,
output reg[31:0] spo
); |
reg[31:0] instMem[0:255];
initial $readmemh( "instRom.data", instMem );
always @ (*) begin
if (enabler == 0)
spo <= 0;
else
spo <= instMem[a[18:2]];
end
endmodule | 1 |
137,836 | data/full_repos/permissive/80510879/memory.v | 80,510,879 | memory.v | v | 315 | 93 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 525: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/80510879/memory.v:2: Cannot find include file: defineOperator.v\n`include "defineOperator.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/defineOperator.v\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/defineOperator.v.v\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/defineOperator.v.sv\n defineOperator.v\n defineOperator.v.v\n defineOperator.v.sv\n obj_dir/defineOperator.v\n obj_dir/defineOperator.v.v\n obj_dir/defineOperator.v.sv\n%Error: data/full_repos/permissive/80510879/memory.v:71: Define or directive not defined: \'`ALUOP_LB\'\n `ALUOP_LB: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:71: syntax error, unexpected \':\', expecting endcase\n `ALUOP_LB: begin\n ^\n%Error: data/full_repos/permissive/80510879/memory.v:97: Define or directive not defined: \'`ALUOP_LBU\'\n `ALUOP_LBU: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:97: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_LBU: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:123: Define or directive not defined: \'`ALUOP_LH\'\n `ALUOP_LH: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:123: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_LH: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:141: Define or directive not defined: \'`ALUOP_LHU\'\n `ALUOP_LHU: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:141: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_LHU: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:159: Define or directive not defined: \'`ALUOP_LW\'\n `ALUOP_LW: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:159: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_LW: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:166: Define or directive not defined: \'`ALUOP_LWL\'\n `ALUOP_LWL: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:166: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_LWL: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:189: Define or directive not defined: \'`ALUOP_LWR\'\n `ALUOP_LWR: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:189: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_LWR: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:212: Define or directive not defined: \'`ALUOP_SB\'\n `ALUOP_SB: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:212: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_SB: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:235: Define or directive not defined: \'`ALUOP_SH\'\n `ALUOP_SH: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:235: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_SH: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:252: Define or directive not defined: \'`ALUOP_SW\'\n `ALUOP_SW: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:252: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_SW: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:259: Define or directive not defined: \'`ALUOP_SWL\'\n `ALUOP_SWL: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:259: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_SWL: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:285: Define or directive not defined: \'`ALUOP_SWR\'\n `ALUOP_SWR: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:285: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUOP_SWR: begin\n ^~~~~\n%Error: data/full_repos/permissive/80510879/memory.v:311: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: Cannot continue\n' | 300,649 | module | module memory(
input rst,
input wire[4:0] dest_addr,
input write_or_not,
input wire[31:0] wdata,
input execute2memory_HILO_enabler,
input wire[31:0] execute2memory_HILO_HI,
input wire[31:0] execute2memory_HILO_LO,
output reg[4:0] dest_addr_output,
output reg write_or_not_output,
output reg[31:0] wdata_output,
output reg memory_HILO_enabler,
output reg[31:0] memory_HILO_HI,
output reg[31:0] memory_HILO_LO,
input wire[7:0] aluop,
input wire[31:0] mem_addr,
input wire[31:0] regOp2,
input wire[31:0] mem_data,
output reg[31:0] mem_addr_output,
output reg[31:0] mem_data_output,
output reg mem_write_enabler_output,
output reg[3:0] mem_select_output,
output reg mem_enabler_output
);
always @ (*) begin
if (rst == 1) begin
dest_addr_output <= 0;
write_or_not_output <= 0;
wdata_output <= 0;
memory_HILO_enabler <= 0;
memory_HILO_HI <= 0;
memory_HILO_LO <= 0;
end else begin
dest_addr_output <= dest_addr;
write_or_not_output <= write_or_not;
wdata_output <= wdata;
memory_HILO_enabler <= execute2memory_HILO_enabler;
memory_HILO_HI <= execute2memory_HILO_HI;
memory_HILO_LO <= execute2memory_HILO_LO;
mem_write_enabler_output <= 0;
mem_addr_output <= 0;
mem_select_output <= 4'b1111;
mem_enabler_output <= 0;
case (aluop)
`ALUOP_LB: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{24{mem_data[31]}},mem_data[31:24]};
mem_select_output <= 4'b1000;
end
2'b01: begin
wdata_output <= {{24{mem_data[23]}},mem_data[23:16]};
mem_select_output <= 4'b0100;
end
2'b10: begin
wdata_output <= {{24{mem_data[15]}},mem_data[15:8]};
mem_select_output <= 4'b0010;
end
2'b11: begin
wdata_output <= {{24{mem_data[7]}},mem_data[7:0]};
mem_select_output <= 4'b0001;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LBU: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{24{1'b0}},mem_data[31:24]};
mem_select_output <= 4'b1000;
end
2'b01: begin
wdata_output <= {{24{1'b0}},mem_data[23:16]};
mem_select_output <= 4'b0100;
end
2'b10: begin
wdata_output <= {{24{1'b0}},mem_data[15:8]};
mem_select_output <= 4'b0010;
end
2'b11: begin
wdata_output <= {{24{1'b0}},mem_data[7:0]};
mem_select_output <= 4'b0001;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LH: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{16{mem_data[31]}},mem_data[31:16]};
mem_select_output <= 4'b1100;
end
2'b10: begin
wdata_output <= {{16{mem_data[15]}},mem_data[15:0]};
mem_select_output <= 4'b0011;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LHU: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{16{1'b0}},mem_data[31:16]};
mem_select_output <= 4'b1100;
end
2'b10: begin
wdata_output <= {{16{1'b0}},mem_data[15:0]};
mem_select_output <= 4'b0011;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LW: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
wdata_output <= mem_data;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
end
`ALUOP_LWL: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 0;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= mem_data[31:0];
end
2'b01: begin
wdata_output <= {mem_data[23:0],regOp2[7:0]};
end
2'b10: begin
wdata_output <= {mem_data[15:0],regOp2[15:0]};
end
2'b11: begin
wdata_output <= {mem_data[7:0],regOp2[23:0]};
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LWR: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 0;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {regOp2[31:8],mem_data[31:24]};
end
2'b01: begin
wdata_output <= {regOp2[31:16],mem_data[31:16]};
end
2'b10: begin
wdata_output <= {regOp2[31:24],mem_data[31:8]};
end
2'b11: begin
wdata_output <= mem_data;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_SB: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 1;
mem_data_output <= {regOp2[7:0],regOp2[7:0],regOp2[7:0],regOp2[7:0]};
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1000;
end
2'b01: begin
mem_select_output <= 4'b0100;
end
2'b10: begin
mem_select_output <= 4'b0010;
end
2'b11: begin
mem_select_output <= 4'b0001;
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
`ALUOP_SH: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 1;
mem_data_output <= {regOp2[15:0],regOp2[15:0]};
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1100;
end
2'b10: begin
mem_select_output <= 4'b0011;
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
`ALUOP_SW: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 1;
mem_data_output <= regOp2;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
end
`ALUOP_SWL: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 1;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1111;
mem_data_output <= regOp2;
end
2'b01: begin
mem_select_output <= 4'b0111;
mem_data_output <= {8'b00000000,regOp2[31:8]};
end
2'b10: begin
mem_select_output <= 4'b0011;
mem_data_output <= {16'b0000000000000000,regOp2[31:16]};
end
2'b11: begin
mem_select_output <= 4'b0001;
mem_data_output <= {24'b000000000000000000000000,regOp2[31:24]};
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
`ALUOP_SWR: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 1;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1000;
mem_data_output <= {regOp2[7:0],24'b000000000000000000000000};
end
2'b01: begin
mem_select_output <= 4'b1100;
mem_data_output <= {regOp2[15:0],16'b0000000000000000};
end
2'b10: begin
mem_select_output <= 4'b1110;
mem_data_output <= {regOp2[23:0],8'b00000000};
end
2'b11: begin
mem_select_output <= 4'b1111;
mem_data_output <= regOp2[31:0];
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
endcase
end
end
endmodule | module memory(
input rst,
input wire[4:0] dest_addr,
input write_or_not,
input wire[31:0] wdata,
input execute2memory_HILO_enabler,
input wire[31:0] execute2memory_HILO_HI,
input wire[31:0] execute2memory_HILO_LO,
output reg[4:0] dest_addr_output,
output reg write_or_not_output,
output reg[31:0] wdata_output,
output reg memory_HILO_enabler,
output reg[31:0] memory_HILO_HI,
output reg[31:0] memory_HILO_LO,
input wire[7:0] aluop,
input wire[31:0] mem_addr,
input wire[31:0] regOp2,
input wire[31:0] mem_data,
output reg[31:0] mem_addr_output,
output reg[31:0] mem_data_output,
output reg mem_write_enabler_output,
output reg[3:0] mem_select_output,
output reg mem_enabler_output
); |
always @ (*) begin
if (rst == 1) begin
dest_addr_output <= 0;
write_or_not_output <= 0;
wdata_output <= 0;
memory_HILO_enabler <= 0;
memory_HILO_HI <= 0;
memory_HILO_LO <= 0;
end else begin
dest_addr_output <= dest_addr;
write_or_not_output <= write_or_not;
wdata_output <= wdata;
memory_HILO_enabler <= execute2memory_HILO_enabler;
memory_HILO_HI <= execute2memory_HILO_HI;
memory_HILO_LO <= execute2memory_HILO_LO;
mem_write_enabler_output <= 0;
mem_addr_output <= 0;
mem_select_output <= 4'b1111;
mem_enabler_output <= 0;
case (aluop)
`ALUOP_LB: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{24{mem_data[31]}},mem_data[31:24]};
mem_select_output <= 4'b1000;
end
2'b01: begin
wdata_output <= {{24{mem_data[23]}},mem_data[23:16]};
mem_select_output <= 4'b0100;
end
2'b10: begin
wdata_output <= {{24{mem_data[15]}},mem_data[15:8]};
mem_select_output <= 4'b0010;
end
2'b11: begin
wdata_output <= {{24{mem_data[7]}},mem_data[7:0]};
mem_select_output <= 4'b0001;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LBU: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{24{1'b0}},mem_data[31:24]};
mem_select_output <= 4'b1000;
end
2'b01: begin
wdata_output <= {{24{1'b0}},mem_data[23:16]};
mem_select_output <= 4'b0100;
end
2'b10: begin
wdata_output <= {{24{1'b0}},mem_data[15:8]};
mem_select_output <= 4'b0010;
end
2'b11: begin
wdata_output <= {{24{1'b0}},mem_data[7:0]};
mem_select_output <= 4'b0001;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LH: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{16{mem_data[31]}},mem_data[31:16]};
mem_select_output <= 4'b1100;
end
2'b10: begin
wdata_output <= {{16{mem_data[15]}},mem_data[15:0]};
mem_select_output <= 4'b0011;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LHU: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {{16{1'b0}},mem_data[31:16]};
mem_select_output <= 4'b1100;
end
2'b10: begin
wdata_output <= {{16{1'b0}},mem_data[15:0]};
mem_select_output <= 4'b0011;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LW: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 0;
wdata_output <= mem_data;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
end
`ALUOP_LWL: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 0;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= mem_data[31:0];
end
2'b01: begin
wdata_output <= {mem_data[23:0],regOp2[7:0]};
end
2'b10: begin
wdata_output <= {mem_data[15:0],regOp2[15:0]};
end
2'b11: begin
wdata_output <= {mem_data[7:0],regOp2[23:0]};
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_LWR: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 0;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
wdata_output <= {regOp2[31:8],mem_data[31:24]};
end
2'b01: begin
wdata_output <= {regOp2[31:16],mem_data[31:16]};
end
2'b10: begin
wdata_output <= {regOp2[31:24],mem_data[31:8]};
end
2'b11: begin
wdata_output <= mem_data;
end
default: begin
wdata_output <= 0;
end
endcase
end
`ALUOP_SB: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 1;
mem_data_output <= {regOp2[7:0],regOp2[7:0],regOp2[7:0],regOp2[7:0]};
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1000;
end
2'b01: begin
mem_select_output <= 4'b0100;
end
2'b10: begin
mem_select_output <= 4'b0010;
end
2'b11: begin
mem_select_output <= 4'b0001;
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
`ALUOP_SH: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 1;
mem_data_output <= {regOp2[15:0],regOp2[15:0]};
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1100;
end
2'b10: begin
mem_select_output <= 4'b0011;
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
`ALUOP_SW: begin
mem_addr_output <= mem_addr;
mem_write_enabler_output <= 1;
mem_data_output <= regOp2;
mem_select_output <= 4'b1111;
mem_enabler_output <= 1;
end
`ALUOP_SWL: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 1;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1111;
mem_data_output <= regOp2;
end
2'b01: begin
mem_select_output <= 4'b0111;
mem_data_output <= {8'b00000000,regOp2[31:8]};
end
2'b10: begin
mem_select_output <= 4'b0011;
mem_data_output <= {16'b0000000000000000,regOp2[31:16]};
end
2'b11: begin
mem_select_output <= 4'b0001;
mem_data_output <= {24'b000000000000000000000000,regOp2[31:24]};
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
`ALUOP_SWR: begin
mem_addr_output <= {mem_addr[31:2], 2'b00};
mem_write_enabler_output <= 1;
mem_enabler_output <= 1;
case (mem_addr[1:0])
2'b00: begin
mem_select_output <= 4'b1000;
mem_data_output <= {regOp2[7:0],24'b000000000000000000000000};
end
2'b01: begin
mem_select_output <= 4'b1100;
mem_data_output <= {regOp2[15:0],16'b0000000000000000};
end
2'b10: begin
mem_select_output <= 4'b1110;
mem_data_output <= {regOp2[23:0],8'b00000000};
end
2'b11: begin
mem_select_output <= 4'b1111;
mem_data_output <= regOp2[31:0];
end
default: begin
mem_select_output <= 4'b0000;
end
endcase
end
endcase
end
end
endmodule | 1 |
137,838 | data/full_repos/permissive/80510879/mips.v | 80,510,879 | mips.v | v | 322 | 111 | [] | [] | [] | null | line:162: before: "," | null | 1: b"%Error: data/full_repos/permissive/80510879/mips.v:140: Cannot find file containing module: 'pc_module'\n pc_module pc_module0(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/pc_module\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/pc_module.v\n data/full_repos/permissive/80510879,data/full_repos/permissive/80510879/pc_module.sv\n pc_module\n pc_module.v\n pc_module.sv\n obj_dir/pc_module\n obj_dir/pc_module.v\n obj_dir/pc_module.sv\n%Error: data/full_repos/permissive/80510879/mips.v:150: Cannot find file containing module: 'insFetch2insDecode'\n insFetch2insDecode insFecth2insDecode0(\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:157: Cannot find file containing module: 'insDecode'\n insDecode insDecode0(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:177: Cannot find file containing module: 'insDecode2execute'\n insDecode2execute insDecode2execute0(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:194: Cannot find file containing module: 'execute'\n execute execute0(\n ^~~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:234: Cannot find file containing module: 'execute2memory'\n execute2memory execute2memory0(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:255: Cannot find file containing module: 'memory'\n memory memory0(\n ^~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:284: Cannot find file containing module: 'memory2writeback'\n memory2writeback memory2writeback0(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:299: Cannot find file containing module: 'regfile'\n regfile regfile0(\n ^~~~~~~\n%Error: data/full_repos/permissive/80510879/mips.v:307: Cannot find file containing module: 'hilo'\n hilo hilo0(\n ^~~~\n%Error: data/full_repos/permissive/80510879/mips.v:314: Cannot find file containing module: 'control'\n control control0(\n ^~~~~~~\n%Error: Exiting due to 11 error(s)\n" | 300,651 | module | module mips(
input rst,
input clk,
input wire[31:0] ins_input,
output wire[31:0] addr_output,
input wire[31:0] ram_data,
output wire[31:0] ram_addr_output,
output wire ram_write_enabler_output,
output wire[3:0] ram_select_output,
output wire[31:0] ram_data_output,
output wire ram_enabler
);
wire [31:0] pc;
wire [31:0] insDecode_PC;
wire [31:0] insDecode_Inst;
wire [7:0] insDecode_AluopOutput;
wire [2:0] insDecode_AluselOutput;
wire [31:0] insDecode_Reg1;
wire [31:0] insDecode_Reg2;
wire [4:0] insDecode_DestAddr;
wire insDecode_WriteOrNot;
wire reg1Enabler;
wire reg2Enabler;
wire [31:0] reg1Data;
wire [31:0] reg2Data;
wire [4:0] reg1Addr;
wire [4:0] reg2Addr;
wire [7:0] InsDecode_Aluop;
wire [2:0] InsDecode_Alusel;
wire [31:0] InsDecode_Reg1;
wire [31:0] InsDecode_Reg2;
wire [4:0]InsDecode_DestAddr;
wire InsDecode_WriteOrNot;
wire [7:0] InsDecode2execute_aluop;
wire [2:0] InsDecode2execute_alusel;
wire [31:0] InsDecode2execute_Reg1;
wire [31:0] InsDecode2execute_Reg2;
wire InsDecode2execute_WriteOrNot;
wire [4:0] InsDecode2execute_DestAddr;
wire execute_WriteOrNot;
wire [4:0] execute_DestAddr;
wire [31:0] execute_Wdata;
wire execute_HILO_enabler;
wire [31:0]execute_HILO_HI;
wire [31:0]execute_HILO_LO;
wire execute2memory_WriteOrNot;
wire [4:0] execute2memory_DestAddr;
wire [31:0] execute2memory_Wdata;
wire execute2memory_HILO_enabler;
wire [31:0] execute2memory_HILO_HI;
wire [31:0] execute2memory_HILO_LO;
wire memory_WriteOrNot;
wire [4:0] memory_DestAddr;
wire [31:0] memory_Wdata;
wire memory_HILO_enabler;
wire [31:0] memory_HILO_HI;
wire [31:0] memory_HILO_LO;
wire memory2writeback_WriteOrNot;
wire [4:0] memory2writeback_DestAddr;
wire [31:0] memory2writeback_Wdata;
wire memory2writeback_HILO_enabler;
wire [31:0] memory2writeback_HILO_HI;
wire [31:0] memory2writeback_HILO_LO;
wire [31:0] hilo_HI;
wire [31:0] hilo_LO;
wire [31:0] insDecode2pc_branchTargetAddr;
wire insDecode2pc_branchFlag;
wire [31:0] insDecode_retAddr;
wire insDecode_inDelayslot;
wire insDecode_nextDelay;
wire insDecode2execute_executeInDelayslot;
wire [31:0] insDecode2execute_retAddr;
wire insDecode2execute_insDecodeInDelayslot;
wire [31:0] insDecode_ins;
wire [31:0] insDecode2execute_ins;
wire [7:0] execute_aluop;
wire [31:0] execute_mem_addr;
wire [31:0] execute_regOp2;
wire [7:0] execute2memory_aluop;
wire [31:0] execute2memory_mem_addr;
wire [31:0] execute2memory_regOp2;
wire [5:0] control_output;
wire insDecode_pause;
wire execute_pause;
assign addr_output = pc;
pc_module pc_module0(
.clk(clk),
.rst(rst),
.branch_flag(insDecode2pc_branchFlag),
.branch_target(insDecode2pc_branchTargetAddr),
.pc(pc),
.ce(enabler_output),
.control(control_output)
);
insFetch2insDecode insFecth2insDecode0(
.clk(clk),.rst(rst),
.insFetchPC(pc),.insFetchInst(ins_input),
.insDecodePC(insDecode_PC), .insDecodeInst(insDecode_Inst),
.control(control_output)
);
insDecode insDecode0(
.rst(rst),
.insDecode_pc(insDecode_PC), .insDecode_ins(insDecode_Inst),
.reg1_data_input(reg1Data), .reg2_data_input(reg2Data),
.reg1_read_enabler(reg1Enabler), .reg2_read_enabler(reg2Enabler),
.execute_WriteOrNot(execute_WriteOrNot), .execute_DestAddr(execute_DestAddr), .execute_Wdata,
.memory_WriteOrNot(memory_WriteOrNot), .memory_DestAddr(memory_DestAddr), .memory_Wdata(memory_Wdata),
.reg1_addr_output(reg1Addr), .reg2_addr_output(reg2Addr),
.aluop_output(InsDecode_Aluop), .alusel_output(InsDecode_Alusel),
.regOp1(InsDecode_Reg1), .regOp2(InsDecode_Reg2),
.dest_addr(InsDecode_DestAddr), .write_or_not(InsDecode_WriteOrNot),
.in_delayslot(insDecode2execute_insDecodeInDelayslot),
.branch_flag_output(insDecode2pc_branchFlag),
.branch_target_output(insDecode2pc_branchTargetAddr),
.ret_addr(insDecode_retAddr), .next_delay(insDecode_nextDelay),
.in_delayslot_output(insDecode_inDelayslot),
.insDecode_ins_output(insDecode_ins),
.insDecode_pause_output(insDecode_pause)
);
insDecode2execute insDecode2execute0(
.clk(clk), .rst(rst),
.aluop_input(InsDecode_Aluop), .alusel_input(InsDecode_Alusel),
.regOp1(InsDecode_Reg1), .regOp2(InsDecode_Reg2),
.dest_addr(InsDecode_DestAddr), .write_or_not(InsDecode_WriteOrNot),
.aluop_output(InsDecode2execute_aluop), .alusel_output(InsDecode2execute_alusel),
.regOp1_output(InsDecode2execute_Reg1), .regOp2_output(InsDecode2execute_Reg2),
.dest_addr_output(InsDecode2execute_DestAddr), .write_or_not_output(InsDecode2execute_WriteOrNot),
.in_delayslot(insDecode_inDelayslot), .ret_addr(insDecode_retAddr), .next_delay(insDecode_nextDelay),
.execute_in_delayslot(insDecode2execute_executeInDelayslot),
.ret_addr_output(insDecode2execute_retAddr),
.insDecode_in_delayslot(insDecode2execute_insDecodeInDelayslot),
.insDecode_ins(insDecode_ins),
.insDecode2execute_ins(insDecode2execute_ins),
.control(control_output)
);
execute execute0(
.rst(rst),
.aluop_input(InsDecode2execute_aluop),
.alusel_input(InsDecode2execute_alusel),
.regOp1(InsDecode2execute_Reg1),
.regOp2(InsDecode2execute_Reg2),
.dest_addr(InsDecode2execute_DestAddr),
.write_or_not(InsDecode2execute_WriteOrNot),
.memory_HILO_enabler(memory_HILO_enabler),
.memory_HILO_HI(memory_HILO_HI),
.memory_HILO_LO(memory_HILO_LO),
.hilo0_HILO_HI(hilo_HI),
.hilo0_HILO_LO(hilo_LO),
.dest_addr_output(execute_DestAddr),
.write_or_not_output(execute_WriteOrNot),
.wdata_output(execute_Wdata),
.memory2writeback_HILO_enabler(memory2writeback_HILO_enabler),
.memory2writeback_HILO_HI(memory2writeback_HILO_HI),
.memory2writeback_HILO_LO(memory2writeback_HILO_LO),
.ret_addr(insDecode2execute_retAddr),
.in_delayslot(insDecode2execute_executeInDelayslot),
.execute_HILO_enabler(execute_HILO_enabler),
.execute_HILO_HI(execute_HILO_HI),
.execute_HILO_LO(execute_HILO_LO),
.insDecode2execute_ins(insDecode2execute_ins),
.aluop_output(execute_aluop),
.mem_addr_output(execute_mem_addr),
.regOp2_output(execute_regOp2),
.execute_pause_output(execute_pause)
);
execute2memory execute2memory0(
.rst(rst), .clk(clk),
.dest_addr(execute_DestAddr), .write_or_not(execute_WriteOrNot),
.wdata(execute_Wdata),
.execute_HILO_enabler(execute_HILO_enabler),
.execute_HILO_HI(execute_HILO_HI),
.execute_HILO_LO(execute_HILO_LO),
.dest_addr_output(execute2memory_DestAddr), .write_or_not_output(execute2memory_WriteOrNot),
.wdata_output(execute2memory_Wdata),
.execute2memory_HILO_enabler(execute2memory_HILO_enabler),
.execute2memory_HILO_HI(execute2memory_HILO_HI),
.execute2memory_HILO_LO(execute2memory_HILO_LO),
.aluop(execute_aluop),
.mem_addr(execute_mem_addr),
.regOp2(execute_regOp2),
.aluop_output(execute2memory_aluop),
.mem_addr_output(execute2memory_mem_addr),
.regOp2_output(execute2memory_regOp2),
.control(control_output)
);
memory memory0(
.rst(rst),
.dest_addr(execute2memory_DestAddr),
.write_or_not(execute2memory_WriteOrNot),
.wdata(execute2memory_Wdata),
.execute2memory_HILO_enabler(execute2memory_HILO_enabler),
.execute2memory_HILO_HI(execute2memory_HILO_HI),
.execute2memory_HILO_LO(execute2memory_HILO_LO),
.dest_addr_output(memory_DestAddr),
.write_or_not_output(memory_WriteOrNot),
.wdata_output(memory_Wdata),
.memory_HILO_enabler(memory_HILO_enabler),
.memory_HILO_HI(memory_HILO_HI),
.memory_HILO_LO(memory_HILO_LO),
.aluop(execute2memory_aluop),
.mem_addr(execute2memory_mem_addr),
.regOp2(execute2memory_regOp2),
.mem_data(ram_data),
.mem_data_output(ram_data_output),
.mem_addr_output(ram_addr_output),
.mem_write_enabler_output(ram_write_enabler_output),
.mem_select_output(ram_select_output),
.mem_enabler_output(ram_enabler)
);
memory2writeback memory2writeback0(
.clk(clk), .rst(rst),
.dest_addr(memory_DestAddr), .write_or_not(memory_WriteOrNot),
.wdata(memory_Wdata),
.memory_HILO_enabler(memory_HILO_enabler),
.memory_HILO_HI(memory_HILO_HI),
.memory_HILO_LO(memory_HILO_LO),
.dest_addr_output(memory2writeback_DestAddr), .write_or_not_output(memory2writeback_WriteOrNot),
.wdata_output(memory2writeback_Wdata),
.memory2writeback_HILO_enabler(memory2writeback_HILO_enabler),
.memory2writeback_HILO_HI(memory2writeback_HILO_HI),
.memory2writeback_HILO_LO(memory2writeback_HILO_LO),
.control(control_output)
);
regfile regfile0(
.clk(clk), .rst(rst),
.we(memory2writeback_WriteOrNot), .waddr(memory2writeback_DestAddr), .wdata(memory2writeback_Wdata),
.re1(reg1Enabler), .re2(reg2Enabler),
.raddr1(reg1Addr), .raddr2(reg2Addr),
.rdata1(reg1Data), .rdata2(reg2Data)
);
hilo hilo0(
.clk(clk), .rst(rst),
.enabler(memory2writeback_HILO_enabler),
.memory2writeback_HI(memory2writeback_HILO_HI), .memory2writeback_LO(memory2writeback_HILO_LO),
.hilo_hi(hilo_HI), .hilo_lo(hilo_LO)
);
control control0(
.rst(rst),
.insDecode_pause(insDecode_pause),
.execute_pause(execute_pause),
.control_output(control_output)
);
endmodule | module mips(
input rst,
input clk,
input wire[31:0] ins_input,
output wire[31:0] addr_output,
input wire[31:0] ram_data,
output wire[31:0] ram_addr_output,
output wire ram_write_enabler_output,
output wire[3:0] ram_select_output,
output wire[31:0] ram_data_output,
output wire ram_enabler
); |
wire [31:0] pc;
wire [31:0] insDecode_PC;
wire [31:0] insDecode_Inst;
wire [7:0] insDecode_AluopOutput;
wire [2:0] insDecode_AluselOutput;
wire [31:0] insDecode_Reg1;
wire [31:0] insDecode_Reg2;
wire [4:0] insDecode_DestAddr;
wire insDecode_WriteOrNot;
wire reg1Enabler;
wire reg2Enabler;
wire [31:0] reg1Data;
wire [31:0] reg2Data;
wire [4:0] reg1Addr;
wire [4:0] reg2Addr;
wire [7:0] InsDecode_Aluop;
wire [2:0] InsDecode_Alusel;
wire [31:0] InsDecode_Reg1;
wire [31:0] InsDecode_Reg2;
wire [4:0]InsDecode_DestAddr;
wire InsDecode_WriteOrNot;
wire [7:0] InsDecode2execute_aluop;
wire [2:0] InsDecode2execute_alusel;
wire [31:0] InsDecode2execute_Reg1;
wire [31:0] InsDecode2execute_Reg2;
wire InsDecode2execute_WriteOrNot;
wire [4:0] InsDecode2execute_DestAddr;
wire execute_WriteOrNot;
wire [4:0] execute_DestAddr;
wire [31:0] execute_Wdata;
wire execute_HILO_enabler;
wire [31:0]execute_HILO_HI;
wire [31:0]execute_HILO_LO;
wire execute2memory_WriteOrNot;
wire [4:0] execute2memory_DestAddr;
wire [31:0] execute2memory_Wdata;
wire execute2memory_HILO_enabler;
wire [31:0] execute2memory_HILO_HI;
wire [31:0] execute2memory_HILO_LO;
wire memory_WriteOrNot;
wire [4:0] memory_DestAddr;
wire [31:0] memory_Wdata;
wire memory_HILO_enabler;
wire [31:0] memory_HILO_HI;
wire [31:0] memory_HILO_LO;
wire memory2writeback_WriteOrNot;
wire [4:0] memory2writeback_DestAddr;
wire [31:0] memory2writeback_Wdata;
wire memory2writeback_HILO_enabler;
wire [31:0] memory2writeback_HILO_HI;
wire [31:0] memory2writeback_HILO_LO;
wire [31:0] hilo_HI;
wire [31:0] hilo_LO;
wire [31:0] insDecode2pc_branchTargetAddr;
wire insDecode2pc_branchFlag;
wire [31:0] insDecode_retAddr;
wire insDecode_inDelayslot;
wire insDecode_nextDelay;
wire insDecode2execute_executeInDelayslot;
wire [31:0] insDecode2execute_retAddr;
wire insDecode2execute_insDecodeInDelayslot;
wire [31:0] insDecode_ins;
wire [31:0] insDecode2execute_ins;
wire [7:0] execute_aluop;
wire [31:0] execute_mem_addr;
wire [31:0] execute_regOp2;
wire [7:0] execute2memory_aluop;
wire [31:0] execute2memory_mem_addr;
wire [31:0] execute2memory_regOp2;
wire [5:0] control_output;
wire insDecode_pause;
wire execute_pause;
assign addr_output = pc;
pc_module pc_module0(
.clk(clk),
.rst(rst),
.branch_flag(insDecode2pc_branchFlag),
.branch_target(insDecode2pc_branchTargetAddr),
.pc(pc),
.ce(enabler_output),
.control(control_output)
);
insFetch2insDecode insFecth2insDecode0(
.clk(clk),.rst(rst),
.insFetchPC(pc),.insFetchInst(ins_input),
.insDecodePC(insDecode_PC), .insDecodeInst(insDecode_Inst),
.control(control_output)
);
insDecode insDecode0(
.rst(rst),
.insDecode_pc(insDecode_PC), .insDecode_ins(insDecode_Inst),
.reg1_data_input(reg1Data), .reg2_data_input(reg2Data),
.reg1_read_enabler(reg1Enabler), .reg2_read_enabler(reg2Enabler),
.execute_WriteOrNot(execute_WriteOrNot), .execute_DestAddr(execute_DestAddr), .execute_Wdata,
.memory_WriteOrNot(memory_WriteOrNot), .memory_DestAddr(memory_DestAddr), .memory_Wdata(memory_Wdata),
.reg1_addr_output(reg1Addr), .reg2_addr_output(reg2Addr),
.aluop_output(InsDecode_Aluop), .alusel_output(InsDecode_Alusel),
.regOp1(InsDecode_Reg1), .regOp2(InsDecode_Reg2),
.dest_addr(InsDecode_DestAddr), .write_or_not(InsDecode_WriteOrNot),
.in_delayslot(insDecode2execute_insDecodeInDelayslot),
.branch_flag_output(insDecode2pc_branchFlag),
.branch_target_output(insDecode2pc_branchTargetAddr),
.ret_addr(insDecode_retAddr), .next_delay(insDecode_nextDelay),
.in_delayslot_output(insDecode_inDelayslot),
.insDecode_ins_output(insDecode_ins),
.insDecode_pause_output(insDecode_pause)
);
insDecode2execute insDecode2execute0(
.clk(clk), .rst(rst),
.aluop_input(InsDecode_Aluop), .alusel_input(InsDecode_Alusel),
.regOp1(InsDecode_Reg1), .regOp2(InsDecode_Reg2),
.dest_addr(InsDecode_DestAddr), .write_or_not(InsDecode_WriteOrNot),
.aluop_output(InsDecode2execute_aluop), .alusel_output(InsDecode2execute_alusel),
.regOp1_output(InsDecode2execute_Reg1), .regOp2_output(InsDecode2execute_Reg2),
.dest_addr_output(InsDecode2execute_DestAddr), .write_or_not_output(InsDecode2execute_WriteOrNot),
.in_delayslot(insDecode_inDelayslot), .ret_addr(insDecode_retAddr), .next_delay(insDecode_nextDelay),
.execute_in_delayslot(insDecode2execute_executeInDelayslot),
.ret_addr_output(insDecode2execute_retAddr),
.insDecode_in_delayslot(insDecode2execute_insDecodeInDelayslot),
.insDecode_ins(insDecode_ins),
.insDecode2execute_ins(insDecode2execute_ins),
.control(control_output)
);
execute execute0(
.rst(rst),
.aluop_input(InsDecode2execute_aluop),
.alusel_input(InsDecode2execute_alusel),
.regOp1(InsDecode2execute_Reg1),
.regOp2(InsDecode2execute_Reg2),
.dest_addr(InsDecode2execute_DestAddr),
.write_or_not(InsDecode2execute_WriteOrNot),
.memory_HILO_enabler(memory_HILO_enabler),
.memory_HILO_HI(memory_HILO_HI),
.memory_HILO_LO(memory_HILO_LO),
.hilo0_HILO_HI(hilo_HI),
.hilo0_HILO_LO(hilo_LO),
.dest_addr_output(execute_DestAddr),
.write_or_not_output(execute_WriteOrNot),
.wdata_output(execute_Wdata),
.memory2writeback_HILO_enabler(memory2writeback_HILO_enabler),
.memory2writeback_HILO_HI(memory2writeback_HILO_HI),
.memory2writeback_HILO_LO(memory2writeback_HILO_LO),
.ret_addr(insDecode2execute_retAddr),
.in_delayslot(insDecode2execute_executeInDelayslot),
.execute_HILO_enabler(execute_HILO_enabler),
.execute_HILO_HI(execute_HILO_HI),
.execute_HILO_LO(execute_HILO_LO),
.insDecode2execute_ins(insDecode2execute_ins),
.aluop_output(execute_aluop),
.mem_addr_output(execute_mem_addr),
.regOp2_output(execute_regOp2),
.execute_pause_output(execute_pause)
);
execute2memory execute2memory0(
.rst(rst), .clk(clk),
.dest_addr(execute_DestAddr), .write_or_not(execute_WriteOrNot),
.wdata(execute_Wdata),
.execute_HILO_enabler(execute_HILO_enabler),
.execute_HILO_HI(execute_HILO_HI),
.execute_HILO_LO(execute_HILO_LO),
.dest_addr_output(execute2memory_DestAddr), .write_or_not_output(execute2memory_WriteOrNot),
.wdata_output(execute2memory_Wdata),
.execute2memory_HILO_enabler(execute2memory_HILO_enabler),
.execute2memory_HILO_HI(execute2memory_HILO_HI),
.execute2memory_HILO_LO(execute2memory_HILO_LO),
.aluop(execute_aluop),
.mem_addr(execute_mem_addr),
.regOp2(execute_regOp2),
.aluop_output(execute2memory_aluop),
.mem_addr_output(execute2memory_mem_addr),
.regOp2_output(execute2memory_regOp2),
.control(control_output)
);
memory memory0(
.rst(rst),
.dest_addr(execute2memory_DestAddr),
.write_or_not(execute2memory_WriteOrNot),
.wdata(execute2memory_Wdata),
.execute2memory_HILO_enabler(execute2memory_HILO_enabler),
.execute2memory_HILO_HI(execute2memory_HILO_HI),
.execute2memory_HILO_LO(execute2memory_HILO_LO),
.dest_addr_output(memory_DestAddr),
.write_or_not_output(memory_WriteOrNot),
.wdata_output(memory_Wdata),
.memory_HILO_enabler(memory_HILO_enabler),
.memory_HILO_HI(memory_HILO_HI),
.memory_HILO_LO(memory_HILO_LO),
.aluop(execute2memory_aluop),
.mem_addr(execute2memory_mem_addr),
.regOp2(execute2memory_regOp2),
.mem_data(ram_data),
.mem_data_output(ram_data_output),
.mem_addr_output(ram_addr_output),
.mem_write_enabler_output(ram_write_enabler_output),
.mem_select_output(ram_select_output),
.mem_enabler_output(ram_enabler)
);
memory2writeback memory2writeback0(
.clk(clk), .rst(rst),
.dest_addr(memory_DestAddr), .write_or_not(memory_WriteOrNot),
.wdata(memory_Wdata),
.memory_HILO_enabler(memory_HILO_enabler),
.memory_HILO_HI(memory_HILO_HI),
.memory_HILO_LO(memory_HILO_LO),
.dest_addr_output(memory2writeback_DestAddr), .write_or_not_output(memory2writeback_WriteOrNot),
.wdata_output(memory2writeback_Wdata),
.memory2writeback_HILO_enabler(memory2writeback_HILO_enabler),
.memory2writeback_HILO_HI(memory2writeback_HILO_HI),
.memory2writeback_HILO_LO(memory2writeback_HILO_LO),
.control(control_output)
);
regfile regfile0(
.clk(clk), .rst(rst),
.we(memory2writeback_WriteOrNot), .waddr(memory2writeback_DestAddr), .wdata(memory2writeback_Wdata),
.re1(reg1Enabler), .re2(reg2Enabler),
.raddr1(reg1Addr), .raddr2(reg2Addr),
.rdata1(reg1Data), .rdata2(reg2Data)
);
hilo hilo0(
.clk(clk), .rst(rst),
.enabler(memory2writeback_HILO_enabler),
.memory2writeback_HI(memory2writeback_HILO_HI), .memory2writeback_LO(memory2writeback_HILO_LO),
.hilo_hi(hilo_HI), .hilo_lo(hilo_LO)
);
control control0(
.rst(rst),
.insDecode_pause(insDecode_pause),
.execute_pause(execute_pause),
.control_output(control_output)
);
endmodule | 1 |
137,840 | data/full_repos/permissive/80510879/ram.v | 80,510,879 | ram.v | v | 98 | 135 | [] | [] | [] | [(21, 97)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:48: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n byte_mem3[addr[18:2]] <= data_input[31:24];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:51: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n byte_mem2[addr[18:2]] <= data_input[23:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:54: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n byte_mem1[addr[18:2]] <= data_input[15:8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:57: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n byte_mem0[addr[18:2]] <= data_input[7:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:87: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n data_output <= {byte_mem3[addr[18:2]], byte_mem2[addr[18:2]], byte_mem1[addr[18:2]], byte_mem0[addr[18:2]]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:87: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n data_output <= {byte_mem3[addr[18:2]], byte_mem2[addr[18:2]], byte_mem1[addr[18:2]], byte_mem0[addr[18:2]]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:87: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n data_output <= {byte_mem3[addr[18:2]], byte_mem2[addr[18:2]], byte_mem1[addr[18:2]], byte_mem0[addr[18:2]]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:87: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n data_output <= {byte_mem3[addr[18:2]], byte_mem2[addr[18:2]], byte_mem1[addr[18:2]], byte_mem0[addr[18:2]]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:94: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n vga_rdata <= {byte_mem3[vga_raddr[18:2]], byte_mem2[vga_raddr[18:2]], byte_mem1[vga_raddr[18:2]], byte_mem0[vga_raddr[18:2]]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:94: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n vga_rdata <= {byte_mem3[vga_raddr[18:2]], byte_mem2[vga_raddr[18:2]], byte_mem1[vga_raddr[18:2]], byte_mem0[vga_raddr[18:2]]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:94: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n vga_rdata <= {byte_mem3[vga_raddr[18:2]], byte_mem2[vga_raddr[18:2]], byte_mem1[vga_raddr[18:2]], byte_mem0[vga_raddr[18:2]]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/80510879/ram.v:94: Bit extraction of array[1023:0] requires 10 bit index, not 17 bits.\n : ... In instance ram\n vga_rdata <= {byte_mem3[vga_raddr[18:2]], byte_mem2[vga_raddr[18:2]], byte_mem1[vga_raddr[18:2]], byte_mem0[vga_raddr[18:2]]};\n ^\n%Error: Exiting due to 12 warning(s)\n' | 300,653 | module | module ram(
input clk,
input enabler,
input write_enabler,
input wire[31:0] addr,
input wire[3:0] select,
input wire[31:0] data_input,
output reg[31:0] data_output,
input wire[31:0] vga_raddr,
output reg[31:0] vga_rdata,
input wire[31:0] btn_data
);
reg[7:0] byte_mem0[0:1023];
reg[7:0] byte_mem1[0:1023];
reg[7:0] byte_mem2[0:1023];
reg[7:0] byte_mem3[0:1023];
reg[31:0] button_mem;
always @ (posedge clk) begin
if (enabler == 1 && write_enabler == 1) begin
if (select[3] == 1) begin
byte_mem3[addr[18:2]] <= data_input[31:24];
end
if (select[2] == 1) begin
byte_mem2[addr[18:2]] <= data_input[23:16];
end
if (select[1] == 1) begin
byte_mem1[addr[18:2]] <= data_input[15:8];
end
if (select[0] == 1) begin
byte_mem0[addr[18:2]] <= data_input[7:0];
end
end
button_mem <= btn_data;
end
always @ (*) begin
if (enabler == 0) begin
data_output <= 0;
end else if (addr[18:2] == 1024) begin
data_output <= button_mem;
end else if (write_enabler == 0) begin
data_output <= {byte_mem3[addr[18:2]], byte_mem2[addr[18:2]], byte_mem1[addr[18:2]], byte_mem0[addr[18:2]]};
end else begin
data_output <= 0;
end
end
always @ (*) begin
vga_rdata <= {byte_mem3[vga_raddr[18:2]], byte_mem2[vga_raddr[18:2]], byte_mem1[vga_raddr[18:2]], byte_mem0[vga_raddr[18:2]]};
end
endmodule | module ram(
input clk,
input enabler,
input write_enabler,
input wire[31:0] addr,
input wire[3:0] select,
input wire[31:0] data_input,
output reg[31:0] data_output,
input wire[31:0] vga_raddr,
output reg[31:0] vga_rdata,
input wire[31:0] btn_data
); |
reg[7:0] byte_mem0[0:1023];
reg[7:0] byte_mem1[0:1023];
reg[7:0] byte_mem2[0:1023];
reg[7:0] byte_mem3[0:1023];
reg[31:0] button_mem;
always @ (posedge clk) begin
if (enabler == 1 && write_enabler == 1) begin
if (select[3] == 1) begin
byte_mem3[addr[18:2]] <= data_input[31:24];
end
if (select[2] == 1) begin
byte_mem2[addr[18:2]] <= data_input[23:16];
end
if (select[1] == 1) begin
byte_mem1[addr[18:2]] <= data_input[15:8];
end
if (select[0] == 1) begin
byte_mem0[addr[18:2]] <= data_input[7:0];
end
end
button_mem <= btn_data;
end
always @ (*) begin
if (enabler == 0) begin
data_output <= 0;
end else if (addr[18:2] == 1024) begin
data_output <= button_mem;
end else if (write_enabler == 0) begin
data_output <= {byte_mem3[addr[18:2]], byte_mem2[addr[18:2]], byte_mem1[addr[18:2]], byte_mem0[addr[18:2]]};
end else begin
data_output <= 0;
end
end
always @ (*) begin
vga_rdata <= {byte_mem3[vga_raddr[18:2]], byte_mem2[vga_raddr[18:2]], byte_mem1[vga_raddr[18:2]], byte_mem0[vga_raddr[18:2]]};
end
endmodule | 1 |
137,842 | data/full_repos/permissive/80510879/segdisplay.v | 80,510,879 | segdisplay.v | v | 153 | 83 | [] | [] | [] | [(22, 49), (51, 126), (128, 152)] | null | null | 1: b"%Error: data/full_repos/permissive/80510879/segdisplay.v:145: syntax error, unexpected '(', expecting IDENTIFIER\n .segclk(segclk),\n ^\n%Error: Exiting due to 1 error(s)\n" | 300,655 | module | module segClk(
input wire clk,
input wire clr,
output wire segclk
);
reg [16:0] q;
always @(posedge clk or posedge clr)
begin
if (clr == 1)
q <= 0;
else
q <= q + 1;
end
assign segclk = q[16];
endmodule | module segClk(
input wire clk,
input wire clr,
output wire segclk
); |
reg [16:0] q;
always @(posedge clk or posedge clr)
begin
if (clr == 1)
q <= 0;
else
q <= q + 1;
end
assign segclk = q[16];
endmodule | 1 |
137,843 | data/full_repos/permissive/80510879/segdisplay.v | 80,510,879 | segdisplay.v | v | 153 | 83 | [] | [] | [] | [(22, 49), (51, 126), (128, 152)] | null | null | 1: b"%Error: data/full_repos/permissive/80510879/segdisplay.v:145: syntax error, unexpected '(', expecting IDENTIFIER\n .segclk(segclk),\n ^\n%Error: Exiting due to 1 error(s)\n" | 300,655 | module | module segdisplay(
input wire segclk,
input wire clr,
output reg [6:0] seg,
output reg [3:0] an,
output dp
);
parameter empty = 7'b1111111;
parameter L = 7'b1000111;
parameter Y = 7'b0010001;
parameter one = 7'b1111001;
parameter three = 7'b0110000;
parameter five = 7'b0010010;
parameter two = 7'b0100100;
parameter four = 7'b0011001;
parameter left = 2'b00;
parameter midleft = 2'b01;
parameter midright = 2'b10;
parameter right = 2'b11;
reg [1:0] state;
assign dp = 1;
integer i;
always @(posedge segclk or posedge clr)
begin
if (clr == 1)
begin
seg <= 7'b1111111;
an <= 7'b1111;
state <= left;
end
else
begin
i <= 4;
case(state)
left:
begin
seg <= empty;
an <= 4'b0111;
state <= midleft;
end
midleft:
begin
seg <= empty;
an <= 4'b1011;
state <= midright;
end
midright:
begin
seg <= L;
an <= 4'b1101;
state <= right;
end
right:
begin
seg <= Y;
an <= 4'b1110;
state <= left;
end
endcase
end
end
endmodule | module segdisplay(
input wire segclk,
input wire clr,
output reg [6:0] seg,
output reg [3:0] an,
output dp
); |
parameter empty = 7'b1111111;
parameter L = 7'b1000111;
parameter Y = 7'b0010001;
parameter one = 7'b1111001;
parameter three = 7'b0110000;
parameter five = 7'b0010010;
parameter two = 7'b0100100;
parameter four = 7'b0011001;
parameter left = 2'b00;
parameter midleft = 2'b01;
parameter midright = 2'b10;
parameter right = 2'b11;
reg [1:0] state;
assign dp = 1;
integer i;
always @(posedge segclk or posedge clr)
begin
if (clr == 1)
begin
seg <= 7'b1111111;
an <= 7'b1111;
state <= left;
end
else
begin
i <= 4;
case(state)
left:
begin
seg <= empty;
an <= 4'b0111;
state <= midleft;
end
midleft:
begin
seg <= empty;
an <= 4'b1011;
state <= midright;
end
midright:
begin
seg <= L;
an <= 4'b1101;
state <= right;
end
right:
begin
seg <= Y;
an <= 4'b1110;
state <= left;
end
endcase
end
end
endmodule | 1 |
137,844 | data/full_repos/permissive/80510879/segdisplay.v | 80,510,879 | segdisplay.v | v | 153 | 83 | [] | [] | [] | [(22, 49), (51, 126), (128, 152)] | null | null | 1: b"%Error: data/full_repos/permissive/80510879/segdisplay.v:145: syntax error, unexpected '(', expecting IDENTIFIER\n .segclk(segclk),\n ^\n%Error: Exiting due to 1 error(s)\n" | 300,655 | module | module segtop(
input clk50,
input rst,
output [6:0] seg,
output [3:0] an,
output dp
);
wire segclk;
segClk segClk0(
.clk(clk50),
.clr(rst),
.segclk(segclk)
);
segdisplay(
.segclk(segclk),
.clr(rst),
.seg(seg),
.an(an),
.dp(dp)
);
endmodule | module segtop(
input clk50,
input rst,
output [6:0] seg,
output [3:0] an,
output dp
); |
wire segclk;
segClk segClk0(
.clk(clk50),
.clr(rst),
.segclk(segclk)
);
segdisplay(
.segclk(segclk),
.clr(rst),
.seg(seg),
.an(an),
.dp(dp)
);
endmodule | 1 |
137,845 | data/full_repos/permissive/80510879/vga.v | 80,510,879 | vga.v | v | 102 | 165 | [] | [] | [] | [(3, 30), (32, 71), (73, 101)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80510879/vga.v:86: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'posY\' generates 11 bits.\n : ... In instance vga\n assign raddr = posX > 800 ? 32\'h400 : posY > 600 ? 32\'h400 : 32\'h400 + (posY/20) * 40 + (posX/20);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80510879/vga.v:86: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'posX\' generates 11 bits.\n : ... In instance vga\n assign raddr = posX > 800 ? 32\'h400 : posY > 600 ? 32\'h400 : 32\'h400 + (posY/20) * 40 + (posX/20);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,656 | module | module vsync(line_clk, vsync_out, posY);
input line_clk;
output vsync_out;
output wire[10:0] posY;
reg [10:0] count = 0;
reg vsync = 0;
always @(posedge line_clk)
if (count < 666)
count <= count + 1;
else
count <= 0;
always @(posedge line_clk)
begin
if (count < 637)
vsync <= 1;
else if (count >= 637 && count < 643)
vsync <= 0;
else if (count >= 643)
vsync <= 1;
end
assign vsync_out = vsync;
assign posY = count;
endmodule | module vsync(line_clk, vsync_out, posY); |
input line_clk;
output vsync_out;
output wire[10:0] posY;
reg [10:0] count = 0;
reg vsync = 0;
always @(posedge line_clk)
if (count < 666)
count <= count + 1;
else
count <= 0;
always @(posedge line_clk)
begin
if (count < 637)
vsync <= 1;
else if (count >= 637 && count < 643)
vsync <= 0;
else if (count >= 643)
vsync <= 1;
end
assign vsync_out = vsync;
assign posY = count;
endmodule | 1 |
137,846 | data/full_repos/permissive/80510879/vga.v | 80,510,879 | vga.v | v | 102 | 165 | [] | [] | [] | [(3, 30), (32, 71), (73, 101)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80510879/vga.v:86: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'posY\' generates 11 bits.\n : ... In instance vga\n assign raddr = posX > 800 ? 32\'h400 : posY > 600 ? 32\'h400 : 32\'h400 + (posY/20) * 40 + (posX/20);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80510879/vga.v:86: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'posX\' generates 11 bits.\n : ... In instance vga\n assign raddr = posX > 800 ? 32\'h400 : posY > 600 ? 32\'h400 : 32\'h400 + (posY/20) * 40 + (posX/20);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,656 | module | module hsync(clk50, hsync_out, newline_out, posX);
input clk50;
output hsync_out, newline_out;
output wire[10:0] posX;
reg [10:0] count = 0;
reg hsync = 0;
reg newline = 0;
always @(posedge clk50)
begin
if (count < 1040)
count <= count + 1;
else
count <= 0;
end
always @(posedge clk50)
begin
if (count == 0)
newline <= 1;
else
newline <= 0;
end
always @(posedge clk50)
begin
if (count < 856)
hsync <= 1;
else if (count >= 856 && count < 976)
hsync <= 0;
else if (count >= 976)
hsync <= 1;
end
assign hsync_out = hsync;
assign newline_out = newline;
assign posX = count;
endmodule | module hsync(clk50, hsync_out, newline_out, posX); |
input clk50;
output hsync_out, newline_out;
output wire[10:0] posX;
reg [10:0] count = 0;
reg hsync = 0;
reg newline = 0;
always @(posedge clk50)
begin
if (count < 1040)
count <= count + 1;
else
count <= 0;
end
always @(posedge clk50)
begin
if (count == 0)
newline <= 1;
else
newline <= 0;
end
always @(posedge clk50)
begin
if (count < 856)
hsync <= 1;
else if (count >= 856 && count < 976)
hsync <= 0;
else if (count >= 976)
hsync <= 1;
end
assign hsync_out = hsync;
assign newline_out = newline;
assign posX = count;
endmodule | 1 |
137,847 | data/full_repos/permissive/80510879/vga.v | 80,510,879 | vga.v | v | 102 | 165 | [] | [] | [] | [(3, 30), (32, 71), (73, 101)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/80510879/vga.v:86: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'posY\' generates 11 bits.\n : ... In instance vga\n assign raddr = posX > 800 ? 32\'h400 : posY > 600 ? 32\'h400 : 32\'h400 + (posY/20) * 40 + (posX/20);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/80510879/vga.v:86: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'posX\' generates 11 bits.\n : ... In instance vga\n assign raddr = posX > 800 ? 32\'h400 : posY > 600 ? 32\'h400 : 32\'h400 + (posY/20) * 40 + (posX/20);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 300,656 | module | module vga(clk50, Hsync, Vsync, red_out, blue_out, green_out, raddr, rdata);
input clk50;
input wire[31:0] rdata;
output Hsync, Vsync;
output wire[2:0] red_out, green_out;
output wire[1:0] blue_out;
output wire[31:0] raddr;
wire line_clk;
wire clk50;
wire [10:0] posY;
wire [10:0] posX;
assign raddr = posX > 800 ? 32'h400 : posY > 600 ? 32'h400 : 32'h400 + (posY/20) * 40 + (posX/20);
assign {red_out, green_out, blue_out} = raddr[1:0] == 2'b11 ? rdata[7:0] : raddr[1:0] == 2'b10 ? rdata[15:8] : raddr[1:0] == 2'b01 ? rdata[23:16] : rdata[31:24];
hsync hs(
.clk50(clk50),
.hsync_out(Hsync),
.newline_out(line_clk),
.posX(posX)
);
vsync vs(
.line_clk(line_clk),
.vsync_out(Vsync),
.posY(posY)
);
endmodule | module vga(clk50, Hsync, Vsync, red_out, blue_out, green_out, raddr, rdata); |
input clk50;
input wire[31:0] rdata;
output Hsync, Vsync;
output wire[2:0] red_out, green_out;
output wire[1:0] blue_out;
output wire[31:0] raddr;
wire line_clk;
wire clk50;
wire [10:0] posY;
wire [10:0] posX;
assign raddr = posX > 800 ? 32'h400 : posY > 600 ? 32'h400 : 32'h400 + (posY/20) * 40 + (posX/20);
assign {red_out, green_out, blue_out} = raddr[1:0] == 2'b11 ? rdata[7:0] : raddr[1:0] == 2'b10 ? rdata[15:8] : raddr[1:0] == 2'b01 ? rdata[23:16] : rdata[31:24];
hsync hs(
.clk50(clk50),
.hsync_out(Hsync),
.newline_out(line_clk),
.posX(posX)
);
vsync vs(
.line_clk(line_clk),
.vsync_out(Vsync),
.posY(posY)
);
endmodule | 1 |
137,849 | data/full_repos/permissive/80582133/Snake.v | 80,582,133 | Snake.v | v | 595 | 130 | [] | [] | [] | [(5, 36), (39, 51), (54, 65), (68, 394), (396, 414), (417, 435), (438, 594)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:84: Signal definition not found, creating implicitly: \'slowCLK\'\ncomplexDivider CLK1(CLK, slowCLK); \n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:85: Signal definition not found, creating implicitly: \'frame\'\ncomplexDivider2 frame1(CLK, frame); \n ^~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:471: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nif ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:485: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nelse if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 300,663 | module | module SinglePulser(button, pulsebutton, clk);
input clk, button;
reg state;
output reg pulsebutton;
initial
begin
state<=0;
end
always @(posedge clk)
begin
if (button==1 && state==0)
begin
state<=1;
pulsebutton<=1;
end
else if (button==1 && state==1)
begin
state<=1;
pulsebutton<=0;
end
else
begin
state<=0;
pulsebutton<=0;
end
end
endmodule | module SinglePulser(button, pulsebutton, clk); |
input clk, button;
reg state;
output reg pulsebutton;
initial
begin
state<=0;
end
always @(posedge clk)
begin
if (button==1 && state==0)
begin
state<=1;
pulsebutton<=1;
end
else if (button==1 && state==1)
begin
state<=1;
pulsebutton<=0;
end
else
begin
state<=0;
pulsebutton<=0;
end
end
endmodule | 0 |
137,850 | data/full_repos/permissive/80582133/Snake.v | 80,582,133 | Snake.v | v | 595 | 130 | [] | [] | [] | [(5, 36), (39, 51), (54, 65), (68, 394), (396, 414), (417, 435), (438, 594)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:84: Signal definition not found, creating implicitly: \'slowCLK\'\ncomplexDivider CLK1(CLK, slowCLK); \n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:85: Signal definition not found, creating implicitly: \'frame\'\ncomplexDivider2 frame1(CLK, frame); \n ^~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:471: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nif ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:485: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nelse if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 300,663 | module | module Top (CLK, SW6, R1, G1, B1, Hs, Vs, PS2Clk, si);
input CLK, SW6, PS2Clk, si;
output Hs, Vs;
output [3:0] R1, B1, G1;
wire [4:0] counter;
wire [21:0] Q;
shift S2(PS2Clk, si, Q, counter);
Master M(CLK, SW6, R1, G1, B1, Hs, Vs, PS2Clk, counter, Q);
endmodule | module Top (CLK, SW6, R1, G1, B1, Hs, Vs, PS2Clk, si); |
input CLK, SW6, PS2Clk, si;
output Hs, Vs;
output [3:0] R1, B1, G1;
wire [4:0] counter;
wire [21:0] Q;
shift S2(PS2Clk, si, Q, counter);
Master M(CLK, SW6, R1, G1, B1, Hs, Vs, PS2Clk, counter, Q);
endmodule | 0 |
137,851 | data/full_repos/permissive/80582133/Snake.v | 80,582,133 | Snake.v | v | 595 | 130 | [] | [] | [] | [(5, 36), (39, 51), (54, 65), (68, 394), (396, 414), (417, 435), (438, 594)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:84: Signal definition not found, creating implicitly: \'slowCLK\'\ncomplexDivider CLK1(CLK, slowCLK); \n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:85: Signal definition not found, creating implicitly: \'frame\'\ncomplexDivider2 frame1(CLK, frame); \n ^~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:471: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nif ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:485: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nelse if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 300,663 | module | module shift (PS2Clk, si, Q, counter);
input PS2Clk,si;
output reg [21:0] Q;
output reg [4:0] counter;
always@(negedge PS2Clk)
begin
Q[21]<=si;
Q[20:0]<=Q[21:1];
if(counter==11) counter=1;
else counter=counter+1;
end
endmodule | module shift (PS2Clk, si, Q, counter); |
input PS2Clk,si;
output reg [21:0] Q;
output reg [4:0] counter;
always@(negedge PS2Clk)
begin
Q[21]<=si;
Q[20:0]<=Q[21:1];
if(counter==11) counter=1;
else counter=counter+1;
end
endmodule | 0 |
137,852 | data/full_repos/permissive/80582133/Snake.v | 80,582,133 | Snake.v | v | 595 | 130 | [] | [] | [] | [(5, 36), (39, 51), (54, 65), (68, 394), (396, 414), (417, 435), (438, 594)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:84: Signal definition not found, creating implicitly: \'slowCLK\'\ncomplexDivider CLK1(CLK, slowCLK); \n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:85: Signal definition not found, creating implicitly: \'frame\'\ncomplexDivider2 frame1(CLK, frame); \n ^~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:471: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nif ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:485: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nelse if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 300,663 | module | module Master (CLK, SW6, R1, G1, B1, Hs, Vs, PS2Clk, counter, Q);
input CLK, SW6, PS2Clk;
reg singlepulser, singlepulserD, singlepulserU, singlepulserL,singlepulserR, singlepulserESC, ap1, ap2, ap3;
wire singlepulser2, singlepulserD2, singlepulserU2, singlepulserL2, singlepulserR2;
wire singlepulser2F, singlepulserDF, singlepulserUF, singlepulserLF, singlepulserRF, singlepulserESC2;
reg [12:0] X1, Y1, X2, Y2;
reg escFlag;
input [21:0] Q;
input [4:0] counter;
output Hs, Vs;
output [3:0] R1, B1, G1;
reg [8:0] length;
reg leftFlag, rightFlag, upFlag, downFlag, moveFlag, VFlag, HFlag, startFlag, deathFlag;
complexDivider CLK1(CLK, slowCLK);
complexDivider2 frame1(CLK, frame);
MonitorB M(slowCLK, X1, X2, Y1, Y2, Hs, Vs, R1, G1, B1, SW6, startFlag, deathFlag, ap1, ap2, ap3, escFlag);
SinglePulser S1(singlepulser, singlepulser2, CLK);
SinglePulser S2(singlepulserD, singlepulserD2, CLK);
SinglePulser S3(singlepulserU, singlepulserU2, CLK);
SinglePulser S4(singlepulserL, singlepulserL2, CLK);
SinglePulser S5(singlepulserR, singlepulserR2, CLK);
SinglePulser S10(singlepulser, singlepulser2F, frame);
SinglePulser S6(singlepulserD, singlepulserDF, frame);
SinglePulser S7(singlepulserU, singlepulserUF, frame);
SinglePulser S8(singlepulserL, singlepulserLF, frame);
SinglePulser S9(singlepulserR, singlepulserRF, frame);
SinglePulser S11(singlepulserESC, singlepulserESC2, frame);
initial
begin
leftFlag <= 0;
upFlag <= 0;
downFlag <= 0;
VFlag <= 0;
startFlag <= 0;
rightFlag <= 1;
moveFlag <= 1;
HFlag <= 1;
X1 <= 70;
X2 <= 20;
Y1 <= 10;
Y2 <= 20;
length <= 50;
ap1 <= 1;
ap2 <= 0;
ap3 <= 0;
end
always @(posedge frame)
begin
singlepulser = ((Q[19:12]==8'h1B) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserD = ((Q[19:12]==8'h72) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserU = ((Q[19:12]==8'h75) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserL = ((Q[19:12]==8'h6B) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserR = ((Q[19:12]==8'h74) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserESC = ((Q[19:12]==8'h76) && (counter == 11) && (Q[8:1] == 8'hF0)) ;
if (ap1==1 && (((X1>=300 && X1<=310) && (rightFlag==1)) || ((X2>=300 && X2<=310) && (leftFlag==1))) && ((Y1>=200 && Y1<=210)))
begin
ap1<=0;
ap2<=1;
ap3<=0;
end
else if (ap1==1 && ((X1>=300 && X1<=310)) && (((Y1>=201 && Y1<=209) && (upFlag==1)) || ((Y2>=200 && Y2<=210) && (downFlag==1))))
begin
ap1<=0;
ap2<=1;
ap3<=0;
end
else if (ap2==1 && (((X1>=600 && X1<=610) && (rightFlag==1)) || ((X2>=600 && X2<=610) && (leftFlag==1))) && ((Y1>=40 && Y1<=50)))
begin
ap1<=0;
ap2<=0;
ap3<=1;
end
else if (ap2==1 && ((X1>=600 && X1<=610)) && (((Y1>=40 && Y1<=50) && (upFlag==1)) || ((Y2>=40 && Y2<=50) && (downFlag==1))))
begin
ap1<=0;
ap2<=0;
ap3<=1;
end
else if (ap3==1 && (((X1>=40 && X1<=50) && (rightFlag==1)) || ((X2>=40 && X2<=50) && (leftFlag==1))) && ((Y1>=400 && Y1<=410)))
begin
ap1<=1;
ap2<=0;
ap3<=0;
end
else if (ap3==1 && ((X1>=40 && X1<=50)) && (((Y1>=400 && Y1<=410) && (upFlag==1)) || ((Y2>=400 && Y2<=410) && (downFlag==1))))
begin
ap1<=1;
ap2<=0;
ap3<=0;
end
if (singlepulser2F ==1)
begin
startFlag <= 1;
rightFlag <= 1;
HFlag <= 1;
moveFlag <= 1;
downFlag <= 0;
upFlag <= 0;
escFlag <= 0;
leftFlag<=0;
ap1<=1;
deathFlag<=0;
end
else if (singlepulserESC2 == 1)
begin
startFlag <= 0;
deathFlag <= 0;
HFlag <= 0;
moveFlag <= 0;
upFlag<=0;
downFlag<=0;
rightFlag<=0;
leftFlag<=0;
escFlag <= 1;
ap1<=0;
ap2<=0;
ap3<=0;
end
else if (singlepulserUF == 1 && startFlag == 1 && HFlag == 1 && moveFlag == 1)
begin
VFlag <= 1;
HFlag <= 0;
upFlag <= 1;
leftFlag <= 0;
rightFlag <= 0;
downFlag <= 0;
end
else if (singlepulserDF == 1 && startFlag == 1 && HFlag == 1 && moveFlag == 1)
begin
VFlag <= 1;
HFlag <= 0;
upFlag <= 0;
leftFlag <= 0;
rightFlag <= 0;
downFlag <= 1;
end
else if (singlepulserLF == 1 && startFlag == 1 && VFlag == 1 && moveFlag == 1)
begin
VFlag <= 0;
HFlag <= 1;
upFlag <= 0;
leftFlag <= 1;
rightFlag <= 0;
downFlag <= 0;
end
else if (singlepulserRF == 1 && startFlag == 1 && VFlag == 1 && moveFlag == 1)
begin
VFlag <= 0;
HFlag <= 1;
upFlag <= 0;
leftFlag <= 0;
rightFlag <= 1;
downFlag <= 0;
end
else if (Q[19:12]==8'h2D && counter == 11 && Q[8:1] == 8'hF0 && startFlag == 1 && moveFlag == 0 && deathFlag==0)
begin
moveFlag <= 1;
end
else if (Q[19:12]==8'h4D && counter == 11 && Q[8:1] == 8'hF0 && startFlag == 1 && moveFlag == 1)
begin
moveFlag <= 0;
end
else if (X1 <= 0 || X2 <= 0 || X1 >= 640 || X2 >= 640 || Y1 <= 0 || Y2 <= 0 || Y1 >= 480 || Y2 >= 480)
begin
moveFlag <= 0;
deathFlag<=1;
startFlag<=0;
ap1<=0;
ap2<=0;
ap3<=0;
end
end
always @(posedge frame)
begin
if (singlepulser2F == 1)
begin
X1 <= 60;
X2 <= 10;
Y1 <= 10;
Y2 <= 20;
end
else if (singlepulserDF == 1 && moveFlag == 1 && rightFlag == 1 && downFlag != 1 && upFlag !=1)
begin
X2 = X1;
X1 = X1 + 10;
Y1 = Y2;
Y2 = Y2 + 50;
end
else if (singlepulserDF == 1 && moveFlag == 1 && leftFlag == 1 && downFlag !=1 && upFlag !=1)
begin
X1 = X2;
X2 = X2 - 10;
Y1 = Y2;
Y2 = Y2 + 50;
end
else if (singlepulserUF == 1 && moveFlag == 1 && upFlag!=1 && downFlag!=1 && rightFlag == 1)
begin
X2 = X1;
X1 = X1 + 10;
Y2 = Y1;
Y1 = Y1 - 50;
end
else if (singlepulserUF == 1 && moveFlag == 1 && upFlag != 1 && downFlag != 1 && leftFlag == 1)
begin
X1 = X2 + 10;
Y1 = Y2 - 50;
end
else if (singlepulserLF == 1 && moveFlag == 1 && leftFlag!=1 && rightFlag!=1 && upFlag == 1)
begin
X2 = X1 - 50;
Y2 = Y1 + 10;
end
else if (singlepulserLF == 1 && moveFlag == 1 && leftFlag!=1 && rightFlag!=1 && downFlag == 1)
begin
X2 = X1 - 50;
Y1 = Y2 - 10;
end
else if (singlepulserRF == 1 && moveFlag == 1 && rightFlag!=1 && leftFlag!=1 && downFlag == 1)
begin
X2 = X1;
X1 = X1 + 50;
Y1 = Y2;
Y2 = Y1 + 10;
end
else if (singlepulserRF == 1 && moveFlag == 1 && rightFlag!=1 && leftFlag!=1 && upFlag == 1)
begin
X1 = X2 + 50;
Y2 = Y1 + 10;
end
else if (leftFlag == 1 && moveFlag == 1)
begin
X1 <= X1 - 10;
X2 <= X2 - 10;
end
else if (rightFlag == 1 && moveFlag == 1 )
begin
X1 <= X1 + 10;
X2 <= X2 + 10;
end
else if (upFlag == 1 && moveFlag == 1)
begin
Y1 <= Y1 - 10;
Y2 <= Y2 - 10;
end
else if (downFlag == 1 && moveFlag == 1)
begin
Y1 <= Y1 + 10;
Y2 <= Y2 + 10;
end
end
endmodule | module Master (CLK, SW6, R1, G1, B1, Hs, Vs, PS2Clk, counter, Q); |
input CLK, SW6, PS2Clk;
reg singlepulser, singlepulserD, singlepulserU, singlepulserL,singlepulserR, singlepulserESC, ap1, ap2, ap3;
wire singlepulser2, singlepulserD2, singlepulserU2, singlepulserL2, singlepulserR2;
wire singlepulser2F, singlepulserDF, singlepulserUF, singlepulserLF, singlepulserRF, singlepulserESC2;
reg [12:0] X1, Y1, X2, Y2;
reg escFlag;
input [21:0] Q;
input [4:0] counter;
output Hs, Vs;
output [3:0] R1, B1, G1;
reg [8:0] length;
reg leftFlag, rightFlag, upFlag, downFlag, moveFlag, VFlag, HFlag, startFlag, deathFlag;
complexDivider CLK1(CLK, slowCLK);
complexDivider2 frame1(CLK, frame);
MonitorB M(slowCLK, X1, X2, Y1, Y2, Hs, Vs, R1, G1, B1, SW6, startFlag, deathFlag, ap1, ap2, ap3, escFlag);
SinglePulser S1(singlepulser, singlepulser2, CLK);
SinglePulser S2(singlepulserD, singlepulserD2, CLK);
SinglePulser S3(singlepulserU, singlepulserU2, CLK);
SinglePulser S4(singlepulserL, singlepulserL2, CLK);
SinglePulser S5(singlepulserR, singlepulserR2, CLK);
SinglePulser S10(singlepulser, singlepulser2F, frame);
SinglePulser S6(singlepulserD, singlepulserDF, frame);
SinglePulser S7(singlepulserU, singlepulserUF, frame);
SinglePulser S8(singlepulserL, singlepulserLF, frame);
SinglePulser S9(singlepulserR, singlepulserRF, frame);
SinglePulser S11(singlepulserESC, singlepulserESC2, frame);
initial
begin
leftFlag <= 0;
upFlag <= 0;
downFlag <= 0;
VFlag <= 0;
startFlag <= 0;
rightFlag <= 1;
moveFlag <= 1;
HFlag <= 1;
X1 <= 70;
X2 <= 20;
Y1 <= 10;
Y2 <= 20;
length <= 50;
ap1 <= 1;
ap2 <= 0;
ap3 <= 0;
end
always @(posedge frame)
begin
singlepulser = ((Q[19:12]==8'h1B) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserD = ((Q[19:12]==8'h72) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserU = ((Q[19:12]==8'h75) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserL = ((Q[19:12]==8'h6B) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserR = ((Q[19:12]==8'h74) && (counter == 11) && (Q[8:1] == 8'hF0));
singlepulserESC = ((Q[19:12]==8'h76) && (counter == 11) && (Q[8:1] == 8'hF0)) ;
if (ap1==1 && (((X1>=300 && X1<=310) && (rightFlag==1)) || ((X2>=300 && X2<=310) && (leftFlag==1))) && ((Y1>=200 && Y1<=210)))
begin
ap1<=0;
ap2<=1;
ap3<=0;
end
else if (ap1==1 && ((X1>=300 && X1<=310)) && (((Y1>=201 && Y1<=209) && (upFlag==1)) || ((Y2>=200 && Y2<=210) && (downFlag==1))))
begin
ap1<=0;
ap2<=1;
ap3<=0;
end
else if (ap2==1 && (((X1>=600 && X1<=610) && (rightFlag==1)) || ((X2>=600 && X2<=610) && (leftFlag==1))) && ((Y1>=40 && Y1<=50)))
begin
ap1<=0;
ap2<=0;
ap3<=1;
end
else if (ap2==1 && ((X1>=600 && X1<=610)) && (((Y1>=40 && Y1<=50) && (upFlag==1)) || ((Y2>=40 && Y2<=50) && (downFlag==1))))
begin
ap1<=0;
ap2<=0;
ap3<=1;
end
else if (ap3==1 && (((X1>=40 && X1<=50) && (rightFlag==1)) || ((X2>=40 && X2<=50) && (leftFlag==1))) && ((Y1>=400 && Y1<=410)))
begin
ap1<=1;
ap2<=0;
ap3<=0;
end
else if (ap3==1 && ((X1>=40 && X1<=50)) && (((Y1>=400 && Y1<=410) && (upFlag==1)) || ((Y2>=400 && Y2<=410) && (downFlag==1))))
begin
ap1<=1;
ap2<=0;
ap3<=0;
end
if (singlepulser2F ==1)
begin
startFlag <= 1;
rightFlag <= 1;
HFlag <= 1;
moveFlag <= 1;
downFlag <= 0;
upFlag <= 0;
escFlag <= 0;
leftFlag<=0;
ap1<=1;
deathFlag<=0;
end
else if (singlepulserESC2 == 1)
begin
startFlag <= 0;
deathFlag <= 0;
HFlag <= 0;
moveFlag <= 0;
upFlag<=0;
downFlag<=0;
rightFlag<=0;
leftFlag<=0;
escFlag <= 1;
ap1<=0;
ap2<=0;
ap3<=0;
end
else if (singlepulserUF == 1 && startFlag == 1 && HFlag == 1 && moveFlag == 1)
begin
VFlag <= 1;
HFlag <= 0;
upFlag <= 1;
leftFlag <= 0;
rightFlag <= 0;
downFlag <= 0;
end
else if (singlepulserDF == 1 && startFlag == 1 && HFlag == 1 && moveFlag == 1)
begin
VFlag <= 1;
HFlag <= 0;
upFlag <= 0;
leftFlag <= 0;
rightFlag <= 0;
downFlag <= 1;
end
else if (singlepulserLF == 1 && startFlag == 1 && VFlag == 1 && moveFlag == 1)
begin
VFlag <= 0;
HFlag <= 1;
upFlag <= 0;
leftFlag <= 1;
rightFlag <= 0;
downFlag <= 0;
end
else if (singlepulserRF == 1 && startFlag == 1 && VFlag == 1 && moveFlag == 1)
begin
VFlag <= 0;
HFlag <= 1;
upFlag <= 0;
leftFlag <= 0;
rightFlag <= 1;
downFlag <= 0;
end
else if (Q[19:12]==8'h2D && counter == 11 && Q[8:1] == 8'hF0 && startFlag == 1 && moveFlag == 0 && deathFlag==0)
begin
moveFlag <= 1;
end
else if (Q[19:12]==8'h4D && counter == 11 && Q[8:1] == 8'hF0 && startFlag == 1 && moveFlag == 1)
begin
moveFlag <= 0;
end
else if (X1 <= 0 || X2 <= 0 || X1 >= 640 || X2 >= 640 || Y1 <= 0 || Y2 <= 0 || Y1 >= 480 || Y2 >= 480)
begin
moveFlag <= 0;
deathFlag<=1;
startFlag<=0;
ap1<=0;
ap2<=0;
ap3<=0;
end
end
always @(posedge frame)
begin
if (singlepulser2F == 1)
begin
X1 <= 60;
X2 <= 10;
Y1 <= 10;
Y2 <= 20;
end
else if (singlepulserDF == 1 && moveFlag == 1 && rightFlag == 1 && downFlag != 1 && upFlag !=1)
begin
X2 = X1;
X1 = X1 + 10;
Y1 = Y2;
Y2 = Y2 + 50;
end
else if (singlepulserDF == 1 && moveFlag == 1 && leftFlag == 1 && downFlag !=1 && upFlag !=1)
begin
X1 = X2;
X2 = X2 - 10;
Y1 = Y2;
Y2 = Y2 + 50;
end
else if (singlepulserUF == 1 && moveFlag == 1 && upFlag!=1 && downFlag!=1 && rightFlag == 1)
begin
X2 = X1;
X1 = X1 + 10;
Y2 = Y1;
Y1 = Y1 - 50;
end
else if (singlepulserUF == 1 && moveFlag == 1 && upFlag != 1 && downFlag != 1 && leftFlag == 1)
begin
X1 = X2 + 10;
Y1 = Y2 - 50;
end
else if (singlepulserLF == 1 && moveFlag == 1 && leftFlag!=1 && rightFlag!=1 && upFlag == 1)
begin
X2 = X1 - 50;
Y2 = Y1 + 10;
end
else if (singlepulserLF == 1 && moveFlag == 1 && leftFlag!=1 && rightFlag!=1 && downFlag == 1)
begin
X2 = X1 - 50;
Y1 = Y2 - 10;
end
else if (singlepulserRF == 1 && moveFlag == 1 && rightFlag!=1 && leftFlag!=1 && downFlag == 1)
begin
X2 = X1;
X1 = X1 + 50;
Y1 = Y2;
Y2 = Y1 + 10;
end
else if (singlepulserRF == 1 && moveFlag == 1 && rightFlag!=1 && leftFlag!=1 && upFlag == 1)
begin
X1 = X2 + 50;
Y2 = Y1 + 10;
end
else if (leftFlag == 1 && moveFlag == 1)
begin
X1 <= X1 - 10;
X2 <= X2 - 10;
end
else if (rightFlag == 1 && moveFlag == 1 )
begin
X1 <= X1 + 10;
X2 <= X2 + 10;
end
else if (upFlag == 1 && moveFlag == 1)
begin
Y1 <= Y1 - 10;
Y2 <= Y2 - 10;
end
else if (downFlag == 1 && moveFlag == 1)
begin
Y1 <= Y1 + 10;
Y2 <= Y2 + 10;
end
end
endmodule | 0 |
137,853 | data/full_repos/permissive/80582133/Snake.v | 80,582,133 | Snake.v | v | 595 | 130 | [] | [] | [] | [(5, 36), (39, 51), (54, 65), (68, 394), (396, 414), (417, 435), (438, 594)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:84: Signal definition not found, creating implicitly: \'slowCLK\'\ncomplexDivider CLK1(CLK, slowCLK); \n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:85: Signal definition not found, creating implicitly: \'frame\'\ncomplexDivider2 frame1(CLK, frame); \n ^~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:471: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nif ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:485: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nelse if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 300,663 | module | module complexDivider(clk100Mhz, slowClk);
input clk100Mhz;
output reg slowClk;
reg[27:0] counter;
initial begin
counter = 0;
slowClk = 0;
end
always @ (posedge clk100Mhz)
begin
if(counter == 2) begin
counter <= 1;
slowClk <= ~slowClk;
end
else begin
counter <= counter + 1;
end
end
endmodule | module complexDivider(clk100Mhz, slowClk); |
input clk100Mhz;
output reg slowClk;
reg[27:0] counter;
initial begin
counter = 0;
slowClk = 0;
end
always @ (posedge clk100Mhz)
begin
if(counter == 2) begin
counter <= 1;
slowClk <= ~slowClk;
end
else begin
counter <= counter + 1;
end
end
endmodule | 0 |
137,854 | data/full_repos/permissive/80582133/Snake.v | 80,582,133 | Snake.v | v | 595 | 130 | [] | [] | [] | [(5, 36), (39, 51), (54, 65), (68, 394), (396, 414), (417, 435), (438, 594)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:84: Signal definition not found, creating implicitly: \'slowCLK\'\ncomplexDivider CLK1(CLK, slowCLK); \n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:85: Signal definition not found, creating implicitly: \'frame\'\ncomplexDivider2 frame1(CLK, frame); \n ^~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:471: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nif ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:485: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nelse if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 300,663 | module | module complexDivider2(clk100Mhz, slowClk);
input clk100Mhz;
output reg slowClk;
reg[27:0] counter;
initial begin
counter = 0;
slowClk = 0;
end
always @ (posedge clk100Mhz)
begin
if(counter == 12500000) begin
counter <= 1;
slowClk <= ~slowClk;
end
else begin
counter <= counter + 1;
end
end
endmodule | module complexDivider2(clk100Mhz, slowClk); |
input clk100Mhz;
output reg slowClk;
reg[27:0] counter;
initial begin
counter = 0;
slowClk = 0;
end
always @ (posedge clk100Mhz)
begin
if(counter == 12500000) begin
counter <= 1;
slowClk <= ~slowClk;
end
else begin
counter <= counter + 1;
end
end
endmodule | 0 |
137,855 | data/full_repos/permissive/80582133/Snake.v | 80,582,133 | Snake.v | v | 595 | 130 | [] | [] | [] | [(5, 36), (39, 51), (54, 65), (68, 394), (396, 414), (417, 435), (438, 594)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:84: Signal definition not found, creating implicitly: \'slowCLK\'\ncomplexDivider CLK1(CLK, slowCLK); \n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/80582133/Snake.v:85: Signal definition not found, creating implicitly: \'frame\'\ncomplexDivider2 frame1(CLK, frame); \n ^~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:471: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nif ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/80582133/Snake.v:485: Comparison is constant due to unsigned arithmetic\n : ... In instance Top.M.M\nelse if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 300,663 | module | module MonitorB(CLK, X1, X2, Y1, Y2, Hsynch, Vsynch, R, G, B, SW6, startFlag, deathFlag, ap1, ap2, ap3, escFlag);
input CLK, SW6, startFlag, deathFlag, escFlag;
output reg [3:0] R, G, B;
input [12:0] X1, X2, Y1, Y2;
reg [12:0] HCount, VCount;
output reg Hsynch, Vsynch;
input ap1, ap2, ap3;
initial
begin
HCount <= 0;
VCount <= 0;
Hsynch <= 1;
Vsynch <= 1;
end
always @(posedge CLK)
begin
if (HCount >= 800)
begin
HCount <= 0;
VCount <= VCount + 1;
end
else
begin
HCount <= HCount + 1;
VCount <= VCount;
end
if ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))
begin
Hsynch <= 1;
Vsynch <= Vsynch;
end
else if (HCount >= 659 && HCount <= 755)
begin
Hsynch <= 0;
Vsynch <= Vsynch;
end
else if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))
begin
Hsynch <= Hsynch;
Vsynch <= 1;
end
else if (VCount == 493 || VCount <= 494)
begin
Vsynch <= 0;
Hsynch <= Hsynch;
end
else
begin
Hsynch <= Hsynch;
Vsynch <= Vsynch;
end
if (VCount >= 525)
begin
VCount <= 0;
end
if (HCount >= 640 || VCount >= 480)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (escFlag==0 &&((startFlag == 1 || deathFlag == 1) && HCount <= X1 && HCount >= X2 && VCount >= Y1 && VCount <= Y2))
begin
R <= 4'hF;
G <= 4'h0;
B <= 4'h0;
end
else if (ap1 == 1 && HCount <= 312 && HCount >= 298 && VCount >= 198 && VCount <= 212 && startFlag == 1)
begin
R<=4'h0;
G<=4'hF;
B<=4'h0;
end
else if (ap1 == 0 && HCount <= 312 && HCount >= 298 && VCount >= 198 && VCount <= 212 && startFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (ap2 == 1 && HCount <= 611 && HCount >= 599 && VCount >= 39 && VCount <= 51 && startFlag == 1)
begin
R<=4'h0;
G<=4'hF;
B<=4'h0;
end
else if (ap2 == 0 && HCount <= 611 && HCount >= 599 && VCount >= 39 && VCount <= 51 && startFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (ap3 == 1 && HCount <= 51 && HCount >= 39 && VCount >= 399 && VCount <= 411 && startFlag == 1)
begin
R<=4'h0;
G<=4'hF;
B<=4'h0;
end
else if (ap3 == 0 && HCount <= 51 && HCount >= 39 && VCount >= 399 && VCount <= 411 && startFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (SW6 == 1)
begin
R <= 4'h0;
G <= 4'hC;
B <= 4'hC;
end
else if (escFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
end
endmodule | module MonitorB(CLK, X1, X2, Y1, Y2, Hsynch, Vsynch, R, G, B, SW6, startFlag, deathFlag, ap1, ap2, ap3, escFlag); |
input CLK, SW6, startFlag, deathFlag, escFlag;
output reg [3:0] R, G, B;
input [12:0] X1, X2, Y1, Y2;
reg [12:0] HCount, VCount;
output reg Hsynch, Vsynch;
input ap1, ap2, ap3;
initial
begin
HCount <= 0;
VCount <= 0;
Hsynch <= 1;
Vsynch <= 1;
end
always @(posedge CLK)
begin
if (HCount >= 800)
begin
HCount <= 0;
VCount <= VCount + 1;
end
else
begin
HCount <= HCount + 1;
VCount <= VCount;
end
if ((HCount >= 0 && HCount <= 659) || (HCount >= 755 && HCount <= 799))
begin
Hsynch <= 1;
Vsynch <= Vsynch;
end
else if (HCount >= 659 && HCount <= 755)
begin
Hsynch <= 0;
Vsynch <= Vsynch;
end
else if ((VCount >= 0 && VCount <= 492) || (VCount >= 495 && VCount <= 524))
begin
Hsynch <= Hsynch;
Vsynch <= 1;
end
else if (VCount == 493 || VCount <= 494)
begin
Vsynch <= 0;
Hsynch <= Hsynch;
end
else
begin
Hsynch <= Hsynch;
Vsynch <= Vsynch;
end
if (VCount >= 525)
begin
VCount <= 0;
end
if (HCount >= 640 || VCount >= 480)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (escFlag==0 &&((startFlag == 1 || deathFlag == 1) && HCount <= X1 && HCount >= X2 && VCount >= Y1 && VCount <= Y2))
begin
R <= 4'hF;
G <= 4'h0;
B <= 4'h0;
end
else if (ap1 == 1 && HCount <= 312 && HCount >= 298 && VCount >= 198 && VCount <= 212 && startFlag == 1)
begin
R<=4'h0;
G<=4'hF;
B<=4'h0;
end
else if (ap1 == 0 && HCount <= 312 && HCount >= 298 && VCount >= 198 && VCount <= 212 && startFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (ap2 == 1 && HCount <= 611 && HCount >= 599 && VCount >= 39 && VCount <= 51 && startFlag == 1)
begin
R<=4'h0;
G<=4'hF;
B<=4'h0;
end
else if (ap2 == 0 && HCount <= 611 && HCount >= 599 && VCount >= 39 && VCount <= 51 && startFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (ap3 == 1 && HCount <= 51 && HCount >= 39 && VCount >= 399 && VCount <= 411 && startFlag == 1)
begin
R<=4'h0;
G<=4'hF;
B<=4'h0;
end
else if (ap3 == 0 && HCount <= 51 && HCount >= 39 && VCount >= 399 && VCount <= 411 && startFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else if (SW6 == 1)
begin
R <= 4'h0;
G <= 4'hC;
B <= 4'hC;
end
else if (escFlag == 1)
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
else
begin
R <= 4'h0;
G <= 4'h0;
B <= 4'h0;
end
end
endmodule | 0 |
137,856 | data/full_repos/permissive/80602845/BS/barrelPipe.v | 80,602,845 | barrelPipe.v | v | 229 | 76 | [] | [] | [] | null | line:16: before: "(" | null | 1: b'%Error: data/full_repos/permissive/80602845/BS/barrelPipe.v:1: Cannot find include file: mux.v\n`include "mux.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/mux.v\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/mux.v.v\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/mux.v.sv\n mux.v\n mux.v.v\n mux.v.sv\n obj_dir/mux.v\n obj_dir/mux.v.v\n obj_dir/mux.v.sv\n%Error: data/full_repos/permissive/80602845/BS/barrelPipe.v:2: Cannot find include file: piped.v\n`include "piped.v" \n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 300,664 | module | module shifter(a , shift , rot , out , clk);
input [31:0] a;
input rot;
input [4:0] shift;
output [31:0] out;
input clk;
reg[4:0] shift1;
reg ip1 , ip2 , ip3 , ip4 , ip5;
wire[31:0] w1 , w1t , w2 , w2t , w3 , w3t , w4 , w4t , w5 , w5t , w6 , at;
piped p1(a , clk , at);
mux m11( (rot & at[31]) , at[0] , shift[0] , w1t[0]);
mux m12( at[0] , at[1] , shift[0] , w1t[1]);
mux m13( at[1] , at[2] , shift[0] , w1t[2]);
mux m14( at[2] , at[3] , shift[0] , w1t[3]);
mux m15( at[3] , at[4] , shift[0] , w1t[4]);
mux m16( at[4] , at[5] , shift[0] , w1t[5]);
mux m17( at[5] , at[6] , shift[0] , w1t[6]);
mux m18( at[6] , at[7] , shift[0] , w1t[7]);
mux m19( at[7] , at[8] , shift[0] , w1t[8]);
mux m110( at[8] , at[9] , shift[0] , w1t[9]);
mux m111( at[9] , at[10] , shift[0] , w1t[10]);
mux m112( at[10] , at[11] , shift[0] , w1t[11]);
mux m113( at[11] , at[12] , shift[0] , w1t[12]);
mux m114( at[12] , at[13] , shift[0] , w1t[13]);
mux m115( at[13] , at[14] , shift[0] , w1t[14]);
mux m116( at[14] , at[15] , shift[0] , w1t[15]);
mux m117( at[15] , at[16] , shift[0] , w1t[16]);
mux m118( at[16] , at[17] , shift[0] , w1t[17]);
mux m119( at[17] , at[18] , shift[0] , w1t[18]);
mux m120( at[18] , at[19] , shift[0] , w1t[19]);
mux m121( at[19] , at[20] , shift[0] , w1t[20]);
mux m122( at[20] , at[21] , shift[0] , w1t[21]);
mux m123( at[21] , at[22] , shift[0] , w1t[22]);
mux m124( at[22] , at[23] , shift[0] , w1t[23]);
mux m125( at[23] , at[24] , shift[0] , w1t[24]);
mux m126( at[24] , at[25] , shift[0] , w1t[25]);
mux m127( at[25] , at[26] , shift[0] , w1t[26]);
mux m128( at[26] , at[27] , shift[0] , w1t[27]);
mux m129( at[27] , at[28] , shift[0] , w1t[28]);
mux m130( at[28] , at[29] , shift[0] , w1t[29]);
mux m131( at[29] , at[30] , shift[0] , w1t[30]);
mux m132( at[30] , at[31] , shift[0] , w1t[31]);
piped p2( w1t , clk , w1);
mux m21( (rot & w1[30]) , w1[0] , shift[1] , w2t[0]);
mux m22( (rot & w1[31]) , w1[1] , shift[1] , w2t[1]);
mux m23( w1[0] , w1[2] , shift[1] , w2t[2]);
mux m24( w1[1] , w1[3] , shift[1] , w2t[3]);
mux m25( w1[2] , w1[4] , shift[1] , w2t[4]);
mux m26( w1[3] , w1[5] , shift[1] , w2t[5]);
mux m27( w1[4] , w1[6] , shift[1] , w2t[6]);
mux m28( w1[5] , w1[7] , shift[1] , w2t[7]);
mux m29( w1[6] , w1[8] , shift[1] , w2t[8]);
mux m210( w1[7] , w1[9] , shift[1] , w2t[9]);
mux m211( w1[8] , w1[10] , shift[1] , w2t[10]);
mux m212( w1[9] , w1[11] , shift[1] , w2t[11]);
mux m213( w1[10] , w1[12] , shift[1] , w2t[12]);
mux m214( w1[11] , w1[13] , shift[1] , w2t[13]);
mux m215( w1[12] , w1[14] , shift[1] , w2t[14]);
mux m216( w1[13] , w1[15] , shift[1] , w2t[15]);
mux m217( w1[14] , w1[16] , shift[1] , w2t[16]);
mux m218( w1[15] , w1[17] , shift[1] , w2t[17]);
mux m219( w1[16] , w1[18] , shift[1] , w2t[18]);
mux m220( w1[17] , w1[19] , shift[1] , w2t[19]);
mux m221( w1[18] , w1[20] , shift[1] , w2t[20]);
mux m222( w1[19] , w1[21] , shift[1] , w2t[21]);
mux m223( w1[20] , w1[22] , shift[1] , w2t[22]);
mux m224( w1[21] , w1[23] , shift[1] , w2t[23]);
mux m225( w1[22] , w1[24] , shift[1] , w2t[24]);
mux m226( w1[23] , w1[25] , shift[1] , w2t[25]);
mux m227( w1[24] , w1[26] , shift[1] , w2t[26]);
mux m228( w1[25] , w1[27] , shift[1] , w2t[27]);
mux m229( w1[26] , w1[28] , shift[1] , w2t[28]);
mux m230( w1[27] , w1[29] , shift[1] , w2t[29]);
mux m231( w1[28] , w1[30] , shift[1] , w2t[30]);
mux m232( w1[29] , w1[31] , shift[1] , w2t[31]);
piped p3(w2t , clk , w2);
mux s31(w2[28] , 0 , rot , w6[0]);
mux s32(w2[29] , 0 , rot , w6[1]);
mux s33(w2[30] , 0 , rot , w6[2]);
mux s34(w2[31] , 0 , rot , w6[3]);
mux m31 ( w6[0] , w2[0] , shift[2] , w3t[0]);
mux m32 ( w6[1] , w2[1] , shift[2] , w3t[1]);
mux m33 ( w6[2] , w2[2] , shift[2] , w3t[2]);
mux m34 ( w6[3] , w2[3] , shift[2] , w3t[3]);
mux m35 ( w2[0] , w2[4] , shift[2] , w3t[4]);
mux m36 ( w2[1] , w2[5] , shift[2] , w3t[5]);
mux m37 ( w2[2] , w2[6] , shift[2] , w3t[6]);
mux m38 ( w2[3] , w2[7] , shift[2] , w3t[7]);
mux m39 ( w2[4] , w2[8] , shift[2] , w3t[8]);
mux m310( w2[5] , w2[9] , shift[2] , w3t[9]);
mux m311( w2[6] , w2[10] , shift[2] , w3t[10]);
mux m312( w2[7] , w2[11] , shift[2] , w3t[11]);
mux m313( w2[8] , w2[12] , shift[2] , w3t[12]);
mux m314( w2[9] , w2[13] , shift[2] , w3t[13]);
mux m315( w2[10] , w2[14] , shift[2] , w3t[14]);
mux m316( w2[11] , w2[15] , shift[2] , w3t[15]);
mux m317( w2[12] , w2[16] , shift[2] , w3t[16]);
mux m318( w2[13] , w2[17] , shift[2] , w3t[17]);
mux m319( w2[14] , w2[18] , shift[2] , w3t[18]);
mux m320( w2[15] , w2[19] , shift[2] , w3t[19]);
mux m321( w2[16] , w2[20] , shift[2] , w3t[20]);
mux m322( w2[17] , w2[21] , shift[2] , w3t[21]);
mux m323( w2[18] , w2[22] , shift[2] , w3t[22]);
mux m324( w2[19] , w2[23] , shift[2] , w3t[23]);
mux m325( w2[20] , w2[24] , shift[2] , w3t[24]);
mux m326( w2[21] , w2[25] , shift[2] , w3t[25]);
mux m327( w2[22] , w2[26] , shift[2] , w3t[26]);
mux m328( w2[23] , w2[27] , shift[2] , w3t[27]);
mux m329( w2[24] , w2[28] , shift[2] , w3t[28]);
mux m330( w2[25] , w2[29] , shift[2] , w3t[29]);
mux m331( w2[26] , w2[30] , shift[2] , w3t[30]);
mux m332( w2[27] , w2[31] , shift[2] , w3t[31]);
piped p4( w3t , clk , w3);
mux s41(w3[24] , 0 , rot , w6[4]);
mux s42(w3[25] , 0 , rot , w6[5]);
mux s43(w3[26] , 0 , rot , w6[6]);
mux s44(w3[27] , 0 , rot , w6[7]);
mux s45(w3[28] , 0 , rot , w6[8]);
mux s46(w3[29] , 0 , rot , w6[9]);
mux s47(w3[30] , 0 , rot , w6[10]);
mux s48(w3[31] , 0 , rot , w6[11]);
mux m41 ( w6[4] , w3[0] , shift[3] , w4t[0]);
mux m42 ( w6[5] , w3[1] , shift[3] , w4t[1]);
mux m43 ( w6[6] , w3[2] , shift[3] , w4t[2]);
mux m44 ( w6[7] , w3[3] , shift[3] , w4t[3]);
mux m45 ( w6[8] , w3[4] , shift[3] , w4t[4]);
mux m46 ( w6[9] , w3[5] , shift[3] , w4t[5]);
mux m47 ( w6[10] , w3[6] , shift[3] , w4t[6]);
mux m48 ( w6[11] , w3[7] , shift[3] , w4t[7]);
mux m49 ( w3[0] , w3[8] , shift[3] , w4t[8]);
mux m410( w3[1] , w3[9] , shift[3] , w4t[9]);
mux m411( w3[2] , w3[10] , shift[3] , w4t[10]);
mux m412( w3[3] , w3[11] , shift[3] , w4t[11]);
mux m413( w3[4] , w3[12] , shift[3] , w4t[12]);
mux m414( w3[5] , w3[13] , shift[3] , w4t[13]);
mux m415( w3[6] , w3[14] , shift[3] , w4t[14]);
mux m416( w3[7] , w3[15] , shift[3] , w4t[15]);
mux m417( w3[8] , w3[16] , shift[3] , w4t[16]);
mux m418( w3[9] , w3[17] , shift[3] , w4t[17]);
mux m419( w3[10] , w3[18] , shift[3] , w4t[18]);
mux m420( w3[11] , w3[19] , shift[3] , w4t[19]);
mux m421( w3[12] , w3[20] , shift[3] , w4t[20]);
mux m422( w3[13] , w3[21] , shift[3] , w4t[21]);
mux m423( w3[14] , w3[22] , shift[3] , w4t[22]);
mux m424( w3[15] , w3[23] , shift[3] , w4t[23]);
mux m425( w3[16] , w3[24] , shift[3] , w4t[24]);
mux m426( w3[17] , w3[25] , shift[3] , w4t[25]);
mux m427( w3[18] , w3[26] , shift[3] , w4t[26]);
mux m428( w3[19] , w3[27] , shift[3] , w4t[27]);
mux m429( w3[20] , w3[28] , shift[3] , w4t[28]);
mux m430( w3[21] , w3[29] , shift[3] , w4t[29]);
mux m431( w3[22] , w3[30] , shift[3] , w4t[30]);
mux m432( w3[23] , w3[31] , shift[3] , w4t[31]);
piped p5(w4t , clk , w4);
mux s51 ( w4[16] , 0 , rot , w6[12]);
mux s52 ( w4[17] , 0 , rot , w6[13]);
mux s53 ( w4[18] , 0 , rot , w6[14]);
mux s54 ( w4[19] , 0 , rot , w6[15]);
mux s55 ( w4[20] , 0 , rot , w6[16]);
mux s56 ( w4[21] , 0 , rot , w6[17]);
mux s57 ( w4[22] , 0 , rot , w6[18]);
mux s58 ( w4[23] , 0 , rot , w6[19]);
mux s59 ( w4[24] , 0 , rot , w6[20]);
mux s510( w4[25] , 0 , rot , w6[21]);
mux s511( w4[26] , 0 , rot , w6[22]);
mux s512( w4[27] , 0 , rot , w6[23]);
mux s513( w4[28] , 0 , rot , w6[24]);
mux s514( w4[29] , 0 , rot , w6[25]);
mux s515( w4[30] , 0 , rot , w6[26]);
mux s516( w4[31] , 0 , rot , w6[27]);
mux m51 ( w6[12] , w4[0] , shift[4] , w5t[0]);
mux m52 ( w6[13] , w4[1] , shift[4] , w5t[1]);
mux m53 ( w6[14] , w4[2] , shift[4] , w5t[2]);
mux m54 ( w6[15] , w4[3] , shift[4] , w5t[3]);
mux m55 ( w6[16] , w4[4] , shift[4] , w5t[4]);
mux m56 ( w6[17] , w4[5] , shift[4] , w5t[5]);
mux m57 ( w6[18] , w4[6] , shift[4] , w5t[6]);
mux m58 ( w6[19] , w4[7] , shift[4] , w5t[7]);
mux m59 ( w6[20] , w4[8] , shift[4] , w5t[8]);
mux m510( w6[21] , w4[9] , shift[4] , w5t[9]);
mux m511( w6[22] , w4[10] , shift[4] , w5t[10]);
mux m512( w6[23] , w4[11] , shift[4] , w5t[11]);
mux m513( w6[24] , w4[12] , shift[4] , w5t[12]);
mux m514( w6[25] , w4[13] , shift[4] , w5t[13]);
mux m515( w6[26] , w4[14] , shift[4] , w5t[14]);
mux m516( w6[27] , w4[15] , shift[4] , w5t[15]);
mux m517( w4[0] , w4[16] , shift[4] , w5t[16]);
mux m518( w4[1] , w4[17] , shift[4] , w5t[17]);
mux m519( w4[2] , w4[18] , shift[4] , w5t[18]);
mux m520( w4[3] , w4[19] , shift[4] , w5t[19]);
mux m521( w4[4] , w4[20] , shift[4] , w5t[20]);
mux m522( w4[5] , w4[21] , shift[4] , w5t[21]);
mux m523( w4[6] , w4[22] , shift[4] , w5t[22]);
mux m524( w4[7] , w4[23] , shift[4] , w5t[23]);
mux m525( w4[8] , w4[24] , shift[4] , w5t[24]);
mux m526( w4[9] , w4[25] , shift[4] , w5t[25]);
mux m527( w4[10] , w4[26] , shift[4] , w5t[26]);
mux m528( w4[11] , w4[27] , shift[4] , w5t[27]);
mux m529( w4[12] , w4[28] , shift[4] , w5t[28]);
mux m530( w4[13] , w4[29] , shift[4] , w5t[29]);
mux m531( w4[14] , w4[30] , shift[4] , w5t[30]);
mux m532( w4[15] , w4[31] , shift[4] , w5t[31]);
piped p6(w5t , clk , w5);
assign out = w5;
endmodule | module shifter(a , shift , rot , out , clk); |
input [31:0] a;
input rot;
input [4:0] shift;
output [31:0] out;
input clk;
reg[4:0] shift1;
reg ip1 , ip2 , ip3 , ip4 , ip5;
wire[31:0] w1 , w1t , w2 , w2t , w3 , w3t , w4 , w4t , w5 , w5t , w6 , at;
piped p1(a , clk , at);
mux m11( (rot & at[31]) , at[0] , shift[0] , w1t[0]);
mux m12( at[0] , at[1] , shift[0] , w1t[1]);
mux m13( at[1] , at[2] , shift[0] , w1t[2]);
mux m14( at[2] , at[3] , shift[0] , w1t[3]);
mux m15( at[3] , at[4] , shift[0] , w1t[4]);
mux m16( at[4] , at[5] , shift[0] , w1t[5]);
mux m17( at[5] , at[6] , shift[0] , w1t[6]);
mux m18( at[6] , at[7] , shift[0] , w1t[7]);
mux m19( at[7] , at[8] , shift[0] , w1t[8]);
mux m110( at[8] , at[9] , shift[0] , w1t[9]);
mux m111( at[9] , at[10] , shift[0] , w1t[10]);
mux m112( at[10] , at[11] , shift[0] , w1t[11]);
mux m113( at[11] , at[12] , shift[0] , w1t[12]);
mux m114( at[12] , at[13] , shift[0] , w1t[13]);
mux m115( at[13] , at[14] , shift[0] , w1t[14]);
mux m116( at[14] , at[15] , shift[0] , w1t[15]);
mux m117( at[15] , at[16] , shift[0] , w1t[16]);
mux m118( at[16] , at[17] , shift[0] , w1t[17]);
mux m119( at[17] , at[18] , shift[0] , w1t[18]);
mux m120( at[18] , at[19] , shift[0] , w1t[19]);
mux m121( at[19] , at[20] , shift[0] , w1t[20]);
mux m122( at[20] , at[21] , shift[0] , w1t[21]);
mux m123( at[21] , at[22] , shift[0] , w1t[22]);
mux m124( at[22] , at[23] , shift[0] , w1t[23]);
mux m125( at[23] , at[24] , shift[0] , w1t[24]);
mux m126( at[24] , at[25] , shift[0] , w1t[25]);
mux m127( at[25] , at[26] , shift[0] , w1t[26]);
mux m128( at[26] , at[27] , shift[0] , w1t[27]);
mux m129( at[27] , at[28] , shift[0] , w1t[28]);
mux m130( at[28] , at[29] , shift[0] , w1t[29]);
mux m131( at[29] , at[30] , shift[0] , w1t[30]);
mux m132( at[30] , at[31] , shift[0] , w1t[31]);
piped p2( w1t , clk , w1);
mux m21( (rot & w1[30]) , w1[0] , shift[1] , w2t[0]);
mux m22( (rot & w1[31]) , w1[1] , shift[1] , w2t[1]);
mux m23( w1[0] , w1[2] , shift[1] , w2t[2]);
mux m24( w1[1] , w1[3] , shift[1] , w2t[3]);
mux m25( w1[2] , w1[4] , shift[1] , w2t[4]);
mux m26( w1[3] , w1[5] , shift[1] , w2t[5]);
mux m27( w1[4] , w1[6] , shift[1] , w2t[6]);
mux m28( w1[5] , w1[7] , shift[1] , w2t[7]);
mux m29( w1[6] , w1[8] , shift[1] , w2t[8]);
mux m210( w1[7] , w1[9] , shift[1] , w2t[9]);
mux m211( w1[8] , w1[10] , shift[1] , w2t[10]);
mux m212( w1[9] , w1[11] , shift[1] , w2t[11]);
mux m213( w1[10] , w1[12] , shift[1] , w2t[12]);
mux m214( w1[11] , w1[13] , shift[1] , w2t[13]);
mux m215( w1[12] , w1[14] , shift[1] , w2t[14]);
mux m216( w1[13] , w1[15] , shift[1] , w2t[15]);
mux m217( w1[14] , w1[16] , shift[1] , w2t[16]);
mux m218( w1[15] , w1[17] , shift[1] , w2t[17]);
mux m219( w1[16] , w1[18] , shift[1] , w2t[18]);
mux m220( w1[17] , w1[19] , shift[1] , w2t[19]);
mux m221( w1[18] , w1[20] , shift[1] , w2t[20]);
mux m222( w1[19] , w1[21] , shift[1] , w2t[21]);
mux m223( w1[20] , w1[22] , shift[1] , w2t[22]);
mux m224( w1[21] , w1[23] , shift[1] , w2t[23]);
mux m225( w1[22] , w1[24] , shift[1] , w2t[24]);
mux m226( w1[23] , w1[25] , shift[1] , w2t[25]);
mux m227( w1[24] , w1[26] , shift[1] , w2t[26]);
mux m228( w1[25] , w1[27] , shift[1] , w2t[27]);
mux m229( w1[26] , w1[28] , shift[1] , w2t[28]);
mux m230( w1[27] , w1[29] , shift[1] , w2t[29]);
mux m231( w1[28] , w1[30] , shift[1] , w2t[30]);
mux m232( w1[29] , w1[31] , shift[1] , w2t[31]);
piped p3(w2t , clk , w2);
mux s31(w2[28] , 0 , rot , w6[0]);
mux s32(w2[29] , 0 , rot , w6[1]);
mux s33(w2[30] , 0 , rot , w6[2]);
mux s34(w2[31] , 0 , rot , w6[3]);
mux m31 ( w6[0] , w2[0] , shift[2] , w3t[0]);
mux m32 ( w6[1] , w2[1] , shift[2] , w3t[1]);
mux m33 ( w6[2] , w2[2] , shift[2] , w3t[2]);
mux m34 ( w6[3] , w2[3] , shift[2] , w3t[3]);
mux m35 ( w2[0] , w2[4] , shift[2] , w3t[4]);
mux m36 ( w2[1] , w2[5] , shift[2] , w3t[5]);
mux m37 ( w2[2] , w2[6] , shift[2] , w3t[6]);
mux m38 ( w2[3] , w2[7] , shift[2] , w3t[7]);
mux m39 ( w2[4] , w2[8] , shift[2] , w3t[8]);
mux m310( w2[5] , w2[9] , shift[2] , w3t[9]);
mux m311( w2[6] , w2[10] , shift[2] , w3t[10]);
mux m312( w2[7] , w2[11] , shift[2] , w3t[11]);
mux m313( w2[8] , w2[12] , shift[2] , w3t[12]);
mux m314( w2[9] , w2[13] , shift[2] , w3t[13]);
mux m315( w2[10] , w2[14] , shift[2] , w3t[14]);
mux m316( w2[11] , w2[15] , shift[2] , w3t[15]);
mux m317( w2[12] , w2[16] , shift[2] , w3t[16]);
mux m318( w2[13] , w2[17] , shift[2] , w3t[17]);
mux m319( w2[14] , w2[18] , shift[2] , w3t[18]);
mux m320( w2[15] , w2[19] , shift[2] , w3t[19]);
mux m321( w2[16] , w2[20] , shift[2] , w3t[20]);
mux m322( w2[17] , w2[21] , shift[2] , w3t[21]);
mux m323( w2[18] , w2[22] , shift[2] , w3t[22]);
mux m324( w2[19] , w2[23] , shift[2] , w3t[23]);
mux m325( w2[20] , w2[24] , shift[2] , w3t[24]);
mux m326( w2[21] , w2[25] , shift[2] , w3t[25]);
mux m327( w2[22] , w2[26] , shift[2] , w3t[26]);
mux m328( w2[23] , w2[27] , shift[2] , w3t[27]);
mux m329( w2[24] , w2[28] , shift[2] , w3t[28]);
mux m330( w2[25] , w2[29] , shift[2] , w3t[29]);
mux m331( w2[26] , w2[30] , shift[2] , w3t[30]);
mux m332( w2[27] , w2[31] , shift[2] , w3t[31]);
piped p4( w3t , clk , w3);
mux s41(w3[24] , 0 , rot , w6[4]);
mux s42(w3[25] , 0 , rot , w6[5]);
mux s43(w3[26] , 0 , rot , w6[6]);
mux s44(w3[27] , 0 , rot , w6[7]);
mux s45(w3[28] , 0 , rot , w6[8]);
mux s46(w3[29] , 0 , rot , w6[9]);
mux s47(w3[30] , 0 , rot , w6[10]);
mux s48(w3[31] , 0 , rot , w6[11]);
mux m41 ( w6[4] , w3[0] , shift[3] , w4t[0]);
mux m42 ( w6[5] , w3[1] , shift[3] , w4t[1]);
mux m43 ( w6[6] , w3[2] , shift[3] , w4t[2]);
mux m44 ( w6[7] , w3[3] , shift[3] , w4t[3]);
mux m45 ( w6[8] , w3[4] , shift[3] , w4t[4]);
mux m46 ( w6[9] , w3[5] , shift[3] , w4t[5]);
mux m47 ( w6[10] , w3[6] , shift[3] , w4t[6]);
mux m48 ( w6[11] , w3[7] , shift[3] , w4t[7]);
mux m49 ( w3[0] , w3[8] , shift[3] , w4t[8]);
mux m410( w3[1] , w3[9] , shift[3] , w4t[9]);
mux m411( w3[2] , w3[10] , shift[3] , w4t[10]);
mux m412( w3[3] , w3[11] , shift[3] , w4t[11]);
mux m413( w3[4] , w3[12] , shift[3] , w4t[12]);
mux m414( w3[5] , w3[13] , shift[3] , w4t[13]);
mux m415( w3[6] , w3[14] , shift[3] , w4t[14]);
mux m416( w3[7] , w3[15] , shift[3] , w4t[15]);
mux m417( w3[8] , w3[16] , shift[3] , w4t[16]);
mux m418( w3[9] , w3[17] , shift[3] , w4t[17]);
mux m419( w3[10] , w3[18] , shift[3] , w4t[18]);
mux m420( w3[11] , w3[19] , shift[3] , w4t[19]);
mux m421( w3[12] , w3[20] , shift[3] , w4t[20]);
mux m422( w3[13] , w3[21] , shift[3] , w4t[21]);
mux m423( w3[14] , w3[22] , shift[3] , w4t[22]);
mux m424( w3[15] , w3[23] , shift[3] , w4t[23]);
mux m425( w3[16] , w3[24] , shift[3] , w4t[24]);
mux m426( w3[17] , w3[25] , shift[3] , w4t[25]);
mux m427( w3[18] , w3[26] , shift[3] , w4t[26]);
mux m428( w3[19] , w3[27] , shift[3] , w4t[27]);
mux m429( w3[20] , w3[28] , shift[3] , w4t[28]);
mux m430( w3[21] , w3[29] , shift[3] , w4t[29]);
mux m431( w3[22] , w3[30] , shift[3] , w4t[30]);
mux m432( w3[23] , w3[31] , shift[3] , w4t[31]);
piped p5(w4t , clk , w4);
mux s51 ( w4[16] , 0 , rot , w6[12]);
mux s52 ( w4[17] , 0 , rot , w6[13]);
mux s53 ( w4[18] , 0 , rot , w6[14]);
mux s54 ( w4[19] , 0 , rot , w6[15]);
mux s55 ( w4[20] , 0 , rot , w6[16]);
mux s56 ( w4[21] , 0 , rot , w6[17]);
mux s57 ( w4[22] , 0 , rot , w6[18]);
mux s58 ( w4[23] , 0 , rot , w6[19]);
mux s59 ( w4[24] , 0 , rot , w6[20]);
mux s510( w4[25] , 0 , rot , w6[21]);
mux s511( w4[26] , 0 , rot , w6[22]);
mux s512( w4[27] , 0 , rot , w6[23]);
mux s513( w4[28] , 0 , rot , w6[24]);
mux s514( w4[29] , 0 , rot , w6[25]);
mux s515( w4[30] , 0 , rot , w6[26]);
mux s516( w4[31] , 0 , rot , w6[27]);
mux m51 ( w6[12] , w4[0] , shift[4] , w5t[0]);
mux m52 ( w6[13] , w4[1] , shift[4] , w5t[1]);
mux m53 ( w6[14] , w4[2] , shift[4] , w5t[2]);
mux m54 ( w6[15] , w4[3] , shift[4] , w5t[3]);
mux m55 ( w6[16] , w4[4] , shift[4] , w5t[4]);
mux m56 ( w6[17] , w4[5] , shift[4] , w5t[5]);
mux m57 ( w6[18] , w4[6] , shift[4] , w5t[6]);
mux m58 ( w6[19] , w4[7] , shift[4] , w5t[7]);
mux m59 ( w6[20] , w4[8] , shift[4] , w5t[8]);
mux m510( w6[21] , w4[9] , shift[4] , w5t[9]);
mux m511( w6[22] , w4[10] , shift[4] , w5t[10]);
mux m512( w6[23] , w4[11] , shift[4] , w5t[11]);
mux m513( w6[24] , w4[12] , shift[4] , w5t[12]);
mux m514( w6[25] , w4[13] , shift[4] , w5t[13]);
mux m515( w6[26] , w4[14] , shift[4] , w5t[14]);
mux m516( w6[27] , w4[15] , shift[4] , w5t[15]);
mux m517( w4[0] , w4[16] , shift[4] , w5t[16]);
mux m518( w4[1] , w4[17] , shift[4] , w5t[17]);
mux m519( w4[2] , w4[18] , shift[4] , w5t[18]);
mux m520( w4[3] , w4[19] , shift[4] , w5t[19]);
mux m521( w4[4] , w4[20] , shift[4] , w5t[20]);
mux m522( w4[5] , w4[21] , shift[4] , w5t[21]);
mux m523( w4[6] , w4[22] , shift[4] , w5t[22]);
mux m524( w4[7] , w4[23] , shift[4] , w5t[23]);
mux m525( w4[8] , w4[24] , shift[4] , w5t[24]);
mux m526( w4[9] , w4[25] , shift[4] , w5t[25]);
mux m527( w4[10] , w4[26] , shift[4] , w5t[26]);
mux m528( w4[11] , w4[27] , shift[4] , w5t[27]);
mux m529( w4[12] , w4[28] , shift[4] , w5t[28]);
mux m530( w4[13] , w4[29] , shift[4] , w5t[29]);
mux m531( w4[14] , w4[30] , shift[4] , w5t[30]);
mux m532( w4[15] , w4[31] , shift[4] , w5t[31]);
piped p6(w5t , clk , w5);
assign out = w5;
endmodule | 0 |
137,857 | data/full_repos/permissive/80602845/BS/dff.v | 80,602,845 | dff.v | v | 11 | 26 | [] | [] | [] | null | line:8: before: "(" | data/verilator_xmls/35a4cbcb-331d-43a8-a7a2-bd356a4da771.xml | null | 300,665 | module | module dff(d , clk , q);
input d , clk;
output q;
reg q;
initial begin
q = 0;
end
always @(posedge(clk))
q<=d;
endmodule | module dff(d , clk , q); |
input d , clk;
output q;
reg q;
initial begin
q = 0;
end
always @(posedge(clk))
q<=d;
endmodule | 0 |
137,858 | data/full_repos/permissive/80602845/BS/mux.v | 80,602,845 | mux.v | v | 9 | 44 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/9560d4c2-2359-4277-9f2b-0e87d98f274a.xml | null | 300,666 | module | module mux(a , b , select , out);
input a , b , select;
output out;
wire a, b, select, out;
assign out = (select & a) | (!select & b);
endmodule | module mux(a , b , select , out); |
input a , b , select;
output out;
wire a, b, select, out;
assign out = (select & a) | (!select & b);
endmodule | 0 |
137,859 | data/full_repos/permissive/80602845/BS/piped.v | 80,602,845 | piped.v | v | 42 | 31 | [] | [] | [] | null | line:8: before: "(" | null | 1: b'%Error: data/full_repos/permissive/80602845/BS/piped.v:1: Cannot find include file: dff.v\n`include "dff.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/dff.v\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/dff.v.v\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/dff.v.sv\n dff.v\n dff.v.v\n dff.v.sv\n obj_dir/dff.v\n obj_dir/dff.v.v\n obj_dir/dff.v.sv\n%Error: Exiting due to 1 error(s)\n' | 300,667 | module | module piped(a , clk , b);
input[31:0] a;
input clk;
output[31:0] b;
wire[31:0] b;
dff d0( a[0] , clk , b[0]);
dff d1( a[1] , clk , b[1]);
dff d2( a[2] , clk , b[2]);
dff d3( a[3] , clk , b[3]);
dff d4( a[4] , clk , b[4]);
dff d5( a[5] , clk , b[5]);
dff d6( a[6] , clk , b[6]);
dff d7( a[7] , clk , b[7]);
dff d8( a[8] , clk , b[8]);
dff d9( a[9] , clk , b[9]);
dff d10(a[10] , clk , b[10]);
dff d11(a[11] , clk , b[11]);
dff d12(a[12] , clk , b[12]);
dff d13(a[13] , clk , b[13]);
dff d14(a[14] , clk , b[14]);
dff d15(a[15] , clk , b[15]);
dff d16(a[16] , clk , b[16]);
dff d17(a[17] , clk , b[17]);
dff d18(a[18] , clk , b[18]);
dff d19(a[19] , clk , b[19]);
dff d20(a[20] , clk , b[20]);
dff d21(a[21] , clk , b[21]);
dff d22(a[22] , clk , b[22]);
dff d23(a[23] , clk , b[23]);
dff d24(a[24] , clk , b[24]);
dff d25(a[25] , clk , b[25]);
dff d26(a[26] , clk , b[26]);
dff d27(a[27] , clk , b[27]);
dff d28(a[28] , clk , b[28]);
dff d29(a[29] , clk , b[29]);
dff d30(a[30] , clk , b[30]);
dff d31(a[31] , clk , b[31]);
endmodule | module piped(a , clk , b); |
input[31:0] a;
input clk;
output[31:0] b;
wire[31:0] b;
dff d0( a[0] , clk , b[0]);
dff d1( a[1] , clk , b[1]);
dff d2( a[2] , clk , b[2]);
dff d3( a[3] , clk , b[3]);
dff d4( a[4] , clk , b[4]);
dff d5( a[5] , clk , b[5]);
dff d6( a[6] , clk , b[6]);
dff d7( a[7] , clk , b[7]);
dff d8( a[8] , clk , b[8]);
dff d9( a[9] , clk , b[9]);
dff d10(a[10] , clk , b[10]);
dff d11(a[11] , clk , b[11]);
dff d12(a[12] , clk , b[12]);
dff d13(a[13] , clk , b[13]);
dff d14(a[14] , clk , b[14]);
dff d15(a[15] , clk , b[15]);
dff d16(a[16] , clk , b[16]);
dff d17(a[17] , clk , b[17]);
dff d18(a[18] , clk , b[18]);
dff d19(a[19] , clk , b[19]);
dff d20(a[20] , clk , b[20]);
dff d21(a[21] , clk , b[21]);
dff d22(a[22] , clk , b[22]);
dff d23(a[23] , clk , b[23]);
dff d24(a[24] , clk , b[24]);
dff d25(a[25] , clk , b[25]);
dff d26(a[26] , clk , b[26]);
dff d27(a[27] , clk , b[27]);
dff d28(a[28] , clk , b[28]);
dff d29(a[29] , clk , b[29]);
dff d30(a[30] , clk , b[30]);
dff d31(a[31] , clk , b[31]);
endmodule | 0 |
137,860 | data/full_repos/permissive/80602845/BS/test.v | 80,602,845 | test.v | v | 37 | 97 | [] | [] | [] | null | line:16: before: "(" | null | 1: b'%Error: data/full_repos/permissive/80602845/BS/test.v:1: Cannot find include file: barrelPipe.v\n`include "barrelPipe.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/barrelPipe.v\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/barrelPipe.v.v\n data/full_repos/permissive/80602845/BS,data/full_repos/permissive/80602845/barrelPipe.v.sv\n barrelPipe.v\n barrelPipe.v.v\n barrelPipe.v.sv\n obj_dir/barrelPipe.v\n obj_dir/barrelPipe.v.v\n obj_dir/barrelPipe.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/80602845/BS/test.v:14: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80602845/BS/test.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 shift=shift+1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80602845/BS/test.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Error: data/full_repos/permissive/80602845/BS/test.v:34: Unsupported or unknown PLI call: $monitor\n $monitor($time , "\\ta = %d\\tshift = %d\\trotate = %d\\toutput = %d", a, shift, rot, out, $time);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 300,668 | module | module test;
reg[31:0] a;
reg[4:0] shift;
reg rot;
wire[31:0] out;
reg clk;
shifter bs(a , shift , rot , out , clk);
always begin
#1
clk = ~clk;
end
initial begin
clk = 1'b1;
a = 32'd1;
rot = 1'b1;
shift = 5'b00001;
end
always begin
#20 shift=shift+1;
end
initial begin
#1000
$finish;
end
initial begin
$monitor($time , "\ta = %d\tshift = %d\trotate = %d\toutput = %d", a, shift, rot, out, $time);
end
endmodule | module test; |
reg[31:0] a;
reg[4:0] shift;
reg rot;
wire[31:0] out;
reg clk;
shifter bs(a , shift , rot , out , clk);
always begin
#1
clk = ~clk;
end
initial begin
clk = 1'b1;
a = 32'd1;
rot = 1'b1;
shift = 5'b00001;
end
always begin
#20 shift=shift+1;
end
initial begin
#1000
$finish;
end
initial begin
$monitor($time , "\ta = %d\tshift = %d\trotate = %d\toutput = %d", a, shift, rot, out, $time);
end
endmodule | 0 |
137,861 | data/full_repos/permissive/80602845/CLA/cla32.v | 80,602,845 | cla32.v | v | 12 | 46 | [] | [] | [] | [(1, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/CLA/cla32.v:7: Cannot find file containing module: 'cla8'\n cla8 fc(a[7:0],b[7:0],cin,s[7:0],w1);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/80602845/CLA,data/full_repos/permissive/80602845/cla8\n data/full_repos/permissive/80602845/CLA,data/full_repos/permissive/80602845/cla8.v\n data/full_repos/permissive/80602845/CLA,data/full_repos/permissive/80602845/cla8.sv\n cla8\n cla8.v\n cla8.sv\n obj_dir/cla8\n obj_dir/cla8.v\n obj_dir/cla8.sv\n%Error: data/full_repos/permissive/80602845/CLA/cla32.v:8: Cannot find file containing module: 'cla8'\n cla8 f2(a[15:8],b[15:8],w1,s[15:8],w2);\n ^~~~\n%Error: data/full_repos/permissive/80602845/CLA/cla32.v:9: Cannot find file containing module: 'cla8'\n cla8 f3(a[23:16],b[23:16],w2,s[23:16],w3);\n ^~~~\n%Error: data/full_repos/permissive/80602845/CLA/cla32.v:10: Cannot find file containing module: 'cla8'\n cla8 f4(a[31:24],b[31:24],w3,s[31:24],cout);\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 300,669 | module | module cla32(a,b,cin,s,cout);
input [31:0]a,b;
input cin;
output [31:0]s;
output cout;
wire w1,w2,w3;
cla8 fc(a[7:0],b[7:0],cin,s[7:0],w1);
cla8 f2(a[15:8],b[15:8],w1,s[15:8],w2);
cla8 f3(a[23:16],b[23:16],w2,s[23:16],w3);
cla8 f4(a[31:24],b[31:24],w3,s[31:24],cout);
endmodule | module cla32(a,b,cin,s,cout); |
input [31:0]a,b;
input cin;
output [31:0]s;
output cout;
wire w1,w2,w3;
cla8 fc(a[7:0],b[7:0],cin,s[7:0],w1);
cla8 f2(a[15:8],b[15:8],w1,s[15:8],w2);
cla8 f3(a[23:16],b[23:16],w2,s[23:16],w3);
cla8 f4(a[31:24],b[31:24],w3,s[31:24],cout);
endmodule | 0 |
137,862 | data/full_repos/permissive/80602845/CLA/cla4.v | 80,602,845 | cla4.v | v | 21 | 96 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/460f642d-a432-429c-b5ac-42f49bb80e0d.xml | null | 300,670 | module | module cla4(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire [3:0]p,g,car;
assign p=a^b;
assign g=a&b;
assign car[0]=cin;
assign car[1]=g[0] | p[0]&cin;
assign car[2]=g[1] | p[1]&g[0] | p[1]&p[0]&cin;
assign car[3]=g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
assign cout=g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&cin;
assign s=p^car;
endmodule | module cla4(a,b,cin,s,cout); |
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire [3:0]p,g,car;
assign p=a^b;
assign g=a&b;
assign car[0]=cin;
assign car[1]=g[0] | p[0]&cin;
assign car[2]=g[1] | p[1]&g[0] | p[1]&p[0]&cin;
assign car[3]=g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
assign cout=g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&cin;
assign s=p^car;
endmodule | 0 |
137,863 | data/full_repos/permissive/80602845/CLA/cla8.v | 80,602,845 | cla8.v | v | 25 | 254 | [] | [] | [] | [(1, 24)] | null | data/verilator_xmls/ac4d4ab3-77da-4a3f-b791-5f03e4b08c9b.xml | null | 300,671 | module | module cla8(a,b,cin,s,cout);
input [7:0]a,b;
input cin;
output [7:0]s;
output cout;
wire [7:0]p,g,car;
assign p=a^b;
assign g=a&b;
assign car[0]=cin;
assign car[1]=g[0] | p[0]&cin;
assign car[2]=g[1] | p[1]&g[0] | p[1]&p[0]&cin;
assign car[3]=g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
assign car[4]=g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&cin;
assign car[5]=g[4] | p[4]&g[3] | p[4]&p[3]&g[2] | p[4]&p[3]&p[2]&g[1] | p[4]&p[3]&p[2]&p[1]&g[0] | p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign car[6]=g[5] | p[5]&g[4] | p[5]&p[4]&g[3] | p[5]&p[4]&p[3]&g[2] | p[5]&p[4]&p[3]&p[2]&g[1] | p[5]&p[4]&p[3]&p[2]&p[1]&g[0] | p[5]&p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign car[7]=g[6] | p[6]&g[5] | p[6]&p[5]&g[4] | p[6]&p[5]&p[4]&g[3] | p[6]&p[5]&p[4]&p[3]&g[2] | p[6]&p[5]&p[4]&p[3]&p[2]&g[1] | p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&g[0] | p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign cout=g[7] | p[7]&g[6] | p[7]&p[6]&g[5] | p[7]&p[6]&p[5]&g[4] | p[7]&p[6]&p[5]&p[4]&g[3] | p[7]&p[6]&p[5]&p[4]&p[3]&g[2] | p[7]&p[6]&p[5]&p[4]&p[3]&p[2]&g[1] | p[7]&p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&g[0] | p[7]&p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign s=p^car;
endmodule | module cla8(a,b,cin,s,cout); |
input [7:0]a,b;
input cin;
output [7:0]s;
output cout;
wire [7:0]p,g,car;
assign p=a^b;
assign g=a&b;
assign car[0]=cin;
assign car[1]=g[0] | p[0]&cin;
assign car[2]=g[1] | p[1]&g[0] | p[1]&p[0]&cin;
assign car[3]=g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
assign car[4]=g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&cin;
assign car[5]=g[4] | p[4]&g[3] | p[4]&p[3]&g[2] | p[4]&p[3]&p[2]&g[1] | p[4]&p[3]&p[2]&p[1]&g[0] | p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign car[6]=g[5] | p[5]&g[4] | p[5]&p[4]&g[3] | p[5]&p[4]&p[3]&g[2] | p[5]&p[4]&p[3]&p[2]&g[1] | p[5]&p[4]&p[3]&p[2]&p[1]&g[0] | p[5]&p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign car[7]=g[6] | p[6]&g[5] | p[6]&p[5]&g[4] | p[6]&p[5]&p[4]&g[3] | p[6]&p[5]&p[4]&p[3]&g[2] | p[6]&p[5]&p[4]&p[3]&p[2]&g[1] | p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&g[0] | p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign cout=g[7] | p[7]&g[6] | p[7]&p[6]&g[5] | p[7]&p[6]&p[5]&g[4] | p[7]&p[6]&p[5]&p[4]&g[3] | p[7]&p[6]&p[5]&p[4]&p[3]&g[2] | p[7]&p[6]&p[5]&p[4]&p[3]&p[2]&g[1] | p[7]&p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&g[0] | p[7]&p[6]&p[5]&p[4]&p[3]&p[2]&p[1]&p[0]&cin;
assign s=p^car;
endmodule | 0 |
137,864 | data/full_repos/permissive/80602845/CLA/tb32.v | 80,602,845 | tb32.v | v | 19 | 53 | [] | [] | [] | [(1, 18)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/80602845/CLA/tb32.v:9: Unsupported: Ignoring delay on this delayed statement.\n #5 a=32\'d2147483647; b=32\'d2147483648; cin=1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/80602845/CLA/tb32.v:16: Unsupported or unknown PLI call: $monitor\n $monitor ($time, " %d %d %b %d %b",a,b,cin,s,cout);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,672 | module | module tb();
reg [31:0]a,b;
reg cin;
wire [31:0]s;
wire cout;
cla32 f(a,b,cin,s,cout);
initial begin
#5 a=32'd2147483647; b=32'd2147483648; cin=1'b0;
end
initial begin
$monitor ($time, " %d %d %b %d %b",a,b,cin,s,cout);
end
endmodule | module tb(); |
reg [31:0]a,b;
reg cin;
wire [31:0]s;
wire cout;
cla32 f(a,b,cin,s,cout);
initial begin
#5 a=32'd2147483647; b=32'd2147483648; cin=1'b0;
end
initial begin
$monitor ($time, " %d %d %b %d %b",a,b,cin,s,cout);
end
endmodule | 0 |
137,865 | data/full_repos/permissive/80602845/CLA/tbcl8.v | 80,602,845 | tbcl8.v | v | 19 | 53 | [] | [] | [] | [(1, 18)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/80602845/CLA/tbcl8.v:9: Unsupported: Ignoring delay on this delayed statement.\n #5 a=8\'d56; b=8\'d24; cin=1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80602845/CLA/tbcl8.v:10: Unsupported: Ignoring delay on this delayed statement.\n #10 a=8\'d34; b=8\'d44; cin=1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80602845/CLA/tbcl8.v:11: Unsupported: Ignoring delay on this delayed statement.\n #15 a=8\'d128; b=8\'d77; cin=1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80602845/CLA/tbcl8.v:12: Unsupported: Ignoring delay on this delayed statement.\n #20 a=8\'d200; b=8\'d11; cin=1\'b1;\n ^\n%Error: data/full_repos/permissive/80602845/CLA/tbcl8.v:16: Unsupported or unknown PLI call: $monitor\n $monitor ($time, " %d %d %b %d %b",a,b,cin,s,cout);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,673 | module | module tb();
reg [7:0]a,b;
reg cin;
wire [7:0]s;
wire cout;
cla8 f(a,b,cin,s,cout);
initial begin
#5 a=8'd56; b=8'd24; cin=1'b0;
#10 a=8'd34; b=8'd44; cin=1'b0;
#15 a=8'd128; b=8'd77; cin=1'b1;
#20 a=8'd200; b=8'd11; cin=1'b1;
end
initial begin
$monitor ($time, " %d %d %b %d %b",a,b,cin,s,cout);
end
endmodule | module tb(); |
reg [7:0]a,b;
reg cin;
wire [7:0]s;
wire cout;
cla8 f(a,b,cin,s,cout);
initial begin
#5 a=8'd56; b=8'd24; cin=1'b0;
#10 a=8'd34; b=8'd44; cin=1'b0;
#15 a=8'd128; b=8'd77; cin=1'b1;
#20 a=8'd200; b=8'd11; cin=1'b1;
end
initial begin
$monitor ($time, " %d %d %b %d %b",a,b,cin,s,cout);
end
endmodule | 0 |
137,866 | data/full_repos/permissive/80602845/FAdd/cirmod.v | 80,602,845 | cirmod.v | v | 8 | 48 | [] | [] | [] | [(1, 7)] | null | data/verilator_xmls/f0481852-0ab1-41e8-afad-843466ca2b36.xml | null | 300,674 | module | module cirmod(gl , al , gr , ar , gout , aout);
input gr , ar , gl , al ;
output gout , aout;
assign gout = gl + (al & gr);
assign aout = al & ar;
endmodule | module cirmod(gl , al , gr , ar , gout , aout); |
input gr , ar , gl , al ;
output gout , aout;
assign gout = gl + (al & gr);
assign aout = al & ar;
endmodule | 0 |
137,867 | data/full_repos/permissive/80602845/FAdd/csave.v | 80,602,845 | csave.v | v | 15 | 41 | [] | [] | [] | [(1, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/FAdd/csave.v:12: Cannot find file containing module: 'dff_64'\n dff_64 d1(s,clk,sum);\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff_64\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff_64.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff_64.sv\n dff_64\n dff_64.v\n dff_64.sv\n obj_dir/dff_64\n obj_dir/dff_64.v\n obj_dir/dff_64.sv\n%Error: data/full_repos/permissive/80602845/FAdd/csave.v:13: Cannot find file containing module: 'dff_64'\n dff_64 d2(ca,clk,carry);\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 300,675 | module | module csave(a,b,c,s,ca,clk);
input [62:0]a,b,c;
input clk;
wire [63:0]sum,carry;
output [63:0]s,ca;
assign sum[62:0]=a^b^c;
assign carry[63:1]= a&b | b&c | c&a;
assign carry[0]=0;
assign sum[63]=0;
dff_64 d1(s,clk,sum);
dff_64 d2(ca,clk,carry);
endmodule | module csave(a,b,c,s,ca,clk); |
input [62:0]a,b,c;
input clk;
wire [63:0]sum,carry;
output [63:0]s,ca;
assign sum[62:0]=a^b^c;
assign carry[63:1]= a&b | b&c | c&a;
assign carry[0]=0;
assign sum[63]=0;
dff_64 d1(s,clk,sum);
dff_64 d2(ca,clk,carry);
endmodule | 0 |
137,868 | data/full_repos/permissive/80602845/FAdd/dotmod.v | 80,602,845 | dotmod.v | v | 7 | 36 | [] | [] | [] | [(1, 6)] | null | data/verilator_xmls/7275b78b-62b6-4001-8f7a-79f623cb56ef.xml | null | 300,677 | module | module dotmod(gl , al , gr , gout);
input gl , al , gr;
output gout;
assign gout = gl + (al & gr);
endmodule | module dotmod(gl , al , gr , gout); |
input gl , al , gr;
output gout;
assign gout = gl + (al & gr);
endmodule | 0 |
137,869 | data/full_repos/permissive/80602845/FAdd/p.v | 80,602,845 | p.v | v | 15 | 38 | [] | [] | [] | [(1, 5), (7, 14)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80602845/FAdd/p.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dot\'\nmodule dot(gout,gl,al,gr);\n ^~~\n : ... Top module \'circle\'\nmodule circle(gout,aout,gl,al,gr,ar);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,678 | module | module dot(gout,gl,al,gr);
output gout;
input gr,gl,al;
assign gout = gl | (al & gr);
endmodule | module dot(gout,gl,al,gr); |
output gout;
input gr,gl,al;
assign gout = gl | (al & gr);
endmodule | 0 |
137,870 | data/full_repos/permissive/80602845/FAdd/p.v | 80,602,845 | p.v | v | 15 | 38 | [] | [] | [] | [(1, 5), (7, 14)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80602845/FAdd/p.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dot\'\nmodule dot(gout,gl,al,gr);\n ^~~\n : ... Top module \'circle\'\nmodule circle(gout,aout,gl,al,gr,ar);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,678 | module | module circle(gout,aout,gl,al,gr,ar);
output gout,aout;
input gl,al,gr,ar;
assign gout = gl | (al & gr);
assign aout = al & ar;
endmodule | module circle(gout,aout,gl,al,gr,ar); |
output gout,aout;
input gl,al,gr,ar;
assign gout = gl | (al & gr);
assign aout = al & ar;
endmodule | 0 |
137,871 | data/full_repos/permissive/80602845/FAdd/partProduct.v | 80,602,845 | partProduct.v | v | 41 | 26 | [] | [] | [] | [(1, 40)] | null | data/verilator_xmls/fe77730f-b516-4d25-8a45-c6e1da7905f6.xml | null | 300,679 | module | module pgen(a,b,c);
input [31:0]a;
input b;
output [31:0]c;
assign c[0]=a[0]&b;
assign c[1]=a[1]&b;
assign c[2]=a[2]&b;
assign c[3]=a[3]&b;
assign c[4]=a[4]&b;
assign c[5]=a[5]&b;
assign c[6]=a[6]&b;
assign c[7]=a[7]&b;
assign c[8]=a[8]&b;
assign c[9]=a[9]&b;
assign c[10]=a[10]&b;
assign c[11]=a[11]&b;
assign c[12]=a[12]&b;
assign c[13]=a[13]&b;
assign c[14]=a[14]&b;
assign c[15]=a[15]&b;
assign c[16]=a[16]&b;
assign c[17]=a[17]&b;
assign c[18]=a[18]&b;
assign c[19]=a[19]&b;
assign c[20]=a[20]&b;
assign c[21]=a[21]&b;
assign c[22]=a[22]&b;
assign c[23]=a[23]&b;
assign c[24]=a[24]&b;
assign c[25]=a[25]&b;
assign c[26]=a[26]&b;
assign c[27]=a[27]&b;
assign c[28]=a[28]&b;
assign c[29]=a[29]&b;
assign c[30]=a[30]&b;
assign c[31]=a[31]&b;
endmodule | module pgen(a,b,c); |
input [31:0]a;
input b;
output [31:0]c;
assign c[0]=a[0]&b;
assign c[1]=a[1]&b;
assign c[2]=a[2]&b;
assign c[3]=a[3]&b;
assign c[4]=a[4]&b;
assign c[5]=a[5]&b;
assign c[6]=a[6]&b;
assign c[7]=a[7]&b;
assign c[8]=a[8]&b;
assign c[9]=a[9]&b;
assign c[10]=a[10]&b;
assign c[11]=a[11]&b;
assign c[12]=a[12]&b;
assign c[13]=a[13]&b;
assign c[14]=a[14]&b;
assign c[15]=a[15]&b;
assign c[16]=a[16]&b;
assign c[17]=a[17]&b;
assign c[18]=a[18]&b;
assign c[19]=a[19]&b;
assign c[20]=a[20]&b;
assign c[21]=a[21]&b;
assign c[22]=a[22]&b;
assign c[23]=a[23]&b;
assign c[24]=a[24]&b;
assign c[25]=a[25]&b;
assign c[26]=a[26]&b;
assign c[27]=a[27]&b;
assign c[28]=a[28]&b;
assign c[29]=a[29]&b;
assign c[30]=a[30]&b;
assign c[31]=a[31]&b;
endmodule | 0 |
137,872 | data/full_repos/permissive/80602845/FAdd/pipeMult.v | 80,602,845 | pipeMult.v | v | 249 | 95 | [] | [] | [] | [(1, 14), (15, 54), (55, 59), (61, 68), (71, 615), (617, 626), (629, 639), (641, 651), (653, 663), (665, 907)] | null | null | 1: b'%Error: data/full_repos/permissive/80602845/FAdd/pipeMult.v:1: Cannot find include file: csave.v\n`include "csave.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/csave.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/csave.v.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/csave.v.sv\n csave.v\n csave.v.v\n csave.v.sv\n obj_dir/csave.v\n obj_dir/csave.v.v\n obj_dir/csave.v.sv\n%Error: data/full_repos/permissive/80602845/FAdd/pipeMult.v:2: Cannot find include file: partProduct.v\n`include "partProduct.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/80602845/FAdd/pipeMult.v:3: Cannot find include file: prefix.v\n`include "prefix.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80602845/FAdd/pipeMult.v:4: Cannot find include file: dff.v\n`include "dff.v" \n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 300,681 | module | module multi(a,b,out,clk);
input [31:0]a,b;
input clk;
output [63:0]out;
wire [62:0]p[0:31];
wire [31:0]x[31:0];
pgen a1(a,b[0],x[0]);
pgen a2(a,b[1],x[1]);
pgen a3(a,b[2],x[2]);
pgen a4(a,b[3],x[3]);
pgen a5(a,b[4],x[4]);
pgen a6(a,b[5],x[5]);
pgen a7(a,b[6],x[6]);
pgen a8(a,b[7],x[7]);
pgen a9(a,b[8],x[8]);
pgen a10(a,b[9],x[9]);
pgen a11(a,b[10],x[10]);
pgen a12(a,b[11],x[11]);
pgen a13(a,b[12],x[12]);
pgen a14(a,b[13],x[13]);
pgen a15(a,b[14],x[14]);
pgen a16(a,b[15],x[15]);
pgen a17(a,b[16],x[16]);
pgen a18(a,b[17],x[17]);
pgen a19(a,b[18],x[18]);
pgen a20(a,b[19],x[19]);
pgen a21(a,b[20],x[20]);
pgen a22(a,b[21],x[21]);
pgen a23(a,b[22],x[22]);
pgen a24(a,b[23],x[23]);
pgen a25(a,b[24],x[24]);
pgen a26(a,b[25],x[25]);
pgen a27(a,b[26],x[26]);
pgen a28(a,b[27],x[27]);
pgen a29(a,b[28],x[28]);
pgen a30(a,b[29],x[29]);
pgen a31(a,b[30],x[30]);
pgen a32(a,b[31],x[31]);
assign p[0][31:0]=x[0];
assign p[1][32:1]=x[1];
assign p[2][33:2]=x[2];
assign p[3][34:3]=x[3];
assign p[4][35:4]=x[4];
assign p[5][36:5]=x[5];
assign p[6][37:6]=x[6];
assign p[7][38:7]=x[7];
assign p[8][39:8]=x[8];
assign p[9][40:9]=x[9];
assign p[10][41:10]=x[10];
assign p[11][42:11]=x[11];
assign p[12][43:12]=x[12];
assign p[13][44:13]=x[13];
assign p[14][45:14]=x[14];
assign p[15][46:15]=x[15];
assign p[16][47:16]=x[16];
assign p[17][48:17]=x[17];
assign p[18][49:18]=x[18];
assign p[19][50:19]=x[19];
assign p[20][51:20]=x[20];
assign p[21][52:21]=x[21];
assign p[22][53:22]=x[22];
assign p[23][54:23]=x[23];
assign p[24][55:24]=x[24];
assign p[25][56:25]=x[25];
assign p[26][57:26]=x[26];
assign p[27][58:27]=x[27];
assign p[28][59:28]=x[28];
assign p[29][60:29]=x[29];
assign p[30][61:30]=x[30];
assign p[31][62:31]=x[31];
assign p[0][62:32]=0;
assign p[1][62:33]=0;
assign p[2][62:34]=0;
assign p[3][62:35]=0;
assign p[4][62:36]=0;
assign p[5][62:37]=0;
assign p[6][62:38]=0;
assign p[7][62:39]=0;
assign p[8][62:40]=0;
assign p[9][62:41]=0;
assign p[10][62:42]=0;
assign p[11][62:43]=0;
assign p[12][62:44]=0;
assign p[13][62:45]=0;
assign p[14][62:46]=0;
assign p[15][62:47]=0;
assign p[16][62:48]=0;
assign p[17][62:49]=0;
assign p[18][62:50]=0;
assign p[19][62:51]=0;
assign p[20][62:52]=0;
assign p[21][62:53]=0;
assign p[22][62:54]=0;
assign p[23][62:55]=0;
assign p[24][62:56]=0;
assign p[25][62:57]=0;
assign p[26][62:58]=0;
assign p[27][62:59]=0;
assign p[28][62:60]=0;
assign p[29][62:61]=0;
assign p[30][62:62]=0;
assign p[1][0:0]=0;
assign p[2][1:0]=0;
assign p[3][2:0]=0;
assign p[4][3:0]=0;
assign p[5][4:0]=0;
assign p[6][5:0]=0;
assign p[7][6:0]=0;
assign p[8][7:0]=0;
assign p[9][8:0]=0;
assign p[10][9:0]=0;
assign p[11][10:0]=0;
assign p[12][11:0]=0;
assign p[13][12:0]=0;
assign p[14][13:0]=0;
assign p[15][14:0]=0;
assign p[16][15:0]=0;
assign p[17][16:0]=0;
assign p[18][17:0]=0;
assign p[19][18:0]=0;
assign p[20][19:0]=0;
assign p[21][20:0]=0;
assign p[22][21:0]=0;
assign p[23][22:0]=0;
assign p[24][23:0]=0;
assign p[25][24:0]=0;
assign p[26][25:0]=0;
assign p[27][26:0]=0;
assign p[28][27:0]=0;
assign p[29][28:0]=0;
assign p[30][29:0]=0;
assign p[31][30:0]=0;
wire [63:0]p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22;
wire [62:0]P1,P2;
csave l11(p[0],p[1],p[2],p1,p2,clk);
csave l12(p[3],p[4],p[5],p3,p4,clk);
csave l13(p[6],p[7],p[8],p5,p6,clk);
csave l14(p[9],p[10],p[11],p7,p8,clk);
csave l15(p[12],p[13],p[14],p9,p10,clk);
csave l16(p[15],p[16],p[17],p11,p12,clk);
csave l17(p[18],p[19],p[20],p13,p14,clk);
csave l18(p[21],p[22],p[23],p15,p16,clk);
csave l19(p[24],p[25],p[26],p17,p18,clk);
csave l110(p[27],p[28],p[29],p19,p20,clk);
dff_63 c1(P1,clk,p[30]);
dff_63 c2(P2,clk,p[31]);
assign p21[63]=0;
assign p22[63]=0;
assign p21[62:0]=P1;
assign p22[62:0]=P2;
wire [63:0]q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15;
csave l21(p1[62:0],p2[62:0],p3[62:0],q1,q2,clk);
csave l22(p4[62:0],p5[62:0],p6[62:0],q3,q4,clk);
csave l23(p7[62:0],p8[62:0],p9[62:0],q5,q6,clk);
csave l24(p10[62:0],p11[62:0],p12[62:0],q7,q8,clk);
csave l25(p13[62:0],p14[62:0],p15[62:0],q9,q10,clk);
csave l26(p16[62:0],p17[62:0],p18[62:0],q11,q12,clk);
csave l27(p19[62:0],p20[62:0],p21[62:0],q13,q14,clk);
dff_64 d(q15,clk,p22);
wire [63:0]r1,r2,r3,r4,r5,r6,r7,r8,r9,r10;
csave l31(q1[62:0],q2[62:0],q3[62:0],r1,r2,clk);
csave l32(q4[62:0],q5[62:0],q6[62:0],r3,r4,clk);
csave l33(q7[62:0],q8[62:0],q9[62:0],r5,r6,clk);
csave l34(q10[62:0],q11[62:0],q12[62:0],r7,r8,clk);
csave l35(q13[62:0],q14[62:0],q15[62:0],r9,r10,clk);
wire [63:0]s1,s2,s3,s4,s5,s6,s7;
csave l41(r1[62:0],r2[62:0],r3[62:0],s1,s2,clk);
csave l42(r4[62:0],r5[62:0],r6[62:0],s3,s4,clk);
csave l43(r7[62:0],r8[62:0],r9[62:0],s5,s6,clk);
dff_64 n(s7,clk,r10);
wire [63:0]t1,t2,t3,t4,t5;
csave l51(s1[62:0],s2[62:0],s3[62:0],t1,t2,clk);
csave l52(s4[62:0],s5[62:0],s6[62:0],t3,t4,clk);
dff_64 o(t5,clk,s7);
wire [63:0]u1,u2,u3,u4;
csave l61(t1[62:0],t2[62:0],t3[62:0],u1,u2,clk);
dff_64 k(u3,clk,t4);
dff_64 l(u4,clk,t5);
wire [63:0]v1,v2,v3;
csave l71(u1[62:0],u2[62:0],u3[62:0],v1,v2,clk);
dff_64 m(v3,clk,u4);
wire [63:0]w1,w2;
csave l81(v1[62:0],v2[62:0],v3[62:0],w1,w2,clk);
wire [63:0]mult,w11,w12,w13,w14,w15,w21,w22,w23,w24,w25;
wire Cout,cout;
wire [31:0]mul;
prefix pre(w1[31:0],w2[31:0],1'd0,cout,mul[31:0],clk);
wire [31:0] kk , k3k , kkk , kkkk , k4;
dff_32 pp1(kk , clk , mul[31:0]);
dff_32 pp2(kkk , clk , kk);
dff_32 pp3(kkkk , clk , kkk);
dff_32 pp4(k4 , clk , kkkk);
dff_32 pp5(k3k , clk , k4);
assign mult[31:0] = k3k;
dff_64 z(w11,clk,w1);
dff_64 z11(w12,clk,w11);
dff_64 z12(w13,clk,w12);
dff_64 z13(w14,clk,w13);
dff_64 z14(w15,clk,w14);
dff_64 z2(w21,clk,w2);
dff_64 z21(w22,clk,w21);
dff_64 z22(w23,clk,w22);
dff_64 z23(w24,clk,w23);
dff_64 z24(w25,clk,w24);
prefix pre1(w15[63:32],w2[63:32],cout,Cout,mult[63:32],clk);
assign out=mult;
endmodule | module multi(a,b,out,clk); |
input [31:0]a,b;
input clk;
output [63:0]out;
wire [62:0]p[0:31];
wire [31:0]x[31:0];
pgen a1(a,b[0],x[0]);
pgen a2(a,b[1],x[1]);
pgen a3(a,b[2],x[2]);
pgen a4(a,b[3],x[3]);
pgen a5(a,b[4],x[4]);
pgen a6(a,b[5],x[5]);
pgen a7(a,b[6],x[6]);
pgen a8(a,b[7],x[7]);
pgen a9(a,b[8],x[8]);
pgen a10(a,b[9],x[9]);
pgen a11(a,b[10],x[10]);
pgen a12(a,b[11],x[11]);
pgen a13(a,b[12],x[12]);
pgen a14(a,b[13],x[13]);
pgen a15(a,b[14],x[14]);
pgen a16(a,b[15],x[15]);
pgen a17(a,b[16],x[16]);
pgen a18(a,b[17],x[17]);
pgen a19(a,b[18],x[18]);
pgen a20(a,b[19],x[19]);
pgen a21(a,b[20],x[20]);
pgen a22(a,b[21],x[21]);
pgen a23(a,b[22],x[22]);
pgen a24(a,b[23],x[23]);
pgen a25(a,b[24],x[24]);
pgen a26(a,b[25],x[25]);
pgen a27(a,b[26],x[26]);
pgen a28(a,b[27],x[27]);
pgen a29(a,b[28],x[28]);
pgen a30(a,b[29],x[29]);
pgen a31(a,b[30],x[30]);
pgen a32(a,b[31],x[31]);
assign p[0][31:0]=x[0];
assign p[1][32:1]=x[1];
assign p[2][33:2]=x[2];
assign p[3][34:3]=x[3];
assign p[4][35:4]=x[4];
assign p[5][36:5]=x[5];
assign p[6][37:6]=x[6];
assign p[7][38:7]=x[7];
assign p[8][39:8]=x[8];
assign p[9][40:9]=x[9];
assign p[10][41:10]=x[10];
assign p[11][42:11]=x[11];
assign p[12][43:12]=x[12];
assign p[13][44:13]=x[13];
assign p[14][45:14]=x[14];
assign p[15][46:15]=x[15];
assign p[16][47:16]=x[16];
assign p[17][48:17]=x[17];
assign p[18][49:18]=x[18];
assign p[19][50:19]=x[19];
assign p[20][51:20]=x[20];
assign p[21][52:21]=x[21];
assign p[22][53:22]=x[22];
assign p[23][54:23]=x[23];
assign p[24][55:24]=x[24];
assign p[25][56:25]=x[25];
assign p[26][57:26]=x[26];
assign p[27][58:27]=x[27];
assign p[28][59:28]=x[28];
assign p[29][60:29]=x[29];
assign p[30][61:30]=x[30];
assign p[31][62:31]=x[31];
assign p[0][62:32]=0;
assign p[1][62:33]=0;
assign p[2][62:34]=0;
assign p[3][62:35]=0;
assign p[4][62:36]=0;
assign p[5][62:37]=0;
assign p[6][62:38]=0;
assign p[7][62:39]=0;
assign p[8][62:40]=0;
assign p[9][62:41]=0;
assign p[10][62:42]=0;
assign p[11][62:43]=0;
assign p[12][62:44]=0;
assign p[13][62:45]=0;
assign p[14][62:46]=0;
assign p[15][62:47]=0;
assign p[16][62:48]=0;
assign p[17][62:49]=0;
assign p[18][62:50]=0;
assign p[19][62:51]=0;
assign p[20][62:52]=0;
assign p[21][62:53]=0;
assign p[22][62:54]=0;
assign p[23][62:55]=0;
assign p[24][62:56]=0;
assign p[25][62:57]=0;
assign p[26][62:58]=0;
assign p[27][62:59]=0;
assign p[28][62:60]=0;
assign p[29][62:61]=0;
assign p[30][62:62]=0;
assign p[1][0:0]=0;
assign p[2][1:0]=0;
assign p[3][2:0]=0;
assign p[4][3:0]=0;
assign p[5][4:0]=0;
assign p[6][5:0]=0;
assign p[7][6:0]=0;
assign p[8][7:0]=0;
assign p[9][8:0]=0;
assign p[10][9:0]=0;
assign p[11][10:0]=0;
assign p[12][11:0]=0;
assign p[13][12:0]=0;
assign p[14][13:0]=0;
assign p[15][14:0]=0;
assign p[16][15:0]=0;
assign p[17][16:0]=0;
assign p[18][17:0]=0;
assign p[19][18:0]=0;
assign p[20][19:0]=0;
assign p[21][20:0]=0;
assign p[22][21:0]=0;
assign p[23][22:0]=0;
assign p[24][23:0]=0;
assign p[25][24:0]=0;
assign p[26][25:0]=0;
assign p[27][26:0]=0;
assign p[28][27:0]=0;
assign p[29][28:0]=0;
assign p[30][29:0]=0;
assign p[31][30:0]=0;
wire [63:0]p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22;
wire [62:0]P1,P2;
csave l11(p[0],p[1],p[2],p1,p2,clk);
csave l12(p[3],p[4],p[5],p3,p4,clk);
csave l13(p[6],p[7],p[8],p5,p6,clk);
csave l14(p[9],p[10],p[11],p7,p8,clk);
csave l15(p[12],p[13],p[14],p9,p10,clk);
csave l16(p[15],p[16],p[17],p11,p12,clk);
csave l17(p[18],p[19],p[20],p13,p14,clk);
csave l18(p[21],p[22],p[23],p15,p16,clk);
csave l19(p[24],p[25],p[26],p17,p18,clk);
csave l110(p[27],p[28],p[29],p19,p20,clk);
dff_63 c1(P1,clk,p[30]);
dff_63 c2(P2,clk,p[31]);
assign p21[63]=0;
assign p22[63]=0;
assign p21[62:0]=P1;
assign p22[62:0]=P2;
wire [63:0]q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15;
csave l21(p1[62:0],p2[62:0],p3[62:0],q1,q2,clk);
csave l22(p4[62:0],p5[62:0],p6[62:0],q3,q4,clk);
csave l23(p7[62:0],p8[62:0],p9[62:0],q5,q6,clk);
csave l24(p10[62:0],p11[62:0],p12[62:0],q7,q8,clk);
csave l25(p13[62:0],p14[62:0],p15[62:0],q9,q10,clk);
csave l26(p16[62:0],p17[62:0],p18[62:0],q11,q12,clk);
csave l27(p19[62:0],p20[62:0],p21[62:0],q13,q14,clk);
dff_64 d(q15,clk,p22);
wire [63:0]r1,r2,r3,r4,r5,r6,r7,r8,r9,r10;
csave l31(q1[62:0],q2[62:0],q3[62:0],r1,r2,clk);
csave l32(q4[62:0],q5[62:0],q6[62:0],r3,r4,clk);
csave l33(q7[62:0],q8[62:0],q9[62:0],r5,r6,clk);
csave l34(q10[62:0],q11[62:0],q12[62:0],r7,r8,clk);
csave l35(q13[62:0],q14[62:0],q15[62:0],r9,r10,clk);
wire [63:0]s1,s2,s3,s4,s5,s6,s7;
csave l41(r1[62:0],r2[62:0],r3[62:0],s1,s2,clk);
csave l42(r4[62:0],r5[62:0],r6[62:0],s3,s4,clk);
csave l43(r7[62:0],r8[62:0],r9[62:0],s5,s6,clk);
dff_64 n(s7,clk,r10);
wire [63:0]t1,t2,t3,t4,t5;
csave l51(s1[62:0],s2[62:0],s3[62:0],t1,t2,clk);
csave l52(s4[62:0],s5[62:0],s6[62:0],t3,t4,clk);
dff_64 o(t5,clk,s7);
wire [63:0]u1,u2,u3,u4;
csave l61(t1[62:0],t2[62:0],t3[62:0],u1,u2,clk);
dff_64 k(u3,clk,t4);
dff_64 l(u4,clk,t5);
wire [63:0]v1,v2,v3;
csave l71(u1[62:0],u2[62:0],u3[62:0],v1,v2,clk);
dff_64 m(v3,clk,u4);
wire [63:0]w1,w2;
csave l81(v1[62:0],v2[62:0],v3[62:0],w1,w2,clk);
wire [63:0]mult,w11,w12,w13,w14,w15,w21,w22,w23,w24,w25;
wire Cout,cout;
wire [31:0]mul;
prefix pre(w1[31:0],w2[31:0],1'd0,cout,mul[31:0],clk);
wire [31:0] kk , k3k , kkk , kkkk , k4;
dff_32 pp1(kk , clk , mul[31:0]);
dff_32 pp2(kkk , clk , kk);
dff_32 pp3(kkkk , clk , kkk);
dff_32 pp4(k4 , clk , kkkk);
dff_32 pp5(k3k , clk , k4);
assign mult[31:0] = k3k;
dff_64 z(w11,clk,w1);
dff_64 z11(w12,clk,w11);
dff_64 z12(w13,clk,w12);
dff_64 z13(w14,clk,w13);
dff_64 z14(w15,clk,w14);
dff_64 z2(w21,clk,w2);
dff_64 z21(w22,clk,w21);
dff_64 z22(w23,clk,w22);
dff_64 z23(w24,clk,w23);
dff_64 z24(w25,clk,w24);
prefix pre1(w15[63:32],w2[63:32],cout,Cout,mult[63:32],clk);
assign out=mult;
endmodule | 0 |
137,873 | data/full_repos/permissive/80602845/FAdd/prefix.v | 80,602,845 | prefix.v | v | 563 | 56 | [] | [] | [] | [(1, 5), (7, 14), (17, 561)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:49: Cannot find file containing module: 'dff'\n dff f1(l1[0],clk,w1[0]);\n ^~~\n ... Looked in:\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:50: Cannot find file containing module: 'dff'\n dff f2(l1[1],clk,w1[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:51: Cannot find file containing module: 'dff'\n dff f3(l1[2],clk,g[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:52: Cannot find file containing module: 'dff'\n dff f4(l1[3],clk,a[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:53: Cannot find file containing module: 'dff'\n dff f5(l1[4],clk,w2[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:54: Cannot find file containing module: 'dff'\n dff f6(l1[5],clk,w2[2]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:55: Cannot find file containing module: 'dff'\n dff f7(l1[6],clk,g[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:56: Cannot find file containing module: 'dff'\n dff f8(l1[7],clk,a[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:57: Cannot find file containing module: 'dff'\n dff f9(l1[8],clk,w2[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:58: Cannot find file containing module: 'dff'\n dff f10(l1[9],clk,w2[4]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:59: Cannot find file containing module: 'dff'\n dff f11(l1[10],clk,g[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:60: Cannot find file containing module: 'dff'\n dff f12(l1[11],clk,a[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:61: Cannot find file containing module: 'dff'\n dff f13(l1[12],clk,w2[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:62: Cannot find file containing module: 'dff'\n dff f14(l1[13],clk,w2[6]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:63: Cannot find file containing module: 'dff'\n dff f15(l1[14],clk,g[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:64: Cannot find file containing module: 'dff'\n dff f16(l1[15],clk,a[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:65: Cannot find file containing module: 'dff'\n dff f17(l1[16],clk,w2[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:66: Cannot find file containing module: 'dff'\n dff f18(l1[17],clk,w2[8]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:67: Cannot find file containing module: 'dff'\n dff f19(l1[18],clk,g[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:68: Cannot find file containing module: 'dff'\n dff f20(l1[19],clk,a[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:69: Cannot find file containing module: 'dff'\n dff f21(l1[20],clk,w2[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:70: Cannot find file containing module: 'dff'\n dff f22(l1[21],clk,w2[10]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:71: Cannot find file containing module: 'dff'\n dff f23(l1[22],clk,g[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:72: Cannot find file containing module: 'dff'\n dff f24(l1[23],clk,a[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:73: Cannot find file containing module: 'dff'\n dff f25(l1[24],clk,w2[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:74: Cannot find file containing module: 'dff'\n dff f26(l1[25],clk,w2[12]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:75: Cannot find file containing module: 'dff'\n dff f27(l1[26],clk,g[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:76: Cannot find file containing module: 'dff'\n dff f28(l1[27],clk,a[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:77: Cannot find file containing module: 'dff'\n dff f29(l1[28],clk,w2[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:78: Cannot find file containing module: 'dff'\n dff f30(l1[29],clk,w2[14]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:79: Cannot find file containing module: 'dff'\n dff f31(l1[30],clk,g[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:80: Cannot find file containing module: 'dff'\n dff f32(l1[31],clk,a[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:81: Cannot find file containing module: 'dff'\n dff f33(l1[32],clk,w2[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:82: Cannot find file containing module: 'dff'\n dff f34(l1[33],clk,w2[16]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:83: Cannot find file containing module: 'dff'\n dff f35(l1[34],clk,g[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:84: Cannot find file containing module: 'dff'\n dff f36(l1[35],clk,a[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:85: Cannot find file containing module: 'dff'\n dff f37(l1[36],clk,w2[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:86: Cannot find file containing module: 'dff'\n dff f38(l1[37],clk,w2[18]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:87: Cannot find file containing module: 'dff'\n dff f39(l1[38],clk,g[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:88: Cannot find file containing module: 'dff'\n dff f40(l1[39],clk,a[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:89: Cannot find file containing module: 'dff'\n dff f41(l1[40],clk,w2[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:90: Cannot find file containing module: 'dff'\n dff f42(l1[41],clk,w2[20]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:91: Cannot find file containing module: 'dff'\n dff f43(l1[42],clk,g[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:92: Cannot find file containing module: 'dff'\n dff f44(l1[43],clk,a[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:93: Cannot find file containing module: 'dff'\n dff f45(l1[44],clk,w2[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:94: Cannot find file containing module: 'dff'\n dff f46(l1[45],clk,w2[22]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:95: Cannot find file containing module: 'dff'\n dff f47(l1[46],clk,g[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:96: Cannot find file containing module: 'dff'\n dff f48(l1[47],clk,a[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:97: Cannot find file containing module: 'dff'\n dff f49(l1[48],clk,w2[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:98: Cannot find file containing module: 'dff'\n dff f50(l1[49],clk,w2[24]);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 300,682 | module | module dot(gout,gl,al,gr);
output gout;
input gr,gl,al;
assign gout = gl | (al & gr);
endmodule | module dot(gout,gl,al,gr); |
output gout;
input gr,gl,al;
assign gout = gl | (al & gr);
endmodule | 0 |
137,874 | data/full_repos/permissive/80602845/FAdd/prefix.v | 80,602,845 | prefix.v | v | 563 | 56 | [] | [] | [] | [(1, 5), (7, 14), (17, 561)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:49: Cannot find file containing module: 'dff'\n dff f1(l1[0],clk,w1[0]);\n ^~~\n ... Looked in:\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:50: Cannot find file containing module: 'dff'\n dff f2(l1[1],clk,w1[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:51: Cannot find file containing module: 'dff'\n dff f3(l1[2],clk,g[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:52: Cannot find file containing module: 'dff'\n dff f4(l1[3],clk,a[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:53: Cannot find file containing module: 'dff'\n dff f5(l1[4],clk,w2[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:54: Cannot find file containing module: 'dff'\n dff f6(l1[5],clk,w2[2]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:55: Cannot find file containing module: 'dff'\n dff f7(l1[6],clk,g[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:56: Cannot find file containing module: 'dff'\n dff f8(l1[7],clk,a[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:57: Cannot find file containing module: 'dff'\n dff f9(l1[8],clk,w2[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:58: Cannot find file containing module: 'dff'\n dff f10(l1[9],clk,w2[4]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:59: Cannot find file containing module: 'dff'\n dff f11(l1[10],clk,g[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:60: Cannot find file containing module: 'dff'\n dff f12(l1[11],clk,a[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:61: Cannot find file containing module: 'dff'\n dff f13(l1[12],clk,w2[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:62: Cannot find file containing module: 'dff'\n dff f14(l1[13],clk,w2[6]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:63: Cannot find file containing module: 'dff'\n dff f15(l1[14],clk,g[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:64: Cannot find file containing module: 'dff'\n dff f16(l1[15],clk,a[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:65: Cannot find file containing module: 'dff'\n dff f17(l1[16],clk,w2[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:66: Cannot find file containing module: 'dff'\n dff f18(l1[17],clk,w2[8]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:67: Cannot find file containing module: 'dff'\n dff f19(l1[18],clk,g[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:68: Cannot find file containing module: 'dff'\n dff f20(l1[19],clk,a[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:69: Cannot find file containing module: 'dff'\n dff f21(l1[20],clk,w2[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:70: Cannot find file containing module: 'dff'\n dff f22(l1[21],clk,w2[10]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:71: Cannot find file containing module: 'dff'\n dff f23(l1[22],clk,g[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:72: Cannot find file containing module: 'dff'\n dff f24(l1[23],clk,a[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:73: Cannot find file containing module: 'dff'\n dff f25(l1[24],clk,w2[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:74: Cannot find file containing module: 'dff'\n dff f26(l1[25],clk,w2[12]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:75: Cannot find file containing module: 'dff'\n dff f27(l1[26],clk,g[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:76: Cannot find file containing module: 'dff'\n dff f28(l1[27],clk,a[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:77: Cannot find file containing module: 'dff'\n dff f29(l1[28],clk,w2[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:78: Cannot find file containing module: 'dff'\n dff f30(l1[29],clk,w2[14]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:79: Cannot find file containing module: 'dff'\n dff f31(l1[30],clk,g[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:80: Cannot find file containing module: 'dff'\n dff f32(l1[31],clk,a[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:81: Cannot find file containing module: 'dff'\n dff f33(l1[32],clk,w2[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:82: Cannot find file containing module: 'dff'\n dff f34(l1[33],clk,w2[16]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:83: Cannot find file containing module: 'dff'\n dff f35(l1[34],clk,g[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:84: Cannot find file containing module: 'dff'\n dff f36(l1[35],clk,a[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:85: Cannot find file containing module: 'dff'\n dff f37(l1[36],clk,w2[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:86: Cannot find file containing module: 'dff'\n dff f38(l1[37],clk,w2[18]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:87: Cannot find file containing module: 'dff'\n dff f39(l1[38],clk,g[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:88: Cannot find file containing module: 'dff'\n dff f40(l1[39],clk,a[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:89: Cannot find file containing module: 'dff'\n dff f41(l1[40],clk,w2[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:90: Cannot find file containing module: 'dff'\n dff f42(l1[41],clk,w2[20]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:91: Cannot find file containing module: 'dff'\n dff f43(l1[42],clk,g[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:92: Cannot find file containing module: 'dff'\n dff f44(l1[43],clk,a[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:93: Cannot find file containing module: 'dff'\n dff f45(l1[44],clk,w2[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:94: Cannot find file containing module: 'dff'\n dff f46(l1[45],clk,w2[22]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:95: Cannot find file containing module: 'dff'\n dff f47(l1[46],clk,g[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:96: Cannot find file containing module: 'dff'\n dff f48(l1[47],clk,a[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:97: Cannot find file containing module: 'dff'\n dff f49(l1[48],clk,w2[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:98: Cannot find file containing module: 'dff'\n dff f50(l1[49],clk,w2[24]);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 300,682 | module | module circle(gout,aout,gl,al,gr,ar);
output gout,aout;
input gl,al,gr,ar;
assign gout = gl | (al & gr);
assign aout = al & ar;
endmodule | module circle(gout,aout,gl,al,gr,ar); |
output gout,aout;
input gl,al,gr,ar;
assign gout = gl | (al & gr);
assign aout = al & ar;
endmodule | 0 |
137,875 | data/full_repos/permissive/80602845/FAdd/prefix.v | 80,602,845 | prefix.v | v | 563 | 56 | [] | [] | [] | [(1, 5), (7, 14), (17, 561)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:49: Cannot find file containing module: 'dff'\n dff f1(l1[0],clk,w1[0]);\n ^~~\n ... Looked in:\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:50: Cannot find file containing module: 'dff'\n dff f2(l1[1],clk,w1[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:51: Cannot find file containing module: 'dff'\n dff f3(l1[2],clk,g[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:52: Cannot find file containing module: 'dff'\n dff f4(l1[3],clk,a[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:53: Cannot find file containing module: 'dff'\n dff f5(l1[4],clk,w2[1]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:54: Cannot find file containing module: 'dff'\n dff f6(l1[5],clk,w2[2]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:55: Cannot find file containing module: 'dff'\n dff f7(l1[6],clk,g[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:56: Cannot find file containing module: 'dff'\n dff f8(l1[7],clk,a[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:57: Cannot find file containing module: 'dff'\n dff f9(l1[8],clk,w2[3]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:58: Cannot find file containing module: 'dff'\n dff f10(l1[9],clk,w2[4]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:59: Cannot find file containing module: 'dff'\n dff f11(l1[10],clk,g[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:60: Cannot find file containing module: 'dff'\n dff f12(l1[11],clk,a[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:61: Cannot find file containing module: 'dff'\n dff f13(l1[12],clk,w2[5]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:62: Cannot find file containing module: 'dff'\n dff f14(l1[13],clk,w2[6]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:63: Cannot find file containing module: 'dff'\n dff f15(l1[14],clk,g[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:64: Cannot find file containing module: 'dff'\n dff f16(l1[15],clk,a[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:65: Cannot find file containing module: 'dff'\n dff f17(l1[16],clk,w2[7]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:66: Cannot find file containing module: 'dff'\n dff f18(l1[17],clk,w2[8]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:67: Cannot find file containing module: 'dff'\n dff f19(l1[18],clk,g[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:68: Cannot find file containing module: 'dff'\n dff f20(l1[19],clk,a[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:69: Cannot find file containing module: 'dff'\n dff f21(l1[20],clk,w2[9]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:70: Cannot find file containing module: 'dff'\n dff f22(l1[21],clk,w2[10]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:71: Cannot find file containing module: 'dff'\n dff f23(l1[22],clk,g[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:72: Cannot find file containing module: 'dff'\n dff f24(l1[23],clk,a[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:73: Cannot find file containing module: 'dff'\n dff f25(l1[24],clk,w2[11]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:74: Cannot find file containing module: 'dff'\n dff f26(l1[25],clk,w2[12]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:75: Cannot find file containing module: 'dff'\n dff f27(l1[26],clk,g[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:76: Cannot find file containing module: 'dff'\n dff f28(l1[27],clk,a[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:77: Cannot find file containing module: 'dff'\n dff f29(l1[28],clk,w2[13]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:78: Cannot find file containing module: 'dff'\n dff f30(l1[29],clk,w2[14]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:79: Cannot find file containing module: 'dff'\n dff f31(l1[30],clk,g[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:80: Cannot find file containing module: 'dff'\n dff f32(l1[31],clk,a[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:81: Cannot find file containing module: 'dff'\n dff f33(l1[32],clk,w2[15]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:82: Cannot find file containing module: 'dff'\n dff f34(l1[33],clk,w2[16]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:83: Cannot find file containing module: 'dff'\n dff f35(l1[34],clk,g[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:84: Cannot find file containing module: 'dff'\n dff f36(l1[35],clk,a[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:85: Cannot find file containing module: 'dff'\n dff f37(l1[36],clk,w2[17]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:86: Cannot find file containing module: 'dff'\n dff f38(l1[37],clk,w2[18]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:87: Cannot find file containing module: 'dff'\n dff f39(l1[38],clk,g[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:88: Cannot find file containing module: 'dff'\n dff f40(l1[39],clk,a[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:89: Cannot find file containing module: 'dff'\n dff f41(l1[40],clk,w2[19]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:90: Cannot find file containing module: 'dff'\n dff f42(l1[41],clk,w2[20]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:91: Cannot find file containing module: 'dff'\n dff f43(l1[42],clk,g[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:92: Cannot find file containing module: 'dff'\n dff f44(l1[43],clk,a[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:93: Cannot find file containing module: 'dff'\n dff f45(l1[44],clk,w2[21]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:94: Cannot find file containing module: 'dff'\n dff f46(l1[45],clk,w2[22]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:95: Cannot find file containing module: 'dff'\n dff f47(l1[46],clk,g[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:96: Cannot find file containing module: 'dff'\n dff f48(l1[47],clk,a[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:97: Cannot find file containing module: 'dff'\n dff f49(l1[48],clk,w2[23]);\n ^~~\n%Error: data/full_repos/permissive/80602845/FAdd/prefix.v:98: Cannot find file containing module: 'dff'\n dff f50(l1[49],clk,w2[24]);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 300,682 | module | module prefix(x,y,c,cout,s,clk);
input[31:0]x,y;input c,clk;
output[31:0]s;output cout;
wire[31:0]p,g,a,l,p1,p2,p3,p4;
wire[31:0]w1;
wire [100:0]w2;
wire [100:0]l1,l2,l3,l4,l5;
assign p = x ^ y;
assign g = x & y;
assign a = g | p;
assign w1[0]=c;
dot d1(w1[1],g[0],a[0],c);
circle c1(w2[1],w2[2],g[2],a[2],g[1],a[1]);
circle c2(w2[3],w2[4],g[4],a[4],g[3],a[3]);
circle c3(w2[5],w2[6],g[6],a[6],g[5],a[5]);
circle c4(w2[7],w2[8],g[8],a[8],g[7],a[7]);
circle c5(w2[9],w2[10],g[10],a[10],g[9],a[9]);
circle c6(w2[11],w2[12],g[12],a[12],g[11],a[11]);
circle c7(w2[13],w2[14],g[14],a[14],g[13],a[13]);
circle c8(w2[15],w2[16],g[16],a[16],g[15],a[15]);
circle c9(w2[17],w2[18],g[18],a[18],g[17],a[17]);
circle c10(w2[19],w2[20],g[20],a[20],g[19],a[19]);
circle c11(w2[21],w2[22],g[22],a[22],g[21],a[21]);
circle c12(w2[23],w2[24],g[24],a[24],g[23],a[23]);
circle c13(w2[25],w2[26],g[26],a[26],g[25],a[25]);
circle c14(w2[27],w2[28],g[28],a[28],g[27],a[27]);
circle c15(w2[29],w2[30],g[30],a[30],g[29],a[29]);
dff f1(l1[0],clk,w1[0]);
dff f2(l1[1],clk,w1[1]);
dff f3(l1[2],clk,g[1]);
dff f4(l1[3],clk,a[1]);
dff f5(l1[4],clk,w2[1]);
dff f6(l1[5],clk,w2[2]);
dff f7(l1[6],clk,g[3]);
dff f8(l1[7],clk,a[3]);
dff f9(l1[8],clk,w2[3]);
dff f10(l1[9],clk,w2[4]);
dff f11(l1[10],clk,g[5]);
dff f12(l1[11],clk,a[5]);
dff f13(l1[12],clk,w2[5]);
dff f14(l1[13],clk,w2[6]);
dff f15(l1[14],clk,g[7]);
dff f16(l1[15],clk,a[7]);
dff f17(l1[16],clk,w2[7]);
dff f18(l1[17],clk,w2[8]);
dff f19(l1[18],clk,g[9]);
dff f20(l1[19],clk,a[9]);
dff f21(l1[20],clk,w2[9]);
dff f22(l1[21],clk,w2[10]);
dff f23(l1[22],clk,g[11]);
dff f24(l1[23],clk,a[11]);
dff f25(l1[24],clk,w2[11]);
dff f26(l1[25],clk,w2[12]);
dff f27(l1[26],clk,g[13]);
dff f28(l1[27],clk,a[13]);
dff f29(l1[28],clk,w2[13]);
dff f30(l1[29],clk,w2[14]);
dff f31(l1[30],clk,g[15]);
dff f32(l1[31],clk,a[15]);
dff f33(l1[32],clk,w2[15]);
dff f34(l1[33],clk,w2[16]);
dff f35(l1[34],clk,g[17]);
dff f36(l1[35],clk,a[17]);
dff f37(l1[36],clk,w2[17]);
dff f38(l1[37],clk,w2[18]);
dff f39(l1[38],clk,g[19]);
dff f40(l1[39],clk,a[19]);
dff f41(l1[40],clk,w2[19]);
dff f42(l1[41],clk,w2[20]);
dff f43(l1[42],clk,g[21]);
dff f44(l1[43],clk,a[21]);
dff f45(l1[44],clk,w2[21]);
dff f46(l1[45],clk,w2[22]);
dff f47(l1[46],clk,g[23]);
dff f48(l1[47],clk,a[23]);
dff f49(l1[48],clk,w2[23]);
dff f50(l1[49],clk,w2[24]);
dff f51(l1[50],clk,g[25]);
dff f52(l1[51],clk,a[25]);
dff f53(l1[52],clk,w2[25]);
dff f54(l1[53],clk,w2[26]);
dff f55(l1[54],clk,g[27]);
dff f56(l1[55],clk,a[27]);
dff f57(l1[56],clk,w2[27]);
dff f58(l1[57],clk,w2[28]);
dff f59(l1[58],clk,g[29]);
dff f60(l1[59],clk,a[29]);
dff f61(l1[60],clk,w2[29]);
dff f62(l1[61],clk,w2[30]);
dff f63(l1[62],clk,g[31]);
dff f64(l1[63],clk,a[31]);
dff f65(l[0],clk,p[0]);
dff f66(l[1],clk,p[1]);
dff f67(l[2],clk,p[2]);
dff f68(l[3],clk,p[3]);
dff f69(l[4],clk,p[4]);
dff f70(l[5],clk,p[5]);
dff f71(l[6],clk,p[6]);
dff f72(l[7],clk,p[7]);
dff f73(l[8],clk,p[8]);
dff f74(l[9],clk,p[9]);
dff f75(l[10],clk,p[10]);
dff f76(l[11],clk,p[11]);
dff f77(l[12],clk,p[12]);
dff f78(l[13],clk,p[13]);
dff f79(l[14],clk,p[14]);
dff f80(l[15],clk,p[15]);
dff f81(l[16],clk,p[16]);
dff f82(l[17],clk,p[17]);
dff f83(l[18],clk,p[18]);
dff f84(l[19],clk,p[19]);
dff f85(l[20],clk,p[20]);
dff f86(l[21],clk,p[21]);
dff f87(l[22],clk,p[22]);
dff f88(l[23],clk,p[23]);
dff f89(l[24],clk,p[24]);
dff f90(l[25],clk,p[25]);
dff f91(l[26],clk,p[26]);
dff f92(l[27],clk,p[27]);
dff f93(l[28],clk,p[28]);
dff f94(l[29],clk,p[29]);
dff f95(l[30],clk,p[30]);
dff f96(l[31],clk,p[31]);
dot d2(w1[2],l1[2],l1[3],l1[1]);
dot d3(w1[3],l1[4],l1[5],l1[1]);
circle c16(w2[31],w2[32],l1[10],l1[11],l1[8],l1[9]);
circle c17(w2[33],w2[34],l1[12],l1[13],l1[8],l1[9]);
circle c18(w2[35],w2[36],l1[18],l1[19],l1[16],l1[17]);
circle c19(w2[37],w2[38],l1[20],l1[21],l1[16],l1[17]);
circle c20(w2[39],w2[40],l1[26],l1[27],l1[24],l1[25]);
circle c21(w2[41],w2[42],l1[28],l1[29],l1[24],l1[25]);
circle c22(w2[43],w2[44],l1[34],l1[35],l1[32],l1[33]);
circle c23(w2[45],w2[46],l1[36],l1[37],l1[32],l1[33]);
circle c24(w2[47],w2[48],l1[42],l1[43],l1[40],l1[41]);
circle c25(w2[49],w2[50],l1[44],l1[45],l1[40],l1[41]);
circle c26(w2[51],w2[52],l1[50],l1[51],l1[48],l1[49]);
circle c27(w2[53],w2[54],l1[52],l1[53],l1[48],l1[49]);
circle c28(w2[55],w2[56],l1[58],l1[59],l1[56],l1[57]);
circle c29(w2[57],w2[58],l1[60],l1[61],l1[56],l1[57]);
dff b1(l2[0],clk,l1[0]);
dff b2(l2[1],clk,l1[1]);
dff b3(l2[2],clk,w1[2]);
dff b4(l2[3],clk,w1[3]);
dff b5(l2[4],clk,l1[6]);
dff b6(l2[5],clk,l1[7]);
dff b7(l2[6],clk,l1[8]);
dff b8(l2[7],clk,l1[9]);
dff b9(l2[8],clk,w2[31]);
dff b10(l2[9],clk,w2[32]);
dff b11(l2[10],clk,w2[33]);
dff b12(l2[11],clk,w2[34]);
dff b13(l2[12],clk,l1[14]);
dff b14(l2[13],clk,l1[15]);
dff b15(l2[14],clk,l1[16]);
dff b16(l2[15],clk,l1[17]);
dff b17(l2[16],clk,w2[35]);
dff b18(l2[17],clk,w2[36]);
dff b19(l2[18],clk,w2[37]);
dff b20(l2[19],clk,w2[38]);
dff b21(l2[20],clk,l1[22]);
dff b22(l2[21],clk,l1[23]);
dff b23(l2[22],clk,l1[24]);
dff b24(l2[23],clk,l1[25]);
dff b25(l2[24],clk,w2[39]);
dff b26(l2[25],clk,w2[40]);
dff b27(l2[26],clk,w2[41]);
dff b28(l2[27],clk,w2[42]);
dff b29(l2[28],clk,l1[30]);
dff b30(l2[29],clk,l1[31]);
dff b31(l2[30],clk,l1[32]);
dff b32(l2[31],clk,l1[33]);
dff b33(l2[32],clk,w2[43]);
dff b34(l2[33],clk,w2[44]);
dff b35(l2[34],clk,w2[45]);
dff b36(l2[35],clk,w2[46]);
dff b37(l2[36],clk,l1[38]);
dff b38(l2[37],clk,l1[39]);
dff b39(l2[38],clk,l1[40]);
dff b40(l2[39],clk,l1[41]);
dff b41(l2[40],clk,w2[47]);
dff b42(l2[41],clk,w2[48]);
dff b43(l2[42],clk,w2[49]);
dff b44(l2[43],clk,w2[50]);
dff b45(l2[44],clk,l1[46]);
dff b46(l2[45],clk,l1[47]);
dff b47(l2[46],clk,l1[48]);
dff b48(l2[47],clk,l1[49]);
dff b49(l2[48],clk,w2[51]);
dff b50(l2[49],clk,w2[52]);
dff b51(l2[50],clk,w2[53]);
dff b52(l2[51],clk,w2[54]);
dff b53(l2[52],clk,l1[54]);
dff b54(l2[53],clk,l1[55]);
dff b55(l2[54],clk,l1[56]);
dff b56(l2[55],clk,l1[57]);
dff b57(l2[56],clk,w2[55]);
dff b58(l2[57],clk,w2[56]);
dff b59(l2[58],clk,w2[57]);
dff b60(l2[59],clk,w2[58]);
dff b61(l2[60],clk,l1[62]);
dff b62(l2[61],clk,l1[63]);
dff b65 (p1[0],clk,l[0]);
dff b66 (p1[1],clk,l[1]);
dff b67 (p1[2],clk,l[2]);
dff b68 (p1[3],clk,l[3]);
dff b69 (p1[4],clk,l[4]);
dff b70 (p1[5],clk,l[5]);
dff b71 (p1[6],clk,l[6]);
dff b72 (p1[7],clk,l[7]);
dff b73 (p1[8],clk,l[8]);
dff b74 (p1[9],clk,l[9]);
dff b75 (p1[10],clk,l[10]);
dff b76 (p1[11],clk,l[11]);
dff b77 (p1[12],clk,l[12]);
dff b78 (p1[13],clk,l[13]);
dff b79 (p1[14],clk,l[14]);
dff b80 (p1[15],clk,l[15]);
dff b81 (p1[16],clk,l[16]);
dff b82 (p1[17],clk,l[17]);
dff b83 (p1[18],clk,l[18]);
dff b84 (p1[19],clk,l[19]);
dff b85 (p1[20],clk,l[20]);
dff b86 (p1[21],clk,l[21]);
dff b87 (p1[22],clk,l[22]);
dff b88 (p1[23],clk,l[23]);
dff b89 (p1[24],clk,l[24]);
dff b90 (p1[25],clk,l[25]);
dff b91 (p1[26],clk,l[26]);
dff b92 (p1[27],clk,l[27]);
dff b93 (p1[28],clk,l[28]);
dff b94 (p1[29],clk,l[29]);
dff b95 (p1[30],clk,l[30]);
dff b96 (p1[31],clk,l[31]);
dot d4(w1[4],l2[4],l2[5],l2[3]);
dot d5(w1[5],l2[6],l2[7],l2[3]);
dot d6(w1[6],l2[8],l2[9],l2[3]);
dot d7(w1[7],l2[10],l2[11],l2[3]);
circle c30(w2[59],w2[60],l2[20],l2[21],l2[18],l2[19]);
circle c31(w2[61],w2[62],l2[22],l2[23],l2[18],l2[19]);
circle c32(w2[63],w2[64],l2[24],l2[25],l2[18],l2[19]);
circle c33(w2[65],w2[66],l2[26],l2[27],l2[18],l2[19]);
circle c34(w2[67],w2[68],l2[36],l2[37],l2[34],l2[35]);
circle c35(w2[69],w2[70],l2[38],l2[39],l2[34],l2[35]);
circle c36(w2[71],w2[72],l2[40],l2[41],l2[34],l2[35]);
circle c37(w2[73],w2[74],l2[42],l2[43],l2[34],l2[35]);
circle c38(w2[75],w2[76],l2[52],l2[53],l2[50],l2[51]);
circle c39(w2[77],w2[78],l2[54],l2[55],l2[50],l2[51]);
circle c40(w2[79],w2[80],l2[56],l2[57],l2[50],l2[51]);
circle c41(w2[81],w2[82],l2[58],l2[59],l2[50],l2[51]);
dff m1(l3[0],clk,l2[0]);
dff m2(l3[1],clk,l2[1]);
dff m3(l3[2],clk,l2[2]);
dff m4(l3[3],clk,l2[3]);
dff m5(l3[4],clk,w1[4]);
dff m6(l3[5],clk,w1[5]);
dff m7(l3[6],clk,w1[6]);
dff m8(l3[7],clk,w1[7]);
dff m9(l3[8],clk,l2[12]);
dff m10(l3[9],clk,l2[13]);
dff m11(l3[10],clk,l2[14]);
dff m12(l3[11],clk,l2[15]);
dff m13(l3[12],clk,l2[16]);
dff m14(l3[13],clk,l2[17]);
dff m15(l3[14],clk,l2[18]);
dff m16(l3[15],clk,l2[19]);
dff m17(l3[16],clk,w2[59]);
dff m18(l3[17],clk,w2[60]);
dff m19(l3[18],clk,w2[61]);
dff m20(l3[19],clk,w2[62]);
dff m21(l3[20],clk,w2[63]);
dff m22(l3[21],clk,w2[64]);
dff m23(l3[22],clk,w2[65]);
dff m24(l3[23],clk,w2[66]);
dff m25(l3[24],clk,l2[28]);
dff m26(l3[25],clk,l2[29]);
dff m27(l3[26],clk,l2[30]);
dff m28(l3[27],clk,l2[31]);
dff m29(l3[28],clk,l2[32]);
dff m30(l3[29],clk,l2[33]);
dff m31(l3[30],clk,l2[34]);
dff m32(l3[31],clk,l2[35]);
dff m33(l3[32],clk,w2[67]);
dff m34(l3[33],clk,w2[68]);
dff m35(l3[34],clk,w2[69]);
dff m36(l3[35],clk,w2[70]);
dff m37(l3[36],clk,w2[71]);
dff m38(l3[37],clk,w2[72]);
dff m39(l3[38],clk,w2[73]);
dff m40(l3[39],clk,w2[74]);
dff m41(l3[40],clk,l2[44]);
dff m42(l3[41],clk,l2[45]);
dff m43(l3[42],clk,l2[46]);
dff m44(l3[43],clk,l2[47]);
dff m45(l3[44],clk,l2[48]);
dff m46(l3[45],clk,l2[49]);
dff m47(l3[46],clk,l2[50]);
dff m48(l3[47],clk,l2[51]);
dff m49(l3[48],clk,w2[75]);
dff m50(l3[49],clk,w2[76]);
dff m51(l3[50],clk,w2[77]);
dff m52(l3[51],clk,w2[78]);
dff m53(l3[52],clk,w2[79]);
dff m54(l3[53],clk,w2[80]);
dff m55(l3[54],clk,w2[81]);
dff m56(l3[56],clk,w2[82]);
dff m57(l3[56],clk,l2[60]);
dff m58(l3[57],clk,l2[61]);
dff m65 (p2[0],clk,p1[0]);
dff m66 (p2[1],clk,p1[1]);
dff m67 (p2[2],clk,p1[2]);
dff m68 (p2[3],clk,p1[3]);
dff m69 (p2[4],clk,p1[4]);
dff m70 (p2[5],clk,p1[5]);
dff m71 (p2[6],clk,p1[6]);
dff m72 (p2[7],clk,p1[7]);
dff m73 (p2[8],clk,p1[8]);
dff m74 (p2[9],clk,p1[9]);
dff m75 (p2[10],clk,p1[10]);
dff m76 (p2[11],clk,p1[11]);
dff m77 (p2[12],clk,p1[12]);
dff m78 (p2[13],clk,p1[13]);
dff m79 (p2[14],clk,p1[14]);
dff m80 (p2[15],clk,p1[15]);
dff m81 (p2[16],clk,p1[16]);
dff m82 (p2[17],clk,p1[17]);
dff m83 (p2[18],clk,p1[18]);
dff m84 (p2[19],clk,p1[19]);
dff m85 (p2[20],clk,p1[20]);
dff m86 (p2[21],clk,p1[21]);
dff m87 (p2[22],clk,p1[22]);
dff m88 (p2[23],clk,p1[23]);
dff m89 (p2[24],clk,p1[24]);
dff m90 (p2[25],clk,p1[25]);
dff m91 (p2[26],clk,p1[26]);
dff m92 (p2[27],clk,p1[27]);
dff m93 (p2[28],clk,p1[28]);
dff m94 (p2[29],clk,p1[29]);
dff m95 (p2[30],clk,p1[30]);
dff m96 (p2[31],clk,p1[31]);
dot d8(w1[8],l3[8],l3[9],l3[7]);
dot d9(w1[9],l3[10],l3[11],l3[7]);
dot d10(w1[10],l3[12],l3[13],l3[7]);
dot d11(w1[11],l3[14],l3[15],l3[7]);
dot d12(w1[12],l3[16],l3[17],l3[7]);
dot d13(w1[13],l3[18],l3[19],l3[7]);
dot d14(w1[14],l3[20],l3[21],l3[7]);
dot d15(w1[15],l3[22],l3[23],l3[7]);
circle c42(w2[83],w2[84],l3[40],l3[41],l3[38],l3[39]);
circle c43(w2[85],w2[86],l3[42],l3[43],l3[38],l3[39]);
circle c44(w2[87],w2[88],l3[44],l3[45],l3[38],l3[39]);
circle c45(w2[89],w2[90],l3[46],l3[47],l3[38],l3[39]);
circle c46(w2[91],w2[92],l3[48],l3[49],l3[38],l3[39]);
circle c47(w2[93],w2[94],l3[50],l3[51],l3[38],l3[39]);
circle c48(w2[95],w2[96],l3[52],l3[53],l3[38],l3[39]);
circle c49(w2[97],w2[98],l3[54],l3[55],l3[38],l3[39]);
dff z1(l4[0],clk,l3[0]);
dff z2(l4[1],clk,l3[1]);
dff z3(l4[2],clk,l3[2]);
dff z4(l4[3],clk,l3[3]);
dff z5(l4[4],clk,l3[4]);
dff z6(l4[5],clk,l3[5]);
dff z7(l4[6],clk,l3[6]);
dff z8(l4[7],clk,l3[7]);
dff z9(l4[8],clk,w1[8]);
dff z10(l4[9],clk,w1[9]);
dff z11(l4[10],clk,w1[10]);
dff z12(l4[11],clk,w1[11]);
dff z13(l4[12],clk,w1[12]);
dff z14(l4[13],clk,w1[13]);
dff z15(l4[14],clk,w1[14]);
dff z16(l4[15],clk,w1[15]);
dff z17(l4[16],clk,l3[24]);
dff z18(l4[17],clk,l3[25]);
dff z19(l4[18],clk,l3[26]);
dff z20(l4[19],clk,l3[27]);
dff z21(l4[20],clk,l3[28]);
dff z22(l4[21],clk,l3[29]);
dff z23(l4[22],clk,l3[30]);
dff z24(l4[23],clk,l3[31]);
dff z25(l4[24],clk,l3[32]);
dff z26(l4[25],clk,l3[33]);
dff z27(l4[26],clk,l3[34]);
dff z28(l4[27],clk,l3[35]);
dff z29(l4[28],clk,l3[36]);
dff z30(l4[29],clk,l3[37]);
dff z31(l4[30],clk,l3[38]);
dff z32(l4[31],clk,l3[39]);
dff z33(l4[32],clk,w2[83]);
dff z34(l4[33],clk,w2[84]);
dff z35(l4[34],clk,w2[85]);
dff z36(l4[35],clk,w2[86]);
dff z37(l4[36],clk,w2[87]);
dff z38(l4[37],clk,w2[88]);
dff z39(l4[38],clk,w2[89]);
dff z40(l4[39],clk,w2[90]);
dff z41(l4[40],clk,w2[91]);
dff z42(l4[41],clk,w2[92]);
dff z43(l4[42],clk,w2[93]);
dff z44(l4[43],clk,w2[94]);
dff z45(l4[44],clk,w2[95]);
dff z46(l4[45],clk,w2[96]);
dff z47(l4[46],clk,w2[97]);
dff z48(l4[47],clk,w2[98]);
dff z49(l4[48],clk,l3[56]);
dff z50(l4[49],clk,l3[57]);
dff n65 (p3[0],clk,p2[0]);
dff n66 (p3[1],clk,p2[1]);
dff n67 (p3[2],clk,p2[2]);
dff n68 (p3[3],clk,p2[3]);
dff n69 (p3[4],clk,p2[4]);
dff n70 (p3[5],clk,p2[5]);
dff n71 (p3[6],clk,p2[6]);
dff n72 (p3[7],clk,p2[7]);
dff n73 (p3[8],clk,p2[8]);
dff n74 (p3[9],clk,p2[9]);
dff n75 (p3[10],clk,p2[10]);
dff n76 (p3[11],clk,p2[11]);
dff n77 (p3[12],clk,p2[12]);
dff n78 (p3[13],clk,p2[13]);
dff n79 (p3[14],clk,p2[14]);
dff n80 (p3[15],clk,p2[15]);
dff n81 (p3[16],clk,p2[16]);
dff n82 (p3[17],clk,p2[17]);
dff n83 (p3[18],clk,p2[18]);
dff n84 (p3[19],clk,p2[19]);
dff n85 (p3[20],clk,p2[20]);
dff n86 (p3[21],clk,p2[21]);
dff n87 (p3[22],clk,p2[22]);
dff n88 (p3[23],clk,p2[23]);
dff n89 (p3[24],clk,p2[24]);
dff n90 (p3[25],clk,p2[25]);
dff n91 (p3[26],clk,p2[26]);
dff n92 (p3[27],clk,p2[27]);
dff n93 (p3[28],clk,p2[28]);
dff n94 (p3[29],clk,p2[29]);
dff n95 (p3[30],clk,p2[30]);
dff n96 (p3[31],clk,p2[31]);
dot d16(w1[16],l4[16],l4[17],l4[15]);
dot d17(w1[17],l4[18],l4[19],l4[15]);
dot d18(w1[18],l4[20],l4[21],l4[15]);
dot d19(w1[19],l4[22],l4[23],l4[15]);
dot d20(w1[20],l4[24],l4[25],l4[15]);
dot d21(w1[21],l4[26],l4[27],l4[15]);
dot d22(w1[22],l4[28],l4[29],l4[15]);
dot d23(w1[23],l4[30],l4[31],l4[15]);
dot d24(w1[24],l4[32],l4[33],l4[15]);
dot d25(w1[25],l4[34],l4[35],l4[15]);
dot d26(w1[26],l4[36],l4[37],l4[15]);
dot d27(w1[27],l4[38],l4[39],l4[15]);
dot d28(w1[28],l4[40],l4[41],l4[15]);
dot d29(w1[29],l4[42],l4[43],l4[15]);
dot d30(w1[30],l4[44],l4[45],l4[15]);
dot d31(w1[31],l4[46],l4[47],l4[15]);
dff q1(l5[0],clk,l4[0]);
dff q2(l5[1],clk,l4[1]);
dff q3(l5[2],clk,l4[2]);
dff q4(l5[3],clk,l4[3]);
dff q5(l5[4],clk,l4[4]);
dff q6(l5[5],clk,l4[5]);
dff q7(l5[6],clk,l4[6]);
dff q8(l5[7],clk,l4[7]);
dff q9(l5[8],clk,l4[8]);
dff q10(l5[9],clk,l4[9]);
dff q11(l5[10],clk,l4[10]);
dff q12(l5[11],clk,l4[11]);
dff q13(l5[12],clk,l4[12]);
dff q14(l5[13],clk,l4[13]);
dff q15(l5[14],clk,l4[14]);
dff q16(l5[15],clk,l4[15]);
dff q17(l5[16],clk,w1[16]);
dff q18(l5[17],clk,w1[17]);
dff q19(l5[18],clk,w1[18]);
dff q20(l5[19],clk,w1[19]);
dff q21(l5[20],clk,w1[20]);
dff q22(l5[21],clk,w1[21]);
dff q23(l5[22],clk,w1[22]);
dff q24(l5[23],clk,w1[23]);
dff q25(l5[24],clk,w1[24]);
dff q26(l5[25],clk,w1[25]);
dff q27(l5[26],clk,w1[26]);
dff q28(l5[27],clk,w1[27]);
dff q29(l5[28],clk,w1[28]);
dff q30(l5[29],clk,w1[29]);
dff q31(l5[30],clk,w1[30]);
dff q32(l5[31],clk,w1[31]);
dff q33(l5[32],clk,l4[48]);
dff q34(l5[33],clk,l4[49]);
dff z65 (p4[0],clk,p3[0]);
dff z66 (p4[1],clk,p3[1]);
dff z67 (p4[2],clk,p3[2]);
dff z68 (p4[3],clk,p3[3]);
dff z69 (p4[4],clk,p3[4]);
dff z70 (p4[5],clk,p3[5]);
dff z71 (p4[6],clk,p3[6]);
dff z72 (p4[7],clk,p3[7]);
dff z73 (p4[8],clk,p3[8]);
dff z74 (p4[9],clk,p3[9]);
dff z75 (p4[10],clk,p3[10]);
dff z76 (p4[11],clk,p3[11]);
dff z77 (p4[12],clk,p3[12]);
dff z78 (p4[13],clk,p3[13]);
dff z79 (p4[14],clk,p3[14]);
dff z80 (p4[15],clk,p3[15]);
dff z81 (p4[16],clk,p3[16]);
dff z82 (p4[17],clk,p3[17]);
dff z83 (p4[18],clk,p3[18]);
dff z84 (p4[19],clk,p3[19]);
dff z85 (p4[20],clk,p3[20]);
dff z86 (p4[21],clk,p3[21]);
dff z87 (p4[22],clk,p3[22]);
dff z88 (p4[23],clk,p3[23]);
dff z89 (p4[24],clk,p3[24]);
dff z90 (p4[25],clk,p3[25]);
dff z91 (p4[26],clk,p3[26]);
dff z92 (p4[27],clk,p3[27]);
dff z93 (p4[28],clk,p3[28]);
dff z94 (p4[29],clk,p3[29]);
dff z95 (p4[30],clk,p3[30]);
dff z96 (p4[31],clk,p3[31]);
dot d32(cout,l5[32],l5[33],l5[31]);
assign s = p4[31:0] ^ l5[31:0];
endmodule | module prefix(x,y,c,cout,s,clk); |
input[31:0]x,y;input c,clk;
output[31:0]s;output cout;
wire[31:0]p,g,a,l,p1,p2,p3,p4;
wire[31:0]w1;
wire [100:0]w2;
wire [100:0]l1,l2,l3,l4,l5;
assign p = x ^ y;
assign g = x & y;
assign a = g | p;
assign w1[0]=c;
dot d1(w1[1],g[0],a[0],c);
circle c1(w2[1],w2[2],g[2],a[2],g[1],a[1]);
circle c2(w2[3],w2[4],g[4],a[4],g[3],a[3]);
circle c3(w2[5],w2[6],g[6],a[6],g[5],a[5]);
circle c4(w2[7],w2[8],g[8],a[8],g[7],a[7]);
circle c5(w2[9],w2[10],g[10],a[10],g[9],a[9]);
circle c6(w2[11],w2[12],g[12],a[12],g[11],a[11]);
circle c7(w2[13],w2[14],g[14],a[14],g[13],a[13]);
circle c8(w2[15],w2[16],g[16],a[16],g[15],a[15]);
circle c9(w2[17],w2[18],g[18],a[18],g[17],a[17]);
circle c10(w2[19],w2[20],g[20],a[20],g[19],a[19]);
circle c11(w2[21],w2[22],g[22],a[22],g[21],a[21]);
circle c12(w2[23],w2[24],g[24],a[24],g[23],a[23]);
circle c13(w2[25],w2[26],g[26],a[26],g[25],a[25]);
circle c14(w2[27],w2[28],g[28],a[28],g[27],a[27]);
circle c15(w2[29],w2[30],g[30],a[30],g[29],a[29]);
dff f1(l1[0],clk,w1[0]);
dff f2(l1[1],clk,w1[1]);
dff f3(l1[2],clk,g[1]);
dff f4(l1[3],clk,a[1]);
dff f5(l1[4],clk,w2[1]);
dff f6(l1[5],clk,w2[2]);
dff f7(l1[6],clk,g[3]);
dff f8(l1[7],clk,a[3]);
dff f9(l1[8],clk,w2[3]);
dff f10(l1[9],clk,w2[4]);
dff f11(l1[10],clk,g[5]);
dff f12(l1[11],clk,a[5]);
dff f13(l1[12],clk,w2[5]);
dff f14(l1[13],clk,w2[6]);
dff f15(l1[14],clk,g[7]);
dff f16(l1[15],clk,a[7]);
dff f17(l1[16],clk,w2[7]);
dff f18(l1[17],clk,w2[8]);
dff f19(l1[18],clk,g[9]);
dff f20(l1[19],clk,a[9]);
dff f21(l1[20],clk,w2[9]);
dff f22(l1[21],clk,w2[10]);
dff f23(l1[22],clk,g[11]);
dff f24(l1[23],clk,a[11]);
dff f25(l1[24],clk,w2[11]);
dff f26(l1[25],clk,w2[12]);
dff f27(l1[26],clk,g[13]);
dff f28(l1[27],clk,a[13]);
dff f29(l1[28],clk,w2[13]);
dff f30(l1[29],clk,w2[14]);
dff f31(l1[30],clk,g[15]);
dff f32(l1[31],clk,a[15]);
dff f33(l1[32],clk,w2[15]);
dff f34(l1[33],clk,w2[16]);
dff f35(l1[34],clk,g[17]);
dff f36(l1[35],clk,a[17]);
dff f37(l1[36],clk,w2[17]);
dff f38(l1[37],clk,w2[18]);
dff f39(l1[38],clk,g[19]);
dff f40(l1[39],clk,a[19]);
dff f41(l1[40],clk,w2[19]);
dff f42(l1[41],clk,w2[20]);
dff f43(l1[42],clk,g[21]);
dff f44(l1[43],clk,a[21]);
dff f45(l1[44],clk,w2[21]);
dff f46(l1[45],clk,w2[22]);
dff f47(l1[46],clk,g[23]);
dff f48(l1[47],clk,a[23]);
dff f49(l1[48],clk,w2[23]);
dff f50(l1[49],clk,w2[24]);
dff f51(l1[50],clk,g[25]);
dff f52(l1[51],clk,a[25]);
dff f53(l1[52],clk,w2[25]);
dff f54(l1[53],clk,w2[26]);
dff f55(l1[54],clk,g[27]);
dff f56(l1[55],clk,a[27]);
dff f57(l1[56],clk,w2[27]);
dff f58(l1[57],clk,w2[28]);
dff f59(l1[58],clk,g[29]);
dff f60(l1[59],clk,a[29]);
dff f61(l1[60],clk,w2[29]);
dff f62(l1[61],clk,w2[30]);
dff f63(l1[62],clk,g[31]);
dff f64(l1[63],clk,a[31]);
dff f65(l[0],clk,p[0]);
dff f66(l[1],clk,p[1]);
dff f67(l[2],clk,p[2]);
dff f68(l[3],clk,p[3]);
dff f69(l[4],clk,p[4]);
dff f70(l[5],clk,p[5]);
dff f71(l[6],clk,p[6]);
dff f72(l[7],clk,p[7]);
dff f73(l[8],clk,p[8]);
dff f74(l[9],clk,p[9]);
dff f75(l[10],clk,p[10]);
dff f76(l[11],clk,p[11]);
dff f77(l[12],clk,p[12]);
dff f78(l[13],clk,p[13]);
dff f79(l[14],clk,p[14]);
dff f80(l[15],clk,p[15]);
dff f81(l[16],clk,p[16]);
dff f82(l[17],clk,p[17]);
dff f83(l[18],clk,p[18]);
dff f84(l[19],clk,p[19]);
dff f85(l[20],clk,p[20]);
dff f86(l[21],clk,p[21]);
dff f87(l[22],clk,p[22]);
dff f88(l[23],clk,p[23]);
dff f89(l[24],clk,p[24]);
dff f90(l[25],clk,p[25]);
dff f91(l[26],clk,p[26]);
dff f92(l[27],clk,p[27]);
dff f93(l[28],clk,p[28]);
dff f94(l[29],clk,p[29]);
dff f95(l[30],clk,p[30]);
dff f96(l[31],clk,p[31]);
dot d2(w1[2],l1[2],l1[3],l1[1]);
dot d3(w1[3],l1[4],l1[5],l1[1]);
circle c16(w2[31],w2[32],l1[10],l1[11],l1[8],l1[9]);
circle c17(w2[33],w2[34],l1[12],l1[13],l1[8],l1[9]);
circle c18(w2[35],w2[36],l1[18],l1[19],l1[16],l1[17]);
circle c19(w2[37],w2[38],l1[20],l1[21],l1[16],l1[17]);
circle c20(w2[39],w2[40],l1[26],l1[27],l1[24],l1[25]);
circle c21(w2[41],w2[42],l1[28],l1[29],l1[24],l1[25]);
circle c22(w2[43],w2[44],l1[34],l1[35],l1[32],l1[33]);
circle c23(w2[45],w2[46],l1[36],l1[37],l1[32],l1[33]);
circle c24(w2[47],w2[48],l1[42],l1[43],l1[40],l1[41]);
circle c25(w2[49],w2[50],l1[44],l1[45],l1[40],l1[41]);
circle c26(w2[51],w2[52],l1[50],l1[51],l1[48],l1[49]);
circle c27(w2[53],w2[54],l1[52],l1[53],l1[48],l1[49]);
circle c28(w2[55],w2[56],l1[58],l1[59],l1[56],l1[57]);
circle c29(w2[57],w2[58],l1[60],l1[61],l1[56],l1[57]);
dff b1(l2[0],clk,l1[0]);
dff b2(l2[1],clk,l1[1]);
dff b3(l2[2],clk,w1[2]);
dff b4(l2[3],clk,w1[3]);
dff b5(l2[4],clk,l1[6]);
dff b6(l2[5],clk,l1[7]);
dff b7(l2[6],clk,l1[8]);
dff b8(l2[7],clk,l1[9]);
dff b9(l2[8],clk,w2[31]);
dff b10(l2[9],clk,w2[32]);
dff b11(l2[10],clk,w2[33]);
dff b12(l2[11],clk,w2[34]);
dff b13(l2[12],clk,l1[14]);
dff b14(l2[13],clk,l1[15]);
dff b15(l2[14],clk,l1[16]);
dff b16(l2[15],clk,l1[17]);
dff b17(l2[16],clk,w2[35]);
dff b18(l2[17],clk,w2[36]);
dff b19(l2[18],clk,w2[37]);
dff b20(l2[19],clk,w2[38]);
dff b21(l2[20],clk,l1[22]);
dff b22(l2[21],clk,l1[23]);
dff b23(l2[22],clk,l1[24]);
dff b24(l2[23],clk,l1[25]);
dff b25(l2[24],clk,w2[39]);
dff b26(l2[25],clk,w2[40]);
dff b27(l2[26],clk,w2[41]);
dff b28(l2[27],clk,w2[42]);
dff b29(l2[28],clk,l1[30]);
dff b30(l2[29],clk,l1[31]);
dff b31(l2[30],clk,l1[32]);
dff b32(l2[31],clk,l1[33]);
dff b33(l2[32],clk,w2[43]);
dff b34(l2[33],clk,w2[44]);
dff b35(l2[34],clk,w2[45]);
dff b36(l2[35],clk,w2[46]);
dff b37(l2[36],clk,l1[38]);
dff b38(l2[37],clk,l1[39]);
dff b39(l2[38],clk,l1[40]);
dff b40(l2[39],clk,l1[41]);
dff b41(l2[40],clk,w2[47]);
dff b42(l2[41],clk,w2[48]);
dff b43(l2[42],clk,w2[49]);
dff b44(l2[43],clk,w2[50]);
dff b45(l2[44],clk,l1[46]);
dff b46(l2[45],clk,l1[47]);
dff b47(l2[46],clk,l1[48]);
dff b48(l2[47],clk,l1[49]);
dff b49(l2[48],clk,w2[51]);
dff b50(l2[49],clk,w2[52]);
dff b51(l2[50],clk,w2[53]);
dff b52(l2[51],clk,w2[54]);
dff b53(l2[52],clk,l1[54]);
dff b54(l2[53],clk,l1[55]);
dff b55(l2[54],clk,l1[56]);
dff b56(l2[55],clk,l1[57]);
dff b57(l2[56],clk,w2[55]);
dff b58(l2[57],clk,w2[56]);
dff b59(l2[58],clk,w2[57]);
dff b60(l2[59],clk,w2[58]);
dff b61(l2[60],clk,l1[62]);
dff b62(l2[61],clk,l1[63]);
dff b65 (p1[0],clk,l[0]);
dff b66 (p1[1],clk,l[1]);
dff b67 (p1[2],clk,l[2]);
dff b68 (p1[3],clk,l[3]);
dff b69 (p1[4],clk,l[4]);
dff b70 (p1[5],clk,l[5]);
dff b71 (p1[6],clk,l[6]);
dff b72 (p1[7],clk,l[7]);
dff b73 (p1[8],clk,l[8]);
dff b74 (p1[9],clk,l[9]);
dff b75 (p1[10],clk,l[10]);
dff b76 (p1[11],clk,l[11]);
dff b77 (p1[12],clk,l[12]);
dff b78 (p1[13],clk,l[13]);
dff b79 (p1[14],clk,l[14]);
dff b80 (p1[15],clk,l[15]);
dff b81 (p1[16],clk,l[16]);
dff b82 (p1[17],clk,l[17]);
dff b83 (p1[18],clk,l[18]);
dff b84 (p1[19],clk,l[19]);
dff b85 (p1[20],clk,l[20]);
dff b86 (p1[21],clk,l[21]);
dff b87 (p1[22],clk,l[22]);
dff b88 (p1[23],clk,l[23]);
dff b89 (p1[24],clk,l[24]);
dff b90 (p1[25],clk,l[25]);
dff b91 (p1[26],clk,l[26]);
dff b92 (p1[27],clk,l[27]);
dff b93 (p1[28],clk,l[28]);
dff b94 (p1[29],clk,l[29]);
dff b95 (p1[30],clk,l[30]);
dff b96 (p1[31],clk,l[31]);
dot d4(w1[4],l2[4],l2[5],l2[3]);
dot d5(w1[5],l2[6],l2[7],l2[3]);
dot d6(w1[6],l2[8],l2[9],l2[3]);
dot d7(w1[7],l2[10],l2[11],l2[3]);
circle c30(w2[59],w2[60],l2[20],l2[21],l2[18],l2[19]);
circle c31(w2[61],w2[62],l2[22],l2[23],l2[18],l2[19]);
circle c32(w2[63],w2[64],l2[24],l2[25],l2[18],l2[19]);
circle c33(w2[65],w2[66],l2[26],l2[27],l2[18],l2[19]);
circle c34(w2[67],w2[68],l2[36],l2[37],l2[34],l2[35]);
circle c35(w2[69],w2[70],l2[38],l2[39],l2[34],l2[35]);
circle c36(w2[71],w2[72],l2[40],l2[41],l2[34],l2[35]);
circle c37(w2[73],w2[74],l2[42],l2[43],l2[34],l2[35]);
circle c38(w2[75],w2[76],l2[52],l2[53],l2[50],l2[51]);
circle c39(w2[77],w2[78],l2[54],l2[55],l2[50],l2[51]);
circle c40(w2[79],w2[80],l2[56],l2[57],l2[50],l2[51]);
circle c41(w2[81],w2[82],l2[58],l2[59],l2[50],l2[51]);
dff m1(l3[0],clk,l2[0]);
dff m2(l3[1],clk,l2[1]);
dff m3(l3[2],clk,l2[2]);
dff m4(l3[3],clk,l2[3]);
dff m5(l3[4],clk,w1[4]);
dff m6(l3[5],clk,w1[5]);
dff m7(l3[6],clk,w1[6]);
dff m8(l3[7],clk,w1[7]);
dff m9(l3[8],clk,l2[12]);
dff m10(l3[9],clk,l2[13]);
dff m11(l3[10],clk,l2[14]);
dff m12(l3[11],clk,l2[15]);
dff m13(l3[12],clk,l2[16]);
dff m14(l3[13],clk,l2[17]);
dff m15(l3[14],clk,l2[18]);
dff m16(l3[15],clk,l2[19]);
dff m17(l3[16],clk,w2[59]);
dff m18(l3[17],clk,w2[60]);
dff m19(l3[18],clk,w2[61]);
dff m20(l3[19],clk,w2[62]);
dff m21(l3[20],clk,w2[63]);
dff m22(l3[21],clk,w2[64]);
dff m23(l3[22],clk,w2[65]);
dff m24(l3[23],clk,w2[66]);
dff m25(l3[24],clk,l2[28]);
dff m26(l3[25],clk,l2[29]);
dff m27(l3[26],clk,l2[30]);
dff m28(l3[27],clk,l2[31]);
dff m29(l3[28],clk,l2[32]);
dff m30(l3[29],clk,l2[33]);
dff m31(l3[30],clk,l2[34]);
dff m32(l3[31],clk,l2[35]);
dff m33(l3[32],clk,w2[67]);
dff m34(l3[33],clk,w2[68]);
dff m35(l3[34],clk,w2[69]);
dff m36(l3[35],clk,w2[70]);
dff m37(l3[36],clk,w2[71]);
dff m38(l3[37],clk,w2[72]);
dff m39(l3[38],clk,w2[73]);
dff m40(l3[39],clk,w2[74]);
dff m41(l3[40],clk,l2[44]);
dff m42(l3[41],clk,l2[45]);
dff m43(l3[42],clk,l2[46]);
dff m44(l3[43],clk,l2[47]);
dff m45(l3[44],clk,l2[48]);
dff m46(l3[45],clk,l2[49]);
dff m47(l3[46],clk,l2[50]);
dff m48(l3[47],clk,l2[51]);
dff m49(l3[48],clk,w2[75]);
dff m50(l3[49],clk,w2[76]);
dff m51(l3[50],clk,w2[77]);
dff m52(l3[51],clk,w2[78]);
dff m53(l3[52],clk,w2[79]);
dff m54(l3[53],clk,w2[80]);
dff m55(l3[54],clk,w2[81]);
dff m56(l3[56],clk,w2[82]);
dff m57(l3[56],clk,l2[60]);
dff m58(l3[57],clk,l2[61]);
dff m65 (p2[0],clk,p1[0]);
dff m66 (p2[1],clk,p1[1]);
dff m67 (p2[2],clk,p1[2]);
dff m68 (p2[3],clk,p1[3]);
dff m69 (p2[4],clk,p1[4]);
dff m70 (p2[5],clk,p1[5]);
dff m71 (p2[6],clk,p1[6]);
dff m72 (p2[7],clk,p1[7]);
dff m73 (p2[8],clk,p1[8]);
dff m74 (p2[9],clk,p1[9]);
dff m75 (p2[10],clk,p1[10]);
dff m76 (p2[11],clk,p1[11]);
dff m77 (p2[12],clk,p1[12]);
dff m78 (p2[13],clk,p1[13]);
dff m79 (p2[14],clk,p1[14]);
dff m80 (p2[15],clk,p1[15]);
dff m81 (p2[16],clk,p1[16]);
dff m82 (p2[17],clk,p1[17]);
dff m83 (p2[18],clk,p1[18]);
dff m84 (p2[19],clk,p1[19]);
dff m85 (p2[20],clk,p1[20]);
dff m86 (p2[21],clk,p1[21]);
dff m87 (p2[22],clk,p1[22]);
dff m88 (p2[23],clk,p1[23]);
dff m89 (p2[24],clk,p1[24]);
dff m90 (p2[25],clk,p1[25]);
dff m91 (p2[26],clk,p1[26]);
dff m92 (p2[27],clk,p1[27]);
dff m93 (p2[28],clk,p1[28]);
dff m94 (p2[29],clk,p1[29]);
dff m95 (p2[30],clk,p1[30]);
dff m96 (p2[31],clk,p1[31]);
dot d8(w1[8],l3[8],l3[9],l3[7]);
dot d9(w1[9],l3[10],l3[11],l3[7]);
dot d10(w1[10],l3[12],l3[13],l3[7]);
dot d11(w1[11],l3[14],l3[15],l3[7]);
dot d12(w1[12],l3[16],l3[17],l3[7]);
dot d13(w1[13],l3[18],l3[19],l3[7]);
dot d14(w1[14],l3[20],l3[21],l3[7]);
dot d15(w1[15],l3[22],l3[23],l3[7]);
circle c42(w2[83],w2[84],l3[40],l3[41],l3[38],l3[39]);
circle c43(w2[85],w2[86],l3[42],l3[43],l3[38],l3[39]);
circle c44(w2[87],w2[88],l3[44],l3[45],l3[38],l3[39]);
circle c45(w2[89],w2[90],l3[46],l3[47],l3[38],l3[39]);
circle c46(w2[91],w2[92],l3[48],l3[49],l3[38],l3[39]);
circle c47(w2[93],w2[94],l3[50],l3[51],l3[38],l3[39]);
circle c48(w2[95],w2[96],l3[52],l3[53],l3[38],l3[39]);
circle c49(w2[97],w2[98],l3[54],l3[55],l3[38],l3[39]);
dff z1(l4[0],clk,l3[0]);
dff z2(l4[1],clk,l3[1]);
dff z3(l4[2],clk,l3[2]);
dff z4(l4[3],clk,l3[3]);
dff z5(l4[4],clk,l3[4]);
dff z6(l4[5],clk,l3[5]);
dff z7(l4[6],clk,l3[6]);
dff z8(l4[7],clk,l3[7]);
dff z9(l4[8],clk,w1[8]);
dff z10(l4[9],clk,w1[9]);
dff z11(l4[10],clk,w1[10]);
dff z12(l4[11],clk,w1[11]);
dff z13(l4[12],clk,w1[12]);
dff z14(l4[13],clk,w1[13]);
dff z15(l4[14],clk,w1[14]);
dff z16(l4[15],clk,w1[15]);
dff z17(l4[16],clk,l3[24]);
dff z18(l4[17],clk,l3[25]);
dff z19(l4[18],clk,l3[26]);
dff z20(l4[19],clk,l3[27]);
dff z21(l4[20],clk,l3[28]);
dff z22(l4[21],clk,l3[29]);
dff z23(l4[22],clk,l3[30]);
dff z24(l4[23],clk,l3[31]);
dff z25(l4[24],clk,l3[32]);
dff z26(l4[25],clk,l3[33]);
dff z27(l4[26],clk,l3[34]);
dff z28(l4[27],clk,l3[35]);
dff z29(l4[28],clk,l3[36]);
dff z30(l4[29],clk,l3[37]);
dff z31(l4[30],clk,l3[38]);
dff z32(l4[31],clk,l3[39]);
dff z33(l4[32],clk,w2[83]);
dff z34(l4[33],clk,w2[84]);
dff z35(l4[34],clk,w2[85]);
dff z36(l4[35],clk,w2[86]);
dff z37(l4[36],clk,w2[87]);
dff z38(l4[37],clk,w2[88]);
dff z39(l4[38],clk,w2[89]);
dff z40(l4[39],clk,w2[90]);
dff z41(l4[40],clk,w2[91]);
dff z42(l4[41],clk,w2[92]);
dff z43(l4[42],clk,w2[93]);
dff z44(l4[43],clk,w2[94]);
dff z45(l4[44],clk,w2[95]);
dff z46(l4[45],clk,w2[96]);
dff z47(l4[46],clk,w2[97]);
dff z48(l4[47],clk,w2[98]);
dff z49(l4[48],clk,l3[56]);
dff z50(l4[49],clk,l3[57]);
dff n65 (p3[0],clk,p2[0]);
dff n66 (p3[1],clk,p2[1]);
dff n67 (p3[2],clk,p2[2]);
dff n68 (p3[3],clk,p2[3]);
dff n69 (p3[4],clk,p2[4]);
dff n70 (p3[5],clk,p2[5]);
dff n71 (p3[6],clk,p2[6]);
dff n72 (p3[7],clk,p2[7]);
dff n73 (p3[8],clk,p2[8]);
dff n74 (p3[9],clk,p2[9]);
dff n75 (p3[10],clk,p2[10]);
dff n76 (p3[11],clk,p2[11]);
dff n77 (p3[12],clk,p2[12]);
dff n78 (p3[13],clk,p2[13]);
dff n79 (p3[14],clk,p2[14]);
dff n80 (p3[15],clk,p2[15]);
dff n81 (p3[16],clk,p2[16]);
dff n82 (p3[17],clk,p2[17]);
dff n83 (p3[18],clk,p2[18]);
dff n84 (p3[19],clk,p2[19]);
dff n85 (p3[20],clk,p2[20]);
dff n86 (p3[21],clk,p2[21]);
dff n87 (p3[22],clk,p2[22]);
dff n88 (p3[23],clk,p2[23]);
dff n89 (p3[24],clk,p2[24]);
dff n90 (p3[25],clk,p2[25]);
dff n91 (p3[26],clk,p2[26]);
dff n92 (p3[27],clk,p2[27]);
dff n93 (p3[28],clk,p2[28]);
dff n94 (p3[29],clk,p2[29]);
dff n95 (p3[30],clk,p2[30]);
dff n96 (p3[31],clk,p2[31]);
dot d16(w1[16],l4[16],l4[17],l4[15]);
dot d17(w1[17],l4[18],l4[19],l4[15]);
dot d18(w1[18],l4[20],l4[21],l4[15]);
dot d19(w1[19],l4[22],l4[23],l4[15]);
dot d20(w1[20],l4[24],l4[25],l4[15]);
dot d21(w1[21],l4[26],l4[27],l4[15]);
dot d22(w1[22],l4[28],l4[29],l4[15]);
dot d23(w1[23],l4[30],l4[31],l4[15]);
dot d24(w1[24],l4[32],l4[33],l4[15]);
dot d25(w1[25],l4[34],l4[35],l4[15]);
dot d26(w1[26],l4[36],l4[37],l4[15]);
dot d27(w1[27],l4[38],l4[39],l4[15]);
dot d28(w1[28],l4[40],l4[41],l4[15]);
dot d29(w1[29],l4[42],l4[43],l4[15]);
dot d30(w1[30],l4[44],l4[45],l4[15]);
dot d31(w1[31],l4[46],l4[47],l4[15]);
dff q1(l5[0],clk,l4[0]);
dff q2(l5[1],clk,l4[1]);
dff q3(l5[2],clk,l4[2]);
dff q4(l5[3],clk,l4[3]);
dff q5(l5[4],clk,l4[4]);
dff q6(l5[5],clk,l4[5]);
dff q7(l5[6],clk,l4[6]);
dff q8(l5[7],clk,l4[7]);
dff q9(l5[8],clk,l4[8]);
dff q10(l5[9],clk,l4[9]);
dff q11(l5[10],clk,l4[10]);
dff q12(l5[11],clk,l4[11]);
dff q13(l5[12],clk,l4[12]);
dff q14(l5[13],clk,l4[13]);
dff q15(l5[14],clk,l4[14]);
dff q16(l5[15],clk,l4[15]);
dff q17(l5[16],clk,w1[16]);
dff q18(l5[17],clk,w1[17]);
dff q19(l5[18],clk,w1[18]);
dff q20(l5[19],clk,w1[19]);
dff q21(l5[20],clk,w1[20]);
dff q22(l5[21],clk,w1[21]);
dff q23(l5[22],clk,w1[22]);
dff q24(l5[23],clk,w1[23]);
dff q25(l5[24],clk,w1[24]);
dff q26(l5[25],clk,w1[25]);
dff q27(l5[26],clk,w1[26]);
dff q28(l5[27],clk,w1[27]);
dff q29(l5[28],clk,w1[28]);
dff q30(l5[29],clk,w1[29]);
dff q31(l5[30],clk,w1[30]);
dff q32(l5[31],clk,w1[31]);
dff q33(l5[32],clk,l4[48]);
dff q34(l5[33],clk,l4[49]);
dff z65 (p4[0],clk,p3[0]);
dff z66 (p4[1],clk,p3[1]);
dff z67 (p4[2],clk,p3[2]);
dff z68 (p4[3],clk,p3[3]);
dff z69 (p4[4],clk,p3[4]);
dff z70 (p4[5],clk,p3[5]);
dff z71 (p4[6],clk,p3[6]);
dff z72 (p4[7],clk,p3[7]);
dff z73 (p4[8],clk,p3[8]);
dff z74 (p4[9],clk,p3[9]);
dff z75 (p4[10],clk,p3[10]);
dff z76 (p4[11],clk,p3[11]);
dff z77 (p4[12],clk,p3[12]);
dff z78 (p4[13],clk,p3[13]);
dff z79 (p4[14],clk,p3[14]);
dff z80 (p4[15],clk,p3[15]);
dff z81 (p4[16],clk,p3[16]);
dff z82 (p4[17],clk,p3[17]);
dff z83 (p4[18],clk,p3[18]);
dff z84 (p4[19],clk,p3[19]);
dff z85 (p4[20],clk,p3[20]);
dff z86 (p4[21],clk,p3[21]);
dff z87 (p4[22],clk,p3[22]);
dff z88 (p4[23],clk,p3[23]);
dff z89 (p4[24],clk,p3[24]);
dff z90 (p4[25],clk,p3[25]);
dff z91 (p4[26],clk,p3[26]);
dff z92 (p4[27],clk,p3[27]);
dff z93 (p4[28],clk,p3[28]);
dff z94 (p4[29],clk,p3[29]);
dff z95 (p4[30],clk,p3[30]);
dff z96 (p4[31],clk,p3[31]);
dot d32(cout,l5[32],l5[33],l5[31]);
assign s = p4[31:0] ^ l5[31:0];
endmodule | 0 |
137,876 | data/full_repos/permissive/80602845/FAdd/test.v | 80,602,845 | test.v | v | 33 | 69 | [] | [] | [] | null | line:932: before: "$" | null | 1: b'%Error: data/full_repos/permissive/80602845/FAdd/test.v:1: Cannot find include file: pipeMult.v\n`include "pipeMult.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/pipeMult.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/pipeMult.v.v\n data/full_repos/permissive/80602845/FAdd,data/full_repos/permissive/80602845/pipeMult.v.sv\n pipeMult.v\n pipeMult.v.v\n pipeMult.v.sv\n obj_dir/pipeMult.v\n obj_dir/pipeMult.v.v\n obj_dir/pipeMult.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/80602845/FAdd/test.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80602845/FAdd/test.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: data/full_repos/permissive/80602845/FAdd/test.v:30: Unsupported or unknown PLI call: $monitor\n $monitor($time, "\\ta = %d\\tb = %d\\tpro = %d\\t" ,a ,b, pro, $time);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 300,683 | module | module test;
reg[31:0]a, b;
reg clk;
wire[63:0] pro;
multi p(a, b, pro, clk);
initial begin
clk = 0;
end
always begin
#1
clk = ~clk;
end
initial begin
a = 32'd1001;
b = 32'd212;
end
always begin
#100
$finish;
end
initial begin
$monitor($time, "\ta = %d\tb = %d\tpro = %d\t" ,a ,b, pro, $time);
end
endmodule | module test; |
reg[31:0]a, b;
reg clk;
wire[63:0] pro;
multi p(a, b, pro, clk);
initial begin
clk = 0;
end
always begin
#1
clk = ~clk;
end
initial begin
a = 32'd1001;
b = 32'd212;
end
always begin
#100
$finish;
end
initial begin
$monitor($time, "\ta = %d\tb = %d\tpro = %d\t" ,a ,b, pro, $time);
end
endmodule | 0 |
137,877 | data/full_repos/permissive/80602845/PA/dff.v | 80,602,845 | dff.v | v | 48 | 25 | [] | [] | [] | [(1, 10), (13, 23), (25, 35), (37, 47)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80602845/PA/dff.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dff\'\nmodule dff(d, clk, q);\n ^~~\n : ... Top module \'dff64\'\nmodule dff64(d, clk, q);\n ^~~~~\n : ... Top module \'dff63\'\nmodule dff63(d, clk, q);\n ^~~~~\n : ... Top module \'dff32\'\nmodule dff32(d, clk, q);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,685 | module | module dff(d, clk, q);
input d,clk;
output q;
reg q;
always@(posedge clk)
begin
q<=d;
end
endmodule | module dff(d, clk, q); |
input d,clk;
output q;
reg q;
always@(posedge clk)
begin
q<=d;
end
endmodule | 0 |
137,878 | data/full_repos/permissive/80602845/PA/dff.v | 80,602,845 | dff.v | v | 48 | 25 | [] | [] | [] | [(1, 10), (13, 23), (25, 35), (37, 47)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80602845/PA/dff.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dff\'\nmodule dff(d, clk, q);\n ^~~\n : ... Top module \'dff64\'\nmodule dff64(d, clk, q);\n ^~~~~\n : ... Top module \'dff63\'\nmodule dff63(d, clk, q);\n ^~~~~\n : ... Top module \'dff32\'\nmodule dff32(d, clk, q);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,685 | module | module dff64(d, clk, q);
input [63:0]d;
input clk;
output [63:0]q;
reg q;
always@(posedge clk)
begin
q<=d;
end
endmodule | module dff64(d, clk, q); |
input [63:0]d;
input clk;
output [63:0]q;
reg q;
always@(posedge clk)
begin
q<=d;
end
endmodule | 0 |
137,879 | data/full_repos/permissive/80602845/PA/dff.v | 80,602,845 | dff.v | v | 48 | 25 | [] | [] | [] | [(1, 10), (13, 23), (25, 35), (37, 47)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80602845/PA/dff.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dff\'\nmodule dff(d, clk, q);\n ^~~\n : ... Top module \'dff64\'\nmodule dff64(d, clk, q);\n ^~~~~\n : ... Top module \'dff63\'\nmodule dff63(d, clk, q);\n ^~~~~\n : ... Top module \'dff32\'\nmodule dff32(d, clk, q);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,685 | module | module dff63(d, clk, q);
input [62:0]d;
input clk;
output [62:0]q;
reg q;
always@(posedge clk)
begin
q<=d;
end
endmodule | module dff63(d, clk, q); |
input [62:0]d;
input clk;
output [62:0]q;
reg q;
always@(posedge clk)
begin
q<=d;
end
endmodule | 0 |
137,880 | data/full_repos/permissive/80602845/PA/dff.v | 80,602,845 | dff.v | v | 48 | 25 | [] | [] | [] | [(1, 10), (13, 23), (25, 35), (37, 47)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80602845/PA/dff.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dff\'\nmodule dff(d, clk, q);\n ^~~\n : ... Top module \'dff64\'\nmodule dff64(d, clk, q);\n ^~~~~\n : ... Top module \'dff63\'\nmodule dff63(d, clk, q);\n ^~~~~\n : ... Top module \'dff32\'\nmodule dff32(d, clk, q);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,685 | module | module dff32(d, clk, q);
input [31:0]d;
input clk;
output [31:0]q;
reg [31:0]q;
always@(posedge clk)
begin
q<=d;
end
endmodule | module dff32(d, clk, q); |
input [31:0]d;
input clk;
output [31:0]q;
reg [31:0]q;
always@(posedge clk)
begin
q<=d;
end
endmodule | 0 |
137,881 | data/full_repos/permissive/80602845/PA/prefix.v | 80,602,845 | prefix.v | v | 171 | 127 | [] | [] | [] | null | line:62: before: "[" | null | 1: b'%Error: data/full_repos/permissive/80602845/PA/prefix.v:1: Cannot find include file: dotmod.v\n`include "dotmod.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/PA,data/full_repos/permissive/80602845/dotmod.v\n data/full_repos/permissive/80602845/PA,data/full_repos/permissive/80602845/dotmod.v.v\n data/full_repos/permissive/80602845/PA,data/full_repos/permissive/80602845/dotmod.v.sv\n dotmod.v\n dotmod.v.v\n dotmod.v.sv\n obj_dir/dotmod.v\n obj_dir/dotmod.v.v\n obj_dir/dotmod.v.sv\n%Error: data/full_repos/permissive/80602845/PA/prefix.v:2: Cannot find include file: cirmod.v\n`include "cirmod.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/80602845/PA/prefix.v:3: Cannot find include file: dff.v\n`include "dff.v" \n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 300,688 | module | module prefix( x[31:0] , y[31:0] , cin , s[31:0] , cout , clk );
input [31:0]x,y;
output [31:0]s;
input cin;
output cout;
input clk;
wire [31:0]p,g,a,pt,gt,at;
wire [31:0] s1 , s1t , s12 , s12t , s21 , s21t , s22 , s22t , s31 , s31t , s32 , s32t , s41 , s41t , s42 , s42t , s51 , s51t;
assign pt = (x^y);
assign gt = (x&y);
assign at = (g|p);
dff32 p11( pt , clk , p );
dff32 p12( gt , clk , g );
dff32 p13( at , clk , a );
dotmod d11 ( g[0] , a[0] , cin , s1t[0] );
cirmod c11 ( g[2] , a[2] , g[1] , a[1] , s1t[1] , s12t[0] );
cirmod c12 ( g[4] , a[4] , g[3] , a[3] , s1t[2] , s12t[1] );
cirmod c13 ( g[6] , a[6] , g[5] , a[5] , s1t[3] , s12t[2] );
cirmod c14 ( g[8] , a[8] , g[7] , a[7] , s1t[4] , s12t[3] );
cirmod c15 ( g[10] , a[10] , g[9] , a[9] , s1t[5] , s12t[4] );
cirmod c16 ( g[12] , a[12] , g[11] , a[11] , s1t[6] , s12t[5] );
cirmod c17 ( g[14] , a[14] , g[13] , a[13] , s1t[7] , s12t[6] );
cirmod c18 ( g[16] , a[16] , g[15] , a[15] , s1t[8] , s12t[7] );
cirmod c19 ( g[18] , a[18] , g[17] , a[17] , s1t[9] , s12t[8] );
cirmod c110( g[20] , a[20] , g[19] , a[19] , s1t[10] , s12t[9] );
cirmod c111( g[22] , a[22] , g[21] , a[21] , s1t[11] , s12t[10] );
cirmod c112( g[24] , a[24] , g[23] , a[23] , s1t[12] , s12t[11] );
cirmod c113( g[26] , a[26] , g[25] , a[25] , s1t[13] , s12t[12] );
cirmod c114( g[28] , a[28] , g[27] , a[27] , s1t[14] , s12t[13] );
cirmod c115( g[30] , a[30] , g[29] , a[29] , s1t[15] , s12t[14] );
dff32 p21( s1t , clk , s1 );
dff32 p22( s12t , clk , s12 );
dotmod d21 (g[1] , a[1] , s1[0] , s21t[0] );
dotmod d22 (s1[1] , s12[0] , s1[0] , s21t[1] );
cirmod c21 (g[5] , a[5] , s1[2] , s12[1] , s21t[2] , s22t[0] );
cirmod c22 (s1[3] , s12[2] , s1[2] , s12[1] , s21t[3] , s22t[1] );
cirmod c23 (g[9] , a[9] , s1[4] , s12[3] , s21t[4] , s22t[2] );
cirmod c24 (s1[5] , s12[4] , s1[4] , s12[3] , s21t[5] , s22t[3] );
cirmod c25 (g[13] , a[13] , s1[6] , s12[5] , s21t[6] , s22t[4] );
cirmod c26 (s1[7] , s12[6] , s1[6] , s12[5] , s21t[7] , s22t[5] );
cirmod c27 (g[7] , a[17] , s1[8] , s12[7] , s21t[8] , s22t[6] );
cirmod c28 (s1[9] , s12[8] , s1[8] , s12[7] , s21t[9] , s22t[7] );
cirmod c29 (g[21] , a[21] , s1[10] , s12[9] , s21t[10] , s22t[8] );
cirmod c210(s1[11] , s12[10] , s1[10] , s12[9] , s21t[11] , s22t[9] );
cirmod c211(g[25] , a[25] , s1[12] , s12[11] , s21t[12] , s22t[10] );
cirmod c212(s1[13] , s12[12] , s1[12] , s12[11] , s21t[13] , s22t[11] );
cirmod c213(g[29] , a[29] , s1[14] , s12[13] , s21t[14] , s22t[12] );
cirmod c214(s1[15] , s12[14] , s1[14] , s12[13] , s21t[15] , s22t[13] );
dff32 p31( s21t , clk , s21 );
dff32 p32( s22t , clk , s22 );
dotmod d31 (g[3] , a[3] , s21[1] , s31t[0] );
dotmod d32 (s1[2] , s12[1] , s21[1] , s31t[1] );
dotmod d33 (s21[2] , s22[0] , s21[1] , s31t[2] );
dotmod d34 (s21[3] , s22[1] , s21[1] , s31t[3] );
cirmod c31 (s21[4] , s22[2] , g[7] , a[7] , s31t[4] , s32t[0] );
cirmod c32 (s21[5] , s22[3] , g[7] , a[7] , s31t[5] , s32t[1] );
cirmod c33 (s21[6] , s22[4] , g[11] , a[11] , s31t[6] , s32t[2] );
cirmod c34 (s21[7] , s22[5] , g[11] , a[11] , s31t[7] , s32t[3] );
cirmod c35 (g[19] , a[19] , s21[9] , s22[7] , s31t[8] , s32t[4] );
cirmod c36 (s1[10] , s12[9] , s21[9] , s22[7] , s31t[9] , s32t[5] );
cirmod c37 (s21[10] , s22[8] , s21[9] , s22[7] , s31t[10] , s32t[6] );
cirmod c38 (s21[11] , s22[9] , s21[9] , s22[7] , s31t[11] , s32t[7] );
cirmod c39 (g[27] , a[27] , s21[13] , s22[11] , s31t[12] , s32t[8] );
cirmod c310(s1[14] , s12[13] , s21[13] , s22[11] , s31t[13] , s32t[9] );
cirmod c311(s21[14] , s22[12] , s21[13] , s22[11] , s31t[14] , s32t[10] );
cirmod c312(s21[15] , s22[13] , s21[13] , s22[11] , s31t[15] , s32t[11] );
dff32 p41( s31t , clk , s31 );
dff32 p42( s32t , clk , s32 );
dotmod d41(s21[4] , s22[2] , s31[3] , s41t[0] );
dotmod d42(s21[5] , s22[3] , s31[3] , s41t[1] );
dotmod d43(s21[6] , s22[4] , s31[3] , s41t[2] );
dotmod d44(s21[7] , s22[5] , s31[3] , s41t[3] );
dotmod d45(s31[4] , s32[0] , s31[3] , s41t[4] );
dotmod d46(s31[5] , s32[1] , s31[3] , s41t[5] );
dotmod d47(s31[6] , s32[2] , s31[3] , s41t[6] );
dotmod d48(s31[7] , s32[3] , s31[3] , s41t[7] );
cirmod c41(g[23] , a[23] , s31[11] , s32[7] , s41t[8] , s42t[0] );
cirmod c42(s1[12] , s12[11] , s31[11] , s32[7] , s41t[9] , s42t[1] );
cirmod c43(s21[12] , s22[10] , s31[11] , s32[7] , s41t[10] , s42t[2] );
cirmod c44(s21[13] , s22[11] , s31[11] , s32[7] , s41t[11] , s42t[3] );
cirmod c45(s31[12] , s32[8] , s31[11] , s32[7] , s41t[12] , s42t[4] );
cirmod c46(s31[13] , s32[9] , s31[11] , s32[7] , s41t[13] , s42t[5] );
cirmod c47(s31[14] , s32[10] , s31[11] , s32[7] , s41t[14] , s42t[6] );
cirmod c48(s31[15] , s32[11] , s31[11] , s32[7] , s41t[15] , s42t[7] );
dff32 p51( s41t , clk , s41 );
dff32 p52( s42t , clk , s42 );
dotmod d51 (g[15] , a[15] , s41[7] , s51t[0]);
dotmod d52 (s1[8] , s12[7] , s41[7] , s51t[1]);
dotmod d53 (s21[8] , s22[6] , s41[7] , s51t[2]);
dotmod d54 (s21[9] , s22[7] , s41[7] , s51t[3]);
dotmod d55 (s31[8] , s32[4] , s41[7] , s51t[4]);
dotmod d56 (s31[9] , s32[5] , s41[7] , s51t[5]);
dotmod d57 (s31[10] , s32[6] , s41[7] , s51t[6]);
dotmod d58 (s31[11] , s32[7] , s41[7] , s51t[7]);
dotmod d59 (s41[8] , s42[0] , s41[7] , s51t[8]);
dotmod d510(s41[9] , s42[1] , s41[7] , s51t[9]);
dotmod d511(s41[10] , s42[2] , s41[7] , s51t[10]);
dotmod d512(s41[11] , s42[3] , s41[7] , s51t[11]);
dotmod d513(s41[12] , s42[4] , s41[7] , s51t[12]);
dotmod d514(s41[13] , s42[5] , s41[7] , s51t[13]);
dotmod d515(s41[14] , s42[6] , s41[7] , s51t[14]);
dotmod d516(s41[15] , s42[7] , s41[7] , s51t[15]);
dotmod d517(g[31] , a[31] , s51[15] , cout);
dff32 pfin( s51t , clk , s51 );
assign s[0] = cin ^ p[0];
assign s[1] = p[1] ^ s1[0];
assign s[2] = p[2] ^ s21[0];
assign s[3] = p[3] ^ s21[1];
assign s[4] = p[4] ^ s31[0];
assign s[5] = p[5] ^ s31[1];
assign s[6] = p[6] ^ s31[2];
assign s[7] = p[7] ^ s31[3];
assign s[8] = p[8] ^ s41[0];
assign s[9] = p[9] ^ s41[1];
assign s[10] = p[10] ^ s41[2];
assign s[11] = p[11] ^ s41[3];
assign s[12] = p[12] ^ s41[4];
assign s[13] = p[13] ^ s41[5];
assign s[14] = p[14] ^ s41[6];
assign s[15] = p[15] ^ s41[7];
assign s[16] = p[16] ^ s51[0];
assign s[17] = p[17] ^ s51[1];
assign s[18] = p[18] ^ s51[2];
assign s[19] = p[19] ^ s51[3];
assign s[20] = p[20] ^ s51[4];
assign s[21] = p[21] ^ s51[5];
assign s[22] = p[22] ^ s51[6];
assign s[23] = p[23] ^ s51[7];
assign s[24] = p[24] ^ s51[8];
assign s[25] = p[25] ^ s51[9];
assign s[26] = p[26] ^ s51[10];
assign s[27] = p[27] ^ s51[11];
assign s[28] = p[28] ^ s51[12];
assign s[29] = p[29] ^ s51[13];
assign s[30] = p[30] ^ s51[14];
assign s[31] = p[31] ^ s51[15];
endmodule | module prefix( x[31:0] , y[31:0] , cin , s[31:0] , cout , clk ); |
input [31:0]x,y;
output [31:0]s;
input cin;
output cout;
input clk;
wire [31:0]p,g,a,pt,gt,at;
wire [31:0] s1 , s1t , s12 , s12t , s21 , s21t , s22 , s22t , s31 , s31t , s32 , s32t , s41 , s41t , s42 , s42t , s51 , s51t;
assign pt = (x^y);
assign gt = (x&y);
assign at = (g|p);
dff32 p11( pt , clk , p );
dff32 p12( gt , clk , g );
dff32 p13( at , clk , a );
dotmod d11 ( g[0] , a[0] , cin , s1t[0] );
cirmod c11 ( g[2] , a[2] , g[1] , a[1] , s1t[1] , s12t[0] );
cirmod c12 ( g[4] , a[4] , g[3] , a[3] , s1t[2] , s12t[1] );
cirmod c13 ( g[6] , a[6] , g[5] , a[5] , s1t[3] , s12t[2] );
cirmod c14 ( g[8] , a[8] , g[7] , a[7] , s1t[4] , s12t[3] );
cirmod c15 ( g[10] , a[10] , g[9] , a[9] , s1t[5] , s12t[4] );
cirmod c16 ( g[12] , a[12] , g[11] , a[11] , s1t[6] , s12t[5] );
cirmod c17 ( g[14] , a[14] , g[13] , a[13] , s1t[7] , s12t[6] );
cirmod c18 ( g[16] , a[16] , g[15] , a[15] , s1t[8] , s12t[7] );
cirmod c19 ( g[18] , a[18] , g[17] , a[17] , s1t[9] , s12t[8] );
cirmod c110( g[20] , a[20] , g[19] , a[19] , s1t[10] , s12t[9] );
cirmod c111( g[22] , a[22] , g[21] , a[21] , s1t[11] , s12t[10] );
cirmod c112( g[24] , a[24] , g[23] , a[23] , s1t[12] , s12t[11] );
cirmod c113( g[26] , a[26] , g[25] , a[25] , s1t[13] , s12t[12] );
cirmod c114( g[28] , a[28] , g[27] , a[27] , s1t[14] , s12t[13] );
cirmod c115( g[30] , a[30] , g[29] , a[29] , s1t[15] , s12t[14] );
dff32 p21( s1t , clk , s1 );
dff32 p22( s12t , clk , s12 );
dotmod d21 (g[1] , a[1] , s1[0] , s21t[0] );
dotmod d22 (s1[1] , s12[0] , s1[0] , s21t[1] );
cirmod c21 (g[5] , a[5] , s1[2] , s12[1] , s21t[2] , s22t[0] );
cirmod c22 (s1[3] , s12[2] , s1[2] , s12[1] , s21t[3] , s22t[1] );
cirmod c23 (g[9] , a[9] , s1[4] , s12[3] , s21t[4] , s22t[2] );
cirmod c24 (s1[5] , s12[4] , s1[4] , s12[3] , s21t[5] , s22t[3] );
cirmod c25 (g[13] , a[13] , s1[6] , s12[5] , s21t[6] , s22t[4] );
cirmod c26 (s1[7] , s12[6] , s1[6] , s12[5] , s21t[7] , s22t[5] );
cirmod c27 (g[7] , a[17] , s1[8] , s12[7] , s21t[8] , s22t[6] );
cirmod c28 (s1[9] , s12[8] , s1[8] , s12[7] , s21t[9] , s22t[7] );
cirmod c29 (g[21] , a[21] , s1[10] , s12[9] , s21t[10] , s22t[8] );
cirmod c210(s1[11] , s12[10] , s1[10] , s12[9] , s21t[11] , s22t[9] );
cirmod c211(g[25] , a[25] , s1[12] , s12[11] , s21t[12] , s22t[10] );
cirmod c212(s1[13] , s12[12] , s1[12] , s12[11] , s21t[13] , s22t[11] );
cirmod c213(g[29] , a[29] , s1[14] , s12[13] , s21t[14] , s22t[12] );
cirmod c214(s1[15] , s12[14] , s1[14] , s12[13] , s21t[15] , s22t[13] );
dff32 p31( s21t , clk , s21 );
dff32 p32( s22t , clk , s22 );
dotmod d31 (g[3] , a[3] , s21[1] , s31t[0] );
dotmod d32 (s1[2] , s12[1] , s21[1] , s31t[1] );
dotmod d33 (s21[2] , s22[0] , s21[1] , s31t[2] );
dotmod d34 (s21[3] , s22[1] , s21[1] , s31t[3] );
cirmod c31 (s21[4] , s22[2] , g[7] , a[7] , s31t[4] , s32t[0] );
cirmod c32 (s21[5] , s22[3] , g[7] , a[7] , s31t[5] , s32t[1] );
cirmod c33 (s21[6] , s22[4] , g[11] , a[11] , s31t[6] , s32t[2] );
cirmod c34 (s21[7] , s22[5] , g[11] , a[11] , s31t[7] , s32t[3] );
cirmod c35 (g[19] , a[19] , s21[9] , s22[7] , s31t[8] , s32t[4] );
cirmod c36 (s1[10] , s12[9] , s21[9] , s22[7] , s31t[9] , s32t[5] );
cirmod c37 (s21[10] , s22[8] , s21[9] , s22[7] , s31t[10] , s32t[6] );
cirmod c38 (s21[11] , s22[9] , s21[9] , s22[7] , s31t[11] , s32t[7] );
cirmod c39 (g[27] , a[27] , s21[13] , s22[11] , s31t[12] , s32t[8] );
cirmod c310(s1[14] , s12[13] , s21[13] , s22[11] , s31t[13] , s32t[9] );
cirmod c311(s21[14] , s22[12] , s21[13] , s22[11] , s31t[14] , s32t[10] );
cirmod c312(s21[15] , s22[13] , s21[13] , s22[11] , s31t[15] , s32t[11] );
dff32 p41( s31t , clk , s31 );
dff32 p42( s32t , clk , s32 );
dotmod d41(s21[4] , s22[2] , s31[3] , s41t[0] );
dotmod d42(s21[5] , s22[3] , s31[3] , s41t[1] );
dotmod d43(s21[6] , s22[4] , s31[3] , s41t[2] );
dotmod d44(s21[7] , s22[5] , s31[3] , s41t[3] );
dotmod d45(s31[4] , s32[0] , s31[3] , s41t[4] );
dotmod d46(s31[5] , s32[1] , s31[3] , s41t[5] );
dotmod d47(s31[6] , s32[2] , s31[3] , s41t[6] );
dotmod d48(s31[7] , s32[3] , s31[3] , s41t[7] );
cirmod c41(g[23] , a[23] , s31[11] , s32[7] , s41t[8] , s42t[0] );
cirmod c42(s1[12] , s12[11] , s31[11] , s32[7] , s41t[9] , s42t[1] );
cirmod c43(s21[12] , s22[10] , s31[11] , s32[7] , s41t[10] , s42t[2] );
cirmod c44(s21[13] , s22[11] , s31[11] , s32[7] , s41t[11] , s42t[3] );
cirmod c45(s31[12] , s32[8] , s31[11] , s32[7] , s41t[12] , s42t[4] );
cirmod c46(s31[13] , s32[9] , s31[11] , s32[7] , s41t[13] , s42t[5] );
cirmod c47(s31[14] , s32[10] , s31[11] , s32[7] , s41t[14] , s42t[6] );
cirmod c48(s31[15] , s32[11] , s31[11] , s32[7] , s41t[15] , s42t[7] );
dff32 p51( s41t , clk , s41 );
dff32 p52( s42t , clk , s42 );
dotmod d51 (g[15] , a[15] , s41[7] , s51t[0]);
dotmod d52 (s1[8] , s12[7] , s41[7] , s51t[1]);
dotmod d53 (s21[8] , s22[6] , s41[7] , s51t[2]);
dotmod d54 (s21[9] , s22[7] , s41[7] , s51t[3]);
dotmod d55 (s31[8] , s32[4] , s41[7] , s51t[4]);
dotmod d56 (s31[9] , s32[5] , s41[7] , s51t[5]);
dotmod d57 (s31[10] , s32[6] , s41[7] , s51t[6]);
dotmod d58 (s31[11] , s32[7] , s41[7] , s51t[7]);
dotmod d59 (s41[8] , s42[0] , s41[7] , s51t[8]);
dotmod d510(s41[9] , s42[1] , s41[7] , s51t[9]);
dotmod d511(s41[10] , s42[2] , s41[7] , s51t[10]);
dotmod d512(s41[11] , s42[3] , s41[7] , s51t[11]);
dotmod d513(s41[12] , s42[4] , s41[7] , s51t[12]);
dotmod d514(s41[13] , s42[5] , s41[7] , s51t[13]);
dotmod d515(s41[14] , s42[6] , s41[7] , s51t[14]);
dotmod d516(s41[15] , s42[7] , s41[7] , s51t[15]);
dotmod d517(g[31] , a[31] , s51[15] , cout);
dff32 pfin( s51t , clk , s51 );
assign s[0] = cin ^ p[0];
assign s[1] = p[1] ^ s1[0];
assign s[2] = p[2] ^ s21[0];
assign s[3] = p[3] ^ s21[1];
assign s[4] = p[4] ^ s31[0];
assign s[5] = p[5] ^ s31[1];
assign s[6] = p[6] ^ s31[2];
assign s[7] = p[7] ^ s31[3];
assign s[8] = p[8] ^ s41[0];
assign s[9] = p[9] ^ s41[1];
assign s[10] = p[10] ^ s41[2];
assign s[11] = p[11] ^ s41[3];
assign s[12] = p[12] ^ s41[4];
assign s[13] = p[13] ^ s41[5];
assign s[14] = p[14] ^ s41[6];
assign s[15] = p[15] ^ s41[7];
assign s[16] = p[16] ^ s51[0];
assign s[17] = p[17] ^ s51[1];
assign s[18] = p[18] ^ s51[2];
assign s[19] = p[19] ^ s51[3];
assign s[20] = p[20] ^ s51[4];
assign s[21] = p[21] ^ s51[5];
assign s[22] = p[22] ^ s51[6];
assign s[23] = p[23] ^ s51[7];
assign s[24] = p[24] ^ s51[8];
assign s[25] = p[25] ^ s51[9];
assign s[26] = p[26] ^ s51[10];
assign s[27] = p[27] ^ s51[11];
assign s[28] = p[28] ^ s51[12];
assign s[29] = p[29] ^ s51[13];
assign s[30] = p[30] ^ s51[14];
assign s[31] = p[31] ^ s51[15];
endmodule | 0 |
137,882 | data/full_repos/permissive/80602845/PA/test.v | 80,602,845 | test.v | v | 35 | 102 | [] | [] | [] | null | line:62: before: "[" | null | 1: b'%Error: data/full_repos/permissive/80602845/PA/test.v:1: Cannot find include file: prefix.v\n`include "prefix.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/PA,data/full_repos/permissive/80602845/prefix.v\n data/full_repos/permissive/80602845/PA,data/full_repos/permissive/80602845/prefix.v.v\n data/full_repos/permissive/80602845/PA,data/full_repos/permissive/80602845/prefix.v.sv\n prefix.v\n prefix.v.v\n prefix.v.sv\n obj_dir/prefix.v\n obj_dir/prefix.v.v\n obj_dir/prefix.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/80602845/PA/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80602845/PA/test.v:27: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: data/full_repos/permissive/80602845/PA/test.v:32: Unsupported or unknown PLI call: $monitor\n $monitor($time, "\\ta = %b\\tb = %b\\tcin = %b\\ts = %b\\tcout = %b\\t" , a , b , cin , s , cout, $time);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 300,689 | module | module test;
reg[31:0]a, b;
reg cin, clk;
wire[31:0] s;
wire cout;
prefix p( a , b , cin , s , cout , clk );
initial begin
clk = 0;
end
always begin
#1
clk = ~clk;
end
initial begin
a = 32'd2147483647;
b = 32'd1;
cin = 0;
end
always begin
#100
$finish;
end
initial begin
$monitor($time, "\ta = %b\tb = %b\tcin = %b\ts = %b\tcout = %b\t" , a , b , cin , s , cout, $time);
end
endmodule | module test; |
reg[31:0]a, b;
reg cin, clk;
wire[31:0] s;
wire cout;
prefix p( a , b , cin , s , cout , clk );
initial begin
clk = 0;
end
always begin
#1
clk = ~clk;
end
initial begin
a = 32'd2147483647;
b = 32'd1;
cin = 0;
end
always begin
#100
$finish;
end
initial begin
$monitor($time, "\ta = %b\tb = %b\tcin = %b\ts = %b\tcout = %b\t" , a , b , cin , s , cout, $time);
end
endmodule | 0 |
137,883 | data/full_repos/permissive/80602845/prac/clock.v | 80,602,845 | clock.v | v | 15 | 27 | [] | [] | [] | [(1, 14)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/80602845/prac/clock.v:12: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,690 | module | module clock(enable, clk);
input enable;
output clk;
reg clk;
initial begin
clk=1;
end
always begin
#5 clk = !clk;
end
endmodule | module clock(enable, clk); |
input enable;
output clk;
reg clk;
initial begin
clk=1;
end
always begin
#5 clk = !clk;
end
endmodule | 0 |
137,884 | data/full_repos/permissive/80602845/prac/dff.v | 80,602,845 | dff.v | v | 15 | 30 | [] | [] | [] | null | line:6: before: "(" | data/verilator_xmls/adb1f898-dc42-454d-89d5-0b645d38f0c8.xml | null | 300,691 | module | module dff(d, clk, reset, q);
input d, clk, reset;
output q;
reg q;
always @(posedge(clk)) begin
if (reset) begin
q<=0;
end
else begin
q<=d;
end
end
endmodule | module dff(d, clk, reset, q); |
input d, clk, reset;
output q;
reg q;
always @(posedge(clk)) begin
if (reset) begin
q<=0;
end
else begin
q<=d;
end
end
endmodule | 0 |
137,885 | data/full_repos/permissive/80602845/prac/tbclock.v | 80,602,845 | tbclock.v | v | 34 | 74 | [] | [] | [] | null | line:39: before: "$" | null | 1: b'%Error: data/full_repos/permissive/80602845/prac/tbclock.v:1: Cannot find include file: tff.v\n`include "tff.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/80602845/prac,data/full_repos/permissive/80602845/tff.v\n data/full_repos/permissive/80602845/prac,data/full_repos/permissive/80602845/tff.v.v\n data/full_repos/permissive/80602845/prac,data/full_repos/permissive/80602845/tff.v.sv\n tff.v\n tff.v.v\n tff.v.sv\n obj_dir/tff.v\n obj_dir/tff.v.v\n obj_dir/tff.v.sv\n%Error: data/full_repos/permissive/80602845/prac/tbclock.v:20: Unsupported or unknown PLI call: $monitor\n $monitor("%g\\t%d\\t%b\\t%b\\t%b\\t%b", $time, clk, q[0], q[1], q[2], q[3]);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/80602845/prac/tbclock.v:25: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80602845/prac/tbclock.v:27: Unsupported: Ignoring delay on this delayed statement.\n #50 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80602845/prac/tbclock.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = !clk;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 300,693 | module | module test;
reg clk;
wire q[3:0];
reg reset, init;
tff a(init, clk, reset, q[0]);
tff b(q[0], clk, reset, q[1]);
tff c(q[1], clk, reset, q[2]);
tff d(q[2], clk, reset, q[3]);
initial begin
$display("Time\tclk\tq");
$monitor("%g\t%d\t%b\t%b\t%b\t%b", $time, clk, q[0], q[1], q[2], q[3]);
clk=0;
reset = 1;
init = 0;
#2 reset = 0;
init = 1;
#50 $finish;
end
always begin
#1 clk = !clk;
end
endmodule | module test; |
reg clk;
wire q[3:0];
reg reset, init;
tff a(init, clk, reset, q[0]);
tff b(q[0], clk, reset, q[1]);
tff c(q[1], clk, reset, q[2]);
tff d(q[2], clk, reset, q[3]);
initial begin
$display("Time\tclk\tq");
$monitor("%g\t%d\t%b\t%b\t%b\t%b", $time, clk, q[0], q[1], q[2], q[3]);
clk=0;
reset = 1;
init = 0;
#2 reset = 0;
init = 1;
#50 $finish;
end
always begin
#1 clk = !clk;
end
endmodule | 0 |
137,886 | data/full_repos/permissive/80602845/prac/tff.v | 80,602,845 | tff.v | v | 14 | 25 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/7f01d79b-2130-430d-8adf-4e47541470b7.xml | null | 300,694 | module | module tff(t, reset, q);
input t, reset;
output q;
reg q;
always @(t) begin
if (reset)
q<=0;
else
q<=!q;
end
endmodule | module tff(t, reset, q); |
input t, reset;
output q;
reg q;
always @(t) begin
if (reset)
q<=0;
else
q<=!q;
end
endmodule | 0 |
137,887 | data/full_repos/permissive/80602845/RCA/fa16.v | 80,602,845 | fa16.v | v | 12 | 45 | [] | [] | [] | [(1, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/RCA/fa16.v:7: Cannot find file containing module: 'fa4'\n fa4 f1(a[3:0],b[3:0],cin,s[3:0],w1);\n ^~~\n ... Looked in:\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa4\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa4.v\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa4.sv\n fa4\n fa4.v\n fa4.sv\n obj_dir/fa4\n obj_dir/fa4.v\n obj_dir/fa4.sv\n%Error: data/full_repos/permissive/80602845/RCA/fa16.v:8: Cannot find file containing module: 'fa4'\n fa4 f2(a[7:4],b[7:4],w1,s[7:4],w2);\n ^~~\n%Error: data/full_repos/permissive/80602845/RCA/fa16.v:9: Cannot find file containing module: 'fa4'\n fa4 f3(a[11:8],b[11:8],w2,s[11:8],w3);\n ^~~\n%Error: data/full_repos/permissive/80602845/RCA/fa16.v:10: Cannot find file containing module: 'fa4'\n fa4 f4(a[15:12],b[15:12],w3,s[15:12],cout);\n ^~~\n%Error: Exiting due to 4 error(s)\n" | 300,696 | module | module fa16(a,b,cin,s,cout);
input [15:0]a,b;
input cin;
output [15:0]s;
output cout;
wire w1,w2,w3;
fa4 f1(a[3:0],b[3:0],cin,s[3:0],w1);
fa4 f2(a[7:4],b[7:4],w1,s[7:4],w2);
fa4 f3(a[11:8],b[11:8],w2,s[11:8],w3);
fa4 f4(a[15:12],b[15:12],w3,s[15:12],cout);
endmodule | module fa16(a,b,cin,s,cout); |
input [15:0]a,b;
input cin;
output [15:0]s;
output cout;
wire w1,w2,w3;
fa4 f1(a[3:0],b[3:0],cin,s[3:0],w1);
fa4 f2(a[7:4],b[7:4],w1,s[7:4],w2);
fa4 f3(a[11:8],b[11:8],w2,s[11:8],w3);
fa4 f4(a[15:12],b[15:12],w3,s[15:12],cout);
endmodule | 0 |
137,888 | data/full_repos/permissive/80602845/RCA/fa32.v | 80,602,845 | fa32.v | v | 10 | 46 | [] | [] | [] | [(1, 9)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/RCA/fa32.v:7: Cannot find file containing module: 'fa16'\n fa16 f1(a[15:0],b[15:0],cin,s[15:0],w1);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa16\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa16.v\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa16.sv\n fa16\n fa16.v\n fa16.sv\n obj_dir/fa16\n obj_dir/fa16.v\n obj_dir/fa16.sv\n%Error: data/full_repos/permissive/80602845/RCA/fa32.v:8: Cannot find file containing module: 'fa16'\n fa16 f2(a[31:16],b[31:16],w1,s[31:16],cout);\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 300,697 | module | module fa32(a,b,cin,s,cout);
input [31:0]a,b;
input cin;
output [31:0]s;
output cout;
wire w1;
fa16 f1(a[15:0],b[15:0],cin,s[15:0],w1);
fa16 f2(a[31:16],b[31:16],w1,s[31:16],cout);
endmodule | module fa32(a,b,cin,s,cout); |
input [31:0]a,b;
input cin;
output [31:0]s;
output cout;
wire w1;
fa16 f1(a[15:0],b[15:0],cin,s[15:0],w1);
fa16 f2(a[31:16],b[31:16],w1,s[31:16],cout);
endmodule | 0 |
137,889 | data/full_repos/permissive/80602845/RCA/fa4.v | 80,602,845 | fa4.v | v | 12 | 32 | [] | [] | [] | [(1, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/80602845/RCA/fa4.v:7: Cannot find file containing module: 'fa'\n fa f1(a[0],b[0],cin,s[0],w1);\n ^~\n ... Looked in:\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa.v\n data/full_repos/permissive/80602845/RCA,data/full_repos/permissive/80602845/fa.sv\n fa\n fa.v\n fa.sv\n obj_dir/fa\n obj_dir/fa.v\n obj_dir/fa.sv\n%Error: data/full_repos/permissive/80602845/RCA/fa4.v:8: Cannot find file containing module: 'fa'\n fa f2(a[1],b[1],w1,s[1],w2);\n ^~\n%Error: data/full_repos/permissive/80602845/RCA/fa4.v:9: Cannot find file containing module: 'fa'\n fa f3(a[2],b[2],w2,s[2],w3);\n ^~\n%Error: data/full_repos/permissive/80602845/RCA/fa4.v:10: Cannot find file containing module: 'fa'\n fa f4(a[3],b[3],w3,s[3],cout);\n ^~\n%Error: Exiting due to 4 error(s)\n" | 300,698 | module | module fa4(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire w1,w2,w3;
fa f1(a[0],b[0],cin,s[0],w1);
fa f2(a[1],b[1],w1,s[1],w2);
fa f3(a[2],b[2],w2,s[2],w3);
fa f4(a[3],b[3],w3,s[3],cout);
endmodule | module fa4(a,b,cin,s,cout); |
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire w1,w2,w3;
fa f1(a[0],b[0],cin,s[0],w1);
fa f2(a[1],b[1],w1,s[1],w2);
fa f3(a[2],b[2],w2,s[2],w3);
fa f4(a[3],b[3],w3,s[3],cout);
endmodule | 0 |
137,890 | data/full_repos/permissive/80602845/RCA/testbench.v | 80,602,845 | testbench.v | v | 19 | 53 | [] | [] | [] | [(1, 18)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/80602845/RCA/testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n #10 A=32\'d1798; B=32\'d2561 ; cin=1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/80602845/RCA/testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10 A=32\'d2561; B=32\'d1798 ; cin=1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/80602845/RCA/testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10 A=32\'d98756; B=32\'d32165 ; cin=1\'b0;\n ^\n%Error: data/full_repos/permissive/80602845/RCA/testbench.v:16: Unsupported or unknown PLI call: $monitor\n $monitor($time, " %d %d %b %d %b",A,B,cin,S,cout);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 300,699 | module | module testb();
reg [31:0]A,B;
reg cin;
wire [31:0] S;
wire cout;
fa32 f(A,B,cin,S,cout);
initial
begin
#10 A=32'd1798; B=32'd2561 ; cin=1'b0;
#10 A=32'd2561; B=32'd1798 ; cin=1'b0;
#10 A=32'd98756; B=32'd32165 ; cin=1'b0;
end
initial begin
$monitor($time, " %d %d %b %d %b",A,B,cin,S,cout);
end
endmodule | module testb(); |
reg [31:0]A,B;
reg cin;
wire [31:0] S;
wire cout;
fa32 f(A,B,cin,S,cout);
initial
begin
#10 A=32'd1798; B=32'd2561 ; cin=1'b0;
#10 A=32'd2561; B=32'd1798 ; cin=1'b0;
#10 A=32'd98756; B=32'd32165 ; cin=1'b0;
end
initial begin
$monitor($time, " %d %d %b %d %b",A,B,cin,S,cout);
end
endmodule | 0 |
137,891 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module inv(input A, output Y);
assign Y = ~A;
endmodule | module inv(input A, output Y); |
assign Y = ~A;
endmodule | 17 |
137,892 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module tri_inv(input A, input S, output reg Y);
always@(*)
begin
if (S==1'b0)
begin
Y <= 1'bz;
end
else
begin
Y <= ~A;
end
end
endmodule | module tri_inv(input A, input S, output reg Y); |
always@(*)
begin
if (S==1'b0)
begin
Y <= 1'bz;
end
else
begin
Y <= ~A;
end
end
endmodule | 17 |
137,893 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module buffer(input A, output Y);
assign Y = A;
endmodule | module buffer(input A, output Y); |
assign Y = A;
endmodule | 17 |
137,894 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module nand2(input A, input B, output Y);
assign Y = ~(A & B);
endmodule | module nand2(input A, input B, output Y); |
assign Y = ~(A & B);
endmodule | 17 |
137,895 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module nor2(input A, input B, output Y);
assign Y = ~(A | B);
endmodule | module nor2(input A, input B, output Y); |
assign Y = ~(A | B);
endmodule | 17 |
137,896 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module xor2(input A, input B, output Y);
assign Y = A ^ B;
endmodule | module xor2(input A, input B, output Y); |
assign Y = A ^ B;
endmodule | 17 |
137,897 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module imux2(input A, input B, input S, output Y);
assign Y = ~(S ? A : B);
endmodule | module imux2(input A, input B, input S, output Y); |
assign Y = ~(S ? A : B);
endmodule | 17 |
137,898 | data/full_repos/permissive/80622510/celllibs/supergate/supergate.v | 80,622,510 | supergate.v | v | 105 | 88 | [] | [] | [] | [(15, 17), (19, 31), (33, 35), (37, 39), (41, 43), (45, 47), (49, 51), (53, 74), (76, 85), (88, 90), (92, 94), (96, 99), (101, 104)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/80622510/celllibs/supergate/supergate.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'inv\'\nmodule inv(input A, output Y);\n ^~~\n : ... Top module \'tri_inv\'\nmodule tri_inv(input A, input S, output reg Y);\n ^~~~~~~\n : ... Top module \'buffer\'\nmodule buffer(input A, output Y);\n ^~~~~~\n : ... Top module \'nand2\'\nmodule nand2(input A, input B, output Y);\n ^~~~~\n : ... Top module \'nor2\'\nmodule nor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'xor2\'\nmodule xor2(input A, input B, output Y);\n ^~~~\n : ... Top module \'imux2\'\nmodule imux2(input A, input B, input S, output Y);\n ^~~~~\n : ... Top module \'dff\'\nmodule dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);\n ^~~\n : ... Top module \'latch\'\nmodule latch(input G, input D, output reg Q, output reg QN);\n ^~~~~\n : ... Top module \'aoi211\'\nmodule aoi211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'oai211\'\nmodule oai211(input A, input B, input C, output Y);\n ^~~~~~\n : ... Top module \'halfadder\'\nmodule halfadder(input A, input B, output C, output Y);\n ^~~~~~~~~\n : ... Top module \'fulladder\'\nmodule fulladder(input A, input B, input CI, output CO, output Y);\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 300,707 | module | module dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN);
always@(CLK or RESET or PRESET)
begin
if (RESET)
begin
Q <= 1'b0;
QN <= 1'b1;
end
else
if (PRESET)
begin
Q <= 1'b1;
QN <= 1'b0;
end
else
if (CLK)
begin
Q <= D;
QN <= ~D;
end
end
endmodule | module dff(input CLK, input D, input RESET, input PRESET, output reg Q, output reg QN); |
always@(CLK or RESET or PRESET)
begin
if (RESET)
begin
Q <= 1'b0;
QN <= 1'b1;
end
else
if (PRESET)
begin
Q <= 1'b1;
QN <= 1'b0;
end
else
if (CLK)
begin
Q <= D;
QN <= ~D;
end
end
endmodule | 17 |
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