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138,340 | data/full_repos/permissive/83270534/mercury/tb/tb_fpga_top.v | 83,270,534 | tb_fpga_top.v | v | 285 | 80 | [] | [] | [] | null | line:285: before: "/" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/83270534/mercury/tb/tb_fpga_top.v:132: Unsupported: Ignoring delay on this delayed statement.\n always #10 CLK = !CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83270534/mercury/tb/tb_fpga_top.v:139: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,184 | module | module TB_FPGA_TOP ();
reg BTN_0;
wire BTN_1 = 1'b0;
wire BTN_2 = 1'b0;
wire BTN_3 = 1'b0;
reg CLK ;
wire EPP_ASTB = 1'b0;
wire EPP_DSTB = 1'b0;
wire EPP_WAIT ;
wire FLASH_CS ;
wire FLASH_RP ;
wire FLASH_ST_STS = 1'b0;
wire LED_0 ;
wire LED_1 ;
wire LED_2 ;
wire LED_3 ;
wire LED_4 ;
wire LED_5 ;
wire LED_6 ;
wire LED_7 ;
wire MEM_ADDR_1 ;
wire MEM_ADDR_2 ;
wire MEM_ADDR_3 ;
wire MEM_ADDR_4 ;
wire MEM_ADDR_5 ;
wire MEM_ADDR_6 ;
wire MEM_ADDR_7 ;
wire MEM_ADDR_8 ;
wire MEM_ADDR_9 ;
wire MEM_ADDR_10 ;
wire MEM_ADDR_11 ;
wire MEM_ADDR_12 ;
wire MEM_ADDR_13 ;
wire MEM_ADDR_14 ;
wire MEM_ADDR_15 ;
wire MEM_ADDR_16 ;
wire MEM_ADDR_17 ;
wire MEM_ADDR_18 ;
wire MEM_ADDR_19 ;
wire MEM_ADDR_20 ;
wire MEM_ADDR_21 ;
wire MEM_ADDR_22 ;
wire MEM_ADDR_23 ;
wire MEM_DATA_0 = 1'b0;
wire MEM_DATA_1 = 1'b0;
wire MEM_DATA_2 = 1'b0;
wire MEM_DATA_3 = 1'b0;
wire MEM_DATA_4 = 1'b0;
wire MEM_DATA_5 = 1'b0;
wire MEM_DATA_6 = 1'b0;
wire MEM_DATA_7 = 1'b0;
wire MEM_DATA_8 = 1'b0;
wire MEM_DATA_9 = 1'b0;
wire MEM_DATA_10 = 1'b0;
wire MEM_DATA_11 = 1'b0;
wire MEM_DATA_12 = 1'b0;
wire MEM_DATA_13 = 1'b0;
wire MEM_DATA_14 = 1'b0;
wire MEM_DATA_15 = 1'b0;
wire MEM_OE ;
wire MEM_WR ;
wire PS2_CLK = 1'b0;
wire PS2_DATA = 1'b0;
wire RAM_ADV ;
wire RAM_CLK ;
wire RAM_CRE ;
wire RAM_CS ;
wire RAM_LB ;
wire RAM_UB ;
wire RAM_WAIT = 1'b0;
wire RS232_RX ;
wire RS232_TX ;
wire SSEG_AN_0 ;
wire SSEG_AN_1 ;
wire SSEG_AN_2 ;
wire SSEG_AN_3 ;
wire SSEG_K_0 ;
wire SSEG_K_1 ;
wire SSEG_K_2 ;
wire SSEG_K_3 ;
wire SSEG_K_4 ;
wire SSEG_K_5 ;
wire SSEG_K_6 ;
wire SSEG_K_7 ;
wire SW_0 = 1'b0;
wire SW_1 = 1'b0;
wire SW_2 = 1'b0;
wire SW_3 = 1'b0;
wire SW_4 = 1'b0;
wire SW_5 = 1'b0;
wire SW_6 = 1'b0;
wire SW_7 = 1'b0;
wire USB_ADDR_0 ;
wire USB_ADDR_1 ;
wire USB_CLK = 1'b0;
wire USB_DATA_0 = 1'b0;
wire USB_DATA_1 = 1'b0;
wire USB_DATA_2 = 1'b0;
wire USB_DATA_3 = 1'b0;
wire USB_DATA_4 = 1'b0;
wire USB_DATA_5 = 1'b0;
wire USB_DATA_6 = 1'b0;
wire USB_DATA_7 = 1'b0;
wire USB_DIR = 1'b0;
wire USB_FLAG = 1'b0;
wire USB_MODE = 1'b0;
wire USB_OE ;
wire USB_PKTEND ;
wire USB_WR ;
wire VGA_BLUE_0 ;
wire VGA_BLUE_1 ;
wire VGA_GREEN_0 ;
wire VGA_GREEN_1 ;
wire VGA_GREEN_2 ;
wire VGA_HSYNC ;
wire VGA_RED_0 ;
wire VGA_RED_1 ;
wire VGA_RED_2 ;
wire VGA_VSYNC ;
initial
begin
CLK = 1'b0;
end
always #10 CLK = !CLK;
initial
begin
BTN_0 = 1'b1;
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
BTN_0 = 1'b0;
end
glbl glbl ();
TESTCASE testcase();
FPGA_TOP fpga_top
(
.BTN_0_IN (BTN_0 ),
.BTN_1_IN (BTN_1 ),
.BTN_2_IN (BTN_2 ),
.BTN_3_IN (BTN_3 ),
.CLK_IN (CLK ),
.EPP_ASTB_IN (EPP_ASTB ),
.EPP_DSTB_IN (EPP_DSTB ),
.EPP_WAIT_OUT (EPP_WAIT ),
.FLASH_CS_OUT (FLASH_CS ),
.FLASH_RP_OUT (FLASH_RP ),
.FLASH_ST_STS_IN (FLASH_ST_STS ),
.LED_0_OUT (LED_0 ),
.LED_1_OUT (LED_1 ),
.LED_2_OUT (LED_2 ),
.LED_3_OUT (LED_3 ),
.LED_4_OUT (LED_4 ),
.LED_5_OUT (LED_5 ),
.LED_6_OUT (LED_6 ),
.LED_7_OUT (LED_7 ),
.MEM_ADDR_1_OUT (MEM_ADDR_1 ),
.MEM_ADDR_2_OUT (MEM_ADDR_2 ),
.MEM_ADDR_3_OUT (MEM_ADDR_3 ),
.MEM_ADDR_4_OUT (MEM_ADDR_4 ),
.MEM_ADDR_5_OUT (MEM_ADDR_5 ),
.MEM_ADDR_6_OUT (MEM_ADDR_6 ),
.MEM_ADDR_7_OUT (MEM_ADDR_7 ),
.MEM_ADDR_8_OUT (MEM_ADDR_8 ),
.MEM_ADDR_9_OUT (MEM_ADDR_9 ),
.MEM_ADDR_10_OUT (MEM_ADDR_10 ),
.MEM_ADDR_11_OUT (MEM_ADDR_11 ),
.MEM_ADDR_12_OUT (MEM_ADDR_12 ),
.MEM_ADDR_13_OUT (MEM_ADDR_13 ),
.MEM_ADDR_14_OUT (MEM_ADDR_14 ),
.MEM_ADDR_15_OUT (MEM_ADDR_15 ),
.MEM_ADDR_16_OUT (MEM_ADDR_16 ),
.MEM_ADDR_17_OUT (MEM_ADDR_17 ),
.MEM_ADDR_18_OUT (MEM_ADDR_18 ),
.MEM_ADDR_19_OUT (MEM_ADDR_19 ),
.MEM_ADDR_20_OUT (MEM_ADDR_20 ),
.MEM_ADDR_21_OUT (MEM_ADDR_21 ),
.MEM_ADDR_22_OUT (MEM_ADDR_22 ),
.MEM_ADDR_23_OUT (MEM_ADDR_23 ),
.MEM_DATA_0_INOUT (MEM_DATA_0 ),
.MEM_DATA_1_INOUT (MEM_DATA_1 ),
.MEM_DATA_2_INOUT (MEM_DATA_2 ),
.MEM_DATA_3_INOUT (MEM_DATA_3 ),
.MEM_DATA_4_INOUT (MEM_DATA_4 ),
.MEM_DATA_5_INOUT (MEM_DATA_5 ),
.MEM_DATA_6_INOUT (MEM_DATA_6 ),
.MEM_DATA_7_INOUT (MEM_DATA_7 ),
.MEM_DATA_8_INOUT (MEM_DATA_8 ),
.MEM_DATA_9_INOUT (MEM_DATA_9 ),
.MEM_DATA_10_INOUT (MEM_DATA_10 ),
.MEM_DATA_11_INOUT (MEM_DATA_11 ),
.MEM_DATA_12_INOUT (MEM_DATA_12 ),
.MEM_DATA_13_INOUT (MEM_DATA_13 ),
.MEM_DATA_14_INOUT (MEM_DATA_14 ),
.MEM_DATA_15_INOUT (MEM_DATA_15 ),
.MEM_OE_OUT (MEM_OE ),
.MEM_WR_OUT (MEM_WR ),
.PS2_CLK_INOUT (PS2_CLK ),
.PS2_DATA_INOUT (PS2_DATA ),
.RAM_ADV_OUT (RAM_ADV ),
.RAM_CLK_OUT (RAM_CLK ),
.RAM_CRE_OUT (RAM_CRE ),
.RAM_CS_OUT (RAM_CS ),
.RAM_LB_OUT (RAM_LB ),
.RAM_UB_OUT (RAM_UB ),
.RAM_WAIT_IN (RAM_WAIT ),
.RS232_RX_IN (RS232_TX ),
.RS232_TX_INOUT (RS232_TX ),
.SSEG_AN_0_OUT (SSEG_AN_0 ),
.SSEG_AN_1_OUT (SSEG_AN_1 ),
.SSEG_AN_2_OUT (SSEG_AN_2 ),
.SSEG_AN_3_OUT (SSEG_AN_3 ),
.SSEG_K_0_OUT (SSEG_K_0 ),
.SSEG_K_1_OUT (SSEG_K_1 ),
.SSEG_K_2_OUT (SSEG_K_2 ),
.SSEG_K_3_OUT (SSEG_K_3 ),
.SSEG_K_4_OUT (SSEG_K_4 ),
.SSEG_K_5_OUT (SSEG_K_5 ),
.SSEG_K_6_OUT (SSEG_K_6 ),
.SSEG_K_7_OUT (SSEG_K_7 ),
.SW_0_IN (SW_0 ),
.SW_1_IN (SW_1 ),
.SW_2_IN (SW_2 ),
.SW_3_IN (SW_3 ),
.SW_4_IN (SW_4 ),
.SW_5_IN (SW_5 ),
.SW_6_IN (SW_6 ),
.SW_7_IN (SW_7 ),
.USB_ADDR_0_OUT (USB_ADDR_0 ),
.USB_ADDR_1_OUT (USB_ADDR_1 ),
.USB_CLK_IN (USB_CLK ),
.USB_DATA_0_INOUT (USB_DATA_0 ),
.USB_DATA_1_INOUT (USB_DATA_1 ),
.USB_DATA_2_INOUT (USB_DATA_2 ),
.USB_DATA_3_INOUT (USB_DATA_3 ),
.USB_DATA_4_INOUT (USB_DATA_4 ),
.USB_DATA_5_INOUT (USB_DATA_5 ),
.USB_DATA_6_INOUT (USB_DATA_6 ),
.USB_DATA_7_INOUT (USB_DATA_7 ),
.USB_DIR_IN (USB_DIR ),
.USB_FLAG_IN (USB_FLAG ),
.USB_MODE_IN (USB_MODE ),
.USB_OE_OUT (USB_OE ),
.USB_PKTEND_OUT (USB_PKTEND ),
.USB_WR_OUT (USB_WR ),
.VGA_BLUE_0_OUT (VGA_BLUE_0 ),
.VGA_BLUE_1_OUT (VGA_BLUE_1 ),
.VGA_GREEN_0_OUT (VGA_GREEN_0 ),
.VGA_GREEN_1_OUT (VGA_GREEN_1 ),
.VGA_GREEN_2_OUT (VGA_GREEN_2 ),
.VGA_HSYNC_OUT (VGA_HSYNC ),
.VGA_RED_0_OUT (VGA_RED_0 ),
.VGA_RED_1_OUT (VGA_RED_1 ),
.VGA_RED_2_OUT (VGA_RED_2 ),
.VGA_VSYNC_OUT (VGA_VSYNC )
);
endmodule | module TB_FPGA_TOP (); |
reg BTN_0;
wire BTN_1 = 1'b0;
wire BTN_2 = 1'b0;
wire BTN_3 = 1'b0;
reg CLK ;
wire EPP_ASTB = 1'b0;
wire EPP_DSTB = 1'b0;
wire EPP_WAIT ;
wire FLASH_CS ;
wire FLASH_RP ;
wire FLASH_ST_STS = 1'b0;
wire LED_0 ;
wire LED_1 ;
wire LED_2 ;
wire LED_3 ;
wire LED_4 ;
wire LED_5 ;
wire LED_6 ;
wire LED_7 ;
wire MEM_ADDR_1 ;
wire MEM_ADDR_2 ;
wire MEM_ADDR_3 ;
wire MEM_ADDR_4 ;
wire MEM_ADDR_5 ;
wire MEM_ADDR_6 ;
wire MEM_ADDR_7 ;
wire MEM_ADDR_8 ;
wire MEM_ADDR_9 ;
wire MEM_ADDR_10 ;
wire MEM_ADDR_11 ;
wire MEM_ADDR_12 ;
wire MEM_ADDR_13 ;
wire MEM_ADDR_14 ;
wire MEM_ADDR_15 ;
wire MEM_ADDR_16 ;
wire MEM_ADDR_17 ;
wire MEM_ADDR_18 ;
wire MEM_ADDR_19 ;
wire MEM_ADDR_20 ;
wire MEM_ADDR_21 ;
wire MEM_ADDR_22 ;
wire MEM_ADDR_23 ;
wire MEM_DATA_0 = 1'b0;
wire MEM_DATA_1 = 1'b0;
wire MEM_DATA_2 = 1'b0;
wire MEM_DATA_3 = 1'b0;
wire MEM_DATA_4 = 1'b0;
wire MEM_DATA_5 = 1'b0;
wire MEM_DATA_6 = 1'b0;
wire MEM_DATA_7 = 1'b0;
wire MEM_DATA_8 = 1'b0;
wire MEM_DATA_9 = 1'b0;
wire MEM_DATA_10 = 1'b0;
wire MEM_DATA_11 = 1'b0;
wire MEM_DATA_12 = 1'b0;
wire MEM_DATA_13 = 1'b0;
wire MEM_DATA_14 = 1'b0;
wire MEM_DATA_15 = 1'b0;
wire MEM_OE ;
wire MEM_WR ;
wire PS2_CLK = 1'b0;
wire PS2_DATA = 1'b0;
wire RAM_ADV ;
wire RAM_CLK ;
wire RAM_CRE ;
wire RAM_CS ;
wire RAM_LB ;
wire RAM_UB ;
wire RAM_WAIT = 1'b0;
wire RS232_RX ;
wire RS232_TX ;
wire SSEG_AN_0 ;
wire SSEG_AN_1 ;
wire SSEG_AN_2 ;
wire SSEG_AN_3 ;
wire SSEG_K_0 ;
wire SSEG_K_1 ;
wire SSEG_K_2 ;
wire SSEG_K_3 ;
wire SSEG_K_4 ;
wire SSEG_K_5 ;
wire SSEG_K_6 ;
wire SSEG_K_7 ;
wire SW_0 = 1'b0;
wire SW_1 = 1'b0;
wire SW_2 = 1'b0;
wire SW_3 = 1'b0;
wire SW_4 = 1'b0;
wire SW_5 = 1'b0;
wire SW_6 = 1'b0;
wire SW_7 = 1'b0;
wire USB_ADDR_0 ;
wire USB_ADDR_1 ;
wire USB_CLK = 1'b0;
wire USB_DATA_0 = 1'b0;
wire USB_DATA_1 = 1'b0;
wire USB_DATA_2 = 1'b0;
wire USB_DATA_3 = 1'b0;
wire USB_DATA_4 = 1'b0;
wire USB_DATA_5 = 1'b0;
wire USB_DATA_6 = 1'b0;
wire USB_DATA_7 = 1'b0;
wire USB_DIR = 1'b0;
wire USB_FLAG = 1'b0;
wire USB_MODE = 1'b0;
wire USB_OE ;
wire USB_PKTEND ;
wire USB_WR ;
wire VGA_BLUE_0 ;
wire VGA_BLUE_1 ;
wire VGA_GREEN_0 ;
wire VGA_GREEN_1 ;
wire VGA_GREEN_2 ;
wire VGA_HSYNC ;
wire VGA_RED_0 ;
wire VGA_RED_1 ;
wire VGA_RED_2 ;
wire VGA_VSYNC ;
initial
begin
CLK = 1'b0;
end
always #10 CLK = !CLK;
initial
begin
BTN_0 = 1'b1;
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
@(posedge CLK);
BTN_0 = 1'b0;
end
glbl glbl ();
TESTCASE testcase();
FPGA_TOP fpga_top
(
.BTN_0_IN (BTN_0 ),
.BTN_1_IN (BTN_1 ),
.BTN_2_IN (BTN_2 ),
.BTN_3_IN (BTN_3 ),
.CLK_IN (CLK ),
.EPP_ASTB_IN (EPP_ASTB ),
.EPP_DSTB_IN (EPP_DSTB ),
.EPP_WAIT_OUT (EPP_WAIT ),
.FLASH_CS_OUT (FLASH_CS ),
.FLASH_RP_OUT (FLASH_RP ),
.FLASH_ST_STS_IN (FLASH_ST_STS ),
.LED_0_OUT (LED_0 ),
.LED_1_OUT (LED_1 ),
.LED_2_OUT (LED_2 ),
.LED_3_OUT (LED_3 ),
.LED_4_OUT (LED_4 ),
.LED_5_OUT (LED_5 ),
.LED_6_OUT (LED_6 ),
.LED_7_OUT (LED_7 ),
.MEM_ADDR_1_OUT (MEM_ADDR_1 ),
.MEM_ADDR_2_OUT (MEM_ADDR_2 ),
.MEM_ADDR_3_OUT (MEM_ADDR_3 ),
.MEM_ADDR_4_OUT (MEM_ADDR_4 ),
.MEM_ADDR_5_OUT (MEM_ADDR_5 ),
.MEM_ADDR_6_OUT (MEM_ADDR_6 ),
.MEM_ADDR_7_OUT (MEM_ADDR_7 ),
.MEM_ADDR_8_OUT (MEM_ADDR_8 ),
.MEM_ADDR_9_OUT (MEM_ADDR_9 ),
.MEM_ADDR_10_OUT (MEM_ADDR_10 ),
.MEM_ADDR_11_OUT (MEM_ADDR_11 ),
.MEM_ADDR_12_OUT (MEM_ADDR_12 ),
.MEM_ADDR_13_OUT (MEM_ADDR_13 ),
.MEM_ADDR_14_OUT (MEM_ADDR_14 ),
.MEM_ADDR_15_OUT (MEM_ADDR_15 ),
.MEM_ADDR_16_OUT (MEM_ADDR_16 ),
.MEM_ADDR_17_OUT (MEM_ADDR_17 ),
.MEM_ADDR_18_OUT (MEM_ADDR_18 ),
.MEM_ADDR_19_OUT (MEM_ADDR_19 ),
.MEM_ADDR_20_OUT (MEM_ADDR_20 ),
.MEM_ADDR_21_OUT (MEM_ADDR_21 ),
.MEM_ADDR_22_OUT (MEM_ADDR_22 ),
.MEM_ADDR_23_OUT (MEM_ADDR_23 ),
.MEM_DATA_0_INOUT (MEM_DATA_0 ),
.MEM_DATA_1_INOUT (MEM_DATA_1 ),
.MEM_DATA_2_INOUT (MEM_DATA_2 ),
.MEM_DATA_3_INOUT (MEM_DATA_3 ),
.MEM_DATA_4_INOUT (MEM_DATA_4 ),
.MEM_DATA_5_INOUT (MEM_DATA_5 ),
.MEM_DATA_6_INOUT (MEM_DATA_6 ),
.MEM_DATA_7_INOUT (MEM_DATA_7 ),
.MEM_DATA_8_INOUT (MEM_DATA_8 ),
.MEM_DATA_9_INOUT (MEM_DATA_9 ),
.MEM_DATA_10_INOUT (MEM_DATA_10 ),
.MEM_DATA_11_INOUT (MEM_DATA_11 ),
.MEM_DATA_12_INOUT (MEM_DATA_12 ),
.MEM_DATA_13_INOUT (MEM_DATA_13 ),
.MEM_DATA_14_INOUT (MEM_DATA_14 ),
.MEM_DATA_15_INOUT (MEM_DATA_15 ),
.MEM_OE_OUT (MEM_OE ),
.MEM_WR_OUT (MEM_WR ),
.PS2_CLK_INOUT (PS2_CLK ),
.PS2_DATA_INOUT (PS2_DATA ),
.RAM_ADV_OUT (RAM_ADV ),
.RAM_CLK_OUT (RAM_CLK ),
.RAM_CRE_OUT (RAM_CRE ),
.RAM_CS_OUT (RAM_CS ),
.RAM_LB_OUT (RAM_LB ),
.RAM_UB_OUT (RAM_UB ),
.RAM_WAIT_IN (RAM_WAIT ),
.RS232_RX_IN (RS232_TX ),
.RS232_TX_INOUT (RS232_TX ),
.SSEG_AN_0_OUT (SSEG_AN_0 ),
.SSEG_AN_1_OUT (SSEG_AN_1 ),
.SSEG_AN_2_OUT (SSEG_AN_2 ),
.SSEG_AN_3_OUT (SSEG_AN_3 ),
.SSEG_K_0_OUT (SSEG_K_0 ),
.SSEG_K_1_OUT (SSEG_K_1 ),
.SSEG_K_2_OUT (SSEG_K_2 ),
.SSEG_K_3_OUT (SSEG_K_3 ),
.SSEG_K_4_OUT (SSEG_K_4 ),
.SSEG_K_5_OUT (SSEG_K_5 ),
.SSEG_K_6_OUT (SSEG_K_6 ),
.SSEG_K_7_OUT (SSEG_K_7 ),
.SW_0_IN (SW_0 ),
.SW_1_IN (SW_1 ),
.SW_2_IN (SW_2 ),
.SW_3_IN (SW_3 ),
.SW_4_IN (SW_4 ),
.SW_5_IN (SW_5 ),
.SW_6_IN (SW_6 ),
.SW_7_IN (SW_7 ),
.USB_ADDR_0_OUT (USB_ADDR_0 ),
.USB_ADDR_1_OUT (USB_ADDR_1 ),
.USB_CLK_IN (USB_CLK ),
.USB_DATA_0_INOUT (USB_DATA_0 ),
.USB_DATA_1_INOUT (USB_DATA_1 ),
.USB_DATA_2_INOUT (USB_DATA_2 ),
.USB_DATA_3_INOUT (USB_DATA_3 ),
.USB_DATA_4_INOUT (USB_DATA_4 ),
.USB_DATA_5_INOUT (USB_DATA_5 ),
.USB_DATA_6_INOUT (USB_DATA_6 ),
.USB_DATA_7_INOUT (USB_DATA_7 ),
.USB_DIR_IN (USB_DIR ),
.USB_FLAG_IN (USB_FLAG ),
.USB_MODE_IN (USB_MODE ),
.USB_OE_OUT (USB_OE ),
.USB_PKTEND_OUT (USB_PKTEND ),
.USB_WR_OUT (USB_WR ),
.VGA_BLUE_0_OUT (VGA_BLUE_0 ),
.VGA_BLUE_1_OUT (VGA_BLUE_1 ),
.VGA_GREEN_0_OUT (VGA_GREEN_0 ),
.VGA_GREEN_1_OUT (VGA_GREEN_1 ),
.VGA_GREEN_2_OUT (VGA_GREEN_2 ),
.VGA_HSYNC_OUT (VGA_HSYNC ),
.VGA_RED_0_OUT (VGA_RED_0 ),
.VGA_RED_1_OUT (VGA_RED_1 ),
.VGA_RED_2_OUT (VGA_RED_2 ),
.VGA_VSYNC_OUT (VGA_VSYNC )
);
endmodule | 1 |
138,342 | data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v | 83,270,534 | testcase.v | v | 105 | 133 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:3: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:18: Define or directive not defined: \'`TB\'\n $readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:18: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n $readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:21: Define or directive not defined: \'`RST\'\n while (`RST)\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n while (`RST)\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:22: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:30: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB \n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:30: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n while (!(`TB.DATA_CYC && `TB.DATA_STB \n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:30: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB \n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:31: Define or directive not defined: \'`TB\'\n && !`TB.DATA_WE && (32\'h0000_0010 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:31: Define or directive not defined: \'`TB\'\n && !`TB.DATA_WE && (32\'h0000_0010 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:32: Define or directive not defined: \'`CLK\'\n @(negedge `CLK);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:36: Define or directive not defined: \'`TB\'\n force `TB.DATA_STALL = 1\'b1;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:36: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n force `TB.DATA_STALL = 1\'b1;\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:37: Define or directive not defined: \'`TB\'\n force `TB.DATA_ACK = 1\'b0;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:38: Define or directive not defined: \'`TB\'\n force `TB.DATA_ERR = 1\'b0;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:40: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:41: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:43: Define or directive not defined: \'`TB\'\n force `TB.DATA_STALL = 1\'b0;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:43: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n force `TB.DATA_STALL = 1\'b0;\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:44: Define or directive not defined: \'`TB\'\n force `TB.DATA_ERR = 1\'b1;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:46: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:47: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:48: Define or directive not defined: \'`TB\'\n force `TB.DATA_ACK = 1\'b0;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:48: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n force `TB.DATA_ACK = 1\'b0;\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:49: Define or directive not defined: \'`TB\'\n force `TB.DATA_ERR = 1\'b0;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:52: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:52: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n while (!(`TB.DATA_CYC && `TB.DATA_STB))\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:52: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:53: Define or directive not defined: \'`CLK\'\n @(negedge `CLK);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:57: Define or directive not defined: \'`TB\'\n release `TB.DATA_STALL;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:57: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n release `TB.DATA_STALL;\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:58: Define or directive not defined: \'`TB\'\n release `TB.DATA_ACK ;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:59: Define or directive not defined: \'`TB\'\n release `TB.DATA_ERR ;\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:61: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:61: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:61: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:61: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:62: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:66: Define or directive not defined: \'`TB\'\n if (32\'d0 == `TB.DATA_DAT_WR) \n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:66: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n if (32\'d0 == `TB.DATA_DAT_WR) \n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:72: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:75: Define or directive not defined: \'`TB\'\n $display("[FAIL ] TEST FAILED with %d errors at time %t", `TB.DATA_DAT_WR, $time);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:81: Define or directive not defined: \'`TB\'\n $writememh("inst_mem_dump.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:82: Define or directive not defined: \'`TB\'\n $writememh("data_mem_dump.hex", `TB.data_wb_slave_bfm.MemArray);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:88: syntax error, unexpected $fwrite\n $fwrite(regFile, "%h\\n", `TB.cpu_core.RegArray[regLoop]);\n ^~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:88: Define or directive not defined: \'`TB\'\n $fwrite(regFile, "%h\\n", `TB.cpu_core.RegArray[regLoop]);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:90: Define or directive not defined: \'`TB\'\n $fwrite(regFile, "%h\\n", `TB.cpu_core.LoVal);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/dbe/testcase.v:91: Define or directive not defined: \'`TB\'\n $fwrite(regFile, "%h\\n", `TB.cpu_core.HiVal);\n ^~~\n%Error: Cannot continue\n' | 302,192 | module | module TESTCASE ();
`include "tb_defines.v"
integer progLoop = 0;
integer regLoop = 0;
integer regFile;
initial
begin : main_test
$readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);
while (`RST)
@(posedge `CLK);
$display("[INFO ] Out of reset at time %t", $time);
while (!(`TB.DATA_CYC && `TB.DATA_STB
&& !`TB.DATA_WE && (32'h0000_0010 == `TB.DATA_ADR)))
@(negedge `CLK);
$display("[INFO ] Detected data read to address 0x10, stalling a couple of cycles and forcing a bus exception at time %t", $time);
#1;
force `TB.DATA_STALL = 1'b1;
force `TB.DATA_ACK = 1'b0;
force `TB.DATA_ERR = 1'b0;
@(posedge `CLK);
@(posedge `CLK);
#1;
force `TB.DATA_STALL = 1'b0;
force `TB.DATA_ERR = 1'b1;
@(posedge `CLK);
#1;
force `TB.DATA_ACK = 1'b0;
force `TB.DATA_ERR = 1'b0;
while (!(`TB.DATA_CYC && `TB.DATA_STB))
@(negedge `CLK);
#1;
$display("[INFO ] Releasing forces on data at time %t", $time);
release `TB.DATA_STALL;
release `TB.DATA_ACK ;
release `TB.DATA_ERR ;
while (!(`TB.DATA_CYC && `TB.DATA_STB && (32'h0000_0000 == `TB.DATA_ADR)))
@(posedge `CLK);
$display("[INFO ] Detected data write to 0, checking result at time %t", $time);
if (32'd0 == `TB.DATA_DAT_WR)
begin
$display("");
$display("[PASS ] TEST PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] TEST FAILED with %d errors at time %t", `TB.DATA_DAT_WR, $time);
$display("");
end
$display("INFO: Dumping register and memory hex files at time $t", $time);
$writememh("inst_mem_dump.hex", `TB.inst_wb_slave_bfm.MemArray);
$writememh("data_mem_dump.hex", `TB.data_wb_slave_bfm.MemArray);
regFile = $fopen("regfile_dump.hex", "w");
for (regLoop = 0 ; regLoop < 32 ; regLoop = regLoop + 1)
begin
$fwrite(regFile, "%h\n", `TB.cpu_core.RegArray[regLoop]);
end
$fwrite(regFile, "%h\n", `TB.cpu_core.LoVal);
$fwrite(regFile, "%h\n", `TB.cpu_core.HiVal);
$fclose (regFile);
$finish();
end
endmodule | module TESTCASE (); |
`include "tb_defines.v"
integer progLoop = 0;
integer regLoop = 0;
integer regFile;
initial
begin : main_test
$readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);
while (`RST)
@(posedge `CLK);
$display("[INFO ] Out of reset at time %t", $time);
while (!(`TB.DATA_CYC && `TB.DATA_STB
&& !`TB.DATA_WE && (32'h0000_0010 == `TB.DATA_ADR)))
@(negedge `CLK);
$display("[INFO ] Detected data read to address 0x10, stalling a couple of cycles and forcing a bus exception at time %t", $time);
#1;
force `TB.DATA_STALL = 1'b1;
force `TB.DATA_ACK = 1'b0;
force `TB.DATA_ERR = 1'b0;
@(posedge `CLK);
@(posedge `CLK);
#1;
force `TB.DATA_STALL = 1'b0;
force `TB.DATA_ERR = 1'b1;
@(posedge `CLK);
#1;
force `TB.DATA_ACK = 1'b0;
force `TB.DATA_ERR = 1'b0;
while (!(`TB.DATA_CYC && `TB.DATA_STB))
@(negedge `CLK);
#1;
$display("[INFO ] Releasing forces on data at time %t", $time);
release `TB.DATA_STALL;
release `TB.DATA_ACK ;
release `TB.DATA_ERR ;
while (!(`TB.DATA_CYC && `TB.DATA_STB && (32'h0000_0000 == `TB.DATA_ADR)))
@(posedge `CLK);
$display("[INFO ] Detected data write to 0, checking result at time %t", $time);
if (32'd0 == `TB.DATA_DAT_WR)
begin
$display("");
$display("[PASS ] TEST PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] TEST FAILED with %d errors at time %t", `TB.DATA_DAT_WR, $time);
$display("");
end
$display("INFO: Dumping register and memory hex files at time $t", $time);
$writememh("inst_mem_dump.hex", `TB.inst_wb_slave_bfm.MemArray);
$writememh("data_mem_dump.hex", `TB.data_wb_slave_bfm.MemArray);
regFile = $fopen("regfile_dump.hex", "w");
for (regLoop = 0 ; regLoop < 32 ; regLoop = regLoop + 1)
begin
$fwrite(regFile, "%h\n", `TB.cpu_core.RegArray[regLoop]);
end
$fwrite(regFile, "%h\n", `TB.cpu_core.LoVal);
$fwrite(regFile, "%h\n", `TB.cpu_core.HiVal);
$fclose (regFile);
$finish();
end
endmodule | 1 |
138,345 | data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v | 83,270,534 | testcase.v | v | 71 | 101 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:3: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:18: Define or directive not defined: \'`TB\'\n $readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:18: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n $readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:21: Define or directive not defined: \'`RST\'\n while (`RST)\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n while (`RST)\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:22: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:27: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:27: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:27: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:27: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:28: Define or directive not defined: \'`TB\'\n @(posedge `TB.Clk);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:32: Define or directive not defined: \'`TB\'\n if (32\'d0 == `TB.DATA_DAT_WR) \n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:32: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n if (32\'d0 == `TB.DATA_DAT_WR) \n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:38: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:41: Define or directive not defined: \'`TB\'\n $display("[FAIL ] TEST FAILED with %d errors at time %t", `TB.DATA_DAT_WR, $time);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:47: Define or directive not defined: \'`TB\'\n $writememh("inst_mem_dump.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:48: Define or directive not defined: \'`TB\'\n $writememh("data_mem_dump.hex", `TB.data_wb_slave_bfm.MemArray);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:54: syntax error, unexpected $fwrite\n $fwrite(regFile, "%h\\n", `TB.cpu_core.RegArray[regLoop]);\n ^~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:54: Define or directive not defined: \'`TB\'\n $fwrite(regFile, "%h\\n", `TB.cpu_core.RegArray[regLoop]);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:56: Define or directive not defined: \'`TB\'\n $fwrite(regFile, "%h\\n", `TB.cpu_core.LoVal);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/exceptions/ovf/testcase.v:57: Define or directive not defined: \'`TB\'\n $fwrite(regFile, "%h\\n", `TB.cpu_core.HiVal);\n ^~~\n%Error: Cannot continue\n' | 302,196 | module | module TESTCASE ();
`include "tb_defines.v"
integer progLoop = 0;
integer regLoop = 0;
integer regFile;
initial
begin : main_test
$readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);
while (`RST)
@(posedge `CLK);
$display("[INFO ] Out of reset at time %t", $time);
while (!(`TB.DATA_CYC && `TB.DATA_STB && (32'h0000_0000 == `TB.DATA_ADR)))
@(posedge `TB.Clk);
$display("[INFO ] Detected data write, checking value at time %t", $time);
if (32'd0 == `TB.DATA_DAT_WR)
begin
$display("");
$display("[PASS ] TEST PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] TEST FAILED with %d errors at time %t", `TB.DATA_DAT_WR, $time);
$display("");
end
$display("INFO: Dumping register and memory hex files at time $t", $time);
$writememh("inst_mem_dump.hex", `TB.inst_wb_slave_bfm.MemArray);
$writememh("data_mem_dump.hex", `TB.data_wb_slave_bfm.MemArray);
regFile = $fopen("regfile_dump.hex", "w");
for (regLoop = 0 ; regLoop < 32 ; regLoop = regLoop + 1)
begin
$fwrite(regFile, "%h\n", `TB.cpu_core.RegArray[regLoop]);
end
$fwrite(regFile, "%h\n", `TB.cpu_core.LoVal);
$fwrite(regFile, "%h\n", `TB.cpu_core.HiVal);
$fclose (regFile);
$finish();
end
endmodule | module TESTCASE (); |
`include "tb_defines.v"
integer progLoop = 0;
integer regLoop = 0;
integer regFile;
initial
begin : main_test
$readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);
while (`RST)
@(posedge `CLK);
$display("[INFO ] Out of reset at time %t", $time);
while (!(`TB.DATA_CYC && `TB.DATA_STB && (32'h0000_0000 == `TB.DATA_ADR)))
@(posedge `TB.Clk);
$display("[INFO ] Detected data write, checking value at time %t", $time);
if (32'd0 == `TB.DATA_DAT_WR)
begin
$display("");
$display("[PASS ] TEST PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] TEST FAILED with %d errors at time %t", `TB.DATA_DAT_WR, $time);
$display("");
end
$display("INFO: Dumping register and memory hex files at time $t", $time);
$writememh("inst_mem_dump.hex", `TB.inst_wb_slave_bfm.MemArray);
$writememh("data_mem_dump.hex", `TB.data_wb_slave_bfm.MemArray);
regFile = $fopen("regfile_dump.hex", "w");
for (regLoop = 0 ; regLoop < 32 ; regLoop = regLoop + 1)
begin
$fwrite(regFile, "%h\n", `TB.cpu_core.RegArray[regLoop]);
end
$fwrite(regFile, "%h\n", `TB.cpu_core.LoVal);
$fwrite(regFile, "%h\n", `TB.cpu_core.HiVal);
$fclose (regFile);
$finish();
end
endmodule | 1 |
138,347 | data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v | 83,270,534 | testcase.v | v | 44 | 92 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:3: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:13: Define or directive not defined: \'`TB\'\n $readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:13: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n $readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:16: Define or directive not defined: \'`RST\'\n while (`RST)\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:16: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n while (`RST)\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:17: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:22: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && `TB.DATA_WE && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:22: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n while (!(`TB.DATA_CYC && `TB.DATA_STB && `TB.DATA_WE && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:22: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && `TB.DATA_WE && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:22: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && `TB.DATA_WE && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:22: Define or directive not defined: \'`TB\'\n while (!(`TB.DATA_CYC && `TB.DATA_STB && `TB.DATA_WE && (32\'h0000_0000 == `TB.DATA_ADR)))\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:23: Define or directive not defined: \'`TB\'\n @(posedge `TB.Clk);\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:27: Define or directive not defined: \'`TB\'\n if (32\'d1 == `TB.DATA_DAT_WR) \n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:27: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n if (32\'d1 == `TB.DATA_DAT_WR) \n ^\n%Error: data/full_repos/permissive/83270534/mips1_cop0/sim/instructions/lswcz/testcase.v:34: syntax error, unexpected else\n else\n ^~~~\n%Error: Cannot continue\n' | 302,200 | module | module TESTCASE ();
`include "tb_defines.v"
initial
begin
$display("[INFO ] Loading test into instruction BFM at time %t", $time);
$readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);
while (`RST)
@(posedge `CLK);
$display("[INFO ] Out of reset at time %t", $time);
while (!(`TB.DATA_CYC && `TB.DATA_STB && `TB.DATA_WE && (32'h0000_0000 == `TB.DATA_ADR)))
@(posedge `TB.Clk);
$display("[INFO ] Detected data write, checking value at time %t", $time);
if (32'd1 == `TB.DATA_DAT_WR)
begin
$display("");
$display("[PASS ] TEST PASSED at time %t", $time);
$display("");
$finish();
end
else
begin
$display("");
$display("[FAIL ] TEST FAILED at time %t", $time);
$display("");
$finish();
end
end
endmodule | module TESTCASE (); |
`include "tb_defines.v"
initial
begin
$display("[INFO ] Loading test into instruction BFM at time %t", $time);
$readmemh ("testcase.hex", `TB.inst_wb_slave_bfm.MemArray);
while (`RST)
@(posedge `CLK);
$display("[INFO ] Out of reset at time %t", $time);
while (!(`TB.DATA_CYC && `TB.DATA_STB && `TB.DATA_WE && (32'h0000_0000 == `TB.DATA_ADR)))
@(posedge `TB.Clk);
$display("[INFO ] Detected data write, checking value at time %t", $time);
if (32'd1 == `TB.DATA_DAT_WR)
begin
$display("");
$display("[PASS ] TEST PASSED at time %t", $time);
$display("");
$finish();
end
else
begin
$display("");
$display("[FAIL ] TEST FAILED at time %t", $time);
$display("");
$finish();
end
end
endmodule | 1 |
138,348 | data/full_repos/permissive/83270534/mips1_cop0/tb/tb_top.v | 83,270,534 | tb_top.v | v | 393 | 134 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_cop0/tb/tb_top.v:13: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_cop0/tb,data/full_repos/permissive/83270534/cpu_defs.v\n data/full_repos/permissive/83270534/mips1_cop0/tb,data/full_repos/permissive/83270534/cpu_defs.v.v\n data/full_repos/permissive/83270534/mips1_cop0/tb,data/full_repos/permissive/83270534/cpu_defs.v.sv\n cpu_defs.v\n cpu_defs.v.v\n cpu_defs.v.sv\n obj_dir/cpu_defs.v\n obj_dir/cpu_defs.v.v\n obj_dir/cpu_defs.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_cop0/tb/tb_top.v:92: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, " ns", 5);\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_cop0/tb/tb_top.v:103: Unsupported: Ignoring delay on this delayed statement.\n #RST_SYNC_TIME RstSync = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_cop0/tb/tb_top.v:106: Unsupported: Ignoring delay on this delayed statement.\n always #CLK_HALF_PERIOD Clk = !Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_cop0/tb/tb_top.v:114: Unsupported: Ignoring delay on this delayed statement.\n #10_000;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 302,204 | module | module TB_TOP
(
);
`define TESTSTR "code.hex"
`include "cpu_defs.v"
parameter CLK_HALF_PERIOD = 5;
parameter RST_SYNC_TIME = (3 * CLK_HALF_PERIOD) + 1;
integer regFile;
integer regLoop;
reg Clk;
reg RstSync;
wire [31:0] INST_ADR ;
wire INST_CYC ;
wire INST_STB ;
wire INST_WE ;
wire [ 3:0] INST_SEL ;
wire [ 2:0] INST_CTI ;
wire [ 1:0] INST_BTE ;
wire INST_ACK ;
wire INST_STALL ;
wire INST_ERR ;
wire [31:0] INST_DAT_RD ;
wire [31:0] INST_DAT_WR ;
wire [31:0] DATA_ADR ;
wire DATA_CYC ;
wire DATA_STB ;
wire DATA_WE ;
wire [ 3:0] DATA_SEL ;
wire [ 2:0] DATA_CTI ;
wire [ 1:0] DATA_BTE ;
wire DATA_ACK ;
wire DATA_STALL ;
wire DATA_ERR ;
wire [31:0] DATA_DAT_RD ;
wire [31:0] DATA_DAT_WR ;
wire COP0_INST_EN ;
wire [4:0] COP0_INST ;
wire COP0_RD_EN ;
wire COP0_RD_CTRL_SEL ;
wire [4:0] COP0_RD_SEL ;
wire [31:0] COP0_RD_DATA ;
wire COP0_WR_EN ;
wire COP0_WR_CTRL_SEL ;
wire [4:0] COP0_WR_SEL ;
wire [31:0] COP0_WR_DATA ;
wire [5:0] HW_IRQ = 6'b000000;
wire COUNT_IRQ ;
wire [3:0] COP_USABLE ;
wire COP0_INT ;
wire CORE_EXC_EN ;
wire [1:0] CORE_EXC_CE ;
wire [4:0] CORE_EXC_CODE ;
wire CORE_EXC_BD ;
wire [31:0] CORE_EXC_EPC ;
wire [31:0] CORE_EXC_BADVA ;
wire [31:0] CORE_EXC_VECTOR ;
wire CACHE_ISO ;
wire CACHE_SWAP ;
wire CACHE_MISS ;
initial
begin
$timeformat(-9, 0, " ns", 5);
end
initial
begin
Clk = 1'b0;
RstSync = 1'b1;
#RST_SYNC_TIME RstSync = 1'b0;
end
always #CLK_HALF_PERIOD Clk = !Clk;
initial
begin
#10_000;
$display("[FAIL ] Watchdog timeout at time %t", $time);
$finish();
end
TESTCASE testcase ();
parameter IMEM_SIZE_P2 = 10;
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (1),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (IMEM_SIZE_P2),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
inst_wb_slave_bfm
(
.CLK (Clk),
.RST_SYNC (RstSync),
.WB_ADR_IN ({ {(32 - IMEM_SIZE_P2){1'b0}} , INST_ADR[IMEM_SIZE_P2-1:0]}),
.WB_CYC_IN (INST_CYC ),
.WB_STB_IN (INST_STB ),
.WB_WE_IN (INST_WE ),
.WB_SEL_IN (INST_SEL ),
.WB_CTI_IN (INST_CTI ),
.WB_BTE_IN (INST_BTE ),
.WB_STALL_OUT (INST_STALL ),
.WB_ACK_OUT (INST_ACK ),
.WB_ERR_OUT (INST_ERR ),
.WB_DAT_RD_OUT (INST_DAT_RD ),
.WB_DAT_WR_IN (INST_DAT_WR )
);
parameter DMEM_SIZE_P2 = 10;
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (DMEM_SIZE_P2),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
data_wb_slave_bfm
(
.CLK (Clk),
.RST_SYNC (RstSync),
.WB_ADR_IN ({ {(32 - DMEM_SIZE_P2){1'b0}} , DATA_ADR[DMEM_SIZE_P2-1:0]}),
.WB_CYC_IN (DATA_CYC ),
.WB_STB_IN (DATA_STB ),
.WB_WE_IN (DATA_WE ),
.WB_SEL_IN (DATA_SEL ),
.WB_CTI_IN (DATA_CTI ),
.WB_BTE_IN (DATA_BTE ),
.WB_STALL_OUT (DATA_STALL ),
.WB_ACK_OUT (DATA_ACK ),
.WB_ERR_OUT (DATA_ERR ),
.WB_DAT_RD_OUT (DATA_DAT_RD ),
.WB_DAT_WR_IN (DATA_DAT_WR )
);
CPU_CORE
#(.PC_RST_VALUE (32'hbfc0_0000))
cpu_core
(
.CLK (Clk),
.RST_SYNC (RstSync),
.CORE_INST_ADR_OUT (INST_ADR ),
.CORE_INST_CYC_OUT (INST_CYC ),
.CORE_INST_STB_OUT (INST_STB ),
.CORE_INST_WE_OUT (INST_WE ),
.CORE_INST_SEL_OUT (INST_SEL ),
.CORE_INST_CTI_OUT (INST_CTI ),
.CORE_INST_BTE_OUT (INST_BTE ),
.CORE_INST_ACK_IN (INST_ACK ),
.CORE_INST_STALL_IN (INST_STALL ),
.CORE_INST_ERR_IN (INST_ERR ),
.CORE_INST_DAT_RD_IN (INST_DAT_RD ),
.CORE_INST_DAT_WR_OUT (INST_DAT_WR ),
.CORE_DATA_ADR_OUT (DATA_ADR ),
.CORE_DATA_CYC_OUT (DATA_CYC ),
.CORE_DATA_STB_OUT (DATA_STB ),
.CORE_DATA_WE_OUT (DATA_WE ),
.CORE_DATA_SEL_OUT (DATA_SEL ),
.CORE_DATA_CTI_OUT (DATA_CTI ),
.CORE_DATA_BTE_OUT (DATA_BTE ),
.CORE_DATA_ACK_IN (DATA_ACK ),
.CORE_DATA_STALL_IN (DATA_STALL ),
.CORE_DATA_ERR_IN (DATA_ERR ),
.CORE_DATA_DAT_RD_IN (DATA_DAT_RD ),
.CORE_DATA_DAT_WR_OUT (DATA_DAT_WR ),
.COP0_INST_EN_OUT (COP0_INST_EN ),
.COP0_INST_OUT (COP0_INST ),
.COP0_RD_EN_OUT (COP0_RD_EN ),
.COP0_RD_CTRL_SEL_OUT (COP0_RD_CTRL_SEL ),
.COP0_RD_SEL_OUT (COP0_RD_SEL ),
.COP0_RD_DATA_IN (COP0_RD_DATA ),
.COP0_WR_EN_OUT (COP0_WR_EN ),
.COP0_WR_CTRL_SEL_OUT (COP0_WR_CTRL_SEL ),
.COP0_WR_SEL_OUT (COP0_WR_SEL ),
.COP0_WR_DATA_OUT (COP0_WR_DATA ),
.COP_USABLE_IN (COP_USABLE ),
.COP0_INT_IN (COP0_INT ),
.CORE_EXC_EN_OUT (CORE_EXC_EN ),
.CORE_EXC_CE_OUT (CORE_EXC_CE ),
.CORE_EXC_CODE_OUT (CORE_EXC_CODE ),
.CORE_EXC_BD_OUT (CORE_EXC_BD ),
.CORE_EXC_EPC_OUT (CORE_EXC_EPC ),
.CORE_EXC_BADVA_OUT (CORE_EXC_BADVA ),
.CORE_EXC_VECTOR_IN (CORE_EXC_VECTOR )
);
COP0 cop0
(
.CLK (Clk),
.RST_SYNC (RstSync),
.COP0_INST_EN_IN (COP0_INST_EN ),
.COP0_INST_IN (COP0_INST ),
.COP0_RD_EN_IN (COP0_RD_EN ),
.COP0_RD_CTRL_SEL_IN (COP0_RD_CTRL_SEL ),
.COP0_RD_SEL_IN (COP0_RD_SEL ),
.COP0_RD_DATA_OUT (COP0_RD_DATA ),
.COP0_WR_EN_IN (COP0_WR_EN ),
.COP0_WR_CTRL_SEL_IN (COP0_WR_CTRL_SEL ),
.COP0_WR_SEL_IN (COP0_WR_SEL ),
.COP0_WR_DATA_IN (COP0_WR_DATA ),
.HW_IRQ_IN (HW_IRQ ),
.COUNT_IRQ_OUT (COUNT_IRQ ),
.COP_USABLE_OUT (COP_USABLE ),
.COP0_INT_OUT (COP0_INT ),
.CORE_EXC_EN_IN (CORE_EXC_EN ),
.CORE_EXC_CE_IN (CORE_EXC_CE ),
.CORE_EXC_CODE_IN (CORE_EXC_CODE ),
.CORE_EXC_BD_IN (CORE_EXC_BD ),
.CORE_EXC_EPC_IN (CORE_EXC_EPC ),
.CORE_EXC_BADVA_IN (CORE_EXC_BADVA ),
.CORE_EXC_VECTOR_OUT (CORE_EXC_VECTOR ),
.CACHE_ISO_OUT (CACHE_ISO ),
.CACHE_SWAP_OUT (CACHE_SWAP ),
.CACHE_MISS_IN (CACHE_MISS )
);
endmodule | module TB_TOP
(
); |
`define TESTSTR "code.hex"
`include "cpu_defs.v"
parameter CLK_HALF_PERIOD = 5;
parameter RST_SYNC_TIME = (3 * CLK_HALF_PERIOD) + 1;
integer regFile;
integer regLoop;
reg Clk;
reg RstSync;
wire [31:0] INST_ADR ;
wire INST_CYC ;
wire INST_STB ;
wire INST_WE ;
wire [ 3:0] INST_SEL ;
wire [ 2:0] INST_CTI ;
wire [ 1:0] INST_BTE ;
wire INST_ACK ;
wire INST_STALL ;
wire INST_ERR ;
wire [31:0] INST_DAT_RD ;
wire [31:0] INST_DAT_WR ;
wire [31:0] DATA_ADR ;
wire DATA_CYC ;
wire DATA_STB ;
wire DATA_WE ;
wire [ 3:0] DATA_SEL ;
wire [ 2:0] DATA_CTI ;
wire [ 1:0] DATA_BTE ;
wire DATA_ACK ;
wire DATA_STALL ;
wire DATA_ERR ;
wire [31:0] DATA_DAT_RD ;
wire [31:0] DATA_DAT_WR ;
wire COP0_INST_EN ;
wire [4:0] COP0_INST ;
wire COP0_RD_EN ;
wire COP0_RD_CTRL_SEL ;
wire [4:0] COP0_RD_SEL ;
wire [31:0] COP0_RD_DATA ;
wire COP0_WR_EN ;
wire COP0_WR_CTRL_SEL ;
wire [4:0] COP0_WR_SEL ;
wire [31:0] COP0_WR_DATA ;
wire [5:0] HW_IRQ = 6'b000000;
wire COUNT_IRQ ;
wire [3:0] COP_USABLE ;
wire COP0_INT ;
wire CORE_EXC_EN ;
wire [1:0] CORE_EXC_CE ;
wire [4:0] CORE_EXC_CODE ;
wire CORE_EXC_BD ;
wire [31:0] CORE_EXC_EPC ;
wire [31:0] CORE_EXC_BADVA ;
wire [31:0] CORE_EXC_VECTOR ;
wire CACHE_ISO ;
wire CACHE_SWAP ;
wire CACHE_MISS ;
initial
begin
$timeformat(-9, 0, " ns", 5);
end
initial
begin
Clk = 1'b0;
RstSync = 1'b1;
#RST_SYNC_TIME RstSync = 1'b0;
end
always #CLK_HALF_PERIOD Clk = !Clk;
initial
begin
#10_000;
$display("[FAIL ] Watchdog timeout at time %t", $time);
$finish();
end
TESTCASE testcase ();
parameter IMEM_SIZE_P2 = 10;
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (1),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (IMEM_SIZE_P2),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
inst_wb_slave_bfm
(
.CLK (Clk),
.RST_SYNC (RstSync),
.WB_ADR_IN ({ {(32 - IMEM_SIZE_P2){1'b0}} , INST_ADR[IMEM_SIZE_P2-1:0]}),
.WB_CYC_IN (INST_CYC ),
.WB_STB_IN (INST_STB ),
.WB_WE_IN (INST_WE ),
.WB_SEL_IN (INST_SEL ),
.WB_CTI_IN (INST_CTI ),
.WB_BTE_IN (INST_BTE ),
.WB_STALL_OUT (INST_STALL ),
.WB_ACK_OUT (INST_ACK ),
.WB_ERR_OUT (INST_ERR ),
.WB_DAT_RD_OUT (INST_DAT_RD ),
.WB_DAT_WR_IN (INST_DAT_WR )
);
parameter DMEM_SIZE_P2 = 10;
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (DMEM_SIZE_P2),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
data_wb_slave_bfm
(
.CLK (Clk),
.RST_SYNC (RstSync),
.WB_ADR_IN ({ {(32 - DMEM_SIZE_P2){1'b0}} , DATA_ADR[DMEM_SIZE_P2-1:0]}),
.WB_CYC_IN (DATA_CYC ),
.WB_STB_IN (DATA_STB ),
.WB_WE_IN (DATA_WE ),
.WB_SEL_IN (DATA_SEL ),
.WB_CTI_IN (DATA_CTI ),
.WB_BTE_IN (DATA_BTE ),
.WB_STALL_OUT (DATA_STALL ),
.WB_ACK_OUT (DATA_ACK ),
.WB_ERR_OUT (DATA_ERR ),
.WB_DAT_RD_OUT (DATA_DAT_RD ),
.WB_DAT_WR_IN (DATA_DAT_WR )
);
CPU_CORE
#(.PC_RST_VALUE (32'hbfc0_0000))
cpu_core
(
.CLK (Clk),
.RST_SYNC (RstSync),
.CORE_INST_ADR_OUT (INST_ADR ),
.CORE_INST_CYC_OUT (INST_CYC ),
.CORE_INST_STB_OUT (INST_STB ),
.CORE_INST_WE_OUT (INST_WE ),
.CORE_INST_SEL_OUT (INST_SEL ),
.CORE_INST_CTI_OUT (INST_CTI ),
.CORE_INST_BTE_OUT (INST_BTE ),
.CORE_INST_ACK_IN (INST_ACK ),
.CORE_INST_STALL_IN (INST_STALL ),
.CORE_INST_ERR_IN (INST_ERR ),
.CORE_INST_DAT_RD_IN (INST_DAT_RD ),
.CORE_INST_DAT_WR_OUT (INST_DAT_WR ),
.CORE_DATA_ADR_OUT (DATA_ADR ),
.CORE_DATA_CYC_OUT (DATA_CYC ),
.CORE_DATA_STB_OUT (DATA_STB ),
.CORE_DATA_WE_OUT (DATA_WE ),
.CORE_DATA_SEL_OUT (DATA_SEL ),
.CORE_DATA_CTI_OUT (DATA_CTI ),
.CORE_DATA_BTE_OUT (DATA_BTE ),
.CORE_DATA_ACK_IN (DATA_ACK ),
.CORE_DATA_STALL_IN (DATA_STALL ),
.CORE_DATA_ERR_IN (DATA_ERR ),
.CORE_DATA_DAT_RD_IN (DATA_DAT_RD ),
.CORE_DATA_DAT_WR_OUT (DATA_DAT_WR ),
.COP0_INST_EN_OUT (COP0_INST_EN ),
.COP0_INST_OUT (COP0_INST ),
.COP0_RD_EN_OUT (COP0_RD_EN ),
.COP0_RD_CTRL_SEL_OUT (COP0_RD_CTRL_SEL ),
.COP0_RD_SEL_OUT (COP0_RD_SEL ),
.COP0_RD_DATA_IN (COP0_RD_DATA ),
.COP0_WR_EN_OUT (COP0_WR_EN ),
.COP0_WR_CTRL_SEL_OUT (COP0_WR_CTRL_SEL ),
.COP0_WR_SEL_OUT (COP0_WR_SEL ),
.COP0_WR_DATA_OUT (COP0_WR_DATA ),
.COP_USABLE_IN (COP_USABLE ),
.COP0_INT_IN (COP0_INT ),
.CORE_EXC_EN_OUT (CORE_EXC_EN ),
.CORE_EXC_CE_OUT (CORE_EXC_CE ),
.CORE_EXC_CODE_OUT (CORE_EXC_CODE ),
.CORE_EXC_BD_OUT (CORE_EXC_BD ),
.CORE_EXC_EPC_OUT (CORE_EXC_EPC ),
.CORE_EXC_BADVA_OUT (CORE_EXC_BADVA ),
.CORE_EXC_VECTOR_IN (CORE_EXC_VECTOR )
);
COP0 cop0
(
.CLK (Clk),
.RST_SYNC (RstSync),
.COP0_INST_EN_IN (COP0_INST_EN ),
.COP0_INST_IN (COP0_INST ),
.COP0_RD_EN_IN (COP0_RD_EN ),
.COP0_RD_CTRL_SEL_IN (COP0_RD_CTRL_SEL ),
.COP0_RD_SEL_IN (COP0_RD_SEL ),
.COP0_RD_DATA_OUT (COP0_RD_DATA ),
.COP0_WR_EN_IN (COP0_WR_EN ),
.COP0_WR_CTRL_SEL_IN (COP0_WR_CTRL_SEL ),
.COP0_WR_SEL_IN (COP0_WR_SEL ),
.COP0_WR_DATA_IN (COP0_WR_DATA ),
.HW_IRQ_IN (HW_IRQ ),
.COUNT_IRQ_OUT (COUNT_IRQ ),
.COP_USABLE_OUT (COP_USABLE ),
.COP0_INT_OUT (COP0_INT ),
.CORE_EXC_EN_IN (CORE_EXC_EN ),
.CORE_EXC_CE_IN (CORE_EXC_CE ),
.CORE_EXC_CODE_IN (CORE_EXC_CODE ),
.CORE_EXC_BD_IN (CORE_EXC_BD ),
.CORE_EXC_EPC_IN (CORE_EXC_EPC ),
.CORE_EXC_BADVA_IN (CORE_EXC_BADVA ),
.CORE_EXC_VECTOR_OUT (CORE_EXC_VECTOR ),
.CACHE_ISO_OUT (CACHE_ISO ),
.CACHE_SWAP_OUT (CACHE_SWAP ),
.CACHE_MISS_IN (CACHE_MISS )
);
endmodule | 1 |
138,349 | data/full_repos/permissive/83270534/mips1_core/rtl/cpu_core_bfm.v | 83,270,534 | cpu_core_bfm.v | v | 112 | 151 | [] | [] | [] | [(5, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/mips1_core/rtl/cpu_core_bfm.v:70: Cannot find file containing module: 'WB_MASTER_BFM'\n WB_MASTER_BFM wb_master_bfm_inst\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_core/rtl,data/full_repos/permissive/83270534/WB_MASTER_BFM\n data/full_repos/permissive/83270534/mips1_core/rtl,data/full_repos/permissive/83270534/WB_MASTER_BFM.v\n data/full_repos/permissive/83270534/mips1_core/rtl,data/full_repos/permissive/83270534/WB_MASTER_BFM.sv\n WB_MASTER_BFM\n WB_MASTER_BFM.v\n WB_MASTER_BFM.sv\n obj_dir/WB_MASTER_BFM\n obj_dir/WB_MASTER_BFM.v\n obj_dir/WB_MASTER_BFM.sv\n%Error: data/full_repos/permissive/83270534/mips1_core/rtl/cpu_core_bfm.v:90: Cannot find file containing module: 'WB_MASTER_BFM'\n WB_MASTER_BFM wb_master_bfm_data\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,207 | module | module CPU_CORE_BFM
#(parameter PC_RST_VALUE = 32'h0000_0000)
(
input CLK ,
input RST_SYNC ,
output [31:0] CORE_INST_ADR_OUT ,
output CORE_INST_CYC_OUT ,
output CORE_INST_STB_OUT ,
output CORE_INST_WE_OUT ,
output [ 3:0] CORE_INST_SEL_OUT ,
output [ 2:0] CORE_INST_CTI_OUT ,
output [ 1:0] CORE_INST_BTE_OUT ,
input CORE_INST_ACK_IN ,
input CORE_INST_STALL_IN ,
input CORE_INST_ERR_IN ,
input [31:0] CORE_INST_DAT_RD_IN ,
output [31:0] CORE_INST_DAT_WR_OUT ,
output [31:0] CORE_DATA_ADR_OUT ,
output CORE_DATA_CYC_OUT ,
output CORE_DATA_STB_OUT ,
output CORE_DATA_WE_OUT ,
output [ 3:0] CORE_DATA_SEL_OUT ,
output [ 2:0] CORE_DATA_CTI_OUT ,
output [ 1:0] CORE_DATA_BTE_OUT ,
input CORE_DATA_ACK_IN ,
input CORE_DATA_STALL_IN ,
input CORE_DATA_ERR_IN ,
input [31:0] CORE_DATA_DAT_RD_IN ,
output [31:0] CORE_DATA_DAT_WR_OUT ,
output COP0_INST_EN_OUT ,
output [4:0] COP0_INST_OUT ,
output COP0_RD_EN_OUT ,
output COP0_RD_CTRL_SEL_OUT ,
output [4:0] COP0_RD_SEL_OUT ,
input [31:0] COP0_RD_DATA_IN ,
output COP0_WR_EN_OUT ,
output COP0_WR_CTRL_SEL_OUT ,
output [4:0] COP0_WR_SEL_OUT ,
output [31:0] COP0_WR_DATA_OUT ,
input [3:0] COP_USABLE_IN ,
input COP0_INT_IN ,
output CORE_EXC_EN_OUT ,
output [1:0] CORE_EXC_CE_OUT ,
output [4:0] CORE_EXC_CODE_OUT ,
output CORE_EXC_BD_OUT ,
output [31:0] CORE_EXC_EPC_OUT ,
output [31:0] CORE_EXC_BADVA_OUT ,
input [31:0] CORE_EXC_VECTOR_IN
);
WB_MASTER_BFM wb_master_bfm_inst
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_ADR_OUT (CORE_INST_ADR_OUT ),
.WB_CYC_OUT (CORE_INST_CYC_OUT ),
.WB_STB_OUT (CORE_INST_STB_OUT ),
.WB_WE_OUT (CORE_INST_WE_OUT ),
.WB_SEL_OUT (CORE_INST_SEL_OUT ),
.WB_CTI_OUT (CORE_INST_CTI_OUT ),
.WB_BTE_OUT (CORE_INST_BTE_OUT ),
.WB_ACK_IN (CORE_INST_ACK_IN ),
.WB_STALL_IN (CORE_INST_STALL_IN ),
.WB_ERR_IN (CORE_INST_ERR_IN ),
.WB_DAT_RD_IN (CORE_INST_DAT_RD_IN ),
.WB_DAT_WR_OUT (CORE_INST_DAT_WR_OUT )
);
WB_MASTER_BFM wb_master_bfm_data
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_ADR_OUT (CORE_DATA_ADR_OUT ),
.WB_CYC_OUT (CORE_DATA_CYC_OUT ),
.WB_STB_OUT (CORE_DATA_STB_OUT ),
.WB_WE_OUT (CORE_DATA_WE_OUT ),
.WB_SEL_OUT (CORE_DATA_SEL_OUT ),
.WB_CTI_OUT (CORE_DATA_CTI_OUT ),
.WB_BTE_OUT (CORE_DATA_BTE_OUT ),
.WB_ACK_IN (CORE_DATA_ACK_IN ),
.WB_STALL_IN (CORE_DATA_STALL_IN ),
.WB_ERR_IN (CORE_DATA_ERR_IN ),
.WB_DAT_RD_IN (CORE_DATA_DAT_RD_IN ),
.WB_DAT_WR_OUT (CORE_DATA_DAT_WR_OUT )
);
endmodule | module CPU_CORE_BFM
#(parameter PC_RST_VALUE = 32'h0000_0000)
(
input CLK ,
input RST_SYNC ,
output [31:0] CORE_INST_ADR_OUT ,
output CORE_INST_CYC_OUT ,
output CORE_INST_STB_OUT ,
output CORE_INST_WE_OUT ,
output [ 3:0] CORE_INST_SEL_OUT ,
output [ 2:0] CORE_INST_CTI_OUT ,
output [ 1:0] CORE_INST_BTE_OUT ,
input CORE_INST_ACK_IN ,
input CORE_INST_STALL_IN ,
input CORE_INST_ERR_IN ,
input [31:0] CORE_INST_DAT_RD_IN ,
output [31:0] CORE_INST_DAT_WR_OUT ,
output [31:0] CORE_DATA_ADR_OUT ,
output CORE_DATA_CYC_OUT ,
output CORE_DATA_STB_OUT ,
output CORE_DATA_WE_OUT ,
output [ 3:0] CORE_DATA_SEL_OUT ,
output [ 2:0] CORE_DATA_CTI_OUT ,
output [ 1:0] CORE_DATA_BTE_OUT ,
input CORE_DATA_ACK_IN ,
input CORE_DATA_STALL_IN ,
input CORE_DATA_ERR_IN ,
input [31:0] CORE_DATA_DAT_RD_IN ,
output [31:0] CORE_DATA_DAT_WR_OUT ,
output COP0_INST_EN_OUT ,
output [4:0] COP0_INST_OUT ,
output COP0_RD_EN_OUT ,
output COP0_RD_CTRL_SEL_OUT ,
output [4:0] COP0_RD_SEL_OUT ,
input [31:0] COP0_RD_DATA_IN ,
output COP0_WR_EN_OUT ,
output COP0_WR_CTRL_SEL_OUT ,
output [4:0] COP0_WR_SEL_OUT ,
output [31:0] COP0_WR_DATA_OUT ,
input [3:0] COP_USABLE_IN ,
input COP0_INT_IN ,
output CORE_EXC_EN_OUT ,
output [1:0] CORE_EXC_CE_OUT ,
output [4:0] CORE_EXC_CODE_OUT ,
output CORE_EXC_BD_OUT ,
output [31:0] CORE_EXC_EPC_OUT ,
output [31:0] CORE_EXC_BADVA_OUT ,
input [31:0] CORE_EXC_VECTOR_IN
); |
WB_MASTER_BFM wb_master_bfm_inst
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_ADR_OUT (CORE_INST_ADR_OUT ),
.WB_CYC_OUT (CORE_INST_CYC_OUT ),
.WB_STB_OUT (CORE_INST_STB_OUT ),
.WB_WE_OUT (CORE_INST_WE_OUT ),
.WB_SEL_OUT (CORE_INST_SEL_OUT ),
.WB_CTI_OUT (CORE_INST_CTI_OUT ),
.WB_BTE_OUT (CORE_INST_BTE_OUT ),
.WB_ACK_IN (CORE_INST_ACK_IN ),
.WB_STALL_IN (CORE_INST_STALL_IN ),
.WB_ERR_IN (CORE_INST_ERR_IN ),
.WB_DAT_RD_IN (CORE_INST_DAT_RD_IN ),
.WB_DAT_WR_OUT (CORE_INST_DAT_WR_OUT )
);
WB_MASTER_BFM wb_master_bfm_data
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_ADR_OUT (CORE_DATA_ADR_OUT ),
.WB_CYC_OUT (CORE_DATA_CYC_OUT ),
.WB_STB_OUT (CORE_DATA_STB_OUT ),
.WB_WE_OUT (CORE_DATA_WE_OUT ),
.WB_SEL_OUT (CORE_DATA_SEL_OUT ),
.WB_CTI_OUT (CORE_DATA_CTI_OUT ),
.WB_BTE_OUT (CORE_DATA_BTE_OUT ),
.WB_ACK_IN (CORE_DATA_ACK_IN ),
.WB_STALL_IN (CORE_DATA_STALL_IN ),
.WB_ERR_IN (CORE_DATA_ERR_IN ),
.WB_DAT_RD_IN (CORE_DATA_DAT_RD_IN ),
.WB_DAT_WR_OUT (CORE_DATA_DAT_WR_OUT )
);
endmodule | 1 |
138,352 | data/full_repos/permissive/83270534/mips1_core/sim/c/add/testcase.v | 83,270,534 | testcase.v | v | 5 | 22 | [] | [] | [] | [(1, 4)] | null | data/verilator_xmls/067daab3-0ebd-4bc5-ae58-6b9de6d08a0f.xml | null | 302,232 | module | module TESTCASE ();
endmodule | module TESTCASE (); |
endmodule | 1 |
138,353 | data/full_repos/permissive/83270534/mips1_core/tb/cpu_core_model.v | 83,270,534 | cpu_core_model.v | v | 768 | 138 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_core/tb/cpu_core_model.v:34: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_core/tb,data/full_repos/permissive/83270534/cpu_defs.v\n data/full_repos/permissive/83270534/mips1_core/tb,data/full_repos/permissive/83270534/cpu_defs.v.v\n data/full_repos/permissive/83270534/mips1_core/tb,data/full_repos/permissive/83270534/cpu_defs.v.sv\n cpu_defs.v\n cpu_defs.v.v\n cpu_defs.v.sv\n obj_dir/cpu_defs.v\n obj_dir/cpu_defs.v.v\n obj_dir/cpu_defs.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_core/tb/cpu_core_model.v:132: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n dataLog = $fopen("model_data_log.txt");\n ^~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_core/tb/cpu_core_model.v:177: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n instrLog = $fopen("model_instr_log.txt");\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n' | 302,233 | module | module CPU_CORE_MODEL
(
input CLK ,
input RST_SYNC ,
input CORE_INST_CYC_IN ,
input CORE_INST_STB_IN ,
input [31:0] CORE_INST_ADR_IN ,
input CORE_INST_ACK_IN ,
input [31:0] CORE_INST_DAT_RD_IN ,
input CORE_DATA_CYC_IN ,
input CORE_DATA_STB_IN ,
input [31:0] CORE_DATA_ADR_IN ,
input [ 3:0] CORE_DATA_SEL_IN ,
input CORE_DATA_WE_IN ,
input CORE_DATA_ACK_IN ,
input [31:0] CORE_DATA_DAT_RD_IN ,
input [31:0] CORE_DATA_DAT_WR_IN
);
`define TESTSTR "code.hex"
`include "cpu_defs.v"
wire [31:0] Instr;
wire [ 4:0] InstrIndex;
wire DmCyc ;
wire DmStb ;
wire [31:0] DmAddr ;
wire [ 3:0] DmSel ;
wire DmWe ;
wire [31:0] DmWriteData ;
wire [31:0] DmReadData ;
wire DmReadEn = DmCyc & DmStb & ~DmWe;
wire DmWriteEn = DmCyc & DmStb & DmWe;
reg TraceEnable;
string register_names [32] = '{ "$zero ", "$at ", "$v0 ", "$v1 ",
"$a0 ", "$a1 ", "$a2 ", "$a3 ",
"$t0 ", "$t1 ", "$t2 ", "$t3 ",
"$t4 ", "$t5 ", "$t6 ", "$t7 ",
"$s0 ", "$s1 ", "$s2 ", "$s3 ",
"$s4 ", "$s5 ", "$s6 ", "$s7 ",
"$s8 ", "$s9 ", "$k0 ", "$k1 ",
"$gp ", "$sp ", "$fp ", "$ra "
};
integer instrLog;
integer dataLog;
reg CoreInstAck;
wire CoreInstCyc;
wire CoreInstStb;
typedef enum {NEWPC, REGWRITE, MEMLOAD, MEMSTORE} T_CPU_ACTION_E;
int QDutPc[$] ;
T_CPU_ACTION_E QDutAction[$] ;
int QDutRegMemAddr[$] ;
int QDutDataVal[$] ;
reg signed [31:0] RegArray [31:0];
reg [31:0] RegHi;
reg [31:0] RegLo;
reg [63:0] MultResult;
reg [63:0] DivResult;
reg DelaySlot;
reg LoadSlot;
reg [5:0] Opcode;
reg [4:0] Rs;
reg [4:0] Rt;
reg [4:0] Rd;
reg [4:0] Shamt;
reg [5:0] Funct;
reg [15:0] Immed;
reg [31:0] SignXImmed;
reg [31:0] ZeroXImmed;
reg [25:0] Target;
reg [31:0] currPc;
reg [31:0] nextPc;
reg [31:0] jumpPc;
reg dataCheck;
reg [31:0] nextDataAdr;
reg [3:0] nextDataSel;
reg nextDataWe;
reg [31:0] nextDataDatRd;
reg [31:0] nextDataDatWr;
reg [4:0] nextDataReg;
integer regLoop;
initial
begin
for (regLoop = 0 ; regLoop < 32 ; regLoop = regLoop + 1)
begin
RegArray[regLoop] <= 32'h0000_0000;
end
RegHi <= 32'h0000_0000;
RegLo <= 32'h0000_0000;
end
initial
begin
dataLog = $fopen("model_data_log.txt");
end
always @(posedge CLK)
begin
if (CORE_DATA_CYC_IN && CORE_DATA_STB_IN && CORE_DATA_ACK_IN)
begin
if (CORE_DATA_WE_IN)
begin
$fwrite(dataLog, "DATA WR: Addr 0x%08x = Data 0x%08x, Byte Sel = 0x%1x\n", CORE_DATA_ADR_IN, CORE_DATA_DAT_WR_IN, CORE_DATA_SEL_IN);
end
else
begin
$fwrite(dataLog, "DATA RD: Addr 0x%08x = Data 0x%08x, Byte Sel = 0x%1x\n", CORE_DATA_ADR_IN, CORE_DATA_DAT_WR_IN, CORE_DATA_SEL_IN);
end
if ( (nextDataAdr == CORE_DATA_ADR_IN)
&& (nextDataSel == CORE_DATA_SEL_IN)
&& (nextDataWe == CORE_DATA_WE_IN )
)
begin
$display("DATA Checked");
end
end
end
initial
begin
instrLog = $fopen("model_instr_log.txt");
TraceEnable = 1'b1;
end
always @(negedge CLK)
begin
if (!RST_SYNC)
begin
if (CORE_INST_CYC_IN && CORE_INST_STB_IN && CORE_INST_ACK_IN)
begin
Opcode = CORE_INST_DAT_RD_IN[OPC_HI:OPC_LO];
Rs = CORE_INST_DAT_RD_IN[RS_HI:RS_LO];
Rt = CORE_INST_DAT_RD_IN[RT_HI:RT_LO];
Rd = CORE_INST_DAT_RD_IN[RD_HI:RD_LO];
Shamt = CORE_INST_DAT_RD_IN[SA_HI:SA_LO];
Funct = CORE_INST_DAT_RD_IN[FUNCT_HI:FUNCT_LO];
Immed = CORE_INST_DAT_RD_IN[IMMED_HI:IMMED_LO];
SignXImmed = {{16{Immed[15]}}, Immed};
ZeroXImmed = {{16{1'b0}}, Immed};
Target = CORE_INST_DAT_RD_IN[TARGET_HI:TARGET_LO];
currPc = CORE_INST_ADR_IN;
nextPc = CORE_INST_ADR_IN + 32'd4;
if (DelaySlot)
begin
$fwrite(instrLog, "DLY_SLOT: ");
nextPc = jumpPc;
DelaySlot = 1'b0;
end
$fwrite(instrLog, "PC: 0x%08x, ", CORE_INST_ADR_IN);
if (Opcode == OPC_SPECIAL)
begin
case (Funct)
FUNCT_SLL :
begin
RegArray[Rd] = RegArray[Rt] << Shamt;
$fwrite(instrLog, "FUNCT = SLL , REG[%2d] = REG[%2d] << %d\n = 0x%08x", Rd, Rt, Shamt, RegArray[Rd]);
end
FUNCT_SRL :
begin
RegArray[Rd] = RegArray[Rt] >> Shamt;
$fwrite(instrLog, "FUNCT = SRL , REG[%2d] = REG[%2d] >> %d\n = 0x%08x", Rd, Rt, Shamt, RegArray[Rd]);
end
FUNCT_SRA :
begin
RegArray[Rd] = RegArray[Rt] <<< Shamt;
$fwrite(instrLog, "FUNCT = SRA , REG[%2d] = REG[%2d] <<< %d\n = 0x%08x", Rd, Rt, Shamt, RegArray[Rd]);
end
FUNCT_SLLV :
begin
RegArray[Rd] = RegArray[Rt] << RegArray[Rs];
$fwrite(instrLog, "FUNCT = SLLV , REG[%2d] = REG[%2d] << %d\n = 0x%08x", Rd, Rt, RegArray[Rs], RegArray[Rd]);
end
FUNCT_SRLV :
begin
RegArray[Rd] = RegArray[Rt] >> RegArray[Rs];
$fwrite(instrLog, "FUNCT = SRLV , REG[%2d] = REG[%2d] >> %d\n = 0x%08x", Rd, Rt, RegArray[Rs], RegArray[Rd]);
end
FUNCT_SRAV :
begin
RegArray[Rd] = RegArray[Rt] >>> RegArray[Rs];
$fwrite(instrLog, "FUNCT = SRAV , REG[%2d] = REG[%2d] >>> %d\n = 0x%08x", Rd, Rt, RegArray[Rs], RegArray[Rd]);
end
FUNCT_JR :
begin
jumpPc = RegArray[Rs] ;
DelaySlot = 1'b1;
$fwrite(instrLog, "FUNCT = JR , Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
FUNCT_JALR :
begin
RegArray[Rd] = nextPc + 32'd4;
jumpPc = RegArray[Rs] ;
DelaySlot = 1'b1;
$fwrite(instrLog, "FUNCT = JALR , Delay PC = 0x%08x, Jump PC = 0x%08x, REG[%2d] = 0x%08x", nextPc, jumpPc, Rd, RegArray[Rd]);
end
FUNCT_SYSCALL :
begin
$fwrite(instrLog, "FUNCT = SYSCALL ");
end
FUNCT_BREAK :
begin
$fwrite(instrLog, "FUNCT = BREAK ");
end
FUNCT_MFHI :
begin
RegArray[Rd] = RegHi;
$fwrite(instrLog, "FUNCT = MFHI , REG[%2d] = REGHI = 0x%08x", Rd, RegHi);
end
FUNCT_MTHI :
begin
RegHi = RegArray[Rs];
$fwrite(instrLog, "FUNCT = MTHI , REGHI = REG[%2d] = 0x%08x", Rs, RegArray[Rs]);
end
FUNCT_MFLO :
begin
RegArray[Rd] = RegLo;
$fwrite(instrLog, "FUNCT = MFLO , REG[%2d] = REGHI = 0x%08x", Rd, RegLo);
end
FUNCT_MTLO :
begin
RegLo = RegArray[Rs];
$fwrite(instrLog, "FUNCT = MTLO , REGLO = REG[%2d] = 0x%08x", Rs, RegArray[Rs]);
end
FUNCT_MULT :
begin
MultResult = RegArray[Rs] * RegArray[Rt];
RegLo = MultResult[31:0];
RegHi = MultResult[63:32];
$fwrite(instrLog, "FUNCT = MULT , REG{HI,LO} = REG[%2d] * REG [%2d] = 0x%08x * 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_MULTU :
begin
MultResult = RegArray[Rs] * RegArray[Rt];
RegLo = MultResult[31:0];
RegHi = MultResult[63:32];
$fwrite(instrLog, "FUNCT = MULTU , REG{HI,LO} = REG[%2d] * REG [%2d] = 0x%08x * 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_DIV :
begin
DivResult = RegArray[Rs] / RegArray[Rt];
RegLo = DivResult[31:0];
RegHi = DivResult[63:32];
$fwrite(instrLog, "FUNCT = DIV , REG{HI,LO} = REG[%2d] / REG [%2d] = 0x%08x / 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_DIVU :
begin
DivResult = RegArray[Rs] / RegArray[Rt];
RegLo = DivResult[31:0];
RegHi = DivResult[63:32];
$fwrite(instrLog, "FUNCT = DIVU , REG{HI,LO} = REG[%2d] / REG [%2d] = 0x%08x / 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_ADD :
begin
RegArray[Rd] = RegArray[Rs] + RegArray[Rt];
$fwrite(instrLog, "FUNCT = ADD , REG[%2d] = REG[%2d] + REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_ADDU :
begin
RegArray[Rd] = RegArray[Rs] + RegArray[Rt];
$fwrite(instrLog, "FUNCT = ADDU , REG[%2d] = REG[%2d] + REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SUB :
begin
RegArray[Rd] = RegArray[Rs] - RegArray[Rt];
$fwrite(instrLog, "FUNCT = SUB , REG[%2d] = REG[%2d] - REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SUBU :
begin
RegArray[Rd] = RegArray[Rs] - RegArray[Rt];
$fwrite(instrLog, "FUNCT = SUB , REG[%2d] = REG[%2d] - REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_AND :
begin
RegArray[Rd] = RegArray[Rs] & RegArray[Rt];
$fwrite(instrLog, "FUNCT = AND , REG[%2d] = REG[%2d] AND REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_OR :
begin
RegArray[Rd] = RegArray[Rs] | RegArray[Rt];
$fwrite(instrLog, "FUNCT = OR , REG[%2d] = REG[%2d] OR REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_XOR :
begin
RegArray[Rd] = RegArray[Rs] ^ RegArray[Rt];
$fwrite(instrLog, "FUNCT = XOR , REG[%2d] = REG[%2d] XOR REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_NOR :
begin
RegArray[Rd] = ~(RegArray[Rs] | RegArray[Rt]);
$fwrite(instrLog, "FUNCT = NOR , REG[%2d] = REG[%2d] NOR REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SLT :
begin
RegArray[Rd] = (RegArray[Rs] < RegArray[Rt]);
$fwrite(instrLog, "FUNCT = SLT , REG[%2d] = (REG[%2d] < REG[%2d]) = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SLTU :
begin
RegArray[Rd] = (RegArray[Rs] < RegArray[Rt]);
$fwrite(instrLog, "FUNCT = SLTU , REG[%2d] = (REG[%2d] < REG[%2d]) = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
default:
begin
$fwrite(instrLog, "UNRECOGNISED SPECIAL OPCODE");
$display("[ERROR] Unrecognized SPECIAL FUNCT");
end
endcase
end
else if (Opcode == OPC_REGIMM)
begin
case (Rt)
REGIMM_BLTZ :
begin
$fwrite(instrLog, "REGIMM = BLTZ , REG[%2d] = 0x%08x < 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] < 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
REGIMM_BGEZ :
begin
$fwrite(instrLog, "REGIMM = BGEZ , REG[%2d] = 0x%08x >= 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] >= 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
REGIMM_BLTZAL :
begin
$fwrite(instrLog, "REGIMM = BLTZAL , REG[%2d] = 0x%08x < 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] < 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
RegArray[31] = nextPc + 32'd4;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x, REG[31] = 0x%08x", nextPc, jumpPc, RegArray[31]);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
REGIMM_BGEZAL :
begin
$fwrite(instrLog, "REGIMM = BGEZAL , REG[%2d] = 0x%08x >= 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] >= 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
RegArray[31] = nextPc + 32'd4;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x, REG[31] = 0x%08x", nextPc, jumpPc, RegArray[31]);
end
else
begin
jumpPc = nextPc + 32'd4 ; DelaySlot = 1'b1;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
default: $display("[ERROR] Unrecognized REGIMM RT");
endcase
end
else
begin
case (Opcode)
OPC_J :
begin
jumpPc = nextPc + {Target, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "OPCODE = J , PC = 0x%08x", jumpPc);
end
OPC_JAL :
begin
jumpPc = nextPc + {Target, 2'b00} ;
DelaySlot = 1'b1;
RegArray[31] = nextPc + 32'd4;
$fwrite(instrLog, "OPCODE = JAL , Delay PC = 0x%08x, Jump PC = 0x%08x, REG[31] = 0x%08x", nextPc, jumpPc, RegArray[Rd]);
end
OPC_BEQ :
begin
$fwrite(instrLog, "OPCODE = BEQ , REG[%2d] 0x%08x == REG [%2d] 0x%08x ?", Rs, Rt, RegArray[Rs], RegArray[Rt]);
if (RegArray[Rs] == RegArray[Rt])
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_BNE :
begin
$fwrite(instrLog, "OPCODE = BNE , REG[%2d] 0x%08x != REG [%2d] 0x%08x ?", Rs, Rt, RegArray[Rs], RegArray[Rt]);
if (RegArray[Rs] != RegArray[Rt])
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_BLEZ :
begin
$fwrite(instrLog, "OPCODE = BLEZ , REG[%2d] = 0x%08x <= 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] == 32'd0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ; DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_BGTZ :
begin
$fwrite(instrLog, "OPCODE = BGTZ , REG[%2d] = 0x%08x > 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] > 32'd0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_ADDI :
begin
RegArray[Rt] = RegArray[Rs] + SignXImmed;
$fwrite(instrLog, "OPCODE = ADDI , REG[%2d] = REG[%2d] + 0x%08x", Rt, Rs, SignXImmed);
end
OPC_ADDIU :
begin
RegArray[Rt] = RegArray[Rs] + SignXImmed;
$fwrite(instrLog, "OPCODE = ADDIU , REG[%2d] = REG[%2d] + 0x%08x", Rt, Rs, SignXImmed);
end
OPC_SLTI :
begin
$fwrite(instrLog, "OPCODE = SLTI , REG[%2d] 0x%08x < IMMED 0x%08x ?", Rs, RegArray[Rs], SignXImmed);
if (RegArray[Rs] < Immed)
begin
RegArray[Rt] = 5'd1;
$fwrite(instrLog, "SET - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
else
begin
RegArray[Rt] = 5'd0;
$fwrite(instrLog, "CLR - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
end
OPC_SLTIU :
begin
$fwrite(instrLog, "OPCODE = SLTIU , REG[%2d] 0x%08x < IMMED 0x%08x ?", Rs, RegArray[Rs], SignXImmed);
if (RegArray[Rs] < Immed)
begin
RegArray[Rt] = 5'd1;
$fwrite(instrLog, "SET - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
else
begin
RegArray[Rt] = 5'd0;
$fwrite(instrLog, "CLR - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
end
OPC_ANDI :
begin
RegArray[Rt] = RegArray[Rs] & ZeroXImmed;
$fwrite(instrLog, "OPCODE = ANDI , REG[%2d] = REG[%2d] 0x%08x AND 0x%08x", Rt, Rs, RegArray[Rs], ZeroXImmed);
end
OPC_ORI :
begin
RegArray[Rt] = RegArray[Rs] | ZeroXImmed;
$fwrite(instrLog, "OPCODE = ORI , REG[%2d] = REG[%2d] 0x%08x OR 0x%08x", Rt, Rs, RegArray[Rs], ZeroXImmed);
end
OPC_XORI :
begin
RegArray[Rt] = RegArray[Rs] ^ ZeroXImmed;
$fwrite(instrLog, "OPCODE = XOR , REG[%2d] = REG[%2d] 0x%08x XOR 0x%08x", Rt, Rs, RegArray[Rs], ZeroXImmed);
end
OPC_LUI :
begin
RegArray[Rt] = {Immed, 16'h0000};
$fwrite(instrLog, "OPCODE = LUI , REG[%2d] = 0x%04x0000", Rt, Immed);
end
OPC_COP0 :
begin
$fwrite(instrLog, "OPC_COP0 , ");
end
OPC_COP1 :
begin
$fwrite(instrLog, "OPC_COP1 , ");
end
OPC_COP2 :
begin
$fwrite(instrLog, "OPC_COP2 , ");
end
OPC_COP3 :
begin
$fwrite(instrLog, "OPC_COP3 , ");
end
OPC_LB :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0001;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LB , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LH :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0011;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LH , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LWL :
begin
$fwrite(instrLog, "OPC_LWL , ");
end
OPC_LW :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b1111;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LW , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LBU :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0001;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LBU , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LHU :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0011;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LHU , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LWR :
begin
$fwrite(instrLog, "OPC_LWR , ");
end
OPC_SB :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0001;
nextDataWe = 1'b1;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = RegArray[Rt];
nextDataReg = 5'd0;
$fwrite(instrLog, "OPCODE = SB , DATA[0x%08x] = REG[%2d] 0x%08x", nextDataAdr, Rt, RegArray[Rt]);
end
OPC_SH :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0011;
nextDataWe = 1'b1;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = RegArray[Rt];
nextDataReg = 5'd0;
$fwrite(instrLog, "OPCODE = SH , DATA[0x%08x] = REG[%2d] 0x%08x", nextDataAdr, Rt, RegArray[Rt]);
end
OPC_SWL :
begin
$fwrite(instrLog, "OPC_SWL , ");
end
OPC_SW :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b1111;
nextDataWe = 1'b1;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = RegArray[Rt];
nextDataReg = 5'd0;
$fwrite(instrLog, "OPCODE = SW , DATA[0x%08x] = REG[%2d] 0x%08x", nextDataAdr, Rt, RegArray[Rt]);
end
OPC_SWR :
begin
$fwrite(instrLog, "OPC_SWR , ");
end
OPC_LWC1 :
begin
$fwrite(instrLog, "OPC_LWC1 , ");
end
OPC_LWC2 :
begin
$fwrite(instrLog, "OPC_LWC2 , ");
end
OPC_LWC3 :
begin
$fwrite(instrLog, "OPC_LWC3 , ");
end
OPC_SWC1 :
begin
$fwrite(instrLog, "OPC_SWC1 , ");
end
OPC_SWC2 :
begin
$fwrite(instrLog, "OPC_SWC2 , ");
end
OPC_SWC3 :
begin
$fwrite(instrLog, "OPC_SWC3 , ");
end
endcase
end
$fwrite(instrLog, "\n");
end
end
end
endmodule | module CPU_CORE_MODEL
(
input CLK ,
input RST_SYNC ,
input CORE_INST_CYC_IN ,
input CORE_INST_STB_IN ,
input [31:0] CORE_INST_ADR_IN ,
input CORE_INST_ACK_IN ,
input [31:0] CORE_INST_DAT_RD_IN ,
input CORE_DATA_CYC_IN ,
input CORE_DATA_STB_IN ,
input [31:0] CORE_DATA_ADR_IN ,
input [ 3:0] CORE_DATA_SEL_IN ,
input CORE_DATA_WE_IN ,
input CORE_DATA_ACK_IN ,
input [31:0] CORE_DATA_DAT_RD_IN ,
input [31:0] CORE_DATA_DAT_WR_IN
); |
`define TESTSTR "code.hex"
`include "cpu_defs.v"
wire [31:0] Instr;
wire [ 4:0] InstrIndex;
wire DmCyc ;
wire DmStb ;
wire [31:0] DmAddr ;
wire [ 3:0] DmSel ;
wire DmWe ;
wire [31:0] DmWriteData ;
wire [31:0] DmReadData ;
wire DmReadEn = DmCyc & DmStb & ~DmWe;
wire DmWriteEn = DmCyc & DmStb & DmWe;
reg TraceEnable;
string register_names [32] = '{ "$zero ", "$at ", "$v0 ", "$v1 ",
"$a0 ", "$a1 ", "$a2 ", "$a3 ",
"$t0 ", "$t1 ", "$t2 ", "$t3 ",
"$t4 ", "$t5 ", "$t6 ", "$t7 ",
"$s0 ", "$s1 ", "$s2 ", "$s3 ",
"$s4 ", "$s5 ", "$s6 ", "$s7 ",
"$s8 ", "$s9 ", "$k0 ", "$k1 ",
"$gp ", "$sp ", "$fp ", "$ra "
};
integer instrLog;
integer dataLog;
reg CoreInstAck;
wire CoreInstCyc;
wire CoreInstStb;
typedef enum {NEWPC, REGWRITE, MEMLOAD, MEMSTORE} T_CPU_ACTION_E;
int QDutPc[$] ;
T_CPU_ACTION_E QDutAction[$] ;
int QDutRegMemAddr[$] ;
int QDutDataVal[$] ;
reg signed [31:0] RegArray [31:0];
reg [31:0] RegHi;
reg [31:0] RegLo;
reg [63:0] MultResult;
reg [63:0] DivResult;
reg DelaySlot;
reg LoadSlot;
reg [5:0] Opcode;
reg [4:0] Rs;
reg [4:0] Rt;
reg [4:0] Rd;
reg [4:0] Shamt;
reg [5:0] Funct;
reg [15:0] Immed;
reg [31:0] SignXImmed;
reg [31:0] ZeroXImmed;
reg [25:0] Target;
reg [31:0] currPc;
reg [31:0] nextPc;
reg [31:0] jumpPc;
reg dataCheck;
reg [31:0] nextDataAdr;
reg [3:0] nextDataSel;
reg nextDataWe;
reg [31:0] nextDataDatRd;
reg [31:0] nextDataDatWr;
reg [4:0] nextDataReg;
integer regLoop;
initial
begin
for (regLoop = 0 ; regLoop < 32 ; regLoop = regLoop + 1)
begin
RegArray[regLoop] <= 32'h0000_0000;
end
RegHi <= 32'h0000_0000;
RegLo <= 32'h0000_0000;
end
initial
begin
dataLog = $fopen("model_data_log.txt");
end
always @(posedge CLK)
begin
if (CORE_DATA_CYC_IN && CORE_DATA_STB_IN && CORE_DATA_ACK_IN)
begin
if (CORE_DATA_WE_IN)
begin
$fwrite(dataLog, "DATA WR: Addr 0x%08x = Data 0x%08x, Byte Sel = 0x%1x\n", CORE_DATA_ADR_IN, CORE_DATA_DAT_WR_IN, CORE_DATA_SEL_IN);
end
else
begin
$fwrite(dataLog, "DATA RD: Addr 0x%08x = Data 0x%08x, Byte Sel = 0x%1x\n", CORE_DATA_ADR_IN, CORE_DATA_DAT_WR_IN, CORE_DATA_SEL_IN);
end
if ( (nextDataAdr == CORE_DATA_ADR_IN)
&& (nextDataSel == CORE_DATA_SEL_IN)
&& (nextDataWe == CORE_DATA_WE_IN )
)
begin
$display("DATA Checked");
end
end
end
initial
begin
instrLog = $fopen("model_instr_log.txt");
TraceEnable = 1'b1;
end
always @(negedge CLK)
begin
if (!RST_SYNC)
begin
if (CORE_INST_CYC_IN && CORE_INST_STB_IN && CORE_INST_ACK_IN)
begin
Opcode = CORE_INST_DAT_RD_IN[OPC_HI:OPC_LO];
Rs = CORE_INST_DAT_RD_IN[RS_HI:RS_LO];
Rt = CORE_INST_DAT_RD_IN[RT_HI:RT_LO];
Rd = CORE_INST_DAT_RD_IN[RD_HI:RD_LO];
Shamt = CORE_INST_DAT_RD_IN[SA_HI:SA_LO];
Funct = CORE_INST_DAT_RD_IN[FUNCT_HI:FUNCT_LO];
Immed = CORE_INST_DAT_RD_IN[IMMED_HI:IMMED_LO];
SignXImmed = {{16{Immed[15]}}, Immed};
ZeroXImmed = {{16{1'b0}}, Immed};
Target = CORE_INST_DAT_RD_IN[TARGET_HI:TARGET_LO];
currPc = CORE_INST_ADR_IN;
nextPc = CORE_INST_ADR_IN + 32'd4;
if (DelaySlot)
begin
$fwrite(instrLog, "DLY_SLOT: ");
nextPc = jumpPc;
DelaySlot = 1'b0;
end
$fwrite(instrLog, "PC: 0x%08x, ", CORE_INST_ADR_IN);
if (Opcode == OPC_SPECIAL)
begin
case (Funct)
FUNCT_SLL :
begin
RegArray[Rd] = RegArray[Rt] << Shamt;
$fwrite(instrLog, "FUNCT = SLL , REG[%2d] = REG[%2d] << %d\n = 0x%08x", Rd, Rt, Shamt, RegArray[Rd]);
end
FUNCT_SRL :
begin
RegArray[Rd] = RegArray[Rt] >> Shamt;
$fwrite(instrLog, "FUNCT = SRL , REG[%2d] = REG[%2d] >> %d\n = 0x%08x", Rd, Rt, Shamt, RegArray[Rd]);
end
FUNCT_SRA :
begin
RegArray[Rd] = RegArray[Rt] <<< Shamt;
$fwrite(instrLog, "FUNCT = SRA , REG[%2d] = REG[%2d] <<< %d\n = 0x%08x", Rd, Rt, Shamt, RegArray[Rd]);
end
FUNCT_SLLV :
begin
RegArray[Rd] = RegArray[Rt] << RegArray[Rs];
$fwrite(instrLog, "FUNCT = SLLV , REG[%2d] = REG[%2d] << %d\n = 0x%08x", Rd, Rt, RegArray[Rs], RegArray[Rd]);
end
FUNCT_SRLV :
begin
RegArray[Rd] = RegArray[Rt] >> RegArray[Rs];
$fwrite(instrLog, "FUNCT = SRLV , REG[%2d] = REG[%2d] >> %d\n = 0x%08x", Rd, Rt, RegArray[Rs], RegArray[Rd]);
end
FUNCT_SRAV :
begin
RegArray[Rd] = RegArray[Rt] >>> RegArray[Rs];
$fwrite(instrLog, "FUNCT = SRAV , REG[%2d] = REG[%2d] >>> %d\n = 0x%08x", Rd, Rt, RegArray[Rs], RegArray[Rd]);
end
FUNCT_JR :
begin
jumpPc = RegArray[Rs] ;
DelaySlot = 1'b1;
$fwrite(instrLog, "FUNCT = JR , Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
FUNCT_JALR :
begin
RegArray[Rd] = nextPc + 32'd4;
jumpPc = RegArray[Rs] ;
DelaySlot = 1'b1;
$fwrite(instrLog, "FUNCT = JALR , Delay PC = 0x%08x, Jump PC = 0x%08x, REG[%2d] = 0x%08x", nextPc, jumpPc, Rd, RegArray[Rd]);
end
FUNCT_SYSCALL :
begin
$fwrite(instrLog, "FUNCT = SYSCALL ");
end
FUNCT_BREAK :
begin
$fwrite(instrLog, "FUNCT = BREAK ");
end
FUNCT_MFHI :
begin
RegArray[Rd] = RegHi;
$fwrite(instrLog, "FUNCT = MFHI , REG[%2d] = REGHI = 0x%08x", Rd, RegHi);
end
FUNCT_MTHI :
begin
RegHi = RegArray[Rs];
$fwrite(instrLog, "FUNCT = MTHI , REGHI = REG[%2d] = 0x%08x", Rs, RegArray[Rs]);
end
FUNCT_MFLO :
begin
RegArray[Rd] = RegLo;
$fwrite(instrLog, "FUNCT = MFLO , REG[%2d] = REGHI = 0x%08x", Rd, RegLo);
end
FUNCT_MTLO :
begin
RegLo = RegArray[Rs];
$fwrite(instrLog, "FUNCT = MTLO , REGLO = REG[%2d] = 0x%08x", Rs, RegArray[Rs]);
end
FUNCT_MULT :
begin
MultResult = RegArray[Rs] * RegArray[Rt];
RegLo = MultResult[31:0];
RegHi = MultResult[63:32];
$fwrite(instrLog, "FUNCT = MULT , REG{HI,LO} = REG[%2d] * REG [%2d] = 0x%08x * 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_MULTU :
begin
MultResult = RegArray[Rs] * RegArray[Rt];
RegLo = MultResult[31:0];
RegHi = MultResult[63:32];
$fwrite(instrLog, "FUNCT = MULTU , REG{HI,LO} = REG[%2d] * REG [%2d] = 0x%08x * 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_DIV :
begin
DivResult = RegArray[Rs] / RegArray[Rt];
RegLo = DivResult[31:0];
RegHi = DivResult[63:32];
$fwrite(instrLog, "FUNCT = DIV , REG{HI,LO} = REG[%2d] / REG [%2d] = 0x%08x / 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_DIVU :
begin
DivResult = RegArray[Rs] / RegArray[Rt];
RegLo = DivResult[31:0];
RegHi = DivResult[63:32];
$fwrite(instrLog, "FUNCT = DIVU , REG{HI,LO} = REG[%2d] / REG [%2d] = 0x%08x / 0x%08x", Rs, Rt, RegArray[Rs], RegArray[Rt]);
end
FUNCT_ADD :
begin
RegArray[Rd] = RegArray[Rs] + RegArray[Rt];
$fwrite(instrLog, "FUNCT = ADD , REG[%2d] = REG[%2d] + REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_ADDU :
begin
RegArray[Rd] = RegArray[Rs] + RegArray[Rt];
$fwrite(instrLog, "FUNCT = ADDU , REG[%2d] = REG[%2d] + REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SUB :
begin
RegArray[Rd] = RegArray[Rs] - RegArray[Rt];
$fwrite(instrLog, "FUNCT = SUB , REG[%2d] = REG[%2d] - REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SUBU :
begin
RegArray[Rd] = RegArray[Rs] - RegArray[Rt];
$fwrite(instrLog, "FUNCT = SUB , REG[%2d] = REG[%2d] - REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_AND :
begin
RegArray[Rd] = RegArray[Rs] & RegArray[Rt];
$fwrite(instrLog, "FUNCT = AND , REG[%2d] = REG[%2d] AND REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_OR :
begin
RegArray[Rd] = RegArray[Rs] | RegArray[Rt];
$fwrite(instrLog, "FUNCT = OR , REG[%2d] = REG[%2d] OR REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_XOR :
begin
RegArray[Rd] = RegArray[Rs] ^ RegArray[Rt];
$fwrite(instrLog, "FUNCT = XOR , REG[%2d] = REG[%2d] XOR REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_NOR :
begin
RegArray[Rd] = ~(RegArray[Rs] | RegArray[Rt]);
$fwrite(instrLog, "FUNCT = NOR , REG[%2d] = REG[%2d] NOR REG[%2d] = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SLT :
begin
RegArray[Rd] = (RegArray[Rs] < RegArray[Rt]);
$fwrite(instrLog, "FUNCT = SLT , REG[%2d] = (REG[%2d] < REG[%2d]) = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
FUNCT_SLTU :
begin
RegArray[Rd] = (RegArray[Rs] < RegArray[Rt]);
$fwrite(instrLog, "FUNCT = SLTU , REG[%2d] = (REG[%2d] < REG[%2d]) = 0x%08x", Rd, Rs, Rt, RegArray[Rd]);
end
default:
begin
$fwrite(instrLog, "UNRECOGNISED SPECIAL OPCODE");
$display("[ERROR] Unrecognized SPECIAL FUNCT");
end
endcase
end
else if (Opcode == OPC_REGIMM)
begin
case (Rt)
REGIMM_BLTZ :
begin
$fwrite(instrLog, "REGIMM = BLTZ , REG[%2d] = 0x%08x < 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] < 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
REGIMM_BGEZ :
begin
$fwrite(instrLog, "REGIMM = BGEZ , REG[%2d] = 0x%08x >= 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] >= 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
REGIMM_BLTZAL :
begin
$fwrite(instrLog, "REGIMM = BLTZAL , REG[%2d] = 0x%08x < 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] < 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
RegArray[31] = nextPc + 32'd4;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x, REG[31] = 0x%08x", nextPc, jumpPc, RegArray[31]);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
REGIMM_BGEZAL :
begin
$fwrite(instrLog, "REGIMM = BGEZAL , REG[%2d] = 0x%08x >= 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] >= 0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
RegArray[31] = nextPc + 32'd4;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x, REG[31] = 0x%08x", nextPc, jumpPc, RegArray[31]);
end
else
begin
jumpPc = nextPc + 32'd4 ; DelaySlot = 1'b1;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
default: $display("[ERROR] Unrecognized REGIMM RT");
endcase
end
else
begin
case (Opcode)
OPC_J :
begin
jumpPc = nextPc + {Target, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "OPCODE = J , PC = 0x%08x", jumpPc);
end
OPC_JAL :
begin
jumpPc = nextPc + {Target, 2'b00} ;
DelaySlot = 1'b1;
RegArray[31] = nextPc + 32'd4;
$fwrite(instrLog, "OPCODE = JAL , Delay PC = 0x%08x, Jump PC = 0x%08x, REG[31] = 0x%08x", nextPc, jumpPc, RegArray[Rd]);
end
OPC_BEQ :
begin
$fwrite(instrLog, "OPCODE = BEQ , REG[%2d] 0x%08x == REG [%2d] 0x%08x ?", Rs, Rt, RegArray[Rs], RegArray[Rt]);
if (RegArray[Rs] == RegArray[Rt])
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_BNE :
begin
$fwrite(instrLog, "OPCODE = BNE , REG[%2d] 0x%08x != REG [%2d] 0x%08x ?", Rs, Rt, RegArray[Rs], RegArray[Rt]);
if (RegArray[Rs] != RegArray[Rt])
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_BLEZ :
begin
$fwrite(instrLog, "OPCODE = BLEZ , REG[%2d] = 0x%08x <= 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] == 32'd0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ; DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_BGTZ :
begin
$fwrite(instrLog, "OPCODE = BGTZ , REG[%2d] = 0x%08x > 0 ? ", Rs, RegArray[Rs]);
if (RegArray[Rs] > 32'd0)
begin
jumpPc = nextPc + {Immed, 2'b00} ;
DelaySlot = 1'b1;
$fwrite(instrLog, "TAKEN - Delay PC = 0x%08x, Jump PC = 0x%08x", nextPc, jumpPc);
end
else
begin
jumpPc = nextPc + 32'd4 ;
DelaySlot = 1'b1;
$fwrite(instrLog, "NOT TAKEN - Delay PC = 0x%08x", nextPc);
end
end
OPC_ADDI :
begin
RegArray[Rt] = RegArray[Rs] + SignXImmed;
$fwrite(instrLog, "OPCODE = ADDI , REG[%2d] = REG[%2d] + 0x%08x", Rt, Rs, SignXImmed);
end
OPC_ADDIU :
begin
RegArray[Rt] = RegArray[Rs] + SignXImmed;
$fwrite(instrLog, "OPCODE = ADDIU , REG[%2d] = REG[%2d] + 0x%08x", Rt, Rs, SignXImmed);
end
OPC_SLTI :
begin
$fwrite(instrLog, "OPCODE = SLTI , REG[%2d] 0x%08x < IMMED 0x%08x ?", Rs, RegArray[Rs], SignXImmed);
if (RegArray[Rs] < Immed)
begin
RegArray[Rt] = 5'd1;
$fwrite(instrLog, "SET - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
else
begin
RegArray[Rt] = 5'd0;
$fwrite(instrLog, "CLR - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
end
OPC_SLTIU :
begin
$fwrite(instrLog, "OPCODE = SLTIU , REG[%2d] 0x%08x < IMMED 0x%08x ?", Rs, RegArray[Rs], SignXImmed);
if (RegArray[Rs] < Immed)
begin
RegArray[Rt] = 5'd1;
$fwrite(instrLog, "SET - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
else
begin
RegArray[Rt] = 5'd0;
$fwrite(instrLog, "CLR - REG[%2d] = 0x%08x", Rt, RegArray[Rt]);
end
end
OPC_ANDI :
begin
RegArray[Rt] = RegArray[Rs] & ZeroXImmed;
$fwrite(instrLog, "OPCODE = ANDI , REG[%2d] = REG[%2d] 0x%08x AND 0x%08x", Rt, Rs, RegArray[Rs], ZeroXImmed);
end
OPC_ORI :
begin
RegArray[Rt] = RegArray[Rs] | ZeroXImmed;
$fwrite(instrLog, "OPCODE = ORI , REG[%2d] = REG[%2d] 0x%08x OR 0x%08x", Rt, Rs, RegArray[Rs], ZeroXImmed);
end
OPC_XORI :
begin
RegArray[Rt] = RegArray[Rs] ^ ZeroXImmed;
$fwrite(instrLog, "OPCODE = XOR , REG[%2d] = REG[%2d] 0x%08x XOR 0x%08x", Rt, Rs, RegArray[Rs], ZeroXImmed);
end
OPC_LUI :
begin
RegArray[Rt] = {Immed, 16'h0000};
$fwrite(instrLog, "OPCODE = LUI , REG[%2d] = 0x%04x0000", Rt, Immed);
end
OPC_COP0 :
begin
$fwrite(instrLog, "OPC_COP0 , ");
end
OPC_COP1 :
begin
$fwrite(instrLog, "OPC_COP1 , ");
end
OPC_COP2 :
begin
$fwrite(instrLog, "OPC_COP2 , ");
end
OPC_COP3 :
begin
$fwrite(instrLog, "OPC_COP3 , ");
end
OPC_LB :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0001;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LB , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LH :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0011;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LH , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LWL :
begin
$fwrite(instrLog, "OPC_LWL , ");
end
OPC_LW :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b1111;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LW , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LBU :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0001;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LBU , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LHU :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0011;
nextDataWe = 1'b0;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = 32'hXXXXXXXX;
nextDataReg = RegArray[Rt];
$fwrite(instrLog, "OPCODE = LHU , REG[%2d] = DATA[0x%08x]", Rt, nextDataAdr);
end
OPC_LWR :
begin
$fwrite(instrLog, "OPC_LWR , ");
end
OPC_SB :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0001;
nextDataWe = 1'b1;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = RegArray[Rt];
nextDataReg = 5'd0;
$fwrite(instrLog, "OPCODE = SB , DATA[0x%08x] = REG[%2d] 0x%08x", nextDataAdr, Rt, RegArray[Rt]);
end
OPC_SH :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b0011;
nextDataWe = 1'b1;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = RegArray[Rt];
nextDataReg = 5'd0;
$fwrite(instrLog, "OPCODE = SH , DATA[0x%08x] = REG[%2d] 0x%08x", nextDataAdr, Rt, RegArray[Rt]);
end
OPC_SWL :
begin
$fwrite(instrLog, "OPC_SWL , ");
end
OPC_SW :
begin
nextDataAdr = RegArray[Rs] + SignXImmed;
nextDataSel = 4'b1111;
nextDataWe = 1'b1;
nextDataDatRd = 32'hXXXXXXXX;
nextDataDatWr = RegArray[Rt];
nextDataReg = 5'd0;
$fwrite(instrLog, "OPCODE = SW , DATA[0x%08x] = REG[%2d] 0x%08x", nextDataAdr, Rt, RegArray[Rt]);
end
OPC_SWR :
begin
$fwrite(instrLog, "OPC_SWR , ");
end
OPC_LWC1 :
begin
$fwrite(instrLog, "OPC_LWC1 , ");
end
OPC_LWC2 :
begin
$fwrite(instrLog, "OPC_LWC2 , ");
end
OPC_LWC3 :
begin
$fwrite(instrLog, "OPC_LWC3 , ");
end
OPC_SWC1 :
begin
$fwrite(instrLog, "OPC_SWC1 , ");
end
OPC_SWC2 :
begin
$fwrite(instrLog, "OPC_SWC2 , ");
end
OPC_SWC3 :
begin
$fwrite(instrLog, "OPC_SWC3 , ");
end
endcase
end
$fwrite(instrLog, "\n");
end
end
end
endmodule | 1 |
138,360 | data/full_repos/permissive/83270534/mips1_top/rtl/cpu_icache.v | 83,270,534 | cpu_icache.v | v | 314 | 147 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_top/rtl/cpu_icache.v:48: Cannot find include file: wb_defs.v\n`include "wb_defs.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_top/rtl,data/full_repos/permissive/83270534/wb_defs.v\n data/full_repos/permissive/83270534/mips1_top/rtl,data/full_repos/permissive/83270534/wb_defs.v.v\n data/full_repos/permissive/83270534/mips1_top/rtl,data/full_repos/permissive/83270534/wb_defs.v.sv\n wb_defs.v\n wb_defs.v.v\n wb_defs.v.sv\n obj_dir/wb_defs.v\n obj_dir/wb_defs.v.v\n obj_dir/wb_defs.v.sv\n%Error: Exiting due to 1 error(s)\n' | 302,237 | module | module CPU_ICACHE
(
input CLK ,
input RST_SYNC ,
input [31:0] CORE_ADR_IN ,
input CORE_CYC_IN ,
input CORE_STB_IN ,
input CORE_WE_IN ,
input [ 3:0] CORE_SEL_IN ,
output CORE_STALL_OUT ,
output CORE_ACK_OUT ,
output CORE_ERR_OUT ,
output [31:0] CORE_DAT_RD_OUT ,
input [31:0] CORE_DAT_WR_IN ,
output [31:0] CACHE_ADR_OUT ,
output CACHE_CYC_OUT ,
output CACHE_STB_OUT ,
output CACHE_WE_OUT ,
output [ 3:0] CACHE_SEL_OUT ,
output [ 2:0] CACHE_CTI_OUT ,
output [ 1:0] CACHE_BTE_OUT ,
input CACHE_ACK_IN ,
input CACHE_STALL_IN ,
input CACHE_ERR_IN ,
input [31:0] CACHE_DAT_RD_IN ,
output [31:0] CACHE_DAT_WR_OUT
);
`include "wb_defs.v"
wire BusReadReq;
wire BusReadAck;
wire BusLastAck;
wire [31:0] BusReadData;
wire TagRamStoreEn;
wire TagRamFlushEn;
reg TagRamFlushEnReg;
wire [9:2] TagRamAddr ;
wire TagRamWriteEn ;
wire [20:0] TagRamWriteData ;
wire [20:0] TagRamReadData ;
wire [11:2] CacheRamReadAddr ;
wire [11:2] CacheRamWriteAddr ;
wire CacheRamWriteEn ;
wire [31:0] CacheRamReadData ;
wire [31:0] CacheRamWriteData ;
wire [19:0] Tag;
wire [7:0] LineIndex;
wire [1:0] WdIndex;
reg [31:0] CoreAdrReg;
reg [19:0] TagReg;
reg [7:0] LineIndexReg;
reg [1:0] WdIndexReg;
wire [9:0] LineWdIndex;
wire [9:0] LineWdIndexReg;
wire CoreWriteAddrStb ;
wire CoreReadAddrStb ;
reg CoreReadAddrStbReg ;
wire CoreAddrStb ;
wire TagHit ;
wire ValidHit ;
wire ValidTagHit ;
reg [1:0] FillCntVal;
assign Tag = CORE_ADR_IN[31:12];
assign LineIndex = CORE_ADR_IN[11: 4];
assign WdIndex = CORE_ADR_IN[ 3: 2];
assign TagReg = CoreAdrReg[31:12];
assign LineIndexReg = CoreAdrReg[11: 4];
assign WdIndexReg = CoreAdrReg[ 3: 2];
assign CoreWriteAddrStb = CORE_CYC_IN & CORE_STB_IN & CORE_WE_IN;
assign CoreReadAddrStb = CORE_CYC_IN & CORE_STB_IN & ~CORE_WE_IN & ~CORE_STALL_OUT;
assign CoreAddrStb = CoreReadAddrStb | CoreWriteAddrStb;
assign TagHit = (TagRamReadData[19:0] == TagReg);
assign ValidHit = TagRamReadData[20];
assign ValidTagHit = ValidHit & TagHit;
assign BusReadReq = CORE_CYC_IN & CoreReadAddrStbReg & ~ValidTagHit;
assign CORE_ACK_OUT = TagRamFlushEn ? 1'b0 : TagRamFlushEnReg ? 1'b1 : ValidTagHit ;
assign CORE_STALL_OUT = (TagRamFlushEnReg) | (CoreReadAddrStbReg & ~ValidTagHit);
assign CORE_DAT_RD_OUT = CacheRamReadData ;
assign CORE_ERR_OUT = 1'b0;
assign TagRamStoreEn = BusReadReq & BusReadAck & BusLastAck;
assign TagRamFlushEn =CORE_WE_IN & CoreWriteAddrStb & ~CORE_STALL_OUT;
assign TagRamAddr = BusReadReq ? LineIndexReg : LineIndex ;
assign TagRamWriteEn = TagRamStoreEn | TagRamFlushEn;
assign TagRamWriteData[20] = TagRamFlushEn ? 1'b0 : 1'b1;
assign TagRamWriteData[19:0] = TagReg;
assign LineWdIndex = {LineIndex, WdIndex};
assign LineWdIndexReg = {LineIndexReg, WdIndexReg};
assign CacheRamReadAddr = BusReadReq ? LineWdIndexReg : LineWdIndex;
assign CacheRamWriteAddr = {LineIndexReg, FillCntVal };
assign CacheRamWriteEn = BusReadReq & BusReadAck;
assign CacheRamWriteData = BusReadData;
always @(posedge CLK)
begin : CORE_ADR_REG
if (RST_SYNC)
begin
CoreAdrReg <= 32'h0000_0000;
end
else if (CoreAddrStb)
begin
CoreAdrReg <= CORE_ADR_IN;
end
end
always @(posedge CLK)
begin : CORE_ADDR_STB_REG
if (RST_SYNC)
begin
CoreReadAddrStbReg <= 1'b0;
end
else if (CoreReadAddrStb)
begin
CoreReadAddrStbReg <= 1'b1;
end
else if (TagRamStoreEn || ValidTagHit)
begin
CoreReadAddrStbReg <= 1'b0;
end
end
always @(posedge CLK)
begin : CORE_FLUSH_EN_REG
if (RST_SYNC)
begin
TagRamFlushEnReg <= 1'b0;
end
else
begin
TagRamFlushEnReg <= TagRamFlushEn;
end
end
always @(posedge CLK)
begin : FILL_COUNTER
if (RST_SYNC)
begin
FillCntVal <= 2'd0;
end
else if (CoreReadAddrStb)
begin
FillCntVal <= 2'd0;
end
else if (CacheRamWriteEn)
begin
FillCntVal <= FillCntVal + 2'd1;
end
end
SPRAM
#(.ADDR_WIDTH ( 8),
.DATA_WIDTH (21)
)
tag_spram
(
.CLK (CLK ),
.EN (1'b1 ),
.WRITE_EN_IN (TagRamWriteEn ),
.ADDR_IN (TagRamAddr ),
.WRITE_DATA_IN (TagRamWriteData ),
.READ_DATA_OUT (TagRamReadData )
);
DPRAM
#(.ADDR_WIDTH (10) ,
.DATA_WIDTH (32)
)
cache_dpram
(
.CLK (CLK ),
.ENA (1'b1 ),
.ENB (1'b1 ),
.WRITE_EN_A_IN (CacheRamWriteEn ),
.ADDR_A_IN (CacheRamWriteAddr ),
.ADDR_B_IN (CacheRamReadAddr ),
.WRITE_DATA_A_IN (BusReadData ),
.READ_DATA_A_OUT ( ),
.READ_DATA_B_OUT (CacheRamReadData )
);
WB_MASTER
#(.COMB_CYC (1) )
wb_master
(
.CLK (CLK ),
.EN (1'b1 ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_SYNC ),
.WB_ADR_OUT (CACHE_ADR_OUT ),
.WB_CYC_OUT (CACHE_CYC_OUT ),
.WB_STB_OUT (CACHE_STB_OUT ),
.WB_WE_OUT (CACHE_WE_OUT ),
.WB_SEL_OUT (CACHE_SEL_OUT ),
.WB_CTI_OUT (CACHE_CTI_OUT ),
.WB_BTE_OUT (CACHE_BTE_OUT ),
.WB_ACK_IN (CACHE_ACK_IN ),
.WB_STALL_IN (CACHE_STALL_IN ),
.WB_ERR_IN (CACHE_ERR_IN ),
.WB_DAT_RD_IN (CACHE_DAT_RD_IN ),
.WB_DAT_WR_OUT (CACHE_DAT_WR_OUT ),
.BUS_START_ADDR_IN ({TagReg, LineIndexReg, 4'd0} ),
.BUS_READ_REQ_IN (BusReadReq ),
.BUS_READ_ACK_OUT (BusReadAck ),
.BUS_WRITE_REQ_IN (1'b0 ),
.BUS_WRITE_ACK_OUT ( ),
.BUS_LAST_ACK_OUT (BusLastAck ),
.BUS_SIZE_IN (2'd2 ),
.BUS_LEN_IN (5'd4 ),
.BUS_BURST_ADDR_INC_IN (1'b1 ),
.BUS_READ_DATA_OUT (BusReadData ),
.BUS_WRITE_DATA_IN (32'h0000_0000 )
);
endmodule | module CPU_ICACHE
(
input CLK ,
input RST_SYNC ,
input [31:0] CORE_ADR_IN ,
input CORE_CYC_IN ,
input CORE_STB_IN ,
input CORE_WE_IN ,
input [ 3:0] CORE_SEL_IN ,
output CORE_STALL_OUT ,
output CORE_ACK_OUT ,
output CORE_ERR_OUT ,
output [31:0] CORE_DAT_RD_OUT ,
input [31:0] CORE_DAT_WR_IN ,
output [31:0] CACHE_ADR_OUT ,
output CACHE_CYC_OUT ,
output CACHE_STB_OUT ,
output CACHE_WE_OUT ,
output [ 3:0] CACHE_SEL_OUT ,
output [ 2:0] CACHE_CTI_OUT ,
output [ 1:0] CACHE_BTE_OUT ,
input CACHE_ACK_IN ,
input CACHE_STALL_IN ,
input CACHE_ERR_IN ,
input [31:0] CACHE_DAT_RD_IN ,
output [31:0] CACHE_DAT_WR_OUT
); |
`include "wb_defs.v"
wire BusReadReq;
wire BusReadAck;
wire BusLastAck;
wire [31:0] BusReadData;
wire TagRamStoreEn;
wire TagRamFlushEn;
reg TagRamFlushEnReg;
wire [9:2] TagRamAddr ;
wire TagRamWriteEn ;
wire [20:0] TagRamWriteData ;
wire [20:0] TagRamReadData ;
wire [11:2] CacheRamReadAddr ;
wire [11:2] CacheRamWriteAddr ;
wire CacheRamWriteEn ;
wire [31:0] CacheRamReadData ;
wire [31:0] CacheRamWriteData ;
wire [19:0] Tag;
wire [7:0] LineIndex;
wire [1:0] WdIndex;
reg [31:0] CoreAdrReg;
reg [19:0] TagReg;
reg [7:0] LineIndexReg;
reg [1:0] WdIndexReg;
wire [9:0] LineWdIndex;
wire [9:0] LineWdIndexReg;
wire CoreWriteAddrStb ;
wire CoreReadAddrStb ;
reg CoreReadAddrStbReg ;
wire CoreAddrStb ;
wire TagHit ;
wire ValidHit ;
wire ValidTagHit ;
reg [1:0] FillCntVal;
assign Tag = CORE_ADR_IN[31:12];
assign LineIndex = CORE_ADR_IN[11: 4];
assign WdIndex = CORE_ADR_IN[ 3: 2];
assign TagReg = CoreAdrReg[31:12];
assign LineIndexReg = CoreAdrReg[11: 4];
assign WdIndexReg = CoreAdrReg[ 3: 2];
assign CoreWriteAddrStb = CORE_CYC_IN & CORE_STB_IN & CORE_WE_IN;
assign CoreReadAddrStb = CORE_CYC_IN & CORE_STB_IN & ~CORE_WE_IN & ~CORE_STALL_OUT;
assign CoreAddrStb = CoreReadAddrStb | CoreWriteAddrStb;
assign TagHit = (TagRamReadData[19:0] == TagReg);
assign ValidHit = TagRamReadData[20];
assign ValidTagHit = ValidHit & TagHit;
assign BusReadReq = CORE_CYC_IN & CoreReadAddrStbReg & ~ValidTagHit;
assign CORE_ACK_OUT = TagRamFlushEn ? 1'b0 : TagRamFlushEnReg ? 1'b1 : ValidTagHit ;
assign CORE_STALL_OUT = (TagRamFlushEnReg) | (CoreReadAddrStbReg & ~ValidTagHit);
assign CORE_DAT_RD_OUT = CacheRamReadData ;
assign CORE_ERR_OUT = 1'b0;
assign TagRamStoreEn = BusReadReq & BusReadAck & BusLastAck;
assign TagRamFlushEn =CORE_WE_IN & CoreWriteAddrStb & ~CORE_STALL_OUT;
assign TagRamAddr = BusReadReq ? LineIndexReg : LineIndex ;
assign TagRamWriteEn = TagRamStoreEn | TagRamFlushEn;
assign TagRamWriteData[20] = TagRamFlushEn ? 1'b0 : 1'b1;
assign TagRamWriteData[19:0] = TagReg;
assign LineWdIndex = {LineIndex, WdIndex};
assign LineWdIndexReg = {LineIndexReg, WdIndexReg};
assign CacheRamReadAddr = BusReadReq ? LineWdIndexReg : LineWdIndex;
assign CacheRamWriteAddr = {LineIndexReg, FillCntVal };
assign CacheRamWriteEn = BusReadReq & BusReadAck;
assign CacheRamWriteData = BusReadData;
always @(posedge CLK)
begin : CORE_ADR_REG
if (RST_SYNC)
begin
CoreAdrReg <= 32'h0000_0000;
end
else if (CoreAddrStb)
begin
CoreAdrReg <= CORE_ADR_IN;
end
end
always @(posedge CLK)
begin : CORE_ADDR_STB_REG
if (RST_SYNC)
begin
CoreReadAddrStbReg <= 1'b0;
end
else if (CoreReadAddrStb)
begin
CoreReadAddrStbReg <= 1'b1;
end
else if (TagRamStoreEn || ValidTagHit)
begin
CoreReadAddrStbReg <= 1'b0;
end
end
always @(posedge CLK)
begin : CORE_FLUSH_EN_REG
if (RST_SYNC)
begin
TagRamFlushEnReg <= 1'b0;
end
else
begin
TagRamFlushEnReg <= TagRamFlushEn;
end
end
always @(posedge CLK)
begin : FILL_COUNTER
if (RST_SYNC)
begin
FillCntVal <= 2'd0;
end
else if (CoreReadAddrStb)
begin
FillCntVal <= 2'd0;
end
else if (CacheRamWriteEn)
begin
FillCntVal <= FillCntVal + 2'd1;
end
end
SPRAM
#(.ADDR_WIDTH ( 8),
.DATA_WIDTH (21)
)
tag_spram
(
.CLK (CLK ),
.EN (1'b1 ),
.WRITE_EN_IN (TagRamWriteEn ),
.ADDR_IN (TagRamAddr ),
.WRITE_DATA_IN (TagRamWriteData ),
.READ_DATA_OUT (TagRamReadData )
);
DPRAM
#(.ADDR_WIDTH (10) ,
.DATA_WIDTH (32)
)
cache_dpram
(
.CLK (CLK ),
.ENA (1'b1 ),
.ENB (1'b1 ),
.WRITE_EN_A_IN (CacheRamWriteEn ),
.ADDR_A_IN (CacheRamWriteAddr ),
.ADDR_B_IN (CacheRamReadAddr ),
.WRITE_DATA_A_IN (BusReadData ),
.READ_DATA_A_OUT ( ),
.READ_DATA_B_OUT (CacheRamReadData )
);
WB_MASTER
#(.COMB_CYC (1) )
wb_master
(
.CLK (CLK ),
.EN (1'b1 ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_SYNC ),
.WB_ADR_OUT (CACHE_ADR_OUT ),
.WB_CYC_OUT (CACHE_CYC_OUT ),
.WB_STB_OUT (CACHE_STB_OUT ),
.WB_WE_OUT (CACHE_WE_OUT ),
.WB_SEL_OUT (CACHE_SEL_OUT ),
.WB_CTI_OUT (CACHE_CTI_OUT ),
.WB_BTE_OUT (CACHE_BTE_OUT ),
.WB_ACK_IN (CACHE_ACK_IN ),
.WB_STALL_IN (CACHE_STALL_IN ),
.WB_ERR_IN (CACHE_ERR_IN ),
.WB_DAT_RD_IN (CACHE_DAT_RD_IN ),
.WB_DAT_WR_OUT (CACHE_DAT_WR_OUT ),
.BUS_START_ADDR_IN ({TagReg, LineIndexReg, 4'd0} ),
.BUS_READ_REQ_IN (BusReadReq ),
.BUS_READ_ACK_OUT (BusReadAck ),
.BUS_WRITE_REQ_IN (1'b0 ),
.BUS_WRITE_ACK_OUT ( ),
.BUS_LAST_ACK_OUT (BusLastAck ),
.BUS_SIZE_IN (2'd2 ),
.BUS_LEN_IN (5'd4 ),
.BUS_BURST_ADDR_INC_IN (1'b1 ),
.BUS_READ_DATA_OUT (BusReadData ),
.BUS_WRITE_DATA_IN (32'h0000_0000 )
);
endmodule | 1 |
138,364 | data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v | 83,270,534 | testcase.v | v | 185 | 128 | [] | [] | [] | null | line:11: before: "not" | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:11: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:12: Cannot find include file: mips1_top_defines.v\n`include "mips1_top_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:25: Unsupported or unknown PLI call: $urandom_range\n const int NumBursts = $urandom_range(MIN_BURSTS, MAX_BURSTS);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:35: Define or directive not defined: \'`RST\'\n while (1\'b0 !== `RST)\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:35: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n while (1\'b0 !== `RST)\n ^\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:36: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:43: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:55: Unsupported or unknown PLI call: $urandom_range\n IbfmBurstLength = $urandom_range(MIN_BURST_LEN, MAX_BURST_LEN);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:56: Unsupported or unknown PLI call: $urandom_range\n IbfmAddrBase = $urandom_range(InstAddrBase, InstAddrBase + ReadWriteSize - (IbfmBurstLength << 2));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:60: Unsupported: Dynamic array new\n Addr = new[IbfmBurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:61: Unsupported: Dynamic array new\n WriteData = new[IbfmBurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:62: Unsupported: Dynamic array new\n ReadData = new[IbfmBurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:71: Unsupported or unknown PLI call: $urandom\n WriteData[i] = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:74: Define or directive not defined: \'`IBFM\'\n `IBFM.wbBurstWrite32b(Addr, WriteData);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:74: syntax error, unexpected \'.\'\n `IBFM.wbBurstWrite32b(Addr, WriteData);\n ^\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:75: Define or directive not defined: \'`IBFM\'\n `IBFM.wbBurstRead32b(Addr, ReadData);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:96: Unsupported or unknown PLI call: $urandom_range\n repeat ($urandom_range(0, 8))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:97: syntax error, unexpected \'@\'\n @(posedge `CLK);\n ^\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:97: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:113: Unsupported or unknown PLI call: $urandom_range\n DbfmBurstLength = $urandom_range(MIN_BURST_LEN, MAX_BURST_LEN);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:114: Unsupported or unknown PLI call: $urandom_range\n DbfmAddrBase = $urandom_range(DataAddrBase, DataAddrBase + ReadWriteSize - (DbfmBurstLength << 2));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:118: Unsupported: Dynamic array new\n Addr = new[DbfmBurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:119: Unsupported: Dynamic array new\n WriteData = new[DbfmBurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:120: Unsupported: Dynamic array new\n ReadData = new[DbfmBurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:129: Unsupported or unknown PLI call: $urandom\n WriteData[i] = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:132: Define or directive not defined: \'`DBFM\'\n `DBFM.wbBurstWrite32b(Addr, WriteData);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:132: syntax error, unexpected \'.\'\n `DBFM.wbBurstWrite32b(Addr, WriteData);\n ^\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:133: Define or directive not defined: \'`DBFM\'\n `DBFM.wbBurstRead32b(Addr, ReadData);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:154: Unsupported or unknown PLI call: $urandom_range\n repeat ($urandom_range(0, 8))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:155: syntax error, unexpected \'@\'\n @(posedge `CLK);\n ^\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:155: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_inst_uncached_mixed_burst/testcase.v:176: Unsupported: Ignoring delay on this delayed statement.\n #10ms;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 31 error(s), 1 warning(s)\n' | 302,244 | module | module TESTCASE ();
`include "tb_defines.v"
`include "mips1_top_defines.v"
parameter MIN_BURST_LEN = 1;
parameter MAX_BURST_LEN = 32;
parameter MIN_BURSTS = 1;
parameter MAX_BURSTS = 32;
initial
begin
const int NumBursts = $urandom_range(MIN_BURSTS, MAX_BURSTS);
int InstAddrBase = USER_RAM_KSEG1_BASE;
int DataAddrBase = USER_RAM_SIZE >> 1;
int ReadWriteSize = USER_RAM_SIZE >> 1;
int testPass = 1;
while (1'b0 !== `RST)
@(posedge `CLK);
$display("[INFO ] Reset de-asserted at time %t", $time);
fork
begin : IBFM_THREAD
int IbfmAddrBase;
int IbfmBurstLength;
int Addr [];
int WriteData [];
int ReadData [];
repeat (NumBursts)
begin : BURST_LOOP
IbfmBurstLength = $urandom_range(MIN_BURST_LEN, MAX_BURST_LEN);
IbfmAddrBase = $urandom_range(InstAddrBase, InstAddrBase + ReadWriteSize - (IbfmBurstLength << 2));
IbfmAddrBase = IbfmAddrBase & 32'hffff_fffc;
$display("[INFO ] IBFM : Beginning Burst: Start Address 0x%x, Length %d at time %t", IbfmAddrBase, IbfmBurstLength, $time);
Addr = new[IbfmBurstLength];
WriteData = new[IbfmBurstLength];
ReadData = new[IbfmBurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = IbfmAddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
`IBFM.wbBurstWrite32b(Addr, WriteData);
`IBFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] IBFM : Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] IBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] IBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
Addr.delete();
WriteData.delete();
ReadData.delete();
repeat ($urandom_range(0, 8))
@(posedge `CLK);
end
end
begin : DBFM_THREAD
int DbfmAddrBase;
int DbfmBurstLength;
int Addr [];
int WriteData [];
int ReadData [];
repeat (NumBursts)
begin : BURST_LOOP
DbfmBurstLength = $urandom_range(MIN_BURST_LEN, MAX_BURST_LEN);
DbfmAddrBase = $urandom_range(DataAddrBase, DataAddrBase + ReadWriteSize - (DbfmBurstLength << 2));
DbfmAddrBase = DbfmAddrBase & 32'hffff_fffc;
$display("[INFO ] DBFM : Beginning Burst: Start Address 0x%x, Length %d at time %t", DbfmAddrBase, DbfmBurstLength, $time);
Addr = new[DbfmBurstLength];
WriteData = new[DbfmBurstLength];
ReadData = new[DbfmBurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = DbfmAddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
`DBFM.wbBurstWrite32b(Addr, WriteData);
`DBFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] DBFM : Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] DBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] DBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
Addr.delete();
WriteData.delete();
ReadData.delete();
repeat ($urandom_range(0, 8))
@(posedge `CLK);
end
end
join
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
$finish();
end
initial
begin
#10ms;
$display("[FAIL] MIPS1 test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`include "tb_defines.v"
`include "mips1_top_defines.v"
parameter MIN_BURST_LEN = 1;
parameter MAX_BURST_LEN = 32;
parameter MIN_BURSTS = 1;
parameter MAX_BURSTS = 32;
initial
begin
const int NumBursts = $urandom_range(MIN_BURSTS, MAX_BURSTS);
int InstAddrBase = USER_RAM_KSEG1_BASE;
int DataAddrBase = USER_RAM_SIZE >> 1;
int ReadWriteSize = USER_RAM_SIZE >> 1;
int testPass = 1;
while (1'b0 !== `RST)
@(posedge `CLK);
$display("[INFO ] Reset de-asserted at time %t", $time);
fork
begin : IBFM_THREAD
int IbfmAddrBase;
int IbfmBurstLength;
int Addr [];
int WriteData [];
int ReadData [];
repeat (NumBursts)
begin : BURST_LOOP
IbfmBurstLength = $urandom_range(MIN_BURST_LEN, MAX_BURST_LEN);
IbfmAddrBase = $urandom_range(InstAddrBase, InstAddrBase + ReadWriteSize - (IbfmBurstLength << 2));
IbfmAddrBase = IbfmAddrBase & 32'hffff_fffc;
$display("[INFO ] IBFM : Beginning Burst: Start Address 0x%x, Length %d at time %t", IbfmAddrBase, IbfmBurstLength, $time);
Addr = new[IbfmBurstLength];
WriteData = new[IbfmBurstLength];
ReadData = new[IbfmBurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = IbfmAddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
`IBFM.wbBurstWrite32b(Addr, WriteData);
`IBFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] IBFM : Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] IBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] IBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
Addr.delete();
WriteData.delete();
ReadData.delete();
repeat ($urandom_range(0, 8))
@(posedge `CLK);
end
end
begin : DBFM_THREAD
int DbfmAddrBase;
int DbfmBurstLength;
int Addr [];
int WriteData [];
int ReadData [];
repeat (NumBursts)
begin : BURST_LOOP
DbfmBurstLength = $urandom_range(MIN_BURST_LEN, MAX_BURST_LEN);
DbfmAddrBase = $urandom_range(DataAddrBase, DataAddrBase + ReadWriteSize - (DbfmBurstLength << 2));
DbfmAddrBase = DbfmAddrBase & 32'hffff_fffc;
$display("[INFO ] DBFM : Beginning Burst: Start Address 0x%x, Length %d at time %t", DbfmAddrBase, DbfmBurstLength, $time);
Addr = new[DbfmBurstLength];
WriteData = new[DbfmBurstLength];
ReadData = new[DbfmBurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = DbfmAddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
`DBFM.wbBurstWrite32b(Addr, WriteData);
`DBFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] DBFM : Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] DBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] DBFM : Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
Addr.delete();
WriteData.delete();
ReadData.delete();
repeat ($urandom_range(0, 8))
@(posedge `CLK);
end
end
join
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
$finish();
end
initial
begin
#10ms;
$display("[FAIL] MIPS1 test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,365 | data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v | 83,270,534 | testcase.v | v | 86 | 104 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:8: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:15: Unsupported or unknown PLI call: $urandom_range\n const int BurstLength = $urandom_range(2, 2);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:24: Unsupported: Dynamic array new\n Addr = new[BurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:25: Unsupported: Dynamic array new\n WriteData = new[BurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:26: Unsupported: Dynamic array new\n ReadData = new[BurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:36: Unsupported or unknown PLI call: $urandom\n WriteData[i] = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:40: Define or directive not defined: \'`RST\'\n while (1\'b0 !== `RST)\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:40: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n while (1\'b0 !== `RST)\n ^\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:41: Define or directive not defined: \'`CLK\'\n @(posedge `CLK);\n ^~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:43: Define or directive not defined: \'`DBFM\'\n `DBFM.wbBurstWrite32b(Addr, WriteData);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:44: Define or directive not defined: \'`DBFM\'\n `DBFM.wbBurstRead32b(Addr, ReadData);\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:60: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mips1_top/sim/platform_ram/data_simple_burst/testcase.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10ms;\n ^\n%Error: Exiting due to 11 error(s), 2 warning(s)\n' | 302,247 | module | module TESTCASE ();
`include "tb_defines.v"
initial
begin
const int BurstLength = $urandom_range(2, 2);
const int AddrBase = 32'h0000_0100;
int testPass = 1;
int Addr [];
int WriteData [];
int ReadData [];
Addr = new[BurstLength];
WriteData = new[BurstLength];
ReadData = new[BurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = AddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
while (1'b0 !== `RST)
@(posedge `CLK);
`DBFM.wbBurstWrite32b(Addr, WriteData);
`DBFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
#1000ns;
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
$finish();
end
initial
begin
#10ms;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`include "tb_defines.v"
initial
begin
const int BurstLength = $urandom_range(2, 2);
const int AddrBase = 32'h0000_0100;
int testPass = 1;
int Addr [];
int WriteData [];
int ReadData [];
Addr = new[BurstLength];
WriteData = new[BurstLength];
ReadData = new[BurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = AddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
while (1'b0 !== `RST)
@(posedge `CLK);
`DBFM.wbBurstWrite32b(Addr, WriteData);
`DBFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
#1000ns;
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
$finish();
end
initial
begin
#10ms;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,368 | data/full_repos/permissive/83270534/mips1_top/tb/tb_top.v | 83,270,534 | tb_top.v | v | 112 | 97 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mips1_top/tb/tb_top.v:11: Cannot find include file: mips1_top_defines.v\n`include "mips1_top_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mips1_top/tb,data/full_repos/permissive/83270534/mips1_top_defines.v\n data/full_repos/permissive/83270534/mips1_top/tb,data/full_repos/permissive/83270534/mips1_top_defines.v.v\n data/full_repos/permissive/83270534/mips1_top/tb,data/full_repos/permissive/83270534/mips1_top_defines.v.sv\n mips1_top_defines.v\n mips1_top_defines.v.v\n mips1_top_defines.v.sv\n obj_dir/mips1_top_defines.v\n obj_dir/mips1_top_defines.v.v\n obj_dir/mips1_top_defines.v.sv\n%Error: data/full_repos/permissive/83270534/mips1_top/tb/tb_top.v:12: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 302,255 | module | module TB_TOP ();
`include "mips1_top_defines.v"
`include "tb_defines.v"
wire Clk;
wire Rst;
wire [31:0] WbAdr ;
wire WbCyc ;
wire WbStb ;
wire WbWe ;
wire [ 3:0] WbSel ;
wire [ 2:0] WbCti ;
wire [ 1:0] WbBte ;
wire WbAck ;
wire WbStall ;
wire WbErr ;
wire [31:0] WbDatRd ;
wire [31:0] WbDatWr ;
wire [5:0] HwIrq = 6'd0;
CLK_RST_GEN
#(.CLK_HALF_PERIOD (5)
)
clk_rst_gen
(
.CLK_OUT (Clk ),
.RST_OUT (Rst )
);
TESTCASE testcase ();
MIPS1_TOP mips1_top
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_OUT (WbAdr ),
.WB_CYC_OUT (WbCyc ),
.WB_STB_OUT (WbStb ),
.WB_WE_OUT (WbWe ),
.WB_SEL_OUT (WbSel ),
.WB_CTI_OUT (WbCti ),
.WB_BTE_OUT (WbBte ),
.WB_ACK_IN (WbAck ),
.WB_STALL_IN (WbStall ),
.WB_ERR_IN (WbErr ),
.WB_DAT_RD_IN (WbDatRd ),
.WB_DAT_WR_OUT (WbDatWr ),
.HW_IRQ_IN (HwIrq )
);
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000 ),
.MEM_SIZE_P2 (21),
.MAX_LATENCY (4)
)
wb_slave_bfm_platform_ram
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbAdr ),
.WB_CYC_IN (WbCyc ),
.WB_STB_IN (WbStb ),
.WB_WE_IN (WbWe ),
.WB_SEL_IN (WbSel ),
.WB_CTI_IN (WbCti ),
.WB_BTE_IN (WbBte ),
.WB_ACK_OUT (WbAck ),
.WB_STALL_OUT (WbStall ),
.WB_ERR_OUT (WbErr ),
.WB_DAT_RD_OUT (WbDatRd ),
.WB_DAT_WR_IN (WbDatWr )
);
endmodule | module TB_TOP (); |
`include "mips1_top_defines.v"
`include "tb_defines.v"
wire Clk;
wire Rst;
wire [31:0] WbAdr ;
wire WbCyc ;
wire WbStb ;
wire WbWe ;
wire [ 3:0] WbSel ;
wire [ 2:0] WbCti ;
wire [ 1:0] WbBte ;
wire WbAck ;
wire WbStall ;
wire WbErr ;
wire [31:0] WbDatRd ;
wire [31:0] WbDatWr ;
wire [5:0] HwIrq = 6'd0;
CLK_RST_GEN
#(.CLK_HALF_PERIOD (5)
)
clk_rst_gen
(
.CLK_OUT (Clk ),
.RST_OUT (Rst )
);
TESTCASE testcase ();
MIPS1_TOP mips1_top
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_OUT (WbAdr ),
.WB_CYC_OUT (WbCyc ),
.WB_STB_OUT (WbStb ),
.WB_WE_OUT (WbWe ),
.WB_SEL_OUT (WbSel ),
.WB_CTI_OUT (WbCti ),
.WB_BTE_OUT (WbBte ),
.WB_ACK_IN (WbAck ),
.WB_STALL_IN (WbStall ),
.WB_ERR_IN (WbErr ),
.WB_DAT_RD_IN (WbDatRd ),
.WB_DAT_WR_OUT (WbDatWr ),
.HW_IRQ_IN (HwIrq )
);
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000 ),
.MEM_SIZE_P2 (21),
.MAX_LATENCY (4)
)
wb_slave_bfm_platform_ram
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbAdr ),
.WB_CYC_IN (WbCyc ),
.WB_STB_IN (WbStb ),
.WB_WE_IN (WbWe ),
.WB_SEL_IN (WbSel ),
.WB_CTI_IN (WbCti ),
.WB_BTE_IN (WbBte ),
.WB_ACK_OUT (WbAck ),
.WB_STALL_OUT (WbStall ),
.WB_ERR_OUT (WbErr ),
.WB_DAT_RD_OUT (WbDatRd ),
.WB_DAT_WR_IN (WbDatWr )
);
endmodule | 1 |
138,372 | data/full_repos/permissive/83270534/psx_top/rtl/dmac_peri.v | 83,270,534 | dmac_peri.v | v | 437 | 116 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/rtl/dmac_peri.v:45: Cannot find include file: psx_mem_map.vh\n`include "psx_mem_map.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh.v\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh.sv\n psx_mem_map.vh\n psx_mem_map.vh.v\n psx_mem_map.vh.sv\n obj_dir/psx_mem_map.vh\n obj_dir/psx_mem_map.vh.v\n obj_dir/psx_mem_map.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 302,260 | module | module DMAC_PERI
#(parameter BLK_FIFO_DEPTH = 16,
parameter BLK_FIFO_WIDTH = 32
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input CFG_DMA_CHCR_TR_IN ,
output CFG_DMA_CHCR_TR_CLR_OUT ,
input CFG_DMA_CHCR_CO_IN ,
input CFG_DMA_CHCR_DR_IN ,
input [31:0] CFG_DMA_MADR_IN ,
input [15:0] CFG_DMA_BLK_CNT_IN ,
input [15:0] CFG_DMA_BLK_SIZE_IN ,
output BUS_READ_REQ_OUT ,
input BUS_READ_ACK_IN ,
output BUS_WRITE_REQ_OUT ,
input BUS_WRITE_ACK_IN ,
input BUS_LAST_ACK_IN ,
output [31:0] BUS_START_ADDR_OUT ,
output [ 1:0] BUS_SIZE_OUT ,
output [ 4:0] BUS_LEN_OUT ,
output BUS_BURST_ADDR_INC_OUT ,
output [31:0] BUS_WRITE_DATA_OUT ,
input [31:0] BUS_READ_DATA_IN ,
input DMAC_REQ_IN ,
output DMAC_ACK_OUT ,
output DMAC_IRQ_OUT
);
`include "psx_mem_map.vh"
parameter [2:0] DPFSM_IDLE = 3'h0;
parameter [2:0] DPFSM_REG_CFG = 3'h1;
parameter [2:0] DPFSM_SRC_RD = 3'h2;
parameter [2:0] DPFSM_SRC_RD_DONE = 3'h3;
parameter [2:0] DPFSM_DST_WR = 3'h4;
parameter [2:0] DPFSM_DST_WR_DONE = 3'h5;
parameter [2:0] DPFSM_DMA_ACK = 3'h6;
reg CfgDmaChcrDrReg ;
reg [ 4:0] CfgDmaBlkSizeReg ;
wire [31:0] SrcAddr ;
wire SrcBusAddrInc ;
wire [31:0] DstAddr ;
wire DstAddrInc ;
reg [31:2] AddrCntVal ;
wire [31:0] AddrCntValByte ;
reg [15:0] BlkTmrVal ;
reg [ 2:0] DpfsmStateCur ;
reg [ 2:0] DpfsmStateNxt ;
reg FsmCfgRegEn ;
reg [31:0] BusAddrNxt ;
reg [31:0] BusAddr ;
reg BusAddrIncNxt ;
reg BusAddrInc ;
reg BusRegEn ;
reg BusReadReqNxt ;
reg BusReadReq ;
reg BusWriteReqNxt ;
reg BusWriteReq ;
reg DmacAckNxt ;
reg DmacAck ;
wire FifoWrFull ;
wire FifoRdEmpty ;
assign SrcAddr = CfgDmaChcrDrReg ? AddrCntValByte : GPU_DATA ;
assign DstAddr = CfgDmaChcrDrReg ? GPU_DATA : AddrCntValByte ;
assign DstAddrInc = CfgDmaChcrDrReg ? 1'b0 : 1'b1 ;
assign SrcBusAddrInc = CfgDmaChcrDrReg ? 1'b1 : 1'b0 ;
assign DstBusAddrInc = CfgDmaChcrDrReg ? 1'b0 : 1'b1 ;
assign AddrCntValByte = {AddrCntVal, 2'b00};
assign BUS_READ_REQ_OUT = BusReadReq ;
assign BUS_WRITE_REQ_OUT = BusWriteReq ;
assign BUS_START_ADDR_OUT = BusAddr ;
assign BUS_SIZE_OUT = 2'b10 ;
assign BUS_LEN_OUT = CfgDmaBlkSizeReg ;
assign BUS_BURST_ADDR_INC_OUT = BusAddrInc ;
assign DMAC_ACK_OUT = DmacAck ;
assign DMAC_IRQ_OUT = DmacAck ;
assign CFG_DMA_CHCR_TR_CLR_OUT = DmacAck ;
always @(posedge CLK or posedge RST_ASYNC)
begin : CHCR_DR_REG
if (RST_ASYNC)
begin
CfgDmaChcrDrReg <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmaChcrDrReg <= 1'b0;
end
else if (EN && FsmCfgRegEn)
begin
CfgDmaChcrDrReg <= CFG_DMA_CHCR_DR_IN;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BLK_SIZE_REG
if (RST_ASYNC)
begin
CfgDmaBlkSizeReg <= 5'd0;
end
else if (RST_SYNC)
begin
CfgDmaBlkSizeReg <= 5'd0;
end
else if (EN && FsmCfgRegEn)
begin
CfgDmaBlkSizeReg <= CFG_DMA_BLK_SIZE_IN[4:0];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMA_ADDR_CNT
if (RST_ASYNC)
begin
AddrCntVal <= 30'd0;
end
else if (RST_SYNC)
begin
AddrCntVal <= 30'd0;
end
else if (EN)
begin
if (FsmCfgRegEn)
begin
AddrCntVal <= CFG_DMA_MADR_IN[31:2];
end
else if (BUS_LAST_ACK_IN)
begin
AddrCntVal <= AddrCntVal + CfgDmaBlkSizeReg;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMA_BLK_TMR
if (RST_ASYNC)
begin
BlkTmrVal <= 16'h0000;
end
else if (RST_SYNC)
begin
BlkTmrVal <= 16'h0000;
end
else if (EN)
begin
if (FsmCfgRegEn)
begin
BlkTmrVal <= CFG_DMA_BLK_CNT_IN;
end
else if (BUS_LAST_ACK_IN)
begin
BlkTmrVal <= BlkTmrVal - CfgDmaBlkSizeReg;
end
end
end
always @*
begin : DPFSM_ST
DpfsmStateNxt = DpfsmStateCur;
FsmCfgRegEn = 1'b0;
BusAddrNxt = 32'h0000_0000;
BusAddrIncNxt = 1'b0;
BusRegEn = 1'b0;
BusReadReqNxt = 1'b0;
BusWriteReqNxt = 1'b0;
DmacAckNxt = 1'b0;
case (DpfsmStateCur)
DPFSM_IDLE :
begin
if (CFG_DMA_CHCR_TR_IN && CFG_DMA_CHCR_CO_IN)
begin
FsmCfgRegEn = 1'b1;
DpfsmStateNxt = DPFSM_REG_CFG;
end
end
DPFSM_REG_CFG :
begin
if (CfgDmaChcrDrReg
|| (!CfgDmaChcrDrReg && DMAC_REQ_IN))
begin
BusAddrNxt = SrcAddr;
BusAddrIncNxt = SrcBusAddrInc;
BusRegEn = 1'b1;
BusReadReqNxt = 1'b1;
DpfsmStateNxt = DPFSM_SRC_RD;
end
end
DPFSM_SRC_RD :
begin
BusReadReqNxt = 1'b1;
if (BUS_LAST_ACK_IN && FifoWrFull)
begin
BusReadReqNxt = 1'b0;
DpfsmStateNxt = DPFSM_SRC_RD_DONE;
end
end
DPFSM_SRC_RD_DONE :
begin
if ((CfgDmaChcrDrReg && DMAC_REQ_IN)
|| !CfgDmaChcrDrReg)
begin
BusAddrNxt = GPU_DATA;
BusAddrIncNxt = DstBusAddrInc;
BusRegEn = 1'b1;
BusWriteReqNxt = 1'b1;
DpfsmStateNxt = DPFSM_DST_WR;
end
end
DPFSM_DST_WR :
begin
BusWriteReqNxt = 1'b1;
if (BUS_LAST_ACK_IN && FifoRdEmpty)
begin
BusWriteReqNxt = 1'b0;
DpfsmStateNxt = DPFSM_DST_WR_DONE;
end
end
DPFSM_DST_WR_DONE :
begin
if (16'h0000 == BlkTmrVal)
begin
DmacAckNxt = 1'b1;
DpfsmStateNxt = DPFSM_DMA_ACK;
end
else
begin
BusAddrNxt = SrcAddr;
BusAddrIncNxt = SrcBusAddrInc;
BusRegEn = 1'b1;
BusReadReqNxt = 1'b1;
DpfsmStateNxt = DPFSM_SRC_RD;
end
end
DPFSM_DMA_ACK :
begin
DpfsmStateNxt = DPFSM_IDLE;
end
default : DpfsmStateNxt = DPFSM_IDLE;
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DPFSM_CP
if (RST_ASYNC)
begin
DpfsmStateCur <= DPFSM_IDLE;
BusReadReq <= 1'b0;
BusWriteReq <= 1'b0;
DmacAck <= 1'b0;
BusAddr <= 32'h0000_0000;
BusAddrInc <= 1'b0;
end
else if (RST_SYNC)
begin
DpfsmStateCur <= DPFSM_IDLE;
BusReadReq <= 1'b0;
BusWriteReq <= 1'b0;
DmacAck <= 1'b0;
BusAddr <= 32'h0000_0000;
BusAddrInc <= 1'b0;
end
else if (EN)
begin
DpfsmStateCur <= DpfsmStateNxt ;
BusReadReq <= BusReadReqNxt ;
BusWriteReq <= BusWriteReqNxt ;
DmacAck <= DmacAckNxt ;
if (BusRegEn)
begin
BusAddr <= BusAddrNxt ;
BusAddrInc <= BusAddrIncNxt ;
end
end
end
SYNC_FIFO
#(
.D_P2 ( 4) ,
.BW (32) ,
.WWM ( 1) ,
.RWM ( 1) ,
.USE_RAM ( 0)
)
sync_fifo
(
.WR_CLK (CLK ),
.RD_CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WRITE_EN_IN (BusReadReq & BUS_READ_ACK_IN ),
.WRITE_DATA_IN (BUS_READ_DATA_IN ),
.WRITE_FULL_OUT (FifoWrFull ),
.READ_EN_IN (BusWriteReq & BUS_WRITE_ACK_IN ),
.READ_DATA_OUT (BUS_WRITE_DATA_OUT ),
.READ_EMPTY_OUT (FifoRdEmpty )
);
endmodule | module DMAC_PERI
#(parameter BLK_FIFO_DEPTH = 16,
parameter BLK_FIFO_WIDTH = 32
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input CFG_DMA_CHCR_TR_IN ,
output CFG_DMA_CHCR_TR_CLR_OUT ,
input CFG_DMA_CHCR_CO_IN ,
input CFG_DMA_CHCR_DR_IN ,
input [31:0] CFG_DMA_MADR_IN ,
input [15:0] CFG_DMA_BLK_CNT_IN ,
input [15:0] CFG_DMA_BLK_SIZE_IN ,
output BUS_READ_REQ_OUT ,
input BUS_READ_ACK_IN ,
output BUS_WRITE_REQ_OUT ,
input BUS_WRITE_ACK_IN ,
input BUS_LAST_ACK_IN ,
output [31:0] BUS_START_ADDR_OUT ,
output [ 1:0] BUS_SIZE_OUT ,
output [ 4:0] BUS_LEN_OUT ,
output BUS_BURST_ADDR_INC_OUT ,
output [31:0] BUS_WRITE_DATA_OUT ,
input [31:0] BUS_READ_DATA_IN ,
input DMAC_REQ_IN ,
output DMAC_ACK_OUT ,
output DMAC_IRQ_OUT
); |
`include "psx_mem_map.vh"
parameter [2:0] DPFSM_IDLE = 3'h0;
parameter [2:0] DPFSM_REG_CFG = 3'h1;
parameter [2:0] DPFSM_SRC_RD = 3'h2;
parameter [2:0] DPFSM_SRC_RD_DONE = 3'h3;
parameter [2:0] DPFSM_DST_WR = 3'h4;
parameter [2:0] DPFSM_DST_WR_DONE = 3'h5;
parameter [2:0] DPFSM_DMA_ACK = 3'h6;
reg CfgDmaChcrDrReg ;
reg [ 4:0] CfgDmaBlkSizeReg ;
wire [31:0] SrcAddr ;
wire SrcBusAddrInc ;
wire [31:0] DstAddr ;
wire DstAddrInc ;
reg [31:2] AddrCntVal ;
wire [31:0] AddrCntValByte ;
reg [15:0] BlkTmrVal ;
reg [ 2:0] DpfsmStateCur ;
reg [ 2:0] DpfsmStateNxt ;
reg FsmCfgRegEn ;
reg [31:0] BusAddrNxt ;
reg [31:0] BusAddr ;
reg BusAddrIncNxt ;
reg BusAddrInc ;
reg BusRegEn ;
reg BusReadReqNxt ;
reg BusReadReq ;
reg BusWriteReqNxt ;
reg BusWriteReq ;
reg DmacAckNxt ;
reg DmacAck ;
wire FifoWrFull ;
wire FifoRdEmpty ;
assign SrcAddr = CfgDmaChcrDrReg ? AddrCntValByte : GPU_DATA ;
assign DstAddr = CfgDmaChcrDrReg ? GPU_DATA : AddrCntValByte ;
assign DstAddrInc = CfgDmaChcrDrReg ? 1'b0 : 1'b1 ;
assign SrcBusAddrInc = CfgDmaChcrDrReg ? 1'b1 : 1'b0 ;
assign DstBusAddrInc = CfgDmaChcrDrReg ? 1'b0 : 1'b1 ;
assign AddrCntValByte = {AddrCntVal, 2'b00};
assign BUS_READ_REQ_OUT = BusReadReq ;
assign BUS_WRITE_REQ_OUT = BusWriteReq ;
assign BUS_START_ADDR_OUT = BusAddr ;
assign BUS_SIZE_OUT = 2'b10 ;
assign BUS_LEN_OUT = CfgDmaBlkSizeReg ;
assign BUS_BURST_ADDR_INC_OUT = BusAddrInc ;
assign DMAC_ACK_OUT = DmacAck ;
assign DMAC_IRQ_OUT = DmacAck ;
assign CFG_DMA_CHCR_TR_CLR_OUT = DmacAck ;
always @(posedge CLK or posedge RST_ASYNC)
begin : CHCR_DR_REG
if (RST_ASYNC)
begin
CfgDmaChcrDrReg <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmaChcrDrReg <= 1'b0;
end
else if (EN && FsmCfgRegEn)
begin
CfgDmaChcrDrReg <= CFG_DMA_CHCR_DR_IN;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BLK_SIZE_REG
if (RST_ASYNC)
begin
CfgDmaBlkSizeReg <= 5'd0;
end
else if (RST_SYNC)
begin
CfgDmaBlkSizeReg <= 5'd0;
end
else if (EN && FsmCfgRegEn)
begin
CfgDmaBlkSizeReg <= CFG_DMA_BLK_SIZE_IN[4:0];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMA_ADDR_CNT
if (RST_ASYNC)
begin
AddrCntVal <= 30'd0;
end
else if (RST_SYNC)
begin
AddrCntVal <= 30'd0;
end
else if (EN)
begin
if (FsmCfgRegEn)
begin
AddrCntVal <= CFG_DMA_MADR_IN[31:2];
end
else if (BUS_LAST_ACK_IN)
begin
AddrCntVal <= AddrCntVal + CfgDmaBlkSizeReg;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMA_BLK_TMR
if (RST_ASYNC)
begin
BlkTmrVal <= 16'h0000;
end
else if (RST_SYNC)
begin
BlkTmrVal <= 16'h0000;
end
else if (EN)
begin
if (FsmCfgRegEn)
begin
BlkTmrVal <= CFG_DMA_BLK_CNT_IN;
end
else if (BUS_LAST_ACK_IN)
begin
BlkTmrVal <= BlkTmrVal - CfgDmaBlkSizeReg;
end
end
end
always @*
begin : DPFSM_ST
DpfsmStateNxt = DpfsmStateCur;
FsmCfgRegEn = 1'b0;
BusAddrNxt = 32'h0000_0000;
BusAddrIncNxt = 1'b0;
BusRegEn = 1'b0;
BusReadReqNxt = 1'b0;
BusWriteReqNxt = 1'b0;
DmacAckNxt = 1'b0;
case (DpfsmStateCur)
DPFSM_IDLE :
begin
if (CFG_DMA_CHCR_TR_IN && CFG_DMA_CHCR_CO_IN)
begin
FsmCfgRegEn = 1'b1;
DpfsmStateNxt = DPFSM_REG_CFG;
end
end
DPFSM_REG_CFG :
begin
if (CfgDmaChcrDrReg
|| (!CfgDmaChcrDrReg && DMAC_REQ_IN))
begin
BusAddrNxt = SrcAddr;
BusAddrIncNxt = SrcBusAddrInc;
BusRegEn = 1'b1;
BusReadReqNxt = 1'b1;
DpfsmStateNxt = DPFSM_SRC_RD;
end
end
DPFSM_SRC_RD :
begin
BusReadReqNxt = 1'b1;
if (BUS_LAST_ACK_IN && FifoWrFull)
begin
BusReadReqNxt = 1'b0;
DpfsmStateNxt = DPFSM_SRC_RD_DONE;
end
end
DPFSM_SRC_RD_DONE :
begin
if ((CfgDmaChcrDrReg && DMAC_REQ_IN)
|| !CfgDmaChcrDrReg)
begin
BusAddrNxt = GPU_DATA;
BusAddrIncNxt = DstBusAddrInc;
BusRegEn = 1'b1;
BusWriteReqNxt = 1'b1;
DpfsmStateNxt = DPFSM_DST_WR;
end
end
DPFSM_DST_WR :
begin
BusWriteReqNxt = 1'b1;
if (BUS_LAST_ACK_IN && FifoRdEmpty)
begin
BusWriteReqNxt = 1'b0;
DpfsmStateNxt = DPFSM_DST_WR_DONE;
end
end
DPFSM_DST_WR_DONE :
begin
if (16'h0000 == BlkTmrVal)
begin
DmacAckNxt = 1'b1;
DpfsmStateNxt = DPFSM_DMA_ACK;
end
else
begin
BusAddrNxt = SrcAddr;
BusAddrIncNxt = SrcBusAddrInc;
BusRegEn = 1'b1;
BusReadReqNxt = 1'b1;
DpfsmStateNxt = DPFSM_SRC_RD;
end
end
DPFSM_DMA_ACK :
begin
DpfsmStateNxt = DPFSM_IDLE;
end
default : DpfsmStateNxt = DPFSM_IDLE;
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DPFSM_CP
if (RST_ASYNC)
begin
DpfsmStateCur <= DPFSM_IDLE;
BusReadReq <= 1'b0;
BusWriteReq <= 1'b0;
DmacAck <= 1'b0;
BusAddr <= 32'h0000_0000;
BusAddrInc <= 1'b0;
end
else if (RST_SYNC)
begin
DpfsmStateCur <= DPFSM_IDLE;
BusReadReq <= 1'b0;
BusWriteReq <= 1'b0;
DmacAck <= 1'b0;
BusAddr <= 32'h0000_0000;
BusAddrInc <= 1'b0;
end
else if (EN)
begin
DpfsmStateCur <= DpfsmStateNxt ;
BusReadReq <= BusReadReqNxt ;
BusWriteReq <= BusWriteReqNxt ;
DmacAck <= DmacAckNxt ;
if (BusRegEn)
begin
BusAddr <= BusAddrNxt ;
BusAddrInc <= BusAddrIncNxt ;
end
end
end
SYNC_FIFO
#(
.D_P2 ( 4) ,
.BW (32) ,
.WWM ( 1) ,
.RWM ( 1) ,
.USE_RAM ( 0)
)
sync_fifo
(
.WR_CLK (CLK ),
.RD_CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WRITE_EN_IN (BusReadReq & BUS_READ_ACK_IN ),
.WRITE_DATA_IN (BUS_READ_DATA_IN ),
.WRITE_FULL_OUT (FifoWrFull ),
.READ_EN_IN (BusWriteReq & BUS_WRITE_ACK_IN ),
.READ_DATA_OUT (BUS_WRITE_DATA_OUT ),
.READ_EMPTY_OUT (FifoRdEmpty )
);
endmodule | 1 |
138,374 | data/full_repos/permissive/83270534/psx_top/rtl/dmac_wb_regs.v | 83,270,534 | dmac_wb_regs.v | v | 430 | 115 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/rtl/dmac_wb_regs.v:58: Cannot find include file: psx_mem_map.vh\n`include "psx_mem_map.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh.v\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh.sv\n psx_mem_map.vh\n psx_mem_map.vh.v\n psx_mem_map.vh.sv\n obj_dir/psx_mem_map.vh\n obj_dir/psx_mem_map.vh.v\n obj_dir/psx_mem_map.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 302,262 | module | module DMAC_WB_REGS
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_REGS_DMAC_CYC_IN ,
input WB_REGS_DMAC_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_REGS_DMAC_ACK_OUT ,
output WB_REGS_DMAC_STALL_OUT ,
output WB_REGS_DMAC_ERR_OUT ,
output [31:0] WB_REGS_DMAC_DAT_RD_OUT ,
input [31:0] WB_REGS_DAT_WR_IN ,
output [31:0] CFG_DMAC_ICR_OUT ,
output [31:0] CFG_DMAC_PCR_OUT ,
output [31:0] CFG_DMAC_MADR0_OUT ,
output [31:0] CFG_DMAC_MADR1_OUT ,
output [31:0] CFG_DMAC_MADR2_OUT ,
output [31:0] CFG_DMAC_MADR3_OUT ,
output [31:0] CFG_DMAC_MADR4_OUT ,
output [31:0] CFG_DMAC_MADR5_OUT ,
output [31:0] CFG_DMAC_MADR6_OUT ,
output [31:0] CFG_DMAC_BCR0_OUT ,
output [31:0] CFG_DMAC_BCR1_OUT ,
output [31:0] CFG_DMAC_BCR2_OUT ,
output [31:0] CFG_DMAC_BCR3_OUT ,
output [31:0] CFG_DMAC_BCR4_OUT ,
output [31:0] CFG_DMAC_BCR5_OUT ,
output [31:0] CFG_DMAC_BCR6_OUT ,
output [ 6:0] CFG_DMAC_CHCR_DR_OUT ,
output [ 6:0] CFG_DMAC_CHCR_CO_OUT ,
output [ 6:0] CFG_DMAC_CHCR_LI_OUT ,
output [ 6:0] CFG_DMAC_CHCR_TR_OUT ,
input [ 6:0] CFG_DMAC_CHCR_TR_CLR_IN
);
`include "psx_mem_map.vh"
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
reg [31:0] WbReadDataMux ;
reg [31:0] WbReadDataMuxAlign ;
reg [31:0] WbReadDataMuxAlignReg ;
wire [2:0] DmacChSel;
wire DmacMadrSel;
wire DmacBcrSel ;
wire DmacChcrSel;
wire DmacPcrSel;
wire DmacIcrSel;
reg [31:0] CfgDmacIcr;
reg [31:0] CfgDmacPcr;
reg [31:0] CfgDmacMadr [6:0];
reg [31:0] CfgDmacBcr [6:0];
reg [ 6:0] CfgDmacChcrDr;
reg [ 6:0] CfgDmacChcrCo;
reg [ 6:0] CfgDmacChcrLi;
reg [ 6:0] CfgDmacChcrTr;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign DmacChSel = WB_REGS_ADR_IN[DMAC_CH_SEL_MSB:DMAC_CH_SEL_LSB];
assign DmacMadrSel = (DMAC_REG_SEL_MADR == WB_REGS_ADR_IN[DMAC_REG_SEL_MSB:DMAC_REG_SEL_LSB]);
assign DmacBcrSel = (DMAC_REG_SEL_BCR == WB_REGS_ADR_IN[DMAC_REG_SEL_MSB:DMAC_REG_SEL_LSB]);
assign DmacChcrSel = (DMAC_REG_SEL_CHCR == WB_REGS_ADR_IN[DMAC_REG_SEL_MSB:DMAC_REG_SEL_LSB]);
assign DmacPcrSel = (8'hf0 == WB_REGS_ADR_IN[7:0]);
assign DmacIcrSel = (8'hf4 == WB_REGS_ADR_IN[7:0]);
assign WB_REGS_DMAC_DAT_RD_OUT = WbReadDataMuxAlignReg;
assign CFG_DMAC_ICR_OUT = CfgDmacIcr;
assign CFG_DMAC_PCR_OUT = CfgDmacPcr;
assign CFG_DMAC_MADR0_OUT = CfgDmacMadr[0];
assign CFG_DMAC_MADR1_OUT = CfgDmacMadr[1];
assign CFG_DMAC_MADR2_OUT = CfgDmacMadr[2];
assign CFG_DMAC_MADR3_OUT = CfgDmacMadr[3];
assign CFG_DMAC_MADR4_OUT = CfgDmacMadr[4];
assign CFG_DMAC_MADR5_OUT = CfgDmacMadr[5];
assign CFG_DMAC_MADR6_OUT = CfgDmacMadr[6];
assign CFG_DMAC_BCR0_OUT = CfgDmacBcr[0];
assign CFG_DMAC_BCR1_OUT = CfgDmacBcr[1];
assign CFG_DMAC_BCR2_OUT = CfgDmacBcr[2];
assign CFG_DMAC_BCR3_OUT = CfgDmacBcr[3];
assign CFG_DMAC_BCR4_OUT = CfgDmacBcr[4];
assign CFG_DMAC_BCR5_OUT = CfgDmacBcr[5];
assign CFG_DMAC_BCR6_OUT = CfgDmacBcr[6];
assign CFG_DMAC_CHCR_TR_OUT = CfgDmacChcrTr;
assign CFG_DMAC_CHCR_LI_OUT = CfgDmacChcrLi;
assign CFG_DMAC_CHCR_CO_OUT = CfgDmacChcrCo;
assign CFG_DMAC_CHCR_DR_OUT = CfgDmacChcrDr;
always @(posedge CLK or posedge RST_ASYNC)
begin : CFG_DMAC_ICR_REG
if (RST_ASYNC)
begin
CfgDmacIcr <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
CfgDmacIcr <= 32'h0000_0000;
end
else if (EN && WbValid && WbWriteAddrStb && DmacIcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacIcr[ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacIcr[15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacIcr[23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacIcr[31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_PCR_REG
if (RST_ASYNC)
begin
CfgDmacPcr <= 32'h0765_4321;
end
else if (RST_SYNC)
begin
CfgDmacPcr <= 32'h0765_4321;
end
else if (EN && WbValid && WbWriteAddrStb && DmacPcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacPcr[ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacPcr[15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacPcr[23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacPcr[31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
genvar MadrChLoop;
generate for (MadrChLoop = 0 ; MadrChLoop <= 6 ; MadrChLoop = MadrChLoop + 1)
begin : MADR_GEN
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_MADR_REG
if (RST_ASYNC)
begin
CfgDmacMadr[MadrChLoop] <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
CfgDmacMadr[MadrChLoop] <= 32'h0000_0000;
end
else if (EN && WbValid && WbWriteAddrStb && (MadrChLoop == DmacChSel) && DmacMadrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacMadr[MadrChLoop][ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacMadr[MadrChLoop][15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacMadr[MadrChLoop][23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacMadr[MadrChLoop][31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
end
endgenerate
genvar BcrChLoop;
generate for (BcrChLoop = 0 ; BcrChLoop <= 6 ; BcrChLoop = BcrChLoop + 1)
begin : BCR_GEN
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_BCR_REG
if (RST_ASYNC)
begin
CfgDmacBcr[BcrChLoop] <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
CfgDmacBcr[BcrChLoop] <= 32'h0000_0000;
end
else if (EN && WbValid && WbWriteAddrStb && (BcrChLoop == DmacChSel) && DmacBcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacBcr[BcrChLoop][ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacBcr[BcrChLoop][15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacBcr[BcrChLoop][23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacBcr[BcrChLoop][31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
end
endgenerate
genvar ChcrChLoop;
generate for (ChcrChLoop = 0 ; ChcrChLoop <= 6 ; ChcrChLoop = ChcrChLoop + 1)
begin : CHCR_GEN
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_DR
if (RST_ASYNC)
begin
CfgDmacChcrDr[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrDr[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacChcrDr[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_DR_BIT];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_CO
if (RST_ASYNC)
begin
CfgDmacChcrCo[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrCo[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[1]) CfgDmacChcrCo[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_CO_BIT-8];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_LI
if (RST_ASYNC)
begin
CfgDmacChcrLi[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrLi[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[1]) CfgDmacChcrLi[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_LI_BIT-8];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_TR
if (RST_ASYNC)
begin
CfgDmacChcrTr[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrTr[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[3]) CfgDmacChcrTr[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_TR_BIT-24];
end
else if (CFG_DMAC_CHCR_TR_CLR_IN[ChcrChLoop])
begin
CfgDmacChcrTr[ChcrChLoop] <= 1'b0;
end
end
end
endgenerate
always @*
begin : WB_RD_DAT_MUX
WbReadDataMux = 32'h0000_0000;
case (1'b1)
DmacMadrSel : WbReadDataMux = CfgDmacMadr[DmacChSel];
DmacBcrSel : WbReadDataMux = CfgDmacBcr [DmacChSel];
DmacChcrSel :
begin
WbReadDataMux[DMAC_CHCR_TR_BIT] = CfgDmacChcrTr[DmacChSel];
WbReadDataMux[DMAC_CHCR_LI_BIT] = CfgDmacChcrLi[DmacChSel];
WbReadDataMux[DMAC_CHCR_CO_BIT] = CfgDmacChcrCo[DmacChSel];
WbReadDataMux[DMAC_CHCR_DR_BIT] = CfgDmacChcrDr[DmacChSel];
end
DmacPcrSel : WbReadDataMux = CfgDmacPcr;
DmacIcrSel : WbReadDataMux = CfgDmacIcr;
endcase
end
always @*
begin : WB_RD_DAT_ALIGN
WbReadDataMuxAlign = 32'h0000_0000;
WbReadDataMuxAlign[ 7: 0] = {8{WB_REGS_SEL_IN[0]}} & WbReadDataMux[ 7: 0];
WbReadDataMuxAlign[15: 8] = {8{WB_REGS_SEL_IN[1]}} & WbReadDataMux[15: 8];
WbReadDataMuxAlign[23:16] = {8{WB_REGS_SEL_IN[2]}} & WbReadDataMux[23:16];
WbReadDataMuxAlign[31:24] = {8{WB_REGS_SEL_IN[3]}} & WbReadDataMux[31:24];
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_READ_DATA_REG
if (RST_ASYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (EN && WbReadAddrStb && WbValid)
begin
WbReadDataMuxAlignReg <= WbReadDataMuxAlign;
end
end
WB_SLAVE_CTRL
#(.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 0)
)
wb_slave_ctrl
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WB_REGS_ADR_IN ),
.WB_REGS_CYC_IN (WB_REGS_DMAC_CYC_IN ),
.WB_REGS_STB_IN (WB_REGS_DMAC_STB_IN ),
.WB_REGS_WE_IN (WB_REGS_WE_IN ),
.WB_REGS_SEL_IN (WB_REGS_SEL_IN ),
.WB_REGS_ACK_OUT (WB_REGS_DMAC_ACK_OUT ),
.WB_REGS_STALL_OUT (WB_REGS_DMAC_STALL_OUT ),
.WB_REGS_ERR_OUT (WB_REGS_DMAC_ERR_OUT ),
.WB_WRITE_ADDR_STB_OUT (WbWriteAddrStb ),
.WB_READ_ADDR_STB_OUT (WbReadAddrStb ),
.WB_VALID_OUT (WbValid )
);
endmodule | module DMAC_WB_REGS
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_REGS_DMAC_CYC_IN ,
input WB_REGS_DMAC_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_REGS_DMAC_ACK_OUT ,
output WB_REGS_DMAC_STALL_OUT ,
output WB_REGS_DMAC_ERR_OUT ,
output [31:0] WB_REGS_DMAC_DAT_RD_OUT ,
input [31:0] WB_REGS_DAT_WR_IN ,
output [31:0] CFG_DMAC_ICR_OUT ,
output [31:0] CFG_DMAC_PCR_OUT ,
output [31:0] CFG_DMAC_MADR0_OUT ,
output [31:0] CFG_DMAC_MADR1_OUT ,
output [31:0] CFG_DMAC_MADR2_OUT ,
output [31:0] CFG_DMAC_MADR3_OUT ,
output [31:0] CFG_DMAC_MADR4_OUT ,
output [31:0] CFG_DMAC_MADR5_OUT ,
output [31:0] CFG_DMAC_MADR6_OUT ,
output [31:0] CFG_DMAC_BCR0_OUT ,
output [31:0] CFG_DMAC_BCR1_OUT ,
output [31:0] CFG_DMAC_BCR2_OUT ,
output [31:0] CFG_DMAC_BCR3_OUT ,
output [31:0] CFG_DMAC_BCR4_OUT ,
output [31:0] CFG_DMAC_BCR5_OUT ,
output [31:0] CFG_DMAC_BCR6_OUT ,
output [ 6:0] CFG_DMAC_CHCR_DR_OUT ,
output [ 6:0] CFG_DMAC_CHCR_CO_OUT ,
output [ 6:0] CFG_DMAC_CHCR_LI_OUT ,
output [ 6:0] CFG_DMAC_CHCR_TR_OUT ,
input [ 6:0] CFG_DMAC_CHCR_TR_CLR_IN
); |
`include "psx_mem_map.vh"
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
reg [31:0] WbReadDataMux ;
reg [31:0] WbReadDataMuxAlign ;
reg [31:0] WbReadDataMuxAlignReg ;
wire [2:0] DmacChSel;
wire DmacMadrSel;
wire DmacBcrSel ;
wire DmacChcrSel;
wire DmacPcrSel;
wire DmacIcrSel;
reg [31:0] CfgDmacIcr;
reg [31:0] CfgDmacPcr;
reg [31:0] CfgDmacMadr [6:0];
reg [31:0] CfgDmacBcr [6:0];
reg [ 6:0] CfgDmacChcrDr;
reg [ 6:0] CfgDmacChcrCo;
reg [ 6:0] CfgDmacChcrLi;
reg [ 6:0] CfgDmacChcrTr;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign DmacChSel = WB_REGS_ADR_IN[DMAC_CH_SEL_MSB:DMAC_CH_SEL_LSB];
assign DmacMadrSel = (DMAC_REG_SEL_MADR == WB_REGS_ADR_IN[DMAC_REG_SEL_MSB:DMAC_REG_SEL_LSB]);
assign DmacBcrSel = (DMAC_REG_SEL_BCR == WB_REGS_ADR_IN[DMAC_REG_SEL_MSB:DMAC_REG_SEL_LSB]);
assign DmacChcrSel = (DMAC_REG_SEL_CHCR == WB_REGS_ADR_IN[DMAC_REG_SEL_MSB:DMAC_REG_SEL_LSB]);
assign DmacPcrSel = (8'hf0 == WB_REGS_ADR_IN[7:0]);
assign DmacIcrSel = (8'hf4 == WB_REGS_ADR_IN[7:0]);
assign WB_REGS_DMAC_DAT_RD_OUT = WbReadDataMuxAlignReg;
assign CFG_DMAC_ICR_OUT = CfgDmacIcr;
assign CFG_DMAC_PCR_OUT = CfgDmacPcr;
assign CFG_DMAC_MADR0_OUT = CfgDmacMadr[0];
assign CFG_DMAC_MADR1_OUT = CfgDmacMadr[1];
assign CFG_DMAC_MADR2_OUT = CfgDmacMadr[2];
assign CFG_DMAC_MADR3_OUT = CfgDmacMadr[3];
assign CFG_DMAC_MADR4_OUT = CfgDmacMadr[4];
assign CFG_DMAC_MADR5_OUT = CfgDmacMadr[5];
assign CFG_DMAC_MADR6_OUT = CfgDmacMadr[6];
assign CFG_DMAC_BCR0_OUT = CfgDmacBcr[0];
assign CFG_DMAC_BCR1_OUT = CfgDmacBcr[1];
assign CFG_DMAC_BCR2_OUT = CfgDmacBcr[2];
assign CFG_DMAC_BCR3_OUT = CfgDmacBcr[3];
assign CFG_DMAC_BCR4_OUT = CfgDmacBcr[4];
assign CFG_DMAC_BCR5_OUT = CfgDmacBcr[5];
assign CFG_DMAC_BCR6_OUT = CfgDmacBcr[6];
assign CFG_DMAC_CHCR_TR_OUT = CfgDmacChcrTr;
assign CFG_DMAC_CHCR_LI_OUT = CfgDmacChcrLi;
assign CFG_DMAC_CHCR_CO_OUT = CfgDmacChcrCo;
assign CFG_DMAC_CHCR_DR_OUT = CfgDmacChcrDr;
always @(posedge CLK or posedge RST_ASYNC)
begin : CFG_DMAC_ICR_REG
if (RST_ASYNC)
begin
CfgDmacIcr <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
CfgDmacIcr <= 32'h0000_0000;
end
else if (EN && WbValid && WbWriteAddrStb && DmacIcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacIcr[ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacIcr[15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacIcr[23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacIcr[31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_PCR_REG
if (RST_ASYNC)
begin
CfgDmacPcr <= 32'h0765_4321;
end
else if (RST_SYNC)
begin
CfgDmacPcr <= 32'h0765_4321;
end
else if (EN && WbValid && WbWriteAddrStb && DmacPcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacPcr[ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacPcr[15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacPcr[23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacPcr[31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
genvar MadrChLoop;
generate for (MadrChLoop = 0 ; MadrChLoop <= 6 ; MadrChLoop = MadrChLoop + 1)
begin : MADR_GEN
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_MADR_REG
if (RST_ASYNC)
begin
CfgDmacMadr[MadrChLoop] <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
CfgDmacMadr[MadrChLoop] <= 32'h0000_0000;
end
else if (EN && WbValid && WbWriteAddrStb && (MadrChLoop == DmacChSel) && DmacMadrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacMadr[MadrChLoop][ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacMadr[MadrChLoop][15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacMadr[MadrChLoop][23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacMadr[MadrChLoop][31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
end
endgenerate
genvar BcrChLoop;
generate for (BcrChLoop = 0 ; BcrChLoop <= 6 ; BcrChLoop = BcrChLoop + 1)
begin : BCR_GEN
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_BCR_REG
if (RST_ASYNC)
begin
CfgDmacBcr[BcrChLoop] <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
CfgDmacBcr[BcrChLoop] <= 32'h0000_0000;
end
else if (EN && WbValid && WbWriteAddrStb && (BcrChLoop == DmacChSel) && DmacBcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacBcr[BcrChLoop][ 7: 0] <= WB_REGS_DAT_WR_IN[ 7: 0];
if (WB_REGS_SEL_IN[1]) CfgDmacBcr[BcrChLoop][15: 8] <= WB_REGS_DAT_WR_IN[15: 8];
if (WB_REGS_SEL_IN[2]) CfgDmacBcr[BcrChLoop][23:16] <= WB_REGS_DAT_WR_IN[23:16];
if (WB_REGS_SEL_IN[3]) CfgDmacBcr[BcrChLoop][31:24] <= WB_REGS_DAT_WR_IN[31:24];
end
end
end
endgenerate
genvar ChcrChLoop;
generate for (ChcrChLoop = 0 ; ChcrChLoop <= 6 ; ChcrChLoop = ChcrChLoop + 1)
begin : CHCR_GEN
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_DR
if (RST_ASYNC)
begin
CfgDmacChcrDr[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrDr[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[0]) CfgDmacChcrDr[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_DR_BIT];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_CO
if (RST_ASYNC)
begin
CfgDmacChcrCo[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrCo[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[1]) CfgDmacChcrCo[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_CO_BIT-8];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_LI
if (RST_ASYNC)
begin
CfgDmacChcrLi[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrLi[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[1]) CfgDmacChcrLi[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_LI_BIT-8];
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DMAC_CHCR_REG_TR
if (RST_ASYNC)
begin
CfgDmacChcrTr[ChcrChLoop] <= 1'b0;
end
else if (RST_SYNC)
begin
CfgDmacChcrTr[ChcrChLoop] <= 1'b0;
end
else if (EN && WbValid && WbWriteAddrStb && (ChcrChLoop == DmacChSel) && DmacChcrSel)
begin
if (WB_REGS_SEL_IN[3]) CfgDmacChcrTr[ChcrChLoop] <= WB_REGS_DAT_WR_IN[DMAC_CHCR_TR_BIT-24];
end
else if (CFG_DMAC_CHCR_TR_CLR_IN[ChcrChLoop])
begin
CfgDmacChcrTr[ChcrChLoop] <= 1'b0;
end
end
end
endgenerate
always @*
begin : WB_RD_DAT_MUX
WbReadDataMux = 32'h0000_0000;
case (1'b1)
DmacMadrSel : WbReadDataMux = CfgDmacMadr[DmacChSel];
DmacBcrSel : WbReadDataMux = CfgDmacBcr [DmacChSel];
DmacChcrSel :
begin
WbReadDataMux[DMAC_CHCR_TR_BIT] = CfgDmacChcrTr[DmacChSel];
WbReadDataMux[DMAC_CHCR_LI_BIT] = CfgDmacChcrLi[DmacChSel];
WbReadDataMux[DMAC_CHCR_CO_BIT] = CfgDmacChcrCo[DmacChSel];
WbReadDataMux[DMAC_CHCR_DR_BIT] = CfgDmacChcrDr[DmacChSel];
end
DmacPcrSel : WbReadDataMux = CfgDmacPcr;
DmacIcrSel : WbReadDataMux = CfgDmacIcr;
endcase
end
always @*
begin : WB_RD_DAT_ALIGN
WbReadDataMuxAlign = 32'h0000_0000;
WbReadDataMuxAlign[ 7: 0] = {8{WB_REGS_SEL_IN[0]}} & WbReadDataMux[ 7: 0];
WbReadDataMuxAlign[15: 8] = {8{WB_REGS_SEL_IN[1]}} & WbReadDataMux[15: 8];
WbReadDataMuxAlign[23:16] = {8{WB_REGS_SEL_IN[2]}} & WbReadDataMux[23:16];
WbReadDataMuxAlign[31:24] = {8{WB_REGS_SEL_IN[3]}} & WbReadDataMux[31:24];
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_READ_DATA_REG
if (RST_ASYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (EN && WbReadAddrStb && WbValid)
begin
WbReadDataMuxAlignReg <= WbReadDataMuxAlign;
end
end
WB_SLAVE_CTRL
#(.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 0)
)
wb_slave_ctrl
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WB_REGS_ADR_IN ),
.WB_REGS_CYC_IN (WB_REGS_DMAC_CYC_IN ),
.WB_REGS_STB_IN (WB_REGS_DMAC_STB_IN ),
.WB_REGS_WE_IN (WB_REGS_WE_IN ),
.WB_REGS_SEL_IN (WB_REGS_SEL_IN ),
.WB_REGS_ACK_OUT (WB_REGS_DMAC_ACK_OUT ),
.WB_REGS_STALL_OUT (WB_REGS_DMAC_STALL_OUT ),
.WB_REGS_ERR_OUT (WB_REGS_DMAC_ERR_OUT ),
.WB_WRITE_ADDR_STB_OUT (WbWriteAddrStb ),
.WB_READ_ADDR_STB_OUT (WbReadAddrStb ),
.WB_VALID_OUT (WbValid )
);
endmodule | 1 |
138,375 | data/full_repos/permissive/83270534/psx_top/rtl/intc.v | 83,270,534 | intc.v | v | 263 | 98 | [] | [] | [] | [(3, 262)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/intc.v:101: Operator AND expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n : ... In instance INTC\n (WB_REGS_DAT_WR_IN[IW-1:8] & {8{WB_REGS_SEL_IN[1]}}),\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/intc.v:100: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 37 bits.\n : ... In instance INTC\n assign IRegWriteData = { {32-IW{1\'b0}}, \n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/intc.v:205: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 3 bits.\n : ... In instance INTC\n assign IntRawSet[i] = IntSourcePipe[1] & ~IntSourcePipe[0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/intc.v:208: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'IRegWriteEn\' generates 1 bits.\n : ... In instance INTC\n assign IntRawClr[i] = IRegWriteEn & ~WB_REGS_DAT_WR_IN;\n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/intc.v:208: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n : ... In instance INTC\n assign IntRawClr[i] = IRegWriteEn & ~WB_REGS_DAT_WR_IN;\n ^\n%Error: Exiting due to 5 warning(s)\n' | 302,263 | module | module INTC
#(parameter IW = 11)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_INTC_CYC_IN ,
input WB_INTC_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_INTC_ACK_OUT ,
output WB_INTC_STALL_OUT ,
output WB_INTC_ERR_OUT ,
output [31:0] WB_INTC_DAT_RD_OUT ,
input [31:0] WB_REGS_DAT_WR_IN ,
input [IW-1:0] INT_SOURCE_IN ,
output MIPS_HW_INT_OUT
);
parameter INTC_SRC_VBLANK = 0 ;
parameter INTC_SRC_GPU = 1 ;
parameter INTC_SRC_CDROM = 2 ;
parameter INTC_SRC_DMAC = 3 ;
parameter INTC_SRC_RTC0 = 4 ;
parameter INTC_SRC_RTC1 = 5 ;
parameter INTC_SRC_RTC2 = 6 ;
parameter INTC_SRC_CNTL = 7 ;
parameter INTC_SRC_SPU = 8 ;
parameter INTC_SRC_PIO = 9 ;
parameter INTC_SRC_SIO = 10 ;
parameter [3:0] INTC_IREG = 4'h0;
parameter [3:0] INTC_IMASK = 4'h4;
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
reg WbAddrStbReg ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
wire [3:0] WbAddrRegSel ;
reg [31:0] WbReadDataMux ;
reg [31:0] WbReadDataMuxAlign ;
reg [31:0] WbReadDataMuxAlignReg ;
reg [IW-1:0] CfgIMask ;
wire IRegWriteEn ;
wire [IW-1:0] IRegWriteData ;
reg [2:0] IntSourcePipe [IW-1:0];
wire [IW-1:0] IntRawSet ;
wire [IW-1:0] IntRawClr ;
reg [IW-1:0] IntRaw ;
wire [IW-1:0] IntMasked ;
assign WbReadAddrStb = WB_INTC_CYC_IN & WB_INTC_STB_IN & ~WB_REGS_WE_IN & ~WB_INTC_STALL_OUT;
assign WbWriteAddrStb = WB_INTC_CYC_IN & WB_INTC_STB_IN & WB_REGS_WE_IN & ~WB_INTC_STALL_OUT;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign WbSelValid = ( ((4'b1111 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[1:0] == 2'b00))
| ((4'b1100 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
| ((4'b0011 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
);
assign WbAddrValid = (4'h0 == WB_REGS_ADR_IN[11:8]);
assign WbValid = WbAddrValid & WbSelValid;
assign WbAddrRegSel = WB_REGS_ADR_IN[3:0];
assign IRegWriteEn = EN && WbWriteAddrStb && WbValid && (INTC_IMASK == WbAddrRegSel);
assign IRegWriteData = { {32-IW{1'b0}},
(WB_REGS_DAT_WR_IN[IW-1:8] & {8{WB_REGS_SEL_IN[1]}}),
(WB_REGS_DAT_WR_IN[ 7:0] & {8{WB_REGS_SEL_IN[0]}})
};
assign WB_INTC_STALL_OUT = WbAddrStbReg;
assign WB_INTC_ACK_OUT = WbAddrStbReg & WbValid;
assign WB_INTC_ERR_OUT = WbAddrStbReg & ~WbValid;
assign WB_INTC_DAT_RD_OUT = WbReadDataMuxAlignReg;
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_ADDR_STB_REG
if (RST_ASYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (RST_SYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (EN)
begin
WbAddrStbReg <= WbAddrStb;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CONFIG_REG
if (RST_ASYNC)
begin
CfgIMask <= {IW{1'b0}};
end
else if (RST_SYNC)
begin
CfgIMask <= {IW{1'b0}};
end
else if (EN && WbWriteAddrStb && WbValid && (INTC_IMASK == WbAddrRegSel))
begin
if (WB_REGS_SEL_IN[0]) CfgIMask[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgIMask[IW-1:8] <= WB_REGS_DAT_WR_IN[IW-1:8];
end
end
always @*
begin : READ_DATA_MUX
WbReadDataMux = 32'h0000_0000;
case (WbAddrRegSel)
INTC_IREG : WbReadDataMux = { {32-IW{1'b0}}, IntMasked};
INTC_IMASK : WbReadDataMux = { {32-IW{1'b0}}, CfgIMask };
endcase
end
always @*
begin : READ_DATA_ALIGN
WbReadDataMuxAlign = 32'h0000_0000;
WbReadDataMuxAlign[ 7:0] = {8{WB_REGS_SEL_IN[0]}} & WbReadDataMux[ 7:0];
WbReadDataMuxAlign[15:8] = {8{WB_REGS_SEL_IN[1]}} & WbReadDataMux[15:8];
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_READ_DATA_REG
if (RST_ASYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (EN && WbReadAddrStb && WbValid)
begin
WbReadDataMuxAlignReg <= WbReadDataMuxAlign;
end
end
genvar i;
generate for (i = 0 ; i < IW ; i = i + 1)
begin : IRQ_PIPE_GEN
assign IntRawSet[i] = IntSourcePipe[1] & ~IntSourcePipe[0];
assign IntRawClr[i] = IRegWriteEn & ~WB_REGS_DAT_WR_IN;
assign IntMasked[i] = CfgIMask[i] & IntRaw[i];
always @(posedge CLK or posedge RST_ASYNC)
begin : INT_SOURCE_RESYNC
if (RST_ASYNC)
begin
IntSourcePipe[i] <= 3'b000;
end
else if (RST_SYNC)
begin
IntSourcePipe[i] <= 3'b000;
end
else if (EN)
begin
IntSourcePipe[i] <= {INT_SOURCE_IN[i], IntSourcePipe[i][2:1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : INT_SR_FLOP
if (RST_ASYNC)
begin
IntRaw[i] <= 1'b0;
end
else if (RST_SYNC)
begin
IntRaw[i] <= 1'b0;
end
else if (EN)
begin
if (IntRawSet[i])
begin
IntRaw[i] <= 1'b1;
end
else if (IntRawClr[i])
begin
IntRaw[i] <= 1'b0;
end
end
end
end
endgenerate
endmodule | module INTC
#(parameter IW = 11)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_INTC_CYC_IN ,
input WB_INTC_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_INTC_ACK_OUT ,
output WB_INTC_STALL_OUT ,
output WB_INTC_ERR_OUT ,
output [31:0] WB_INTC_DAT_RD_OUT ,
input [31:0] WB_REGS_DAT_WR_IN ,
input [IW-1:0] INT_SOURCE_IN ,
output MIPS_HW_INT_OUT
); |
parameter INTC_SRC_VBLANK = 0 ;
parameter INTC_SRC_GPU = 1 ;
parameter INTC_SRC_CDROM = 2 ;
parameter INTC_SRC_DMAC = 3 ;
parameter INTC_SRC_RTC0 = 4 ;
parameter INTC_SRC_RTC1 = 5 ;
parameter INTC_SRC_RTC2 = 6 ;
parameter INTC_SRC_CNTL = 7 ;
parameter INTC_SRC_SPU = 8 ;
parameter INTC_SRC_PIO = 9 ;
parameter INTC_SRC_SIO = 10 ;
parameter [3:0] INTC_IREG = 4'h0;
parameter [3:0] INTC_IMASK = 4'h4;
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
reg WbAddrStbReg ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
wire [3:0] WbAddrRegSel ;
reg [31:0] WbReadDataMux ;
reg [31:0] WbReadDataMuxAlign ;
reg [31:0] WbReadDataMuxAlignReg ;
reg [IW-1:0] CfgIMask ;
wire IRegWriteEn ;
wire [IW-1:0] IRegWriteData ;
reg [2:0] IntSourcePipe [IW-1:0];
wire [IW-1:0] IntRawSet ;
wire [IW-1:0] IntRawClr ;
reg [IW-1:0] IntRaw ;
wire [IW-1:0] IntMasked ;
assign WbReadAddrStb = WB_INTC_CYC_IN & WB_INTC_STB_IN & ~WB_REGS_WE_IN & ~WB_INTC_STALL_OUT;
assign WbWriteAddrStb = WB_INTC_CYC_IN & WB_INTC_STB_IN & WB_REGS_WE_IN & ~WB_INTC_STALL_OUT;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign WbSelValid = ( ((4'b1111 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[1:0] == 2'b00))
| ((4'b1100 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
| ((4'b0011 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
);
assign WbAddrValid = (4'h0 == WB_REGS_ADR_IN[11:8]);
assign WbValid = WbAddrValid & WbSelValid;
assign WbAddrRegSel = WB_REGS_ADR_IN[3:0];
assign IRegWriteEn = EN && WbWriteAddrStb && WbValid && (INTC_IMASK == WbAddrRegSel);
assign IRegWriteData = { {32-IW{1'b0}},
(WB_REGS_DAT_WR_IN[IW-1:8] & {8{WB_REGS_SEL_IN[1]}}),
(WB_REGS_DAT_WR_IN[ 7:0] & {8{WB_REGS_SEL_IN[0]}})
};
assign WB_INTC_STALL_OUT = WbAddrStbReg;
assign WB_INTC_ACK_OUT = WbAddrStbReg & WbValid;
assign WB_INTC_ERR_OUT = WbAddrStbReg & ~WbValid;
assign WB_INTC_DAT_RD_OUT = WbReadDataMuxAlignReg;
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_ADDR_STB_REG
if (RST_ASYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (RST_SYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (EN)
begin
WbAddrStbReg <= WbAddrStb;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CONFIG_REG
if (RST_ASYNC)
begin
CfgIMask <= {IW{1'b0}};
end
else if (RST_SYNC)
begin
CfgIMask <= {IW{1'b0}};
end
else if (EN && WbWriteAddrStb && WbValid && (INTC_IMASK == WbAddrRegSel))
begin
if (WB_REGS_SEL_IN[0]) CfgIMask[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgIMask[IW-1:8] <= WB_REGS_DAT_WR_IN[IW-1:8];
end
end
always @*
begin : READ_DATA_MUX
WbReadDataMux = 32'h0000_0000;
case (WbAddrRegSel)
INTC_IREG : WbReadDataMux = { {32-IW{1'b0}}, IntMasked};
INTC_IMASK : WbReadDataMux = { {32-IW{1'b0}}, CfgIMask };
endcase
end
always @*
begin : READ_DATA_ALIGN
WbReadDataMuxAlign = 32'h0000_0000;
WbReadDataMuxAlign[ 7:0] = {8{WB_REGS_SEL_IN[0]}} & WbReadDataMux[ 7:0];
WbReadDataMuxAlign[15:8] = {8{WB_REGS_SEL_IN[1]}} & WbReadDataMux[15:8];
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_READ_DATA_REG
if (RST_ASYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (EN && WbReadAddrStb && WbValid)
begin
WbReadDataMuxAlignReg <= WbReadDataMuxAlign;
end
end
genvar i;
generate for (i = 0 ; i < IW ; i = i + 1)
begin : IRQ_PIPE_GEN
assign IntRawSet[i] = IntSourcePipe[1] & ~IntSourcePipe[0];
assign IntRawClr[i] = IRegWriteEn & ~WB_REGS_DAT_WR_IN;
assign IntMasked[i] = CfgIMask[i] & IntRaw[i];
always @(posedge CLK or posedge RST_ASYNC)
begin : INT_SOURCE_RESYNC
if (RST_ASYNC)
begin
IntSourcePipe[i] <= 3'b000;
end
else if (RST_SYNC)
begin
IntSourcePipe[i] <= 3'b000;
end
else if (EN)
begin
IntSourcePipe[i] <= {INT_SOURCE_IN[i], IntSourcePipe[i][2:1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : INT_SR_FLOP
if (RST_ASYNC)
begin
IntRaw[i] <= 1'b0;
end
else if (RST_SYNC)
begin
IntRaw[i] <= 1'b0;
end
else if (EN)
begin
if (IntRawSet[i])
begin
IntRaw[i] <= 1'b1;
end
else if (IntRawClr[i])
begin
IntRaw[i] <= 1'b0;
end
end
end
end
endgenerate
endmodule | 1 |
138,376 | data/full_repos/permissive/83270534/psx_top/rtl/psx_bus.v | 83,270,534 | psx_bus.v | v | 1,118 | 115 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_bus.v:154: Cannot find include file: psx_mem_map.vh\n`include "psx_mem_map.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh.v\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/psx_mem_map.vh.sv\n psx_mem_map.vh\n psx_mem_map.vh.v\n psx_mem_map.vh.sv\n obj_dir/psx_mem_map.vh\n obj_dir/psx_mem_map.vh.v\n obj_dir/psx_mem_map.vh.sv\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_bus.v:155: Cannot find include file: wb_defs.v\n`include "wb_defs.v" \n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 302,264 | module | module PSX_BUS
(
input CLK_SYS ,
input EN_SYS ,
input RST_SYNC_SYS ,
input RST_ASYNC_SYS ,
input CLK_REGS ,
input EN_REGS ,
input RST_SYNC_REGS ,
input RST_ASYNC_REGS ,
input [31:0] WB_MIPS_ADR_IN ,
input WB_MIPS_CYC_IN ,
input WB_MIPS_STB_IN ,
input WB_MIPS_WE_IN ,
input [ 3:0] WB_MIPS_SEL_IN ,
input [ 2:0] WB_MIPS_CTI_IN ,
input [ 1:0] WB_MIPS_BTE_IN ,
output WB_MIPS_STALL_OUT ,
output WB_MIPS_ACK_OUT ,
output WB_MIPS_ERR_OUT ,
output [31:0] WB_MIPS_RD_DAT_OUT ,
input [31:0] WB_MIPS_WR_DAT_IN ,
input [31:0] WB_DMAC_ADR_IN ,
input WB_DMAC_CYC_IN ,
input WB_DMAC_STB_IN ,
input WB_DMAC_WE_IN ,
input [ 3:0] WB_DMAC_SEL_IN ,
input [ 2:0] WB_DMAC_CTI_IN ,
input [ 1:0] WB_DMAC_BTE_IN ,
output WB_DMAC_STALL_OUT ,
output WB_DMAC_ACK_OUT ,
output WB_DMAC_ERR_OUT ,
output [31:0] WB_DMAC_RD_DAT_OUT ,
input [31:0] WB_DMAC_WR_DAT_IN ,
output [31:0] WB_SYS_ADR_OUT ,
output WB_SYS_WE_OUT ,
output [ 3:0] WB_SYS_SEL_OUT ,
output [ 2:0] WB_SYS_CTI_OUT ,
output [ 1:0] WB_SYS_BTE_OUT ,
output [31:0] WB_SYS_DAT_WR_OUT ,
output WB_SYS_ROM_CYC_OUT ,
output WB_SYS_ROM_STB_OUT ,
output WB_SYS_DRAM_CYC_OUT ,
output WB_SYS_DRAM_STB_OUT ,
output WB_SYS_GPU_CYC_OUT ,
output WB_SYS_GPU_STB_OUT ,
input WB_SYS_ROM_ACK_IN ,
input WB_SYS_ROM_STALL_IN ,
input WB_SYS_ROM_ERR_IN ,
input [31:0] WB_SYS_ROM_DAT_RD_IN ,
input WB_SYS_DRAM_ACK_IN ,
input WB_SYS_DRAM_STALL_IN ,
input WB_SYS_DRAM_ERR_IN ,
input [31:0] WB_SYS_DRAM_DAT_RD_IN ,
input WB_SYS_GPU_ACK_IN ,
input WB_SYS_GPU_STALL_IN ,
input WB_SYS_GPU_ERR_IN ,
input [31:0] WB_SYS_GPU_DAT_RD_IN ,
output [31:0] WB_REGS_ADR_OUT ,
output WB_REGS_WE_OUT ,
output [ 3:0] WB_REGS_SEL_OUT ,
output [31:0] WB_REGS_DAT_WR_OUT ,
output WB_REGS_RCNT_CYC_OUT ,
output WB_REGS_RCNT_STB_OUT ,
output WB_REGS_INTC_CYC_OUT ,
output WB_REGS_INTC_STB_OUT ,
output WB_REGS_DMAC_CYC_OUT ,
output WB_REGS_DMAC_STB_OUT ,
output WB_REGS_BIOS_CYC_OUT ,
output WB_REGS_BIOS_STB_OUT ,
output WB_REGS_MDEC_CYC_OUT ,
output WB_REGS_MDEC_STB_OUT ,
output WB_REGS_MEMCARD_CYC_OUT ,
output WB_REGS_MEMCARD_STB_OUT ,
output WB_REGS_SPU_CYC_OUT ,
output WB_REGS_SPU_STB_OUT ,
output WB_REGS_CDROM_CYC_OUT ,
output WB_REGS_CDROM_STB_OUT ,
output WB_REGS_PAD_CYC_OUT ,
output WB_REGS_PAD_STB_OUT ,
input WB_REGS_RCNT_ACK_IN ,
input WB_REGS_RCNT_STALL_IN ,
input WB_REGS_RCNT_ERR_IN ,
input [31:0] WB_REGS_RCNT_DAT_RD_IN ,
input WB_REGS_INTC_ACK_IN ,
input WB_REGS_INTC_STALL_IN ,
input WB_REGS_INTC_ERR_IN ,
input [31:0] WB_REGS_INTC_DAT_RD_IN ,
input WB_REGS_DMAC_ACK_IN ,
input WB_REGS_DMAC_STALL_IN ,
input WB_REGS_DMAC_ERR_IN ,
input [31:0] WB_REGS_DMAC_DAT_RD_IN ,
input WB_REGS_BIOS_ACK_IN ,
input WB_REGS_BIOS_STALL_IN ,
input WB_REGS_BIOS_ERR_IN ,
input [31:0] WB_REGS_BIOS_DAT_RD_IN ,
input WB_REGS_MDEC_ACK_IN ,
input WB_REGS_MDEC_STALL_IN ,
input WB_REGS_MDEC_ERR_IN ,
input [31:0] WB_REGS_MDEC_DAT_RD_IN ,
input WB_REGS_MEMCARD_ACK_IN ,
input WB_REGS_MEMCARD_STALL_IN ,
input WB_REGS_MEMCARD_ERR_IN ,
input [31:0] WB_REGS_MEMCARD_DAT_RD_IN ,
input WB_REGS_SPU_ACK_IN ,
input WB_REGS_SPU_STALL_IN ,
input WB_REGS_SPU_ERR_IN ,
input [31:0] WB_REGS_SPU_DAT_RD_IN ,
input WB_REGS_CDROM_ACK_IN ,
input WB_REGS_CDROM_STALL_IN ,
input WB_REGS_CDROM_ERR_IN ,
input [31:0] WB_REGS_CDROM_DAT_RD_IN ,
input WB_REGS_PAD_ACK_IN ,
input WB_REGS_PAD_STALL_IN ,
input WB_REGS_PAD_ERR_IN ,
input [31:0] WB_REGS_PAD_DAT_RD_IN
);
`include "psx_mem_map.vh"
`include "wb_defs.v"
wire [31:0] WbSysAdr ;
wire WbSysCyc ;
wire WbSysStb ;
wire WbSysWe ;
wire [ 3:0] WbSysSel ;
wire [ 2:0] WbSysCti ;
wire [ 1:0] WbSysBte ;
wire WbSysAck ;
wire WbSysStall ;
wire WbSysErr ;
wire [31:0] WbSysDatRd ;
wire [31:0] WbSysDatWr ;
wire WbSysRomSel ;
reg WbSysRomSelReg ;
wire WbSysRomCyc ;
wire WbSysRomStb ;
wire WbSysDramSel ;
reg WbSysDramSelReg ;
wire WbSysDramCyc ;
wire WbSysDramStb ;
wire WbSysGpuSel ;
reg WbSysGpuSelReg ;
wire WbSysGpuCyc ;
wire WbSysGpuStb ;
wire WbSysRegsSel ;
reg WbSysRegsSelReg ;
wire WbSysRegsCyc ;
wire WbSysRegsStb ;
wire WbSysDefaultSel ;
reg WbSysDefaultSelReg ;
wire WbSysDefaultCyc ;
wire WbSysDefaultStb ;
wire WbSysRegsAck ;
wire WbSysRegsStall ;
wire WbSysRegsErr ;
wire [31:0] WbSysRegsDatRd ;
wire WbSysDefaultAck ;
wire WbSysDefaultStall ;
wire WbSysDefaultErr ;
wire [31:0] WbSysDefaultDatRd = 32'h0000_0000;
wire [31:0] WbRegsAdr ;
wire WbRegsCyc ;
wire WbRegsStb ;
wire WbRegsWe ;
wire [ 3:0] WbRegsSel ;
wire [ 2:0] WbRegsCti ;
wire [ 1:0] WbRegsBte ;
wire WbRegsAck ;
wire WbRegsStall ;
wire WbRegsErr ;
wire [31:0] WbRegsDatRd ;
wire [31:0] WbRegsDatWr ;
reg WbRegsRcntSel ;
reg WbRegsRcntSelReg ;
wire WbRegsRcntCyc ;
wire WbRegsRcntStb ;
reg WbRegsIntcSel ;
reg WbRegsIntcSelReg ;
wire WbRegsIntcCyc ;
wire WbRegsIntcStb ;
reg WbRegsDmacSel ;
reg WbRegsDmacSelReg ;
wire WbRegsDmacCyc ;
wire WbRegsDmacStb ;
reg WbRegsBiosSel ;
reg WbRegsBiosSelReg ;
wire WbRegsBiosCyc ;
wire WbRegsBiosStb ;
reg WbRegsMdecSel ;
reg WbRegsMdecSelReg ;
wire WbRegsMdecCyc ;
wire WbRegsMdecStb ;
reg WbRegsMemcardSel ;
reg WbRegsMemcardSelReg ;
wire WbRegsMemcardCyc ;
wire WbRegsMemcardStb ;
reg WbRegsSpuSel ;
reg WbRegsSpuSelReg ;
wire WbRegsSpuCyc ;
wire WbRegsSpuStb ;
reg WbRegsCdromSel ;
reg WbRegsCdromSelReg ;
wire WbRegsCdromCyc ;
wire WbRegsCdromStb ;
reg WbRegsPadSel ;
reg WbRegsPadSelReg ;
wire WbRegsPadCyc ;
wire WbRegsPadStb ;
reg WbRegsDefaultSel ;
reg WbRegsDefaultSelReg ;
wire WbRegsDefaultCyc ;
wire WbRegsDefaultStb ;
wire WbRegsDefaultAck ;
wire WbRegsDefaultStall ;
wire WbRegsDefaultErr ;
wire [31:0] WbRegsDefaultDatRd = 32'h0000_0000;
assign WbSysRomSel = WbSysCyc & WbSysStb & (ROM_SEL_VAL == WbSysAdr[ROM_SEL_MSB :ROM_SEL_LSB ]);
assign WbSysDramSel = WbSysCyc & WbSysStb & (DRAM_SEL_VAL == WbSysAdr[DRAM_SEL_MSB:DRAM_SEL_LSB ]);
assign WbSysGpuSel = WbSysCyc & WbSysStb & (GPU_SEL_VAL == WbSysAdr[GPU_SEL_MSB :GPU_SEL_LSB ]);
assign WbSysRegsSel = WbSysCyc & WbSysStb & (REGS_SEL_VAL == WbSysAdr[REGS_SEL_MSB:REGS_SEL_LSB ]
& ~WbSysGpuSel);
assign WbSysDefaultSel = WbSysCyc & WbSysStb & ~(WbSysRomSel | WbSysDramSel | WbSysGpuSel | WbSysRegsSel);
assign WbSysRomCyc = WbSysCyc & (WbSysRomSel | WbSysRomSelReg );
assign WbSysDramCyc = WbSysCyc & (WbSysDramSel | WbSysDramSelReg );
assign WbSysGpuCyc = WbSysCyc & (WbSysGpuSel | WbSysGpuSelReg );
assign WbSysRegsCyc = WbSysCyc & (WbSysRegsSel | WbSysRegsSelReg );
assign WbSysDefaultCyc = WbSysCyc & (WbSysDefaultSel | WbSysDefaultSelReg);
assign WbSysRomStb = WbSysStb & WbSysRomSel ;
assign WbSysDramStb = WbSysStb & WbSysDramSel;
assign WbSysGpuStb = WbSysStb & WbSysGpuSel ;
assign WbSysRegsStb = WbSysStb & WbSysRegsSel;
assign WbSysDefaultStb = WbSysStb & WbSysDefaultSel;
assign WbRegsRcntCyc = WbRegsCyc & (WbRegsRcntSel | WbRegsRcntSelReg );
assign WbRegsIntcCyc = WbRegsCyc & (WbRegsIntcSel | WbRegsIntcSelReg );
assign WbRegsDmacCyc = WbRegsCyc & (WbRegsDmacSel | WbRegsDmacSelReg );
assign WbRegsBiosCyc = WbRegsCyc & (WbRegsBiosSel | WbRegsBiosSelReg );
assign WbRegsMdecCyc = WbRegsCyc & (WbRegsMdecSel | WbRegsMdecSelReg );
assign WbRegsMemcardCyc = WbRegsCyc & (WbRegsMemcardSel | WbRegsMemcardSelReg );
assign WbRegsSpuCyc = WbRegsCyc & (WbRegsSpuSel | WbRegsSpuSelReg );
assign WbRegsCdromCyc = WbRegsCyc & (WbRegsCdromSel | WbRegsCdromSelReg );
assign WbRegsPadCyc = WbRegsCyc & (WbRegsPadSel | WbRegsPadSelReg );
assign WbRegsDefaultCyc = WbRegsCyc & (WbRegsDefaultSel | WbRegsDefaultSelReg );
assign WbRegsRcntStb = WbRegsStb & WbRegsRcntSel ;
assign WbRegsIntcStb = WbRegsStb & WbRegsIntcSel ;
assign WbRegsDmacStb = WbRegsStb & WbRegsDmacSel ;
assign WbRegsBiosStb = WbRegsStb & WbRegsBiosSel ;
assign WbRegsMdecStb = WbRegsStb & WbRegsMdecSel ;
assign WbRegsMemcardStb = WbRegsStb & WbRegsMemcardSel;
assign WbRegsSpuStb = WbRegsStb & WbRegsSpuSel ;
assign WbRegsCdromStb = WbRegsStb & WbRegsCdromSel ;
assign WbRegsPadStb = WbRegsStb & WbRegsPadSel ;
assign WbRegsDefaultStb = WbRegsStb & WbRegsDefaultSel;
assign WbRegsAck = ( ( WbRegsRcntSelReg & WB_REGS_RCNT_ACK_IN )
| ( WbRegsIntcSelReg & WB_REGS_INTC_ACK_IN )
| ( WbRegsDmacSelReg & WB_REGS_DMAC_ACK_IN )
| ( WbRegsBiosSelReg & WB_REGS_BIOS_ACK_IN )
| ( WbRegsMdecSelReg & WB_REGS_MDEC_ACK_IN )
| ( WbRegsMemcardSelReg & WB_REGS_MEMCARD_ACK_IN )
| ( WbRegsSpuSelReg & WB_REGS_SPU_ACK_IN )
| ( WbRegsCdromSelReg & WB_REGS_CDROM_ACK_IN )
| ( WbRegsPadSelReg & WB_REGS_PAD_ACK_IN )
| ( WbRegsDefaultSelReg & WbRegsDefaultAck )
);
assign WbRegsStall =( ( WbRegsRcntSel & WB_REGS_RCNT_STALL_IN )
| ( WbRegsIntcSel & WB_REGS_INTC_STALL_IN )
| ( WbRegsDmacSel & WB_REGS_DMAC_STALL_IN )
| ( WbRegsBiosSel & WB_REGS_BIOS_STALL_IN )
| ( WbRegsMdecSel & WB_REGS_MDEC_STALL_IN )
| ( WbRegsMemcardSel & WB_REGS_MEMCARD_STALL_IN )
| ( WbRegsSpuSel & WB_REGS_SPU_STALL_IN )
| ( WbRegsCdromSel & WB_REGS_CDROM_STALL_IN )
| ( WbRegsPadSel & WB_REGS_PAD_STALL_IN )
| ( WbRegsDefaultSel & WbRegsDefaultStall )
| ( WbRegsRcntSelReg & ~WB_REGS_RCNT_ACK_IN )
| ( WbRegsIntcSelReg & ~WB_REGS_INTC_ACK_IN )
| ( WbRegsDmacSelReg & ~WB_REGS_DMAC_ACK_IN )
| ( WbRegsBiosSelReg & ~WB_REGS_BIOS_ACK_IN )
| ( WbRegsMdecSelReg & ~WB_REGS_MDEC_ACK_IN )
| ( WbRegsMemcardSelReg & ~WB_REGS_MEMCARD_ACK_IN )
| ( WbRegsSpuSelReg & ~WB_REGS_SPU_ACK_IN )
| ( WbRegsCdromSelReg & ~WB_REGS_CDROM_ACK_IN )
| ( WbRegsPadSelReg & ~WB_REGS_PAD_ACK_IN )
| ( WbRegsDefaultSelReg & ~WbRegsDefaultAck )
);
assign WbRegsErr = ( ( WbRegsRcntSelReg & WB_REGS_RCNT_ERR_IN )
| ( WbRegsIntcSelReg & WB_REGS_INTC_ERR_IN )
| ( WbRegsDmacSelReg & WB_REGS_DMAC_ERR_IN )
| ( WbRegsBiosSelReg & WB_REGS_BIOS_ERR_IN )
| ( WbRegsMdecSelReg & WB_REGS_MDEC_ERR_IN )
| ( WbRegsMemcardSelReg & WB_REGS_MEMCARD_ERR_IN )
| ( WbRegsSpuSelReg & WB_REGS_SPU_ERR_IN )
| ( WbRegsCdromSelReg & WB_REGS_CDROM_ERR_IN )
| ( WbRegsPadSelReg & WB_REGS_PAD_ERR_IN )
| ( WbRegsDefaultSelReg & WbRegsDefaultErr )
);
assign WbRegsDatRd = ( ( {DAT_W {WbRegsRcntSelReg}} & WB_REGS_RCNT_DAT_RD_IN )
| ( {DAT_W {WbRegsIntcSelReg}} & WB_REGS_INTC_DAT_RD_IN )
| ( {DAT_W {WbRegsDmacSelReg}} & WB_REGS_DMAC_DAT_RD_IN )
| ( {DAT_W {WbRegsBiosSelReg}} & WB_REGS_BIOS_DAT_RD_IN )
| ( {DAT_W {WbRegsMdecSelReg}} & WB_REGS_MDEC_DAT_RD_IN )
| ( {DAT_W {WbRegsMemcardSelReg}} & WB_REGS_MEMCARD_DAT_RD_IN )
| ( {DAT_W {WbRegsSpuSelReg}} & WB_REGS_SPU_DAT_RD_IN )
| ( {DAT_W {WbRegsCdromSelReg}} & WB_REGS_CDROM_DAT_RD_IN )
| ( {DAT_W {WbRegsPadSelReg}} & WB_REGS_PAD_DAT_RD_IN )
| ( {DAT_W {WbRegsDefaultSelReg}} & WbRegsDefaultDatRd )
);
assign WB_REGS_ADR_OUT = WbRegsAdr ;
assign WB_REGS_WE_OUT = WbRegsWe ;
assign WB_REGS_SEL_OUT = WbRegsSel ;
assign WB_REGS_DAT_WR_OUT = WbRegsDatWr ;
assign WB_REGS_RCNT_CYC_OUT = WbRegsRcntCyc ;
assign WB_REGS_RCNT_STB_OUT = WbRegsRcntStb ;
assign WB_REGS_INTC_CYC_OUT = WbRegsIntcCyc ;
assign WB_REGS_INTC_STB_OUT = WbRegsIntcStb ;
assign WB_REGS_DMAC_CYC_OUT = WbRegsDmacCyc ;
assign WB_REGS_DMAC_STB_OUT = WbRegsDmacStb ;
assign WB_REGS_BIOS_CYC_OUT = WbRegsBiosCyc ;
assign WB_REGS_BIOS_STB_OUT = WbRegsBiosStb ;
assign WB_REGS_MDEC_CYC_OUT = WbRegsMdecCyc ;
assign WB_REGS_MDEC_STB_OUT = WbRegsMdecStb ;
assign WB_REGS_MEMCARD_CYC_OUT = WbRegsMemcardCyc ;
assign WB_REGS_MEMCARD_STB_OUT = WbRegsMemcardStb ;
assign WB_REGS_SPU_CYC_OUT = WbRegsSpuCyc ;
assign WB_REGS_SPU_STB_OUT = WbRegsSpuStb ;
assign WB_REGS_CDROM_CYC_OUT = WbRegsCdromCyc ;
assign WB_REGS_CDROM_STB_OUT = WbRegsCdromStb ;
assign WB_REGS_PAD_CYC_OUT = WbRegsPadCyc ;
assign WB_REGS_PAD_STB_OUT = WbRegsPadStb ;
assign WB_SYS_ADR_OUT = WbSysAdr ;
assign WB_SYS_WE_OUT = WbSysWe ;
assign WB_SYS_SEL_OUT = WbSysSel ;
assign WB_SYS_CTI_OUT = WbSysCti ;
assign WB_SYS_BTE_OUT = WbSysBte ;
assign WB_SYS_DAT_WR_OUT = WbSysDatWr ;
assign WB_SYS_ROM_CYC_OUT = WbSysRomCyc ;
assign WB_SYS_ROM_STB_OUT = WbSysRomStb ;
assign WB_SYS_DRAM_CYC_OUT = WbSysDramCyc;
assign WB_SYS_DRAM_STB_OUT = WbSysDramStb;
assign WB_SYS_GPU_CYC_OUT = WbSysGpuCyc ;
assign WB_SYS_GPU_STB_OUT = WbSysGpuStb ;
assign WbSysAck = ( (WbSysRomSelReg & WB_SYS_ROM_ACK_IN )
| (WbSysDramSelReg & WB_SYS_DRAM_ACK_IN )
| (WbSysGpuSelReg & WB_SYS_GPU_ACK_IN )
| (WbSysRegsSelReg & WbSysRegsAck )
| (WbSysDefaultSelReg & WbSysDefaultAck )
);
assign WbSysStall = ( (WbSysRomSel & WB_SYS_ROM_STALL_IN )
| (WbSysDramSel & WB_SYS_DRAM_STALL_IN )
| (WbSysGpuSel & WB_SYS_GPU_STALL_IN )
| (WbSysRegsSel & WbSysRegsStall )
| (WbSysDefaultSel & WbSysDefaultStall )
| (WbSysRomSelReg & ~WB_SYS_ROM_ACK_IN )
| (WbSysDramSelReg & ~WB_SYS_DRAM_ACK_IN )
| (WbSysGpuSelReg & ~WB_SYS_GPU_ACK_IN )
| (WbSysRegsSelReg & ~WbSysRegsAck )
| (WbSysDefaultSelReg & ~WbSysDefaultAck )
);
assign WbSysErr = ( (WbSysRomSelReg & WB_SYS_ROM_ERR_IN )
| (WbSysDramSelReg & WB_SYS_DRAM_ERR_IN )
| (WbSysGpuSelReg & WB_SYS_GPU_ERR_IN )
| (WbSysRegsSelReg & WbSysRegsErr )
| (WbSysDefaultSelReg & WbSysDefaultErr )
) ;
assign WbSysDatRd = ( ({DAT_W {WbSysRomSelReg}} & WB_SYS_ROM_DAT_RD_IN )
| ({DAT_W {WbSysDramSelReg}} & WB_SYS_DRAM_DAT_RD_IN )
| ({DAT_W {WbSysGpuSelReg}} & WB_SYS_GPU_DAT_RD_IN )
| ({DAT_W {WbSysRegsSelReg}} & WbSysRegsDatRd )
| ({DAT_W {WbSysDefaultSelReg}} & WbSysDefaultDatRd )
);
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysRomSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysRomSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysRomSel)
begin
WbSysRomSelReg <= 1'b1;
end
else if (WbSysCyc && (WB_SYS_ROM_ACK_IN || WB_SYS_ROM_ERR_IN))
begin
WbSysRomSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysDramSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysDramSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysDramSel)
begin
WbSysDramSelReg <= 1'b1;
end
else if (WbSysCyc && (WB_SYS_DRAM_ACK_IN || WB_SYS_DRAM_ERR_IN))
begin
WbSysDramSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysGpuSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysGpuSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysGpuSel)
begin
WbSysGpuSelReg <= 1'b1;
end
else if (WbSysCyc && (WB_SYS_GPU_ACK_IN || WB_SYS_GPU_ERR_IN))
begin
WbSysGpuSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysRegsSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysRegsSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysRegsSel)
begin
WbSysRegsSelReg <= 1'b1;
end
else if (WbSysCyc && (WbSysRegsAck || WbSysRegsErr))
begin
WbSysRegsSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysDefaultSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysDefaultSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysDefaultSel)
begin
WbSysDefaultSelReg <= 1'b1;
end
else if (WbSysCyc && (WbSysDefaultAck || WbSysDefaultErr))
begin
WbSysDefaultSelReg <= 1'b0;
end
end
end
always @*
begin : REGS_SEL_DECODE
WbRegsRcntSel = 1'b0;
WbRegsIntcSel = 1'b0;
WbRegsDmacSel = 1'b0;
WbRegsBiosSel = 1'b0;
WbRegsMdecSel = 1'b0;
WbRegsMemcardSel = 1'b0;
WbRegsSpuSel = 1'b0;
WbRegsCdromSel = 1'b0;
WbRegsPadSel = 1'b0;
WbRegsDefaultSel = 1'b0;
if (WbRegsAdr[REGS_SEL_LSB-1:0] >= SPU_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsSpuSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= MDEC_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsMdecSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= CDROM_REGS_BASE_WIRE[REGS_SEL_LSB-1:0])
begin
WbRegsCdromSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= RCNT_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsRcntSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= DMAC_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsDmacSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= INTC_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsIntcSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= BIOS_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsBiosSel = 1'b1;
end
else
begin
WbRegsDefaultSel = 1'b1;
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsRcntSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsRcntSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsRcntSel)
begin
WbRegsRcntSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_RCNT_ACK_IN || WB_REGS_RCNT_ERR_IN))
begin
WbRegsRcntSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsIntcSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsIntcSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsIntcSel)
begin
WbRegsIntcSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_INTC_ACK_IN || WB_REGS_INTC_ERR_IN))
begin
WbRegsIntcSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsDmacSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsDmacSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsDmacSel)
begin
WbRegsDmacSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_DMAC_ACK_IN || WB_REGS_DMAC_ERR_IN))
begin
WbRegsDmacSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsBiosSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsBiosSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsBiosSel)
begin
WbRegsBiosSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_BIOS_ACK_IN || WB_REGS_BIOS_ERR_IN))
begin
WbRegsBiosSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsMdecSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsMdecSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsMdecSel)
begin
WbRegsMdecSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_MDEC_ACK_IN || WB_REGS_MDEC_ERR_IN))
begin
WbRegsMdecSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsMemcardSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsMemcardSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsMemcardSel)
begin
WbRegsMemcardSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_MDEC_ACK_IN || WB_REGS_MEMCARD_ERR_IN))
begin
WbRegsMemcardSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsSpuSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsSpuSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsSpuSel)
begin
WbRegsSpuSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_SPU_ACK_IN || WB_REGS_SPU_ERR_IN))
begin
WbRegsSpuSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsCdromSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsCdromSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsCdromSel)
begin
WbRegsCdromSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_CDROM_ACK_IN || WB_REGS_CDROM_ERR_IN))
begin
WbRegsCdromSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsPadSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsPadSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsPadSel)
begin
WbRegsPadSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_PAD_ACK_IN || WB_REGS_PAD_ERR_IN))
begin
WbRegsPadSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsDefaultSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsDefaultSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsDefaultSel)
begin
WbRegsDefaultSelReg <= 1'b1;
end
else if (WbRegsCyc && (WbRegsDefaultAck || WbRegsDefaultErr))
begin
WbRegsDefaultSelReg <= 1'b0;
end
end
end
WB_ARB_2M_1S wb_arb_2m_1s
(
.CLK (CLK_SYS ),
.EN (EN_SYS ),
.RST_SYNC (RST_SYNC_SYS ),
.RST_ASYNC (RST_ASYNC_SYS ),
.WB_SL0_ADR_IN (WB_MIPS_ADR_IN ),
.WB_SL0_CYC_IN (WB_MIPS_CYC_IN ),
.WB_SL0_STB_IN (WB_MIPS_STB_IN ),
.WB_SL0_WE_IN (WB_MIPS_WE_IN ),
.WB_SL0_SEL_IN (WB_MIPS_SEL_IN ),
.WB_SL0_CTI_IN (WB_MIPS_CTI_IN ),
.WB_SL0_BTE_IN (WB_MIPS_BTE_IN ),
.WB_SL0_STALL_OUT (WB_MIPS_STALL_OUT ),
.WB_SL0_ACK_OUT (WB_MIPS_ACK_OUT ),
.WB_SL0_ERR_OUT (WB_MIPS_ERR_OUT ),
.WB_SL0_RD_DAT_OUT (WB_MIPS_RD_DAT_OUT ),
.WB_SL0_WR_DAT_IN (WB_MIPS_WR_DAT_IN ),
.WB_SL1_ADR_IN (WB_DMAC_ADR_IN ),
.WB_SL1_CYC_IN (WB_DMAC_CYC_IN ),
.WB_SL1_STB_IN (WB_DMAC_STB_IN ),
.WB_SL1_WE_IN (WB_DMAC_WE_IN ),
.WB_SL1_SEL_IN (WB_DMAC_SEL_IN ),
.WB_SL1_CTI_IN (WB_DMAC_CTI_IN ),
.WB_SL1_BTE_IN (WB_DMAC_BTE_IN ),
.WB_SL1_STALL_OUT (WB_DMAC_STALL_OUT ),
.WB_SL1_ACK_OUT (WB_DMAC_ACK_OUT ),
.WB_SL1_ERR_OUT (WB_DMAC_ERR_OUT ),
.WB_SL1_RD_DAT_OUT (WB_DMAC_RD_DAT_OUT ),
.WB_SL1_WR_DAT_IN (WB_DMAC_WR_DAT_IN ),
.WB_M0_ADR_OUT (WbSysAdr ),
.WB_M0_CYC_OUT (WbSysCyc ),
.WB_M0_STB_OUT (WbSysStb ),
.WB_M0_WE_OUT (WbSysWe ),
.WB_M0_SEL_OUT (WbSysSel ),
.WB_M0_CTI_OUT (WbSysCti ),
.WB_M0_BTE_OUT (WbSysBte ),
.WB_M0_STALL_IN (WbSysStall ),
.WB_M0_ACK_IN (WbSysAck ),
.WB_M0_ERR_IN (WbSysErr ),
.WB_M0_RD_DAT_IN (WbSysDatRd ),
.WB_M0_WR_DAT_OUT (WbSysDatWr )
);
WB_SLAVE_CTRL
#(.DEFAULT_SLAVE ( 1),
.DEFAULT_ERR ( 0),
.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 0)
)
wb_slave_ctrl_sys
(
.CLK (CLK_SYS ),
.EN (EN_SYS ),
.RST_SYNC (RST_SYNC_SYS ),
.RST_ASYNC (RST_ASYNC_SYS ),
.WB_REGS_ADR_IN (WbSysAdr ),
.WB_REGS_CYC_IN (WbSysDefaultCyc ),
.WB_REGS_STB_IN (WbSysDefaultStb ),
.WB_REGS_WE_IN (WbSysWe ),
.WB_REGS_SEL_IN (WbSysSel ),
.WB_REGS_ACK_OUT (WbSysDefaultAck ),
.WB_REGS_STALL_OUT (WbSysDefaultStall ),
.WB_REGS_ERR_OUT (WbSysDefaultErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
WB_SLAVE_CTRL
#(.DEFAULT_SLAVE ( 1),
.DEFAULT_ERR ( 0),
.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 0)
)
wb_slave_ctrl_regs
(
.CLK (CLK_REGS ),
.EN (EN_REGS ),
.RST_SYNC (RST_SYNC_REGS ),
.RST_ASYNC (RST_ASYNC_REGS ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsDefaultCyc ),
.WB_REGS_STB_IN (WbRegsDefaultStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsDefaultAck ),
.WB_REGS_STALL_OUT (WbRegsDefaultStall ),
.WB_REGS_ERR_OUT (WbRegsDefaultErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
WB_SYNC_BRIDGE wb_sync_bridge_regs
(
.CLK_SRC (CLK_SYS ),
.EN_SRC (EN_SYS ),
.RST_SRC_SYNC (RST_SYNC_SYS ),
.RST_SRC_ASYNC (RST_ASYNC_SYS ),
.CLK_DST (CLK_REGS ),
.EN_DST (EN_REGS ),
.RST_DST_SYNC (RST_SYNC_REGS ),
.RST_DST_ASYNC (RST_ASYNC_REGS ),
.WB_S_ADR_IN (WbSysAdr ),
.WB_S_CYC_IN (WbSysRegsCyc ),
.WB_S_STB_IN (WbSysRegsStb ),
.WB_S_WE_IN (WbSysWe ),
.WB_S_SEL_IN (WbSysSel ),
.WB_S_CTI_IN (WbSysCti ),
.WB_S_BTE_IN (WbSysBte ),
.WB_S_STALL_OUT (WbSysRegsStall ),
.WB_S_ACK_OUT (WbSysRegsAck ),
.WB_S_ERR_OUT (WbSysRegsErr ),
.WB_S_DAT_RD_OUT (WbSysRegsDatRd ),
.WB_S_DAT_WR_IN (WbSysDatWr ),
.WB_M_ADR_OUT (WbRegsAdr ),
.WB_M_CYC_OUT (WbRegsCyc ),
.WB_M_STB_OUT (WbRegsStb ),
.WB_M_WE_OUT (WbRegsWe ),
.WB_M_SEL_OUT (WbRegsSel ),
.WB_M_CTI_OUT (WbRegsCti ),
.WB_M_BTE_OUT (WbRegsBte ),
.WB_M_ACK_IN (WbRegsAck ),
.WB_M_STALL_IN (WbRegsStall ),
.WB_M_ERR_IN (WbRegsErr ),
.WB_M_DAT_RD_IN (WbRegsDatRd ),
.WB_M_DAT_WR_OUT (WbRegsDatWr )
);
endmodule | module PSX_BUS
(
input CLK_SYS ,
input EN_SYS ,
input RST_SYNC_SYS ,
input RST_ASYNC_SYS ,
input CLK_REGS ,
input EN_REGS ,
input RST_SYNC_REGS ,
input RST_ASYNC_REGS ,
input [31:0] WB_MIPS_ADR_IN ,
input WB_MIPS_CYC_IN ,
input WB_MIPS_STB_IN ,
input WB_MIPS_WE_IN ,
input [ 3:0] WB_MIPS_SEL_IN ,
input [ 2:0] WB_MIPS_CTI_IN ,
input [ 1:0] WB_MIPS_BTE_IN ,
output WB_MIPS_STALL_OUT ,
output WB_MIPS_ACK_OUT ,
output WB_MIPS_ERR_OUT ,
output [31:0] WB_MIPS_RD_DAT_OUT ,
input [31:0] WB_MIPS_WR_DAT_IN ,
input [31:0] WB_DMAC_ADR_IN ,
input WB_DMAC_CYC_IN ,
input WB_DMAC_STB_IN ,
input WB_DMAC_WE_IN ,
input [ 3:0] WB_DMAC_SEL_IN ,
input [ 2:0] WB_DMAC_CTI_IN ,
input [ 1:0] WB_DMAC_BTE_IN ,
output WB_DMAC_STALL_OUT ,
output WB_DMAC_ACK_OUT ,
output WB_DMAC_ERR_OUT ,
output [31:0] WB_DMAC_RD_DAT_OUT ,
input [31:0] WB_DMAC_WR_DAT_IN ,
output [31:0] WB_SYS_ADR_OUT ,
output WB_SYS_WE_OUT ,
output [ 3:0] WB_SYS_SEL_OUT ,
output [ 2:0] WB_SYS_CTI_OUT ,
output [ 1:0] WB_SYS_BTE_OUT ,
output [31:0] WB_SYS_DAT_WR_OUT ,
output WB_SYS_ROM_CYC_OUT ,
output WB_SYS_ROM_STB_OUT ,
output WB_SYS_DRAM_CYC_OUT ,
output WB_SYS_DRAM_STB_OUT ,
output WB_SYS_GPU_CYC_OUT ,
output WB_SYS_GPU_STB_OUT ,
input WB_SYS_ROM_ACK_IN ,
input WB_SYS_ROM_STALL_IN ,
input WB_SYS_ROM_ERR_IN ,
input [31:0] WB_SYS_ROM_DAT_RD_IN ,
input WB_SYS_DRAM_ACK_IN ,
input WB_SYS_DRAM_STALL_IN ,
input WB_SYS_DRAM_ERR_IN ,
input [31:0] WB_SYS_DRAM_DAT_RD_IN ,
input WB_SYS_GPU_ACK_IN ,
input WB_SYS_GPU_STALL_IN ,
input WB_SYS_GPU_ERR_IN ,
input [31:0] WB_SYS_GPU_DAT_RD_IN ,
output [31:0] WB_REGS_ADR_OUT ,
output WB_REGS_WE_OUT ,
output [ 3:0] WB_REGS_SEL_OUT ,
output [31:0] WB_REGS_DAT_WR_OUT ,
output WB_REGS_RCNT_CYC_OUT ,
output WB_REGS_RCNT_STB_OUT ,
output WB_REGS_INTC_CYC_OUT ,
output WB_REGS_INTC_STB_OUT ,
output WB_REGS_DMAC_CYC_OUT ,
output WB_REGS_DMAC_STB_OUT ,
output WB_REGS_BIOS_CYC_OUT ,
output WB_REGS_BIOS_STB_OUT ,
output WB_REGS_MDEC_CYC_OUT ,
output WB_REGS_MDEC_STB_OUT ,
output WB_REGS_MEMCARD_CYC_OUT ,
output WB_REGS_MEMCARD_STB_OUT ,
output WB_REGS_SPU_CYC_OUT ,
output WB_REGS_SPU_STB_OUT ,
output WB_REGS_CDROM_CYC_OUT ,
output WB_REGS_CDROM_STB_OUT ,
output WB_REGS_PAD_CYC_OUT ,
output WB_REGS_PAD_STB_OUT ,
input WB_REGS_RCNT_ACK_IN ,
input WB_REGS_RCNT_STALL_IN ,
input WB_REGS_RCNT_ERR_IN ,
input [31:0] WB_REGS_RCNT_DAT_RD_IN ,
input WB_REGS_INTC_ACK_IN ,
input WB_REGS_INTC_STALL_IN ,
input WB_REGS_INTC_ERR_IN ,
input [31:0] WB_REGS_INTC_DAT_RD_IN ,
input WB_REGS_DMAC_ACK_IN ,
input WB_REGS_DMAC_STALL_IN ,
input WB_REGS_DMAC_ERR_IN ,
input [31:0] WB_REGS_DMAC_DAT_RD_IN ,
input WB_REGS_BIOS_ACK_IN ,
input WB_REGS_BIOS_STALL_IN ,
input WB_REGS_BIOS_ERR_IN ,
input [31:0] WB_REGS_BIOS_DAT_RD_IN ,
input WB_REGS_MDEC_ACK_IN ,
input WB_REGS_MDEC_STALL_IN ,
input WB_REGS_MDEC_ERR_IN ,
input [31:0] WB_REGS_MDEC_DAT_RD_IN ,
input WB_REGS_MEMCARD_ACK_IN ,
input WB_REGS_MEMCARD_STALL_IN ,
input WB_REGS_MEMCARD_ERR_IN ,
input [31:0] WB_REGS_MEMCARD_DAT_RD_IN ,
input WB_REGS_SPU_ACK_IN ,
input WB_REGS_SPU_STALL_IN ,
input WB_REGS_SPU_ERR_IN ,
input [31:0] WB_REGS_SPU_DAT_RD_IN ,
input WB_REGS_CDROM_ACK_IN ,
input WB_REGS_CDROM_STALL_IN ,
input WB_REGS_CDROM_ERR_IN ,
input [31:0] WB_REGS_CDROM_DAT_RD_IN ,
input WB_REGS_PAD_ACK_IN ,
input WB_REGS_PAD_STALL_IN ,
input WB_REGS_PAD_ERR_IN ,
input [31:0] WB_REGS_PAD_DAT_RD_IN
); |
`include "psx_mem_map.vh"
`include "wb_defs.v"
wire [31:0] WbSysAdr ;
wire WbSysCyc ;
wire WbSysStb ;
wire WbSysWe ;
wire [ 3:0] WbSysSel ;
wire [ 2:0] WbSysCti ;
wire [ 1:0] WbSysBte ;
wire WbSysAck ;
wire WbSysStall ;
wire WbSysErr ;
wire [31:0] WbSysDatRd ;
wire [31:0] WbSysDatWr ;
wire WbSysRomSel ;
reg WbSysRomSelReg ;
wire WbSysRomCyc ;
wire WbSysRomStb ;
wire WbSysDramSel ;
reg WbSysDramSelReg ;
wire WbSysDramCyc ;
wire WbSysDramStb ;
wire WbSysGpuSel ;
reg WbSysGpuSelReg ;
wire WbSysGpuCyc ;
wire WbSysGpuStb ;
wire WbSysRegsSel ;
reg WbSysRegsSelReg ;
wire WbSysRegsCyc ;
wire WbSysRegsStb ;
wire WbSysDefaultSel ;
reg WbSysDefaultSelReg ;
wire WbSysDefaultCyc ;
wire WbSysDefaultStb ;
wire WbSysRegsAck ;
wire WbSysRegsStall ;
wire WbSysRegsErr ;
wire [31:0] WbSysRegsDatRd ;
wire WbSysDefaultAck ;
wire WbSysDefaultStall ;
wire WbSysDefaultErr ;
wire [31:0] WbSysDefaultDatRd = 32'h0000_0000;
wire [31:0] WbRegsAdr ;
wire WbRegsCyc ;
wire WbRegsStb ;
wire WbRegsWe ;
wire [ 3:0] WbRegsSel ;
wire [ 2:0] WbRegsCti ;
wire [ 1:0] WbRegsBte ;
wire WbRegsAck ;
wire WbRegsStall ;
wire WbRegsErr ;
wire [31:0] WbRegsDatRd ;
wire [31:0] WbRegsDatWr ;
reg WbRegsRcntSel ;
reg WbRegsRcntSelReg ;
wire WbRegsRcntCyc ;
wire WbRegsRcntStb ;
reg WbRegsIntcSel ;
reg WbRegsIntcSelReg ;
wire WbRegsIntcCyc ;
wire WbRegsIntcStb ;
reg WbRegsDmacSel ;
reg WbRegsDmacSelReg ;
wire WbRegsDmacCyc ;
wire WbRegsDmacStb ;
reg WbRegsBiosSel ;
reg WbRegsBiosSelReg ;
wire WbRegsBiosCyc ;
wire WbRegsBiosStb ;
reg WbRegsMdecSel ;
reg WbRegsMdecSelReg ;
wire WbRegsMdecCyc ;
wire WbRegsMdecStb ;
reg WbRegsMemcardSel ;
reg WbRegsMemcardSelReg ;
wire WbRegsMemcardCyc ;
wire WbRegsMemcardStb ;
reg WbRegsSpuSel ;
reg WbRegsSpuSelReg ;
wire WbRegsSpuCyc ;
wire WbRegsSpuStb ;
reg WbRegsCdromSel ;
reg WbRegsCdromSelReg ;
wire WbRegsCdromCyc ;
wire WbRegsCdromStb ;
reg WbRegsPadSel ;
reg WbRegsPadSelReg ;
wire WbRegsPadCyc ;
wire WbRegsPadStb ;
reg WbRegsDefaultSel ;
reg WbRegsDefaultSelReg ;
wire WbRegsDefaultCyc ;
wire WbRegsDefaultStb ;
wire WbRegsDefaultAck ;
wire WbRegsDefaultStall ;
wire WbRegsDefaultErr ;
wire [31:0] WbRegsDefaultDatRd = 32'h0000_0000;
assign WbSysRomSel = WbSysCyc & WbSysStb & (ROM_SEL_VAL == WbSysAdr[ROM_SEL_MSB :ROM_SEL_LSB ]);
assign WbSysDramSel = WbSysCyc & WbSysStb & (DRAM_SEL_VAL == WbSysAdr[DRAM_SEL_MSB:DRAM_SEL_LSB ]);
assign WbSysGpuSel = WbSysCyc & WbSysStb & (GPU_SEL_VAL == WbSysAdr[GPU_SEL_MSB :GPU_SEL_LSB ]);
assign WbSysRegsSel = WbSysCyc & WbSysStb & (REGS_SEL_VAL == WbSysAdr[REGS_SEL_MSB:REGS_SEL_LSB ]
& ~WbSysGpuSel);
assign WbSysDefaultSel = WbSysCyc & WbSysStb & ~(WbSysRomSel | WbSysDramSel | WbSysGpuSel | WbSysRegsSel);
assign WbSysRomCyc = WbSysCyc & (WbSysRomSel | WbSysRomSelReg );
assign WbSysDramCyc = WbSysCyc & (WbSysDramSel | WbSysDramSelReg );
assign WbSysGpuCyc = WbSysCyc & (WbSysGpuSel | WbSysGpuSelReg );
assign WbSysRegsCyc = WbSysCyc & (WbSysRegsSel | WbSysRegsSelReg );
assign WbSysDefaultCyc = WbSysCyc & (WbSysDefaultSel | WbSysDefaultSelReg);
assign WbSysRomStb = WbSysStb & WbSysRomSel ;
assign WbSysDramStb = WbSysStb & WbSysDramSel;
assign WbSysGpuStb = WbSysStb & WbSysGpuSel ;
assign WbSysRegsStb = WbSysStb & WbSysRegsSel;
assign WbSysDefaultStb = WbSysStb & WbSysDefaultSel;
assign WbRegsRcntCyc = WbRegsCyc & (WbRegsRcntSel | WbRegsRcntSelReg );
assign WbRegsIntcCyc = WbRegsCyc & (WbRegsIntcSel | WbRegsIntcSelReg );
assign WbRegsDmacCyc = WbRegsCyc & (WbRegsDmacSel | WbRegsDmacSelReg );
assign WbRegsBiosCyc = WbRegsCyc & (WbRegsBiosSel | WbRegsBiosSelReg );
assign WbRegsMdecCyc = WbRegsCyc & (WbRegsMdecSel | WbRegsMdecSelReg );
assign WbRegsMemcardCyc = WbRegsCyc & (WbRegsMemcardSel | WbRegsMemcardSelReg );
assign WbRegsSpuCyc = WbRegsCyc & (WbRegsSpuSel | WbRegsSpuSelReg );
assign WbRegsCdromCyc = WbRegsCyc & (WbRegsCdromSel | WbRegsCdromSelReg );
assign WbRegsPadCyc = WbRegsCyc & (WbRegsPadSel | WbRegsPadSelReg );
assign WbRegsDefaultCyc = WbRegsCyc & (WbRegsDefaultSel | WbRegsDefaultSelReg );
assign WbRegsRcntStb = WbRegsStb & WbRegsRcntSel ;
assign WbRegsIntcStb = WbRegsStb & WbRegsIntcSel ;
assign WbRegsDmacStb = WbRegsStb & WbRegsDmacSel ;
assign WbRegsBiosStb = WbRegsStb & WbRegsBiosSel ;
assign WbRegsMdecStb = WbRegsStb & WbRegsMdecSel ;
assign WbRegsMemcardStb = WbRegsStb & WbRegsMemcardSel;
assign WbRegsSpuStb = WbRegsStb & WbRegsSpuSel ;
assign WbRegsCdromStb = WbRegsStb & WbRegsCdromSel ;
assign WbRegsPadStb = WbRegsStb & WbRegsPadSel ;
assign WbRegsDefaultStb = WbRegsStb & WbRegsDefaultSel;
assign WbRegsAck = ( ( WbRegsRcntSelReg & WB_REGS_RCNT_ACK_IN )
| ( WbRegsIntcSelReg & WB_REGS_INTC_ACK_IN )
| ( WbRegsDmacSelReg & WB_REGS_DMAC_ACK_IN )
| ( WbRegsBiosSelReg & WB_REGS_BIOS_ACK_IN )
| ( WbRegsMdecSelReg & WB_REGS_MDEC_ACK_IN )
| ( WbRegsMemcardSelReg & WB_REGS_MEMCARD_ACK_IN )
| ( WbRegsSpuSelReg & WB_REGS_SPU_ACK_IN )
| ( WbRegsCdromSelReg & WB_REGS_CDROM_ACK_IN )
| ( WbRegsPadSelReg & WB_REGS_PAD_ACK_IN )
| ( WbRegsDefaultSelReg & WbRegsDefaultAck )
);
assign WbRegsStall =( ( WbRegsRcntSel & WB_REGS_RCNT_STALL_IN )
| ( WbRegsIntcSel & WB_REGS_INTC_STALL_IN )
| ( WbRegsDmacSel & WB_REGS_DMAC_STALL_IN )
| ( WbRegsBiosSel & WB_REGS_BIOS_STALL_IN )
| ( WbRegsMdecSel & WB_REGS_MDEC_STALL_IN )
| ( WbRegsMemcardSel & WB_REGS_MEMCARD_STALL_IN )
| ( WbRegsSpuSel & WB_REGS_SPU_STALL_IN )
| ( WbRegsCdromSel & WB_REGS_CDROM_STALL_IN )
| ( WbRegsPadSel & WB_REGS_PAD_STALL_IN )
| ( WbRegsDefaultSel & WbRegsDefaultStall )
| ( WbRegsRcntSelReg & ~WB_REGS_RCNT_ACK_IN )
| ( WbRegsIntcSelReg & ~WB_REGS_INTC_ACK_IN )
| ( WbRegsDmacSelReg & ~WB_REGS_DMAC_ACK_IN )
| ( WbRegsBiosSelReg & ~WB_REGS_BIOS_ACK_IN )
| ( WbRegsMdecSelReg & ~WB_REGS_MDEC_ACK_IN )
| ( WbRegsMemcardSelReg & ~WB_REGS_MEMCARD_ACK_IN )
| ( WbRegsSpuSelReg & ~WB_REGS_SPU_ACK_IN )
| ( WbRegsCdromSelReg & ~WB_REGS_CDROM_ACK_IN )
| ( WbRegsPadSelReg & ~WB_REGS_PAD_ACK_IN )
| ( WbRegsDefaultSelReg & ~WbRegsDefaultAck )
);
assign WbRegsErr = ( ( WbRegsRcntSelReg & WB_REGS_RCNT_ERR_IN )
| ( WbRegsIntcSelReg & WB_REGS_INTC_ERR_IN )
| ( WbRegsDmacSelReg & WB_REGS_DMAC_ERR_IN )
| ( WbRegsBiosSelReg & WB_REGS_BIOS_ERR_IN )
| ( WbRegsMdecSelReg & WB_REGS_MDEC_ERR_IN )
| ( WbRegsMemcardSelReg & WB_REGS_MEMCARD_ERR_IN )
| ( WbRegsSpuSelReg & WB_REGS_SPU_ERR_IN )
| ( WbRegsCdromSelReg & WB_REGS_CDROM_ERR_IN )
| ( WbRegsPadSelReg & WB_REGS_PAD_ERR_IN )
| ( WbRegsDefaultSelReg & WbRegsDefaultErr )
);
assign WbRegsDatRd = ( ( {DAT_W {WbRegsRcntSelReg}} & WB_REGS_RCNT_DAT_RD_IN )
| ( {DAT_W {WbRegsIntcSelReg}} & WB_REGS_INTC_DAT_RD_IN )
| ( {DAT_W {WbRegsDmacSelReg}} & WB_REGS_DMAC_DAT_RD_IN )
| ( {DAT_W {WbRegsBiosSelReg}} & WB_REGS_BIOS_DAT_RD_IN )
| ( {DAT_W {WbRegsMdecSelReg}} & WB_REGS_MDEC_DAT_RD_IN )
| ( {DAT_W {WbRegsMemcardSelReg}} & WB_REGS_MEMCARD_DAT_RD_IN )
| ( {DAT_W {WbRegsSpuSelReg}} & WB_REGS_SPU_DAT_RD_IN )
| ( {DAT_W {WbRegsCdromSelReg}} & WB_REGS_CDROM_DAT_RD_IN )
| ( {DAT_W {WbRegsPadSelReg}} & WB_REGS_PAD_DAT_RD_IN )
| ( {DAT_W {WbRegsDefaultSelReg}} & WbRegsDefaultDatRd )
);
assign WB_REGS_ADR_OUT = WbRegsAdr ;
assign WB_REGS_WE_OUT = WbRegsWe ;
assign WB_REGS_SEL_OUT = WbRegsSel ;
assign WB_REGS_DAT_WR_OUT = WbRegsDatWr ;
assign WB_REGS_RCNT_CYC_OUT = WbRegsRcntCyc ;
assign WB_REGS_RCNT_STB_OUT = WbRegsRcntStb ;
assign WB_REGS_INTC_CYC_OUT = WbRegsIntcCyc ;
assign WB_REGS_INTC_STB_OUT = WbRegsIntcStb ;
assign WB_REGS_DMAC_CYC_OUT = WbRegsDmacCyc ;
assign WB_REGS_DMAC_STB_OUT = WbRegsDmacStb ;
assign WB_REGS_BIOS_CYC_OUT = WbRegsBiosCyc ;
assign WB_REGS_BIOS_STB_OUT = WbRegsBiosStb ;
assign WB_REGS_MDEC_CYC_OUT = WbRegsMdecCyc ;
assign WB_REGS_MDEC_STB_OUT = WbRegsMdecStb ;
assign WB_REGS_MEMCARD_CYC_OUT = WbRegsMemcardCyc ;
assign WB_REGS_MEMCARD_STB_OUT = WbRegsMemcardStb ;
assign WB_REGS_SPU_CYC_OUT = WbRegsSpuCyc ;
assign WB_REGS_SPU_STB_OUT = WbRegsSpuStb ;
assign WB_REGS_CDROM_CYC_OUT = WbRegsCdromCyc ;
assign WB_REGS_CDROM_STB_OUT = WbRegsCdromStb ;
assign WB_REGS_PAD_CYC_OUT = WbRegsPadCyc ;
assign WB_REGS_PAD_STB_OUT = WbRegsPadStb ;
assign WB_SYS_ADR_OUT = WbSysAdr ;
assign WB_SYS_WE_OUT = WbSysWe ;
assign WB_SYS_SEL_OUT = WbSysSel ;
assign WB_SYS_CTI_OUT = WbSysCti ;
assign WB_SYS_BTE_OUT = WbSysBte ;
assign WB_SYS_DAT_WR_OUT = WbSysDatWr ;
assign WB_SYS_ROM_CYC_OUT = WbSysRomCyc ;
assign WB_SYS_ROM_STB_OUT = WbSysRomStb ;
assign WB_SYS_DRAM_CYC_OUT = WbSysDramCyc;
assign WB_SYS_DRAM_STB_OUT = WbSysDramStb;
assign WB_SYS_GPU_CYC_OUT = WbSysGpuCyc ;
assign WB_SYS_GPU_STB_OUT = WbSysGpuStb ;
assign WbSysAck = ( (WbSysRomSelReg & WB_SYS_ROM_ACK_IN )
| (WbSysDramSelReg & WB_SYS_DRAM_ACK_IN )
| (WbSysGpuSelReg & WB_SYS_GPU_ACK_IN )
| (WbSysRegsSelReg & WbSysRegsAck )
| (WbSysDefaultSelReg & WbSysDefaultAck )
);
assign WbSysStall = ( (WbSysRomSel & WB_SYS_ROM_STALL_IN )
| (WbSysDramSel & WB_SYS_DRAM_STALL_IN )
| (WbSysGpuSel & WB_SYS_GPU_STALL_IN )
| (WbSysRegsSel & WbSysRegsStall )
| (WbSysDefaultSel & WbSysDefaultStall )
| (WbSysRomSelReg & ~WB_SYS_ROM_ACK_IN )
| (WbSysDramSelReg & ~WB_SYS_DRAM_ACK_IN )
| (WbSysGpuSelReg & ~WB_SYS_GPU_ACK_IN )
| (WbSysRegsSelReg & ~WbSysRegsAck )
| (WbSysDefaultSelReg & ~WbSysDefaultAck )
);
assign WbSysErr = ( (WbSysRomSelReg & WB_SYS_ROM_ERR_IN )
| (WbSysDramSelReg & WB_SYS_DRAM_ERR_IN )
| (WbSysGpuSelReg & WB_SYS_GPU_ERR_IN )
| (WbSysRegsSelReg & WbSysRegsErr )
| (WbSysDefaultSelReg & WbSysDefaultErr )
) ;
assign WbSysDatRd = ( ({DAT_W {WbSysRomSelReg}} & WB_SYS_ROM_DAT_RD_IN )
| ({DAT_W {WbSysDramSelReg}} & WB_SYS_DRAM_DAT_RD_IN )
| ({DAT_W {WbSysGpuSelReg}} & WB_SYS_GPU_DAT_RD_IN )
| ({DAT_W {WbSysRegsSelReg}} & WbSysRegsDatRd )
| ({DAT_W {WbSysDefaultSelReg}} & WbSysDefaultDatRd )
);
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysRomSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysRomSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysRomSel)
begin
WbSysRomSelReg <= 1'b1;
end
else if (WbSysCyc && (WB_SYS_ROM_ACK_IN || WB_SYS_ROM_ERR_IN))
begin
WbSysRomSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysDramSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysDramSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysDramSel)
begin
WbSysDramSelReg <= 1'b1;
end
else if (WbSysCyc && (WB_SYS_DRAM_ACK_IN || WB_SYS_DRAM_ERR_IN))
begin
WbSysDramSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysGpuSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysGpuSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysGpuSel)
begin
WbSysGpuSelReg <= 1'b1;
end
else if (WbSysCyc && (WB_SYS_GPU_ACK_IN || WB_SYS_GPU_ERR_IN))
begin
WbSysGpuSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysRegsSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysRegsSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysRegsSel)
begin
WbSysRegsSelReg <= 1'b1;
end
else if (WbSysCyc && (WbSysRegsAck || WbSysRegsErr))
begin
WbSysRegsSelReg <= 1'b0;
end
end
end
always @(posedge CLK_SYS or posedge RST_ASYNC_SYS)
begin
if (RST_ASYNC_SYS)
begin
WbSysDefaultSelReg <= 1'b0;
end
else if (RST_SYNC_SYS)
begin
WbSysDefaultSelReg <= 1'b0;
end
else if (EN_SYS)
begin
if (WbSysCyc && WbSysStb && !WbSysStall && WbSysDefaultSel)
begin
WbSysDefaultSelReg <= 1'b1;
end
else if (WbSysCyc && (WbSysDefaultAck || WbSysDefaultErr))
begin
WbSysDefaultSelReg <= 1'b0;
end
end
end
always @*
begin : REGS_SEL_DECODE
WbRegsRcntSel = 1'b0;
WbRegsIntcSel = 1'b0;
WbRegsDmacSel = 1'b0;
WbRegsBiosSel = 1'b0;
WbRegsMdecSel = 1'b0;
WbRegsMemcardSel = 1'b0;
WbRegsSpuSel = 1'b0;
WbRegsCdromSel = 1'b0;
WbRegsPadSel = 1'b0;
WbRegsDefaultSel = 1'b0;
if (WbRegsAdr[REGS_SEL_LSB-1:0] >= SPU_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsSpuSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= MDEC_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsMdecSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= CDROM_REGS_BASE_WIRE[REGS_SEL_LSB-1:0])
begin
WbRegsCdromSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= RCNT_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsRcntSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= DMAC_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsDmacSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= INTC_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsIntcSel = 1'b1;
end
else if(WbRegsAdr[REGS_SEL_LSB-1:0] >= BIOS_REGS_BASE_WIRE[REGS_SEL_LSB-1:0] )
begin
WbRegsBiosSel = 1'b1;
end
else
begin
WbRegsDefaultSel = 1'b1;
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsRcntSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsRcntSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsRcntSel)
begin
WbRegsRcntSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_RCNT_ACK_IN || WB_REGS_RCNT_ERR_IN))
begin
WbRegsRcntSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsIntcSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsIntcSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsIntcSel)
begin
WbRegsIntcSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_INTC_ACK_IN || WB_REGS_INTC_ERR_IN))
begin
WbRegsIntcSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsDmacSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsDmacSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsDmacSel)
begin
WbRegsDmacSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_DMAC_ACK_IN || WB_REGS_DMAC_ERR_IN))
begin
WbRegsDmacSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsBiosSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsBiosSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsBiosSel)
begin
WbRegsBiosSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_BIOS_ACK_IN || WB_REGS_BIOS_ERR_IN))
begin
WbRegsBiosSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsMdecSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsMdecSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsMdecSel)
begin
WbRegsMdecSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_MDEC_ACK_IN || WB_REGS_MDEC_ERR_IN))
begin
WbRegsMdecSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsMemcardSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsMemcardSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsMemcardSel)
begin
WbRegsMemcardSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_MDEC_ACK_IN || WB_REGS_MEMCARD_ERR_IN))
begin
WbRegsMemcardSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsSpuSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsSpuSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsSpuSel)
begin
WbRegsSpuSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_SPU_ACK_IN || WB_REGS_SPU_ERR_IN))
begin
WbRegsSpuSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsCdromSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsCdromSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsCdromSel)
begin
WbRegsCdromSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_CDROM_ACK_IN || WB_REGS_CDROM_ERR_IN))
begin
WbRegsCdromSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsPadSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsPadSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsPadSel)
begin
WbRegsPadSelReg <= 1'b1;
end
else if (WbRegsCyc && (WB_REGS_PAD_ACK_IN || WB_REGS_PAD_ERR_IN))
begin
WbRegsPadSelReg <= 1'b0;
end
end
end
always @(posedge CLK_REGS or posedge RST_ASYNC_REGS)
begin
if (RST_ASYNC_REGS)
begin
WbRegsDefaultSelReg <= 1'b0;
end
else if (RST_SYNC_REGS)
begin
WbRegsDefaultSelReg <= 1'b0;
end
else if (EN_REGS)
begin
if (WbRegsCyc && WbRegsStb && !WbRegsStall && WbRegsDefaultSel)
begin
WbRegsDefaultSelReg <= 1'b1;
end
else if (WbRegsCyc && (WbRegsDefaultAck || WbRegsDefaultErr))
begin
WbRegsDefaultSelReg <= 1'b0;
end
end
end
WB_ARB_2M_1S wb_arb_2m_1s
(
.CLK (CLK_SYS ),
.EN (EN_SYS ),
.RST_SYNC (RST_SYNC_SYS ),
.RST_ASYNC (RST_ASYNC_SYS ),
.WB_SL0_ADR_IN (WB_MIPS_ADR_IN ),
.WB_SL0_CYC_IN (WB_MIPS_CYC_IN ),
.WB_SL0_STB_IN (WB_MIPS_STB_IN ),
.WB_SL0_WE_IN (WB_MIPS_WE_IN ),
.WB_SL0_SEL_IN (WB_MIPS_SEL_IN ),
.WB_SL0_CTI_IN (WB_MIPS_CTI_IN ),
.WB_SL0_BTE_IN (WB_MIPS_BTE_IN ),
.WB_SL0_STALL_OUT (WB_MIPS_STALL_OUT ),
.WB_SL0_ACK_OUT (WB_MIPS_ACK_OUT ),
.WB_SL0_ERR_OUT (WB_MIPS_ERR_OUT ),
.WB_SL0_RD_DAT_OUT (WB_MIPS_RD_DAT_OUT ),
.WB_SL0_WR_DAT_IN (WB_MIPS_WR_DAT_IN ),
.WB_SL1_ADR_IN (WB_DMAC_ADR_IN ),
.WB_SL1_CYC_IN (WB_DMAC_CYC_IN ),
.WB_SL1_STB_IN (WB_DMAC_STB_IN ),
.WB_SL1_WE_IN (WB_DMAC_WE_IN ),
.WB_SL1_SEL_IN (WB_DMAC_SEL_IN ),
.WB_SL1_CTI_IN (WB_DMAC_CTI_IN ),
.WB_SL1_BTE_IN (WB_DMAC_BTE_IN ),
.WB_SL1_STALL_OUT (WB_DMAC_STALL_OUT ),
.WB_SL1_ACK_OUT (WB_DMAC_ACK_OUT ),
.WB_SL1_ERR_OUT (WB_DMAC_ERR_OUT ),
.WB_SL1_RD_DAT_OUT (WB_DMAC_RD_DAT_OUT ),
.WB_SL1_WR_DAT_IN (WB_DMAC_WR_DAT_IN ),
.WB_M0_ADR_OUT (WbSysAdr ),
.WB_M0_CYC_OUT (WbSysCyc ),
.WB_M0_STB_OUT (WbSysStb ),
.WB_M0_WE_OUT (WbSysWe ),
.WB_M0_SEL_OUT (WbSysSel ),
.WB_M0_CTI_OUT (WbSysCti ),
.WB_M0_BTE_OUT (WbSysBte ),
.WB_M0_STALL_IN (WbSysStall ),
.WB_M0_ACK_IN (WbSysAck ),
.WB_M0_ERR_IN (WbSysErr ),
.WB_M0_RD_DAT_IN (WbSysDatRd ),
.WB_M0_WR_DAT_OUT (WbSysDatWr )
);
WB_SLAVE_CTRL
#(.DEFAULT_SLAVE ( 1),
.DEFAULT_ERR ( 0),
.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 0)
)
wb_slave_ctrl_sys
(
.CLK (CLK_SYS ),
.EN (EN_SYS ),
.RST_SYNC (RST_SYNC_SYS ),
.RST_ASYNC (RST_ASYNC_SYS ),
.WB_REGS_ADR_IN (WbSysAdr ),
.WB_REGS_CYC_IN (WbSysDefaultCyc ),
.WB_REGS_STB_IN (WbSysDefaultStb ),
.WB_REGS_WE_IN (WbSysWe ),
.WB_REGS_SEL_IN (WbSysSel ),
.WB_REGS_ACK_OUT (WbSysDefaultAck ),
.WB_REGS_STALL_OUT (WbSysDefaultStall ),
.WB_REGS_ERR_OUT (WbSysDefaultErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
WB_SLAVE_CTRL
#(.DEFAULT_SLAVE ( 1),
.DEFAULT_ERR ( 0),
.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 0)
)
wb_slave_ctrl_regs
(
.CLK (CLK_REGS ),
.EN (EN_REGS ),
.RST_SYNC (RST_SYNC_REGS ),
.RST_ASYNC (RST_ASYNC_REGS ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsDefaultCyc ),
.WB_REGS_STB_IN (WbRegsDefaultStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsDefaultAck ),
.WB_REGS_STALL_OUT (WbRegsDefaultStall ),
.WB_REGS_ERR_OUT (WbRegsDefaultErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
WB_SYNC_BRIDGE wb_sync_bridge_regs
(
.CLK_SRC (CLK_SYS ),
.EN_SRC (EN_SYS ),
.RST_SRC_SYNC (RST_SYNC_SYS ),
.RST_SRC_ASYNC (RST_ASYNC_SYS ),
.CLK_DST (CLK_REGS ),
.EN_DST (EN_REGS ),
.RST_DST_SYNC (RST_SYNC_REGS ),
.RST_DST_ASYNC (RST_ASYNC_REGS ),
.WB_S_ADR_IN (WbSysAdr ),
.WB_S_CYC_IN (WbSysRegsCyc ),
.WB_S_STB_IN (WbSysRegsStb ),
.WB_S_WE_IN (WbSysWe ),
.WB_S_SEL_IN (WbSysSel ),
.WB_S_CTI_IN (WbSysCti ),
.WB_S_BTE_IN (WbSysBte ),
.WB_S_STALL_OUT (WbSysRegsStall ),
.WB_S_ACK_OUT (WbSysRegsAck ),
.WB_S_ERR_OUT (WbSysRegsErr ),
.WB_S_DAT_RD_OUT (WbSysRegsDatRd ),
.WB_S_DAT_WR_IN (WbSysDatWr ),
.WB_M_ADR_OUT (WbRegsAdr ),
.WB_M_CYC_OUT (WbRegsCyc ),
.WB_M_STB_OUT (WbRegsStb ),
.WB_M_WE_OUT (WbRegsWe ),
.WB_M_SEL_OUT (WbRegsSel ),
.WB_M_CTI_OUT (WbRegsCti ),
.WB_M_BTE_OUT (WbRegsBte ),
.WB_M_ACK_IN (WbRegsAck ),
.WB_M_STALL_IN (WbRegsStall ),
.WB_M_ERR_IN (WbRegsErr ),
.WB_M_DAT_RD_IN (WbRegsDatRd ),
.WB_M_DAT_WR_OUT (WbRegsDatWr )
);
endmodule | 1 |
138,377 | data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v | 83,270,534 | psx_top.v | v | 674 | 88 | [] | [] | [] | [(2, 673)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:237: Cannot find file containing module: 'MIPS1_TOP'\n MIPS1_TOP mips1_top\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/MIPS1_TOP\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/MIPS1_TOP.v\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/MIPS1_TOP.sv\n MIPS1_TOP\n MIPS1_TOP.v\n MIPS1_TOP.sv\n obj_dir/MIPS1_TOP\n obj_dir/MIPS1_TOP.v\n obj_dir/MIPS1_TOP.sv\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:258: Cannot find file containing module: 'DMAC_TOP'\n DMAC_TOP dmac_top\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:300: Cannot find file containing module: 'ROOT_CNT'\n ROOT_CNT root_cnt\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:326: Cannot find file containing module: 'INTC'\n INTC intc\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:349: Cannot find file containing module: 'PSX_BUS'\n PSX_BUS psx_bus\n ^~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:489: Cannot find file containing module: 'WB_SLAVE_CTRL'\n WB_SLAVE_CTRL \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:519: Cannot find file containing module: 'WB_SLAVE_CTRL'\n WB_SLAVE_CTRL \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:549: Cannot find file containing module: 'WB_SLAVE_CTRL'\n WB_SLAVE_CTRL \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:579: Cannot find file containing module: 'WB_SLAVE_CTRL'\n WB_SLAVE_CTRL \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:610: Cannot find file containing module: 'WB_SLAVE_CTRL'\n WB_SLAVE_CTRL \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/psx_top.v:641: Cannot find file containing module: 'WB_SLAVE_CTRL'\n WB_SLAVE_CTRL \n ^~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n" | 302,265 | module | module PSX_TOP
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output [31:0] WB_SYS_ADR_OUT ,
output WB_SYS_ROM_CYC_OUT ,
output WB_SYS_ROM_STB_OUT ,
output WB_SYS_DRAM_CYC_OUT ,
output WB_SYS_DRAM_STB_OUT ,
output WB_SYS_WE_OUT ,
output [ 3:0] WB_SYS_SEL_OUT ,
output [ 2:0] WB_SYS_CTI_OUT ,
output [ 1:0] WB_SYS_BTE_OUT ,
input WB_SYS_ROM_ACK_IN ,
input WB_SYS_ROM_STALL_IN ,
input WB_SYS_ROM_ERR_IN ,
input WB_SYS_DRAM_ACK_IN ,
input WB_SYS_DRAM_STALL_IN ,
input WB_SYS_DRAM_ERR_IN ,
input [31:0] WB_SYS_DAT_ROM_RD_IN ,
input [31:0] WB_SYS_DAT_DRAM_RD_IN ,
output [31:0] WB_SYS_DAT_WR_OUT ,
output [31:0] WB_GPU_ADR_OUT ,
output WB_GPU_CYC_OUT ,
output WB_GPU_STB_OUT ,
output WB_GPU_WE_OUT ,
output [ 3:0] WB_GPU_SEL_OUT ,
output [ 2:0] WB_GPU_CTI_OUT ,
output [ 1:0] WB_GPU_BTE_OUT ,
input WB_GPU_ACK_IN ,
input WB_GPU_STALL_IN ,
input WB_GPU_ERR_IN ,
input [31:0] WB_GPU_DAT_RD_IN ,
output [31:0] WB_GPU_DAT_WR_OUT
);
wire [31:0] WbMipsAdr ;
wire WbMipsCyc ;
wire WbMipsStb ;
wire WbMipsWe ;
wire [ 3:0] WbMipsSel ;
wire [ 2:0] WbMipsCti ;
wire [ 1:0] WbMipsBte ;
wire WbMipsAck ;
wire WbMipsStall ;
wire WbMipsErr ;
wire [31:0] WbMipsDatRd ;
wire [31:0] WbMipsDatWr ;
wire [5:0] MipsTopHwIrq ;
wire WbVsStb ;
wire WbHsStb ;
wire WbActiveRow ;
wire WbActiveCol ;
wire [3:0] RcntIrq ;
wire [10:0] IntSource ;
wire MipsHwInt ;
wire [31:0] WbDmacAdr ;
wire WbDmacCyc ;
wire WbDmacStb ;
wire WbDmacWe ;
wire [ 3:0] WbDmacSel ;
wire [ 2:0] WbDmacCti ;
wire [ 1:0] WbDmacBte ;
wire WbDmacAck ;
wire WbDmacStall ;
wire WbDmacErr ;
wire [31:0] WbDmacDatRd ;
wire [31:0] WbDmacDatWr ;
wire [6:0] DmacReq = 7'b000_0000;
wire [6:0] DmacAck ;
wire DmacIrq ;
wire [31:0] WbSysAdr ;
wire WbSysCyc ;
wire WbSysStb ;
wire WbSysWe ;
wire [ 3:0] WbSysSel ;
wire [ 2:0] WbSysCti ;
wire [ 1:0] WbSysBte ;
wire [31:0] WbSysDatWr ;
wire WbSysRomCyc ;
wire WbSysRomStb ;
wire WbSysDramCyc ;
wire WbSysDramStb ;
wire WbSysGpuCyc ;
wire WbSysGpuStb ;
wire WbSysRomAck ;
wire WbSysRomStall ;
wire WbSysRomErr ;
wire [31:0] WbSysRomDatRd ;
wire WbSysDramAck ;
wire WbSysDramStall ;
wire WbSysDramErr ;
wire [31:0] WbSysDramDatRd ;
wire WbSysGpuAck ;
wire WbSysGpuStall ;
wire WbSysGpuErr ;
wire [31:0] WbSysGpuDatRd ;
wire [31:0] WbRegsAdr ;
wire WbRegsWe ;
wire [ 3:0] WbRegsSel ;
wire [31:0] WbRegsDatWr ;
wire WbRegsRcntCyc ;
wire WbRegsRcntStb ;
wire WbRegsIntcCyc ;
wire WbRegsIntcStb ;
wire WbRegsDmacCyc ;
wire WbRegsDmacStb ;
wire WbRegsBiosCyc ;
wire WbRegsBiosStb ;
wire WbRegsMdecCyc ;
wire WbRegsMdecStb ;
wire WbRegsMemCardStb ;
wire WbRegsMemCardCyc ;
wire WbRegsSpuCyc ;
wire WbRegsSpuStb ;
wire WbRegsCdromStb ;
wire WbRegsCdromCyc ;
wire WbRegsPadStb ;
wire WbRegsPadCyc ;
wire WbRegsRcntAck ;
wire WbRegsRcntStall ;
wire WbRegsRcntErr ;
wire [31:0] WbRegsRcntDatRd ;
wire WbRegsIntcAck ;
wire WbRegsIntcStall ;
wire WbRegsIntcErr ;
wire [31:0] WbRegsIntcDatRd ;
wire WbRegsDmacAck ;
wire WbRegsDmacStall ;
wire WbRegsDmacErr ;
wire [31:0] WbRegsDmacDatRd ;
wire WbRegsBiosAck ;
wire WbRegsBiosStall ;
wire WbRegsBiosErr ;
wire [31:0] WbRegsBiosDatRd ;
wire WbRegsMdecAck ;
wire WbRegsMdecStall ;
wire WbRegsMdecErr ;
wire [31:0] WbRegsMdecDatRd ;
wire WbRegsMemCardAck ;
wire WbRegsMemCardStall ;
wire WbRegsMemCardErr ;
wire [31:0] WbRegsMemCardDatRd ;
wire WbRegsSpuAck ;
wire WbRegsSpuStall ;
wire WbRegsSpuErr ;
wire [31:0] WbRegsSpuDatRd ;
wire WbRegsCdromAck ;
wire WbRegsCdromStall ;
wire WbRegsCdromErr ;
wire [31:0] WbRegsCdromDatRd ;
wire WbRegsPadAck ;
wire WbRegsPadStall ;
wire WbRegsPadErr ;
wire [31:0] WbRegsPadDatRd ;
assign WB_GPU_ADR_OUT = 32'h0000_0000;
assign WB_GPU_CYC_OUT = 1'b0;
assign WB_GPU_STB_OUT = 1'b0;
assign WB_GPU_WE_OUT = 1'b0;
assign WB_GPU_SEL_OUT = 4'd0;
assign WB_GPU_CTI_OUT = 3'd0;
assign WB_GPU_BTE_OUT = 2'd0;
assign WB_GPU_DAT_WR_OUT = 32'h0000_0000;
MIPS1_TOP mips1_top
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_ADR_OUT (WbMipsAdr ),
.WB_CYC_OUT (WbMipsCyc ),
.WB_STB_OUT (WbMipsStb ),
.WB_WE_OUT (WbMipsWe ),
.WB_SEL_OUT (WbMipsSel ),
.WB_CTI_OUT (WbMipsCti ),
.WB_BTE_OUT (WbMipsBte ),
.WB_ACK_IN (WbMipsAck ),
.WB_STALL_IN (WbMipsStall ),
.WB_ERR_IN (WbMipsErr ),
.WB_DAT_RD_IN (WbMipsDatRd ),
.WB_DAT_WR_OUT (WbMipsDatWr ),
.HW_IRQ_IN ({5'd0, MipsHwInt})
);
DMAC_TOP dmac_top
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_DMAC_CYC_IN (WbRegsDmacCyc ),
.WB_REGS_DMAC_STB_IN (WbRegsDmacStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_DMAC_ACK_OUT (WbRegsDmacAck ),
.WB_REGS_DMAC_STALL_OUT (WbRegsDmacStall ),
.WB_REGS_DMAC_ERR_OUT (WbRegsDmacErr ),
.WB_REGS_DMAC_DAT_RD_OUT (WbRegsDmacDatRd ),
.WB_REGS_DAT_WR_IN (WbRegsDatWr ),
.WB_ADR_OUT (WbDmacAdr ),
.WB_CYC_OUT (WbDmacCyc ),
.WB_STB_OUT (WbDmacStb ),
.WB_WE_OUT (WbDmacWe ),
.WB_SEL_OUT (WbDmacSel ),
.WB_CTI_OUT (WbDmacCti ),
.WB_BTE_OUT (WbDmacBte ),
.WB_ACK_IN (WbDmacAck ),
.WB_STALL_IN (WbDmacStall ),
.WB_ERR_IN (WbDmacErr ),
.WB_DAT_RD_IN (WbDmacDatRd ),
.WB_DAT_WR_OUT (WbDmacDatWr ),
.DMAC_REQ_IN (DmacReq ),
.DMAC_ACK_OUT (DmacAck ),
.DMAC_IRQ_OUT (DmacIrq )
);
ROOT_CNT root_cnt
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_RCNT_CYC_IN (WbRegsRcntCyc ),
.WB_REGS_RCNT_STB_IN (WbRegsRcntStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_RCNT_ACK_OUT (WbRegsRcntAck ),
.WB_REGS_RCNT_STALL_OUT (WbRegsRcntStall ),
.WB_REGS_RCNT_ERR_OUT (WbRegsRcntErr ),
.WB_REGS_RCNT_DAT_RD_OUT (WbRegsRcntDatRd ),
.WB_REGS_DAT_WR_IN (WbRegsDatWr ),
.WB_VS_STB_IN (WbVsStb ),
.WB_HS_STB_IN (WbHsStb ),
.WB_ACTIVE_ROW_IN (WbActiveRow ),
.WB_ACTIVE_COL_IN (WbActiveCol ),
.RCNT_IRQ_OUT (RcntIrq )
);
INTC intc
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_INTC_CYC_IN (WbRegsIntcCyc ),
.WB_INTC_STB_IN (WbRegsIntcStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_INTC_ACK_OUT (WbRegsIntcAck ),
.WB_INTC_STALL_OUT (WbRegsIntcStall ),
.WB_INTC_ERR_OUT (WbRegsIntcErr ),
.WB_INTC_DAT_RD_OUT (WbRegsIntcDatRd ),
.WB_REGS_DAT_WR_IN (WbRegsDatWr ),
.INT_SOURCE_IN (IntSource ),
.MIPS_HW_INT_OUT (MipsHwInt )
);
PSX_BUS psx_bus
(
.CLK_SYS (CLK ),
.EN_SYS (EN ),
.RST_SYNC_SYS (RST_SYNC ),
.RST_ASYNC_SYS (RST_ASYNC ),
.CLK_REGS (CLK ),
.EN_REGS (EN ),
.RST_SYNC_REGS (RST_SYNC ),
.RST_ASYNC_REGS (RST_ASYNC ),
.WB_MIPS_ADR_IN (WbMipsAdr ),
.WB_MIPS_CYC_IN (WbMipsCyc ),
.WB_MIPS_STB_IN (WbMipsStb ),
.WB_MIPS_WE_IN (WbMipsWe ),
.WB_MIPS_SEL_IN (WbMipsSel ),
.WB_MIPS_CTI_IN (WbMipsCti ),
.WB_MIPS_BTE_IN (WbMipsBte ),
.WB_MIPS_STALL_OUT (WbMipsStall ),
.WB_MIPS_ACK_OUT (WbMipsAck ),
.WB_MIPS_ERR_OUT (WbMipsErr ),
.WB_MIPS_RD_DAT_OUT (WbMipsDatRd ),
.WB_MIPS_WR_DAT_IN (WbMipsDatWr ),
.WB_DMAC_ADR_IN (WbDmacAdr ),
.WB_DMAC_CYC_IN (WbDmacCyc ),
.WB_DMAC_STB_IN (WbDmacStb ),
.WB_DMAC_WE_IN (WbDmacWe ),
.WB_DMAC_SEL_IN (WbDmacSel ),
.WB_DMAC_CTI_IN (WbDmacCti ),
.WB_DMAC_BTE_IN (WbDmacBte ),
.WB_DMAC_STALL_OUT (WbDmacStall ),
.WB_DMAC_ACK_OUT (WbDmacAck ),
.WB_DMAC_ERR_OUT (WbDmacErr ),
.WB_DMAC_RD_DAT_OUT (WbDmacDatRd ),
.WB_DMAC_WR_DAT_IN (WbDmacDatWr ),
.WB_SYS_ADR_OUT (WB_SYS_ADR_OUT ),
.WB_SYS_WE_OUT (WB_SYS_WE_OUT ),
.WB_SYS_SEL_OUT (WB_SYS_SEL_OUT ),
.WB_SYS_CTI_OUT (WB_SYS_CTI_OUT ),
.WB_SYS_BTE_OUT (WB_SYS_BTE_OUT ),
.WB_SYS_DAT_WR_OUT (WB_SYS_DAT_WR_OUT ),
.WB_SYS_ROM_CYC_OUT (WB_SYS_ROM_CYC_OUT ),
.WB_SYS_ROM_STB_OUT (WB_SYS_ROM_STB_OUT ),
.WB_SYS_DRAM_CYC_OUT (WB_SYS_DRAM_CYC_OUT ),
.WB_SYS_DRAM_STB_OUT (WB_SYS_DRAM_STB_OUT ),
.WB_SYS_GPU_CYC_OUT (WB_GPU_CYC_OUT ),
.WB_SYS_GPU_STB_OUT (WB_GPU_STB_OUT ),
.WB_SYS_ROM_ACK_IN (WB_SYS_ROM_ACK_IN ),
.WB_SYS_ROM_STALL_IN (WB_SYS_ROM_STALL_IN ),
.WB_SYS_ROM_ERR_IN (WB_SYS_ROM_ERR_IN ),
.WB_SYS_ROM_DAT_RD_IN (WB_SYS_DAT_ROM_RD_IN ),
.WB_SYS_DRAM_ACK_IN (WB_SYS_DRAM_ACK_IN ),
.WB_SYS_DRAM_STALL_IN (WB_SYS_DRAM_STALL_IN ),
.WB_SYS_DRAM_ERR_IN (WB_SYS_DRAM_ERR_IN ),
.WB_SYS_DRAM_DAT_RD_IN (WB_SYS_DAT_DRAM_RD_IN ),
.WB_SYS_GPU_ACK_IN (WB_GPU_ACK_IN ),
.WB_SYS_GPU_STALL_IN (WB_GPU_STALL_IN ),
.WB_SYS_GPU_ERR_IN (WB_GPU_ERR_IN ),
.WB_SYS_GPU_DAT_RD_IN (WB_GPU_DAT_RD_IN ),
.WB_REGS_ADR_OUT (WbRegsAdr ),
.WB_REGS_WE_OUT (WbRegsWe ),
.WB_REGS_SEL_OUT (WbRegsSel ),
.WB_REGS_DAT_WR_OUT (WbRegsDatWr ),
.WB_REGS_RCNT_CYC_OUT (WbRegsRcntCyc ),
.WB_REGS_RCNT_STB_OUT (WbRegsRcntStb ),
.WB_REGS_INTC_CYC_OUT (WbRegsIntcCyc ),
.WB_REGS_INTC_STB_OUT (WbRegsIntcStb ),
.WB_REGS_DMAC_CYC_OUT (WbRegsDmacCyc ),
.WB_REGS_DMAC_STB_OUT (WbRegsDmacStb ),
.WB_REGS_BIOS_CYC_OUT (WbRegsBiosCyc ),
.WB_REGS_BIOS_STB_OUT (WbRegsBiosStb ),
.WB_REGS_MDEC_CYC_OUT (WbRegsMdecCyc ),
.WB_REGS_MDEC_STB_OUT (WbRegsMdecStb ),
.WB_REGS_MEMCARD_CYC_OUT (WbRegsMemCardStb ),
.WB_REGS_MEMCARD_STB_OUT (WbRegsMemCardCyc ),
.WB_REGS_SPU_CYC_OUT (WbRegsSpuCyc ),
.WB_REGS_SPU_STB_OUT (WbRegsSpuStb ),
.WB_REGS_CDROM_CYC_OUT (WbRegsCdromStb ),
.WB_REGS_CDROM_STB_OUT (WbRegsCdromCyc ),
.WB_REGS_PAD_CYC_OUT (WbRegsPadStb ),
.WB_REGS_PAD_STB_OUT (WbRegsPadCyc ),
.WB_REGS_RCNT_ACK_IN (WbRegsRcntAck ),
.WB_REGS_RCNT_STALL_IN (WbRegsRcntStall ),
.WB_REGS_RCNT_ERR_IN (WbRegsRcntErr ),
.WB_REGS_RCNT_DAT_RD_IN (WbRegsRcntDatRd ),
.WB_REGS_INTC_ACK_IN (WbRegsIntcAck ),
.WB_REGS_INTC_STALL_IN (WbRegsIntcStall ),
.WB_REGS_INTC_ERR_IN (WbRegsIntcErr ),
.WB_REGS_INTC_DAT_RD_IN (WbRegsIntcDatRd ),
.WB_REGS_DMAC_ACK_IN (WbRegsDmacAck ),
.WB_REGS_DMAC_STALL_IN (WbRegsDmacStall ),
.WB_REGS_DMAC_ERR_IN (WbRegsDmacErr ),
.WB_REGS_DMAC_DAT_RD_IN (WbRegsDmacDatRd ),
.WB_REGS_BIOS_ACK_IN (WbRegsBiosAck ),
.WB_REGS_BIOS_STALL_IN (WbRegsBiosStall ),
.WB_REGS_BIOS_ERR_IN (WbRegsBiosErr ),
.WB_REGS_BIOS_DAT_RD_IN (WbRegsBiosDatRd ),
.WB_REGS_MDEC_ACK_IN (WbRegsMdecAck ),
.WB_REGS_MDEC_STALL_IN (WbRegsMdecStall ),
.WB_REGS_MDEC_ERR_IN (WbRegsMdecErr ),
.WB_REGS_MDEC_DAT_RD_IN (WbRegsMdecDatRd ),
.WB_REGS_MEMCARD_ACK_IN (WbRegsMemCardAck ),
.WB_REGS_MEMCARD_STALL_IN (WbRegsMemCardStall ),
.WB_REGS_MEMCARD_ERR_IN (WbRegsMemCardErr ),
.WB_REGS_MEMCARD_DAT_RD_IN (WbRegsMemCardDatRd ),
.WB_REGS_SPU_ACK_IN (WbRegsSpuAck ),
.WB_REGS_SPU_STALL_IN (WbRegsSpuStall ),
.WB_REGS_SPU_ERR_IN (WbRegsSpuErr ),
.WB_REGS_SPU_DAT_RD_IN (WbRegsSpuDatRd ),
.WB_REGS_CDROM_ACK_IN (WbRegsCdromAck ),
.WB_REGS_CDROM_STALL_IN (WbRegsCdromStall ),
.WB_REGS_CDROM_ERR_IN (WbRegsCdromErr ),
.WB_REGS_CDROM_DAT_RD_IN (WbRegsCdromDatRd ),
.WB_REGS_PAD_ACK_IN (WbRegsPadAck ),
.WB_REGS_PAD_STALL_IN (WbRegsPadStall ),
.WB_REGS_PAD_ERR_IN (WbRegsPadErr ),
.WB_REGS_PAD_DAT_RD_IN (WbRegsPadDatRd )
);
assign WbRegsBiosDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_bios
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsBiosCyc ),
.WB_REGS_STB_IN (WbRegsBiosStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsBiosAck ),
.WB_REGS_STALL_OUT (WbRegsBiosStall ),
.WB_REGS_ERR_OUT (WbRegsBiosErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsMdecDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_mdec
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsMdecCyc ),
.WB_REGS_STB_IN (WbRegsMdecStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsMdecAck ),
.WB_REGS_STALL_OUT (WbRegsMdecStall ),
.WB_REGS_ERR_OUT (WbRegsMdecErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsMemCardDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_memcard
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsMemCardCyc ),
.WB_REGS_STB_IN (WbRegsMemCardStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsMemCardAck ),
.WB_REGS_STALL_OUT (WbRegsMemCardStall ),
.WB_REGS_ERR_OUT (WbRegsMemCardErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsSpuDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_spu
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsSpuCyc ),
.WB_REGS_STB_IN (WbRegsSpuStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsSpuAck ),
.WB_REGS_STALL_OUT (WbRegsSpuStall ),
.WB_REGS_ERR_OUT (WbRegsSpuErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsCdromDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_cdrom
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsCdromCyc ),
.WB_REGS_STB_IN (WbRegsCdromStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsCdromAck ),
.WB_REGS_STALL_OUT (WbRegsCdromStall ),
.WB_REGS_ERR_OUT (WbRegsCdromErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsPadDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_pad
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsPadCyc ),
.WB_REGS_STB_IN (WbRegsPadStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsPadAck ),
.WB_REGS_STALL_OUT (WbRegsPadStall ),
.WB_REGS_ERR_OUT (WbRegsPadErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
endmodule | module PSX_TOP
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output [31:0] WB_SYS_ADR_OUT ,
output WB_SYS_ROM_CYC_OUT ,
output WB_SYS_ROM_STB_OUT ,
output WB_SYS_DRAM_CYC_OUT ,
output WB_SYS_DRAM_STB_OUT ,
output WB_SYS_WE_OUT ,
output [ 3:0] WB_SYS_SEL_OUT ,
output [ 2:0] WB_SYS_CTI_OUT ,
output [ 1:0] WB_SYS_BTE_OUT ,
input WB_SYS_ROM_ACK_IN ,
input WB_SYS_ROM_STALL_IN ,
input WB_SYS_ROM_ERR_IN ,
input WB_SYS_DRAM_ACK_IN ,
input WB_SYS_DRAM_STALL_IN ,
input WB_SYS_DRAM_ERR_IN ,
input [31:0] WB_SYS_DAT_ROM_RD_IN ,
input [31:0] WB_SYS_DAT_DRAM_RD_IN ,
output [31:0] WB_SYS_DAT_WR_OUT ,
output [31:0] WB_GPU_ADR_OUT ,
output WB_GPU_CYC_OUT ,
output WB_GPU_STB_OUT ,
output WB_GPU_WE_OUT ,
output [ 3:0] WB_GPU_SEL_OUT ,
output [ 2:0] WB_GPU_CTI_OUT ,
output [ 1:0] WB_GPU_BTE_OUT ,
input WB_GPU_ACK_IN ,
input WB_GPU_STALL_IN ,
input WB_GPU_ERR_IN ,
input [31:0] WB_GPU_DAT_RD_IN ,
output [31:0] WB_GPU_DAT_WR_OUT
); |
wire [31:0] WbMipsAdr ;
wire WbMipsCyc ;
wire WbMipsStb ;
wire WbMipsWe ;
wire [ 3:0] WbMipsSel ;
wire [ 2:0] WbMipsCti ;
wire [ 1:0] WbMipsBte ;
wire WbMipsAck ;
wire WbMipsStall ;
wire WbMipsErr ;
wire [31:0] WbMipsDatRd ;
wire [31:0] WbMipsDatWr ;
wire [5:0] MipsTopHwIrq ;
wire WbVsStb ;
wire WbHsStb ;
wire WbActiveRow ;
wire WbActiveCol ;
wire [3:0] RcntIrq ;
wire [10:0] IntSource ;
wire MipsHwInt ;
wire [31:0] WbDmacAdr ;
wire WbDmacCyc ;
wire WbDmacStb ;
wire WbDmacWe ;
wire [ 3:0] WbDmacSel ;
wire [ 2:0] WbDmacCti ;
wire [ 1:0] WbDmacBte ;
wire WbDmacAck ;
wire WbDmacStall ;
wire WbDmacErr ;
wire [31:0] WbDmacDatRd ;
wire [31:0] WbDmacDatWr ;
wire [6:0] DmacReq = 7'b000_0000;
wire [6:0] DmacAck ;
wire DmacIrq ;
wire [31:0] WbSysAdr ;
wire WbSysCyc ;
wire WbSysStb ;
wire WbSysWe ;
wire [ 3:0] WbSysSel ;
wire [ 2:0] WbSysCti ;
wire [ 1:0] WbSysBte ;
wire [31:0] WbSysDatWr ;
wire WbSysRomCyc ;
wire WbSysRomStb ;
wire WbSysDramCyc ;
wire WbSysDramStb ;
wire WbSysGpuCyc ;
wire WbSysGpuStb ;
wire WbSysRomAck ;
wire WbSysRomStall ;
wire WbSysRomErr ;
wire [31:0] WbSysRomDatRd ;
wire WbSysDramAck ;
wire WbSysDramStall ;
wire WbSysDramErr ;
wire [31:0] WbSysDramDatRd ;
wire WbSysGpuAck ;
wire WbSysGpuStall ;
wire WbSysGpuErr ;
wire [31:0] WbSysGpuDatRd ;
wire [31:0] WbRegsAdr ;
wire WbRegsWe ;
wire [ 3:0] WbRegsSel ;
wire [31:0] WbRegsDatWr ;
wire WbRegsRcntCyc ;
wire WbRegsRcntStb ;
wire WbRegsIntcCyc ;
wire WbRegsIntcStb ;
wire WbRegsDmacCyc ;
wire WbRegsDmacStb ;
wire WbRegsBiosCyc ;
wire WbRegsBiosStb ;
wire WbRegsMdecCyc ;
wire WbRegsMdecStb ;
wire WbRegsMemCardStb ;
wire WbRegsMemCardCyc ;
wire WbRegsSpuCyc ;
wire WbRegsSpuStb ;
wire WbRegsCdromStb ;
wire WbRegsCdromCyc ;
wire WbRegsPadStb ;
wire WbRegsPadCyc ;
wire WbRegsRcntAck ;
wire WbRegsRcntStall ;
wire WbRegsRcntErr ;
wire [31:0] WbRegsRcntDatRd ;
wire WbRegsIntcAck ;
wire WbRegsIntcStall ;
wire WbRegsIntcErr ;
wire [31:0] WbRegsIntcDatRd ;
wire WbRegsDmacAck ;
wire WbRegsDmacStall ;
wire WbRegsDmacErr ;
wire [31:0] WbRegsDmacDatRd ;
wire WbRegsBiosAck ;
wire WbRegsBiosStall ;
wire WbRegsBiosErr ;
wire [31:0] WbRegsBiosDatRd ;
wire WbRegsMdecAck ;
wire WbRegsMdecStall ;
wire WbRegsMdecErr ;
wire [31:0] WbRegsMdecDatRd ;
wire WbRegsMemCardAck ;
wire WbRegsMemCardStall ;
wire WbRegsMemCardErr ;
wire [31:0] WbRegsMemCardDatRd ;
wire WbRegsSpuAck ;
wire WbRegsSpuStall ;
wire WbRegsSpuErr ;
wire [31:0] WbRegsSpuDatRd ;
wire WbRegsCdromAck ;
wire WbRegsCdromStall ;
wire WbRegsCdromErr ;
wire [31:0] WbRegsCdromDatRd ;
wire WbRegsPadAck ;
wire WbRegsPadStall ;
wire WbRegsPadErr ;
wire [31:0] WbRegsPadDatRd ;
assign WB_GPU_ADR_OUT = 32'h0000_0000;
assign WB_GPU_CYC_OUT = 1'b0;
assign WB_GPU_STB_OUT = 1'b0;
assign WB_GPU_WE_OUT = 1'b0;
assign WB_GPU_SEL_OUT = 4'd0;
assign WB_GPU_CTI_OUT = 3'd0;
assign WB_GPU_BTE_OUT = 2'd0;
assign WB_GPU_DAT_WR_OUT = 32'h0000_0000;
MIPS1_TOP mips1_top
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_ADR_OUT (WbMipsAdr ),
.WB_CYC_OUT (WbMipsCyc ),
.WB_STB_OUT (WbMipsStb ),
.WB_WE_OUT (WbMipsWe ),
.WB_SEL_OUT (WbMipsSel ),
.WB_CTI_OUT (WbMipsCti ),
.WB_BTE_OUT (WbMipsBte ),
.WB_ACK_IN (WbMipsAck ),
.WB_STALL_IN (WbMipsStall ),
.WB_ERR_IN (WbMipsErr ),
.WB_DAT_RD_IN (WbMipsDatRd ),
.WB_DAT_WR_OUT (WbMipsDatWr ),
.HW_IRQ_IN ({5'd0, MipsHwInt})
);
DMAC_TOP dmac_top
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_DMAC_CYC_IN (WbRegsDmacCyc ),
.WB_REGS_DMAC_STB_IN (WbRegsDmacStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_DMAC_ACK_OUT (WbRegsDmacAck ),
.WB_REGS_DMAC_STALL_OUT (WbRegsDmacStall ),
.WB_REGS_DMAC_ERR_OUT (WbRegsDmacErr ),
.WB_REGS_DMAC_DAT_RD_OUT (WbRegsDmacDatRd ),
.WB_REGS_DAT_WR_IN (WbRegsDatWr ),
.WB_ADR_OUT (WbDmacAdr ),
.WB_CYC_OUT (WbDmacCyc ),
.WB_STB_OUT (WbDmacStb ),
.WB_WE_OUT (WbDmacWe ),
.WB_SEL_OUT (WbDmacSel ),
.WB_CTI_OUT (WbDmacCti ),
.WB_BTE_OUT (WbDmacBte ),
.WB_ACK_IN (WbDmacAck ),
.WB_STALL_IN (WbDmacStall ),
.WB_ERR_IN (WbDmacErr ),
.WB_DAT_RD_IN (WbDmacDatRd ),
.WB_DAT_WR_OUT (WbDmacDatWr ),
.DMAC_REQ_IN (DmacReq ),
.DMAC_ACK_OUT (DmacAck ),
.DMAC_IRQ_OUT (DmacIrq )
);
ROOT_CNT root_cnt
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_RCNT_CYC_IN (WbRegsRcntCyc ),
.WB_REGS_RCNT_STB_IN (WbRegsRcntStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_RCNT_ACK_OUT (WbRegsRcntAck ),
.WB_REGS_RCNT_STALL_OUT (WbRegsRcntStall ),
.WB_REGS_RCNT_ERR_OUT (WbRegsRcntErr ),
.WB_REGS_RCNT_DAT_RD_OUT (WbRegsRcntDatRd ),
.WB_REGS_DAT_WR_IN (WbRegsDatWr ),
.WB_VS_STB_IN (WbVsStb ),
.WB_HS_STB_IN (WbHsStb ),
.WB_ACTIVE_ROW_IN (WbActiveRow ),
.WB_ACTIVE_COL_IN (WbActiveCol ),
.RCNT_IRQ_OUT (RcntIrq )
);
INTC intc
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_INTC_CYC_IN (WbRegsIntcCyc ),
.WB_INTC_STB_IN (WbRegsIntcStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_INTC_ACK_OUT (WbRegsIntcAck ),
.WB_INTC_STALL_OUT (WbRegsIntcStall ),
.WB_INTC_ERR_OUT (WbRegsIntcErr ),
.WB_INTC_DAT_RD_OUT (WbRegsIntcDatRd ),
.WB_REGS_DAT_WR_IN (WbRegsDatWr ),
.INT_SOURCE_IN (IntSource ),
.MIPS_HW_INT_OUT (MipsHwInt )
);
PSX_BUS psx_bus
(
.CLK_SYS (CLK ),
.EN_SYS (EN ),
.RST_SYNC_SYS (RST_SYNC ),
.RST_ASYNC_SYS (RST_ASYNC ),
.CLK_REGS (CLK ),
.EN_REGS (EN ),
.RST_SYNC_REGS (RST_SYNC ),
.RST_ASYNC_REGS (RST_ASYNC ),
.WB_MIPS_ADR_IN (WbMipsAdr ),
.WB_MIPS_CYC_IN (WbMipsCyc ),
.WB_MIPS_STB_IN (WbMipsStb ),
.WB_MIPS_WE_IN (WbMipsWe ),
.WB_MIPS_SEL_IN (WbMipsSel ),
.WB_MIPS_CTI_IN (WbMipsCti ),
.WB_MIPS_BTE_IN (WbMipsBte ),
.WB_MIPS_STALL_OUT (WbMipsStall ),
.WB_MIPS_ACK_OUT (WbMipsAck ),
.WB_MIPS_ERR_OUT (WbMipsErr ),
.WB_MIPS_RD_DAT_OUT (WbMipsDatRd ),
.WB_MIPS_WR_DAT_IN (WbMipsDatWr ),
.WB_DMAC_ADR_IN (WbDmacAdr ),
.WB_DMAC_CYC_IN (WbDmacCyc ),
.WB_DMAC_STB_IN (WbDmacStb ),
.WB_DMAC_WE_IN (WbDmacWe ),
.WB_DMAC_SEL_IN (WbDmacSel ),
.WB_DMAC_CTI_IN (WbDmacCti ),
.WB_DMAC_BTE_IN (WbDmacBte ),
.WB_DMAC_STALL_OUT (WbDmacStall ),
.WB_DMAC_ACK_OUT (WbDmacAck ),
.WB_DMAC_ERR_OUT (WbDmacErr ),
.WB_DMAC_RD_DAT_OUT (WbDmacDatRd ),
.WB_DMAC_WR_DAT_IN (WbDmacDatWr ),
.WB_SYS_ADR_OUT (WB_SYS_ADR_OUT ),
.WB_SYS_WE_OUT (WB_SYS_WE_OUT ),
.WB_SYS_SEL_OUT (WB_SYS_SEL_OUT ),
.WB_SYS_CTI_OUT (WB_SYS_CTI_OUT ),
.WB_SYS_BTE_OUT (WB_SYS_BTE_OUT ),
.WB_SYS_DAT_WR_OUT (WB_SYS_DAT_WR_OUT ),
.WB_SYS_ROM_CYC_OUT (WB_SYS_ROM_CYC_OUT ),
.WB_SYS_ROM_STB_OUT (WB_SYS_ROM_STB_OUT ),
.WB_SYS_DRAM_CYC_OUT (WB_SYS_DRAM_CYC_OUT ),
.WB_SYS_DRAM_STB_OUT (WB_SYS_DRAM_STB_OUT ),
.WB_SYS_GPU_CYC_OUT (WB_GPU_CYC_OUT ),
.WB_SYS_GPU_STB_OUT (WB_GPU_STB_OUT ),
.WB_SYS_ROM_ACK_IN (WB_SYS_ROM_ACK_IN ),
.WB_SYS_ROM_STALL_IN (WB_SYS_ROM_STALL_IN ),
.WB_SYS_ROM_ERR_IN (WB_SYS_ROM_ERR_IN ),
.WB_SYS_ROM_DAT_RD_IN (WB_SYS_DAT_ROM_RD_IN ),
.WB_SYS_DRAM_ACK_IN (WB_SYS_DRAM_ACK_IN ),
.WB_SYS_DRAM_STALL_IN (WB_SYS_DRAM_STALL_IN ),
.WB_SYS_DRAM_ERR_IN (WB_SYS_DRAM_ERR_IN ),
.WB_SYS_DRAM_DAT_RD_IN (WB_SYS_DAT_DRAM_RD_IN ),
.WB_SYS_GPU_ACK_IN (WB_GPU_ACK_IN ),
.WB_SYS_GPU_STALL_IN (WB_GPU_STALL_IN ),
.WB_SYS_GPU_ERR_IN (WB_GPU_ERR_IN ),
.WB_SYS_GPU_DAT_RD_IN (WB_GPU_DAT_RD_IN ),
.WB_REGS_ADR_OUT (WbRegsAdr ),
.WB_REGS_WE_OUT (WbRegsWe ),
.WB_REGS_SEL_OUT (WbRegsSel ),
.WB_REGS_DAT_WR_OUT (WbRegsDatWr ),
.WB_REGS_RCNT_CYC_OUT (WbRegsRcntCyc ),
.WB_REGS_RCNT_STB_OUT (WbRegsRcntStb ),
.WB_REGS_INTC_CYC_OUT (WbRegsIntcCyc ),
.WB_REGS_INTC_STB_OUT (WbRegsIntcStb ),
.WB_REGS_DMAC_CYC_OUT (WbRegsDmacCyc ),
.WB_REGS_DMAC_STB_OUT (WbRegsDmacStb ),
.WB_REGS_BIOS_CYC_OUT (WbRegsBiosCyc ),
.WB_REGS_BIOS_STB_OUT (WbRegsBiosStb ),
.WB_REGS_MDEC_CYC_OUT (WbRegsMdecCyc ),
.WB_REGS_MDEC_STB_OUT (WbRegsMdecStb ),
.WB_REGS_MEMCARD_CYC_OUT (WbRegsMemCardStb ),
.WB_REGS_MEMCARD_STB_OUT (WbRegsMemCardCyc ),
.WB_REGS_SPU_CYC_OUT (WbRegsSpuCyc ),
.WB_REGS_SPU_STB_OUT (WbRegsSpuStb ),
.WB_REGS_CDROM_CYC_OUT (WbRegsCdromStb ),
.WB_REGS_CDROM_STB_OUT (WbRegsCdromCyc ),
.WB_REGS_PAD_CYC_OUT (WbRegsPadStb ),
.WB_REGS_PAD_STB_OUT (WbRegsPadCyc ),
.WB_REGS_RCNT_ACK_IN (WbRegsRcntAck ),
.WB_REGS_RCNT_STALL_IN (WbRegsRcntStall ),
.WB_REGS_RCNT_ERR_IN (WbRegsRcntErr ),
.WB_REGS_RCNT_DAT_RD_IN (WbRegsRcntDatRd ),
.WB_REGS_INTC_ACK_IN (WbRegsIntcAck ),
.WB_REGS_INTC_STALL_IN (WbRegsIntcStall ),
.WB_REGS_INTC_ERR_IN (WbRegsIntcErr ),
.WB_REGS_INTC_DAT_RD_IN (WbRegsIntcDatRd ),
.WB_REGS_DMAC_ACK_IN (WbRegsDmacAck ),
.WB_REGS_DMAC_STALL_IN (WbRegsDmacStall ),
.WB_REGS_DMAC_ERR_IN (WbRegsDmacErr ),
.WB_REGS_DMAC_DAT_RD_IN (WbRegsDmacDatRd ),
.WB_REGS_BIOS_ACK_IN (WbRegsBiosAck ),
.WB_REGS_BIOS_STALL_IN (WbRegsBiosStall ),
.WB_REGS_BIOS_ERR_IN (WbRegsBiosErr ),
.WB_REGS_BIOS_DAT_RD_IN (WbRegsBiosDatRd ),
.WB_REGS_MDEC_ACK_IN (WbRegsMdecAck ),
.WB_REGS_MDEC_STALL_IN (WbRegsMdecStall ),
.WB_REGS_MDEC_ERR_IN (WbRegsMdecErr ),
.WB_REGS_MDEC_DAT_RD_IN (WbRegsMdecDatRd ),
.WB_REGS_MEMCARD_ACK_IN (WbRegsMemCardAck ),
.WB_REGS_MEMCARD_STALL_IN (WbRegsMemCardStall ),
.WB_REGS_MEMCARD_ERR_IN (WbRegsMemCardErr ),
.WB_REGS_MEMCARD_DAT_RD_IN (WbRegsMemCardDatRd ),
.WB_REGS_SPU_ACK_IN (WbRegsSpuAck ),
.WB_REGS_SPU_STALL_IN (WbRegsSpuStall ),
.WB_REGS_SPU_ERR_IN (WbRegsSpuErr ),
.WB_REGS_SPU_DAT_RD_IN (WbRegsSpuDatRd ),
.WB_REGS_CDROM_ACK_IN (WbRegsCdromAck ),
.WB_REGS_CDROM_STALL_IN (WbRegsCdromStall ),
.WB_REGS_CDROM_ERR_IN (WbRegsCdromErr ),
.WB_REGS_CDROM_DAT_RD_IN (WbRegsCdromDatRd ),
.WB_REGS_PAD_ACK_IN (WbRegsPadAck ),
.WB_REGS_PAD_STALL_IN (WbRegsPadStall ),
.WB_REGS_PAD_ERR_IN (WbRegsPadErr ),
.WB_REGS_PAD_DAT_RD_IN (WbRegsPadDatRd )
);
assign WbRegsBiosDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_bios
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsBiosCyc ),
.WB_REGS_STB_IN (WbRegsBiosStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsBiosAck ),
.WB_REGS_STALL_OUT (WbRegsBiosStall ),
.WB_REGS_ERR_OUT (WbRegsBiosErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsMdecDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_mdec
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsMdecCyc ),
.WB_REGS_STB_IN (WbRegsMdecStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsMdecAck ),
.WB_REGS_STALL_OUT (WbRegsMdecStall ),
.WB_REGS_ERR_OUT (WbRegsMdecErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsMemCardDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_memcard
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsMemCardCyc ),
.WB_REGS_STB_IN (WbRegsMemCardStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsMemCardAck ),
.WB_REGS_STALL_OUT (WbRegsMemCardStall ),
.WB_REGS_ERR_OUT (WbRegsMemCardErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsSpuDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_spu
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsSpuCyc ),
.WB_REGS_STB_IN (WbRegsSpuStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsSpuAck ),
.WB_REGS_STALL_OUT (WbRegsSpuStall ),
.WB_REGS_ERR_OUT (WbRegsSpuErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsCdromDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_cdrom
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsCdromCyc ),
.WB_REGS_STB_IN (WbRegsCdromStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsCdromAck ),
.WB_REGS_STALL_OUT (WbRegsCdromStall ),
.WB_REGS_ERR_OUT (WbRegsCdromErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
assign WbRegsPadDatRd = 32'h0000_0000;
WB_SLAVE_CTRL
#(
.DEFAULT_SLAVE (1),
.DEFAULT_ERR (0)
)
wb_slave_ctrl_pad
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WbRegsAdr ),
.WB_REGS_CYC_IN (WbRegsPadCyc ),
.WB_REGS_STB_IN (WbRegsPadStb ),
.WB_REGS_WE_IN (WbRegsWe ),
.WB_REGS_SEL_IN (WbRegsSel ),
.WB_REGS_ACK_OUT (WbRegsPadAck ),
.WB_REGS_STALL_OUT (WbRegsPadStall ),
.WB_REGS_ERR_OUT (WbRegsPadErr ),
.WB_WRITE_ADDR_STB_OUT ( ),
.WB_READ_ADDR_STB_OUT ( ),
.WB_VALID_OUT ( )
);
endmodule | 1 |
138,378 | data/full_repos/permissive/83270534/psx_top/rtl/root_cnt.v | 83,270,534 | root_cnt.v | v | 524 | 115 | [] | [] | [] | [(3, 523)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/root_cnt.v:363: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'23\'h0\' generates 23 bits.\n : ... In instance ROOT_CNT\n RootCnt0Val <= 23\'h0000_00;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/root_cnt.v:367: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'23\'h0\' generates 23 bits.\n : ... In instance ROOT_CNT\n RootCnt0Val <= 23\'h0000_00;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/psx_top/rtl/root_cnt.v:371: Operator ADD expects 24 bits on the RHS, but RHS\'s VARREF \'Rcnt0IncVal\' generates 9 bits.\n : ... In instance ROOT_CNT\n RootCnt0Val <= RootCnt0Val + Rcnt0IncVal;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/rtl/root_cnt.v:495: Cannot find file containing module: \'WB_SLAVE_CTRL\'\n WB_SLAVE_CTRL \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/WB_SLAVE_CTRL\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/WB_SLAVE_CTRL.v\n data/full_repos/permissive/83270534/psx_top/rtl,data/full_repos/permissive/83270534/WB_SLAVE_CTRL.sv\n WB_SLAVE_CTRL\n WB_SLAVE_CTRL.v\n WB_SLAVE_CTRL.sv\n obj_dir/WB_SLAVE_CTRL\n obj_dir/WB_SLAVE_CTRL.v\n obj_dir/WB_SLAVE_CTRL.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 302,266 | module | module ROOT_CNT
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_REGS_RCNT_CYC_IN ,
input WB_REGS_RCNT_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_REGS_RCNT_ACK_OUT ,
output WB_REGS_RCNT_STALL_OUT ,
output WB_REGS_RCNT_ERR_OUT ,
output [31:0] WB_REGS_RCNT_DAT_RD_OUT ,
input [31:0] WB_REGS_DAT_WR_IN ,
input WB_VS_STB_IN,
input WB_HS_STB_IN,
input WB_ACTIVE_ROW_IN,
input WB_ACTIVE_COL_IN,
output [3:0] RCNT_IRQ_OUT
);
parameter [1:0] RCNT_COUNT = 2'b00;
parameter [1:0] RCNT_MODE = 2'b01;
parameter [1:0] RCNT_TARGET = 2'b10;
parameter RCNT_CNT_SEL_MSB = 5;
parameter RCNT_CNT_SEL_LSB = 4;
parameter RCNT_REG_SEL_MSB = 3;
parameter RCNT_REG_SEL_LSB = 2;
parameter RCNT_MODE_EN_BIT = 0;
parameter RCNT_MODE_TGT_BIT = 3;
parameter RCNT_MODE_IRQ1_BIT = 4;
parameter RCNT_MODE_IRQ2_BIT = 6;
parameter RCNT_MODE_SRC_BIT = 8;
parameter RCNT_MODE_DIV_BIT = 9;
parameter RCNT_TARGET_MSB = 15;
parameter RCNT_TARGET_LSB = 0;
parameter [8:0] VGA_DIV_WB_RATIO = 9'h0_C1;
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
reg WbAddrStbReg ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
wire [1:0] WbAddrCntSel ;
wire [1:0] WbAddrRegSel ;
reg [3:0] CfgDiv ;
reg [3:0] CfgSrc ;
reg [3:0] CfgIrq1 ;
reg [3:0] CfgIrq2 ;
reg [3:0] CfgTgt ;
reg [3:0] CfgEn ;
reg [15:0] CfgTarget0;
reg [15:0] CfgTarget1;
reg [15:0] CfgTarget2;
reg [31:0] WbReadDataMux ;
reg [31:0] WbReadDataMuxAlign ;
reg [31:0] WbReadDataMuxAlignReg ;
wire Rcnt0Clr;
wire Rcnt1Clr;
wire Rcnt2Clr;
wire Rcnt0Wrap;
wire Rcnt1Wrap;
wire Rcnt2Wrap;
wire Rcnt0Match;
wire Rcnt1Match;
wire Rcnt2Match;
wire PclkInc;
wire Rcnt0Inc;
wire [8:0] Rcnt0IncVal;
wire Rcnt1Inc;
reg [23:0] RootCnt0Val;
wire [15:0] RootCnt0ValInt;
wire [ 7:0] RootCnt0ValFrac;
reg [15:0] RootCnt1Val;
reg [15:0] RootCnt2Val;
reg [3:0] Div8CntVal;
wire Div8En;
wire Rcnt0Irq;
wire Rcnt1Irq;
wire Rcnt2Irq;
wire Rcnt3Irq;
reg Rcnt0IrqReg;
reg Rcnt1IrqReg;
reg Rcnt2IrqReg;
reg Rcnt3IrqReg;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign WbAddrCntSel = WB_REGS_ADR_IN[RCNT_CNT_SEL_MSB:RCNT_CNT_SEL_LSB];
assign WbAddrRegSel = WB_REGS_ADR_IN[RCNT_REG_SEL_MSB:RCNT_REG_SEL_LSB];
assign RootCnt0ValInt = RootCnt0Val[23:8];
assign RootCnt0ValFrac = RootCnt0Val[ 7:0];
assign PclkInc = WB_ACTIVE_ROW_IN & WB_ACTIVE_COL_IN;
assign Rcnt0Inc = CfgSrc[0] ? PclkInc : 1'b1;
assign Rcnt0IncVal = CfgSrc[0] ? VGA_DIV_WB_RATIO : 9'h100;
assign Rcnt1Inc = CfgSrc[1] ? WB_ACTIVE_ROW_IN & WB_HS_STB_IN : 1'b1;
assign Rcnt0Wrap = | RootCnt0ValInt;
assign Rcnt1Wrap = | RootCnt1Val;
assign Rcnt2Wrap = | RootCnt2Val;
assign Rcnt0Match = (RootCnt0ValInt == CfgTarget0);
assign Rcnt1Match = (RootCnt1Val == CfgTarget1);
assign Rcnt2Match = (RootCnt2Val == CfgTarget2);
assign Rcnt0Clr = CfgTgt[0] ? Rcnt0Match : Rcnt0Wrap;
assign Rcnt1Clr = CfgTgt[1] ? Rcnt1Match : Rcnt1Wrap;
assign Rcnt2Clr = CfgTgt[2] ? Rcnt2Match : Rcnt2Wrap;
assign Div8En = (4'd7 == Div8CntVal);
assign Rcnt0Irq = CfgEn[0] & Rcnt0Clr & CfgIrq1[0] & CfgIrq2[0];
assign Rcnt1Irq = CfgEn[1] & Rcnt1Clr & CfgIrq1[1] & CfgIrq2[1];
assign Rcnt2Irq = CfgEn[2] & Rcnt2Clr & CfgIrq1[2] & CfgIrq2[2];
assign Rcnt3Irq = CfgEn[3] & WB_VS_STB_IN & CfgIrq1[3] & CfgIrq2[3];
assign WB_REGS_RCNT_DAT_RD_OUT = WbReadDataMuxAlignReg;
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CONFIG_REG
if (RST_ASYNC)
begin
CfgDiv <= 4'h0;
CfgSrc <= 4'h0;
CfgIrq1 <= 4'h0;
CfgIrq2 <= 4'h0;
CfgTgt <= 4'h0;
CfgEn <= 4'h0;
end
else if (RST_SYNC)
begin
CfgDiv <= 4'h0;
CfgSrc <= 4'h0;
CfgIrq1 <= 4'h0;
CfgIrq2 <= 4'h0;
CfgTgt <= 4'h0;
CfgEn <= 4'h0;
end
else if (EN && WbWriteAddrStb && WbValid && (RCNT_MODE == WbAddrRegSel))
begin
if (WB_REGS_SEL_IN[0])
begin
CfgIrq1 [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_IRQ1_BIT ];
CfgIrq2 [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_IRQ2_BIT ];
CfgTgt [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_TGT_BIT ];
CfgEn [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_EN_BIT ];
end
if (WB_REGS_SEL_IN[1])
begin
CfgDiv [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_DIV_BIT ];
CfgSrc [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_SRC_BIT ];
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_TARGET_REG
if (RST_ASYNC)
begin
CfgTarget0 <= 16'h0000;
CfgTarget1 <= 16'h0000;
CfgTarget2 <= 16'h0000;
end
else if (RST_SYNC)
begin
CfgTarget0 <= 16'h0000;
CfgTarget1 <= 16'h0000;
CfgTarget2 <= 16'h0000;
end
else if (EN && WbWriteAddrStb && WbValid && (RCNT_TARGET == WbAddrRegSel))
begin
case (WbAddrCntSel)
2'd0 :
begin
if (WB_REGS_SEL_IN[0]) CfgTarget0[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgTarget0[15:8] <= WB_REGS_DAT_WR_IN[15:8];
end
2'd1 :
begin
if (WB_REGS_SEL_IN[0]) CfgTarget1[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgTarget1[15:8] <= WB_REGS_DAT_WR_IN[15:8];
end
2'd2 :
begin
if (WB_REGS_SEL_IN[0]) CfgTarget2[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgTarget2[15:8] <= WB_REGS_DAT_WR_IN[15:8];
end
endcase
end
end
always @*
begin : READ_DATA_MUX
WbReadDataMux = 32'h0000_0000;
case (WbAddrRegSel)
RCNT_COUNT :
begin
case (WbAddrCntSel)
2'd0 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = RootCnt0ValInt;
2'd1 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = RootCnt1Val;
2'd2 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = RootCnt2Val;
endcase
end
RCNT_MODE :
begin
WbReadDataMux[RCNT_MODE_EN_BIT ] = CfgDiv [WbAddrCntSel];
WbReadDataMux[RCNT_MODE_TGT_BIT ] = CfgSrc [WbAddrCntSel];
WbReadDataMux[RCNT_MODE_IRQ1_BIT ] = CfgIrq1[WbAddrCntSel];
WbReadDataMux[RCNT_MODE_IRQ2_BIT ] = CfgIrq2[WbAddrCntSel];
WbReadDataMux[RCNT_MODE_SRC_BIT ] = CfgTgt [WbAddrCntSel];
WbReadDataMux[RCNT_MODE_DIV_BIT ] = CfgEn [WbAddrCntSel];
end
RCNT_TARGET :
begin
case (WbAddrCntSel)
2'd0 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = CfgTarget0;
2'd1 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = CfgTarget1;
2'd2 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = CfgTarget2;
endcase
end
endcase
end
always @*
begin : READ_DATA_ALIGN
WbReadDataMuxAlign = 32'h0000_0000;
WbReadDataMuxAlign[ 7:0] = {8{WB_REGS_SEL_IN[0]}} & WbReadDataMux[ 7:0];
WbReadDataMuxAlign[15:8] = {8{WB_REGS_SEL_IN[1]}} & WbReadDataMux[15:8];
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_READ_DATA_REG
if (RST_ASYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (EN && WbReadAddrStb && WbValid)
begin
WbReadDataMuxAlignReg <= WbReadDataMuxAlign;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ROOT_CNT_0
if (RST_ASYNC)
begin
RootCnt0Val <= 23'h0000_00;
end
else if (RST_SYNC || Rcnt0Clr)
begin
RootCnt0Val <= 23'h0000_00;
end
else if (EN && CfgEn[0] && Rcnt0Inc)
begin
RootCnt0Val <= RootCnt0Val + Rcnt0IncVal;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ROOT_CNT_1
if (RST_ASYNC)
begin
RootCnt1Val <= 16'h0000;
end
else if (RST_SYNC || Rcnt1Clr)
begin
RootCnt1Val <= 16'h0000;
end
else if (EN && CfgEn[1] && Rcnt1Inc)
begin
RootCnt1Val <= RootCnt1Val + 16'd1;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ROOT_CNT_2
if (RST_ASYNC)
begin
RootCnt2Val <= 16'h0000;
end
else if (RST_SYNC || Rcnt2Clr)
begin
RootCnt2Val <= 16'h0000;
end
else if (EN && CfgEn[1])
begin
RootCnt2Val <= RootCnt2Val + 16'd1;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DIV8_CNT
if (RST_ASYNC)
begin
Div8CntVal <= 4'd0;
end
else if (RST_SYNC || !CfgDiv[2] || Div8En)
begin
Div8CntVal <= 4'd0;
end
else if (EN && CfgDiv[2])
begin
Div8CntVal <= Div8CntVal + 4'd1;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ0_REG
if (RST_ASYNC)
begin
Rcnt0IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt0IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt0IrqReg <= Rcnt0Irq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ1_REG
if (RST_ASYNC)
begin
Rcnt1IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt1IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt1IrqReg <= Rcnt1Irq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ2_REG
if (RST_ASYNC)
begin
Rcnt2IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt2IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt2IrqReg <= Rcnt2Irq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ3_REG
if (RST_ASYNC)
begin
Rcnt3IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt3IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt3IrqReg <= Rcnt3Irq;
end
end
WB_SLAVE_CTRL
#(.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 1)
)
wb_slave_ctrl
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WB_REGS_ADR_IN ),
.WB_REGS_CYC_IN (WB_REGS_RCNT_CYC_IN ),
.WB_REGS_STB_IN (WB_REGS_RCNT_STB_IN ),
.WB_REGS_WE_IN (WB_REGS_WE_IN ),
.WB_REGS_SEL_IN (WB_REGS_SEL_IN ),
.WB_REGS_ACK_OUT (WB_REGS_RCNT_ACK_OUT ),
.WB_REGS_STALL_OUT (WB_REGS_RCNT_STALL_OUT ),
.WB_REGS_ERR_OUT (WB_REGS_RCNT_ERR_OUT ),
.WB_WRITE_ADDR_STB_OUT (WbWriteAddrStb ),
.WB_READ_ADDR_STB_OUT (WbReadAddrStb ),
.WB_VALID_OUT (WbValid )
);
endmodule | module ROOT_CNT
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_REGS_RCNT_CYC_IN ,
input WB_REGS_RCNT_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_REGS_RCNT_ACK_OUT ,
output WB_REGS_RCNT_STALL_OUT ,
output WB_REGS_RCNT_ERR_OUT ,
output [31:0] WB_REGS_RCNT_DAT_RD_OUT ,
input [31:0] WB_REGS_DAT_WR_IN ,
input WB_VS_STB_IN,
input WB_HS_STB_IN,
input WB_ACTIVE_ROW_IN,
input WB_ACTIVE_COL_IN,
output [3:0] RCNT_IRQ_OUT
); |
parameter [1:0] RCNT_COUNT = 2'b00;
parameter [1:0] RCNT_MODE = 2'b01;
parameter [1:0] RCNT_TARGET = 2'b10;
parameter RCNT_CNT_SEL_MSB = 5;
parameter RCNT_CNT_SEL_LSB = 4;
parameter RCNT_REG_SEL_MSB = 3;
parameter RCNT_REG_SEL_LSB = 2;
parameter RCNT_MODE_EN_BIT = 0;
parameter RCNT_MODE_TGT_BIT = 3;
parameter RCNT_MODE_IRQ1_BIT = 4;
parameter RCNT_MODE_IRQ2_BIT = 6;
parameter RCNT_MODE_SRC_BIT = 8;
parameter RCNT_MODE_DIV_BIT = 9;
parameter RCNT_TARGET_MSB = 15;
parameter RCNT_TARGET_LSB = 0;
parameter [8:0] VGA_DIV_WB_RATIO = 9'h0_C1;
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
reg WbAddrStbReg ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
wire [1:0] WbAddrCntSel ;
wire [1:0] WbAddrRegSel ;
reg [3:0] CfgDiv ;
reg [3:0] CfgSrc ;
reg [3:0] CfgIrq1 ;
reg [3:0] CfgIrq2 ;
reg [3:0] CfgTgt ;
reg [3:0] CfgEn ;
reg [15:0] CfgTarget0;
reg [15:0] CfgTarget1;
reg [15:0] CfgTarget2;
reg [31:0] WbReadDataMux ;
reg [31:0] WbReadDataMuxAlign ;
reg [31:0] WbReadDataMuxAlignReg ;
wire Rcnt0Clr;
wire Rcnt1Clr;
wire Rcnt2Clr;
wire Rcnt0Wrap;
wire Rcnt1Wrap;
wire Rcnt2Wrap;
wire Rcnt0Match;
wire Rcnt1Match;
wire Rcnt2Match;
wire PclkInc;
wire Rcnt0Inc;
wire [8:0] Rcnt0IncVal;
wire Rcnt1Inc;
reg [23:0] RootCnt0Val;
wire [15:0] RootCnt0ValInt;
wire [ 7:0] RootCnt0ValFrac;
reg [15:0] RootCnt1Val;
reg [15:0] RootCnt2Val;
reg [3:0] Div8CntVal;
wire Div8En;
wire Rcnt0Irq;
wire Rcnt1Irq;
wire Rcnt2Irq;
wire Rcnt3Irq;
reg Rcnt0IrqReg;
reg Rcnt1IrqReg;
reg Rcnt2IrqReg;
reg Rcnt3IrqReg;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign WbAddrCntSel = WB_REGS_ADR_IN[RCNT_CNT_SEL_MSB:RCNT_CNT_SEL_LSB];
assign WbAddrRegSel = WB_REGS_ADR_IN[RCNT_REG_SEL_MSB:RCNT_REG_SEL_LSB];
assign RootCnt0ValInt = RootCnt0Val[23:8];
assign RootCnt0ValFrac = RootCnt0Val[ 7:0];
assign PclkInc = WB_ACTIVE_ROW_IN & WB_ACTIVE_COL_IN;
assign Rcnt0Inc = CfgSrc[0] ? PclkInc : 1'b1;
assign Rcnt0IncVal = CfgSrc[0] ? VGA_DIV_WB_RATIO : 9'h100;
assign Rcnt1Inc = CfgSrc[1] ? WB_ACTIVE_ROW_IN & WB_HS_STB_IN : 1'b1;
assign Rcnt0Wrap = | RootCnt0ValInt;
assign Rcnt1Wrap = | RootCnt1Val;
assign Rcnt2Wrap = | RootCnt2Val;
assign Rcnt0Match = (RootCnt0ValInt == CfgTarget0);
assign Rcnt1Match = (RootCnt1Val == CfgTarget1);
assign Rcnt2Match = (RootCnt2Val == CfgTarget2);
assign Rcnt0Clr = CfgTgt[0] ? Rcnt0Match : Rcnt0Wrap;
assign Rcnt1Clr = CfgTgt[1] ? Rcnt1Match : Rcnt1Wrap;
assign Rcnt2Clr = CfgTgt[2] ? Rcnt2Match : Rcnt2Wrap;
assign Div8En = (4'd7 == Div8CntVal);
assign Rcnt0Irq = CfgEn[0] & Rcnt0Clr & CfgIrq1[0] & CfgIrq2[0];
assign Rcnt1Irq = CfgEn[1] & Rcnt1Clr & CfgIrq1[1] & CfgIrq2[1];
assign Rcnt2Irq = CfgEn[2] & Rcnt2Clr & CfgIrq1[2] & CfgIrq2[2];
assign Rcnt3Irq = CfgEn[3] & WB_VS_STB_IN & CfgIrq1[3] & CfgIrq2[3];
assign WB_REGS_RCNT_DAT_RD_OUT = WbReadDataMuxAlignReg;
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CONFIG_REG
if (RST_ASYNC)
begin
CfgDiv <= 4'h0;
CfgSrc <= 4'h0;
CfgIrq1 <= 4'h0;
CfgIrq2 <= 4'h0;
CfgTgt <= 4'h0;
CfgEn <= 4'h0;
end
else if (RST_SYNC)
begin
CfgDiv <= 4'h0;
CfgSrc <= 4'h0;
CfgIrq1 <= 4'h0;
CfgIrq2 <= 4'h0;
CfgTgt <= 4'h0;
CfgEn <= 4'h0;
end
else if (EN && WbWriteAddrStb && WbValid && (RCNT_MODE == WbAddrRegSel))
begin
if (WB_REGS_SEL_IN[0])
begin
CfgIrq1 [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_IRQ1_BIT ];
CfgIrq2 [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_IRQ2_BIT ];
CfgTgt [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_TGT_BIT ];
CfgEn [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_EN_BIT ];
end
if (WB_REGS_SEL_IN[1])
begin
CfgDiv [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_DIV_BIT ];
CfgSrc [WbAddrCntSel] <= WB_REGS_DAT_WR_IN[RCNT_MODE_SRC_BIT ];
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_TARGET_REG
if (RST_ASYNC)
begin
CfgTarget0 <= 16'h0000;
CfgTarget1 <= 16'h0000;
CfgTarget2 <= 16'h0000;
end
else if (RST_SYNC)
begin
CfgTarget0 <= 16'h0000;
CfgTarget1 <= 16'h0000;
CfgTarget2 <= 16'h0000;
end
else if (EN && WbWriteAddrStb && WbValid && (RCNT_TARGET == WbAddrRegSel))
begin
case (WbAddrCntSel)
2'd0 :
begin
if (WB_REGS_SEL_IN[0]) CfgTarget0[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgTarget0[15:8] <= WB_REGS_DAT_WR_IN[15:8];
end
2'd1 :
begin
if (WB_REGS_SEL_IN[0]) CfgTarget1[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgTarget1[15:8] <= WB_REGS_DAT_WR_IN[15:8];
end
2'd2 :
begin
if (WB_REGS_SEL_IN[0]) CfgTarget2[ 7:0] <= WB_REGS_DAT_WR_IN[ 7:0];
if (WB_REGS_SEL_IN[1]) CfgTarget2[15:8] <= WB_REGS_DAT_WR_IN[15:8];
end
endcase
end
end
always @*
begin : READ_DATA_MUX
WbReadDataMux = 32'h0000_0000;
case (WbAddrRegSel)
RCNT_COUNT :
begin
case (WbAddrCntSel)
2'd0 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = RootCnt0ValInt;
2'd1 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = RootCnt1Val;
2'd2 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = RootCnt2Val;
endcase
end
RCNT_MODE :
begin
WbReadDataMux[RCNT_MODE_EN_BIT ] = CfgDiv [WbAddrCntSel];
WbReadDataMux[RCNT_MODE_TGT_BIT ] = CfgSrc [WbAddrCntSel];
WbReadDataMux[RCNT_MODE_IRQ1_BIT ] = CfgIrq1[WbAddrCntSel];
WbReadDataMux[RCNT_MODE_IRQ2_BIT ] = CfgIrq2[WbAddrCntSel];
WbReadDataMux[RCNT_MODE_SRC_BIT ] = CfgTgt [WbAddrCntSel];
WbReadDataMux[RCNT_MODE_DIV_BIT ] = CfgEn [WbAddrCntSel];
end
RCNT_TARGET :
begin
case (WbAddrCntSel)
2'd0 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = CfgTarget0;
2'd1 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = CfgTarget1;
2'd2 : WbReadDataMux[RCNT_TARGET_MSB:RCNT_TARGET_LSB] = CfgTarget2;
endcase
end
endcase
end
always @*
begin : READ_DATA_ALIGN
WbReadDataMuxAlign = 32'h0000_0000;
WbReadDataMuxAlign[ 7:0] = {8{WB_REGS_SEL_IN[0]}} & WbReadDataMux[ 7:0];
WbReadDataMuxAlign[15:8] = {8{WB_REGS_SEL_IN[1]}} & WbReadDataMux[15:8];
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_READ_DATA_REG
if (RST_ASYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
WbReadDataMuxAlignReg <= 32'h0000_0000;
end
else if (EN && WbReadAddrStb && WbValid)
begin
WbReadDataMuxAlignReg <= WbReadDataMuxAlign;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ROOT_CNT_0
if (RST_ASYNC)
begin
RootCnt0Val <= 23'h0000_00;
end
else if (RST_SYNC || Rcnt0Clr)
begin
RootCnt0Val <= 23'h0000_00;
end
else if (EN && CfgEn[0] && Rcnt0Inc)
begin
RootCnt0Val <= RootCnt0Val + Rcnt0IncVal;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ROOT_CNT_1
if (RST_ASYNC)
begin
RootCnt1Val <= 16'h0000;
end
else if (RST_SYNC || Rcnt1Clr)
begin
RootCnt1Val <= 16'h0000;
end
else if (EN && CfgEn[1] && Rcnt1Inc)
begin
RootCnt1Val <= RootCnt1Val + 16'd1;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ROOT_CNT_2
if (RST_ASYNC)
begin
RootCnt2Val <= 16'h0000;
end
else if (RST_SYNC || Rcnt2Clr)
begin
RootCnt2Val <= 16'h0000;
end
else if (EN && CfgEn[1])
begin
RootCnt2Val <= RootCnt2Val + 16'd1;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : DIV8_CNT
if (RST_ASYNC)
begin
Div8CntVal <= 4'd0;
end
else if (RST_SYNC || !CfgDiv[2] || Div8En)
begin
Div8CntVal <= 4'd0;
end
else if (EN && CfgDiv[2])
begin
Div8CntVal <= Div8CntVal + 4'd1;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ0_REG
if (RST_ASYNC)
begin
Rcnt0IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt0IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt0IrqReg <= Rcnt0Irq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ1_REG
if (RST_ASYNC)
begin
Rcnt1IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt1IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt1IrqReg <= Rcnt1Irq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ2_REG
if (RST_ASYNC)
begin
Rcnt2IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt2IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt2IrqReg <= Rcnt2Irq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RCNT_IRQ3_REG
if (RST_ASYNC)
begin
Rcnt3IrqReg <= 1'b0;
end
else if (RST_SYNC)
begin
Rcnt3IrqReg <= 1'b0;
end
else if (EN)
begin
Rcnt3IrqReg <= Rcnt3Irq;
end
end
WB_SLAVE_CTRL
#(.WB_ADDR_MSB (11),
.WB_ADDR_LSB ( 8),
.WB_ADDR_VAL ( 1)
)
wb_slave_ctrl
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_REGS_ADR_IN (WB_REGS_ADR_IN ),
.WB_REGS_CYC_IN (WB_REGS_RCNT_CYC_IN ),
.WB_REGS_STB_IN (WB_REGS_RCNT_STB_IN ),
.WB_REGS_WE_IN (WB_REGS_WE_IN ),
.WB_REGS_SEL_IN (WB_REGS_SEL_IN ),
.WB_REGS_ACK_OUT (WB_REGS_RCNT_ACK_OUT ),
.WB_REGS_STALL_OUT (WB_REGS_RCNT_STALL_OUT ),
.WB_REGS_ERR_OUT (WB_REGS_RCNT_ERR_OUT ),
.WB_WRITE_ADDR_STB_OUT (WbWriteAddrStb ),
.WB_READ_ADDR_STB_OUT (WbReadAddrStb ),
.WB_VALID_OUT (WbValid )
);
endmodule | 1 |
138,381 | data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v | 83,270,534 | mips1_core_monitor.v | v | 971 | 135 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:15: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:16: Cannot find include file: psx_top_defines.vh\n`include "psx_top_defines.vh" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:17: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:69: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport CPU_CORE_MONITOR_PKG::regWriteEvent;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:140: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, " ns", 6);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:151: syntax error, unexpected IDENTIFIER, expecting \')\'\n function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:166: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:173: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:206: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:213: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:232: syntax error, unexpected endfunction\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:246: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = 1 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:247: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = 32\'h0000_000f ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = Address ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:249: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = 0 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:251: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:258: syntax error, unexpected \'(\', expecting IDENTIFIER\n refInstM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:273: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = RdWrB ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:276: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = WrValue ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:286: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:290: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = Address;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:300: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:305: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b1100;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:314: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b0011;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:323: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:329: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b00 : DataAligned[ 7: 0] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:330: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b01 : DataAligned[15: 8] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:331: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b10 : DataAligned[23:16] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:332: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b11 : DataAligned[31:24] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:337: syntax error, unexpected $display\n default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:341: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = Sel ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:342: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = AddrAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = DataAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:345: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n refDataM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,274 | module | module MIPS1_CORE_MONITOR
#(parameter VERBOSE = 0)
();
`define TESTSTR "code.hex"
`include "tb_defines.v"
`include "psx_top_defines.vh"
`include "cpu_defs.v"
`define MON_CLK `CPU.CLK
`define MON_RST_SYNC `CPU.RST_SYNC
`define MON_CORE_INST_ADR `CPU.CORE_INST_ADR_OUT
`define MON_CORE_INST_CYC `CPU.CORE_INST_CYC_OUT
`define MON_CORE_INST_STB `CPU.CORE_INST_STB_OUT
`define MON_CORE_INST_WE `CPU.CORE_INST_WE_OUT
`define MON_CORE_INST_SEL `CPU.CORE_INST_SEL_OUT
`define MON_CORE_INST_CTI `CPU.CORE_INST_CTI_OUT
`define MON_CORE_INST_BTE `CPU.CORE_INST_BTE_OUT
`define MON_CORE_INST_ACK `CPU.CORE_INST_ACK_IN
`define MON_CORE_INST_STALL `CPU.CORE_INST_STALL_IN
`define MON_CORE_INST_ERR `CPU.CORE_INST_ERR_IN
`define MON_CORE_INST_DAT_RD `CPU.CORE_INST_DAT_RD_IN
`define MON_CORE_INST_DAT_WR `CPU.CORE_INST_DAT_WR_OUT
`define MON_CORE_DATA_ADR `CPU.CORE_DATA_ADR_OUT
`define MON_CORE_DATA_CYC `CPU.CORE_DATA_CYC_OUT
`define MON_CORE_DATA_STB `CPU.CORE_DATA_STB_OUT
`define MON_CORE_DATA_WE `CPU.CORE_DATA_WE_OUT
`define MON_CORE_DATA_SEL `CPU.CORE_DATA_SEL_OUT
`define MON_CORE_DATA_CTI `CPU.CORE_DATA_CTI_OUT
`define MON_CORE_DATA_BTE `CPU.CORE_DATA_BTE_OUT
`define MON_CORE_DATA_ACK `CPU.CORE_DATA_ACK_IN
`define MON_CORE_DATA_STALL `CPU.CORE_DATA_STALL_IN
`define MON_CORE_DATA_ERR `CPU.CORE_DATA_ERR_IN
`define MON_CORE_DATA_DAT_RD `CPU.CORE_DATA_DAT_RD_IN
`define MON_CORE_DATA_DAT_WR `CPU.CORE_DATA_DAT_WR_OUT
`define MON_STALL `CPU.Stall
`define MON_LO_VAL `CPU.LoVal
`define MON_HI_VAL `CPU.HiVal
`define MON_REG_WR `CPU.RegWriteWb
`define MON_REG_SEL `CPU.RegWrWb
`define MON_REG_WR_DATA `CPU.WriteDataWb
`define MON_MULT_REQ `CPU.MultReq
`define MON_MULT_ACK `CPU.MultAck
`define MON_DIV_REQ `CPU.DivReq
`define MON_DIV_ACK `CPU.DivAck
`define MON_MTHI `CPU.MthiMem
`define MON_MTLO `CPU.MtloMem
import CPU_CORE_MONITOR_PKG::regWriteEvent;
import CPU_CORE_MONITOR_PKG::wbM2SEvent;
import CPU_CORE_MONITOR_PKG::wbS2MEvent;
import "DPI-C" context function void helloWorld ();
import "DPI-C" context function void cpuInit ();
import "DPI-C" context function void cpuCycle(int pc, int opcode, int rd_data, int show_mode);
import "DPI-C" context function int cpuEnd ();
export "DPI-C" function refInstM2SPush ;
export "DPI-C" function refRegPush ;
export "DPI-C" function refDataM2SPush ;
export "DPI-C" function refLoHiPush ;
wbM2SEvent dutInstM2SQ[$];
wbS2MEvent dutInstS2MQ[$];
wbM2SEvent dutDataM2SQ[$];
wbS2MEvent dutDataS2MQ[$];
regWriteEvent dutRegQ[$];
int dutLoQ[$];
int dutHiQ[$];
wbM2SEvent refInstM2SQ[$];
wbS2MEvent refInstS2MQ[$];
wbM2SEvent refDataM2SQ[$];
wbS2MEvent refDataS2MQ[$];
regWriteEvent refRegQ[$];
int refLoQ[$];
int refHiQ[$];
int modelTraceActive;
wire WbCoreInstAddrStb = `MON_CORE_INST_CYC & `MON_CORE_INST_STB & ~`MON_CORE_INST_STALL;
wire WbCoreInstDataStb = `MON_CORE_INST_CYC & `MON_CORE_INST_ACK;
wire WbCoreDataAddrStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_STB & ~`MON_CORE_DATA_STALL;
wire WbCoreDataDataStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_ACK;
initial
begin
cpuInit();
if (VERBOSE > 0) $display("[INFO ] MIPS1 Core Monitor initialised at time %t", $time);
end
initial
begin
$timeformat(-9, 0, " ns", 6);
end
function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);
chkM2SData = 0;
if (wbM2SEventRef.RdWrB)
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
end
end
else
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address ) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB ) &&
(wbM2SEventRef.WrValue == wbM2SEventDut.WrValue )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
$display("[ERROR] -> Value Expected 0x%x, Actual 0x%x"
,wbM2SEventRef.WrValue
,wbM2SEventDut.WrValue );
end
end
endfunction
function void refInstM2SPush (int Address);
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = 1 ;
wbM2SEventLocal.Sel = 32'h0000_000f ;
wbM2SEventLocal.Address = Address ;
wbM2SEventLocal.WrValue = 0 ;
if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refInstM2SQ.push_front(wbM2SEventLocal);
endfunction
function void refDataM2SPush (int RdWrB, int Size, int Address, int WrValue);
logic [31:0] AddrAligned;
logic [ 3:0] Sel;
logic [31:0] DataAligned;
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = RdWrB ;
wbM2SEventLocal.WrValue = WrValue ;
DataAligned = 0;
case (Size)
4 :
begin
if (2'b00 != Address[1:0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = Address;
Sel = 4'b1111;
DataAligned = WrValue;
end
end
2 :
begin
if (1'b0 != Address[0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = {Address[31:2], 2'b00};
if (Address[1])
begin
Sel = 4'b1100;
DataAligned[31:16] = WrValue[15:0];
end
else
begin
Sel = 4'b0011;
DataAligned[15:0] = WrValue[15:0];
end
end
end
1 :
begin
AddrAligned = {Address[31:2], 2'b00};
Sel = 4'b0000;
Sel[Address[1:0]] = 1'b1;
case (Address[1:0])
2'b00 : DataAligned[ 7: 0] = WrValue[7:0];
2'b01 : DataAligned[15: 8] = WrValue[7:0];
2'b10 : DataAligned[23:16] = WrValue[7:0];
2'b11 : DataAligned[31:24] = WrValue[7:0];
endcase
end
default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);
endcase
wbM2SEventLocal.Sel = Sel ;
wbM2SEventLocal.Address = AddrAligned ;
wbM2SEventLocal.WrValue = DataAligned ;
if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refDataM2SQ.push_front(wbM2SEventLocal);
endfunction
function void refRegPush (input int regIndex, input int regValue);
regWriteEvent regWriteEventLocal;
regWriteEventLocal.regIndex = regIndex;
regWriteEventLocal.regValue = regValue;
if (VERBOSE) $display("[DEBUG] REF REG WR Push : Index = %2d, Data = 0x%x at time %t"
, regWriteEventLocal.regIndex
, regWriteEventLocal.regValue
, $time );
refRegQ.push_front(regWriteEventLocal);
endfunction
function void refLoHiPush (input int regIndex, input int regValue);
if (regIndex)
begin
if (VERBOSE) $display("[DEBUG] REF HI REG WR Push : Hi = 0x%x at time %t"
, regValue
, $time );
refHiQ.push_front(regValue);
end
else
begin
if (VERBOSE) $display("[DEBUG] REF LO REG WR Push : Lo = 0x%x at time %t"
, regValue
, $time );
refLoQ.push_front(regValue);
end
endfunction
always @(negedge `MON_CLK)
begin
wbM2SEvent wbM2SEventLocal;
if (WbCoreInstAddrStb)
begin
wbM2SEventLocal.RdWrB = (32'd1 === `MON_CORE_INST_WE) ? 0 : 1;
wbM2SEventLocal.Sel = {28'h000_0000, `MON_CORE_INST_SEL};
wbM2SEventLocal.Address = `MON_CORE_INST_ADR;
wbM2SEventLocal.WrValue = `MON_CORE_INST_DAT_WR;
assert (!$isunknown(`MON_CORE_INST_WE));
assert (!$isunknown(`MON_CORE_INST_SEL));
assert (!$isunknown(`MON_CORE_INST_ADR));
assert (!$isunknown(`MON_CORE_INST_DAT_WR));
if (VERBOSE) $display("[DEBUG] DUT INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
dutInstM2SQ.push_front(wbM2SEventLocal);
end
end
always @(negedge `MON_CLK)
begin
wbM2SEvent wbM2SEventLocal;
if (WbCoreDataAddrStb)
begin
wbM2SEventLocal.RdWrB = (32'd1 == `MON_CORE_DATA_WE) ? 0 : 1;
wbM2SEventLocal.Sel = {28'h000_0000, `MON_CORE_DATA_SEL};
wbM2SEventLocal.Address = `MON_CORE_DATA_ADR;
wbM2SEventLocal.WrValue = `MON_CORE_DATA_DAT_WR;
if (VERBOSE) $display("[DEBUG] DUT DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
dutDataM2SQ.push_front(wbM2SEventLocal);
end
end
always @(negedge `MON_CLK)
begin
wbS2MEvent wbS2MEventLocal;
if (WbCoreInstDataStb)
begin
wbS2MEventLocal.RdValue = `MON_CORE_INST_DAT_RD;
if (VERBOSE) $display("[DEBUG] DUT INST S2M Push : RdValue = 0x%x at time %t"
,wbS2MEventLocal.RdValue
, $time );
dutInstS2MQ.push_front(wbS2MEventLocal);
end
end
always @(negedge `MON_CLK)
begin
wbS2MEvent wbS2MEventLocal;
if (WbCoreDataDataStb)
begin
wbS2MEventLocal.RdValue = `MON_CORE_DATA_DAT_RD;
if (VERBOSE) $display("[DEBUG] DUT DATA S2M Push : RdValue = 0x%x at time %t"
,wbS2MEventLocal.RdValue
, $time );
dutDataS2MQ.push_front(wbS2MEventLocal);
end
end
always @(negedge `MON_CLK)
begin
regWriteEvent regWriteEventLocal;
if (`MON_REG_WR && !`MON_STALL)
begin
regWriteEventLocal.regIndex = `MON_REG_SEL;
regWriteEventLocal.regValue = `MON_REG_WR_DATA;
if (VERBOSE) $display("[DEBUG] DUT REG WR Push : Index = %2d, Data = 0x%x at time %t"
, regWriteEventLocal.regIndex
, regWriteEventLocal.regValue
, $time );
dutRegQ.push_front(regWriteEventLocal);
end
end
always @(negedge `MON_CLK)
begin
regWriteEvent regWriteEventLocal;
if ((`MON_MULT_REQ && `MON_MULT_ACK ) ||
(`MON_DIV_REQ && `MON_DIV_ACK ))
begin
if (VERBOSE) $display("[DEBUG] DUT LO REG WR Push : Lo = 0x%x at time %t"
, `MON_LO_VAL
, $time );
if (VERBOSE) $display("[DEBUG] DUT HI REG WR Push : Hi = 0x%x at time %t"
, `MON_HI_VAL
, $time );
dutLoQ.push_front(`MON_LO_VAL);
dutHiQ.push_front(`MON_HI_VAL);
end
if (`MON_MTHI && !`MON_STALL)
begin
if (VERBOSE) $display("[DEBUG] DUT HI REG WR Push : Hi = 0x%x at time %t"
, `MON_HI_VAL
, $time );
dutHiQ.push_front(`MON_HI_VAL);
end
if (`MON_MTLO && !`MON_STALL)
begin
if (VERBOSE) $display("[DEBUG] DUT LO REG WR Push : Lo = 0x%x at time %t"
, `MON_LO_VAL
, $time );
dutLoQ.push_front(`MON_LO_VAL);
end
end
initial
begin : CORE_INST_DATA_CHECK
regWriteEvent regWriteEventLocal;
wbM2SEvent wbM2SEventLocal;
wbS2MEvent wbS2MEventLocal;
wbM2SEvent refM2SDataEventLocal;
wbM2SEvent dutM2SDataEventLocal;
wbS2MEvent refS2MDataEventLocal;
wbS2MEvent dutS2MDataEventLocal;
wbM2SEvent refM2SInstEventLocal;
wbM2SEvent dutM2SInstEventLocal;
wbS2MEvent refS2MInstEventLocal;
wbS2MEvent dutS2MInstEventLocal;
int LoadInst;
int StoreInst;
logic [5:0] InstOpcode;
int RdData;
int instCount = 0;
wbM2SEventLocal.RdWrB = 1;
wbM2SEventLocal.Sel = 32'h0000_000f;
wbM2SEventLocal.Address = CPU_RST_VECTOR;
wbM2SEventLocal.WrValue = 0;
refInstM2SQ.push_front(wbM2SEventLocal);
regWriteEventLocal.regIndex = 0;
regWriteEventLocal.regValue = 0;
refRegQ.push_front(regWriteEventLocal);
modelTraceActive = 1;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while ((dutInstM2SQ.size() == 0) ||
(dutInstS2MQ.size() == 0))
@(posedge `MON_CLK);
if (VERBOSE) $display("[DEBUG] CPU WB Instruction ready at time %t", $time);
instCount++;
if (0 == (instCount % 10000))
begin
$display("[INFO ] Instruction %6d issued at time %t", instCount, $time);
end
dutM2SInstEventLocal = dutInstM2SQ.pop_back();
dutS2MInstEventLocal = dutInstS2MQ.pop_back();
InstOpcode = dutS2MInstEventLocal.RdValue[OPC_HI:OPC_LO];
if ((OPC_LB == InstOpcode) ||
(OPC_LH == InstOpcode) ||
(OPC_LW == InstOpcode) ||
(OPC_LBU == InstOpcode) ||
(OPC_LHU == InstOpcode)
)
begin
LoadInst = 1;
StoreInst = 0;
end
else if ((OPC_SB == InstOpcode) ||
(OPC_SH == InstOpcode) ||
(OPC_SW == InstOpcode)
)
begin
LoadInst = 0;
StoreInst = 1;
end
else if ((OPC_LWL == InstOpcode) ||
(OPC_LBU == InstOpcode) ||
(OPC_LHU == InstOpcode) ||
(OPC_LWR == InstOpcode) ||
(OPC_SWL == InstOpcode) ||
(OPC_SWR == InstOpcode) ||
(OPC_LWC0 == InstOpcode) ||
(OPC_LWC1 == InstOpcode) ||
(OPC_LWC2 == InstOpcode) ||
(OPC_LWC3 == InstOpcode) ||
(OPC_SWC0 == InstOpcode) ||
(OPC_SWC1 == InstOpcode) ||
(OPC_SWC2 == InstOpcode) ||
(OPC_SWC3 == InstOpcode)
)
begin
LoadInst = 0;
StoreInst = 0;
$display("[ERROR] Unsupported Load or Store (0x%x) found at time %t",
InstOpcode,
$time);
end
else
begin
LoadInst = 0;
StoreInst = 0;
end
if (LoadInst)
begin
if (VERBOSE) $display("[DEBUG] Load instruction (OPC = 0x%x) detected at time %t",
InstOpcode,
$time);
if (VERBOSE) $display("[DEBUG] Waiting for DUT Data M2S and S2M at time %t", $time);
while ((0 == dutDataM2SQ.size()) || (0 == dutDataS2MQ.size()))
@(posedge `MON_CLK);
if (VERBOSE) $display("[DEBUG] DUT Data M2S and S2M ready at time %t", $time);
dutM2SDataEventLocal = dutDataM2SQ.pop_back();
dutS2MDataEventLocal = dutDataS2MQ.pop_back();
RdData = 0;
case(dutM2SDataEventLocal.Sel)
4'b1111 : RdData = dutS2MDataEventLocal.RdValue;
4'h1100 : RdData = {16'd0, dutS2MDataEventLocal.RdValue[31:16]};
4'b0011 : RdData = {16'd0, dutS2MDataEventLocal.RdValue[15: 0]};
4'b1000 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[31:24]};
4'b0100 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[23:16]};
4'b0010 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[15: 8]};
4'b0001 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[ 7: 0]};
endcase
if (VERBOSE) $display("[INFO ] C Model call. PC = 0x%x, Inst = 0x%x at time %t",
dutM2SInstEventLocal.Address,
dutS2MInstEventLocal.RdValue,
$time);
cpuCycle(dutM2SInstEventLocal.Address ,
dutS2MInstEventLocal.RdValue ,
RdData,
VERBOSE);
end
else if (StoreInst)
begin
if (VERBOSE) $display("[DEBUG] Store instruction (OPC = 0x%x) detected at time %t",
InstOpcode,
$time);
while ((0 == dutDataM2SQ.size()) || (0 == dutDataS2MQ.size()))
@(posedge `MON_CLK);
if (VERBOSE) $display("[DEBUG] DUT Data M2S and S2M ready at time %t", $time);
dutM2SDataEventLocal = dutDataM2SQ.pop_back();
dutS2MDataEventLocal = dutDataS2MQ.pop_back();
if (VERBOSE) $display("[INFO ] C Model call. PC = 0x%x, Inst = 0x%x at time %t",
dutM2SInstEventLocal.Address,
dutS2MInstEventLocal.RdValue,
$time);
cpuCycle(dutM2SInstEventLocal.Address ,
dutS2MInstEventLocal.RdValue ,
0 ,
VERBOSE);
end
else
begin
if (VERBOSE) $display("[INFO ] C Model call. PC = 0x%x, Inst = 0x%x at time %t",
dutM2SInstEventLocal.Address,
dutS2MInstEventLocal.RdValue,
$time);
cpuCycle(dutM2SInstEventLocal.Address ,
dutS2MInstEventLocal.RdValue ,
0 ,
VERBOSE);
end
if (StoreInst || LoadInst)
begin
refM2SDataEventLocal = refDataM2SQ.pop_back();
chkM2SData (refM2SDataEventLocal, dutM2SDataEventLocal, "Data",VERBOSE);
end
refM2SInstEventLocal = refInstM2SQ.pop_back();
chkM2SData (refM2SInstEventLocal, dutM2SInstEventLocal, "Inst",VERBOSE);
end
end
initial
begin : CORE_REG_CHECK
regWriteEvent refRegWriteEventLocal;
regWriteEvent dutRegWriteEventLocal;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while (refRegQ.size() == 0)
@(posedge `MON_CLK);
while (dutRegQ.size() == 0)
@(posedge `MON_CLK);
refRegWriteEventLocal = refRegQ.pop_back();
dutRegWriteEventLocal = dutRegQ.pop_back();
if (refRegWriteEventLocal == dutRegWriteEventLocal)
begin
if (VERBOSE > 0) $display("[INFO ] CPU REG Write Match at time %t", $time);
end
else
begin
$display("[ERROR] CPU REGS Write Mismatch at time %t", $time);
$display("[ERROR] -> regIndex Expected 0x%x, Actual 0x%x"
, refRegWriteEventLocal.regIndex
, dutRegWriteEventLocal.regIndex );
$display("[ERROR] -> regValue Expected 0x%x, Actual 0x%x"
, refRegWriteEventLocal.regValue
, dutRegWriteEventLocal.regValue );
end
end
end
initial
begin : CORE_LO_REG_CHECK
int refLoVal;
int dutLoVal;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while (refLoQ.size() == 0)
@(posedge `MON_CLK);
while (dutLoQ.size() == 0)
@(posedge `MON_CLK);
refLoVal = refLoQ.pop_back();
dutLoVal = dutLoQ.pop_back();
if (refLoVal == dutLoVal)
begin
$display("[INFO ] CPU LO REG Write Match at time %t", $time);
end
else
begin
$display("[ERROR] CPU LO REG Write Mismatch at time %t", $time);
if (VERBOSE) $display("[DEBUG] -> Expected 0x%x, Actual 0x%x"
, refLoVal
, dutLoVal );
end
end
end
initial
begin : CORE_HI_REG_CHECK
int refHiVal;
int dutHiVal;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while (refHiQ.size() == 0)
@(posedge `MON_CLK);
while (dutHiQ.size() == 0)
@(posedge `MON_CLK);
refHiVal = refHiQ.pop_back();
dutHiVal = dutHiQ.pop_back();
if (refHiVal == dutHiVal)
begin
$display("[INFO ] CPU HI REG Write Match at time %t", $time);
end
else
begin
$display("[ERROR] CPU HI REG Write Mismatch at time %t", $time);
if (VERBOSE) $display("[DEBUG] -> Expected 0x%x, Actual 0x%x"
, refHiVal
, dutHiVal );
end
end
end
endmodule | module MIPS1_CORE_MONITOR
#(parameter VERBOSE = 0)
(); |
`define TESTSTR "code.hex"
`include "tb_defines.v"
`include "psx_top_defines.vh"
`include "cpu_defs.v"
`define MON_CLK `CPU.CLK
`define MON_RST_SYNC `CPU.RST_SYNC
`define MON_CORE_INST_ADR `CPU.CORE_INST_ADR_OUT
`define MON_CORE_INST_CYC `CPU.CORE_INST_CYC_OUT
`define MON_CORE_INST_STB `CPU.CORE_INST_STB_OUT
`define MON_CORE_INST_WE `CPU.CORE_INST_WE_OUT
`define MON_CORE_INST_SEL `CPU.CORE_INST_SEL_OUT
`define MON_CORE_INST_CTI `CPU.CORE_INST_CTI_OUT
`define MON_CORE_INST_BTE `CPU.CORE_INST_BTE_OUT
`define MON_CORE_INST_ACK `CPU.CORE_INST_ACK_IN
`define MON_CORE_INST_STALL `CPU.CORE_INST_STALL_IN
`define MON_CORE_INST_ERR `CPU.CORE_INST_ERR_IN
`define MON_CORE_INST_DAT_RD `CPU.CORE_INST_DAT_RD_IN
`define MON_CORE_INST_DAT_WR `CPU.CORE_INST_DAT_WR_OUT
`define MON_CORE_DATA_ADR `CPU.CORE_DATA_ADR_OUT
`define MON_CORE_DATA_CYC `CPU.CORE_DATA_CYC_OUT
`define MON_CORE_DATA_STB `CPU.CORE_DATA_STB_OUT
`define MON_CORE_DATA_WE `CPU.CORE_DATA_WE_OUT
`define MON_CORE_DATA_SEL `CPU.CORE_DATA_SEL_OUT
`define MON_CORE_DATA_CTI `CPU.CORE_DATA_CTI_OUT
`define MON_CORE_DATA_BTE `CPU.CORE_DATA_BTE_OUT
`define MON_CORE_DATA_ACK `CPU.CORE_DATA_ACK_IN
`define MON_CORE_DATA_STALL `CPU.CORE_DATA_STALL_IN
`define MON_CORE_DATA_ERR `CPU.CORE_DATA_ERR_IN
`define MON_CORE_DATA_DAT_RD `CPU.CORE_DATA_DAT_RD_IN
`define MON_CORE_DATA_DAT_WR `CPU.CORE_DATA_DAT_WR_OUT
`define MON_STALL `CPU.Stall
`define MON_LO_VAL `CPU.LoVal
`define MON_HI_VAL `CPU.HiVal
`define MON_REG_WR `CPU.RegWriteWb
`define MON_REG_SEL `CPU.RegWrWb
`define MON_REG_WR_DATA `CPU.WriteDataWb
`define MON_MULT_REQ `CPU.MultReq
`define MON_MULT_ACK `CPU.MultAck
`define MON_DIV_REQ `CPU.DivReq
`define MON_DIV_ACK `CPU.DivAck
`define MON_MTHI `CPU.MthiMem
`define MON_MTLO `CPU.MtloMem
import CPU_CORE_MONITOR_PKG::regWriteEvent;
import CPU_CORE_MONITOR_PKG::wbM2SEvent;
import CPU_CORE_MONITOR_PKG::wbS2MEvent;
import "DPI-C" context function void helloWorld ();
import "DPI-C" context function void cpuInit ();
import "DPI-C" context function void cpuCycle(int pc, int opcode, int rd_data, int show_mode);
import "DPI-C" context function int cpuEnd ();
export "DPI-C" function refInstM2SPush ;
export "DPI-C" function refRegPush ;
export "DPI-C" function refDataM2SPush ;
export "DPI-C" function refLoHiPush ;
wbM2SEvent dutInstM2SQ[$];
wbS2MEvent dutInstS2MQ[$];
wbM2SEvent dutDataM2SQ[$];
wbS2MEvent dutDataS2MQ[$];
regWriteEvent dutRegQ[$];
int dutLoQ[$];
int dutHiQ[$];
wbM2SEvent refInstM2SQ[$];
wbS2MEvent refInstS2MQ[$];
wbM2SEvent refDataM2SQ[$];
wbS2MEvent refDataS2MQ[$];
regWriteEvent refRegQ[$];
int refLoQ[$];
int refHiQ[$];
int modelTraceActive;
wire WbCoreInstAddrStb = `MON_CORE_INST_CYC & `MON_CORE_INST_STB & ~`MON_CORE_INST_STALL;
wire WbCoreInstDataStb = `MON_CORE_INST_CYC & `MON_CORE_INST_ACK;
wire WbCoreDataAddrStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_STB & ~`MON_CORE_DATA_STALL;
wire WbCoreDataDataStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_ACK;
initial
begin
cpuInit();
if (VERBOSE > 0) $display("[INFO ] MIPS1 Core Monitor initialised at time %t", $time);
end
initial
begin
$timeformat(-9, 0, " ns", 6);
end
function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);
chkM2SData = 0;
if (wbM2SEventRef.RdWrB)
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
end
end
else
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address ) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB ) &&
(wbM2SEventRef.WrValue == wbM2SEventDut.WrValue )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
$display("[ERROR] -> Value Expected 0x%x, Actual 0x%x"
,wbM2SEventRef.WrValue
,wbM2SEventDut.WrValue );
end
end
endfunction
function void refInstM2SPush (int Address);
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = 1 ;
wbM2SEventLocal.Sel = 32'h0000_000f ;
wbM2SEventLocal.Address = Address ;
wbM2SEventLocal.WrValue = 0 ;
if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refInstM2SQ.push_front(wbM2SEventLocal);
endfunction
function void refDataM2SPush (int RdWrB, int Size, int Address, int WrValue);
logic [31:0] AddrAligned;
logic [ 3:0] Sel;
logic [31:0] DataAligned;
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = RdWrB ;
wbM2SEventLocal.WrValue = WrValue ;
DataAligned = 0;
case (Size)
4 :
begin
if (2'b00 != Address[1:0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = Address;
Sel = 4'b1111;
DataAligned = WrValue;
end
end
2 :
begin
if (1'b0 != Address[0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = {Address[31:2], 2'b00};
if (Address[1])
begin
Sel = 4'b1100;
DataAligned[31:16] = WrValue[15:0];
end
else
begin
Sel = 4'b0011;
DataAligned[15:0] = WrValue[15:0];
end
end
end
1 :
begin
AddrAligned = {Address[31:2], 2'b00};
Sel = 4'b0000;
Sel[Address[1:0]] = 1'b1;
case (Address[1:0])
2'b00 : DataAligned[ 7: 0] = WrValue[7:0];
2'b01 : DataAligned[15: 8] = WrValue[7:0];
2'b10 : DataAligned[23:16] = WrValue[7:0];
2'b11 : DataAligned[31:24] = WrValue[7:0];
endcase
end
default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);
endcase
wbM2SEventLocal.Sel = Sel ;
wbM2SEventLocal.Address = AddrAligned ;
wbM2SEventLocal.WrValue = DataAligned ;
if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refDataM2SQ.push_front(wbM2SEventLocal);
endfunction
function void refRegPush (input int regIndex, input int regValue);
regWriteEvent regWriteEventLocal;
regWriteEventLocal.regIndex = regIndex;
regWriteEventLocal.regValue = regValue;
if (VERBOSE) $display("[DEBUG] REF REG WR Push : Index = %2d, Data = 0x%x at time %t"
, regWriteEventLocal.regIndex
, regWriteEventLocal.regValue
, $time );
refRegQ.push_front(regWriteEventLocal);
endfunction
function void refLoHiPush (input int regIndex, input int regValue);
if (regIndex)
begin
if (VERBOSE) $display("[DEBUG] REF HI REG WR Push : Hi = 0x%x at time %t"
, regValue
, $time );
refHiQ.push_front(regValue);
end
else
begin
if (VERBOSE) $display("[DEBUG] REF LO REG WR Push : Lo = 0x%x at time %t"
, regValue
, $time );
refLoQ.push_front(regValue);
end
endfunction
always @(negedge `MON_CLK)
begin
wbM2SEvent wbM2SEventLocal;
if (WbCoreInstAddrStb)
begin
wbM2SEventLocal.RdWrB = (32'd1 === `MON_CORE_INST_WE) ? 0 : 1;
wbM2SEventLocal.Sel = {28'h000_0000, `MON_CORE_INST_SEL};
wbM2SEventLocal.Address = `MON_CORE_INST_ADR;
wbM2SEventLocal.WrValue = `MON_CORE_INST_DAT_WR;
assert (!$isunknown(`MON_CORE_INST_WE));
assert (!$isunknown(`MON_CORE_INST_SEL));
assert (!$isunknown(`MON_CORE_INST_ADR));
assert (!$isunknown(`MON_CORE_INST_DAT_WR));
if (VERBOSE) $display("[DEBUG] DUT INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
dutInstM2SQ.push_front(wbM2SEventLocal);
end
end
always @(negedge `MON_CLK)
begin
wbM2SEvent wbM2SEventLocal;
if (WbCoreDataAddrStb)
begin
wbM2SEventLocal.RdWrB = (32'd1 == `MON_CORE_DATA_WE) ? 0 : 1;
wbM2SEventLocal.Sel = {28'h000_0000, `MON_CORE_DATA_SEL};
wbM2SEventLocal.Address = `MON_CORE_DATA_ADR;
wbM2SEventLocal.WrValue = `MON_CORE_DATA_DAT_WR;
if (VERBOSE) $display("[DEBUG] DUT DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
dutDataM2SQ.push_front(wbM2SEventLocal);
end
end
always @(negedge `MON_CLK)
begin
wbS2MEvent wbS2MEventLocal;
if (WbCoreInstDataStb)
begin
wbS2MEventLocal.RdValue = `MON_CORE_INST_DAT_RD;
if (VERBOSE) $display("[DEBUG] DUT INST S2M Push : RdValue = 0x%x at time %t"
,wbS2MEventLocal.RdValue
, $time );
dutInstS2MQ.push_front(wbS2MEventLocal);
end
end
always @(negedge `MON_CLK)
begin
wbS2MEvent wbS2MEventLocal;
if (WbCoreDataDataStb)
begin
wbS2MEventLocal.RdValue = `MON_CORE_DATA_DAT_RD;
if (VERBOSE) $display("[DEBUG] DUT DATA S2M Push : RdValue = 0x%x at time %t"
,wbS2MEventLocal.RdValue
, $time );
dutDataS2MQ.push_front(wbS2MEventLocal);
end
end
always @(negedge `MON_CLK)
begin
regWriteEvent regWriteEventLocal;
if (`MON_REG_WR && !`MON_STALL)
begin
regWriteEventLocal.regIndex = `MON_REG_SEL;
regWriteEventLocal.regValue = `MON_REG_WR_DATA;
if (VERBOSE) $display("[DEBUG] DUT REG WR Push : Index = %2d, Data = 0x%x at time %t"
, regWriteEventLocal.regIndex
, regWriteEventLocal.regValue
, $time );
dutRegQ.push_front(regWriteEventLocal);
end
end
always @(negedge `MON_CLK)
begin
regWriteEvent regWriteEventLocal;
if ((`MON_MULT_REQ && `MON_MULT_ACK ) ||
(`MON_DIV_REQ && `MON_DIV_ACK ))
begin
if (VERBOSE) $display("[DEBUG] DUT LO REG WR Push : Lo = 0x%x at time %t"
, `MON_LO_VAL
, $time );
if (VERBOSE) $display("[DEBUG] DUT HI REG WR Push : Hi = 0x%x at time %t"
, `MON_HI_VAL
, $time );
dutLoQ.push_front(`MON_LO_VAL);
dutHiQ.push_front(`MON_HI_VAL);
end
if (`MON_MTHI && !`MON_STALL)
begin
if (VERBOSE) $display("[DEBUG] DUT HI REG WR Push : Hi = 0x%x at time %t"
, `MON_HI_VAL
, $time );
dutHiQ.push_front(`MON_HI_VAL);
end
if (`MON_MTLO && !`MON_STALL)
begin
if (VERBOSE) $display("[DEBUG] DUT LO REG WR Push : Lo = 0x%x at time %t"
, `MON_LO_VAL
, $time );
dutLoQ.push_front(`MON_LO_VAL);
end
end
initial
begin : CORE_INST_DATA_CHECK
regWriteEvent regWriteEventLocal;
wbM2SEvent wbM2SEventLocal;
wbS2MEvent wbS2MEventLocal;
wbM2SEvent refM2SDataEventLocal;
wbM2SEvent dutM2SDataEventLocal;
wbS2MEvent refS2MDataEventLocal;
wbS2MEvent dutS2MDataEventLocal;
wbM2SEvent refM2SInstEventLocal;
wbM2SEvent dutM2SInstEventLocal;
wbS2MEvent refS2MInstEventLocal;
wbS2MEvent dutS2MInstEventLocal;
int LoadInst;
int StoreInst;
logic [5:0] InstOpcode;
int RdData;
int instCount = 0;
wbM2SEventLocal.RdWrB = 1;
wbM2SEventLocal.Sel = 32'h0000_000f;
wbM2SEventLocal.Address = CPU_RST_VECTOR;
wbM2SEventLocal.WrValue = 0;
refInstM2SQ.push_front(wbM2SEventLocal);
regWriteEventLocal.regIndex = 0;
regWriteEventLocal.regValue = 0;
refRegQ.push_front(regWriteEventLocal);
modelTraceActive = 1;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while ((dutInstM2SQ.size() == 0) ||
(dutInstS2MQ.size() == 0))
@(posedge `MON_CLK);
if (VERBOSE) $display("[DEBUG] CPU WB Instruction ready at time %t", $time);
instCount++;
if (0 == (instCount % 10000))
begin
$display("[INFO ] Instruction %6d issued at time %t", instCount, $time);
end
dutM2SInstEventLocal = dutInstM2SQ.pop_back();
dutS2MInstEventLocal = dutInstS2MQ.pop_back();
InstOpcode = dutS2MInstEventLocal.RdValue[OPC_HI:OPC_LO];
if ((OPC_LB == InstOpcode) ||
(OPC_LH == InstOpcode) ||
(OPC_LW == InstOpcode) ||
(OPC_LBU == InstOpcode) ||
(OPC_LHU == InstOpcode)
)
begin
LoadInst = 1;
StoreInst = 0;
end
else if ((OPC_SB == InstOpcode) ||
(OPC_SH == InstOpcode) ||
(OPC_SW == InstOpcode)
)
begin
LoadInst = 0;
StoreInst = 1;
end
else if ((OPC_LWL == InstOpcode) ||
(OPC_LBU == InstOpcode) ||
(OPC_LHU == InstOpcode) ||
(OPC_LWR == InstOpcode) ||
(OPC_SWL == InstOpcode) ||
(OPC_SWR == InstOpcode) ||
(OPC_LWC0 == InstOpcode) ||
(OPC_LWC1 == InstOpcode) ||
(OPC_LWC2 == InstOpcode) ||
(OPC_LWC3 == InstOpcode) ||
(OPC_SWC0 == InstOpcode) ||
(OPC_SWC1 == InstOpcode) ||
(OPC_SWC2 == InstOpcode) ||
(OPC_SWC3 == InstOpcode)
)
begin
LoadInst = 0;
StoreInst = 0;
$display("[ERROR] Unsupported Load or Store (0x%x) found at time %t",
InstOpcode,
$time);
end
else
begin
LoadInst = 0;
StoreInst = 0;
end
if (LoadInst)
begin
if (VERBOSE) $display("[DEBUG] Load instruction (OPC = 0x%x) detected at time %t",
InstOpcode,
$time);
if (VERBOSE) $display("[DEBUG] Waiting for DUT Data M2S and S2M at time %t", $time);
while ((0 == dutDataM2SQ.size()) || (0 == dutDataS2MQ.size()))
@(posedge `MON_CLK);
if (VERBOSE) $display("[DEBUG] DUT Data M2S and S2M ready at time %t", $time);
dutM2SDataEventLocal = dutDataM2SQ.pop_back();
dutS2MDataEventLocal = dutDataS2MQ.pop_back();
RdData = 0;
case(dutM2SDataEventLocal.Sel)
4'b1111 : RdData = dutS2MDataEventLocal.RdValue;
4'h1100 : RdData = {16'd0, dutS2MDataEventLocal.RdValue[31:16]};
4'b0011 : RdData = {16'd0, dutS2MDataEventLocal.RdValue[15: 0]};
4'b1000 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[31:24]};
4'b0100 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[23:16]};
4'b0010 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[15: 8]};
4'b0001 : RdData = {24'd0, dutS2MDataEventLocal.RdValue[ 7: 0]};
endcase
if (VERBOSE) $display("[INFO ] C Model call. PC = 0x%x, Inst = 0x%x at time %t",
dutM2SInstEventLocal.Address,
dutS2MInstEventLocal.RdValue,
$time);
cpuCycle(dutM2SInstEventLocal.Address ,
dutS2MInstEventLocal.RdValue ,
RdData,
VERBOSE);
end
else if (StoreInst)
begin
if (VERBOSE) $display("[DEBUG] Store instruction (OPC = 0x%x) detected at time %t",
InstOpcode,
$time);
while ((0 == dutDataM2SQ.size()) || (0 == dutDataS2MQ.size()))
@(posedge `MON_CLK);
if (VERBOSE) $display("[DEBUG] DUT Data M2S and S2M ready at time %t", $time);
dutM2SDataEventLocal = dutDataM2SQ.pop_back();
dutS2MDataEventLocal = dutDataS2MQ.pop_back();
if (VERBOSE) $display("[INFO ] C Model call. PC = 0x%x, Inst = 0x%x at time %t",
dutM2SInstEventLocal.Address,
dutS2MInstEventLocal.RdValue,
$time);
cpuCycle(dutM2SInstEventLocal.Address ,
dutS2MInstEventLocal.RdValue ,
0 ,
VERBOSE);
end
else
begin
if (VERBOSE) $display("[INFO ] C Model call. PC = 0x%x, Inst = 0x%x at time %t",
dutM2SInstEventLocal.Address,
dutS2MInstEventLocal.RdValue,
$time);
cpuCycle(dutM2SInstEventLocal.Address ,
dutS2MInstEventLocal.RdValue ,
0 ,
VERBOSE);
end
if (StoreInst || LoadInst)
begin
refM2SDataEventLocal = refDataM2SQ.pop_back();
chkM2SData (refM2SDataEventLocal, dutM2SDataEventLocal, "Data",VERBOSE);
end
refM2SInstEventLocal = refInstM2SQ.pop_back();
chkM2SData (refM2SInstEventLocal, dutM2SInstEventLocal, "Inst",VERBOSE);
end
end
initial
begin : CORE_REG_CHECK
regWriteEvent refRegWriteEventLocal;
regWriteEvent dutRegWriteEventLocal;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while (refRegQ.size() == 0)
@(posedge `MON_CLK);
while (dutRegQ.size() == 0)
@(posedge `MON_CLK);
refRegWriteEventLocal = refRegQ.pop_back();
dutRegWriteEventLocal = dutRegQ.pop_back();
if (refRegWriteEventLocal == dutRegWriteEventLocal)
begin
if (VERBOSE > 0) $display("[INFO ] CPU REG Write Match at time %t", $time);
end
else
begin
$display("[ERROR] CPU REGS Write Mismatch at time %t", $time);
$display("[ERROR] -> regIndex Expected 0x%x, Actual 0x%x"
, refRegWriteEventLocal.regIndex
, dutRegWriteEventLocal.regIndex );
$display("[ERROR] -> regValue Expected 0x%x, Actual 0x%x"
, refRegWriteEventLocal.regValue
, dutRegWriteEventLocal.regValue );
end
end
end
initial
begin : CORE_LO_REG_CHECK
int refLoVal;
int dutLoVal;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while (refLoQ.size() == 0)
@(posedge `MON_CLK);
while (dutLoQ.size() == 0)
@(posedge `MON_CLK);
refLoVal = refLoQ.pop_back();
dutLoVal = dutLoQ.pop_back();
if (refLoVal == dutLoVal)
begin
$display("[INFO ] CPU LO REG Write Match at time %t", $time);
end
else
begin
$display("[ERROR] CPU LO REG Write Mismatch at time %t", $time);
if (VERBOSE) $display("[DEBUG] -> Expected 0x%x, Actual 0x%x"
, refLoVal
, dutLoVal );
end
end
end
initial
begin : CORE_HI_REG_CHECK
int refHiVal;
int dutHiVal;
while (1'b0 !== `MON_RST_SYNC)
@(posedge `MON_CLK);
while (modelTraceActive)
begin
while (refHiQ.size() == 0)
@(posedge `MON_CLK);
while (dutHiQ.size() == 0)
@(posedge `MON_CLK);
refHiVal = refHiQ.pop_back();
dutHiVal = dutHiQ.pop_back();
if (refHiVal == dutHiVal)
begin
$display("[INFO ] CPU HI REG Write Match at time %t", $time);
end
else
begin
$display("[ERROR] CPU HI REG Write Mismatch at time %t", $time);
if (VERBOSE) $display("[DEBUG] -> Expected 0x%x, Actual 0x%x"
, refHiVal
, dutHiVal );
end
end
end
endmodule | 1 |
138,382 | data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v | 83,270,534 | mips1_core_monitor.v | v | 971 | 135 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:15: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:16: Cannot find include file: psx_top_defines.vh\n`include "psx_top_defines.vh" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:17: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:69: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport CPU_CORE_MONITOR_PKG::regWriteEvent;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:140: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, " ns", 6);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:151: syntax error, unexpected IDENTIFIER, expecting \')\'\n function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:166: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:173: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:206: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:213: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:232: syntax error, unexpected endfunction\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:246: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = 1 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:247: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = 32\'h0000_000f ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = Address ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:249: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = 0 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:251: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:258: syntax error, unexpected \'(\', expecting IDENTIFIER\n refInstM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:273: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = RdWrB ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:276: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = WrValue ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:286: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:290: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = Address;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:300: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:305: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b1100;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:314: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b0011;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:323: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:329: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b00 : DataAligned[ 7: 0] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:330: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b01 : DataAligned[15: 8] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:331: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b10 : DataAligned[23:16] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:332: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b11 : DataAligned[31:24] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:337: syntax error, unexpected $display\n default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:341: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = Sel ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:342: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = AddrAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = DataAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:345: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n refDataM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,274 | function | function void helloWorld ();
import "DPI-C" context function void cpuInit ();
import "DPI-C" context function void cpuCycle(int pc, int opcode, int rd_data, int show_mode);
import "DPI-C" context function int cpuEnd ();
export "DPI-C" function refInstM2SPush ;
export "DPI-C" function refRegPush ;
export "DPI-C" function refDataM2SPush ;
export "DPI-C" function refLoHiPush ;
wbM2SEvent dutInstM2SQ[$];
wbS2MEvent dutInstS2MQ[$];
wbM2SEvent dutDataM2SQ[$];
wbS2MEvent dutDataS2MQ[$];
regWriteEvent dutRegQ[$];
int dutLoQ[$];
int dutHiQ[$];
wbM2SEvent refInstM2SQ[$];
wbS2MEvent refInstS2MQ[$];
wbM2SEvent refDataM2SQ[$];
wbS2MEvent refDataS2MQ[$];
regWriteEvent refRegQ[$];
int refLoQ[$];
int refHiQ[$];
int modelTraceActive;
wire WbCoreInstAddrStb = `MON_CORE_INST_CYC & `MON_CORE_INST_STB & ~`MON_CORE_INST_STALL;
wire WbCoreInstDataStb = `MON_CORE_INST_CYC & `MON_CORE_INST_ACK;
wire WbCoreDataAddrStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_STB & ~`MON_CORE_DATA_STALL;
wire WbCoreDataDataStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_ACK;
initial
begin
cpuInit();
if (VERBOSE > 0) $display("[INFO ] MIPS1 Core Monitor initialised at time %t", $time);
end
initial
begin
$timeformat(-9, 0, " ns", 6);
end
function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);
chkM2SData = 0;
if (wbM2SEventRef.RdWrB)
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
end
end
else
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address ) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB ) &&
(wbM2SEventRef.WrValue == wbM2SEventDut.WrValue )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
$display("[ERROR] -> Value Expected 0x%x, Actual 0x%x"
,wbM2SEventRef.WrValue
,wbM2SEventDut.WrValue );
end
end
endfunction | function void helloWorld (); |
import "DPI-C" context function void cpuInit ();
import "DPI-C" context function void cpuCycle(int pc, int opcode, int rd_data, int show_mode);
import "DPI-C" context function int cpuEnd ();
export "DPI-C" function refInstM2SPush ;
export "DPI-C" function refRegPush ;
export "DPI-C" function refDataM2SPush ;
export "DPI-C" function refLoHiPush ;
wbM2SEvent dutInstM2SQ[$];
wbS2MEvent dutInstS2MQ[$];
wbM2SEvent dutDataM2SQ[$];
wbS2MEvent dutDataS2MQ[$];
regWriteEvent dutRegQ[$];
int dutLoQ[$];
int dutHiQ[$];
wbM2SEvent refInstM2SQ[$];
wbS2MEvent refInstS2MQ[$];
wbM2SEvent refDataM2SQ[$];
wbS2MEvent refDataS2MQ[$];
regWriteEvent refRegQ[$];
int refLoQ[$];
int refHiQ[$];
int modelTraceActive;
wire WbCoreInstAddrStb = `MON_CORE_INST_CYC & `MON_CORE_INST_STB & ~`MON_CORE_INST_STALL;
wire WbCoreInstDataStb = `MON_CORE_INST_CYC & `MON_CORE_INST_ACK;
wire WbCoreDataAddrStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_STB & ~`MON_CORE_DATA_STALL;
wire WbCoreDataDataStb = `MON_CORE_DATA_CYC & `MON_CORE_DATA_ACK;
initial
begin
cpuInit();
if (VERBOSE > 0) $display("[INFO ] MIPS1 Core Monitor initialised at time %t", $time);
end
initial
begin
$timeformat(-9, 0, " ns", 6);
end
function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);
chkM2SData = 0;
if (wbM2SEventRef.RdWrB)
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
end
end
else
begin
if ((wbM2SEventRef.Address == wbM2SEventDut.Address ) &&
(wbM2SEventRef.Sel == wbM2SEventDut.Sel ) &&
(wbM2SEventRef.RdWrB == wbM2SEventDut.RdWrB ) &&
(wbM2SEventRef.WrValue == wbM2SEventDut.WrValue )
)
begin
if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);
chkM2SData = 1;
end
else
begin
$display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);
$display("[ERROR] -> RdWrB Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.RdWrB
, wbM2SEventDut.RdWrB );
$display("[ERROR] -> Sel Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Sel
, wbM2SEventDut.Sel );
$display("[ERROR] -> Address Expected 0x%x, Actual 0x%x"
, wbM2SEventRef.Address
, wbM2SEventDut.Address );
$display("[ERROR] -> Value Expected 0x%x, Actual 0x%x"
,wbM2SEventRef.WrValue
,wbM2SEventDut.WrValue );
end
end
endfunction | 1 |
138,383 | data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v | 83,270,534 | mips1_core_monitor.v | v | 971 | 135 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:15: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:16: Cannot find include file: psx_top_defines.vh\n`include "psx_top_defines.vh" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:17: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:69: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport CPU_CORE_MONITOR_PKG::regWriteEvent;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:140: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, " ns", 6);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:151: syntax error, unexpected IDENTIFIER, expecting \')\'\n function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:166: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:173: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:206: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:213: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:232: syntax error, unexpected endfunction\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:246: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = 1 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:247: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = 32\'h0000_000f ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = Address ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:249: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = 0 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:251: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:258: syntax error, unexpected \'(\', expecting IDENTIFIER\n refInstM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:273: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = RdWrB ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:276: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = WrValue ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:286: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:290: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = Address;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:300: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:305: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b1100;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:314: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b0011;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:323: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:329: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b00 : DataAligned[ 7: 0] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:330: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b01 : DataAligned[15: 8] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:331: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b10 : DataAligned[23:16] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:332: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b11 : DataAligned[31:24] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:337: syntax error, unexpected $display\n default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:341: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = Sel ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:342: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = AddrAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = DataAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:345: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n refDataM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,274 | function | function void refInstM2SPush (int Address);
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = 1 ;
wbM2SEventLocal.Sel = 32'h0000_000f ;
wbM2SEventLocal.Address = Address ;
wbM2SEventLocal.WrValue = 0 ;
if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refInstM2SQ.push_front(wbM2SEventLocal);
endfunction | function void refInstM2SPush (int Address); |
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = 1 ;
wbM2SEventLocal.Sel = 32'h0000_000f ;
wbM2SEventLocal.Address = Address ;
wbM2SEventLocal.WrValue = 0 ;
if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refInstM2SQ.push_front(wbM2SEventLocal);
endfunction | 1 |
138,384 | data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v | 83,270,534 | mips1_core_monitor.v | v | 971 | 135 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:15: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:16: Cannot find include file: psx_top_defines.vh\n`include "psx_top_defines.vh" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:17: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:69: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport CPU_CORE_MONITOR_PKG::regWriteEvent;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:140: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, " ns", 6);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:151: syntax error, unexpected IDENTIFIER, expecting \')\'\n function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:166: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:173: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:206: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:213: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:232: syntax error, unexpected endfunction\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:246: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = 1 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:247: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = 32\'h0000_000f ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = Address ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:249: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = 0 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:251: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:258: syntax error, unexpected \'(\', expecting IDENTIFIER\n refInstM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:273: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = RdWrB ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:276: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = WrValue ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:286: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:290: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = Address;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:300: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:305: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b1100;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:314: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b0011;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:323: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:329: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b00 : DataAligned[ 7: 0] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:330: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b01 : DataAligned[15: 8] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:331: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b10 : DataAligned[23:16] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:332: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b11 : DataAligned[31:24] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:337: syntax error, unexpected $display\n default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:341: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = Sel ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:342: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = AddrAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = DataAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:345: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n refDataM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,274 | function | function void refDataM2SPush (int RdWrB, int Size, int Address, int WrValue);
logic [31:0] AddrAligned;
logic [ 3:0] Sel;
logic [31:0] DataAligned;
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = RdWrB ;
wbM2SEventLocal.WrValue = WrValue ;
DataAligned = 0;
case (Size)
4 :
begin
if (2'b00 != Address[1:0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = Address;
Sel = 4'b1111;
DataAligned = WrValue;
end
end
2 :
begin
if (1'b0 != Address[0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = {Address[31:2], 2'b00};
if (Address[1])
begin
Sel = 4'b1100;
DataAligned[31:16] = WrValue[15:0];
end
else
begin
Sel = 4'b0011;
DataAligned[15:0] = WrValue[15:0];
end
end
end
1 :
begin
AddrAligned = {Address[31:2], 2'b00};
Sel = 4'b0000;
Sel[Address[1:0]] = 1'b1;
case (Address[1:0])
2'b00 : DataAligned[ 7: 0] = WrValue[7:0];
2'b01 : DataAligned[15: 8] = WrValue[7:0];
2'b10 : DataAligned[23:16] = WrValue[7:0];
2'b11 : DataAligned[31:24] = WrValue[7:0];
endcase
end
default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);
endcase
wbM2SEventLocal.Sel = Sel ;
wbM2SEventLocal.Address = AddrAligned ;
wbM2SEventLocal.WrValue = DataAligned ;
if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refDataM2SQ.push_front(wbM2SEventLocal);
endfunction | function void refDataM2SPush (int RdWrB, int Size, int Address, int WrValue); |
logic [31:0] AddrAligned;
logic [ 3:0] Sel;
logic [31:0] DataAligned;
wbM2SEvent wbM2SEventLocal;
wbM2SEventLocal.RdWrB = RdWrB ;
wbM2SEventLocal.WrValue = WrValue ;
DataAligned = 0;
case (Size)
4 :
begin
if (2'b00 != Address[1:0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = Address;
Sel = 4'b1111;
DataAligned = WrValue;
end
end
2 :
begin
if (1'b0 != Address[0])
begin
$display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);
end
else
begin
AddrAligned = {Address[31:2], 2'b00};
if (Address[1])
begin
Sel = 4'b1100;
DataAligned[31:16] = WrValue[15:0];
end
else
begin
Sel = 4'b0011;
DataAligned[15:0] = WrValue[15:0];
end
end
end
1 :
begin
AddrAligned = {Address[31:2], 2'b00};
Sel = 4'b0000;
Sel[Address[1:0]] = 1'b1;
case (Address[1:0])
2'b00 : DataAligned[ 7: 0] = WrValue[7:0];
2'b01 : DataAligned[15: 8] = WrValue[7:0];
2'b10 : DataAligned[23:16] = WrValue[7:0];
2'b11 : DataAligned[31:24] = WrValue[7:0];
endcase
end
default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);
endcase
wbM2SEventLocal.Sel = Sel ;
wbM2SEventLocal.Address = AddrAligned ;
wbM2SEventLocal.WrValue = DataAligned ;
if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"
,wbM2SEventLocal.Address
,wbM2SEventLocal.Sel[3:0]
,wbM2SEventLocal.RdWrB
,wbM2SEventLocal.WrValue
, $time );
refDataM2SQ.push_front(wbM2SEventLocal);
endfunction | 1 |
138,385 | data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v | 83,270,534 | mips1_core_monitor.v | v | 971 | 135 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:15: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:16: Cannot find include file: psx_top_defines.vh\n`include "psx_top_defines.vh" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:17: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:69: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport CPU_CORE_MONITOR_PKG::regWriteEvent;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:140: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, " ns", 6);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:151: syntax error, unexpected IDENTIFIER, expecting \')\'\n function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:166: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:173: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:206: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:213: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:232: syntax error, unexpected endfunction\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:246: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = 1 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:247: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = 32\'h0000_000f ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = Address ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:249: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = 0 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:251: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:258: syntax error, unexpected \'(\', expecting IDENTIFIER\n refInstM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:273: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = RdWrB ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:276: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = WrValue ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:286: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:290: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = Address;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:300: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:305: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b1100;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:314: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b0011;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:323: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:329: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b00 : DataAligned[ 7: 0] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:330: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b01 : DataAligned[15: 8] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:331: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b10 : DataAligned[23:16] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:332: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b11 : DataAligned[31:24] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:337: syntax error, unexpected $display\n default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:341: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = Sel ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:342: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = AddrAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = DataAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:345: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n refDataM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,274 | function | function void refRegPush (input int regIndex, input int regValue);
regWriteEvent regWriteEventLocal;
regWriteEventLocal.regIndex = regIndex;
regWriteEventLocal.regValue = regValue;
if (VERBOSE) $display("[DEBUG] REF REG WR Push : Index = %2d, Data = 0x%x at time %t"
, regWriteEventLocal.regIndex
, regWriteEventLocal.regValue
, $time );
refRegQ.push_front(regWriteEventLocal);
endfunction | function void refRegPush (input int regIndex, input int regValue); |
regWriteEvent regWriteEventLocal;
regWriteEventLocal.regIndex = regIndex;
regWriteEventLocal.regValue = regValue;
if (VERBOSE) $display("[DEBUG] REF REG WR Push : Index = %2d, Data = 0x%x at time %t"
, regWriteEventLocal.regIndex
, regWriteEventLocal.regValue
, $time );
refRegQ.push_front(regWriteEventLocal);
endfunction | 1 |
138,386 | data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v | 83,270,534 | mips1_core_monitor.v | v | 971 | 135 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:15: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:16: Cannot find include file: psx_top_defines.vh\n`include "psx_top_defines.vh" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:17: Cannot find include file: cpu_defs.v\n`include "cpu_defs.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:69: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport CPU_CORE_MONITOR_PKG::regWriteEvent;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:121: Define or directive not defined: \'`CPU\'\n wire WbCoreInstAddrStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_STB_OUT & ~`CPU.CORE_INST_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:122: Define or directive not defined: \'`CPU\'\n wire WbCoreInstDataStb = `CPU.CORE_INST_CYC_OUT & `CPU.CORE_INST_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:123: Define or directive not defined: \'`CPU\'\n wire WbCoreDataAddrStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_STB_OUT & ~`CPU.CORE_DATA_STALL_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:124: Define or directive not defined: \'`CPU\'\n wire WbCoreDataDataStb = `CPU.CORE_DATA_CYC_OUT & `CPU.CORE_DATA_ACK_IN;\n ^~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:140: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, " ns", 6);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:151: syntax error, unexpected IDENTIFIER, expecting \')\'\n function int chkM2SData (wbM2SEvent wbM2SEventRef, wbM2SEvent wbM2SEventDut, string dataType, int Verbose = 1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:166: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:173: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:206: syntax error, unexpected $display\n if (VERBOSE > 0) $display("[INFO ] WB M2S %s Match at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:213: syntax error, unexpected $display\n $display("[ERROR] WB M2S %s Mismatch at time %t", dataType, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:232: syntax error, unexpected endfunction\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:246: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = 1 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:247: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = 32\'h0000_000f ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = Address ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:249: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = 0 ; \n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:251: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF INST M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:258: syntax error, unexpected \'(\', expecting IDENTIFIER\n refInstM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:273: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.RdWrB = RdWrB ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:276: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = WrValue ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:286: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:290: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = Address;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:300: syntax error, unexpected $display\n $display("[ERROR] Unaligned C Ref model M2S Data Push. Address = 0x%x, Size = %2d at time %t", Address, Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:305: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b1100;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:314: syntax error, unexpected \'=\', expecting IDENTIFIER\n Sel = 4\'b0011;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:323: syntax error, unexpected \'=\', expecting IDENTIFIER\n AddrAligned = {Address[31:2], 2\'b00};\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:329: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b00 : DataAligned[ 7: 0] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:330: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b01 : DataAligned[15: 8] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:331: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b10 : DataAligned[23:16] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:332: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2\'b11 : DataAligned[31:24] = WrValue[7:0];\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:337: syntax error, unexpected $display\n default : $display("[ERROR] Illegal Size pushed from C model = 0x%x at time %t", Size, $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:341: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Sel = Sel ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:342: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.Address = AddrAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n wbM2SEventLocal.WrValue = DataAligned ;\n ^\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:345: syntax error, unexpected $display\n if (VERBOSE) $display("[DEBUG] REF DATA M2S Push : Addr = 0x%x, Sel = 0x%x, RdWrB = %1d, WrValue = 0x%x at time %t"\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/psx_top/tb/mips1_core_monitor.v:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n refDataM2SQ.push_front(wbM2SEventLocal);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,274 | function | function void refLoHiPush (input int regIndex, input int regValue);
if (regIndex)
begin
if (VERBOSE) $display("[DEBUG] REF HI REG WR Push : Hi = 0x%x at time %t"
, regValue
, $time );
refHiQ.push_front(regValue);
end
else
begin
if (VERBOSE) $display("[DEBUG] REF LO REG WR Push : Lo = 0x%x at time %t"
, regValue
, $time );
refLoQ.push_front(regValue);
end
endfunction | function void refLoHiPush (input int regIndex, input int regValue); |
if (regIndex)
begin
if (VERBOSE) $display("[DEBUG] REF HI REG WR Push : Hi = 0x%x at time %t"
, regValue
, $time );
refHiQ.push_front(regValue);
end
else
begin
if (VERBOSE) $display("[DEBUG] REF LO REG WR Push : Lo = 0x%x at time %t"
, regValue
, $time );
refLoQ.push_front(regValue);
end
endfunction | 1 |
138,387 | data/full_repos/permissive/83270534/psx_top/tb/tb_top.v | 83,270,534 | tb_top.v | v | 240 | 78 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/psx_top/tb/tb_top.v:4: Cannot find include file: psx_mem_map.vh\n`include "psx_mem_map.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/psx_mem_map.vh\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/psx_mem_map.vh.v\n data/full_repos/permissive/83270534/psx_top/tb,data/full_repos/permissive/83270534/psx_mem_map.vh.sv\n psx_mem_map.vh\n psx_mem_map.vh.v\n psx_mem_map.vh.sv\n obj_dir/psx_mem_map.vh\n obj_dir/psx_mem_map.vh.v\n obj_dir/psx_mem_map.vh.sv\n%Error: data/full_repos/permissive/83270534/psx_top/tb/tb_top.v:5: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 302,276 | module | module TB_TOP ();
`include "psx_mem_map.vh"
`include "tb_defines.v"
wire Clk;
wire Rst;
wire [31:0] WbSysAdr ;
wire WbSysRomCyc ;
wire WbSysRomStb ;
wire WbSysDramCyc ;
wire WbSysDramStb ;
wire WbSysWe ;
wire [ 3:0] WbSysSel ;
wire [ 2:0] WbSysCti ;
wire [ 1:0] WbSysBte ;
wire WbSysRomAck ;
wire WbSysRomStall ;
wire WbSysRomErr ;
wire WbSysDramAck ;
wire WbSysDramStall ;
wire WbSysDramErr ;
wire [31:0] WbSysDatRomRd ;
wire [31:0] WbSysDatDramRd ;
wire [31:0] WbSysDatWr ;
wire [31:0] WbGpuAdr ;
wire WbGpuCyc ;
wire WbGpuStb ;
wire WbGpuWe ;
wire [ 3:0] WbGpuSel ;
wire [ 2:0] WbGpuCti ;
wire [ 1:0] WbGpuBte ;
wire WbGpuAck ;
wire WbGpuStall ;
wire WbGpuErr ;
wire [31:0] WbGpuDatRd ;
wire [31:0] WbGpuDatWr ;
`ifndef CPU_CORE_BFM
MIPS1_CORE_MONITOR
#(.VERBOSE (0))
mips1_core_monitor ();
`endif
CLK_RST_GEN
#(.CLK_HALF_PERIOD (5)
)
clk_rst_gen
(
.CLK_OUT (Clk ),
.RST_OUT (Rst )
);
TESTCASE testcase ();
PSX_TOP psx_top
(
.CLK (Clk ),
.EN (1'b1 ),
.RST_SYNC (Rst ),
.RST_ASYNC (Rst ),
.WB_SYS_ADR_OUT (WbSysAdr ),
.WB_SYS_ROM_CYC_OUT (WbSysRomCyc ),
.WB_SYS_ROM_STB_OUT (WbSysRomStb ),
.WB_SYS_DRAM_CYC_OUT (WbSysDramCyc ),
.WB_SYS_DRAM_STB_OUT (WbSysDramStb ),
.WB_SYS_WE_OUT (WbSysWe ),
.WB_SYS_SEL_OUT (WbSysSel ),
.WB_SYS_CTI_OUT (WbSysCti ),
.WB_SYS_BTE_OUT (WbSysBte ),
.WB_SYS_ROM_ACK_IN (WbSysRomAck ),
.WB_SYS_ROM_STALL_IN (WbSysRomStall ),
.WB_SYS_ROM_ERR_IN (WbSysRomErr ),
.WB_SYS_DRAM_ACK_IN (WbSysDramAck ),
.WB_SYS_DRAM_STALL_IN (WbSysDramStall ),
.WB_SYS_DRAM_ERR_IN (WbSysDramErr ),
.WB_SYS_DAT_ROM_RD_IN (WbSysDatRomRd ),
.WB_SYS_DAT_DRAM_RD_IN (WbSysDatDramRd ),
.WB_SYS_DAT_WR_OUT (WbSysDatWr ),
.WB_GPU_ADR_OUT (WbGpuAdr ),
.WB_GPU_CYC_OUT (WbGpuCyc ),
.WB_GPU_STB_OUT (WbGpuStb ),
.WB_GPU_WE_OUT (WbGpuWe ),
.WB_GPU_SEL_OUT (WbGpuSel ),
.WB_GPU_CTI_OUT (WbGpuCti ),
.WB_GPU_BTE_OUT (WbGpuBte ),
.WB_GPU_ACK_IN (WbGpuAck ),
.WB_GPU_STALL_IN (WbGpuStall ),
.WB_GPU_ERR_IN (WbGpuErr ),
.WB_GPU_DAT_RD_IN (WbGpuDatRd ),
.WB_GPU_DAT_WR_OUT (WbGpuDatWr )
);
WB_SLAVE_BFM
#(
.VERBOSE (0),
.READ_ONLY (1),
.MEM_BASE (32'h1fc0_0000),
.MEM_SIZE_P2 (ROM_SIZE_P2),
.MIN_LATENCY (0),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
wb_slave_bfm_rom
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbSysAdr ),
.WB_CYC_IN (WbSysRomCyc ),
.WB_STB_IN (WbSysRomStb ),
.WB_WE_IN (WbSysWe ),
.WB_SEL_IN (WbSysSel ),
.WB_CTI_IN (WbSysCti ),
.WB_BTE_IN (WbSysBte ),
.WB_STALL_OUT (WbSysRomStall ),
.WB_ACK_OUT (WbSysRomAck ),
.WB_ERR_OUT (WbSysRomErr ),
.WB_DAT_RD_OUT (WbSysDatRomRd ),
.WB_DAT_WR_IN (WbSysDatWr )
);
WB_SLAVE_BFM
#(
.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (DRAM_SIZE_P2),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
wb_slave_bfm_dram
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbSysAdr ),
.WB_CYC_IN (WbSysDramCyc ),
.WB_STB_IN (WbSysDramStb ),
.WB_WE_IN (WbSysWe ),
.WB_SEL_IN (WbSysSel ),
.WB_CTI_IN (WbSysCti ),
.WB_BTE_IN (WbSysBte ),
.WB_STALL_OUT (WbSysDramStall ),
.WB_ACK_OUT (WbSysDramAck ),
.WB_ERR_OUT (WbSysDramErr ),
.WB_DAT_RD_OUT (WbSysDatDramRd ),
.WB_DAT_WR_IN (WbSysDatWr )
);
WB_SLAVE_BFM
#(
.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (20),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
wb_slave_bfm_gpu_local_ram
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbGpuAdr ),
.WB_CYC_IN (WbGpuCyc ),
.WB_STB_IN (WbGpuStb ),
.WB_WE_IN (WbGpuWe ),
.WB_SEL_IN (WbGpuSel ),
.WB_CTI_IN (WbGpuCti ),
.WB_BTE_IN (WbGpuBte ),
.WB_STALL_OUT (WbGpuStall ),
.WB_ACK_OUT (WbGpuAck ),
.WB_ERR_OUT (WbGpuErr ),
.WB_DAT_RD_OUT (WbGpuDatRd ),
.WB_DAT_WR_IN (WbGpuDatWr )
);
endmodule | module TB_TOP (); |
`include "psx_mem_map.vh"
`include "tb_defines.v"
wire Clk;
wire Rst;
wire [31:0] WbSysAdr ;
wire WbSysRomCyc ;
wire WbSysRomStb ;
wire WbSysDramCyc ;
wire WbSysDramStb ;
wire WbSysWe ;
wire [ 3:0] WbSysSel ;
wire [ 2:0] WbSysCti ;
wire [ 1:0] WbSysBte ;
wire WbSysRomAck ;
wire WbSysRomStall ;
wire WbSysRomErr ;
wire WbSysDramAck ;
wire WbSysDramStall ;
wire WbSysDramErr ;
wire [31:0] WbSysDatRomRd ;
wire [31:0] WbSysDatDramRd ;
wire [31:0] WbSysDatWr ;
wire [31:0] WbGpuAdr ;
wire WbGpuCyc ;
wire WbGpuStb ;
wire WbGpuWe ;
wire [ 3:0] WbGpuSel ;
wire [ 2:0] WbGpuCti ;
wire [ 1:0] WbGpuBte ;
wire WbGpuAck ;
wire WbGpuStall ;
wire WbGpuErr ;
wire [31:0] WbGpuDatRd ;
wire [31:0] WbGpuDatWr ;
`ifndef CPU_CORE_BFM
MIPS1_CORE_MONITOR
#(.VERBOSE (0))
mips1_core_monitor ();
`endif
CLK_RST_GEN
#(.CLK_HALF_PERIOD (5)
)
clk_rst_gen
(
.CLK_OUT (Clk ),
.RST_OUT (Rst )
);
TESTCASE testcase ();
PSX_TOP psx_top
(
.CLK (Clk ),
.EN (1'b1 ),
.RST_SYNC (Rst ),
.RST_ASYNC (Rst ),
.WB_SYS_ADR_OUT (WbSysAdr ),
.WB_SYS_ROM_CYC_OUT (WbSysRomCyc ),
.WB_SYS_ROM_STB_OUT (WbSysRomStb ),
.WB_SYS_DRAM_CYC_OUT (WbSysDramCyc ),
.WB_SYS_DRAM_STB_OUT (WbSysDramStb ),
.WB_SYS_WE_OUT (WbSysWe ),
.WB_SYS_SEL_OUT (WbSysSel ),
.WB_SYS_CTI_OUT (WbSysCti ),
.WB_SYS_BTE_OUT (WbSysBte ),
.WB_SYS_ROM_ACK_IN (WbSysRomAck ),
.WB_SYS_ROM_STALL_IN (WbSysRomStall ),
.WB_SYS_ROM_ERR_IN (WbSysRomErr ),
.WB_SYS_DRAM_ACK_IN (WbSysDramAck ),
.WB_SYS_DRAM_STALL_IN (WbSysDramStall ),
.WB_SYS_DRAM_ERR_IN (WbSysDramErr ),
.WB_SYS_DAT_ROM_RD_IN (WbSysDatRomRd ),
.WB_SYS_DAT_DRAM_RD_IN (WbSysDatDramRd ),
.WB_SYS_DAT_WR_OUT (WbSysDatWr ),
.WB_GPU_ADR_OUT (WbGpuAdr ),
.WB_GPU_CYC_OUT (WbGpuCyc ),
.WB_GPU_STB_OUT (WbGpuStb ),
.WB_GPU_WE_OUT (WbGpuWe ),
.WB_GPU_SEL_OUT (WbGpuSel ),
.WB_GPU_CTI_OUT (WbGpuCti ),
.WB_GPU_BTE_OUT (WbGpuBte ),
.WB_GPU_ACK_IN (WbGpuAck ),
.WB_GPU_STALL_IN (WbGpuStall ),
.WB_GPU_ERR_IN (WbGpuErr ),
.WB_GPU_DAT_RD_IN (WbGpuDatRd ),
.WB_GPU_DAT_WR_OUT (WbGpuDatWr )
);
WB_SLAVE_BFM
#(
.VERBOSE (0),
.READ_ONLY (1),
.MEM_BASE (32'h1fc0_0000),
.MEM_SIZE_P2 (ROM_SIZE_P2),
.MIN_LATENCY (0),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
wb_slave_bfm_rom
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbSysAdr ),
.WB_CYC_IN (WbSysRomCyc ),
.WB_STB_IN (WbSysRomStb ),
.WB_WE_IN (WbSysWe ),
.WB_SEL_IN (WbSysSel ),
.WB_CTI_IN (WbSysCti ),
.WB_BTE_IN (WbSysBte ),
.WB_STALL_OUT (WbSysRomStall ),
.WB_ACK_OUT (WbSysRomAck ),
.WB_ERR_OUT (WbSysRomErr ),
.WB_DAT_RD_OUT (WbSysDatRomRd ),
.WB_DAT_WR_IN (WbSysDatWr )
);
WB_SLAVE_BFM
#(
.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (DRAM_SIZE_P2),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
wb_slave_bfm_dram
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbSysAdr ),
.WB_CYC_IN (WbSysDramCyc ),
.WB_STB_IN (WbSysDramStb ),
.WB_WE_IN (WbSysWe ),
.WB_SEL_IN (WbSysSel ),
.WB_CTI_IN (WbSysCti ),
.WB_BTE_IN (WbSysBte ),
.WB_STALL_OUT (WbSysDramStall ),
.WB_ACK_OUT (WbSysDramAck ),
.WB_ERR_OUT (WbSysDramErr ),
.WB_DAT_RD_OUT (WbSysDatDramRd ),
.WB_DAT_WR_IN (WbSysDatWr )
);
WB_SLAVE_BFM
#(
.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000),
.MEM_SIZE_P2 (20),
.MAX_LATENCY (4),
.ADDR_LIMIT (1)
)
wb_slave_bfm_gpu_local_ram
(
.CLK (Clk ),
.RST_SYNC (Rst ),
.WB_ADR_IN (WbGpuAdr ),
.WB_CYC_IN (WbGpuCyc ),
.WB_STB_IN (WbGpuStb ),
.WB_WE_IN (WbGpuWe ),
.WB_SEL_IN (WbGpuSel ),
.WB_CTI_IN (WbGpuCti ),
.WB_BTE_IN (WbGpuBte ),
.WB_STALL_OUT (WbGpuStall ),
.WB_ACK_OUT (WbGpuAck ),
.WB_ERR_OUT (WbGpuErr ),
.WB_DAT_RD_OUT (WbGpuDatRd ),
.WB_DAT_WR_IN (WbGpuDatWr )
);
endmodule | 1 |
138,388 | data/full_repos/permissive/83270534/sdram_controller/rtl/sdram_controller.v | 83,270,534 | sdram_controller.v | v | 788 | 157 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/sdram_controller/rtl/sdram_controller.v:46: Cannot find include file: sdr_defs.v\n`include "sdr_defs.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/sdram_controller/rtl,data/full_repos/permissive/83270534/sdr_defs.v\n data/full_repos/permissive/83270534/sdram_controller/rtl,data/full_repos/permissive/83270534/sdr_defs.v.v\n data/full_repos/permissive/83270534/sdram_controller/rtl,data/full_repos/permissive/83270534/sdr_defs.v.sv\n sdr_defs.v\n sdr_defs.v.v\n sdr_defs.v.sv\n obj_dir/sdr_defs.v\n obj_dir/sdr_defs.v.v\n obj_dir/sdr_defs.v.sv\n%Error: Exiting due to 1 error(s)\n' | 302,278 | module | module SDRAM_CONTROLLER
#(
parameter [31:0] WBA = 32'h0000_0000,
parameter WS_P2 = 24
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output CLK_SDR_EN_OUT ,
input [31:0] WB_ADR_IN ,
input WB_CYC_IN ,
input WB_STB_IN ,
input WB_WE_IN ,
input [ 3:0] WB_SEL_IN ,
input [ 2:0] WB_CTI_IN ,
input [ 1:0] WB_BTE_IN ,
output WB_ACK_OUT ,
output WB_STALL_OUT ,
output WB_ERR_OUT ,
input [31:0] WB_WR_DAT_IN ,
output [31:0] WB_RD_DAT_OUT ,
output [23:1] SDR_ADDR_OUT ,
output SDR_CRE_OUT ,
output SDR_ADVB_OUT ,
output SDR_CEB_OUT ,
output SDR_OEB_OUT ,
output SDR_WEB_OUT ,
input SDR_WAIT_IN ,
output SDR_LBB_OUT ,
output SDR_UBB_OUT ,
inout [15:0] SDR_DATA_INOUT
);
`include "sdr_defs.v"
parameter WS_MSB = WS_P2 - 1;
parameter [3:0] ASYNC_CLKS = 4'd4;
wire WbRead ;
wire WbWrite ;
wire WbAddrStb ;
reg WbWriteAck ;
wire [22:0] SdrBcrVal = 23'd0
| BCR_RS_BCR << BCR_RS_LO
| BCR_OM_SYNC << BCR_OM
| BCR_IL_VAR << BCR_IL
| BCR_LC_C3 << BCR_LC_LO
| BCR_WP_LOW << BCR_WP
| BCR_WC_NONE << BCR_WC
| BCR_DS_HALF << BCR_DS_LO
| BCR_BW_NO_WRAP << BCR_BW
| BCR_BL_CONT << BCR_BL_LO;
wire [31:0] SdrAddr32b ;
wire [WS_MSB:0] SdrAddr ;
wire [WS_MSB:1] SdrAddrMux ;
reg [WS_MSB:1] SdrAddrReg ;
wire WriteFifoWriteEn ;
wire WriteFifoWriteFull ;
wire [35:0] WriteFifoWriteData ;
wire WriteFifoReadEn ;
wire WriteFifoReadEmpty ;
wire [17:0] WriteFifoReadData ;
wire [ 1:0] SdrByteEn ;
wire [15:0] SdrWriteData ;
reg [ 1:0] SdrByteEnReg ;
reg [15:0] SdrWriteDataReg ;
wire ReadFifoReadEmpty ;
wire ReadFifoWriteEn ;
wire ReadFifoWriteFull ;
wire SdrDriveEn ;
wire [15:0] SdrReadData ;
wire SdrDataStb ;
reg [2:0] WbAddrCntVal ;
wire [3:0] WbAddrCntValShift = {WbAddrCntVal, 1'b0};
reg [3:0] SdrDataCntVal ;
wire SdrDataDriveEn;
reg ClkSdrEnSet;
reg ClkSdrEn;
wire WbRowWrapStall;
parameter [3:0] SDRFSM_IDLE = 4'h0;
parameter [3:0] SDRFSM_BCR_WRITE_REQ = 4'h1;
parameter [3:0] SDRFSM_BCR_WRITE_ACK = 4'h2;
parameter [3:0] SDRFSM_READY = 4'h3;
parameter [3:0] SDRFSM_WB_READ_ADDR = 4'h4;
parameter [3:0] SDRFSM_SDR_READ_DATA = 4'h5;
parameter [3:0] SDRFSM_WB_READ_DATA = 4'h6;
parameter [3:0] SDRFSM_WB_WRITE_DATA = 4'h7;
parameter [3:0] SDRFSM_SDR_WRITE_DATA = 4'h8;
parameter [3:0] SDRFSM_WRITE_END = 4'h9;
reg [3:0] SdrFsmStateCur ;
reg [3:0] SdrFsmStateNxt ;
reg WbReadAckNxt ;
reg WbReadAck ;
reg WbWriteStallNxt ;
reg WbWriteStall ;
reg WbReadStallNxt ;
reg WbReadStall ;
reg WbAsyncStallNxt ;
reg WbAsyncStall ;
reg SdrCreNxt ;
reg SdrCre ;
reg SdrAdvbNxt ;
reg SdrAdvb ;
reg SdrCebNxt ;
reg SdrCeb ;
reg SdrOebNxt ;
reg SdrOeb ;
reg SdrWebNxt ;
reg SdrWeb ;
reg SdrWaitValidNxt ;
reg SdrWaitValid ;
reg SdrBcrAddrbSel ;
reg SdrAddrRegEn ;
reg WbAddrCntClr ;
reg SdrDataCntClr ;
reg SdrAsyncCntLd ;
reg [3:0] SdrAsyncCntVal ;
wire SdrDataEn;
assign WbRead = WB_CYC_IN & ~WB_WE_IN;
assign WbWrite = WB_CYC_IN & WB_WE_IN;
assign WbAddrStb = WB_CYC_IN & WB_STB_IN & ~WB_STALL_OUT;
assign SdrAddr32b = (WB_ADR_IN - WBA);
assign SdrAddr = {SdrAddr32b[WS_MSB:1], 1'b0};
assign SdrAddrMux = SdrBcrAddrbSel ? SdrBcrVal : SdrAddr[23:1];
assign WriteFifoWriteEn = WbWrite & WbAddrStb & ~WriteFifoWriteFull;
assign WriteFifoWriteData = {WB_SEL_IN[3:2], WB_WR_DAT_IN[31:16], WB_SEL_IN[1:0], WB_WR_DAT_IN[15:0]};
assign WriteFifoReadEn = SdrDataStb & ~SdrWeb;
assign ReadFifoWriteEn = SdrDataStb & SdrWeb;
assign SdrByteEn = WriteFifoReadData[17:16];
assign SdrWriteData = WriteFifoReadData[15: 0];
assign SdrDataDriveEn = SdrOeb & SdrDataStb;
assign SdrDataStb = ~SdrCeb & SdrWaitValid & SDR_WAIT_IN;
assign WbRowWrapStall = (WbAddrCntVal > 3'd0) & (WB_ADR_IN[7:2] == 6'h00);
assign WB_STALL_OUT = (WB_CYC_IN & WB_STB_IN) & (WbReadStall | WbWriteStall | WbAsyncStall | WbRowWrapStall);
assign WB_ACK_OUT = (WbReadAck & ~ReadFifoReadEmpty) | WbWriteAck;
assign WB_ERR_OUT = WB_ADR_IN > (WBA + (2 ** 24));
assign SDR_ADDR_OUT = SdrAddrReg ;
assign SDR_CRE_OUT = SdrCre ;
assign SDR_ADVB_OUT = SdrAdvb ;
assign SDR_CEB_OUT = SdrCeb ;
assign SDR_OEB_OUT = SdrOeb ;
assign SDR_WEB_OUT = SdrWeb ;
assign SDR_LBB_OUT = (~SdrCeb & SdrWeb) ? 1'b0 : ~SdrByteEnReg[0] ;
assign SDR_UBB_OUT = (~SdrCeb & SdrWeb) ? 1'b0 : ~SdrByteEnReg[1] ;
assign SDR_DATA_INOUT = SdrDataDriveEn ? SdrWriteDataReg : 16'hzzzz;
assign SdrReadData = SDR_DATA_INOUT;
assign CLK_SDR_EN_OUT = ClkSdrEn;
always @(posedge CLK or posedge RST_ASYNC)
begin : CLK_SDR_EN_SR
if (RST_ASYNC)
begin
ClkSdrEn <= 1'b0;
end
else if (RST_SYNC)
begin
ClkSdrEn <= 1'b0;
end
else if (EN)
begin
if (ClkSdrEnSet)
begin
ClkSdrEn <= 1'b1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_WRITE_ACK_REG
if (RST_ASYNC)
begin
WbWriteAck <= 1'b0;
end
else if (RST_SYNC)
begin
WbWriteAck <= 1'b0;
end
else if (EN)
begin
WbWriteAck <= WriteFifoWriteEn;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_ADDR_REG
if (RST_ASYNC)
begin
SdrAddrReg <= 22'd0;
end
else if (RST_SYNC)
begin
SdrAddrReg <= 22'd0;
end
else if (EN)
begin
if (SdrAddrRegEn)
begin
SdrAddrReg <= SdrAddrMux;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_BYTE_EN_REG
if (RST_ASYNC)
begin
SdrByteEnReg <= 2'b00;
end
else if (RST_SYNC)
begin
SdrByteEnReg <= 2'b00;
end
else if (EN && !SdrCeb)
begin
SdrByteEnReg <= SdrByteEn;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_WRITE_DATA_REG
if (RST_ASYNC)
begin
SdrWriteDataReg <= 16'h0000;
end
else if (RST_SYNC)
begin
SdrWriteDataReg <= 16'h0000;
end
else if (EN && !SdrCeb)
begin
SdrWriteDataReg <= SdrWriteData;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_ADDR_CNT
if (RST_ASYNC)
begin
WbAddrCntVal <= 3'd0;
end
else if (RST_SYNC)
begin
WbAddrCntVal <= 3'd0;
end
else if (EN)
begin
if (WbAddrCntClr && WbAddrStb)
begin
WbAddrCntVal <= 3'd1;
end
else if (WbAddrCntClr)
begin
WbAddrCntVal <= 3'd0;
end
else if (WbAddrStb)
begin
WbAddrCntVal <= WbAddrCntVal + 3'd1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_DATA_CNT
if (RST_ASYNC)
begin
SdrDataCntVal <= 4'd0;
end
else if (RST_SYNC)
begin
SdrDataCntVal <= 4'd0;
end
else if (EN)
begin
if (SdrDataCntClr && SdrDataStb)
begin
SdrDataCntVal <= 4'd1;
end
else if (SdrDataStb)
begin
SdrDataCntVal <= SdrDataCntVal + 4'd1;
end
else if (SdrDataCntClr)
begin
SdrDataCntVal <= 4'd0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_ASYNC_CNT
if (RST_ASYNC)
begin
SdrAsyncCntVal <= 4'd0;
end
else if (RST_SYNC)
begin
SdrAsyncCntVal <= 4'd0;
end
else if (EN)
begin
if (SdrAsyncCntLd)
begin
SdrAsyncCntVal <= ASYNC_CLKS;
end
else if (| SdrAsyncCntVal)
begin
SdrAsyncCntVal <= SdrAsyncCntVal - 4'd1;
end
end
end
always @(*)
begin : SDRFSM_ST
SdrFsmStateNxt = SdrFsmStateCur;
WbReadAckNxt = 1'b0;
WbReadStallNxt = 1'b0;
WbWriteStallNxt = 1'b0;
WbAsyncStallNxt = 1'b0;
SdrCreNxt = 1'b0;
SdrAdvbNxt = 1'b1;
SdrCebNxt = 1'b1;
SdrOebNxt = 1'b1;
SdrWebNxt = 1'b1;
SdrBcrAddrbSel = 1'b0;
SdrAddrRegEn = 1'b0;
WbAddrCntClr = 1'b0;
SdrDataCntClr = 1'b0;
SdrAsyncCntLd = 1'b0;
ClkSdrEnSet = 1'b0;
SdrWaitValidNxt = 1'b0;
case (SdrFsmStateCur)
SDRFSM_IDLE :
begin
SdrCreNxt = 1'b1;
SdrAdvbNxt = 1'b0;
SdrCebNxt = 1'b0;
SdrBcrAddrbSel = 1'b1;
SdrAddrRegEn = 1'b1;
SdrAsyncCntLd = 1'b1;
WbAsyncStallNxt = 1'b1;
SdrFsmStateNxt = SDRFSM_BCR_WRITE_REQ;
end
SDRFSM_BCR_WRITE_REQ :
begin
SdrCreNxt = 1'b1;
SdrCebNxt = 1'b0;
SdrWebNxt = 1'b0;
WbAsyncStallNxt = 1'b1;
if (3'd1 == SdrAsyncCntVal)
begin
SdrCreNxt = 1'b0;
SdrCebNxt = 1'b1;
SdrWebNxt = 1'b1;
WbAddrCntClr = 1'b1;
SdrDataCntClr = 1'b1;
SdrFsmStateNxt = SDRFSM_BCR_WRITE_ACK;
end
end
SDRFSM_BCR_WRITE_ACK :
begin
ClkSdrEnSet = 1'b1;
SdrFsmStateNxt = SDRFSM_READY;
end
SDRFSM_READY :
begin
if (WbRead && WbAddrStb)
begin
SdrAddrRegEn = 1'b1;
SdrFsmStateNxt = SDRFSM_WB_READ_ADDR;
end
else if (WbWrite && WbAddrStb)
begin
SdrAddrRegEn = 1'b1;
SdrFsmStateNxt = SDRFSM_WB_WRITE_DATA;
end
end
SDRFSM_WB_READ_ADDR :
begin
if ((!WbAddrStb) || ((3'd3 == WbAddrCntVal) && WbAddrStb))
begin
SdrAdvbNxt = 1'b0;
SdrCebNxt = 1'b0;
WbReadStallNxt = 1'b1;
SdrFsmStateNxt = SDRFSM_SDR_READ_DATA;
end
end
SDRFSM_SDR_READ_DATA :
begin
SdrCebNxt = 1'b0;
SdrOebNxt = 1'b0;
SdrWaitValidNxt = 1'b1;
WbReadStallNxt = 1'b1;
if ((SdrDataCntVal == WbAddrCntValShift - 1) && SdrDataStb)
begin
SdrCebNxt = 1'b1;
SdrOebNxt = 1'b1;
WbReadAckNxt = 1'b1;
SdrWaitValidNxt = 1'b0;
SdrFsmStateNxt = SDRFSM_WB_READ_DATA;
end
end
SDRFSM_WB_READ_DATA :
begin
WbReadAckNxt = 1'b1;
WbReadStallNxt = 1'b1;
if ((3'd2 == SdrDataCntVal) || ReadFifoReadEmpty)
begin
WbReadAckNxt = 1'b0;
WbReadStallNxt = 1'b0;
WbAddrCntClr = 1'b1;
SdrDataCntClr = 1'b1;
SdrFsmStateNxt = SDRFSM_READY;
end
end
SDRFSM_WB_WRITE_DATA :
begin
if (!WbAddrStb || ((3'd3 == WbAddrCntVal) && WbAddrStb))
begin
SdrAdvbNxt = 1'b0;
SdrCebNxt = 1'b0;
SdrWebNxt = 1'b0;
WbWriteStallNxt = 1'b1;
SdrFsmStateNxt = SDRFSM_SDR_WRITE_DATA;
end
end
SDRFSM_SDR_WRITE_DATA :
begin
SdrCebNxt = 1'b0;
SdrWebNxt = 1'b0;
WbWriteStallNxt = 1'b1;
SdrWaitValidNxt = 1'b1;
if ((SdrDataCntVal == WbAddrCntValShift) && SdrDataStb)
begin
SdrCebNxt = 1'b1;
SdrWebNxt = 1'b1;
SdrWaitValidNxt = 1'b0;
SdrFsmStateNxt = SDRFSM_WRITE_END;
end
end
SDRFSM_WRITE_END :
begin
SdrDataCntClr = 1'b1;
WbAddrCntClr = 1'b1;
SdrFsmStateNxt = SDRFSM_READY;
end
default : SdrFsmStateNxt = SdrFsmStateCur;
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDRFSM_CP
if (RST_ASYNC)
begin
SdrFsmStateCur <= SDRFSM_IDLE;
WbReadAck <= 1'b0 ;
WbWriteStall <= 1'b0 ;
WbAsyncStall <= 1'b1 ;
SdrCre <= 1'b0 ;
SdrAdvb <= 1'b1 ;
SdrCeb <= 1'b1 ;
SdrOeb <= 1'b1 ;
SdrWeb <= 1'b1 ;
SdrWaitValid <= 1'b0;
end
else if (RST_SYNC)
begin
SdrFsmStateCur <= SDRFSM_IDLE;
WbReadAck <= 1'b0 ;
WbWriteStall <= 1'b0 ;
WbAsyncStall <= 1'b1 ;
SdrCre <= 1'b0 ;
SdrAdvb <= 1'b1 ;
SdrCeb <= 1'b1 ;
SdrOeb <= 1'b1 ;
SdrWeb <= 1'b1 ;
SdrWaitValid <= 1'b0;
end
else if (EN)
begin
SdrFsmStateCur <= SdrFsmStateNxt;
WbReadAck <= WbReadAckNxt ;
WbWriteStall <= WbWriteStallNxt ;
WbReadStall <= WbReadStallNxt ;
WbAsyncStall <= WbAsyncStallNxt ;
SdrCre <= SdrCreNxt ;
SdrAdvb <= SdrAdvbNxt ;
SdrCeb <= SdrCebNxt ;
SdrOeb <= SdrOebNxt ;
SdrWeb <= SdrWebNxt ;
SdrWaitValid <= SdrWaitValidNxt;
end
end
SYNC_FIFO
#(
.D_P2 ( 2),
.BW (18),
.WWM ( 2),
.RWM ( 1),
.USE_RAM ( 0)
)
sync_fifo_write_data
(
.WR_CLK (CLK ),
.RD_CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WRITE_EN_IN (WriteFifoWriteEn ),
.WRITE_DATA_IN (WriteFifoWriteData ),
.WRITE_FULL_OUT (WriteFifoWriteFull ),
.READ_EN_IN (WriteFifoReadEn ),
.READ_DATA_OUT (WriteFifoReadData ),
.READ_EMPTY_OUT (WriteFifoReadEmpty )
);
SYNC_FIFO
#(
.D_P2 ( 3),
.BW (16),
.WWM ( 1),
.RWM ( 2),
.USE_RAM ( 0)
)
sync_fifo_read_data
(
.WR_CLK (CLK ),
.RD_CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WRITE_EN_IN (ReadFifoWriteEn ),
.WRITE_DATA_IN (SdrReadData ),
.WRITE_FULL_OUT (ReadFifoWriteFull ),
.READ_EN_IN (WbReadAck ),
.READ_DATA_OUT (WB_RD_DAT_OUT ),
.READ_EMPTY_OUT (ReadFifoReadEmpty )
);
endmodule | module SDRAM_CONTROLLER
#(
parameter [31:0] WBA = 32'h0000_0000,
parameter WS_P2 = 24
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output CLK_SDR_EN_OUT ,
input [31:0] WB_ADR_IN ,
input WB_CYC_IN ,
input WB_STB_IN ,
input WB_WE_IN ,
input [ 3:0] WB_SEL_IN ,
input [ 2:0] WB_CTI_IN ,
input [ 1:0] WB_BTE_IN ,
output WB_ACK_OUT ,
output WB_STALL_OUT ,
output WB_ERR_OUT ,
input [31:0] WB_WR_DAT_IN ,
output [31:0] WB_RD_DAT_OUT ,
output [23:1] SDR_ADDR_OUT ,
output SDR_CRE_OUT ,
output SDR_ADVB_OUT ,
output SDR_CEB_OUT ,
output SDR_OEB_OUT ,
output SDR_WEB_OUT ,
input SDR_WAIT_IN ,
output SDR_LBB_OUT ,
output SDR_UBB_OUT ,
inout [15:0] SDR_DATA_INOUT
); |
`include "sdr_defs.v"
parameter WS_MSB = WS_P2 - 1;
parameter [3:0] ASYNC_CLKS = 4'd4;
wire WbRead ;
wire WbWrite ;
wire WbAddrStb ;
reg WbWriteAck ;
wire [22:0] SdrBcrVal = 23'd0
| BCR_RS_BCR << BCR_RS_LO
| BCR_OM_SYNC << BCR_OM
| BCR_IL_VAR << BCR_IL
| BCR_LC_C3 << BCR_LC_LO
| BCR_WP_LOW << BCR_WP
| BCR_WC_NONE << BCR_WC
| BCR_DS_HALF << BCR_DS_LO
| BCR_BW_NO_WRAP << BCR_BW
| BCR_BL_CONT << BCR_BL_LO;
wire [31:0] SdrAddr32b ;
wire [WS_MSB:0] SdrAddr ;
wire [WS_MSB:1] SdrAddrMux ;
reg [WS_MSB:1] SdrAddrReg ;
wire WriteFifoWriteEn ;
wire WriteFifoWriteFull ;
wire [35:0] WriteFifoWriteData ;
wire WriteFifoReadEn ;
wire WriteFifoReadEmpty ;
wire [17:0] WriteFifoReadData ;
wire [ 1:0] SdrByteEn ;
wire [15:0] SdrWriteData ;
reg [ 1:0] SdrByteEnReg ;
reg [15:0] SdrWriteDataReg ;
wire ReadFifoReadEmpty ;
wire ReadFifoWriteEn ;
wire ReadFifoWriteFull ;
wire SdrDriveEn ;
wire [15:0] SdrReadData ;
wire SdrDataStb ;
reg [2:0] WbAddrCntVal ;
wire [3:0] WbAddrCntValShift = {WbAddrCntVal, 1'b0};
reg [3:0] SdrDataCntVal ;
wire SdrDataDriveEn;
reg ClkSdrEnSet;
reg ClkSdrEn;
wire WbRowWrapStall;
parameter [3:0] SDRFSM_IDLE = 4'h0;
parameter [3:0] SDRFSM_BCR_WRITE_REQ = 4'h1;
parameter [3:0] SDRFSM_BCR_WRITE_ACK = 4'h2;
parameter [3:0] SDRFSM_READY = 4'h3;
parameter [3:0] SDRFSM_WB_READ_ADDR = 4'h4;
parameter [3:0] SDRFSM_SDR_READ_DATA = 4'h5;
parameter [3:0] SDRFSM_WB_READ_DATA = 4'h6;
parameter [3:0] SDRFSM_WB_WRITE_DATA = 4'h7;
parameter [3:0] SDRFSM_SDR_WRITE_DATA = 4'h8;
parameter [3:0] SDRFSM_WRITE_END = 4'h9;
reg [3:0] SdrFsmStateCur ;
reg [3:0] SdrFsmStateNxt ;
reg WbReadAckNxt ;
reg WbReadAck ;
reg WbWriteStallNxt ;
reg WbWriteStall ;
reg WbReadStallNxt ;
reg WbReadStall ;
reg WbAsyncStallNxt ;
reg WbAsyncStall ;
reg SdrCreNxt ;
reg SdrCre ;
reg SdrAdvbNxt ;
reg SdrAdvb ;
reg SdrCebNxt ;
reg SdrCeb ;
reg SdrOebNxt ;
reg SdrOeb ;
reg SdrWebNxt ;
reg SdrWeb ;
reg SdrWaitValidNxt ;
reg SdrWaitValid ;
reg SdrBcrAddrbSel ;
reg SdrAddrRegEn ;
reg WbAddrCntClr ;
reg SdrDataCntClr ;
reg SdrAsyncCntLd ;
reg [3:0] SdrAsyncCntVal ;
wire SdrDataEn;
assign WbRead = WB_CYC_IN & ~WB_WE_IN;
assign WbWrite = WB_CYC_IN & WB_WE_IN;
assign WbAddrStb = WB_CYC_IN & WB_STB_IN & ~WB_STALL_OUT;
assign SdrAddr32b = (WB_ADR_IN - WBA);
assign SdrAddr = {SdrAddr32b[WS_MSB:1], 1'b0};
assign SdrAddrMux = SdrBcrAddrbSel ? SdrBcrVal : SdrAddr[23:1];
assign WriteFifoWriteEn = WbWrite & WbAddrStb & ~WriteFifoWriteFull;
assign WriteFifoWriteData = {WB_SEL_IN[3:2], WB_WR_DAT_IN[31:16], WB_SEL_IN[1:0], WB_WR_DAT_IN[15:0]};
assign WriteFifoReadEn = SdrDataStb & ~SdrWeb;
assign ReadFifoWriteEn = SdrDataStb & SdrWeb;
assign SdrByteEn = WriteFifoReadData[17:16];
assign SdrWriteData = WriteFifoReadData[15: 0];
assign SdrDataDriveEn = SdrOeb & SdrDataStb;
assign SdrDataStb = ~SdrCeb & SdrWaitValid & SDR_WAIT_IN;
assign WbRowWrapStall = (WbAddrCntVal > 3'd0) & (WB_ADR_IN[7:2] == 6'h00);
assign WB_STALL_OUT = (WB_CYC_IN & WB_STB_IN) & (WbReadStall | WbWriteStall | WbAsyncStall | WbRowWrapStall);
assign WB_ACK_OUT = (WbReadAck & ~ReadFifoReadEmpty) | WbWriteAck;
assign WB_ERR_OUT = WB_ADR_IN > (WBA + (2 ** 24));
assign SDR_ADDR_OUT = SdrAddrReg ;
assign SDR_CRE_OUT = SdrCre ;
assign SDR_ADVB_OUT = SdrAdvb ;
assign SDR_CEB_OUT = SdrCeb ;
assign SDR_OEB_OUT = SdrOeb ;
assign SDR_WEB_OUT = SdrWeb ;
assign SDR_LBB_OUT = (~SdrCeb & SdrWeb) ? 1'b0 : ~SdrByteEnReg[0] ;
assign SDR_UBB_OUT = (~SdrCeb & SdrWeb) ? 1'b0 : ~SdrByteEnReg[1] ;
assign SDR_DATA_INOUT = SdrDataDriveEn ? SdrWriteDataReg : 16'hzzzz;
assign SdrReadData = SDR_DATA_INOUT;
assign CLK_SDR_EN_OUT = ClkSdrEn;
always @(posedge CLK or posedge RST_ASYNC)
begin : CLK_SDR_EN_SR
if (RST_ASYNC)
begin
ClkSdrEn <= 1'b0;
end
else if (RST_SYNC)
begin
ClkSdrEn <= 1'b0;
end
else if (EN)
begin
if (ClkSdrEnSet)
begin
ClkSdrEn <= 1'b1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_WRITE_ACK_REG
if (RST_ASYNC)
begin
WbWriteAck <= 1'b0;
end
else if (RST_SYNC)
begin
WbWriteAck <= 1'b0;
end
else if (EN)
begin
WbWriteAck <= WriteFifoWriteEn;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_ADDR_REG
if (RST_ASYNC)
begin
SdrAddrReg <= 22'd0;
end
else if (RST_SYNC)
begin
SdrAddrReg <= 22'd0;
end
else if (EN)
begin
if (SdrAddrRegEn)
begin
SdrAddrReg <= SdrAddrMux;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_BYTE_EN_REG
if (RST_ASYNC)
begin
SdrByteEnReg <= 2'b00;
end
else if (RST_SYNC)
begin
SdrByteEnReg <= 2'b00;
end
else if (EN && !SdrCeb)
begin
SdrByteEnReg <= SdrByteEn;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_WRITE_DATA_REG
if (RST_ASYNC)
begin
SdrWriteDataReg <= 16'h0000;
end
else if (RST_SYNC)
begin
SdrWriteDataReg <= 16'h0000;
end
else if (EN && !SdrCeb)
begin
SdrWriteDataReg <= SdrWriteData;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_ADDR_CNT
if (RST_ASYNC)
begin
WbAddrCntVal <= 3'd0;
end
else if (RST_SYNC)
begin
WbAddrCntVal <= 3'd0;
end
else if (EN)
begin
if (WbAddrCntClr && WbAddrStb)
begin
WbAddrCntVal <= 3'd1;
end
else if (WbAddrCntClr)
begin
WbAddrCntVal <= 3'd0;
end
else if (WbAddrStb)
begin
WbAddrCntVal <= WbAddrCntVal + 3'd1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_DATA_CNT
if (RST_ASYNC)
begin
SdrDataCntVal <= 4'd0;
end
else if (RST_SYNC)
begin
SdrDataCntVal <= 4'd0;
end
else if (EN)
begin
if (SdrDataCntClr && SdrDataStb)
begin
SdrDataCntVal <= 4'd1;
end
else if (SdrDataStb)
begin
SdrDataCntVal <= SdrDataCntVal + 4'd1;
end
else if (SdrDataCntClr)
begin
SdrDataCntVal <= 4'd0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDR_ASYNC_CNT
if (RST_ASYNC)
begin
SdrAsyncCntVal <= 4'd0;
end
else if (RST_SYNC)
begin
SdrAsyncCntVal <= 4'd0;
end
else if (EN)
begin
if (SdrAsyncCntLd)
begin
SdrAsyncCntVal <= ASYNC_CLKS;
end
else if (| SdrAsyncCntVal)
begin
SdrAsyncCntVal <= SdrAsyncCntVal - 4'd1;
end
end
end
always @(*)
begin : SDRFSM_ST
SdrFsmStateNxt = SdrFsmStateCur;
WbReadAckNxt = 1'b0;
WbReadStallNxt = 1'b0;
WbWriteStallNxt = 1'b0;
WbAsyncStallNxt = 1'b0;
SdrCreNxt = 1'b0;
SdrAdvbNxt = 1'b1;
SdrCebNxt = 1'b1;
SdrOebNxt = 1'b1;
SdrWebNxt = 1'b1;
SdrBcrAddrbSel = 1'b0;
SdrAddrRegEn = 1'b0;
WbAddrCntClr = 1'b0;
SdrDataCntClr = 1'b0;
SdrAsyncCntLd = 1'b0;
ClkSdrEnSet = 1'b0;
SdrWaitValidNxt = 1'b0;
case (SdrFsmStateCur)
SDRFSM_IDLE :
begin
SdrCreNxt = 1'b1;
SdrAdvbNxt = 1'b0;
SdrCebNxt = 1'b0;
SdrBcrAddrbSel = 1'b1;
SdrAddrRegEn = 1'b1;
SdrAsyncCntLd = 1'b1;
WbAsyncStallNxt = 1'b1;
SdrFsmStateNxt = SDRFSM_BCR_WRITE_REQ;
end
SDRFSM_BCR_WRITE_REQ :
begin
SdrCreNxt = 1'b1;
SdrCebNxt = 1'b0;
SdrWebNxt = 1'b0;
WbAsyncStallNxt = 1'b1;
if (3'd1 == SdrAsyncCntVal)
begin
SdrCreNxt = 1'b0;
SdrCebNxt = 1'b1;
SdrWebNxt = 1'b1;
WbAddrCntClr = 1'b1;
SdrDataCntClr = 1'b1;
SdrFsmStateNxt = SDRFSM_BCR_WRITE_ACK;
end
end
SDRFSM_BCR_WRITE_ACK :
begin
ClkSdrEnSet = 1'b1;
SdrFsmStateNxt = SDRFSM_READY;
end
SDRFSM_READY :
begin
if (WbRead && WbAddrStb)
begin
SdrAddrRegEn = 1'b1;
SdrFsmStateNxt = SDRFSM_WB_READ_ADDR;
end
else if (WbWrite && WbAddrStb)
begin
SdrAddrRegEn = 1'b1;
SdrFsmStateNxt = SDRFSM_WB_WRITE_DATA;
end
end
SDRFSM_WB_READ_ADDR :
begin
if ((!WbAddrStb) || ((3'd3 == WbAddrCntVal) && WbAddrStb))
begin
SdrAdvbNxt = 1'b0;
SdrCebNxt = 1'b0;
WbReadStallNxt = 1'b1;
SdrFsmStateNxt = SDRFSM_SDR_READ_DATA;
end
end
SDRFSM_SDR_READ_DATA :
begin
SdrCebNxt = 1'b0;
SdrOebNxt = 1'b0;
SdrWaitValidNxt = 1'b1;
WbReadStallNxt = 1'b1;
if ((SdrDataCntVal == WbAddrCntValShift - 1) && SdrDataStb)
begin
SdrCebNxt = 1'b1;
SdrOebNxt = 1'b1;
WbReadAckNxt = 1'b1;
SdrWaitValidNxt = 1'b0;
SdrFsmStateNxt = SDRFSM_WB_READ_DATA;
end
end
SDRFSM_WB_READ_DATA :
begin
WbReadAckNxt = 1'b1;
WbReadStallNxt = 1'b1;
if ((3'd2 == SdrDataCntVal) || ReadFifoReadEmpty)
begin
WbReadAckNxt = 1'b0;
WbReadStallNxt = 1'b0;
WbAddrCntClr = 1'b1;
SdrDataCntClr = 1'b1;
SdrFsmStateNxt = SDRFSM_READY;
end
end
SDRFSM_WB_WRITE_DATA :
begin
if (!WbAddrStb || ((3'd3 == WbAddrCntVal) && WbAddrStb))
begin
SdrAdvbNxt = 1'b0;
SdrCebNxt = 1'b0;
SdrWebNxt = 1'b0;
WbWriteStallNxt = 1'b1;
SdrFsmStateNxt = SDRFSM_SDR_WRITE_DATA;
end
end
SDRFSM_SDR_WRITE_DATA :
begin
SdrCebNxt = 1'b0;
SdrWebNxt = 1'b0;
WbWriteStallNxt = 1'b1;
SdrWaitValidNxt = 1'b1;
if ((SdrDataCntVal == WbAddrCntValShift) && SdrDataStb)
begin
SdrCebNxt = 1'b1;
SdrWebNxt = 1'b1;
SdrWaitValidNxt = 1'b0;
SdrFsmStateNxt = SDRFSM_WRITE_END;
end
end
SDRFSM_WRITE_END :
begin
SdrDataCntClr = 1'b1;
WbAddrCntClr = 1'b1;
SdrFsmStateNxt = SDRFSM_READY;
end
default : SdrFsmStateNxt = SdrFsmStateCur;
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : SDRFSM_CP
if (RST_ASYNC)
begin
SdrFsmStateCur <= SDRFSM_IDLE;
WbReadAck <= 1'b0 ;
WbWriteStall <= 1'b0 ;
WbAsyncStall <= 1'b1 ;
SdrCre <= 1'b0 ;
SdrAdvb <= 1'b1 ;
SdrCeb <= 1'b1 ;
SdrOeb <= 1'b1 ;
SdrWeb <= 1'b1 ;
SdrWaitValid <= 1'b0;
end
else if (RST_SYNC)
begin
SdrFsmStateCur <= SDRFSM_IDLE;
WbReadAck <= 1'b0 ;
WbWriteStall <= 1'b0 ;
WbAsyncStall <= 1'b1 ;
SdrCre <= 1'b0 ;
SdrAdvb <= 1'b1 ;
SdrCeb <= 1'b1 ;
SdrOeb <= 1'b1 ;
SdrWeb <= 1'b1 ;
SdrWaitValid <= 1'b0;
end
else if (EN)
begin
SdrFsmStateCur <= SdrFsmStateNxt;
WbReadAck <= WbReadAckNxt ;
WbWriteStall <= WbWriteStallNxt ;
WbReadStall <= WbReadStallNxt ;
WbAsyncStall <= WbAsyncStallNxt ;
SdrCre <= SdrCreNxt ;
SdrAdvb <= SdrAdvbNxt ;
SdrCeb <= SdrCebNxt ;
SdrOeb <= SdrOebNxt ;
SdrWeb <= SdrWebNxt ;
SdrWaitValid <= SdrWaitValidNxt;
end
end
SYNC_FIFO
#(
.D_P2 ( 2),
.BW (18),
.WWM ( 2),
.RWM ( 1),
.USE_RAM ( 0)
)
sync_fifo_write_data
(
.WR_CLK (CLK ),
.RD_CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WRITE_EN_IN (WriteFifoWriteEn ),
.WRITE_DATA_IN (WriteFifoWriteData ),
.WRITE_FULL_OUT (WriteFifoWriteFull ),
.READ_EN_IN (WriteFifoReadEn ),
.READ_DATA_OUT (WriteFifoReadData ),
.READ_EMPTY_OUT (WriteFifoReadEmpty )
);
SYNC_FIFO
#(
.D_P2 ( 3),
.BW (16),
.WWM ( 1),
.RWM ( 2),
.USE_RAM ( 0)
)
sync_fifo_read_data
(
.WR_CLK (CLK ),
.RD_CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WRITE_EN_IN (ReadFifoWriteEn ),
.WRITE_DATA_IN (SdrReadData ),
.WRITE_FULL_OUT (ReadFifoWriteFull ),
.READ_EN_IN (WbReadAck ),
.READ_DATA_OUT (WB_RD_DAT_OUT ),
.READ_EMPTY_OUT (ReadFifoReadEmpty )
);
endmodule | 1 |
138,390 | data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v | 83,270,534 | testcase.v | v | 85 | 104 | [] | [] | [] | null | line:13: before: "int" | null | 1: b'%Error: data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v:22: Unsupported: Dynamic array new\n Addr = new[BurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v:23: Unsupported: Dynamic array new\n WriteData = new[BurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v:24: Unsupported: Dynamic array new\n ReadData = new[BurstLength];\n ^~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v:34: Unsupported or unknown PLI call: $urandom\n WriteData[i] = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v:38: syntax error, unexpected \'@\'\n @(negedge SDRAM_CONTROLLER_TB.Rst);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v:59: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/burst_access/row_wrap/testcase.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10us;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,280 | module | module TESTCASE ();
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
initial
begin
const int BurstLength = 8;
const int AddrBase = 32'h0000_00f0;
int testPass = 1;
int Addr [];
int WriteData [];
int ReadData [];
Addr = new[BurstLength];
WriteData = new[BurstLength];
ReadData = new[BurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = AddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
`BFM.wbBurstWrite32b(Addr, WriteData);
`BFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
#1000ns;
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
$finish();
end
initial
begin
#10us;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
initial
begin
const int BurstLength = 8;
const int AddrBase = 32'h0000_00f0;
int testPass = 1;
int Addr [];
int WriteData [];
int ReadData [];
Addr = new[BurstLength];
WriteData = new[BurstLength];
ReadData = new[BurstLength];
foreach (Addr[i])
begin : ADDR_STORE
Addr[i] = AddrBase + (i << 2);
end
foreach (WriteData[i])
begin : WRITE_DATA_RANDOMISE
WriteData[i] = $urandom();
end
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
`BFM.wbBurstWrite32b(Addr, WriteData);
`BFM.wbBurstRead32b(Addr, ReadData);
$display("[INFO ] Verifying Read Data ...");
foreach (WriteData[i])
begin : READ_DATA_CHECK
if (ReadData[i] == WriteData[i])
begin
$display("[INFO ] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
end
else
begin
$display("[ERROR] Index %02d : Write Data = 0x%x, Read Data = 0x%x", i, WriteData[i], ReadData[i]);
testPass = 0;
end
end
#1000ns;
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
$finish();
end
initial
begin
#10us;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,391 | data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_fill/testcase.v | 83,270,534 | testcase.v | v | 149 | 170 | [] | [] | [] | null | line:17: before: "int" | null | 1: b'%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_fill/testcase.v:35: Unsupported or unknown PLI call: $urandom\n randomData[dataLoop] = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_fill/testcase.v:40: syntax error, unexpected \'@\'\n @(negedge SDRAM_CONTROLLER_TB.Rst);\n ^\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_fill/testcase.v:51: Unsupported or unknown PLI call: $urandom_range\n fillType = $urandom_range(0, 2);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_fill/testcase.v:80: Unsupported or unknown PLI call: $urandom_range\n fillType = $urandom_range(0, 2);\n ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_fill/testcase.v:133: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,282 | module | module TESTCASE ();
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
parameter RAM_SIZE_32B = 2 ** 22;
logic [31:0] randomData [RAM_SIZE_32B-1:0];
initial
begin
const int addrInc = 32'h0000_1000;
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData32 [3:0] ;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
for (dataLoop = 0 ; dataLoop < RAM_SIZE_32B ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $urandom();
end
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Filling Memory (mixed accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop = addrLoop + addrInc)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`BFM.wbWrite((addrLoop << 2), 4'b1000, {randomData[addrLoop][31:24], 24'hDEADDE});
`BFM.wbWrite((addrLoop << 2), 4'b0010, {16'hDEAD, randomData[addrLoop][15: 8], 8'hDE});
`BFM.wbWrite((addrLoop << 2), 4'b0001, {24'hDEADDE, randomData[addrLoop][ 7: 0]});
`BFM.wbWrite((addrLoop << 2), 4'b0100, {8'hDE, randomData[addrLoop][23:16], 16'hDEAD});
end
1 :
begin
`BFM.wbWrite((addrLoop << 2), 4'b1100, {randomData[addrLoop][31:16], 16'hDEAD});
`BFM.wbWrite((addrLoop << 2), 4'b0011, {16'hDEAD, randomData[addrLoop][15: 0]});
end
2 :
begin
`BFM.wbWrite((addrLoop << 2), 4'b1111, randomData[addrLoop][31: 0]);
end
endcase
end
$display("[INFO ] Reading back memory contents (word accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop = addrLoop + addrInc)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`BFM.wbRead((addrLoop << 2), 4'b0100, readData32[2]);
`BFM.wbRead((addrLoop << 2), 4'b0010, readData32[1]);
`BFM.wbRead((addrLoop << 2), 4'b1000, readData32[3]);
`BFM.wbRead((addrLoop << 2), 4'b0001, readData32[0]);
readData = {readData32[3][31:24], readData32[2][23:16], readData32[1][15:8], readData32[0][7:0]};
end
1 :
begin
`BFM.wbRead((addrLoop << 2), 4'b1100, readData32[1]);
`BFM.wbRead((addrLoop << 2), 4'b0011, readData32[0]);
readData = {readData32[1][31:16], readData32[0][15:0]};
end
2 :
begin
`BFM.wbRead((addrLoop << 2), 4'b1111, readData);
end
endcase
if (randomData[addrLoop] === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", addrLoop << 2, $time);
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x FAILED, Read 0x%x, Expected 0x%x at time %t", addrLoop << 2, readData, randomData[addrLoop], $time);
testPass = 0;
end
end
if (testPass)
begin
$display("");
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
endmodule | module TESTCASE (); |
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
parameter RAM_SIZE_32B = 2 ** 22;
logic [31:0] randomData [RAM_SIZE_32B-1:0];
initial
begin
const int addrInc = 32'h0000_1000;
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData32 [3:0] ;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
for (dataLoop = 0 ; dataLoop < RAM_SIZE_32B ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $urandom();
end
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Filling Memory (mixed accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop = addrLoop + addrInc)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`BFM.wbWrite((addrLoop << 2), 4'b1000, {randomData[addrLoop][31:24], 24'hDEADDE});
`BFM.wbWrite((addrLoop << 2), 4'b0010, {16'hDEAD, randomData[addrLoop][15: 8], 8'hDE});
`BFM.wbWrite((addrLoop << 2), 4'b0001, {24'hDEADDE, randomData[addrLoop][ 7: 0]});
`BFM.wbWrite((addrLoop << 2), 4'b0100, {8'hDE, randomData[addrLoop][23:16], 16'hDEAD});
end
1 :
begin
`BFM.wbWrite((addrLoop << 2), 4'b1100, {randomData[addrLoop][31:16], 16'hDEAD});
`BFM.wbWrite((addrLoop << 2), 4'b0011, {16'hDEAD, randomData[addrLoop][15: 0]});
end
2 :
begin
`BFM.wbWrite((addrLoop << 2), 4'b1111, randomData[addrLoop][31: 0]);
end
endcase
end
$display("[INFO ] Reading back memory contents (word accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop = addrLoop + addrInc)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`BFM.wbRead((addrLoop << 2), 4'b0100, readData32[2]);
`BFM.wbRead((addrLoop << 2), 4'b0010, readData32[1]);
`BFM.wbRead((addrLoop << 2), 4'b1000, readData32[3]);
`BFM.wbRead((addrLoop << 2), 4'b0001, readData32[0]);
readData = {readData32[3][31:24], readData32[2][23:16], readData32[1][15:8], readData32[0][7:0]};
end
1 :
begin
`BFM.wbRead((addrLoop << 2), 4'b1100, readData32[1]);
`BFM.wbRead((addrLoop << 2), 4'b0011, readData32[0]);
readData = {readData32[1][31:16], readData32[0][15:0]};
end
2 :
begin
`BFM.wbRead((addrLoop << 2), 4'b1111, readData);
end
endcase
if (randomData[addrLoop] === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", addrLoop << 2, $time);
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x FAILED, Read 0x%x, Expected 0x%x at time %t", addrLoop << 2, readData, randomData[addrLoop], $time);
testPass = 0;
end
end
if (testPass)
begin
$display("");
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
endmodule | 1 |
138,392 | data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v | 83,270,534 | testcase.v | v | 90 | 70 | [] | [] | [] | null | line:12: before: "Addr" | null | 1: b'%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v:20: syntax error, unexpected \'@\'\n @(negedge SDRAM_CONTROLLER_TB.Rst);\n ^\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v:23: Unsupported or unknown PLI call: $urandom\n writeData =$urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v:30: Unsupported or unknown PLI call: $urandom\n writeData =$urandom(); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v:40: Unsupported or unknown PLI call: $urandom\n writeData =$urandom(); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/mixed_widths/testcase.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10ms;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 302,283 | module | module TESTCASE ();
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
initial
begin
int Addr;
int writeData;
int readData;
bit verifyOk = 0;
bit testPass = 1;
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
writeData =$urandom();
Addr = 32'h0000_0100;
`BFM.wbWrite(Addr, 4'b1111, writeData);
`BFM.wbRead (Addr, 4'b1111, readData );
if (writeData != readData) testPass = 0;
writeData =$urandom();
Addr = 32'h0000_0200;
`BFM.wbWrite (Addr, 4'b0011, writeData);
`BFM.wbRead (Addr, 4'b0011, readData );
if (writeData[15:0] != readData[15:0]) testPass = 0;
`BFM.wbWrite (Addr+4, 4'b1100, writeData);
`BFM.wbRead (Addr+4, 4'b1100, readData );
if (writeData[31:16] != readData[31:16]) testPass = 0;
writeData =$urandom();
Addr = 32'h0000_0300;
`BFM.wbWrite (Addr , 4'b0001, writeData);
`BFM.wbRead (Addr , 4'b0001, readData );
if (writeData[7:0] != readData[7:0]) testPass = 0;
`BFM.wbWrite (Addr+4 , 4'b0010, writeData);
`BFM.wbRead (Addr+4 , 4'b0010, readData );
if (writeData[15:8] != readData[15:8]) testPass = 0;
`BFM.wbWrite (Addr+8 , 4'b0100, writeData);
`BFM.wbRead (Addr+8 , 4'b0100, readData );
if (writeData[23:16] != readData[23:16]) testPass = 0;
`BFM.wbWrite (Addr+12, 4'b1000, writeData);
`BFM.wbRead (Addr+12, 4'b1000, readData );
if (writeData[31:24] != readData[31:24]) testPass = 0;
#1000ns;
if (testPass)
begin
$display("");
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
initial
begin
#10ms;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
initial
begin
int Addr;
int writeData;
int readData;
bit verifyOk = 0;
bit testPass = 1;
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
writeData =$urandom();
Addr = 32'h0000_0100;
`BFM.wbWrite(Addr, 4'b1111, writeData);
`BFM.wbRead (Addr, 4'b1111, readData );
if (writeData != readData) testPass = 0;
writeData =$urandom();
Addr = 32'h0000_0200;
`BFM.wbWrite (Addr, 4'b0011, writeData);
`BFM.wbRead (Addr, 4'b0011, readData );
if (writeData[15:0] != readData[15:0]) testPass = 0;
`BFM.wbWrite (Addr+4, 4'b1100, writeData);
`BFM.wbRead (Addr+4, 4'b1100, readData );
if (writeData[31:16] != readData[31:16]) testPass = 0;
writeData =$urandom();
Addr = 32'h0000_0300;
`BFM.wbWrite (Addr , 4'b0001, writeData);
`BFM.wbRead (Addr , 4'b0001, readData );
if (writeData[7:0] != readData[7:0]) testPass = 0;
`BFM.wbWrite (Addr+4 , 4'b0010, writeData);
`BFM.wbRead (Addr+4 , 4'b0010, readData );
if (writeData[15:8] != readData[15:8]) testPass = 0;
`BFM.wbWrite (Addr+8 , 4'b0100, writeData);
`BFM.wbRead (Addr+8 , 4'b0100, readData );
if (writeData[23:16] != readData[23:16]) testPass = 0;
`BFM.wbWrite (Addr+12, 4'b1000, writeData);
`BFM.wbRead (Addr+12, 4'b1000, readData );
if (writeData[31:24] != readData[31:24]) testPass = 0;
#1000ns;
if (testPass)
begin
$display("");
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
initial
begin
#10ms;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,393 | data/full_repos/permissive/83270534/sdram_controller/sim/single_access/simple/testcase.v | 83,270,534 | testcase.v | v | 61 | 70 | [] | [] | [] | null | line:12: before: "writeData" | null | 1: b'%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/simple/testcase.v:19: syntax error, unexpected \'@\'\n @(negedge SDRAM_CONTROLLER_TB.Rst);\n ^\n%Error: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/simple/testcase.v:22: Unsupported or unknown PLI call: $urandom\n writeData =$urandom();\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/simple/testcase.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/sdram_controller/sim/single_access/simple/testcase.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10ms;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 302,284 | module | module TESTCASE ();
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
initial
begin
int writeData;
int readData;
bit verifyOk = 0;
bit testPass = 0;
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
writeData =$urandom();
`BFM.wbWrite (32'h0000_0100, 4'b1111, writeData);
`BFM.wbRead (32'h0000_0100, 4'b1111, readData );
if (writeData == readData) testPass = 1;
if (testPass)
begin
$display("");
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
initial
begin
#10ms;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`define TB SDRAM_CONTROLLER_TB
`define BFM SDRAM_CONTROLLER_TB.wb_master_bfm
initial
begin
int writeData;
int readData;
bit verifyOk = 0;
bit testPass = 0;
@(negedge `TB.Rst);
$display("[INFO ] Reset de-asserted at time %t", $time);
writeData =$urandom();
`BFM.wbWrite (32'h0000_0100, 4'b1111, writeData);
`BFM.wbRead (32'h0000_0100, 4'b1111, readData );
if (writeData == readData) testPass = 1;
if (testPass)
begin
$display("");
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("");
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
initial
begin
#10ms;
$display("[FAIL] SDRAM test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,395 | data/full_repos/permissive/83270534/venus/rtl/digital_top.v | 83,270,534 | digital_top.v | v | 454 | 125 | [] | [] | [] | [(16, 436)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/venus/rtl/digital_top.v:215: Cannot find file containing module: 'ADI_TOP'\n ADI_TOP adi_top\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/venus/rtl,data/full_repos/permissive/83270534/ADI_TOP\n data/full_repos/permissive/83270534/venus/rtl,data/full_repos/permissive/83270534/ADI_TOP.v\n data/full_repos/permissive/83270534/venus/rtl,data/full_repos/permissive/83270534/ADI_TOP.sv\n ADI_TOP\n ADI_TOP.v\n ADI_TOP.sv\n obj_dir/ADI_TOP\n obj_dir/ADI_TOP.v\n obj_dir/ADI_TOP.sv\n%Error: data/full_repos/permissive/83270534/venus/rtl/digital_top.v:249: Cannot find file containing module: 'VGA_TOP'\n VGA_TOP \n ^~~~~~~\n%Error: data/full_repos/permissive/83270534/venus/rtl/digital_top.v:310: Cannot find file containing module: 'WB_ARB_2M_1S'\n WB_ARB_2M_1S wb_arb_2m_1s\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/venus/rtl/digital_top.v:393: Cannot find file containing module: 'SDRAM_CONTROLLER'\n SDRAM_CONTROLLER \n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,310 | module | module DIGITAL_TOP
(
input CLK_33M ,
input CLK_25M ,
input CLK_SDR_33M ,
input RST_ASYNC_33M ,
input RST_ASYNC_25M ,
input RST_ASYNC_SDR_33M ,
input DCMS_LOCKED_IN ,
input [ 3:0] BTN_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output FLASH_CS_OUT ,
output FLASH_RP_OUT ,
input FLASH_ST_STS_IN ,
output [ 7:0] LED_OUT ,
output [23:1] MEM_ADDR_OUT ,
inout [15:0] MEM_DATA_INOUT ,
output MEM_OE_OUT ,
output MEM_WR_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
output RAM_ADV_OUT ,
output RAM_CLK_EN_OUT ,
output RAM_CRE_OUT ,
output RAM_CS_OUT ,
output RAM_LB_OUT ,
output RAM_UB_OUT ,
input RAM_WAIT_IN ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
output [3:0] SSEG_AN_OUT ,
output [7:0] SSEG_K_OUT ,
input [7:0] SW_IN ,
output [1:0] USB_ADDR_OUT ,
input USB_CLK_IN ,
inout [7:0] USB_DATA_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output [1:0] VGA_BLUE_OUT ,
output [2:0] VGA_GREEN_OUT ,
output VGA_HSYNC_OUT ,
output [2:0] VGA_RED_OUT ,
output VGA_VSYNC_OUT
);
parameter X_MSB = 9;
parameter Y_MSB = 8;
parameter [1:0] PSX_16B = 2'b00;
parameter [1:0] PSX_24B = 2'b01;
parameter [1:0] RGB_8B = 2'b10;
parameter [1:0] RGB_24B = 2'b11;
parameter [X_MSB:0] VGA_WIDTH_16B_COL = 640;
parameter [X_MSB:0] VGA_WIDTH_24B_COL = VGA_WIDTH_16B_COL * (3/2);
wire AdiWbArbReq ;
wire AdiWbArbGnt ;
wire [31:0] AdiWbAdr ;
wire AdiWbCyc ;
wire AdiWbStb ;
wire AdiWbWe ;
wire [ 3:0] AdiWbSel ;
wire AdiWbStall ;
wire AdiWbAck ;
wire AdiWbErr ;
wire [31:0] AdiWbRdDat ;
wire [31:0] AdiWbWrDat ;
wire VgaWbArbReq ;
wire VgaWbArbGnt ;
wire [31:0] VgaWbAdr ;
wire VgaWbCyc ;
wire VgaWbStb ;
wire VgaWbWe ;
wire [ 3:0] VgaWbSel ;
wire VgaWbStall ;
wire VgaWbAck ;
wire VgaWbErr ;
wire [31:0] VgaWbRdDat ;
wire [31:0] VgaWbWrDat ;
wire [31:0] SdramWbAdr ;
wire SdramWbCyc ;
wire SdramWbStb ;
wire SdramWbWe ;
wire [ 3:0] SdramWbSel ;
wire SdramWbStall ;
wire SdramWbAck ;
wire SdramWbErr ;
wire [31:0] SdramWbRdDat ;
wire [31:0] SdramWbWrDat ;
reg [2:0] Sw0Resync33M;
reg [2:0] Sw0Resync25M;
reg [2:0] Sw1Resync25M;
assign LED_OUT = {AdiWbArbReq ,
AdiWbArbGnt ,
AdiWbCyc ,
AdiWbAck ,
VgaWbArbReq ,
VgaWbArbGnt ,
SdramWbCyc ,
DCMS_LOCKED_IN
};
always @(posedge CLK_33M or posedge RST_ASYNC_33M)
begin : SW_0_33M_RESYNC
if (RST_ASYNC_33M)
begin
Sw0Resync33M <= 3'b000;
end
else
begin
Sw0Resync33M <= {SW_IN[0], Sw0Resync33M[2:1]};
end
end
always @(posedge CLK_25M or posedge RST_ASYNC_25M)
begin : SW_0_25M_RESYNC
if (RST_ASYNC_25M)
begin
Sw0Resync25M <= 3'b000;
end
else
begin
Sw0Resync25M <= {SW_IN[0], Sw0Resync25M[2:1]};
end
end
always @(posedge CLK_25M or posedge RST_ASYNC_25M)
begin : SW_1_25M_RESYNC
if (RST_ASYNC_25M)
begin
Sw1Resync25M <= 3'b000;
end
else
begin
Sw1Resync25M <= {SW_IN[1], Sw1Resync25M[2:1]};
end
end
ADI_TOP adi_top
(
.CLK (CLK_33M ),
.EN (1'b1 ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC_33M ),
.EPP_DATA_INOUT (USB_DATA_INOUT ),
.EPP_WRITE_IN (USB_FLAG_IN ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.EPP_INT_OUT ( ),
.EPP_RESET_IN (1'b0 ),
.WB_ARB_REQ_OUT (AdiWbArbReq ),
.WB_ARB_GNT_IN (AdiWbArbGnt ),
.WB_ADR_OUT (AdiWbAdr ),
.WB_CYC_OUT (AdiWbCyc ),
.WB_STB_OUT (AdiWbStb ),
.WB_WE_OUT (AdiWbWe ),
.WB_SEL_OUT (AdiWbSel ),
.WB_STALL_IN (AdiWbStall ),
.WB_ACK_IN (AdiWbAck ),
.WB_ERR_IN (AdiWbErr ),
.WB_RD_DAT_IN (AdiWbRdDat ),
.WB_WR_DAT_OUT (AdiWbWrDat )
);
VGA_TOP
#(.X_MSB (X_MSB),
.Y_MSB (Y_MSB)
)
vga_top
(
.CLK_VGA (CLK_25M ),
.EN_VGA (Sw0Resync25M[0] ),
.RST_SYNC_VGA (~Sw0Resync25M[0] ),
.RST_ASYNC_VGA (RST_ASYNC_25M ),
.CLK_WB (CLK_33M ),
.EN_WB (Sw0Resync33M[0] ),
.RST_SYNC_WB (~Sw0Resync33M[0] ),
.RST_ASYNC_WB (RST_ASYNC_33M ),
.WB_ARB_REQ_OUT (VgaWbArbReq ),
.WB_ARB_GNT_IN (VgaWbArbGnt ),
.VGA_TEST_EN_IN (Sw1Resync25M[0]),
.WB_ADR_OUT (VgaWbAdr ),
.WB_CYC_OUT (VgaWbCyc ),
.WB_STB_OUT (VgaWbStb ),
.WB_WE_OUT (VgaWbWe ),
.WB_SEL_OUT (VgaWbSel ),
.WB_STALL_IN (VgaWbStall ),
.WB_ACK_IN (VgaWbAck ),
.WB_ERR_IN (VgaWbErr ),
.WB_RD_DAT_IN (VgaWbRdDat ),
.WB_WR_DAT_OUT (VgaWbWrDat ),
.VGA_VS_OUT (VGA_VSYNC_OUT ),
.VGA_HS_OUT (VGA_HSYNC_OUT ),
.VGA_RED_OUT (VGA_RED_OUT ),
.VGA_GREEN_OUT (VGA_GREEN_OUT ),
.VGA_BLUE_OUT (VGA_BLUE_OUT ),
.CFG_DITHER_IN (1'b0 ),
.CFG_LINEAR_FB_IN (1'b1 ),
.CFG_PIXEL_FMT_IN (RGB_24B ),
.CFG_BASE_ADDR_IN (12'd0 ),
.CFG_TOP_LEFT_X_IN ({X_MSB+1{1'b0}} ),
.CFG_TOP_LEFT_Y_IN ({Y_MSB+1{1'b0}} ),
.CFG_START_X_IN ({X_MSB+1{1'b0}} ),
.CFG_END_X_IN (VGA_WIDTH_24B_COL ),
.CFG_START_Y_IN ({Y_MSB+1{1'b0}} ),
.CFG_END_Y_IN (9'd480 )
);
WB_ARB_2M_1S wb_arb_2m_1s
(
.CLK (CLK_33M ),
.EN (1'b1 ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC_33M ),
.WB_ARB_REQ_IN ({AdiWbArbReq, VgaWbArbReq} ),
.WB_ARB_GNT_OUT ({AdiWbArbGnt, VgaWbArbGnt} ),
.WB_SL0_ADR_IN (VgaWbAdr ),
.WB_SL0_CYC_IN (VgaWbCyc ),
.WB_SL0_STB_IN (VgaWbStb ),
.WB_SL0_WE_IN (VgaWbWe ),
.WB_SL0_SEL_IN (VgaWbSel ),
.WB_SL0_STALL_OUT (VgaWbStall ),
.WB_SL0_ACK_OUT (VgaWbAck ),
.WB_SL0_ERR_OUT (VgaWbErr ),
.WB_SL0_RD_DAT_OUT (VgaWbRdDat ),
.WB_SL0_WR_DAT_IN (VgaWbWrDat ),
.WB_SL1_ADR_IN (AdiWbAdr ),
.WB_SL1_CYC_IN (AdiWbCyc ),
.WB_SL1_STB_IN (AdiWbStb ),
.WB_SL1_WE_IN (AdiWbWe ),
.WB_SL1_SEL_IN (AdiWbSel ),
.WB_SL1_STALL_OUT (AdiWbStall ),
.WB_SL1_ACK_OUT (AdiWbAck ),
.WB_SL1_ERR_OUT (AdiWbErr ),
.WB_SL1_RD_DAT_OUT (AdiWbRdDat ),
.WB_SL1_WR_DAT_IN (AdiWbWrDat ),
.WB_M0_ADR_OUT (SdramWbAdr ),
.WB_M0_CYC_OUT (SdramWbCyc ),
.WB_M0_STB_OUT (SdramWbStb ),
.WB_M0_WE_OUT (SdramWbWe ),
.WB_M0_SEL_OUT (SdramWbSel ),
.WB_M0_STALL_IN (SdramWbStall ),
.WB_M0_ACK_IN (SdramWbAck ),
.WB_M0_ERR_IN (SdramWbErr ),
.WB_M0_RD_DAT_IN (SdramWbRdDat ),
.WB_M0_WR_DAT_OUT (SdramWbWrDat )
);
SDRAM_CONTROLLER
#(
.WBA (32'h0000_0000),
.WS_P2 (24)
)
sdram_controller
(
.CLK (CLK_33M ),
.EN (1'b1 ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC_33M ),
.CLK_SDR_EN_OUT (RAM_CLK_EN_OUT ),
.WB_ADR_IN (SdramWbAdr ),
.WB_CYC_IN (SdramWbCyc ),
.WB_STB_IN (SdramWbStb ),
.WB_WE_IN (SdramWbWe ),
.WB_SEL_IN (SdramWbSel ),
.WB_CTI_IN (3'b000 ),
.WB_BTE_IN (2'b00 ),
.WB_ACK_OUT (SdramWbAck ),
.WB_STALL_OUT (SdramWbStall ),
.WB_ERR_OUT (SdramWbErr ),
.WB_WR_DAT_IN (SdramWbWrDat ),
.WB_RD_DAT_OUT (SdramWbRdDat ),
.SDR_ADDR_OUT (MEM_ADDR_OUT ),
.SDR_CRE_OUT (RAM_CRE_OUT ),
.SDR_ADVB_OUT (RAM_ADV_OUT ),
.SDR_CEB_OUT (RAM_CS_OUT ),
.SDR_OEB_OUT (MEM_OE_OUT ),
.SDR_WEB_OUT (MEM_WR_OUT ),
.SDR_WAIT_IN (RAM_WAIT_IN ),
.SDR_LBB_OUT (RAM_LB_OUT ),
.SDR_UBB_OUT (RAM_UB_OUT ),
.SDR_DATA_INOUT (MEM_DATA_INOUT )
);
endmodule | module DIGITAL_TOP
(
input CLK_33M ,
input CLK_25M ,
input CLK_SDR_33M ,
input RST_ASYNC_33M ,
input RST_ASYNC_25M ,
input RST_ASYNC_SDR_33M ,
input DCMS_LOCKED_IN ,
input [ 3:0] BTN_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output FLASH_CS_OUT ,
output FLASH_RP_OUT ,
input FLASH_ST_STS_IN ,
output [ 7:0] LED_OUT ,
output [23:1] MEM_ADDR_OUT ,
inout [15:0] MEM_DATA_INOUT ,
output MEM_OE_OUT ,
output MEM_WR_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
output RAM_ADV_OUT ,
output RAM_CLK_EN_OUT ,
output RAM_CRE_OUT ,
output RAM_CS_OUT ,
output RAM_LB_OUT ,
output RAM_UB_OUT ,
input RAM_WAIT_IN ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
output [3:0] SSEG_AN_OUT ,
output [7:0] SSEG_K_OUT ,
input [7:0] SW_IN ,
output [1:0] USB_ADDR_OUT ,
input USB_CLK_IN ,
inout [7:0] USB_DATA_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output [1:0] VGA_BLUE_OUT ,
output [2:0] VGA_GREEN_OUT ,
output VGA_HSYNC_OUT ,
output [2:0] VGA_RED_OUT ,
output VGA_VSYNC_OUT
); |
parameter X_MSB = 9;
parameter Y_MSB = 8;
parameter [1:0] PSX_16B = 2'b00;
parameter [1:0] PSX_24B = 2'b01;
parameter [1:0] RGB_8B = 2'b10;
parameter [1:0] RGB_24B = 2'b11;
parameter [X_MSB:0] VGA_WIDTH_16B_COL = 640;
parameter [X_MSB:0] VGA_WIDTH_24B_COL = VGA_WIDTH_16B_COL * (3/2);
wire AdiWbArbReq ;
wire AdiWbArbGnt ;
wire [31:0] AdiWbAdr ;
wire AdiWbCyc ;
wire AdiWbStb ;
wire AdiWbWe ;
wire [ 3:0] AdiWbSel ;
wire AdiWbStall ;
wire AdiWbAck ;
wire AdiWbErr ;
wire [31:0] AdiWbRdDat ;
wire [31:0] AdiWbWrDat ;
wire VgaWbArbReq ;
wire VgaWbArbGnt ;
wire [31:0] VgaWbAdr ;
wire VgaWbCyc ;
wire VgaWbStb ;
wire VgaWbWe ;
wire [ 3:0] VgaWbSel ;
wire VgaWbStall ;
wire VgaWbAck ;
wire VgaWbErr ;
wire [31:0] VgaWbRdDat ;
wire [31:0] VgaWbWrDat ;
wire [31:0] SdramWbAdr ;
wire SdramWbCyc ;
wire SdramWbStb ;
wire SdramWbWe ;
wire [ 3:0] SdramWbSel ;
wire SdramWbStall ;
wire SdramWbAck ;
wire SdramWbErr ;
wire [31:0] SdramWbRdDat ;
wire [31:0] SdramWbWrDat ;
reg [2:0] Sw0Resync33M;
reg [2:0] Sw0Resync25M;
reg [2:0] Sw1Resync25M;
assign LED_OUT = {AdiWbArbReq ,
AdiWbArbGnt ,
AdiWbCyc ,
AdiWbAck ,
VgaWbArbReq ,
VgaWbArbGnt ,
SdramWbCyc ,
DCMS_LOCKED_IN
};
always @(posedge CLK_33M or posedge RST_ASYNC_33M)
begin : SW_0_33M_RESYNC
if (RST_ASYNC_33M)
begin
Sw0Resync33M <= 3'b000;
end
else
begin
Sw0Resync33M <= {SW_IN[0], Sw0Resync33M[2:1]};
end
end
always @(posedge CLK_25M or posedge RST_ASYNC_25M)
begin : SW_0_25M_RESYNC
if (RST_ASYNC_25M)
begin
Sw0Resync25M <= 3'b000;
end
else
begin
Sw0Resync25M <= {SW_IN[0], Sw0Resync25M[2:1]};
end
end
always @(posedge CLK_25M or posedge RST_ASYNC_25M)
begin : SW_1_25M_RESYNC
if (RST_ASYNC_25M)
begin
Sw1Resync25M <= 3'b000;
end
else
begin
Sw1Resync25M <= {SW_IN[1], Sw1Resync25M[2:1]};
end
end
ADI_TOP adi_top
(
.CLK (CLK_33M ),
.EN (1'b1 ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC_33M ),
.EPP_DATA_INOUT (USB_DATA_INOUT ),
.EPP_WRITE_IN (USB_FLAG_IN ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.EPP_INT_OUT ( ),
.EPP_RESET_IN (1'b0 ),
.WB_ARB_REQ_OUT (AdiWbArbReq ),
.WB_ARB_GNT_IN (AdiWbArbGnt ),
.WB_ADR_OUT (AdiWbAdr ),
.WB_CYC_OUT (AdiWbCyc ),
.WB_STB_OUT (AdiWbStb ),
.WB_WE_OUT (AdiWbWe ),
.WB_SEL_OUT (AdiWbSel ),
.WB_STALL_IN (AdiWbStall ),
.WB_ACK_IN (AdiWbAck ),
.WB_ERR_IN (AdiWbErr ),
.WB_RD_DAT_IN (AdiWbRdDat ),
.WB_WR_DAT_OUT (AdiWbWrDat )
);
VGA_TOP
#(.X_MSB (X_MSB),
.Y_MSB (Y_MSB)
)
vga_top
(
.CLK_VGA (CLK_25M ),
.EN_VGA (Sw0Resync25M[0] ),
.RST_SYNC_VGA (~Sw0Resync25M[0] ),
.RST_ASYNC_VGA (RST_ASYNC_25M ),
.CLK_WB (CLK_33M ),
.EN_WB (Sw0Resync33M[0] ),
.RST_SYNC_WB (~Sw0Resync33M[0] ),
.RST_ASYNC_WB (RST_ASYNC_33M ),
.WB_ARB_REQ_OUT (VgaWbArbReq ),
.WB_ARB_GNT_IN (VgaWbArbGnt ),
.VGA_TEST_EN_IN (Sw1Resync25M[0]),
.WB_ADR_OUT (VgaWbAdr ),
.WB_CYC_OUT (VgaWbCyc ),
.WB_STB_OUT (VgaWbStb ),
.WB_WE_OUT (VgaWbWe ),
.WB_SEL_OUT (VgaWbSel ),
.WB_STALL_IN (VgaWbStall ),
.WB_ACK_IN (VgaWbAck ),
.WB_ERR_IN (VgaWbErr ),
.WB_RD_DAT_IN (VgaWbRdDat ),
.WB_WR_DAT_OUT (VgaWbWrDat ),
.VGA_VS_OUT (VGA_VSYNC_OUT ),
.VGA_HS_OUT (VGA_HSYNC_OUT ),
.VGA_RED_OUT (VGA_RED_OUT ),
.VGA_GREEN_OUT (VGA_GREEN_OUT ),
.VGA_BLUE_OUT (VGA_BLUE_OUT ),
.CFG_DITHER_IN (1'b0 ),
.CFG_LINEAR_FB_IN (1'b1 ),
.CFG_PIXEL_FMT_IN (RGB_24B ),
.CFG_BASE_ADDR_IN (12'd0 ),
.CFG_TOP_LEFT_X_IN ({X_MSB+1{1'b0}} ),
.CFG_TOP_LEFT_Y_IN ({Y_MSB+1{1'b0}} ),
.CFG_START_X_IN ({X_MSB+1{1'b0}} ),
.CFG_END_X_IN (VGA_WIDTH_24B_COL ),
.CFG_START_Y_IN ({Y_MSB+1{1'b0}} ),
.CFG_END_Y_IN (9'd480 )
);
WB_ARB_2M_1S wb_arb_2m_1s
(
.CLK (CLK_33M ),
.EN (1'b1 ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC_33M ),
.WB_ARB_REQ_IN ({AdiWbArbReq, VgaWbArbReq} ),
.WB_ARB_GNT_OUT ({AdiWbArbGnt, VgaWbArbGnt} ),
.WB_SL0_ADR_IN (VgaWbAdr ),
.WB_SL0_CYC_IN (VgaWbCyc ),
.WB_SL0_STB_IN (VgaWbStb ),
.WB_SL0_WE_IN (VgaWbWe ),
.WB_SL0_SEL_IN (VgaWbSel ),
.WB_SL0_STALL_OUT (VgaWbStall ),
.WB_SL0_ACK_OUT (VgaWbAck ),
.WB_SL0_ERR_OUT (VgaWbErr ),
.WB_SL0_RD_DAT_OUT (VgaWbRdDat ),
.WB_SL0_WR_DAT_IN (VgaWbWrDat ),
.WB_SL1_ADR_IN (AdiWbAdr ),
.WB_SL1_CYC_IN (AdiWbCyc ),
.WB_SL1_STB_IN (AdiWbStb ),
.WB_SL1_WE_IN (AdiWbWe ),
.WB_SL1_SEL_IN (AdiWbSel ),
.WB_SL1_STALL_OUT (AdiWbStall ),
.WB_SL1_ACK_OUT (AdiWbAck ),
.WB_SL1_ERR_OUT (AdiWbErr ),
.WB_SL1_RD_DAT_OUT (AdiWbRdDat ),
.WB_SL1_WR_DAT_IN (AdiWbWrDat ),
.WB_M0_ADR_OUT (SdramWbAdr ),
.WB_M0_CYC_OUT (SdramWbCyc ),
.WB_M0_STB_OUT (SdramWbStb ),
.WB_M0_WE_OUT (SdramWbWe ),
.WB_M0_SEL_OUT (SdramWbSel ),
.WB_M0_STALL_IN (SdramWbStall ),
.WB_M0_ACK_IN (SdramWbAck ),
.WB_M0_ERR_IN (SdramWbErr ),
.WB_M0_RD_DAT_IN (SdramWbRdDat ),
.WB_M0_WR_DAT_OUT (SdramWbWrDat )
);
SDRAM_CONTROLLER
#(
.WBA (32'h0000_0000),
.WS_P2 (24)
)
sdram_controller
(
.CLK (CLK_33M ),
.EN (1'b1 ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC_33M ),
.CLK_SDR_EN_OUT (RAM_CLK_EN_OUT ),
.WB_ADR_IN (SdramWbAdr ),
.WB_CYC_IN (SdramWbCyc ),
.WB_STB_IN (SdramWbStb ),
.WB_WE_IN (SdramWbWe ),
.WB_SEL_IN (SdramWbSel ),
.WB_CTI_IN (3'b000 ),
.WB_BTE_IN (2'b00 ),
.WB_ACK_OUT (SdramWbAck ),
.WB_STALL_OUT (SdramWbStall ),
.WB_ERR_OUT (SdramWbErr ),
.WB_WR_DAT_IN (SdramWbWrDat ),
.WB_RD_DAT_OUT (SdramWbRdDat ),
.SDR_ADDR_OUT (MEM_ADDR_OUT ),
.SDR_CRE_OUT (RAM_CRE_OUT ),
.SDR_ADVB_OUT (RAM_ADV_OUT ),
.SDR_CEB_OUT (RAM_CS_OUT ),
.SDR_OEB_OUT (MEM_OE_OUT ),
.SDR_WEB_OUT (MEM_WR_OUT ),
.SDR_WAIT_IN (RAM_WAIT_IN ),
.SDR_LBB_OUT (RAM_LB_OUT ),
.SDR_UBB_OUT (RAM_UB_OUT ),
.SDR_DATA_INOUT (MEM_DATA_INOUT )
);
endmodule | 1 |
138,398 | data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v | 83,270,534 | testcase.v | v | 136 | 105 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:8: Cannot find include file: epp_bus_bridge_defs.v\n`include "epp_bus_bridge_defs.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v\n data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.v\n data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.sv\n epp_bus_bridge_defs.v\n epp_bus_bridge_defs.v.v\n epp_bus_bridge_defs.v.sv\n obj_dir/epp_bus_bridge_defs.v\n obj_dir/epp_bus_bridge_defs.v.v\n obj_dir/epp_bus_bridge_defs.v.sv\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:45: syntax error, unexpected \'@\'\n @(negedge `RST);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:45: Define or directive not defined: \'`RST\'\n @(negedge `RST);\n ^~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:54: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:54: syntax error, unexpected \'.\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8\'h00);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:55: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:56: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:57: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:60: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppAddrWrite(ERW_STREAM);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:65: Define or directive not defined: \'`CRAM\'\n `CRAM.memory_write(wordLoop, 2\'b00, wordLoop);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:65: syntax error, unexpected \'.\'\n `CRAM.memory_write(wordLoop, 2\'b00, wordLoop);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:66: Define or directive not defined: \'`CRAM\'\n readData = `CRAM.memory_read(wordLoop);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:66: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n readData = `CRAM.memory_read(wordLoop);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:95: Define or directive not defined: \'`TB\'\n `TB.btn_sw_bfm.SwClose(0);\n ^~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:95: syntax error, unexpected \'.\'\n `TB.btn_sw_bfm.SwClose(0);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:98: Define or directive not defined: \'`TB\'\n @(negedge `TB.VGA_VSYNC);\n ^~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:100: syntax error, unexpected \'@\'\n @(negedge `TB.VGA_VSYNC);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:100: Define or directive not defined: \'`TB\'\n @(negedge `TB.VGA_VSYNC);\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:120: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/venus/sim/vga/epp_to_vga/testcase.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100ms;\n ^\n%Error: Exiting due to 18 error(s), 2 warning(s)\n' | 302,317 | module | module TESTCASE ();
`include "epp_bus_bridge_defs.v"
parameter RAM_SIZE_PIXELS = (640 * 480);
parameter RAM_SIZE_2PIXELS = RAM_SIZE_PIXELS >> 1;
initial
begin
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
string inputFileName = "frame_in.bin.rgb";
int inputFile;
int r;
byte writeByte;
int filePosition;
bit verifyOk = 0;
bit testPass = 1;
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Storing %d pixels data in VGA memory at time %t", RAM_SIZE_PIXELS, $time);
`EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8'h00);
`EPP_MASTER.doEppAddrWrite(ERW_STREAM);
$display("[INFO ] Initialising SDRAM with incrementing data values");
for (int wordLoop = 0 ; wordLoop < 1024 ; wordLoop++)
begin
`CRAM.memory_write(wordLoop, 2'b00, wordLoop);
readData = `CRAM.memory_read(wordLoop);
if (readData !== wordLoop)
begin
$display("[ERROR] SDRAM readback failed. Expectged 0x%x, read 0x%x", wordLoop, readData);
end
end
$display("[INFO ] Turning on VGA driver at time %t", $time);
`TB.btn_sw_bfm.SwClose(0);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] Start of frame at time %t", $time);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] End of frame at time %t", $time);
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`include "epp_bus_bridge_defs.v"
parameter RAM_SIZE_PIXELS = (640 * 480);
parameter RAM_SIZE_2PIXELS = RAM_SIZE_PIXELS >> 1;
initial
begin
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
string inputFileName = "frame_in.bin.rgb";
int inputFile;
int r;
byte writeByte;
int filePosition;
bit verifyOk = 0;
bit testPass = 1;
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Storing %d pixels data in VGA memory at time %t", RAM_SIZE_PIXELS, $time);
`EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8'h00);
`EPP_MASTER.doEppAddrWrite(ERW_STREAM);
$display("[INFO ] Initialising SDRAM with incrementing data values");
for (int wordLoop = 0 ; wordLoop < 1024 ; wordLoop++)
begin
`CRAM.memory_write(wordLoop, 2'b00, wordLoop);
readData = `CRAM.memory_read(wordLoop);
if (readData !== wordLoop)
begin
$display("[ERROR] SDRAM readback failed. Expectged 0x%x, read 0x%x", wordLoop, readData);
end
end
$display("[INFO ] Turning on VGA driver at time %t", $time);
`TB.btn_sw_bfm.SwClose(0);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] Start of frame at time %t", $time);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] End of frame at time %t", $time);
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,399 | data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v | 83,270,534 | testcase.v | v | 111 | 123 | [] | [] | [] | null | line:12: before: "dataLoop" | null | 1: b'%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:40: Define or directive not defined: \'`CRAM\'\n `CRAM.memory_write(wordLoop, 2\'b00, wordLoop);\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:40: syntax error, unexpected \'.\'\n `CRAM.memory_write(wordLoop, 2\'b00, wordLoop);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:67: Define or directive not defined: \'`CRAM\'\n $display("[INFO ] Cellular RAM Word %3d = 0x%x", wordLoop, `CRAM.memory_read(wordLoop++));\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:67: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n $display("[INFO ] Cellular RAM Word %3d = 0x%x", wordLoop, `CRAM.memory_read(wordLoop++));\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:71: Define or directive not defined: \'`RST\'\n @(negedge `RST);\n ^~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:74: Define or directive not defined: \'`CRAM\'\n FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:74: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:74: Define or directive not defined: \'`CRAM\'\n FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:74: Define or directive not defined: \'`CRAM\'\n FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:74: Define or directive not defined: \'`CRAM\'\n FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:74: Define or directive not defined: \'`CRAM\'\n FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:74: Define or directive not defined: \'`CRAM\'\n FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};\n ^~~~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:84: Define or directive not defined: \'`TB\'\n `TB.btn_sw_bfm.SwClose(0);\n ^~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:84: syntax error, unexpected \'.\'\n `TB.btn_sw_bfm.SwClose(0);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:87: Define or directive not defined: \'`TB\'\n @(negedge `TB.VGA_VSYNC);\n ^~~\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:89: syntax error, unexpected \'@\'\n @(negedge `TB.VGA_VSYNC);\n ^\n%Error: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:89: Define or directive not defined: \'`TB\'\n @(negedge `TB.VGA_VSYNC);\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:94: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/venus/sim/vga/simple_colour/testcase.v:102: Unsupported: Ignoring delay on this delayed statement.\n #100ms;\n ^\n%Error: Exiting due to 17 error(s), 2 warning(s)\n' | 302,318 | module | module TESTCASE ();
parameter FRAME_SIZE_BYTE = (1024 * 512 * 2);
initial
begin
int dataLoop;
int wordLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
logic [47:0] FirstTwoPixels;
$display("[INFO ] Storing %d bytes of pixel data directly in VGA memory at time %t", FRAME_SIZE_BYTE, $time);
wordLoop = 0;
while (wordLoop < 16)
begin
`CRAM.memory_write(wordLoop, 2'b00, wordLoop);
wordLoop++;
end
$display("[INFO ] Programmed %d 16-bit words", wordLoop);
wordLoop = 0;
while (wordLoop < 16)
begin
$display("[INFO ] Cellular RAM Word %3d = 0x%x", wordLoop, `CRAM.memory_read(wordLoop++));
end
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};
$display("[DEBUG] Reading back first 2 pixels of data = 0x%x at time %t", FirstTwoPixels, $time);
$finish();
$display("[INFO ] Turning on VGA in test mode at time %t", $time);
`TB.btn_sw_bfm.SwClose(0);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] Start of frame at time %t", $time);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] End of frame at time %t", $time);
#1000ns;
$display("[INFO ] Test completed (without check) at time %t", $time);
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
parameter FRAME_SIZE_BYTE = (1024 * 512 * 2);
initial
begin
int dataLoop;
int wordLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
logic [47:0] FirstTwoPixels;
$display("[INFO ] Storing %d bytes of pixel data directly in VGA memory at time %t", FRAME_SIZE_BYTE, $time);
wordLoop = 0;
while (wordLoop < 16)
begin
`CRAM.memory_write(wordLoop, 2'b00, wordLoop);
wordLoop++;
end
$display("[INFO ] Programmed %d 16-bit words", wordLoop);
wordLoop = 0;
while (wordLoop < 16)
begin
$display("[INFO ] Cellular RAM Word %3d = 0x%x", wordLoop, `CRAM.memory_read(wordLoop++));
end
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
FirstTwoPixels = {`CRAM.memory[5], `CRAM.memory[4], `CRAM.memory[3], `CRAM.memory[2], `CRAM.memory[1], `CRAM.memory[0]};
$display("[DEBUG] Reading back first 2 pixels of data = 0x%x at time %t", FirstTwoPixels, $time);
$finish();
$display("[INFO ] Turning on VGA in test mode at time %t", $time);
`TB.btn_sw_bfm.SwClose(0);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] Start of frame at time %t", $time);
@(negedge `TB.VGA_VSYNC);
$display("[INFO ] End of frame at time %t", $time);
#1000ns;
$display("[INFO ] Test completed (without check) at time %t", $time);
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,401 | data/full_repos/permissive/83270534/venus/tb/board_top.v | 83,270,534 | board_top.v | v | 410 | 81 | [] | [] | [] | [(4, 409)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/83270534/venus/tb/board_top.v:249: Unsupported: Ignoring delay on this delayed statement.\n always #10 CLK = !CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83270534/venus/tb/board_top.v:251: Cannot find file containing module: \'cellram\'\ncellram cellram\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/venus/tb,data/full_repos/permissive/83270534/cellram\n data/full_repos/permissive/83270534/venus/tb,data/full_repos/permissive/83270534/cellram.v\n data/full_repos/permissive/83270534/venus/tb,data/full_repos/permissive/83270534/cellram.sv\n cellram\n cellram.v\n cellram.sv\n obj_dir/cellram\n obj_dir/cellram.v\n obj_dir/cellram.sv\n%Error: data/full_repos/permissive/83270534/venus/tb/board_top.v:267: Cannot find file containing module: \'FPGA_TOP\'\nFPGA_TOP fpga_top\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,320 | module | module BOARD_TOP
(
input BTN_0_IN ,
input BTN_1_IN ,
input BTN_2_IN ,
input BTN_3_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
input SW_0_IN ,
input SW_1_IN ,
input SW_2_IN ,
input SW_3_IN ,
input SW_4_IN ,
input SW_5_IN ,
input SW_6_IN ,
input SW_7_IN ,
output USB_ADDR_0_OUT ,
output USB_ADDR_1_OUT ,
input USB_CLK_IN ,
inout USB_DATA_0_INOUT ,
inout USB_DATA_1_INOUT ,
inout USB_DATA_2_INOUT ,
inout USB_DATA_3_INOUT ,
inout USB_DATA_4_INOUT ,
inout USB_DATA_5_INOUT ,
inout USB_DATA_6_INOUT ,
inout USB_DATA_7_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output VGA_BLUE_0_OUT ,
output VGA_BLUE_1_OUT ,
output VGA_GREEN_0_OUT ,
output VGA_GREEN_1_OUT ,
output VGA_GREEN_2_OUT ,
output VGA_HSYNC_OUT ,
output VGA_RED_0_OUT ,
output VGA_RED_1_OUT ,
output VGA_RED_2_OUT ,
output VGA_VSYNC_OUT
);
reg CLK;
wire FLASH_CS ;
wire FLASH_RP ;
wire FLASH_ST_STS = 1'b0;
wire LED_0 ;
wire LED_1 ;
wire LED_2 ;
wire LED_3 ;
wire LED_4 ;
wire LED_5 ;
wire LED_6 ;
wire LED_7 ;
wire [7:0] LED = {LED_7, LED_6, LED_5, LED_4, LED_3, LED_2, LED_1, LED_0};
wire MEM_ADDR_1 ;
wire MEM_ADDR_2 ;
wire MEM_ADDR_3 ;
wire MEM_ADDR_4 ;
wire MEM_ADDR_5 ;
wire MEM_ADDR_6 ;
wire MEM_ADDR_7 ;
wire MEM_ADDR_8 ;
wire MEM_ADDR_9 ;
wire MEM_ADDR_10 ;
wire MEM_ADDR_11 ;
wire MEM_ADDR_12 ;
wire MEM_ADDR_13 ;
wire MEM_ADDR_14 ;
wire MEM_ADDR_15 ;
wire MEM_ADDR_16 ;
wire MEM_ADDR_17 ;
wire MEM_ADDR_18 ;
wire MEM_ADDR_19 ;
wire MEM_ADDR_20 ;
wire MEM_ADDR_21 ;
wire MEM_ADDR_22 ;
wire MEM_ADDR_23 ;
wire [23:1] MEM_ADDR = {MEM_ADDR_23, MEM_ADDR_22, MEM_ADDR_21, MEM_ADDR_20,
MEM_ADDR_19, MEM_ADDR_18, MEM_ADDR_17, MEM_ADDR_16,
MEM_ADDR_15, MEM_ADDR_14, MEM_ADDR_13, MEM_ADDR_12,
MEM_ADDR_11, MEM_ADDR_10, MEM_ADDR_9 , MEM_ADDR_8 ,
MEM_ADDR_7 , MEM_ADDR_6 , MEM_ADDR_5 , MEM_ADDR_4 ,
MEM_ADDR_3 , MEM_ADDR_2 , MEM_ADDR_1 };
wire MEM_OE ;
wire MEM_WR ;
wire RAM_ADV ;
wire RAM_CLK ;
wire RAM_CRE ;
wire RAM_CS ;
wire RAM_LB ;
wire RAM_UB ;
wire RAM_WAIT ;
wire SSEG_AN_0 ;
wire SSEG_AN_1 ;
wire SSEG_AN_2 ;
wire SSEG_AN_3 ;
wire SSEG_K_0 ;
wire SSEG_K_1 ;
wire SSEG_K_2 ;
wire SSEG_K_3 ;
wire SSEG_K_4 ;
wire SSEG_K_5 ;
wire SSEG_K_6 ;
wire SSEG_K_7 ;
wire [15:0] MEM_DATA;
initial
begin
CLK = 1'b0;
end
always #10 CLK = !CLK;
cellram cellram
(
.clk (RAM_CLK ),
.adv_n (RAM_ADV ),
.cre (RAM_CRE ),
.o_wait (RAM_WAIT ),
.ce_n (RAM_CS ),
.oe_n (MEM_OE ),
.we_n (MEM_WR ),
.lb_n (RAM_LB ),
.ub_n (RAM_UB ),
.addr (MEM_ADDR ),
.dq (MEM_DATA )
);
FPGA_TOP fpga_top
(
.BTN_0_IN (BTN_0_IN ),
.BTN_1_IN (BTN_1_IN ),
.BTN_2_IN (BTN_2_IN ),
.BTN_3_IN (BTN_3_IN ),
.CLK_IN (CLK ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.FLASH_CS_OUT (FLASH_CS ),
.FLASH_RP_OUT (FLASH_RP ),
.FLASH_ST_STS_IN (FLASH_ST_STS ),
.LED_0_OUT (LED_0 ),
.LED_1_OUT (LED_1 ),
.LED_2_OUT (LED_2 ),
.LED_3_OUT (LED_3 ),
.LED_4_OUT (LED_4 ),
.LED_5_OUT (LED_5 ),
.LED_6_OUT (LED_6 ),
.LED_7_OUT (LED_7 ),
.MEM_ADDR_1_OUT (MEM_ADDR_1 ),
.MEM_ADDR_2_OUT (MEM_ADDR_2 ),
.MEM_ADDR_3_OUT (MEM_ADDR_3 ),
.MEM_ADDR_4_OUT (MEM_ADDR_4 ),
.MEM_ADDR_5_OUT (MEM_ADDR_5 ),
.MEM_ADDR_6_OUT (MEM_ADDR_6 ),
.MEM_ADDR_7_OUT (MEM_ADDR_7 ),
.MEM_ADDR_8_OUT (MEM_ADDR_8 ),
.MEM_ADDR_9_OUT (MEM_ADDR_9 ),
.MEM_ADDR_10_OUT (MEM_ADDR_10 ),
.MEM_ADDR_11_OUT (MEM_ADDR_11 ),
.MEM_ADDR_12_OUT (MEM_ADDR_12 ),
.MEM_ADDR_13_OUT (MEM_ADDR_13 ),
.MEM_ADDR_14_OUT (MEM_ADDR_14 ),
.MEM_ADDR_15_OUT (MEM_ADDR_15 ),
.MEM_ADDR_16_OUT (MEM_ADDR_16 ),
.MEM_ADDR_17_OUT (MEM_ADDR_17 ),
.MEM_ADDR_18_OUT (MEM_ADDR_18 ),
.MEM_ADDR_19_OUT (MEM_ADDR_19 ),
.MEM_ADDR_20_OUT (MEM_ADDR_20 ),
.MEM_ADDR_21_OUT (MEM_ADDR_21 ),
.MEM_ADDR_22_OUT (MEM_ADDR_22 ),
.MEM_ADDR_23_OUT (MEM_ADDR_23 ),
.MEM_DATA_0_INOUT (MEM_DATA[0] ),
.MEM_DATA_1_INOUT (MEM_DATA[1] ),
.MEM_DATA_2_INOUT (MEM_DATA[2] ),
.MEM_DATA_3_INOUT (MEM_DATA[3] ),
.MEM_DATA_4_INOUT (MEM_DATA[4] ),
.MEM_DATA_5_INOUT (MEM_DATA[5] ),
.MEM_DATA_6_INOUT (MEM_DATA[6] ),
.MEM_DATA_7_INOUT (MEM_DATA[7] ),
.MEM_DATA_8_INOUT (MEM_DATA[8] ),
.MEM_DATA_9_INOUT (MEM_DATA[9] ),
.MEM_DATA_10_INOUT (MEM_DATA[10] ),
.MEM_DATA_11_INOUT (MEM_DATA[11] ),
.MEM_DATA_12_INOUT (MEM_DATA[12] ),
.MEM_DATA_13_INOUT (MEM_DATA[13] ),
.MEM_DATA_14_INOUT (MEM_DATA[14] ),
.MEM_DATA_15_INOUT (MEM_DATA[15] ),
.MEM_OE_OUT (MEM_OE ),
.MEM_WR_OUT (MEM_WR ),
.PS2_CLK_INOUT (PS2_CLK_INOUT ),
.PS2_DATA_INOUT (PS2_DATA_INOUT ),
.RAM_ADV_OUT (RAM_ADV ),
.RAM_CLK_OUT (RAM_CLK ),
.RAM_CRE_OUT (RAM_CRE ),
.RAM_CS_OUT (RAM_CS ),
.RAM_LB_OUT (RAM_LB ),
.RAM_UB_OUT (RAM_UB ),
.RAM_WAIT_IN (RAM_WAIT ),
.RS232_RX_IN (RS232_RX_IN ),
.RS232_TX_INOUT (RS232_TX_INOUT ),
.SSEG_AN_0_OUT (SSEG_AN_0 ),
.SSEG_AN_1_OUT (SSEG_AN_1 ),
.SSEG_AN_2_OUT (SSEG_AN_2 ),
.SSEG_AN_3_OUT (SSEG_AN_3 ),
.SSEG_K_0_OUT (SSEG_K_0 ),
.SSEG_K_1_OUT (SSEG_K_1 ),
.SSEG_K_2_OUT (SSEG_K_2 ),
.SSEG_K_3_OUT (SSEG_K_3 ),
.SSEG_K_4_OUT (SSEG_K_4 ),
.SSEG_K_5_OUT (SSEG_K_5 ),
.SSEG_K_6_OUT (SSEG_K_6 ),
.SSEG_K_7_OUT (SSEG_K_7 ),
.SW_0_IN (SW_0_IN ),
.SW_1_IN (SW_1_IN ),
.SW_2_IN (SW_2_IN ),
.SW_3_IN (SW_3_IN ),
.SW_4_IN (SW_4_IN ),
.SW_5_IN (SW_5_IN ),
.SW_6_IN (SW_6_IN ),
.SW_7_IN (SW_7_IN ),
.USB_ADDR_0_OUT (USB_ADDR_0_OUT ),
.USB_ADDR_1_OUT (USB_ADDR_1_OUT ),
.USB_CLK_IN (USB_CLK_IN ),
.USB_DATA_0_INOUT (USB_DATA_0_INOUT ),
.USB_DATA_1_INOUT (USB_DATA_1_INOUT ),
.USB_DATA_2_INOUT (USB_DATA_2_INOUT ),
.USB_DATA_3_INOUT (USB_DATA_3_INOUT ),
.USB_DATA_4_INOUT (USB_DATA_4_INOUT ),
.USB_DATA_5_INOUT (USB_DATA_5_INOUT ),
.USB_DATA_6_INOUT (USB_DATA_6_INOUT ),
.USB_DATA_7_INOUT (USB_DATA_7_INOUT ),
.USB_DIR_IN (USB_DIR_IN ),
.USB_FLAG_IN (USB_FLAG_IN ),
.USB_MODE_IN (USB_MODE_IN ),
.USB_OE_OUT (USB_OE_OUT ),
.USB_PKTEND_OUT (USB_PKTEND_OUT ),
.USB_WR_OUT (USB_WR_OUT ),
.VGA_BLUE_0_OUT (VGA_BLUE_0_OUT ),
.VGA_BLUE_1_OUT (VGA_BLUE_1_OUT ),
.VGA_GREEN_0_OUT (VGA_GREEN_0_OUT ),
.VGA_GREEN_1_OUT (VGA_GREEN_1_OUT ),
.VGA_GREEN_2_OUT (VGA_GREEN_2_OUT ),
.VGA_HSYNC_OUT (VGA_HSYNC_OUT ),
.VGA_RED_0_OUT (VGA_RED_0_OUT ),
.VGA_RED_1_OUT (VGA_RED_1_OUT ),
.VGA_RED_2_OUT (VGA_RED_2_OUT ),
.VGA_VSYNC_OUT (VGA_VSYNC_OUT )
);
endmodule | module BOARD_TOP
(
input BTN_0_IN ,
input BTN_1_IN ,
input BTN_2_IN ,
input BTN_3_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
input SW_0_IN ,
input SW_1_IN ,
input SW_2_IN ,
input SW_3_IN ,
input SW_4_IN ,
input SW_5_IN ,
input SW_6_IN ,
input SW_7_IN ,
output USB_ADDR_0_OUT ,
output USB_ADDR_1_OUT ,
input USB_CLK_IN ,
inout USB_DATA_0_INOUT ,
inout USB_DATA_1_INOUT ,
inout USB_DATA_2_INOUT ,
inout USB_DATA_3_INOUT ,
inout USB_DATA_4_INOUT ,
inout USB_DATA_5_INOUT ,
inout USB_DATA_6_INOUT ,
inout USB_DATA_7_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output VGA_BLUE_0_OUT ,
output VGA_BLUE_1_OUT ,
output VGA_GREEN_0_OUT ,
output VGA_GREEN_1_OUT ,
output VGA_GREEN_2_OUT ,
output VGA_HSYNC_OUT ,
output VGA_RED_0_OUT ,
output VGA_RED_1_OUT ,
output VGA_RED_2_OUT ,
output VGA_VSYNC_OUT
); |
reg CLK;
wire FLASH_CS ;
wire FLASH_RP ;
wire FLASH_ST_STS = 1'b0;
wire LED_0 ;
wire LED_1 ;
wire LED_2 ;
wire LED_3 ;
wire LED_4 ;
wire LED_5 ;
wire LED_6 ;
wire LED_7 ;
wire [7:0] LED = {LED_7, LED_6, LED_5, LED_4, LED_3, LED_2, LED_1, LED_0};
wire MEM_ADDR_1 ;
wire MEM_ADDR_2 ;
wire MEM_ADDR_3 ;
wire MEM_ADDR_4 ;
wire MEM_ADDR_5 ;
wire MEM_ADDR_6 ;
wire MEM_ADDR_7 ;
wire MEM_ADDR_8 ;
wire MEM_ADDR_9 ;
wire MEM_ADDR_10 ;
wire MEM_ADDR_11 ;
wire MEM_ADDR_12 ;
wire MEM_ADDR_13 ;
wire MEM_ADDR_14 ;
wire MEM_ADDR_15 ;
wire MEM_ADDR_16 ;
wire MEM_ADDR_17 ;
wire MEM_ADDR_18 ;
wire MEM_ADDR_19 ;
wire MEM_ADDR_20 ;
wire MEM_ADDR_21 ;
wire MEM_ADDR_22 ;
wire MEM_ADDR_23 ;
wire [23:1] MEM_ADDR = {MEM_ADDR_23, MEM_ADDR_22, MEM_ADDR_21, MEM_ADDR_20,
MEM_ADDR_19, MEM_ADDR_18, MEM_ADDR_17, MEM_ADDR_16,
MEM_ADDR_15, MEM_ADDR_14, MEM_ADDR_13, MEM_ADDR_12,
MEM_ADDR_11, MEM_ADDR_10, MEM_ADDR_9 , MEM_ADDR_8 ,
MEM_ADDR_7 , MEM_ADDR_6 , MEM_ADDR_5 , MEM_ADDR_4 ,
MEM_ADDR_3 , MEM_ADDR_2 , MEM_ADDR_1 };
wire MEM_OE ;
wire MEM_WR ;
wire RAM_ADV ;
wire RAM_CLK ;
wire RAM_CRE ;
wire RAM_CS ;
wire RAM_LB ;
wire RAM_UB ;
wire RAM_WAIT ;
wire SSEG_AN_0 ;
wire SSEG_AN_1 ;
wire SSEG_AN_2 ;
wire SSEG_AN_3 ;
wire SSEG_K_0 ;
wire SSEG_K_1 ;
wire SSEG_K_2 ;
wire SSEG_K_3 ;
wire SSEG_K_4 ;
wire SSEG_K_5 ;
wire SSEG_K_6 ;
wire SSEG_K_7 ;
wire [15:0] MEM_DATA;
initial
begin
CLK = 1'b0;
end
always #10 CLK = !CLK;
cellram cellram
(
.clk (RAM_CLK ),
.adv_n (RAM_ADV ),
.cre (RAM_CRE ),
.o_wait (RAM_WAIT ),
.ce_n (RAM_CS ),
.oe_n (MEM_OE ),
.we_n (MEM_WR ),
.lb_n (RAM_LB ),
.ub_n (RAM_UB ),
.addr (MEM_ADDR ),
.dq (MEM_DATA )
);
FPGA_TOP fpga_top
(
.BTN_0_IN (BTN_0_IN ),
.BTN_1_IN (BTN_1_IN ),
.BTN_2_IN (BTN_2_IN ),
.BTN_3_IN (BTN_3_IN ),
.CLK_IN (CLK ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.FLASH_CS_OUT (FLASH_CS ),
.FLASH_RP_OUT (FLASH_RP ),
.FLASH_ST_STS_IN (FLASH_ST_STS ),
.LED_0_OUT (LED_0 ),
.LED_1_OUT (LED_1 ),
.LED_2_OUT (LED_2 ),
.LED_3_OUT (LED_3 ),
.LED_4_OUT (LED_4 ),
.LED_5_OUT (LED_5 ),
.LED_6_OUT (LED_6 ),
.LED_7_OUT (LED_7 ),
.MEM_ADDR_1_OUT (MEM_ADDR_1 ),
.MEM_ADDR_2_OUT (MEM_ADDR_2 ),
.MEM_ADDR_3_OUT (MEM_ADDR_3 ),
.MEM_ADDR_4_OUT (MEM_ADDR_4 ),
.MEM_ADDR_5_OUT (MEM_ADDR_5 ),
.MEM_ADDR_6_OUT (MEM_ADDR_6 ),
.MEM_ADDR_7_OUT (MEM_ADDR_7 ),
.MEM_ADDR_8_OUT (MEM_ADDR_8 ),
.MEM_ADDR_9_OUT (MEM_ADDR_9 ),
.MEM_ADDR_10_OUT (MEM_ADDR_10 ),
.MEM_ADDR_11_OUT (MEM_ADDR_11 ),
.MEM_ADDR_12_OUT (MEM_ADDR_12 ),
.MEM_ADDR_13_OUT (MEM_ADDR_13 ),
.MEM_ADDR_14_OUT (MEM_ADDR_14 ),
.MEM_ADDR_15_OUT (MEM_ADDR_15 ),
.MEM_ADDR_16_OUT (MEM_ADDR_16 ),
.MEM_ADDR_17_OUT (MEM_ADDR_17 ),
.MEM_ADDR_18_OUT (MEM_ADDR_18 ),
.MEM_ADDR_19_OUT (MEM_ADDR_19 ),
.MEM_ADDR_20_OUT (MEM_ADDR_20 ),
.MEM_ADDR_21_OUT (MEM_ADDR_21 ),
.MEM_ADDR_22_OUT (MEM_ADDR_22 ),
.MEM_ADDR_23_OUT (MEM_ADDR_23 ),
.MEM_DATA_0_INOUT (MEM_DATA[0] ),
.MEM_DATA_1_INOUT (MEM_DATA[1] ),
.MEM_DATA_2_INOUT (MEM_DATA[2] ),
.MEM_DATA_3_INOUT (MEM_DATA[3] ),
.MEM_DATA_4_INOUT (MEM_DATA[4] ),
.MEM_DATA_5_INOUT (MEM_DATA[5] ),
.MEM_DATA_6_INOUT (MEM_DATA[6] ),
.MEM_DATA_7_INOUT (MEM_DATA[7] ),
.MEM_DATA_8_INOUT (MEM_DATA[8] ),
.MEM_DATA_9_INOUT (MEM_DATA[9] ),
.MEM_DATA_10_INOUT (MEM_DATA[10] ),
.MEM_DATA_11_INOUT (MEM_DATA[11] ),
.MEM_DATA_12_INOUT (MEM_DATA[12] ),
.MEM_DATA_13_INOUT (MEM_DATA[13] ),
.MEM_DATA_14_INOUT (MEM_DATA[14] ),
.MEM_DATA_15_INOUT (MEM_DATA[15] ),
.MEM_OE_OUT (MEM_OE ),
.MEM_WR_OUT (MEM_WR ),
.PS2_CLK_INOUT (PS2_CLK_INOUT ),
.PS2_DATA_INOUT (PS2_DATA_INOUT ),
.RAM_ADV_OUT (RAM_ADV ),
.RAM_CLK_OUT (RAM_CLK ),
.RAM_CRE_OUT (RAM_CRE ),
.RAM_CS_OUT (RAM_CS ),
.RAM_LB_OUT (RAM_LB ),
.RAM_UB_OUT (RAM_UB ),
.RAM_WAIT_IN (RAM_WAIT ),
.RS232_RX_IN (RS232_RX_IN ),
.RS232_TX_INOUT (RS232_TX_INOUT ),
.SSEG_AN_0_OUT (SSEG_AN_0 ),
.SSEG_AN_1_OUT (SSEG_AN_1 ),
.SSEG_AN_2_OUT (SSEG_AN_2 ),
.SSEG_AN_3_OUT (SSEG_AN_3 ),
.SSEG_K_0_OUT (SSEG_K_0 ),
.SSEG_K_1_OUT (SSEG_K_1 ),
.SSEG_K_2_OUT (SSEG_K_2 ),
.SSEG_K_3_OUT (SSEG_K_3 ),
.SSEG_K_4_OUT (SSEG_K_4 ),
.SSEG_K_5_OUT (SSEG_K_5 ),
.SSEG_K_6_OUT (SSEG_K_6 ),
.SSEG_K_7_OUT (SSEG_K_7 ),
.SW_0_IN (SW_0_IN ),
.SW_1_IN (SW_1_IN ),
.SW_2_IN (SW_2_IN ),
.SW_3_IN (SW_3_IN ),
.SW_4_IN (SW_4_IN ),
.SW_5_IN (SW_5_IN ),
.SW_6_IN (SW_6_IN ),
.SW_7_IN (SW_7_IN ),
.USB_ADDR_0_OUT (USB_ADDR_0_OUT ),
.USB_ADDR_1_OUT (USB_ADDR_1_OUT ),
.USB_CLK_IN (USB_CLK_IN ),
.USB_DATA_0_INOUT (USB_DATA_0_INOUT ),
.USB_DATA_1_INOUT (USB_DATA_1_INOUT ),
.USB_DATA_2_INOUT (USB_DATA_2_INOUT ),
.USB_DATA_3_INOUT (USB_DATA_3_INOUT ),
.USB_DATA_4_INOUT (USB_DATA_4_INOUT ),
.USB_DATA_5_INOUT (USB_DATA_5_INOUT ),
.USB_DATA_6_INOUT (USB_DATA_6_INOUT ),
.USB_DATA_7_INOUT (USB_DATA_7_INOUT ),
.USB_DIR_IN (USB_DIR_IN ),
.USB_FLAG_IN (USB_FLAG_IN ),
.USB_MODE_IN (USB_MODE_IN ),
.USB_OE_OUT (USB_OE_OUT ),
.USB_PKTEND_OUT (USB_PKTEND_OUT ),
.USB_WR_OUT (USB_WR_OUT ),
.VGA_BLUE_0_OUT (VGA_BLUE_0_OUT ),
.VGA_BLUE_1_OUT (VGA_BLUE_1_OUT ),
.VGA_GREEN_0_OUT (VGA_GREEN_0_OUT ),
.VGA_GREEN_1_OUT (VGA_GREEN_1_OUT ),
.VGA_GREEN_2_OUT (VGA_GREEN_2_OUT ),
.VGA_HSYNC_OUT (VGA_HSYNC_OUT ),
.VGA_RED_0_OUT (VGA_RED_0_OUT ),
.VGA_RED_1_OUT (VGA_RED_1_OUT ),
.VGA_RED_2_OUT (VGA_RED_2_OUT ),
.VGA_VSYNC_OUT (VGA_VSYNC_OUT )
);
endmodule | 1 |
138,403 | data/full_repos/permissive/83270534/vga_controller/rtl/vga_cdc.v | 83,270,534 | vga_cdc.v | v | 132 | 76 | [] | [] | [] | [(5, 131)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/vga_controller/rtl/vga_cdc.v:108: Cannot find file containing module: 'ASYNC_FIFO'\n ASYNC_FIFO \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/ASYNC_FIFO\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/ASYNC_FIFO.v\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/ASYNC_FIFO.sv\n ASYNC_FIFO\n ASYNC_FIFO.v\n ASYNC_FIFO.sv\n obj_dir/ASYNC_FIFO\n obj_dir/ASYNC_FIFO.v\n obj_dir/ASYNC_FIFO.sv\n%Error: Exiting due to 1 error(s)\n" | 302,322 | module | module VGA_CDC
(
input CLK_VGA ,
input RST_ASYNC_VGA ,
input CLK_WB ,
input RST_ASYNC_WB ,
output [7:0] VGA_DATA_OUT ,
input VGA_DATA_REQ_IN ,
input VGA_ACTIVE_LINE_IN ,
input VGA_HS_IN ,
input VGA_VS_IN ,
input WB_DATA_EN_IN ,
input [7:0] WB_DATA_IN ,
output WB_DATA_FULL_OUT ,
output WB_ACTIVE_LINE_OUT ,
output WB_VS_STB_OUT ,
output WB_HS_STB_OUT ,
output WB_RCNT_ACTIVE_ROW_OUT ,
output WB_RCNT_ACTIVE_COL_OUT
);
reg [2:0] VgaVsPipe;
reg [2:0] VgaHsPipe;
reg [1:0] VgaActiveLinePipe;
reg [1:0] VgaDataReqPipe;
wire FifoReadEmpty;
assign WB_VS_STB_OUT = (VgaVsPipe[2] & ~VgaVsPipe[1]);
assign WB_HS_STB_OUT = (VgaHsPipe[2] & ~VgaHsPipe[1]);
assign WB_ACTIVE_LINE_OUT = VgaActiveLinePipe[1];
assign WB_RCNT_ACTIVE_ROW_OUT = VgaActiveLinePipe[1];
assign WB_RCNT_ACTIVE_COL_OUT = VgaDataReqPipe[1];
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : VSYNC_RESYNC
if (RST_ASYNC_WB)
begin
VgaVsPipe <= 3'b000;
end
else
begin
VgaVsPipe <= {VgaVsPipe[1:0], VGA_VS_IN};
end
end
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : HSYNC_RESYNC
if (RST_ASYNC_WB)
begin
VgaHsPipe <= 3'b000;
end
else
begin
VgaHsPipe <= {VgaHsPipe[1:0], VGA_HS_IN};
end
end
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : VGA_ACTIVE_RESYNC
if (RST_ASYNC_WB)
begin
VgaActiveLinePipe <= 2'b00;
end
else
begin
VgaActiveLinePipe <= {VgaActiveLinePipe[0], VGA_ACTIVE_LINE_IN};
end
end
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : VGA_DATA_REQ_RESYNC
if (RST_ASYNC_WB)
begin
VgaDataReqPipe <= 2'b00;
end
else
begin
VgaDataReqPipe <= {VgaDataReqPipe[0], VGA_DATA_REQ_IN};
end
end
ASYNC_FIFO
#(
.DSIZE ( 8),
.ASIZE (10)
)
async_fifo_vga
(
.wclk (CLK_WB ),
.wrst_n (~RST_ASYNC_WB ),
.rclk (CLK_VGA ),
.rrst_n (~RST_ASYNC_VGA ),
.winc (WB_DATA_EN_IN ),
.wfull (WB_DATA_FULL_OUT ),
.wdata (WB_DATA_IN ),
.rinc (VGA_DATA_REQ_IN ),
.rempty (FifoReadEmpty ),
.rdata (VGA_DATA_OUT )
);
endmodule | module VGA_CDC
(
input CLK_VGA ,
input RST_ASYNC_VGA ,
input CLK_WB ,
input RST_ASYNC_WB ,
output [7:0] VGA_DATA_OUT ,
input VGA_DATA_REQ_IN ,
input VGA_ACTIVE_LINE_IN ,
input VGA_HS_IN ,
input VGA_VS_IN ,
input WB_DATA_EN_IN ,
input [7:0] WB_DATA_IN ,
output WB_DATA_FULL_OUT ,
output WB_ACTIVE_LINE_OUT ,
output WB_VS_STB_OUT ,
output WB_HS_STB_OUT ,
output WB_RCNT_ACTIVE_ROW_OUT ,
output WB_RCNT_ACTIVE_COL_OUT
); |
reg [2:0] VgaVsPipe;
reg [2:0] VgaHsPipe;
reg [1:0] VgaActiveLinePipe;
reg [1:0] VgaDataReqPipe;
wire FifoReadEmpty;
assign WB_VS_STB_OUT = (VgaVsPipe[2] & ~VgaVsPipe[1]);
assign WB_HS_STB_OUT = (VgaHsPipe[2] & ~VgaHsPipe[1]);
assign WB_ACTIVE_LINE_OUT = VgaActiveLinePipe[1];
assign WB_RCNT_ACTIVE_ROW_OUT = VgaActiveLinePipe[1];
assign WB_RCNT_ACTIVE_COL_OUT = VgaDataReqPipe[1];
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : VSYNC_RESYNC
if (RST_ASYNC_WB)
begin
VgaVsPipe <= 3'b000;
end
else
begin
VgaVsPipe <= {VgaVsPipe[1:0], VGA_VS_IN};
end
end
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : HSYNC_RESYNC
if (RST_ASYNC_WB)
begin
VgaHsPipe <= 3'b000;
end
else
begin
VgaHsPipe <= {VgaHsPipe[1:0], VGA_HS_IN};
end
end
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : VGA_ACTIVE_RESYNC
if (RST_ASYNC_WB)
begin
VgaActiveLinePipe <= 2'b00;
end
else
begin
VgaActiveLinePipe <= {VgaActiveLinePipe[0], VGA_ACTIVE_LINE_IN};
end
end
always @(posedge CLK_WB or posedge RST_ASYNC_WB)
begin : VGA_DATA_REQ_RESYNC
if (RST_ASYNC_WB)
begin
VgaDataReqPipe <= 2'b00;
end
else
begin
VgaDataReqPipe <= {VgaDataReqPipe[0], VGA_DATA_REQ_IN};
end
end
ASYNC_FIFO
#(
.DSIZE ( 8),
.ASIZE (10)
)
async_fifo_vga
(
.wclk (CLK_WB ),
.wrst_n (~RST_ASYNC_WB ),
.rclk (CLK_VGA ),
.rrst_n (~RST_ASYNC_VGA ),
.winc (WB_DATA_EN_IN ),
.wfull (WB_DATA_FULL_OUT ),
.wdata (WB_DATA_IN ),
.rinc (VGA_DATA_REQ_IN ),
.rempty (FifoReadEmpty ),
.rdata (VGA_DATA_OUT )
);
endmodule | 1 |
138,404 | data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v | 83,270,534 | vga_dma.v | v | 694 | 135 | [] | [] | [] | [(1, 691)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:122: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 15 bits.\n : ... In instance VGA_DMA\n wire [31:0] BusAddr = CfgLinearFbReg ? {CfgBaseAddrReg , \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:122: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s REPLICATE generates 15 bits.\n : ... In instance VGA_DMA\n wire [31:0] BusAddr = CfgLinearFbReg ? {CfgBaseAddrReg , \n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:146: Operator ADD expects 3 bits on the LHS, but LHS\'s VARREF \'CfgStartYReg\' generates 1 bits.\n : ... In instance VGA_DMA\n assign LinearFbXY = (CfgStartXRegByte + FbXByte) + (CfgStartYReg + (FbY * CfgEndXRegByte));\n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:240: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n : ... In instance VGA_DMA\n FbXByte <= {X_MSB+1{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:244: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n : ... In instance VGA_DMA\n FbXByte <= {X_MSB+1{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:256: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 3 bits.\n : ... In instance VGA_DMA\n WB_32B : FbXByte <= FbXByte + 4;\n ^~\n%Error: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:271: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n : ... In instance VGA_DMA\n FbY <= {Y_MSB{1\'b0}};\n ^\n%Error: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:275: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n : ... In instance VGA_DMA\n FbY <= {Y_MSB{1\'b0}};\n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:410: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d0 : PixelShiftReg[15: 0] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:411: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d1 : PixelShiftReg[23: 8] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:412: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d2 : PixelShiftReg[31:16] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:413: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d3 : PixelShiftReg[39:24] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:414: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d4 : PixelShiftReg[47:32] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:415: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d5 : PixelShiftReg[55:40] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:416: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d6 : PixelShiftReg[63:48] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:417: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d7 : PixelShiftReg[71:56] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:418: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d8 : PixelShiftReg[79:64] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:419: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d9 : PixelShiftReg[87:72] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:420: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d10 : PixelShiftReg[95:80] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d0 : PixelShiftReg[7 :0 ] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:429: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d1 : PixelShiftReg[15:8 ] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:430: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d2 : PixelShiftReg[23:16] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:431: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d3 : PixelShiftReg[31:24] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d4 : PixelShiftReg[39:32] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:433: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d5 : PixelShiftReg[47:40] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:434: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d6 : PixelShiftReg[55:48] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:435: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d7 : PixelShiftReg[63:56] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d8 : PixelShiftReg[71:64] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:437: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d9 : PixelShiftReg[79:72] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:438: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d10 : PixelShiftReg[87:80] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:439: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusReadData\' generates 32 bits.\n : ... In instance VGA_DMA\n 5\'d11 : PixelShiftReg[95:88] <= BusReadData ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:512: Operator GTE expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'FbXBytesLeft\' generates 2 bits.\n : ... In instance VGA_DMA\n else if (FbXBytesLeft >= 4)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:506: Operator GTE expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'FbXBytesLeft\' generates 2 bits.\n : ... In instance VGA_DMA\n else if (FbXBytesLeft >= 8)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:500: Operator GTE expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'FbXBytesLeft\' generates 2 bits.\n : ... In instance VGA_DMA\n if (FbXBytesLeft >= 12)\n ^~\n%Error: data/full_repos/permissive/83270534/vga_controller/rtl/vga_dma.v:648: Cannot find file containing module: \'WB_MASTER\'\n WB_MASTER wb_master\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/WB_MASTER\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/WB_MASTER.v\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/WB_MASTER.sv\n WB_MASTER\n WB_MASTER.v\n WB_MASTER.sv\n obj_dir/WB_MASTER\n obj_dir/WB_MASTER.v\n obj_dir/WB_MASTER.sv\n%Error: Exiting due to 3 error(s), 32 warning(s)\n' | 302,323 | module | module VGA_DMA
#(parameter X_MSB = 0,
parameter Y_MSB = 0,
parameter R_HI = 7,
parameter R_LO = 5,
parameter G_HI = 4,
parameter G_LO = 2,
parameter B_HI = 1,
parameter B_LO = 0
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_STALL_IN ,
input WB_ACK_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT ,
output WB_PIXEL_DATA_EN_OUT ,
output [7:0] WB_PIXEL_DATA_OUT ,
input WB_PIXEL_DATA_FULL_IN ,
input WB_VS_STB_IN ,
input WB_HS_STB_IN ,
input WB_ACTIVE_LINE_IN ,
input CFG_DITHER_IN ,
input CFG_LINEAR_FB_IN ,
input [ 1: 0] CFG_PIXEL_FMT_IN ,
input [ 31:20] CFG_BASE_ADDR_IN ,
input [X_MSB: 0] CFG_TOP_LEFT_X_IN ,
input [Y_MSB: 0] CFG_TOP_LEFT_Y_IN ,
input [X_MSB: 0] CFG_START_X_IN ,
input [X_MSB: 0] CFG_END_X_IN ,
input [Y_MSB: 0] CFG_START_Y_IN ,
input [Y_MSB: 0] CFG_END_Y_IN
);
parameter [1:0] WB_8B = 2'b00;
parameter [1:0] WB_16B = 2'b01;
parameter [1:0] WB_32B = 2'b10;
parameter [1:0] PIXEL_FMT_PSX_16B = 2'b00;
parameter [1:0] PIXEL_FMT_PSX_24B = 2'b01;
parameter [1:0] PIXEL_FMT_RGB_8B = 2'b10;
parameter [1:0] PIXEL_FMT_RGB_24B = 2'b11;
parameter [1:0] VDFSM_IDLE = 2'b00;
parameter [1:0] VDFSM_ACTIVE = 2'b01;
parameter [1:0] VDFSM_REQ_DATA = 2'b10;
parameter [1:0] VDFSM_PIXEL_DATA = 2'b11;
reg [1:0] VdfsmStateCur;
reg [1:0] VdfsmStateNxt;
reg [4:0] BusTmrVal;
reg BusReadReqNxt;
reg BusReadReq;
reg WbMasterRegEn;
reg PixelDataEn;
reg CfgDitherReg ;
reg CfgLinearFbReg ;
reg [ 1: 0] CfgPixelFmtReg ;
reg [ 31:20] CfgBaseAddrReg ;
reg [X_MSB: 0] CfgTopLeftXReg ;
reg [Y_MSB: 0] CfgTopLeftYReg ;
reg [X_MSB: 0] CfgStartXReg ;
reg [X_MSB: 0] CfgEndXReg ;
reg [Y_MSB: 0] CfgStartYReg ;
reg [Y_MSB: 0] CfgEndYReg ;
wire [X_MSB+1:0] CfgStartXRegByte = {CfgStartXReg, 1'b0};
wire [X_MSB+1:0] CfgEndXRegByte = {CfgEndXReg , 1'b0};
wire [X_MSB+Y_MSB+2:0] LinearFbXY;
reg [X_MSB+1:0] FbXByte;
wire [X_MSB+1:0] FbXBytesLeft = CfgEndXRegByte - FbXByte;
wire FbEndOfLine = (FbXByte >= CfgEndXRegByte);
reg [Y_MSB:0] FbY;
wire FbEndOfFrame = (FbY == CfgEndYReg);
wire [31:0] BusAddr = CfgLinearFbReg ? {CfgBaseAddrReg ,
LinearFbXY
} :
{CfgBaseAddrReg ,
FbY ,
FbXByte
};
wire BusReadAck ;
wire BusReadDataEn = BusReadReq & BusReadAck;
wire [31:0] BusReadData;
reg [ 4:0] PixelByteCnt;
reg [ 95:0] PixelShiftReg;
reg [1:0] WbMasterBusSize ;
reg [4:0] WbMasterBusLen ;
reg [1:0] WbMasterBusSizeReg ;
reg [4:0] WbMasterBusLenReg ;
assign LinearFbXY = (CfgStartXRegByte + FbXByte) + (CfgStartYReg + (FbY * CfgEndXRegByte));
assign WB_PIXEL_DATA_EN_OUT = PixelDataEn;
assign WB_PIXEL_DATA_OUT[R_HI:R_LO] = PixelShiftReg[ 7: 5];
assign WB_PIXEL_DATA_OUT[G_HI:G_LO] = PixelShiftReg[15:13];
assign WB_PIXEL_DATA_OUT[B_HI:B_LO] = PixelShiftReg[23:22];
always @(posedge CLK or posedge RST_ASYNC)
begin : CONFIG_REG
if (RST_ASYNC)
begin
CfgDitherReg <= 1'b0;
CfgLinearFbReg <= 1'b0;
CfgPixelFmtReg <= 2'b00;
CfgBaseAddrReg <= 12'd0;
CfgTopLeftXReg <= {X_MSB+1{1'b0}};
CfgTopLeftYReg <= {Y_MSB+1{1'b0}};
CfgStartXReg <= {X_MSB+1{1'b0}};
CfgEndXReg <= {X_MSB+1{1'b0}};
CfgStartYReg <= {Y_MSB+1{1'b0}};
CfgEndYReg <= {Y_MSB+1{1'b0}};
end
else if (RST_SYNC)
begin
CfgDitherReg <= 1'b0;
CfgLinearFbReg <= 1'b0;
CfgPixelFmtReg <= 2'b00;
CfgBaseAddrReg <= 12'd0;
CfgTopLeftXReg <= {X_MSB+1{1'b0}};
CfgTopLeftYReg <= {Y_MSB+1{1'b0}};
CfgStartXReg <= {X_MSB+1{1'b0}};
CfgEndXReg <= {X_MSB+1{1'b0}};
CfgStartYReg <= {Y_MSB+1{1'b0}};
CfgEndYReg <= {Y_MSB+1{1'b0}};
end
else if (EN && WB_VS_STB_IN)
begin
CfgDitherReg <= CFG_DITHER_IN ;
CfgLinearFbReg <= CFG_LINEAR_FB_IN ;
CfgPixelFmtReg <= CFG_PIXEL_FMT_IN ;
CfgBaseAddrReg <= CFG_BASE_ADDR_IN ;
CfgTopLeftXReg <= CFG_TOP_LEFT_X_IN ;
CfgTopLeftYReg <= CFG_TOP_LEFT_Y_IN ;
CfgStartXReg <= CFG_START_X_IN ;
CfgEndXReg <= CFG_END_X_IN ;
CfgStartYReg <= CFG_START_Y_IN ;
CfgEndYReg <= CFG_END_Y_IN ;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : X_CNT
if (RST_ASYNC)
begin
FbXByte <= {X_MSB+1{1'b0}};
end
else if (RST_SYNC)
begin
FbXByte <= {X_MSB+1{1'b0}};
end
else if (EN && WB_ACTIVE_LINE_IN)
begin
if (WB_HS_STB_IN)
begin
FbXByte <= CfgStartXRegByte;
end
else if (BusReadDataEn)
begin
case (WbMasterBusSize)
WB_32B : FbXByte <= FbXByte + 4;
WB_16B : FbXByte <= FbXByte + 2;
WB_8B : FbXByte <= FbXByte + 1;
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : Y_CNT
if (RST_ASYNC)
begin
FbY <= {Y_MSB{1'b0}};
end
else if (RST_SYNC)
begin
FbY <= {Y_MSB{1'b0}};
end
else if (EN && WB_ACTIVE_LINE_IN)
begin
if (WB_VS_STB_IN)
begin
FbY <= {Y_MSB+1{1'b0}};
end
else if (WB_HS_STB_IN && (FbEndOfLine))
begin
FbY <= FbY + 1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_PIXEL_SHIFT_REG_CNT
if (RST_ASYNC)
begin
PixelByteCnt <= 5'd0;
end
else if (RST_SYNC)
begin
PixelByteCnt <= 5'd0;
end
else if (EN)
begin
if (BusReadDataEn)
begin
case (WbMasterBusSize)
WB_32B : PixelByteCnt <= PixelByteCnt + 5'd4;
WB_16B : PixelByteCnt <= PixelByteCnt + 5'd2;
WB_8B : PixelByteCnt <= PixelByteCnt + 5'd1;
endcase
end
else if (PixelDataEn)
begin
case (CfgPixelFmtReg)
PIXEL_FMT_PSX_16B :
begin
if (PixelByteCnt > 5'd2)
begin
PixelByteCnt <= PixelByteCnt - 5'd2;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
PIXEL_FMT_PSX_24B :
begin
if (PixelByteCnt > 5'd3)
begin
PixelByteCnt <= PixelByteCnt - 5'd3;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
PIXEL_FMT_RGB_8B :
begin
if (PixelByteCnt > 5'd1)
begin
PixelByteCnt <= PixelByteCnt - 5'd1;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
PIXEL_FMT_RGB_24B :
begin
if (PixelByteCnt > 5'd3)
begin
PixelByteCnt <= PixelByteCnt - 5'd3;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_PIXEL_SHIFT_REG
if (RST_ASYNC)
begin
PixelShiftReg <= 96'd0;
end
else if (RST_ASYNC)
begin
PixelShiftReg <= 96'd0;
end
else if (EN)
begin
if (BusReadDataEn)
begin
if (WB_32B == WbMasterBusSize)
begin
case (PixelByteCnt)
5'd0 : PixelShiftReg[ 31: 0] <= BusReadData ;
5'd1 : PixelShiftReg[ 39: 8] <= BusReadData ;
5'd2 : PixelShiftReg[ 47: 16] <= BusReadData ;
5'd3 : PixelShiftReg[ 55: 24] <= BusReadData ;
5'd4 : PixelShiftReg[ 63: 32] <= BusReadData ;
5'd5 : PixelShiftReg[ 71: 40] <= BusReadData ;
5'd6 : PixelShiftReg[ 79: 48] <= BusReadData ;
5'd7 : PixelShiftReg[ 87: 56] <= BusReadData ;
5'd8 : PixelShiftReg[ 95: 64] <= BusReadData ;
endcase
end
else if (WB_16B == WbMasterBusSize)
begin
case (PixelByteCnt)
5'd0 : PixelShiftReg[15: 0] <= BusReadData ;
5'd1 : PixelShiftReg[23: 8] <= BusReadData ;
5'd2 : PixelShiftReg[31:16] <= BusReadData ;
5'd3 : PixelShiftReg[39:24] <= BusReadData ;
5'd4 : PixelShiftReg[47:32] <= BusReadData ;
5'd5 : PixelShiftReg[55:40] <= BusReadData ;
5'd6 : PixelShiftReg[63:48] <= BusReadData ;
5'd7 : PixelShiftReg[71:56] <= BusReadData ;
5'd8 : PixelShiftReg[79:64] <= BusReadData ;
5'd9 : PixelShiftReg[87:72] <= BusReadData ;
5'd10 : PixelShiftReg[95:80] <= BusReadData ;
endcase
end
else if (WB_8B == WbMasterBusSize)
begin
case (PixelByteCnt)
5'd0 : PixelShiftReg[7 :0 ] <= BusReadData ;
5'd1 : PixelShiftReg[15:8 ] <= BusReadData ;
5'd2 : PixelShiftReg[23:16] <= BusReadData ;
5'd3 : PixelShiftReg[31:24] <= BusReadData ;
5'd4 : PixelShiftReg[39:32] <= BusReadData ;
5'd5 : PixelShiftReg[47:40] <= BusReadData ;
5'd6 : PixelShiftReg[55:48] <= BusReadData ;
5'd7 : PixelShiftReg[63:56] <= BusReadData ;
5'd8 : PixelShiftReg[71:64] <= BusReadData ;
5'd9 : PixelShiftReg[79:72] <= BusReadData ;
5'd10 : PixelShiftReg[87:80] <= BusReadData ;
5'd11 : PixelShiftReg[95:88] <= BusReadData ;
endcase
end
end
else if (PixelDataEn)
begin
case (CfgPixelFmtReg)
PIXEL_FMT_PSX_16B : PixelShiftReg <= {16'd0, PixelShiftReg[95:16]};
PIXEL_FMT_PSX_24B : PixelShiftReg <= {24'd0, PixelShiftReg[95:24]};
PIXEL_FMT_RGB_8B : PixelShiftReg <= {8'd0 , PixelShiftReg[95: 8]};
PIXEL_FMT_RGB_24B : PixelShiftReg <= {24'd0, PixelShiftReg[95:24]};
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_TMR
if (RST_ASYNC)
begin
BusTmrVal <= 5'd0;
end
else if (RST_SYNC)
begin
BusTmrVal <= 5'd0;
end
else if (EN)
begin
if (BusReadDataEn)
begin
BusTmrVal <= BusTmrVal - 5'd1;
end
else if (WbMasterRegEn)
begin
BusTmrVal <= WbMasterBusLen;
end
end
end
always @*
begin : WB_MASTER_ACCESS_DECODE
WbMasterBusSize = 2'b10;
WbMasterBusLen = 5'd3 ;
if (FbXBytesLeft >= 12)
begin
WbMasterBusSize = WB_32B;
WbMasterBusLen = 5'd3 ;
end
else if (FbXBytesLeft >= 8)
begin
WbMasterBusSize = WB_32B;
WbMasterBusLen = 5'd2 ;
end
else if (FbXBytesLeft >= 4)
begin
WbMasterBusSize = WB_32B;
WbMasterBusLen = 5'd1 ;
end
else if (FbXBytesLeft >= 2)
begin
WbMasterBusSize = WB_16B;
WbMasterBusLen = 5'd1 ;
end
else if (FbXBytesLeft > 0)
begin
WbMasterBusSize = WB_8B;
WbMasterBusLen = 5'd1 ;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WBM_REG
if (RST_ASYNC)
begin
WbMasterBusSizeReg <= 2'b00;
WbMasterBusLenReg <= 5'd0;
end
else if (RST_SYNC)
begin
WbMasterBusSizeReg <= 2'b00;
WbMasterBusLenReg <= 5'd0;
end
else if (EN && WbMasterRegEn)
begin
WbMasterBusSizeReg <= WbMasterBusSize;
WbMasterBusLenReg <= WbMasterBusLen;
end
end
always @*
begin : VDFSM_ST
VdfsmStateNxt = VdfsmStateCur;
BusReadReqNxt = 1'b0;
WbMasterRegEn = 1'b0;
PixelDataEn = 1'b0;
case (VdfsmStateCur)
VDFSM_IDLE :
begin
if (WB_HS_STB_IN && WB_ACTIVE_LINE_IN)
begin
VdfsmStateNxt = VDFSM_ACTIVE;
end
end
VDFSM_ACTIVE :
begin
if ((CfgEndXRegByte > FbXByte) & (!WB_PIXEL_DATA_FULL_IN))
begin
WbMasterRegEn = 1'b1;
BusReadReqNxt = 1'b1;
VdfsmStateNxt = VDFSM_REQ_DATA;
end
else
begin
VdfsmStateNxt = VDFSM_IDLE;
end
end
VDFSM_REQ_DATA :
begin
BusReadReqNxt = 1'b1;
if ((5'd1 == BusTmrVal) && (BusReadDataEn))
begin
BusReadReqNxt = 1'b0;
VdfsmStateNxt = VDFSM_PIXEL_DATA;
end
end
VDFSM_PIXEL_DATA :
begin
PixelDataEn = 1'b1;
if (5'd0 == PixelByteCnt)
begin
PixelDataEn = 1'b0;
VdfsmStateNxt = VDFSM_ACTIVE;
end
end
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : VDFSM_CP
if (RST_ASYNC)
begin
BusReadReq <= 1'b0;
VdfsmStateCur <= VDFSM_IDLE;
end
else if (RST_SYNC)
begin
BusReadReq <= 1'b0;
VdfsmStateCur <= VDFSM_IDLE;
end
else if (EN)
begin
BusReadReq <= BusReadReqNxt;
VdfsmStateCur <= VdfsmStateNxt;
end
end
WB_MASTER wb_master
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_ADR_OUT (WB_ADR_OUT ),
.WB_CYC_OUT (WB_CYC_OUT ),
.WB_STB_OUT (WB_STB_OUT ),
.WB_WE_OUT (WB_WE_OUT ),
.WB_SEL_OUT (WB_SEL_OUT ),
.WB_CTI_OUT (WB_CTI_OUT ),
.WB_BTE_OUT (WB_BTE_OUT ),
.WB_STALL_IN (WB_STALL_IN ),
.WB_ACK_IN (WB_ACK_IN ),
.WB_ERR_IN (WB_ERR_IN ),
.WB_DAT_RD_IN (WB_DAT_RD_IN ),
.WB_DAT_WR_OUT (WB_DAT_WR_OUT ),
.BUS_START_ADDR_IN (BusAddr ),
.BUS_READ_REQ_IN (BusReadReq ),
.BUS_READ_ACK_OUT (BusReadAck ),
.BUS_WRITE_REQ_IN (1'b0),
.BUS_WRITE_ACK_OUT ( ),
.BUS_LAST_ACK_OUT ( ),
.BUS_SIZE_IN (WbMasterBusSizeReg ),
.BUS_LEN_IN (WbMasterBusLenReg ),
.BUS_BURST_ADDR_INC_IN (1'b1 ),
.BUS_READ_DATA_OUT (BusReadData ),
.BUS_WRITE_DATA_IN (32'h0000_0000 )
);
endmodule | module VGA_DMA
#(parameter X_MSB = 0,
parameter Y_MSB = 0,
parameter R_HI = 7,
parameter R_LO = 5,
parameter G_HI = 4,
parameter G_LO = 2,
parameter B_HI = 1,
parameter B_LO = 0
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_STALL_IN ,
input WB_ACK_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT ,
output WB_PIXEL_DATA_EN_OUT ,
output [7:0] WB_PIXEL_DATA_OUT ,
input WB_PIXEL_DATA_FULL_IN ,
input WB_VS_STB_IN ,
input WB_HS_STB_IN ,
input WB_ACTIVE_LINE_IN ,
input CFG_DITHER_IN ,
input CFG_LINEAR_FB_IN ,
input [ 1: 0] CFG_PIXEL_FMT_IN ,
input [ 31:20] CFG_BASE_ADDR_IN ,
input [X_MSB: 0] CFG_TOP_LEFT_X_IN ,
input [Y_MSB: 0] CFG_TOP_LEFT_Y_IN ,
input [X_MSB: 0] CFG_START_X_IN ,
input [X_MSB: 0] CFG_END_X_IN ,
input [Y_MSB: 0] CFG_START_Y_IN ,
input [Y_MSB: 0] CFG_END_Y_IN
); |
parameter [1:0] WB_8B = 2'b00;
parameter [1:0] WB_16B = 2'b01;
parameter [1:0] WB_32B = 2'b10;
parameter [1:0] PIXEL_FMT_PSX_16B = 2'b00;
parameter [1:0] PIXEL_FMT_PSX_24B = 2'b01;
parameter [1:0] PIXEL_FMT_RGB_8B = 2'b10;
parameter [1:0] PIXEL_FMT_RGB_24B = 2'b11;
parameter [1:0] VDFSM_IDLE = 2'b00;
parameter [1:0] VDFSM_ACTIVE = 2'b01;
parameter [1:0] VDFSM_REQ_DATA = 2'b10;
parameter [1:0] VDFSM_PIXEL_DATA = 2'b11;
reg [1:0] VdfsmStateCur;
reg [1:0] VdfsmStateNxt;
reg [4:0] BusTmrVal;
reg BusReadReqNxt;
reg BusReadReq;
reg WbMasterRegEn;
reg PixelDataEn;
reg CfgDitherReg ;
reg CfgLinearFbReg ;
reg [ 1: 0] CfgPixelFmtReg ;
reg [ 31:20] CfgBaseAddrReg ;
reg [X_MSB: 0] CfgTopLeftXReg ;
reg [Y_MSB: 0] CfgTopLeftYReg ;
reg [X_MSB: 0] CfgStartXReg ;
reg [X_MSB: 0] CfgEndXReg ;
reg [Y_MSB: 0] CfgStartYReg ;
reg [Y_MSB: 0] CfgEndYReg ;
wire [X_MSB+1:0] CfgStartXRegByte = {CfgStartXReg, 1'b0};
wire [X_MSB+1:0] CfgEndXRegByte = {CfgEndXReg , 1'b0};
wire [X_MSB+Y_MSB+2:0] LinearFbXY;
reg [X_MSB+1:0] FbXByte;
wire [X_MSB+1:0] FbXBytesLeft = CfgEndXRegByte - FbXByte;
wire FbEndOfLine = (FbXByte >= CfgEndXRegByte);
reg [Y_MSB:0] FbY;
wire FbEndOfFrame = (FbY == CfgEndYReg);
wire [31:0] BusAddr = CfgLinearFbReg ? {CfgBaseAddrReg ,
LinearFbXY
} :
{CfgBaseAddrReg ,
FbY ,
FbXByte
};
wire BusReadAck ;
wire BusReadDataEn = BusReadReq & BusReadAck;
wire [31:0] BusReadData;
reg [ 4:0] PixelByteCnt;
reg [ 95:0] PixelShiftReg;
reg [1:0] WbMasterBusSize ;
reg [4:0] WbMasterBusLen ;
reg [1:0] WbMasterBusSizeReg ;
reg [4:0] WbMasterBusLenReg ;
assign LinearFbXY = (CfgStartXRegByte + FbXByte) + (CfgStartYReg + (FbY * CfgEndXRegByte));
assign WB_PIXEL_DATA_EN_OUT = PixelDataEn;
assign WB_PIXEL_DATA_OUT[R_HI:R_LO] = PixelShiftReg[ 7: 5];
assign WB_PIXEL_DATA_OUT[G_HI:G_LO] = PixelShiftReg[15:13];
assign WB_PIXEL_DATA_OUT[B_HI:B_LO] = PixelShiftReg[23:22];
always @(posedge CLK or posedge RST_ASYNC)
begin : CONFIG_REG
if (RST_ASYNC)
begin
CfgDitherReg <= 1'b0;
CfgLinearFbReg <= 1'b0;
CfgPixelFmtReg <= 2'b00;
CfgBaseAddrReg <= 12'd0;
CfgTopLeftXReg <= {X_MSB+1{1'b0}};
CfgTopLeftYReg <= {Y_MSB+1{1'b0}};
CfgStartXReg <= {X_MSB+1{1'b0}};
CfgEndXReg <= {X_MSB+1{1'b0}};
CfgStartYReg <= {Y_MSB+1{1'b0}};
CfgEndYReg <= {Y_MSB+1{1'b0}};
end
else if (RST_SYNC)
begin
CfgDitherReg <= 1'b0;
CfgLinearFbReg <= 1'b0;
CfgPixelFmtReg <= 2'b00;
CfgBaseAddrReg <= 12'd0;
CfgTopLeftXReg <= {X_MSB+1{1'b0}};
CfgTopLeftYReg <= {Y_MSB+1{1'b0}};
CfgStartXReg <= {X_MSB+1{1'b0}};
CfgEndXReg <= {X_MSB+1{1'b0}};
CfgStartYReg <= {Y_MSB+1{1'b0}};
CfgEndYReg <= {Y_MSB+1{1'b0}};
end
else if (EN && WB_VS_STB_IN)
begin
CfgDitherReg <= CFG_DITHER_IN ;
CfgLinearFbReg <= CFG_LINEAR_FB_IN ;
CfgPixelFmtReg <= CFG_PIXEL_FMT_IN ;
CfgBaseAddrReg <= CFG_BASE_ADDR_IN ;
CfgTopLeftXReg <= CFG_TOP_LEFT_X_IN ;
CfgTopLeftYReg <= CFG_TOP_LEFT_Y_IN ;
CfgStartXReg <= CFG_START_X_IN ;
CfgEndXReg <= CFG_END_X_IN ;
CfgStartYReg <= CFG_START_Y_IN ;
CfgEndYReg <= CFG_END_Y_IN ;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : X_CNT
if (RST_ASYNC)
begin
FbXByte <= {X_MSB+1{1'b0}};
end
else if (RST_SYNC)
begin
FbXByte <= {X_MSB+1{1'b0}};
end
else if (EN && WB_ACTIVE_LINE_IN)
begin
if (WB_HS_STB_IN)
begin
FbXByte <= CfgStartXRegByte;
end
else if (BusReadDataEn)
begin
case (WbMasterBusSize)
WB_32B : FbXByte <= FbXByte + 4;
WB_16B : FbXByte <= FbXByte + 2;
WB_8B : FbXByte <= FbXByte + 1;
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : Y_CNT
if (RST_ASYNC)
begin
FbY <= {Y_MSB{1'b0}};
end
else if (RST_SYNC)
begin
FbY <= {Y_MSB{1'b0}};
end
else if (EN && WB_ACTIVE_LINE_IN)
begin
if (WB_VS_STB_IN)
begin
FbY <= {Y_MSB+1{1'b0}};
end
else if (WB_HS_STB_IN && (FbEndOfLine))
begin
FbY <= FbY + 1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_PIXEL_SHIFT_REG_CNT
if (RST_ASYNC)
begin
PixelByteCnt <= 5'd0;
end
else if (RST_SYNC)
begin
PixelByteCnt <= 5'd0;
end
else if (EN)
begin
if (BusReadDataEn)
begin
case (WbMasterBusSize)
WB_32B : PixelByteCnt <= PixelByteCnt + 5'd4;
WB_16B : PixelByteCnt <= PixelByteCnt + 5'd2;
WB_8B : PixelByteCnt <= PixelByteCnt + 5'd1;
endcase
end
else if (PixelDataEn)
begin
case (CfgPixelFmtReg)
PIXEL_FMT_PSX_16B :
begin
if (PixelByteCnt > 5'd2)
begin
PixelByteCnt <= PixelByteCnt - 5'd2;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
PIXEL_FMT_PSX_24B :
begin
if (PixelByteCnt > 5'd3)
begin
PixelByteCnt <= PixelByteCnt - 5'd3;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
PIXEL_FMT_RGB_8B :
begin
if (PixelByteCnt > 5'd1)
begin
PixelByteCnt <= PixelByteCnt - 5'd1;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
PIXEL_FMT_RGB_24B :
begin
if (PixelByteCnt > 5'd3)
begin
PixelByteCnt <= PixelByteCnt - 5'd3;
end
else
begin
PixelByteCnt <= 5'd0;
end
end
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_PIXEL_SHIFT_REG
if (RST_ASYNC)
begin
PixelShiftReg <= 96'd0;
end
else if (RST_ASYNC)
begin
PixelShiftReg <= 96'd0;
end
else if (EN)
begin
if (BusReadDataEn)
begin
if (WB_32B == WbMasterBusSize)
begin
case (PixelByteCnt)
5'd0 : PixelShiftReg[ 31: 0] <= BusReadData ;
5'd1 : PixelShiftReg[ 39: 8] <= BusReadData ;
5'd2 : PixelShiftReg[ 47: 16] <= BusReadData ;
5'd3 : PixelShiftReg[ 55: 24] <= BusReadData ;
5'd4 : PixelShiftReg[ 63: 32] <= BusReadData ;
5'd5 : PixelShiftReg[ 71: 40] <= BusReadData ;
5'd6 : PixelShiftReg[ 79: 48] <= BusReadData ;
5'd7 : PixelShiftReg[ 87: 56] <= BusReadData ;
5'd8 : PixelShiftReg[ 95: 64] <= BusReadData ;
endcase
end
else if (WB_16B == WbMasterBusSize)
begin
case (PixelByteCnt)
5'd0 : PixelShiftReg[15: 0] <= BusReadData ;
5'd1 : PixelShiftReg[23: 8] <= BusReadData ;
5'd2 : PixelShiftReg[31:16] <= BusReadData ;
5'd3 : PixelShiftReg[39:24] <= BusReadData ;
5'd4 : PixelShiftReg[47:32] <= BusReadData ;
5'd5 : PixelShiftReg[55:40] <= BusReadData ;
5'd6 : PixelShiftReg[63:48] <= BusReadData ;
5'd7 : PixelShiftReg[71:56] <= BusReadData ;
5'd8 : PixelShiftReg[79:64] <= BusReadData ;
5'd9 : PixelShiftReg[87:72] <= BusReadData ;
5'd10 : PixelShiftReg[95:80] <= BusReadData ;
endcase
end
else if (WB_8B == WbMasterBusSize)
begin
case (PixelByteCnt)
5'd0 : PixelShiftReg[7 :0 ] <= BusReadData ;
5'd1 : PixelShiftReg[15:8 ] <= BusReadData ;
5'd2 : PixelShiftReg[23:16] <= BusReadData ;
5'd3 : PixelShiftReg[31:24] <= BusReadData ;
5'd4 : PixelShiftReg[39:32] <= BusReadData ;
5'd5 : PixelShiftReg[47:40] <= BusReadData ;
5'd6 : PixelShiftReg[55:48] <= BusReadData ;
5'd7 : PixelShiftReg[63:56] <= BusReadData ;
5'd8 : PixelShiftReg[71:64] <= BusReadData ;
5'd9 : PixelShiftReg[79:72] <= BusReadData ;
5'd10 : PixelShiftReg[87:80] <= BusReadData ;
5'd11 : PixelShiftReg[95:88] <= BusReadData ;
endcase
end
end
else if (PixelDataEn)
begin
case (CfgPixelFmtReg)
PIXEL_FMT_PSX_16B : PixelShiftReg <= {16'd0, PixelShiftReg[95:16]};
PIXEL_FMT_PSX_24B : PixelShiftReg <= {24'd0, PixelShiftReg[95:24]};
PIXEL_FMT_RGB_8B : PixelShiftReg <= {8'd0 , PixelShiftReg[95: 8]};
PIXEL_FMT_RGB_24B : PixelShiftReg <= {24'd0, PixelShiftReg[95:24]};
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_TMR
if (RST_ASYNC)
begin
BusTmrVal <= 5'd0;
end
else if (RST_SYNC)
begin
BusTmrVal <= 5'd0;
end
else if (EN)
begin
if (BusReadDataEn)
begin
BusTmrVal <= BusTmrVal - 5'd1;
end
else if (WbMasterRegEn)
begin
BusTmrVal <= WbMasterBusLen;
end
end
end
always @*
begin : WB_MASTER_ACCESS_DECODE
WbMasterBusSize = 2'b10;
WbMasterBusLen = 5'd3 ;
if (FbXBytesLeft >= 12)
begin
WbMasterBusSize = WB_32B;
WbMasterBusLen = 5'd3 ;
end
else if (FbXBytesLeft >= 8)
begin
WbMasterBusSize = WB_32B;
WbMasterBusLen = 5'd2 ;
end
else if (FbXBytesLeft >= 4)
begin
WbMasterBusSize = WB_32B;
WbMasterBusLen = 5'd1 ;
end
else if (FbXBytesLeft >= 2)
begin
WbMasterBusSize = WB_16B;
WbMasterBusLen = 5'd1 ;
end
else if (FbXBytesLeft > 0)
begin
WbMasterBusSize = WB_8B;
WbMasterBusLen = 5'd1 ;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WBM_REG
if (RST_ASYNC)
begin
WbMasterBusSizeReg <= 2'b00;
WbMasterBusLenReg <= 5'd0;
end
else if (RST_SYNC)
begin
WbMasterBusSizeReg <= 2'b00;
WbMasterBusLenReg <= 5'd0;
end
else if (EN && WbMasterRegEn)
begin
WbMasterBusSizeReg <= WbMasterBusSize;
WbMasterBusLenReg <= WbMasterBusLen;
end
end
always @*
begin : VDFSM_ST
VdfsmStateNxt = VdfsmStateCur;
BusReadReqNxt = 1'b0;
WbMasterRegEn = 1'b0;
PixelDataEn = 1'b0;
case (VdfsmStateCur)
VDFSM_IDLE :
begin
if (WB_HS_STB_IN && WB_ACTIVE_LINE_IN)
begin
VdfsmStateNxt = VDFSM_ACTIVE;
end
end
VDFSM_ACTIVE :
begin
if ((CfgEndXRegByte > FbXByte) & (!WB_PIXEL_DATA_FULL_IN))
begin
WbMasterRegEn = 1'b1;
BusReadReqNxt = 1'b1;
VdfsmStateNxt = VDFSM_REQ_DATA;
end
else
begin
VdfsmStateNxt = VDFSM_IDLE;
end
end
VDFSM_REQ_DATA :
begin
BusReadReqNxt = 1'b1;
if ((5'd1 == BusTmrVal) && (BusReadDataEn))
begin
BusReadReqNxt = 1'b0;
VdfsmStateNxt = VDFSM_PIXEL_DATA;
end
end
VDFSM_PIXEL_DATA :
begin
PixelDataEn = 1'b1;
if (5'd0 == PixelByteCnt)
begin
PixelDataEn = 1'b0;
VdfsmStateNxt = VDFSM_ACTIVE;
end
end
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : VDFSM_CP
if (RST_ASYNC)
begin
BusReadReq <= 1'b0;
VdfsmStateCur <= VDFSM_IDLE;
end
else if (RST_SYNC)
begin
BusReadReq <= 1'b0;
VdfsmStateCur <= VDFSM_IDLE;
end
else if (EN)
begin
BusReadReq <= BusReadReqNxt;
VdfsmStateCur <= VdfsmStateNxt;
end
end
WB_MASTER wb_master
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (RST_SYNC ),
.RST_ASYNC (RST_ASYNC ),
.WB_ADR_OUT (WB_ADR_OUT ),
.WB_CYC_OUT (WB_CYC_OUT ),
.WB_STB_OUT (WB_STB_OUT ),
.WB_WE_OUT (WB_WE_OUT ),
.WB_SEL_OUT (WB_SEL_OUT ),
.WB_CTI_OUT (WB_CTI_OUT ),
.WB_BTE_OUT (WB_BTE_OUT ),
.WB_STALL_IN (WB_STALL_IN ),
.WB_ACK_IN (WB_ACK_IN ),
.WB_ERR_IN (WB_ERR_IN ),
.WB_DAT_RD_IN (WB_DAT_RD_IN ),
.WB_DAT_WR_OUT (WB_DAT_WR_OUT ),
.BUS_START_ADDR_IN (BusAddr ),
.BUS_READ_REQ_IN (BusReadReq ),
.BUS_READ_ACK_OUT (BusReadAck ),
.BUS_WRITE_REQ_IN (1'b0),
.BUS_WRITE_ACK_OUT ( ),
.BUS_LAST_ACK_OUT ( ),
.BUS_SIZE_IN (WbMasterBusSizeReg ),
.BUS_LEN_IN (WbMasterBusLenReg ),
.BUS_BURST_ADDR_INC_IN (1'b1 ),
.BUS_READ_DATA_OUT (BusReadData ),
.BUS_WRITE_DATA_IN (32'h0000_0000 )
);
endmodule | 1 |
138,406 | data/full_repos/permissive/83270534/vga_controller/rtl/vga_top.v | 83,270,534 | vga_top.v | v | 218 | 105 | [] | [] | [] | [(7, 216)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/vga_controller/rtl/vga_top.v:98: Cannot find file containing module: 'VGA_DMA'\n VGA_DMA\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/VGA_DMA\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/VGA_DMA.v\n data/full_repos/permissive/83270534/vga_controller/rtl,data/full_repos/permissive/83270534/VGA_DMA.sv\n VGA_DMA\n VGA_DMA.v\n VGA_DMA.sv\n obj_dir/VGA_DMA\n obj_dir/VGA_DMA.v\n obj_dir/VGA_DMA.sv\n%Error: data/full_repos/permissive/83270534/vga_controller/rtl/vga_top.v:151: Cannot find file containing module: 'VGA_CDC'\n VGA_CDC vga_cdc\n ^~~~~~~\n%Error: data/full_repos/permissive/83270534/vga_controller/rtl/vga_top.v:178: Cannot find file containing module: 'VGA_DRIVER'\n VGA_DRIVER \n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 302,325 | module | module VGA_TOP
#(parameter X_MSB = 0,
parameter Y_MSB = 0,
parameter R_HI = 7,
parameter R_LO = 5,
parameter G_HI = 4,
parameter G_LO = 2,
parameter B_HI = 1,
parameter B_LO = 0
)
(
input CLK_VGA ,
input EN_VGA ,
input RST_SYNC_VGA ,
input RST_ASYNC_VGA ,
input CLK_WB ,
input EN_WB ,
input RST_SYNC_WB ,
input RST_ASYNC_WB ,
input VGA_TEST_EN_IN,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_ACK_IN ,
input WB_STALL_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT ,
output VGA_VS_OUT ,
output VGA_HS_OUT ,
output [2:0] VGA_RED_OUT ,
output [2:0] VGA_GREEN_OUT ,
output [1:0] VGA_BLUE_OUT ,
output WB_RCNT_ACTIVE_ROW_OUT ,
output WB_RCNT_ACTIVE_COL_OUT ,
input CFG_DITHER_IN ,
input CFG_LINEAR_FB_IN ,
input [ 1: 0] CFG_PIXEL_FMT_IN ,
input [ 31:20] CFG_BASE_ADDR_IN ,
input [X_MSB: 0] CFG_TOP_LEFT_X_IN ,
input [Y_MSB: 0] CFG_TOP_LEFT_Y_IN ,
input [X_MSB: 0] CFG_START_X_IN ,
input [X_MSB: 0] CFG_END_X_IN ,
input [Y_MSB: 0] CFG_START_Y_IN ,
input [Y_MSB: 0] CFG_END_Y_IN
);
wire WbPixelDataEn ;
wire [7:0] WbPixelData ;
wire WbPixelDataFull ;
wire WbActiveLine ;
wire WbVsStb ;
wire WbHsStb ;
wire VgaPixelDataEn ;
wire VgaActiveLine ;
wire [7:0] VgaPixelData ;
wire VgaVsStb ;
wire VgaHsStb ;
assign VGA_VS_OUT = VgaVsStb;
assign VGA_HS_OUT = VgaHsStb;
VGA_DMA
#( .X_MSB (X_MSB),
.Y_MSB (Y_MSB),
.R_HI (R_HI ),
.R_LO (R_LO ),
.G_HI (G_HI ),
.G_LO (G_LO ),
.B_HI (B_HI ),
.B_LO (B_LO )
)
vga_dma
(
.CLK (CLK_WB ),
.EN (EN_WB & ~VGA_TEST_EN_IN ),
.RST_SYNC (~EN_WB | VGA_TEST_EN_IN ),
.RST_ASYNC (RST_ASYNC_WB | VGA_TEST_EN_IN ),
.WB_ADR_OUT (WB_ADR_OUT ),
.WB_CYC_OUT (WB_CYC_OUT ),
.WB_STB_OUT (WB_STB_OUT ),
.WB_WE_OUT (WB_WE_OUT ),
.WB_SEL_OUT (WB_SEL_OUT ),
.WB_CTI_OUT (WB_CTI_OUT ),
.WB_BTE_OUT (WB_BTE_OUT ),
.WB_ACK_IN (WB_ACK_IN ),
.WB_STALL_IN (WB_STALL_IN ),
.WB_ERR_IN (WB_ERR_IN ),
.WB_DAT_RD_IN (WB_DAT_RD_IN ),
.WB_DAT_WR_OUT (WB_DAT_WR_OUT ),
.WB_PIXEL_DATA_EN_OUT (WbPixelDataEn ),
.WB_PIXEL_DATA_OUT (WbPixelData ),
.WB_PIXEL_DATA_FULL_IN (WbPixelDataFull ),
.WB_VS_STB_IN (WbVsStb ),
.WB_HS_STB_IN (WbHsStb ),
.WB_ACTIVE_LINE_IN (WbActiveLine ),
.CFG_DITHER_IN (CFG_DITHER_IN ),
.CFG_LINEAR_FB_IN (CFG_LINEAR_FB_IN ),
.CFG_PIXEL_FMT_IN (CFG_PIXEL_FMT_IN ),
.CFG_BASE_ADDR_IN (CFG_BASE_ADDR_IN ),
.CFG_TOP_LEFT_X_IN (CFG_TOP_LEFT_X_IN ),
.CFG_TOP_LEFT_Y_IN (CFG_TOP_LEFT_Y_IN ),
.CFG_START_X_IN (CFG_START_X_IN ),
.CFG_END_X_IN (CFG_END_X_IN ),
.CFG_START_Y_IN (CFG_START_Y_IN ),
.CFG_END_Y_IN (CFG_END_Y_IN )
);
VGA_CDC vga_cdc
(
.CLK_VGA (CLK_VGA ),
.RST_ASYNC_VGA (RST_ASYNC_VGA ),
.CLK_WB (CLK_WB ),
.RST_ASYNC_WB (RST_ASYNC_WB ),
.VGA_DATA_OUT (VgaPixelData ),
.VGA_DATA_REQ_IN (VgaPixelDataEn ),
.VGA_ACTIVE_LINE_IN (VgaActiveLine ),
.VGA_HS_IN (VgaHsStb ),
.VGA_VS_IN (VgaVsStb ),
.WB_DATA_EN_IN (WbPixelDataEn ),
.WB_DATA_IN (WbPixelData ),
.WB_DATA_FULL_OUT (WbPixelDataFull ),
.WB_ACTIVE_LINE_OUT (WbActiveLine ),
.WB_VS_STB_OUT (WbVsStb ),
.WB_HS_STB_OUT (WbHsStb ),
.WB_RCNT_ACTIVE_ROW_OUT (WB_RCNT_ACTIVE_ROW_OUT),
.WB_RCNT_ACTIVE_COL_OUT (WB_RCNT_ACTIVE_COL_OUT)
);
VGA_DRIVER
#(
.R_HI (7),
.R_LO (5),
.G_HI (4),
.G_LO (2),
.B_HI (1),
.B_LO (0)
)
vga_driver
(
.CLK (CLK_VGA ),
.EN (EN_VGA ),
.RST_SYNC (RST_SYNC_VGA ),
.RST_ASYNC (RST_ASYNC_VGA ),
.VGA_TEST_EN_IN (VGA_TEST_EN_IN ),
.VGA_DATA_IN (VgaPixelData ),
.VGA_DATA_REQ_OUT (VgaPixelDataEn ),
.VGA_ACTIVE_LINE_OUT (VgaActiveLine ),
.VGA_VS_OUT (VgaVsStb ),
.VGA_HS_OUT (VgaHsStb ),
.VGA_RED_OUT (VGA_RED_OUT ),
.VGA_GREEN_OUT (VGA_GREEN_OUT ),
.VGA_BLUE_OUT (VGA_BLUE_OUT )
);
endmodule | module VGA_TOP
#(parameter X_MSB = 0,
parameter Y_MSB = 0,
parameter R_HI = 7,
parameter R_LO = 5,
parameter G_HI = 4,
parameter G_LO = 2,
parameter B_HI = 1,
parameter B_LO = 0
)
(
input CLK_VGA ,
input EN_VGA ,
input RST_SYNC_VGA ,
input RST_ASYNC_VGA ,
input CLK_WB ,
input EN_WB ,
input RST_SYNC_WB ,
input RST_ASYNC_WB ,
input VGA_TEST_EN_IN,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_ACK_IN ,
input WB_STALL_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT ,
output VGA_VS_OUT ,
output VGA_HS_OUT ,
output [2:0] VGA_RED_OUT ,
output [2:0] VGA_GREEN_OUT ,
output [1:0] VGA_BLUE_OUT ,
output WB_RCNT_ACTIVE_ROW_OUT ,
output WB_RCNT_ACTIVE_COL_OUT ,
input CFG_DITHER_IN ,
input CFG_LINEAR_FB_IN ,
input [ 1: 0] CFG_PIXEL_FMT_IN ,
input [ 31:20] CFG_BASE_ADDR_IN ,
input [X_MSB: 0] CFG_TOP_LEFT_X_IN ,
input [Y_MSB: 0] CFG_TOP_LEFT_Y_IN ,
input [X_MSB: 0] CFG_START_X_IN ,
input [X_MSB: 0] CFG_END_X_IN ,
input [Y_MSB: 0] CFG_START_Y_IN ,
input [Y_MSB: 0] CFG_END_Y_IN
); |
wire WbPixelDataEn ;
wire [7:0] WbPixelData ;
wire WbPixelDataFull ;
wire WbActiveLine ;
wire WbVsStb ;
wire WbHsStb ;
wire VgaPixelDataEn ;
wire VgaActiveLine ;
wire [7:0] VgaPixelData ;
wire VgaVsStb ;
wire VgaHsStb ;
assign VGA_VS_OUT = VgaVsStb;
assign VGA_HS_OUT = VgaHsStb;
VGA_DMA
#( .X_MSB (X_MSB),
.Y_MSB (Y_MSB),
.R_HI (R_HI ),
.R_LO (R_LO ),
.G_HI (G_HI ),
.G_LO (G_LO ),
.B_HI (B_HI ),
.B_LO (B_LO )
)
vga_dma
(
.CLK (CLK_WB ),
.EN (EN_WB & ~VGA_TEST_EN_IN ),
.RST_SYNC (~EN_WB | VGA_TEST_EN_IN ),
.RST_ASYNC (RST_ASYNC_WB | VGA_TEST_EN_IN ),
.WB_ADR_OUT (WB_ADR_OUT ),
.WB_CYC_OUT (WB_CYC_OUT ),
.WB_STB_OUT (WB_STB_OUT ),
.WB_WE_OUT (WB_WE_OUT ),
.WB_SEL_OUT (WB_SEL_OUT ),
.WB_CTI_OUT (WB_CTI_OUT ),
.WB_BTE_OUT (WB_BTE_OUT ),
.WB_ACK_IN (WB_ACK_IN ),
.WB_STALL_IN (WB_STALL_IN ),
.WB_ERR_IN (WB_ERR_IN ),
.WB_DAT_RD_IN (WB_DAT_RD_IN ),
.WB_DAT_WR_OUT (WB_DAT_WR_OUT ),
.WB_PIXEL_DATA_EN_OUT (WbPixelDataEn ),
.WB_PIXEL_DATA_OUT (WbPixelData ),
.WB_PIXEL_DATA_FULL_IN (WbPixelDataFull ),
.WB_VS_STB_IN (WbVsStb ),
.WB_HS_STB_IN (WbHsStb ),
.WB_ACTIVE_LINE_IN (WbActiveLine ),
.CFG_DITHER_IN (CFG_DITHER_IN ),
.CFG_LINEAR_FB_IN (CFG_LINEAR_FB_IN ),
.CFG_PIXEL_FMT_IN (CFG_PIXEL_FMT_IN ),
.CFG_BASE_ADDR_IN (CFG_BASE_ADDR_IN ),
.CFG_TOP_LEFT_X_IN (CFG_TOP_LEFT_X_IN ),
.CFG_TOP_LEFT_Y_IN (CFG_TOP_LEFT_Y_IN ),
.CFG_START_X_IN (CFG_START_X_IN ),
.CFG_END_X_IN (CFG_END_X_IN ),
.CFG_START_Y_IN (CFG_START_Y_IN ),
.CFG_END_Y_IN (CFG_END_Y_IN )
);
VGA_CDC vga_cdc
(
.CLK_VGA (CLK_VGA ),
.RST_ASYNC_VGA (RST_ASYNC_VGA ),
.CLK_WB (CLK_WB ),
.RST_ASYNC_WB (RST_ASYNC_WB ),
.VGA_DATA_OUT (VgaPixelData ),
.VGA_DATA_REQ_IN (VgaPixelDataEn ),
.VGA_ACTIVE_LINE_IN (VgaActiveLine ),
.VGA_HS_IN (VgaHsStb ),
.VGA_VS_IN (VgaVsStb ),
.WB_DATA_EN_IN (WbPixelDataEn ),
.WB_DATA_IN (WbPixelData ),
.WB_DATA_FULL_OUT (WbPixelDataFull ),
.WB_ACTIVE_LINE_OUT (WbActiveLine ),
.WB_VS_STB_OUT (WbVsStb ),
.WB_HS_STB_OUT (WbHsStb ),
.WB_RCNT_ACTIVE_ROW_OUT (WB_RCNT_ACTIVE_ROW_OUT),
.WB_RCNT_ACTIVE_COL_OUT (WB_RCNT_ACTIVE_COL_OUT)
);
VGA_DRIVER
#(
.R_HI (7),
.R_LO (5),
.G_HI (4),
.G_LO (2),
.B_HI (1),
.B_LO (0)
)
vga_driver
(
.CLK (CLK_VGA ),
.EN (EN_VGA ),
.RST_SYNC (RST_SYNC_VGA ),
.RST_ASYNC (RST_ASYNC_VGA ),
.VGA_TEST_EN_IN (VGA_TEST_EN_IN ),
.VGA_DATA_IN (VgaPixelData ),
.VGA_DATA_REQ_OUT (VgaPixelDataEn ),
.VGA_ACTIVE_LINE_OUT (VgaActiveLine ),
.VGA_VS_OUT (VgaVsStb ),
.VGA_HS_OUT (VgaHsStb ),
.VGA_RED_OUT (VGA_RED_OUT ),
.VGA_GREEN_OUT (VGA_GREEN_OUT ),
.VGA_BLUE_OUT (VGA_BLUE_OUT )
);
endmodule | 1 |
138,410 | data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v | 83,270,534 | testcase.v | v | 61 | 80 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:5: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:12: Define or directive not defined: \'`VGA_TEST_EN\'\n force `VGA_TEST_EN = 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:12: syntax error, unexpected \'=\', expecting TYPE-IDENTIFIER\n force `VGA_TEST_EN = 1\'b1;\n ^\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:15: Define or directive not defined: \'`RST\'\n @(negedge `RST);\n ^~~~\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:19: syntax error, unexpected \'@\'\n @(negedge `TB.VgaVs);\n ^\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:19: Define or directive not defined: \'`TB\'\n @(negedge `TB.VgaVs);\n ^~~\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:21: syntax error, unexpected \'@\'\n @(negedge `TB.VgaVs);\n ^\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:21: Define or directive not defined: \'`TB\'\n @(negedge `TB.VgaVs);\n ^~~\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:26: syntax error, unexpected \'@\'\n @(negedge `TB.VgaHs);\n ^\n%Error: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:26: Define or directive not defined: \'`TB\'\n @(negedge `TB.VgaHs);\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/vga_controller/sim/vga/testmode/testcase.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100ms;\n ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 302,329 | module | module TESTCASE ();
`include "tb_defines.v"
initial
begin
$display("[INFO ] Setting VGA Test Mode input at time %t", $time);
force `VGA_TEST_EN = 1'b1;
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
@(negedge `TB.VgaVs);
$display("[INFO ] Start of frame at time %t", $time);
@(negedge `TB.VgaVs);
$display("[INFO ] End of frame at time %t", $time);
repeat (10)
@(negedge `TB.VgaHs);
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`include "tb_defines.v"
initial
begin
$display("[INFO ] Setting VGA Test Mode input at time %t", $time);
force `VGA_TEST_EN = 1'b1;
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
@(negedge `TB.VgaVs);
$display("[INFO ] Start of frame at time %t", $time);
@(negedge `TB.VgaVs);
$display("[INFO ] End of frame at time %t", $time);
repeat (10)
@(negedge `TB.VgaHs);
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,411 | data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v | 83,270,534 | tb_top.v | v | 274 | 95 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:4: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/vga_controller/tb,data/full_repos/permissive/83270534/tb_defines.v\n data/full_repos/permissive/83270534/vga_controller/tb,data/full_repos/permissive/83270534/tb_defines.v.v\n data/full_repos/permissive/83270534/vga_controller/tb,data/full_repos/permissive/83270534/tb_defines.v.sv\n tb_defines.v\n tb_defines.v.v\n tb_defines.v.sv\n obj_dir/tb_defines.v\n obj_dir/tb_defines.v.v\n obj_dir/tb_defines.v.sv\n%Error: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:100: syntax error, unexpected \'@\'\n @(posedge ClkVga);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:107: Unsupported: Ignoring delay on this delayed statement.\n always #CLK_VGA_HALF_PERIOD ClkVga = !ClkVga;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:114: syntax error, unexpected \'@\'\n @(posedge ClkWb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:121: Unsupported: Ignoring delay on this delayed statement.\n always #CLK_WB_HALF_PERIOD ClkWb = !ClkWb;\n ^\n%Error: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:128: Define or directive not defined: \'`VGA_FIFO_RD_EMPTY\'\n if (`VGA_FIFO_RD_EMPTY && `VGA_FIFO_RD_EN && !VgaTestEn)\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:128: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if (`VGA_FIFO_RD_EMPTY && `VGA_FIFO_RD_EN && !VgaTestEn)\n ^~\n%Error: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:128: Define or directive not defined: \'`VGA_FIFO_RD_EN\'\n if (`VGA_FIFO_RD_EMPTY && `VGA_FIFO_RD_EN && !VgaTestEn)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/vga_controller/tb/tb_top.v:133: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 7 error(s), 2 warning(s)\n' | 302,330 | module | module TB_TOP ();
`include "tb_defines.v"
parameter CLK_VGA_HALF_PERIOD = 20;
parameter CLK_WB_HALF_PERIOD = 6;
parameter X_MSB = 9;
parameter Y_MSB = 8;
parameter R_HI = 7;
parameter R_LO = 5;
parameter G_HI = 4;
parameter G_LO = 2;
parameter B_HI = 1;
parameter B_LO = 0;
reg ClkVga ;
reg RstVga ;
reg ClkWb ;
reg RstWb ;
reg EnVga;
wire WbCyc ;
wire WbStb ;
wire [31:0] WbAdr ;
wire [ 3:0] WbSel ;
wire WbWe ;
wire WbStall ;
wire WbAck ;
wire [31:0] WbDatWr ;
wire [31:0] WbDatRd ;
wire VgaVs ;
wire VgaHs ;
wire [2:0] VgaRed ;
wire [2:0] VgaGreen ;
wire [1:0] VgaBlue ;
wire [7:0] VgaRed8b ;
wire [7:0] VgaGreen8b ;
wire [7:0] VgaBlue8b ;
wire VgaTestEn = 1'b0;
reg CfgDither ;
reg CfgLinearFb ;
reg [1:0] CfgPixelFmt ;
reg [ 31:20] CfgBaseAddr ;
reg [X_MSB: 0] CfgTopLeftX ;
reg [Y_MSB: 0] CfgTopLeftY ;
reg [X_MSB: 0] CfgStartX ;
reg [X_MSB: 0] CfgEndX ;
reg [Y_MSB: 0] CfgStartY ;
reg [Y_MSB: 0] CfgEndY ;
assign VgaRed8b = VgaRed * 36;
assign VgaGreen8b = VgaGreen * 36;
assign VgaBlue8b = VgaBlue * 85;
initial
begin
CfgDither = 1'b0 ;
CfgLinearFb = 1'b1 ;
CfgPixelFmt = 2'b11 ;
CfgBaseAddr = 12'd0 ;
CfgTopLeftX = {X_MSB+1{1'b0}} ;
CfgTopLeftY = {Y_MSB+1{1'b0}} ;
CfgStartX = {X_MSB+1{1'b0}} ;
CfgEndX = 960 ;
CfgStartY = {Y_MSB+1{1'b0}} ;
CfgEndY = 480 ;
end
initial
begin
ClkVga = 1'b0;
RstVga = 1'b1;
@(posedge ClkVga);
@(posedge ClkVga);
@(posedge ClkVga);
@(posedge ClkVga);
RstVga = 1'b0;
end
always #CLK_VGA_HALF_PERIOD ClkVga = !ClkVga;
initial
begin
ClkWb = 1'b0;
RstWb = 1'b1;
@(posedge ClkWb);
@(posedge ClkWb);
@(posedge ClkWb);
@(posedge ClkWb);
RstWb = 1'b0;
end
always #CLK_WB_HALF_PERIOD ClkWb = !ClkWb;
always @(posedge ClkVga)
begin : VGA_FIFO_MONITOR
if (`VGA_FIFO_RD_EMPTY && `VGA_FIFO_RD_EN && !VgaTestEn)
begin
$display("[ERROR] VGA Fifo underrun at time %t !", $time);
$finish();
end
end
TESTCASE testcase();
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000 ),
.MEM_SIZE_P2 (20),
.MAX_LATENCY (1),
.ADDR_LIMIT (1)
)
wb_slave_bfm
(
.CLK (ClkWb ),
.RST_SYNC (RstWb ),
.WB_ADR_IN (WbAdr ),
.WB_CYC_IN (WbCyc ),
.WB_STB_IN (WbStb ),
.WB_SEL_IN (WbSel ),
.WB_WE_IN (WbWe ),
.WB_CTI_IN ( ),
.WB_BTE_IN ( ),
.WB_STALL_OUT (WbStall ),
.WB_ACK_OUT (WbAck ),
.WB_ERR_OUT ( ),
.WB_DAT_RD_OUT (WbDatRd ),
.WB_DAT_WR_IN (WbDatWr )
);
VGA_TOP
#(.X_MSB (X_MSB ),
.Y_MSB (Y_MSB ),
.R_HI (R_HI ),
.R_LO (R_LO ),
.G_HI (G_HI ),
.G_LO (G_LO ),
.B_HI (B_HI ),
.B_LO (B_LO )
)
vga_top
(
.CLK_VGA (ClkVga ),
.EN_VGA (~RstVga ),
.RST_SYNC_VGA (RstVga ),
.RST_ASYNC_VGA (RstVga ),
.CLK_WB (ClkWb ),
.EN_WB (~RstWb ),
.RST_SYNC_WB (RstWb ),
.RST_ASYNC_WB (RstWb ),
.VGA_TEST_EN_IN (VgaTestEn ),
.WB_ADR_OUT (WbAdr ),
.WB_CYC_OUT (WbCyc ),
.WB_STB_OUT (WbStb ),
.WB_WE_OUT (WbWe ),
.WB_SEL_OUT (WbSel ),
.WB_CTI_OUT ( ),
.WB_BTE_OUT ( ),
.WB_STALL_IN (WbStall ),
.WB_ACK_IN (WbAck ),
.WB_ERR_IN (1'b0 ),
.WB_DAT_RD_IN (WbDatRd ),
.WB_DAT_WR_OUT (WbDatWr ),
.VGA_VS_OUT (VgaVs ),
.VGA_HS_OUT (VgaHs ),
.VGA_RED_OUT (VgaRed ),
.VGA_GREEN_OUT (VgaGreen ),
.VGA_BLUE_OUT (VgaBlue ),
.WB_RCNT_ACTIVE_ROW_OUT (),
.WB_RCNT_ACTIVE_COL_OUT (),
.CFG_DITHER_IN (CfgDither ),
.CFG_LINEAR_FB_IN (CfgLinearFb ),
.CFG_PIXEL_FMT_IN (CfgPixelFmt ),
.CFG_BASE_ADDR_IN (CfgBaseAddr ),
.CFG_TOP_LEFT_X_IN (CfgTopLeftX ),
.CFG_TOP_LEFT_Y_IN (CfgTopLeftY ),
.CFG_START_X_IN (CfgStartX ),
.CFG_END_X_IN (CfgEndX ),
.CFG_START_Y_IN (CfgStartY ),
.CFG_END_Y_IN (CfgEndY )
);
VGA_SLAVE_MONITOR
#(
.STORE_IMAGES ( 1),
.PCLK_PERIOD_NS ( 40),
.HORIZ_SYNC ( 96),
.HORIZ_BACK_PORCH ( 48),
.HORIZ_ACTIVE_WIDTH (640),
.HORIZ_FRONT_PORCH ( 16),
.VERT_SYNC ( 2),
.VERT_BACK_PORCH ( 33),
.VERT_ACTIVE_HEIGHT (480),
.VERT_FRONT_PORCH ( 10),
.R_HI (23),
.R_LO (16),
.G_HI (15),
.G_LO ( 8),
.B_HI ( 7),
.B_LO ( 0),
.COLOUR_DEPTH ( 8)
)
vga_slave_monitor
(
.PCLK (ClkVga ),
.VSYNC_IN (VgaVs ),
.HSYNC_IN (VgaHs ),
.RED_IN (VgaRed8b ),
.GREEN_IN (VgaGreen8b ),
.BLUE_IN (VgaBlue8b )
);
endmodule | module TB_TOP (); |
`include "tb_defines.v"
parameter CLK_VGA_HALF_PERIOD = 20;
parameter CLK_WB_HALF_PERIOD = 6;
parameter X_MSB = 9;
parameter Y_MSB = 8;
parameter R_HI = 7;
parameter R_LO = 5;
parameter G_HI = 4;
parameter G_LO = 2;
parameter B_HI = 1;
parameter B_LO = 0;
reg ClkVga ;
reg RstVga ;
reg ClkWb ;
reg RstWb ;
reg EnVga;
wire WbCyc ;
wire WbStb ;
wire [31:0] WbAdr ;
wire [ 3:0] WbSel ;
wire WbWe ;
wire WbStall ;
wire WbAck ;
wire [31:0] WbDatWr ;
wire [31:0] WbDatRd ;
wire VgaVs ;
wire VgaHs ;
wire [2:0] VgaRed ;
wire [2:0] VgaGreen ;
wire [1:0] VgaBlue ;
wire [7:0] VgaRed8b ;
wire [7:0] VgaGreen8b ;
wire [7:0] VgaBlue8b ;
wire VgaTestEn = 1'b0;
reg CfgDither ;
reg CfgLinearFb ;
reg [1:0] CfgPixelFmt ;
reg [ 31:20] CfgBaseAddr ;
reg [X_MSB: 0] CfgTopLeftX ;
reg [Y_MSB: 0] CfgTopLeftY ;
reg [X_MSB: 0] CfgStartX ;
reg [X_MSB: 0] CfgEndX ;
reg [Y_MSB: 0] CfgStartY ;
reg [Y_MSB: 0] CfgEndY ;
assign VgaRed8b = VgaRed * 36;
assign VgaGreen8b = VgaGreen * 36;
assign VgaBlue8b = VgaBlue * 85;
initial
begin
CfgDither = 1'b0 ;
CfgLinearFb = 1'b1 ;
CfgPixelFmt = 2'b11 ;
CfgBaseAddr = 12'd0 ;
CfgTopLeftX = {X_MSB+1{1'b0}} ;
CfgTopLeftY = {Y_MSB+1{1'b0}} ;
CfgStartX = {X_MSB+1{1'b0}} ;
CfgEndX = 960 ;
CfgStartY = {Y_MSB+1{1'b0}} ;
CfgEndY = 480 ;
end
initial
begin
ClkVga = 1'b0;
RstVga = 1'b1;
@(posedge ClkVga);
@(posedge ClkVga);
@(posedge ClkVga);
@(posedge ClkVga);
RstVga = 1'b0;
end
always #CLK_VGA_HALF_PERIOD ClkVga = !ClkVga;
initial
begin
ClkWb = 1'b0;
RstWb = 1'b1;
@(posedge ClkWb);
@(posedge ClkWb);
@(posedge ClkWb);
@(posedge ClkWb);
RstWb = 1'b0;
end
always #CLK_WB_HALF_PERIOD ClkWb = !ClkWb;
always @(posedge ClkVga)
begin : VGA_FIFO_MONITOR
if (`VGA_FIFO_RD_EMPTY && `VGA_FIFO_RD_EN && !VgaTestEn)
begin
$display("[ERROR] VGA Fifo underrun at time %t !", $time);
$finish();
end
end
TESTCASE testcase();
WB_SLAVE_BFM
#(.VERBOSE (0),
.READ_ONLY (0),
.MEM_BASE (32'h0000_0000 ),
.MEM_SIZE_P2 (20),
.MAX_LATENCY (1),
.ADDR_LIMIT (1)
)
wb_slave_bfm
(
.CLK (ClkWb ),
.RST_SYNC (RstWb ),
.WB_ADR_IN (WbAdr ),
.WB_CYC_IN (WbCyc ),
.WB_STB_IN (WbStb ),
.WB_SEL_IN (WbSel ),
.WB_WE_IN (WbWe ),
.WB_CTI_IN ( ),
.WB_BTE_IN ( ),
.WB_STALL_OUT (WbStall ),
.WB_ACK_OUT (WbAck ),
.WB_ERR_OUT ( ),
.WB_DAT_RD_OUT (WbDatRd ),
.WB_DAT_WR_IN (WbDatWr )
);
VGA_TOP
#(.X_MSB (X_MSB ),
.Y_MSB (Y_MSB ),
.R_HI (R_HI ),
.R_LO (R_LO ),
.G_HI (G_HI ),
.G_LO (G_LO ),
.B_HI (B_HI ),
.B_LO (B_LO )
)
vga_top
(
.CLK_VGA (ClkVga ),
.EN_VGA (~RstVga ),
.RST_SYNC_VGA (RstVga ),
.RST_ASYNC_VGA (RstVga ),
.CLK_WB (ClkWb ),
.EN_WB (~RstWb ),
.RST_SYNC_WB (RstWb ),
.RST_ASYNC_WB (RstWb ),
.VGA_TEST_EN_IN (VgaTestEn ),
.WB_ADR_OUT (WbAdr ),
.WB_CYC_OUT (WbCyc ),
.WB_STB_OUT (WbStb ),
.WB_WE_OUT (WbWe ),
.WB_SEL_OUT (WbSel ),
.WB_CTI_OUT ( ),
.WB_BTE_OUT ( ),
.WB_STALL_IN (WbStall ),
.WB_ACK_IN (WbAck ),
.WB_ERR_IN (1'b0 ),
.WB_DAT_RD_IN (WbDatRd ),
.WB_DAT_WR_OUT (WbDatWr ),
.VGA_VS_OUT (VgaVs ),
.VGA_HS_OUT (VgaHs ),
.VGA_RED_OUT (VgaRed ),
.VGA_GREEN_OUT (VgaGreen ),
.VGA_BLUE_OUT (VgaBlue ),
.WB_RCNT_ACTIVE_ROW_OUT (),
.WB_RCNT_ACTIVE_COL_OUT (),
.CFG_DITHER_IN (CfgDither ),
.CFG_LINEAR_FB_IN (CfgLinearFb ),
.CFG_PIXEL_FMT_IN (CfgPixelFmt ),
.CFG_BASE_ADDR_IN (CfgBaseAddr ),
.CFG_TOP_LEFT_X_IN (CfgTopLeftX ),
.CFG_TOP_LEFT_Y_IN (CfgTopLeftY ),
.CFG_START_X_IN (CfgStartX ),
.CFG_END_X_IN (CfgEndX ),
.CFG_START_Y_IN (CfgStartY ),
.CFG_END_Y_IN (CfgEndY )
);
VGA_SLAVE_MONITOR
#(
.STORE_IMAGES ( 1),
.PCLK_PERIOD_NS ( 40),
.HORIZ_SYNC ( 96),
.HORIZ_BACK_PORCH ( 48),
.HORIZ_ACTIVE_WIDTH (640),
.HORIZ_FRONT_PORCH ( 16),
.VERT_SYNC ( 2),
.VERT_BACK_PORCH ( 33),
.VERT_ACTIVE_HEIGHT (480),
.VERT_FRONT_PORCH ( 10),
.R_HI (23),
.R_LO (16),
.G_HI (15),
.G_LO ( 8),
.B_HI ( 7),
.B_LO ( 0),
.COLOUR_DEPTH ( 8)
)
vga_slave_monitor
(
.PCLK (ClkVga ),
.VSYNC_IN (VgaVs ),
.HSYNC_IN (VgaHs ),
.RED_IN (VgaRed8b ),
.GREEN_IN (VgaGreen8b ),
.BLUE_IN (VgaBlue8b )
);
endmodule | 1 |
138,414 | data/full_repos/permissive/83307298/spislv/tb_spi.v | 83,307,298 | tb_spi.v | v | 225 | 115 | [] | [] | [] | null | line:91: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:64: Unsupported: Ignoring delay on this delayed statement.\nalways #(250/2.0) SCK <= ~SCK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:70: Unsupported: Ignoring delay on this delayed statement.\n #(250*1) Reset_n <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:71: Unsupported: Ignoring delay on this delayed statement.\n #(250*10) Reset_n <= 1\'b1;\n ^\n%Error: data/full_repos/permissive/83307298/spislv/tb_spi.v:77: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("SPI_SLAVE.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/83307298/spislv/tb_spi.v:78: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:79: Unsupported: Ignoring delay on this delayed statement.\n #(250*400);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:89: Unsupported: Ignoring delay on this delayed statement.\n #(250*12);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:90: Unsupported: Ignoring delay on this delayed statement.\n #(250/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:94: Unsupported: Ignoring delay on this delayed statement.\n #(250*12);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:105: Unsupported: Ignoring delay on this delayed statement.\n #(250*20);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:131: Unsupported: Ignoring delay on this delayed statement.\n #(250*44);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:147: Unsupported: Ignoring delay on this delayed statement.\n #(250*44);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83307298/spislv/tb_spi.v:176: Unsupported: Ignoring delay on this delayed statement.\n #(250);\n ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,340 | module | module tb_spi;
wire SPI_SOMI;
wire [5:0] ctrlCNT;
reg write_on;
reg Reset_n;
reg SPI_CS;
reg SCK;
reg SPI_SIMO;
reg SPI_CLK;
reg [31:0] received_data;
reg [42:0] shift_wdata;
reg [10:0] shift_rdata;
localparam [2:0] SPI_ID_VALUE = 3'b010;
SPI_SLAVE DUT (
.SID_assign (SPI_ID_VALUE),
.SPI_RST (Reset_n),
.SPI_CS (SPI_CS),
.SPI_CLK (SPI_CLK),
.SPI_MOSI (SPI_SIMO),
.SPI_MISO (SPI_SOMI)
);
initial
begin
SCK = 1'b0;
end
always #(`TCLK/2.0) SCK <= ~SCK;
initial
begin
Reset_n <= 1'b1;
#(`TCLK*1) Reset_n <= 1'b0;
#(`TCLK*10) Reset_n <= 1'b1;
end
initial
begin
$dumpfile("SPI_SLAVE.vcd");
$dumpvars();
#(`TCLK*400);
$finish;
end
initial
begin
SPI_CS = 1'b1;
#(`TCLK*12);
#(`TCLK/2);
write(1'b0, SPI_ID_VALUE, 1'b1, 7'd30, 32'h92345679);
done(1'b1);
#(`TCLK*12);
read(1'b0, 3'b111, 1'b0, 7'd30);
cmp(7'd30,32'h92345679);
done(1'b1);
read(1'b0, SPI_ID_VALUE, 1'b0, 7'd30);
cmp(7'd30,32'h92345679);
done(1'b1);
#(`TCLK*20);
end
always @*
begin
if(SPI_CS == 1'b0)
SPI_CLK <= SCK;
else
SPI_CLK <= 1'b0;
end
task write;
input CS;
input [2:0] SID;
input wrb;
input [6:0] addr;
input [31:0] data;
begin
SPI_CS = CS;
write_on = 1'b1;
shift_wdata = {SID,wrb,addr,data};
$write("WRITE : At[%2d] = 0x%0x\n", addr,data);
#(`TCLK*44);
end
endtask
task read;
input CS;
input [2:0] SID;
input wrb;
input [6:0] addr;
begin
SPI_CS = CS;
write_on = 1'b0;
shift_rdata = {SID,wrb,addr};
#(`TCLK*44);
end
endtask
task cmp;
input [6:0] addr;
input [31:0] expectedData;
begin
if(expectedData != received_data)
begin
$write("****** READ ERROR : At[%2d] = Expected 0x%0x, got 0x%0x\n", addr,expectedData, received_data);
end
else
begin
$write("READ : At[%2d] = 0x%0x\n", addr,received_data);
end
end
endtask
task done;
input CS;
begin
SPI_CS = CS;
#(`TCLK);
end
endtask
always @(posedge SPI_CLK or negedge Reset_n)
begin
if (~Reset_n)
begin
SPI_SIMO <= 1'b0;
shift_wdata <= 43'h0;
shift_rdata <= 11'h000;
end
else if(write_on == 1'b1)
begin
shift_wdata <= shift_wdata << 1'b1;
SPI_SIMO <= shift_wdata[42];
end
else if(write_on == 1'b0)
begin
shift_rdata <= shift_rdata << 1'b1;
SPI_SIMO <= shift_rdata[10];
end
end
always @(negedge SPI_CLK or negedge Reset_n)
begin
if (~Reset_n)
begin
received_data <= 32'h0;
end
else if(write_on == 1'b0 && DUT.ctrl_cnt >= 5'd0 && DUT.ctrl_cnt <= 5'd31)
begin
received_data <= {received_data[30:0],SPI_SOMI};
end
end
endmodule | module tb_spi; |
wire SPI_SOMI;
wire [5:0] ctrlCNT;
reg write_on;
reg Reset_n;
reg SPI_CS;
reg SCK;
reg SPI_SIMO;
reg SPI_CLK;
reg [31:0] received_data;
reg [42:0] shift_wdata;
reg [10:0] shift_rdata;
localparam [2:0] SPI_ID_VALUE = 3'b010;
SPI_SLAVE DUT (
.SID_assign (SPI_ID_VALUE),
.SPI_RST (Reset_n),
.SPI_CS (SPI_CS),
.SPI_CLK (SPI_CLK),
.SPI_MOSI (SPI_SIMO),
.SPI_MISO (SPI_SOMI)
);
initial
begin
SCK = 1'b0;
end
always #(`TCLK/2.0) SCK <= ~SCK;
initial
begin
Reset_n <= 1'b1;
#(`TCLK*1) Reset_n <= 1'b0;
#(`TCLK*10) Reset_n <= 1'b1;
end
initial
begin
$dumpfile("SPI_SLAVE.vcd");
$dumpvars();
#(`TCLK*400);
$finish;
end
initial
begin
SPI_CS = 1'b1;
#(`TCLK*12);
#(`TCLK/2);
write(1'b0, SPI_ID_VALUE, 1'b1, 7'd30, 32'h92345679);
done(1'b1);
#(`TCLK*12);
read(1'b0, 3'b111, 1'b0, 7'd30);
cmp(7'd30,32'h92345679);
done(1'b1);
read(1'b0, SPI_ID_VALUE, 1'b0, 7'd30);
cmp(7'd30,32'h92345679);
done(1'b1);
#(`TCLK*20);
end
always @*
begin
if(SPI_CS == 1'b0)
SPI_CLK <= SCK;
else
SPI_CLK <= 1'b0;
end
task write;
input CS;
input [2:0] SID;
input wrb;
input [6:0] addr;
input [31:0] data;
begin
SPI_CS = CS;
write_on = 1'b1;
shift_wdata = {SID,wrb,addr,data};
$write("WRITE : At[%2d] = 0x%0x\n", addr,data);
#(`TCLK*44);
end
endtask
task read;
input CS;
input [2:0] SID;
input wrb;
input [6:0] addr;
begin
SPI_CS = CS;
write_on = 1'b0;
shift_rdata = {SID,wrb,addr};
#(`TCLK*44);
end
endtask
task cmp;
input [6:0] addr;
input [31:0] expectedData;
begin
if(expectedData != received_data)
begin
$write("****** READ ERROR : At[%2d] = Expected 0x%0x, got 0x%0x\n", addr,expectedData, received_data);
end
else
begin
$write("READ : At[%2d] = 0x%0x\n", addr,received_data);
end
end
endtask
task done;
input CS;
begin
SPI_CS = CS;
#(`TCLK);
end
endtask
always @(posedge SPI_CLK or negedge Reset_n)
begin
if (~Reset_n)
begin
SPI_SIMO <= 1'b0;
shift_wdata <= 43'h0;
shift_rdata <= 11'h000;
end
else if(write_on == 1'b1)
begin
shift_wdata <= shift_wdata << 1'b1;
SPI_SIMO <= shift_wdata[42];
end
else if(write_on == 1'b0)
begin
shift_rdata <= shift_rdata << 1'b1;
SPI_SIMO <= shift_rdata[10];
end
end
always @(negedge SPI_CLK or negedge Reset_n)
begin
if (~Reset_n)
begin
received_data <= 32'h0;
end
else if(write_on == 1'b0 && DUT.ctrl_cnt >= 5'd0 && DUT.ctrl_cnt <= 5'd31)
begin
received_data <= {received_data[30:0],SPI_SOMI};
end
end
endmodule | 4 |
138,415 | data/full_repos/permissive/83311855/src/beepDri.v | 83,311,855 | beepDri.v | v | 387 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd2 in position 801: invalid continuation byte | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:74: Signal definition not found, creating implicitly: \'CLK_5M\'\n : ... Suggested alternative: \'CLK_50M\'\nalways @(posedge CLK_5M)\n ^~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:91: Signal definition not found, creating implicitly: \'CLK_1\'\n : ... Suggested alternative: \'CLK_5M\'\nalways @(posedge CLK_1)\n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:152: Signal definition not found, creating implicitly: \'CLK_500\'\n : ... Suggested alternative: \'CLK_50M\'\nalways @(posedge CLK_500)\n ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:163: Signal definition not found, creating implicitly: \'syms1\'\n assign dig = syms1; \n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:169: Signal definition not found, creating implicitly: \'syms2\'\n : ... Suggested alternative: \'syms1\'\n dig = syms2; \n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:175: Signal definition not found, creating implicitly: \'syms3\'\n : ... Suggested alternative: \'syms1\'\n dig = syms3; \n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:181: Signal definition not found, creating implicitly: \'syms4\'\n : ... Suggested alternative: \'syms1\'\n dig = syms4; \n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/83311855/src/beepDri.v:224: Signal definition not found, creating implicitly: \'CLK_5\'\n : ... Suggested alternative: \'CLK_1\'\nalways @(posedge CLK_5)\n ^~~~~\n%Error: data/full_repos/permissive/83311855/src/beepDri.v:32: Cannot find file containing module: \'freDiv\'\nfreDiv A1(.CLK_50M(CLK_50M),\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/83311855/src,data/full_repos/permissive/83311855/freDiv\n data/full_repos/permissive/83311855/src,data/full_repos/permissive/83311855/freDiv.v\n data/full_repos/permissive/83311855/src,data/full_repos/permissive/83311855/freDiv.sv\n freDiv\n freDiv.v\n freDiv.sv\n obj_dir/freDiv\n obj_dir/freDiv.v\n obj_dir/freDiv.sv\n%Error: data/full_repos/permissive/83311855/src/beepDri.v:86: Cannot find file containing module: \'seg_sym_sub\'\nseg_sym_sub d1(.CLK_50M(CLK_50M),.state(state1),.s_to_d(syms1));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/83311855/src/beepDri.v:87: Cannot find file containing module: \'seg_sym_sub\'\nseg_sym_sub d2(.CLK_50M(CLK_50M),.state(state2),.s_to_d(syms2));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/83311855/src/beepDri.v:88: Cannot find file containing module: \'seg_sym_sub\'\nseg_sym_sub d3(.CLK_50M(CLK_50M),.state(state3),.s_to_d(syms3));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/83311855/src/beepDri.v:89: Cannot find file containing module: \'seg_sym_sub\'\nseg_sym_sub d4(.CLK_50M(CLK_50M),.state(state4),.s_to_d(syms4));\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/83311855/src/beepDri.v:163: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'syms1\' generates 1 bits.\n : ... In instance beepDri\n assign dig = syms1; \n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/83311855/src/beepDri.v:169: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'syms2\' generates 1 bits.\n : ... In instance beepDri\n dig = syms2; \n ^\n%Warning-WIDTH: data/full_repos/permissive/83311855/src/beepDri.v:175: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'syms3\' generates 1 bits.\n : ... In instance beepDri\n dig = syms3; \n ^\n%Warning-WIDTH: data/full_repos/permissive/83311855/src/beepDri.v:181: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'syms4\' generates 1 bits.\n : ... In instance beepDri\n dig = syms4; \n ^\n%Warning-WIDTH: data/full_repos/permissive/83311855/src/beepDri.v:216: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'count\' generates 2 bits.\n : ... In instance beepDri\n if(count==4\'d0)\n ^~\n%Error: Exiting due to 5 error(s), 13 warning(s)\n' | 302,341 | module | module beepDri(
input CLK_50M,
input pau_flag,
input on_off,
output reg speaker,
output reg [3:0] lit,
output reg [6:0] dig
);
freDiv A1(.CLK_50M(CLK_50M),
.CLK_5M(CLK_5M),
.CLK_500(CLK_500),
.CLK_50(CLK_50),
.CLK_5(CLK_5),
.CLK_1(CLK_1),
.CLK_05(CLK_05)
);
parameter wide=15;
reg[7:0] cnt;
reg[wide-1:0] origin;
reg[wide-1:0] drive;
reg[1:0] count;
reg carrier;
reg digit1;
reg digit2;
reg digit3;
reg digit4;
reg [2:0]state1;
reg [2:0]state2;
reg [2:0]state3;
reg [2:0]state4;
reg [3:0]count_dig;
reg dig_sym_flag1;
reg dig_sym_flag2;
reg dig_sym_flag3;
reg dig_sym_flag4;
initial
begin
state1<=3'b000;
state2<=3'b000;
state3<=3'b000;
state4<=3'b000;
lit <= 4'b1111;
dig <= 7'b1111111;
end
always @(posedge CLK_5M)
begin
digit1 <=1;
digit2 <=1;
digit3 <=1;
digit4 <=1;
dig_sym_flag1 <=1;
dig_sym_flag2 <=1;
dig_sym_flag3 <=1;
dig_sym_flag4 <=1;
end
seg_sym_sub d1(.CLK_50M(CLK_50M),.state(state1),.s_to_d(syms1));
seg_sym_sub d2(.CLK_50M(CLK_50M),.state(state2),.s_to_d(syms2));
seg_sym_sub d3(.CLK_50M(CLK_50M),.state(state3),.s_to_d(syms3));
seg_sym_sub d4(.CLK_50M(CLK_50M),.state(state4),.s_to_d(syms4));
always @(posedge CLK_1)
begin
if(dig_sym_flag1 ==1) begin
if (state1 == 3'b111) begin
state1 = 3'b000;
end
else
state1 = state1 + 3'b001;
end
if(dig_sym_flag2 ==1) begin
if (state2 == 3'b111) begin
state2 = 3'b000;
end
else
state2 = state2 + 3'b001;
end
if(dig_sym_flag3 ==1) begin
if (state3 == 3'b111) begin
state3 = 3'b000;
end
else
state3 = state3 + 3'b001;
end
if(dig_sym_flag4 ==1) begin
if (state4 == 3'b111) begin
state4 = 3'b000;
end
else
state4 = state4 + 3'b001;
end
end
always @(posedge CLK_500)
begin
if(on_off) begin
if (count_dig == 4'b1111)
count_dig = 4'b0000;
else
count_dig = count_dig + 4'b0001;
if (count_dig % 4 == 0) begin
if (digit1 == 1) begin
lit = 4'b0111;
assign dig = syms1;
end
end
else if (count_dig % 4 == 1)begin
if (digit2 == 1)begin
lit = 4'b1011;
dig = syms2;
end
end
else if (count_dig % 4 == 2)begin
if (digit3 == 1)begin
lit = 4'b1101;
dig = syms3;
end
end
else begin
if (digit4 == 1)begin
lit = 4'b1110;
dig = syms4;
end
end
end
else
lit=4'b1111;
end
always @(posedge CLK_5M)
begin
if (!pau_flag)
if (on_off)
begin
if(drive==15'h7fff)
begin
drive<=origin;
carrier<=1'b1;
end
else
begin
drive<=drive+1'b1;
carrier<=1'b0;
end
end
end
always @(posedge carrier)
begin
if (!pau_flag)
if (on_off)
begin
count<=count+1'b1;
if(count==4'd0)
speaker<=1'b1;
else
speaker<=1'b0;
end
end
always @(posedge CLK_5)
begin
if (!pau_flag)
if (on_off)
begin
if(cnt==8'd139)
cnt<=8'd0;
else
cnt<=cnt+1'b1;
case (cnt)
8'd0:origin<=15'h625F;
8'd1:origin<=15'h625F;
8'd2:origin<=15'h625F;
8'd3:origin<=15'h625F;
8'd4:origin<=15'h6715;
8'd5:origin<=15'h6715;
8'd6:origin<=15'h6715;
8'd7:origin<=15'h69cd;
8'd8:origin<=15'h6d55;
8'd9:origin<=15'h6d55;
8'd10:origin<=15'h6d55;
8'd11:origin<=15'h6f5f;
8'd12:origin<=15'h69cd;
8'd13:origin<=15'h6d55;
8'd14:origin<=15'h6715;
8'd15:origin<=15'h6715;
8'd16:origin<=15'h738a;
8'd17:origin<=15'h738a;
8'd18:origin<=15'h738a;
8'd19:origin<=15'h76aa;
8'd20:origin<=15'h69cd;
8'd21:origin<=15'h6715;
8'd22:origin<=15'h712f;
8'd23:origin<=15'h6715;
8'd24:origin<=15'h6f5f;
8'd25:origin<=15'h6f5f;
8'd26:origin<=15'h6f5f;
8'd27:origin<=15'h6f5f;
8'd28:origin<=15'h6f5f;
8'd29:origin<=15'h6f5f;
8'd30:origin<=15'h6f5f;
8'd31:origin<=15'h6f5f;
8'd32:origin<=15'h6f5f;
8'd33:origin<=15'h6f5f;
8'd34:origin<=15'h6f5f;
8'd35:origin<=15'h712f;
8'd36:origin<=15'h6c39;
8'd37:origin<=15'h6c39;
8'd38:origin<=15'h69cd;
8'd39:origin<=15'h69cd;
8'd40:origin<=15'h6715;
8'd41:origin<=15'h6715;
8'd42:origin<=15'h6715;
8'd43:origin<=15'h69cd;
8'd44:origin<=15'h6d55;
8'd45:origin<=15'h6d55;
8'd46:origin<=15'h6f5f;
8'd47:origin<=15'h6f5f;
8'd48:origin<=15'h625f;
8'd49:origin<=15'h625f;
8'd50:origin<=15'h6d55;
8'd51:origin<=15'h6d55;
8'd52:origin<=15'h69cd;
8'd53:origin<=15'h6715;
8'd54:origin<=15'h69cd;
8'd55:origin<=15'h6d55;
8'd56:origin<=15'h6715;
8'd57:origin<=15'h6715;
8'd58:origin<=15'h6715;
8'd59:origin<=15'h6715;
8'd60:origin<=15'h6715;
8'd61:origin<=15'h6715;
8'd62:origin<=15'h6715;
8'd63:origin<=15'h6715;
8'd64:origin<=15'h712f;
8'd65:origin<=15'h712f;
8'd66:origin<=15'h712f;
8'd67:origin<=15'h738a;
8'd68:origin<=15'h6c39;
8'd69:origin<=15'h6c39;
8'd70:origin<=15'h6f5f;
8'd71:origin<=15'h6f5f;
8'd72:origin<=15'h69cd;
8'd73:origin<=15'h6d55;
8'd74:origin<=15'h6715;
8'd75:origin<=15'h6715;
8'd76:origin<=15'h6715;
8'd77:origin<=15'h6715;
8'd78:origin<=15'h6715;
8'd79:origin<=15'h6715;
8'd80:origin<=15'h625f;
8'd81:origin<=15'h6715;
8'd82:origin<=15'h625f;
8'd83:origin<=15'h625f;
8'd84:origin<=15'h6715;
8'd85:origin<=15'h69cd;
8'd86:origin<=15'h6c39;
8'd87:origin<=15'h6f5f;
8'd88:origin<=15'h69cd;
8'd89:origin<=15'h69cd;
8'd90:origin<=15'h69cd;
8'd91:origin<=15'h69cd;
8'd92:origin<=15'h69cd;
8'd93:origin<=15'h69cd;
8'd94:origin<=15'h6715;
8'd95:origin<=15'h69cd;
8'd96:origin<=15'h6d55;
8'd97:origin<=15'h6d55;
8'd98:origin<=15'h6d55;
8'd99:origin<=15'h6f5f;
8'd100:origin<=15'h738a;
8'd101:origin<=15'h738a;
8'd102:origin<=15'h738a;
8'd103:origin<=15'h712f;
8'd104:origin<=15'h6f5f;
8'd105:origin<=15'h6f5f;
8'd106:origin<=15'h712f;
8'd107:origin<=15'h6f5f;
8'd108:origin<=15'h6d55;
8'd109:origin<=15'h6d55;
8'd110:origin<=15'h69cd;
8'd111:origin<=15'h6715;
8'd112:origin<=15'h625f;
8'd113:origin<=15'h625f;
8'd114:origin<=15'h625f;
8'd115:origin<=15'h625f;
8'd116:origin<=15'h6d55;
8'd117:origin<=15'h6d55;
8'd118:origin<=15'h69cd;
8'd119:origin<=15'h6d55;
8'd120:origin<=15'h69cd;
8'd121:origin<=15'h625f;
8'd122:origin<=15'h625f;
8'd123:origin<=15'h6f5f;
8'd124:origin<=15'h625f;
8'd125:origin<=15'h6715;
8'd126:origin<=15'h69cd;
8'd127:origin<=15'h6d55;
8'd128:origin<=15'h6715;
8'd129:origin<=15'h6715;
8'd130:origin<=15'h6715;
8'd131:origin<=15'h6715;
8'd132:origin<=15'h6715;
8'd133:origin<=15'h6715;
8'd134:origin<=15'h6715;
8'd135:origin<=15'h6715;
8'd136:origin<=15'h3fff;
8'd137:origin<=15'h3fff;
8'd138:origin<=15'h3fff;
8'd139:origin<=15'h3fff;
default:origin<=15'h3fff;
endcase
end
else
begin
cnt<=8'd0;
end
end
endmodule | module beepDri(
input CLK_50M,
input pau_flag,
input on_off,
output reg speaker,
output reg [3:0] lit,
output reg [6:0] dig
); |
freDiv A1(.CLK_50M(CLK_50M),
.CLK_5M(CLK_5M),
.CLK_500(CLK_500),
.CLK_50(CLK_50),
.CLK_5(CLK_5),
.CLK_1(CLK_1),
.CLK_05(CLK_05)
);
parameter wide=15;
reg[7:0] cnt;
reg[wide-1:0] origin;
reg[wide-1:0] drive;
reg[1:0] count;
reg carrier;
reg digit1;
reg digit2;
reg digit3;
reg digit4;
reg [2:0]state1;
reg [2:0]state2;
reg [2:0]state3;
reg [2:0]state4;
reg [3:0]count_dig;
reg dig_sym_flag1;
reg dig_sym_flag2;
reg dig_sym_flag3;
reg dig_sym_flag4;
initial
begin
state1<=3'b000;
state2<=3'b000;
state3<=3'b000;
state4<=3'b000;
lit <= 4'b1111;
dig <= 7'b1111111;
end
always @(posedge CLK_5M)
begin
digit1 <=1;
digit2 <=1;
digit3 <=1;
digit4 <=1;
dig_sym_flag1 <=1;
dig_sym_flag2 <=1;
dig_sym_flag3 <=1;
dig_sym_flag4 <=1;
end
seg_sym_sub d1(.CLK_50M(CLK_50M),.state(state1),.s_to_d(syms1));
seg_sym_sub d2(.CLK_50M(CLK_50M),.state(state2),.s_to_d(syms2));
seg_sym_sub d3(.CLK_50M(CLK_50M),.state(state3),.s_to_d(syms3));
seg_sym_sub d4(.CLK_50M(CLK_50M),.state(state4),.s_to_d(syms4));
always @(posedge CLK_1)
begin
if(dig_sym_flag1 ==1) begin
if (state1 == 3'b111) begin
state1 = 3'b000;
end
else
state1 = state1 + 3'b001;
end
if(dig_sym_flag2 ==1) begin
if (state2 == 3'b111) begin
state2 = 3'b000;
end
else
state2 = state2 + 3'b001;
end
if(dig_sym_flag3 ==1) begin
if (state3 == 3'b111) begin
state3 = 3'b000;
end
else
state3 = state3 + 3'b001;
end
if(dig_sym_flag4 ==1) begin
if (state4 == 3'b111) begin
state4 = 3'b000;
end
else
state4 = state4 + 3'b001;
end
end
always @(posedge CLK_500)
begin
if(on_off) begin
if (count_dig == 4'b1111)
count_dig = 4'b0000;
else
count_dig = count_dig + 4'b0001;
if (count_dig % 4 == 0) begin
if (digit1 == 1) begin
lit = 4'b0111;
assign dig = syms1;
end
end
else if (count_dig % 4 == 1)begin
if (digit2 == 1)begin
lit = 4'b1011;
dig = syms2;
end
end
else if (count_dig % 4 == 2)begin
if (digit3 == 1)begin
lit = 4'b1101;
dig = syms3;
end
end
else begin
if (digit4 == 1)begin
lit = 4'b1110;
dig = syms4;
end
end
end
else
lit=4'b1111;
end
always @(posedge CLK_5M)
begin
if (!pau_flag)
if (on_off)
begin
if(drive==15'h7fff)
begin
drive<=origin;
carrier<=1'b1;
end
else
begin
drive<=drive+1'b1;
carrier<=1'b0;
end
end
end
always @(posedge carrier)
begin
if (!pau_flag)
if (on_off)
begin
count<=count+1'b1;
if(count==4'd0)
speaker<=1'b1;
else
speaker<=1'b0;
end
end
always @(posedge CLK_5)
begin
if (!pau_flag)
if (on_off)
begin
if(cnt==8'd139)
cnt<=8'd0;
else
cnt<=cnt+1'b1;
case (cnt)
8'd0:origin<=15'h625F;
8'd1:origin<=15'h625F;
8'd2:origin<=15'h625F;
8'd3:origin<=15'h625F;
8'd4:origin<=15'h6715;
8'd5:origin<=15'h6715;
8'd6:origin<=15'h6715;
8'd7:origin<=15'h69cd;
8'd8:origin<=15'h6d55;
8'd9:origin<=15'h6d55;
8'd10:origin<=15'h6d55;
8'd11:origin<=15'h6f5f;
8'd12:origin<=15'h69cd;
8'd13:origin<=15'h6d55;
8'd14:origin<=15'h6715;
8'd15:origin<=15'h6715;
8'd16:origin<=15'h738a;
8'd17:origin<=15'h738a;
8'd18:origin<=15'h738a;
8'd19:origin<=15'h76aa;
8'd20:origin<=15'h69cd;
8'd21:origin<=15'h6715;
8'd22:origin<=15'h712f;
8'd23:origin<=15'h6715;
8'd24:origin<=15'h6f5f;
8'd25:origin<=15'h6f5f;
8'd26:origin<=15'h6f5f;
8'd27:origin<=15'h6f5f;
8'd28:origin<=15'h6f5f;
8'd29:origin<=15'h6f5f;
8'd30:origin<=15'h6f5f;
8'd31:origin<=15'h6f5f;
8'd32:origin<=15'h6f5f;
8'd33:origin<=15'h6f5f;
8'd34:origin<=15'h6f5f;
8'd35:origin<=15'h712f;
8'd36:origin<=15'h6c39;
8'd37:origin<=15'h6c39;
8'd38:origin<=15'h69cd;
8'd39:origin<=15'h69cd;
8'd40:origin<=15'h6715;
8'd41:origin<=15'h6715;
8'd42:origin<=15'h6715;
8'd43:origin<=15'h69cd;
8'd44:origin<=15'h6d55;
8'd45:origin<=15'h6d55;
8'd46:origin<=15'h6f5f;
8'd47:origin<=15'h6f5f;
8'd48:origin<=15'h625f;
8'd49:origin<=15'h625f;
8'd50:origin<=15'h6d55;
8'd51:origin<=15'h6d55;
8'd52:origin<=15'h69cd;
8'd53:origin<=15'h6715;
8'd54:origin<=15'h69cd;
8'd55:origin<=15'h6d55;
8'd56:origin<=15'h6715;
8'd57:origin<=15'h6715;
8'd58:origin<=15'h6715;
8'd59:origin<=15'h6715;
8'd60:origin<=15'h6715;
8'd61:origin<=15'h6715;
8'd62:origin<=15'h6715;
8'd63:origin<=15'h6715;
8'd64:origin<=15'h712f;
8'd65:origin<=15'h712f;
8'd66:origin<=15'h712f;
8'd67:origin<=15'h738a;
8'd68:origin<=15'h6c39;
8'd69:origin<=15'h6c39;
8'd70:origin<=15'h6f5f;
8'd71:origin<=15'h6f5f;
8'd72:origin<=15'h69cd;
8'd73:origin<=15'h6d55;
8'd74:origin<=15'h6715;
8'd75:origin<=15'h6715;
8'd76:origin<=15'h6715;
8'd77:origin<=15'h6715;
8'd78:origin<=15'h6715;
8'd79:origin<=15'h6715;
8'd80:origin<=15'h625f;
8'd81:origin<=15'h6715;
8'd82:origin<=15'h625f;
8'd83:origin<=15'h625f;
8'd84:origin<=15'h6715;
8'd85:origin<=15'h69cd;
8'd86:origin<=15'h6c39;
8'd87:origin<=15'h6f5f;
8'd88:origin<=15'h69cd;
8'd89:origin<=15'h69cd;
8'd90:origin<=15'h69cd;
8'd91:origin<=15'h69cd;
8'd92:origin<=15'h69cd;
8'd93:origin<=15'h69cd;
8'd94:origin<=15'h6715;
8'd95:origin<=15'h69cd;
8'd96:origin<=15'h6d55;
8'd97:origin<=15'h6d55;
8'd98:origin<=15'h6d55;
8'd99:origin<=15'h6f5f;
8'd100:origin<=15'h738a;
8'd101:origin<=15'h738a;
8'd102:origin<=15'h738a;
8'd103:origin<=15'h712f;
8'd104:origin<=15'h6f5f;
8'd105:origin<=15'h6f5f;
8'd106:origin<=15'h712f;
8'd107:origin<=15'h6f5f;
8'd108:origin<=15'h6d55;
8'd109:origin<=15'h6d55;
8'd110:origin<=15'h69cd;
8'd111:origin<=15'h6715;
8'd112:origin<=15'h625f;
8'd113:origin<=15'h625f;
8'd114:origin<=15'h625f;
8'd115:origin<=15'h625f;
8'd116:origin<=15'h6d55;
8'd117:origin<=15'h6d55;
8'd118:origin<=15'h69cd;
8'd119:origin<=15'h6d55;
8'd120:origin<=15'h69cd;
8'd121:origin<=15'h625f;
8'd122:origin<=15'h625f;
8'd123:origin<=15'h6f5f;
8'd124:origin<=15'h625f;
8'd125:origin<=15'h6715;
8'd126:origin<=15'h69cd;
8'd127:origin<=15'h6d55;
8'd128:origin<=15'h6715;
8'd129:origin<=15'h6715;
8'd130:origin<=15'h6715;
8'd131:origin<=15'h6715;
8'd132:origin<=15'h6715;
8'd133:origin<=15'h6715;
8'd134:origin<=15'h6715;
8'd135:origin<=15'h6715;
8'd136:origin<=15'h3fff;
8'd137:origin<=15'h3fff;
8'd138:origin<=15'h3fff;
8'd139:origin<=15'h3fff;
default:origin<=15'h3fff;
endcase
end
else
begin
cnt<=8'd0;
end
end
endmodule | 0 |
138,416 | data/full_repos/permissive/83311855/src/freDiv.v | 83,311,855 | freDiv.v | v | 79 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc2 in position 646: invalid continuation byte | data/verilator_xmls/98d8922b-3e30-45bd-b1ca-41d39c90edde.xml | null | 302,342 | module | module freDiv(
input CLK_50M,
output reg CLK_5M,
output reg CLK_500,
output reg CLK_50,
output reg CLK_5,
output reg CLK_1,
output reg CLK_05
);
reg[3:0] cnt1;
reg[16:0] cnt2;
reg[19:0] cnt3;
reg[23:0] cnt4;
reg[25:0] cnt5;
reg[27:0] cnt6;
always @(posedge CLK_50M)
begin
cnt1<=cnt1+1'b1;
cnt2<=cnt2+1'b1;
cnt3<=cnt3+1'b1;
cnt4<=cnt4+1'b1;
cnt5<=cnt5+1'b1;
cnt6<=cnt6+1'b1;
if(cnt1==4'd9)
begin
cnt1<=4'd0;
CLK_5M <= ~CLK_5M;
end
if(cnt2==17'h1869F)
begin
cnt2<=17'h0;
CLK_500 <= ~CLK_500;
end
if(cnt3==20'hF423F)
begin
cnt3<=20'h0;
CLK_50 <= ~CLK_50;
end
if(cnt4==24'h98967F)
begin
cnt4<=24'h0;
CLK_5 <= ~CLK_5;
end
if(cnt5==26'h2FAF07F)
begin
cnt5<=26'h0;
CLK_1 <= ~CLK_1;
end
if(cnt6==28'h5F5E0FF)
begin
cnt6<=28'h0;
CLK_05 <= ~CLK_05;
end
end
endmodule | module freDiv(
input CLK_50M,
output reg CLK_5M,
output reg CLK_500,
output reg CLK_50,
output reg CLK_5,
output reg CLK_1,
output reg CLK_05
); |
reg[3:0] cnt1;
reg[16:0] cnt2;
reg[19:0] cnt3;
reg[23:0] cnt4;
reg[25:0] cnt5;
reg[27:0] cnt6;
always @(posedge CLK_50M)
begin
cnt1<=cnt1+1'b1;
cnt2<=cnt2+1'b1;
cnt3<=cnt3+1'b1;
cnt4<=cnt4+1'b1;
cnt5<=cnt5+1'b1;
cnt6<=cnt6+1'b1;
if(cnt1==4'd9)
begin
cnt1<=4'd0;
CLK_5M <= ~CLK_5M;
end
if(cnt2==17'h1869F)
begin
cnt2<=17'h0;
CLK_500 <= ~CLK_500;
end
if(cnt3==20'hF423F)
begin
cnt3<=20'h0;
CLK_50 <= ~CLK_50;
end
if(cnt4==24'h98967F)
begin
cnt4<=24'h0;
CLK_5 <= ~CLK_5;
end
if(cnt5==26'h2FAF07F)
begin
cnt5<=26'h0;
CLK_1 <= ~CLK_1;
end
if(cnt6==28'h5F5E0FF)
begin
cnt6<=28'h0;
CLK_05 <= ~CLK_05;
end
end
endmodule | 0 |
138,417 | data/full_repos/permissive/83311855/src/seg_diaplay.v | 83,311,855 | seg_diaplay.v | v | 40 | 83 | [] | [] | [] | [(21, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/83311855/src/seg_diaplay.v:30: Cannot find file containing module: 'freDiv'\nfreDiv A1(.CLK_50M(CLK_50M),\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/83311855/src,data/full_repos/permissive/83311855/freDiv\n data/full_repos/permissive/83311855/src,data/full_repos/permissive/83311855/freDiv.v\n data/full_repos/permissive/83311855/src,data/full_repos/permissive/83311855/freDiv.sv\n freDiv\n freDiv.v\n freDiv.sv\n obj_dir/freDiv\n obj_dir/freDiv.v\n obj_dir/freDiv.sv\n%Error: Exiting due to 1 error(s)\n" | 302,343 | module | module seg_diaplay(
input CLK_50M,
input pau_flag,
input on_off,
output reg [3:0] lit,
output reg [6:0] dig
);
freDiv A1(.CLK_50M(CLK_50M),
.CLK_5M(CLK_5M),
.CLK_500(CLK_500),
.CLK_50(CLK_50),
.CLK_5(CLK_5),
.CLK_1(CLK_1),
.CLK_05(CLK_05)
);
endmodule | module seg_diaplay(
input CLK_50M,
input pau_flag,
input on_off,
output reg [3:0] lit,
output reg [6:0] dig
); |
freDiv A1(.CLK_50M(CLK_50M),
.CLK_5M(CLK_5M),
.CLK_500(CLK_500),
.CLK_50(CLK_50),
.CLK_5(CLK_5),
.CLK_1(CLK_1),
.CLK_05(CLK_05)
);
endmodule | 0 |
138,418 | data/full_repos/permissive/83311855/src/seg_dig_sub.v | 83,311,855 | seg_dig_sub.v | v | 49 | 83 | [] | [] | [] | [(21, 48)] | null | data/verilator_xmls/765b4804-e64c-4d0e-9ce7-a72686e0ba41.xml | null | 302,344 | module | module seg_dig_sub(
input [3:0] num,
output reg[6:0] a_to_g
);
always @(*)
case(num)
0: a_to_g = 7'b0000001;
1: a_to_g = 7'b1001111;
2: a_to_g = 7'b0010010;
3: a_to_g = 7'b0000110;
4: a_to_g = 7'b1001100;
5: a_to_g = 7'b0100100;
6: a_to_g = 7'b0100000;
7: a_to_g = 7'b0001111;
8: a_to_g = 7'b0000000;
9: a_to_g = 7'b0000100;
'hA: a_to_g = 7'b0001000;
'hB: a_to_g = 7'b1100000;
'hC: a_to_g = 7'b0110001;
'hD: a_to_g = 7'b1000010;
'hE: a_to_g = 7'b0110000;
'hF: a_to_g = 7'b0111000;
default: a_to_g = 7'b0000001;
endcase
endmodule | module seg_dig_sub(
input [3:0] num,
output reg[6:0] a_to_g
); |
always @(*)
case(num)
0: a_to_g = 7'b0000001;
1: a_to_g = 7'b1001111;
2: a_to_g = 7'b0010010;
3: a_to_g = 7'b0000110;
4: a_to_g = 7'b1001100;
5: a_to_g = 7'b0100100;
6: a_to_g = 7'b0100000;
7: a_to_g = 7'b0001111;
8: a_to_g = 7'b0000000;
9: a_to_g = 7'b0000100;
'hA: a_to_g = 7'b0001000;
'hB: a_to_g = 7'b1100000;
'hC: a_to_g = 7'b0110001;
'hD: a_to_g = 7'b1000010;
'hE: a_to_g = 7'b0110000;
'hF: a_to_g = 7'b0111000;
default: a_to_g = 7'b0000001;
endcase
endmodule | 0 |
138,419 | data/full_repos/permissive/83311855/src/seg_sym_sub.v | 83,311,855 | seg_sym_sub.v | v | 41 | 83 | [] | [] | [] | [(21, 40)] | null | data/verilator_xmls/45bc34fb-bb36-4d6d-8004-bf41c525e7b6.xml | null | 302,345 | module | module seg_sym_sub(
input [2:0] state,
output reg[6:0] s_to_d
);
always @(*)
case(state)
3'b000: s_to_d = 7'b1111111;
3'b001: s_to_d = 7'b0111111;
3'b010: s_to_d = 7'b0011111;
3'b011: s_to_d = 7'b0001111;
3'b100: s_to_d = 7'b0000111;
3'b101: s_to_d = 7'b0000011;
3'b110: s_to_d = 7'b0000001;
3'b111: s_to_d = 7'b0000000;
default: s_to_d = 7'b1111111;
endcase
endmodule | module seg_sym_sub(
input [2:0] state,
output reg[6:0] s_to_d
); |
always @(*)
case(state)
3'b000: s_to_d = 7'b1111111;
3'b001: s_to_d = 7'b0111111;
3'b010: s_to_d = 7'b0011111;
3'b011: s_to_d = 7'b0001111;
3'b100: s_to_d = 7'b0000111;
3'b101: s_to_d = 7'b0000011;
3'b110: s_to_d = 7'b0000001;
3'b111: s_to_d = 7'b0000000;
default: s_to_d = 7'b1111111;
endcase
endmodule | 0 |
138,420 | data/full_repos/permissive/83528847/display-controller/board_icestick.v | 83,528,847 | board_icestick.v | v | 43 | 84 | [] | [] | [] | null | line:20: before: ")" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/board_icestick.v:16: Cannot find file containing module: 'pll'\n pll u_pll (\n ^~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller,data/full_repos/permissive/83528847/pll\n data/full_repos/permissive/83528847/display-controller,data/full_repos/permissive/83528847/pll.v\n data/full_repos/permissive/83528847/display-controller,data/full_repos/permissive/83528847/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/83528847/display-controller/board_icestick.v:22: Cannot find file containing module: 'top'\n top #(\n ^~~\n%Error: Exiting due to 2 error(s)\n" | 302,346 | module | module board_icestick(clk, rgb, a, oe, lat, oclk, uart_txo, uart_rxi, leds, debug);
input wire clk;
output wire [4:0] leds;
output wire [7:0] debug;
input wire uart_rxi;
output wire uart_txo;
output wire oe, lat, oclk;
output wire [2:0] a;
output wire [5:0] rgb;
wire pll_locked;
wire pll_clk;
pll u_pll (
.locked(pll_locked),
.clock_in(clk),
.clock_out(pll_clk),
);
top #(
.if_uart(1)
) u_top (
.clk(pll_clk),
.leds(leds),
.debug(debug),
.rgb(rgb),
.a(a),
.oe(oe),
.lat(lat),
.oclk(oclk),
.uart_rxi(uart_rxi),
.uart_txo(uart_txo)
);
endmodule | module board_icestick(clk, rgb, a, oe, lat, oclk, uart_txo, uart_rxi, leds, debug); |
input wire clk;
output wire [4:0] leds;
output wire [7:0] debug;
input wire uart_rxi;
output wire uart_txo;
output wire oe, lat, oclk;
output wire [2:0] a;
output wire [5:0] rgb;
wire pll_locked;
wire pll_clk;
pll u_pll (
.locked(pll_locked),
.clock_in(clk),
.clock_out(pll_clk),
);
top #(
.if_uart(1)
) u_top (
.clk(pll_clk),
.leds(leds),
.debug(debug),
.rgb(rgb),
.a(a),
.oe(oe),
.lat(lat),
.oclk(oclk),
.uart_rxi(uart_rxi),
.uart_txo(uart_txo)
);
endmodule | 0 |
138,421 | data/full_repos/permissive/83528847/display-controller/board_up5k.v | 83,528,847 | board_up5k.v | v | 71 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/board_up5k.v:25: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer rst_counter;\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,347 | module | module board_up5k(r, g, b, a, clk, lat, oe, spi_sclk, spi_ss, spi_mosi, spi_miso);
input wire spi_sclk, spi_ss, spi_mosi;
output wire spi_miso;
wire int_clk;
SB_HFOSC u_hf_osc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF(int_clk)
);
wire pll_locked;
wire pll_clk;
pll u_pll (
.locked(pll_locked),
.clock_in(int_clk),
.clock_out(pll_clk),
);
reg rst;
reg integer rst_counter;
always @(posedge pll_clk) begin
if (pll_locked == 0) begin
rst_counter <= 0;
rst <= 1;
end else begin
if (rst_counter[5] == 1) begin
rst <= 0;
end else begin
rst <= 1;
rst_counter <= rst_counter + 1;
end
end
end
output wire [1:0] r;
output wire [1:0] g;
output wire [1:0] b;
output wire [3:0] a;
output wire clk;
output wire lat;
output wire oe;
assign a[3] = 0'b0;
top #(
.if_spi(1)
) u_top (
.clk(pll_clk),
.rst(rst),
.rgb({r[0], g[0], b[0], r[1], g[1], b[1]}),
.a(a[2:0]),
.oclk(clk),
.lat(lat),
.oe(oe),
.spi_sclk(spi_sclk),
.spi_ss(spi_ss),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
);
endmodule | module board_up5k(r, g, b, a, clk, lat, oe, spi_sclk, spi_ss, spi_mosi, spi_miso); |
input wire spi_sclk, spi_ss, spi_mosi;
output wire spi_miso;
wire int_clk;
SB_HFOSC u_hf_osc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF(int_clk)
);
wire pll_locked;
wire pll_clk;
pll u_pll (
.locked(pll_locked),
.clock_in(int_clk),
.clock_out(pll_clk),
);
reg rst;
reg integer rst_counter;
always @(posedge pll_clk) begin
if (pll_locked == 0) begin
rst_counter <= 0;
rst <= 1;
end else begin
if (rst_counter[5] == 1) begin
rst <= 0;
end else begin
rst <= 1;
rst_counter <= rst_counter + 1;
end
end
end
output wire [1:0] r;
output wire [1:0] g;
output wire [1:0] b;
output wire [3:0] a;
output wire clk;
output wire lat;
output wire oe;
assign a[3] = 0'b0;
top #(
.if_spi(1)
) u_top (
.clk(pll_clk),
.rst(rst),
.rgb({r[0], g[0], b[0], r[1], g[1], b[1]}),
.a(a[2:0]),
.oclk(clk),
.lat(lat),
.oe(oe),
.spi_sclk(spi_sclk),
.spi_ss(spi_ss),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
);
endmodule | 0 |
138,422 | data/full_repos/permissive/83528847/display-controller/data_loader.v | 83,528,847 | data_loader.v | v | 119 | 84 | [] | [] | [] | null | line:36: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/data_loader.v:36: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer column = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/data_loader.v:47: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer cmd = 0;\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,348 | module | module data_loader(clk, rst, idata, ivalid, wdata, wen, wrow, wcol, ready, loaded);
parameter segments = 1;
parameter rows = 8;
parameter columns = 32;
parameter bitwidth = 8;
input wire clk, rst;
output reg [(segments * bitwidth * 3) - 1:0] wdata = 0;
output reg [$clog2(rows) - 1:0] wrow = 0;
output reg [$clog2(columns) - 1:0] wcol = 0;
reg integer column = 0;
reg integer channel = 0;
output reg wen = 0;
input wire ready;
parameter
_cmd_wait = 0,
_cmd_load_row = 1;
reg integer cmd = 0;
reg dummy_write = 0;
output reg loaded = 0;
input wire [7:0] idata;
input wire ivalid;
always @(posedge clk) begin
if (rst == 1) begin
loaded <= 0;
column <= 0;
channel <= 0;
cmd <= 0;
wen <= 0;
end else begin
wen <= 0;
if (cmd == _cmd_wait) begin
loaded <= 0;
if (ivalid == 1) begin
if (idata[7:4] == 4'hf) begin
channel <= 0;
column <= 0;
wrow <= idata[3:0];
cmd <= _cmd_load_row;
dummy_write <= ready;
end else if (idata == 8'h10) begin
if (ready == 1) begin
loaded <= 1;
end
end
end
end else if (cmd == _cmd_load_row) begin
if (ivalid == 1) begin
wdata <= {wdata[(segments * bitwidth * 3) - bitwidth - 1:0], idata};
if (channel == ((segments * 3) - 1)) begin
wcol <= column;
wen <= dummy_write;
channel <= 0;
if (column == (columns - 1)) begin
column <= 0;
cmd <= _cmd_wait;
end else begin
column <= column + 1;
end
end else begin
channel <= channel + 1;
end
end
end else begin
cmd <= _cmd_wait;
end
end
end
endmodule | module data_loader(clk, rst, idata, ivalid, wdata, wen, wrow, wcol, ready, loaded); |
parameter segments = 1;
parameter rows = 8;
parameter columns = 32;
parameter bitwidth = 8;
input wire clk, rst;
output reg [(segments * bitwidth * 3) - 1:0] wdata = 0;
output reg [$clog2(rows) - 1:0] wrow = 0;
output reg [$clog2(columns) - 1:0] wcol = 0;
reg integer column = 0;
reg integer channel = 0;
output reg wen = 0;
input wire ready;
parameter
_cmd_wait = 0,
_cmd_load_row = 1;
reg integer cmd = 0;
reg dummy_write = 0;
output reg loaded = 0;
input wire [7:0] idata;
input wire ivalid;
always @(posedge clk) begin
if (rst == 1) begin
loaded <= 0;
column <= 0;
channel <= 0;
cmd <= 0;
wen <= 0;
end else begin
wen <= 0;
if (cmd == _cmd_wait) begin
loaded <= 0;
if (ivalid == 1) begin
if (idata[7:4] == 4'hf) begin
channel <= 0;
column <= 0;
wrow <= idata[3:0];
cmd <= _cmd_load_row;
dummy_write <= ready;
end else if (idata == 8'h10) begin
if (ready == 1) begin
loaded <= 1;
end
end
end
end else if (cmd == _cmd_load_row) begin
if (ivalid == 1) begin
wdata <= {wdata[(segments * bitwidth * 3) - bitwidth - 1:0], idata};
if (channel == ((segments * 3) - 1)) begin
wcol <= column;
wen <= dummy_write;
channel <= 0;
if (column == (columns - 1)) begin
column <= 0;
cmd <= _cmd_wait;
end else begin
column <= column + 1;
end
end else begin
channel <= channel + 1;
end
end
end else begin
cmd <= _cmd_wait;
end
end
end
endmodule | 0 |
138,423 | data/full_repos/permissive/83528847/display-controller/display_driver.v | 83,528,847 | display_driver.v | v | 316 | 90 | [] | [] | [] | null | line:91: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/display_driver.v:91: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer load_delay_counter = 0;\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,350 | module | module display_driver (clk, rst, frame_complete, row, column, pixel, rgb, oe, lat, oclk);
parameter integer load_delay = 1;
parameter integer segments = 1;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer bitwidth = 8;
input wire clk, rst;
input wire [((bitwidth * 3) * segments) - 1:0] pixel;
output reg [(3 * segments) - 1:0] rgb;
output reg oe, lat, oclk;
output reg [$clog2(rows) - 1:0] row;
integer column_counter;
output wire [$clog2(columns) - 1:0] column;
assign column = column_counter[0 +:$clog2(columns)];
reg [bitwidth:0] cycle = 0;
integer i = 0, c = 0;
always @(posedge clk) begin
if (rst == 1) begin
rgb <= {(3 * segments){1'b0}};
end else begin
for (i = 0; i < segments; i = i + 1) begin
for (c = 0; c < 3; c = c + 1) begin
rgb[(3 * i) + c] <=
(pixel[(bitwidth * 3 * i) + (bitwidth * c) +:bitwidth] >= cycle[0 +:bitwidth]) &&
(pixel[(bitwidth * 3 * i) + (bitwidth * c) +:bitwidth] != 0);
end
end
end
end
integer fsm1_state = 0;
reg integer load_delay_counter = 0;
reg load_complete = 0;
parameter
_fsm1_hold = 0,
_fsm1_wait = 1,
_fsm1_addr = 2,
_fsm1_rgbbits = 5,
_fsm1_push = 6,
_fsm1_push_hold = 7;
always @(posedge clk) begin
if (rst == 1) begin
oclk <= 0;
column_counter <= 0;
load_complete <= 0;
load_delay_counter <= 0;
fsm1_state <= _fsm1_wait;
end else begin
oclk <= (fsm1_state == _fsm1_rgbbits || fsm1_state == _fsm1_push_hold);
case (fsm1_state)
_fsm1_hold: begin
if (push_row == 0) begin
fsm1_state <= _fsm1_wait;
end
load_complete <= 1;
end
_fsm1_wait: begin
if (push_row == 1) begin
fsm1_state <= _fsm1_addr;
end
column_counter <= 0;
load_complete <= 0;
end
_fsm1_addr: begin
if (load_delay_counter >= load_delay) begin
fsm1_state <= _fsm1_rgbbits;
load_delay_counter <= 0;
column_counter <= column_counter + 1;
end else begin
load_delay_counter <= load_delay_counter + 1;
end
end
_fsm1_rgbbits: begin
fsm1_state <= _fsm1_push;
end
_fsm1_push: begin
fsm1_state <= _fsm1_push_hold;
column_counter <= column_counter + 1;
end
_fsm1_push_hold: begin
if (column_counter >= columns) begin
fsm1_state <= _fsm1_hold;
column_counter <= 0;
end else begin
fsm1_state <= _fsm1_push;
end
load_complete <= 0;
end
default: fsm1_state <= _fsm1_wait;
endcase
end
end
integer fsm2_state = 0;
reg cycle_complete = 0;
reg push_row = 0;
parameter
_fsm2_hold = 0,
_fsm2_wait = 1,
_fsm2_load = 2,
_fsm2_load_wait = 3,
_fsm2_latch = 4,
_fsm2_latch_hold = 5;
always @(posedge clk) begin
if (rst == 1) begin
lat <= 0;
oe <= 0;
cycle <= 0;
cycle_complete <= 0;
push_row <= 0;
fsm2_state <= _fsm1_wait;
end else begin
case (fsm2_state)
_fsm2_hold: begin
if (push_cycle == 0) begin
fsm2_state <= _fsm2_wait;
end
cycle_complete <= 1;
end
_fsm2_wait: begin
if (push_cycle == 1) begin
fsm2_state <= _fsm2_load;
end
cycle <= 0;
cycle_complete <= 0;
end
_fsm2_load: begin
fsm2_state <= _fsm2_load_wait;
push_row <= 1;
end
_fsm2_load_wait: begin
if (load_complete == 1) begin
if (cycle >= (2 ** bitwidth)) begin
fsm2_state <= _fsm2_hold;
cycle <= 0;
end else begin
fsm2_state <= _fsm2_latch;
cycle <= cycle + 1;
end
oe <= 0;
end
push_row <= 0;
end
_fsm2_latch: begin
fsm2_state <= _fsm2_latch_hold;
lat <= 1;
end
_fsm2_latch_hold: begin
fsm2_state <= _fsm2_load;
lat <= 0;
oe <= 1;
end
default: fsm2_state <= _fsm2_wait;
endcase
end
end
integer fsm3_state = 0;
output reg frame_complete = 0;
reg push_cycle = 0;
parameter
_fsm3_hold = 0,
_fsm3_wait = 1,
_fsm3_cycle = 2,
_fsm3_cycle_wait = 3;
always @(posedge clk) begin
if (rst == 1) begin
row <= 0;
frame_complete <= 0;
push_cycle <= 0;
fsm3_state <= _fsm1_wait;
end else begin
case (fsm3_state)
_fsm3_hold: begin
fsm3_state <= _fsm3_wait;
frame_complete <= 1;
end
_fsm3_wait: begin
fsm3_state <= _fsm3_cycle;
row <= 0;
frame_complete <= 0;
end
_fsm3_cycle: begin
fsm3_state <= _fsm3_cycle_wait;
push_cycle <= 1;
end
_fsm3_cycle_wait: begin
if (cycle_complete == 1) begin
if (row + 1 >= rows) begin
fsm3_state <= _fsm3_hold;
row <= 0;
end else begin
fsm3_state <= _fsm3_cycle;
row <= row + 1;
end
end
push_cycle <= 0;
end
default: fsm3_state <= _fsm3_wait;
endcase
end
end
endmodule | module display_driver (clk, rst, frame_complete, row, column, pixel, rgb, oe, lat, oclk); |
parameter integer load_delay = 1;
parameter integer segments = 1;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer bitwidth = 8;
input wire clk, rst;
input wire [((bitwidth * 3) * segments) - 1:0] pixel;
output reg [(3 * segments) - 1:0] rgb;
output reg oe, lat, oclk;
output reg [$clog2(rows) - 1:0] row;
integer column_counter;
output wire [$clog2(columns) - 1:0] column;
assign column = column_counter[0 +:$clog2(columns)];
reg [bitwidth:0] cycle = 0;
integer i = 0, c = 0;
always @(posedge clk) begin
if (rst == 1) begin
rgb <= {(3 * segments){1'b0}};
end else begin
for (i = 0; i < segments; i = i + 1) begin
for (c = 0; c < 3; c = c + 1) begin
rgb[(3 * i) + c] <=
(pixel[(bitwidth * 3 * i) + (bitwidth * c) +:bitwidth] >= cycle[0 +:bitwidth]) &&
(pixel[(bitwidth * 3 * i) + (bitwidth * c) +:bitwidth] != 0);
end
end
end
end
integer fsm1_state = 0;
reg integer load_delay_counter = 0;
reg load_complete = 0;
parameter
_fsm1_hold = 0,
_fsm1_wait = 1,
_fsm1_addr = 2,
_fsm1_rgbbits = 5,
_fsm1_push = 6,
_fsm1_push_hold = 7;
always @(posedge clk) begin
if (rst == 1) begin
oclk <= 0;
column_counter <= 0;
load_complete <= 0;
load_delay_counter <= 0;
fsm1_state <= _fsm1_wait;
end else begin
oclk <= (fsm1_state == _fsm1_rgbbits || fsm1_state == _fsm1_push_hold);
case (fsm1_state)
_fsm1_hold: begin
if (push_row == 0) begin
fsm1_state <= _fsm1_wait;
end
load_complete <= 1;
end
_fsm1_wait: begin
if (push_row == 1) begin
fsm1_state <= _fsm1_addr;
end
column_counter <= 0;
load_complete <= 0;
end
_fsm1_addr: begin
if (load_delay_counter >= load_delay) begin
fsm1_state <= _fsm1_rgbbits;
load_delay_counter <= 0;
column_counter <= column_counter + 1;
end else begin
load_delay_counter <= load_delay_counter + 1;
end
end
_fsm1_rgbbits: begin
fsm1_state <= _fsm1_push;
end
_fsm1_push: begin
fsm1_state <= _fsm1_push_hold;
column_counter <= column_counter + 1;
end
_fsm1_push_hold: begin
if (column_counter >= columns) begin
fsm1_state <= _fsm1_hold;
column_counter <= 0;
end else begin
fsm1_state <= _fsm1_push;
end
load_complete <= 0;
end
default: fsm1_state <= _fsm1_wait;
endcase
end
end
integer fsm2_state = 0;
reg cycle_complete = 0;
reg push_row = 0;
parameter
_fsm2_hold = 0,
_fsm2_wait = 1,
_fsm2_load = 2,
_fsm2_load_wait = 3,
_fsm2_latch = 4,
_fsm2_latch_hold = 5;
always @(posedge clk) begin
if (rst == 1) begin
lat <= 0;
oe <= 0;
cycle <= 0;
cycle_complete <= 0;
push_row <= 0;
fsm2_state <= _fsm1_wait;
end else begin
case (fsm2_state)
_fsm2_hold: begin
if (push_cycle == 0) begin
fsm2_state <= _fsm2_wait;
end
cycle_complete <= 1;
end
_fsm2_wait: begin
if (push_cycle == 1) begin
fsm2_state <= _fsm2_load;
end
cycle <= 0;
cycle_complete <= 0;
end
_fsm2_load: begin
fsm2_state <= _fsm2_load_wait;
push_row <= 1;
end
_fsm2_load_wait: begin
if (load_complete == 1) begin
if (cycle >= (2 ** bitwidth)) begin
fsm2_state <= _fsm2_hold;
cycle <= 0;
end else begin
fsm2_state <= _fsm2_latch;
cycle <= cycle + 1;
end
oe <= 0;
end
push_row <= 0;
end
_fsm2_latch: begin
fsm2_state <= _fsm2_latch_hold;
lat <= 1;
end
_fsm2_latch_hold: begin
fsm2_state <= _fsm2_load;
lat <= 0;
oe <= 1;
end
default: fsm2_state <= _fsm2_wait;
endcase
end
end
integer fsm3_state = 0;
output reg frame_complete = 0;
reg push_cycle = 0;
parameter
_fsm3_hold = 0,
_fsm3_wait = 1,
_fsm3_cycle = 2,
_fsm3_cycle_wait = 3;
always @(posedge clk) begin
if (rst == 1) begin
row <= 0;
frame_complete <= 0;
push_cycle <= 0;
fsm3_state <= _fsm1_wait;
end else begin
case (fsm3_state)
_fsm3_hold: begin
fsm3_state <= _fsm3_wait;
frame_complete <= 1;
end
_fsm3_wait: begin
fsm3_state <= _fsm3_cycle;
row <= 0;
frame_complete <= 0;
end
_fsm3_cycle: begin
fsm3_state <= _fsm3_cycle_wait;
push_cycle <= 1;
end
_fsm3_cycle_wait: begin
if (cycle_complete == 1) begin
if (row + 1 >= rows) begin
fsm3_state <= _fsm3_hold;
row <= 0;
end else begin
fsm3_state <= _fsm3_cycle;
row <= row + 1;
end
end
push_cycle <= 0;
end
default: fsm3_state <= _fsm3_wait;
endcase
end
end
endmodule | 0 |
138,424 | data/full_repos/permissive/83528847/display-controller/display_driver_pulsewidth.v | 83,528,847 | display_driver_pulsewidth.v | v | 190 | 101 | [] | [] | [] | null | line:108: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/display_driver_pulsewidth.v:108: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer fsm = 0;\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,351 | module | module display_driver_pulsewidth (clk, rst, frame_complete, row, column, pixel, rgb, oe, lat, oclk);
parameter integer load_delay = 1;
parameter integer segments = 1;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer bitwidth = 8;
input wire clk, rst;
input wire [((bitwidth * 3) * segments) - 1:0] pixel;
output reg frame_complete = 0;
output wire oe, lat, oclk;
output wire [(3 * segments) - 1:0] rgb;
output wire [$clog2(columns) - 1:0] column;
output reg [$clog2(rows) - 1:0] row = 0;
wire [$clog2(bitwidth) - 1:0] select_bit;
reg pulse_go = 0;
wire pulse_complete, pulse_full_complete;
display_driver_pulse_generator #(
.bitwidth(bitwidth)
) u_pulse (
.clk(clk),
.rst(rst),
.go(pulse_go),
.complete(pulse_complete),
.full_complete(pulse_full_complete),
.select(select_bit)
);
wire pipe_go;
display_driver_rgb_pipe #(
.pipe_length(load_delay),
.segments(segments),
.bitwidth(bitwidth)
) u_pipe (
.clk(clk),
.rst(rst),
.go(pipe_go),
.select(select_bit),
.pixel(pixel),
.rgb(rgb)
);
reg row_load = 0;
wire row_complete;
display_driver_row_loader #(
.pipe_length(load_delay),
.columns(columns)
) u_loader (
.clk(clk),
.rst(rst),
.load(row_load),
.complete(row_complete),
.pipe(pipe_go),
.column(column),
.oclk(oclk)
);
assign lat = row_complete;
assign oe = ((fsm == _fsm_row_wait) && pulse_go);
reg pulse_full_completed = 0;
reg integer fsm = 0;
parameter
_fsm_wait = 0,
_fsm_irow_load = 1,
_fsm_irow_wait = 2,
_fsm_row_load = 3,
_fsm_row_wait = 4,
_fsm_row_complete = 5;
always @(posedge clk) begin
if (rst == 1) begin
fsm <= _fsm_wait;
row_load <= 0;
pulse_go <= 0;
row <= 0;
frame_complete <= 0;
pulse_full_completed <= 0;
end else begin
if (fsm == _fsm_wait) begin
fsm <= _fsm_irow_load;
end else begin
if (fsm == _fsm_irow_load || fsm == _fsm_row_load) begin
row_load <= 1;
if (fsm == _fsm_row_load) begin
pulse_go <= 1;
end
pulse_full_completed <= 0;
end else if (fsm == _fsm_irow_wait || fsm == _fsm_row_wait) begin
if (row_complete == 1) begin
row_load <= 0;
end
if (pulse_complete == 1) begin
pulse_go <= 0;
end
pulse_full_completed <= pulse_full_completed | pulse_full_complete;
end
if (fsm == _fsm_irow_load) begin
fsm <= _fsm_irow_wait;
frame_complete <= 0;
end else if (fsm == _fsm_irow_wait) begin
if (row_complete == 1) begin
fsm <= _fsm_row_load;
end
frame_complete <= 0;
end else if (fsm == _fsm_row_load) begin
fsm <= _fsm_row_wait;
frame_complete <= 0;
end else if (fsm == _fsm_row_wait) begin
if ((row_complete == 1 || row_load == 0) && (pulse_complete == 1 || pulse_go == 0)) begin
if (pulse_full_completed == 1) begin
fsm <= _fsm_irow_load;
if (row == rows - 1) begin
frame_complete <= 1;
row <= 0;
end else begin
frame_complete <= 0;
row <= row + 1;
end
end else begin
fsm <= _fsm_row_load;
frame_complete <= 0;
end
end
end
end
end
end
endmodule | module display_driver_pulsewidth (clk, rst, frame_complete, row, column, pixel, rgb, oe, lat, oclk); |
parameter integer load_delay = 1;
parameter integer segments = 1;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer bitwidth = 8;
input wire clk, rst;
input wire [((bitwidth * 3) * segments) - 1:0] pixel;
output reg frame_complete = 0;
output wire oe, lat, oclk;
output wire [(3 * segments) - 1:0] rgb;
output wire [$clog2(columns) - 1:0] column;
output reg [$clog2(rows) - 1:0] row = 0;
wire [$clog2(bitwidth) - 1:0] select_bit;
reg pulse_go = 0;
wire pulse_complete, pulse_full_complete;
display_driver_pulse_generator #(
.bitwidth(bitwidth)
) u_pulse (
.clk(clk),
.rst(rst),
.go(pulse_go),
.complete(pulse_complete),
.full_complete(pulse_full_complete),
.select(select_bit)
);
wire pipe_go;
display_driver_rgb_pipe #(
.pipe_length(load_delay),
.segments(segments),
.bitwidth(bitwidth)
) u_pipe (
.clk(clk),
.rst(rst),
.go(pipe_go),
.select(select_bit),
.pixel(pixel),
.rgb(rgb)
);
reg row_load = 0;
wire row_complete;
display_driver_row_loader #(
.pipe_length(load_delay),
.columns(columns)
) u_loader (
.clk(clk),
.rst(rst),
.load(row_load),
.complete(row_complete),
.pipe(pipe_go),
.column(column),
.oclk(oclk)
);
assign lat = row_complete;
assign oe = ((fsm == _fsm_row_wait) && pulse_go);
reg pulse_full_completed = 0;
reg integer fsm = 0;
parameter
_fsm_wait = 0,
_fsm_irow_load = 1,
_fsm_irow_wait = 2,
_fsm_row_load = 3,
_fsm_row_wait = 4,
_fsm_row_complete = 5;
always @(posedge clk) begin
if (rst == 1) begin
fsm <= _fsm_wait;
row_load <= 0;
pulse_go <= 0;
row <= 0;
frame_complete <= 0;
pulse_full_completed <= 0;
end else begin
if (fsm == _fsm_wait) begin
fsm <= _fsm_irow_load;
end else begin
if (fsm == _fsm_irow_load || fsm == _fsm_row_load) begin
row_load <= 1;
if (fsm == _fsm_row_load) begin
pulse_go <= 1;
end
pulse_full_completed <= 0;
end else if (fsm == _fsm_irow_wait || fsm == _fsm_row_wait) begin
if (row_complete == 1) begin
row_load <= 0;
end
if (pulse_complete == 1) begin
pulse_go <= 0;
end
pulse_full_completed <= pulse_full_completed | pulse_full_complete;
end
if (fsm == _fsm_irow_load) begin
fsm <= _fsm_irow_wait;
frame_complete <= 0;
end else if (fsm == _fsm_irow_wait) begin
if (row_complete == 1) begin
fsm <= _fsm_row_load;
end
frame_complete <= 0;
end else if (fsm == _fsm_row_load) begin
fsm <= _fsm_row_wait;
frame_complete <= 0;
end else if (fsm == _fsm_row_wait) begin
if ((row_complete == 1 || row_load == 0) && (pulse_complete == 1 || pulse_go == 0)) begin
if (pulse_full_completed == 1) begin
fsm <= _fsm_irow_load;
if (row == rows - 1) begin
frame_complete <= 1;
row <= 0;
end else begin
frame_complete <= 0;
row <= row + 1;
end
end else begin
fsm <= _fsm_row_load;
frame_complete <= 0;
end
end
end
end
end
end
endmodule | 0 |
138,425 | data/full_repos/permissive/83528847/display-controller/display_driver_pulse_generator.v | 83,528,847 | display_driver_pulse_generator.v | v | 67 | 87 | [] | [] | [] | null | line:31: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/display_driver_pulse_generator.v:31: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer pulse_bit = 0;\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,352 | module | module display_driver_pulse_generator (clk, rst, go, complete, full_complete, select);
parameter integer bitwidth = 8;
input wire clk, rst;
output wire [$clog2(bitwidth) - 1:0] select;
assign select = pulse_bit[$clog2(bitwidth) - 1:0];
input wire go;
output reg complete = 0;
output reg full_complete = 0;
reg integer pulse_bit = 0;
reg [bitwidth - 1:0] pulse_length = {bitwidth{1'b1}};
reg [bitwidth - 1:0] pulse_counter = {bitwidth{1'b0}};
always @(posedge clk) begin
if (rst == 1) begin
complete <= 0;
full_complete <= 0;
pulse_counter <= 0;
pulse_bit <= 0;
pulse_length <= {bitwidth{1'b1}};
end else begin
if (complete == 0 && go == 1) begin
if (pulse_counter == pulse_length) begin
complete <= 1;
pulse_counter <= 0;
if (pulse_bit == bitwidth - 1) begin
pulse_bit <= 0;
pulse_length <= {bitwidth{1'b1}};
full_complete <= 1;
end else begin
pulse_bit <= pulse_bit + 1;
pulse_length <= {1'b0, pulse_length[bitwidth - 1:1]};
end
end else begin
pulse_counter <= pulse_counter + 1;
end
end else begin
complete <= 0;
full_complete <= 0;
pulse_counter <= 0;
end
end
end
endmodule | module display_driver_pulse_generator (clk, rst, go, complete, full_complete, select); |
parameter integer bitwidth = 8;
input wire clk, rst;
output wire [$clog2(bitwidth) - 1:0] select;
assign select = pulse_bit[$clog2(bitwidth) - 1:0];
input wire go;
output reg complete = 0;
output reg full_complete = 0;
reg integer pulse_bit = 0;
reg [bitwidth - 1:0] pulse_length = {bitwidth{1'b1}};
reg [bitwidth - 1:0] pulse_counter = {bitwidth{1'b0}};
always @(posedge clk) begin
if (rst == 1) begin
complete <= 0;
full_complete <= 0;
pulse_counter <= 0;
pulse_bit <= 0;
pulse_length <= {bitwidth{1'b1}};
end else begin
if (complete == 0 && go == 1) begin
if (pulse_counter == pulse_length) begin
complete <= 1;
pulse_counter <= 0;
if (pulse_bit == bitwidth - 1) begin
pulse_bit <= 0;
pulse_length <= {bitwidth{1'b1}};
full_complete <= 1;
end else begin
pulse_bit <= pulse_bit + 1;
pulse_length <= {1'b0, pulse_length[bitwidth - 1:1]};
end
end else begin
pulse_counter <= pulse_counter + 1;
end
end else begin
complete <= 0;
full_complete <= 0;
pulse_counter <= 0;
end
end
end
endmodule | 0 |
138,426 | data/full_repos/permissive/83528847/display-controller/display_driver_rgb_pipe.v | 83,528,847 | display_driver_rgb_pipe.v | v | 62 | 93 | [] | [] | [] | [(1, 61)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83528847/display-controller/display_driver_rgb_pipe.v:38: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'select\' generates 3 bits.\n : ... In instance display_driver_rgb_pipe\n rgb_pipe[g] <= pixel[(g * bitwidth) + select];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,353 | module | module display_driver_rgb_pipe (clk, rst, go, select, pixel, rgb);
parameter integer pipe_length = 1;
parameter integer segments = 1;
parameter integer bitwidth = 8;
input wire clk, rst;
input wire [((bitwidth * 3) * segments) - 1:0] pixel;
output wire [(3 * segments) - 1:0] rgb;
input wire [$clog2(bitwidth) - 1:0] select;
input wire go;
reg [(pipe_length * (segments * 3)) - 1:0] rgb_pipe = {pipe_length * (segments * 3){1'b0}};
genvar g, gg;
generate
for (g = 0; g < segments * 3; g = g + 1) begin
always @(posedge clk) begin
if (rst == 1) begin
rgb_pipe[g] <= 1'b0;
end else begin
if (go == 1) begin
rgb_pipe[g] <= pixel[(g * bitwidth) + select];
end
end
end
assign rgb[g] = rgb_pipe[((segments * 3) * (pipe_length - 1)) + g];
for (gg = 1; gg < pipe_length; gg = gg + 1) begin
always @(posedge clk) begin
if (rst == 1) begin
rgb_pipe[((segments * 3) * gg) + g] <= 1'b0;
end else begin
if (go == 1) begin
rgb_pipe[((segments * 3) * gg) + g] <= rgb_pipe[((segments * 3) * (gg - 1)) + g];
end
end
end
end
end
endgenerate
endmodule | module display_driver_rgb_pipe (clk, rst, go, select, pixel, rgb); |
parameter integer pipe_length = 1;
parameter integer segments = 1;
parameter integer bitwidth = 8;
input wire clk, rst;
input wire [((bitwidth * 3) * segments) - 1:0] pixel;
output wire [(3 * segments) - 1:0] rgb;
input wire [$clog2(bitwidth) - 1:0] select;
input wire go;
reg [(pipe_length * (segments * 3)) - 1:0] rgb_pipe = {pipe_length * (segments * 3){1'b0}};
genvar g, gg;
generate
for (g = 0; g < segments * 3; g = g + 1) begin
always @(posedge clk) begin
if (rst == 1) begin
rgb_pipe[g] <= 1'b0;
end else begin
if (go == 1) begin
rgb_pipe[g] <= pixel[(g * bitwidth) + select];
end
end
end
assign rgb[g] = rgb_pipe[((segments * 3) * (pipe_length - 1)) + g];
for (gg = 1; gg < pipe_length; gg = gg + 1) begin
always @(posedge clk) begin
if (rst == 1) begin
rgb_pipe[((segments * 3) * gg) + g] <= 1'b0;
end else begin
if (go == 1) begin
rgb_pipe[((segments * 3) * gg) + g] <= rgb_pipe[((segments * 3) * (gg - 1)) + g];
end
end
end
end
end
endgenerate
endmodule | 0 |
138,427 | data/full_repos/permissive/83528847/display-controller/display_driver_row_loader.v | 83,528,847 | display_driver_row_loader.v | v | 99 | 95 | [] | [] | [] | null | line:45: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/display_driver_row_loader.v:45: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer prepared = 0;\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,354 | module | module display_driver_row_loader (clk, rst, load, complete, oclk, column, pipe);
parameter integer pipe_length = 1;
parameter integer columns = 32;
input wire clk, rst;
input wire load;
output reg complete = 0;
output reg oclk = 0;
output reg pipe = 0;
reg integer prepared = 0;
output wire [$clog2(columns) - 1:0] column;
assign column = prepared[$clog2(columns) - 1:0];
always @(posedge clk) begin
if (rst == 1) begin
prepared <= 0;
complete <= 0;
pipe <= 0;
end else begin
if (complete == 0 && load == 1) begin
if (oclk == 0 || (prepared < pipe_length)) begin
if (prepared > pipe_length) begin
oclk <= 1;
pipe <= 1;
end else if (prepared == pipe_length) begin
pipe <= 0;
end else begin
pipe <= 1;
end
end else if (oclk == 1) begin
oclk <= 0;
pipe <= 0;
end
if ((oclk == 0 && prepared <= pipe_length) || (oclk == 1 && prepared > pipe_length)) begin
if (prepared == pipe_length + columns) begin
complete <= 1;
prepared <= 0;
end else begin
prepared <= prepared + 1;
end
end
end else begin
prepared <= 0;
complete <= 0;
pipe <= 0;
oclk <= 0;
end
end
end
endmodule | module display_driver_row_loader (clk, rst, load, complete, oclk, column, pipe); |
parameter integer pipe_length = 1;
parameter integer columns = 32;
input wire clk, rst;
input wire load;
output reg complete = 0;
output reg oclk = 0;
output reg pipe = 0;
reg integer prepared = 0;
output wire [$clog2(columns) - 1:0] column;
assign column = prepared[$clog2(columns) - 1:0];
always @(posedge clk) begin
if (rst == 1) begin
prepared <= 0;
complete <= 0;
pipe <= 0;
end else begin
if (complete == 0 && load == 1) begin
if (oclk == 0 || (prepared < pipe_length)) begin
if (prepared > pipe_length) begin
oclk <= 1;
pipe <= 1;
end else if (prepared == pipe_length) begin
pipe <= 0;
end else begin
pipe <= 1;
end
end else if (oclk == 1) begin
oclk <= 0;
pipe <= 0;
end
if ((oclk == 0 && prepared <= pipe_length) || (oclk == 1 && prepared > pipe_length)) begin
if (prepared == pipe_length + columns) begin
complete <= 1;
prepared <= 0;
end else begin
prepared <= prepared + 1;
end
end
end else begin
prepared <= 0;
complete <= 0;
pipe <= 0;
oclk <= 0;
end
end
end
endmodule | 0 |
138,428 | data/full_repos/permissive/83528847/display-controller/display_memory.v | 83,528,847 | display_memory.v | v | 37 | 108 | [] | [] | [] | [(2, 35)] | null | data/verilator_xmls/3d56d5b7-945a-4ed7-b096-310fb73b89aa.xml | null | 302,355 | module | module display_memory(clk, flip, wen, wrow, wcol, rrow, rcol, wdata, rdata);
parameter integer segments = 1;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer width = 24;
input wire clk, flip, wen;
input wire [$clog2(rows)-1:0] wrow, rrow;
input wire [$clog2(columns)-1:0] wcol, rcol;
input wire [(width * segments) - 1:0] wdata;
output reg [(width * segments) - 1:0] rdata;
reg [(width * segments) - 1:0] memory[0:(2 ** ($clog2(rows) + $clog2(columns) + 1)) - 1];
integer ik;
initial begin
for (ik = 0; ik < (2 ** ($clog2(rows) + $clog2(columns) + 1)) - 1; ik = ik + 1) begin
memory[ik] <= {(width * segments){1'b0}};
end
end
always @(posedge clk) begin
if (wen) begin
`ifndef SYNTHESIS
$display("memory wr @ flip %d, wrow %2d, wcol %2d == %h", !flip, wrow, wcol, wdata);
`endif
memory[{!flip, wrow, wcol}] <= wdata;
end
`ifndef SYNTHESIS
$display("memory rd @ flip %d, rrow %2d, rcol %2d == %h", flip, rrow, rcol, memory[{flip, rrow, rcol}]);
`endif
rdata <= memory[{flip, rrow, rcol}];
end
endmodule | module display_memory(clk, flip, wen, wrow, wcol, rrow, rcol, wdata, rdata); |
parameter integer segments = 1;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer width = 24;
input wire clk, flip, wen;
input wire [$clog2(rows)-1:0] wrow, rrow;
input wire [$clog2(columns)-1:0] wcol, rcol;
input wire [(width * segments) - 1:0] wdata;
output reg [(width * segments) - 1:0] rdata;
reg [(width * segments) - 1:0] memory[0:(2 ** ($clog2(rows) + $clog2(columns) + 1)) - 1];
integer ik;
initial begin
for (ik = 0; ik < (2 ** ($clog2(rows) + $clog2(columns) + 1)) - 1; ik = ik + 1) begin
memory[ik] <= {(width * segments){1'b0}};
end
end
always @(posedge clk) begin
if (wen) begin
`ifndef SYNTHESIS
$display("memory wr @ flip %d, wrow %2d, wcol %2d == %h", !flip, wrow, wcol, wdata);
`endif
memory[{!flip, wrow, wcol}] <= wdata;
end
`ifndef SYNTHESIS
$display("memory rd @ flip %d, rrow %2d, rcol %2d == %h", flip, rrow, rcol, memory[{flip, rrow, rcol}]);
`endif
rdata <= memory[{flip, rrow, rcol}];
end
endmodule | 0 |
138,429 | data/full_repos/permissive/83528847/display-controller/spi_controller.v | 83,528,847 | spi_controller.v | v | 149 | 94 | [] | [] | [] | null | line:17: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/spi_controller.v:17: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer column = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/spi_controller.v:30: syntax error, unexpected integer, expecting IDENTIFIER or '=' or do or final\n reg integer cmd = 0;\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,357 | module | module spi_controller(clk, rst, sclk, ss, mosi, miso, wdata, wen, wrow, wcol, ready, loaded);
parameter segments = 1;
parameter rows = 8;
parameter columns = 32;
parameter bitwidth = 8;
input wire clk, rst;
input wire sclk, ss, mosi;
output wire miso;
output reg [(segments * bitwidth * 3) - 1:0] wdata = 0;
output reg [$clog2(rows) - 1:0] wrow = 0;
output reg [$clog2(columns) - 1:0] wcol = 0;
reg integer column = 0;
reg integer channel = 0;
output reg wen = 0;
input wire ready;
parameter
_cmd_invalid = 0,
_cmd_load_row = 1,
_cmd_end = 2;
reg started = 0;
reg integer cmd = 0;
output reg loaded = 0;
reg complete = 0;
reg last_ready = 0;
reg mem_ready = 0;
wire [7:0] load_data;
wire load_valid;
reg [5:0] ss_buf;
always @(posedge clk) begin
if (rst == 1) begin
started <= 0;
loaded <= 0;
complete <= 0;
column <= 0;
channel <= 0;
cmd <= 0;
wen <= 0;
last_ready <= 0;
mem_ready <= 0;
end else begin
wen <= 0;
ss_buf <= {ss_buf[4:0], ss};
if (ready == 1 && last_ready == 0) begin
mem_ready <= 1;
end else if (ready == 0) begin
mem_ready <= 0;
end
last_ready <= ready;
if (started == 0) begin
if (load_valid == 1) begin
started <= 1;
if (load_data[7:4] == 4'hf) begin
channel <= 0;
column <= 0;
wrow <= load_data[3:0];
cmd <= _cmd_load_row;
end else if (load_data == 8'h10) begin
cmd <= _cmd_end;
end else begin
cmd <= _cmd_invalid;
end
if (complete == 1 && mem_ready == 1) begin
complete <= 0;
end
end
loaded <= 0;
end else if (started == 1) begin
case (cmd)
_cmd_load_row: begin
if (load_valid && (complete == 0)) begin
wdata <= {wdata[(segments * bitwidth * 3) - bitwidth - 1:0], load_data};
if (channel == ((segments * 3) - 1)) begin
wcol <= column;
wen <= 1;
channel <= 0;
if (column == (columns - 1)) begin
column <= 0;
end else begin
column <= column + 1;
end
end else begin
channel <= channel + 1;
end
end
end
_cmd_end: begin
if (ss == 0) begin
complete <= 1;
loaded <= (complete == 0);
end
end
endcase
if (ss_buf == 6'b110000) begin
started <= 0;
cmd <= _cmd_invalid;
end
end
end
end
spi_slave u_spi_slave (
.clk(clk),
.rst(rst),
.sclk(sclk),
.ss(ss),
.mosi(mosi),
.miso(miso),
.data(load_data),
.valid(load_valid)
);
endmodule | module spi_controller(clk, rst, sclk, ss, mosi, miso, wdata, wen, wrow, wcol, ready, loaded); |
parameter segments = 1;
parameter rows = 8;
parameter columns = 32;
parameter bitwidth = 8;
input wire clk, rst;
input wire sclk, ss, mosi;
output wire miso;
output reg [(segments * bitwidth * 3) - 1:0] wdata = 0;
output reg [$clog2(rows) - 1:0] wrow = 0;
output reg [$clog2(columns) - 1:0] wcol = 0;
reg integer column = 0;
reg integer channel = 0;
output reg wen = 0;
input wire ready;
parameter
_cmd_invalid = 0,
_cmd_load_row = 1,
_cmd_end = 2;
reg started = 0;
reg integer cmd = 0;
output reg loaded = 0;
reg complete = 0;
reg last_ready = 0;
reg mem_ready = 0;
wire [7:0] load_data;
wire load_valid;
reg [5:0] ss_buf;
always @(posedge clk) begin
if (rst == 1) begin
started <= 0;
loaded <= 0;
complete <= 0;
column <= 0;
channel <= 0;
cmd <= 0;
wen <= 0;
last_ready <= 0;
mem_ready <= 0;
end else begin
wen <= 0;
ss_buf <= {ss_buf[4:0], ss};
if (ready == 1 && last_ready == 0) begin
mem_ready <= 1;
end else if (ready == 0) begin
mem_ready <= 0;
end
last_ready <= ready;
if (started == 0) begin
if (load_valid == 1) begin
started <= 1;
if (load_data[7:4] == 4'hf) begin
channel <= 0;
column <= 0;
wrow <= load_data[3:0];
cmd <= _cmd_load_row;
end else if (load_data == 8'h10) begin
cmd <= _cmd_end;
end else begin
cmd <= _cmd_invalid;
end
if (complete == 1 && mem_ready == 1) begin
complete <= 0;
end
end
loaded <= 0;
end else if (started == 1) begin
case (cmd)
_cmd_load_row: begin
if (load_valid && (complete == 0)) begin
wdata <= {wdata[(segments * bitwidth * 3) - bitwidth - 1:0], load_data};
if (channel == ((segments * 3) - 1)) begin
wcol <= column;
wen <= 1;
channel <= 0;
if (column == (columns - 1)) begin
column <= 0;
end else begin
column <= column + 1;
end
end else begin
channel <= channel + 1;
end
end
end
_cmd_end: begin
if (ss == 0) begin
complete <= 1;
loaded <= (complete == 0);
end
end
endcase
if (ss_buf == 6'b110000) begin
started <= 0;
cmd <= _cmd_invalid;
end
end
end
end
spi_slave u_spi_slave (
.clk(clk),
.rst(rst),
.sclk(sclk),
.ss(ss),
.mosi(mosi),
.miso(miso),
.data(load_data),
.valid(load_valid)
);
endmodule | 0 |
138,430 | data/full_repos/permissive/83528847/display-controller/spi_slave.v | 83,528,847 | spi_slave.v | v | 74 | 74 | [] | [] | [] | [(2, 72)] | null | data/verilator_xmls/ea78c026-09fe-4885-b2a5-1ce9473178ad.xml | null | 302,358 | module | module spi_slave(clk, rst, sclk, ss, mosi, miso, data, valid);
parameter ss_active = 1;
input wire clk, rst, sclk, ss;
input wire mosi;
output wire miso;
reg [7:0] iword = 0;
reg [7:0] oword = 0;
reg [2:0] count = 0;
output wire [7:0] data;
output reg valid;
assign data = iword;
assign miso = oword[7];
reg [1:0] sclk_buf;
always @(posedge clk) begin
sclk_buf <= {sclk_buf[0], sclk};
if (rst == 1) begin
sclk_buf <= 2'b00;
end
end
always @(posedge clk) begin
valid <= 0;
if (ss == ss_active && sclk_buf == 2'b01) begin
iword <= {iword[6:0], mosi};
count <= count + 1;
if (count == 7) begin
valid <= 1;
end
end
if (rst == 1) begin
valid <= 0;
iword <= {8{1'b0}};
count <= 0;
end
end
always @(posedge clk) begin
if (ss == ss_active && sclk_buf == 2'b10) begin
oword <= {oword[6:0], 1'b0};
if (count == 0) begin
oword <= iword;
end
end
if (rst == 1) begin
oword <= {8{1'b0}};
end
end
endmodule | module spi_slave(clk, rst, sclk, ss, mosi, miso, data, valid); |
parameter ss_active = 1;
input wire clk, rst, sclk, ss;
input wire mosi;
output wire miso;
reg [7:0] iword = 0;
reg [7:0] oword = 0;
reg [2:0] count = 0;
output wire [7:0] data;
output reg valid;
assign data = iword;
assign miso = oword[7];
reg [1:0] sclk_buf;
always @(posedge clk) begin
sclk_buf <= {sclk_buf[0], sclk};
if (rst == 1) begin
sclk_buf <= 2'b00;
end
end
always @(posedge clk) begin
valid <= 0;
if (ss == ss_active && sclk_buf == 2'b01) begin
iword <= {iword[6:0], mosi};
count <= count + 1;
if (count == 7) begin
valid <= 1;
end
end
if (rst == 1) begin
valid <= 0;
iword <= {8{1'b0}};
count <= 0;
end
end
always @(posedge clk) begin
if (ss == ss_active && sclk_buf == 2'b10) begin
oword <= {oword[6:0], 1'b0};
if (count == 0) begin
oword <= iword;
end
end
if (rst == 1) begin
oword <= {8{1'b0}};
end
end
endmodule | 0 |
138,431 | data/full_repos/permissive/83528847/display-controller/top.v | 83,528,847 | top.v | v | 165 | 116 | [] | [] | [] | null | line:129: before: "*" | null | 1: b"%Error: data/full_repos/permissive/83528847/display-controller/top.v:129: Define or directive not defined: '`TARGET_FREQ'\n .divisor((`TARGET_FREQ * 1000000) / 115200 / 2)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/top.v:129: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n .divisor((`TARGET_FREQ * 1000000) / 115200 / 2)\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/top.v:140: Define or directive not defined: '`TARGET_FREQ'\n .divisor((`TARGET_FREQ * 1000000) / 115200)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/top.v:140: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n .divisor((`TARGET_FREQ * 1000000) / 115200)\n ^\n%Error: Exiting due to 4 error(s)\n" | 302,359 | module | module top(clk, rst, rgb, a, oe, lat, oclk, uart_txo, uart_rxi, spi_sclk, spi_ss, spi_mosi, spi_miso, leds, debug);
input wire clk;
input wire rst;
output reg [7:0] debug = 0;
output reg [4:0] leds = 5'b10000;
parameter integer segments = 2;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer bitdepth = 8;
wire internal_oe;
wire [$clog2(rows) - 1:0] row;
wire [$clog2(rows) - 1:0] wrow;
wire [$clog2(columns) - 1:0] column;
wire [$clog2(columns) - 1:0] wcol;
wire [(segments * 3) - 1:0] orgb;
wire frame_complete;
reg mem_flip = 0;
reg frame_flipped = 0;
reg ready = 1;
wire wen, loaded;
wire [(bitdepth * 3 * segments) - 1:0] pixel_load;
wire [(bitdepth * 3 * segments) - 1:0] pixel_data;
output wire oe, lat, oclk;
output wire [2:0] a;
output wire [5:0] rgb;
assign oe = ~internal_oe;
assign a = row[2:0];
assign rgb = orgb;
always @(posedge clk) begin
frame_flipped <= 0;
if (frame_complete && (ready == 0)) begin
mem_flip <= ~mem_flip;
ready <= 1;
frame_flipped <= 1;
end else if (ready && loaded) begin
ready <= 0;
end
end
display_driver #(
.segments(segments),
.rows(rows),
.columns(columns),
.bitwidth(bitdepth)
) u_driver (
.clk(clk),
.rst(rst),
.row(row),
.column(column),
.frame_complete(frame_complete),
.pixel(pixel_data),
.rgb(orgb),
.oe(internal_oe),
.lat(lat),
.oclk(oclk)
);
display_memory #(
.segments(segments),
.rows(rows),
.columns(columns),
.width(bitdepth * 3)
) u_memory (
.clk(clk),
.flip(mem_flip),
.wen(wen),
.wrow(wrow),
.wcol(wcol),
.wdata(pixel_load),
.rrow(row),
.rcol(column),
.rdata(pixel_data)
);
wire [7:0] loader_data;
wire loader_valid;
data_loader #(
.segments(segments),
.rows(rows),
.columns(columns),
.bitwidth(bitdepth)
) u_loader (
.clk(clk),
.rst(rst),
.idata(loader_data),
.ivalid(loader_valid),
.wdata(pixel_load),
.wen(wen),
.wrow(wrow),
.wcol(wcol),
.ready(ready),
.loaded(loaded)
);
input wire spi_sclk, spi_ss, spi_mosi;
output wire spi_miso;
input wire uart_rxi;
output wire uart_txo;
parameter integer if_uart = 0;
parameter integer if_spi = 0;
generate
if (if_uart == 1) begin
uart_rx #(
.bitwidth(bitdepth),
.divisor((`TARGET_FREQ * 1000000) / 115200 / 2)
) u_uart_rx (
.clk(clk),
.rst(rst),
.rxi(uart_rxi),
.data(loader_data),
.valid(loader_valid)
);
uart_tx #(
.bitwidth(bitdepth),
.divisor((`TARGET_FREQ * 1000000) / 115200)
) u_uart_tx (
.clk(clk),
.rst(rst),
.txo(uart_txo),
.data('he0),
.valid(frame_flipped)
);
end else if (if_spi == 1) begin
spi_slave #(
.ss_active(0)
) u_spi_slave (
.clk(clk),
.rst(rst),
.sclk(spi_sclk),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso),
.data(loader_data),
.valid(loader_valid)
);
end
endgenerate
endmodule | module top(clk, rst, rgb, a, oe, lat, oclk, uart_txo, uart_rxi, spi_sclk, spi_ss, spi_mosi, spi_miso, leds, debug); |
input wire clk;
input wire rst;
output reg [7:0] debug = 0;
output reg [4:0] leds = 5'b10000;
parameter integer segments = 2;
parameter integer rows = 8;
parameter integer columns = 32;
parameter integer bitdepth = 8;
wire internal_oe;
wire [$clog2(rows) - 1:0] row;
wire [$clog2(rows) - 1:0] wrow;
wire [$clog2(columns) - 1:0] column;
wire [$clog2(columns) - 1:0] wcol;
wire [(segments * 3) - 1:0] orgb;
wire frame_complete;
reg mem_flip = 0;
reg frame_flipped = 0;
reg ready = 1;
wire wen, loaded;
wire [(bitdepth * 3 * segments) - 1:0] pixel_load;
wire [(bitdepth * 3 * segments) - 1:0] pixel_data;
output wire oe, lat, oclk;
output wire [2:0] a;
output wire [5:0] rgb;
assign oe = ~internal_oe;
assign a = row[2:0];
assign rgb = orgb;
always @(posedge clk) begin
frame_flipped <= 0;
if (frame_complete && (ready == 0)) begin
mem_flip <= ~mem_flip;
ready <= 1;
frame_flipped <= 1;
end else if (ready && loaded) begin
ready <= 0;
end
end
display_driver #(
.segments(segments),
.rows(rows),
.columns(columns),
.bitwidth(bitdepth)
) u_driver (
.clk(clk),
.rst(rst),
.row(row),
.column(column),
.frame_complete(frame_complete),
.pixel(pixel_data),
.rgb(orgb),
.oe(internal_oe),
.lat(lat),
.oclk(oclk)
);
display_memory #(
.segments(segments),
.rows(rows),
.columns(columns),
.width(bitdepth * 3)
) u_memory (
.clk(clk),
.flip(mem_flip),
.wen(wen),
.wrow(wrow),
.wcol(wcol),
.wdata(pixel_load),
.rrow(row),
.rcol(column),
.rdata(pixel_data)
);
wire [7:0] loader_data;
wire loader_valid;
data_loader #(
.segments(segments),
.rows(rows),
.columns(columns),
.bitwidth(bitdepth)
) u_loader (
.clk(clk),
.rst(rst),
.idata(loader_data),
.ivalid(loader_valid),
.wdata(pixel_load),
.wen(wen),
.wrow(wrow),
.wcol(wcol),
.ready(ready),
.loaded(loaded)
);
input wire spi_sclk, spi_ss, spi_mosi;
output wire spi_miso;
input wire uart_rxi;
output wire uart_txo;
parameter integer if_uart = 0;
parameter integer if_spi = 0;
generate
if (if_uart == 1) begin
uart_rx #(
.bitwidth(bitdepth),
.divisor((`TARGET_FREQ * 1000000) / 115200 / 2)
) u_uart_rx (
.clk(clk),
.rst(rst),
.rxi(uart_rxi),
.data(loader_data),
.valid(loader_valid)
);
uart_tx #(
.bitwidth(bitdepth),
.divisor((`TARGET_FREQ * 1000000) / 115200)
) u_uart_tx (
.clk(clk),
.rst(rst),
.txo(uart_txo),
.data('he0),
.valid(frame_flipped)
);
end else if (if_spi == 1) begin
spi_slave #(
.ss_active(0)
) u_spi_slave (
.clk(clk),
.rst(rst),
.sclk(spi_sclk),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso),
.data(loader_data),
.valid(loader_valid)
);
end
endgenerate
endmodule | 0 |
138,432 | data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v | 83,528,847 | data_loader_simple.v | v | 231 | 116 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:34: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:39: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(data_loader_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:39: syntax error, unexpected \';\'\n `setup_vcd(data_loader_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:46: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:49: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:54: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:54: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:59: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:59: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:62: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:62: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:65: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:65: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:69: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:69: syntax error, unexpected \',\'\n `assert_eq(wen, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:70: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pixel, ({16\'hffff, i[7:0]}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:70: syntax error, unexpected \',\'\n `assert_eq(pixel, ({16\'hffff, i[7:0]}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:71: Define or directive not defined: \'`assert_eq\'\n `assert_eq(row, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:71: syntax error, unexpected \',\'\n `assert_eq(row, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:72: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, i);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:72: syntax error, unexpected \',\'\n `assert_eq(column, i);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:75: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:83: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:83: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:89: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:89: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:92: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:92: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:95: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:95: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:98: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:98: syntax error, unexpected \',\'\n `assert_eq(wen, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:99: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pixel, ({j[7:0], 8\'hed, i[7:0]}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:99: syntax error, unexpected \',\'\n `assert_eq(pixel, ({j[7:0], 8\'hed, i[7:0]}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:100: Define or directive not defined: \'`assert_eq\'\n `assert_eq(row, j);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:100: syntax error, unexpected \',\'\n `assert_eq(row, j);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:101: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, i);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:101: syntax error, unexpected \',\'\n `assert_eq(column, i);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:105: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:110: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:111: Define or directive not defined: \'`assert_eq\'\n `assert_eq(loaded, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:111: syntax error, unexpected \',\'\n `assert_eq(loaded, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:113: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:114: Define or directive not defined: \'`assert_eq\'\n `assert_eq(loaded, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:114: syntax error, unexpected \',\'\n `assert_eq(loaded, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:120: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:120: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:124: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:124: syntax error, unexpected \',\'\n `assert_eq(wen, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/data_loader_simple.v:127: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 0);\n ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,360 | module | module data_loader_simple;
reg clk = 0, rst = 0;
reg [7:0] idata;
reg ivalid;
wire [2:0] row;
wire [4:0] column;
wire [23:0] pixel;
wire wen;
reg ready = 0;
wire loaded;
data_loader #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(8)
) u_loader (
.clk(clk),
.rst(rst),
.idata(idata),
.ivalid(ivalid),
.wrow(row),
.wcol(column),
.wen(wen),
.wdata(pixel),
.ready(ready),
.loaded(loaded)
);
always
# 5 clk = !clk;
initial begin
integer i, j, z, x, y;
`setup_vcd(data_loader_simple);
idata <= 8'h00;
ivalid <= 0;
clk = 0; rst = 1;
ready <= 0;
@(negedge clk);
rst = 0;
ready <= 1;
@(negedge clk);
idata <= 8'hf0;
ivalid <= 1;
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
idata <= 8'hff;
if (i == 0)
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ivalid <= 0;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
$display("load content into row %d", j);
idata <= {4'hf, j[3:0]};
ivalid <= 1;
if (j == 0)
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
$display("pixel data row %d, col %d", j, i);
idata <= j[7:0];
if (i == 0)
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hed;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({j[7:0], 8'hed, i[7:0]}));
`assert_eq(row, j);
`assert_eq(column, i);
end
end
ivalid <= 0;
@(negedge clk);
ivalid <= 1;
idata <= 8'h10;
@(negedge clk);
`assert_eq(loaded, 1);
ivalid <= 0;
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 0;
idata <= 8'hf0;
ivalid <= 1;
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 0);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ivalid <= 0;
@(negedge clk);
ivalid <= 1;
idata <= 8'h10;
@(negedge clk);
`assert_eq(loaded, 0);
ivalid <= 0;
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 1;
idata <= 8'hf0;
ivalid <= 1;
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
idata <= 8'hff;
if (i == 0)
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ivalid <= 0;
@(negedge clk);
ready <= 1;
for (y = 0; y < 3; y = y + 1) begin
for (z = 0; z < 256; z = z + 1) begin
if (z == 0 && y == 0)
`assert_eq(loaded, 0);
for (j = 0; j < 8; j = j + 1) begin
ivalid <= 1;
idata <= {4'hf, j[3:0]};
if (j == 0)
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(loaded, 0);
for (i = 0; i < 32; i = i + 1) begin
idata <= (y == 0) ? z[7:0] : 8'h00;
if (i == 0)
`assert_eq(wen, 0);
`assert_eq(loaded, 0);
@(negedge clk);
idata <= (y == 1) ? z[7:0] : 8'h00;
`assert_eq(wen, 0);
`assert_eq(loaded, 0);
@(negedge clk);
idata <= (y == 2) ? z[7:0] : 8'h00;
`assert_eq(wen, 0);
`assert_eq(loaded, 0);
@(negedge clk);
$display("Writing colour %1d/%3d to row %2d[%2d], col %2d[%2d]. pixel = %h", y, z, row, j, column, i, pixel);
`assert_eq(wen, 1);
`assert_eq(pixel, ({
(y == 0) ? z[7:0] : 8'h00,
(y == 1) ? z[7:0] : 8'h00,
(y == 2) ? z[7:0] : 8'h00
}));
`assert_eq(row, j);
`assert_eq(column, i);
`assert_eq(loaded, 0);
end
end
idata <= 8'h10;
@(negedge clk);
`assert_eq(loaded, 1);
end
end
ivalid <= 0;
@(negedge clk);
$finish(0);
end
endmodule | module data_loader_simple; |
reg clk = 0, rst = 0;
reg [7:0] idata;
reg ivalid;
wire [2:0] row;
wire [4:0] column;
wire [23:0] pixel;
wire wen;
reg ready = 0;
wire loaded;
data_loader #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(8)
) u_loader (
.clk(clk),
.rst(rst),
.idata(idata),
.ivalid(ivalid),
.wrow(row),
.wcol(column),
.wen(wen),
.wdata(pixel),
.ready(ready),
.loaded(loaded)
);
always
# 5 clk = !clk;
initial begin
integer i, j, z, x, y;
`setup_vcd(data_loader_simple);
idata <= 8'h00;
ivalid <= 0;
clk = 0; rst = 1;
ready <= 0;
@(negedge clk);
rst = 0;
ready <= 1;
@(negedge clk);
idata <= 8'hf0;
ivalid <= 1;
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
idata <= 8'hff;
if (i == 0)
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ivalid <= 0;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
$display("load content into row %d", j);
idata <= {4'hf, j[3:0]};
ivalid <= 1;
if (j == 0)
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
$display("pixel data row %d, col %d", j, i);
idata <= j[7:0];
if (i == 0)
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hed;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({j[7:0], 8'hed, i[7:0]}));
`assert_eq(row, j);
`assert_eq(column, i);
end
end
ivalid <= 0;
@(negedge clk);
ivalid <= 1;
idata <= 8'h10;
@(negedge clk);
`assert_eq(loaded, 1);
ivalid <= 0;
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 0;
idata <= 8'hf0;
ivalid <= 1;
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 0);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ivalid <= 0;
@(negedge clk);
ivalid <= 1;
idata <= 8'h10;
@(negedge clk);
`assert_eq(loaded, 0);
ivalid <= 0;
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 1;
idata <= 8'hf0;
ivalid <= 1;
`assert_eq(wen, 0);
@(negedge clk);
for (i = 0; i < 32; i = i + 1) begin
idata <= 8'hff;
if (i == 0)
`assert_eq(wen, 0);
@(negedge clk);
idata <= 8'hff;
`assert_eq(wen, 0);
@(negedge clk);
idata <= i[7:0];
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ivalid <= 0;
@(negedge clk);
ready <= 1;
for (y = 0; y < 3; y = y + 1) begin
for (z = 0; z < 256; z = z + 1) begin
if (z == 0 && y == 0)
`assert_eq(loaded, 0);
for (j = 0; j < 8; j = j + 1) begin
ivalid <= 1;
idata <= {4'hf, j[3:0]};
if (j == 0)
`assert_eq(wen, 0);
@(negedge clk);
`assert_eq(loaded, 0);
for (i = 0; i < 32; i = i + 1) begin
idata <= (y == 0) ? z[7:0] : 8'h00;
if (i == 0)
`assert_eq(wen, 0);
`assert_eq(loaded, 0);
@(negedge clk);
idata <= (y == 1) ? z[7:0] : 8'h00;
`assert_eq(wen, 0);
`assert_eq(loaded, 0);
@(negedge clk);
idata <= (y == 2) ? z[7:0] : 8'h00;
`assert_eq(wen, 0);
`assert_eq(loaded, 0);
@(negedge clk);
$display("Writing colour %1d/%3d to row %2d[%2d], col %2d[%2d]. pixel = %h", y, z, row, j, column, i, pixel);
`assert_eq(wen, 1);
`assert_eq(pixel, ({
(y == 0) ? z[7:0] : 8'h00,
(y == 1) ? z[7:0] : 8'h00,
(y == 2) ? z[7:0] : 8'h00
}));
`assert_eq(row, j);
`assert_eq(column, i);
`assert_eq(loaded, 0);
end
end
idata <= 8'h10;
@(negedge clk);
`assert_eq(loaded, 1);
end
end
ivalid <= 0;
@(negedge clk);
$finish(0);
end
endmodule | 0 |
138,433 | data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v | 83,528,847 | display_color_encoder_10b.v | v | 60 | 80 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:20: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:24: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(display_color_encoder_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:24: syntax error, unexpected \';\'\n `setup_vcd(display_color_encoder_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:33: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:34: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h3ff, 10\'h3ff}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:34: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h3ff, 10\'h3ff}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:37: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:38: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h3ff, 10\'h000}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:38: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h3ff, 10\'h000}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:41: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:42: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h000, 10\'h3ff}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:42: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h000, 10\'h3ff}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:45: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:46: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h3ff}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:46: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h000, 10\'h3ff, 10\'h3ff}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:49: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:50: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h000, 10\'h000, 10\'h000}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:50: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({10\'h000, 10\'h000, 10\'h000, 10\'h000, 10\'h000, 10\'h000}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:53: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:54: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({10\'h3ff, 10\'h3ff, 10\'h3ff, 10\'h000, 10\'h000, 10\'h000}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_10b.v:54: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({10\'h3ff, 10\'h3ff, 10\'h3ff, 10\'h000, 10\'h000, 10\'h000}));\n ^\n%Error: Exiting due to 21 error(s), 1 warning(s)\n' | 302,361 | module | module display_color_encoder_simple;
reg clk = 0;
reg [47:0] pixel;
reg [59:0] cpixel;
display_color_encoder #(
.segments(2),
.bitwidth(8),
.cyclewidth(10)
) u_encoder (
.clk(clk),
.pixel(pixel),
.cpixel(cpixel)
);
always
# 5 clk = !clk;
integer i, c;
initial begin
`setup_vcd(display_color_encoder_simple);
pixel = 'h000000000000;
pixel = {24'h000000, 24'hffffff};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h3ff, 10'h3ff, 10'h3ff}));
pixel = {24'h000000, 24'hffff00};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h3ff, 10'h3ff, 10'h000}));
pixel = {24'h000000, 24'hff00ff};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h3ff, 10'h000, 10'h3ff}));
pixel = {24'h000000, 24'h00ffff};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h000, 10'h3ff, 10'h3ff}));
pixel = {24'h000000, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h000, 10'h000, 10'h000}));
pixel = {24'hffffff, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({10'h3ff, 10'h3ff, 10'h3ff, 10'h000, 10'h000, 10'h000}));
$finish(0);
end
endmodule | module display_color_encoder_simple; |
reg clk = 0;
reg [47:0] pixel;
reg [59:0] cpixel;
display_color_encoder #(
.segments(2),
.bitwidth(8),
.cyclewidth(10)
) u_encoder (
.clk(clk),
.pixel(pixel),
.cpixel(cpixel)
);
always
# 5 clk = !clk;
integer i, c;
initial begin
`setup_vcd(display_color_encoder_simple);
pixel = 'h000000000000;
pixel = {24'h000000, 24'hffffff};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h3ff, 10'h3ff, 10'h3ff}));
pixel = {24'h000000, 24'hffff00};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h3ff, 10'h3ff, 10'h000}));
pixel = {24'h000000, 24'hff00ff};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h3ff, 10'h000, 10'h3ff}));
pixel = {24'h000000, 24'h00ffff};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h000, 10'h3ff, 10'h3ff}));
pixel = {24'h000000, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({10'h000, 10'h000, 10'h000, 10'h000, 10'h000, 10'h000}));
pixel = {24'hffffff, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({10'h3ff, 10'h3ff, 10'h3ff, 10'h000, 10'h000, 10'h000}));
$finish(0);
end
endmodule | 0 |
138,434 | data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v | 83,528,847 | display_color_encoder_simple.v | v | 60 | 72 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:20: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:24: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(display_color_encoder_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:24: syntax error, unexpected \';\'\n `setup_vcd(display_color_encoder_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:33: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:34: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({24\'h000000, 24\'hffffff}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:34: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({24\'h000000, 24\'hffffff}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:37: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:38: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({24\'h000000, 24\'hffff00}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:38: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({24\'h000000, 24\'hffff00}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:41: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:42: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({24\'h000000, 24\'hff00ff}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:42: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({24\'h000000, 24\'hff00ff}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:45: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:46: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({24\'h000000, 24\'h00ffff}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:46: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({24\'h000000, 24\'h00ffff}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:49: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:50: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({24\'h000000, 24\'h000000}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:50: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({24\'h000000, 24\'h000000}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:53: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:54: Define or directive not defined: \'`assert_eq\'\n `assert_eq(cpixel, ({24\'hffffff, 24\'h000000}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_color_encoder_simple.v:54: syntax error, unexpected \',\'\n `assert_eq(cpixel, ({24\'hffffff, 24\'h000000}));\n ^\n%Error: Exiting due to 21 error(s), 1 warning(s)\n' | 302,362 | module | module display_color_encoder_simple;
reg clk = 0;
reg [47:0] pixel;
reg [47:0] cpixel;
display_color_encoder #(
.segments(2),
.bitwidth(8),
.cyclewidth(8)
) u_encoder (
.clk(clk),
.pixel(pixel),
.cpixel(cpixel)
);
always
# 5 clk = !clk;
integer i, c;
initial begin
`setup_vcd(display_color_encoder_simple);
pixel = 'h000000000000;
pixel = {24'h000000, 24'hffffff};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'hffffff}));
pixel = {24'h000000, 24'hffff00};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'hffff00}));
pixel = {24'h000000, 24'hff00ff};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'hff00ff}));
pixel = {24'h000000, 24'h00ffff};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'h00ffff}));
pixel = {24'h000000, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'h000000}));
pixel = {24'hffffff, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({24'hffffff, 24'h000000}));
$finish(0);
end
endmodule | module display_color_encoder_simple; |
reg clk = 0;
reg [47:0] pixel;
reg [47:0] cpixel;
display_color_encoder #(
.segments(2),
.bitwidth(8),
.cyclewidth(8)
) u_encoder (
.clk(clk),
.pixel(pixel),
.cpixel(cpixel)
);
always
# 5 clk = !clk;
integer i, c;
initial begin
`setup_vcd(display_color_encoder_simple);
pixel = 'h000000000000;
pixel = {24'h000000, 24'hffffff};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'hffffff}));
pixel = {24'h000000, 24'hffff00};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'hffff00}));
pixel = {24'h000000, 24'hff00ff};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'hff00ff}));
pixel = {24'h000000, 24'h00ffff};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'h00ffff}));
pixel = {24'h000000, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({24'h000000, 24'h000000}));
pixel = {24'hffffff, 24'h000000};
@(negedge clk);
`assert_eq(cpixel, ({24'hffffff, 24'h000000}));
$finish(0);
end
endmodule | 0 |
138,435 | data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v | 83,528,847 | display_driver_simple.v | v | 119 | 171 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:31: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:41: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(display_driver_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:41: syntax error, unexpected \';\'\n `setup_vcd(display_driver_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:53: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:67: syntax error, unexpected \'@\'\n @(posedge oclk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:70: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, in[4:0]); \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:70: syntax error, unexpected \',\'\n `assert_eq(column, in[4:0]); \n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:72: Define or directive not defined: \'`assert_eq\'\n `assert_eq(row, r);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:72: syntax error, unexpected \',\'\n `assert_eq(row, r);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:73: Define or directive not defined: \'`assert_eq\'\n `assert_eq(lat, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:73: syntax error, unexpected \',\'\n `assert_eq(lat, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:74: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oe, (k != 0));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:74: syntax error, unexpected \',\'\n `assert_eq(oe, (k != 0));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:75: Define or directive not defined: \'`assert_eq\'\n `assert_eq(frame_complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:75: syntax error, unexpected \',\'\n `assert_eq(frame_complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:77: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b100);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:77: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b100);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:79: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b000);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:79: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b000);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:82: Define or directive not defined: \'`assert_eq\'\n `assert_eq(row, r);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:82: syntax error, unexpected \',\'\n `assert_eq(row, r);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:83: Define or directive not defined: \'`assert_eq\'\n `assert_eq(lat, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:83: syntax error, unexpected \',\'\n `assert_eq(lat, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:85: Define or directive not defined: \'`assert_eq\'\n `assert_eq(frame_complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:85: syntax error, unexpected \',\'\n `assert_eq(frame_complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:89: syntax error, unexpected \'@\'\n @(posedge lat);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:91: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oe, 0); \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:91: syntax error, unexpected \',\'\n `assert_eq(oe, 0); \n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:92: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:92: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:93: Define or directive not defined: \'`assert_eq\'\n `assert_eq(frame_complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:93: syntax error, unexpected \',\'\n `assert_eq(frame_complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:95: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oe, 1); \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:95: syntax error, unexpected \',\'\n `assert_eq(oe, 1); \n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:96: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:96: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:97: Define or directive not defined: \'`assert_eq\'\n `assert_eq(frame_complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:97: syntax error, unexpected \',\'\n `assert_eq(frame_complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:99: syntax error, unexpected \'@\'\n @(negedge oe); \n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:101: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:101: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:102: Define or directive not defined: \'`assert_eq\'\n `assert_eq(frame_complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:102: syntax error, unexpected \',\'\n `assert_eq(frame_complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:107: syntax error, unexpected \'@\'\n @(posedge frame_complete);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:109: Define or directive not defined: \'`assert_eq\'\n `assert_eq(lat, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:109: syntax error, unexpected \',\'\n `assert_eq(lat, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:110: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oe, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:110: syntax error, unexpected \',\'\n `assert_eq(oe, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:111: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_simple.v:111: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,365 | module | module display_driver_simple;
reg clk, rst;
wire [2:0] row;
wire [4:0] column;
reg [23:0] pixel = 0;
wire frame_complete, oe, lat, oclk;
wire [2:0] rgb;
display_driver #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(8)
) u_driver (
.clk(clk),
.rst(rst),
.frame_complete(frame_complete),
.row(row),
.column(column),
.pixel(pixel),
.rgb(rgb),
.oe(oe),
.lat(lat),
.oclk(oclk)
);
always
# 5 clk = !clk;
reg [23:0] pixel_data [0:(32 * 8) - 1];
always @(posedge clk) begin
pixel <= pixel_data[{row, column}];
end
integer i, in, inn, j, r, k, kn;
initial begin
`setup_vcd(display_driver_simple);
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
if (i == 0 && j == 0)
pixel_data[(j * 32) + i] <= 24'hff0000;
else
pixel_data[(j * 32) + i] <= 24'h000000;
end
end
clk = 0;
rst = 1;
@(negedge clk)
rst = 0;
`define display_state(state) \
$display("[%t] {%10s} %4d/(%4d)/%4d | %2dx%2d, OE(%d) LAT(%d) OCLK(%d) SF(%d) | B:%2d(%2d)", $time, state, r, kn, k, row, column, oe, lat, oclk, frame_complete, i, in)
for (r = 0; r < 2; r = r + 1) begin
for (k = 0; k < 256 + 1; k = k + 1) begin
kn = (k + 1);
for (i = 0; i < 32; i = i + 1) begin
in = (i + 1);
inn = (in + 1);
@(posedge oclk);
`display_state("col+");
if (i == 32) begin
`assert_eq(column, in[4:0]);
end
`assert_eq(row, r);
`assert_eq(lat, 0);
`assert_eq(oe, (k != 0));
`assert_eq(frame_complete, 0);
if (r == 0 && i == 0)
`assert_eq(rgb, 3'b100);
else
`assert_eq(rgb, 3'b000);
@(negedge oclk);
`display_state("col-");
`assert_eq(row, r);
`assert_eq(lat, 0);
`assert_eq(frame_complete, 0);
end
if (k != 256) begin
@(posedge lat);
`display_state("latch");
`assert_eq(oe, 0);
`assert_eq(oclk, 0);
`assert_eq(frame_complete, 0);
@(negedge lat);
`assert_eq(oe, 1);
`assert_eq(oclk, 0);
`assert_eq(frame_complete, 0);
end else begin
@(negedge oe);
`display_state("load-end");
`assert_eq(oclk, 0);
`assert_eq(frame_complete, 0);
end
end
if (r == 7) begin
@(posedge frame_complete);
$display("safe flip asserted");
`assert_eq(lat, 0);
`assert_eq(oe, 0);
`assert_eq(oclk, 0);
end
end
$finish(0);
end
endmodule | module display_driver_simple; |
reg clk, rst;
wire [2:0] row;
wire [4:0] column;
reg [23:0] pixel = 0;
wire frame_complete, oe, lat, oclk;
wire [2:0] rgb;
display_driver #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(8)
) u_driver (
.clk(clk),
.rst(rst),
.frame_complete(frame_complete),
.row(row),
.column(column),
.pixel(pixel),
.rgb(rgb),
.oe(oe),
.lat(lat),
.oclk(oclk)
);
always
# 5 clk = !clk;
reg [23:0] pixel_data [0:(32 * 8) - 1];
always @(posedge clk) begin
pixel <= pixel_data[{row, column}];
end
integer i, in, inn, j, r, k, kn;
initial begin
`setup_vcd(display_driver_simple);
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
if (i == 0 && j == 0)
pixel_data[(j * 32) + i] <= 24'hff0000;
else
pixel_data[(j * 32) + i] <= 24'h000000;
end
end
clk = 0;
rst = 1;
@(negedge clk)
rst = 0;
`define display_state(state) \
$display("[%t] {%10s} %4d/(%4d)/%4d | %2dx%2d, OE(%d) LAT(%d) OCLK(%d) SF(%d) | B:%2d(%2d)", $time, state, r, kn, k, row, column, oe, lat, oclk, frame_complete, i, in)
for (r = 0; r < 2; r = r + 1) begin
for (k = 0; k < 256 + 1; k = k + 1) begin
kn = (k + 1);
for (i = 0; i < 32; i = i + 1) begin
in = (i + 1);
inn = (in + 1);
@(posedge oclk);
`display_state("col+");
if (i == 32) begin
`assert_eq(column, in[4:0]);
end
`assert_eq(row, r);
`assert_eq(lat, 0);
`assert_eq(oe, (k != 0));
`assert_eq(frame_complete, 0);
if (r == 0 && i == 0)
`assert_eq(rgb, 3'b100);
else
`assert_eq(rgb, 3'b000);
@(negedge oclk);
`display_state("col-");
`assert_eq(row, r);
`assert_eq(lat, 0);
`assert_eq(frame_complete, 0);
end
if (k != 256) begin
@(posedge lat);
`display_state("latch");
`assert_eq(oe, 0);
`assert_eq(oclk, 0);
`assert_eq(frame_complete, 0);
@(negedge lat);
`assert_eq(oe, 1);
`assert_eq(oclk, 0);
`assert_eq(frame_complete, 0);
end else begin
@(negedge oe);
`display_state("load-end");
`assert_eq(oclk, 0);
`assert_eq(frame_complete, 0);
end
end
if (r == 7) begin
@(posedge frame_complete);
$display("safe flip asserted");
`assert_eq(lat, 0);
`assert_eq(oe, 0);
`assert_eq(oclk, 0);
end
end
$finish(0);
end
endmodule | 0 |
138,436 | data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v | 83,528,847 | display_driver_timing.v | v | 104 | 138 | [] | [] | [] | null | line:10: before: "window" | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:34: Unsupported: Ignoring delay on this delayed statement.\n # period clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:37: syntax error, unexpected integer, expecting IDENTIFIER or \'=\' or do or final\n reg integer pixel_cycles [0:(32 * 8) - 1];\n ^~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:44: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(display_driver_timing);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:44: syntax error, unexpected \';\'\n `setup_vcd(display_driver_timing);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:58: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:64: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:85: Define or directive not defined: \'`assert_dge\'\n `assert_dge((clkfreq / frame_cycles), 60);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_driver_timing.v:85: syntax error, unexpected \',\'\n `assert_dge((clkfreq / frame_cycles), 60);\n ^\n%Error: Exiting due to 8 error(s), 1 warning(s)\n' | 302,366 | module | module display_driver_timing;
reg clk, rst;
wire [2:0] row;
wire [4:0] column;
reg [(10 * 3) - 1:0] pixel = 0;
wire frame_complete, oe, lat, oclk;
wire [2:0] rgb;
display_driver #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(10)
) u_driver (
.clk(clk),
.rst(rst),
.frame_complete(frame_complete),
.row(row),
.column(column),
.pixel(pixel),
.rgb(rgb),
.oe(oe),
.lat(lat),
.oclk(oclk)
);
parameter clkfreq = 48000000;
parameter period = ((1 * 1000 * 1000 * 1000) / clkfreq);
always
# period clk = !clk;
reg integer pixel_cycles [0:(32 * 8) - 1];
initial begin
integer i, j, z, t;
integer frame_count, frame_cycles;
integer mark_complete;
`setup_vcd(display_driver_timing);
pixel <= 24'hffffff;
frame_count = 0;
frame_cycles = 0;
mark_complete = 0;
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
pixel_cycles[(j * 32) + i] <= 0;
end
end
clk = 0;
rst = 1;
@(negedge clk)
rst = 0;
repeat (1) begin
$display("[%t] info: frame %d", $time, frame_count);
while (mark_complete == 0) begin
@(posedge clk);
frame_cycles = frame_cycles + 1;
for (z = 0; z < 32; z = z + 1) begin
if (oe == 1) begin
pixel_cycles[(row * 32) + z] = pixel_cycles[(row * 32) + z] + 1;
end
end
if (frame_complete == 1) begin
t = 0;
for (j = 0; j < 8; j = j + 1) begin
z = pixel_cycles[(j * 32)];
t = t + z;
$display("[%t] info: row %3d = %d/%d, %d %%", $time, j, z, frame_cycles, (z * 100) / frame_cycles);
end
$display("[%t] info: inter-frame = %d/%d, %d %%", $time, frame_cycles - t, frame_cycles, ((frame_cycles - t) * 100) / frame_cycles);
$display("[%t] info: frame takes %d cycles, vert %d hz (%d Hz clk)", $time, frame_cycles, (clkfreq / frame_cycles), clkfreq);
`assert_dge((clkfreq / frame_cycles), 60);
frame_cycles = 0;
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
pixel_cycles[(j * 32) + i] = 0;
end
end
mark_complete = 1;
end
end
mark_complete = 0;
frame_count = frame_count + 1;
end
$finish(0);
end
endmodule | module display_driver_timing; |
reg clk, rst;
wire [2:0] row;
wire [4:0] column;
reg [(10 * 3) - 1:0] pixel = 0;
wire frame_complete, oe, lat, oclk;
wire [2:0] rgb;
display_driver #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(10)
) u_driver (
.clk(clk),
.rst(rst),
.frame_complete(frame_complete),
.row(row),
.column(column),
.pixel(pixel),
.rgb(rgb),
.oe(oe),
.lat(lat),
.oclk(oclk)
);
parameter clkfreq = 48000000;
parameter period = ((1 * 1000 * 1000 * 1000) / clkfreq);
always
# period clk = !clk;
reg integer pixel_cycles [0:(32 * 8) - 1];
initial begin
integer i, j, z, t;
integer frame_count, frame_cycles;
integer mark_complete;
`setup_vcd(display_driver_timing);
pixel <= 24'hffffff;
frame_count = 0;
frame_cycles = 0;
mark_complete = 0;
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
pixel_cycles[(j * 32) + i] <= 0;
end
end
clk = 0;
rst = 1;
@(negedge clk)
rst = 0;
repeat (1) begin
$display("[%t] info: frame %d", $time, frame_count);
while (mark_complete == 0) begin
@(posedge clk);
frame_cycles = frame_cycles + 1;
for (z = 0; z < 32; z = z + 1) begin
if (oe == 1) begin
pixel_cycles[(row * 32) + z] = pixel_cycles[(row * 32) + z] + 1;
end
end
if (frame_complete == 1) begin
t = 0;
for (j = 0; j < 8; j = j + 1) begin
z = pixel_cycles[(j * 32)];
t = t + z;
$display("[%t] info: row %3d = %d/%d, %d %%", $time, j, z, frame_cycles, (z * 100) / frame_cycles);
end
$display("[%t] info: inter-frame = %d/%d, %d %%", $time, frame_cycles - t, frame_cycles, ((frame_cycles - t) * 100) / frame_cycles);
$display("[%t] info: frame takes %d cycles, vert %d hz (%d Hz clk)", $time, frame_cycles, (clkfreq / frame_cycles), clkfreq);
`assert_dge((clkfreq / frame_cycles), 60);
frame_cycles = 0;
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
pixel_cycles[(j * 32) + i] = 0;
end
end
mark_complete = 1;
end
end
mark_complete = 0;
frame_count = frame_count + 1;
end
$finish(0);
end
endmodule | 0 |
138,437 | data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v | 83,528,847 | display_memory_simple.v | v | 106 | 70 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:26: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:31: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(display_memory_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:31: syntax error, unexpected \';\'\n `setup_vcd(display_memory_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:41: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:51: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:54: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rdata, 24\'h000000);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:54: syntax error, unexpected \',\'\n `assert_eq(rdata, 24\'h000000);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:60: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:63: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rdata, 24\'hffffff);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:63: syntax error, unexpected \',\'\n `assert_eq(rdata, 24\'hffffff);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:76: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:77: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rdata, \'hffffff);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:77: syntax error, unexpected \',\'\n `assert_eq(rdata, \'hffffff);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:87: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:88: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rdata, \'h111111);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:88: syntax error, unexpected \',\'\n `assert_eq(rdata, \'h111111);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:98: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:99: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rdata, \'hffffff);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/display_memory_simple.v:99: syntax error, unexpected \',\'\n `assert_eq(rdata, \'hffffff);\n ^\n%Error: Exiting due to 19 error(s), 1 warning(s)\n' | 302,367 | module | module display_memory_simple;
reg clk = 0;
reg flip, wen = 0;
reg [2:0] wrow, rrow = 0;
reg [4:0] wcol, rcol = 0;
reg [23:0] wdata = 0;
wire [23:0] rdata;
display_memory #(
.rows(8),
.columns(32)
) u_memory (
.clk(clk),
.flip(flip),
.wen(wen),
.wrow(wrow), .wcol(wcol),
.rrow(rrow), .rcol(rcol),
.wdata(wdata),
.rdata(rdata)
);
always
# 5 clk = !clk;
initial begin
integer i = 0, j = 0;
`setup_vcd(display_memory_simple);
flip <= 0;
wrow <= 0;
rrow <= 0;
wcol <= 0;
rcol <= 0;
wdata <= 'h000000;
wen <= 0;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
flip <= 0;
wdata <= 'hffffff;
wcol <= i;
wrow <= j;
wen <= 1;
@(negedge clk);
`assert_eq(rdata, 24'h000000);
wen <= 0;
flip <= 1;
rcol <= i;
rrow <= j;
@(negedge clk);
`assert_eq(rdata, 24'hffffff);
end
end
$finish(0);
flip = 1;
for (i = 0; i < 32; i = i + 1) begin
wdata = 'h111111;
wcol = i;
rcol = i;
wen = 1;
@(negedge clk);
`assert_eq(rdata, 'hffffff);
end
flip = 0;
for (i = 0; i < 32; i = i + 1) begin
wdata = 'h101010;
wcol = i;
rcol = i;
wen = 0;
@(negedge clk);
`assert_eq(rdata, 'h111111);
end
flip = 1;
for (i = 0; i < 32; i = i + 1) begin
wdata = 'h010101;
wcol = i;
rcol = i;
wen = 0;
@(negedge clk);
`assert_eq(rdata, 'hffffff);
end
$finish(0);
end
endmodule | module display_memory_simple; |
reg clk = 0;
reg flip, wen = 0;
reg [2:0] wrow, rrow = 0;
reg [4:0] wcol, rcol = 0;
reg [23:0] wdata = 0;
wire [23:0] rdata;
display_memory #(
.rows(8),
.columns(32)
) u_memory (
.clk(clk),
.flip(flip),
.wen(wen),
.wrow(wrow), .wcol(wcol),
.rrow(rrow), .rcol(rcol),
.wdata(wdata),
.rdata(rdata)
);
always
# 5 clk = !clk;
initial begin
integer i = 0, j = 0;
`setup_vcd(display_memory_simple);
flip <= 0;
wrow <= 0;
rrow <= 0;
wcol <= 0;
rcol <= 0;
wdata <= 'h000000;
wen <= 0;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
flip <= 0;
wdata <= 'hffffff;
wcol <= i;
wrow <= j;
wen <= 1;
@(negedge clk);
`assert_eq(rdata, 24'h000000);
wen <= 0;
flip <= 1;
rcol <= i;
rrow <= j;
@(negedge clk);
`assert_eq(rdata, 24'hffffff);
end
end
$finish(0);
flip = 1;
for (i = 0; i < 32; i = i + 1) begin
wdata = 'h111111;
wcol = i;
rcol = i;
wen = 1;
@(negedge clk);
`assert_eq(rdata, 'hffffff);
end
flip = 0;
for (i = 0; i < 32; i = i + 1) begin
wdata = 'h101010;
wcol = i;
rcol = i;
wen = 0;
@(negedge clk);
`assert_eq(rdata, 'h111111);
end
flip = 1;
for (i = 0; i < 32; i = i + 1) begin
wdata = 'h010101;
wcol = i;
rcol = i;
wen = 0;
@(negedge clk);
`assert_eq(rdata, 'hffffff);
end
$finish(0);
end
endmodule | 0 |
138,438 | data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v | 83,528,847 | pulse_generator_simple.v | v | 60 | 44 | [] | [] | [] | null | line:10: before: "window" | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:22: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:26: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(pulse_generator_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:26: syntax error, unexpected \';\'\n `setup_vcd(pulse_generator_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:31: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:40: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:40: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:41: Define or directive not defined: \'`assert_eq\'\n `assert_eq(select, k);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:41: syntax error, unexpected \',\'\n `assert_eq(select, k);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:46: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:46: syntax error, unexpected \',\'\n `assert_eq(complete, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:47: Define or directive not defined: \'`assert_eq\'\n `assert_eq(i, j); \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:47: syntax error, unexpected \',\'\n `assert_eq(i, j); \n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:51: Define or directive not defined: \'`assert_eq\'\n `assert_eq(select, k);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:51: syntax error, unexpected \',\'\n `assert_eq(select, k);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:53: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:53: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:54: Define or directive not defined: \'`assert_eq\'\n `assert_eq(select, k);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/pulse_generator_simple.v:54: syntax error, unexpected \',\'\n `assert_eq(select, k);\n ^\n%Error: Exiting due to 18 error(s), 1 warning(s)\n' | 302,368 | module | module pulse_generator_simple;
reg clk = 0;
reg rst = 0;
reg go = 0;
wire complete;
wire [$clog2(8) - 1:0] select;
display_driver_pulse_generator #(
.bitwidth(8)
) u_pulse (
.clk(clk),
.rst(rst),
.go(go),
.complete(complete),
.select(select)
);
always
# 5 clk = !clk;
integer i = 0, j = 0, k = 0;
initial begin
`setup_vcd(pulse_generator_simple);
rst <= 0;
go <= 0;
@(posedge clk);
@(negedge clk);
k = 0;
for (j = 256; j > 1; j = j / 2) begin
i = 0;
$display("pulse width halfed to %d", j);
go <= 1;
repeat (j) begin
`assert_eq(complete, 0);
`assert_eq(select, k);
@(negedge clk);
i = i + 1;
end
go <= 0;
`assert_eq(complete, 1);
`assert_eq(i, j);
k = k + 1;
if (k > 7)
k = 0;
`assert_eq(select, k);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(select, k);
end
$finish(0);
end
endmodule | module pulse_generator_simple; |
reg clk = 0;
reg rst = 0;
reg go = 0;
wire complete;
wire [$clog2(8) - 1:0] select;
display_driver_pulse_generator #(
.bitwidth(8)
) u_pulse (
.clk(clk),
.rst(rst),
.go(go),
.complete(complete),
.select(select)
);
always
# 5 clk = !clk;
integer i = 0, j = 0, k = 0;
initial begin
`setup_vcd(pulse_generator_simple);
rst <= 0;
go <= 0;
@(posedge clk);
@(negedge clk);
k = 0;
for (j = 256; j > 1; j = j / 2) begin
i = 0;
$display("pulse width halfed to %d", j);
go <= 1;
repeat (j) begin
`assert_eq(complete, 0);
`assert_eq(select, k);
@(negedge clk);
i = i + 1;
end
go <= 0;
`assert_eq(complete, 1);
`assert_eq(i, j);
k = k + 1;
if (k > 7)
k = 0;
`assert_eq(select, k);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(select, k);
end
$finish(0);
end
endmodule | 0 |
138,439 | data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v | 83,528,847 | rgb_pipe_simple.v | v | 87 | 57 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:5: syntax error, unexpected integer, expecting IDENTIFIER or \'=\' or do or final\n reg integer select = 0;\n ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:25: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:29: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(rgb_pipe_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:29: syntax error, unexpected \';\'\n `setup_vcd(rgb_pipe_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:35: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:43: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:44: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b000);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:44: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b000);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:47: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b001);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:47: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b001);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:51: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:52: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b001);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:52: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b001);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:54: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:55: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b000);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:55: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b000);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:57: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b001);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:57: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b001);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:62: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:63: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b001);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:63: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b001);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:65: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b001);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:65: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b001);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:67: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b001);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:67: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b001);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:69: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:70: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b001);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:70: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b001);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:72: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, 3\'b000);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:72: syntax error, unexpected \',\'\n `assert_eq(rgb, 3\'b000);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:78: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:80: Define or directive not defined: \'`assert_eq\'\n `assert_eq(rgb, ({2\'b00, (i % 2) == 1}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/rgb_pipe_simple.v:80: syntax error, unexpected \',\'\n `assert_eq(rgb, ({2\'b00, (i % 2) == 1}));\n ^\n%Error: Exiting due to 33 error(s), 1 warning(s)\n' | 302,369 | module | module rgb_pipe_simple;
reg clk = 0;
reg integer select = 0;
reg go = 0;
reg [(8 * 3) - 1:0] pixel = {8 * 3{1'b0}};
wire [2:0] rgb;
display_driver_rgb_pipe #(
.pipe_length(2),
.segments(1),
.bitwidth(8)
) u_pipe (
.clk(clk),
.rst(rst),
.go(go),
.select(select[$clog2(8) - 1:0]),
.pixel(pixel),
.rgb(rgb)
);
always
# 5 clk = !clk;
initial begin
integer i = 0;
`setup_vcd(rgb_pipe_simple);
select <= 0;
go <= 0;
pixel <= 24'h000000;
@(posedge clk);
@(negedge clk);
pixel <= 24'h0000ff;
go <= 1;
@(negedge clk);
`assert_eq(rgb, 3'b000);
@(negedge clk);
`assert_eq(rgb, 3'b001);
pixel <= 24'h0000f0;
@(negedge clk);
`assert_eq(rgb, 3'b001);
pixel <= 24'h0000ff;
@(negedge clk);
`assert_eq(rgb, 3'b000);
@(negedge clk);
`assert_eq(rgb, 3'b001);
pixel <= 24'h0000f0;
go <= 0;
@(negedge clk);
`assert_eq(rgb, 3'b001);
@(negedge clk);
`assert_eq(rgb, 3'b001);
@(negedge clk);
`assert_eq(rgb, 3'b001);
go <= 1;
@(negedge clk);
`assert_eq(rgb, 3'b001);
@(negedge clk);
`assert_eq(rgb, 3'b000);
for (i = 0; i < (8 * 2); i = i + 1) begin
select <= i / 2;
pixel <= {16'h0000, {8{(i % 2) == 1}}};
@(negedge clk);
@(negedge clk);
`assert_eq(rgb, ({2'b00, (i % 2) == 1}));
end
$finish(0);
end
endmodule | module rgb_pipe_simple; |
reg clk = 0;
reg integer select = 0;
reg go = 0;
reg [(8 * 3) - 1:0] pixel = {8 * 3{1'b0}};
wire [2:0] rgb;
display_driver_rgb_pipe #(
.pipe_length(2),
.segments(1),
.bitwidth(8)
) u_pipe (
.clk(clk),
.rst(rst),
.go(go),
.select(select[$clog2(8) - 1:0]),
.pixel(pixel),
.rgb(rgb)
);
always
# 5 clk = !clk;
initial begin
integer i = 0;
`setup_vcd(rgb_pipe_simple);
select <= 0;
go <= 0;
pixel <= 24'h000000;
@(posedge clk);
@(negedge clk);
pixel <= 24'h0000ff;
go <= 1;
@(negedge clk);
`assert_eq(rgb, 3'b000);
@(negedge clk);
`assert_eq(rgb, 3'b001);
pixel <= 24'h0000f0;
@(negedge clk);
`assert_eq(rgb, 3'b001);
pixel <= 24'h0000ff;
@(negedge clk);
`assert_eq(rgb, 3'b000);
@(negedge clk);
`assert_eq(rgb, 3'b001);
pixel <= 24'h0000f0;
go <= 0;
@(negedge clk);
`assert_eq(rgb, 3'b001);
@(negedge clk);
`assert_eq(rgb, 3'b001);
@(negedge clk);
`assert_eq(rgb, 3'b001);
go <= 1;
@(negedge clk);
`assert_eq(rgb, 3'b001);
@(negedge clk);
`assert_eq(rgb, 3'b000);
for (i = 0; i < (8 * 2); i = i + 1) begin
select <= i / 2;
pixel <= {16'h0000, {8{(i % 2) == 1}}};
@(negedge clk);
@(negedge clk);
`assert_eq(rgb, ({2'b00, (i % 2) == 1}));
end
$finish(0);
end
endmodule | 0 |
138,440 | data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v | 83,528,847 | row_loader_simple.v | v | 104 | 65 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:26: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:30: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(row_loader_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:30: syntax error, unexpected \';\'\n `setup_vcd(row_loader_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:35: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:41: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:41: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:42: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:42: syntax error, unexpected \',\'\n `assert_eq(column, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:43: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pipe, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:43: syntax error, unexpected \',\'\n `assert_eq(pipe, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:44: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:44: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:48: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:48: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:49: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:49: syntax error, unexpected \',\'\n `assert_eq(column, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:50: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pipe, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:50: syntax error, unexpected \',\'\n `assert_eq(pipe, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:51: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:51: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:54: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:54: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:55: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, 2);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:55: syntax error, unexpected \',\'\n `assert_eq(column, 2);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:56: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pipe, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:56: syntax error, unexpected \',\'\n `assert_eq(pipe, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:57: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:57: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:61: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:63: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:63: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:64: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, 3);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:64: syntax error, unexpected \',\'\n `assert_eq(column, 3);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:65: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pipe, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:65: syntax error, unexpected \',\'\n `assert_eq(pipe, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:66: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:66: syntax error, unexpected \',\'\n `assert_eq(oclk, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:70: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:72: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:72: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:73: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, 3);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:73: syntax error, unexpected \',\'\n `assert_eq(column, 3);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:74: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pipe, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:74: syntax error, unexpected \',\'\n `assert_eq(pipe, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:75: Define or directive not defined: \'`assert_eq\'\n `assert_eq(oclk, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:75: syntax error, unexpected \',\'\n `assert_eq(oclk, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:81: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:82: Define or directive not defined: \'`assert_eq\'\n `assert_eq(complete, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:82: syntax error, unexpected \',\'\n `assert_eq(complete, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/row_loader_simple.v:83: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, i[$clog2(32) - 1:0]);\n ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,370 | module | module row_loader_simple;
reg clk = 0, rst = 0;
reg load = 0;
wire complete;
wire oclk;
wire pipe;
wire [$clog2(32) - 1:0] column;
display_driver_row_loader #(
.pipe_length(2),
.columns(32)
) u_loader (
.clk(clk),
.rst(rst),
.load(load),
.complete(complete),
.oclk(oclk),
.pipe(pipe),
.column(column[$clog2(32) - 1:0])
);
always
# 5 clk = !clk;
initial begin
integer i = 0;
`setup_vcd(row_loader_simple);
rst <= 0;
load <= 0;
@(posedge clk);
@(negedge clk);
load <= 1;
`assert_eq(complete, 0);
`assert_eq(column, 0);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 1);
`assert_eq(pipe, 1);
`assert_eq(oclk, 0);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 2);
`assert_eq(pipe, 1);
`assert_eq(oclk, 0);
$display("assertion, col's 0 and 1 are in the 2 length pipe");
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 3);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
$display("assertion, col 2 in pipe, ");
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 3);
`assert_eq(pipe, 1);
`assert_eq(oclk, 1);
i = 3;
repeat (31) begin
i = i + 1;
$display("assertion, checking cycle depth %d", i);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, i[$clog2(32) - 1:0]);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, i[$clog2(32) - 1:0]);
`assert_eq(pipe, 1);
`assert_eq(oclk, 1);
end
@(negedge clk);
`assert_eq(complete, 1);
`assert_eq(column, 0);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
# 100
$finish(0);
end
endmodule | module row_loader_simple; |
reg clk = 0, rst = 0;
reg load = 0;
wire complete;
wire oclk;
wire pipe;
wire [$clog2(32) - 1:0] column;
display_driver_row_loader #(
.pipe_length(2),
.columns(32)
) u_loader (
.clk(clk),
.rst(rst),
.load(load),
.complete(complete),
.oclk(oclk),
.pipe(pipe),
.column(column[$clog2(32) - 1:0])
);
always
# 5 clk = !clk;
initial begin
integer i = 0;
`setup_vcd(row_loader_simple);
rst <= 0;
load <= 0;
@(posedge clk);
@(negedge clk);
load <= 1;
`assert_eq(complete, 0);
`assert_eq(column, 0);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 1);
`assert_eq(pipe, 1);
`assert_eq(oclk, 0);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 2);
`assert_eq(pipe, 1);
`assert_eq(oclk, 0);
$display("assertion, col's 0 and 1 are in the 2 length pipe");
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 3);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
$display("assertion, col 2 in pipe, ");
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, 3);
`assert_eq(pipe, 1);
`assert_eq(oclk, 1);
i = 3;
repeat (31) begin
i = i + 1;
$display("assertion, checking cycle depth %d", i);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, i[$clog2(32) - 1:0]);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
@(negedge clk);
`assert_eq(complete, 0);
`assert_eq(column, i[$clog2(32) - 1:0]);
`assert_eq(pipe, 1);
`assert_eq(oclk, 1);
end
@(negedge clk);
`assert_eq(complete, 1);
`assert_eq(column, 0);
`assert_eq(pipe, 0);
`assert_eq(oclk, 0);
# 100
$finish(0);
end
endmodule | 0 |
138,441 | data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v | 83,528,847 | spi_controller_simple.v | v | 275 | 116 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:36: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:45: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk <= 1;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:46: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk <= 0;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:54: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(spi_controller_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:54: syntax error, unexpected \';\'\n `setup_vcd(spi_controller_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:59: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:61: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:65: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:67: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:75: syntax error, unexpected \'@\'\n @(negedge clk); \n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:77: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:77: syntax error, unexpected \',\'\n `assert_eq(wen, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:78: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pixel, ({16\'hffff, i[7:0]}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:78: syntax error, unexpected \',\'\n `assert_eq(pixel, ({16\'hffff, i[7:0]}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:79: Define or directive not defined: \'`assert_eq\'\n `assert_eq(row, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:79: syntax error, unexpected \',\'\n `assert_eq(row, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:80: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, i);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:80: syntax error, unexpected \',\'\n `assert_eq(column, i);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:84: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:90: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:97: syntax error, unexpected \'@\'\n @(negedge clk); \n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:99: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:99: syntax error, unexpected \',\'\n `assert_eq(wen, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:100: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pixel, ({16\'h00ed, i[7:0]}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:100: syntax error, unexpected \',\'\n `assert_eq(pixel, ({16\'h00ed, i[7:0]}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:101: Define or directive not defined: \'`assert_eq\'\n `assert_eq(row, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:101: syntax error, unexpected \',\'\n `assert_eq(row, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:102: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, i);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:102: syntax error, unexpected \',\'\n `assert_eq(column, i);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:106: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:119: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:121: Define or directive not defined: \'`assert_eq\'\n `assert_eq(wen, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:121: syntax error, unexpected \',\'\n `assert_eq(wen, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:122: Define or directive not defined: \'`assert_eq\'\n `assert_eq(pixel, ({j[7:0], 8\'hed, i[7:0]}));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:122: syntax error, unexpected \',\'\n `assert_eq(pixel, ({j[7:0], 8\'hed, i[7:0]}));\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:123: Define or directive not defined: \'`assert_eq\'\n `assert_eq(row, j);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:123: syntax error, unexpected \',\'\n `assert_eq(row, j);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:124: Define or directive not defined: \'`assert_eq\'\n `assert_eq(column, i);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:124: syntax error, unexpected \',\'\n `assert_eq(column, i);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:127: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:140: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:142: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:144: syntax error, unexpected \'@\'\n @(negedge clk); `assert_eq(loaded, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:144: Define or directive not defined: \'`assert_eq\'\n @(negedge clk); `assert_eq(loaded, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:144: syntax error, unexpected \',\'\n @(negedge clk); `assert_eq(loaded, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:145: Define or directive not defined: \'`assert_eq\'\n @(negedge clk); `assert_eq(loaded, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:145: syntax error, unexpected \',\'\n @(negedge clk); `assert_eq(loaded, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:147: syntax error, unexpected \'@\'\n @(negedge clk); `assert_eq(loaded, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:147: Define or directive not defined: \'`assert_eq\'\n @(negedge clk); `assert_eq(loaded, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_controller_simple.v:147: syntax error, unexpected \',\'\n @(negedge clk); `assert_eq(loaded, 0);\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,371 | module | module spi_controller_simple;
reg clk = 0, rst = 0;
reg sclk = 0, ss = 0, mosi = 0;
wire miso;
wire [2:0] row;
wire [4:0] column;
wire [23:0] pixel;
wire wen;
reg ready = 0;
wire loaded;
spi_controller #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(8)
) u_controller (
.clk(clk),
.rst(rst),
.sclk(sclk),
.ss(ss),
.mosi(mosi),
.miso(miso),
.wrow(row),
.wcol(column),
.wen(wen),
.wdata(pixel),
.ready(ready),
.loaded(loaded)
);
always
# 5 clk = !clk;
task clkword;
input [7:0] x;
integer i;
begin
for (i = 0; i < 8; i = i + 1) begin
mosi <= x[7 - i];
@(negedge clk); @(negedge clk); sclk <= 1;
@(negedge clk); @(negedge clk); sclk <= 0;
end
end
endtask
initial begin
integer i, j, z, x, y;
`setup_vcd(spi_controller_simple);
mosi <= 0; sclk <= 0; ss <= 0;
clk = 0; rst = 1;
ready <= 0;
@(negedge clk);
rst = 0;
@(negedge clk);
ready <= 1;
@(negedge clk);
ss <= 1;
@(negedge clk);
clkword(8'hf0);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'hff);
clkword(8'hff);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
ss <= 1;
@(negedge clk);
clkword(8'hf1);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'h00);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'h00ed, i[7:0]}));
`assert_eq(row, 1);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
for (j = 2; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword(j[7:0]);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({j[7:0], 8'hed, i[7:0]}));
`assert_eq(row, j);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
end
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 1);
@(negedge clk); `assert_eq(loaded, 0);
ready <= 0;
@(negedge clk); `assert_eq(loaded, 0);
repeat (2) begin
@(negedge clk);
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 0;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword(j[7:0]);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 0);
end
ss <= 0;
@(negedge clk);
end
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 0);
@(negedge clk); `assert_eq(loaded, 0);
end
@(negedge clk);
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 1;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword(j[7:0]);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({j[7:0], 8'hed, i[7:0]}));
`assert_eq(row, j);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
end
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 1);
@(negedge clk); `assert_eq(loaded, 0);
for (y = 0; y < 3; y = y + 1) begin
for (z = 0; z < 256; z = z + 1) begin
@(negedge clk);
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 1;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword((y == 0) ? z[7:0] : 8'h00);
clkword((y == 1) ? z[7:0] : 8'h00);
clkword((y == 2) ? z[7:0] : 8'h00);
@(negedge clk);
$display("Writing colour %1d/%3d to row %2d[%2d], col %2d[%2d]. pixel = %h", y, z, row, j, column, i, pixel);
`assert_eq(wen, 1);
`assert_eq(pixel, ({
(y == 0) ? z[7:0] : 8'h00,
(y == 1) ? z[7:0] : 8'h00,
(y == 2) ? z[7:0] : 8'h00
}));
`assert_eq(row, j);
`assert_eq(column, i);
@(negedge clk);
`assert_eq(wen, 0);
end
ss <= 0;
@(negedge clk);
`assert_eq(wen, 0);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
end
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 1);
@(negedge clk); `assert_eq(loaded, 0);
end
end
# 100
ss <= 0;
$finish(0);
end
endmodule | module spi_controller_simple; |
reg clk = 0, rst = 0;
reg sclk = 0, ss = 0, mosi = 0;
wire miso;
wire [2:0] row;
wire [4:0] column;
wire [23:0] pixel;
wire wen;
reg ready = 0;
wire loaded;
spi_controller #(
.segments(1),
.rows(8),
.columns(32),
.bitwidth(8)
) u_controller (
.clk(clk),
.rst(rst),
.sclk(sclk),
.ss(ss),
.mosi(mosi),
.miso(miso),
.wrow(row),
.wcol(column),
.wen(wen),
.wdata(pixel),
.ready(ready),
.loaded(loaded)
);
always
# 5 clk = !clk;
task clkword;
input [7:0] x;
integer i;
begin
for (i = 0; i < 8; i = i + 1) begin
mosi <= x[7 - i];
@(negedge clk); @(negedge clk); sclk <= 1;
@(negedge clk); @(negedge clk); sclk <= 0;
end
end
endtask
initial begin
integer i, j, z, x, y;
`setup_vcd(spi_controller_simple);
mosi <= 0; sclk <= 0; ss <= 0;
clk = 0; rst = 1;
ready <= 0;
@(negedge clk);
rst = 0;
@(negedge clk);
ready <= 1;
@(negedge clk);
ss <= 1;
@(negedge clk);
clkword(8'hf0);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'hff);
clkword(8'hff);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'hffff, i[7:0]}));
`assert_eq(row, 0);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
ss <= 1;
@(negedge clk);
clkword(8'hf1);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'h00);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({16'h00ed, i[7:0]}));
`assert_eq(row, 1);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
for (j = 2; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword(j[7:0]);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({j[7:0], 8'hed, i[7:0]}));
`assert_eq(row, j);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
end
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 1);
@(negedge clk); `assert_eq(loaded, 0);
ready <= 0;
@(negedge clk); `assert_eq(loaded, 0);
repeat (2) begin
@(negedge clk);
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 0;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword(j[7:0]);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 0);
end
ss <= 0;
@(negedge clk);
end
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 0);
@(negedge clk); `assert_eq(loaded, 0);
end
@(negedge clk);
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 1;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword(j[7:0]);
clkword(8'hed);
clkword(i[7:0]);
@(negedge clk);
`assert_eq(wen, 1);
`assert_eq(pixel, ({j[7:0], 8'hed, i[7:0]}));
`assert_eq(row, j);
`assert_eq(column, i);
end
ss <= 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
end
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 1);
@(negedge clk); `assert_eq(loaded, 0);
for (y = 0; y < 3; y = y + 1) begin
for (z = 0; z < 256; z = z + 1) begin
@(negedge clk);
@(negedge clk);
`assert_eq(loaded, 0);
ready <= 1;
@(negedge clk);
for (j = 0; j < 8; j = j + 1) begin
ss <= 1;
clkword({4'hf, j[3:0]});
for (i = 0; i < 32; i = i + 1) begin
clkword((y == 0) ? z[7:0] : 8'h00);
clkword((y == 1) ? z[7:0] : 8'h00);
clkword((y == 2) ? z[7:0] : 8'h00);
@(negedge clk);
$display("Writing colour %1d/%3d to row %2d[%2d], col %2d[%2d]. pixel = %h", y, z, row, j, column, i, pixel);
`assert_eq(wen, 1);
`assert_eq(pixel, ({
(y == 0) ? z[7:0] : 8'h00,
(y == 1) ? z[7:0] : 8'h00,
(y == 2) ? z[7:0] : 8'h00
}));
`assert_eq(row, j);
`assert_eq(column, i);
@(negedge clk);
`assert_eq(wen, 0);
end
ss <= 0;
@(negedge clk);
`assert_eq(wen, 0);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
end
ss <= 1;
@(negedge clk);
clkword(8'h10);
@(negedge clk);
ss <= 0;
@(negedge clk); `assert_eq(loaded, 1);
@(negedge clk); `assert_eq(loaded, 0);
end
end
# 100
ss <= 0;
$finish(0);
end
endmodule | 0 |
138,442 | data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v | 83,528,847 | spi_slave_simple.v | v | 125 | 71 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:23: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:29: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(spi_slave_simple);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:29: syntax error, unexpected \';\'\n `setup_vcd(spi_slave_simple);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:35: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:39: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:43: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk = 1;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:44: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk = 0;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:47: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:47: syntax error, unexpected \',\'\n `assert_eq(valid, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:48: Define or directive not defined: \'`assert_eq\'\n `assert_eq(data, \'hff);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:48: syntax error, unexpected \',\'\n `assert_eq(data, \'hff);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:51: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:51: syntax error, unexpected \',\'\n `assert_eq(valid, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:54: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:55: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:55: syntax error, unexpected \',\'\n `assert_eq(valid, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:63: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:69: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk = 1;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:71: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk = 0;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:75: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:75: syntax error, unexpected \',\'\n `assert_eq(valid, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:77: Define or directive not defined: \'`assert_eq\'\n `assert_eq(data, test_data[7:0]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:77: syntax error, unexpected \',\'\n `assert_eq(data, test_data[7:0]);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:79: Define or directive not defined: \'`assert_eq\'\n `assert_eq(read_data, i - 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:79: syntax error, unexpected \',\'\n `assert_eq(read_data, i - 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:83: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:83: syntax error, unexpected \',\'\n `assert_eq(valid, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:86: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:87: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:87: syntax error, unexpected \',\'\n `assert_eq(valid, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:91: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:97: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk = 1;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:99: syntax error, unexpected \'@\'\n @(negedge clk); @(negedge clk); sclk = 0;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:103: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:103: syntax error, unexpected \',\'\n `assert_eq(valid, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:106: Define or directive not defined: \'`assert_eq\'\n `assert_eq(data, test_data[7:0]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:106: syntax error, unexpected \',\'\n `assert_eq(data, test_data[7:0]);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:108: Define or directive not defined: \'`assert_eq\'\n `assert_eq(read_data, i - 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:108: syntax error, unexpected \',\'\n `assert_eq(read_data, i - 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:112: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:116: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:117: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/spi_slave_simple.v:117: syntax error, unexpected \',\'\n `assert_eq(valid, 0);\n ^\n%Error: Exiting due to 43 error(s), 1 warning(s)\n' | 302,372 | module | module spi_slave_simple;
reg clk = 0, sclk = 0, rst = 0, ss = 1;
reg mosi = 0;
wire miso;
wire [7:0] data;
wire valid;
spi_slave u_spi_slave (
.clk(clk),
.rst(rst),
.sclk(sclk),
.ss(ss),
.mosi(mosi),
.miso(miso),
.data(data),
.valid(valid)
);
always
# 5 clk = !clk;
reg [7:0] test_data = 0;
reg [7:0] read_data = 0;
integer i, c, j;
initial begin
`setup_vcd(spi_slave_simple);
mosi = 0;
sclk = 0;
ss = 1;
@(negedge clk);
ss = 1;
@(negedge clk);
mosi = 1;
repeat(8) begin
@(negedge clk); @(negedge clk); sclk = 1;
@(negedge clk); @(negedge clk); sclk = 0;
end
`assert_eq(valid, 1);
`assert_eq(data, 'hff);
@(negedge clk);
`assert_eq(valid, 0);
ss = 0;
@(negedge clk);
`assert_eq(valid, 0);
@(negedge clk);
@(negedge clk);
@(negedge clk);
ss = 1;
@(negedge clk);
for (i = 0; i < 4; i = i + 1) begin
test_data = i;
for (j = 0; j < 8; j = j + 1) begin
mosi = test_data[7 - j];
@(negedge clk); @(negedge clk); sclk = 1;
read_data = {read_data[6:0], miso};
@(negedge clk); @(negedge clk); sclk = 0;
end
`assert_eq(valid, 1);
$display("got %h, expected %h", data, test_data[7:0]);
`assert_eq(data, test_data[7:0]);
if (i != 0)
`assert_eq(read_data, i - 1);
end
@(negedge clk);
`assert_eq(valid, 0);
ss = 0;
@(negedge clk);
`assert_eq(valid, 0);
ss = 1;
@(negedge clk);
for (i = 0; i < 257; i = i + 1) begin
test_data = i;
for (j = 0; j < 8; j = j + 1) begin
mosi = test_data[7 - j];
@(negedge clk); @(negedge clk); sclk = 1;
read_data = {read_data[6:0], miso};
@(negedge clk); @(negedge clk); sclk = 0;
end
`assert_eq(valid, 1);
$display("got %h, expected %h", data, test_data[7:0]);
$display("read %h, expected %h", read_data, i - 1);
`assert_eq(data, test_data[7:0]);
if (i != 0)
`assert_eq(read_data, i - 1);
for (j = 0; j < 512; j = j + 1) begin
@(negedge clk);
end
end
@(negedge clk);
`assert_eq(valid, 0);
ss = 0;
$finish(0);
end
endmodule | module spi_slave_simple; |
reg clk = 0, sclk = 0, rst = 0, ss = 1;
reg mosi = 0;
wire miso;
wire [7:0] data;
wire valid;
spi_slave u_spi_slave (
.clk(clk),
.rst(rst),
.sclk(sclk),
.ss(ss),
.mosi(mosi),
.miso(miso),
.data(data),
.valid(valid)
);
always
# 5 clk = !clk;
reg [7:0] test_data = 0;
reg [7:0] read_data = 0;
integer i, c, j;
initial begin
`setup_vcd(spi_slave_simple);
mosi = 0;
sclk = 0;
ss = 1;
@(negedge clk);
ss = 1;
@(negedge clk);
mosi = 1;
repeat(8) begin
@(negedge clk); @(negedge clk); sclk = 1;
@(negedge clk); @(negedge clk); sclk = 0;
end
`assert_eq(valid, 1);
`assert_eq(data, 'hff);
@(negedge clk);
`assert_eq(valid, 0);
ss = 0;
@(negedge clk);
`assert_eq(valid, 0);
@(negedge clk);
@(negedge clk);
@(negedge clk);
ss = 1;
@(negedge clk);
for (i = 0; i < 4; i = i + 1) begin
test_data = i;
for (j = 0; j < 8; j = j + 1) begin
mosi = test_data[7 - j];
@(negedge clk); @(negedge clk); sclk = 1;
read_data = {read_data[6:0], miso};
@(negedge clk); @(negedge clk); sclk = 0;
end
`assert_eq(valid, 1);
$display("got %h, expected %h", data, test_data[7:0]);
`assert_eq(data, test_data[7:0]);
if (i != 0)
`assert_eq(read_data, i - 1);
end
@(negedge clk);
`assert_eq(valid, 0);
ss = 0;
@(negedge clk);
`assert_eq(valid, 0);
ss = 1;
@(negedge clk);
for (i = 0; i < 257; i = i + 1) begin
test_data = i;
for (j = 0; j < 8; j = j + 1) begin
mosi = test_data[7 - j];
@(negedge clk); @(negedge clk); sclk = 1;
read_data = {read_data[6:0], miso};
@(negedge clk); @(negedge clk); sclk = 0;
end
`assert_eq(valid, 1);
$display("got %h, expected %h", data, test_data[7:0]);
$display("read %h, expected %h", read_data, i - 1);
`assert_eq(data, test_data[7:0]);
if (i != 0)
`assert_eq(read_data, i - 1);
for (j = 0; j < 512; j = j + 1) begin
@(negedge clk);
end
end
@(negedge clk);
`assert_eq(valid, 0);
ss = 0;
$finish(0);
end
endmodule | 0 |
138,443 | data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v | 83,528,847 | top_load_spi.v | v | 94 | 68 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:20: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:29: syntax error, unexpected \'@\'\n @(posedge clk); mosi <= x[i];\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:30: syntax error, unexpected \'@\'\n @(negedge clk); sclk <= 1;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:31: syntax error, unexpected \'@\'\n @(posedge clk); sclk <= 0;\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:32: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:39: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(top_load_spi);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:39: syntax error, unexpected \';\'\n `setup_vcd(top_load_spi);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:44: Unsupported: Ignoring delay on this delayed statement.\n # 2000000\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:52: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:56: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:65: Unsupported: Ignoring delay on this delayed statement.\n # 20000000\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:74: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:78: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_load_spi.v:87: Unsupported: Ignoring delay on this delayed statement.\n # 2000000\n ^\n%Error: Exiting due to 11 error(s), 4 warning(s)\n' | 302,373 | module | module top_load_spi;
reg clk = 0;
reg sclk = 0;
reg ss = 1;
reg mosi = 0;
wire miso;
top u_top (
.clk(clk),
.spi_sclk(sclk),
.spi_ss(ss),
.spi_mosi(mosi),
.spi_miso(miso)
);
always
# 5 clk = !clk;
task clkword;
input [7:0] x;
integer i;
begin
$display("[SPI] write 0x%h to mosi", x);
for (i = 0; i < 8; i = i + 1) begin
sclk <= 0;
@(posedge clk); mosi <= x[i];
@(negedge clk); sclk <= 1;
@(posedge clk); sclk <= 0;
@(posedge clk);
end
end
endtask
integer i = 0;
initial begin
`setup_vcd(top_load_spi);
# 2000000
ss <= 0;
clkword(8'hf0);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'hff);
clkword(i[7:0]);
clkword(8'hff);
@(posedge clk);
end
ss <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
ss <= 0;
clkword(8'h10);
ss <= 1;
# 20000000
ss <= 1;
ss <= 0;
clkword(8'hf0);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'hff);
clkword(i[7:0]);
clkword(8'hff);
@(posedge clk);
end
ss <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
ss <= 0;
clkword(8'h10);
ss <= 1;
# 2000000
ss <= 1;
$finish(0);
end
endmodule | module top_load_spi; |
reg clk = 0;
reg sclk = 0;
reg ss = 1;
reg mosi = 0;
wire miso;
top u_top (
.clk(clk),
.spi_sclk(sclk),
.spi_ss(ss),
.spi_mosi(mosi),
.spi_miso(miso)
);
always
# 5 clk = !clk;
task clkword;
input [7:0] x;
integer i;
begin
$display("[SPI] write 0x%h to mosi", x);
for (i = 0; i < 8; i = i + 1) begin
sclk <= 0;
@(posedge clk); mosi <= x[i];
@(negedge clk); sclk <= 1;
@(posedge clk); sclk <= 0;
@(posedge clk);
end
end
endtask
integer i = 0;
initial begin
`setup_vcd(top_load_spi);
# 2000000
ss <= 0;
clkword(8'hf0);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'hff);
clkword(i[7:0]);
clkword(8'hff);
@(posedge clk);
end
ss <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
ss <= 0;
clkword(8'h10);
ss <= 1;
# 20000000
ss <= 1;
ss <= 0;
clkword(8'hf0);
for (i = 0; i < 32; i = i + 1) begin
clkword(8'hff);
clkword(i[7:0]);
clkword(8'hff);
@(posedge clk);
end
ss <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
ss <= 0;
clkword(8'h10);
ss <= 1;
# 2000000
ss <= 1;
$finish(0);
end
endmodule | 0 |
138,444 | data/full_repos/permissive/83528847/display-controller/tests/top_run.v | 83,528,847 | top_run.v | v | 33 | 30 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/tests/top_run.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_run.v:17: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(top_run);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/tests/top_run.v:17: syntax error, unexpected \';\'\n `setup_vcd(top_run);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_run.v:19: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_run.v:20: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_run.v:26: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/tests/top_run.v:27: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 302,374 | module | module top_run;
reg clk = 0;
reg rst = 1;
top u_top (
.clk(clk),
.rst(rst)
);
initial begin
`setup_vcd(top_run);
repeat(32) begin
# 5 clk = !clk;
# 5 clk = !clk;
rst <= 1;
end
rst <= 0;
repeat(500000) begin
# 5 clk = !clk;
# 5 clk = !clk;
end
$finish(0);
end
endmodule | module top_run; |
reg clk = 0;
reg rst = 1;
top u_top (
.clk(clk),
.rst(rst)
);
initial begin
`setup_vcd(top_run);
repeat(32) begin
# 5 clk = !clk;
# 5 clk = !clk;
rst <= 1;
end
rst <= 0;
repeat(500000) begin
# 5 clk = !clk;
# 5 clk = !clk;
end
$finish(0);
end
endmodule | 0 |
138,445 | data/full_repos/permissive/83528847/display-controller/uart/uart_rx.v | 83,528,847 | uart_rx.v | v | 100 | 77 | [] | [] | [] | [(16, 99)] | null | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/uart/uart_rx.v:69: Extracting 31 bits from only 6 bit number\n : ... In instance uart_rx\n rxi_buf[0], cbit[31:1], baud_counter,\n ^\n%Warning-SELRANGE: data/full_repos/permissive/83528847/display-controller/uart/uart_rx.v:69: Selection index out of range: 31:1 outside 5:0\n : ... In instance uart_rx\n rxi_buf[0], cbit[31:1], baud_counter,\n ^\n ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83528847/display-controller/uart/uart_rx.v:75: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'cbit\' generates 6 bits.\n : ... In instance uart_rx\n if (cbit == ((_framelen) * 2)) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83528847/display-controller/uart/uart_rx.v:60: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'baud_counter\' generates 5 bits.\n : ... In instance uart_rx\n if (baud_counter == divisor - 1) begin\n ^~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 302,375 | module | module uart_rx(clk, rst, rxi, data, valid);
parameter integer bitwidth = 8;
parameter integer divisor = 32;
parameter integer startbits = 1;
parameter integer stopbits = 1;
parameter integer _framelen = bitwidth + startbits + stopbits;
input wire clk, rst;
input wire rxi;
reg [_framelen - 1:0] sdata = {_framelen{1'b0}};
output reg valid = 0;
output wire [bitwidth - 1:0] data;
assign data = sdata[_framelen - stopbits - 1: startbits];
reg [1:0] rxi_buf = 2'b11;
reg [$clog2(divisor) - 1:0] baud_counter = 0;
reg [$clog2(_framelen * 2):0] cbit = 0;
always @(posedge clk) begin
if (rst == 1) begin
rxi_buf <= 2'b11;
baud_counter <= 0;
sdata <= {_framelen{1'b0}};
valid <= 0;
cbit <= 0;
end else begin
rxi_buf <= {rxi_buf[0], rxi};
valid <= 0;
if (cbit == 0 && rxi_buf == 2'b10) begin
cbit <= cbit + 1;
baud_counter <= 2;
end else if (cbit != 0) begin
baud_counter <= baud_counter + 1;
if (baud_counter == divisor - 1) begin
baud_counter <= 0;
cbit <= cbit + 1;
if (cbit[0] == 1) begin
`ifndef SYNTHESIS
$display("sample bit %b here, cbit %d, b %d, %b|%h|%b",
rxi_buf[0], cbit[31:1], baud_counter,
rxi_buf[0], sdata[_framelen - 1:2], sdata[0]);
`endif
sdata <= {rxi_buf[0], sdata[_framelen - 1:1]};
end else begin
if (cbit == ((_framelen) * 2)) begin
cbit <= 0;
valid <= 1;
`ifndef SYNTHESIS
$display("valid here, %b|%h|%b",
sdata[_framelen - 1],
sdata[_framelen - 2:1],
sdata[0]);
`endif
end
end
end
if (cbit == 1 && rxi_buf[0] == 1) begin
`ifndef SYNTHESIS
$display("stray pulse detected");
`endif
cbit <= 0;
end
end
end
end
endmodule | module uart_rx(clk, rst, rxi, data, valid); |
parameter integer bitwidth = 8;
parameter integer divisor = 32;
parameter integer startbits = 1;
parameter integer stopbits = 1;
parameter integer _framelen = bitwidth + startbits + stopbits;
input wire clk, rst;
input wire rxi;
reg [_framelen - 1:0] sdata = {_framelen{1'b0}};
output reg valid = 0;
output wire [bitwidth - 1:0] data;
assign data = sdata[_framelen - stopbits - 1: startbits];
reg [1:0] rxi_buf = 2'b11;
reg [$clog2(divisor) - 1:0] baud_counter = 0;
reg [$clog2(_framelen * 2):0] cbit = 0;
always @(posedge clk) begin
if (rst == 1) begin
rxi_buf <= 2'b11;
baud_counter <= 0;
sdata <= {_framelen{1'b0}};
valid <= 0;
cbit <= 0;
end else begin
rxi_buf <= {rxi_buf[0], rxi};
valid <= 0;
if (cbit == 0 && rxi_buf == 2'b10) begin
cbit <= cbit + 1;
baud_counter <= 2;
end else if (cbit != 0) begin
baud_counter <= baud_counter + 1;
if (baud_counter == divisor - 1) begin
baud_counter <= 0;
cbit <= cbit + 1;
if (cbit[0] == 1) begin
`ifndef SYNTHESIS
$display("sample bit %b here, cbit %d, b %d, %b|%h|%b",
rxi_buf[0], cbit[31:1], baud_counter,
rxi_buf[0], sdata[_framelen - 1:2], sdata[0]);
`endif
sdata <= {rxi_buf[0], sdata[_framelen - 1:1]};
end else begin
if (cbit == ((_framelen) * 2)) begin
cbit <= 0;
valid <= 1;
`ifndef SYNTHESIS
$display("valid here, %b|%h|%b",
sdata[_framelen - 1],
sdata[_framelen - 2:1],
sdata[0]);
`endif
end
end
end
if (cbit == 1 && rxi_buf[0] == 1) begin
`ifndef SYNTHESIS
$display("stray pulse detected");
`endif
cbit <= 0;
end
end
end
end
endmodule | 0 |
138,446 | data/full_repos/permissive/83528847/display-controller/uart/uart_tx.v | 83,528,847 | uart_tx.v | v | 69 | 78 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83528847/display-controller/uart/uart_tx.v:27: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n : ... In instance uart_tx\n reg [_framelen - 2:0] sdata = {_framelen{1\'b0}};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83528847/display-controller/uart/uart_tx.v:35: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n : ... In instance uart_tx\n sdata <= {_framelen{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83528847/display-controller/uart/uart_tx.v:49: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'cbit\' generates 5 bits.\n : ... In instance uart_tx\n if (cbit == _framelen) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83528847/display-controller/uart/uart_tx.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'baud_counter\' generates 5 bits.\n : ... In instance uart_tx\n if (baud_counter == divisor - 1) begin\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 302,376 | module | module uart_tx(clk, rst, txo, data, valid);
parameter integer bitwidth = 8;
parameter integer divisor = 32;
parameter integer startbits = 1;
parameter integer stopbits = 1;
parameter integer _framelen = bitwidth + startbits + stopbits;
input wire clk, rst;
output reg txo = 1;
input wire [bitwidth - 1:0] data;
input wire valid;
reg [_framelen - 2:0] sdata = {_framelen{1'b0}};
reg [$clog2(divisor) - 1:0] baud_counter = 0;
reg [$clog2(_framelen):0] cbit = 0;
always @(posedge clk) begin
if (rst == 1) begin
baud_counter <= 0;
cbit <= 0;
sdata <= {_framelen{1'b0}};
txo <= 1;
end else begin
if (cbit != 0) begin
baud_counter <= baud_counter + 1;
if (baud_counter == divisor - 1) begin
sdata <= {1'b1, sdata[_framelen - 2:1]};
txo <= sdata[0];
baud_counter <= 0;
cbit <= cbit + 1;
if (cbit == _framelen) begin
cbit <= 0;
end
end
end else begin
txo <= 1;
if (valid == 1) begin
baud_counter <= 0;
cbit <= 1;
sdata <= {{stopbits{1'b1}}, data, {startbits - 1{1'b0}}};
txo <= 0;
end
end
end
end
endmodule | module uart_tx(clk, rst, txo, data, valid); |
parameter integer bitwidth = 8;
parameter integer divisor = 32;
parameter integer startbits = 1;
parameter integer stopbits = 1;
parameter integer _framelen = bitwidth + startbits + stopbits;
input wire clk, rst;
output reg txo = 1;
input wire [bitwidth - 1:0] data;
input wire valid;
reg [_framelen - 2:0] sdata = {_framelen{1'b0}};
reg [$clog2(divisor) - 1:0] baud_counter = 0;
reg [$clog2(_framelen):0] cbit = 0;
always @(posedge clk) begin
if (rst == 1) begin
baud_counter <= 0;
cbit <= 0;
sdata <= {_framelen{1'b0}};
txo <= 1;
end else begin
if (cbit != 0) begin
baud_counter <= baud_counter + 1;
if (baud_counter == divisor - 1) begin
sdata <= {1'b1, sdata[_framelen - 2:1]};
txo <= sdata[0];
baud_counter <= 0;
cbit <= cbit + 1;
if (cbit == _framelen) begin
cbit <= 0;
end
end
end else begin
txo <= 1;
if (valid == 1) begin
baud_counter <= 0;
cbit <= 1;
sdata <= {{stopbits{1'b1}}, data, {startbits - 1{1'b0}}};
txo <= 0;
end
end
end
end
endmodule | 0 |
138,447 | data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v | 83,528,847 | uart_loopback.v | v | 70 | 40 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:33: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:37: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(uart_loopback);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:37: syntax error, unexpected \';\'\n `setup_vcd(uart_loopback);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:43: Define or directive not defined: \'`assert_eq\'\n `assert_eq(txo, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:43: syntax error, unexpected \',\'\n `assert_eq(txo, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:44: Define or directive not defined: \'`assert_eq\'\n `assert_eq(ovalid, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:44: syntax error, unexpected \',\'\n `assert_eq(ovalid, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:46: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:53: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:57: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:61: Define or directive not defined: \'`assert_ge\'\n `assert_ge(c, 64);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:61: syntax error, unexpected \',\'\n `assert_ge(c, 64);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:62: Define or directive not defined: \'`assert_eq\'\n `assert_eq(ovalid, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:62: syntax error, unexpected \',\'\n `assert_eq(ovalid, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:63: Define or directive not defined: \'`assert_eq\'\n `assert_eq(odata, j[7:0]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_loopback.v:63: syntax error, unexpected \',\'\n `assert_eq(odata, j[7:0]);\n ^\n%Error: Exiting due to 16 error(s), 1 warning(s)\n' | 302,377 | module | module uart_loopback;
reg clk = 0, rst = 0;
reg [7:0] idata;
wire [7:0] odata;
reg ivalid;
wire ovalid;
wire txo;
uart_tx #(
.divisor(64)
) u_uart_tx (
.clk(clk),
.rst(rst),
.txo(txo),
.data(idata),
.valid(ivalid)
);
uart_rx #(
.divisor(32)
) u_uart_rx (
.clk(clk),
.rst(rst),
.rxi(txo),
.data(odata),
.valid(ovalid)
);
always
# 5 clk = !clk;
integer c = 0, j = 0;
initial begin
`setup_vcd(uart_loopback);
idata <= 8'h00;
ivalid <= 0;
`assert_eq(txo, 1);
`assert_eq(ovalid, 0);
rst <= 1;
@(negedge clk);
rst <= 0;
for (j = 0; j < 256; j = j + 1) begin
idata <= j[7:0];
ivalid <= 1;
@(negedge clk);
ivalid <= 0;
while (ovalid == 0) begin
@(negedge clk);
c = c + 1;
end
`assert_ge(c, 64);
`assert_eq(ovalid, 1);
`assert_eq(odata, j[7:0]);
end
$finish(0);
end
endmodule | module uart_loopback; |
reg clk = 0, rst = 0;
reg [7:0] idata;
wire [7:0] odata;
reg ivalid;
wire ovalid;
wire txo;
uart_tx #(
.divisor(64)
) u_uart_tx (
.clk(clk),
.rst(rst),
.txo(txo),
.data(idata),
.valid(ivalid)
);
uart_rx #(
.divisor(32)
) u_uart_rx (
.clk(clk),
.rst(rst),
.rxi(txo),
.data(odata),
.valid(ovalid)
);
always
# 5 clk = !clk;
integer c = 0, j = 0;
initial begin
`setup_vcd(uart_loopback);
idata <= 8'h00;
ivalid <= 0;
`assert_eq(txo, 1);
`assert_eq(ovalid, 0);
rst <= 1;
@(negedge clk);
rst <= 0;
for (j = 0; j < 256; j = j + 1) begin
idata <= j[7:0];
ivalid <= 1;
@(negedge clk);
ivalid <= 0;
while (ovalid == 0) begin
@(negedge clk);
c = c + 1;
end
`assert_ge(c, 64);
`assert_eq(ovalid, 1);
`assert_eq(odata, j[7:0]);
end
$finish(0);
end
endmodule | 0 |
138,448 | data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v | 83,528,847 | uart_rx_pattern.v | v | 62 | 66 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:25: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(uart_rx_pattern);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:25: syntax error, unexpected \';\'\n `setup_vcd(uart_rx_pattern);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:28: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:34: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:49: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:54: Define or directive not defined: \'`assert_eq\'\n `assert_eq(valid, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:54: syntax error, unexpected \',\'\n `assert_eq(valid, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:55: Define or directive not defined: \'`assert_eq\'\n `assert_eq(data, j[7:0]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_rx_pattern.v:55: syntax error, unexpected \',\'\n `assert_eq(data, j[7:0]);\n ^\n%Error: Exiting due to 10 error(s), 1 warning(s)\n' | 302,378 | module | module uart_rx_pattern;
reg clk = 0, rst = 0;
reg rxi = 0;
wire [7:0] data;
wire valid;
uart_rx #(
.divisor(32)
) u_uart_rx (
.clk(clk),
.rst(rst),
.rxi(rxi),
.data(data),
.valid(valid)
);
always
# 5 clk = !clk;
integer i, j;
initial begin
`setup_vcd(uart_rx_pattern);
rst <= 1;
@(negedge clk);
rst <= 0;
rxi <= 1;
repeat (10) begin
@(negedge clk);
end
for (j = 0; j < 256; j = j + 1) begin
for (i = 0; i < 10; i = i + 1) begin
if (i == 0)
rxi <= 0;
else if (i == 9)
rxi <= 1;
else
rxi <= j[i - 1];
repeat (32 * 2) begin
@(negedge clk);
end
end
`assert_eq(valid, 1);
`assert_eq(data, j[7:0]);
@(negedge clk);
end
$finish(0);
end
endmodule | module uart_rx_pattern; |
reg clk = 0, rst = 0;
reg rxi = 0;
wire [7:0] data;
wire valid;
uart_rx #(
.divisor(32)
) u_uart_rx (
.clk(clk),
.rst(rst),
.rxi(rxi),
.data(data),
.valid(valid)
);
always
# 5 clk = !clk;
integer i, j;
initial begin
`setup_vcd(uart_rx_pattern);
rst <= 1;
@(negedge clk);
rst <= 0;
rxi <= 1;
repeat (10) begin
@(negedge clk);
end
for (j = 0; j < 256; j = j + 1) begin
for (i = 0; i < 10; i = i + 1) begin
if (i == 0)
rxi <= 0;
else if (i == 9)
rxi <= 1;
else
rxi <= j[i - 1];
repeat (32 * 2) begin
@(negedge clk);
end
end
`assert_eq(valid, 1);
`assert_eq(data, j[7:0]);
@(negedge clk);
end
$finish(0);
end
endmodule | 0 |
138,449 | data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v | 83,528,847 | uart_tx_pattern.v | v | 63 | 40 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:1: Cannot find include file: helpers.v\n`include "helpers.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v.v\n data/full_repos/permissive/83528847/display-controller/uart/tests,data/full_repos/permissive/83528847/helpers.v.sv\n helpers.v\n helpers.v.v\n helpers.v.sv\n obj_dir/helpers.v\n obj_dir/helpers.v.v\n obj_dir/helpers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:25: Define or directive not defined: \'`setup_vcd\'\n `setup_vcd(uart_tx_pattern);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:25: syntax error, unexpected \';\'\n `setup_vcd(uart_tx_pattern);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:31: Define or directive not defined: \'`assert_eq\'\n `assert_eq(txo, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:31: syntax error, unexpected \',\'\n `assert_eq(txo, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:34: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:42: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:48: Define or directive not defined: \'`assert_eq\'\n `assert_eq(txo, 0);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:48: syntax error, unexpected \',\'\n `assert_eq(txo, 0);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:50: Define or directive not defined: \'`assert_eq\'\n `assert_eq(txo, 1);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:50: syntax error, unexpected \',\'\n `assert_eq(txo, 1);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:52: Define or directive not defined: \'`assert_eq\'\n `assert_eq(txo, data[i - 1]);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:52: syntax error, unexpected \',\'\n `assert_eq(txo, data[i - 1]);\n ^\n%Error: data/full_repos/permissive/83528847/display-controller/uart/tests/uart_tx_pattern.v:56: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: Exiting due to 14 error(s), 1 warning(s)\n' | 302,379 | module | module uart_tx_pattern;
reg clk = 0, rst = 0;
reg [7:0] data;
reg valid;
wire txo;
uart_tx #(
.divisor(32)
) u_uart_tx (
.clk(clk),
.rst(rst),
.txo(txo),
.data(data),
.valid(valid)
);
always
# 5 clk = !clk;
integer i, c, j;
initial begin
`setup_vcd(uart_tx_pattern);
data <= 8'h00;
valid <= 0;
`assert_eq(txo, 1);
rst <= 1;
repeat (10) begin
@(negedge clk);
end
rst <= 0;
for (j = 0; j < 256; j = j + 1) begin
data <= j[7:0];
valid <= 1;
@(negedge clk);
valid <= 0;
for (i = 0; i < 10; i = i + 1) begin
repeat (32) begin
if (i == 0)
`assert_eq(txo, 0);
else if (i == 9)
`assert_eq(txo, 1);
else
`assert_eq(txo, data[i - 1]);
@(negedge clk);
end
end
@(negedge clk);
end
$finish(0);
end
endmodule | module uart_tx_pattern; |
reg clk = 0, rst = 0;
reg [7:0] data;
reg valid;
wire txo;
uart_tx #(
.divisor(32)
) u_uart_tx (
.clk(clk),
.rst(rst),
.txo(txo),
.data(data),
.valid(valid)
);
always
# 5 clk = !clk;
integer i, c, j;
initial begin
`setup_vcd(uart_tx_pattern);
data <= 8'h00;
valid <= 0;
`assert_eq(txo, 1);
rst <= 1;
repeat (10) begin
@(negedge clk);
end
rst <= 0;
for (j = 0; j < 256; j = j + 1) begin
data <= j[7:0];
valid <= 1;
@(negedge clk);
valid <= 0;
for (i = 0; i < 10; i = i + 1) begin
repeat (32) begin
if (i == 0)
`assert_eq(txo, 0);
else if (i == 9)
`assert_eq(txo, 1);
else
`assert_eq(txo, data[i - 1]);
@(negedge clk);
end
end
@(negedge clk);
end
$finish(0);
end
endmodule | 0 |
138,450 | data/full_repos/permissive/83585882/Temperature Controller Simulation/challenge_3.srcs/sim_1/new/challenge3.v | 83,585,882 | challenge3.v | v | 30 | 41 | [] | [] | [] | null | line:27: before: "$" | null | 1: b'%Error: Cannot find file containing module: Controller\n ... Looked in:\n data/full_repos/permissive/83585882/Temperature/Controller\n data/full_repos/permissive/83585882/Temperature/Controller.v\n data/full_repos/permissive/83585882/Temperature/Controller.sv\n Controller\n Controller.v\n Controller.sv\n obj_dir/Controller\n obj_dir/Controller.v\n obj_dir/Controller.sv\n%Error: Cannot find file containing module: Simulation/challenge_3.srcs/sim_1/new,data/full_repos/permissive/83585882\n%Error: Cannot find file containing module: data/full_repos/permissive/83585882/Temperature\n%Error: Cannot find file containing module: Simulation/challenge_3.srcs/sim_1/new/challenge3.v\n%Error: Exiting due to 4 error(s)\n' | 302,380 | module | module challenge3;
reg [7:0] sw;
wire led;
challenge_3 uut (
.sw(sw),
.led(led)
);
integer k;
initial
begin
sw = 0;
for (k=0; k<256; k=k+1)
#2 sw = k;
#2 $finish;
end
endmodule | module challenge3; |
reg [7:0] sw;
wire led;
challenge_3 uut (
.sw(sw),
.led(led)
);
integer k;
initial
begin
sw = 0;
for (k=0; k<256; k=k+1)
#2 sw = k;
#2 $finish;
end
endmodule | 0 |
138,451 | data/full_repos/permissive/83585882/Temperature Controller Simulation/challenge_3.srcs/sim_1/new/test2.v | 83,585,882 | test2.v | v | 30 | 41 | [] | [] | [] | null | line:27: before: "$" | null | 1: b'%Error: Cannot find file containing module: Controller\n ... Looked in:\n data/full_repos/permissive/83585882/Temperature/Controller\n data/full_repos/permissive/83585882/Temperature/Controller.v\n data/full_repos/permissive/83585882/Temperature/Controller.sv\n Controller\n Controller.v\n Controller.sv\n obj_dir/Controller\n obj_dir/Controller.v\n obj_dir/Controller.sv\n%Error: Cannot find file containing module: Simulation/challenge_3.srcs/sim_1/new,data/full_repos/permissive/83585882\n%Error: Cannot find file containing module: data/full_repos/permissive/83585882/Temperature\n%Error: Cannot find file containing module: Simulation/challenge_3.srcs/sim_1/new/test2.v\n%Error: Exiting due to 4 error(s)\n' | 302,381 | module | module challenge3;
reg [7:0] sw;
wire led;
test2 uut (
.sw(sw),
.led(led)
);
integer i;
initial
begin
sw = 0;
for (i=0; i<256; i=i+1)
#20 sw = i;
#20 $finish;
end
endmodule | module challenge3; |
reg [7:0] sw;
wire led;
test2 uut (
.sw(sw),
.led(led)
);
integer i;
initial
begin
sw = 0;
for (i=0; i<256; i=i+1)
#20 sw = i;
#20 $finish;
end
endmodule | 0 |
138,452 | data/full_repos/permissive/83585882/Temperature Controller Simulation/challenge_3.srcs/sources_1/new/challenge_3.v | 83,585,882 | challenge_3.v | v | 21 | 72 | [] | [] | [] | [(3, 20)] | null | null | 1: b'%Error: Cannot find file containing module: Controller\n ... Looked in:\n data/full_repos/permissive/83585882/Temperature/Controller\n data/full_repos/permissive/83585882/Temperature/Controller.v\n data/full_repos/permissive/83585882/Temperature/Controller.sv\n Controller\n Controller.v\n Controller.sv\n obj_dir/Controller\n obj_dir/Controller.v\n obj_dir/Controller.sv\n%Error: Cannot find file containing module: Simulation/challenge_3.srcs/sources_1/new,data/full_repos/permissive/83585882\n%Error: Cannot find file containing module: data/full_repos/permissive/83585882/Temperature\n%Error: Cannot find file containing module: Simulation/challenge_3.srcs/sources_1/new/challenge_3.v\n%Error: Exiting due to 4 error(s)\n' | 302,382 | module | module challenge_3(
input [7:0] sw,
output led
);
assign led = sw[7] &
~sw[6] &
~sw[5] &
(~sw[4] | ~sw[3] | ~sw[2]) &
(~sw[4] | ~sw[3] | ~sw[1]);
endmodule | module challenge_3(
input [7:0] sw,
output led
); |
assign led = sw[7] &
~sw[6] &
~sw[5] &
(~sw[4] | ~sw[3] | ~sw[2]) &
(~sw[4] | ~sw[3] | ~sw[1]);
endmodule | 0 |
138,454 | data/full_repos/permissive/83862729/base_arbi/mem_ctrl_verb.v | 83,862,729 | mem_ctrl_verb.v | v | 386 | 53 | [] | [] | [] | [(2, 386)] | null | null | 1: b"%Error: data/full_repos/permissive/83862729/base_arbi/mem_ctrl_verb.v:166: Cannot find file containing module: 'mem_burst_v2'\nmem_burst_v2\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83862729/base_arbi,data/full_repos/permissive/83862729/mem_burst_v2\n data/full_repos/permissive/83862729/base_arbi,data/full_repos/permissive/83862729/mem_burst_v2.v\n data/full_repos/permissive/83862729/base_arbi,data/full_repos/permissive/83862729/mem_burst_v2.sv\n mem_burst_v2\n mem_burst_v2.v\n mem_burst_v2.sv\n obj_dir/mem_burst_v2\n obj_dir/mem_burst_v2.v\n obj_dir/mem_burst_v2.sv\n%Error: data/full_repos/permissive/83862729/base_arbi/mem_ctrl_verb.v:200: Cannot find file containing module: 'mem_read_arbi_verb'\nmem_read_arbi_verb \n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83862729/base_arbi/mem_ctrl_verb.v:275: Cannot find file containing module: 'mem_write_arbi_verb'\nmem_write_arbi_verb\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83862729/base_arbi/mem_ctrl_verb.v:349: Cannot find file containing module: 'ddr_ip'\nddr_ip ddr_m0(\n^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,385 | module | module mem_ctrl_verb#(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter READ_PORTS = 8,
parameter WRITE_PORTS = 8
)
(
input rst_n,
input source_clk,
output phy_clk,
output aux_half_rate_clk,
input ch0_rd_burst_req,
input[9:0] ch0_rd_burst_len,
input[ADDR_BITS-1:0] ch0_rd_burst_addr,
output ch0_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch0_rd_burst_data,
output ch0_rd_burst_finish,
input ch1_rd_burst_req,
input[9:0] ch1_rd_burst_len,
input[ADDR_BITS-1:0] ch1_rd_burst_addr,
output ch1_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch1_rd_burst_data,
output ch1_rd_burst_finish,
input ch2_rd_burst_req,
input[9:0] ch2_rd_burst_len,
input[ADDR_BITS-1:0] ch2_rd_burst_addr,
output ch2_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch2_rd_burst_data,
output ch2_rd_burst_finish,
input ch3_rd_burst_req,
input[9:0] ch3_rd_burst_len,
input[ADDR_BITS-1:0] ch3_rd_burst_addr,
output ch3_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch3_rd_burst_data,
output ch3_rd_burst_finish,
input ch4_rd_burst_req,
input[9:0] ch4_rd_burst_len,
input[ADDR_BITS-1:0] ch4_rd_burst_addr,
output ch4_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch4_rd_burst_data,
output ch4_rd_burst_finish,
input ch5_rd_burst_req,
input[9:0] ch5_rd_burst_len,
input[ADDR_BITS-1:0] ch5_rd_burst_addr,
output ch5_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch5_rd_burst_data,
output ch5_rd_burst_finish,
input ch6_rd_burst_req,
input[9:0] ch6_rd_burst_len,
input[ADDR_BITS-1:0] ch6_rd_burst_addr,
output ch6_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch6_rd_burst_data,
output ch6_rd_burst_finish,
input ch7_rd_burst_req,
input[9:0] ch7_rd_burst_len,
input[ADDR_BITS-1:0] ch7_rd_burst_addr,
output ch7_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch7_rd_burst_data,
output ch7_rd_burst_finish,
input ch0_wr_burst_req,
input[9:0] ch0_wr_burst_len,
input[ADDR_BITS-1:0] ch0_wr_burst_addr,
output ch0_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch0_wr_burst_data,
output ch0_wr_burst_finish,
input ch1_wr_burst_req,
input[9:0] ch1_wr_burst_len,
input[ADDR_BITS-1:0] ch1_wr_burst_addr,
output ch1_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch1_wr_burst_data,
output ch1_wr_burst_finish,
input ch2_wr_burst_req,
input[9:0] ch2_wr_burst_len,
input[ADDR_BITS-1:0] ch2_wr_burst_addr,
output ch2_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch2_wr_burst_data,
output ch2_wr_burst_finish,
input ch3_wr_burst_req,
input[9:0] ch3_wr_burst_len,
input[ADDR_BITS-1:0] ch3_wr_burst_addr,
output ch3_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch3_wr_burst_data,
output ch3_wr_burst_finish,
input ch4_wr_burst_req,
input[9:0] ch4_wr_burst_len,
input[ADDR_BITS-1:0] ch4_wr_burst_addr,
output ch4_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch4_wr_burst_data,
output ch4_wr_burst_finish,
input ch5_wr_burst_req,
input[9:0] ch5_wr_burst_len,
input[ADDR_BITS-1:0] ch5_wr_burst_addr,
output ch5_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch5_wr_burst_data,
output ch5_wr_burst_finish,
input ch6_wr_burst_req,
input[9:0] ch6_wr_burst_len,
input[ADDR_BITS-1:0] ch6_wr_burst_addr,
output ch6_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch6_wr_burst_data,
output ch6_wr_burst_finish,
input ch7_wr_burst_req,
input[9:0] ch7_wr_burst_len,
input[ADDR_BITS-1:0] ch7_wr_burst_addr,
output ch7_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch7_wr_burst_data,
output ch7_wr_burst_finish,
output wire[0 : 0] mem_cs_n,
output wire[0 : 0] mem_cke,
output wire[12: 0] mem_addr,
output wire[2 : 0] mem_ba,
output wire mem_ras_n,
output wire mem_cas_n,
output wire mem_we_n,
inout wire[0 : 0] mem_clk,
inout wire[0 : 0] mem_clk_n,
output wire[3 : 0] mem_dm,
inout wire[31: 0] mem_dq,
inout wire[3 : 0] mem_dqs,
output[0:0] mem_odt
);
wire[ADDR_BITS-1:0] local_address;
wire local_write_req;
wire local_read_req;
wire[MEM_DATA_BITS - 1:0] local_wdata;
wire[MEM_DATA_BITS/8 - 1:0] local_be;
wire[2:0] local_size;
wire local_ready;
wire[MEM_DATA_BITS - 1:0] local_rdata;
wire local_rdata_valid;
wire local_wdata_req;
wire local_init_done;
wire rd_burst_finish;
wire wr_burst_finish;
wire[ADDR_BITS-1:0] wr_burst_addr;
wire[ADDR_BITS-1:0] rd_burst_addr;
wire wr_burst_data_req;
wire rd_burst_data_valid;
wire[9:0] wr_burst_len;
wire[9:0] rd_burst_len;
wire wr_burst_req;
wire rd_burst_req;
wire[MEM_DATA_BITS - 1:0] wr_burst_data;
wire[MEM_DATA_BITS - 1:0] rd_burst_data;
wire ddr_rst_n;
wire local_burstbegin;
mem_burst_v2
#(
.MEM_DATA_BITS (MEM_DATA_BITS),
.ADDR_BITS (ADDR_BITS)
)
mem_burst_m0(
.rst_n(rst_n),
.mem_clk(phy_clk),
.rd_burst_req(rd_burst_req),
.wr_burst_req(wr_burst_req),
.rd_burst_len(rd_burst_len),
.wr_burst_len(wr_burst_len),
.rd_burst_addr(rd_burst_addr),
.wr_burst_addr(wr_burst_addr),
.rd_burst_data_valid(rd_burst_data_valid),
.wr_burst_data_req(wr_burst_data_req),
.rd_burst_data(rd_burst_data),
.wr_burst_data(wr_burst_data),
.rd_burst_finish(rd_burst_finish),
.wr_burst_finish(wr_burst_finish),
.local_init_done(local_init_done),
.local_ready(local_ready),
.local_burstbegin(local_burstbegin),
.local_wdata(local_wdata),
.local_rdata_valid(local_rdata_valid),
.local_rdata(local_rdata),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_address(local_address),
.local_be(local_be),
.local_size(local_size)
);
mem_read_arbi_verb
#(
.MEM_DATA_BITS (MEM_DATA_BITS ),
.ADDR_BITS (ADDR_BITS ),
.PINTS (READ_PORTS )
)
mem_read_arbi_m0
(
.rst_n (rst_n),
.mem_clk (phy_clk),
.ch0_rd_burst_req (ch0_rd_burst_req),
.ch0_rd_burst_len (ch0_rd_burst_len),
.ch0_rd_burst_addr (ch0_rd_burst_addr),
.ch0_rd_burst_data_valid (ch0_rd_burst_data_valid),
.ch0_rd_burst_data (ch0_rd_burst_data),
.ch0_rd_burst_finish (ch0_rd_burst_finish),
.ch1_rd_burst_req (ch1_rd_burst_req),
.ch1_rd_burst_len (ch1_rd_burst_len),
.ch1_rd_burst_addr (ch1_rd_burst_addr),
.ch1_rd_burst_data_valid (ch1_rd_burst_data_valid),
.ch1_rd_burst_data (ch1_rd_burst_data),
.ch1_rd_burst_finish (ch1_rd_burst_finish),
.ch2_rd_burst_req (ch2_rd_burst_req),
.ch2_rd_burst_len (ch2_rd_burst_len),
.ch2_rd_burst_addr (ch2_rd_burst_addr),
.ch2_rd_burst_data_valid (ch2_rd_burst_data_valid),
.ch2_rd_burst_data (ch2_rd_burst_data),
.ch2_rd_burst_finish (ch2_rd_burst_finish),
.ch3_rd_burst_req (ch3_rd_burst_req),
.ch3_rd_burst_len (ch3_rd_burst_len),
.ch3_rd_burst_addr (ch3_rd_burst_addr),
.ch3_rd_burst_data_valid (ch3_rd_burst_data_valid),
.ch3_rd_burst_data (ch3_rd_burst_data),
.ch3_rd_burst_finish (ch3_rd_burst_finish),
.ch4_rd_burst_req (ch4_rd_burst_req),
.ch4_rd_burst_len (ch4_rd_burst_len),
.ch4_rd_burst_addr (ch4_rd_burst_addr),
.ch4_rd_burst_data_valid (ch4_rd_burst_data_valid),
.ch4_rd_burst_data (ch4_rd_burst_data),
.ch4_rd_burst_finish (ch4_rd_burst_finish),
.ch5_rd_burst_req (ch5_rd_burst_req),
.ch5_rd_burst_len (ch5_rd_burst_len),
.ch5_rd_burst_addr (ch5_rd_burst_addr),
.ch5_rd_burst_data_valid (ch5_rd_burst_data_valid),
.ch5_rd_burst_data (ch5_rd_burst_data),
.ch5_rd_burst_finish (ch5_rd_burst_finish),
.ch6_rd_burst_req (ch6_rd_burst_req),
.ch6_rd_burst_len (ch6_rd_burst_len),
.ch6_rd_burst_addr (ch6_rd_burst_addr),
.ch6_rd_burst_data_valid (ch6_rd_burst_data_valid),
.ch6_rd_burst_data (ch6_rd_burst_data),
.ch6_rd_burst_finish (ch6_rd_burst_finish),
.ch7_rd_burst_req (ch7_rd_burst_req),
.ch7_rd_burst_len (ch7_rd_burst_len),
.ch7_rd_burst_addr (ch7_rd_burst_addr),
.ch7_rd_burst_data_valid (ch7_rd_burst_data_valid),
.ch7_rd_burst_data (ch7_rd_burst_data),
.ch7_rd_burst_finish (ch7_rd_burst_finish),
.rd_burst_req (rd_burst_req),
.rd_burst_len (rd_burst_len),
.rd_burst_addr (rd_burst_addr),
.rd_burst_data_valid (rd_burst_data_valid),
.rd_burst_data (rd_burst_data),
.rd_burst_finish (rd_burst_finish)
);
mem_write_arbi_verb
#(
.MEM_DATA_BITS (MEM_DATA_BITS),
.ADDR_BITS (ADDR_BITS),
.PINTS (WRITE_PORTS)
)
mem_write_arbi_m0(
.rst_n (rst_n),
.mem_clk (phy_clk),
.ch0_wr_burst_req (ch0_wr_burst_req),
.ch0_wr_burst_len (ch0_wr_burst_len),
.ch0_wr_burst_addr (ch0_wr_burst_addr),
.ch0_wr_burst_data_req (ch0_wr_burst_data_req),
.ch0_wr_burst_data (ch0_wr_burst_data),
.ch0_wr_burst_finish (ch0_wr_burst_finish),
.ch1_wr_burst_req (ch1_wr_burst_req),
.ch1_wr_burst_len (ch1_wr_burst_len),
.ch1_wr_burst_addr (ch1_wr_burst_addr),
.ch1_wr_burst_data_req (ch1_wr_burst_data_req),
.ch1_wr_burst_data (ch1_wr_burst_data),
.ch1_wr_burst_finish (ch1_wr_burst_finish),
.ch2_wr_burst_req (ch2_wr_burst_req),
.ch2_wr_burst_len (ch2_wr_burst_len),
.ch2_wr_burst_addr (ch2_wr_burst_addr),
.ch2_wr_burst_data_req (ch2_wr_burst_data_req),
.ch2_wr_burst_data (ch2_wr_burst_data),
.ch2_wr_burst_finish (ch2_wr_burst_finish),
.ch3_wr_burst_req (ch3_wr_burst_req),
.ch3_wr_burst_len (ch3_wr_burst_len),
.ch3_wr_burst_addr (ch3_wr_burst_addr),
.ch3_wr_burst_data_req (ch3_wr_burst_data_req),
.ch3_wr_burst_data (ch3_wr_burst_data),
.ch3_wr_burst_finish (ch3_wr_burst_finish),
.ch4_wr_burst_req (ch4_wr_burst_req),
.ch4_wr_burst_len (ch4_wr_burst_len),
.ch4_wr_burst_addr (ch4_wr_burst_addr),
.ch4_wr_burst_data_req (ch4_wr_burst_data_req),
.ch4_wr_burst_data (ch4_wr_burst_data),
.ch4_wr_burst_finish (ch4_wr_burst_finish),
.ch5_wr_burst_req (ch5_wr_burst_req),
.ch5_wr_burst_len (ch5_wr_burst_len),
.ch5_wr_burst_addr (ch5_wr_burst_addr),
.ch5_wr_burst_data_req (ch5_wr_burst_data_req),
.ch5_wr_burst_data (ch5_wr_burst_data),
.ch5_wr_burst_finish (ch5_wr_burst_finish),
.ch6_wr_burst_req (ch6_wr_burst_req),
.ch6_wr_burst_len (ch6_wr_burst_len),
.ch6_wr_burst_addr (ch6_wr_burst_addr),
.ch6_wr_burst_data_req (ch6_wr_burst_data_req),
.ch6_wr_burst_data (ch6_wr_burst_data),
.ch6_wr_burst_finish (ch6_wr_burst_finish),
.ch7_wr_burst_req (ch7_wr_burst_req),
.ch7_wr_burst_len (ch7_wr_burst_len),
.ch7_wr_burst_addr (ch7_wr_burst_addr),
.ch7_wr_burst_data_req (ch7_wr_burst_data_req),
.ch7_wr_burst_data (ch7_wr_burst_data),
.ch7_wr_burst_finish (ch7_wr_burst_finish),
.wr_burst_req (wr_burst_req),
.wr_burst_len (wr_burst_len),
.wr_burst_addr (wr_burst_addr),
.wr_burst_data_req (wr_burst_data_req),
.wr_burst_data (wr_burst_data),
.wr_burst_finish (wr_burst_finish)
);
ddr_ip ddr_m0(
.local_address(local_address),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.global_reset_n(rst_n),
.pll_ref_clk(source_clk),
.soft_reset_n(1'b1),
.local_ready(local_ready),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.reset_request_n(),
.mem_cs_n(mem_cs_n),
.mem_cke(mem_cke),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_ras_n(mem_ras_n),
.mem_cas_n(mem_cas_n),
.mem_we_n(mem_we_n),
.mem_dm(mem_dm),
.local_refresh_ack(),
.local_burstbegin(local_burstbegin),
.local_init_done(local_init_done),
.reset_phy_clk_n(),
.phy_clk(phy_clk),
.aux_full_rate_clk(),
.aux_half_rate_clk(),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_odt(mem_odt)
);
endmodule | module mem_ctrl_verb#(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter READ_PORTS = 8,
parameter WRITE_PORTS = 8
)
(
input rst_n,
input source_clk,
output phy_clk,
output aux_half_rate_clk,
input ch0_rd_burst_req,
input[9:0] ch0_rd_burst_len,
input[ADDR_BITS-1:0] ch0_rd_burst_addr,
output ch0_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch0_rd_burst_data,
output ch0_rd_burst_finish,
input ch1_rd_burst_req,
input[9:0] ch1_rd_burst_len,
input[ADDR_BITS-1:0] ch1_rd_burst_addr,
output ch1_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch1_rd_burst_data,
output ch1_rd_burst_finish,
input ch2_rd_burst_req,
input[9:0] ch2_rd_burst_len,
input[ADDR_BITS-1:0] ch2_rd_burst_addr,
output ch2_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch2_rd_burst_data,
output ch2_rd_burst_finish,
input ch3_rd_burst_req,
input[9:0] ch3_rd_burst_len,
input[ADDR_BITS-1:0] ch3_rd_burst_addr,
output ch3_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch3_rd_burst_data,
output ch3_rd_burst_finish,
input ch4_rd_burst_req,
input[9:0] ch4_rd_burst_len,
input[ADDR_BITS-1:0] ch4_rd_burst_addr,
output ch4_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch4_rd_burst_data,
output ch4_rd_burst_finish,
input ch5_rd_burst_req,
input[9:0] ch5_rd_burst_len,
input[ADDR_BITS-1:0] ch5_rd_burst_addr,
output ch5_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch5_rd_burst_data,
output ch5_rd_burst_finish,
input ch6_rd_burst_req,
input[9:0] ch6_rd_burst_len,
input[ADDR_BITS-1:0] ch6_rd_burst_addr,
output ch6_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch6_rd_burst_data,
output ch6_rd_burst_finish,
input ch7_rd_burst_req,
input[9:0] ch7_rd_burst_len,
input[ADDR_BITS-1:0] ch7_rd_burst_addr,
output ch7_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch7_rd_burst_data,
output ch7_rd_burst_finish,
input ch0_wr_burst_req,
input[9:0] ch0_wr_burst_len,
input[ADDR_BITS-1:0] ch0_wr_burst_addr,
output ch0_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch0_wr_burst_data,
output ch0_wr_burst_finish,
input ch1_wr_burst_req,
input[9:0] ch1_wr_burst_len,
input[ADDR_BITS-1:0] ch1_wr_burst_addr,
output ch1_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch1_wr_burst_data,
output ch1_wr_burst_finish,
input ch2_wr_burst_req,
input[9:0] ch2_wr_burst_len,
input[ADDR_BITS-1:0] ch2_wr_burst_addr,
output ch2_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch2_wr_burst_data,
output ch2_wr_burst_finish,
input ch3_wr_burst_req,
input[9:0] ch3_wr_burst_len,
input[ADDR_BITS-1:0] ch3_wr_burst_addr,
output ch3_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch3_wr_burst_data,
output ch3_wr_burst_finish,
input ch4_wr_burst_req,
input[9:0] ch4_wr_burst_len,
input[ADDR_BITS-1:0] ch4_wr_burst_addr,
output ch4_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch4_wr_burst_data,
output ch4_wr_burst_finish,
input ch5_wr_burst_req,
input[9:0] ch5_wr_burst_len,
input[ADDR_BITS-1:0] ch5_wr_burst_addr,
output ch5_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch5_wr_burst_data,
output ch5_wr_burst_finish,
input ch6_wr_burst_req,
input[9:0] ch6_wr_burst_len,
input[ADDR_BITS-1:0] ch6_wr_burst_addr,
output ch6_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch6_wr_burst_data,
output ch6_wr_burst_finish,
input ch7_wr_burst_req,
input[9:0] ch7_wr_burst_len,
input[ADDR_BITS-1:0] ch7_wr_burst_addr,
output ch7_wr_burst_data_req,
input[MEM_DATA_BITS - 1:0] ch7_wr_burst_data,
output ch7_wr_burst_finish,
output wire[0 : 0] mem_cs_n,
output wire[0 : 0] mem_cke,
output wire[12: 0] mem_addr,
output wire[2 : 0] mem_ba,
output wire mem_ras_n,
output wire mem_cas_n,
output wire mem_we_n,
inout wire[0 : 0] mem_clk,
inout wire[0 : 0] mem_clk_n,
output wire[3 : 0] mem_dm,
inout wire[31: 0] mem_dq,
inout wire[3 : 0] mem_dqs,
output[0:0] mem_odt
); |
wire[ADDR_BITS-1:0] local_address;
wire local_write_req;
wire local_read_req;
wire[MEM_DATA_BITS - 1:0] local_wdata;
wire[MEM_DATA_BITS/8 - 1:0] local_be;
wire[2:0] local_size;
wire local_ready;
wire[MEM_DATA_BITS - 1:0] local_rdata;
wire local_rdata_valid;
wire local_wdata_req;
wire local_init_done;
wire rd_burst_finish;
wire wr_burst_finish;
wire[ADDR_BITS-1:0] wr_burst_addr;
wire[ADDR_BITS-1:0] rd_burst_addr;
wire wr_burst_data_req;
wire rd_burst_data_valid;
wire[9:0] wr_burst_len;
wire[9:0] rd_burst_len;
wire wr_burst_req;
wire rd_burst_req;
wire[MEM_DATA_BITS - 1:0] wr_burst_data;
wire[MEM_DATA_BITS - 1:0] rd_burst_data;
wire ddr_rst_n;
wire local_burstbegin;
mem_burst_v2
#(
.MEM_DATA_BITS (MEM_DATA_BITS),
.ADDR_BITS (ADDR_BITS)
)
mem_burst_m0(
.rst_n(rst_n),
.mem_clk(phy_clk),
.rd_burst_req(rd_burst_req),
.wr_burst_req(wr_burst_req),
.rd_burst_len(rd_burst_len),
.wr_burst_len(wr_burst_len),
.rd_burst_addr(rd_burst_addr),
.wr_burst_addr(wr_burst_addr),
.rd_burst_data_valid(rd_burst_data_valid),
.wr_burst_data_req(wr_burst_data_req),
.rd_burst_data(rd_burst_data),
.wr_burst_data(wr_burst_data),
.rd_burst_finish(rd_burst_finish),
.wr_burst_finish(wr_burst_finish),
.local_init_done(local_init_done),
.local_ready(local_ready),
.local_burstbegin(local_burstbegin),
.local_wdata(local_wdata),
.local_rdata_valid(local_rdata_valid),
.local_rdata(local_rdata),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_address(local_address),
.local_be(local_be),
.local_size(local_size)
);
mem_read_arbi_verb
#(
.MEM_DATA_BITS (MEM_DATA_BITS ),
.ADDR_BITS (ADDR_BITS ),
.PINTS (READ_PORTS )
)
mem_read_arbi_m0
(
.rst_n (rst_n),
.mem_clk (phy_clk),
.ch0_rd_burst_req (ch0_rd_burst_req),
.ch0_rd_burst_len (ch0_rd_burst_len),
.ch0_rd_burst_addr (ch0_rd_burst_addr),
.ch0_rd_burst_data_valid (ch0_rd_burst_data_valid),
.ch0_rd_burst_data (ch0_rd_burst_data),
.ch0_rd_burst_finish (ch0_rd_burst_finish),
.ch1_rd_burst_req (ch1_rd_burst_req),
.ch1_rd_burst_len (ch1_rd_burst_len),
.ch1_rd_burst_addr (ch1_rd_burst_addr),
.ch1_rd_burst_data_valid (ch1_rd_burst_data_valid),
.ch1_rd_burst_data (ch1_rd_burst_data),
.ch1_rd_burst_finish (ch1_rd_burst_finish),
.ch2_rd_burst_req (ch2_rd_burst_req),
.ch2_rd_burst_len (ch2_rd_burst_len),
.ch2_rd_burst_addr (ch2_rd_burst_addr),
.ch2_rd_burst_data_valid (ch2_rd_burst_data_valid),
.ch2_rd_burst_data (ch2_rd_burst_data),
.ch2_rd_burst_finish (ch2_rd_burst_finish),
.ch3_rd_burst_req (ch3_rd_burst_req),
.ch3_rd_burst_len (ch3_rd_burst_len),
.ch3_rd_burst_addr (ch3_rd_burst_addr),
.ch3_rd_burst_data_valid (ch3_rd_burst_data_valid),
.ch3_rd_burst_data (ch3_rd_burst_data),
.ch3_rd_burst_finish (ch3_rd_burst_finish),
.ch4_rd_burst_req (ch4_rd_burst_req),
.ch4_rd_burst_len (ch4_rd_burst_len),
.ch4_rd_burst_addr (ch4_rd_burst_addr),
.ch4_rd_burst_data_valid (ch4_rd_burst_data_valid),
.ch4_rd_burst_data (ch4_rd_burst_data),
.ch4_rd_burst_finish (ch4_rd_burst_finish),
.ch5_rd_burst_req (ch5_rd_burst_req),
.ch5_rd_burst_len (ch5_rd_burst_len),
.ch5_rd_burst_addr (ch5_rd_burst_addr),
.ch5_rd_burst_data_valid (ch5_rd_burst_data_valid),
.ch5_rd_burst_data (ch5_rd_burst_data),
.ch5_rd_burst_finish (ch5_rd_burst_finish),
.ch6_rd_burst_req (ch6_rd_burst_req),
.ch6_rd_burst_len (ch6_rd_burst_len),
.ch6_rd_burst_addr (ch6_rd_burst_addr),
.ch6_rd_burst_data_valid (ch6_rd_burst_data_valid),
.ch6_rd_burst_data (ch6_rd_burst_data),
.ch6_rd_burst_finish (ch6_rd_burst_finish),
.ch7_rd_burst_req (ch7_rd_burst_req),
.ch7_rd_burst_len (ch7_rd_burst_len),
.ch7_rd_burst_addr (ch7_rd_burst_addr),
.ch7_rd_burst_data_valid (ch7_rd_burst_data_valid),
.ch7_rd_burst_data (ch7_rd_burst_data),
.ch7_rd_burst_finish (ch7_rd_burst_finish),
.rd_burst_req (rd_burst_req),
.rd_burst_len (rd_burst_len),
.rd_burst_addr (rd_burst_addr),
.rd_burst_data_valid (rd_burst_data_valid),
.rd_burst_data (rd_burst_data),
.rd_burst_finish (rd_burst_finish)
);
mem_write_arbi_verb
#(
.MEM_DATA_BITS (MEM_DATA_BITS),
.ADDR_BITS (ADDR_BITS),
.PINTS (WRITE_PORTS)
)
mem_write_arbi_m0(
.rst_n (rst_n),
.mem_clk (phy_clk),
.ch0_wr_burst_req (ch0_wr_burst_req),
.ch0_wr_burst_len (ch0_wr_burst_len),
.ch0_wr_burst_addr (ch0_wr_burst_addr),
.ch0_wr_burst_data_req (ch0_wr_burst_data_req),
.ch0_wr_burst_data (ch0_wr_burst_data),
.ch0_wr_burst_finish (ch0_wr_burst_finish),
.ch1_wr_burst_req (ch1_wr_burst_req),
.ch1_wr_burst_len (ch1_wr_burst_len),
.ch1_wr_burst_addr (ch1_wr_burst_addr),
.ch1_wr_burst_data_req (ch1_wr_burst_data_req),
.ch1_wr_burst_data (ch1_wr_burst_data),
.ch1_wr_burst_finish (ch1_wr_burst_finish),
.ch2_wr_burst_req (ch2_wr_burst_req),
.ch2_wr_burst_len (ch2_wr_burst_len),
.ch2_wr_burst_addr (ch2_wr_burst_addr),
.ch2_wr_burst_data_req (ch2_wr_burst_data_req),
.ch2_wr_burst_data (ch2_wr_burst_data),
.ch2_wr_burst_finish (ch2_wr_burst_finish),
.ch3_wr_burst_req (ch3_wr_burst_req),
.ch3_wr_burst_len (ch3_wr_burst_len),
.ch3_wr_burst_addr (ch3_wr_burst_addr),
.ch3_wr_burst_data_req (ch3_wr_burst_data_req),
.ch3_wr_burst_data (ch3_wr_burst_data),
.ch3_wr_burst_finish (ch3_wr_burst_finish),
.ch4_wr_burst_req (ch4_wr_burst_req),
.ch4_wr_burst_len (ch4_wr_burst_len),
.ch4_wr_burst_addr (ch4_wr_burst_addr),
.ch4_wr_burst_data_req (ch4_wr_burst_data_req),
.ch4_wr_burst_data (ch4_wr_burst_data),
.ch4_wr_burst_finish (ch4_wr_burst_finish),
.ch5_wr_burst_req (ch5_wr_burst_req),
.ch5_wr_burst_len (ch5_wr_burst_len),
.ch5_wr_burst_addr (ch5_wr_burst_addr),
.ch5_wr_burst_data_req (ch5_wr_burst_data_req),
.ch5_wr_burst_data (ch5_wr_burst_data),
.ch5_wr_burst_finish (ch5_wr_burst_finish),
.ch6_wr_burst_req (ch6_wr_burst_req),
.ch6_wr_burst_len (ch6_wr_burst_len),
.ch6_wr_burst_addr (ch6_wr_burst_addr),
.ch6_wr_burst_data_req (ch6_wr_burst_data_req),
.ch6_wr_burst_data (ch6_wr_burst_data),
.ch6_wr_burst_finish (ch6_wr_burst_finish),
.ch7_wr_burst_req (ch7_wr_burst_req),
.ch7_wr_burst_len (ch7_wr_burst_len),
.ch7_wr_burst_addr (ch7_wr_burst_addr),
.ch7_wr_burst_data_req (ch7_wr_burst_data_req),
.ch7_wr_burst_data (ch7_wr_burst_data),
.ch7_wr_burst_finish (ch7_wr_burst_finish),
.wr_burst_req (wr_burst_req),
.wr_burst_len (wr_burst_len),
.wr_burst_addr (wr_burst_addr),
.wr_burst_data_req (wr_burst_data_req),
.wr_burst_data (wr_burst_data),
.wr_burst_finish (wr_burst_finish)
);
ddr_ip ddr_m0(
.local_address(local_address),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.global_reset_n(rst_n),
.pll_ref_clk(source_clk),
.soft_reset_n(1'b1),
.local_ready(local_ready),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.reset_request_n(),
.mem_cs_n(mem_cs_n),
.mem_cke(mem_cke),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_ras_n(mem_ras_n),
.mem_cas_n(mem_cas_n),
.mem_we_n(mem_we_n),
.mem_dm(mem_dm),
.local_refresh_ack(),
.local_burstbegin(local_burstbegin),
.local_init_done(local_init_done),
.reset_phy_clk_n(),
.phy_clk(phy_clk),
.aux_full_rate_clk(),
.aux_half_rate_clk(),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_odt(mem_odt)
);
endmodule | 5 |
138,455 | data/full_repos/permissive/83862729/base_arbi/mem_read_arbi_verb.v | 83,862,729 | mem_read_arbi_verb.v | v | 379 | 118 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83862729/base_arbi/mem_read_arbi_verb.v:77: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n : ... In instance mem_read_arbi_verb\nreg[15:0] cnt_timer = 15\'d0;\n ^~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83862729/base_arbi/mem_read_arbi_verb.v:124: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 6 bits.\n : ... In instance mem_read_arbi_verb\n read_state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/base_arbi/mem_read_arbi_verb.v:126: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 6 bits.\n : ... In instance mem_read_arbi_verb\n read_state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/base_arbi/mem_read_arbi_verb.v:269: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 6 bits.\n : ... In instance mem_read_arbi_verb\n read_state_next <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/base_arbi/mem_read_arbi_verb.v:143: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 6 bits.\n : ... In instance mem_read_arbi_verb\n case(read_state)\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 302,386 | module | module mem_read_arbi_verb
#(
parameter MEM_DATA_BITS = 32,
parameter ADDR_BITS = 25,
parameter PINTS = 8
)
(
input rst_n,
input mem_clk,
input ch0_rd_burst_req,
input[9:0] ch0_rd_burst_len,
input[ADDR_BITS-1:0] ch0_rd_burst_addr,
output ch0_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch0_rd_burst_data,
output ch0_rd_burst_finish,
input ch1_rd_burst_req,
input[9:0] ch1_rd_burst_len,
input[ADDR_BITS-1:0] ch1_rd_burst_addr,
output ch1_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch1_rd_burst_data,
output ch1_rd_burst_finish,
input ch2_rd_burst_req,
input[9:0] ch2_rd_burst_len,
input[ADDR_BITS-1:0] ch2_rd_burst_addr,
output ch2_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch2_rd_burst_data,
output ch2_rd_burst_finish,
input ch3_rd_burst_req,
input[9:0] ch3_rd_burst_len,
input[ADDR_BITS-1:0] ch3_rd_burst_addr,
output ch3_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch3_rd_burst_data,
output ch3_rd_burst_finish,
input ch4_rd_burst_req,
input[9:0] ch4_rd_burst_len,
input[ADDR_BITS-1:0] ch4_rd_burst_addr,
output ch4_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch4_rd_burst_data,
output ch4_rd_burst_finish,
input ch5_rd_burst_req,
input[9:0] ch5_rd_burst_len,
input[ADDR_BITS-1:0] ch5_rd_burst_addr,
output ch5_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch5_rd_burst_data,
output ch5_rd_burst_finish,
input ch6_rd_burst_req,
input[9:0] ch6_rd_burst_len,
input[ADDR_BITS-1:0] ch6_rd_burst_addr,
output ch6_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch6_rd_burst_data,
output ch6_rd_burst_finish,
input ch7_rd_burst_req,
input[9:0] ch7_rd_burst_len,
input[ADDR_BITS-1:0] ch7_rd_burst_addr,
output ch7_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch7_rd_burst_data,
output ch7_rd_burst_finish,
output reg rd_burst_req,
output reg[9:0] rd_burst_len,
output reg[ADDR_BITS-1:0] rd_burst_addr,
input rd_burst_data_valid,
input[MEM_DATA_BITS - 1:0] rd_burst_data,
input rd_burst_finish
);
reg[6:0] read_state = 7'd0;
reg[6:0] read_state_next = 7'd0;
reg[15:0] cnt_timer = 15'd0;
localparam IDLE = 6'd0;
localparam CH0_CHECK = 7'd1;
localparam CH0_BEGIN = 7'd2;
localparam CH0_READ = 7'd3;
localparam CH0_END = 7'd4;
localparam CH1_CHECK = 7'd5;
localparam CH1_BEGIN = 7'd6;
localparam CH1_READ = 7'd7;
localparam CH1_END = 7'd8;
localparam CH2_CHECK = 7'd9;
localparam CH2_BEGIN = 7'd10;
localparam CH2_READ = 7'd11;
localparam CH2_END = 7'd12;
localparam CH3_CHECK = 7'd13;
localparam CH3_BEGIN = 7'd14;
localparam CH3_READ = 7'd15;
localparam CH3_END = 7'd16;
localparam CH4_CHECK = 7'd1+7'd16;
localparam CH4_BEGIN = 7'd2+7'd16;
localparam CH4_READ = 7'd3+7'd16;
localparam CH4_END = 7'd4+7'd16;
localparam CH5_CHECK = 6'd5+7'd16;
localparam CH5_BEGIN = 6'd6+7'd16;
localparam CH5_READ = 6'd7+7'd16;
localparam CH5_END = 6'd8+7'd16;
localparam CH6_CHECK = 6'd9 +7'd16;
localparam CH6_BEGIN = 6'd10+7'd16;
localparam CH6_READ = 6'd11+7'd16;
localparam CH6_END = 6'd12+7'd16;
localparam CH7_CHECK = 6'd13+7'd16;
localparam CH7_BEGIN = 6'd14+7'd16;
localparam CH7_READ = 6'd15+7'd16;
localparam CH7_END = 6'd16+7'd16;
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
read_state <= IDLE;
else if(cnt_timer > 16'd8000)
read_state <= IDLE;
else
read_state <= read_state_next;
end
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
cnt_timer <= 16'd0;
else if(read_state == CH0_CHECK)
cnt_timer <= 16'd0;
else
cnt_timer <= cnt_timer + 16'd1;
end
always@(*)
begin
case(read_state)
IDLE:
read_state_next <= CH0_CHECK;
CH0_CHECK:
if(ch0_rd_burst_req && ch0_rd_burst_len != 10'd0)
read_state_next <= CH0_BEGIN;
else
read_state_next <= CH1_CHECK;
CH0_BEGIN:
read_state_next <= CH0_READ;
CH0_READ:
if(rd_burst_finish)
read_state_next <= CH0_END;
else
read_state_next <= CH0_READ;
CH0_END:
read_state_next <= CH1_CHECK;
CH1_CHECK:
if(ch1_rd_burst_req && ch1_rd_burst_len != 10'd0)
read_state_next <= CH1_BEGIN;
else
read_state_next <= (PINTS!=2)? CH2_CHECK : CH0_CHECK;
CH1_BEGIN:
read_state_next <= CH1_READ;
CH1_READ:
if(rd_burst_finish)
read_state_next <= CH1_END;
else
read_state_next <= CH1_READ;
CH1_END:
read_state_next <= (PINTS!=2)? CH2_CHECK : CH0_CHECK;
CH2_CHECK:
if(ch2_rd_burst_req && ch2_rd_burst_len != 10'd0)
read_state_next <= CH2_BEGIN;
else
read_state_next <= (PINTS!=3)? CH3_CHECK : CH0_CHECK;
CH2_BEGIN:
read_state_next <= CH2_READ;
CH2_READ:
if(rd_burst_finish)
read_state_next <= CH2_END;
else
read_state_next <= CH2_READ;
CH2_END:
read_state_next <= (PINTS!=3)? CH3_CHECK : CH0_CHECK;
CH3_CHECK:
if(ch3_rd_burst_req && ch3_rd_burst_len != 10'd0)
read_state_next <= CH3_BEGIN;
else
read_state_next <= (PINTS!=4)? CH4_CHECK : CH0_CHECK;
CH3_BEGIN:
read_state_next <= CH3_READ;
CH3_READ:
if(rd_burst_finish)
read_state_next <= CH3_END;
else
read_state_next <= CH3_READ;
CH3_END:
read_state_next <= (PINTS!=4)? CH4_CHECK : CH0_CHECK;
CH4_CHECK:
if(ch4_rd_burst_req && ch4_rd_burst_len != 10'd0)
read_state_next <= CH4_BEGIN;
else
read_state_next <= (PINTS!=5)? CH5_CHECK : CH0_CHECK;
CH4_BEGIN:
read_state_next <= CH4_READ;
CH4_READ:
if(rd_burst_finish)
read_state_next <= CH4_END;
else
read_state_next <= CH4_READ;
CH4_END:
read_state_next <= (PINTS!=5)? CH5_CHECK : CH0_CHECK;
CH5_CHECK:
if(ch5_rd_burst_req && ch5_rd_burst_len != 10'd0)
read_state_next <= CH5_BEGIN;
else
read_state_next <= (PINTS!=6)? CH6_CHECK : CH0_CHECK;
CH5_BEGIN:
read_state_next <= CH5_READ;
CH5_READ:
if(rd_burst_finish)
read_state_next <= CH5_END;
else
read_state_next <= CH5_READ;
CH5_END:
read_state_next <= (PINTS!=6)? CH6_CHECK : CH0_CHECK;
CH6_CHECK:
if(ch6_rd_burst_req && ch6_rd_burst_len != 10'd0)
read_state_next <= CH6_BEGIN;
else
read_state_next <= (PINTS!=7)? CH7_CHECK : CH0_CHECK;
CH6_BEGIN:
read_state_next <= CH6_READ;
CH6_READ:
if(rd_burst_finish)
read_state_next <= CH6_END;
else
read_state_next <= CH6_READ;
CH6_END:
read_state_next <= (PINTS!=7)? CH7_CHECK : CH0_CHECK;
CH7_CHECK:
if(ch7_rd_burst_req && ch7_rd_burst_len != 10'd0)
read_state_next <= CH7_BEGIN;
else
read_state_next <= CH0_CHECK;
CH7_BEGIN:
read_state_next <= CH7_READ;
CH7_READ:
if(rd_burst_finish)
read_state_next <= CH7_END;
else
read_state_next <= CH7_READ;
CH7_END:
read_state_next <= CH0_CHECK;
default:
read_state_next <= IDLE;
endcase
end
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
begin
rd_burst_len <= 10'd0;
rd_burst_addr <= {ADDR_BITS{1'b0}};
end
else
begin
case(read_state)
CH0_BEGIN:
begin
rd_burst_len <= ch0_rd_burst_len;
rd_burst_addr <= ch0_rd_burst_addr;
end
CH1_BEGIN:
begin
rd_burst_len <= ch1_rd_burst_len;
rd_burst_addr <= ch1_rd_burst_addr;
end
CH2_BEGIN:
begin
rd_burst_len <= ch2_rd_burst_len;
rd_burst_addr <= ch2_rd_burst_addr;
end
CH3_BEGIN:
begin
rd_burst_len <= ch3_rd_burst_len;
rd_burst_addr <= ch3_rd_burst_addr;
end
CH4_BEGIN:
begin
rd_burst_len <= ch4_rd_burst_len;
rd_burst_addr <= ch4_rd_burst_addr;
end
CH5_BEGIN:
begin
rd_burst_len <= ch5_rd_burst_len;
rd_burst_addr <= ch5_rd_burst_addr;
end
CH6_BEGIN:
begin
rd_burst_len <= ch6_rd_burst_len;
rd_burst_addr <= ch6_rd_burst_addr;
end
CH7_BEGIN:
begin
rd_burst_len <= ch7_rd_burst_len;
rd_burst_addr <= ch7_rd_burst_addr;
end
default:
begin
rd_burst_len <= rd_burst_len;
rd_burst_addr <= rd_burst_addr;
end
endcase
end
end
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
rd_burst_req <= 1'b0;
else if(read_state == CH0_BEGIN || read_state == CH1_BEGIN || read_state == CH2_BEGIN || read_state == CH3_BEGIN ||
read_state == CH4_BEGIN || read_state == CH5_BEGIN || read_state == CH6_BEGIN || read_state == CH7_BEGIN)
rd_burst_req <= 1'b1;
else if(rd_burst_data_valid || read_state == CH0_CHECK || read_state == CH1_CHECK
|| read_state == CH2_CHECK || read_state == CH3_CHECK
|| read_state == CH4_BEGIN || read_state == CH5_BEGIN
|| read_state == CH6_BEGIN || read_state == CH7_BEGIN)
rd_burst_req <= 1'b0;
else
rd_burst_req <= rd_burst_req;
end
assign ch0_rd_burst_finish = (read_state == CH0_END);
assign ch1_rd_burst_finish = (read_state == CH1_END);
assign ch2_rd_burst_finish = (read_state == CH2_END);
assign ch3_rd_burst_finish = (read_state == CH3_END);
assign ch0_rd_burst_data_valid = (read_state == CH0_READ || read_state == CH0_END) ? rd_burst_data_valid : 1'b0;
assign ch1_rd_burst_data_valid = (read_state == CH1_READ || read_state == CH1_END) ? rd_burst_data_valid : 1'b0;
assign ch2_rd_burst_data_valid = (read_state == CH2_READ || read_state == CH2_END) ? rd_burst_data_valid : 1'b0;
assign ch3_rd_burst_data_valid = (read_state == CH3_READ || read_state == CH3_END) ? rd_burst_data_valid : 1'b0;
assign ch0_rd_burst_data = (read_state == CH0_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch1_rd_burst_data = (read_state == CH1_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch2_rd_burst_data = (read_state == CH2_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch3_rd_burst_data = (read_state == CH3_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch4_rd_burst_finish = (read_state == CH4_END);
assign ch5_rd_burst_finish = (read_state == CH5_END);
assign ch6_rd_burst_finish = (read_state == CH6_END);
assign ch7_rd_burst_finish = (read_state == CH7_END);
assign ch4_rd_burst_data_valid = (read_state == CH4_READ || read_state == CH4_END) ? rd_burst_data_valid : 1'b0;
assign ch5_rd_burst_data_valid = (read_state == CH5_READ || read_state == CH5_END) ? rd_burst_data_valid : 1'b0;
assign ch6_rd_burst_data_valid = (read_state == CH6_READ || read_state == CH6_END) ? rd_burst_data_valid : 1'b0;
assign ch7_rd_burst_data_valid = (read_state == CH7_READ || read_state == CH7_END) ? rd_burst_data_valid : 1'b0;
assign ch4_rd_burst_data = (read_state == CH4_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch5_rd_burst_data = (read_state == CH5_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch6_rd_burst_data = (read_state == CH6_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch7_rd_burst_data = (read_state == CH7_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
endmodule | module mem_read_arbi_verb
#(
parameter MEM_DATA_BITS = 32,
parameter ADDR_BITS = 25,
parameter PINTS = 8
)
(
input rst_n,
input mem_clk,
input ch0_rd_burst_req,
input[9:0] ch0_rd_burst_len,
input[ADDR_BITS-1:0] ch0_rd_burst_addr,
output ch0_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch0_rd_burst_data,
output ch0_rd_burst_finish,
input ch1_rd_burst_req,
input[9:0] ch1_rd_burst_len,
input[ADDR_BITS-1:0] ch1_rd_burst_addr,
output ch1_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch1_rd_burst_data,
output ch1_rd_burst_finish,
input ch2_rd_burst_req,
input[9:0] ch2_rd_burst_len,
input[ADDR_BITS-1:0] ch2_rd_burst_addr,
output ch2_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch2_rd_burst_data,
output ch2_rd_burst_finish,
input ch3_rd_burst_req,
input[9:0] ch3_rd_burst_len,
input[ADDR_BITS-1:0] ch3_rd_burst_addr,
output ch3_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch3_rd_burst_data,
output ch3_rd_burst_finish,
input ch4_rd_burst_req,
input[9:0] ch4_rd_burst_len,
input[ADDR_BITS-1:0] ch4_rd_burst_addr,
output ch4_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch4_rd_burst_data,
output ch4_rd_burst_finish,
input ch5_rd_burst_req,
input[9:0] ch5_rd_burst_len,
input[ADDR_BITS-1:0] ch5_rd_burst_addr,
output ch5_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch5_rd_burst_data,
output ch5_rd_burst_finish,
input ch6_rd_burst_req,
input[9:0] ch6_rd_burst_len,
input[ADDR_BITS-1:0] ch6_rd_burst_addr,
output ch6_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch6_rd_burst_data,
output ch6_rd_burst_finish,
input ch7_rd_burst_req,
input[9:0] ch7_rd_burst_len,
input[ADDR_BITS-1:0] ch7_rd_burst_addr,
output ch7_rd_burst_data_valid,
output[MEM_DATA_BITS - 1:0] ch7_rd_burst_data,
output ch7_rd_burst_finish,
output reg rd_burst_req,
output reg[9:0] rd_burst_len,
output reg[ADDR_BITS-1:0] rd_burst_addr,
input rd_burst_data_valid,
input[MEM_DATA_BITS - 1:0] rd_burst_data,
input rd_burst_finish
); |
reg[6:0] read_state = 7'd0;
reg[6:0] read_state_next = 7'd0;
reg[15:0] cnt_timer = 15'd0;
localparam IDLE = 6'd0;
localparam CH0_CHECK = 7'd1;
localparam CH0_BEGIN = 7'd2;
localparam CH0_READ = 7'd3;
localparam CH0_END = 7'd4;
localparam CH1_CHECK = 7'd5;
localparam CH1_BEGIN = 7'd6;
localparam CH1_READ = 7'd7;
localparam CH1_END = 7'd8;
localparam CH2_CHECK = 7'd9;
localparam CH2_BEGIN = 7'd10;
localparam CH2_READ = 7'd11;
localparam CH2_END = 7'd12;
localparam CH3_CHECK = 7'd13;
localparam CH3_BEGIN = 7'd14;
localparam CH3_READ = 7'd15;
localparam CH3_END = 7'd16;
localparam CH4_CHECK = 7'd1+7'd16;
localparam CH4_BEGIN = 7'd2+7'd16;
localparam CH4_READ = 7'd3+7'd16;
localparam CH4_END = 7'd4+7'd16;
localparam CH5_CHECK = 6'd5+7'd16;
localparam CH5_BEGIN = 6'd6+7'd16;
localparam CH5_READ = 6'd7+7'd16;
localparam CH5_END = 6'd8+7'd16;
localparam CH6_CHECK = 6'd9 +7'd16;
localparam CH6_BEGIN = 6'd10+7'd16;
localparam CH6_READ = 6'd11+7'd16;
localparam CH6_END = 6'd12+7'd16;
localparam CH7_CHECK = 6'd13+7'd16;
localparam CH7_BEGIN = 6'd14+7'd16;
localparam CH7_READ = 6'd15+7'd16;
localparam CH7_END = 6'd16+7'd16;
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
read_state <= IDLE;
else if(cnt_timer > 16'd8000)
read_state <= IDLE;
else
read_state <= read_state_next;
end
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
cnt_timer <= 16'd0;
else if(read_state == CH0_CHECK)
cnt_timer <= 16'd0;
else
cnt_timer <= cnt_timer + 16'd1;
end
always@(*)
begin
case(read_state)
IDLE:
read_state_next <= CH0_CHECK;
CH0_CHECK:
if(ch0_rd_burst_req && ch0_rd_burst_len != 10'd0)
read_state_next <= CH0_BEGIN;
else
read_state_next <= CH1_CHECK;
CH0_BEGIN:
read_state_next <= CH0_READ;
CH0_READ:
if(rd_burst_finish)
read_state_next <= CH0_END;
else
read_state_next <= CH0_READ;
CH0_END:
read_state_next <= CH1_CHECK;
CH1_CHECK:
if(ch1_rd_burst_req && ch1_rd_burst_len != 10'd0)
read_state_next <= CH1_BEGIN;
else
read_state_next <= (PINTS!=2)? CH2_CHECK : CH0_CHECK;
CH1_BEGIN:
read_state_next <= CH1_READ;
CH1_READ:
if(rd_burst_finish)
read_state_next <= CH1_END;
else
read_state_next <= CH1_READ;
CH1_END:
read_state_next <= (PINTS!=2)? CH2_CHECK : CH0_CHECK;
CH2_CHECK:
if(ch2_rd_burst_req && ch2_rd_burst_len != 10'd0)
read_state_next <= CH2_BEGIN;
else
read_state_next <= (PINTS!=3)? CH3_CHECK : CH0_CHECK;
CH2_BEGIN:
read_state_next <= CH2_READ;
CH2_READ:
if(rd_burst_finish)
read_state_next <= CH2_END;
else
read_state_next <= CH2_READ;
CH2_END:
read_state_next <= (PINTS!=3)? CH3_CHECK : CH0_CHECK;
CH3_CHECK:
if(ch3_rd_burst_req && ch3_rd_burst_len != 10'd0)
read_state_next <= CH3_BEGIN;
else
read_state_next <= (PINTS!=4)? CH4_CHECK : CH0_CHECK;
CH3_BEGIN:
read_state_next <= CH3_READ;
CH3_READ:
if(rd_burst_finish)
read_state_next <= CH3_END;
else
read_state_next <= CH3_READ;
CH3_END:
read_state_next <= (PINTS!=4)? CH4_CHECK : CH0_CHECK;
CH4_CHECK:
if(ch4_rd_burst_req && ch4_rd_burst_len != 10'd0)
read_state_next <= CH4_BEGIN;
else
read_state_next <= (PINTS!=5)? CH5_CHECK : CH0_CHECK;
CH4_BEGIN:
read_state_next <= CH4_READ;
CH4_READ:
if(rd_burst_finish)
read_state_next <= CH4_END;
else
read_state_next <= CH4_READ;
CH4_END:
read_state_next <= (PINTS!=5)? CH5_CHECK : CH0_CHECK;
CH5_CHECK:
if(ch5_rd_burst_req && ch5_rd_burst_len != 10'd0)
read_state_next <= CH5_BEGIN;
else
read_state_next <= (PINTS!=6)? CH6_CHECK : CH0_CHECK;
CH5_BEGIN:
read_state_next <= CH5_READ;
CH5_READ:
if(rd_burst_finish)
read_state_next <= CH5_END;
else
read_state_next <= CH5_READ;
CH5_END:
read_state_next <= (PINTS!=6)? CH6_CHECK : CH0_CHECK;
CH6_CHECK:
if(ch6_rd_burst_req && ch6_rd_burst_len != 10'd0)
read_state_next <= CH6_BEGIN;
else
read_state_next <= (PINTS!=7)? CH7_CHECK : CH0_CHECK;
CH6_BEGIN:
read_state_next <= CH6_READ;
CH6_READ:
if(rd_burst_finish)
read_state_next <= CH6_END;
else
read_state_next <= CH6_READ;
CH6_END:
read_state_next <= (PINTS!=7)? CH7_CHECK : CH0_CHECK;
CH7_CHECK:
if(ch7_rd_burst_req && ch7_rd_burst_len != 10'd0)
read_state_next <= CH7_BEGIN;
else
read_state_next <= CH0_CHECK;
CH7_BEGIN:
read_state_next <= CH7_READ;
CH7_READ:
if(rd_burst_finish)
read_state_next <= CH7_END;
else
read_state_next <= CH7_READ;
CH7_END:
read_state_next <= CH0_CHECK;
default:
read_state_next <= IDLE;
endcase
end
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
begin
rd_burst_len <= 10'd0;
rd_burst_addr <= {ADDR_BITS{1'b0}};
end
else
begin
case(read_state)
CH0_BEGIN:
begin
rd_burst_len <= ch0_rd_burst_len;
rd_burst_addr <= ch0_rd_burst_addr;
end
CH1_BEGIN:
begin
rd_burst_len <= ch1_rd_burst_len;
rd_burst_addr <= ch1_rd_burst_addr;
end
CH2_BEGIN:
begin
rd_burst_len <= ch2_rd_burst_len;
rd_burst_addr <= ch2_rd_burst_addr;
end
CH3_BEGIN:
begin
rd_burst_len <= ch3_rd_burst_len;
rd_burst_addr <= ch3_rd_burst_addr;
end
CH4_BEGIN:
begin
rd_burst_len <= ch4_rd_burst_len;
rd_burst_addr <= ch4_rd_burst_addr;
end
CH5_BEGIN:
begin
rd_burst_len <= ch5_rd_burst_len;
rd_burst_addr <= ch5_rd_burst_addr;
end
CH6_BEGIN:
begin
rd_burst_len <= ch6_rd_burst_len;
rd_burst_addr <= ch6_rd_burst_addr;
end
CH7_BEGIN:
begin
rd_burst_len <= ch7_rd_burst_len;
rd_burst_addr <= ch7_rd_burst_addr;
end
default:
begin
rd_burst_len <= rd_burst_len;
rd_burst_addr <= rd_burst_addr;
end
endcase
end
end
always@(posedge mem_clk or negedge rst_n)
begin
if(~rst_n)
rd_burst_req <= 1'b0;
else if(read_state == CH0_BEGIN || read_state == CH1_BEGIN || read_state == CH2_BEGIN || read_state == CH3_BEGIN ||
read_state == CH4_BEGIN || read_state == CH5_BEGIN || read_state == CH6_BEGIN || read_state == CH7_BEGIN)
rd_burst_req <= 1'b1;
else if(rd_burst_data_valid || read_state == CH0_CHECK || read_state == CH1_CHECK
|| read_state == CH2_CHECK || read_state == CH3_CHECK
|| read_state == CH4_BEGIN || read_state == CH5_BEGIN
|| read_state == CH6_BEGIN || read_state == CH7_BEGIN)
rd_burst_req <= 1'b0;
else
rd_burst_req <= rd_burst_req;
end
assign ch0_rd_burst_finish = (read_state == CH0_END);
assign ch1_rd_burst_finish = (read_state == CH1_END);
assign ch2_rd_burst_finish = (read_state == CH2_END);
assign ch3_rd_burst_finish = (read_state == CH3_END);
assign ch0_rd_burst_data_valid = (read_state == CH0_READ || read_state == CH0_END) ? rd_burst_data_valid : 1'b0;
assign ch1_rd_burst_data_valid = (read_state == CH1_READ || read_state == CH1_END) ? rd_burst_data_valid : 1'b0;
assign ch2_rd_burst_data_valid = (read_state == CH2_READ || read_state == CH2_END) ? rd_burst_data_valid : 1'b0;
assign ch3_rd_burst_data_valid = (read_state == CH3_READ || read_state == CH3_END) ? rd_burst_data_valid : 1'b0;
assign ch0_rd_burst_data = (read_state == CH0_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch1_rd_burst_data = (read_state == CH1_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch2_rd_burst_data = (read_state == CH2_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch3_rd_burst_data = (read_state == CH3_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch4_rd_burst_finish = (read_state == CH4_END);
assign ch5_rd_burst_finish = (read_state == CH5_END);
assign ch6_rd_burst_finish = (read_state == CH6_END);
assign ch7_rd_burst_finish = (read_state == CH7_END);
assign ch4_rd_burst_data_valid = (read_state == CH4_READ || read_state == CH4_END) ? rd_burst_data_valid : 1'b0;
assign ch5_rd_burst_data_valid = (read_state == CH5_READ || read_state == CH5_END) ? rd_burst_data_valid : 1'b0;
assign ch6_rd_burst_data_valid = (read_state == CH6_READ || read_state == CH6_END) ? rd_burst_data_valid : 1'b0;
assign ch7_rd_burst_data_valid = (read_state == CH7_READ || read_state == CH7_END) ? rd_burst_data_valid : 1'b0;
assign ch4_rd_burst_data = (read_state == CH4_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch5_rd_burst_data = (read_state == CH5_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch6_rd_burst_data = (read_state == CH6_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
assign ch7_rd_burst_data = (read_state == CH7_READ) ? rd_burst_data : {MEM_DATA_BITS{1'd0}};
endmodule | 5 |
138,457 | data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v | 83,862,729 | in_fifo_line_by_line.v | v | 390 | 83 | [] | [] | [] | [(12, 389)] | null | null | 1: b'%Error: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:49: Cannot find file containing module: \'cross_clk_sync\'\ncross_clk_sync #(\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83862729/data_stream_in,data/full_repos/permissive/83862729/cross_clk_sync\n data/full_repos/permissive/83862729/data_stream_in,data/full_repos/permissive/83862729/cross_clk_sync.v\n data/full_repos/permissive/83862729/data_stream_in,data/full_repos/permissive/83862729/cross_clk_sync.sv\n cross_clk_sync\n cross_clk_sync.v\n cross_clk_sync.sv\n obj_dir/cross_clk_sync\n obj_dir/cross_clk_sync.v\n obj_dir/cross_clk_sync.sv\n%Error: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:59: Cannot find file containing module: \'cross_clk_sync\'\ncross_clk_sync #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:100: Cannot find file containing module: \'latch_data\'\nlatch_data #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:108: Cannot find file containing module: \'latch_data\'\nlatch_data #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:116: Cannot find file containing module: \'latch_data\'\nlatch_data #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:132: Cannot find file containing module: \'vin_frame_buffer_ctrl_fifo_256_64\'\nvin_frame_buffer_ctrl_fifo_256_64 vin_frame_buffer_ctrl_fifo_256_64_m0(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:170: Operator GTE expects 24 bits on the LHS, but LHS\'s VARREF \'rdusedw\' generates 8 bits.\n : ... In instance in_fifo_line_by_line\n else if(pro_short) fifo_get_enough_data <= (rdusedw >= sync_line_length);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:171: Operator GTE expects 24 bits on the LHS, but LHS\'s VARREF \'rdusedw\' generates 8 bits.\n : ... In instance in_fifo_line_by_line\n else if(pro_tail) fifo_get_enough_data <= (rdusedw >= remain_cnt);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:291: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n : ... In instance in_fifo_line_by_line\n address <= 10\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:310: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s VARREF \'col_arigen\' generates 12 bits.\n : ... In instance in_fifo_line_by_line\n address <= sync_baseaddr + (col_arigen << DETAL);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:318: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance in_fifo_line_by_line\n address <= {address[ADDR_BITS-1:DETAL],offsize_addr} + (1\'b1<<DETAL);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:320: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance in_fifo_line_by_line\n address <= {address[ADDR_BITS-1:DETAL],offsize_addr} - (1\'b1<<DETAL);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83862729/data_stream_in/in_fifo_line_by_line.v:321: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance in_fifo_line_by_line\n else address <= {address[ADDR_BITS-1:DETAL],offsize_addr} + (1\'b1<<DETAL);\n ^~\n%Error: Exiting due to 6 error(s), 7 warning(s)\n' | 302,388 | module | module in_fifo_line_by_line #(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter FIFO_DEPTH = 256,
parameter BURST_LEN = 128,
parameter DETAL = 8,
parameter FLIPPING = "FALSE"
)(
input inclk,
input [ADDR_BITS-1:0] baseaddr,
input loadbase,
input [23:0] ddr_line_length,
input [11:0] ddr_col_length,
output fifo_empty,
input arst_fifo,
input [MEM_DATA_BITS - 1:0] indata,
input wr_en,
input mem_clk,
input mem_rst_n,
output wr_burst_req,
output[9:0] wr_burst_len,
output[ADDR_BITS-1:0] wr_burst_addr,
input wr_burst_data_req,
output[MEM_DATA_BITS - 1:0] wr_burst_data,
input wr_burst_finish
);
wire sync_loadbase;
wire[ADDR_BITS-1:0] sync_baseaddr;
wire[23:0] sync_line_length;
wire sync_fifo_empty;
wire afifo_empty;
wire[11:0] sync_column;
cross_clk_sync #(
.DSIZE (1)
)cross_clk_load_false_path(
mem_clk,
mem_rst_n,
loadbase,
sync_loadbase
);
cross_clk_sync #(
.DSIZE (1)
)cross_clk_empty(
inclk,
1'b1,
afifo_empty,
sync_fifo_empty
);
latch_data #(
.DSIZE (ADDR_BITS)
)latch_addr(
.enable (loadbase ),
.in (baseaddr ),
.out (sync_baseaddr )
);
latch_data #(
.DSIZE (24)
)latch_length(
.enable (loadbase ),
.in (ddr_line_length ),
.out (sync_line_length )
);
latch_data #(
.DSIZE (12)
)latch_col_length(
.enable (loadbase ),
.in (ddr_col_length ),
.out (sync_column )
);
assign fifo_empty = sync_fifo_empty;
localparam DW = (FIFO_DEPTH == 256)? 8 : ( (FIFO_DEPTH == 512)? 9 : 8) ;
wire[DW-1:0] rdusedw,wrusedw;
generate
if(FIFO_DEPTH == 256)
vin_frame_buffer_ctrl_fifo_256_64 vin_frame_buffer_ctrl_fifo_256_64_m0(
.aclr (arst_fifo),
.data (indata),
.rdclk (mem_clk),
.rdreq (wr_burst_data_req),
.wrclk (inclk),
.wrreq (wr_en),
.q (wr_burst_data),
.rdempty (afifo_empty),
.rdusedw (rdusedw),
.wrfull (),
.wrusedw (wrusedw));
else if(FIFO_DEPTH == 512)
frame_buffer_ctrl_fifo_512_64 frame_buffer_ctrl_fifo_512_64_m0(
.aclr (arst_fifo),
.data (indata),
.rdclk (mem_clk),
.rdreq (wr_burst_data_req),
.wrclk (inclk),
.wrreq (wr_en),
.q (wr_burst_data),
.rdempty (afifo_empty),
.rdusedw (rdusedw),
.wrfull (),
.wrusedw (wrusedw));
endgenerate
reg pro_short;
reg pro_tail;
reg [23:0] remain_cnt;
reg line_enough;
reg fifo_get_enough_data;
always@(posedge mem_clk,negedge mem_rst_n)
if(~mem_rst_n) fifo_get_enough_data <= 1'b0;
else if(pro_short) fifo_get_enough_data <= (rdusedw >= sync_line_length);
else if(pro_tail) fifo_get_enough_data <= (rdusedw >= remain_cnt);
else fifo_get_enough_data <= (rdusedw >= BURST_LEN) && !afifo_empty;
reg [4:0] cstate,nstate;
localparam IDLE = 5'd0 ,
FRAME = 5'd1 ,
LINE_START = 5'd2 ,
REQ_WAIT = 5'd3 ,
REQING = 5'd4 ,
BURSTING = 5'd5 ,
BURST_END = 5'd6 ,
JUMP_TAIL = 5'd7 ,
TAIL_WAIT = 5'd8 ,
REQ_TAIL = 5'd9 ,
BURST_TAIL = 5'd10 ,
TAIL_END = 5'd11 ,
SHORT_WAIT = 5'd12 ,
REQ_SHORT = 5'd13 ,
BURST_SHORT = 5'd14 ,
SHORT_END = 5'd15 ,
LINE_END = 5'd16 ,
FRAME_END = 5'd17 ,
NOP = 5'd19 ;
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n) cstate <= NOP;
else if(sync_loadbase)
cstate <= IDLE;
else cstate <= nstate;
end
always@(*)
case(cstate)
IDLE: nstate = FRAME;
FRAME: nstate = LINE_START;
LINE_START:if(pro_short) nstate = SHORT_WAIT; else nstate = REQ_WAIT;
REQ_WAIT:if(fifo_get_enough_data) nstate = REQING; else nstate = REQ_WAIT;
REQING: if(wr_burst_data_req) nstate = BURSTING; else nstate = REQING;
BURSTING:if(wr_burst_finish) nstate = BURST_END; else nstate = BURSTING;
BURST_END: nstate = JUMP_TAIL;
JUMP_TAIL:if(pro_tail) nstate = TAIL_WAIT; else nstate = REQ_WAIT;
TAIL_WAIT:if(fifo_get_enough_data) nstate = REQ_TAIL; else nstate = TAIL_WAIT;
REQ_TAIL:if(wr_burst_data_req) nstate = BURST_TAIL; else nstate = REQ_TAIL;
BURST_TAIL:if(wr_burst_finish) nstate = TAIL_END; else nstate = BURST_TAIL;
TAIL_END: nstate = LINE_END;
SHORT_WAIT:if(fifo_get_enough_data) nstate = REQ_SHORT; else nstate = SHORT_WAIT;
REQ_SHORT:if(wr_burst_data_req) nstate = BURST_SHORT; else nstate = REQ_SHORT;
BURST_SHORT:if(wr_burst_finish) nstate = SHORT_END; else nstate = BURST_SHORT;
SHORT_END: nstate = LINE_END;
LINE_END:if(line_enough) nstate = FRAME_END; else nstate = LINE_START;
FRAME_END: nstate = FRAME_END;
default: nstate = FRAME_END;
endcase
reg burst_req;
reg [9:0] burst_length;
reg [ADDR_BITS-1:0] burst_addr;
reg [ADDR_BITS-1:0] address;
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
burst_req <= 1'b0;
burst_length <= 10'd0;
burst_addr <= {ADDR_BITS{1'b0}};
end else begin
case(nstate)
FRAME:begin
burst_req <= 1'b0;
burst_length <= 10'd0;
burst_addr <= {ADDR_BITS{1'b0}};
end
REQING:begin
burst_req <= 1'b1;
burst_length <= BURST_LEN;
burst_addr <= address;
end
BURSTING:begin
burst_req <= 1'b0;
end
REQ_TAIL:begin
burst_req <= 1'b1;
burst_length <= remain_cnt[9:0];
burst_addr <= address;
end
BURST_TAIL:begin
burst_req <= 1'b0;
end
REQ_SHORT:begin
burst_req <= 1'b1;
burst_length <= remain_cnt[9:0];
burst_addr <= address;
end
BURST_SHORT:begin
burst_req <= 1'b0;
end
BURST_END,TAIL_END,SHORT_END:begin
burst_req <= 1'b0;
end
default:;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin:GEN_ADDR_BLOCK
reg [DETAL-1:0] offsize_addr;
reg [11:0] col_arigen;
if(~mem_rst_n)begin
address <= 10'd0;
offsize_addr <= {DETAL{1'b0}};
col_arigen <= 12'd0;
end else begin
col_arigen <= sync_column-1'b1;
case(nstate)
FRAME:begin
offsize_addr <= sync_baseaddr[DETAL-1:0];
if(FLIPPING == "FALSE")
address <= sync_baseaddr;
else if(FLIPPING == "TRUE")
address <= sync_baseaddr + (col_arigen << DETAL);
else address <= sync_baseaddr;
end
BURST_END: address <= address + BURST_LEN;
TAIL_END: address <= address;
SHORT_END: address <= address;
LINE_END:begin
if(FLIPPING == "FALSE")
address <= {address[ADDR_BITS-1:DETAL],offsize_addr} + (1'b1<<DETAL);
else if(FLIPPING == "TRUE")
address <= {address[ADDR_BITS-1:DETAL],offsize_addr} - (1'b1<<DETAL);
else address <= {address[ADDR_BITS-1:DETAL],offsize_addr} + (1'b1<<DETAL);
end
default:;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
pro_short <= 1'b0;
end else begin
case(nstate)
FRAME: pro_short <= sync_line_length <= BURST_LEN;
default: pro_short <= pro_short;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
remain_cnt <= 24'hFFFF_FF;
end else begin
case(nstate)
FRAME: remain_cnt <= sync_line_length;
BURST_END: remain_cnt <= remain_cnt - BURST_LEN;
TAIL_END,SHORT_END,LINE_END:
remain_cnt <= sync_line_length;
default:;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
pro_tail <= 1'b0;
end else begin
case(nstate)
FRAME,LINE_START,TAIL_END,LINE_END:
pro_tail <= 1'b0;
BURST_END,JUMP_TAIL:
pro_tail <= remain_cnt <= BURST_LEN;
default: pro_tail <= pro_tail;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin:GEN_COL_CNT
reg [11:0] col_cnt;
reg [11:0] lock_col;
if(~mem_rst_n)begin
col_cnt <= 12'd0;
line_enough <= 1'b0;
lock_col <= 12'd0;
end else begin
lock_col <= sync_loadbase? sync_column : lock_col;
line_enough <= col_cnt >= (lock_col - 1'b1);
case(nstate)
IDLE,FRAME_END,FRAME:
col_cnt <= 12'd0;
LINE_END: col_cnt <= col_cnt + 1'b1;
default:;
endcase
end end
assign wr_burst_req = burst_req;
assign wr_burst_len = burst_length;
assign wr_burst_addr = burst_addr;
endmodule | module in_fifo_line_by_line #(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter FIFO_DEPTH = 256,
parameter BURST_LEN = 128,
parameter DETAL = 8,
parameter FLIPPING = "FALSE"
)(
input inclk,
input [ADDR_BITS-1:0] baseaddr,
input loadbase,
input [23:0] ddr_line_length,
input [11:0] ddr_col_length,
output fifo_empty,
input arst_fifo,
input [MEM_DATA_BITS - 1:0] indata,
input wr_en,
input mem_clk,
input mem_rst_n,
output wr_burst_req,
output[9:0] wr_burst_len,
output[ADDR_BITS-1:0] wr_burst_addr,
input wr_burst_data_req,
output[MEM_DATA_BITS - 1:0] wr_burst_data,
input wr_burst_finish
); |
wire sync_loadbase;
wire[ADDR_BITS-1:0] sync_baseaddr;
wire[23:0] sync_line_length;
wire sync_fifo_empty;
wire afifo_empty;
wire[11:0] sync_column;
cross_clk_sync #(
.DSIZE (1)
)cross_clk_load_false_path(
mem_clk,
mem_rst_n,
loadbase,
sync_loadbase
);
cross_clk_sync #(
.DSIZE (1)
)cross_clk_empty(
inclk,
1'b1,
afifo_empty,
sync_fifo_empty
);
latch_data #(
.DSIZE (ADDR_BITS)
)latch_addr(
.enable (loadbase ),
.in (baseaddr ),
.out (sync_baseaddr )
);
latch_data #(
.DSIZE (24)
)latch_length(
.enable (loadbase ),
.in (ddr_line_length ),
.out (sync_line_length )
);
latch_data #(
.DSIZE (12)
)latch_col_length(
.enable (loadbase ),
.in (ddr_col_length ),
.out (sync_column )
);
assign fifo_empty = sync_fifo_empty;
localparam DW = (FIFO_DEPTH == 256)? 8 : ( (FIFO_DEPTH == 512)? 9 : 8) ;
wire[DW-1:0] rdusedw,wrusedw;
generate
if(FIFO_DEPTH == 256)
vin_frame_buffer_ctrl_fifo_256_64 vin_frame_buffer_ctrl_fifo_256_64_m0(
.aclr (arst_fifo),
.data (indata),
.rdclk (mem_clk),
.rdreq (wr_burst_data_req),
.wrclk (inclk),
.wrreq (wr_en),
.q (wr_burst_data),
.rdempty (afifo_empty),
.rdusedw (rdusedw),
.wrfull (),
.wrusedw (wrusedw));
else if(FIFO_DEPTH == 512)
frame_buffer_ctrl_fifo_512_64 frame_buffer_ctrl_fifo_512_64_m0(
.aclr (arst_fifo),
.data (indata),
.rdclk (mem_clk),
.rdreq (wr_burst_data_req),
.wrclk (inclk),
.wrreq (wr_en),
.q (wr_burst_data),
.rdempty (afifo_empty),
.rdusedw (rdusedw),
.wrfull (),
.wrusedw (wrusedw));
endgenerate
reg pro_short;
reg pro_tail;
reg [23:0] remain_cnt;
reg line_enough;
reg fifo_get_enough_data;
always@(posedge mem_clk,negedge mem_rst_n)
if(~mem_rst_n) fifo_get_enough_data <= 1'b0;
else if(pro_short) fifo_get_enough_data <= (rdusedw >= sync_line_length);
else if(pro_tail) fifo_get_enough_data <= (rdusedw >= remain_cnt);
else fifo_get_enough_data <= (rdusedw >= BURST_LEN) && !afifo_empty;
reg [4:0] cstate,nstate;
localparam IDLE = 5'd0 ,
FRAME = 5'd1 ,
LINE_START = 5'd2 ,
REQ_WAIT = 5'd3 ,
REQING = 5'd4 ,
BURSTING = 5'd5 ,
BURST_END = 5'd6 ,
JUMP_TAIL = 5'd7 ,
TAIL_WAIT = 5'd8 ,
REQ_TAIL = 5'd9 ,
BURST_TAIL = 5'd10 ,
TAIL_END = 5'd11 ,
SHORT_WAIT = 5'd12 ,
REQ_SHORT = 5'd13 ,
BURST_SHORT = 5'd14 ,
SHORT_END = 5'd15 ,
LINE_END = 5'd16 ,
FRAME_END = 5'd17 ,
NOP = 5'd19 ;
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n) cstate <= NOP;
else if(sync_loadbase)
cstate <= IDLE;
else cstate <= nstate;
end
always@(*)
case(cstate)
IDLE: nstate = FRAME;
FRAME: nstate = LINE_START;
LINE_START:if(pro_short) nstate = SHORT_WAIT; else nstate = REQ_WAIT;
REQ_WAIT:if(fifo_get_enough_data) nstate = REQING; else nstate = REQ_WAIT;
REQING: if(wr_burst_data_req) nstate = BURSTING; else nstate = REQING;
BURSTING:if(wr_burst_finish) nstate = BURST_END; else nstate = BURSTING;
BURST_END: nstate = JUMP_TAIL;
JUMP_TAIL:if(pro_tail) nstate = TAIL_WAIT; else nstate = REQ_WAIT;
TAIL_WAIT:if(fifo_get_enough_data) nstate = REQ_TAIL; else nstate = TAIL_WAIT;
REQ_TAIL:if(wr_burst_data_req) nstate = BURST_TAIL; else nstate = REQ_TAIL;
BURST_TAIL:if(wr_burst_finish) nstate = TAIL_END; else nstate = BURST_TAIL;
TAIL_END: nstate = LINE_END;
SHORT_WAIT:if(fifo_get_enough_data) nstate = REQ_SHORT; else nstate = SHORT_WAIT;
REQ_SHORT:if(wr_burst_data_req) nstate = BURST_SHORT; else nstate = REQ_SHORT;
BURST_SHORT:if(wr_burst_finish) nstate = SHORT_END; else nstate = BURST_SHORT;
SHORT_END: nstate = LINE_END;
LINE_END:if(line_enough) nstate = FRAME_END; else nstate = LINE_START;
FRAME_END: nstate = FRAME_END;
default: nstate = FRAME_END;
endcase
reg burst_req;
reg [9:0] burst_length;
reg [ADDR_BITS-1:0] burst_addr;
reg [ADDR_BITS-1:0] address;
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
burst_req <= 1'b0;
burst_length <= 10'd0;
burst_addr <= {ADDR_BITS{1'b0}};
end else begin
case(nstate)
FRAME:begin
burst_req <= 1'b0;
burst_length <= 10'd0;
burst_addr <= {ADDR_BITS{1'b0}};
end
REQING:begin
burst_req <= 1'b1;
burst_length <= BURST_LEN;
burst_addr <= address;
end
BURSTING:begin
burst_req <= 1'b0;
end
REQ_TAIL:begin
burst_req <= 1'b1;
burst_length <= remain_cnt[9:0];
burst_addr <= address;
end
BURST_TAIL:begin
burst_req <= 1'b0;
end
REQ_SHORT:begin
burst_req <= 1'b1;
burst_length <= remain_cnt[9:0];
burst_addr <= address;
end
BURST_SHORT:begin
burst_req <= 1'b0;
end
BURST_END,TAIL_END,SHORT_END:begin
burst_req <= 1'b0;
end
default:;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin:GEN_ADDR_BLOCK
reg [DETAL-1:0] offsize_addr;
reg [11:0] col_arigen;
if(~mem_rst_n)begin
address <= 10'd0;
offsize_addr <= {DETAL{1'b0}};
col_arigen <= 12'd0;
end else begin
col_arigen <= sync_column-1'b1;
case(nstate)
FRAME:begin
offsize_addr <= sync_baseaddr[DETAL-1:0];
if(FLIPPING == "FALSE")
address <= sync_baseaddr;
else if(FLIPPING == "TRUE")
address <= sync_baseaddr + (col_arigen << DETAL);
else address <= sync_baseaddr;
end
BURST_END: address <= address + BURST_LEN;
TAIL_END: address <= address;
SHORT_END: address <= address;
LINE_END:begin
if(FLIPPING == "FALSE")
address <= {address[ADDR_BITS-1:DETAL],offsize_addr} + (1'b1<<DETAL);
else if(FLIPPING == "TRUE")
address <= {address[ADDR_BITS-1:DETAL],offsize_addr} - (1'b1<<DETAL);
else address <= {address[ADDR_BITS-1:DETAL],offsize_addr} + (1'b1<<DETAL);
end
default:;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
pro_short <= 1'b0;
end else begin
case(nstate)
FRAME: pro_short <= sync_line_length <= BURST_LEN;
default: pro_short <= pro_short;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
remain_cnt <= 24'hFFFF_FF;
end else begin
case(nstate)
FRAME: remain_cnt <= sync_line_length;
BURST_END: remain_cnt <= remain_cnt - BURST_LEN;
TAIL_END,SHORT_END,LINE_END:
remain_cnt <= sync_line_length;
default:;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin
if(~mem_rst_n)begin
pro_tail <= 1'b0;
end else begin
case(nstate)
FRAME,LINE_START,TAIL_END,LINE_END:
pro_tail <= 1'b0;
BURST_END,JUMP_TAIL:
pro_tail <= remain_cnt <= BURST_LEN;
default: pro_tail <= pro_tail;
endcase
end end
always@(posedge mem_clk,negedge mem_rst_n)begin:GEN_COL_CNT
reg [11:0] col_cnt;
reg [11:0] lock_col;
if(~mem_rst_n)begin
col_cnt <= 12'd0;
line_enough <= 1'b0;
lock_col <= 12'd0;
end else begin
lock_col <= sync_loadbase? sync_column : lock_col;
line_enough <= col_cnt >= (lock_col - 1'b1);
case(nstate)
IDLE,FRAME_END,FRAME:
col_cnt <= 12'd0;
LINE_END: col_cnt <= col_cnt + 1'b1;
default:;
endcase
end end
assign wr_burst_req = burst_req;
assign wr_burst_len = burst_length;
assign wr_burst_addr = burst_addr;
endmodule | 5 |
138,459 | data/full_repos/permissive/83862729/data_stream_in/vin_process_discontinuous.v | 83,862,729 | vin_process_discontinuous.v | v | 183 | 49 | [] | [] | [] | [(13, 182)] | null | null | 1: b"%Error: data/full_repos/permissive/83862729/data_stream_in/vin_process_discontinuous.v:55: Cannot find file containing module: 'video24bit_in_discontinuous'\nvideo24bit_in_discontinuous #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83862729/data_stream_in,data/full_repos/permissive/83862729/video24bit_in_discontinuous\n data/full_repos/permissive/83862729/data_stream_in,data/full_repos/permissive/83862729/video24bit_in_discontinuous.v\n data/full_repos/permissive/83862729/data_stream_in,data/full_repos/permissive/83862729/video24bit_in_discontinuous.sv\n video24bit_in_discontinuous\n video24bit_in_discontinuous.v\n video24bit_in_discontinuous.sv\n obj_dir/video24bit_in_discontinuous\n obj_dir/video24bit_in_discontinuous.v\n obj_dir/video24bit_in_discontinuous.sv\n%Error: data/full_repos/permissive/83862729/data_stream_in/vin_process_discontinuous.v:153: Cannot find file containing module: 'in_fifo_line_by_line'\nin_fifo_line_by_line #(\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,394 | module | module vin_process_discontinuous #(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter DSIZE = 24,
parameter FIFO_DEPTH = 256,
parameter DETAL = 8,
parameter FLIPPING = "FALSE"
)(
input pclk,
input prst_n,
input vsync,
input de,
output wait_for_data,
input [DSIZE-1:0] indata,
input [ADDR_BITS-1:0] baseaddr,
input [11:0] video_width,
input [11:0] video_height,
input mem_clk,
input mem_rst_n,
output wr_burst_req,
output[9:0] wr_burst_len,
output[ADDR_BITS-1:0] wr_burst_addr,
input wr_burst_data_req,
output[MEM_DATA_BITS - 1:0] wr_burst_data,
input wr_burst_finish
);
wire wr_fifo_en ;
wire[63:0] wr_data ;
wire sync_fifo_empty ;
wire arst_fifo ;
wire loadbase ;
wire[ADDR_BITS-1:0] ddr_baseaddr;
wire[23:0] ddr_line_length;
wire[11:0] ddr_col_length;
generate
if(DSIZE == 24)
video24bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
else if (DSIZE == 8)
video8bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
else if (DSIZE == 16)
video16bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
else if(DSIZE == 32)
video32bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
endgenerate
in_fifo_line_by_line #(
.BURST_LEN (128 ),
.MEM_DATA_BITS (64 ),
.ADDR_BITS (ADDR_BITS ),
.FIFO_DEPTH (FIFO_DEPTH ),
.DETAL (DETAL ),
.FLIPPING (FLIPPING )
)in_fifo_line_by_line_inst(
.inclk (pclk ),
.baseaddr (ddr_baseaddr ),
.loadbase (loadbase ),
.fifo_empty (sync_fifo_empty ),
.arst_fifo (arst_fifo ),
.indata (wr_data ),
.wr_en (wr_fifo_en ),
.ddr_line_length (ddr_line_length ),
.ddr_col_length (ddr_col_length ),
.mem_clk (mem_clk ),
.mem_rst_n (mem_rst_n ),
.wr_burst_req (wr_burst_req ),
.wr_burst_len (wr_burst_len ),
.wr_burst_addr (wr_burst_addr ),
.wr_burst_data_req (wr_burst_data_req ),
.wr_burst_data (wr_burst_data ),
.wr_burst_finish (wr_burst_finish )
);
endmodule | module vin_process_discontinuous #(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter DSIZE = 24,
parameter FIFO_DEPTH = 256,
parameter DETAL = 8,
parameter FLIPPING = "FALSE"
)(
input pclk,
input prst_n,
input vsync,
input de,
output wait_for_data,
input [DSIZE-1:0] indata,
input [ADDR_BITS-1:0] baseaddr,
input [11:0] video_width,
input [11:0] video_height,
input mem_clk,
input mem_rst_n,
output wr_burst_req,
output[9:0] wr_burst_len,
output[ADDR_BITS-1:0] wr_burst_addr,
input wr_burst_data_req,
output[MEM_DATA_BITS - 1:0] wr_burst_data,
input wr_burst_finish
); |
wire wr_fifo_en ;
wire[63:0] wr_data ;
wire sync_fifo_empty ;
wire arst_fifo ;
wire loadbase ;
wire[ADDR_BITS-1:0] ddr_baseaddr;
wire[23:0] ddr_line_length;
wire[11:0] ddr_col_length;
generate
if(DSIZE == 24)
video24bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
else if (DSIZE == 8)
video8bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
else if (DSIZE == 16)
video16bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
else if(DSIZE == 32)
video32bit_in_discontinuous #(
.ADDR_BITS (ADDR_BITS ),
.BROADEN_LOAD ("TRUE" )
)video_in_line_by_line_inst(
.pclk (pclk ),
.prst_n (prst_n ),
.vsync (vsync ),
.de (de ),
.fifo_empty (wait_for_data ),
.indata (indata ),
.baseaddr (baseaddr ),
.video_width ({12'd0,video_width} ),
.video_height (video_height ),
.wr_fifo_en (wr_fifo_en ),
.wr_data (wr_data ),
.sync_fifo_empty (sync_fifo_empty),
.arst_fifo (arst_fifo ),
.loadbase (loadbase ),
.ddr_baseaddr (ddr_baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length )
);
endgenerate
in_fifo_line_by_line #(
.BURST_LEN (128 ),
.MEM_DATA_BITS (64 ),
.ADDR_BITS (ADDR_BITS ),
.FIFO_DEPTH (FIFO_DEPTH ),
.DETAL (DETAL ),
.FLIPPING (FLIPPING )
)in_fifo_line_by_line_inst(
.inclk (pclk ),
.baseaddr (ddr_baseaddr ),
.loadbase (loadbase ),
.fifo_empty (sync_fifo_empty ),
.arst_fifo (arst_fifo ),
.indata (wr_data ),
.wr_en (wr_fifo_en ),
.ddr_line_length (ddr_line_length ),
.ddr_col_length (ddr_col_length ),
.mem_clk (mem_clk ),
.mem_rst_n (mem_rst_n ),
.wr_burst_req (wr_burst_req ),
.wr_burst_len (wr_burst_len ),
.wr_burst_addr (wr_burst_addr ),
.wr_burst_data_req (wr_burst_data_req ),
.wr_burst_data (wr_burst_data ),
.wr_burst_finish (wr_burst_finish )
);
endmodule | 5 |
138,461 | data/full_repos/permissive/83862729/data_stream_out/out_stream_process.v | 83,862,729 | out_stream_process.v | v | 219 | 84 | [] | [] | [] | [(18, 218)] | null | null | 1: b"%Error: data/full_repos/permissive/83862729/data_stream_out/out_stream_process.v:60: Cannot find file containing module: 'video24bit_out_discontinuous_A2'\nvideo24bit_out_discontinuous_A2 #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83862729/data_stream_out,data/full_repos/permissive/83862729/video24bit_out_discontinuous_A2\n data/full_repos/permissive/83862729/data_stream_out,data/full_repos/permissive/83862729/video24bit_out_discontinuous_A2.v\n data/full_repos/permissive/83862729/data_stream_out,data/full_repos/permissive/83862729/video24bit_out_discontinuous_A2.sv\n video24bit_out_discontinuous_A2\n video24bit_out_discontinuous_A2.v\n video24bit_out_discontinuous_A2.sv\n obj_dir/video24bit_out_discontinuous_A2\n obj_dir/video24bit_out_discontinuous_A2.v\n obj_dir/video24bit_out_discontinuous_A2.sv\n%Error: data/full_repos/permissive/83862729/data_stream_out/out_stream_process.v:190: Cannot find file containing module: 'out_fifo_line_by_line'\nout_fifo_line_by_line #(\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,396 | module | module out_stream_process #(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter DSIZE = 24,
parameter FIFO_DEPTH = 256
)(
input stream_clk,
input stream_rst_n,
input stream_in_request,
input stream_in_read,
output stream_out_sof,
output stream_out_read_sync,
output stream_out_not_ready,
output[DSIZE-1:0] stream_out_data,
output stream_out_vld,
input [23:0] stream_in_length,
input [ADDR_BITS-1:0] stream_in_baseaddr,
output stream_out_req_respond,
output stream_out_req_waiting,
output stream_out_req_proc_fsh,
input mem_clk,
input mem_rst_n,
output rd_burst_req,
output[9:0] rd_burst_len,
output[ADDR_BITS-1:0] rd_burst_addr,
input rd_burst_data_valid,
input[MEM_DATA_BITS - 1:0] rd_burst_data,
input rd_burst_finish
);
wire rd_req ;
wire[63:0] rd_data ;
wire rd_data_en;
wire fifo_empty;
wire[ADDR_BITS-1:0] baseaddr ;
wire[23:0] ddr_line_length ;
wire[11:0] ddr_col_length ;
wire req_end ;
generate
if(DSIZE == 24)
video24bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
else if (DSIZE == 8)
video8bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
else if (DSIZE == 16)
video16bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
else if (DSIZE == 32)
video32bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
endgenerate
out_fifo_line_by_line #(
.BURST_LEN (100 ),
.ADDR_BITS (ADDR_BITS ),
.MEM_DATA_BITS (MEM_DATA_BITS ),
.FIFO_DEPTH (FIFO_DEPTH ),
.DETAL (16 )
)out_fifo_line_by_line_inst(
.rclk (stream_clk ),
.rst_n (stream_rst_n ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.fifo_empty (fifo_empty ),
.req_end (req_end ),
.ddr_line_length (ddr_line_length ),
.ddr_col_length (ddr_col_length ),
.mem_clk (mem_clk ),
.mem_rst_n (mem_rst_n ),
.rd_burst_req (rd_burst_req ),
.rd_burst_len (rd_burst_len ),
.rd_burst_addr (rd_burst_addr ),
.rd_burst_data_valid (rd_burst_data_valid),
.rd_burst_data (rd_burst_data ),
.rd_burst_finish (rd_burst_finish )
);
endmodule | module out_stream_process #(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 25,
parameter DSIZE = 24,
parameter FIFO_DEPTH = 256
)(
input stream_clk,
input stream_rst_n,
input stream_in_request,
input stream_in_read,
output stream_out_sof,
output stream_out_read_sync,
output stream_out_not_ready,
output[DSIZE-1:0] stream_out_data,
output stream_out_vld,
input [23:0] stream_in_length,
input [ADDR_BITS-1:0] stream_in_baseaddr,
output stream_out_req_respond,
output stream_out_req_waiting,
output stream_out_req_proc_fsh,
input mem_clk,
input mem_rst_n,
output rd_burst_req,
output[9:0] rd_burst_len,
output[ADDR_BITS-1:0] rd_burst_addr,
input rd_burst_data_valid,
input[MEM_DATA_BITS - 1:0] rd_burst_data,
input rd_burst_finish
); |
wire rd_req ;
wire[63:0] rd_data ;
wire rd_data_en;
wire fifo_empty;
wire[ADDR_BITS-1:0] baseaddr ;
wire[23:0] ddr_line_length ;
wire[11:0] ddr_col_length ;
wire req_end ;
generate
if(DSIZE == 24)
video24bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
else if (DSIZE == 8)
video8bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
else if (DSIZE == 16)
video16bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
else if (DSIZE == 32)
video32bit_out_discontinuous_A2 #(
.ADDR_BITS (25 )
)video_out_line_by_line_inst(
.pclk (stream_clk ),
.prst_n (stream_rst_n ),
.invsync (stream_in_request ),
.inhsync (1'b0 ),
.inde (stream_in_read ),
.outvsync (stream_out_sof ),
.outhsync ( ),
.outde (stream_out_read_sync ),
.out_valid (stream_out_vld ),
.outdata (stream_out_data ),
.video_width (stream_in_length ),
.video_height (12'd1 ),
.video_baseaddr (stream_in_baseaddr ),
.fifo_empty (stream_out_not_ready ),
.req_respond (stream_out_req_respond ),
.req_waiting (stream_out_req_waiting ),
.req_proc_fsh (stream_out_req_proc_fsh ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.ddr_line_length (ddr_line_length),
.ddr_col_length (ddr_col_length ),
.sync_fifo_empty (fifo_empty ),
.req_end (req_end )
);
endgenerate
out_fifo_line_by_line #(
.BURST_LEN (100 ),
.ADDR_BITS (ADDR_BITS ),
.MEM_DATA_BITS (MEM_DATA_BITS ),
.FIFO_DEPTH (FIFO_DEPTH ),
.DETAL (16 )
)out_fifo_line_by_line_inst(
.rclk (stream_clk ),
.rst_n (stream_rst_n ),
.rd_req (rd_req ),
.rd_data (rd_data ),
.rd_data_en (rd_data_en ),
.baseaddr (baseaddr ),
.fifo_empty (fifo_empty ),
.req_end (req_end ),
.ddr_line_length (ddr_line_length ),
.ddr_col_length (ddr_col_length ),
.mem_clk (mem_clk ),
.mem_rst_n (mem_rst_n ),
.rd_burst_req (rd_burst_req ),
.rd_burst_len (rd_burst_len ),
.rd_burst_addr (rd_burst_addr ),
.rd_burst_data_valid (rd_burst_data_valid),
.rd_burst_data (rd_burst_data ),
.rd_burst_finish (rd_burst_finish )
);
endmodule | 5 |
138,467 | data/full_repos/permissive/83899885/CPU/source/InterruptController.v | 83,899,885 | InterruptController.v | v | 112 | 87 | [] | [] | [] | [(1, 111)] | null | null | 1: b'%Error: data/full_repos/permissive/83899885/CPU/source/InterruptController.v:24: Cannot find file containing module: \'KeyboardReader\'\nKeyboardReader reader (\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/KeyboardReader\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/KeyboardReader.v\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/KeyboardReader.sv\n KeyboardReader\n KeyboardReader.v\n KeyboardReader.sv\n obj_dir/KeyboardReader\n obj_dir/KeyboardReader.v\n obj_dir/KeyboardReader.sv\n%Warning-WIDTH: data/full_repos/permissive/83899885/CPU/source/InterruptController.v:81: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'pressedKey\' generates 9 bits.\n : ... In instance InterruptController\n intData <= pressedKey;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83899885/CPU/source/InterruptController.v:85: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'irData\' generates 4 bits.\n : ... In instance InterruptController\n intData <= irData;\n ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 302,408 | module | module InterruptController (
input wire rst,
input wire clk,
input wire fastClk,
output reg irq,
input wire turnOffIRQ,
output reg[31:0] intAddr,
output reg[15:0] intData,
inout wire ps2CLK,
inout wire ps2DATA,
input wire[31:0] addr,
input wire re,
input wire we,
input wire[3:0] irData,
input wire irPressed,
input wire[31:0] bp0Addr, bp1Addr, bp2Addr, bp3Addr, bpAddr, keyboardAddr, irAddr,
input wire bp0En, bp1En, bp2En, bp3En, keyboardEn, irEn
);
wire[8:0] pressedKey;
wire pressed;
KeyboardReader reader (
.rst (rst),
.clk (fastClk),
.ps2CLK (ps2CLK),
.ps2DATA (ps2DATA),
.pressedKey (pressedKey),
.pressed (pressed)
);
wire isBP0 = (addr == bp0Addr) & bp0En & (re | we);
wire isBP1 = (addr == bp1Addr) & bp1En & (re | we);
wire isBP2 = (addr == bp2Addr) & bp2En & (re | we);
wire isBP3 = (addr == bp3Addr) & bp3En & (re | we);
reg keyPressedSync, irPressedSync;
reg clk0, clk1, clk2;
always @(posedge fastClk) begin
if (rst) begin
clk0 <= 0;
clk1 <= 0;
clk2 <= 0;
end
else begin
clk0 <= clk;
clk1 <= clk0;
clk2 <= clk1;
end
end
wire posedgeClk = ~clk2 & clk1;
always @(posedge clk) begin
if (rst) begin
irq <= 0;
intAddr <= 32'd0;
intData <= 16'd0;
end else if (isBP0) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd0;
end else if (isBP1) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd1;
end else if (isBP2) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd2;
end else if (isBP3) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd3;
end else if (keyPressedSync) begin
irq <= 1;
intAddr <= keyboardAddr;
intData <= pressedKey;
end else if (irPressedSync) begin
irq <= 1;
intAddr <= irAddr;
intData <= irData;
end else if (turnOffIRQ) begin
irq <= 0;
end
end
always @(posedge fastClk) begin
if (rst) begin
keyPressedSync <= 0;
end else if (pressed) begin
keyPressedSync <= 1;
end else if (posedgeClk) begin
keyPressedSync <= 0;
end
end
always @(posedge fastClk) begin
if (rst) begin
irPressedSync <= 0;
end else if (irPressed) begin
irPressedSync <= 1;
end else if (posedgeClk) begin
irPressedSync <= 0;
end
end
endmodule | module InterruptController (
input wire rst,
input wire clk,
input wire fastClk,
output reg irq,
input wire turnOffIRQ,
output reg[31:0] intAddr,
output reg[15:0] intData,
inout wire ps2CLK,
inout wire ps2DATA,
input wire[31:0] addr,
input wire re,
input wire we,
input wire[3:0] irData,
input wire irPressed,
input wire[31:0] bp0Addr, bp1Addr, bp2Addr, bp3Addr, bpAddr, keyboardAddr, irAddr,
input wire bp0En, bp1En, bp2En, bp3En, keyboardEn, irEn
); |
wire[8:0] pressedKey;
wire pressed;
KeyboardReader reader (
.rst (rst),
.clk (fastClk),
.ps2CLK (ps2CLK),
.ps2DATA (ps2DATA),
.pressedKey (pressedKey),
.pressed (pressed)
);
wire isBP0 = (addr == bp0Addr) & bp0En & (re | we);
wire isBP1 = (addr == bp1Addr) & bp1En & (re | we);
wire isBP2 = (addr == bp2Addr) & bp2En & (re | we);
wire isBP3 = (addr == bp3Addr) & bp3En & (re | we);
reg keyPressedSync, irPressedSync;
reg clk0, clk1, clk2;
always @(posedge fastClk) begin
if (rst) begin
clk0 <= 0;
clk1 <= 0;
clk2 <= 0;
end
else begin
clk0 <= clk;
clk1 <= clk0;
clk2 <= clk1;
end
end
wire posedgeClk = ~clk2 & clk1;
always @(posedge clk) begin
if (rst) begin
irq <= 0;
intAddr <= 32'd0;
intData <= 16'd0;
end else if (isBP0) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd0;
end else if (isBP1) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd1;
end else if (isBP2) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd2;
end else if (isBP3) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd3;
end else if (keyPressedSync) begin
irq <= 1;
intAddr <= keyboardAddr;
intData <= pressedKey;
end else if (irPressedSync) begin
irq <= 1;
intAddr <= irAddr;
intData <= irData;
end else if (turnOffIRQ) begin
irq <= 0;
end
end
always @(posedge fastClk) begin
if (rst) begin
keyPressedSync <= 0;
end else if (pressed) begin
keyPressedSync <= 1;
end else if (posedgeClk) begin
keyPressedSync <= 0;
end
end
always @(posedge fastClk) begin
if (rst) begin
irPressedSync <= 0;
end else if (irPressed) begin
irPressedSync <= 1;
end else if (posedgeClk) begin
irPressedSync <= 0;
end
end
endmodule | 1 |
138,469 | data/full_repos/permissive/83899885/CPU/source/RAM.v | 83,899,885 | RAM.v | v | 222 | 88 | [] | [] | [] | [(1, 221)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83899885/CPU/source/RAM.v:42: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'addrLeast\' generates 2 bits.\n : ... In instance RAM\n addrLeast? {write[7:0], write[15:8]} : write;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83899885/CPU/source/RAM.v:44: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'addrLeast\' generates 2 bits.\n : ... In instance RAM\nwire[1:0] byteenable = addrLeast? {outMask[0], outMask[1]}: outMask;\n ^\n%Error: data/full_repos/permissive/83899885/CPU/source/RAM.v:46: Cannot find file containing module: \'InstrROM\'\nInstrROM rom (\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/InstrROM\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/InstrROM.v\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/InstrROM.sv\n InstrROM\n InstrROM.v\n InstrROM.sv\n obj_dir/InstrROM\n obj_dir/InstrROM.v\n obj_dir/InstrROM.sv\n%Error: data/full_repos/permissive/83899885/CPU/source/RAM.v:54: Cannot find file containing module: \'StackRAM\'\nStackRAM ram1 (\n^~~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/source/RAM.v:65: Cannot find file containing module: \'HeapRAM\'\nHeapRAM ram2 (\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/83899885/CPU/source/RAM.v:199: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'switch\' generates 4 bits.\n : ... In instance RAM\n isSwitch? switch :\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n' | 302,410 | module | module RAM (
input wire rst,
input wire clk,
input wire[31:0] addrIn,
input wire[15:0] write,
input wire we,
output wire[15:0] read,
input wire re,
input wire[1:0] inMask,
input wire[1:0] outMask,
output wire ready,
output wire[10:0] lcdPins,
output wire[15:0] page,
input wire[3:0] switch,
output wire[31:0] bp0Addr, bp1Addr, bp2Addr, bp3Addr, bpAddr, keyboardAddr, irAddr,
output wire bp0En, bp1En, bp2En, bp3En, keyboardEn, irEn,
output wire[15:0] lcdIn
);
wire[31:0] addr = (re || we)? addrIn : 32'h00000000;
wire isStack = addr <= 32'hD000FFFF && addr >= 32'hD0000000;
wire isInstr = addr <= 32'h000FFFFF;
wire isLCD = addr == 32'hFFFF0000 || addr == 32'hFFFF0001;
wire isSwitch = addr == 32'hFFFF0002;
wire isFastMem = addr >= 32'hFFFF1000 && addr <= 32'hFFFF101F;
wire isBPRegs = addr >= 32'hFFFFF000 && addr <= 32'hFFFFF015;
wire isInt = addr >= 32'hFFFFFFF6 && addr <= 32'hFFFFFFFF;
wire isHeap = addr <= 32'h8FFFFFFF && addr >= 32'h10000000;
wire[15:0] romOut, ram1Out, ram2Out;
wire[1:0] addrLeast = {2{addr[0]}};
wire[7:0] write8 = (inMask == 2'b01)? write[7:0] :
(inMask == 2'b10)? write[15:8] :
write[7:0];
wire[15:0] write8S = outMask == (2'b01 ^ addrLeast)? {8'h00, write8} :
outMask == (2'b10 ^ addrLeast)? {write8, 8'h00} :
addrLeast? {write[7:0], write[15:8]} : write;
wire[15:0] mask = {{8{byteenable[1]}}, {8{byteenable[0]}}};
wire[1:0] byteenable = addrLeast? {outMask[0], outMask[1]}: outMask;
InstrROM rom (
.address (addr[10:1]),
.clock (clk),
.q (romOut)
);
wire[15:0] stackAddr = addr[15:0];
StackRAM ram1 (
.address (stackAddr[10:1]),
.clock (clk),
.data (write8S),
.wren (we && isStack),
.byteena(byteenable),
.q (ram1Out)
);
wire[30:0] heapAddr = addr[30:0];
HeapRAM ram2 (
.address (heapAddr[12:1]),
.clock (clk),
.data (write8S),
.wren (we && isHeap),
.byteena(byteenable),
.q (ram2Out)
);
reg[7:0] lcdData = 8'h00;
reg[2:0] lcdCtrl = 3'b000;
assign lcdPins = {lcdCtrl, lcdData};
assign lcdIn = ((write8S & mask) | ({5'b0, lcdCtrl, lcdData} & ~mask));
always @ (posedge clk) begin
if (rst) begin
lcdData <= 8'h00;
lcdCtrl <= 3'b000;
end else if (we && isLCD) begin
{lcdCtrl, lcdData} <= lcdIn[10:0];
end
end
reg[15:0] keyboardAddrHigh = 16'h0000;
reg[15:0] keyboardAddrLow = 16'h0000;
reg enKeyboard = 1;
assign keyboardAddr = {keyboardAddrHigh, keyboardAddrLow};
assign keyboardEn = enKeyboard;
reg[15:0] irAddrHigh = 16'h0000;
reg[15:0] irAddrLow = 16'h0000;
reg enIR = 1;
assign irAddr = {irAddrHigh, irAddrLow};
assign irEn = enIR;
wire[15:0] intEnWrite = (write8S & mask) | ({7'b0, enKeyboard, 7'b0, enIR} & ~mask);
always @ (posedge clk) begin
if (rst) begin
keyboardAddrHigh <= 16'h0000;
keyboardAddrLow <= 16'h0000;
enKeyboard <= 1'b0;
irAddrHigh <= 16'h0000;
irAddrLow <= 16'h0000;
enIR <= 1'b0;
end else if (we) begin
if (addr[31:1] == 31'h7FFFFFFB) begin
enIR <= |(intEnWrite[7:0]);
enKeyboard <= |(intEnWrite[15:8]);
end else if (addr[31:1] == 31'h7FFFFFFC)
irAddrLow <= (write8S & mask) | (irAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFFFFD)
irAddrHigh <= (write8S & mask) | (irAddrHigh & ~mask);
else if (addr[31:1] == 31'h7FFFFFFE)
keyboardAddrLow <= (write8S & mask) | (keyboardAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFFFFF)
keyboardAddrHigh <= (write8S & mask) | (keyboardAddrHigh & ~mask);
end
end
reg[15:0] breakPoint0High, breakPoint0Low;
reg[15:0] breakPoint1High, breakPoint1Low;
reg[15:0] breakPoint2High, breakPoint2Low;
reg[15:0] breakPoint3High, breakPoint3Low;
reg[15:0] breakPointAddrHigh, breakPointAddrLow;
reg[3:0] enBreakPoints;
assign bp0Addr = {breakPoint0High, breakPoint0Low};
assign bp1Addr = {breakPoint1High, breakPoint1Low};
assign bp2Addr = {breakPoint2High, breakPoint2Low};
assign bp3Addr = {breakPoint3High, breakPoint3Low};
assign bpAddr = {breakPointAddrHigh, breakPointAddrLow};
assign bp0En = enBreakPoints[0];
assign bp1En = enBreakPoints[1];
assign bp2En = enBreakPoints[2];
assign bp3En = enBreakPoints[3];
wire[15:0] bpEnIn = ((write8S & mask) | ({12'b0, enBreakPoints} & ~mask));
always @ (posedge clk) begin
if (rst) begin
breakPoint0High <= 16'h0000;
breakPoint0Low <= 16'h0000;
breakPoint1High <= 16'h0000;
breakPoint1Low <= 16'h0000;
breakPoint2High <= 16'h0000;
breakPoint2Low <= 16'h0000;
breakPoint3High <= 16'h0000;
breakPoint3Low <= 16'h0000;
breakPointAddrHigh <= 16'h0000;
breakPointAddrLow <= 16'h0000;
enBreakPoints <= 4'b0000;
end
else if (we) begin
if (addr[31:1] == 31'h7FFFF800)
enBreakPoints <= bpEnIn[3:0];
else if (addr[31:1] == 31'h7FFFF801)
breakPoint0Low <= (write8S & mask) | (breakPoint0Low & ~mask);
else if (addr[31:1] == 31'h7FFFF802)
breakPoint0High <= (write8S & mask) | (breakPoint0High & ~mask);
else if (addr[31:1] == 31'h7FFFF803)
breakPoint1Low <= (write8S & mask) | (breakPoint1Low & ~mask);
else if (addr[31:1] == 31'h7FFFF804)
breakPoint1High <= (write8S & mask) | (breakPoint1High & ~mask);
else if (addr[31:1] == 31'h7FFFF805)
breakPoint2Low <= (write8S & mask) | (breakPoint2Low & ~mask);
else if (addr[31:1] == 31'h7FFFF806)
breakPoint2High <= (write8S & mask) | (breakPoint2High & ~mask);
else if (addr[31:1] == 31'h7FFFF807)
breakPoint3Low <= (write8S & mask) | (breakPoint3Low & ~mask);
else if (addr[31:1] == 31'h7FFFF808)
breakPoint3High <= (write8S & mask) | (breakPoint3High & ~mask);
else if (addr[31:1] == 31'h7FFFF809)
breakPointAddrLow <= (write8S & mask) | (breakPointAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFF80A)
breakPointAddrHigh <= (write8S & mask) | (breakPointAddrHigh & ~mask);
end
end
reg[15:0] fastMem [0:14];
assign page = fastMem[0];
integer i;
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i <= 14; i = i + 1)
fastMem[i] <= 16'b0;
end else if (we && isFastMem)
fastMem[addr[4:1]] <= (write8S & mask) | (fastMem[addr[4:1]] & ~mask);;
end
wire[15:0] readNoSwap = isStack? ram1Out :
isHeap? ram2Out :
isInstr? romOut :
isSwitch? switch :
isFastMem? fastMem[addr[3:0]] :
16'h0000;
assign read = addr[0]? {readNoSwap[7:0], readNoSwap[15:8]} : readNoSwap;
reg isReading1 = 0;
reg isReading2 = 0;
reg regReady = 0;
assign ready = 1;
endmodule | module RAM (
input wire rst,
input wire clk,
input wire[31:0] addrIn,
input wire[15:0] write,
input wire we,
output wire[15:0] read,
input wire re,
input wire[1:0] inMask,
input wire[1:0] outMask,
output wire ready,
output wire[10:0] lcdPins,
output wire[15:0] page,
input wire[3:0] switch,
output wire[31:0] bp0Addr, bp1Addr, bp2Addr, bp3Addr, bpAddr, keyboardAddr, irAddr,
output wire bp0En, bp1En, bp2En, bp3En, keyboardEn, irEn,
output wire[15:0] lcdIn
); |
wire[31:0] addr = (re || we)? addrIn : 32'h00000000;
wire isStack = addr <= 32'hD000FFFF && addr >= 32'hD0000000;
wire isInstr = addr <= 32'h000FFFFF;
wire isLCD = addr == 32'hFFFF0000 || addr == 32'hFFFF0001;
wire isSwitch = addr == 32'hFFFF0002;
wire isFastMem = addr >= 32'hFFFF1000 && addr <= 32'hFFFF101F;
wire isBPRegs = addr >= 32'hFFFFF000 && addr <= 32'hFFFFF015;
wire isInt = addr >= 32'hFFFFFFF6 && addr <= 32'hFFFFFFFF;
wire isHeap = addr <= 32'h8FFFFFFF && addr >= 32'h10000000;
wire[15:0] romOut, ram1Out, ram2Out;
wire[1:0] addrLeast = {2{addr[0]}};
wire[7:0] write8 = (inMask == 2'b01)? write[7:0] :
(inMask == 2'b10)? write[15:8] :
write[7:0];
wire[15:0] write8S = outMask == (2'b01 ^ addrLeast)? {8'h00, write8} :
outMask == (2'b10 ^ addrLeast)? {write8, 8'h00} :
addrLeast? {write[7:0], write[15:8]} : write;
wire[15:0] mask = {{8{byteenable[1]}}, {8{byteenable[0]}}};
wire[1:0] byteenable = addrLeast? {outMask[0], outMask[1]}: outMask;
InstrROM rom (
.address (addr[10:1]),
.clock (clk),
.q (romOut)
);
wire[15:0] stackAddr = addr[15:0];
StackRAM ram1 (
.address (stackAddr[10:1]),
.clock (clk),
.data (write8S),
.wren (we && isStack),
.byteena(byteenable),
.q (ram1Out)
);
wire[30:0] heapAddr = addr[30:0];
HeapRAM ram2 (
.address (heapAddr[12:1]),
.clock (clk),
.data (write8S),
.wren (we && isHeap),
.byteena(byteenable),
.q (ram2Out)
);
reg[7:0] lcdData = 8'h00;
reg[2:0] lcdCtrl = 3'b000;
assign lcdPins = {lcdCtrl, lcdData};
assign lcdIn = ((write8S & mask) | ({5'b0, lcdCtrl, lcdData} & ~mask));
always @ (posedge clk) begin
if (rst) begin
lcdData <= 8'h00;
lcdCtrl <= 3'b000;
end else if (we && isLCD) begin
{lcdCtrl, lcdData} <= lcdIn[10:0];
end
end
reg[15:0] keyboardAddrHigh = 16'h0000;
reg[15:0] keyboardAddrLow = 16'h0000;
reg enKeyboard = 1;
assign keyboardAddr = {keyboardAddrHigh, keyboardAddrLow};
assign keyboardEn = enKeyboard;
reg[15:0] irAddrHigh = 16'h0000;
reg[15:0] irAddrLow = 16'h0000;
reg enIR = 1;
assign irAddr = {irAddrHigh, irAddrLow};
assign irEn = enIR;
wire[15:0] intEnWrite = (write8S & mask) | ({7'b0, enKeyboard, 7'b0, enIR} & ~mask);
always @ (posedge clk) begin
if (rst) begin
keyboardAddrHigh <= 16'h0000;
keyboardAddrLow <= 16'h0000;
enKeyboard <= 1'b0;
irAddrHigh <= 16'h0000;
irAddrLow <= 16'h0000;
enIR <= 1'b0;
end else if (we) begin
if (addr[31:1] == 31'h7FFFFFFB) begin
enIR <= |(intEnWrite[7:0]);
enKeyboard <= |(intEnWrite[15:8]);
end else if (addr[31:1] == 31'h7FFFFFFC)
irAddrLow <= (write8S & mask) | (irAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFFFFD)
irAddrHigh <= (write8S & mask) | (irAddrHigh & ~mask);
else if (addr[31:1] == 31'h7FFFFFFE)
keyboardAddrLow <= (write8S & mask) | (keyboardAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFFFFF)
keyboardAddrHigh <= (write8S & mask) | (keyboardAddrHigh & ~mask);
end
end
reg[15:0] breakPoint0High, breakPoint0Low;
reg[15:0] breakPoint1High, breakPoint1Low;
reg[15:0] breakPoint2High, breakPoint2Low;
reg[15:0] breakPoint3High, breakPoint3Low;
reg[15:0] breakPointAddrHigh, breakPointAddrLow;
reg[3:0] enBreakPoints;
assign bp0Addr = {breakPoint0High, breakPoint0Low};
assign bp1Addr = {breakPoint1High, breakPoint1Low};
assign bp2Addr = {breakPoint2High, breakPoint2Low};
assign bp3Addr = {breakPoint3High, breakPoint3Low};
assign bpAddr = {breakPointAddrHigh, breakPointAddrLow};
assign bp0En = enBreakPoints[0];
assign bp1En = enBreakPoints[1];
assign bp2En = enBreakPoints[2];
assign bp3En = enBreakPoints[3];
wire[15:0] bpEnIn = ((write8S & mask) | ({12'b0, enBreakPoints} & ~mask));
always @ (posedge clk) begin
if (rst) begin
breakPoint0High <= 16'h0000;
breakPoint0Low <= 16'h0000;
breakPoint1High <= 16'h0000;
breakPoint1Low <= 16'h0000;
breakPoint2High <= 16'h0000;
breakPoint2Low <= 16'h0000;
breakPoint3High <= 16'h0000;
breakPoint3Low <= 16'h0000;
breakPointAddrHigh <= 16'h0000;
breakPointAddrLow <= 16'h0000;
enBreakPoints <= 4'b0000;
end
else if (we) begin
if (addr[31:1] == 31'h7FFFF800)
enBreakPoints <= bpEnIn[3:0];
else if (addr[31:1] == 31'h7FFFF801)
breakPoint0Low <= (write8S & mask) | (breakPoint0Low & ~mask);
else if (addr[31:1] == 31'h7FFFF802)
breakPoint0High <= (write8S & mask) | (breakPoint0High & ~mask);
else if (addr[31:1] == 31'h7FFFF803)
breakPoint1Low <= (write8S & mask) | (breakPoint1Low & ~mask);
else if (addr[31:1] == 31'h7FFFF804)
breakPoint1High <= (write8S & mask) | (breakPoint1High & ~mask);
else if (addr[31:1] == 31'h7FFFF805)
breakPoint2Low <= (write8S & mask) | (breakPoint2Low & ~mask);
else if (addr[31:1] == 31'h7FFFF806)
breakPoint2High <= (write8S & mask) | (breakPoint2High & ~mask);
else if (addr[31:1] == 31'h7FFFF807)
breakPoint3Low <= (write8S & mask) | (breakPoint3Low & ~mask);
else if (addr[31:1] == 31'h7FFFF808)
breakPoint3High <= (write8S & mask) | (breakPoint3High & ~mask);
else if (addr[31:1] == 31'h7FFFF809)
breakPointAddrLow <= (write8S & mask) | (breakPointAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFF80A)
breakPointAddrHigh <= (write8S & mask) | (breakPointAddrHigh & ~mask);
end
end
reg[15:0] fastMem [0:14];
assign page = fastMem[0];
integer i;
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i <= 14; i = i + 1)
fastMem[i] <= 16'b0;
end else if (we && isFastMem)
fastMem[addr[4:1]] <= (write8S & mask) | (fastMem[addr[4:1]] & ~mask);;
end
wire[15:0] readNoSwap = isStack? ram1Out :
isHeap? ram2Out :
isInstr? romOut :
isSwitch? switch :
isFastMem? fastMem[addr[3:0]] :
16'h0000;
assign read = addr[0]? {readNoSwap[7:0], readNoSwap[15:8]} : readNoSwap;
reg isReading1 = 0;
reg isReading2 = 0;
reg regReady = 0;
assign ready = 1;
endmodule | 1 |
138,471 | data/full_repos/permissive/83899885/CPU/source/rcpu.v | 83,899,885 | rcpu.v | v | 276 | 109 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83899885/CPU/source/rcpu.v:34: Cannot find include file: constants\n`include "constants" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/constants\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/constants.v\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/constants.sv\n constants\n constants.v\n constants.sv\n obj_dir/constants\n obj_dir/constants.v\n obj_dir/constants.sv\n%Error: Exiting due to 1 error(s)\n' | 302,412 | module | module rcpu (
input wire rst,
input wire clk,
input wire irq,
output wire turnOffIRQ,
input wire memReady,
input wire[N-1:0] intAddr,
input wire[M-1:0] intData,
input wire[M-1:0] page,
output reg[N-1:0] memAddr,
input wire[M-1:0] memReadIn,
output reg[M-1:0] memWrite,
output wire memRE,
output wire memWE,
output wire[1:0] inMask,
output wire[1:0] outMask,
output wire[M-1:0] A,
output wire[M-1:0] B,
output wire[M-1:0] C,
output wire[N-1:0] PC,
output wire[M-1:0] FP,
output wire[M-1:0] SP,
output wire[5:0] state,
output wire[3:0] F
);
`include "constants"
parameter M = 16;
parameter N = 32;
wire[M-1:0] memRead;
wire stall = !memReady && memRE;
wire enA;
wire enB;
wire enC;
wire enPC;
wire enSP;
wire enFP;
wire[1:0] sourcePC;
wire sourceFP;
wire[M-1:0] inR = aluY;
reg[N-1:0] inPC;
always @ ( * ) begin
inPC = {aluYHigh, aluY};
if (sourcePC == 2'b01)
inPC = {PC[31:16], memRead};
else if (sourcePC == 2'b10)
inPC = {memRead, PC[15:0]};
else if (sourcePC == 2'b11)
inPC = {PC[31:17], aluB, 1'b0};
end
wire[M-1:0] opcode;
wire enIR;
wire[M-1:0] value1;
wire enV1;
wire[M-1:0] value2;
wire enV2;
wire[M-1:0] res;
wire enR;
wire enF;
wire[3:0] inFFromAlu;
reg[3:0] inF;
wire c = F[3];
wire n = F[2];
wire z = F[1];
wire v = F[0];
wire[M-1:0] aluY;
wire[M-1:0] aluYHigh;
wire[1:0] sourceF;
wire[3:0] altF;
wire isMul;
wire initSPFP;
wire writeToSP = (memAddr == 32'hFFFF100F) && memWE;
wire[M-1:0] inSP = initSPFP? 16'hFFFE:
writeToSP? memWrite:
aluY;
register #(M) rIR (clk, memRead, opcode, enIR && !stall, rst, 2'b11, 2'b11);
register #(M) rV1 (clk, memRead, value1, enV1 && !stall, rst, 2'b11, 2'b11);
register #(M) rV2 (clk, memRead, value2, enV2 && !stall, rst, 2'b11, 2'b11);
register #(M) rR (clk, aluY, res, enR && !stall, rst, 2'b11, 2'b11);
register #(M) rA (clk, isMul? yhigh : inR, A, enA && !stall, rst, inMask, outMask);
register #(M) rB (clk, inR, B, enB && !stall, rst, inMask, outMask);
register #(M) rC (clk, inR, C, enC && !stall, rst, inMask, outMask);
register #(N) rPC (clk, inPC, PC, enPC && !stall, rst, 2'b11, 2'b11);
register #(M) rSP (clk, inSP, SP, (enSP || writeToSP) && !stall, rst, 2'b11, 2'b11);
register #(M) rFP (clk, initSPFP? 16'hFFFE: sourceFP? memRead: aluY, FP, enFP && !stall, rst, 2'b11, 2'b11);
register #(4) rF (clk, inF, F, enF && !stall, rst, 2'b11, 2'b11);
assign memRead = memAddr == 32'hFFFF100F ? SP : memReadIn;
reg[M-1:0] aluA;
reg[M-1:0] aluAHigh;
reg[M-1:0] aluB;
wire[3:0] aluFunc;
wire[M-1:0] aluOutA;
wire[3:0] aluASource;
wire[3:0] aluBSource;
reg use32bit;
alu alu1 (
.a (aluA),
.ahigh (aluAHigh),
.b (aluB),
.y (aluY),
.yhigh (aluYHigh),
.func (aluFunc),
.use32bit (use32bit),
.co (inFFromAlu[3]),
.negative (inFFromAlu[2]),
.zero (inFFromAlu[1]),
.overflow (inFFromAlu[0]),
.ci (c)
);
wire[2:0] memAddrSource;
wire[3:0] writeDataSource;
wire readStack;
cpuController cpuCTRL (
.clk (clk),
.stall(stall),
.rst (rst),
.opcode (enIR? memRead : opcode),
.flags (F),
.irq (irq),
.enPC (enPC),
.aluFunc (aluFunc),
.aluA (aluASource),
.aluB (aluBSource),
.enA (enA),
.enB (enB),
.enC (enC),
.saveOpcode (enIR),
.saveMem1 (enV1),
.saveMem2 (enV2),
.memAddr (memAddrSource),
.we (memWE),
.re (memRE),
.writeDataSource (writeDataSource),
.saveResult (enR),
.enF (enF),
.sourceF (sourceF),
.sourceFP (sourceFP),
.enFP (enFP),
.sourcePC (sourcePC),
.inF (altF),
.enSP (enSP),
.state (state),
.turnOffIRQ (turnOffIRQ),
.readStack (readStack),
.isMul (isMul),
.initSPFP (initSPFP),
.inMask (inMask),
.outMask (outMask)
);
always @ ( * ) begin
aluA = 0;
use32bit = 0;
aluAHigh = 0;
case (aluASource)
ALU1_FROM_0: aluA = 0;
ALU1_FROM_A: aluA = A;
ALU1_FROM_B: aluA = B;
ALU1_FROM_C: aluA = C;
ALU1_FROM_PC: begin {aluAHigh, aluA} = PC; use32bit = 1; end
ALU1_FROM_MEM: aluA = value1;
ALU1_FROM_HIMEM: begin {aluAHigh, aluA} = {value2, value1};
use32bit = 1;
end
ALU1_FROM_SP: aluA = SP;
ALU1_FROM_XX: aluA = opcode[6:0];
ALU1_FROM_INTADDR: begin {aluAHigh, aluA} = intAddr; use32bit = 1; end
ALU1_FROM_DIRECTREAD: aluA = memRead;
default: aluA = 0;
endcase
end
always @ ( * ) begin
aluB = 0;
case (aluBSource)
ALU2_FROM_0: aluB = 0;
ALU2_FROM_A: aluB = A;
ALU2_FROM_B: aluB = B;
ALU2_FROM_C: aluB = C;
ALU2_FROM_OP: aluB = {{9{opcode[7]}}, opcode[6:0]};
ALU2_FROM_ADDR: aluB = {{3{opcode[12]}}, opcode[11:0], 1'b0};
ALU2_FROM_FADDR: aluB = {{8{opcode[7]}}, opcode[6:0], 1'b0};
ALU2_FROM_2: aluB = 2;
ALU2_FROM_FP: aluB = FP;
ALU2_FROM_MEM: aluB = value1;
default: aluB = 0;
endcase
end
always @ ( * ) begin
case (sourceF)
FLAG_FROM_ALU: inF = inFFromAlu;
FLAG_FROM_ALU_OUT: inF = aluY[3:0];
FLAG_FROM_8BIT: inF = {1'b0, aluY[7], aluY[7:0] == 8'h00, 1'b0};
default: inF = inFFromAlu;
endcase
end
always @ ( * ) begin
case (memAddrSource)
READ_FROM_PC: memAddr = PC;
READ_FROM_A: memAddr = {page, A};
READ_FROM_ALU: memAddr = readStack? {16'hD000, aluY} : {aluYHigh, aluY};
READ_FROM_SP: memAddr = {16'hD000, SP};
READ_FROM_FASTMEM: memAddr = {25'h1FFFE20, opcode[6:0]};
default: memAddr = PC;
endcase
end
always @ ( * ) begin
memWrite = aluY;
case (writeDataSource)
WRITE_FROM_ALU: memWrite = aluY;
WRITE_FROM_RES: memWrite = res;
WRITE_FROM_PC1: memWrite = PC[15:0];
WRITE_FROM_PC2: memWrite = PC[31:16];
WRITE_FROM_FP: memWrite = FP;
WRITE_FROM_A: memWrite = A;
WRITE_FROM_B: memWrite = B;
WRITE_FROM_C: memWrite = C;
WRITE_FROM_INTDATA: memWrite = intData;
WRITE_FROM_F: memWrite = F;
endcase
end
endmodule | module rcpu (
input wire rst,
input wire clk,
input wire irq,
output wire turnOffIRQ,
input wire memReady,
input wire[N-1:0] intAddr,
input wire[M-1:0] intData,
input wire[M-1:0] page,
output reg[N-1:0] memAddr,
input wire[M-1:0] memReadIn,
output reg[M-1:0] memWrite,
output wire memRE,
output wire memWE,
output wire[1:0] inMask,
output wire[1:0] outMask,
output wire[M-1:0] A,
output wire[M-1:0] B,
output wire[M-1:0] C,
output wire[N-1:0] PC,
output wire[M-1:0] FP,
output wire[M-1:0] SP,
output wire[5:0] state,
output wire[3:0] F
); |
`include "constants"
parameter M = 16;
parameter N = 32;
wire[M-1:0] memRead;
wire stall = !memReady && memRE;
wire enA;
wire enB;
wire enC;
wire enPC;
wire enSP;
wire enFP;
wire[1:0] sourcePC;
wire sourceFP;
wire[M-1:0] inR = aluY;
reg[N-1:0] inPC;
always @ ( * ) begin
inPC = {aluYHigh, aluY};
if (sourcePC == 2'b01)
inPC = {PC[31:16], memRead};
else if (sourcePC == 2'b10)
inPC = {memRead, PC[15:0]};
else if (sourcePC == 2'b11)
inPC = {PC[31:17], aluB, 1'b0};
end
wire[M-1:0] opcode;
wire enIR;
wire[M-1:0] value1;
wire enV1;
wire[M-1:0] value2;
wire enV2;
wire[M-1:0] res;
wire enR;
wire enF;
wire[3:0] inFFromAlu;
reg[3:0] inF;
wire c = F[3];
wire n = F[2];
wire z = F[1];
wire v = F[0];
wire[M-1:0] aluY;
wire[M-1:0] aluYHigh;
wire[1:0] sourceF;
wire[3:0] altF;
wire isMul;
wire initSPFP;
wire writeToSP = (memAddr == 32'hFFFF100F) && memWE;
wire[M-1:0] inSP = initSPFP? 16'hFFFE:
writeToSP? memWrite:
aluY;
register #(M) rIR (clk, memRead, opcode, enIR && !stall, rst, 2'b11, 2'b11);
register #(M) rV1 (clk, memRead, value1, enV1 && !stall, rst, 2'b11, 2'b11);
register #(M) rV2 (clk, memRead, value2, enV2 && !stall, rst, 2'b11, 2'b11);
register #(M) rR (clk, aluY, res, enR && !stall, rst, 2'b11, 2'b11);
register #(M) rA (clk, isMul? yhigh : inR, A, enA && !stall, rst, inMask, outMask);
register #(M) rB (clk, inR, B, enB && !stall, rst, inMask, outMask);
register #(M) rC (clk, inR, C, enC && !stall, rst, inMask, outMask);
register #(N) rPC (clk, inPC, PC, enPC && !stall, rst, 2'b11, 2'b11);
register #(M) rSP (clk, inSP, SP, (enSP || writeToSP) && !stall, rst, 2'b11, 2'b11);
register #(M) rFP (clk, initSPFP? 16'hFFFE: sourceFP? memRead: aluY, FP, enFP && !stall, rst, 2'b11, 2'b11);
register #(4) rF (clk, inF, F, enF && !stall, rst, 2'b11, 2'b11);
assign memRead = memAddr == 32'hFFFF100F ? SP : memReadIn;
reg[M-1:0] aluA;
reg[M-1:0] aluAHigh;
reg[M-1:0] aluB;
wire[3:0] aluFunc;
wire[M-1:0] aluOutA;
wire[3:0] aluASource;
wire[3:0] aluBSource;
reg use32bit;
alu alu1 (
.a (aluA),
.ahigh (aluAHigh),
.b (aluB),
.y (aluY),
.yhigh (aluYHigh),
.func (aluFunc),
.use32bit (use32bit),
.co (inFFromAlu[3]),
.negative (inFFromAlu[2]),
.zero (inFFromAlu[1]),
.overflow (inFFromAlu[0]),
.ci (c)
);
wire[2:0] memAddrSource;
wire[3:0] writeDataSource;
wire readStack;
cpuController cpuCTRL (
.clk (clk),
.stall(stall),
.rst (rst),
.opcode (enIR? memRead : opcode),
.flags (F),
.irq (irq),
.enPC (enPC),
.aluFunc (aluFunc),
.aluA (aluASource),
.aluB (aluBSource),
.enA (enA),
.enB (enB),
.enC (enC),
.saveOpcode (enIR),
.saveMem1 (enV1),
.saveMem2 (enV2),
.memAddr (memAddrSource),
.we (memWE),
.re (memRE),
.writeDataSource (writeDataSource),
.saveResult (enR),
.enF (enF),
.sourceF (sourceF),
.sourceFP (sourceFP),
.enFP (enFP),
.sourcePC (sourcePC),
.inF (altF),
.enSP (enSP),
.state (state),
.turnOffIRQ (turnOffIRQ),
.readStack (readStack),
.isMul (isMul),
.initSPFP (initSPFP),
.inMask (inMask),
.outMask (outMask)
);
always @ ( * ) begin
aluA = 0;
use32bit = 0;
aluAHigh = 0;
case (aluASource)
ALU1_FROM_0: aluA = 0;
ALU1_FROM_A: aluA = A;
ALU1_FROM_B: aluA = B;
ALU1_FROM_C: aluA = C;
ALU1_FROM_PC: begin {aluAHigh, aluA} = PC; use32bit = 1; end
ALU1_FROM_MEM: aluA = value1;
ALU1_FROM_HIMEM: begin {aluAHigh, aluA} = {value2, value1};
use32bit = 1;
end
ALU1_FROM_SP: aluA = SP;
ALU1_FROM_XX: aluA = opcode[6:0];
ALU1_FROM_INTADDR: begin {aluAHigh, aluA} = intAddr; use32bit = 1; end
ALU1_FROM_DIRECTREAD: aluA = memRead;
default: aluA = 0;
endcase
end
always @ ( * ) begin
aluB = 0;
case (aluBSource)
ALU2_FROM_0: aluB = 0;
ALU2_FROM_A: aluB = A;
ALU2_FROM_B: aluB = B;
ALU2_FROM_C: aluB = C;
ALU2_FROM_OP: aluB = {{9{opcode[7]}}, opcode[6:0]};
ALU2_FROM_ADDR: aluB = {{3{opcode[12]}}, opcode[11:0], 1'b0};
ALU2_FROM_FADDR: aluB = {{8{opcode[7]}}, opcode[6:0], 1'b0};
ALU2_FROM_2: aluB = 2;
ALU2_FROM_FP: aluB = FP;
ALU2_FROM_MEM: aluB = value1;
default: aluB = 0;
endcase
end
always @ ( * ) begin
case (sourceF)
FLAG_FROM_ALU: inF = inFFromAlu;
FLAG_FROM_ALU_OUT: inF = aluY[3:0];
FLAG_FROM_8BIT: inF = {1'b0, aluY[7], aluY[7:0] == 8'h00, 1'b0};
default: inF = inFFromAlu;
endcase
end
always @ ( * ) begin
case (memAddrSource)
READ_FROM_PC: memAddr = PC;
READ_FROM_A: memAddr = {page, A};
READ_FROM_ALU: memAddr = readStack? {16'hD000, aluY} : {aluYHigh, aluY};
READ_FROM_SP: memAddr = {16'hD000, SP};
READ_FROM_FASTMEM: memAddr = {25'h1FFFE20, opcode[6:0]};
default: memAddr = PC;
endcase
end
always @ ( * ) begin
memWrite = aluY;
case (writeDataSource)
WRITE_FROM_ALU: memWrite = aluY;
WRITE_FROM_RES: memWrite = res;
WRITE_FROM_PC1: memWrite = PC[15:0];
WRITE_FROM_PC2: memWrite = PC[31:16];
WRITE_FROM_FP: memWrite = FP;
WRITE_FROM_A: memWrite = A;
WRITE_FROM_B: memWrite = B;
WRITE_FROM_C: memWrite = C;
WRITE_FROM_INTDATA: memWrite = intData;
WRITE_FROM_F: memWrite = F;
endcase
end
endmodule | 1 |
138,472 | data/full_repos/permissive/83899885/CPU/source/register.v | 83,899,885 | register.v | v | 37 | 55 | [] | [] | [] | [(5, 36)] | null | data/verilator_xmls/8dc3760a-02df-43a1-80d9-d7edaff61e99.xml | null | 302,413 | module | module register(
input wire clk,
input wire[N-1:0] in,
output wire[N-1:0] out,
input wire en,
input wire rst,
input wire[1:0] inMask,
input wire[1:0] outMask);
parameter N = 16;
reg[N-1:0] value;
wire[N/2-1:0] halfIn = (inMask == 2'b01)? in[N/2-1:0]:
(inMask == 2'b10)? in[N-1:N/2]:
{N/2{1'b0}};
always @ (posedge clk)
if (rst)
value <= 0;
else if (en) begin
if (inMask == 2'b11 || outMask == 2'b11)
value <= in;
else if (outMask == 2'b01)
value[N/2-1:0] <= halfIn;
else if (outMask == 2'b10)
value[N-1:N/2] <= halfIn;
end
assign out = value;
endmodule | module register(
input wire clk,
input wire[N-1:0] in,
output wire[N-1:0] out,
input wire en,
input wire rst,
input wire[1:0] inMask,
input wire[1:0] outMask); |
parameter N = 16;
reg[N-1:0] value;
wire[N/2-1:0] halfIn = (inMask == 2'b01)? in[N/2-1:0]:
(inMask == 2'b10)? in[N-1:N/2]:
{N/2{1'b0}};
always @ (posedge clk)
if (rst)
value <= 0;
else if (en) begin
if (inMask == 2'b11 || outMask == 2'b11)
value <= in;
else if (outMask == 2'b01)
value[N/2-1:0] <= halfIn;
else if (outMask == 2'b10)
value[N-1:N/2] <= halfIn;
end
assign out = value;
endmodule | 1 |
138,474 | data/full_repos/permissive/83899885/CPU/source/TopLevel.v | 83,899,885 | TopLevel.v | v | 122 | 78 | [] | [] | [] | [(1, 121)] | null | null | 1: b"%Error: data/full_repos/permissive/83899885/CPU/source/TopLevel.v:80: Cannot find file containing module: 'PushButton_Debouncer'\nPushButton_Debouncer debouncer (clk, switch_in[3], bttnClk);\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/PushButton_Debouncer\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/PushButton_Debouncer.v\n data/full_repos/permissive/83899885/CPU/source,data/full_repos/permissive/83899885/PushButton_Debouncer.sv\n PushButton_Debouncer\n PushButton_Debouncer.v\n PushButton_Debouncer.sv\n obj_dir/PushButton_Debouncer\n obj_dir/PushButton_Debouncer.v\n obj_dir/PushButton_Debouncer.sv\n%Error: data/full_repos/permissive/83899885/CPU/source/TopLevel.v:86: Cannot find file containing module: 'Rintaro'\nRintaro rintaro (\n^~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/source/TopLevel.v:108: Cannot find file containing module: 'RS232Controller'\nRS232Controller rs232 (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 302,416 | module | module TopLevel (
input wire clk,
input wire rst_in,
input wire[3:0] switch_in,
output wire buzzer,
output wire[3:0] led_out,
inout wire ps2CLK_in,
input wire ps2DATA_in,
output wire[3:0] tubeDig_out,
output wire[7:0] tubeSeg_out,
output wire[7:0] lcdData,
output wire lcdRS,
output wire lcdRW,
output wire lcdE,
input wire ir_in,
output wire uartTXD_out,
input wire uartRXD_in
);
parameter DIVISIONREGSIZE = 18;
reg[DIVISIONREGSIZE-1 : 0] adder = {DIVISIONREGSIZE{1'b0}};
always @ (posedge clk)
adder <= adder + 18'b1;
wire[3:0] led;
wire[3:0] tubeDig;
wire[7:0] tubeSeg;
wire uartTXD;
wire[3:0] switch = ~switch_in;
wire rst = ~rst_in;
wire ps2Inhibit;
reg ps2InhibitPrev = 0;
reg[10:0] inhibitCounter = 11'h7FF;
always @ (posedge clk) begin
ps2InhibitPrev <= ps2Inhibit;
if (ps2Inhibit && !ps2InhibitPrev) inhibitCounter <= 0;
else if (inhibitCounter != 11'h7FF) inhibitCounter <= inhibitCounter + 1;
end
assign led_out = ~led;
assign tubeSeg_out = ~tubeSeg;
assign tubeDig_out = ~tubeDig;
assign buzzer = 0;
assign uartTXD_out = uartTXD;
wire uartRXD = uartRXD_in;
wire ir = ~ir_in;
reg[1:0] dig;
always @ (posedge adder[17])
dig <= dig + 2'b1;
wire[10:0] lcdPins;
assign {lcdRS, lcdRW, lcdE, lcdData} = lcdPins;
wire bttnClk;
wire irq;
PushButton_Debouncer debouncer (clk, switch_in[3], bttnClk);
wire[1:0] cpuClkMode;
wire cpuClk = cpuClkMode[1] == 1'b0 ? bttnClk :
cpuClkMode[0] == 1'b0 ? adder[15] : adder[6];
Rintaro rintaro (
.fastClk (clk),
.clk1 (!cpuClk),
.clk2 (cpuClk),
.rst (rst),
.dig (dig),
.switch (switch[2:0]),
.tubeDig (tubeDig),
.tubeSeg (tubeSeg),
.lcdPins (lcdPins),
.ps2CLK (ps2CLK_in),
.ps2DATA (ps2DATA_in),
.irqOut (irq),
.ir (ir),
.err (err),
.stateOut (stateOut),
.cpuClkMode (cpuClkMode)
);
wire[7:0] rs232Data;
wire rs232Ready;
RS232Controller rs232 (
.clk (clk),
.rst (rst),
.rs232RX (uartRXD),
.rs232TX (uartTXD),
.rxData (rs232Data),
.rxReady (rs232Ready),
.txData (rs232Data),
.txStart (rs232Ready)
);
assign led = {lcdRS, lcdRW, lcdE, lcdData[0]};
endmodule | module TopLevel (
input wire clk,
input wire rst_in,
input wire[3:0] switch_in,
output wire buzzer,
output wire[3:0] led_out,
inout wire ps2CLK_in,
input wire ps2DATA_in,
output wire[3:0] tubeDig_out,
output wire[7:0] tubeSeg_out,
output wire[7:0] lcdData,
output wire lcdRS,
output wire lcdRW,
output wire lcdE,
input wire ir_in,
output wire uartTXD_out,
input wire uartRXD_in
); |
parameter DIVISIONREGSIZE = 18;
reg[DIVISIONREGSIZE-1 : 0] adder = {DIVISIONREGSIZE{1'b0}};
always @ (posedge clk)
adder <= adder + 18'b1;
wire[3:0] led;
wire[3:0] tubeDig;
wire[7:0] tubeSeg;
wire uartTXD;
wire[3:0] switch = ~switch_in;
wire rst = ~rst_in;
wire ps2Inhibit;
reg ps2InhibitPrev = 0;
reg[10:0] inhibitCounter = 11'h7FF;
always @ (posedge clk) begin
ps2InhibitPrev <= ps2Inhibit;
if (ps2Inhibit && !ps2InhibitPrev) inhibitCounter <= 0;
else if (inhibitCounter != 11'h7FF) inhibitCounter <= inhibitCounter + 1;
end
assign led_out = ~led;
assign tubeSeg_out = ~tubeSeg;
assign tubeDig_out = ~tubeDig;
assign buzzer = 0;
assign uartTXD_out = uartTXD;
wire uartRXD = uartRXD_in;
wire ir = ~ir_in;
reg[1:0] dig;
always @ (posedge adder[17])
dig <= dig + 2'b1;
wire[10:0] lcdPins;
assign {lcdRS, lcdRW, lcdE, lcdData} = lcdPins;
wire bttnClk;
wire irq;
PushButton_Debouncer debouncer (clk, switch_in[3], bttnClk);
wire[1:0] cpuClkMode;
wire cpuClk = cpuClkMode[1] == 1'b0 ? bttnClk :
cpuClkMode[0] == 1'b0 ? adder[15] : adder[6];
Rintaro rintaro (
.fastClk (clk),
.clk1 (!cpuClk),
.clk2 (cpuClk),
.rst (rst),
.dig (dig),
.switch (switch[2:0]),
.tubeDig (tubeDig),
.tubeSeg (tubeSeg),
.lcdPins (lcdPins),
.ps2CLK (ps2CLK_in),
.ps2DATA (ps2DATA_in),
.irqOut (irq),
.ir (ir),
.err (err),
.stateOut (stateOut),
.cpuClkMode (cpuClkMode)
);
wire[7:0] rs232Data;
wire rs232Ready;
RS232Controller rs232 (
.clk (clk),
.rst (rst),
.rs232RX (uartRXD),
.rs232TX (uartTXD),
.rxData (rs232Data),
.rxReady (rs232Ready),
.txData (rs232Data),
.txStart (rs232Ready)
);
assign led = {lcdRS, lcdRW, lcdE, lcdData[0]};
endmodule | 1 |
138,475 | data/full_repos/permissive/83899885/CPU/source/TubeController.v | 83,899,885 | TubeController.v | v | 69 | 47 | [] | [] | [] | [(1, 42), (44, 68)] | null | data/verilator_xmls/41823066-3081-469e-ac42-49d7b5124972.xml | null | 302,417 | module | module TubeROM (
input wire[3:0] value,
input wire auxValue,
output reg[6:0] segments
);
always @ (*) begin
if (auxValue) begin
case (value)
4'h0: segments = 7'h00;
4'h1: segments = 7'h73;
4'h2: segments = 7'h78;
4'h3: segments = 7'h50;
4'h4: segments = 7'h1C;
4'h5: segments = 7'h76;
4'h6: segments = 7'h38;
default: segments = 7'b0;
endcase
end
else begin
case (value)
4'h0: segments = 7'h3F;
4'h1: segments = 7'h06;
4'h2: segments = 7'h5B;
4'h3: segments = 7'h4F;
4'h4: segments = 7'h66;
4'h5: segments = 7'h6D;
4'h6: segments = 7'h7D;
4'h7: segments = 7'h07;
4'h8: segments = 7'h7F;
4'h9: segments = 7'h6F;
4'hA: segments = 7'h77;
4'hB: segments = 7'h7C;
4'hC: segments = 7'h39;
4'hD: segments = 7'h5E;
4'hE: segments = 7'h79;
4'hF: segments = 7'h71;
default: segments = 7'b0;
endcase
end
end
endmodule | module TubeROM (
input wire[3:0] value,
input wire auxValue,
output reg[6:0] segments
); |
always @ (*) begin
if (auxValue) begin
case (value)
4'h0: segments = 7'h00;
4'h1: segments = 7'h73;
4'h2: segments = 7'h78;
4'h3: segments = 7'h50;
4'h4: segments = 7'h1C;
4'h5: segments = 7'h76;
4'h6: segments = 7'h38;
default: segments = 7'b0;
endcase
end
else begin
case (value)
4'h0: segments = 7'h3F;
4'h1: segments = 7'h06;
4'h2: segments = 7'h5B;
4'h3: segments = 7'h4F;
4'h4: segments = 7'h66;
4'h5: segments = 7'h6D;
4'h6: segments = 7'h7D;
4'h7: segments = 7'h07;
4'h8: segments = 7'h7F;
4'h9: segments = 7'h6F;
4'hA: segments = 7'h77;
4'hB: segments = 7'h7C;
4'hC: segments = 7'h39;
4'hD: segments = 7'h5E;
4'hE: segments = 7'h79;
4'hF: segments = 7'h71;
default: segments = 7'b0;
endcase
end
end
endmodule | 1 |
138,476 | data/full_repos/permissive/83899885/CPU/source/TubeController.v | 83,899,885 | TubeController.v | v | 69 | 47 | [] | [] | [] | [(1, 42), (44, 68)] | null | data/verilator_xmls/41823066-3081-469e-ac42-49d7b5124972.xml | null | 302,417 | module | module TubeController (
input wire[1:0] dig,
input wire[3:0] dig1,
input wire[3:0] dig2,
input wire[3:0] dig3,
input wire[3:0] dig4,
input wire[3:0] dots,
input wire[3:0] auxs,
output wire[3:0] tubeDig,
output wire[7:0] tubeSeg
);
wire[3:0] value = (dig == 2'd0)? dig1 :
(dig == 2'd1)? dig2 :
(dig == 2'd2)? dig3 :
dig4;
TubeROM rom (value, auxs[dig], tubeSeg[6:0]);
assign tubeSeg[7] = dots[dig];
assign tubeDig = (dig == 2'd0)? 4'b0001 :
(dig == 2'd1)? 4'b0010 :
(dig == 2'd2)? 4'b0100 :
4'b1000;
endmodule | module TubeController (
input wire[1:0] dig,
input wire[3:0] dig1,
input wire[3:0] dig2,
input wire[3:0] dig3,
input wire[3:0] dig4,
input wire[3:0] dots,
input wire[3:0] auxs,
output wire[3:0] tubeDig,
output wire[7:0] tubeSeg
); |
wire[3:0] value = (dig == 2'd0)? dig1 :
(dig == 2'd1)? dig2 :
(dig == 2'd2)? dig3 :
dig4;
TubeROM rom (value, auxs[dig], tubeSeg[6:0]);
assign tubeSeg[7] = dots[dig];
assign tubeDig = (dig == 2'd0)? 4'b0001 :
(dig == 2'd1)? 4'b0010 :
(dig == 2'd2)? 4'b0100 :
4'b1000;
endmodule | 1 |
138,478 | data/full_repos/permissive/83899885/CPU/source/UART_Controller/RS232Controller.v | 83,899,885 | RS232Controller.v | v | 40 | 59 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/83899885/CPU/source/UART_Controller/RS232Controller.v:15: Cannot find file containing module: 'RS232BaudRateController'\nRS232BaudRateController baud1 (clk, rst, startBPS1, bps1);\n^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83899885/CPU/source/UART_Controller,data/full_repos/permissive/83899885/RS232BaudRateController\n data/full_repos/permissive/83899885/CPU/source/UART_Controller,data/full_repos/permissive/83899885/RS232BaudRateController.v\n data/full_repos/permissive/83899885/CPU/source/UART_Controller,data/full_repos/permissive/83899885/RS232BaudRateController.sv\n RS232BaudRateController\n RS232BaudRateController.v\n RS232BaudRateController.sv\n obj_dir/RS232BaudRateController\n obj_dir/RS232BaudRateController.v\n obj_dir/RS232BaudRateController.sv\n%Error: data/full_repos/permissive/83899885/CPU/source/UART_Controller/RS232Controller.v:16: Cannot find file containing module: 'RS232RX'\nRS232RX rx (\n^~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/source/UART_Controller/RS232Controller.v:27: Cannot find file containing module: 'RS232BaudRateController'\nRS232BaudRateController baud2 (clk, rst, startBPS2, bps2);\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/source/UART_Controller/RS232Controller.v:28: Cannot find file containing module: 'RS232TX'\nRS232TX tx (\n^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,422 | module | module RS232Controller (
input wire clk,
input wire rst,
input wire rs232RX,
output wire rs232TX,
output wire[7:0] rxData,
output wire rxReady,
input wire[7:0] txData,
input wire txStart,
output wire txBusy
);
wire bps1, startBPS1;
RS232BaudRateController baud1 (clk, rst, startBPS1, bps1);
RS232RX rx (
.clk (clk),
.rst (rst),
.rs232RX (rs232RX),
.data (rxData),
.ready (rxReady),
.bps (bps1),
.startBPS (startBPS1)
);
wire bps2, startBPS2;
RS232BaudRateController baud2 (clk, rst, startBPS2, bps2);
RS232TX tx (
.clk (clk),
.rst (rst),
.rs232TX (rs232TX),
.data (txData),
.startTX (txStart),
.busy (txBusy),
.bps (bps2),
.startBPS (startBPS2)
);
endmodule | module RS232Controller (
input wire clk,
input wire rst,
input wire rs232RX,
output wire rs232TX,
output wire[7:0] rxData,
output wire rxReady,
input wire[7:0] txData,
input wire txStart,
output wire txBusy
); |
wire bps1, startBPS1;
RS232BaudRateController baud1 (clk, rst, startBPS1, bps1);
RS232RX rx (
.clk (clk),
.rst (rst),
.rs232RX (rs232RX),
.data (rxData),
.ready (rxReady),
.bps (bps1),
.startBPS (startBPS1)
);
wire bps2, startBPS2;
RS232BaudRateController baud2 (clk, rst, startBPS2, bps2);
RS232TX tx (
.clk (clk),
.rst (rst),
.rs232TX (rs232TX),
.data (txData),
.startTX (txStart),
.busy (txBusy),
.bps (bps2),
.startBPS (startBPS2)
);
endmodule | 1 |
138,480 | data/full_repos/permissive/83899885/CPU/source/UART_Controller/RS232TX.v | 83,899,885 | RS232TX.v | v | 70 | 52 | [] | [] | [] | [(1, 69)] | null | data/verilator_xmls/4a574dd0-f80b-4283-9cc8-d9676be4d330.xml | null | 302,424 | module | module RS232TX (
input wire clk,
input wire rst,
output reg rs232TX,
input wire[7:0] data,
input wire startTX,
output reg busy,
input wire bps,
output reg startBPS
);
reg startTX0, startTX1, startTX2;
always @(posedge clk) begin
if (rst) begin
startTX0 <= 1'b0;
startTX1 <= 1'b0;
startTX2 <= 1'b0;
end else begin
startTX0 <= startTX;
startTX1 <= startTX0;
startTX2 <= startTX1;
end
end
wire startTXPosEdge = ~startTX2 & startTX1;
reg[7:0] txData;
reg[3:0] state;
always @(posedge clk) begin
if (rst) begin
startBPS <= 1'b0;
busy <= 1'b0;
txData <= 8'b0;
end else if (startTXPosEdge) begin
startBPS <= 1'b1;
txData <= data;
busy <= 1'b1;
end else if (state == 4'd11) begin
startBPS <= 1'b0;
busy <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
state <= 4'b0;
rs232TX <= 1'b1;
end
else if (busy) begin
if (bps) begin
state <= state + 1;
case (state)
4'd0: rs232TX <= 1'b0;
4'd1: rs232TX <= txData[0];
4'd2: rs232TX <= txData[1];
4'd3: rs232TX <= txData[2];
4'd4: rs232TX <= txData[3];
4'd5: rs232TX <= txData[4];
4'd6: rs232TX <= txData[5];
4'd7: rs232TX <= txData[6];
4'd8: rs232TX <= txData[7];
4'd9: rs232TX <= 1'b1;
default: rs232TX <= 1'b1;
endcase
end else if (state == 4'd11) state <= 4'd0;
end
end
endmodule | module RS232TX (
input wire clk,
input wire rst,
output reg rs232TX,
input wire[7:0] data,
input wire startTX,
output reg busy,
input wire bps,
output reg startBPS
); |
reg startTX0, startTX1, startTX2;
always @(posedge clk) begin
if (rst) begin
startTX0 <= 1'b0;
startTX1 <= 1'b0;
startTX2 <= 1'b0;
end else begin
startTX0 <= startTX;
startTX1 <= startTX0;
startTX2 <= startTX1;
end
end
wire startTXPosEdge = ~startTX2 & startTX1;
reg[7:0] txData;
reg[3:0] state;
always @(posedge clk) begin
if (rst) begin
startBPS <= 1'b0;
busy <= 1'b0;
txData <= 8'b0;
end else if (startTXPosEdge) begin
startBPS <= 1'b1;
txData <= data;
busy <= 1'b1;
end else if (state == 4'd11) begin
startBPS <= 1'b0;
busy <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
state <= 4'b0;
rs232TX <= 1'b1;
end
else if (busy) begin
if (bps) begin
state <= state + 1;
case (state)
4'd0: rs232TX <= 1'b0;
4'd1: rs232TX <= txData[0];
4'd2: rs232TX <= txData[1];
4'd3: rs232TX <= txData[2];
4'd4: rs232TX <= txData[3];
4'd5: rs232TX <= txData[4];
4'd6: rs232TX <= txData[5];
4'd7: rs232TX <= txData[6];
4'd8: rs232TX <= txData[7];
4'd9: rs232TX <= 1'b1;
default: rs232TX <= 1'b1;
endcase
end else if (state == 4'd11) state <= 4'd0;
end
end
endmodule | 1 |
138,484 | data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v | 83,899,885 | testRCPU.v | v | 69 | 62 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:1: Cannot find include file: ../source/rcpu.v\n`include "../source/rcpu.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83899885/CPU/testbenches,data/full_repos/permissive/83899885/../source/rcpu.v\n data/full_repos/permissive/83899885/CPU/testbenches,data/full_repos/permissive/83899885/../source/rcpu.v.v\n data/full_repos/permissive/83899885/CPU/testbenches,data/full_repos/permissive/83899885/../source/rcpu.v.sv\n ../source/rcpu.v\n ../source/rcpu.v.v\n ../source/rcpu.v.sv\n obj_dir/../source/rcpu.v\n obj_dir/../source/rcpu.v.v\n obj_dir/../source/rcpu.v.sv\n%Error: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:2: Cannot find include file: ../source/RAM2.v\n`include "../source/RAM2.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:46: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("../test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:47: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (0);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:48: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (1, ram.memory[0]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:49: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (1, ram.memory[1]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:51: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (1, ram.memory[i]);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:54: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:64: Unsupported: Ignoring delay on this delayed statement.\n #1 rst = 0; $readmemb("../fact.rcpu", ram.memory); #9\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83899885/CPU/testbenches/testRCPU.v:64: Unsupported: Ignoring delay on this delayed statement.\n #1 rst = 0; $readmemb("../fact.rcpu", ram.memory); #9\n ^\n%Error: Exiting due to 7 error(s), 4 warning(s)\n' | 302,429 | module | module testRCPU;
reg clk;
reg rst;
wire[31:0] addr;
wire[15:0] read;
wire[15:0] write;
wire we;
wire re;
wire ready;
RAM2 ram(
.clk (clk),
.rst (rst),
.addr (addr[15:0]),
.rdata (read),
.wdata (write),
.we (we),
.re (re),
.ready (ready)
);
rcpu cpu(
.clk (!clk),
.rst (rst),
.memAddr (addr),
.memRead (read),
.memWrite (write),
.memWE (we),
.memRE (re),
.memReady (ready)
);
integer i;
integer clocks = 0;
integer stalled = 0;
initial begin
$dumpfile ("../test.vcd");
$dumpvars (0);
$dumpvars (1, ram.memory[0]);
$dumpvars (1, ram.memory[1]);
for (i = 16'hD000; i>16'hCFE0; i = i - 1)
$dumpvars (1, ram.memory[i]);
end
always #5 clk = !clk;
always @ (posedge clk) begin
clocks <= clocks + 1;
if (cpu.stall)
stalled <= stalled + 1;
end
initial begin
clk = 0;
rst = 1;
#1 rst = 0; $readmemb("../fact.rcpu", ram.memory); #9
#10000 $finish;
end
endmodule | module testRCPU; |
reg clk;
reg rst;
wire[31:0] addr;
wire[15:0] read;
wire[15:0] write;
wire we;
wire re;
wire ready;
RAM2 ram(
.clk (clk),
.rst (rst),
.addr (addr[15:0]),
.rdata (read),
.wdata (write),
.we (we),
.re (re),
.ready (ready)
);
rcpu cpu(
.clk (!clk),
.rst (rst),
.memAddr (addr),
.memRead (read),
.memWrite (write),
.memWE (we),
.memRE (re),
.memReady (ready)
);
integer i;
integer clocks = 0;
integer stalled = 0;
initial begin
$dumpfile ("../test.vcd");
$dumpvars (0);
$dumpvars (1, ram.memory[0]);
$dumpvars (1, ram.memory[1]);
for (i = 16'hD000; i>16'hCFE0; i = i - 1)
$dumpvars (1, ram.memory[i]);
end
always #5 clk = !clk;
always @ (posedge clk) begin
clocks <= clocks + 1;
if (cpu.stall)
stalled <= stalled + 1;
end
initial begin
clk = 0;
rst = 1;
#1 rst = 0; $readmemb("../fact.rcpu", ram.memory); #9
#10000 $finish;
end
endmodule | 1 |
138,486 | data/full_repos/permissive/84007307/DFF.v | 84,007,307 | DFF.v | v | 42 | 83 | [] | [] | [] | [(21, 41)] | null | null | 1: b"%Error: data/full_repos/permissive/84007307/DFF.v:31: Cannot find file containing module: 'INVERTER'\n INVERTER i1(D,Dnot);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER.sv\n INVERTER\n INVERTER.v\n INVERTER.sv\n obj_dir/INVERTER\n obj_dir/INVERTER.v\n obj_dir/INVERTER.sv\n%Error: data/full_repos/permissive/84007307/DFF.v:32: Cannot find file containing module: 'NOR'\n NOR n1(R,Dnot,D1);\n ^~~\n%Error: data/full_repos/permissive/84007307/DFF.v:33: Cannot find file containing module: 'DNlatch_NOR'\n DNlatch_NOR dn1(clk,D1,Q1,Q1not);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/84007307/DFF.v:34: Cannot find file containing module: 'NOR'\n NOR n2(R,Q1not,D2); \n ^~~\n%Error: data/full_repos/permissive/84007307/DFF.v:35: Cannot find file containing module: 'Dlatch_NAND'\n Dlatch_NAND d1(clk,D2,Q2,Q2not); \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/84007307/DFF.v:36: Cannot find file containing module: 'NOR'\n NOR n3(R,Q2not,Q);\n ^~~\n%Error: data/full_repos/permissive/84007307/DFF.v:37: Cannot find file containing module: 'INVERTER'\n INVERTER i2(Q,not_Q);\n ^~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 302,431 | module | module DFF(
input clk,
input D,
input R,
output Q,
output not_Q
);
wire Dnot,D1,Q1,Q1not,D2,Q2,Q2not;
INVERTER i1(D,Dnot);
NOR n1(R,Dnot,D1);
DNlatch_NOR dn1(clk,D1,Q1,Q1not);
NOR n2(R,Q1not,D2);
Dlatch_NAND d1(clk,D2,Q2,Q2not);
NOR n3(R,Q2not,Q);
INVERTER i2(Q,not_Q);
endmodule | module DFF(
input clk,
input D,
input R,
output Q,
output not_Q
); |
wire Dnot,D1,Q1,Q1not,D2,Q2,Q2not;
INVERTER i1(D,Dnot);
NOR n1(R,Dnot,D1);
DNlatch_NOR dn1(clk,D1,Q1,Q1not);
NOR n2(R,Q1not,D2);
Dlatch_NAND d1(clk,D2,Q2,Q2not);
NOR n3(R,Q2not,Q);
INVERTER i2(Q,not_Q);
endmodule | 0 |
138,487 | data/full_repos/permissive/84007307/Dlatch_NAND.v | 84,007,307 | Dlatch_NAND.v | v | 39 | 83 | [] | [] | [] | [(21, 38)] | null | null | 1: b"%Error: data/full_repos/permissive/84007307/Dlatch_NAND.v:30: Cannot find file containing module: 'NAND'\n NAND n1(D,D,not_D);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NAND\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NAND.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NAND.sv\n NAND\n NAND.v\n NAND.sv\n obj_dir/NAND\n obj_dir/NAND.v\n obj_dir/NAND.sv\n%Error: data/full_repos/permissive/84007307/Dlatch_NAND.v:31: Cannot find file containing module: 'NAND'\n NAND n2(D,En,A);\n ^~~~\n%Error: data/full_repos/permissive/84007307/Dlatch_NAND.v:32: Cannot find file containing module: 'NAND'\n NAND n3(not_D,En,B);\n ^~~~\n%Error: data/full_repos/permissive/84007307/Dlatch_NAND.v:33: Cannot find file containing module: 'NAND'\n NAND n4(A,not_Q,Q);\n ^~~~\n%Error: data/full_repos/permissive/84007307/Dlatch_NAND.v:34: Cannot find file containing module: 'NAND'\n NAND n5(B,Q,not_Q); \n ^~~~\n%Error: Exiting due to 5 error(s)\n" | 302,432 | module | module Dlatch_NAND(
input En,
input D,
output Q,
output not_Q
);
wire not_D,A,B ;
NAND n1(D,D,not_D);
NAND n2(D,En,A);
NAND n3(not_D,En,B);
NAND n4(A,not_Q,Q);
NAND n5(B,Q,not_Q);
endmodule | module Dlatch_NAND(
input En,
input D,
output Q,
output not_Q
); |
wire not_D,A,B ;
NAND n1(D,D,not_D);
NAND n2(D,En,A);
NAND n3(not_D,En,B);
NAND n4(A,not_Q,Q);
NAND n5(B,Q,not_Q);
endmodule | 0 |
138,488 | data/full_repos/permissive/84007307/Dlatch_NOR.v | 84,007,307 | Dlatch_NOR.v | v | 40 | 83 | [] | [] | [] | [(21, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/84007307/Dlatch_NOR.v:30: Cannot find file containing module: 'NOR'\n NOR n1(D,D,not_D);\n ^~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NOR\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NOR.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NOR.sv\n NOR\n NOR.v\n NOR.sv\n obj_dir/NOR\n obj_dir/NOR.v\n obj_dir/NOR.sv\n%Error: data/full_repos/permissive/84007307/Dlatch_NOR.v:31: Cannot find file containing module: 'NOR'\n NOR n2(En,En,not_En);\n ^~~\n%Error: data/full_repos/permissive/84007307/Dlatch_NOR.v:32: Cannot find file containing module: 'NOR'\n NOR n3(D,not_En,A);\n ^~~\n%Error: data/full_repos/permissive/84007307/Dlatch_NOR.v:33: Cannot find file containing module: 'NOR'\n NOR n4(not_D,not_En,B);\n ^~~\n%Error: data/full_repos/permissive/84007307/Dlatch_NOR.v:34: Cannot find file containing module: 'NOR'\n NOR n5(A,not_Q,Q);\n ^~~\n%Error: data/full_repos/permissive/84007307/Dlatch_NOR.v:35: Cannot find file containing module: 'NOR'\n NOR n6(B,Q,not_Q);\n ^~~\n%Error: Exiting due to 6 error(s)\n" | 302,433 | module | module Dlatch_NOR(
input En,
input D,
output Q,
output not_Q
);
wire not_D,not_En,A,B ;
NOR n1(D,D,not_D);
NOR n2(En,En,not_En);
NOR n3(D,not_En,A);
NOR n4(not_D,not_En,B);
NOR n5(A,not_Q,Q);
NOR n6(B,Q,not_Q);
endmodule | module Dlatch_NOR(
input En,
input D,
output Q,
output not_Q
); |
wire not_D,not_En,A,B ;
NOR n1(D,D,not_D);
NOR n2(En,En,not_En);
NOR n3(D,not_En,A);
NOR n4(not_D,not_En,B);
NOR n5(A,not_Q,Q);
NOR n6(B,Q,not_Q);
endmodule | 0 |
138,489 | data/full_repos/permissive/84007307/FULL_ADDER.v | 84,007,307 | FULL_ADDER.v | v | 38 | 83 | [] | [] | [] | [(21, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/84007307/FULL_ADDER.v:29: Cannot find file containing module: 'XOR'\n XOR x1(A,B,P);\n ^~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/XOR\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/XOR.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/XOR.sv\n XOR\n XOR.v\n XOR.sv\n obj_dir/XOR\n obj_dir/XOR.v\n obj_dir/XOR.sv\n%Error: data/full_repos/permissive/84007307/FULL_ADDER.v:30: Cannot find file containing module: 'NAND'\n NAND n1(A,B,G); \n ^~~~\n%Error: data/full_repos/permissive/84007307/FULL_ADDER.v:32: Cannot find file containing module: 'XOR'\n XOR x2(P,Ci,S);\n ^~~\n%Error: data/full_repos/permissive/84007307/FULL_ADDER.v:33: Cannot find file containing module: 'NAND'\n NAND n2(P,Ci,i1);\n ^~~~\n%Error: data/full_repos/permissive/84007307/FULL_ADDER.v:35: Cannot find file containing module: 'NAND'\n NAND n3(G,i1,Co);\n ^~~~\n%Error: Exiting due to 5 error(s)\n" | 302,436 | module | module FULL_ADDER(
input A,
input B,
input Ci,
output S,
output Co
);
wire P , i1 , G ;
XOR x1(A,B,P);
NAND n1(A,B,G);
XOR x2(P,Ci,S);
NAND n2(P,Ci,i1);
NAND n3(G,i1,Co);
endmodule | module FULL_ADDER(
input A,
input B,
input Ci,
output S,
output Co
); |
wire P , i1 , G ;
XOR x1(A,B,P);
NAND n1(A,B,G);
XOR x2(P,Ci,S);
NAND n2(P,Ci,i1);
NAND n3(G,i1,Co);
endmodule | 0 |
138,490 | data/full_repos/permissive/84007307/INVERTER.v | 84,007,307 | INVERTER.v | v | 29 | 83 | [] | [] | [] | null | line:26: before: "(" | data/verilator_xmls/878e101d-ff94-4a83-a066-368b8f2cd078.xml | null | 302,437 | module | module INVERTER(
input in,
output out
);
buf#(2,1) (out,~in);
endmodule | module INVERTER(
input in,
output out
); |
buf#(2,1) (out,~in);
endmodule | 0 |
138,491 | data/full_repos/permissive/84007307/MUX2.v | 84,007,307 | MUX2.v | v | 36 | 83 | [] | [] | [] | [(21, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/84007307/MUX2.v:29: Cannot find file containing module: 'INVERTER'\n INVERTER i1(sel,notS);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER.sv\n INVERTER\n INVERTER.v\n INVERTER.sv\n obj_dir/INVERTER\n obj_dir/INVERTER.v\n obj_dir/INVERTER.sv\n%Error: data/full_repos/permissive/84007307/MUX2.v:30: Cannot find file containing module: 'NAND'\n NAND n1(notS,in[0],A0);\n ^~~~\n%Error: data/full_repos/permissive/84007307/MUX2.v:31: Cannot find file containing module: 'NAND'\n NAND n2(sel,in[1],A1);\n ^~~~\n%Error: data/full_repos/permissive/84007307/MUX2.v:32: Cannot find file containing module: 'NAND'\n NAND n3(A1,A0,out);\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 302,438 | module | module MUX2(
input [1:0] in,
input sel,
output out
);
wire notS,A0,A1 ;
INVERTER i1(sel,notS);
NAND n1(notS,in[0],A0);
NAND n2(sel,in[1],A1);
NAND n3(A1,A0,out);
endmodule | module MUX2(
input [1:0] in,
input sel,
output out
); |
wire notS,A0,A1 ;
INVERTER i1(sel,notS);
NAND n1(notS,in[0],A0);
NAND n2(sel,in[1],A1);
NAND n3(A1,A0,out);
endmodule | 0 |
138,492 | data/full_repos/permissive/84007307/MUX32.v | 84,007,307 | MUX32.v | v | 50 | 83 | [] | [] | [] | [(21, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/84007307/MUX32.v:34: Cannot find file containing module: 'MUX2'\n MUX2 m(in[2*i+1:2*i], sel[0] , A[i]);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX2\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX2.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX2.sv\n MUX2\n MUX2.v\n MUX2.sv\n obj_dir/MUX2\n obj_dir/MUX2.v\n obj_dir/MUX2.sv\n%Error: data/full_repos/permissive/84007307/MUX32.v:37: Cannot find file containing module: 'MUX2'\n MUX2 m(A[2*l+1:2*l], sel[1] , B[l]);\n ^~~~\n%Error: data/full_repos/permissive/84007307/MUX32.v:40: Cannot find file containing module: 'MUX2'\n MUX2 m(B[2*j+1:2*j], sel[2] , C[j]);\n ^~~~\n%Error: data/full_repos/permissive/84007307/MUX32.v:43: Cannot find file containing module: 'MUX2'\n MUX2 m(C[2*k+1:2*k], sel[3] , D[k]);\n ^~~~\n%Error: data/full_repos/permissive/84007307/MUX32.v:46: Cannot find file containing module: 'MUX2'\n MUX2 m4(D, sel[4] , out); \n ^~~~\n%Error: Exiting due to 5 error(s)\n" | 302,439 | module | module MUX32(
input [31:0] in,
input [4:0] sel,
output out
);
wire [16:0] A;
wire [7:0] B;
wire [3:0] C;
wire [1:0] D;
generate
genvar i,j,k,l;
for (i=0; i < 16; i=i+1) begin: m0
MUX2 m(in[2*i+1:2*i], sel[0] , A[i]);
end
for (l=0; l < 8; l=l+1) begin: m1
MUX2 m(A[2*l+1:2*l], sel[1] , B[l]);
end
for (j=0; j < 4; j=j+1) begin: m2
MUX2 m(B[2*j+1:2*j], sel[2] , C[j]);
end
for (k=0; k < 2; k=k+1) begin: m3
MUX2 m(C[2*k+1:2*k], sel[3] , D[k]);
end
endgenerate
MUX2 m4(D, sel[4] , out);
endmodule | module MUX32(
input [31:0] in,
input [4:0] sel,
output out
); |
wire [16:0] A;
wire [7:0] B;
wire [3:0] C;
wire [1:0] D;
generate
genvar i,j,k,l;
for (i=0; i < 16; i=i+1) begin: m0
MUX2 m(in[2*i+1:2*i], sel[0] , A[i]);
end
for (l=0; l < 8; l=l+1) begin: m1
MUX2 m(A[2*l+1:2*l], sel[1] , B[l]);
end
for (j=0; j < 4; j=j+1) begin: m2
MUX2 m(B[2*j+1:2*j], sel[2] , C[j]);
end
for (k=0; k < 2; k=k+1) begin: m3
MUX2 m(C[2*k+1:2*k], sel[3] , D[k]);
end
endgenerate
MUX2 m4(D, sel[4] , out);
endmodule | 0 |
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