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138,785 | data/full_repos/permissive/86135381/io_init_adc.v | 86,135,381 | io_init_adc.v | v | 123 | 81 | [] | [] | [] | [(1, 122)] | null | null | 1: b'%Error: data/full_repos/permissive/86135381/io_init_adc.v:45: Cannot find file containing module: \'io_spi\'\n io_spi #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.sv\n io_spi\n io_spi.v\n io_spi.sv\n obj_dir/io_spi\n obj_dir/io_spi.v\n obj_dir/io_spi.sv\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_adc.v:94: Bit extraction of array[1:0] requires 1 bit index, not 8 bits.\n : ... In instance io_init_adc\n rom_data <= adc_calibrated ? mem_normal[rom_addr] : mem_test[rom_addr];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_adc.v:94: Bit extraction of array[18:0] requires 5 bit index, not 8 bits.\n : ... In instance io_init_adc\n rom_data <= adc_calibrated ? mem_normal[rom_addr] : mem_test[rom_addr];\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 302,795 | module | module io_init_adc (
input wire rst,
input wire clk,
input wire init_ads_ena,
output wire init_ads_done,
output wire spi_clk,
output wire spi_mosi,
output wire ads_n_en,
output wire adc_reset,
input wire adc_calibrated);
localparam WIDTH = 16;
localparam IDLE = 6'b000001;
localparam RESET = 6'b000010;
localparam START_SPI = 6'b000100;
localparam WRITE_DATA = 6'b001000;
localparam INC_ADDR = 6'b010000;
localparam FINISHED = 6'b100000;
reg [5:0] state;
reg [5:0] next_state;
reg rst_lcl;
reg start_tx;
wire done_tx;
wire spi_clk_n;
wire last_addr;
reg [7:0] rom_addr;
wire [7:0] end_addr;
reg [WIDTH-1:0] mem_test [18:0];
reg [WIDTH-1:0] mem_normal [1:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
assign adc_reset = (state == RESET) && !adc_calibrated;
assign spi_clk = ~spi_clk_n;
io_spi #(
.WIDTH (WIDTH),
.FLIP (0),
.SCLK_TIME (4))
io_spi_ads (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_clk_n),
.spi_mosi (spi_mosi),
.spi_cs (ads_n_en),
.spi_miso (1'b0),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_ads_ena) next_state = RESET;
RESET : next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (init_ads_ena == 0) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_ads_done = state == FINISHED;
assign end_addr = adc_calibrated ? 1 : 18;
assign last_addr = rom_addr == end_addr;
always @(posedge clk) begin
if (state == IDLE) rom_addr <= 0;
else if (state == INC_ADDR) rom_addr <= rom_addr + 1;
rom_data <= adc_calibrated ? mem_normal[rom_addr] : mem_test[rom_addr];
start_tx <= state == START_SPI;
end
initial begin
mem_test[00] = 16'h0080;
mem_test[01] = 16'h2000;
mem_test[02] = 16'h3F00;
mem_test[03] = 16'h4008;
mem_test[04] = 16'h4180;
mem_test[05] = 16'h4400;
mem_test[06] = 16'h5044;
mem_test[07] = 16'h5100;
mem_test[08] = 16'h5200;
mem_test[09] = 16'h5300;
mem_test[10] = 16'h55C0;
mem_test[11] = 16'h5700;
mem_test[12] = 16'h6204;
mem_test[13] = 16'h6300;
mem_test[14] = 16'h6600;
mem_test[15] = 16'h68C0;
mem_test[16] = 16'h6A00;
mem_test[17] = 16'h7504;
mem_test[18] = 16'h7600;
mem_normal[0] = 16'h6200;
mem_normal[1] = 16'h7500;
end
endmodule | module io_init_adc (
input wire rst,
input wire clk,
input wire init_ads_ena,
output wire init_ads_done,
output wire spi_clk,
output wire spi_mosi,
output wire ads_n_en,
output wire adc_reset,
input wire adc_calibrated); |
localparam WIDTH = 16;
localparam IDLE = 6'b000001;
localparam RESET = 6'b000010;
localparam START_SPI = 6'b000100;
localparam WRITE_DATA = 6'b001000;
localparam INC_ADDR = 6'b010000;
localparam FINISHED = 6'b100000;
reg [5:0] state;
reg [5:0] next_state;
reg rst_lcl;
reg start_tx;
wire done_tx;
wire spi_clk_n;
wire last_addr;
reg [7:0] rom_addr;
wire [7:0] end_addr;
reg [WIDTH-1:0] mem_test [18:0];
reg [WIDTH-1:0] mem_normal [1:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
assign adc_reset = (state == RESET) && !adc_calibrated;
assign spi_clk = ~spi_clk_n;
io_spi #(
.WIDTH (WIDTH),
.FLIP (0),
.SCLK_TIME (4))
io_spi_ads (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_clk_n),
.spi_mosi (spi_mosi),
.spi_cs (ads_n_en),
.spi_miso (1'b0),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_ads_ena) next_state = RESET;
RESET : next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (init_ads_ena == 0) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_ads_done = state == FINISHED;
assign end_addr = adc_calibrated ? 1 : 18;
assign last_addr = rom_addr == end_addr;
always @(posedge clk) begin
if (state == IDLE) rom_addr <= 0;
else if (state == INC_ADDR) rom_addr <= rom_addr + 1;
rom_data <= adc_calibrated ? mem_normal[rom_addr] : mem_test[rom_addr];
start_tx <= state == START_SPI;
end
initial begin
mem_test[00] = 16'h0080;
mem_test[01] = 16'h2000;
mem_test[02] = 16'h3F00;
mem_test[03] = 16'h4008;
mem_test[04] = 16'h4180;
mem_test[05] = 16'h4400;
mem_test[06] = 16'h5044;
mem_test[07] = 16'h5100;
mem_test[08] = 16'h5200;
mem_test[09] = 16'h5300;
mem_test[10] = 16'h55C0;
mem_test[11] = 16'h5700;
mem_test[12] = 16'h6204;
mem_test[13] = 16'h6300;
mem_test[14] = 16'h6600;
mem_test[15] = 16'h68C0;
mem_test[16] = 16'h6A00;
mem_test[17] = 16'h7504;
mem_test[18] = 16'h7600;
mem_normal[0] = 16'h6200;
mem_normal[1] = 16'h7500;
end
endmodule | 0 |
138,786 | data/full_repos/permissive/86135381/io_init_clock.v | 86,135,381 | io_init_clock.v | v | 122 | 84 | [] | [] | [] | [(1, 121)] | null | null | 1: b'%Error: data/full_repos/permissive/86135381/io_init_clock.v:48: Cannot find file containing module: \'io_spi\'\n io_spi #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.sv\n io_spi\n io_spi.v\n io_spi.sv\n obj_dir/io_spi\n obj_dir/io_spi.v\n obj_dir/io_spi.sv\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_clock.v:94: Bit extraction of array[12:0] requires 4 bit index, not 8 bits.\n : ... In instance io_init_clock\n rom_data <= mem[rom_addr];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 302,796 | module | module io_init_clock (
input wire rst,
input wire clk,
input wire init_cdce_ena,
output wire init_cdce_done,
output wire spi_sclk,
output wire spi_sdata,
output wire cdce_n_en,
input wire cdce_miso,
output wire ref_en,
output wire cdce_n_reset,
output wire cdce_n_pd);
localparam WIDTH = 32;
localparam END_ADDR = 12;
localparam ENABLE_INTERNAL_CLOCK = 1;
localparam CLOCK_NOT_RESET = 1;
localparam CLOCK_NOT_POWER_DOWN = 1;
localparam IDLE = 5'b00001;
localparam START_SPI = 5'b00010;
localparam WRITE_DATA = 5'b00100;
localparam INC_ADDR = 5'b01000;
localparam FINISHED = 5'b10000;
reg [4:0] state, next_state;
reg rst_lcl;
reg start_tx;
wire done_tx;
wire last_addr;
reg [7:0] rom_addr;
reg [WIDTH-1:0] mem [END_ADDR:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
assign ref_en = ENABLE_INTERNAL_CLOCK;
assign cdce_n_reset = CLOCK_NOT_RESET;
assign cdce_n_pd = CLOCK_NOT_POWER_DOWN;
io_spi #(
.WIDTH (WIDTH),
.FLIP (1),
.SCLK_TIME (4))
io_spi_cdce (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_sclk),
.spi_mosi (spi_sdata),
.spi_cs (cdce_n_en),
.spi_miso (cdce_miso),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_cdce_ena) next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (~init_cdce_ena) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_cdce_done = state == FINISHED;
assign last_addr = rom_addr == END_ADDR;
always @(posedge clk) begin
if (state == IDLE) rom_addr <= 0;
else if (state == INC_ADDR) rom_addr <= rom_addr + 1;
rom_data <= mem[rom_addr];
start_tx <= state == START_SPI;
end
localparam DIV1 = 7'b0100000;
localparam DIV2 = 7'b1000000;
localparam DIV4 = 7'b1000010;
initial begin
mem[00] = 32'h683C0250;
mem[01] = 32'h68000271;
mem[02] = {8'h83,DIV4,13'h0000,4'h2};
mem[03] = 32'h68000003;
mem[04] = {8'hE9,DIV4,13'h0000,4'h4};
mem[05] = 32'h68000005;
mem[06] = 32'h68000006;
mem[07] = {8'h83,DIV2,13'h0015,4'h7};
mem[08] = 32'h680001D8;
mem[09] = 32'h68050C49;
mem[10] = 32'h05FC270A;
mem[11] = 32'h9000048B;
mem[12] = 32'h0000180C;
end
endmodule | module io_init_clock (
input wire rst,
input wire clk,
input wire init_cdce_ena,
output wire init_cdce_done,
output wire spi_sclk,
output wire spi_sdata,
output wire cdce_n_en,
input wire cdce_miso,
output wire ref_en,
output wire cdce_n_reset,
output wire cdce_n_pd); |
localparam WIDTH = 32;
localparam END_ADDR = 12;
localparam ENABLE_INTERNAL_CLOCK = 1;
localparam CLOCK_NOT_RESET = 1;
localparam CLOCK_NOT_POWER_DOWN = 1;
localparam IDLE = 5'b00001;
localparam START_SPI = 5'b00010;
localparam WRITE_DATA = 5'b00100;
localparam INC_ADDR = 5'b01000;
localparam FINISHED = 5'b10000;
reg [4:0] state, next_state;
reg rst_lcl;
reg start_tx;
wire done_tx;
wire last_addr;
reg [7:0] rom_addr;
reg [WIDTH-1:0] mem [END_ADDR:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
assign ref_en = ENABLE_INTERNAL_CLOCK;
assign cdce_n_reset = CLOCK_NOT_RESET;
assign cdce_n_pd = CLOCK_NOT_POWER_DOWN;
io_spi #(
.WIDTH (WIDTH),
.FLIP (1),
.SCLK_TIME (4))
io_spi_cdce (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_sclk),
.spi_mosi (spi_sdata),
.spi_cs (cdce_n_en),
.spi_miso (cdce_miso),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_cdce_ena) next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (~init_cdce_ena) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_cdce_done = state == FINISHED;
assign last_addr = rom_addr == END_ADDR;
always @(posedge clk) begin
if (state == IDLE) rom_addr <= 0;
else if (state == INC_ADDR) rom_addr <= rom_addr + 1;
rom_data <= mem[rom_addr];
start_tx <= state == START_SPI;
end
localparam DIV1 = 7'b0100000;
localparam DIV2 = 7'b1000000;
localparam DIV4 = 7'b1000010;
initial begin
mem[00] = 32'h683C0250;
mem[01] = 32'h68000271;
mem[02] = {8'h83,DIV4,13'h0000,4'h2};
mem[03] = 32'h68000003;
mem[04] = {8'hE9,DIV4,13'h0000,4'h4};
mem[05] = 32'h68000005;
mem[06] = 32'h68000006;
mem[07] = {8'h83,DIV2,13'h0015,4'h7};
mem[08] = 32'h680001D8;
mem[09] = 32'h68050C49;
mem[10] = 32'h05FC270A;
mem[11] = 32'h9000048B;
mem[12] = 32'h0000180C;
end
endmodule | 0 |
138,787 | data/full_repos/permissive/86135381/io_init_dac.v | 86,135,381 | io_init_dac.v | v | 125 | 85 | [] | [] | [] | [(1, 124)] | null | null | 1: b'%Error: data/full_repos/permissive/86135381/io_init_dac.v:37: Cannot find file containing module: \'io_spi\'\n io_spi #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.sv\n io_spi\n io_spi.v\n io_spi.sv\n obj_dir/io_spi\n obj_dir/io_spi.v\n obj_dir/io_spi.sv\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_dac.v:84: Bit extraction of array[31:0] requires 5 bit index, not 8 bits.\n : ... In instance io_init_dac\n rom_data <= mem[rom_addr];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 302,797 | module | module io_init_dac (
input wire rst,
input wire clk,
input wire init_dac_ena,
output wire init_dac_done,
output wire spi_sclk,
output wire spi_sdata,
output wire dac_n_en);
localparam WIDTH = 16;
localparam END_ADDR = 31;
localparam IDLE = 5'b00001;
localparam START_SPI = 5'b00010;
localparam WRITE_DATA = 5'b00100;
localparam INC_ADDR = 5'b01000;
localparam FINISHED = 5'b10000;
reg rst_lcl;
reg start_tx;
wire done_tx;
wire last_addr;
reg [7:0] rom_addr;
reg [4:0] state;
reg [4:0] next_state;
reg [WIDTH-1:0] mem [END_ADDR:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
io_spi #(
.WIDTH (WIDTH),
.FLIP (0),
.SCLK_TIME (4))
io_spi_ads (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_sclk),
.spi_mosi (spi_sdata),
.spi_cs (dac_n_en),
.spi_miso (1'b0),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_dac_ena) next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (~init_dac_ena) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_dac_done = state == FINISHED;
assign last_addr = rom_addr == END_ADDR;
always @(posedge clk) begin
if (state == IDLE) rom_addr <= 0;
else if (state == INC_ADDR) rom_addr <= rom_addr + 1;
rom_data <= mem[rom_addr];
start_tx <= state == START_SPI;
end
initial begin
mem[00] = 16'h0070;
mem[01] = 16'h0121;
mem[02] = 16'h0200;
mem[03] = 16'h0310;
mem[04] = 16'h04FF;
mem[05] = 16'h0500;
mem[06] = 16'h0600;
mem[07] = 16'h0700;
mem[08] = 16'h0800;
mem[09] = 16'h0955;
mem[10] = 16'h0AAA;
mem[11] = 16'h0B55;
mem[12] = 16'h0CAA;
mem[13] = 16'h0D55;
mem[14] = 16'h0EAA;
mem[15] = 16'h0F55;
mem[16] = 16'h10AA;
mem[17] = 16'h1124;
mem[18] = 16'h1202;
mem[19] = 16'h13C2;
mem[20] = 16'h1400;
mem[21] = 16'h1500;
mem[22] = 16'h1600;
mem[23] = 16'h1700;
mem[24] = 16'h1803;
mem[25] = 16'h1900;
mem[26] = 16'h1A00;
mem[27] = 16'h1B00;
mem[28] = 16'h1C00;
mem[29] = 16'h1D00;
mem[30] = 16'h1E24;
mem[31] = 16'h1F00;
end
endmodule | module io_init_dac (
input wire rst,
input wire clk,
input wire init_dac_ena,
output wire init_dac_done,
output wire spi_sclk,
output wire spi_sdata,
output wire dac_n_en); |
localparam WIDTH = 16;
localparam END_ADDR = 31;
localparam IDLE = 5'b00001;
localparam START_SPI = 5'b00010;
localparam WRITE_DATA = 5'b00100;
localparam INC_ADDR = 5'b01000;
localparam FINISHED = 5'b10000;
reg rst_lcl;
reg start_tx;
wire done_tx;
wire last_addr;
reg [7:0] rom_addr;
reg [4:0] state;
reg [4:0] next_state;
reg [WIDTH-1:0] mem [END_ADDR:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
io_spi #(
.WIDTH (WIDTH),
.FLIP (0),
.SCLK_TIME (4))
io_spi_ads (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_sclk),
.spi_mosi (spi_sdata),
.spi_cs (dac_n_en),
.spi_miso (1'b0),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_dac_ena) next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (~init_dac_ena) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_dac_done = state == FINISHED;
assign last_addr = rom_addr == END_ADDR;
always @(posedge clk) begin
if (state == IDLE) rom_addr <= 0;
else if (state == INC_ADDR) rom_addr <= rom_addr + 1;
rom_data <= mem[rom_addr];
start_tx <= state == START_SPI;
end
initial begin
mem[00] = 16'h0070;
mem[01] = 16'h0121;
mem[02] = 16'h0200;
mem[03] = 16'h0310;
mem[04] = 16'h04FF;
mem[05] = 16'h0500;
mem[06] = 16'h0600;
mem[07] = 16'h0700;
mem[08] = 16'h0800;
mem[09] = 16'h0955;
mem[10] = 16'h0AAA;
mem[11] = 16'h0B55;
mem[12] = 16'h0CAA;
mem[13] = 16'h0D55;
mem[14] = 16'h0EAA;
mem[15] = 16'h0F55;
mem[16] = 16'h10AA;
mem[17] = 16'h1124;
mem[18] = 16'h1202;
mem[19] = 16'h13C2;
mem[20] = 16'h1400;
mem[21] = 16'h1500;
mem[22] = 16'h1600;
mem[23] = 16'h1700;
mem[24] = 16'h1803;
mem[25] = 16'h1900;
mem[26] = 16'h1A00;
mem[27] = 16'h1B00;
mem[28] = 16'h1C00;
mem[29] = 16'h1D00;
mem[30] = 16'h1E24;
mem[31] = 16'h1F00;
end
endmodule | 0 |
138,788 | data/full_repos/permissive/86135381/io_init_monitor.v | 86,135,381 | io_init_monitor.v | v | 109 | 84 | [] | [] | [] | [(1, 108)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/86135381/io_init_monitor.v:68: Signal definition not found, creating implicitly: \'last_addr\'\n WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86135381/io_init_monitor.v:40: Cannot find file containing module: \'io_spi\'\n io_spi #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_spi.sv\n io_spi\n io_spi.v\n io_spi.sv\n obj_dir/io_spi\n obj_dir/io_spi.v\n obj_dir/io_spi.sv\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_monitor.v:89: Bit extraction of array[11:0] requires 4 bit index, not 8 bits.\n : ... In instance io_init_monitor\n rom_data <= mem[rom_addr];\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 302,798 | module | module io_init_monitor (
input wire rst,
input wire clk,
input wire init_mon_ena,
output wire init_mon_done,
output wire spi_clk,
output wire spi_mosi,
output wire mon_cs,
output wire mon_n_reset);
localparam WIDTH = 32;
localparam END_ADDR = 11;
localparam IDLE = 5'b00001;
localparam START_SPI = 5'b00010;
localparam WRITE_DATA = 5'b00100;
localparam INC_ADDR = 5'b01000;
localparam FINISHED = 5'b10000;
reg rst_lcl;
reg [4:0] state, next_state;
reg start_tx;
wire done_tx;
wire spi_clk_n;
reg [7:0] rom_addr;
reg [WIDTH-1:0] mem [END_ADDR:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
assign mon_n_reset = 0;
assign spi_clk = ~spi_clk_n;
io_spi #(
.WIDTH (WIDTH),
.FLIP (0),
.SCLK_TIME (4))
io_spi_monitor (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_clk_n),
.spi_mosi (spi_mosi),
.spi_cs (mon_cs),
.spi_miso (0),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_mon_ena) next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (~init_mon_ena) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_mon_done = state == FINISHED;
assign last_addr = rom_addr == END_ADDR;
always @(posedge clk) begin
if (state == IDLE)
rom_addr <= 0;
else if (state == INC_ADDR)
rom_addr <= rom_addr + 1;
rom_data <= mem[rom_addr];
start_tx <= state == START_SPI;
end
initial begin
mem[00] = 32'h000AFFFF;
mem[01] = 32'h010A0000;
mem[02] = 32'h010B8080;
mem[03] = 32'h010D8000;
mem[04] = 32'h010E0B16;
mem[05] = 32'h010F0A08;
mem[06] = 32'h01100B16;
mem[07] = 32'h01110A08;
mem[08] = 32'h01120C18;
mem[09] = 32'h01130AF1;
mem[10] = 32'h01140C18;
mem[11] = 32'h01150AF1;
end
endmodule | module io_init_monitor (
input wire rst,
input wire clk,
input wire init_mon_ena,
output wire init_mon_done,
output wire spi_clk,
output wire spi_mosi,
output wire mon_cs,
output wire mon_n_reset); |
localparam WIDTH = 32;
localparam END_ADDR = 11;
localparam IDLE = 5'b00001;
localparam START_SPI = 5'b00010;
localparam WRITE_DATA = 5'b00100;
localparam INC_ADDR = 5'b01000;
localparam FINISHED = 5'b10000;
reg rst_lcl;
reg [4:0] state, next_state;
reg start_tx;
wire done_tx;
wire spi_clk_n;
reg [7:0] rom_addr;
reg [WIDTH-1:0] mem [END_ADDR:0];
reg [WIDTH-1:0] rom_data;
always @(posedge clk)
rst_lcl <= rst;
assign mon_n_reset = 0;
assign spi_clk = ~spi_clk_n;
io_spi #(
.WIDTH (WIDTH),
.FLIP (0),
.SCLK_TIME (4))
io_spi_monitor (
.rst (rst_lcl),
.clk (clk),
.start_tx (start_tx),
.done_tx (done_tx),
.spi_clk (spi_clk_n),
.spi_mosi (spi_mosi),
.spi_cs (mon_cs),
.spi_miso (0),
.tx_data (rom_data),
.rx_data ());
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_mon_ena) next_state = START_SPI;
START_SPI : next_state = WRITE_DATA;
WRITE_DATA : if (done_tx & last_addr) next_state = FINISHED;
else if (done_tx) next_state = INC_ADDR;
INC_ADDR : next_state = START_SPI;
FINISHED : if (~init_mon_ena) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_mon_done = state == FINISHED;
assign last_addr = rom_addr == END_ADDR;
always @(posedge clk) begin
if (state == IDLE)
rom_addr <= 0;
else if (state == INC_ADDR)
rom_addr <= rom_addr + 1;
rom_data <= mem[rom_addr];
start_tx <= state == START_SPI;
end
initial begin
mem[00] = 32'h000AFFFF;
mem[01] = 32'h010A0000;
mem[02] = 32'h010B8080;
mem[03] = 32'h010D8000;
mem[04] = 32'h010E0B16;
mem[05] = 32'h010F0A08;
mem[06] = 32'h01100B16;
mem[07] = 32'h01110A08;
mem[08] = 32'h01120C18;
mem[09] = 32'h01130AF1;
mem[10] = 32'h01140C18;
mem[11] = 32'h01150AF1;
end
endmodule | 0 |
138,789 | data/full_repos/permissive/86135381/io_init_offsets.v | 86,135,381 | io_init_offsets.v | v | 152 | 81 | [] | [] | [] | [(1, 151)] | null | null | 1: b'%Error: data/full_repos/permissive/86135381/io_init_offsets.v:50: Cannot find file containing module: \'i2c_master\'\n i2c_master #(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/i2c_master\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/i2c_master.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/i2c_master.sv\n i2c_master\n i2c_master.v\n i2c_master.sv\n obj_dir/i2c_master\n obj_dir/i2c_master.v\n obj_dir/i2c_master.sv\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_offsets.v:120: Bit extraction of array[12:0] requires 4 bit index, not 8 bits.\n : ... In instance io_init_offsets\n data_buf <= data[data_addr];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_offsets.v:121: Bit extraction of array[4:0] requires 3 bit index, not 8 bits.\n : ... In instance io_init_offsets\n addr_buf <= addr[addr_addr];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_init_offsets.v:122: Bit extraction of array[4:0] requires 3 bit index, not 8 bits.\n : ... In instance io_init_offsets\n dev_buf <= dev[dev_addr];\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 302,799 | module | module io_init_offsets (
input wire rst,
input wire clk,
input wire start,
output wire iic_rst,
inout wire iic_scl,
inout wire iic_sda);
localparam IDLE = 8'b00000001;
localparam START = 8'b00000010;
localparam WAIT = 8'b00000100;
localparam INC = 8'b00001000;
localparam LOAD_INC = 8'b00010000;
localparam WAIT_LAST = 8'b00100000;
localparam NEXT = 8'b01000000;
localparam DONE = 8'b10000000;
localparam OFFSET_ADC_A = 12'h850;
localparam OFFSET_ADC_B = 12'h840;
localparam OFFSET_DAC_A = 12'h800;
localparam OFFSET_DAC_B = 12'h800;
reg rst_lcl;
reg start_tx;
wire busy;
wire load;
wire last_address;
wire last_device;
reg [7:0] data_addr;
reg [7:0] addr_addr;
reg [7:0] dev_addr;
reg [7:0] addr [4:0];
reg [7:0] dev [4:0];
reg [7:0] data [12:0];
reg [7:0] addr_buf;
reg [7:0] data_buf;
reg [7:0] dev_buf;
reg [7:0] state;
reg [7:0] next_state;
always @(posedge clk)
rst_lcl <= rst;
i2c_master #(
.input_clk (200_000_000),
.bus_clk (400_000))
i2c_master_inst (
.clk (clk),
.rst (rst_lcl),
.ena (start_tx),
.addr (addr_buf[7:1]),
.rw (addr_buf[0]),
.data_wr (data_buf),
.busy (busy),
.load (load),
.data_rd (),
.sda (iic_sda),
.scl (iic_scl));
assign iic_rst = ~rst_lcl;
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (start) next_state = START;
START : if (busy)
if (last_address) next_state = WAIT_LAST;
else next_state = WAIT;
WAIT : if (load) next_state = INC;
INC : next_state = LOAD_INC;
LOAD_INC : if (!load)
if (last_address) next_state = WAIT_LAST;
else next_state = WAIT;
WAIT_LAST : if (!busy)
if (last_device) next_state = DONE;
else next_state = NEXT;
NEXT : next_state = START;
DONE : if (~start) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign last_device = (dev_addr == 4) && last_address;
assign last_address = dev_buf == data_addr;
always @(posedge clk)
if (rst_lcl) start_tx <= 0;
else if (state == START) start_tx <= 1;
else if (state == WAIT_LAST) start_tx <= 0;
always @(posedge clk) begin
if (state == IDLE) addr_addr <= 0;
else if (state == NEXT) addr_addr <= addr_addr + 1;
if (state == IDLE) data_addr <= 0;
else if (state == NEXT) data_addr <= data_addr + 1;
else if (state == INC) data_addr <= data_addr + 1;
if (state == IDLE) dev_addr <= 0;
else if (state == NEXT) dev_addr <= dev_addr + 1;
data_buf <= data[data_addr];
addr_buf <= addr[addr_addr];
dev_buf <= dev[dev_addr];
end
initial begin
addr[0] = {7'h74,1'b0};
addr[1] = {7'h10,1'b0};
addr[2] = {7'h10,1'b0};
addr[3] = {7'h10,1'b0};
addr[4] = {7'h10,1'b0};
data[0] = 8'h04;
data[1] = 8'h30;
data[2] = OFFSET_ADC_A[11:4];
data[3] = {OFFSET_ADC_A[3:0],4'b0};
data[4] = 8'h31;
data[5] = OFFSET_ADC_B[11:4];
data[6] = {OFFSET_ADC_B[3:0],4'b0};
data[7] = 8'h32;
data[8] = OFFSET_DAC_A[11:4];
data[9] = {OFFSET_DAC_A[3:0],4'b0};
data[10] = 8'h33;
data[11] = OFFSET_DAC_B[11:4];
data[12] = {OFFSET_DAC_B[3:0],4'b0};
dev[0] = 8'd0;
dev[1] = 8'd3;
dev[2] = 8'd6;
dev[3] = 8'd9;
dev[4] = 8'd12;
end
endmodule | module io_init_offsets (
input wire rst,
input wire clk,
input wire start,
output wire iic_rst,
inout wire iic_scl,
inout wire iic_sda); |
localparam IDLE = 8'b00000001;
localparam START = 8'b00000010;
localparam WAIT = 8'b00000100;
localparam INC = 8'b00001000;
localparam LOAD_INC = 8'b00010000;
localparam WAIT_LAST = 8'b00100000;
localparam NEXT = 8'b01000000;
localparam DONE = 8'b10000000;
localparam OFFSET_ADC_A = 12'h850;
localparam OFFSET_ADC_B = 12'h840;
localparam OFFSET_DAC_A = 12'h800;
localparam OFFSET_DAC_B = 12'h800;
reg rst_lcl;
reg start_tx;
wire busy;
wire load;
wire last_address;
wire last_device;
reg [7:0] data_addr;
reg [7:0] addr_addr;
reg [7:0] dev_addr;
reg [7:0] addr [4:0];
reg [7:0] dev [4:0];
reg [7:0] data [12:0];
reg [7:0] addr_buf;
reg [7:0] data_buf;
reg [7:0] dev_buf;
reg [7:0] state;
reg [7:0] next_state;
always @(posedge clk)
rst_lcl <= rst;
i2c_master #(
.input_clk (200_000_000),
.bus_clk (400_000))
i2c_master_inst (
.clk (clk),
.rst (rst_lcl),
.ena (start_tx),
.addr (addr_buf[7:1]),
.rw (addr_buf[0]),
.data_wr (data_buf),
.busy (busy),
.load (load),
.data_rd (),
.sda (iic_sda),
.scl (iic_scl));
assign iic_rst = ~rst_lcl;
always @(posedge clk)
if (rst_lcl) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (start) next_state = START;
START : if (busy)
if (last_address) next_state = WAIT_LAST;
else next_state = WAIT;
WAIT : if (load) next_state = INC;
INC : next_state = LOAD_INC;
LOAD_INC : if (!load)
if (last_address) next_state = WAIT_LAST;
else next_state = WAIT;
WAIT_LAST : if (!busy)
if (last_device) next_state = DONE;
else next_state = NEXT;
NEXT : next_state = START;
DONE : if (~start) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign last_device = (dev_addr == 4) && last_address;
assign last_address = dev_buf == data_addr;
always @(posedge clk)
if (rst_lcl) start_tx <= 0;
else if (state == START) start_tx <= 1;
else if (state == WAIT_LAST) start_tx <= 0;
always @(posedge clk) begin
if (state == IDLE) addr_addr <= 0;
else if (state == NEXT) addr_addr <= addr_addr + 1;
if (state == IDLE) data_addr <= 0;
else if (state == NEXT) data_addr <= data_addr + 1;
else if (state == INC) data_addr <= data_addr + 1;
if (state == IDLE) dev_addr <= 0;
else if (state == NEXT) dev_addr <= dev_addr + 1;
data_buf <= data[data_addr];
addr_buf <= addr[addr_addr];
dev_buf <= dev[dev_addr];
end
initial begin
addr[0] = {7'h74,1'b0};
addr[1] = {7'h10,1'b0};
addr[2] = {7'h10,1'b0};
addr[3] = {7'h10,1'b0};
addr[4] = {7'h10,1'b0};
data[0] = 8'h04;
data[1] = 8'h30;
data[2] = OFFSET_ADC_A[11:4];
data[3] = {OFFSET_ADC_A[3:0],4'b0};
data[4] = 8'h31;
data[5] = OFFSET_ADC_B[11:4];
data[6] = {OFFSET_ADC_B[3:0],4'b0};
data[7] = 8'h32;
data[8] = OFFSET_DAC_A[11:4];
data[9] = {OFFSET_DAC_A[3:0],4'b0};
data[10] = 8'h33;
data[11] = OFFSET_DAC_B[11:4];
data[12] = {OFFSET_DAC_B[3:0],4'b0};
dev[0] = 8'd0;
dev[1] = 8'd3;
dev[2] = 8'd6;
dev[3] = 8'd9;
dev[4] = 8'd12;
end
endmodule | 0 |
138,790 | data/full_repos/permissive/86135381/io_main.v | 86,135,381 | io_main.v | v | 204 | 83 | [] | [] | [] | [(1, 203)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/86135381/io_main.v:68: Signal definition not found, creating implicitly: \'rst_sync_adc\'\n if (rst_sync_adc) dac_a <= 16\'b0;\n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/86135381/io_main.v:187: Signal definition not found, creating implicitly: \'rst_sync_sys\'\n : ... Suggested alternative: \'rst_sync_adc\'\n if (rst_sync_sys == 1) sys_count <= 0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:77: Cannot find file containing module: \'io_clk_sys\'\n io_clk_sys clk_sys (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_clk_sys\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_clk_sys.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_clk_sys.sv\n io_clk_sys\n io_clk_sys.v\n io_clk_sys.sv\n obj_dir/io_clk_sys\n obj_dir/io_clk_sys.v\n obj_dir/io_clk_sys.sv\n%Error: data/full_repos/permissive/86135381/io_main.v:84: Cannot find file containing module: \'io_clk_adc\'\n io_clk_adc clk_adc_inst (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:92: Cannot find file containing module: \'io_reset_synchroniser\'\n io_reset_synchroniser reset_synchroniser_sys (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:98: Cannot find file containing module: \'io_reset_synchroniser\'\n io_reset_synchroniser reset_synchroniser_adc (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:107: Cannot find file containing module: \'io_init\'\n io_init init_modules (\n ^~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:127: Cannot find file containing module: \'io_init_offsets\'\n io_init_offsets init_offsets (\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:140: Cannot find file containing module: \'io_synchroniser\'\n io_synchroniser done_signal ( \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:146: Cannot find file containing module: \'io_synchroniser\'\n io_synchroniser start_signal (\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:155: Cannot find file containing module: \'io_main_adc\'\n io_main_adc adc_driver (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main.v:168: Cannot find file containing module: \'io_main_dac\'\n io_main_dac dac_driver (\n ^~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 302,800 | module | module io_main (
input wire cpu_reset,
input wire sysclk_p,
input wire sysclk_n,
output wire gpio_led_0,
output wire gpio_led_1,
output wire gpio_led_2,
output wire gpio_led_3,
output wire gpio_led_4,
output wire gpio_led_5,
output wire gpio_led_6,
output wire gpio_led_7,
output wire spi_clk,
output wire spi_mosi,
output wire iic_rst,
inout wire iic_scl,
inout wire iic_sda,
input wire cdce_miso,
input wire pll_status,
output wire cdce_n_en,
output wire cdce_n_reset,
output wire cdce_n_pd,
output wire ref_en,
input wire clk_ab_p,
input wire clk_ab_n,
input wire [6:0] cha_p,
input wire [6:0] cha_n,
input wire [6:0] chb_p,
input wire [6:0] chb_n,
output wire adc_n_en,
output wire adc_reset,
output wire dac_clk_p,
output wire dac_clk_n,
output wire dac_frame_p,
output wire dac_frame_n,
output wire dac_tx_en,
output wire dac_n_en,
output wire [7:0] dac_data_p,
output wire [7:0] dac_data_n,
input wire mon_n_int,
output wire mon_n_en,
output wire mon_n_reset);
wire clk_200MHz;
wire clk_adc;
wire clk_adc_ddr;
wire clk_sys_locked;
wire clk_adc_locked;
wire init_done;
wire adc_calibrated_fast;
wire adc_calibrated_slow;
wire start_calibration_slow;
wire start_calibration_fast;
wire [13:0] adc_a;
wire [13:0] adc_b;
reg [15:0] dac_a;
reg [15:0] dac_b;
always @(posedge clk_adc) begin
if (rst_sync_adc) dac_a <= 16'b0;
else dac_a <= {adc_a,2'b0};
if (rst_sync_adc) dac_b <= 16'b0;
else dac_b <= {adc_b,2'b0};
end
io_clk_sys clk_sys (
.clk_in1_p (sysclk_p),
.clk_in1_n (sysclk_n),
.clk_out1 (clk_200MHz),
.reset (cpu_reset),
.locked (clk_sys_locked));
io_clk_adc clk_adc_inst (
.clk_in1_p (clk_ab_p),
.clk_in1_n (clk_ab_n),
.clk_out1 (clk_adc),
.clk_out2 (clk_adc_ddr),
.reset (cpu_reset),
.locked (clk_adc_locked));
io_reset_synchroniser reset_synchroniser_sys (
.clk (clk_200MHz),
.locked (clk_sys_locked),
.cpu_reset (cpu_reset),
.rst_sync (rst_sync_sys));
io_reset_synchroniser reset_synchroniser_adc (
.clk (clk_adc),
.locked (clk_adc_locked),
.cpu_reset (cpu_reset),
.rst_sync (rst_sync_adc));
io_init init_modules (
.rst (rst_sync_sys),
.clk (clk_200MHz),
.init_ena (1'b1),
.spi_sclk (spi_clk),
.spi_sdata (spi_mosi),
.cdce_n_en (cdce_n_en),
.cdce_miso (cdce_miso),
.cdce_n_reset (cdce_n_reset),
.cdce_n_pd (cdce_n_pd),
.ref_en (ref_en),
.ads_n_en (adc_n_en),
.adc_reset (adc_reset),
.dac_n_en (dac_n_en),
.amc_n_en (mon_n_en),
.mon_n_rst (mon_n_reset),
.init_done (init_done),
.start_calibration (start_calibration_slow),
.adc_calibrated (adc_calibrated_slow));
io_init_offsets init_offsets (
.rst (rst_sync_sys),
.clk (clk_200MHz),
.start (init_done),
.iic_rst (iic_rst),
.iic_scl (iic_scl),
.iic_sda (iic_sda));
io_synchroniser done_signal (
.clk_in (clk_adc),
.clk_out (clk_200MHz),
.data_in (adc_calibrated_fast),
.data_out (adc_calibrated_slow));
io_synchroniser start_signal (
.clk_in (clk_200MHz),
.clk_out (clk_adc),
.data_in (start_calibration_slow),
.data_out (start_calibration_fast));
io_main_adc adc_driver (
.rst (rst_sync_adc),
.clk (clk_adc),
.clk_200MHz (clk_200MHz),
.cha_p (cha_p),
.cha_n (cha_n),
.chb_p (chb_p),
.chb_n (chb_n),
.adc_a_buf (adc_a),
.adc_b_buf (adc_b),
.start (start_calibration_fast),
.done (adc_calibrated_fast));
io_main_dac dac_driver (
.rst (rst_sync_adc),
.clk (clk_adc_ddr),
.clk_2 (clk_adc),
.dac_a (dac_a),
.dac_b (dac_b),
.dac_clk_p (dac_clk_p),
.dac_clk_n (dac_clk_n),
.dac_frame_p (dac_frame_p),
.dac_frame_n (dac_frame_n),
.dac_tx_en (dac_tx_en),
.dac_data_p (dac_data_p),
.dac_data_n (dac_data_n));
reg [31:0] adc_count, sys_count;
always @(posedge clk_200MHz)
if (rst_sync_sys == 1) sys_count <= 0;
else sys_count <= sys_count + 1;
always @(posedge clk_adc)
if (rst_sync_adc == 1) adc_count <= 0;
else adc_count <= adc_count + 1;
assign gpio_led_0 = clk_adc_locked;
assign gpio_led_1 = init_done;
assign gpio_led_2 = pll_status;
assign gpio_led_3 = mon_n_int;
assign gpio_led_4 = clk_adc_locked & adc_calibrated_fast;
assign gpio_led_5 = clk_sys_locked & pll_status & mon_n_int & init_done;
assign gpio_led_6 = sys_count[28];
assign gpio_led_7 = adc_count[28];
endmodule | module io_main (
input wire cpu_reset,
input wire sysclk_p,
input wire sysclk_n,
output wire gpio_led_0,
output wire gpio_led_1,
output wire gpio_led_2,
output wire gpio_led_3,
output wire gpio_led_4,
output wire gpio_led_5,
output wire gpio_led_6,
output wire gpio_led_7,
output wire spi_clk,
output wire spi_mosi,
output wire iic_rst,
inout wire iic_scl,
inout wire iic_sda,
input wire cdce_miso,
input wire pll_status,
output wire cdce_n_en,
output wire cdce_n_reset,
output wire cdce_n_pd,
output wire ref_en,
input wire clk_ab_p,
input wire clk_ab_n,
input wire [6:0] cha_p,
input wire [6:0] cha_n,
input wire [6:0] chb_p,
input wire [6:0] chb_n,
output wire adc_n_en,
output wire adc_reset,
output wire dac_clk_p,
output wire dac_clk_n,
output wire dac_frame_p,
output wire dac_frame_n,
output wire dac_tx_en,
output wire dac_n_en,
output wire [7:0] dac_data_p,
output wire [7:0] dac_data_n,
input wire mon_n_int,
output wire mon_n_en,
output wire mon_n_reset); |
wire clk_200MHz;
wire clk_adc;
wire clk_adc_ddr;
wire clk_sys_locked;
wire clk_adc_locked;
wire init_done;
wire adc_calibrated_fast;
wire adc_calibrated_slow;
wire start_calibration_slow;
wire start_calibration_fast;
wire [13:0] adc_a;
wire [13:0] adc_b;
reg [15:0] dac_a;
reg [15:0] dac_b;
always @(posedge clk_adc) begin
if (rst_sync_adc) dac_a <= 16'b0;
else dac_a <= {adc_a,2'b0};
if (rst_sync_adc) dac_b <= 16'b0;
else dac_b <= {adc_b,2'b0};
end
io_clk_sys clk_sys (
.clk_in1_p (sysclk_p),
.clk_in1_n (sysclk_n),
.clk_out1 (clk_200MHz),
.reset (cpu_reset),
.locked (clk_sys_locked));
io_clk_adc clk_adc_inst (
.clk_in1_p (clk_ab_p),
.clk_in1_n (clk_ab_n),
.clk_out1 (clk_adc),
.clk_out2 (clk_adc_ddr),
.reset (cpu_reset),
.locked (clk_adc_locked));
io_reset_synchroniser reset_synchroniser_sys (
.clk (clk_200MHz),
.locked (clk_sys_locked),
.cpu_reset (cpu_reset),
.rst_sync (rst_sync_sys));
io_reset_synchroniser reset_synchroniser_adc (
.clk (clk_adc),
.locked (clk_adc_locked),
.cpu_reset (cpu_reset),
.rst_sync (rst_sync_adc));
io_init init_modules (
.rst (rst_sync_sys),
.clk (clk_200MHz),
.init_ena (1'b1),
.spi_sclk (spi_clk),
.spi_sdata (spi_mosi),
.cdce_n_en (cdce_n_en),
.cdce_miso (cdce_miso),
.cdce_n_reset (cdce_n_reset),
.cdce_n_pd (cdce_n_pd),
.ref_en (ref_en),
.ads_n_en (adc_n_en),
.adc_reset (adc_reset),
.dac_n_en (dac_n_en),
.amc_n_en (mon_n_en),
.mon_n_rst (mon_n_reset),
.init_done (init_done),
.start_calibration (start_calibration_slow),
.adc_calibrated (adc_calibrated_slow));
io_init_offsets init_offsets (
.rst (rst_sync_sys),
.clk (clk_200MHz),
.start (init_done),
.iic_rst (iic_rst),
.iic_scl (iic_scl),
.iic_sda (iic_sda));
io_synchroniser done_signal (
.clk_in (clk_adc),
.clk_out (clk_200MHz),
.data_in (adc_calibrated_fast),
.data_out (adc_calibrated_slow));
io_synchroniser start_signal (
.clk_in (clk_200MHz),
.clk_out (clk_adc),
.data_in (start_calibration_slow),
.data_out (start_calibration_fast));
io_main_adc adc_driver (
.rst (rst_sync_adc),
.clk (clk_adc),
.clk_200MHz (clk_200MHz),
.cha_p (cha_p),
.cha_n (cha_n),
.chb_p (chb_p),
.chb_n (chb_n),
.adc_a_buf (adc_a),
.adc_b_buf (adc_b),
.start (start_calibration_fast),
.done (adc_calibrated_fast));
io_main_dac dac_driver (
.rst (rst_sync_adc),
.clk (clk_adc_ddr),
.clk_2 (clk_adc),
.dac_a (dac_a),
.dac_b (dac_b),
.dac_clk_p (dac_clk_p),
.dac_clk_n (dac_clk_n),
.dac_frame_p (dac_frame_p),
.dac_frame_n (dac_frame_n),
.dac_tx_en (dac_tx_en),
.dac_data_p (dac_data_p),
.dac_data_n (dac_data_n));
reg [31:0] adc_count, sys_count;
always @(posedge clk_200MHz)
if (rst_sync_sys == 1) sys_count <= 0;
else sys_count <= sys_count + 1;
always @(posedge clk_adc)
if (rst_sync_adc == 1) adc_count <= 0;
else adc_count <= adc_count + 1;
assign gpio_led_0 = clk_adc_locked;
assign gpio_led_1 = init_done;
assign gpio_led_2 = pll_status;
assign gpio_led_3 = mon_n_int;
assign gpio_led_4 = clk_adc_locked & adc_calibrated_fast;
assign gpio_led_5 = clk_sys_locked & pll_status & mon_n_int & init_done;
assign gpio_led_6 = sys_count[28];
assign gpio_led_7 = adc_count[28];
endmodule | 0 |
138,791 | data/full_repos/permissive/86135381/io_main_adc.v | 86,135,381 | io_main_adc.v | v | 186 | 81 | [] | [] | [] | null | line:134: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86135381/io_main_adc.v:51: Cannot find file containing module: 'IBUFDS'\n IBUFDS #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/IBUFDS\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/IBUFDS.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/IBUFDS.sv\n IBUFDS\n IBUFDS.v\n IBUFDS.sv\n obj_dir/IBUFDS\n obj_dir/IBUFDS.v\n obj_dir/IBUFDS.sv\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:60: Cannot find file containing module: 'IBUFDS'\n IBUFDS #(\n ^~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:77: Cannot find file containing module: 'IDELAYCTRL'\n IDELAYCTRL delay_controller (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:82: Cannot find file containing module: 'io_calibration'\n io_calibration calibration_cha (rst_lcl, clk, start, adc_a, ce_a, done_a);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:83: Cannot find file containing module: 'io_calibration'\n io_calibration calibration_chb (rst_lcl, clk, start, adc_b, ce_b, done_b);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:88: Cannot find file containing module: 'IDELAYE2'\n IDELAYE2 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:111: Cannot find file containing module: 'IDELAYE2'\n IDELAYE2 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:141: Cannot find file containing module: 'IDDR'\n IDDR #(\n ^~~~\n%Error: data/full_repos/permissive/86135381/io_main_adc.v:156: Cannot find file containing module: 'IDDR'\n IDDR #(\n ^~~~\n%Error: Exiting due to 9 error(s)\n" | 302,801 | module | module io_main_adc (
input wire rst,
input wire clk,
input wire clk_200MHz,
input wire [6:0] cha_p,
input wire [6:0] cha_n,
input wire [6:0] chb_p,
input wire [6:0] chb_n,
output reg [13:0] adc_a_buf,
output reg [13:0] adc_b_buf,
input wire start,
output wire done);
genvar ii;
reg rst_lcl;
wire done_a;
wire done_b;
wire ce_a;
wire ce_b;
wire [6:0] cha;
wire [6:0] chb;
wire [6:0] cha_dly;
wire [6:0] chb_dly;
wire [13:0] adc_a;
wire [13:0] adc_b;
always @(posedge clk)
rst_lcl <= rst;
generate for (ii = 0; ii < 7; ii = ii + 1) begin : adc_buffers
IBUFDS #(
.IOSTANDARD ("LVDS_25"),
.IBUF_LOW_PWR ("FALSE"),
.DIFF_TERM ("TRUE"))
IBUFDS_cha (
.O (cha[ii]),
.I (cha_p[ii]),
.IB (cha_n[ii]));
IBUFDS #(
.IOSTANDARD ("LVDS_25"),
.IBUF_LOW_PWR ("FALSE"),
.DIFF_TERM ("TRUE"))
IBUFDS_chb (
.O (chb[ii]),
.I (chb_p[ii]),
.IB (chb_n[ii]));
end endgenerate
IDELAYCTRL delay_controller (
.RST (rst_lcl),
.REFCLK (clk_200MHz),
.RDY ());
io_calibration calibration_cha (rst_lcl, clk, start, adc_a, ce_a, done_a);
io_calibration calibration_chb (rst_lcl, clk, start, adc_b, ce_b, done_b);
assign done = done_a && done_b;
generate for (ii = 0; ii < 7; ii = ii + 1) begin : adc_delays
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VARIABLE"),
.IDELAY_VALUE (0),
.PIPE_SEL ("FALSE"),
.REFCLK_FREQUENCY (200),
.SIGNAL_PATTERN ("DATA"))
delay_cha (
.CNTVALUEOUT (),
.DATAOUT (cha_dly[ii]),
.C (clk),
.CE (ce_a),
.CINVCTRL (0),
.CNTVALUEIN (0),
.DATAIN (0),
.IDATAIN (cha[ii]),
.INC (1),
.LD (rst_lcl),
.LDPIPEEN (0),
.REGRST (0));
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VARIABLE"),
.IDELAY_VALUE (0),
.PIPE_SEL ("FALSE"),
.REFCLK_FREQUENCY (200),
.SIGNAL_PATTERN ("DATA"))
delay_chb (
.CNTVALUEOUT (),
.DATAOUT (chb_dly[ii]),
.C (clk),
.CE (ce_b),
.CINVCTRL (0),
.CNTVALUEIN (0),
.DATAIN (0),
.IDATAIN (chb[ii]),
.INC (1),
.LD (rst_lcl),
.LDPIPEEN (0),
.REGRST (0));
end endgenerate;
generate for (ii = 0; ii < 7; ii = ii + 1) begin : adc_ddrs
IDDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
IDDR_a (
.Q1 (adc_a[2*ii]),
.Q2 (adc_a[2*ii+1]),
.C (clk),
.CE (1),
.D (cha_dly[ii]),
.R (0),
.S (0));
IDDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
IDDR_b (
.Q1 (adc_b[2*ii]),
.Q2 (adc_b[2*ii+1]),
.C (clk),
.CE (1),
.D (chb_dly[ii]),
.R (0),
.S (0));
end endgenerate;
always @(posedge clk)
if (rst_lcl) begin
adc_a_buf <= 0;
adc_b_buf <= 0;
end else begin
adc_a_buf <= adc_a;
adc_b_buf <= adc_b;
end
endmodule | module io_main_adc (
input wire rst,
input wire clk,
input wire clk_200MHz,
input wire [6:0] cha_p,
input wire [6:0] cha_n,
input wire [6:0] chb_p,
input wire [6:0] chb_n,
output reg [13:0] adc_a_buf,
output reg [13:0] adc_b_buf,
input wire start,
output wire done); |
genvar ii;
reg rst_lcl;
wire done_a;
wire done_b;
wire ce_a;
wire ce_b;
wire [6:0] cha;
wire [6:0] chb;
wire [6:0] cha_dly;
wire [6:0] chb_dly;
wire [13:0] adc_a;
wire [13:0] adc_b;
always @(posedge clk)
rst_lcl <= rst;
generate for (ii = 0; ii < 7; ii = ii + 1) begin : adc_buffers
IBUFDS #(
.IOSTANDARD ("LVDS_25"),
.IBUF_LOW_PWR ("FALSE"),
.DIFF_TERM ("TRUE"))
IBUFDS_cha (
.O (cha[ii]),
.I (cha_p[ii]),
.IB (cha_n[ii]));
IBUFDS #(
.IOSTANDARD ("LVDS_25"),
.IBUF_LOW_PWR ("FALSE"),
.DIFF_TERM ("TRUE"))
IBUFDS_chb (
.O (chb[ii]),
.I (chb_p[ii]),
.IB (chb_n[ii]));
end endgenerate
IDELAYCTRL delay_controller (
.RST (rst_lcl),
.REFCLK (clk_200MHz),
.RDY ());
io_calibration calibration_cha (rst_lcl, clk, start, adc_a, ce_a, done_a);
io_calibration calibration_chb (rst_lcl, clk, start, adc_b, ce_b, done_b);
assign done = done_a && done_b;
generate for (ii = 0; ii < 7; ii = ii + 1) begin : adc_delays
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VARIABLE"),
.IDELAY_VALUE (0),
.PIPE_SEL ("FALSE"),
.REFCLK_FREQUENCY (200),
.SIGNAL_PATTERN ("DATA"))
delay_cha (
.CNTVALUEOUT (),
.DATAOUT (cha_dly[ii]),
.C (clk),
.CE (ce_a),
.CINVCTRL (0),
.CNTVALUEIN (0),
.DATAIN (0),
.IDATAIN (cha[ii]),
.INC (1),
.LD (rst_lcl),
.LDPIPEEN (0),
.REGRST (0));
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VARIABLE"),
.IDELAY_VALUE (0),
.PIPE_SEL ("FALSE"),
.REFCLK_FREQUENCY (200),
.SIGNAL_PATTERN ("DATA"))
delay_chb (
.CNTVALUEOUT (),
.DATAOUT (chb_dly[ii]),
.C (clk),
.CE (ce_b),
.CINVCTRL (0),
.CNTVALUEIN (0),
.DATAIN (0),
.IDATAIN (chb[ii]),
.INC (1),
.LD (rst_lcl),
.LDPIPEEN (0),
.REGRST (0));
end endgenerate;
generate for (ii = 0; ii < 7; ii = ii + 1) begin : adc_ddrs
IDDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
IDDR_a (
.Q1 (adc_a[2*ii]),
.Q2 (adc_a[2*ii+1]),
.C (clk),
.CE (1),
.D (cha_dly[ii]),
.R (0),
.S (0));
IDDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
IDDR_b (
.Q1 (adc_b[2*ii]),
.Q2 (adc_b[2*ii+1]),
.C (clk),
.CE (1),
.D (chb_dly[ii]),
.R (0),
.S (0));
end endgenerate;
always @(posedge clk)
if (rst_lcl) begin
adc_a_buf <= 0;
adc_b_buf <= 0;
end else begin
adc_a_buf <= adc_a;
adc_b_buf <= adc_b;
end
endmodule | 0 |
138,792 | data/full_repos/permissive/86135381/io_main_dac.v | 86,135,381 | io_main_dac.v | v | 203 | 82 | [] | [] | [] | [(19, 202)] | null | null | 1: b"%Error: data/full_repos/permissive/86135381/io_main_dac.v:82: Cannot find file containing module: 'OBUFDS'\n OBUFDS #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/OBUFDS\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/OBUFDS.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/OBUFDS.sv\n OBUFDS\n OBUFDS.v\n OBUFDS.sv\n obj_dir/OBUFDS\n obj_dir/OBUFDS.v\n obj_dir/OBUFDS.sv\n%Error: data/full_repos/permissive/86135381/io_main_dac.v:95: Cannot find file containing module: 'OSERDESE2'\n OSERDESE2 #(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_dac.v:136: Cannot find file containing module: 'OBUFDS'\n OBUFDS #(\n ^~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_dac.v:151: Cannot find file containing module: 'OSERDESE2'\n OSERDESE2 #(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_main_dac.v:192: Cannot find file containing module: 'OBUFDS'\n OBUFDS #(\n ^~~~~~\n%Error: Exiting due to 5 error(s)\n" | 302,802 | module | module io_main_dac (
input wire rst,
input wire clk,
input wire clk_2,
input wire [15:0] dac_a,
input wire [15:0] dac_b,
output wire dac_clk_p,
output wire dac_clk_n,
output wire dac_frame_p,
output wire dac_frame_n,
output reg dac_tx_en,
output wire [7:0] dac_data_p,
output wire [7:0] dac_data_n);
genvar ii;
reg rst_lcl;
wire dac_clk;
reg dac_rst;
reg dac_frame;
wire [7:0] dac_data;
reg [10:0] cnt;
reg [15:0] dac_a_buf;
reg [15:0] dac_b_buf;
wire [15:0] dac_temp;
wire [15:0] dac_a_neg;
always @(posedge clk_2) begin
rst_lcl <= rst;
dac_a_buf <= dac_a;
dac_b_buf <= dac_b;
end
assign dac_temp = ~dac_a_buf + 16'h0001;
assign dac_a_neg = (dac_temp == 16'h8000) ? 16'h7FFF : dac_temp;
always @(posedge clk_2) begin
if (rst_lcl) cnt <= 0;
else if (cnt < 2047) cnt <= cnt + 1;
if (rst_lcl) dac_rst <= 1;
else if (cnt[10:1] == 255) dac_rst <= 1;
else dac_rst <= 0;
if (cnt[10:1] == 511) dac_frame <= 1;
else dac_frame <= 0;
if (cnt[10:1] == 1023) dac_tx_en <= 1;
else dac_tx_en <= 0;
end
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW"))
OBUFDS_dac_frame (
.O (dac_frame_p),
.OB (dac_frame_n),
.I (dac_frame));
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("DDR"),
.DATA_WIDTH(4),
.INIT_OQ(1'b0),
.INIT_TQ(1'b0),
.SERDES_MODE("MASTER"),
.SRVAL_OQ(0),
.SRVAL_TQ(0),
.TBYTE_CTL("FALSE"),
.TBYTE_SRC("FALSE"),
.TRISTATE_WIDTH(4))
OSERDESE2_dac_clock (
.OFB(),
.OQ(dac_clk),
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(),
.TFB(),
.TQ(),
.CLK(clk),
.CLKDIV(clk_2),
.D1(1),
.D2(0),
.D3(1),
.D4(0),
.D5(0),
.D6(0),
.D7(0),
.D8(0),
.OCE(1),
.RST(dac_rst),
.SHIFTIN1(0),
.SHIFTIN2(0),
.T1(0),
.T2(0),
.T3(0),
.T4(0),
.TBYTEIN(0),
.TCE(0));
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW"))
OBUFDS_dac_dclk (
.O (dac_clk_p),
.OB (dac_clk_n),
.I (dac_clk));
generate for (ii = 0; ii < 8; ii = ii + 1) begin
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("DDR"),
.DATA_WIDTH(4),
.INIT_OQ(1'b0),
.INIT_TQ(1'b0),
.SERDES_MODE("MASTER"),
.SRVAL_OQ(0),
.SRVAL_TQ(0),
.TBYTE_CTL("FALSE"),
.TBYTE_SRC("FALSE"),
.TRISTATE_WIDTH(4))
OSERDESE2_dac_data (
.OFB(),
.OQ(dac_data[ii]),
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(),
.TFB(),
.TQ(),
.CLK(clk),
.CLKDIV(clk_2),
.D1(dac_a_neg[ii + 8]),
.D2(dac_a_neg[ii]),
.D3(dac_b_buf[ii + 8]),
.D4(dac_b_buf[ii]),
.D5(0),
.D6(0),
.D7(0),
.D8(0),
.OCE(1),
.RST(dac_rst),
.SHIFTIN1(0),
.SHIFTIN2(0),
.T1(0),
.T2(0),
.T3(0),
.T4(0),
.TBYTEIN(0),
.TCE(0));
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW"))
OBUFDS_dac_data (
.O (dac_data_p[ii]),
.OB (dac_data_n[ii]),
.I (dac_data[ii]));
end endgenerate
endmodule | module io_main_dac (
input wire rst,
input wire clk,
input wire clk_2,
input wire [15:0] dac_a,
input wire [15:0] dac_b,
output wire dac_clk_p,
output wire dac_clk_n,
output wire dac_frame_p,
output wire dac_frame_n,
output reg dac_tx_en,
output wire [7:0] dac_data_p,
output wire [7:0] dac_data_n); |
genvar ii;
reg rst_lcl;
wire dac_clk;
reg dac_rst;
reg dac_frame;
wire [7:0] dac_data;
reg [10:0] cnt;
reg [15:0] dac_a_buf;
reg [15:0] dac_b_buf;
wire [15:0] dac_temp;
wire [15:0] dac_a_neg;
always @(posedge clk_2) begin
rst_lcl <= rst;
dac_a_buf <= dac_a;
dac_b_buf <= dac_b;
end
assign dac_temp = ~dac_a_buf + 16'h0001;
assign dac_a_neg = (dac_temp == 16'h8000) ? 16'h7FFF : dac_temp;
always @(posedge clk_2) begin
if (rst_lcl) cnt <= 0;
else if (cnt < 2047) cnt <= cnt + 1;
if (rst_lcl) dac_rst <= 1;
else if (cnt[10:1] == 255) dac_rst <= 1;
else dac_rst <= 0;
if (cnt[10:1] == 511) dac_frame <= 1;
else dac_frame <= 0;
if (cnt[10:1] == 1023) dac_tx_en <= 1;
else dac_tx_en <= 0;
end
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW"))
OBUFDS_dac_frame (
.O (dac_frame_p),
.OB (dac_frame_n),
.I (dac_frame));
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("DDR"),
.DATA_WIDTH(4),
.INIT_OQ(1'b0),
.INIT_TQ(1'b0),
.SERDES_MODE("MASTER"),
.SRVAL_OQ(0),
.SRVAL_TQ(0),
.TBYTE_CTL("FALSE"),
.TBYTE_SRC("FALSE"),
.TRISTATE_WIDTH(4))
OSERDESE2_dac_clock (
.OFB(),
.OQ(dac_clk),
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(),
.TFB(),
.TQ(),
.CLK(clk),
.CLKDIV(clk_2),
.D1(1),
.D2(0),
.D3(1),
.D4(0),
.D5(0),
.D6(0),
.D7(0),
.D8(0),
.OCE(1),
.RST(dac_rst),
.SHIFTIN1(0),
.SHIFTIN2(0),
.T1(0),
.T2(0),
.T3(0),
.T4(0),
.TBYTEIN(0),
.TCE(0));
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW"))
OBUFDS_dac_dclk (
.O (dac_clk_p),
.OB (dac_clk_n),
.I (dac_clk));
generate for (ii = 0; ii < 8; ii = ii + 1) begin
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("DDR"),
.DATA_WIDTH(4),
.INIT_OQ(1'b0),
.INIT_TQ(1'b0),
.SERDES_MODE("MASTER"),
.SRVAL_OQ(0),
.SRVAL_TQ(0),
.TBYTE_CTL("FALSE"),
.TBYTE_SRC("FALSE"),
.TRISTATE_WIDTH(4))
OSERDESE2_dac_data (
.OFB(),
.OQ(dac_data[ii]),
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(),
.TFB(),
.TQ(),
.CLK(clk),
.CLKDIV(clk_2),
.D1(dac_a_neg[ii + 8]),
.D2(dac_a_neg[ii]),
.D3(dac_b_buf[ii + 8]),
.D4(dac_b_buf[ii]),
.D5(0),
.D6(0),
.D7(0),
.D8(0),
.OCE(1),
.RST(dac_rst),
.SHIFTIN1(0),
.SHIFTIN2(0),
.T1(0),
.T2(0),
.T3(0),
.T4(0),
.TBYTEIN(0),
.TCE(0));
OBUFDS #(
.IOSTANDARD("LVDS_25"),
.SLEW("SLOW"))
OBUFDS_dac_data (
.O (dac_data_p[ii]),
.OB (dac_data_n[ii]),
.I (dac_data[ii]));
end endgenerate
endmodule | 0 |
138,793 | data/full_repos/permissive/86135381/io_reset_synchroniser.v | 86,135,381 | io_reset_synchroniser.v | v | 22 | 83 | [] | [] | [] | [(5, 21)] | null | data/verilator_xmls/4bbcd092-b9a9-4903-981b-8eb517eb6734.xml | null | 302,803 | module | module io_reset_synchroniser (
input wire clk,
input wire locked,
input wire cpu_reset,
output wire rst_sync);
wire rst_async;
reg [1:0] rst_shift_reg = 2'b11;
always @(posedge clk or posedge rst_async)
if (rst_async) rst_shift_reg <= 2'b11;
else rst_shift_reg <= {rst_shift_reg[0], 1'b0};
assign rst_async = cpu_reset | !locked;
assign rst_sync = rst_shift_reg[1];
endmodule | module io_reset_synchroniser (
input wire clk,
input wire locked,
input wire cpu_reset,
output wire rst_sync); |
wire rst_async;
reg [1:0] rst_shift_reg = 2'b11;
always @(posedge clk or posedge rst_async)
if (rst_async) rst_shift_reg <= 2'b11;
else rst_shift_reg <= {rst_shift_reg[0], 1'b0};
assign rst_async = cpu_reset | !locked;
assign rst_sync = rst_shift_reg[1];
endmodule | 0 |
138,794 | data/full_repos/permissive/86135381/io_spi.v | 86,135,381 | io_spi.v | v | 109 | 82 | [] | [] | [] | [(1, 108)] | null | data/verilator_xmls/bf10272f-c7b0-49bd-b86e-d0fe9496f3e6.xml | null | 302,804 | module | module io_spi #(
parameter WIDTH = 32,
parameter FLIP = 0,
parameter SCLK_TIME = 4
)(
input wire rst,
input wire clk,
input wire start_tx,
output reg done_tx,
output reg spi_clk,
output wire spi_mosi,
output reg spi_cs,
input wire spi_miso,
input wire [WIDTH-1:0] tx_data,
output reg [WIDTH-1:0] rx_data);
localparam IDLE = 6'b000001;
localparam QUIET = 6'b000010;
localparam HIGH = 6'b000100;
localparam READ = 6'b001000;
localparam LOW = 6'b010000;
localparam BUFFER = 6'b100000;
reg rst_lcl;
wire last_read, at_zero, shift, quiet, low, buffer, idle;
reg [5:0] state, next_state;
reg [7:0] shift_counter, state_counter;
reg [WIDTH-1:0] shift_reg;
always @(posedge clk)
rst_lcl <= rst;
always @(posedge clk)
if (!quiet) spi_cs <= 0;
else spi_cs <= 1;
always @(posedge clk)
if (low) spi_clk <= 0;
else spi_clk <= 1;
assign last_read = shift_counter == 0;
assign spi_mosi = FLIP ? shift_reg[0] : shift_reg[WIDTH-1];
always @(posedge clk) begin
if (start_tx) shift_counter <= WIDTH - 1;
else if (shift) shift_counter <= shift_counter - 1;
if (start_tx) shift_reg <= tx_data;
else if (shift)
if (FLIP) shift_reg <= {spi_miso,shift_reg[WIDTH-1:1]};
else shift_reg <= {shift_reg[WIDTH-2:0],spi_miso};
end
always @(posedge clk) begin
done_tx <= buffer;
if (buffer) rx_data <= shift_reg;
end
assign at_zero = state_counter == 0;
always @(posedge clk)
if (at_zero | idle) state_counter <= SCLK_TIME;
else state_counter <= state_counter - 1;
always @(posedge clk)
if (rst) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE: if (start_tx) next_state = QUIET;
QUIET: if (at_zero) next_state = LOW;
LOW: if (at_zero) next_state = HIGH;
HIGH: if (at_zero & last_read) next_state = BUFFER;
else if (at_zero) next_state = READ;
READ: next_state = LOW;
BUFFER: next_state = IDLE;
endcase
end
assign shift = (state == READ);
assign quiet = (state == QUIET) || (state == IDLE) || (state == BUFFER);
assign low = (state != HIGH);
assign buffer = (state == BUFFER);
assign idle = (state == IDLE);
endmodule | module io_spi #(
parameter WIDTH = 32,
parameter FLIP = 0,
parameter SCLK_TIME = 4
)(
input wire rst,
input wire clk,
input wire start_tx,
output reg done_tx,
output reg spi_clk,
output wire spi_mosi,
output reg spi_cs,
input wire spi_miso,
input wire [WIDTH-1:0] tx_data,
output reg [WIDTH-1:0] rx_data); |
localparam IDLE = 6'b000001;
localparam QUIET = 6'b000010;
localparam HIGH = 6'b000100;
localparam READ = 6'b001000;
localparam LOW = 6'b010000;
localparam BUFFER = 6'b100000;
reg rst_lcl;
wire last_read, at_zero, shift, quiet, low, buffer, idle;
reg [5:0] state, next_state;
reg [7:0] shift_counter, state_counter;
reg [WIDTH-1:0] shift_reg;
always @(posedge clk)
rst_lcl <= rst;
always @(posedge clk)
if (!quiet) spi_cs <= 0;
else spi_cs <= 1;
always @(posedge clk)
if (low) spi_clk <= 0;
else spi_clk <= 1;
assign last_read = shift_counter == 0;
assign spi_mosi = FLIP ? shift_reg[0] : shift_reg[WIDTH-1];
always @(posedge clk) begin
if (start_tx) shift_counter <= WIDTH - 1;
else if (shift) shift_counter <= shift_counter - 1;
if (start_tx) shift_reg <= tx_data;
else if (shift)
if (FLIP) shift_reg <= {spi_miso,shift_reg[WIDTH-1:1]};
else shift_reg <= {shift_reg[WIDTH-2:0],spi_miso};
end
always @(posedge clk) begin
done_tx <= buffer;
if (buffer) rx_data <= shift_reg;
end
assign at_zero = state_counter == 0;
always @(posedge clk)
if (at_zero | idle) state_counter <= SCLK_TIME;
else state_counter <= state_counter - 1;
always @(posedge clk)
if (rst) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE: if (start_tx) next_state = QUIET;
QUIET: if (at_zero) next_state = LOW;
LOW: if (at_zero) next_state = HIGH;
HIGH: if (at_zero & last_read) next_state = BUFFER;
else if (at_zero) next_state = READ;
READ: next_state = LOW;
BUFFER: next_state = IDLE;
endcase
end
assign shift = (state == READ);
assign quiet = (state == QUIET) || (state == IDLE) || (state == BUFFER);
assign low = (state != HIGH);
assign buffer = (state == BUFFER);
assign idle = (state == IDLE);
endmodule | 0 |
138,795 | data/full_repos/permissive/86135381/io_synchroniser.v | 86,135,381 | io_synchroniser.v | v | 21 | 45 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/91e4b7c7-efd6-4a95-a149-2e8b20e81354.xml | null | 302,805 | module | module io_synchroniser (
input wire clk_in,
input wire clk_out,
input wire data_in,
output wire data_out);
(* keep = "true" *) reg data_cross;
(* async_reg = "true" *) reg [1:0] meta;
always @(posedge clk_in)
data_cross <= data_in;
always @(posedge clk_out) begin
meta[0] <= data_cross;
meta[1] <= meta[0];
end
assign data_out = meta[1];
endmodule | module io_synchroniser (
input wire clk_in,
input wire clk_out,
input wire data_in,
output wire data_out); |
(* keep = "true" *) reg data_cross;
(* async_reg = "true" *) reg [1:0] meta;
always @(posedge clk_in)
data_cross <= data_in;
always @(posedge clk_out) begin
meta[0] <= data_cross;
meta[1] <= meta[0];
end
assign data_out = meta[1];
endmodule | 0 |
138,799 | data/full_repos/permissive/86169941/Protocol 1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion Bootloader_v2_source/Led_control.v | 86,169,941 | Led_control.v | v | 75 | 78 | [] | ['general public license', 'free software foundation'] | [] | [(35, 74)] | null | null | 1: b'%Error: Cannot find file containing module: 1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion\n data/full_repos/permissive/86169941/Protocol/1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion.v\n data/full_repos/permissive/86169941/Protocol/1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion.sv\n 1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion\n 1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion.v\n 1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion.sv\n obj_dir/1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion\n obj_dir/1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion.v\n obj_dir/1/ANAN-7000DLE_ANAN-8000DLE-Andromeda/Orion_MkII/Orion.sv\n%Error: Cannot find file containing module: Bootloader_v2_source,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: Bootloader_v2_source/Led_control.v\n%Error: Exiting due to 4 error(s)\n' | 302,812 | module | module Led_control (clock, on, slow_flash, fast_flash, LED);
input clock;
input on;
input slow_flash;
input fast_flash;
output reg LED;
parameter clock_speed = 1;
localparam slow_period = clock_speed/2;
localparam fast_period = clock_speed/10;
reg [23:0]counter;
always @ (posedge clock)
begin
if (on)
LED <= 0;
else if (slow_flash) begin
if (counter == slow_period) begin
LED <= ~LED;
counter <= 0;
end
else counter <= counter + 1'b1;
end
else if (fast_flash) begin
if (counter == fast_period) begin
LED <= ~LED;
counter <= 0;
end
else counter <= counter + 1'b1;
end
else LED <= 1'b1;
end
endmodule | module Led_control (clock, on, slow_flash, fast_flash, LED); |
input clock;
input on;
input slow_flash;
input fast_flash;
output reg LED;
parameter clock_speed = 1;
localparam slow_period = clock_speed/2;
localparam fast_period = clock_speed/10;
reg [23:0]counter;
always @ (posedge clock)
begin
if (on)
LED <= 0;
else if (slow_flash) begin
if (counter == slow_period) begin
LED <= ~LED;
counter <= 0;
end
else counter <= counter + 1'b1;
end
else if (fast_flash) begin
if (counter == fast_period) begin
LED <= ~LED;
counter <= 0;
end
else counter <= counter + 1'b1;
end
else LED <= 1'b1;
end
endmodule | 17 |
138,803 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/Alex_relays.v | 86,169,941 | Alex_relays.v | v | 49 | 105 | [] | [] | [] | [(24, 48)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/Alex_relays.v\n%Error: Exiting due to 4 error(s)\n' | 302,839 | module | module Alex_relays(TX_relay, RX_relay, Rout, ANT1, ANT2, ANT3, Rx_1_out, Rx_1_in, Rx_2_in, Transverter);
input [1:0]TX_relay;
input [1:0]RX_relay;
input Rout;
output ANT1;
output ANT2;
output ANT3;
output Rx_1_out;
output Rx_1_in;
output Rx_2_in;
output Transverter;
assign Rx_1_out = Rout;
assign ANT1 = (TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign ANT2 = (TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign ANT3 = (TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Rx_1_in = (RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign Rx_2_in = (RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Transverter = (RX_relay == 2'b11) ? 1'b1 : 1'b0;
endmodule | module Alex_relays(TX_relay, RX_relay, Rout, ANT1, ANT2, ANT3, Rx_1_out, Rx_1_in, Rx_2_in, Transverter); |
input [1:0]TX_relay;
input [1:0]RX_relay;
input Rout;
output ANT1;
output ANT2;
output ANT3;
output Rx_1_out;
output Rx_1_in;
output Rx_2_in;
output Transverter;
assign Rx_1_out = Rout;
assign ANT1 = (TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign ANT2 = (TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign ANT3 = (TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Rx_1_in = (RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign Rx_2_in = (RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Transverter = (RX_relay == 2'b11) ? 1'b1 : 1'b0;
endmodule | 17 |
138,804 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/cic.v | 86,169,941 | cic.v | v | 124 | 81 | [] | [] | [] | [(25, 122)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/cic.v\n%Error: Exiting due to 4 error(s)\n' | 302,841 | module | module cic( clock, in_strobe, out_strobe, in_data, out_data );
parameter STAGES = 3;
parameter DECIMATION = 16;
parameter IN_WIDTH = 18;
parameter ACC_WIDTH = IN_WIDTH + 12;
parameter OUT_WIDTH = IN_WIDTH + 2;
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output signed [OUT_WIDTH-1:0] out_data;
reg [15:0] sample_no;
initial sample_no = 15'd0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == (DECIMATION-1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
assign out_data = comb_data[STAGES][ACC_WIDTH-1:ACC_WIDTH-OUT_WIDTH] +
{{(OUT_WIDTH-1){1'b0}}, comb_data[STAGES][ACC_WIDTH-OUT_WIDTH-1]};
endmodule | module cic( clock, in_strobe, out_strobe, in_data, out_data ); |
parameter STAGES = 3;
parameter DECIMATION = 16;
parameter IN_WIDTH = 18;
parameter ACC_WIDTH = IN_WIDTH + 12;
parameter OUT_WIDTH = IN_WIDTH + 2;
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output signed [OUT_WIDTH-1:0] out_data;
reg [15:0] sample_no;
initial sample_no = 15'd0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == (DECIMATION-1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
assign out_data = comb_data[STAGES][ACC_WIDTH-1:ACC_WIDTH-OUT_WIDTH] +
{{(OUT_WIDTH-1){1'b0}}, comb_data[STAGES][ACC_WIDTH-OUT_WIDTH-1]};
endmodule | 17 |
138,805 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/clocks.v | 86,169,941 | clocks.v | v | 41 | 74 | [] | [] | [] | [(4, 40)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/clocks.v\n%Error: Exiting due to 4 error(s)\n' | 302,844 | module | module clocks(
input clock,
input CBCLK,
output reg MCLK_12MHZ,
output reg SPI_clk
);
reg [2:0] MCLK_count;
always @ (posedge clock)
begin
if (MCLK_count == 4)
begin
MCLK_12MHZ <= ~MCLK_12MHZ;
MCLK_count <= 0;
end
else
MCLK_count <= MCLK_count + 1'b1;
end
reg SPI_count;
always @(posedge CBCLK)
begin
if(SPI_count == 1)
begin
SPI_clk <= ~SPI_clk;
SPI_count <=0;
end
else
SPI_count <= SPI_count + 1'b1;
end
endmodule | module clocks(
input clock,
input CBCLK,
output reg MCLK_12MHZ,
output reg SPI_clk
); |
reg [2:0] MCLK_count;
always @ (posedge clock)
begin
if (MCLK_count == 4)
begin
MCLK_12MHZ <= ~MCLK_12MHZ;
MCLK_count <= 0;
end
else
MCLK_count <= MCLK_count + 1'b1;
end
reg SPI_count;
always @(posedge CBCLK)
begin
if(SPI_count == 1)
begin
SPI_clk <= ~SPI_clk;
SPI_count <=0;
end
else
SPI_count <= SPI_count + 1'b1;
end
endmodule | 17 |
138,809 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/fir_mac.v | 86,169,941 | fir_mac.v | v | 52 | 81 | [] | [] | [] | [(28, 51)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/fir_mac.v\n%Error: Exiting due to 4 error(s)\n' | 302,852 | module | module fir_mac(
input clock,
input clear,
input signed [23:0] in_data_1,
input signed [23:0] in_data_2,
output reg signed [55:0] out_data
);
wire signed [47:0] product;
always @(posedge clock)
if (clear) out_data <= 0;
else out_data <= out_data + product;
mult_24Sx24S mult_24Sx24S_inst(
.aclr (clear),
.clock (clock),
.dataa (in_data_1),
.datab (in_data_2),
.result (product)
);
endmodule | module fir_mac(
input clock,
input clear,
input signed [23:0] in_data_1,
input signed [23:0] in_data_2,
output reg signed [55:0] out_data
); |
wire signed [47:0] product;
always @(posedge clock)
if (clear) out_data <= 0;
else out_data <= out_data + product;
mult_24Sx24S mult_24Sx24S_inst(
.aclr (clear),
.clock (clock),
.dataa (in_data_1),
.datab (in_data_2),
.result (product)
);
endmodule | 17 |
138,811 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/HPF_select.v | 86,169,941 | HPF_select.v | v | 57 | 78 | [] | ['general public license', 'free software foundation'] | [] | [(43, 57)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/HPF_select.v\n%Error: Exiting due to 4 error(s)\n' | 302,855 | module | module HPF_select(frequency,HPF);
input wire [31:0]frequency;
output reg [5:0]HPF;
always @ (frequency)
begin
if (frequency < 1700000) HPF <= 6'b100000;
else if (frequency < 6500000) HPF <= 6'b010000;
else if (frequency < 9500000) HPF <= 6'b001000;
else if (frequency < 13000000) HPF <= 6'b000100;
else if (frequency < 20000000) HPF <= 6'b000001;
else HPF <= 6'b000010;
end
endmodule | module HPF_select(frequency,HPF); |
input wire [31:0]frequency;
output reg [5:0]HPF;
always @ (frequency)
begin
if (frequency < 1700000) HPF <= 6'b100000;
else if (frequency < 6500000) HPF <= 6'b010000;
else if (frequency < 9500000) HPF <= 6'b001000;
else if (frequency < 13000000) HPF <= 6'b000100;
else if (frequency < 20000000) HPF <= 6'b000001;
else HPF <= 6'b000010;
end
endmodule | 17 |
138,813 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/mac.v | 86,169,941 | mac.v | v | 57 | 71 | [] | [] | [] | [(26, 56)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/mac.v\n%Error: Exiting due to 4 error(s)\n' | 302,858 | module | module MAC(clk, reset, rden, wren, data_in_M1, data_in_M2, accum_out);
parameter WIDTH = 24;
input clk;
input reset;
input rden;
input wren;
input signed [WIDTH-1:0] data_in_M1;
input signed [WIDTH-1:0] data_in_M2;
output reg signed [(WIDTH * 2)-1:0] accum_out;
reg signed [((WIDTH * 2)-1):0] mult_temp;
reg signed [(WIDTH * 2):0] accum_temp;
always @(posedge clk)
begin
if (reset) begin
accum_temp <= 0;
mult_temp <= 0;
accum_out <= accum_out;
end else begin
if (wren) begin
mult_temp <= data_in_M1 * data_in_M2;
accum_temp <= accum_temp + mult_temp;
end else if (rden) begin
accum_out <= accum_temp[((WIDTH * 2)):1];
end
end
end
endmodule | module MAC(clk, reset, rden, wren, data_in_M1, data_in_M2, accum_out); |
parameter WIDTH = 24;
input clk;
input reset;
input rden;
input wren;
input signed [WIDTH-1:0] data_in_M1;
input signed [WIDTH-1:0] data_in_M2;
output reg signed [(WIDTH * 2)-1:0] accum_out;
reg signed [((WIDTH * 2)-1):0] mult_temp;
reg signed [(WIDTH * 2):0] accum_temp;
always @(posedge clk)
begin
if (reset) begin
accum_temp <= 0;
mult_temp <= 0;
accum_out <= accum_out;
end else begin
if (wren) begin
mult_temp <= data_in_M1 * data_in_M2;
accum_temp <= accum_temp + mult_temp;
end else if (rden) begin
accum_out <= accum_temp[((WIDTH * 2)):1];
end
end
end
endmodule | 17 |
138,815 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/Mercury_V2.0.v | 86,169,941 | Mercury_V2.0.v | v | 650 | 120 | [] | ['general public license', 'free software foundation'] | [] | [(79, 646)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/Mercury_V2.0.v\n%Error: Exiting due to 4 error(s)\n' | 302,860 | module | module Mercury(
input OSC_10MHZ,
inout ext_10MHZ,
input CLKA,
input [15:0]INA,
input CC,
output reg ATTRLY,
output A6,
input C4,
input C8,
input C9,
input C17,
output MDOUT,
input BCLK,
input LRCLK,
output CDIN,
output CBCLK,
output CLRCLK,
output CLRCOUT,
output CMCLK,
output CMODE,
output reg MOSI,
output reg SCLK,
output reg nCS,
output SPI_data,
output SPI_clock,
output Tx_load_strobe,
output Rx_load_strobe,
output FPGA_PLL,
output LVDS_TXE,
output LVDS_RXE_N,
input OVERFLOW,
output reg DITHER,
output SHDN,
output reg PGA,
output reg RAND,
output INIT_DONE,
output TEST0,
output TEST1,
output TEST2,
output TEST3,
output DEBUG_LED0,
output DEBUG_LED1,
output DEBUG_LED2,
output DEBUG_LED3,
output DEBUG_LED4,
output DEBUG_LED5,
output DEBUG_LED6,
output DEBUG_LED7,
input DFS0, DFS1
);
reg data_ready;
assign CDIN = C4;
assign CLRCLK = C9;
assign CLRCOUT = C9;
assign CBCLK = C8;
assign CMCLK = C17;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
always @ (posedge clock)
begin
if (RAND) begin
if (INA[0]) temp_ADC <= {~INA[15:1],INA[0]};
else temp_ADC <= INA;
end
else temp_ADC <= INA;
end
reg index;
reg [15:0]tdata;
reg [2:0]load;
reg [3:0]TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @ (posedge index)
begin
load <= load + 3'b1;
case (load)
3'd0: tdata <= 16'h1E00;
3'd1: tdata <= 16'h1201;
3'd2: tdata <= 16'h0814;
3'd3: tdata <= 16'h0C00;
3'd4: tdata <= 16'h0E02;
3'd5: tdata <= 16'h1000;
3'd6: tdata <= 16'h0A00;
default: load <= 0;
endcase
end
assign CMODE = 1'b1;
always @ (posedge BCLK)
begin
case (TLV)
4'd0: begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
index <= ~index;
TLV <= TLV + 4'b1;
end
4'd1: begin
nCS <= 1'b0;
TLV_data <= tdata;
MOSI <= TLV_data[bit_cnt];
TLV <= TLV + 4'b1;
end
4'd2: begin
SCLK <= 1'b1;
TLV <= TLV + 4'b1;
end
4'd3: begin
SCLK <= 1'b0;
TLV <= TLV + 4'b1;
end
4'd4: begin
if(bit_cnt == 0) begin
index <= ~index;
TLV <= 4'd5;
end
else begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'b1;
end
end
4'd5: begin
if (load == 7)begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else TLV <= 0;
end
default: TLV <= 0;
endcase
end
reg MCLK_12MHZ;
reg [2:0]MCLK_count;
always @ (posedge clock)
begin
if (MCLK_count == 4)
begin
MCLK_12MHZ <= ~MCLK_12MHZ;
MCLK_count <= 0;
end
else MCLK_count <= MCLK_count + 1'b1;
end
reg SPI_clk;
reg SPI_count;
always @(posedge CBCLK)
begin
if(SPI_count == 1)begin
SPI_clk <= ~SPI_clk;
SPI_count <=0;
end
else SPI_count <= SPI_count + 1'b1;
end
wire clock;
assign clock = CLKA;
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
assign A6 = MCLK_12MHZ;
wire reference;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bZ ;
wire [31:0]freq;
wire ready;
always @ (posedge ready)
begin
frequency <= frequency_HZ;
end
division division_DDS(.quotient(freq),.ready(ready),.dividend(frequency),.divider(32'd122880000),.clk(clock));
reg [31:0]sync_frequency;
always @ (posedge clock)
begin
sync_frequency <= freq;
end
reg [15:0]temp_ADC;
reg [31:0]frequency;
receiver receiver_inst(
.clock(clock),
.rate({DFS1, DFS0}),
.frequency(sync_frequency),
.out_strobe(),
.in_data(temp_ADC),
.out_data_I(rx_out_data_I),
.out_data_Q(rx_out_data_Q)
);
wire [23:0] rx_out_data_I;
wire [23:0] rx_out_data_Q;
I2SEncode I2S(.LRCLK(LRCLK), .BCLK(BCLK), .left_sample(rx_out_data_I), .right_sample(rx_out_data_Q), .outbit(MDOUT));
reg [5:0] bits;
reg [1:0]CC_state;
reg [58:0] CCdata;
always @(posedge CBCLK)
begin
case(CC_state)
0: begin
if (CLRCLK == 0)CC_state <= 0;
else CC_state <= 1;
end
1: begin
if (CLRCLK) CC_state <= 1;
else begin
bits <= 6'd58;
CC_state <= 2;
end
end
2: begin
CCdata[bits] <= CC;
if (bits == 0)CC_state <= 0;
else begin
bits <= bits - 1'b1;
CC_state <= 2;
end
end
default: CC_state <= 0;
endcase
end
reg PTT_out;
reg [3:0]Address;
reg [31:0]frequency_HZ;
reg [3:0]clock_select;
wire ref_ext;
wire source_122MHZ;
reg [1:0] ATTEN;
reg [1:0]TX_relay;
reg Rout;
reg [1:0]RX_relay;
always @ (negedge CLRCLK)
begin
PTT_out <= (CCdata[58]);
Address <= CCdata[57:54];
if(Address == 0)begin
frequency_HZ <= CCdata[53:22];
clock_select <= CCdata[21:18];
PGA <= 1'b0;
ATTRLY <= ~CCdata[9];
DITHER <= CCdata[8];
RAND <= CCdata[7];
ATTEN <= CCdata[6:5];
TX_relay <= CCdata[4:3];
Rout <= CCdata[2];
RX_relay <= CCdata[1:0];
end
end
assign ref_ext = clock_select[1];
assign source_122MHZ = clock_select[2] ;
wire [6:0]LPF;
wire [5:0]select_HPF;
wire [31:0]frequency_plus_IF;
assign frequency_plus_IF = frequency + 32'd9000;
LPF_select Alex_LPF_select(.frequency(frequency_plus_IF), .LPF(LPF));
HPF_select Alex_HPF_select(.frequency(frequency_plus_IF), .HPF(select_HPF));
wire ANT1;
wire ANT2;
wire ANT3;
wire Rx_1_out;
wire Transverter;
wire Rx_2_in;
wire Rx_1_in;
assign Rx_1_out = Rout;
assign ANT1 = (TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign ANT2 = (TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign ANT3 = (TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Rx_1_in = (RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign Rx_2_in = (RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Transverter = (RX_relay == 2'b11) ? 1'b1 : 1'b0;
wire _6m_preamp;
wire Tx_yellow_led = 1'b1;
wire Rx_yellow_led = 1'b1;
wire Tx_red_led;
wire Rx_red_led;
wire TR_relay;
wire [15:0]Alex_Tx_data;
wire [15:0]Alex_Rx_data;
wire _10dB_atten = ATTEN[0];
wire _20dB_atten = ATTEN[1];
assign Tx_red_led = PTT_out;
assign TR_relay = PTT_out;
assign Alex_Tx_data = {LPF[6:4],Tx_red_led,TR_relay,ANT3,ANT2,ANT1,LPF[3:0],Tx_yellow_led,3'b000};
assign Rx_red_led = PTT_out;
assign _6m_preamp = (frequency_plus_IF > 50000000) ? 1'b1 : 1'b0;
wire [5:0]HPF;
assign HPF = _6m_preamp ? 6'd0 : select_HPF;
assign Alex_Rx_data = {Rx_red_led,_10dB_atten ,_20dB_atten, HPF[5], Rx_1_out,Rx_1_in,Rx_2_in,Transverter,
1'b0, HPF[4:2],_6m_preamp,HPF[1:0],Rx_yellow_led};
wire [31:0]Alex_data;
assign Alex_data[31:0] = {Alex_Tx_data[15:0],Alex_Rx_data[15:0]};
SPI Alex_SPI_Tx(.Alex_data(Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe),.spi_clock(SPI_clk));
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge clock) begin
if (count_12288 == 767) begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else begin
count_12288 <= 1'b1 + count_12288;
end
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED3 = TX_relay[0];
assign DEBUG_LED4 = TX_relay[1];
assign DEBUG_LED5 = RX_relay[0];
assign DEBUG_LED6 = RX_relay[1];
assign DEBUG_LED7 = Rout;
assign TEST0 = osc_80khz;
assign TEST1 = ref_80khz;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
reg [26:0]counter;
always @(posedge CLKA) counter = counter + 1'b1;
assign {DEBUG_LED2,DEBUG_LED1} = counter[26:25];
endmodule | module Mercury(
input OSC_10MHZ,
inout ext_10MHZ,
input CLKA,
input [15:0]INA,
input CC,
output reg ATTRLY,
output A6,
input C4,
input C8,
input C9,
input C17,
output MDOUT,
input BCLK,
input LRCLK,
output CDIN,
output CBCLK,
output CLRCLK,
output CLRCOUT,
output CMCLK,
output CMODE,
output reg MOSI,
output reg SCLK,
output reg nCS,
output SPI_data,
output SPI_clock,
output Tx_load_strobe,
output Rx_load_strobe,
output FPGA_PLL,
output LVDS_TXE,
output LVDS_RXE_N,
input OVERFLOW,
output reg DITHER,
output SHDN,
output reg PGA,
output reg RAND,
output INIT_DONE,
output TEST0,
output TEST1,
output TEST2,
output TEST3,
output DEBUG_LED0,
output DEBUG_LED1,
output DEBUG_LED2,
output DEBUG_LED3,
output DEBUG_LED4,
output DEBUG_LED5,
output DEBUG_LED6,
output DEBUG_LED7,
input DFS0, DFS1
); |
reg data_ready;
assign CDIN = C4;
assign CLRCLK = C9;
assign CLRCOUT = C9;
assign CBCLK = C8;
assign CMCLK = C17;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
always @ (posedge clock)
begin
if (RAND) begin
if (INA[0]) temp_ADC <= {~INA[15:1],INA[0]};
else temp_ADC <= INA;
end
else temp_ADC <= INA;
end
reg index;
reg [15:0]tdata;
reg [2:0]load;
reg [3:0]TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @ (posedge index)
begin
load <= load + 3'b1;
case (load)
3'd0: tdata <= 16'h1E00;
3'd1: tdata <= 16'h1201;
3'd2: tdata <= 16'h0814;
3'd3: tdata <= 16'h0C00;
3'd4: tdata <= 16'h0E02;
3'd5: tdata <= 16'h1000;
3'd6: tdata <= 16'h0A00;
default: load <= 0;
endcase
end
assign CMODE = 1'b1;
always @ (posedge BCLK)
begin
case (TLV)
4'd0: begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
index <= ~index;
TLV <= TLV + 4'b1;
end
4'd1: begin
nCS <= 1'b0;
TLV_data <= tdata;
MOSI <= TLV_data[bit_cnt];
TLV <= TLV + 4'b1;
end
4'd2: begin
SCLK <= 1'b1;
TLV <= TLV + 4'b1;
end
4'd3: begin
SCLK <= 1'b0;
TLV <= TLV + 4'b1;
end
4'd4: begin
if(bit_cnt == 0) begin
index <= ~index;
TLV <= 4'd5;
end
else begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'b1;
end
end
4'd5: begin
if (load == 7)begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else TLV <= 0;
end
default: TLV <= 0;
endcase
end
reg MCLK_12MHZ;
reg [2:0]MCLK_count;
always @ (posedge clock)
begin
if (MCLK_count == 4)
begin
MCLK_12MHZ <= ~MCLK_12MHZ;
MCLK_count <= 0;
end
else MCLK_count <= MCLK_count + 1'b1;
end
reg SPI_clk;
reg SPI_count;
always @(posedge CBCLK)
begin
if(SPI_count == 1)begin
SPI_clk <= ~SPI_clk;
SPI_count <=0;
end
else SPI_count <= SPI_count + 1'b1;
end
wire clock;
assign clock = CLKA;
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
assign A6 = MCLK_12MHZ;
wire reference;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bZ ;
wire [31:0]freq;
wire ready;
always @ (posedge ready)
begin
frequency <= frequency_HZ;
end
division division_DDS(.quotient(freq),.ready(ready),.dividend(frequency),.divider(32'd122880000),.clk(clock));
reg [31:0]sync_frequency;
always @ (posedge clock)
begin
sync_frequency <= freq;
end
reg [15:0]temp_ADC;
reg [31:0]frequency;
receiver receiver_inst(
.clock(clock),
.rate({DFS1, DFS0}),
.frequency(sync_frequency),
.out_strobe(),
.in_data(temp_ADC),
.out_data_I(rx_out_data_I),
.out_data_Q(rx_out_data_Q)
);
wire [23:0] rx_out_data_I;
wire [23:0] rx_out_data_Q;
I2SEncode I2S(.LRCLK(LRCLK), .BCLK(BCLK), .left_sample(rx_out_data_I), .right_sample(rx_out_data_Q), .outbit(MDOUT));
reg [5:0] bits;
reg [1:0]CC_state;
reg [58:0] CCdata;
always @(posedge CBCLK)
begin
case(CC_state)
0: begin
if (CLRCLK == 0)CC_state <= 0;
else CC_state <= 1;
end
1: begin
if (CLRCLK) CC_state <= 1;
else begin
bits <= 6'd58;
CC_state <= 2;
end
end
2: begin
CCdata[bits] <= CC;
if (bits == 0)CC_state <= 0;
else begin
bits <= bits - 1'b1;
CC_state <= 2;
end
end
default: CC_state <= 0;
endcase
end
reg PTT_out;
reg [3:0]Address;
reg [31:0]frequency_HZ;
reg [3:0]clock_select;
wire ref_ext;
wire source_122MHZ;
reg [1:0] ATTEN;
reg [1:0]TX_relay;
reg Rout;
reg [1:0]RX_relay;
always @ (negedge CLRCLK)
begin
PTT_out <= (CCdata[58]);
Address <= CCdata[57:54];
if(Address == 0)begin
frequency_HZ <= CCdata[53:22];
clock_select <= CCdata[21:18];
PGA <= 1'b0;
ATTRLY <= ~CCdata[9];
DITHER <= CCdata[8];
RAND <= CCdata[7];
ATTEN <= CCdata[6:5];
TX_relay <= CCdata[4:3];
Rout <= CCdata[2];
RX_relay <= CCdata[1:0];
end
end
assign ref_ext = clock_select[1];
assign source_122MHZ = clock_select[2] ;
wire [6:0]LPF;
wire [5:0]select_HPF;
wire [31:0]frequency_plus_IF;
assign frequency_plus_IF = frequency + 32'd9000;
LPF_select Alex_LPF_select(.frequency(frequency_plus_IF), .LPF(LPF));
HPF_select Alex_HPF_select(.frequency(frequency_plus_IF), .HPF(select_HPF));
wire ANT1;
wire ANT2;
wire ANT3;
wire Rx_1_out;
wire Transverter;
wire Rx_2_in;
wire Rx_1_in;
assign Rx_1_out = Rout;
assign ANT1 = (TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign ANT2 = (TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign ANT3 = (TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Rx_1_in = (RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign Rx_2_in = (RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Transverter = (RX_relay == 2'b11) ? 1'b1 : 1'b0;
wire _6m_preamp;
wire Tx_yellow_led = 1'b1;
wire Rx_yellow_led = 1'b1;
wire Tx_red_led;
wire Rx_red_led;
wire TR_relay;
wire [15:0]Alex_Tx_data;
wire [15:0]Alex_Rx_data;
wire _10dB_atten = ATTEN[0];
wire _20dB_atten = ATTEN[1];
assign Tx_red_led = PTT_out;
assign TR_relay = PTT_out;
assign Alex_Tx_data = {LPF[6:4],Tx_red_led,TR_relay,ANT3,ANT2,ANT1,LPF[3:0],Tx_yellow_led,3'b000};
assign Rx_red_led = PTT_out;
assign _6m_preamp = (frequency_plus_IF > 50000000) ? 1'b1 : 1'b0;
wire [5:0]HPF;
assign HPF = _6m_preamp ? 6'd0 : select_HPF;
assign Alex_Rx_data = {Rx_red_led,_10dB_atten ,_20dB_atten, HPF[5], Rx_1_out,Rx_1_in,Rx_2_in,Transverter,
1'b0, HPF[4:2],_6m_preamp,HPF[1:0],Rx_yellow_led};
wire [31:0]Alex_data;
assign Alex_data[31:0] = {Alex_Tx_data[15:0],Alex_Rx_data[15:0]};
SPI Alex_SPI_Tx(.Alex_data(Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe),.spi_clock(SPI_clk));
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge clock) begin
if (count_12288 == 767) begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else begin
count_12288 <= 1'b1 + count_12288;
end
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED3 = TX_relay[0];
assign DEBUG_LED4 = TX_relay[1];
assign DEBUG_LED5 = RX_relay[0];
assign DEBUG_LED6 = RX_relay[1];
assign DEBUG_LED7 = Rout;
assign TEST0 = osc_80khz;
assign TEST1 = ref_80khz;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
reg [26:0]counter;
always @(posedge CLKA) counter = counter + 1'b1;
assign {DEBUG_LED2,DEBUG_LED1} = counter[26:25];
endmodule | 17 |
138,816 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/PLL.v | 86,169,941 | PLL.v | v | 49 | 75 | [] | [] | [] | [(11, 47)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/PLL.v\n%Error: Exiting due to 4 error(s)\n' | 302,863 | module | module PLL(clock, reference, FPGA_PLL, osc_80khz, ref_80khz);
input clock;
inout reference;
output FPGA_PLL;
output osc_80khz;
output ref_80khz;
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge clock)
begin
if (count_12288 == 767)
begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else
count_12288 <= count_12288 + 1'b1;
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
endmodule | module PLL(clock, reference, FPGA_PLL, osc_80khz, ref_80khz); |
input clock;
inout reference;
output FPGA_PLL;
output osc_80khz;
output ref_80khz;
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge clock)
begin
if (count_12288 == 767)
begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else
count_12288 <= count_12288 + 1'b1;
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
endmodule | 17 |
138,817 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/random.v | 86,169,941 | random.v | v | 25 | 90 | [] | [] | [] | [(5, 24)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/random.v\n%Error: Exiting due to 4 error(s)\n' | 302,864 | module | module random(
input clock,
input signed [15:0]ADC_samples,
input random,
output reg[15:0]out
);
always @ (posedge clock)
begin
if (random)begin
if (ADC_samples[0])
out <= {~ADC_samples[15:1],ADC_samples[0]};
else
out <= ADC_samples;
end
else
out <= ADC_samples;
end
endmodule | module random(
input clock,
input signed [15:0]ADC_samples,
input random,
output reg[15:0]out
); |
always @ (posedge clock)
begin
if (random)begin
if (ADC_samples[0])
out <= {~ADC_samples[15:1],ADC_samples[0]};
else
out <= ADC_samples;
end
else
out <= ADC_samples;
end
endmodule | 17 |
138,818 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/software_serial.v | 86,169,941 | software_serial.v | v | 72 | 106 | [] | [] | [] | [(24, 70)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/software_serial.v\n%Error: Exiting due to 4 error(s)\n' | 302,866 | module | module software_serial(BCLK,LRCLK,SERIAL,serno);
input BCLK;
input LRCLK;
input [7:0]SERIAL;
output reg serno;
reg [1:0]sno_send;
reg [3:0]sno_data_count;
always @ (posedge BCLK)
begin
case(sno_send)
0: if (LRCLK) sno_send <= 1;
else sno_send <= 0;
1: if (LRCLK) sno_send <= 1;
else begin
sno_data_count <= 15;
sno_send <= 2;
end
2: begin
if (sno_data_count == 0)begin
sno_send <= 0;
end
else begin
sno_data_count <= sno_data_count - 1'b1;
sno_send <= 2;
end
end
default: sno_send <= 0;
endcase
end
reg serial_number;
always @ (negedge BCLK)
begin
if (sno_send == 2 && sno_data_count < 8)
serno <= SERIAL[sno_data_count];
else serno <= 1'bz;
end
endmodule | module software_serial(BCLK,LRCLK,SERIAL,serno); |
input BCLK;
input LRCLK;
input [7:0]SERIAL;
output reg serno;
reg [1:0]sno_send;
reg [3:0]sno_data_count;
always @ (posedge BCLK)
begin
case(sno_send)
0: if (LRCLK) sno_send <= 1;
else sno_send <= 0;
1: if (LRCLK) sno_send <= 1;
else begin
sno_data_count <= 15;
sno_send <= 2;
end
2: begin
if (sno_data_count == 0)begin
sno_send <= 0;
end
else begin
sno_data_count <= sno_data_count - 1'b1;
sno_send <= 2;
end
end
default: sno_send <= 0;
endcase
end
reg serial_number;
always @ (negedge BCLK)
begin
if (sno_send == 2 && sno_data_count < 8)
serno <= SERIAL[sno_data_count];
else serno <= 1'bz;
end
endmodule | 17 |
138,820 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/TLV320.v | 86,169,941 | TLV320.v | v | 121 | 71 | [] | [] | [] | [(21, 120)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/TLV320.v\n%Error: Exiting due to 4 error(s)\n' | 302,870 | module | module TLV320(
input clock,
output reg nCS,
output reg MOSI,
output reg SCLK,
output CMODE
);
reg [2:0] load;
reg [3:0] TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @*
begin
case (load)
3'd0: TLV_data = 16'h1E00;
3'd1: TLV_data = 16'h1201;
3'd2: TLV_data = 16'h0814;
3'd3: TLV_data = 16'h0C00;
3'd4: TLV_data = 16'h0E02;
3'd5: TLV_data = 16'h1000;
3'd6: TLV_data = 16'h0A00;
default: TLV_data = 0;
endcase
end
assign CMODE = 1'b1;
reg [23:0] tlv_timeout;
always @ (posedge clock)
begin
if (tlv_timeout != (200*12288))
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
if (tlv_timeout == (200*12288))
TLV <= 4'd1;
else
TLV <= 4'd0;
end
4'd1:
begin
nCS <= 1'b0;
MOSI <= TLV_data[bit_cnt];
TLV <= 4'd2;
end
4'd2:
begin
SCLK <= 1'b1;
TLV <= 4'd3;
end
4'd3:
begin
SCLK <= 1'b0;
TLV <= 4'd4;
end
4'd4:
begin
if (bit_cnt == 0)
TLV <= 4'd5;
else
begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1;
end
end
4'd5:
begin
if (load == 6)
begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else
begin
TLV <= 4'd0;
load <= load + 3'b1;
end
end
default: TLV <= 4'd0;
endcase
end
endmodule | module TLV320(
input clock,
output reg nCS,
output reg MOSI,
output reg SCLK,
output CMODE
); |
reg [2:0] load;
reg [3:0] TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @*
begin
case (load)
3'd0: TLV_data = 16'h1E00;
3'd1: TLV_data = 16'h1201;
3'd2: TLV_data = 16'h0814;
3'd3: TLV_data = 16'h0C00;
3'd4: TLV_data = 16'h0E02;
3'd5: TLV_data = 16'h1000;
3'd6: TLV_data = 16'h0A00;
default: TLV_data = 0;
endcase
end
assign CMODE = 1'b1;
reg [23:0] tlv_timeout;
always @ (posedge clock)
begin
if (tlv_timeout != (200*12288))
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
if (tlv_timeout == (200*12288))
TLV <= 4'd1;
else
TLV <= 4'd0;
end
4'd1:
begin
nCS <= 1'b0;
MOSI <= TLV_data[bit_cnt];
TLV <= 4'd2;
end
4'd2:
begin
SCLK <= 1'b1;
TLV <= 4'd3;
end
4'd3:
begin
SCLK <= 1'b0;
TLV <= 4'd4;
end
4'd4:
begin
if (bit_cnt == 0)
TLV <= 4'd5;
else
begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1;
end
end
4'd5:
begin
if (load == 6)
begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else
begin
TLV <= 4'd0;
load <= load + 3'b1;
end
end
default: TLV <= 4'd0;
endcase
end
endmodule | 17 |
138,821 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2/varcic.v | 86,169,941 | varcic.v | v | 147 | 85 | [] | [] | [] | [(25, 145)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2/varcic.v\n%Error: Exiting due to 4 error(s)\n' | 302,871 | module | module varcic( extra_decimation, clock, in_strobe, out_strobe, in_data, out_data );
parameter STAGES = 5;
parameter DECIMATION = 320;
parameter IN_WIDTH = 22;
parameter ACC_WIDTH = 64;
parameter OUT_WIDTH = 27;
input [1:0] extra_decimation;
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output reg signed [OUT_WIDTH-1:0] out_data;
reg [15:0] sample_no;
initial sample_no = 16'd0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == ((DECIMATION << (2-extra_decimation))-1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
localparam MSB0 = ACC_WIDTH - 1;
localparam LSB0 = ACC_WIDTH - OUT_WIDTH;
localparam MSB1 = MSB0 - STAGES;
localparam LSB1 = LSB0 - STAGES;
localparam MSB2 = MSB1 - STAGES;
localparam LSB2 = LSB1 - STAGES;
always @(posedge clock)
case (extra_decimation)
0: out_data <= comb_data[STAGES][MSB0:LSB0] + comb_data[STAGES][LSB0-1];
1: out_data <= comb_data[STAGES][MSB1:LSB1] + comb_data[STAGES][LSB1-1];
2: out_data <= comb_data[STAGES][MSB2:LSB2] + comb_data[STAGES][LSB2-1];
endcase
endmodule | module varcic( extra_decimation, clock, in_strobe, out_strobe, in_data, out_data ); |
parameter STAGES = 5;
parameter DECIMATION = 320;
parameter IN_WIDTH = 22;
parameter ACC_WIDTH = 64;
parameter OUT_WIDTH = 27;
input [1:0] extra_decimation;
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output reg signed [OUT_WIDTH-1:0] out_data;
reg [15:0] sample_no;
initial sample_no = 16'd0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == ((DECIMATION << (2-extra_decimation))-1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
localparam MSB0 = ACC_WIDTH - 1;
localparam LSB0 = ACC_WIDTH - OUT_WIDTH;
localparam MSB1 = MSB0 - STAGES;
localparam LSB1 = LSB0 - STAGES;
localparam MSB2 = MSB1 - STAGES;
localparam LSB2 = LSB1 - STAGES;
always @(posedge clock)
case (extra_decimation)
0: out_data <= comb_data[STAGES][MSB0:LSB0] + comb_data[STAGES][LSB0-1];
1: out_data <= comb_data[STAGES][MSB1:LSB1] + comb_data[STAGES][LSB1-1];
2: out_data <= comb_data[STAGES][MSB2:LSB2] + comb_data[STAGES][LSB2-1];
endcase
endmodule | 17 |
138,822 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2.7/LPF_select.v | 86,169,941 | LPF_select.v | v | 61 | 82 | [] | ['general public license', 'free software foundation'] | [] | [(43, 61)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2.7,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2.7/LPF_select.v\n%Error: Exiting due to 4 error(s)\n' | 302,886 | module | module LPF_select(clock, frequency, LPF);
input wire clock;
input wire [31:0] frequency;
output reg [6:0] LPF;
always @(posedge clock)
begin
if (frequency > 29700000) LPF <= 7'b0010000;
else if (frequency > 21450000) LPF <= 7'b0100000;
else if (frequency > 14350000) LPF <= 7'b1000000;
else if (frequency > 7300000) LPF <= 7'b0000001;
else if (frequency > 4000000) LPF <= 7'b0000010;
else if (frequency > 2000000) LPF <= 7'b0000100;
else LPF <= 7'b0001000;
end
endmodule | module LPF_select(clock, frequency, LPF); |
input wire clock;
input wire [31:0] frequency;
output reg [6:0] LPF;
always @(posedge clock)
begin
if (frequency > 29700000) LPF <= 7'b0010000;
else if (frequency > 21450000) LPF <= 7'b0100000;
else if (frequency > 14350000) LPF <= 7'b1000000;
else if (frequency > 7300000) LPF <= 7'b0000001;
else if (frequency > 4000000) LPF <= 7'b0000010;
else if (frequency > 2000000) LPF <= 7'b0000100;
else LPF <= 7'b0001000;
end
endmodule | 17 |
138,824 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2.7/common/NWire_xmit.v | 86,169,941 | NWire_xmit.v | v | 295 | 131 | [] | ['general public license', 'free software foundation'] | [] | [(78, 295)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2.7/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2.7/common/NWire_xmit.v\n%Error: Exiting due to 4 error(s)\n' | 302,904 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,825 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2.8/common/clk_div.v | 86,169,941 | clk_div.v | v | 43 | 64 | [] | [] | [] | [(9, 43)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2.8/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2.8/common/clk_div.v\n%Error: Exiting due to 4 error(s)\n' | 302,909 | module | module clk_div (reset, clk_in, clk_out);
input wire reset;
input wire clk_in;
output reg clk_out;
parameter CLK_DIV = 10;
parameter TPD = 1;
localparam SZ = clogb2 ((CLK_DIV/2)-1);
reg [SZ-1:0] cnt;
always @ (posedge clk_in)
begin
if (reset)
clk_out <= #TPD 1'b0;
else if (cnt == ((CLK_DIV/2)-1))
clk_out <= #TPD ~clk_out;
if (reset)
cnt <= #TPD 0;
else if (cnt == ((CLK_DIV/2)-1))
cnt <= #TPD 1'b0;
else
cnt <= #TPD cnt + 1'b1;
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | module clk_div (reset, clk_in, clk_out); |
input wire reset;
input wire clk_in;
output reg clk_out;
parameter CLK_DIV = 10;
parameter TPD = 1;
localparam SZ = clogb2 ((CLK_DIV/2)-1);
reg [SZ-1:0] cnt;
always @ (posedge clk_in)
begin
if (reset)
clk_out <= #TPD 1'b0;
else if (cnt == ((CLK_DIV/2)-1))
clk_out <= #TPD ~clk_out;
if (reset)
cnt <= #TPD 0;
else if (cnt == ((CLK_DIV/2)-1))
cnt <= #TPD 1'b0;
else
cnt <= #TPD cnt + 1'b1;
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | 17 |
138,826 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2.8/common/clk_div.v | 86,169,941 | clk_div.v | v | 43 | 64 | [] | [] | [] | [(9, 43)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2.8/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2.8/common/clk_div.v\n%Error: Exiting due to 4 error(s)\n' | 302,909 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,827 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2.8/common/clk_lrclk_gen.v | 86,169,941 | clk_lrclk_gen.v | v | 118 | 100 | [] | [] | [] | [(9, 118)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2.8/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2.8/common/clk_lrclk_gen.v\n%Error: Exiting due to 4 error(s)\n' | 302,910 | module | module clk_lrclk_gen (reset, CLK_IN, BCLK, Brise, Bfall, LRCLK, LRrise, LRfall, Speed);
parameter BCLK_00 = 32;
parameter BCLK_01 = 32;
parameter BCLK_10 = 32;
parameter CLK_FREQ = 122880000;
input wire reset;
input wire CLK_IN;
output reg BCLK;
output reg Brise;
output reg Bfall;
output reg LRCLK;
output reg LRrise;
output reg LRfall;
input wire [1:0] Speed;
localparam LS = clogb2 (BCLK_00-1);
reg [15:0] BCLK_cnt;
reg [15:0] BCLK_DIV;
reg [LS-1:0] LRCLK_cnt;
localparam TPD = 1;
always @*
begin
case (Speed)
2'b00:
BCLK_DIV = (CLK_FREQ/48000/(BCLK_00*2));
2'b01:
BCLK_DIV = (CLK_FREQ/96000/(BCLK_01*2));
2'b10:
BCLK_DIV = (CLK_FREQ/192000/(BCLK_10*2));
2'b11:
BCLK_DIV = (CLK_FREQ/48000/(BCLK_00*2));
endcase
end
always @ (posedge CLK_IN)
begin
if (reset)
BCLK_cnt <= #TPD 0;
else if (BCLK_cnt == (BCLK_DIV-1))
BCLK_cnt <= #TPD 0;
else
BCLK_cnt <= #TPD BCLK_cnt + 1'b1;
if (reset)
Brise <= 1'b0;
else
Brise <= (BCLK_cnt == (BCLK_DIV/2));
if (reset)
Bfall <= 1'b0;
else
Bfall <= (BCLK_cnt == 1'b0);
if (Brise)
BCLK <= #TPD 1'b1;
else if (Bfall)
BCLK <= #TPD 1'b0;
if (reset)
LRCLK_cnt <= #TPD 0;
else
begin
if ((LRCLK_cnt == 0) && Bfall)
begin
case (Speed)
2'b00:
LRCLK_cnt <= #TPD BCLK_00-1;
2'b01:
LRCLK_cnt <= #TPD BCLK_01-1;
2'b10:
LRCLK_cnt <= #TPD BCLK_10-1;
2'b11:
LRCLK_cnt <= #TPD BCLK_00-1;
endcase
end
else if (Bfall)
LRCLK_cnt <= #TPD LRCLK_cnt - 1'b1;
end
if (reset)
LRCLK <= #TPD 1'b1;
else if ((LRCLK_cnt == 0) && Bfall)
LRCLK <= #TPD ~LRCLK;
if (reset)
LRrise <= 1'b0;
else
LRrise <= (LRCLK_cnt == 0) && Bfall && !LRCLK;
if (reset)
LRfall <= 1'b0;
else
LRfall <= (LRCLK_cnt == 0) && Bfall && LRCLK;
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | module clk_lrclk_gen (reset, CLK_IN, BCLK, Brise, Bfall, LRCLK, LRrise, LRfall, Speed); |
parameter BCLK_00 = 32;
parameter BCLK_01 = 32;
parameter BCLK_10 = 32;
parameter CLK_FREQ = 122880000;
input wire reset;
input wire CLK_IN;
output reg BCLK;
output reg Brise;
output reg Bfall;
output reg LRCLK;
output reg LRrise;
output reg LRfall;
input wire [1:0] Speed;
localparam LS = clogb2 (BCLK_00-1);
reg [15:0] BCLK_cnt;
reg [15:0] BCLK_DIV;
reg [LS-1:0] LRCLK_cnt;
localparam TPD = 1;
always @*
begin
case (Speed)
2'b00:
BCLK_DIV = (CLK_FREQ/48000/(BCLK_00*2));
2'b01:
BCLK_DIV = (CLK_FREQ/96000/(BCLK_01*2));
2'b10:
BCLK_DIV = (CLK_FREQ/192000/(BCLK_10*2));
2'b11:
BCLK_DIV = (CLK_FREQ/48000/(BCLK_00*2));
endcase
end
always @ (posedge CLK_IN)
begin
if (reset)
BCLK_cnt <= #TPD 0;
else if (BCLK_cnt == (BCLK_DIV-1))
BCLK_cnt <= #TPD 0;
else
BCLK_cnt <= #TPD BCLK_cnt + 1'b1;
if (reset)
Brise <= 1'b0;
else
Brise <= (BCLK_cnt == (BCLK_DIV/2));
if (reset)
Bfall <= 1'b0;
else
Bfall <= (BCLK_cnt == 1'b0);
if (Brise)
BCLK <= #TPD 1'b1;
else if (Bfall)
BCLK <= #TPD 1'b0;
if (reset)
LRCLK_cnt <= #TPD 0;
else
begin
if ((LRCLK_cnt == 0) && Bfall)
begin
case (Speed)
2'b00:
LRCLK_cnt <= #TPD BCLK_00-1;
2'b01:
LRCLK_cnt <= #TPD BCLK_01-1;
2'b10:
LRCLK_cnt <= #TPD BCLK_10-1;
2'b11:
LRCLK_cnt <= #TPD BCLK_00-1;
endcase
end
else if (Bfall)
LRCLK_cnt <= #TPD LRCLK_cnt - 1'b1;
end
if (reset)
LRCLK <= #TPD 1'b1;
else if ((LRCLK_cnt == 0) && Bfall)
LRCLK <= #TPD ~LRCLK;
if (reset)
LRrise <= 1'b0;
else
LRrise <= (LRCLK_cnt == 0) && Bfall && !LRCLK;
if (reset)
LRfall <= 1'b0;
else
LRfall <= (LRCLK_cnt == 0) && Bfall && LRCLK;
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | 17 |
138,828 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2.8/common/clk_lrclk_gen.v | 86,169,941 | clk_lrclk_gen.v | v | 118 | 100 | [] | [] | [] | [(9, 118)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2.8/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2.8/common/clk_lrclk_gen.v\n%Error: Exiting due to 4 error(s)\n' | 302,910 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,831 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V2.8/common/OneWire_rcv.v | 86,169,941 | OneWire_rcv.v | v | 194 | 104 | [] | [] | [] | null | line:22 column:73: Illegal character '\x00' | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V2.8/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V2.8/common/OneWire_rcv.v\n%Error: Exiting due to 4 error(s)\n' | 302,915 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,838 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury V3.0/Mercury/Mercury.v | 86,169,941 | Mercury.v | v | 815 | 124 | [] | ['general public license', 'free software foundation'] | [] | [(58, 811)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury.sv\n 1/Mercury/Source/Archive/Mercury\n 1/Mercury/Source/Archive/Mercury.v\n 1/Mercury/Source/Archive/Mercury.sv\n obj_dir/1/Mercury/Source/Archive/Mercury\n obj_dir/1/Mercury/Source/Archive/Mercury.v\n obj_dir/1/Mercury/Source/Archive/Mercury.sv\n%Error: Cannot find file containing module: V3.0/Mercury,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V3.0/Mercury/Mercury.v\n%Error: Exiting due to 4 error(s)\n' | 303,013 | module | module Mercury(OSC_10MHZ, ext_10MHZ,AUX_CLK, C122_clk,INA,CC,ATTRLY,A6,A12,C21,C23,C24,MDOUT,CDIN,TLV320_BCLK,TLV320_LRCIN,
TLV320_LRCOUT,TLV320_MCLK,CMODE,MOSI,SCLK,nCS,SPI_data,SPI_clock,Tx_load_strobe,Rx_load_strobe,
FPGA_PLL,LVDS_TXE,LVDS_RXE_N,OVERFLOW,DITHER,SHDN,PGA,RAND,INIT_DONE,TEST0,TEST1,TEST2,TEST3,
DEBUG_LED0,DEBUG_LED1,DEBUG_LED2,DEBUG_LED3,DEBUG_LED4,DEBUG_LED5,DEBUG_LED6,DEBUG_LED7 );
input wire OSC_10MHZ;
inout tri ext_10MHZ;
input wire AUX_CLK;
input wire C122_clk;
input wire [15:0] INA;
input wire CC;
output reg ATTRLY;
output wire A6;
output wire A12;
input wire C21;
output wire C23;
input wire C24;
output wire MDOUT;
output wire CDIN;
output wire TLV320_BCLK;
output wire TLV320_LRCIN;
output wire TLV320_LRCOUT;
output wire TLV320_MCLK;
output wire CMODE;
output reg MOSI;
output reg SCLK;
output reg nCS;
output wire SPI_data;
output wire SPI_clock;
output wire Tx_load_strobe;
output wire Rx_load_strobe;
output wire FPGA_PLL;
output wire LVDS_TXE;
output wire LVDS_RXE_N;
input wire OVERFLOW;
output reg DITHER;
output wire SHDN;
output wire PGA;
output reg RAND;
output wire INIT_DONE;
output wire TEST0;
output wire TEST1;
output wire TEST2;
output wire TEST3;
output wire DEBUG_LED0;
output wire DEBUG_LED1;
output wire DEBUG_LED2;
output wire DEBUG_LED3;
output wire DEBUG_LED4;
output wire DEBUG_LED5;
output wire DEBUG_LED6;
output wire DEBUG_LED7;
parameter C122_TPD = 2.1;
localparam SERIAL = 8'd30;
reg [15:0] temp_ADC;
reg data_ready;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
assign PGA = 1'b0;
reg C122_rst;
reg [10:0] C122_rst_cnt;
always @(posedge C122_clk)
begin
if (!C122_rst_cnt[10])
C122_rst_cnt <= #C122_TPD C122_rst_cnt + 1'b1;
C122_rst <= #C122_TPD C122_rst_cnt[10] ? 1'b0 : 1'b1;
end
always @ (posedge C122_clk)
begin
if (RAND)
begin
if (INA[0])
temp_ADC <= {~INA[15:1],INA[0]};
else
temp_ADC <= INA;
end
else
temp_ADC <= INA;
end
reg [2:0] load;
reg [3:0] TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @*
begin
case (load)
3'd0: TLV_data = 16'h1E00;
3'd1: TLV_data = 16'h1201;
3'd2: TLV_data = 16'h0814;
3'd3: TLV_data = 16'h0C00;
3'd4: TLV_data = 16'h0E02;
3'd5: TLV_data = 16'h1000;
3'd6: TLV_data = 16'h0A00;
default: TLV_data = 0;
endcase
end
assign CMODE = 1'b1;
reg [23:0] tlv_timeout;
always @ (posedge BCLK)
begin
if (tlv_timeout != (200*12288))
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
if (tlv_timeout == (200*12288))
TLV <= 4'd1;
else
TLV <= 4'd0;
end
4'd1:
begin
nCS <= 1'b0;
MOSI <= TLV_data[bit_cnt];
TLV <= 4'd2;
end
4'd2:
begin
SCLK <= 1'b1;
TLV <= 4'd3;
end
4'd3:
begin
SCLK <= 1'b0;
TLV <= 4'd4;
end
4'd4:
begin
if (bit_cnt == 0)
TLV <= 4'd5;
else
begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1;
end
end
4'd5:
begin
if (load == 6)
begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else
begin
TLV <= 4'd0;
load <= load + 3'b1;
end
end
default: TLV <= 4'd0;
endcase
end
localparam SPEED_48K = 2'b00;
reg C122_DFS1, C122_DFS0;
wire C122_cbrise, C122_cbfall;
wire source_122MHZ;
reg C122_cgen_rst;
reg [1:0] C122_SPEED;
clk_div TLVCLK (.reset(C122_rst), .clk_in(C122_clk), .clk_out(TLV320_MCLK));
always @(posedge C122_clk)
begin
if (C122_rst)
C122_SPEED <= 2'b00;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_SPEED <= {C122_DFS1,C122_DFS0};
if (C122_rst)
C122_cgen_rst <= 1'b1;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_cgen_rst <= 1'b1;
else
C122_cgen_rst <= 1'b0;
end
wire C122_cbclk, CLRCLK;
clk_lrclk_gen clrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(C122_cbclk),
.Brise(C122_cbrise), .Bfall(C122_cbfall), .LRCLK(CLRCLK), .Speed(SPEED_48K));
assign TLV320_BCLK = C122_cbclk;
assign TLV320_LRCIN = CLRCLK;
assign TLV320_LRCOUT = CLRCLK;
wire BCLK;
clk_lrclk_gen lrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(BCLK), .Speed(C122_SPEED));
wire SPI_clk;
reg [1:0] spc;
always @(posedge C122_cbclk)
begin
if (C122_rst)
spc <= 2'b00;
else spc <= spc + 2'b01;
end
assign SPI_clk = spc[1];
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
wire reference;
wire ref_ext;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bz;
wire C122_LR_rdy;
wire [31:0] C122_LR_data;
NWire_rcv #(.DATA_BITS(32), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
LRAudio (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_rdy(C122_LR_rdy), .xrcv_ack(C122_LR_rdy), .xrcv_data(C122_LR_data),
.din(C24));
TestModeChecker tmc (C122_rst, C122_clk, C122_LR_data, C122_LR_rdy);
assign C23 = CLRCLK;
I2S_xmit #(.DATA_BITS(32))
LR (.rst(C122_rst), .lrclk(CLRCLK), .clk(C122_clk), .CBrise(C122_cbrise),
.CBfall(C122_cbfall), .sample(C122_LR_data), .outbit(CDIN));
reg [31:0] C122_frequency_HZ;
reg [31:0] C122_last_freq;
reg [31:0] C122_sync_phase_word;
wire [63:0] C122_ratio;
localparam M2 = 32'd1172812403;
assign C122_ratio = C122_frequency_HZ * M2;
always @ (posedge C122_clk)
begin
if (C122_cbrise)
begin
C122_last_freq <= C122_frequency_HZ;
if (C122_last_freq != C122_frequency_HZ)
C122_sync_phase_word <= C122_ratio[56:25];
end
end
wire [23:0] rx_I;
wire [23:0] rx_Q;
wire strobe;
receiver receiver_inst(
.clock(C122_clk),
.rate({C122_DFS1, C122_DFS0}),
.frequency(C122_sync_phase_word),
.out_strobe(strobe),
.in_data(temp_ADC),
.out_data_I(rx_I),
.out_data_Q(rx_Q)
);
NWire_xmit #(.SEND_FREQ(192000), .DATA_BITS(48), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .LOW_TIME(1'b0))
M_IQ (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata({rx_I,rx_Q}), .xreq(strobe), .xrdy(), .xack(), .dout(MDOUT));
wire [15:0] spd_data;
wire spd_req, spd_rdy, spd_ack;
wire spf_wreq, spf_rreq, spf_full, spf_empty;
wire trigger;
assign trigger = C21;
NWire_xmit #(.SEND_FREQ(48000), .DATA_BITS(16), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000))
SPD (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(spd_data), .xreq(spd_req), .xrdy(spd_rdy), .xack(spd_ack), .dout(A12));
SP_fifo SPF (.sclr(C122_rst), .clock (C122_clk), .full(spf_full), .empty(spf_empty),
.wrreq (spf_wreq), .data (temp_ADC), .rdreq (spf_rreq), .q(spd_data) );
sp_xmit_ctrl
SPC (.rst(C122_rst), .clk(C122_clk), .trigger(trigger), .fifo_full(spf_full),
.fifo_empty(spf_empty), .fifo_wreq(spf_wreq), .fifo_rreq(spf_rreq),
.xfer_req(spd_req), .xfer_rdy(spd_rdy), .xfer_ack(spd_ack) );
wire [8:0] xmit_data;
assign xmit_data = {SERIAL,OVERFLOW};
NWire_xmit #(.DATA_BITS(9), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SEND_FREQ(1000))
ser_no (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(xmit_data), .xreq(1'b1), .xrdy(), .xack(), .dout(A6));
wire [83:0] C122_rcv_data;
wire C122_rcv_rdy;
reg C122_PTT_out;
reg [3:0] clock_select;
reg [1:0] C122_ATTEN;
reg [1:0] C122_TX_relay;
reg C122_Rout;
reg [1:0] C122_RX_relay;
reg C122_new_data;
reg [14:0] C122_Alex;
reg Alex_manual;
reg Alex_6m_preamp;
reg [6:0] Alex_manual_LPF;
reg [5:0] Alex_manual_HPF;
localparam MERCURY_ADDR = 4'b1;
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
C122_new_data <= 1'b0;
C122_DFS1 <= 1'b0;
C122_DFS0 <= 1'b0;
C122_PTT_out <= 1'b0;
C122_frequency_HZ <= 32'b0;
clock_select <= 4'b0000;
ATTRLY <= 1'b0;
DITHER <= 1'b0;
RAND <= 1'b0;
C122_ATTEN <= 2'b00;
C122_TX_relay <= 2'b00;
C122_Rout <= 1'b0;
C122_RX_relay <= 2'b00;
Alex_manual <= 1'b0;
Alex_6m_preamp <= 1'b0;
Alex_manual_LPF <= 7'b0;
Alex_manual_HPF <= 6'b0;
end
else if (C122_rcv_rdy)
begin
C122_new_data <= 1'b1;
C122_DFS1 <= C122_rcv_data[83];
C122_DFS0 <= C122_rcv_data[82];
C122_PTT_out <= C122_rcv_data[81];
if (C122_rcv_data[80:77] == MERCURY_ADDR)
begin
C122_frequency_HZ <= C122_rcv_data[76:45];
clock_select <= C122_rcv_data[44:41];
ATTRLY <= ~C122_rcv_data[32];
DITHER <= C122_rcv_data[31];
RAND <= C122_rcv_data[30];
C122_ATTEN <= C122_rcv_data[29:28];
C122_TX_relay <= C122_rcv_data[27:26];
C122_Rout <= C122_rcv_data[25];
C122_RX_relay <= C122_rcv_data[24:23];
Alex_manual <= C122_rcv_data[22];
Alex_manual_LPF <= C122_rcv_data[21:15];
Alex_6m_preamp <= C122_rcv_data[14];
Alex_manual_HPF <= C122_rcv_data[13:8];
end
end
else
C122_new_data <= 1'b0;
end
NWire_rcv #(.DATA_BITS(84), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
CCrcv (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_data(C122_rcv_data), .xrcv_rdy(C122_rcv_rdy), .xrcv_ack(C122_rcv_rdy), .din(CC));
assign ref_ext = clock_select[1];
assign source_122MHZ = (clock_select[3:2] == 2'b01);
wire [6:0] C122_LPF;
wire [6:0] C122_LPF_auto;
wire [5:0] C122_select_HPF;
wire [5:0] C122_select_HPF_auto;
LPF_select Alex_LPF_select(.clock(C122_clk), .frequency(C122_frequency_HZ), .LPF(C122_LPF_auto));
HPF_select Alex_HPF_select(.clock(C122_clk), .frequency(C122_frequency_HZ), .HPF(C122_select_HPF_auto));
assign C122_LPF = Alex_manual ? Alex_manual_LPF : C122_LPF_auto;
assign C122_select_HPF = Alex_manual ? Alex_manual_HPF : C122_select_HPF_auto;
wire C122_ANT1;
wire C122_ANT2;
wire C122_ANT3;
wire C122_Rx_1_out;
wire C122_Transverter;
wire C122_Rx_2_in;
wire C122_Rx_1_in;
assign C122_Rx_1_out = C122_Rout;
assign C122_ANT1 = (C122_TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign C122_ANT2 = (C122_TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_ANT3 = (C122_TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Rx_1_in = (C122_RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_Rx_2_in = (C122_RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Transverter = (C122_RX_relay == 2'b11) ? 1'b1 : 1'b0;
localparam TX_YELLOW_LED = 1'b1;
localparam RX_YELLOW_LED = 1'b1;
wire C122_6m_preamp;
wire C122_Tx_red_led;
wire C122_Rx_red_led;
wire C122_TR_relay;
wire [15:0] C122_Alex_Tx_data;
wire [15:0] C122_Alex_Rx_data;
wire C122_10dB_atten = C122_ATTEN[0];
wire C122_20dB_atten = C122_ATTEN[1];
assign C122_Tx_red_led = ~C122_PTT_out;
assign C122_TR_relay = C122_PTT_out;
assign C122_Alex_Tx_data = {C122_LPF[6:4], C122_Tx_red_led, C122_TR_relay, C122_ANT3, C122_ANT2,
C122_ANT1, C122_LPF[3:0], TX_YELLOW_LED, 3'b000};
assign C122_Rx_red_led = C122_PTT_out;
assign C122_6m_preamp = (C122_frequency_HZ > 50000000 && Alex_manual == 1'b0) ? 1'b1 : Alex_6m_preamp;
wire [5:0] C122_HPF;
assign C122_HPF = C122_6m_preamp ? 6'd0 : C122_select_HPF;
assign C122_Alex_Rx_data = {C122_Rx_red_led, C122_10dB_atten, C122_20dB_atten, C122_HPF[5],
C122_Rx_1_out, C122_Rx_1_in, C122_Rx_2_in, C122_Transverter, 1'b0,
C122_HPF[4:2], C122_6m_preamp, C122_HPF[1:0], RX_YELLOW_LED};
wire [31:0] C122_Alex_data;
reg [31:0] SPI_Alex_data;
assign C122_Alex_data = {C122_Alex_Tx_data[15:0], C122_Alex_Rx_data[15:0]};
reg C122_Alex_req;
reg SPI_Alex_ack;
always @ (posedge C122_clk)
begin: C122_ALEX_HANDSHAKE
reg ack;
reg C122_Alex_ack;
if (C122_rst)
C122_Alex_req <= 1'b0;
else if (C122_new_data)
C122_Alex_req <= 1'b1;
else if (C122_Alex_ack)
C122_Alex_req <= 1'b0;
if (C122_rst)
{C122_Alex_ack, ack} <= 2'b00;
else
{C122_Alex_ack, ack} <= {ack, SPI_Alex_ack};
end
always @ (posedge SPI_clk)
begin: SPI_ALEX_HANDSHAKE
reg a2, a1, a0;
reg [31:0] ad0, ad1;
{ad1, ad0} <= {ad0, C122_Alex_data};
{a2, SPI_Alex_ack, a1, a0} <= {SPI_Alex_ack, a1, a0, C122_Alex_req};
if (SPI_Alex_ack & !a2)
SPI_Alex_data <= ad1;
end
SPI Alex_SPI_Tx (.Alex_data(SPI_Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe), .spi_clock(SPI_clk));
wire ref_80khz;
wire osc_80khz;
wire exc_80khz;
wire ref_clock;
wire C10_locked;
wire C122_locked;
oddClockDivider refClockDivider(reference, ref_80khz);
C10_PLL PLL2_inst (.inclk0(AUX_CLK), .c0(exc_80khz), .locked(C10_locked));
C122_PLL PLL_inst (.inclk0(C122_clk), .c0(osc_80khz), .locked(C122_locked));
assign ref_clock = C10_locked ? exc_80khz : ref_80khz;
assign FPGA_PLL = ref_clock ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED3 = C122_locked;
assign DEBUG_LED4 = C10_locked;
assign DEBUG_LED5 = 1'b0;
assign DEBUG_LED6 = 1'b0;
assign DEBUG_LED7 = 1'b0;
assign TEST0 = osc_80khz;
assign TEST1 = ref_clock;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
reg [26:0]counter;
always @(posedge C122_clk) counter = counter + 1'b1;
assign {DEBUG_LED2,DEBUG_LED1} = counter[24:23];
endmodule | module Mercury(OSC_10MHZ, ext_10MHZ,AUX_CLK, C122_clk,INA,CC,ATTRLY,A6,A12,C21,C23,C24,MDOUT,CDIN,TLV320_BCLK,TLV320_LRCIN,
TLV320_LRCOUT,TLV320_MCLK,CMODE,MOSI,SCLK,nCS,SPI_data,SPI_clock,Tx_load_strobe,Rx_load_strobe,
FPGA_PLL,LVDS_TXE,LVDS_RXE_N,OVERFLOW,DITHER,SHDN,PGA,RAND,INIT_DONE,TEST0,TEST1,TEST2,TEST3,
DEBUG_LED0,DEBUG_LED1,DEBUG_LED2,DEBUG_LED3,DEBUG_LED4,DEBUG_LED5,DEBUG_LED6,DEBUG_LED7 ); |
input wire OSC_10MHZ;
inout tri ext_10MHZ;
input wire AUX_CLK;
input wire C122_clk;
input wire [15:0] INA;
input wire CC;
output reg ATTRLY;
output wire A6;
output wire A12;
input wire C21;
output wire C23;
input wire C24;
output wire MDOUT;
output wire CDIN;
output wire TLV320_BCLK;
output wire TLV320_LRCIN;
output wire TLV320_LRCOUT;
output wire TLV320_MCLK;
output wire CMODE;
output reg MOSI;
output reg SCLK;
output reg nCS;
output wire SPI_data;
output wire SPI_clock;
output wire Tx_load_strobe;
output wire Rx_load_strobe;
output wire FPGA_PLL;
output wire LVDS_TXE;
output wire LVDS_RXE_N;
input wire OVERFLOW;
output reg DITHER;
output wire SHDN;
output wire PGA;
output reg RAND;
output wire INIT_DONE;
output wire TEST0;
output wire TEST1;
output wire TEST2;
output wire TEST3;
output wire DEBUG_LED0;
output wire DEBUG_LED1;
output wire DEBUG_LED2;
output wire DEBUG_LED3;
output wire DEBUG_LED4;
output wire DEBUG_LED5;
output wire DEBUG_LED6;
output wire DEBUG_LED7;
parameter C122_TPD = 2.1;
localparam SERIAL = 8'd30;
reg [15:0] temp_ADC;
reg data_ready;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
assign PGA = 1'b0;
reg C122_rst;
reg [10:0] C122_rst_cnt;
always @(posedge C122_clk)
begin
if (!C122_rst_cnt[10])
C122_rst_cnt <= #C122_TPD C122_rst_cnt + 1'b1;
C122_rst <= #C122_TPD C122_rst_cnt[10] ? 1'b0 : 1'b1;
end
always @ (posedge C122_clk)
begin
if (RAND)
begin
if (INA[0])
temp_ADC <= {~INA[15:1],INA[0]};
else
temp_ADC <= INA;
end
else
temp_ADC <= INA;
end
reg [2:0] load;
reg [3:0] TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @*
begin
case (load)
3'd0: TLV_data = 16'h1E00;
3'd1: TLV_data = 16'h1201;
3'd2: TLV_data = 16'h0814;
3'd3: TLV_data = 16'h0C00;
3'd4: TLV_data = 16'h0E02;
3'd5: TLV_data = 16'h1000;
3'd6: TLV_data = 16'h0A00;
default: TLV_data = 0;
endcase
end
assign CMODE = 1'b1;
reg [23:0] tlv_timeout;
always @ (posedge BCLK)
begin
if (tlv_timeout != (200*12288))
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
if (tlv_timeout == (200*12288))
TLV <= 4'd1;
else
TLV <= 4'd0;
end
4'd1:
begin
nCS <= 1'b0;
MOSI <= TLV_data[bit_cnt];
TLV <= 4'd2;
end
4'd2:
begin
SCLK <= 1'b1;
TLV <= 4'd3;
end
4'd3:
begin
SCLK <= 1'b0;
TLV <= 4'd4;
end
4'd4:
begin
if (bit_cnt == 0)
TLV <= 4'd5;
else
begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1;
end
end
4'd5:
begin
if (load == 6)
begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else
begin
TLV <= 4'd0;
load <= load + 3'b1;
end
end
default: TLV <= 4'd0;
endcase
end
localparam SPEED_48K = 2'b00;
reg C122_DFS1, C122_DFS0;
wire C122_cbrise, C122_cbfall;
wire source_122MHZ;
reg C122_cgen_rst;
reg [1:0] C122_SPEED;
clk_div TLVCLK (.reset(C122_rst), .clk_in(C122_clk), .clk_out(TLV320_MCLK));
always @(posedge C122_clk)
begin
if (C122_rst)
C122_SPEED <= 2'b00;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_SPEED <= {C122_DFS1,C122_DFS0};
if (C122_rst)
C122_cgen_rst <= 1'b1;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_cgen_rst <= 1'b1;
else
C122_cgen_rst <= 1'b0;
end
wire C122_cbclk, CLRCLK;
clk_lrclk_gen clrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(C122_cbclk),
.Brise(C122_cbrise), .Bfall(C122_cbfall), .LRCLK(CLRCLK), .Speed(SPEED_48K));
assign TLV320_BCLK = C122_cbclk;
assign TLV320_LRCIN = CLRCLK;
assign TLV320_LRCOUT = CLRCLK;
wire BCLK;
clk_lrclk_gen lrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(BCLK), .Speed(C122_SPEED));
wire SPI_clk;
reg [1:0] spc;
always @(posedge C122_cbclk)
begin
if (C122_rst)
spc <= 2'b00;
else spc <= spc + 2'b01;
end
assign SPI_clk = spc[1];
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
wire reference;
wire ref_ext;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bz;
wire C122_LR_rdy;
wire [31:0] C122_LR_data;
NWire_rcv #(.DATA_BITS(32), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
LRAudio (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_rdy(C122_LR_rdy), .xrcv_ack(C122_LR_rdy), .xrcv_data(C122_LR_data),
.din(C24));
TestModeChecker tmc (C122_rst, C122_clk, C122_LR_data, C122_LR_rdy);
assign C23 = CLRCLK;
I2S_xmit #(.DATA_BITS(32))
LR (.rst(C122_rst), .lrclk(CLRCLK), .clk(C122_clk), .CBrise(C122_cbrise),
.CBfall(C122_cbfall), .sample(C122_LR_data), .outbit(CDIN));
reg [31:0] C122_frequency_HZ;
reg [31:0] C122_last_freq;
reg [31:0] C122_sync_phase_word;
wire [63:0] C122_ratio;
localparam M2 = 32'd1172812403;
assign C122_ratio = C122_frequency_HZ * M2;
always @ (posedge C122_clk)
begin
if (C122_cbrise)
begin
C122_last_freq <= C122_frequency_HZ;
if (C122_last_freq != C122_frequency_HZ)
C122_sync_phase_word <= C122_ratio[56:25];
end
end
wire [23:0] rx_I;
wire [23:0] rx_Q;
wire strobe;
receiver receiver_inst(
.clock(C122_clk),
.rate({C122_DFS1, C122_DFS0}),
.frequency(C122_sync_phase_word),
.out_strobe(strobe),
.in_data(temp_ADC),
.out_data_I(rx_I),
.out_data_Q(rx_Q)
);
NWire_xmit #(.SEND_FREQ(192000), .DATA_BITS(48), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .LOW_TIME(1'b0))
M_IQ (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata({rx_I,rx_Q}), .xreq(strobe), .xrdy(), .xack(), .dout(MDOUT));
wire [15:0] spd_data;
wire spd_req, spd_rdy, spd_ack;
wire spf_wreq, spf_rreq, spf_full, spf_empty;
wire trigger;
assign trigger = C21;
NWire_xmit #(.SEND_FREQ(48000), .DATA_BITS(16), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000))
SPD (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(spd_data), .xreq(spd_req), .xrdy(spd_rdy), .xack(spd_ack), .dout(A12));
SP_fifo SPF (.sclr(C122_rst), .clock (C122_clk), .full(spf_full), .empty(spf_empty),
.wrreq (spf_wreq), .data (temp_ADC), .rdreq (spf_rreq), .q(spd_data) );
sp_xmit_ctrl
SPC (.rst(C122_rst), .clk(C122_clk), .trigger(trigger), .fifo_full(spf_full),
.fifo_empty(spf_empty), .fifo_wreq(spf_wreq), .fifo_rreq(spf_rreq),
.xfer_req(spd_req), .xfer_rdy(spd_rdy), .xfer_ack(spd_ack) );
wire [8:0] xmit_data;
assign xmit_data = {SERIAL,OVERFLOW};
NWire_xmit #(.DATA_BITS(9), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SEND_FREQ(1000))
ser_no (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(xmit_data), .xreq(1'b1), .xrdy(), .xack(), .dout(A6));
wire [83:0] C122_rcv_data;
wire C122_rcv_rdy;
reg C122_PTT_out;
reg [3:0] clock_select;
reg [1:0] C122_ATTEN;
reg [1:0] C122_TX_relay;
reg C122_Rout;
reg [1:0] C122_RX_relay;
reg C122_new_data;
reg [14:0] C122_Alex;
reg Alex_manual;
reg Alex_6m_preamp;
reg [6:0] Alex_manual_LPF;
reg [5:0] Alex_manual_HPF;
localparam MERCURY_ADDR = 4'b1;
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
C122_new_data <= 1'b0;
C122_DFS1 <= 1'b0;
C122_DFS0 <= 1'b0;
C122_PTT_out <= 1'b0;
C122_frequency_HZ <= 32'b0;
clock_select <= 4'b0000;
ATTRLY <= 1'b0;
DITHER <= 1'b0;
RAND <= 1'b0;
C122_ATTEN <= 2'b00;
C122_TX_relay <= 2'b00;
C122_Rout <= 1'b0;
C122_RX_relay <= 2'b00;
Alex_manual <= 1'b0;
Alex_6m_preamp <= 1'b0;
Alex_manual_LPF <= 7'b0;
Alex_manual_HPF <= 6'b0;
end
else if (C122_rcv_rdy)
begin
C122_new_data <= 1'b1;
C122_DFS1 <= C122_rcv_data[83];
C122_DFS0 <= C122_rcv_data[82];
C122_PTT_out <= C122_rcv_data[81];
if (C122_rcv_data[80:77] == MERCURY_ADDR)
begin
C122_frequency_HZ <= C122_rcv_data[76:45];
clock_select <= C122_rcv_data[44:41];
ATTRLY <= ~C122_rcv_data[32];
DITHER <= C122_rcv_data[31];
RAND <= C122_rcv_data[30];
C122_ATTEN <= C122_rcv_data[29:28];
C122_TX_relay <= C122_rcv_data[27:26];
C122_Rout <= C122_rcv_data[25];
C122_RX_relay <= C122_rcv_data[24:23];
Alex_manual <= C122_rcv_data[22];
Alex_manual_LPF <= C122_rcv_data[21:15];
Alex_6m_preamp <= C122_rcv_data[14];
Alex_manual_HPF <= C122_rcv_data[13:8];
end
end
else
C122_new_data <= 1'b0;
end
NWire_rcv #(.DATA_BITS(84), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
CCrcv (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_data(C122_rcv_data), .xrcv_rdy(C122_rcv_rdy), .xrcv_ack(C122_rcv_rdy), .din(CC));
assign ref_ext = clock_select[1];
assign source_122MHZ = (clock_select[3:2] == 2'b01);
wire [6:0] C122_LPF;
wire [6:0] C122_LPF_auto;
wire [5:0] C122_select_HPF;
wire [5:0] C122_select_HPF_auto;
LPF_select Alex_LPF_select(.clock(C122_clk), .frequency(C122_frequency_HZ), .LPF(C122_LPF_auto));
HPF_select Alex_HPF_select(.clock(C122_clk), .frequency(C122_frequency_HZ), .HPF(C122_select_HPF_auto));
assign C122_LPF = Alex_manual ? Alex_manual_LPF : C122_LPF_auto;
assign C122_select_HPF = Alex_manual ? Alex_manual_HPF : C122_select_HPF_auto;
wire C122_ANT1;
wire C122_ANT2;
wire C122_ANT3;
wire C122_Rx_1_out;
wire C122_Transverter;
wire C122_Rx_2_in;
wire C122_Rx_1_in;
assign C122_Rx_1_out = C122_Rout;
assign C122_ANT1 = (C122_TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign C122_ANT2 = (C122_TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_ANT3 = (C122_TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Rx_1_in = (C122_RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_Rx_2_in = (C122_RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Transverter = (C122_RX_relay == 2'b11) ? 1'b1 : 1'b0;
localparam TX_YELLOW_LED = 1'b1;
localparam RX_YELLOW_LED = 1'b1;
wire C122_6m_preamp;
wire C122_Tx_red_led;
wire C122_Rx_red_led;
wire C122_TR_relay;
wire [15:0] C122_Alex_Tx_data;
wire [15:0] C122_Alex_Rx_data;
wire C122_10dB_atten = C122_ATTEN[0];
wire C122_20dB_atten = C122_ATTEN[1];
assign C122_Tx_red_led = ~C122_PTT_out;
assign C122_TR_relay = C122_PTT_out;
assign C122_Alex_Tx_data = {C122_LPF[6:4], C122_Tx_red_led, C122_TR_relay, C122_ANT3, C122_ANT2,
C122_ANT1, C122_LPF[3:0], TX_YELLOW_LED, 3'b000};
assign C122_Rx_red_led = C122_PTT_out;
assign C122_6m_preamp = (C122_frequency_HZ > 50000000 && Alex_manual == 1'b0) ? 1'b1 : Alex_6m_preamp;
wire [5:0] C122_HPF;
assign C122_HPF = C122_6m_preamp ? 6'd0 : C122_select_HPF;
assign C122_Alex_Rx_data = {C122_Rx_red_led, C122_10dB_atten, C122_20dB_atten, C122_HPF[5],
C122_Rx_1_out, C122_Rx_1_in, C122_Rx_2_in, C122_Transverter, 1'b0,
C122_HPF[4:2], C122_6m_preamp, C122_HPF[1:0], RX_YELLOW_LED};
wire [31:0] C122_Alex_data;
reg [31:0] SPI_Alex_data;
assign C122_Alex_data = {C122_Alex_Tx_data[15:0], C122_Alex_Rx_data[15:0]};
reg C122_Alex_req;
reg SPI_Alex_ack;
always @ (posedge C122_clk)
begin: C122_ALEX_HANDSHAKE
reg ack;
reg C122_Alex_ack;
if (C122_rst)
C122_Alex_req <= 1'b0;
else if (C122_new_data)
C122_Alex_req <= 1'b1;
else if (C122_Alex_ack)
C122_Alex_req <= 1'b0;
if (C122_rst)
{C122_Alex_ack, ack} <= 2'b00;
else
{C122_Alex_ack, ack} <= {ack, SPI_Alex_ack};
end
always @ (posedge SPI_clk)
begin: SPI_ALEX_HANDSHAKE
reg a2, a1, a0;
reg [31:0] ad0, ad1;
{ad1, ad0} <= {ad0, C122_Alex_data};
{a2, SPI_Alex_ack, a1, a0} <= {SPI_Alex_ack, a1, a0, C122_Alex_req};
if (SPI_Alex_ack & !a2)
SPI_Alex_data <= ad1;
end
SPI Alex_SPI_Tx (.Alex_data(SPI_Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe), .spi_clock(SPI_clk));
wire ref_80khz;
wire osc_80khz;
wire exc_80khz;
wire ref_clock;
wire C10_locked;
wire C122_locked;
oddClockDivider refClockDivider(reference, ref_80khz);
C10_PLL PLL2_inst (.inclk0(AUX_CLK), .c0(exc_80khz), .locked(C10_locked));
C122_PLL PLL_inst (.inclk0(C122_clk), .c0(osc_80khz), .locked(C122_locked));
assign ref_clock = C10_locked ? exc_80khz : ref_80khz;
assign FPGA_PLL = ref_clock ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED3 = C122_locked;
assign DEBUG_LED4 = C10_locked;
assign DEBUG_LED5 = 1'b0;
assign DEBUG_LED6 = 1'b0;
assign DEBUG_LED7 = 1'b0;
assign TEST0 = osc_80khz;
assign TEST1 = ref_clock;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
reg [26:0]counter;
always @(posedge C122_clk) counter = counter + 1'b1;
assign {DEBUG_LED2,DEBUG_LED1} = counter[24:23];
endmodule | 17 |
138,840 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury_V1/cROM.v | 86,169,941 | cROM.v | v | 284 | 41 | [] | [] | [] | [(8, 283)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1/cROM.v\n%Error: Exiting due to 3 error(s)\n' | 303,029 | module | module cROM(clk, addr, data, reset);
input clk;
input [7:0] addr;
input reset;
output signed [23:0] data;
reg [23:0] data;
always @(posedge clk) begin
if (reset)
data <= 0;
else begin
case(addr)
8'd0: data <= 24'shFFFFA0;
8'd1: data <= 24'shFFFE8E;
8'd2: data <= 24'shFFFD67;
8'd3: data <= 24'shFFFE01;
8'd4: data <= 24'sh000191;
8'd5: data <= 24'sh000626;
8'd6: data <= 24'sh000772;
8'd7: data <= 24'sh0003A8;
8'd8: data <= 24'shFFFEBF;
8'd9: data <= 24'shFFFE6B;
8'd10: data <= 24'sh00028B;
8'd11: data <= 24'sh0004A5;
8'd12: data <= 24'sh0000D2;
8'd13: data <= 24'shFFFC21;
8'd14: data <= 24'shFFFDD4;
8'd15: data <= 24'sh0003F0;
8'd16: data <= 24'sh0004EF;
8'd17: data <= 24'shFFFE2D;
8'd18: data <= 24'shFFF989;
8'd19: data <= 24'shFFFF17;
8'd20: data <= 24'sh000743;
8'd21: data <= 24'sh0004BF;
8'd22: data <= 24'shFFF9E5;
8'd23: data <= 24'shFFF786;
8'd24: data <= 24'sh00030D;
8'd25: data <= 24'sh000B62;
8'd26: data <= 24'sh0001F2;
8'd27: data <= 24'shFFF3BB;
8'd28: data <= 24'shFFF7EB;
8'd29: data <= 24'sh000A5F;
8'd30: data <= 24'sh000E3C;
8'd31: data <= 24'shFFFABD;
8'd32: data <= 24'shFFED2B;
8'd33: data <= 24'shFFFD46;
8'd34: data <= 24'sh001452;
8'd35: data <= 24'sh000C84;
8'd36: data <= 24'shFFEE8E;
8'd37: data <= 24'shFFE9B9;
8'd38: data <= 24'sh0009AB;
8'd39: data <= 24'sh001DBB;
8'd40: data <= 24'sh00028C;
8'd41: data <= 24'shFFDF79;
8'd42: data <= 24'shFFEE6B;
8'd43: data <= 24'sh001CD2;
8'd44: data <= 24'sh0020CA;
8'd45: data <= 24'shFFEE3C;
8'd46: data <= 24'shFFD32D;
8'd47: data <= 24'shFFFFF5;
8'd48: data <= 24'sh003245;
8'd49: data <= 24'sh001660;
8'd50: data <= 24'shFFD1AA;
8'd51: data <= 24'shFFD280;
8'd52: data <= 24'sh001FA5;
8'd53: data <= 24'sh0040AD;
8'd54: data <= 24'shFFF930;
8'd55: data <= 24'shFFB50D;
8'd56: data <= 24'shFFE6BB;
8'd57: data <= 24'sh004829;
8'd58: data <= 24'sh003B89;
8'd59: data <= 24'shFFC9FF;
8'd60: data <= 24'shFFA695;
8'd61: data <= 24'sh0014DC;
8'd62: data <= 24'sh006BDD;
8'd63: data <= 24'sh0017BA;
8'd64: data <= 24'shFF9349;
8'd65: data <= 24'shFFB6D8;
8'd66: data <= 24'sh005826;
8'd67: data <= 24'sh00768A;
8'd68: data <= 24'shFFD21F;
8'd69: data <= 24'shFF69F9;
8'd70: data <= 24'shFFF1E3;
8'd71: data <= 24'sh009E9E;
8'd72: data <= 24'sh00538A;
8'd73: data <= 24'shFF75E6;
8'd74: data <= 24'shFF694C;
8'd75: data <= 24'sh0056C5;
8'd76: data <= 24'sh00CA19;
8'd77: data <= 24'shFFF767;
8'd78: data <= 24'shFF1F3D;
8'd79: data <= 24'shFFA97D;
8'd80: data <= 24'sh00D0D6;
8'd81: data <= 24'sh00B794;
8'd82: data <= 24'shFF69FE;
8'd83: data <= 24'shFEF78A;
8'd84: data <= 24'sh003352;
8'd85: data <= 24'sh0136C1;
8'd86: data <= 24'sh004C1D;
8'd87: data <= 24'shFECCDA;
8'd88: data <= 24'shFF2A3E;
8'd89: data <= 24'sh00F4CF;
8'd90: data <= 24'sh0151BD;
8'd91: data <= 24'shFF83D8;
8'd92: data <= 24'shFE59BB;
8'd93: data <= 24'shFFD45F;
8'd94: data <= 24'sh01BBED;
8'd95: data <= 24'sh00ECA6;
8'd96: data <= 24'shFE7DC4;
8'd97: data <= 24'shFE57C0;
8'd98: data <= 24'sh00F3C5;
8'd99: data <= 24'sh023AC4;
8'd100: data <= 24'shFFE6EB;
8'd101: data <= 24'shFD7F66;
8'd102: data <= 24'shFF09CE;
8'd103: data <= 24'sh025C25;
8'd104: data <= 24'sh021460;
8'd105: data <= 24'shFE446F;
8'd106: data <= 24'shFCEEFF;
8'd107: data <= 24'sh009DC1;
8'd108: data <= 24'sh03B5FD;
8'd109: data <= 24'sh00EA73;
8'd110: data <= 24'shFC3219;
8'd111: data <= 24'shFD4B14;
8'd112: data <= 24'sh032A8A;
8'd113: data <= 24'sh0484FC;
8'd114: data <= 24'shFE558D;
8'd115: data <= 24'shF9F501;
8'd116: data <= 24'shFF3C21;
8'd117: data <= 24'sh06E434;
8'd118: data <= 24'sh042271;
8'd119: data <= 24'shF96DD0;
8'd120: data <= 24'shF796AE;
8'd121: data <= 24'sh04561A;
8'd122: data <= 24'sh0D9048;
8'd123: data <= 24'sh015BFC;
8'd124: data <= 24'shEC8390;
8'd125: data <= 24'shF09DC6;
8'd126: data <= 24'sh17C6D6;
8'd127: data <= 24'sh403E65;
8'd128: data <= 24'sh403E65;
8'd129: data <= 24'sh17C6D6;
8'd130: data <= 24'shF09DC6;
8'd131: data <= 24'shEC8390;
8'd132: data <= 24'sh015BFC;
8'd133: data <= 24'sh0D9048;
8'd134: data <= 24'sh04561A;
8'd135: data <= 24'shF796AE;
8'd136: data <= 24'shF96DD0;
8'd137: data <= 24'sh042271;
8'd138: data <= 24'sh06E434;
8'd139: data <= 24'shFF3C21;
8'd140: data <= 24'shF9F501;
8'd141: data <= 24'shFE558D;
8'd142: data <= 24'sh0484FC;
8'd143: data <= 24'sh032A8A;
8'd144: data <= 24'shFD4B14;
8'd145: data <= 24'shFC3219;
8'd146: data <= 24'sh00EA73;
8'd147: data <= 24'sh03B5FD;
8'd148: data <= 24'sh009DC1;
8'd149: data <= 24'shFCEEFF;
8'd150: data <= 24'shFE446F;
8'd151: data <= 24'sh021460;
8'd152: data <= 24'sh025C25;
8'd153: data <= 24'shFF09CE;
8'd154: data <= 24'shFD7F66;
8'd155: data <= 24'shFFE6EB;
8'd156: data <= 24'sh023AC4;
8'd157: data <= 24'sh00F3C5;
8'd158: data <= 24'shFE57C0;
8'd159: data <= 24'shFE7DC4;
8'd160: data <= 24'sh00ECA6;
8'd161: data <= 24'sh01BBED;
8'd162: data <= 24'shFFD45F;
8'd163: data <= 24'shFE59BB;
8'd164: data <= 24'shFF83D8;
8'd165: data <= 24'sh0151BD;
8'd166: data <= 24'sh00F4CF;
8'd167: data <= 24'shFF2A3E;
8'd168: data <= 24'shFECCDA;
8'd169: data <= 24'sh004C1D;
8'd170: data <= 24'sh0136C1;
8'd171: data <= 24'sh003352;
8'd172: data <= 24'shFEF78A;
8'd173: data <= 24'shFF69FE;
8'd174: data <= 24'sh00B794;
8'd175: data <= 24'sh00D0D6;
8'd176: data <= 24'shFFA97D;
8'd177: data <= 24'shFF1F3D;
8'd178: data <= 24'shFFF767;
8'd179: data <= 24'sh00CA19;
8'd180: data <= 24'sh0056C5;
8'd181: data <= 24'shFF694C;
8'd182: data <= 24'shFF75E6;
8'd183: data <= 24'sh00538A;
8'd184: data <= 24'sh009E9E;
8'd185: data <= 24'shFFF1E3;
8'd186: data <= 24'shFF69F9;
8'd187: data <= 24'shFFD21F;
8'd188: data <= 24'sh00768A;
8'd189: data <= 24'sh005826;
8'd190: data <= 24'shFFB6D8;
8'd191: data <= 24'shFF9349;
8'd192: data <= 24'sh0017BA;
8'd193: data <= 24'sh006BDD;
8'd194: data <= 24'sh0014DC;
8'd195: data <= 24'shFFA695;
8'd196: data <= 24'shFFC9FF;
8'd197: data <= 24'sh003B89;
8'd198: data <= 24'sh004829;
8'd199: data <= 24'shFFE6BB;
8'd200: data <= 24'shFFB50D;
8'd201: data <= 24'shFFF930;
8'd202: data <= 24'sh0040AD;
8'd203: data <= 24'sh001FA5;
8'd204: data <= 24'shFFD280;
8'd205: data <= 24'shFFD1AA;
8'd206: data <= 24'sh001660;
8'd207: data <= 24'sh003245;
8'd208: data <= 24'shFFFFF5;
8'd209: data <= 24'shFFD32D;
8'd210: data <= 24'shFFEE3C;
8'd211: data <= 24'sh0020CA;
8'd212: data <= 24'sh001CD2;
8'd213: data <= 24'shFFEE6B;
8'd214: data <= 24'shFFDF79;
8'd215: data <= 24'sh00028C;
8'd216: data <= 24'sh001DBB;
8'd217: data <= 24'sh0009AB;
8'd218: data <= 24'shFFE9B9;
8'd219: data <= 24'shFFEE8E;
8'd220: data <= 24'sh000C84;
8'd221: data <= 24'sh001452;
8'd222: data <= 24'shFFFD46;
8'd223: data <= 24'shFFED2B;
8'd224: data <= 24'shFFFABD;
8'd225: data <= 24'sh000E3C;
8'd226: data <= 24'sh000A5F;
8'd227: data <= 24'shFFF7EB;
8'd228: data <= 24'shFFF3BB;
8'd229: data <= 24'sh0001F2;
8'd230: data <= 24'sh000B62;
8'd231: data <= 24'sh00030D;
8'd232: data <= 24'shFFF786;
8'd233: data <= 24'shFFF9E5;
8'd234: data <= 24'sh0004BF;
8'd235: data <= 24'sh000743;
8'd236: data <= 24'shFFFF17;
8'd237: data <= 24'shFFF989;
8'd238: data <= 24'shFFFE2D;
8'd239: data <= 24'sh0004EF;
8'd240: data <= 24'sh0003F0;
8'd241: data <= 24'shFFFDD4;
8'd242: data <= 24'shFFFC21;
8'd243: data <= 24'sh0000D2;
8'd244: data <= 24'sh0004A5;
8'd245: data <= 24'sh00028B;
8'd246: data <= 24'shFFFE6B;
8'd247: data <= 24'shFFFEBF;
8'd248: data <= 24'sh0003A8;
8'd249: data <= 24'sh000772;
8'd250: data <= 24'sh000626;
8'd251: data <= 24'sh000191;
8'd252: data <= 24'shFFFE01;
8'd253: data <= 24'shFFFD67;
8'd254: data <= 24'shFFFE8E;
8'd255: data <= 24'shFFFFA0;
default: data <= 24'sh0;
endcase
end
end
endmodule | module cROM(clk, addr, data, reset); |
input clk;
input [7:0] addr;
input reset;
output signed [23:0] data;
reg [23:0] data;
always @(posedge clk) begin
if (reset)
data <= 0;
else begin
case(addr)
8'd0: data <= 24'shFFFFA0;
8'd1: data <= 24'shFFFE8E;
8'd2: data <= 24'shFFFD67;
8'd3: data <= 24'shFFFE01;
8'd4: data <= 24'sh000191;
8'd5: data <= 24'sh000626;
8'd6: data <= 24'sh000772;
8'd7: data <= 24'sh0003A8;
8'd8: data <= 24'shFFFEBF;
8'd9: data <= 24'shFFFE6B;
8'd10: data <= 24'sh00028B;
8'd11: data <= 24'sh0004A5;
8'd12: data <= 24'sh0000D2;
8'd13: data <= 24'shFFFC21;
8'd14: data <= 24'shFFFDD4;
8'd15: data <= 24'sh0003F0;
8'd16: data <= 24'sh0004EF;
8'd17: data <= 24'shFFFE2D;
8'd18: data <= 24'shFFF989;
8'd19: data <= 24'shFFFF17;
8'd20: data <= 24'sh000743;
8'd21: data <= 24'sh0004BF;
8'd22: data <= 24'shFFF9E5;
8'd23: data <= 24'shFFF786;
8'd24: data <= 24'sh00030D;
8'd25: data <= 24'sh000B62;
8'd26: data <= 24'sh0001F2;
8'd27: data <= 24'shFFF3BB;
8'd28: data <= 24'shFFF7EB;
8'd29: data <= 24'sh000A5F;
8'd30: data <= 24'sh000E3C;
8'd31: data <= 24'shFFFABD;
8'd32: data <= 24'shFFED2B;
8'd33: data <= 24'shFFFD46;
8'd34: data <= 24'sh001452;
8'd35: data <= 24'sh000C84;
8'd36: data <= 24'shFFEE8E;
8'd37: data <= 24'shFFE9B9;
8'd38: data <= 24'sh0009AB;
8'd39: data <= 24'sh001DBB;
8'd40: data <= 24'sh00028C;
8'd41: data <= 24'shFFDF79;
8'd42: data <= 24'shFFEE6B;
8'd43: data <= 24'sh001CD2;
8'd44: data <= 24'sh0020CA;
8'd45: data <= 24'shFFEE3C;
8'd46: data <= 24'shFFD32D;
8'd47: data <= 24'shFFFFF5;
8'd48: data <= 24'sh003245;
8'd49: data <= 24'sh001660;
8'd50: data <= 24'shFFD1AA;
8'd51: data <= 24'shFFD280;
8'd52: data <= 24'sh001FA5;
8'd53: data <= 24'sh0040AD;
8'd54: data <= 24'shFFF930;
8'd55: data <= 24'shFFB50D;
8'd56: data <= 24'shFFE6BB;
8'd57: data <= 24'sh004829;
8'd58: data <= 24'sh003B89;
8'd59: data <= 24'shFFC9FF;
8'd60: data <= 24'shFFA695;
8'd61: data <= 24'sh0014DC;
8'd62: data <= 24'sh006BDD;
8'd63: data <= 24'sh0017BA;
8'd64: data <= 24'shFF9349;
8'd65: data <= 24'shFFB6D8;
8'd66: data <= 24'sh005826;
8'd67: data <= 24'sh00768A;
8'd68: data <= 24'shFFD21F;
8'd69: data <= 24'shFF69F9;
8'd70: data <= 24'shFFF1E3;
8'd71: data <= 24'sh009E9E;
8'd72: data <= 24'sh00538A;
8'd73: data <= 24'shFF75E6;
8'd74: data <= 24'shFF694C;
8'd75: data <= 24'sh0056C5;
8'd76: data <= 24'sh00CA19;
8'd77: data <= 24'shFFF767;
8'd78: data <= 24'shFF1F3D;
8'd79: data <= 24'shFFA97D;
8'd80: data <= 24'sh00D0D6;
8'd81: data <= 24'sh00B794;
8'd82: data <= 24'shFF69FE;
8'd83: data <= 24'shFEF78A;
8'd84: data <= 24'sh003352;
8'd85: data <= 24'sh0136C1;
8'd86: data <= 24'sh004C1D;
8'd87: data <= 24'shFECCDA;
8'd88: data <= 24'shFF2A3E;
8'd89: data <= 24'sh00F4CF;
8'd90: data <= 24'sh0151BD;
8'd91: data <= 24'shFF83D8;
8'd92: data <= 24'shFE59BB;
8'd93: data <= 24'shFFD45F;
8'd94: data <= 24'sh01BBED;
8'd95: data <= 24'sh00ECA6;
8'd96: data <= 24'shFE7DC4;
8'd97: data <= 24'shFE57C0;
8'd98: data <= 24'sh00F3C5;
8'd99: data <= 24'sh023AC4;
8'd100: data <= 24'shFFE6EB;
8'd101: data <= 24'shFD7F66;
8'd102: data <= 24'shFF09CE;
8'd103: data <= 24'sh025C25;
8'd104: data <= 24'sh021460;
8'd105: data <= 24'shFE446F;
8'd106: data <= 24'shFCEEFF;
8'd107: data <= 24'sh009DC1;
8'd108: data <= 24'sh03B5FD;
8'd109: data <= 24'sh00EA73;
8'd110: data <= 24'shFC3219;
8'd111: data <= 24'shFD4B14;
8'd112: data <= 24'sh032A8A;
8'd113: data <= 24'sh0484FC;
8'd114: data <= 24'shFE558D;
8'd115: data <= 24'shF9F501;
8'd116: data <= 24'shFF3C21;
8'd117: data <= 24'sh06E434;
8'd118: data <= 24'sh042271;
8'd119: data <= 24'shF96DD0;
8'd120: data <= 24'shF796AE;
8'd121: data <= 24'sh04561A;
8'd122: data <= 24'sh0D9048;
8'd123: data <= 24'sh015BFC;
8'd124: data <= 24'shEC8390;
8'd125: data <= 24'shF09DC6;
8'd126: data <= 24'sh17C6D6;
8'd127: data <= 24'sh403E65;
8'd128: data <= 24'sh403E65;
8'd129: data <= 24'sh17C6D6;
8'd130: data <= 24'shF09DC6;
8'd131: data <= 24'shEC8390;
8'd132: data <= 24'sh015BFC;
8'd133: data <= 24'sh0D9048;
8'd134: data <= 24'sh04561A;
8'd135: data <= 24'shF796AE;
8'd136: data <= 24'shF96DD0;
8'd137: data <= 24'sh042271;
8'd138: data <= 24'sh06E434;
8'd139: data <= 24'shFF3C21;
8'd140: data <= 24'shF9F501;
8'd141: data <= 24'shFE558D;
8'd142: data <= 24'sh0484FC;
8'd143: data <= 24'sh032A8A;
8'd144: data <= 24'shFD4B14;
8'd145: data <= 24'shFC3219;
8'd146: data <= 24'sh00EA73;
8'd147: data <= 24'sh03B5FD;
8'd148: data <= 24'sh009DC1;
8'd149: data <= 24'shFCEEFF;
8'd150: data <= 24'shFE446F;
8'd151: data <= 24'sh021460;
8'd152: data <= 24'sh025C25;
8'd153: data <= 24'shFF09CE;
8'd154: data <= 24'shFD7F66;
8'd155: data <= 24'shFFE6EB;
8'd156: data <= 24'sh023AC4;
8'd157: data <= 24'sh00F3C5;
8'd158: data <= 24'shFE57C0;
8'd159: data <= 24'shFE7DC4;
8'd160: data <= 24'sh00ECA6;
8'd161: data <= 24'sh01BBED;
8'd162: data <= 24'shFFD45F;
8'd163: data <= 24'shFE59BB;
8'd164: data <= 24'shFF83D8;
8'd165: data <= 24'sh0151BD;
8'd166: data <= 24'sh00F4CF;
8'd167: data <= 24'shFF2A3E;
8'd168: data <= 24'shFECCDA;
8'd169: data <= 24'sh004C1D;
8'd170: data <= 24'sh0136C1;
8'd171: data <= 24'sh003352;
8'd172: data <= 24'shFEF78A;
8'd173: data <= 24'shFF69FE;
8'd174: data <= 24'sh00B794;
8'd175: data <= 24'sh00D0D6;
8'd176: data <= 24'shFFA97D;
8'd177: data <= 24'shFF1F3D;
8'd178: data <= 24'shFFF767;
8'd179: data <= 24'sh00CA19;
8'd180: data <= 24'sh0056C5;
8'd181: data <= 24'shFF694C;
8'd182: data <= 24'shFF75E6;
8'd183: data <= 24'sh00538A;
8'd184: data <= 24'sh009E9E;
8'd185: data <= 24'shFFF1E3;
8'd186: data <= 24'shFF69F9;
8'd187: data <= 24'shFFD21F;
8'd188: data <= 24'sh00768A;
8'd189: data <= 24'sh005826;
8'd190: data <= 24'shFFB6D8;
8'd191: data <= 24'shFF9349;
8'd192: data <= 24'sh0017BA;
8'd193: data <= 24'sh006BDD;
8'd194: data <= 24'sh0014DC;
8'd195: data <= 24'shFFA695;
8'd196: data <= 24'shFFC9FF;
8'd197: data <= 24'sh003B89;
8'd198: data <= 24'sh004829;
8'd199: data <= 24'shFFE6BB;
8'd200: data <= 24'shFFB50D;
8'd201: data <= 24'shFFF930;
8'd202: data <= 24'sh0040AD;
8'd203: data <= 24'sh001FA5;
8'd204: data <= 24'shFFD280;
8'd205: data <= 24'shFFD1AA;
8'd206: data <= 24'sh001660;
8'd207: data <= 24'sh003245;
8'd208: data <= 24'shFFFFF5;
8'd209: data <= 24'shFFD32D;
8'd210: data <= 24'shFFEE3C;
8'd211: data <= 24'sh0020CA;
8'd212: data <= 24'sh001CD2;
8'd213: data <= 24'shFFEE6B;
8'd214: data <= 24'shFFDF79;
8'd215: data <= 24'sh00028C;
8'd216: data <= 24'sh001DBB;
8'd217: data <= 24'sh0009AB;
8'd218: data <= 24'shFFE9B9;
8'd219: data <= 24'shFFEE8E;
8'd220: data <= 24'sh000C84;
8'd221: data <= 24'sh001452;
8'd222: data <= 24'shFFFD46;
8'd223: data <= 24'shFFED2B;
8'd224: data <= 24'shFFFABD;
8'd225: data <= 24'sh000E3C;
8'd226: data <= 24'sh000A5F;
8'd227: data <= 24'shFFF7EB;
8'd228: data <= 24'shFFF3BB;
8'd229: data <= 24'sh0001F2;
8'd230: data <= 24'sh000B62;
8'd231: data <= 24'sh00030D;
8'd232: data <= 24'shFFF786;
8'd233: data <= 24'shFFF9E5;
8'd234: data <= 24'sh0004BF;
8'd235: data <= 24'sh000743;
8'd236: data <= 24'shFFFF17;
8'd237: data <= 24'shFFF989;
8'd238: data <= 24'shFFFE2D;
8'd239: data <= 24'sh0004EF;
8'd240: data <= 24'sh0003F0;
8'd241: data <= 24'shFFFDD4;
8'd242: data <= 24'shFFFC21;
8'd243: data <= 24'sh0000D2;
8'd244: data <= 24'sh0004A5;
8'd245: data <= 24'sh00028B;
8'd246: data <= 24'shFFFE6B;
8'd247: data <= 24'shFFFEBF;
8'd248: data <= 24'sh0003A8;
8'd249: data <= 24'sh000772;
8'd250: data <= 24'sh000626;
8'd251: data <= 24'sh000191;
8'd252: data <= 24'shFFFE01;
8'd253: data <= 24'shFFFD67;
8'd254: data <= 24'shFFFE8E;
8'd255: data <= 24'shFFFFA0;
default: data <= 24'sh0;
endcase
end
end
endmodule | 17 |
138,841 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury_V1/cROM_Sequencer.v | 86,169,941 | cROM_Sequencer.v | v | 57 | 66 | [] | [] | [] | [(26, 56)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1/cROM_Sequencer.v\n%Error: Exiting due to 3 error(s)\n' | 303,030 | module | module cROM_Sequencer(clk, reset, data);
input clk;
input reset;
output signed [COEF_WIDTH-1:0] data;
parameter COEF_WIDTH = 24;
parameter TAPS = 256;
parameter MAX_ADR = 8;
reg [MAX_ADR-1:0] sequence_counter;
cROM cROM_inst(
.clk(clk),
.reset(reset),
.addr(sequence_counter),
.data(data)
);
always @(posedge clk) begin
if (reset) begin
sequence_counter <= 0;
end else if (sequence_counter < (TAPS-1)) begin
sequence_counter <= sequence_counter + 1;
end else begin
sequence_counter <= (TAPS-1);
end
end
endmodule | module cROM_Sequencer(clk, reset, data); |
input clk;
input reset;
output signed [COEF_WIDTH-1:0] data;
parameter COEF_WIDTH = 24;
parameter TAPS = 256;
parameter MAX_ADR = 8;
reg [MAX_ADR-1:0] sequence_counter;
cROM cROM_inst(
.clk(clk),
.reset(reset),
.addr(sequence_counter),
.data(data)
);
always @(posedge clk) begin
if (reset) begin
sequence_counter <= 0;
end else if (sequence_counter < (TAPS-1)) begin
sequence_counter <= sequence_counter + 1;
end else begin
sequence_counter <= (TAPS-1);
end
end
endmodule | 17 |
138,842 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury_V1/dc_offset_correct_new.v | 86,169,941 | dc_offset_correct_new.v | v | 55 | 72 | [] | [] | [] | [(22, 51)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1/dc_offset_correct_new.v\n%Error: Exiting due to 3 error(s)\n' | 303,031 | module | module dc_offset_correct_new(
input clk,
input clken,
input signed [23:0] data_in,
output signed [23:0] data_out
);
wire signed [23:0] dc_level = accumulator[34:11];
wire signed [23:0] corrected = data_in[23:0] - dc_level[23:0];
reg signed [34:0] accumulator;
always @(posedge clk) begin
if (clken == 1'b0) begin
accumulator <= 40'd0;
end
else begin
accumulator <= accumulator + {{11{corrected[23]}},corrected[23:0]};
end
end
assign data_out[23:0] = corrected[23:0];
endmodule | module dc_offset_correct_new(
input clk,
input clken,
input signed [23:0] data_in,
output signed [23:0] data_out
); |
wire signed [23:0] dc_level = accumulator[34:11];
wire signed [23:0] corrected = data_in[23:0] - dc_level[23:0];
reg signed [34:0] accumulator;
always @(posedge clk) begin
if (clken == 1'b0) begin
accumulator <= 40'd0;
end
else begin
accumulator <= accumulator + {{11{corrected[23]}},corrected[23:0]};
end
end
assign data_out[23:0] = corrected[23:0];
endmodule | 17 |
138,844 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury_V1/Mercury.v | 86,169,941 | Mercury.v | v | 721 | 183 | [] | ['general public license', 'free software foundation'] | [] | [(66, 717)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1/Mercury.v\n%Error: Exiting due to 3 error(s)\n' | 303,039 | module | module Mercury(
input OSC_10MHZ,
inout ext_10MHZ,
input CLKA,
input [15:0]INA,
input CC,
output reg ATTRLY,
output A6,
input C4,
input C8,
input C9,
input C17,
output MDOUT,
input BCLK,
input LRCLK,
output CDIN,
output CBCLK,
output CLRCLK,
output CLRCOUT,
output CMCLK,
output CMODE,
output reg MOSI,
output reg SCLK,
output reg nCS,
output SPI_data,
output SPI_clock,
output Tx_load_strobe,
output Rx_load_strobe,
output FPGA_PLL,
output LVDS_TXE,
output LVDS_RXE_N,
input OVERFLOW,
output reg DITHER,
output SHDN,
output reg PGA,
output reg RAND,
output INIT_DONE,
output TEST0,
output TEST1,
output TEST2,
output TEST3,
output DEBUG_LED0,
output DEBUG_LED1,
output DEBUG_LED2,
output DEBUG_LED3,
output DEBUG_LED4,
output DEBUG_LED5,
output DEBUG_LED6,
output DEBUG_LED7
);
reg data_ready;
assign CDIN = C4;
assign CLRCLK = C9;
assign CLRCOUT = C9;
assign CBCLK = C8;
assign CMCLK = C17;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
reg clk_enable;
reg [10:0]reset_count;
always @ (posedge clock) begin
if (reset_count[10]) begin
clk_enable <= 1'b1;
end
else begin
clk_enable <= 0;
reset_count <= reset_count + 1'b1;
end
end
always @ (posedge clock)
begin
if (RAND) begin
if (INA[0]) temp_ADC <= {~INA[15:1],INA[0]};
else temp_ADC <= INA;
end
else temp_ADC <= INA;
end
reg index;
reg [15:0]tdata;
reg [2:0]load;
reg [3:0]TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @ (posedge index)
begin
load <= load + 3'b1;
case (load)
3'd0: tdata <= 16'h1E00;
3'd1: tdata <= 16'h1201;
3'd2: tdata <= 16'h0814;
3'd3: tdata <= 16'h0C00;
3'd4: tdata <= 16'h0E02;
3'd5: tdata <= 16'h1000;
3'd6: tdata <= 16'h0A00;
default: load <= 0;
endcase
end
assign CMODE = 1'b1;
always @ (posedge BCLK)
begin
case (TLV)
4'd0: begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
index <= ~index;
TLV <= TLV + 4'b1;
end
4'd1: begin
nCS <= 1'b0;
TLV_data <= tdata;
MOSI <= TLV_data[bit_cnt];
TLV <= TLV + 4'b1;
end
4'd2: begin
SCLK <= 1'b1;
TLV <= TLV + 4'b1;
end
4'd3: begin
SCLK <= 1'b0;
TLV <= TLV + 4'b1;
end
4'd4: begin
if(bit_cnt == 0) begin
index <= ~index;
TLV <= 4'd5;
end
else begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'b1;
end
end
4'd5: begin
if (load == 7)begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else TLV <= 0;
end
default: TLV <= 0;
endcase
end
reg MCLK_12MHZ;
reg [2:0]MCLK_count;
always @ (posedge clock)
begin
if (MCLK_count == 4)
begin
MCLK_12MHZ <= ~MCLK_12MHZ;
MCLK_count <= 0;
end
else MCLK_count <= MCLK_count + 1'b1;
end
reg SPI_clk;
reg SPI_count;
always @(posedge CBCLK)
begin
if(SPI_count == 1)begin
SPI_clk <= ~SPI_clk;
SPI_count <=0;
end
else SPI_count <= SPI_count + 1'b1;
end
wire clock;
assign clock = CLKA;
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
assign A6 = MCLK_12MHZ;
wire reference;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bZ ;
wire [31:0]freq;
wire ready;
always @ (posedge ready)
begin
frequency <= frequency_HZ;
end
division division_DDS(.quotient(freq),.ready(ready),.dividend(frequency),.divider(32'd122880000),.clk(clock));
reg [31:0]sync_frequency;
always @ (posedge clock)
begin
sync_frequency <= freq;
end
wire [17:0]i_out;
wire [17:0]q_out;
reg [15:0]temp_ADC;
wire[31:0] phase;
reg [31:0]frequency;
phase_accumulator rx_phase_accumulator(.clk(~clock),.reset(~clk_enable),.frequency(sync_frequency),.phase_out(phase));
cordic_VK6APH cordic (.i_in(16'd0), .q_in(temp_ADC), .iout(i_out), .qout(q_out), .ain(phase[31:12]), .clk(clock));
wire signed [23:0]cic_out_i;
wire signed [23:0]cic_out_q;
wire signed [23:0]cic_out_i_1;
wire signed [23:0]cic_out_q_1;
wire signed [23:0]cic_out_i_2;
wire signed [23:0]cic_out_q_2;
wire ce_out_i_1;
wire ce_out_q_1;
wire ce_out_i_2;
wire ce_out_q_2;
wire ce_out_i;
wire ce_out_q;
cic_10_1_3_nofraction cic_I_1( .clk(clock),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(i_out),.filter_out(cic_out_i_1),.ce_out(ce_out_i_1));
cic_10_1_3_nofraction cic_Q_1( .clk(clock),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(q_out),.filter_out(cic_out_q_1),.ce_out(ce_out_q_1));
cic_8_1_5_nofraction cic_I_2( .clk(ce_out_i_1),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_i_1),.filter_out(cic_out_i_2),.ce_out(ce_out_i_2));
cic_8_1_5_nofraction cic_Q_2( .clk(ce_out_q_1),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_q_1),.filter_out(cic_out_q_2),.ce_out(ce_out_q_2));
cic_4_1_12_nofraction cic_I_3( .clk(ce_out_i_2),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_i_2),.filter_out(cic_out_i),.ce_out(ce_out_i));
cic_4_1_12_nofraction cic_Q_3( .clk(ce_out_q_2),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_q_2),.filter_out(cic_out_q),.ce_out(ce_out_q));
wire signed [47:0]FIR_i_out;
wire signed [47:0]FIR_q_out;
wire FIR_strobe;
FIR_top FIR(.clk(clock),.reset(~clk_enable),.data_in_I(cic_out_i),.data_in_Q(cic_out_q),.strobe_in(ce_out_i ),.data_out_I(FIR_i_out),.data_out_Q(FIR_q_out),.strobe_out(FIR_strobe));
wire signed [23:0]i_no_dc;
wire signed [23:0]q_no_dc;
wire signed [23:0]dc_in_i;
wire signed [23:0]dc_in_q;
assign dc_in_i = FIR_i_out[47:24];
assign dc_in_q = FIR_q_out[47:24];
dc_offset_correct_new dc_offset_correct_i(.clk(~FIR_strobe),.clken(clk_enable),.data_in(dc_in_i),.data_out(i_no_dc),.dc_level_out());
dc_offset_correct_new dc_offset_correct_q(.clk(~FIR_strobe),.clken(clk_enable),.data_in(dc_in_q),.data_out(q_no_dc),.dc_level_out());
reg signed [23:0]i;
reg signed [23:0]q;
always @ (negedge BCLK)
begin
i <= i_no_dc;
q <= q_no_dc;
end
I2SEncode I2S(.LRCLK(LRCLK), .BCLK(BCLK), .left_sample(i), .right_sample(q), .outbit(MDOUT));
reg [5:0] bits;
reg [1:0]CC_state;
reg [58:0] CCdata;
always @(posedge CBCLK)
begin
case(CC_state)
0: begin
if (CLRCLK == 0)CC_state <= 0;
else CC_state <= 1;
end
1: begin
if (CLRCLK) CC_state <= 1;
else begin
bits <= 6'd58;
CC_state <= 2;
end
end
2: begin
CCdata[bits] <= CC;
if (bits == 0)CC_state <= 0;
else begin
bits <= bits - 1'b1;
CC_state <= 2;
end
end
default: CC_state <= 0;
endcase
end
reg PTT_out;
reg [3:0]Address;
reg [31:0]frequency_HZ;
reg [3:0]clock_select;
wire ref_ext;
wire source_122MHZ;
reg [1:0] ATTEN;
reg [1:0]TX_relay;
reg Rout;
reg [1:0]RX_relay;
always @ (negedge CLRCLK)
begin
PTT_out <= (CCdata[58]);
Address <= CCdata[57:54];
if(Address == 0)begin
frequency_HZ <= CCdata[53:22];
clock_select <= CCdata[21:18];
PGA <= 1'b0;
ATTRLY <= ~CCdata[9];
DITHER <= CCdata[8];
RAND <= CCdata[7];
ATTEN <= CCdata[6:5];
TX_relay <= CCdata[4:3];
Rout <= CCdata[2];
RX_relay <= CCdata[1:0];
end
end
assign ref_ext = clock_select[1];
assign source_122MHZ = clock_select[2] ;
wire [6:0]LPF;
wire [5:0]select_HPF;
wire [31:0]frequency_plus_IF;
assign frequency_plus_IF = frequency + 32'd9000;
LPF_select Alex_LPF_select(.frequency(frequency_plus_IF), .LPF(LPF));
HPF_select Alex_HPF_select(.frequency(frequency_plus_IF), .HPF(select_HPF));
wire ANT1;
wire ANT2;
wire ANT3;
wire Rx_1_out;
wire Transverter;
wire Rx_2_in;
wire Rx_1_in;
assign Rx_1_out = Rout;
assign ANT1 = (TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign ANT2 = (TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign ANT3 = (TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Rx_1_in = (RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign Rx_2_in = (RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Transverter = (RX_relay == 2'b11) ? 1'b1 : 1'b0;
wire _6m_preamp;
wire Tx_yellow_led = 1'b1;
wire Rx_yellow_led = 1'b1;
wire Tx_red_led;
wire Rx_red_led;
wire TR_relay;
wire [15:0]Alex_Tx_data;
wire [15:0]Alex_Rx_data;
wire _10dB_atten = ATTEN[0];
wire _20dB_atten = ATTEN[1];
assign Tx_red_led = PTT_out;
assign TR_relay = PTT_out;
assign Alex_Tx_data = {LPF[6:4],Tx_red_led,TR_relay,ANT3,ANT2,ANT1,LPF[3:0],Tx_yellow_led,3'b000};
assign Rx_red_led = PTT_out;
assign _6m_preamp = (frequency_plus_IF > 50000000) ? 1'b1 : 1'b0;
wire [5:0]HPF;
assign HPF = _6m_preamp ? 6'd0 : select_HPF;
assign Alex_Rx_data = {Rx_red_led,_10dB_atten ,_20dB_atten, HPF[5], Rx_1_out,Rx_1_in,Rx_2_in,Transverter,
1'b0, HPF[4:2],_6m_preamp,HPF[1:0],Rx_yellow_led};
wire [31:0]Alex_data;
assign Alex_data[31:0] = {Alex_Tx_data[15:0],Alex_Rx_data[15:0]};
SPI Alex_SPI_Tx(.Alex_data(Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe),.spi_clock(SPI_clk));
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge clock) begin
if (count_12288 == 767) begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else begin
count_12288 <= 1'b1 + count_12288;
end
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED1 = 1'b1;
assign DEBUG_LED2 = 1'b1;
assign DEBUG_LED3 = TX_relay[0];
assign DEBUG_LED4 = TX_relay[1];
assign DEBUG_LED5 = RX_relay[0];
assign DEBUG_LED6 = RX_relay[1];
assign DEBUG_LED7 = Rout;
assign TEST0 = osc_80khz;
assign TEST1 = ref_80khz;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
endmodule | module Mercury(
input OSC_10MHZ,
inout ext_10MHZ,
input CLKA,
input [15:0]INA,
input CC,
output reg ATTRLY,
output A6,
input C4,
input C8,
input C9,
input C17,
output MDOUT,
input BCLK,
input LRCLK,
output CDIN,
output CBCLK,
output CLRCLK,
output CLRCOUT,
output CMCLK,
output CMODE,
output reg MOSI,
output reg SCLK,
output reg nCS,
output SPI_data,
output SPI_clock,
output Tx_load_strobe,
output Rx_load_strobe,
output FPGA_PLL,
output LVDS_TXE,
output LVDS_RXE_N,
input OVERFLOW,
output reg DITHER,
output SHDN,
output reg PGA,
output reg RAND,
output INIT_DONE,
output TEST0,
output TEST1,
output TEST2,
output TEST3,
output DEBUG_LED0,
output DEBUG_LED1,
output DEBUG_LED2,
output DEBUG_LED3,
output DEBUG_LED4,
output DEBUG_LED5,
output DEBUG_LED6,
output DEBUG_LED7
); |
reg data_ready;
assign CDIN = C4;
assign CLRCLK = C9;
assign CLRCOUT = C9;
assign CBCLK = C8;
assign CMCLK = C17;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
reg clk_enable;
reg [10:0]reset_count;
always @ (posedge clock) begin
if (reset_count[10]) begin
clk_enable <= 1'b1;
end
else begin
clk_enable <= 0;
reset_count <= reset_count + 1'b1;
end
end
always @ (posedge clock)
begin
if (RAND) begin
if (INA[0]) temp_ADC <= {~INA[15:1],INA[0]};
else temp_ADC <= INA;
end
else temp_ADC <= INA;
end
reg index;
reg [15:0]tdata;
reg [2:0]load;
reg [3:0]TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @ (posedge index)
begin
load <= load + 3'b1;
case (load)
3'd0: tdata <= 16'h1E00;
3'd1: tdata <= 16'h1201;
3'd2: tdata <= 16'h0814;
3'd3: tdata <= 16'h0C00;
3'd4: tdata <= 16'h0E02;
3'd5: tdata <= 16'h1000;
3'd6: tdata <= 16'h0A00;
default: load <= 0;
endcase
end
assign CMODE = 1'b1;
always @ (posedge BCLK)
begin
case (TLV)
4'd0: begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
index <= ~index;
TLV <= TLV + 4'b1;
end
4'd1: begin
nCS <= 1'b0;
TLV_data <= tdata;
MOSI <= TLV_data[bit_cnt];
TLV <= TLV + 4'b1;
end
4'd2: begin
SCLK <= 1'b1;
TLV <= TLV + 4'b1;
end
4'd3: begin
SCLK <= 1'b0;
TLV <= TLV + 4'b1;
end
4'd4: begin
if(bit_cnt == 0) begin
index <= ~index;
TLV <= 4'd5;
end
else begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'b1;
end
end
4'd5: begin
if (load == 7)begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else TLV <= 0;
end
default: TLV <= 0;
endcase
end
reg MCLK_12MHZ;
reg [2:0]MCLK_count;
always @ (posedge clock)
begin
if (MCLK_count == 4)
begin
MCLK_12MHZ <= ~MCLK_12MHZ;
MCLK_count <= 0;
end
else MCLK_count <= MCLK_count + 1'b1;
end
reg SPI_clk;
reg SPI_count;
always @(posedge CBCLK)
begin
if(SPI_count == 1)begin
SPI_clk <= ~SPI_clk;
SPI_count <=0;
end
else SPI_count <= SPI_count + 1'b1;
end
wire clock;
assign clock = CLKA;
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
assign A6 = MCLK_12MHZ;
wire reference;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bZ ;
wire [31:0]freq;
wire ready;
always @ (posedge ready)
begin
frequency <= frequency_HZ;
end
division division_DDS(.quotient(freq),.ready(ready),.dividend(frequency),.divider(32'd122880000),.clk(clock));
reg [31:0]sync_frequency;
always @ (posedge clock)
begin
sync_frequency <= freq;
end
wire [17:0]i_out;
wire [17:0]q_out;
reg [15:0]temp_ADC;
wire[31:0] phase;
reg [31:0]frequency;
phase_accumulator rx_phase_accumulator(.clk(~clock),.reset(~clk_enable),.frequency(sync_frequency),.phase_out(phase));
cordic_VK6APH cordic (.i_in(16'd0), .q_in(temp_ADC), .iout(i_out), .qout(q_out), .ain(phase[31:12]), .clk(clock));
wire signed [23:0]cic_out_i;
wire signed [23:0]cic_out_q;
wire signed [23:0]cic_out_i_1;
wire signed [23:0]cic_out_q_1;
wire signed [23:0]cic_out_i_2;
wire signed [23:0]cic_out_q_2;
wire ce_out_i_1;
wire ce_out_q_1;
wire ce_out_i_2;
wire ce_out_q_2;
wire ce_out_i;
wire ce_out_q;
cic_10_1_3_nofraction cic_I_1( .clk(clock),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(i_out),.filter_out(cic_out_i_1),.ce_out(ce_out_i_1));
cic_10_1_3_nofraction cic_Q_1( .clk(clock),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(q_out),.filter_out(cic_out_q_1),.ce_out(ce_out_q_1));
cic_8_1_5_nofraction cic_I_2( .clk(ce_out_i_1),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_i_1),.filter_out(cic_out_i_2),.ce_out(ce_out_i_2));
cic_8_1_5_nofraction cic_Q_2( .clk(ce_out_q_1),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_q_1),.filter_out(cic_out_q_2),.ce_out(ce_out_q_2));
cic_4_1_12_nofraction cic_I_3( .clk(ce_out_i_2),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_i_2),.filter_out(cic_out_i),.ce_out(ce_out_i));
cic_4_1_12_nofraction cic_Q_3( .clk(ce_out_q_2),.clk_enable(clk_enable),.reset(~clk_enable),.filter_in(cic_out_q_2),.filter_out(cic_out_q),.ce_out(ce_out_q));
wire signed [47:0]FIR_i_out;
wire signed [47:0]FIR_q_out;
wire FIR_strobe;
FIR_top FIR(.clk(clock),.reset(~clk_enable),.data_in_I(cic_out_i),.data_in_Q(cic_out_q),.strobe_in(ce_out_i ),.data_out_I(FIR_i_out),.data_out_Q(FIR_q_out),.strobe_out(FIR_strobe));
wire signed [23:0]i_no_dc;
wire signed [23:0]q_no_dc;
wire signed [23:0]dc_in_i;
wire signed [23:0]dc_in_q;
assign dc_in_i = FIR_i_out[47:24];
assign dc_in_q = FIR_q_out[47:24];
dc_offset_correct_new dc_offset_correct_i(.clk(~FIR_strobe),.clken(clk_enable),.data_in(dc_in_i),.data_out(i_no_dc),.dc_level_out());
dc_offset_correct_new dc_offset_correct_q(.clk(~FIR_strobe),.clken(clk_enable),.data_in(dc_in_q),.data_out(q_no_dc),.dc_level_out());
reg signed [23:0]i;
reg signed [23:0]q;
always @ (negedge BCLK)
begin
i <= i_no_dc;
q <= q_no_dc;
end
I2SEncode I2S(.LRCLK(LRCLK), .BCLK(BCLK), .left_sample(i), .right_sample(q), .outbit(MDOUT));
reg [5:0] bits;
reg [1:0]CC_state;
reg [58:0] CCdata;
always @(posedge CBCLK)
begin
case(CC_state)
0: begin
if (CLRCLK == 0)CC_state <= 0;
else CC_state <= 1;
end
1: begin
if (CLRCLK) CC_state <= 1;
else begin
bits <= 6'd58;
CC_state <= 2;
end
end
2: begin
CCdata[bits] <= CC;
if (bits == 0)CC_state <= 0;
else begin
bits <= bits - 1'b1;
CC_state <= 2;
end
end
default: CC_state <= 0;
endcase
end
reg PTT_out;
reg [3:0]Address;
reg [31:0]frequency_HZ;
reg [3:0]clock_select;
wire ref_ext;
wire source_122MHZ;
reg [1:0] ATTEN;
reg [1:0]TX_relay;
reg Rout;
reg [1:0]RX_relay;
always @ (negedge CLRCLK)
begin
PTT_out <= (CCdata[58]);
Address <= CCdata[57:54];
if(Address == 0)begin
frequency_HZ <= CCdata[53:22];
clock_select <= CCdata[21:18];
PGA <= 1'b0;
ATTRLY <= ~CCdata[9];
DITHER <= CCdata[8];
RAND <= CCdata[7];
ATTEN <= CCdata[6:5];
TX_relay <= CCdata[4:3];
Rout <= CCdata[2];
RX_relay <= CCdata[1:0];
end
end
assign ref_ext = clock_select[1];
assign source_122MHZ = clock_select[2] ;
wire [6:0]LPF;
wire [5:0]select_HPF;
wire [31:0]frequency_plus_IF;
assign frequency_plus_IF = frequency + 32'd9000;
LPF_select Alex_LPF_select(.frequency(frequency_plus_IF), .LPF(LPF));
HPF_select Alex_HPF_select(.frequency(frequency_plus_IF), .HPF(select_HPF));
wire ANT1;
wire ANT2;
wire ANT3;
wire Rx_1_out;
wire Transverter;
wire Rx_2_in;
wire Rx_1_in;
assign Rx_1_out = Rout;
assign ANT1 = (TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign ANT2 = (TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign ANT3 = (TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Rx_1_in = (RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign Rx_2_in = (RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign Transverter = (RX_relay == 2'b11) ? 1'b1 : 1'b0;
wire _6m_preamp;
wire Tx_yellow_led = 1'b1;
wire Rx_yellow_led = 1'b1;
wire Tx_red_led;
wire Rx_red_led;
wire TR_relay;
wire [15:0]Alex_Tx_data;
wire [15:0]Alex_Rx_data;
wire _10dB_atten = ATTEN[0];
wire _20dB_atten = ATTEN[1];
assign Tx_red_led = PTT_out;
assign TR_relay = PTT_out;
assign Alex_Tx_data = {LPF[6:4],Tx_red_led,TR_relay,ANT3,ANT2,ANT1,LPF[3:0],Tx_yellow_led,3'b000};
assign Rx_red_led = PTT_out;
assign _6m_preamp = (frequency_plus_IF > 50000000) ? 1'b1 : 1'b0;
wire [5:0]HPF;
assign HPF = _6m_preamp ? 6'd0 : select_HPF;
assign Alex_Rx_data = {Rx_red_led,_10dB_atten ,_20dB_atten, HPF[5], Rx_1_out,Rx_1_in,Rx_2_in,Transverter,
1'b0, HPF[4:2],_6m_preamp,HPF[1:0],Rx_yellow_led};
wire [31:0]Alex_data;
assign Alex_data[31:0] = {Alex_Tx_data[15:0],Alex_Rx_data[15:0]};
SPI Alex_SPI_Tx(.Alex_data(Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe),.spi_clock(SPI_clk));
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge clock) begin
if (count_12288 == 767) begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else begin
count_12288 <= 1'b1 + count_12288;
end
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED1 = 1'b1;
assign DEBUG_LED2 = 1'b1;
assign DEBUG_LED3 = TX_relay[0];
assign DEBUG_LED4 = TX_relay[1];
assign DEBUG_LED5 = RX_relay[0];
assign DEBUG_LED6 = RX_relay[1];
assign DEBUG_LED7 = Rout;
assign TEST0 = osc_80khz;
assign TEST1 = ref_80khz;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
endmodule | 17 |
138,845 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury_V1/oddClockDiv.v | 86,169,941 | oddClockDiv.v | v | 77 | 80 | [] | ['general public license', 'free software foundation'] | [] | [(29, 77)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1/oddClockDiv.v\n%Error: Exiting due to 3 error(s)\n' | 303,040 | module | module oddClockDivider(clk_i, clk_o);
input clk_i;
output clk_o;
wire clk_i;
wire clk_o;
parameter DIVIDE_RATE = 125;
parameter COUNTER_WIDTH=7;
reg [(COUNTER_WIDTH-1):0] count;
always @ (posedge clk_i) begin
case ( count )
DIVIDE_RATE-1: count <= 0;
default: count <= count + 1;
endcase
end
wire en_tff1;
wire en_tff2;
reg div1;
reg div2;
assign en_tff1 = ( count == 0 ? 1 : 0 ) ;
assign en_tff2 = ( count == (((DIVIDE_RATE-1)/2)+1) ? 1 : 0 );
always @ (posedge clk_i) begin
if ( en_tff1 == 1 ) div1 <= ~div1;
end
always @ (negedge clk_i) begin
if ( en_tff2 == 1 ) div2 <= ~div2;
end
assign clk_o = div1 ^ div2;
endmodule | module oddClockDivider(clk_i, clk_o); |
input clk_i;
output clk_o;
wire clk_i;
wire clk_o;
parameter DIVIDE_RATE = 125;
parameter COUNTER_WIDTH=7;
reg [(COUNTER_WIDTH-1):0] count;
always @ (posedge clk_i) begin
case ( count )
DIVIDE_RATE-1: count <= 0;
default: count <= count + 1;
endcase
end
wire en_tff1;
wire en_tff2;
reg div1;
reg div2;
assign en_tff1 = ( count == 0 ? 1 : 0 ) ;
assign en_tff2 = ( count == (((DIVIDE_RATE-1)/2)+1) ? 1 : 0 );
always @ (posedge clk_i) begin
if ( en_tff1 == 1 ) div1 <= ~div1;
end
always @ (negedge clk_i) begin
if ( en_tff2 == 1 ) div2 <= ~div2;
end
assign clk_o = div1 ^ div2;
endmodule | 17 |
138,846 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury_V1/phase_accumulator.v | 86,169,941 | phase_accumulator.v | v | 44 | 97 | [] | ['general public license', 'free software foundation'] | [] | [(30, 44)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Archive/Mercury_V1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V1/phase_accumulator.v\n%Error: Exiting due to 3 error(s)\n' | 303,041 | module | module phase_accumulator(clk,reset,frequency,phase_out);
parameter RESOLUTION = 32;
input clk;
input reset;
input [RESOLUTION-1:0] frequency;
output reg [RESOLUTION-1:0] phase_out;
always @(posedge clk)
if(reset)
phase_out <= #1 32'b0;
else
phase_out <= #1 phase_out + frequency;
endmodule | module phase_accumulator(clk,reset,frequency,phase_out); |
parameter RESOLUTION = 32;
input clk;
input reset;
input [RESOLUTION-1:0] frequency;
output reg [RESOLUTION-1:0] phase_out;
always @(posedge clk)
if(reset)
phase_out <= #1 32'b0;
else
phase_out <= #1 phase_out + frequency;
endmodule | 17 |
138,848 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Archive/Mercury_V3.1/memreceiver.v | 86,169,941 | memreceiver.v | v | 177 | 115 | [] | [] | [] | [(25, 176)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941\n 1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Archive/Mercury_V3.1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Archive/Mercury_V3.1/memreceiver.v\n%Error: Exiting due to 3 error(s)\n' | 303,061 | module | module memreceiver(
input clock,
input [1:0] rate,
input [31:0] frequency,
output out_strobe,
input signed [15:0] in_data,
output [23:0] out_data_I,
output [23:0] out_data_Q
);
parameter INITIAL_STAGES = 3;
wire signed [21:0] cordic_outdata_I;
wire signed [21:0] cordic_outdata_Q;
cordic cordic_inst(
.clock(clock),
.in_data(in_data),
.frequency(frequency),
.out_data_I(cordic_outdata_I),
.out_data_Q(cordic_outdata_Q)
);
wire cic_outstrobe_1;
wire signed [23:0] cic_outdata_I1;
wire signed [23:0] cic_outdata_Q1;
varcic #(.STAGES(INITIAL_STAGES), .DECIMATION(32), .IN_WIDTH(22), .ACC_WIDTH(22+7*INITIAL_STAGES), .OUT_WIDTH(24))
varcic_inst_I1(
.clock(clock),
.in_strobe(1'b1),
.extra_decimation(rate),
.out_strobe(cic_outstrobe_1),
.in_data(cordic_outdata_I),
.out_data(cic_outdata_I1)
);
varcic #(.STAGES(INITIAL_STAGES), .DECIMATION(32), .IN_WIDTH(22), .ACC_WIDTH(22+7*INITIAL_STAGES), .OUT_WIDTH(24))
varcic_inst_Q1(
.clock(clock),
.in_strobe(1'b1),
.extra_decimation(rate),
.out_strobe(),
.in_data(cordic_outdata_Q),
.out_data(cic_outdata_Q1)
);
wire cic_outstrobe_2;
wire signed [23:0] cic_outdata_I2;
wire signed [23:0] cic_outdata_Q2;
memcic #(.STAGES(12), .DECIMATION(10), .ACC_WIDTH(24+40))
cic_inst_I2(
.clock(clock),
.in_strobe(cic_outstrobe_1),
.out_strobe(cic_outstrobe_2),
.in_data(cic_outdata_I1),
.out_data(cic_outdata_I2)
);
memcic #(.STAGES(12), .DECIMATION(10), .ACC_WIDTH(24+40))
cic_inst_Q2(
.clock(clock),
.in_strobe(cic_outstrobe_1),
.out_strobe(),
.in_data(cic_outdata_Q1),
.out_data(cic_outdata_Q2)
);
wire signed [23:0] fir_coeff;
fir_coeffs fir_coeffs_inst(
.clock(clock),
.start(cic_outstrobe_2),
.coeff(fir_coeff)
);
fir #(.OUT_WIDTH(24))
fir_inst_I(
.clock(clock),
.start(cic_outstrobe_2),
.coeff(fir_coeff),
.in_data(cic_outdata_I2),
.out_data(out_data_I),
.out_strobe(out_strobe)
);
fir #(.OUT_WIDTH(24))
fir_inst_Q(
.clock(clock),
.start(cic_outstrobe_2),
.coeff(fir_coeff),
.in_data(cic_outdata_Q2),
.out_data(out_data_Q),
.out_strobe()
);
endmodule | module memreceiver(
input clock,
input [1:0] rate,
input [31:0] frequency,
output out_strobe,
input signed [15:0] in_data,
output [23:0] out_data_I,
output [23:0] out_data_Q
); |
parameter INITIAL_STAGES = 3;
wire signed [21:0] cordic_outdata_I;
wire signed [21:0] cordic_outdata_Q;
cordic cordic_inst(
.clock(clock),
.in_data(in_data),
.frequency(frequency),
.out_data_I(cordic_outdata_I),
.out_data_Q(cordic_outdata_Q)
);
wire cic_outstrobe_1;
wire signed [23:0] cic_outdata_I1;
wire signed [23:0] cic_outdata_Q1;
varcic #(.STAGES(INITIAL_STAGES), .DECIMATION(32), .IN_WIDTH(22), .ACC_WIDTH(22+7*INITIAL_STAGES), .OUT_WIDTH(24))
varcic_inst_I1(
.clock(clock),
.in_strobe(1'b1),
.extra_decimation(rate),
.out_strobe(cic_outstrobe_1),
.in_data(cordic_outdata_I),
.out_data(cic_outdata_I1)
);
varcic #(.STAGES(INITIAL_STAGES), .DECIMATION(32), .IN_WIDTH(22), .ACC_WIDTH(22+7*INITIAL_STAGES), .OUT_WIDTH(24))
varcic_inst_Q1(
.clock(clock),
.in_strobe(1'b1),
.extra_decimation(rate),
.out_strobe(),
.in_data(cordic_outdata_Q),
.out_data(cic_outdata_Q1)
);
wire cic_outstrobe_2;
wire signed [23:0] cic_outdata_I2;
wire signed [23:0] cic_outdata_Q2;
memcic #(.STAGES(12), .DECIMATION(10), .ACC_WIDTH(24+40))
cic_inst_I2(
.clock(clock),
.in_strobe(cic_outstrobe_1),
.out_strobe(cic_outstrobe_2),
.in_data(cic_outdata_I1),
.out_data(cic_outdata_I2)
);
memcic #(.STAGES(12), .DECIMATION(10), .ACC_WIDTH(24+40))
cic_inst_Q2(
.clock(clock),
.in_strobe(cic_outstrobe_1),
.out_strobe(),
.in_data(cic_outdata_Q1),
.out_data(cic_outdata_Q2)
);
wire signed [23:0] fir_coeff;
fir_coeffs fir_coeffs_inst(
.clock(clock),
.start(cic_outstrobe_2),
.coeff(fir_coeff)
);
fir #(.OUT_WIDTH(24))
fir_inst_I(
.clock(clock),
.start(cic_outstrobe_2),
.coeff(fir_coeff),
.in_data(cic_outdata_I2),
.out_data(out_data_I),
.out_strobe(out_strobe)
);
fir #(.OUT_WIDTH(24))
fir_inst_Q(
.clock(clock),
.start(cic_outstrobe_2),
.coeff(fir_coeff),
.in_data(cic_outdata_Q2),
.out_data(out_data_Q),
.out_strobe()
);
endmodule | 17 |
138,851 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Mercury_V3.4/Mercury.v | 86,169,941 | Mercury.v | v | 1,097 | 169 | [] | ['general public license', 'free software foundation'] | [] | null | line:511: before: "{" | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/Mercury.v\n%Error: Exiting due to 3 error(s)\n' | 303,159 | module | module Mercury(OSC_10MHZ, ext_10MHZ,AUX_CLK, C122_clk,INA,CC,ATTRLY,A12,C21,C23,C24,MDOUT_I,MDOUT_Q,CDIN,
TLV320_BCLK,TLV320_LRCIN,TLV320_LRCOUT,TLV320_MCLK,CMODE,MOSI,SCLK,nCS,SPI_data,SPI_clock,
Tx_load_strobe,Rx_load_strobe,FPGA_PLL,LVDS_TXE,LVDS_RXE_N,OVERFLOW,DITHER,SHDN,PGA,RAND,INIT_DONE,
TEST0,TEST1,TEST2,TEST3,DEBUG_LED0,DEBUG_LED1,DEBUG_LED2,DEBUG_LED3,DEBUG_LED4,DEBUG_LED5,
DEBUG_LED6,DEBUG_LED7, Merc_ID,Merc_ID_drv, MULTIPLE_MERC, SDA, SCL);
input wire OSC_10MHZ;
inout tri ext_10MHZ;
input wire AUX_CLK;
input wire C122_clk;
input wire [15:0] INA;
input wire CC;
output wire ATTRLY;
output wire A12;
input wire C21;
output wire C23;
input wire C24;
output wire [2:0] MDOUT_I;
output wire [2:0] MDOUT_Q;
output wire CDIN;
output wire TLV320_BCLK;
output wire TLV320_LRCIN;
output wire TLV320_LRCOUT;
output wire TLV320_MCLK;
output wire CMODE;
output reg MOSI;
output reg SCLK;
output reg nCS;
output wire SPI_data;
output wire SPI_clock;
output wire Tx_load_strobe;
output wire Rx_load_strobe;
output wire FPGA_PLL;
output wire LVDS_TXE;
output wire LVDS_RXE_N;
input wire OVERFLOW;
output reg DITHER;
output wire SHDN;
output wire PGA;
output reg RAND;
output wire INIT_DONE;
output wire TEST0;
output wire TEST1;
output wire TEST2;
output wire TEST3;
output wire DEBUG_LED0;
output wire DEBUG_LED1;
output wire DEBUG_LED2;
output wire DEBUG_LED3;
output wire DEBUG_LED4;
output wire DEBUG_LED5;
output wire DEBUG_LED6;
output wire DEBUG_LED7;
input wire [2:0] Merc_ID;
output wire [3:0] Merc_ID_drv;
input wire MULTIPLE_MERC;
inout wire SDA;
input wire SCL;
parameter C122_TPD = 2.1;
localparam SERIAL = 8'd34;
reg [15:0] temp_ADC;
reg data_ready;
reg Rx_preamp;
wire [3:0] Mercury_Addr;
assign Mercury_Addr = Merc_ID + 1'b1;
assign Merc_ID_drv = 4'b1111;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
assign ATTRLY = ~Rx_preamp;
assign PGA = 1'b0;
reg C122_rst;
reg [10:0] C122_rst_cnt;
always @(posedge C122_clk)
begin
if (!C122_rst_cnt[10])
C122_rst_cnt <= #C122_TPD C122_rst_cnt + 1'b1;
C122_rst <= #C122_TPD C122_rst_cnt[10] ? 1'b0 : 1'b1;
end
always @ (posedge C122_clk)
begin
if (RAND)
begin
if (INA[0])
temp_ADC <= {~INA[15:1],INA[0]};
else
temp_ADC <= INA;
end
else
temp_ADC <= INA;
end
reg [2:0] load;
reg [3:0] TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @*
begin
case (load)
3'd0: TLV_data = 16'h1E00;
3'd1: TLV_data = 16'h1201;
3'd2: TLV_data = 16'h0814;
3'd3: TLV_data = 16'h0C00;
3'd4: TLV_data = 16'h0E02;
3'd5: TLV_data = 16'h1000;
3'd6: TLV_data = 16'h0A00;
default: TLV_data = 0;
endcase
end
assign CMODE = 1'b1;
reg [23:0] tlv_timeout;
always @ (posedge BCLK)
begin
if (tlv_timeout != (200*12288))
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
if (tlv_timeout == (200*12288))
TLV <= 4'd1;
else
TLV <= 4'd0;
end
4'd1:
begin
nCS <= 1'b0;
MOSI <= TLV_data[bit_cnt];
TLV <= 4'd2;
end
4'd2:
begin
SCLK <= 1'b1;
TLV <= 4'd3;
end
4'd3:
begin
SCLK <= 1'b0;
TLV <= 4'd4;
end
4'd4:
begin
if (bit_cnt == 0)
TLV <= 4'd5;
else
begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1;
end
end
4'd5:
begin
if (load == 6)
begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else
begin
TLV <= 4'd0;
load <= load + 3'b1;
end
end
default: TLV <= 4'd0;
endcase
end
localparam SPEED_48K = 2'b00;
reg C122_DFS1, C122_DFS0;
wire C122_cbrise, C122_cbfall;
wire source_122MHZ;
reg C122_cgen_rst;
reg [1:0] C122_SPEED;
clk_div TLVCLK (.reset(C122_rst), .clk_in(C122_clk), .clk_out(TLV320_MCLK));
always @(posedge C122_clk)
begin
if (C122_rst)
C122_SPEED <= 2'b00;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_SPEED <= {C122_DFS1,C122_DFS0};
if (C122_rst)
C122_cgen_rst <= 1'b1;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_cgen_rst <= 1'b1;
else
C122_cgen_rst <= 1'b0;
end
wire C122_cbclk, CLRCLK;
clk_lrclk_gen clrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(C122_cbclk),
.Brise(C122_cbrise), .Bfall(C122_cbfall), .LRCLK(CLRCLK), .Speed(SPEED_48K));
assign TLV320_BCLK = C122_cbclk;
assign TLV320_LRCIN = CLRCLK;
assign TLV320_LRCOUT = CLRCLK;
wire BCLK;
clk_lrclk_gen lrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(BCLK), .Speed(C122_SPEED));
wire SPI_clk;
reg [1:0] spc;
always @(posedge C122_cbclk)
begin
if (C122_rst)
spc <= 2'b00;
else spc <= spc + 2'b01;
end
assign SPI_clk = spc[1];
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
wire reference;
wire ref_ext;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bz;
wire C122_LR_rdy;
wire [31:0] C122_LR_data;
NWire_rcv #(.OSL(32), .OSW(1), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
LRAudio (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_rdy(C122_LR_rdy), .xrcv_ack(C122_LR_rdy), .xrcv_data(C122_LR_data),
.din(C24));
assign C23 = (Merc_ID == 3'b000) ? CLRCLK : 1'bz;
I2S_xmit #(.DATA_BITS(32))
LR (.rst(C122_rst), .lrclk(CLRCLK), .clk(C122_clk), .CBrise(C122_cbrise),
.CBfall(C122_cbfall), .sample(C122_LR_data), .outbit(CDIN));
wire [6:0]i2c_address;
assign i2c_address = {4'b0010, Merc_ID};
i2c_interface i2c_interface(.CLK(TLV320_MCLK), .sda(SDA), .scl(SCL), .version_no(SERIAL),
.ADC_overload(OVERFLOW), .address(i2c_address));
localparam NR = 3;
reg [31:0] C122_frequency_HZ [0:NR-1];
reg [31:0] C122_frequency_HZ_Tx;
reg [31:0] C122_last_freq [0:NR-1];
reg [31:0] C122_sync_phase_word [0:NR-1];
wire [63:0] C122_ratio [0:NR-1];
wire [23:0] rx_I [0:NR-1];
wire [23:0] rx_Q [0:NR-1];
wire strobe [0:NR-1];
wire [NR-1:0] MDO_I;
wire [NR*24-1:0] MDIN_I;
wire [NR-1:0] MDO_Q;
wire [NR*24-1:0] MDIN_Q;
localparam M2 = 32'd1172812403;
reg [5:0] sampling_rate;
always @ ({C122_DFS1, C122_DFS0})
begin
case ({C122_DFS1, C122_DFS0})
0: sampling_rate <= 6'd40;
1: sampling_rate <= 6'd20;
2: sampling_rate <= 6'd10;
3: sampling_rate <= 6'd5;
default: sampling_rate <= 6'd40;
endcase
end
wire C122_clk_ONOFF[0:NR-1];
wire latch[0:NR-1];
reg gate[0:NR-1];
assign latch[0] = 1'b1;
assign latch[1] = (multiRx_mode > 3'b000) ? 1'b1 : 1'b0;
assign latch[2] = (multiRx_mode > 3'b001) ? 1'b1 : 1'b0;
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
gate[0] = 1'b1;
gate[1] = 1'b0;
gate[2] = 1'b0;
end
else
begin
if (latch[0])
gate[0] = 1'b1;
if (latch[1])
gate[1] = 1'b1;
if (latch[2])
gate[2] = 1'b1;
end
end
assign C122_clk_ONOFF[0] = (gate[0]) ? C122_clk : 1'b0;
assign C122_clk_ONOFF[1] = (gate[1]) ? C122_clk : 1'b0;
generate
genvar c;
for (c = 0; c < NR; c = c + 1)
begin: MDC
assign C122_ratio[c] = C122_frequency_HZ[c] * M2;
always @ (posedge C122_clk)
begin
if (C122_cbrise)
begin
C122_last_freq[c] <= C122_frequency_HZ[c];
if (C122_last_freq[c] != C122_frequency_HZ[c])
C122_sync_phase_word[c] <= C122_ratio[c][56:25];
end
end
receiver receiver_inst(
.clock(C122_clk),
.rate(sampling_rate),
.frequency(C122_sync_phase_word[c]),
.out_strobe(strobe[c]),
.in_data(temp_ADC),
.out_data_I(rx_I[c]),
.out_data_Q(rx_Q[c]),
);
assign MDOUT_I[c] = MULTIPLE_MERC ? ((Merc_ID == c) ? (common_Merc_freq ? MDO_I[0] : MDO_I[c]) : 1'bz) : MDO_I[c];
assign MDIN_I[c*24 +: 24] = rx_I[c];
assign MDOUT_Q[c] = MULTIPLE_MERC ? ((Merc_ID == c) ? (common_Merc_freq ? MDO_Q[0] : MDO_Q[c]) : 1'bz) : MDO_Q[c];
assign MDIN_Q[c*24 +: 24] = rx_Q[c];
end
endgenerate
NWire_xmit #(.SEND_FREQ(384000), .OSL(24), .OSW(NR), .ICLK_FREQ(122880000),
.XCLK_FREQ(122880000), .LOW_TIME(1'b0))
M_I (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(MDIN_I), .xreq(strobe[0]), .xrdy(), .xack(), .dout(MDO_I));
NWire_xmit #(.SEND_FREQ(384000), .OSL(24), .OSW(NR), .ICLK_FREQ(122880000),
.XCLK_FREQ(122880000), .LOW_TIME(1'b0))
M_Q (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(MDIN_Q), .xreq(strobe[0]), .xrdy(), .xack(), .dout(MDO_Q));
wire [15:0] spd_data;
wire spd_req, spd_rdy, spd_ack;
wire spf_wreq, spf_rreq, spf_full, spf_empty;
wire trigger;
wire spectrum_out;
assign trigger = C21;
assign A12 = (Merc_ID == 3'b000) ? spectrum_out : 1'bz;
NWire_xmit #(.SEND_FREQ(768000), .OSL(16), .OSW(1), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000))
SPD (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(spd_data), .xreq(spd_req), .xrdy(spd_rdy), .xack(spd_ack), .dout(spectrum_out));
SP_fifo SPF (.sclr(C122_rst), .clock (C122_clk), .full(spf_full), .empty(spf_empty),
.wrreq (spf_wreq), .data (temp_ADC), .rdreq (spf_rreq), .q(spd_data) );
sp_xmit_ctrl
SPC (.rst(C122_rst), .clk(C122_clk), .trigger(trigger), .fifo_full(spf_full),
.fifo_empty(spf_empty), .fifo_wreq(spf_wreq), .fifo_rreq(spf_rreq),
.xfer_req(spd_req), .xfer_rdy(spd_rdy), .xfer_ack(spd_ack) );
wire [90:0] C122_rcv_data;
wire C122_rcv_rdy;
reg C122_PTT_out;
reg [2:0] clock_select;
reg [1:0] C122_ATTEN;
reg [1:0] C122_TX_relay;
reg C122_Rout;
reg [1:0] C122_RX_relay;
reg C122_new_data;
reg [14:0] C122_Alex;
reg Alex_manual;
reg Alex_6m_preamp;
reg [6:0] Alex_manual_LPF;
reg [5:0] Alex_manual_HPF;
reg [2:0] multiRx_mode;
reg [3:0] RxN_preamps;
reg PREAMP;
reg common_Merc_freq;
wire common_select;
wire [3:0] fn;
assign fn = C122_rcv_data[87:84];
assign common_select = ((common_Merc_freq & (fn == 4'b1)) | (!common_Merc_freq & (MULTIPLE_MERC & (fn == Mercury_Addr)))) ? 1'b1 : 1'b0;
generate
genvar j;
for (j = 0; j < NR; j = j + 1)
begin: Fsave
always @ (posedge C122_clk)
begin
if (C122_rst)
C122_frequency_HZ[j] <= 32'b0;
else
if (C122_rcv_rdy && (common_select | (!MULTIPLE_MERC & (fn == j+1))))
C122_frequency_HZ[j] <= C122_rcv_data[83:52];
end
end
endgenerate
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
C122_new_data <= 1'b0;
C122_DFS1 <= 1'b0;
C122_DFS0 <= 1'b0;
C122_PTT_out <= 1'b0;
clock_select <= 3'b000;
DITHER <= 1'b0;
RAND <= 1'b0;
C122_ATTEN <= 2'b00;
C122_TX_relay <= 2'b00;
C122_Rout <= 1'b0;
C122_RX_relay <= 2'b00;
Alex_manual <= 1'b0;
Alex_6m_preamp <= 1'b0;
Alex_manual_LPF <= 7'b0;
Alex_manual_HPF <= 6'b0;
end
else if (C122_rcv_rdy)
begin
if (fn == 0) C122_frequency_HZ_Tx <= C122_rcv_data[83:52];
C122_new_data <= 1'b1;
C122_DFS1 <= C122_rcv_data[90];
C122_DFS0 <= C122_rcv_data[89];
C122_PTT_out <= C122_rcv_data[88];
multiRx_mode <= C122_rcv_data[7:5];
RxN_preamps <= C122_rcv_data[4:1];
common_Merc_freq <= C122_rcv_data[0];
if (C122_rcv_data[87:84] == 4'b0)
begin
clock_select <= C122_rcv_data[51:49];
PREAMP <= C122_rcv_data[40];
DITHER <= C122_rcv_data[39];
RAND <= C122_rcv_data[38];
C122_ATTEN <= C122_rcv_data[37:36];
C122_TX_relay <= C122_rcv_data[35:34];
C122_Rout <= C122_rcv_data[33];
C122_RX_relay <= C122_rcv_data[32:31];
Alex_manual <= C122_rcv_data[30];
if (Merc_ID == 0)
begin
Alex_manual_LPF <= C122_rcv_data[29:23];
Alex_6m_preamp <= C122_rcv_data[22];
Alex_manual_HPF <= C122_rcv_data[21:16];
end
end
if (C122_rcv_data[87:84] == 4'b1)
begin
if (Merc_ID == 1)
begin
Alex_manual_LPF <= C122_rcv_data[29:23];
Alex_6m_preamp <= C122_rcv_data[22];
Alex_manual_HPF <= C122_rcv_data[21:16];
end
end
if (Merc_ID == 0)
begin
if (PREAMP | RxN_preamps[0]) Rx_preamp = 1'b1;
else Rx_preamp = 1'b0;
end
else
Rx_preamp = RxN_preamps[Merc_ID];
end
else
C122_new_data <= 1'b0;
end
NWire_rcv #(.OSL(91), .OSW(1), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
CCrcv (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_data(C122_rcv_data), .xrcv_rdy(C122_rcv_rdy), .xrcv_ack(C122_rcv_rdy), .din(CC));
assign ref_ext = clock_select[1];
assign source_122MHZ = (Merc_ID > 0) ? 1'b0 : (clock_select[2] == 1'b1);
wire [6:0] C122_LPF;
wire [6:0] C122_LPF_auto;
wire [5:0] C122_select_HPF;
wire [5:0] C122_select_HPF_auto;
reg [31:0] C122_freq_max;
reg [31:0] C122_freq_min;
reg [31:0] C122_HPF_freq;
reg [31:0] C122_LPF_freq;
always @ (posedge C122_clk) begin
if (C122_cbrise) begin
C122_freq_max <= C122_frequency_HZ[0];
C122_freq_min <= C122_frequency_HZ[0];
if (C122_frequency_HZ[1] > C122_frequency_HZ[0] && C122_frequency_HZ[1] >= C122_frequency_HZ[2])
C122_freq_max <= C122_frequency_HZ[1];
if (C122_frequency_HZ[2] > C122_frequency_HZ[0] && C122_frequency_HZ[2] >= C122_frequency_HZ[1])
C122_freq_max <= C122_frequency_HZ[2];
if (C122_frequency_HZ[1] < C122_frequency_HZ[0] && C122_frequency_HZ[1] <= C122_frequency_HZ[2] &&
C122_frequency_HZ[1] > 0) C122_freq_min <= C122_frequency_HZ[1];
if (C122_frequency_HZ[2] < C122_frequency_HZ[0] && C122_frequency_HZ[2] <= C122_frequency_HZ[1] &&
C122_frequency_HZ[2] > 0) C122_freq_min <= C122_frequency_HZ[2];
C122_HPF_freq = C122_freq_min;
C122_LPF_freq = (C122_PTT_out) ? C122_frequency_HZ_Tx : C122_freq_max;
end
end
assign C122_LPF = Alex_manual ? Alex_manual_LPF : C122_LPF_auto;
assign C122_select_HPF = Alex_manual ? Alex_manual_HPF : C122_select_HPF_auto;
LPF_select Alex_LPF_select(.clock(C122_clk), .frequency(C122_LPF_freq), .LPF(C122_LPF_auto));
HPF_select Alex_HPF_select(.clock(C122_clk), .frequency(C122_HPF_freq), .HPF(C122_select_HPF_auto));
wire C122_ANT1;
wire C122_ANT2;
wire C122_ANT3;
wire C122_Rx_1_out;
wire C122_Transverter;
wire C122_Rx_2_in;
wire C122_Rx_1_in;
assign C122_Rx_1_out = C122_Rout;
assign C122_ANT1 = (C122_TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign C122_ANT2 = (C122_TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_ANT3 = (C122_TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Rx_1_in = (C122_RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_Rx_2_in = (C122_RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Transverter = (C122_RX_relay == 2'b11) ? 1'b1 : 1'b0;
localparam TX_YELLOW_LED = 1'b1;
localparam RX_YELLOW_LED = 1'b1;
wire C122_6m_preamp;
wire C122_Tx_red_led;
wire C122_Rx_red_led;
wire C122_TR_relay;
wire [15:0] C122_Alex_Tx_data;
wire [15:0] C122_Alex_Rx_data;
wire C122_10dB_atten = C122_ATTEN[0];
wire C122_20dB_atten = C122_ATTEN[1];
assign C122_Tx_red_led = C122_PTT_out;
assign C122_TR_relay = C122_PTT_out;
assign C122_Alex_Tx_data = {C122_LPF[6:4], C122_Tx_red_led, C122_TR_relay, C122_ANT3, C122_ANT2,
C122_ANT1, C122_LPF[3:0], TX_YELLOW_LED, 3'b000};
assign C122_Rx_red_led = C122_PTT_out;
assign C122_6m_preamp = (C122_frequency_HZ[0] > 50000000 && Alex_manual == 1'b0) ? 1'b1 : Alex_6m_preamp;
wire [5:0] C122_HPF;
assign C122_HPF = C122_6m_preamp ? 6'd0 : C122_select_HPF;
assign C122_Alex_Rx_data = {C122_Rx_red_led, C122_10dB_atten, C122_20dB_atten, C122_HPF[5],
C122_Rx_1_out, C122_Rx_1_in, C122_Rx_2_in, C122_Transverter, 1'b0,
C122_HPF[4:2], C122_6m_preamp, C122_HPF[1:0], RX_YELLOW_LED};
wire [31:0] C122_Alex_data;
reg [31:0] SPI_Alex_data;
assign C122_Alex_data = {C122_Alex_Tx_data[15:0], C122_Alex_Rx_data[15:0]};
reg C122_Alex_req;
reg SPI_Alex_ack;
always @ (posedge C122_clk)
begin: C122_ALEX_HANDSHAKE
reg ack;
reg C122_Alex_ack;
if (C122_rst)
C122_Alex_req <= 1'b0;
else if (C122_new_data)
C122_Alex_req <= 1'b1;
else if (C122_Alex_ack)
C122_Alex_req <= 1'b0;
if (C122_rst)
{C122_Alex_ack, ack} <= 2'b00;
else
{C122_Alex_ack, ack} <= {ack, SPI_Alex_ack};
end
always @ (posedge SPI_clk)
begin: SPI_ALEX_HANDSHAKE
reg a2, a1, a0;
reg [31:0] ad0, ad1;
{ad1, ad0} <= {ad0, C122_Alex_data};
{a2, SPI_Alex_ack, a1, a0} <= {SPI_Alex_ack, a1, a0, C122_Alex_req};
if (SPI_Alex_ack & !a2)
SPI_Alex_data <= ad1;
end
SPI Alex_SPI_Tx (.Alex_data(SPI_Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe), .spi_clock(SPI_clk));
wire ref_80khz;
wire osc_80khz;
wire exc_80khz;
wire ref_clock;
wire C10_locked;
wire C122_locked;
oddClockDivider refClockDivider(reference, ref_80khz);
C10_PLL PLL2_inst (.inclk0(AUX_CLK), .c0(exc_80khz), .locked(C10_locked));
C122_PLL PLL_inst (.inclk0(C122_clk), .c0(osc_80khz), .locked(C122_locked));
assign ref_clock = C10_locked ? exc_80khz : ref_80khz;
assign FPGA_PLL = ref_clock ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED3 = C122_locked;
assign DEBUG_LED4 = C10_locked;
assign DEBUG_LED5 = 1'b0;
assign DEBUG_LED6 = 1'b0;
assign DEBUG_LED7 = 1'b0;
assign TEST0 = osc_80khz;
assign TEST1 = ref_clock;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
reg [26:0]counter;
always @(posedge C122_clk) counter = counter + 1'b1;
assign {DEBUG_LED2,DEBUG_LED1} = counter[24:23];
endmodule | module Mercury(OSC_10MHZ, ext_10MHZ,AUX_CLK, C122_clk,INA,CC,ATTRLY,A12,C21,C23,C24,MDOUT_I,MDOUT_Q,CDIN,
TLV320_BCLK,TLV320_LRCIN,TLV320_LRCOUT,TLV320_MCLK,CMODE,MOSI,SCLK,nCS,SPI_data,SPI_clock,
Tx_load_strobe,Rx_load_strobe,FPGA_PLL,LVDS_TXE,LVDS_RXE_N,OVERFLOW,DITHER,SHDN,PGA,RAND,INIT_DONE,
TEST0,TEST1,TEST2,TEST3,DEBUG_LED0,DEBUG_LED1,DEBUG_LED2,DEBUG_LED3,DEBUG_LED4,DEBUG_LED5,
DEBUG_LED6,DEBUG_LED7, Merc_ID,Merc_ID_drv, MULTIPLE_MERC, SDA, SCL); |
input wire OSC_10MHZ;
inout tri ext_10MHZ;
input wire AUX_CLK;
input wire C122_clk;
input wire [15:0] INA;
input wire CC;
output wire ATTRLY;
output wire A12;
input wire C21;
output wire C23;
input wire C24;
output wire [2:0] MDOUT_I;
output wire [2:0] MDOUT_Q;
output wire CDIN;
output wire TLV320_BCLK;
output wire TLV320_LRCIN;
output wire TLV320_LRCOUT;
output wire TLV320_MCLK;
output wire CMODE;
output reg MOSI;
output reg SCLK;
output reg nCS;
output wire SPI_data;
output wire SPI_clock;
output wire Tx_load_strobe;
output wire Rx_load_strobe;
output wire FPGA_PLL;
output wire LVDS_TXE;
output wire LVDS_RXE_N;
input wire OVERFLOW;
output reg DITHER;
output wire SHDN;
output wire PGA;
output reg RAND;
output wire INIT_DONE;
output wire TEST0;
output wire TEST1;
output wire TEST2;
output wire TEST3;
output wire DEBUG_LED0;
output wire DEBUG_LED1;
output wire DEBUG_LED2;
output wire DEBUG_LED3;
output wire DEBUG_LED4;
output wire DEBUG_LED5;
output wire DEBUG_LED6;
output wire DEBUG_LED7;
input wire [2:0] Merc_ID;
output wire [3:0] Merc_ID_drv;
input wire MULTIPLE_MERC;
inout wire SDA;
input wire SCL;
parameter C122_TPD = 2.1;
localparam SERIAL = 8'd34;
reg [15:0] temp_ADC;
reg data_ready;
reg Rx_preamp;
wire [3:0] Mercury_Addr;
assign Mercury_Addr = Merc_ID + 1'b1;
assign Merc_ID_drv = 4'b1111;
assign SHDN = 1'b0;
assign INIT_DONE = 1'b0;
assign ATTRLY = ~Rx_preamp;
assign PGA = 1'b0;
reg C122_rst;
reg [10:0] C122_rst_cnt;
always @(posedge C122_clk)
begin
if (!C122_rst_cnt[10])
C122_rst_cnt <= #C122_TPD C122_rst_cnt + 1'b1;
C122_rst <= #C122_TPD C122_rst_cnt[10] ? 1'b0 : 1'b1;
end
always @ (posedge C122_clk)
begin
if (RAND)
begin
if (INA[0])
temp_ADC <= {~INA[15:1],INA[0]};
else
temp_ADC <= INA;
end
else
temp_ADC <= INA;
end
reg [2:0] load;
reg [3:0] TLV;
reg [15:0] TLV_data;
reg [3:0] bit_cnt;
always @*
begin
case (load)
3'd0: TLV_data = 16'h1E00;
3'd1: TLV_data = 16'h1201;
3'd2: TLV_data = 16'h0814;
3'd3: TLV_data = 16'h0C00;
3'd4: TLV_data = 16'h0E02;
3'd5: TLV_data = 16'h1000;
3'd6: TLV_data = 16'h0A00;
default: TLV_data = 0;
endcase
end
assign CMODE = 1'b1;
reg [23:0] tlv_timeout;
always @ (posedge BCLK)
begin
if (tlv_timeout != (200*12288))
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
if (tlv_timeout == (200*12288))
TLV <= 4'd1;
else
TLV <= 4'd0;
end
4'd1:
begin
nCS <= 1'b0;
MOSI <= TLV_data[bit_cnt];
TLV <= 4'd2;
end
4'd2:
begin
SCLK <= 1'b1;
TLV <= 4'd3;
end
4'd3:
begin
SCLK <= 1'b0;
TLV <= 4'd4;
end
4'd4:
begin
if (bit_cnt == 0)
TLV <= 4'd5;
else
begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1;
end
end
4'd5:
begin
if (load == 6)
begin
TLV <= 4'd5;
nCS <= 1'b1;
end
else
begin
TLV <= 4'd0;
load <= load + 3'b1;
end
end
default: TLV <= 4'd0;
endcase
end
localparam SPEED_48K = 2'b00;
reg C122_DFS1, C122_DFS0;
wire C122_cbrise, C122_cbfall;
wire source_122MHZ;
reg C122_cgen_rst;
reg [1:0] C122_SPEED;
clk_div TLVCLK (.reset(C122_rst), .clk_in(C122_clk), .clk_out(TLV320_MCLK));
always @(posedge C122_clk)
begin
if (C122_rst)
C122_SPEED <= 2'b00;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_SPEED <= {C122_DFS1,C122_DFS0};
if (C122_rst)
C122_cgen_rst <= 1'b1;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_cgen_rst <= 1'b1;
else
C122_cgen_rst <= 1'b0;
end
wire C122_cbclk, CLRCLK;
clk_lrclk_gen clrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(C122_cbclk),
.Brise(C122_cbrise), .Bfall(C122_cbfall), .LRCLK(CLRCLK), .Speed(SPEED_48K));
assign TLV320_BCLK = C122_cbclk;
assign TLV320_LRCIN = CLRCLK;
assign TLV320_LRCOUT = CLRCLK;
wire BCLK;
clk_lrclk_gen lrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(BCLK), .Speed(C122_SPEED));
wire SPI_clk;
reg [1:0] spc;
always @(posedge C122_cbclk)
begin
if (C122_rst)
spc <= 2'b00;
else spc <= spc + 2'b01;
end
assign SPI_clk = spc[1];
assign LVDS_RXE_N = source_122MHZ ? 1'b1 : 1'b0;
assign LVDS_TXE = source_122MHZ ? 1'b1 : 1'b0;
wire reference;
wire ref_ext;
assign reference = ref_ext ? OSC_10MHZ : ext_10MHZ;
assign ext_10MHZ = ref_ext ? OSC_10MHZ : 1'bz;
wire C122_LR_rdy;
wire [31:0] C122_LR_data;
NWire_rcv #(.OSL(32), .OSW(1), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
LRAudio (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_rdy(C122_LR_rdy), .xrcv_ack(C122_LR_rdy), .xrcv_data(C122_LR_data),
.din(C24));
assign C23 = (Merc_ID == 3'b000) ? CLRCLK : 1'bz;
I2S_xmit #(.DATA_BITS(32))
LR (.rst(C122_rst), .lrclk(CLRCLK), .clk(C122_clk), .CBrise(C122_cbrise),
.CBfall(C122_cbfall), .sample(C122_LR_data), .outbit(CDIN));
wire [6:0]i2c_address;
assign i2c_address = {4'b0010, Merc_ID};
i2c_interface i2c_interface(.CLK(TLV320_MCLK), .sda(SDA), .scl(SCL), .version_no(SERIAL),
.ADC_overload(OVERFLOW), .address(i2c_address));
localparam NR = 3;
reg [31:0] C122_frequency_HZ [0:NR-1];
reg [31:0] C122_frequency_HZ_Tx;
reg [31:0] C122_last_freq [0:NR-1];
reg [31:0] C122_sync_phase_word [0:NR-1];
wire [63:0] C122_ratio [0:NR-1];
wire [23:0] rx_I [0:NR-1];
wire [23:0] rx_Q [0:NR-1];
wire strobe [0:NR-1];
wire [NR-1:0] MDO_I;
wire [NR*24-1:0] MDIN_I;
wire [NR-1:0] MDO_Q;
wire [NR*24-1:0] MDIN_Q;
localparam M2 = 32'd1172812403;
reg [5:0] sampling_rate;
always @ ({C122_DFS1, C122_DFS0})
begin
case ({C122_DFS1, C122_DFS0})
0: sampling_rate <= 6'd40;
1: sampling_rate <= 6'd20;
2: sampling_rate <= 6'd10;
3: sampling_rate <= 6'd5;
default: sampling_rate <= 6'd40;
endcase
end
wire C122_clk_ONOFF[0:NR-1];
wire latch[0:NR-1];
reg gate[0:NR-1];
assign latch[0] = 1'b1;
assign latch[1] = (multiRx_mode > 3'b000) ? 1'b1 : 1'b0;
assign latch[2] = (multiRx_mode > 3'b001) ? 1'b1 : 1'b0;
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
gate[0] = 1'b1;
gate[1] = 1'b0;
gate[2] = 1'b0;
end
else
begin
if (latch[0])
gate[0] = 1'b1;
if (latch[1])
gate[1] = 1'b1;
if (latch[2])
gate[2] = 1'b1;
end
end
assign C122_clk_ONOFF[0] = (gate[0]) ? C122_clk : 1'b0;
assign C122_clk_ONOFF[1] = (gate[1]) ? C122_clk : 1'b0;
generate
genvar c;
for (c = 0; c < NR; c = c + 1)
begin: MDC
assign C122_ratio[c] = C122_frequency_HZ[c] * M2;
always @ (posedge C122_clk)
begin
if (C122_cbrise)
begin
C122_last_freq[c] <= C122_frequency_HZ[c];
if (C122_last_freq[c] != C122_frequency_HZ[c])
C122_sync_phase_word[c] <= C122_ratio[c][56:25];
end
end
receiver receiver_inst(
.clock(C122_clk),
.rate(sampling_rate),
.frequency(C122_sync_phase_word[c]),
.out_strobe(strobe[c]),
.in_data(temp_ADC),
.out_data_I(rx_I[c]),
.out_data_Q(rx_Q[c]),
);
assign MDOUT_I[c] = MULTIPLE_MERC ? ((Merc_ID == c) ? (common_Merc_freq ? MDO_I[0] : MDO_I[c]) : 1'bz) : MDO_I[c];
assign MDIN_I[c*24 +: 24] = rx_I[c];
assign MDOUT_Q[c] = MULTIPLE_MERC ? ((Merc_ID == c) ? (common_Merc_freq ? MDO_Q[0] : MDO_Q[c]) : 1'bz) : MDO_Q[c];
assign MDIN_Q[c*24 +: 24] = rx_Q[c];
end
endgenerate
NWire_xmit #(.SEND_FREQ(384000), .OSL(24), .OSW(NR), .ICLK_FREQ(122880000),
.XCLK_FREQ(122880000), .LOW_TIME(1'b0))
M_I (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(MDIN_I), .xreq(strobe[0]), .xrdy(), .xack(), .dout(MDO_I));
NWire_xmit #(.SEND_FREQ(384000), .OSL(24), .OSW(NR), .ICLK_FREQ(122880000),
.XCLK_FREQ(122880000), .LOW_TIME(1'b0))
M_Q (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(MDIN_Q), .xreq(strobe[0]), .xrdy(), .xack(), .dout(MDO_Q));
wire [15:0] spd_data;
wire spd_req, spd_rdy, spd_ack;
wire spf_wreq, spf_rreq, spf_full, spf_empty;
wire trigger;
wire spectrum_out;
assign trigger = C21;
assign A12 = (Merc_ID == 3'b000) ? spectrum_out : 1'bz;
NWire_xmit #(.SEND_FREQ(768000), .OSL(16), .OSW(1), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000))
SPD (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(spd_data), .xreq(spd_req), .xrdy(spd_rdy), .xack(spd_ack), .dout(spectrum_out));
SP_fifo SPF (.sclr(C122_rst), .clock (C122_clk), .full(spf_full), .empty(spf_empty),
.wrreq (spf_wreq), .data (temp_ADC), .rdreq (spf_rreq), .q(spd_data) );
sp_xmit_ctrl
SPC (.rst(C122_rst), .clk(C122_clk), .trigger(trigger), .fifo_full(spf_full),
.fifo_empty(spf_empty), .fifo_wreq(spf_wreq), .fifo_rreq(spf_rreq),
.xfer_req(spd_req), .xfer_rdy(spd_rdy), .xfer_ack(spd_ack) );
wire [90:0] C122_rcv_data;
wire C122_rcv_rdy;
reg C122_PTT_out;
reg [2:0] clock_select;
reg [1:0] C122_ATTEN;
reg [1:0] C122_TX_relay;
reg C122_Rout;
reg [1:0] C122_RX_relay;
reg C122_new_data;
reg [14:0] C122_Alex;
reg Alex_manual;
reg Alex_6m_preamp;
reg [6:0] Alex_manual_LPF;
reg [5:0] Alex_manual_HPF;
reg [2:0] multiRx_mode;
reg [3:0] RxN_preamps;
reg PREAMP;
reg common_Merc_freq;
wire common_select;
wire [3:0] fn;
assign fn = C122_rcv_data[87:84];
assign common_select = ((common_Merc_freq & (fn == 4'b1)) | (!common_Merc_freq & (MULTIPLE_MERC & (fn == Mercury_Addr)))) ? 1'b1 : 1'b0;
generate
genvar j;
for (j = 0; j < NR; j = j + 1)
begin: Fsave
always @ (posedge C122_clk)
begin
if (C122_rst)
C122_frequency_HZ[j] <= 32'b0;
else
if (C122_rcv_rdy && (common_select | (!MULTIPLE_MERC & (fn == j+1))))
C122_frequency_HZ[j] <= C122_rcv_data[83:52];
end
end
endgenerate
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
C122_new_data <= 1'b0;
C122_DFS1 <= 1'b0;
C122_DFS0 <= 1'b0;
C122_PTT_out <= 1'b0;
clock_select <= 3'b000;
DITHER <= 1'b0;
RAND <= 1'b0;
C122_ATTEN <= 2'b00;
C122_TX_relay <= 2'b00;
C122_Rout <= 1'b0;
C122_RX_relay <= 2'b00;
Alex_manual <= 1'b0;
Alex_6m_preamp <= 1'b0;
Alex_manual_LPF <= 7'b0;
Alex_manual_HPF <= 6'b0;
end
else if (C122_rcv_rdy)
begin
if (fn == 0) C122_frequency_HZ_Tx <= C122_rcv_data[83:52];
C122_new_data <= 1'b1;
C122_DFS1 <= C122_rcv_data[90];
C122_DFS0 <= C122_rcv_data[89];
C122_PTT_out <= C122_rcv_data[88];
multiRx_mode <= C122_rcv_data[7:5];
RxN_preamps <= C122_rcv_data[4:1];
common_Merc_freq <= C122_rcv_data[0];
if (C122_rcv_data[87:84] == 4'b0)
begin
clock_select <= C122_rcv_data[51:49];
PREAMP <= C122_rcv_data[40];
DITHER <= C122_rcv_data[39];
RAND <= C122_rcv_data[38];
C122_ATTEN <= C122_rcv_data[37:36];
C122_TX_relay <= C122_rcv_data[35:34];
C122_Rout <= C122_rcv_data[33];
C122_RX_relay <= C122_rcv_data[32:31];
Alex_manual <= C122_rcv_data[30];
if (Merc_ID == 0)
begin
Alex_manual_LPF <= C122_rcv_data[29:23];
Alex_6m_preamp <= C122_rcv_data[22];
Alex_manual_HPF <= C122_rcv_data[21:16];
end
end
if (C122_rcv_data[87:84] == 4'b1)
begin
if (Merc_ID == 1)
begin
Alex_manual_LPF <= C122_rcv_data[29:23];
Alex_6m_preamp <= C122_rcv_data[22];
Alex_manual_HPF <= C122_rcv_data[21:16];
end
end
if (Merc_ID == 0)
begin
if (PREAMP | RxN_preamps[0]) Rx_preamp = 1'b1;
else Rx_preamp = 1'b0;
end
else
Rx_preamp = RxN_preamps[Merc_ID];
end
else
C122_new_data <= 1'b0;
end
NWire_rcv #(.OSL(91), .OSW(1), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
CCrcv (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_data(C122_rcv_data), .xrcv_rdy(C122_rcv_rdy), .xrcv_ack(C122_rcv_rdy), .din(CC));
assign ref_ext = clock_select[1];
assign source_122MHZ = (Merc_ID > 0) ? 1'b0 : (clock_select[2] == 1'b1);
wire [6:0] C122_LPF;
wire [6:0] C122_LPF_auto;
wire [5:0] C122_select_HPF;
wire [5:0] C122_select_HPF_auto;
reg [31:0] C122_freq_max;
reg [31:0] C122_freq_min;
reg [31:0] C122_HPF_freq;
reg [31:0] C122_LPF_freq;
always @ (posedge C122_clk) begin
if (C122_cbrise) begin
C122_freq_max <= C122_frequency_HZ[0];
C122_freq_min <= C122_frequency_HZ[0];
if (C122_frequency_HZ[1] > C122_frequency_HZ[0] && C122_frequency_HZ[1] >= C122_frequency_HZ[2])
C122_freq_max <= C122_frequency_HZ[1];
if (C122_frequency_HZ[2] > C122_frequency_HZ[0] && C122_frequency_HZ[2] >= C122_frequency_HZ[1])
C122_freq_max <= C122_frequency_HZ[2];
if (C122_frequency_HZ[1] < C122_frequency_HZ[0] && C122_frequency_HZ[1] <= C122_frequency_HZ[2] &&
C122_frequency_HZ[1] > 0) C122_freq_min <= C122_frequency_HZ[1];
if (C122_frequency_HZ[2] < C122_frequency_HZ[0] && C122_frequency_HZ[2] <= C122_frequency_HZ[1] &&
C122_frequency_HZ[2] > 0) C122_freq_min <= C122_frequency_HZ[2];
C122_HPF_freq = C122_freq_min;
C122_LPF_freq = (C122_PTT_out) ? C122_frequency_HZ_Tx : C122_freq_max;
end
end
assign C122_LPF = Alex_manual ? Alex_manual_LPF : C122_LPF_auto;
assign C122_select_HPF = Alex_manual ? Alex_manual_HPF : C122_select_HPF_auto;
LPF_select Alex_LPF_select(.clock(C122_clk), .frequency(C122_LPF_freq), .LPF(C122_LPF_auto));
HPF_select Alex_HPF_select(.clock(C122_clk), .frequency(C122_HPF_freq), .HPF(C122_select_HPF_auto));
wire C122_ANT1;
wire C122_ANT2;
wire C122_ANT3;
wire C122_Rx_1_out;
wire C122_Transverter;
wire C122_Rx_2_in;
wire C122_Rx_1_in;
assign C122_Rx_1_out = C122_Rout;
assign C122_ANT1 = (C122_TX_relay == 2'b00) ? 1'b1 : 1'b0;
assign C122_ANT2 = (C122_TX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_ANT3 = (C122_TX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Rx_1_in = (C122_RX_relay == 2'b01) ? 1'b1 : 1'b0;
assign C122_Rx_2_in = (C122_RX_relay == 2'b10) ? 1'b1 : 1'b0;
assign C122_Transverter = (C122_RX_relay == 2'b11) ? 1'b1 : 1'b0;
localparam TX_YELLOW_LED = 1'b1;
localparam RX_YELLOW_LED = 1'b1;
wire C122_6m_preamp;
wire C122_Tx_red_led;
wire C122_Rx_red_led;
wire C122_TR_relay;
wire [15:0] C122_Alex_Tx_data;
wire [15:0] C122_Alex_Rx_data;
wire C122_10dB_atten = C122_ATTEN[0];
wire C122_20dB_atten = C122_ATTEN[1];
assign C122_Tx_red_led = C122_PTT_out;
assign C122_TR_relay = C122_PTT_out;
assign C122_Alex_Tx_data = {C122_LPF[6:4], C122_Tx_red_led, C122_TR_relay, C122_ANT3, C122_ANT2,
C122_ANT1, C122_LPF[3:0], TX_YELLOW_LED, 3'b000};
assign C122_Rx_red_led = C122_PTT_out;
assign C122_6m_preamp = (C122_frequency_HZ[0] > 50000000 && Alex_manual == 1'b0) ? 1'b1 : Alex_6m_preamp;
wire [5:0] C122_HPF;
assign C122_HPF = C122_6m_preamp ? 6'd0 : C122_select_HPF;
assign C122_Alex_Rx_data = {C122_Rx_red_led, C122_10dB_atten, C122_20dB_atten, C122_HPF[5],
C122_Rx_1_out, C122_Rx_1_in, C122_Rx_2_in, C122_Transverter, 1'b0,
C122_HPF[4:2], C122_6m_preamp, C122_HPF[1:0], RX_YELLOW_LED};
wire [31:0] C122_Alex_data;
reg [31:0] SPI_Alex_data;
assign C122_Alex_data = {C122_Alex_Tx_data[15:0], C122_Alex_Rx_data[15:0]};
reg C122_Alex_req;
reg SPI_Alex_ack;
always @ (posedge C122_clk)
begin: C122_ALEX_HANDSHAKE
reg ack;
reg C122_Alex_ack;
if (C122_rst)
C122_Alex_req <= 1'b0;
else if (C122_new_data)
C122_Alex_req <= 1'b1;
else if (C122_Alex_ack)
C122_Alex_req <= 1'b0;
if (C122_rst)
{C122_Alex_ack, ack} <= 2'b00;
else
{C122_Alex_ack, ack} <= {ack, SPI_Alex_ack};
end
always @ (posedge SPI_clk)
begin: SPI_ALEX_HANDSHAKE
reg a2, a1, a0;
reg [31:0] ad0, ad1;
{ad1, ad0} <= {ad0, C122_Alex_data};
{a2, SPI_Alex_ack, a1, a0} <= {SPI_Alex_ack, a1, a0, C122_Alex_req};
if (SPI_Alex_ack & !a2)
SPI_Alex_data <= ad1;
end
SPI Alex_SPI_Tx (.Alex_data(SPI_Alex_data), .SPI_data(SPI_data),
.SPI_clock(SPI_clock), .Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe), .spi_clock(SPI_clk));
wire ref_80khz;
wire osc_80khz;
wire exc_80khz;
wire ref_clock;
wire C10_locked;
wire C122_locked;
oddClockDivider refClockDivider(reference, ref_80khz);
C10_PLL PLL2_inst (.inclk0(AUX_CLK), .c0(exc_80khz), .locked(C10_locked));
C122_PLL PLL_inst (.inclk0(C122_clk), .c0(osc_80khz), .locked(C122_locked));
assign ref_clock = C10_locked ? exc_80khz : ref_80khz;
assign FPGA_PLL = ref_clock ^ osc_80khz;
assign DEBUG_LED0 = OVERFLOW;
assign DEBUG_LED3 = C122_locked;
assign DEBUG_LED4 = C10_locked;
assign DEBUG_LED5 = 1'b0;
assign DEBUG_LED6 = 1'b0;
assign DEBUG_LED7 = 1'b0;
assign TEST0 = osc_80khz;
assign TEST1 = ref_clock;
assign TEST2 = FPGA_PLL;
assign TEST3 = 1'b0;
reg [26:0]counter;
always @(posedge C122_clk) counter = counter + 1'b1;
assign {DEBUG_LED2,DEBUG_LED1} = counter[24:23];
endmodule | 17 |
138,853 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Mercury_V3.4/varcic.v | 86,169,941 | varcic.v | v | 168 | 81 | [] | [] | [] | [(25, 165)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Mercury_V3.4,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/varcic.v\n%Error: Exiting due to 3 error(s)\n' | 303,169 | module | module varcic(decimation, clock, in_strobe, out_strobe, in_data, out_data );
parameter STAGES = 5;
parameter IN_WIDTH = 18;
parameter ACC_WIDTH = 45;
parameter OUT_WIDTH = 18;
input [5:0] decimation;
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output reg signed [OUT_WIDTH-1:0] out_data;
reg [15:0] sample_no;
initial sample_no = 16'd0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == (decimation - 1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
localparam GROWTH2 = 5;
localparam GROWTH4 = 10;
localparam GROWTH5 = 12;
localparam GROWTH8 = 15;
localparam GROWTH10 = 17;
localparam GROWTH20 = 22;
localparam GROWTH40 = 27;
localparam MSB2 = (IN_WIDTH + GROWTH2) - 1;
localparam LSB2 = (IN_WIDTH + GROWTH2) - OUT_WIDTH;
localparam MSB4 = (IN_WIDTH + GROWTH4) - 1;
localparam LSB4 = (IN_WIDTH + GROWTH4) - OUT_WIDTH;
localparam MSB5 = (IN_WIDTH + GROWTH5) - 1;
localparam LSB5 = (IN_WIDTH + GROWTH5) - OUT_WIDTH;
localparam MSB8 = (IN_WIDTH + GROWTH8) - 1;
localparam LSB8 = (IN_WIDTH + GROWTH8) - OUT_WIDTH;
localparam MSB10 = (IN_WIDTH + GROWTH10) - 1;
localparam LSB10 = (IN_WIDTH + GROWTH10) - OUT_WIDTH;
localparam MSB20 = (IN_WIDTH + GROWTH20) - 1;
localparam LSB20 = (IN_WIDTH + GROWTH20) - OUT_WIDTH;
localparam MSB40 = (IN_WIDTH + GROWTH40) - 1;
localparam LSB40 = (IN_WIDTH + GROWTH40) - OUT_WIDTH;
always @(posedge clock)
case (decimation)
2: out_data <= comb_data[STAGES][MSB2:LSB2] + comb_data[STAGES][LSB2-1];
4: out_data <= comb_data[STAGES][MSB4:LSB4] + comb_data[STAGES][LSB4-1];
5: out_data <= comb_data[STAGES][MSB5:LSB5] + comb_data[STAGES][LSB5-1];
8: out_data <= comb_data[STAGES][MSB8:LSB8] + comb_data[STAGES][LSB8-1];
10: out_data <= comb_data[STAGES][MSB10:LSB10] + comb_data[STAGES][LSB10-1];
20: out_data <= comb_data[STAGES][MSB20:LSB20] + comb_data[STAGES][LSB20-1];
40: out_data <= comb_data[STAGES][MSB40:LSB40] + comb_data[STAGES][LSB40-1];
endcase
endmodule | module varcic(decimation, clock, in_strobe, out_strobe, in_data, out_data ); |
parameter STAGES = 5;
parameter IN_WIDTH = 18;
parameter ACC_WIDTH = 45;
parameter OUT_WIDTH = 18;
input [5:0] decimation;
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output reg signed [OUT_WIDTH-1:0] out_data;
reg [15:0] sample_no;
initial sample_no = 16'd0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == (decimation - 1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
localparam GROWTH2 = 5;
localparam GROWTH4 = 10;
localparam GROWTH5 = 12;
localparam GROWTH8 = 15;
localparam GROWTH10 = 17;
localparam GROWTH20 = 22;
localparam GROWTH40 = 27;
localparam MSB2 = (IN_WIDTH + GROWTH2) - 1;
localparam LSB2 = (IN_WIDTH + GROWTH2) - OUT_WIDTH;
localparam MSB4 = (IN_WIDTH + GROWTH4) - 1;
localparam LSB4 = (IN_WIDTH + GROWTH4) - OUT_WIDTH;
localparam MSB5 = (IN_WIDTH + GROWTH5) - 1;
localparam LSB5 = (IN_WIDTH + GROWTH5) - OUT_WIDTH;
localparam MSB8 = (IN_WIDTH + GROWTH8) - 1;
localparam LSB8 = (IN_WIDTH + GROWTH8) - OUT_WIDTH;
localparam MSB10 = (IN_WIDTH + GROWTH10) - 1;
localparam LSB10 = (IN_WIDTH + GROWTH10) - OUT_WIDTH;
localparam MSB20 = (IN_WIDTH + GROWTH20) - 1;
localparam LSB20 = (IN_WIDTH + GROWTH20) - OUT_WIDTH;
localparam MSB40 = (IN_WIDTH + GROWTH40) - 1;
localparam LSB40 = (IN_WIDTH + GROWTH40) - OUT_WIDTH;
always @(posedge clock)
case (decimation)
2: out_data <= comb_data[STAGES][MSB2:LSB2] + comb_data[STAGES][LSB2-1];
4: out_data <= comb_data[STAGES][MSB4:LSB4] + comb_data[STAGES][LSB4-1];
5: out_data <= comb_data[STAGES][MSB5:LSB5] + comb_data[STAGES][LSB5-1];
8: out_data <= comb_data[STAGES][MSB8:LSB8] + comb_data[STAGES][LSB8-1];
10: out_data <= comb_data[STAGES][MSB10:LSB10] + comb_data[STAGES][LSB10-1];
20: out_data <= comb_data[STAGES][MSB20:LSB20] + comb_data[STAGES][LSB20-1];
40: out_data <= comb_data[STAGES][MSB40:LSB40] + comb_data[STAGES][LSB40-1];
endcase
endmodule | 17 |
138,855 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Mercury_V3.4/common/i2c_interface.v | 86,169,941 | i2c_interface.v | v | 100 | 103 | [] | ['general public license', 'free software foundation'] | [] | [(31, 100)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/common/i2c_interface.v\n%Error: Exiting due to 3 error(s)\n' | 303,173 | module | module i2c_interface (CLK, sda, scl, version_no, ADC_overload, address);
input CLK;
inout sda;
input scl;
input [7:0] version_no;
input ADC_overload;
input [6:0] address;
reg reset;
wire [7:0] int_reg0;
wire [7:0] int_reg1;
reg [7:0] rcv_reg0;
reg [7:0] rcv_reg1;
wire sda_out;
wire sda_oe;
wire dg_scl;
wire dg_sda;
reg [6:0] slave_addr;
always @ (posedge CLK) begin
if (slave_addr == address) begin
rcv_reg0 <= {7'b0, !ADC_overload};
rcv_reg1 <= version_no;
end
end
reg [5:0]reset_count;
always @ (posedge CLK)
begin
if (reset_count[5]) begin
reset <= 1'b1;
end
else begin
reset <= 0;
reset_count <= reset_count + 1'b1;
end
end
deglitch deglitch_scl(.clock(CLK), .in(scl),.out(dg_scl));
deglitch deglitch_sda(.clock(CLK), .in(sda),.out(dg_sda));
i2c_slave(.rst_n(reset), .slave_addr(slave_addr), .address(address),
.sda_i(dg_sda), .sda_out(sda_out),.sda_oe(sda_oe),.scl_in(dg_scl),
.int_reg0(LED),.int_reg1(), .rcv_reg0(rcv_reg0), .rcv_reg1(rcv_reg1));
assign sda = sda_oe ? (sda_out ? 1'bz : 1'b0) : 1'bz;
endmodule | module i2c_interface (CLK, sda, scl, version_no, ADC_overload, address); |
input CLK;
inout sda;
input scl;
input [7:0] version_no;
input ADC_overload;
input [6:0] address;
reg reset;
wire [7:0] int_reg0;
wire [7:0] int_reg1;
reg [7:0] rcv_reg0;
reg [7:0] rcv_reg1;
wire sda_out;
wire sda_oe;
wire dg_scl;
wire dg_sda;
reg [6:0] slave_addr;
always @ (posedge CLK) begin
if (slave_addr == address) begin
rcv_reg0 <= {7'b0, !ADC_overload};
rcv_reg1 <= version_no;
end
end
reg [5:0]reset_count;
always @ (posedge CLK)
begin
if (reset_count[5]) begin
reset <= 1'b1;
end
else begin
reset <= 0;
reset_count <= reset_count + 1'b1;
end
end
deglitch deglitch_scl(.clock(CLK), .in(scl),.out(dg_scl));
deglitch deglitch_sda(.clock(CLK), .in(sda),.out(dg_sda));
i2c_slave(.rst_n(reset), .slave_addr(slave_addr), .address(address),
.sda_i(dg_sda), .sda_out(sda_out),.sda_oe(sda_oe),.scl_in(dg_scl),
.int_reg0(LED),.int_reg1(), .rcv_reg0(rcv_reg0), .rcv_reg1(rcv_reg1));
assign sda = sda_oe ? (sda_out ? 1'bz : 1'b0) : 1'bz;
endmodule | 17 |
138,856 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Mercury_V3.4/common/i2c_slave.v | 86,169,941 | i2c_slave.v | v | 309 | 93 | [] | ['general public license', 'free software foundation'] | [] | [(41, 308)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Mercury_V3.4/common,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/common/i2c_slave.v\n%Error: Exiting due to 3 error(s)\n' | 303,174 | module | module i2c_slave (
rst_n,
slave_addr,
address,
sda_i,
sda_out,
sda_oe,
scl_in,
int_reg0,
int_reg1,
rcv_reg0,
rcv_reg1,
probe
);
input rst_n;
output wire [6:0] slave_addr;
input [6:0] address;
input sda_i;
output sda_out;
output sda_oe;
input scl_in;
output [7:0] int_reg0;
output [7:0] int_reg1;
input [7:0] rcv_reg0;
input [7:0] rcv_reg1;
output reg probe;
reg start;
reg stop;
reg [9:0] rcv_reg;
reg [3:0] rcv_cntr;
reg [2:0] i2c_sm;
reg [2:0] nxt_i2c_sm;
reg cyc_cnt;
reg target;
wire ack;
wire nack;
wire int_sda;
reg sda_in;
wire read;
wire write;
wire addr_dec;
always @(sda_i)
#1 sda_in = sda_i;
wire start_clr = ~rst_n | (rcv_cntr == 4'h2);
always @(negedge sda_in or posedge start_clr)
if(start_clr)
start <= 1'b0;
else
if(scl_in == 1)
start <= 1'b1;
wire stop_clr = ~rst_n | ack | start;
always @(posedge sda_in or posedge stop_clr)
if(stop_clr)
stop <= 1'b0;
else
if(scl_in == 1)
stop <= 1'b1;
wire cnt8 = (rcv_cntr == 4'h8);
wire cnt7 = (rcv_cntr == 4'h7);
wire cntr_rst = ~rst_n;
always @(negedge scl_in or posedge cntr_rst)
if(cntr_rst)
rcv_cntr <= 4'b0;
else
if(cnt8 | start & ((i2c_sm == `SM_WRITE) | (i2c_sm == `SM_READ)) )
rcv_cntr <= 4'b0;
else
if(i2c_sm != `SM_IDLE)
rcv_cntr <= rcv_cntr + 4'h1;
wire last_bit = (read & end_counter >= 18);
reg [5:0] end_counter;
always @ (posedge scl_in or posedge cntr_rst) begin
if (cntr_rst) begin
end_counter <= 0;
end
else begin
if (target) begin
end_counter <= end_counter + 1;
end
else end_counter <= 6'd0;
end
end
always @(posedge scl_in or negedge rst_n)
begin
if(~rst_n) begin
rcv_reg <= 10'b0;
end
else begin
if(rcv_cntr <= 4'h7)
rcv_reg <= {rcv_reg[8:0],sda_in};
end
end
assign ack = cnt8 & ~sda_in;
assign nack = cnt8 & sda_in;
assign slave_addr = (i2c_sm == `SM_ADDR) ? rcv_reg[7:1] : 7'b0;
wire i2c_write = ~rcv_reg[0] & (i2c_sm == `SM_ADDR);
assign addr_dec = (slave_addr == address) & (i2c_sm == `SM_ADDR);
assign read = (i2c_sm == `SM_READ);
assign write = (i2c_sm == `SM_WRITE);
always @(start or cnt8 or addr_dec or
ack or i2c_write or nack or i2c_sm)
case(i2c_sm)
`SM_IDLE: if(start) begin
nxt_i2c_sm = `SM_ADDR;
end
else
nxt_i2c_sm = `SM_IDLE;
`SM_ADDR: if(cnt8 & ~addr_dec)
nxt_i2c_sm = `SM_IDLE;
else
if(cnt8 & addr_dec & ack & i2c_write)
nxt_i2c_sm = `SM_WRITE;
else
if(cnt8 & addr_dec & ack & ~i2c_write)
nxt_i2c_sm = `SM_READ;
else
if(cnt8 & addr_dec & nack)
nxt_i2c_sm = `SM_IDLE;
else
nxt_i2c_sm = `SM_ADDR;
`SM_WRITE: if(start)
nxt_i2c_sm = `SM_ADDR;
else
if(cnt8 & ack)
nxt_i2c_sm = `SM_WRITE;
else
nxt_i2c_sm = `SM_WRITE;
`SM_READ: if(start)
nxt_i2c_sm = `SM_ADDR;
else
if(cnt8 & nack)
nxt_i2c_sm = `SM_WAIT;
else
nxt_i2c_sm = `SM_READ;
`SM_WAIT: nxt_i2c_sm = `SM_WAIT;
default: nxt_i2c_sm = `SM_IDLE;
endcase
wire sm_rst = stop | ~rst_n;
always @(posedge scl_in or posedge sm_rst)
if(sm_rst)
i2c_sm <= `SM_IDLE;
else
i2c_sm <= nxt_i2c_sm;
wire cyc_rst = ~rst_n | stop | start;
always @(posedge scl_in or posedge cyc_rst)
if(cyc_rst == 1'b1)
cyc_cnt <= 3'b0;
else
if(target & cnt8)
cyc_cnt <= cyc_cnt + 3'b1;
reg sda_oe;
always @(negedge scl_in or negedge rst_n)
if(~rst_n)
sda_oe <= 1'b0;
else sda_oe <= (target & read & ~cnt7 & ~last_bit) |
(i2c_sm == `SM_ADDR) & cnt7 |
write & cnt7;
assign sda_out = (target & read & ~cnt8) ? int_sda :
((addr_dec | target) ? 1'b0 : 1'b1);
always @(posedge scl_in or posedge cyc_rst)
if(cyc_rst == 1'b1)
target <= 1'b0;
else
if(ack & (i2c_sm == `SM_ADDR))
target <= addr_dec;
reg [7:0] int_reg0;
reg [7:0] int_reg1;
wire load_int_reg = ack & target & write;
always @(posedge scl_in or negedge rst_n)
if(~rst_n)
begin
int_reg0 <= 8'b0;
int_reg1 <= 8'b0;
end
else
if(load_int_reg)
case(cyc_cnt)
3'h0: int_reg0 <= rcv_reg[7:0];
3'h1: int_reg1 <= rcv_reg[7:0];
endcase
reg [7:0] main_out;
always @(cyc_cnt or rcv_reg0 or rcv_reg1)
case(cyc_cnt)
3'h0: main_out = rcv_reg0;
3'h1: main_out = rcv_reg1;
endcase
assign int_sda = main_out[7-rcv_cntr[2:0]];
endmodule | module i2c_slave (
rst_n,
slave_addr,
address,
sda_i,
sda_out,
sda_oe,
scl_in,
int_reg0,
int_reg1,
rcv_reg0,
rcv_reg1,
probe
); |
input rst_n;
output wire [6:0] slave_addr;
input [6:0] address;
input sda_i;
output sda_out;
output sda_oe;
input scl_in;
output [7:0] int_reg0;
output [7:0] int_reg1;
input [7:0] rcv_reg0;
input [7:0] rcv_reg1;
output reg probe;
reg start;
reg stop;
reg [9:0] rcv_reg;
reg [3:0] rcv_cntr;
reg [2:0] i2c_sm;
reg [2:0] nxt_i2c_sm;
reg cyc_cnt;
reg target;
wire ack;
wire nack;
wire int_sda;
reg sda_in;
wire read;
wire write;
wire addr_dec;
always @(sda_i)
#1 sda_in = sda_i;
wire start_clr = ~rst_n | (rcv_cntr == 4'h2);
always @(negedge sda_in or posedge start_clr)
if(start_clr)
start <= 1'b0;
else
if(scl_in == 1)
start <= 1'b1;
wire stop_clr = ~rst_n | ack | start;
always @(posedge sda_in or posedge stop_clr)
if(stop_clr)
stop <= 1'b0;
else
if(scl_in == 1)
stop <= 1'b1;
wire cnt8 = (rcv_cntr == 4'h8);
wire cnt7 = (rcv_cntr == 4'h7);
wire cntr_rst = ~rst_n;
always @(negedge scl_in or posedge cntr_rst)
if(cntr_rst)
rcv_cntr <= 4'b0;
else
if(cnt8 | start & ((i2c_sm == `SM_WRITE) | (i2c_sm == `SM_READ)) )
rcv_cntr <= 4'b0;
else
if(i2c_sm != `SM_IDLE)
rcv_cntr <= rcv_cntr + 4'h1;
wire last_bit = (read & end_counter >= 18);
reg [5:0] end_counter;
always @ (posedge scl_in or posedge cntr_rst) begin
if (cntr_rst) begin
end_counter <= 0;
end
else begin
if (target) begin
end_counter <= end_counter + 1;
end
else end_counter <= 6'd0;
end
end
always @(posedge scl_in or negedge rst_n)
begin
if(~rst_n) begin
rcv_reg <= 10'b0;
end
else begin
if(rcv_cntr <= 4'h7)
rcv_reg <= {rcv_reg[8:0],sda_in};
end
end
assign ack = cnt8 & ~sda_in;
assign nack = cnt8 & sda_in;
assign slave_addr = (i2c_sm == `SM_ADDR) ? rcv_reg[7:1] : 7'b0;
wire i2c_write = ~rcv_reg[0] & (i2c_sm == `SM_ADDR);
assign addr_dec = (slave_addr == address) & (i2c_sm == `SM_ADDR);
assign read = (i2c_sm == `SM_READ);
assign write = (i2c_sm == `SM_WRITE);
always @(start or cnt8 or addr_dec or
ack or i2c_write or nack or i2c_sm)
case(i2c_sm)
`SM_IDLE: if(start) begin
nxt_i2c_sm = `SM_ADDR;
end
else
nxt_i2c_sm = `SM_IDLE;
`SM_ADDR: if(cnt8 & ~addr_dec)
nxt_i2c_sm = `SM_IDLE;
else
if(cnt8 & addr_dec & ack & i2c_write)
nxt_i2c_sm = `SM_WRITE;
else
if(cnt8 & addr_dec & ack & ~i2c_write)
nxt_i2c_sm = `SM_READ;
else
if(cnt8 & addr_dec & nack)
nxt_i2c_sm = `SM_IDLE;
else
nxt_i2c_sm = `SM_ADDR;
`SM_WRITE: if(start)
nxt_i2c_sm = `SM_ADDR;
else
if(cnt8 & ack)
nxt_i2c_sm = `SM_WRITE;
else
nxt_i2c_sm = `SM_WRITE;
`SM_READ: if(start)
nxt_i2c_sm = `SM_ADDR;
else
if(cnt8 & nack)
nxt_i2c_sm = `SM_WAIT;
else
nxt_i2c_sm = `SM_READ;
`SM_WAIT: nxt_i2c_sm = `SM_WAIT;
default: nxt_i2c_sm = `SM_IDLE;
endcase
wire sm_rst = stop | ~rst_n;
always @(posedge scl_in or posedge sm_rst)
if(sm_rst)
i2c_sm <= `SM_IDLE;
else
i2c_sm <= nxt_i2c_sm;
wire cyc_rst = ~rst_n | stop | start;
always @(posedge scl_in or posedge cyc_rst)
if(cyc_rst == 1'b1)
cyc_cnt <= 3'b0;
else
if(target & cnt8)
cyc_cnt <= cyc_cnt + 3'b1;
reg sda_oe;
always @(negedge scl_in or negedge rst_n)
if(~rst_n)
sda_oe <= 1'b0;
else sda_oe <= (target & read & ~cnt7 & ~last_bit) |
(i2c_sm == `SM_ADDR) & cnt7 |
write & cnt7;
assign sda_out = (target & read & ~cnt8) ? int_sda :
((addr_dec | target) ? 1'b0 : 1'b1);
always @(posedge scl_in or posedge cyc_rst)
if(cyc_rst == 1'b1)
target <= 1'b0;
else
if(ack & (i2c_sm == `SM_ADDR))
target <= addr_dec;
reg [7:0] int_reg0;
reg [7:0] int_reg1;
wire load_int_reg = ack & target & write;
always @(posedge scl_in or negedge rst_n)
if(~rst_n)
begin
int_reg0 <= 8'b0;
int_reg1 <= 8'b0;
end
else
if(load_int_reg)
case(cyc_cnt)
3'h0: int_reg0 <= rcv_reg[7:0];
3'h1: int_reg1 <= rcv_reg[7:0];
endcase
reg [7:0] main_out;
always @(cyc_cnt or rcv_reg0 or rcv_reg1)
case(cyc_cnt)
3'h0: main_out = rcv_reg0;
3'h1: main_out = rcv_reg1;
endcase
assign int_sda = main_out[7-rcv_cntr[2:0]];
endmodule | 17 |
138,857 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR/firfilt.v | 86,169,941 | firfilt.v | v | 237 | 125 | [] | ['general public license', 'free software foundation'] | [] | [(51, 161), (171, 236)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR/firfilt.v\n%Error: Exiting due to 3 error(s)\n' | 303,178 | module | module firX8R8 (
input clock,
input x_avail,
input signed [MBITS-1:0] x_real,
input signed [MBITS-1:0] x_imag,
output wire y_avail,
output wire signed [OBITS-1:0] y_real,
output wire signed [OBITS-1:0] y_imag);
localparam ADDRBITS = 8;
localparam MBITS = 18;
parameter
TAPS = NTAPS / 8,
ABITS = 24,
OBITS = 24,
NTAPS = 976;
reg [4:0] wstate;
reg [ADDRBITS-1:0] waddr;
wire weA, weB, weC, weD, weE, weF, weG, weH;
reg signed [ABITS-1:0] Racc, Iacc;
wire signed [ABITS-1:0] RaccA, RaccB, RaccC, RaccD, RaccE, RaccF, RaccG, RaccH;
wire signed [ABITS-1:0] IaccA, IaccB, IaccC, IaccD, IaccE, IaccF, IaccG, IaccH;
assign y_real = Racc[ABITS-1:0];
assign y_imag = Iacc[ABITS-1:0];
initial
begin
wstate = 0;
waddr = 0;
end
always @(posedge clock)
begin
if (wstate == 8) wstate <= wstate + 1'd1;
if (wstate == 9) begin
wstate <= 0;
waddr <= waddr + 1'd1;
end
if (x_avail)
begin
wstate <= wstate + 1'd1;
case (wstate)
0: begin
Racc <= RaccA;
Iacc <= IaccA;
end
1: begin
Racc <= Racc + RaccB;
Iacc <= Iacc + IaccB;
end
2: begin
Racc <= Racc + RaccC;
Iacc <= Iacc + IaccC;
end
3: begin
Racc <= Racc + RaccD;
Iacc <= Iacc + IaccD;
end
4: begin
Racc <= Racc + RaccE;
Iacc <= Iacc + IaccE;
end
5: begin
Racc <= Racc + RaccF;
Iacc <= Iacc + IaccF;
end
6: begin
Racc <= Racc + RaccG;
Iacc <= Iacc + IaccG;
end
7: begin
Racc <= Racc + RaccH;
Iacc <= Iacc + IaccH;
end
endcase
end
end
assign weA = (x_avail && wstate == 0);
assign weB = (x_avail && wstate == 1);
assign weC = (x_avail && wstate == 2);
assign weD = (x_avail && wstate == 3);
assign weE = (x_avail && wstate == 4);
assign weF = (x_avail && wstate == 5);
assign weG = (x_avail && wstate == 6);
assign weH = (x_avail && wstate == 7);
assign y_avail = (wstate == 8);
fir256 #("coefL8A.mif", ABITS, TAPS) A (clock, waddr, weA, x_real, x_imag, RaccA, IaccA);
fir256 #("coefL8B.mif", ABITS, TAPS) B (clock, waddr, weB, x_real, x_imag, RaccB, IaccB);
fir256 #("coefL8C.mif", ABITS, TAPS) C (clock, waddr, weC, x_real, x_imag, RaccC, IaccC);
fir256 #("coefL8D.mif", ABITS, TAPS) D (clock, waddr, weD, x_real, x_imag, RaccD, IaccD);
fir256 #("coefL8E.mif", ABITS, TAPS) E (clock, waddr, weE, x_real, x_imag, RaccE, IaccE);
fir256 #("coefL8F.mif", ABITS, TAPS) F (clock, waddr, weF, x_real, x_imag, RaccF, IaccF);
fir256 #("coefL8G.mif", ABITS, TAPS) G (clock, waddr, weG, x_real, x_imag, RaccG, IaccG);
fir256 #("coefL8H.mif", ABITS, TAPS) H (clock, waddr, weH, x_real, x_imag, RaccH, IaccH);
endmodule | module firX8R8 (
input clock,
input x_avail,
input signed [MBITS-1:0] x_real,
input signed [MBITS-1:0] x_imag,
output wire y_avail,
output wire signed [OBITS-1:0] y_real,
output wire signed [OBITS-1:0] y_imag); |
localparam ADDRBITS = 8;
localparam MBITS = 18;
parameter
TAPS = NTAPS / 8,
ABITS = 24,
OBITS = 24,
NTAPS = 976;
reg [4:0] wstate;
reg [ADDRBITS-1:0] waddr;
wire weA, weB, weC, weD, weE, weF, weG, weH;
reg signed [ABITS-1:0] Racc, Iacc;
wire signed [ABITS-1:0] RaccA, RaccB, RaccC, RaccD, RaccE, RaccF, RaccG, RaccH;
wire signed [ABITS-1:0] IaccA, IaccB, IaccC, IaccD, IaccE, IaccF, IaccG, IaccH;
assign y_real = Racc[ABITS-1:0];
assign y_imag = Iacc[ABITS-1:0];
initial
begin
wstate = 0;
waddr = 0;
end
always @(posedge clock)
begin
if (wstate == 8) wstate <= wstate + 1'd1;
if (wstate == 9) begin
wstate <= 0;
waddr <= waddr + 1'd1;
end
if (x_avail)
begin
wstate <= wstate + 1'd1;
case (wstate)
0: begin
Racc <= RaccA;
Iacc <= IaccA;
end
1: begin
Racc <= Racc + RaccB;
Iacc <= Iacc + IaccB;
end
2: begin
Racc <= Racc + RaccC;
Iacc <= Iacc + IaccC;
end
3: begin
Racc <= Racc + RaccD;
Iacc <= Iacc + IaccD;
end
4: begin
Racc <= Racc + RaccE;
Iacc <= Iacc + IaccE;
end
5: begin
Racc <= Racc + RaccF;
Iacc <= Iacc + IaccF;
end
6: begin
Racc <= Racc + RaccG;
Iacc <= Iacc + IaccG;
end
7: begin
Racc <= Racc + RaccH;
Iacc <= Iacc + IaccH;
end
endcase
end
end
assign weA = (x_avail && wstate == 0);
assign weB = (x_avail && wstate == 1);
assign weC = (x_avail && wstate == 2);
assign weD = (x_avail && wstate == 3);
assign weE = (x_avail && wstate == 4);
assign weF = (x_avail && wstate == 5);
assign weG = (x_avail && wstate == 6);
assign weH = (x_avail && wstate == 7);
assign y_avail = (wstate == 8);
fir256 #("coefL8A.mif", ABITS, TAPS) A (clock, waddr, weA, x_real, x_imag, RaccA, IaccA);
fir256 #("coefL8B.mif", ABITS, TAPS) B (clock, waddr, weB, x_real, x_imag, RaccB, IaccB);
fir256 #("coefL8C.mif", ABITS, TAPS) C (clock, waddr, weC, x_real, x_imag, RaccC, IaccC);
fir256 #("coefL8D.mif", ABITS, TAPS) D (clock, waddr, weD, x_real, x_imag, RaccD, IaccD);
fir256 #("coefL8E.mif", ABITS, TAPS) E (clock, waddr, weE, x_real, x_imag, RaccE, IaccE);
fir256 #("coefL8F.mif", ABITS, TAPS) F (clock, waddr, weF, x_real, x_imag, RaccF, IaccF);
fir256 #("coefL8G.mif", ABITS, TAPS) G (clock, waddr, weG, x_real, x_imag, RaccG, IaccG);
fir256 #("coefL8H.mif", ABITS, TAPS) H (clock, waddr, weH, x_real, x_imag, RaccH, IaccH);
endmodule | 17 |
138,858 | data/full_repos/permissive/86169941/Protocol 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR/firfilt.v | 86,169,941 | firfilt.v | v | 237 | 125 | [] | ['general public license', 'free software foundation'] | [] | [(51, 161), (171, 236)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.sv\n 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.v\n 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.sv\n obj_dir/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941\n obj_dir/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.v\n obj_dir/1/Mercury/Source/Mercury_V3.4/Polyphase_FIR,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Mercury/Source/Mercury_V3.4/Polyphase_FIR/firfilt.v\n%Error: Exiting due to 3 error(s)\n' | 303,178 | module | module fir256(
input clock,
input [ADDRBITS-1:0] waddr,
input we,
input signed [MBITS-1:0] x_real,
input signed [MBITS-1:0] x_imag,
output reg signed [ABITS-1:0] Raccum,
output reg signed [ABITS-1:0] Iaccum
);
localparam ADDRBITS = 8;
localparam MBITS = 18;
parameter MifFile = "xx.mif";
parameter ABITS = 0;
parameter TAPS = 0;
reg [ADDRBITS-1:0] raddr, caddr;
wire [MBITS*2-1:0] q;
reg [MBITS*2-1:0] reg_q;
wire signed [MBITS-1:0] q_real, q_imag;
wire signed [MBITS-1:0] coef;
reg signed [MBITS-1:0] reg_coef;
reg signed [MBITS*2-1:0] Rmult, Imult;
reg signed [MBITS*2-1:0] RmultSum, ImultSum;
reg [ADDRBITS:0] counter;
assign q_real = reg_q[MBITS*2-1:MBITS];
assign q_imag = reg_q[MBITS-1:0];
firromH #(MifFile) rom (caddr, clock, coef);
firram36 ram (clock, {x_real, x_imag}, raddr, waddr, we, q);
always @(posedge clock)
begin
if (we)
begin
counter = TAPS[ADDRBITS:0] + 4;
raddr = waddr;
caddr = 1'd0;
Raccum <= 0;
Iaccum <= 0;
Rmult <= 0;
Imult <= 0;
end
else
begin
if (counter < (TAPS[ADDRBITS:0] + 2))
begin
Rmult <= q_real * reg_coef;
Imult <= q_imag * reg_coef;
Raccum <= Raccum + Rmult[35:12] + Rmult[11];
Iaccum <= Iaccum + Imult[35:12] + Imult[11];
end
if (counter > 0)
begin
counter <= counter - 1'd1;
raddr <= raddr - 1'd1;
caddr <= caddr + 1'd1;
reg_q <= q;
reg_coef <= coef;
end
end
end
endmodule | module fir256(
input clock,
input [ADDRBITS-1:0] waddr,
input we,
input signed [MBITS-1:0] x_real,
input signed [MBITS-1:0] x_imag,
output reg signed [ABITS-1:0] Raccum,
output reg signed [ABITS-1:0] Iaccum
); |
localparam ADDRBITS = 8;
localparam MBITS = 18;
parameter MifFile = "xx.mif";
parameter ABITS = 0;
parameter TAPS = 0;
reg [ADDRBITS-1:0] raddr, caddr;
wire [MBITS*2-1:0] q;
reg [MBITS*2-1:0] reg_q;
wire signed [MBITS-1:0] q_real, q_imag;
wire signed [MBITS-1:0] coef;
reg signed [MBITS-1:0] reg_coef;
reg signed [MBITS*2-1:0] Rmult, Imult;
reg signed [MBITS*2-1:0] RmultSum, ImultSum;
reg [ADDRBITS:0] counter;
assign q_real = reg_q[MBITS*2-1:MBITS];
assign q_imag = reg_q[MBITS-1:0];
firromH #(MifFile) rom (caddr, clock, coef);
firram36 ram (clock, {x_real, x_imag}, raddr, waddr, we, q);
always @(posedge clock)
begin
if (we)
begin
counter = TAPS[ADDRBITS:0] + 4;
raddr = waddr;
caddr = 1'd0;
Raccum <= 0;
Iaccum <= 0;
Rmult <= 0;
Imult <= 0;
end
else
begin
if (counter < (TAPS[ADDRBITS:0] + 2))
begin
Rmult <= q_real * reg_coef;
Imult <= q_imag * reg_coef;
Raccum <= Raccum + Rmult[35:12] + Rmult[11];
Iaccum <= Iaccum + Imult[35:12] + Imult[11];
end
if (counter > 0)
begin
counter <= counter - 1'd1;
raddr <= raddr - 1'd1;
caddr <= caddr + 1'd1;
reg_q <= q;
reg_coef <= coef;
end
end
end
endmodule | 17 |
138,859 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_V1.1/debounce.v | 86,169,941 | debounce.v | v | 67 | 78 | [] | ['general public license', 'free software foundation'] | [] | [(45, 67)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1/debounce.v\n%Error: Exiting due to 3 error(s)\n' | 303,184 | module | module debounce(clean_pb, pb, clk);
output clean_pb;
input pb, clk;
parameter counter_bits = 18;
reg [counter_bits:0] count;
reg [3:0] pb_history;
reg clean_pb;
always @ (posedge clk)
begin
pb_history <= {pb_history[2:0], pb};
if (pb_history[3] != pb_history[2])
count <= 1'b0;
else if(count[counter_bits])
clean_pb <= pb_history[3];
else
count <= count + 1'b1;
end
endmodule | module debounce(clean_pb, pb, clk); |
output clean_pb;
input pb, clk;
parameter counter_bits = 18;
reg [counter_bits:0] count;
reg [3:0] pb_history;
reg clean_pb;
always @ (posedge clk)
begin
pb_history <= {pb_history[2:0], pb};
if (pb_history[3] != pb_history[2])
count <= 1'b0;
else if(count[counter_bits])
clean_pb <= pb_history[3];
else
count <= count + 1'b1;
end
endmodule | 17 |
138,860 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_V1.1/FIFO.v | 86,169,941 | FIFO.v | v | 89 | 78 | [] | ['general public license', 'free software foundation'] | [] | [(32, 89)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1/FIFO.v\n%Error: Exiting due to 3 error(s)\n' | 303,188 | module | module FIFO (rst, clk, full, usedw, empty, wrreq, data, rdreq, q);
parameter SZ = 2048;
parameter WD = 16;
localparam DP= clogb2(SZ-1);
input wire rst;
input wire clk;
output wire full;
output reg [DP-1:0] usedw;
output wire empty;
input wire wrreq;
input wire [WD-1:0] data;
input wire rdreq;
output reg [WD-1:0] q;
reg [WD-1:0] mem [0:SZ-1];
reg [DP-1:0] inptr, outptr;
assign full = (usedw == {DP{1'b1}});
assign empty = (usedw == 1'b0);
always @(posedge clk)
begin
if (rst)
inptr <= 1'b0;
else if (wrreq)
inptr <= inptr + 1'b1;
if (rst)
outptr <= 1'b0;
else if (rdreq)
outptr <= outptr + 1'b1;
if (rst)
usedw <= 1'b0;
else if (rdreq & !wrreq)
usedw <= usedw - 1'b1;
else if (wrreq & !rdreq)
usedw <= usedw + 1'b1;
if (wrreq)
mem[inptr] <= data;
if (rdreq)
q <= mem[outptr];
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | module FIFO (rst, clk, full, usedw, empty, wrreq, data, rdreq, q); |
parameter SZ = 2048;
parameter WD = 16;
localparam DP= clogb2(SZ-1);
input wire rst;
input wire clk;
output wire full;
output reg [DP-1:0] usedw;
output wire empty;
input wire wrreq;
input wire [WD-1:0] data;
input wire rdreq;
output reg [WD-1:0] q;
reg [WD-1:0] mem [0:SZ-1];
reg [DP-1:0] inptr, outptr;
assign full = (usedw == {DP{1'b1}});
assign empty = (usedw == 1'b0);
always @(posedge clk)
begin
if (rst)
inptr <= 1'b0;
else if (wrreq)
inptr <= inptr + 1'b1;
if (rst)
outptr <= 1'b0;
else if (rdreq)
outptr <= outptr + 1'b1;
if (rst)
usedw <= 1'b0;
else if (rdreq & !wrreq)
usedw <= usedw - 1'b1;
else if (wrreq & !rdreq)
usedw <= usedw + 1'b1;
if (wrreq)
mem[inptr] <= data;
if (rdreq)
q <= mem[outptr];
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | 17 |
138,861 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_V1.1/FIFO.v | 86,169,941 | FIFO.v | v | 89 | 78 | [] | ['general public license', 'free software foundation'] | [] | [(32, 89)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1/FIFO.v\n%Error: Exiting due to 3 error(s)\n' | 303,188 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,864 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_V1.1/Tx_fifo_ctrl.v | 86,169,941 | Tx_fifo_ctrl.v | v | 412 | 100 | [] | ['general public license', 'free software foundation'] | [] | [(55, 412)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1/Tx_fifo_ctrl.v\n%Error: Exiting due to 3 error(s)\n' | 303,201 | module | module Tx_fifo_ctrl(IF_reset, IF_clk, Tx_fifo_wdata, Tx_fifo_wreq, Tx_fifo_full, Tx_fifo_used,
Tx_fifo_clr, Tx_IQ_mic_rdy, Tx_IQ_mic_ack,
IF_chan, IF_last_chan, Tx_IQ_mic_data,
clean_dash, clean_dot, clean_PTT_in, ADC_OVERLOAD, ADC_OVERLOAD2,
ADC_OVERLOAD3, ADC_OVERLOAD4,Penny_serialno, Merc_serialno, Merc2_version,
Merc3_version, Merc4_version, Metis_serialno, Penny_ALC);
parameter RX_FIFO_SZ = 2048;
parameter TX_FIFO_SZ = 1024;
parameter IF_TPD = 1;
localparam RFSZ = clogb2(RX_FIFO_SZ-1);
localparam TFSZ = clogb2(TX_FIFO_SZ-1);
input wire IF_reset;
input wire IF_clk;
output reg [15:0] Tx_fifo_wdata;
output reg Tx_fifo_wreq;
input wire Tx_fifo_full;
input wire [TFSZ-1:0] Tx_fifo_used;
output reg Tx_fifo_clr;
input wire Tx_IQ_mic_rdy;
output wire Tx_IQ_mic_ack;
output reg [2:0] IF_chan;
input wire [2:0] IF_last_chan;
input wire [63:0] Tx_IQ_mic_data;
input wire clean_dash;
input wire clean_dot;
input wire clean_PTT_in;
input wire ADC_OVERLOAD;
input wire ADC_OVERLOAD2;
input wire ADC_OVERLOAD3;
input wire ADC_OVERLOAD4;
input wire [7:0] Penny_serialno;
input wire [7:0] Merc_serialno;
input wire [7:0] Merc2_version;
input wire [7:0] Merc3_version;
input wire [7:0] Merc4_version;
input wire [7:0] Metis_serialno;
input wire [11:0] Penny_ALC;
reg [3:0] AD_state;
reg [3:0] AD_state_next;
reg [5:0] AD_timer;
localparam MAX_ADDR = 4;
reg [4:0] tx_addr;
reg [7:0] C1_DATA, C2_DATA, C3_DATA, C4_DATA;
localparam AD_IDLE = 0,
AD_SEND_SYNC1 = 1,
AD_SEND_SYNC2 = 2,
AD_SEND_CTL1_2 = 3,
AD_SEND_CTL3_4 = 4,
AD_SEND_MJ_RDY = 5,
AD_SEND_MJ1 = 6,
AD_SEND_MJ2 = 7,
AD_SEND_MJ3 = 8,
AD_SEND_PJ = 9,
AD_WAIT = 10,
AD_LOOP_CHK = 11,
AD_PAD_CHK = 12,
AD_ERR = 13;
reg [6:0] loop_cnt, num_loops;
reg [5:0] pad_cnt, pad_loops;
always @*
begin
case (IF_last_chan)
0: num_loops = 62;
1: num_loops = 35;
2: num_loops = 24;
3: num_loops = 18;
default: num_loops = 62;
endcase
end
always @*
begin
case (IF_last_chan)
0: pad_loops = 0;
1: pad_loops = 0;
2: pad_loops = 4;
3: pad_loops = 10;
default: pad_loops = 0;
endcase
end
assign Tx_IQ_mic_ack = (AD_state == AD_WAIT);
always @ (posedge IF_clk)
begin
if ((AD_state == AD_IDLE) || (AD_state == AD_SEND_SYNC1))
loop_cnt <= #IF_TPD 1'b0;
else if (AD_state == AD_LOOP_CHK)
loop_cnt <= #IF_TPD loop_cnt + 1'b1;
if ((AD_state == AD_IDLE) || (AD_state == AD_SEND_SYNC1))
pad_cnt <= #IF_TPD 1'b0;
else if (AD_state == AD_PAD_CHK)
pad_cnt <= #IF_TPD pad_cnt + 1'b1;
if (IF_reset)
AD_state <= #IF_TPD AD_IDLE;
else
AD_state <= #IF_TPD AD_state_next;
if (IF_reset)
tx_addr <= #IF_TPD 1'b0;
else if (AD_state == AD_SEND_CTL3_4)
begin
if (tx_addr != MAX_ADDR)
tx_addr <= #IF_TPD tx_addr + 1'b1;
else
tx_addr <= #IF_TPD 1'b0;
end
if (IF_reset)
AD_timer <= #IF_TPD 0;
else if (AD_state == AD_ERR)
AD_timer <= #IF_TPD 0;
else if (!AD_timer[5])
AD_timer <= #IF_TPD AD_timer + 1'b1;
Tx_fifo_clr <= #IF_TPD (AD_state == AD_ERR);
if (IF_reset)
IF_chan <= #IF_TPD 1'b0;
else if (AD_state == AD_SEND_MJ_RDY)
IF_chan <= #IF_TPD 1'b0;
else if (AD_state == AD_SEND_MJ3)
IF_chan <= #IF_TPD IF_chan + 1'b1;
end
always @*
begin
case (tx_addr)
0:
begin
C1_DATA = {7'b0,ADC_OVERLOAD};
C2_DATA = Merc_serialno;
C3_DATA = Penny_serialno;
C4_DATA = Metis_serialno;
end
1:
begin
C1_DATA = {4'b0,Penny_ALC[11:8]};
C2_DATA = Penny_ALC[7:0];
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
2:
begin
C1_DATA = 8'b0;
C2_DATA = 8'b0;
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
3:
begin
C1_DATA = 8'b0;
C2_DATA = 8'b0;
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
4:
begin
C1_DATA = {Merc_serialno, ADC_OVERLOAD};
C2_DATA = {Merc2_version, ADC_OVERLOAD2};
C3_DATA = {Merc3_version, ADC_OVERLOAD3};
C4_DATA = {Merc4_version, ADC_OVERLOAD4};
end
default:
begin
C1_DATA = 8'b0;
C2_DATA = 8'b0;
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
endcase
end
always @*
begin
case (AD_state)
AD_IDLE:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (IF_reset || !AD_timer[5])
AD_state_next = AD_IDLE;
else
AD_state_next = AD_SEND_SYNC1;
end
AD_SEND_SYNC1:
begin
Tx_fifo_wdata = 16'h7F7F;
Tx_fifo_wreq = 1'b1;
if (Tx_fifo_full)
AD_state_next = AD_ERR;
else
AD_state_next = AD_SEND_SYNC2;
end
AD_SEND_SYNC2:
begin
Tx_fifo_wdata = {8'h7F, tx_addr, clean_dot, clean_dash, clean_PTT_in};
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_CTL1_2;
end
AD_SEND_CTL1_2:
begin
Tx_fifo_wdata = {C1_DATA, C2_DATA};
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_CTL3_4;
end
AD_SEND_CTL3_4:
begin
Tx_fifo_wdata = {C3_DATA, C4_DATA};
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_MJ_RDY;
end
AD_SEND_MJ_RDY:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (!Tx_IQ_mic_rdy)
AD_state_next = AD_SEND_MJ_RDY;
else
AD_state_next = AD_SEND_MJ1;
end
AD_SEND_MJ1:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[63:48];
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_MJ2;
end
AD_SEND_MJ2:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[47:32];
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_MJ3;
end
AD_SEND_MJ3:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[31:16];
Tx_fifo_wreq = 1'b1;
if (IF_chan != IF_last_chan)
AD_state_next = AD_SEND_MJ1;
else
AD_state_next = AD_SEND_PJ;
end
AD_SEND_PJ:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[15:0];
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_WAIT;
end
AD_WAIT:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (Tx_IQ_mic_rdy)
AD_state_next = AD_WAIT;
else
AD_state_next = AD_LOOP_CHK;
end
AD_LOOP_CHK:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (loop_cnt != num_loops)
AD_state_next = AD_SEND_MJ_RDY;
else
AD_state_next = AD_PAD_CHK;
end
AD_PAD_CHK:
begin
Tx_fifo_wdata = 16'b0;
Tx_fifo_wreq = (pad_cnt != pad_loops);
if (pad_cnt != pad_loops)
AD_state_next = AD_PAD_CHK;
else
AD_state_next = AD_SEND_SYNC1;
end
AD_ERR:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
AD_state_next = AD_IDLE;
end
default:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
AD_state_next = AD_IDLE;
end
endcase
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | module Tx_fifo_ctrl(IF_reset, IF_clk, Tx_fifo_wdata, Tx_fifo_wreq, Tx_fifo_full, Tx_fifo_used,
Tx_fifo_clr, Tx_IQ_mic_rdy, Tx_IQ_mic_ack,
IF_chan, IF_last_chan, Tx_IQ_mic_data,
clean_dash, clean_dot, clean_PTT_in, ADC_OVERLOAD, ADC_OVERLOAD2,
ADC_OVERLOAD3, ADC_OVERLOAD4,Penny_serialno, Merc_serialno, Merc2_version,
Merc3_version, Merc4_version, Metis_serialno, Penny_ALC); |
parameter RX_FIFO_SZ = 2048;
parameter TX_FIFO_SZ = 1024;
parameter IF_TPD = 1;
localparam RFSZ = clogb2(RX_FIFO_SZ-1);
localparam TFSZ = clogb2(TX_FIFO_SZ-1);
input wire IF_reset;
input wire IF_clk;
output reg [15:0] Tx_fifo_wdata;
output reg Tx_fifo_wreq;
input wire Tx_fifo_full;
input wire [TFSZ-1:0] Tx_fifo_used;
output reg Tx_fifo_clr;
input wire Tx_IQ_mic_rdy;
output wire Tx_IQ_mic_ack;
output reg [2:0] IF_chan;
input wire [2:0] IF_last_chan;
input wire [63:0] Tx_IQ_mic_data;
input wire clean_dash;
input wire clean_dot;
input wire clean_PTT_in;
input wire ADC_OVERLOAD;
input wire ADC_OVERLOAD2;
input wire ADC_OVERLOAD3;
input wire ADC_OVERLOAD4;
input wire [7:0] Penny_serialno;
input wire [7:0] Merc_serialno;
input wire [7:0] Merc2_version;
input wire [7:0] Merc3_version;
input wire [7:0] Merc4_version;
input wire [7:0] Metis_serialno;
input wire [11:0] Penny_ALC;
reg [3:0] AD_state;
reg [3:0] AD_state_next;
reg [5:0] AD_timer;
localparam MAX_ADDR = 4;
reg [4:0] tx_addr;
reg [7:0] C1_DATA, C2_DATA, C3_DATA, C4_DATA;
localparam AD_IDLE = 0,
AD_SEND_SYNC1 = 1,
AD_SEND_SYNC2 = 2,
AD_SEND_CTL1_2 = 3,
AD_SEND_CTL3_4 = 4,
AD_SEND_MJ_RDY = 5,
AD_SEND_MJ1 = 6,
AD_SEND_MJ2 = 7,
AD_SEND_MJ3 = 8,
AD_SEND_PJ = 9,
AD_WAIT = 10,
AD_LOOP_CHK = 11,
AD_PAD_CHK = 12,
AD_ERR = 13;
reg [6:0] loop_cnt, num_loops;
reg [5:0] pad_cnt, pad_loops;
always @*
begin
case (IF_last_chan)
0: num_loops = 62;
1: num_loops = 35;
2: num_loops = 24;
3: num_loops = 18;
default: num_loops = 62;
endcase
end
always @*
begin
case (IF_last_chan)
0: pad_loops = 0;
1: pad_loops = 0;
2: pad_loops = 4;
3: pad_loops = 10;
default: pad_loops = 0;
endcase
end
assign Tx_IQ_mic_ack = (AD_state == AD_WAIT);
always @ (posedge IF_clk)
begin
if ((AD_state == AD_IDLE) || (AD_state == AD_SEND_SYNC1))
loop_cnt <= #IF_TPD 1'b0;
else if (AD_state == AD_LOOP_CHK)
loop_cnt <= #IF_TPD loop_cnt + 1'b1;
if ((AD_state == AD_IDLE) || (AD_state == AD_SEND_SYNC1))
pad_cnt <= #IF_TPD 1'b0;
else if (AD_state == AD_PAD_CHK)
pad_cnt <= #IF_TPD pad_cnt + 1'b1;
if (IF_reset)
AD_state <= #IF_TPD AD_IDLE;
else
AD_state <= #IF_TPD AD_state_next;
if (IF_reset)
tx_addr <= #IF_TPD 1'b0;
else if (AD_state == AD_SEND_CTL3_4)
begin
if (tx_addr != MAX_ADDR)
tx_addr <= #IF_TPD tx_addr + 1'b1;
else
tx_addr <= #IF_TPD 1'b0;
end
if (IF_reset)
AD_timer <= #IF_TPD 0;
else if (AD_state == AD_ERR)
AD_timer <= #IF_TPD 0;
else if (!AD_timer[5])
AD_timer <= #IF_TPD AD_timer + 1'b1;
Tx_fifo_clr <= #IF_TPD (AD_state == AD_ERR);
if (IF_reset)
IF_chan <= #IF_TPD 1'b0;
else if (AD_state == AD_SEND_MJ_RDY)
IF_chan <= #IF_TPD 1'b0;
else if (AD_state == AD_SEND_MJ3)
IF_chan <= #IF_TPD IF_chan + 1'b1;
end
always @*
begin
case (tx_addr)
0:
begin
C1_DATA = {7'b0,ADC_OVERLOAD};
C2_DATA = Merc_serialno;
C3_DATA = Penny_serialno;
C4_DATA = Metis_serialno;
end
1:
begin
C1_DATA = {4'b0,Penny_ALC[11:8]};
C2_DATA = Penny_ALC[7:0];
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
2:
begin
C1_DATA = 8'b0;
C2_DATA = 8'b0;
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
3:
begin
C1_DATA = 8'b0;
C2_DATA = 8'b0;
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
4:
begin
C1_DATA = {Merc_serialno, ADC_OVERLOAD};
C2_DATA = {Merc2_version, ADC_OVERLOAD2};
C3_DATA = {Merc3_version, ADC_OVERLOAD3};
C4_DATA = {Merc4_version, ADC_OVERLOAD4};
end
default:
begin
C1_DATA = 8'b0;
C2_DATA = 8'b0;
C3_DATA = 8'b0;
C4_DATA = 8'b0;
end
endcase
end
always @*
begin
case (AD_state)
AD_IDLE:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (IF_reset || !AD_timer[5])
AD_state_next = AD_IDLE;
else
AD_state_next = AD_SEND_SYNC1;
end
AD_SEND_SYNC1:
begin
Tx_fifo_wdata = 16'h7F7F;
Tx_fifo_wreq = 1'b1;
if (Tx_fifo_full)
AD_state_next = AD_ERR;
else
AD_state_next = AD_SEND_SYNC2;
end
AD_SEND_SYNC2:
begin
Tx_fifo_wdata = {8'h7F, tx_addr, clean_dot, clean_dash, clean_PTT_in};
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_CTL1_2;
end
AD_SEND_CTL1_2:
begin
Tx_fifo_wdata = {C1_DATA, C2_DATA};
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_CTL3_4;
end
AD_SEND_CTL3_4:
begin
Tx_fifo_wdata = {C3_DATA, C4_DATA};
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_MJ_RDY;
end
AD_SEND_MJ_RDY:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (!Tx_IQ_mic_rdy)
AD_state_next = AD_SEND_MJ_RDY;
else
AD_state_next = AD_SEND_MJ1;
end
AD_SEND_MJ1:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[63:48];
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_MJ2;
end
AD_SEND_MJ2:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[47:32];
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_SEND_MJ3;
end
AD_SEND_MJ3:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[31:16];
Tx_fifo_wreq = 1'b1;
if (IF_chan != IF_last_chan)
AD_state_next = AD_SEND_MJ1;
else
AD_state_next = AD_SEND_PJ;
end
AD_SEND_PJ:
begin
Tx_fifo_wdata = Tx_IQ_mic_data[15:0];
Tx_fifo_wreq = 1'b1;
AD_state_next = AD_WAIT;
end
AD_WAIT:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (Tx_IQ_mic_rdy)
AD_state_next = AD_WAIT;
else
AD_state_next = AD_LOOP_CHK;
end
AD_LOOP_CHK:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
if (loop_cnt != num_loops)
AD_state_next = AD_SEND_MJ_RDY;
else
AD_state_next = AD_PAD_CHK;
end
AD_PAD_CHK:
begin
Tx_fifo_wdata = 16'b0;
Tx_fifo_wreq = (pad_cnt != pad_loops);
if (pad_cnt != pad_loops)
AD_state_next = AD_PAD_CHK;
else
AD_state_next = AD_SEND_SYNC1;
end
AD_ERR:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
AD_state_next = AD_IDLE;
end
default:
begin
Tx_fifo_wdata = {16{1'bx}};
Tx_fifo_wreq = 1'b0;
AD_state_next = AD_IDLE;
end
endcase
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | 17 |
138,865 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_V1.1/Tx_fifo_ctrl.v | 86,169,941 | Tx_fifo_ctrl.v | v | 412 | 100 | [] | ['general public license', 'free software foundation'] | [] | [(55, 412)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_V1.1,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1/Tx_fifo_ctrl.v\n%Error: Exiting due to 3 error(s)\n' | 303,201 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,866 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_V1.1/common/cdc_mcp.v | 86,169,941 | cdc_mcp.v | v | 71 | 106 | [] | ['general public license', 'free software foundation'] | [] | null | line:40: before: "A" | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_V1.1/common,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.1/common/cdc_mcp.v\n%Error: Exiting due to 3 error(s)\n' | 303,203 | module | module cdc_mcp #(parameter SIZE=1, TPD = 0.5)
(input wire a_rst, a_clk,
input wire [SIZE-1:0] a_data,
input wire a_data_rdy,
input wire b_rst, b_clk,
output reg [SIZE-1:0] b_data,
output reg b_data_ack);
reg a_rdy;
wire a_data_ack, b_data_rdy;
wire b_data_rdy_pulse;
always @(posedge a_clk)
begin
if (a_rst)
a_rdy <= #TPD 1'b0;
else if (a_data_rdy)
a_rdy <= #TPD 1'b1;
else if (a_data_ack)
a_rdy <= #TPD 1'b0;
end
cdc_sync rdy (.siga(a_rdy), .rstb(b_rst), .clkb(b_clk), .sigb(b_data_rdy));
pulsegen pls (.sig(b_data_rdy), .rst(b_rst), .clk(b_clk), .pulse(b_data_rdy_pulse));
cdc_sync ack (.siga(b_data_ack), .rstb(a_rst), .clkb(a_clk), .sigb(a_data_ack));
always @(posedge b_clk)
begin
if (b_rst)
b_data <= #TPD 1'b0;
else if (b_data_rdy_pulse)
b_data <= #TPD a_data;
if (b_rst)
b_data_ack <= #TPD 1'b0;
else
b_data_ack <= #TPD b_data_rdy;
end
endmodule | module cdc_mcp #(parameter SIZE=1, TPD = 0.5)
(input wire a_rst, a_clk,
input wire [SIZE-1:0] a_data,
input wire a_data_rdy,
input wire b_rst, b_clk,
output reg [SIZE-1:0] b_data,
output reg b_data_ack); |
reg a_rdy;
wire a_data_ack, b_data_rdy;
wire b_data_rdy_pulse;
always @(posedge a_clk)
begin
if (a_rst)
a_rdy <= #TPD 1'b0;
else if (a_data_rdy)
a_rdy <= #TPD 1'b1;
else if (a_data_ack)
a_rdy <= #TPD 1'b0;
end
cdc_sync rdy (.siga(a_rdy), .rstb(b_rst), .clkb(b_clk), .sigb(b_data_rdy));
pulsegen pls (.sig(b_data_rdy), .rst(b_rst), .clk(b_clk), .pulse(b_data_rdy_pulse));
cdc_sync ack (.siga(b_data_ack), .rstb(a_rst), .clkb(a_clk), .sigb(a_data_ack));
always @(posedge b_clk)
begin
if (b_rst)
b_data <= #TPD 1'b0;
else if (b_data_rdy_pulse)
b_data <= #TPD a_data;
if (b_rst)
b_data_ack <= #TPD 1'b0;
else
b_data_ack <= #TPD b_data_rdy;
end
endmodule | 17 |
138,867 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_V1.2/Rx_MAC.v | 86,169,941 | Rx_MAC.v | v | 666 | 130 | [] | ['general public license', 'free software foundation'] | [] | [(151, 665)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_V1.2,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_V1.2/Rx_MAC.v\n%Error: Exiting due to 3 error(s)\n' | 303,233 | module | module Rx_MAC (PHY_RX_CLOCK, PHY_data_clock, PHY_DV, PHY_RX, broadcast, ARP_request,
ping_request, ping_data, Rx_enable, this_MAC, DHCP_offer, DHCP_ACK, DHCP_NAK,
RS232_Tx, RS232_data, ARP_PC_MAC, ARP_PC_IP, This_IP, Ping_PC_IP, Ping_PC_MAC,
YIADDR, This_MAC, METIS_discovery, METIS_discover_sent, PC_IP, PC_MAC, Port, Length, data_match,
PHY_100T_state, Rx_fifo_data, seq_error, run, wide_spectrum, IP_lease, DHCP_IP, DHCP_MAC,
erase, erase_ACK, num_blocks, EPCS_FIFO_enable);
input PHY_RX_CLOCK;
input PHY_data_clock;
input PHY_DV;
input [3:0]PHY_RX;
input [47:0]This_MAC;
input [31:0]This_IP;
input METIS_discover_sent;
output [15:0]Port;
input erase_ACK;
output reg broadcast;
output reg ARP_request;
output reg ping_request;
output reg [7:0]ping_data[0:59];
output reg Rx_enable;
output wire this_MAC;
output reg DHCP_offer;
output reg RS232_Tx;
output reg [7:0]RS232_data;
output reg [31:0]YIADDR;
output reg DHCP_ACK;
output reg DHCP_NAK;
output reg METIS_discovery;
output reg [31:0]PC_IP;
output reg [47:0]PC_MAC;
output reg [47:0]ARP_PC_MAC;
output reg [31:0]ARP_PC_IP;
output reg [31:0]Ping_PC_IP;
output reg [47:0]Ping_PC_MAC;
output reg [15:0]Length;
output reg data_match;
output reg PHY_100T_state;
output wire [7:0]Rx_fifo_data;
output seq_error;
output reg run;
output reg wide_spectrum;
output reg [31:0]IP_lease;
output reg [31:0]DHCP_IP;
output reg [47:0]DHCP_MAC;
output reg erase;
output reg [31:0]num_blocks;
output reg EPCS_FIFO_enable;
reg [111:0] PHY_output;
reg [4:0] PHY_Rx_state;
reg [9:0] left_shift;
reg [31:0] PC_sequence_number;
reg [11:0] PHY_data_count;
reg [8:0] EPCS_data_count;
reg [47:0] FromMAC;
reg [31:0] FromIP;
reg [7:0] ping_count;
reg [31:0]temp_YIADDR;
reg [15:0]UDP_check;
reg [31:0]To_IP;
reg [7:0]skip;
reg [15:0] FromPort;
reg [15:0] ToPort;
reg [31:0]temp_PC_IP;
reg [47:0]temp_PC_MAC;
reg [15:0]temp_Port;
localparam Rx_port = 1024;
localparam START = 5'd0,
GET_TYPE = 5'd1,
ARP = 5'd2,
UDP = 5'd3,
METIS_DISCOVERY = 5'd4,
SEND_TO_FIFO = 5'd5,
DHCP = 5'd6,
PING = 5'd7,
PROGRAM_FIFO = 5'd8,
ERASE = 5'd9,
RETURN = 5'd10;
localparam Broadcast = 48'hFF_FF_FF_FF_FF_FF;
wire [3:0] PHY_RX;
wire [3:0] PHY_data_h;
wire [3:0] PHY_data_l;
reg [7:0] PHY_byte;
reg PHY_Rx_fifo_reset;
reg [31:0]prev_seq_number;
reg seq_error;
always @ (negedge PHY_RX_CLOCK)
begin
case (PHY_100T_state)
0: begin
if (PHY_DV) begin
PHY_byte <= {PHY_byte[7:4],PHY_RX};
PHY_100T_state <= 1'd1;
end
end
1: begin
PHY_byte <= {PHY_RX, PHY_byte[3:0]};
PHY_100T_state <= 1'd0;
end
endcase
end
always @ (posedge PHY_RX_CLOCK)
if (PHY_100T_state == 0) PHY_output <= {PHY_output[103:0], PHY_byte};
assign Rx_fifo_data = PHY_output[7:0];
always @ (negedge PHY_data_clock)
begin
case (PHY_Rx_state)
START:
begin
broadcast <= 1'b0;
left_shift <= 0;
ARP_request <= 1'b0;
ping_request <= 1'b0;
this_MAC <= 1'b0;
PHY_data_count <= 0;
EPCS_data_count <= 0;
RS232_Tx <= 0;
ping_count <= 0;
erase <= 0;
if (PHY_output[63:0] == {16'h55_D5, Broadcast} ) begin
broadcast <= 1'b1;
PHY_Rx_state <= GET_TYPE;
end
else if (PHY_output[63:0] == {16'h55_D5, This_MAC}) begin
this_MAC <= 1'b1;
PHY_Rx_state <= GET_TYPE;
end
else PHY_Rx_state <= START;
end
GET_TYPE:
begin
data_match <= 1'b1;
case(left_shift)
13: begin
FromMAC <= PHY_output[111:64];
Length <= PHY_output[31:16];
if (PHY_output[63:48] == 16'h0806 && broadcast) begin
left_shift <= 0;
PHY_Rx_state <= ARP;
end
else begin
UDP_check <= PHY_output[63:48];
left_shift <= left_shift + 1'b1;
end
end
27: begin
if (PHY_output[87:80] == 8'h11 && UDP_check == 16'h0800 ) begin
FromIP <= PHY_output[63:32];
To_IP <= PHY_output[31:0];
left_shift <= 0;
PHY_Rx_state <= UDP;
end
else left_shift <= left_shift + 1'b1;
end
30: begin
if (PHY_output[111:104] == 8'h01 && PHY_output[55:24] == This_IP)begin
if (PHY_output[23:16] == 8'h08) begin
Ping_PC_IP <= PHY_output[87:56];
Ping_PC_MAC <= FromMAC;
left_shift <= left_shift + 1'b1;
end
else if (PHY_output[23:16] == 8'h03) begin
run <= 1'b0;
wide_spectrum <= 1'b0;
PHY_Rx_state <= RETURN;
end
end
else PHY_Rx_state <= RETURN;
end
31: begin
left_shift <= 0;
PHY_Rx_state <= PING;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= GET_TYPE;
end
endcase
end
ARP:
begin
case (left_shift)
13: begin
if ( PHY_output[111:96] == 16'h0001) begin
ARP_PC_MAC <= PHY_output[95:48];
ARP_PC_IP <= PHY_output[47:16];
left_shift <= left_shift + 1'b1;
end
else PHY_Rx_state <= RETURN;
end
21: begin
if (PHY_output[31:0] == This_IP)
ARP_request <= 1'b1;
PHY_Rx_state <= RETURN;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= ARP;
end
endcase
end
UDP:
begin
case (left_shift)
13: begin
FromPort <= PHY_output[111:96];
ToPort <= PHY_output[95:80];
if (PHY_output[95:80] == 16'h0044 && PHY_output[47:40] == 8'h02)begin
left_shift <= 0;
PHY_Rx_state <= DHCP;
end
else left_shift <= left_shift + 1'b1;
end
15: begin
if (PHY_output[63:48] == 16'hEFFE && ToPort == Rx_port) begin
if (To_IP == This_IP) begin
case (PHY_output[47:40])
1: begin
if (PHY_output[39:32] == 8'h02) begin
PC_sequence_number <= PHY_output[31:0];
PHY_Rx_state <= SEND_TO_FIFO;
end
end
3: begin
num_blocks <= PHY_output[31:0];
if (PHY_output[39:32] == 8'd1) begin
PHY_Rx_state <= PROGRAM_FIFO;
end
else if (PHY_output[39:32] == 8'd2) begin
erase <= 1'b1;
PHY_Rx_state <= ERASE;
end
end
4: begin
run <= PHY_output[32];
wide_spectrum <= PHY_output[33];
PC_IP <= FromIP;
PC_MAC <= FromMAC;
Port <= FromPort;
PHY_Rx_state <= RETURN;
end
default: PHY_Rx_state <= RETURN;
endcase
end
else if (broadcast) begin
if (PHY_output[47:40] == 8'h02) begin
left_shift <= 0;
temp_PC_IP <= PC_IP;
temp_PC_MAC <= PC_MAC;
temp_Port <= Port;
PHY_Rx_state <= METIS_DISCOVERY;
end
end
else PHY_Rx_state <= RETURN;
end
else PHY_Rx_state <= RETURN;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= UDP;
end
endcase
end
METIS_DISCOVERY:
begin
case (left_shift)
1: begin
PC_IP <= FromIP;
PC_MAC <= FromMAC;
Port <= FromPort;
METIS_discovery <= 1'b1;
left_shift <= left_shift + 1'b1;
end
3: begin
METIS_discovery <= 0;
PC_IP <= temp_PC_IP;
PC_MAC <= temp_PC_MAC;
Port <= temp_Port;
PHY_Rx_state <= RETURN;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= METIS_DISCOVERY;
end
endcase
end
SEND_TO_FIFO:
begin
if (PC_sequence_number != prev_seq_number + 1'b1)
seq_error <= 1'b1;
if (PHY_data_count == 1024) begin
data_match <= 1'b0;
Rx_enable <= 0;
prev_seq_number <= PC_sequence_number;
seq_error <= 1'b0;
PHY_Rx_state <= START;
end
else begin
Rx_enable <= 1'b1;
PHY_data_count <= PHY_data_count + 1'b1;
end
end
DHCP:
begin
DHCP_offer <= 0;
DHCP_ACK <= 0;
DHCP_NAK <= 0;
DHCP_MAC <= FromMAC;
case (left_shift)
13: begin
temp_YIADDR <= PHY_output[31:0];
left_shift <= left_shift + 1'b1;
end
27: begin
if (PHY_output[47:0] == This_MAC) begin
YIADDR <= temp_YIADDR;
left_shift <= left_shift + 1'b1;
end
else PHY_Rx_state <= RETURN;
end
236: begin
if (PHY_output[23:0] == 24'h35_01_02) begin
DHCP_offer <= 1'b1;
left_shift <= left_shift + 1'b1;
end
else if (PHY_output[23:0] == 24'h35_01_05) begin
DHCP_ACK <= 1'b1;
PHY_Rx_state <= RETURN;
end
else if (PHY_output[23:0] == 24'h35_01_06) begin
DHCP_NAK <= 1'b1;
PHY_Rx_state <= RETURN;
end
end
238: begin
if (PHY_output[15:8] == 8'hFF)
PHY_Rx_state <= RETURN;
else if (PHY_output[15:0] == 16'h3304) begin
left_shift <= 241;
end
else if (PHY_output[15:0] == 16'h3604) begin
left_shift <= 245;
end
else begin
skip <= PHY_output[7:0];
left_shift <= left_shift + 1'b1;
end
end
239: begin
if (skip - 1 == 0) left_shift <= 240;
else begin
skip <= skip - 1'b1;
left_shift <= 239;
end
end
240: left_shift <= 238;
241: left_shift <= left_shift + 1'b1;
244: begin
IP_lease <= PHY_output[31:0];
left_shift <= 240;
end
245: left_shift <= left_shift + 1'b1;
248: begin
DHCP_IP <= PHY_output[31:0];
left_shift <= 240;
end
default: begin
left_shift <= left_shift + 1'b1;
RS232_Tx <= 1'b0;
PHY_Rx_state <= DHCP;
end
endcase
end
PING:
begin
if (ping_count == (Length - 24)) begin
ping_request <= 1'b1;
PHY_Rx_state <= RETURN;
end
else begin
ping_data[ping_count] <= PHY_output[7:0];
ping_count <= ping_count + 1'b1;
PHY_Rx_state <= PING;
end
end
PROGRAM_FIFO:
begin
if (EPCS_data_count == 9'd256) begin
EPCS_data_count <= 0;
EPCS_FIFO_enable <= 0;
PHY_Rx_state <= RETURN;
end
else begin
EPCS_FIFO_enable <= 1'b1;
EPCS_data_count <= EPCS_data_count + 9'd1;
end
end
ERASE: if (erase_ACK) PHY_Rx_state <= RETURN;
RETURN:
begin
data_match <= 1'b0;
PHY_Rx_state <= START;
end
default: PHY_Rx_state <= START;
endcase
end
endmodule | module Rx_MAC (PHY_RX_CLOCK, PHY_data_clock, PHY_DV, PHY_RX, broadcast, ARP_request,
ping_request, ping_data, Rx_enable, this_MAC, DHCP_offer, DHCP_ACK, DHCP_NAK,
RS232_Tx, RS232_data, ARP_PC_MAC, ARP_PC_IP, This_IP, Ping_PC_IP, Ping_PC_MAC,
YIADDR, This_MAC, METIS_discovery, METIS_discover_sent, PC_IP, PC_MAC, Port, Length, data_match,
PHY_100T_state, Rx_fifo_data, seq_error, run, wide_spectrum, IP_lease, DHCP_IP, DHCP_MAC,
erase, erase_ACK, num_blocks, EPCS_FIFO_enable); |
input PHY_RX_CLOCK;
input PHY_data_clock;
input PHY_DV;
input [3:0]PHY_RX;
input [47:0]This_MAC;
input [31:0]This_IP;
input METIS_discover_sent;
output [15:0]Port;
input erase_ACK;
output reg broadcast;
output reg ARP_request;
output reg ping_request;
output reg [7:0]ping_data[0:59];
output reg Rx_enable;
output wire this_MAC;
output reg DHCP_offer;
output reg RS232_Tx;
output reg [7:0]RS232_data;
output reg [31:0]YIADDR;
output reg DHCP_ACK;
output reg DHCP_NAK;
output reg METIS_discovery;
output reg [31:0]PC_IP;
output reg [47:0]PC_MAC;
output reg [47:0]ARP_PC_MAC;
output reg [31:0]ARP_PC_IP;
output reg [31:0]Ping_PC_IP;
output reg [47:0]Ping_PC_MAC;
output reg [15:0]Length;
output reg data_match;
output reg PHY_100T_state;
output wire [7:0]Rx_fifo_data;
output seq_error;
output reg run;
output reg wide_spectrum;
output reg [31:0]IP_lease;
output reg [31:0]DHCP_IP;
output reg [47:0]DHCP_MAC;
output reg erase;
output reg [31:0]num_blocks;
output reg EPCS_FIFO_enable;
reg [111:0] PHY_output;
reg [4:0] PHY_Rx_state;
reg [9:0] left_shift;
reg [31:0] PC_sequence_number;
reg [11:0] PHY_data_count;
reg [8:0] EPCS_data_count;
reg [47:0] FromMAC;
reg [31:0] FromIP;
reg [7:0] ping_count;
reg [31:0]temp_YIADDR;
reg [15:0]UDP_check;
reg [31:0]To_IP;
reg [7:0]skip;
reg [15:0] FromPort;
reg [15:0] ToPort;
reg [31:0]temp_PC_IP;
reg [47:0]temp_PC_MAC;
reg [15:0]temp_Port;
localparam Rx_port = 1024;
localparam START = 5'd0,
GET_TYPE = 5'd1,
ARP = 5'd2,
UDP = 5'd3,
METIS_DISCOVERY = 5'd4,
SEND_TO_FIFO = 5'd5,
DHCP = 5'd6,
PING = 5'd7,
PROGRAM_FIFO = 5'd8,
ERASE = 5'd9,
RETURN = 5'd10;
localparam Broadcast = 48'hFF_FF_FF_FF_FF_FF;
wire [3:0] PHY_RX;
wire [3:0] PHY_data_h;
wire [3:0] PHY_data_l;
reg [7:0] PHY_byte;
reg PHY_Rx_fifo_reset;
reg [31:0]prev_seq_number;
reg seq_error;
always @ (negedge PHY_RX_CLOCK)
begin
case (PHY_100T_state)
0: begin
if (PHY_DV) begin
PHY_byte <= {PHY_byte[7:4],PHY_RX};
PHY_100T_state <= 1'd1;
end
end
1: begin
PHY_byte <= {PHY_RX, PHY_byte[3:0]};
PHY_100T_state <= 1'd0;
end
endcase
end
always @ (posedge PHY_RX_CLOCK)
if (PHY_100T_state == 0) PHY_output <= {PHY_output[103:0], PHY_byte};
assign Rx_fifo_data = PHY_output[7:0];
always @ (negedge PHY_data_clock)
begin
case (PHY_Rx_state)
START:
begin
broadcast <= 1'b0;
left_shift <= 0;
ARP_request <= 1'b0;
ping_request <= 1'b0;
this_MAC <= 1'b0;
PHY_data_count <= 0;
EPCS_data_count <= 0;
RS232_Tx <= 0;
ping_count <= 0;
erase <= 0;
if (PHY_output[63:0] == {16'h55_D5, Broadcast} ) begin
broadcast <= 1'b1;
PHY_Rx_state <= GET_TYPE;
end
else if (PHY_output[63:0] == {16'h55_D5, This_MAC}) begin
this_MAC <= 1'b1;
PHY_Rx_state <= GET_TYPE;
end
else PHY_Rx_state <= START;
end
GET_TYPE:
begin
data_match <= 1'b1;
case(left_shift)
13: begin
FromMAC <= PHY_output[111:64];
Length <= PHY_output[31:16];
if (PHY_output[63:48] == 16'h0806 && broadcast) begin
left_shift <= 0;
PHY_Rx_state <= ARP;
end
else begin
UDP_check <= PHY_output[63:48];
left_shift <= left_shift + 1'b1;
end
end
27: begin
if (PHY_output[87:80] == 8'h11 && UDP_check == 16'h0800 ) begin
FromIP <= PHY_output[63:32];
To_IP <= PHY_output[31:0];
left_shift <= 0;
PHY_Rx_state <= UDP;
end
else left_shift <= left_shift + 1'b1;
end
30: begin
if (PHY_output[111:104] == 8'h01 && PHY_output[55:24] == This_IP)begin
if (PHY_output[23:16] == 8'h08) begin
Ping_PC_IP <= PHY_output[87:56];
Ping_PC_MAC <= FromMAC;
left_shift <= left_shift + 1'b1;
end
else if (PHY_output[23:16] == 8'h03) begin
run <= 1'b0;
wide_spectrum <= 1'b0;
PHY_Rx_state <= RETURN;
end
end
else PHY_Rx_state <= RETURN;
end
31: begin
left_shift <= 0;
PHY_Rx_state <= PING;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= GET_TYPE;
end
endcase
end
ARP:
begin
case (left_shift)
13: begin
if ( PHY_output[111:96] == 16'h0001) begin
ARP_PC_MAC <= PHY_output[95:48];
ARP_PC_IP <= PHY_output[47:16];
left_shift <= left_shift + 1'b1;
end
else PHY_Rx_state <= RETURN;
end
21: begin
if (PHY_output[31:0] == This_IP)
ARP_request <= 1'b1;
PHY_Rx_state <= RETURN;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= ARP;
end
endcase
end
UDP:
begin
case (left_shift)
13: begin
FromPort <= PHY_output[111:96];
ToPort <= PHY_output[95:80];
if (PHY_output[95:80] == 16'h0044 && PHY_output[47:40] == 8'h02)begin
left_shift <= 0;
PHY_Rx_state <= DHCP;
end
else left_shift <= left_shift + 1'b1;
end
15: begin
if (PHY_output[63:48] == 16'hEFFE && ToPort == Rx_port) begin
if (To_IP == This_IP) begin
case (PHY_output[47:40])
1: begin
if (PHY_output[39:32] == 8'h02) begin
PC_sequence_number <= PHY_output[31:0];
PHY_Rx_state <= SEND_TO_FIFO;
end
end
3: begin
num_blocks <= PHY_output[31:0];
if (PHY_output[39:32] == 8'd1) begin
PHY_Rx_state <= PROGRAM_FIFO;
end
else if (PHY_output[39:32] == 8'd2) begin
erase <= 1'b1;
PHY_Rx_state <= ERASE;
end
end
4: begin
run <= PHY_output[32];
wide_spectrum <= PHY_output[33];
PC_IP <= FromIP;
PC_MAC <= FromMAC;
Port <= FromPort;
PHY_Rx_state <= RETURN;
end
default: PHY_Rx_state <= RETURN;
endcase
end
else if (broadcast) begin
if (PHY_output[47:40] == 8'h02) begin
left_shift <= 0;
temp_PC_IP <= PC_IP;
temp_PC_MAC <= PC_MAC;
temp_Port <= Port;
PHY_Rx_state <= METIS_DISCOVERY;
end
end
else PHY_Rx_state <= RETURN;
end
else PHY_Rx_state <= RETURN;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= UDP;
end
endcase
end
METIS_DISCOVERY:
begin
case (left_shift)
1: begin
PC_IP <= FromIP;
PC_MAC <= FromMAC;
Port <= FromPort;
METIS_discovery <= 1'b1;
left_shift <= left_shift + 1'b1;
end
3: begin
METIS_discovery <= 0;
PC_IP <= temp_PC_IP;
PC_MAC <= temp_PC_MAC;
Port <= temp_Port;
PHY_Rx_state <= RETURN;
end
default: begin
left_shift <= left_shift + 1'b1;
PHY_Rx_state <= METIS_DISCOVERY;
end
endcase
end
SEND_TO_FIFO:
begin
if (PC_sequence_number != prev_seq_number + 1'b1)
seq_error <= 1'b1;
if (PHY_data_count == 1024) begin
data_match <= 1'b0;
Rx_enable <= 0;
prev_seq_number <= PC_sequence_number;
seq_error <= 1'b0;
PHY_Rx_state <= START;
end
else begin
Rx_enable <= 1'b1;
PHY_data_count <= PHY_data_count + 1'b1;
end
end
DHCP:
begin
DHCP_offer <= 0;
DHCP_ACK <= 0;
DHCP_NAK <= 0;
DHCP_MAC <= FromMAC;
case (left_shift)
13: begin
temp_YIADDR <= PHY_output[31:0];
left_shift <= left_shift + 1'b1;
end
27: begin
if (PHY_output[47:0] == This_MAC) begin
YIADDR <= temp_YIADDR;
left_shift <= left_shift + 1'b1;
end
else PHY_Rx_state <= RETURN;
end
236: begin
if (PHY_output[23:0] == 24'h35_01_02) begin
DHCP_offer <= 1'b1;
left_shift <= left_shift + 1'b1;
end
else if (PHY_output[23:0] == 24'h35_01_05) begin
DHCP_ACK <= 1'b1;
PHY_Rx_state <= RETURN;
end
else if (PHY_output[23:0] == 24'h35_01_06) begin
DHCP_NAK <= 1'b1;
PHY_Rx_state <= RETURN;
end
end
238: begin
if (PHY_output[15:8] == 8'hFF)
PHY_Rx_state <= RETURN;
else if (PHY_output[15:0] == 16'h3304) begin
left_shift <= 241;
end
else if (PHY_output[15:0] == 16'h3604) begin
left_shift <= 245;
end
else begin
skip <= PHY_output[7:0];
left_shift <= left_shift + 1'b1;
end
end
239: begin
if (skip - 1 == 0) left_shift <= 240;
else begin
skip <= skip - 1'b1;
left_shift <= 239;
end
end
240: left_shift <= 238;
241: left_shift <= left_shift + 1'b1;
244: begin
IP_lease <= PHY_output[31:0];
left_shift <= 240;
end
245: left_shift <= left_shift + 1'b1;
248: begin
DHCP_IP <= PHY_output[31:0];
left_shift <= 240;
end
default: begin
left_shift <= left_shift + 1'b1;
RS232_Tx <= 1'b0;
PHY_Rx_state <= DHCP;
end
endcase
end
PING:
begin
if (ping_count == (Length - 24)) begin
ping_request <= 1'b1;
PHY_Rx_state <= RETURN;
end
else begin
ping_data[ping_count] <= PHY_output[7:0];
ping_count <= ping_count + 1'b1;
PHY_Rx_state <= PING;
end
end
PROGRAM_FIFO:
begin
if (EPCS_data_count == 9'd256) begin
EPCS_data_count <= 0;
EPCS_FIFO_enable <= 0;
PHY_Rx_state <= RETURN;
end
else begin
EPCS_FIFO_enable <= 1'b1;
EPCS_data_count <= EPCS_data_count + 9'd1;
end
end
ERASE: if (erase_ACK) PHY_Rx_state <= RETURN;
RETURN:
begin
data_match <= 1'b0;
PHY_Rx_state <= START;
end
default: PHY_Rx_state <= START;
endcase
end
endmodule | 17 |
138,870 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_v2.6/I2C_Master.v | 86,169,941 | I2C_Master.v | v | 264 | 128 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_v2.6,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_v2.6/I2C_Master.v\n%Error: Exiting due to 3 error(s)\n' | 303,718 | module | module i2c_master (I2C_clock, reset_n, ena, addr, rw, data_wr, busy, data_rd, ack_error, sda, scl, probe);
input wire I2C_clock;
input reg reset_n;
input reg ena;
input reg [6:0] addr;
input reg rw;
input reg [15:0] data_wr;
output reg busy;
output reg [15:0] data_rd;
output reg ack_error;
inout wire sda;
output wire scl;
output wire probe;
reg [6:0] state;
reg data_clk;
reg scl_clk;
reg scl_ena;
reg sda_int;
reg sda_ena_n;
reg [7:0] addr_rw;
reg [15:0] data_tx;
reg [15:0] data_rx;
reg [4:0] bit_cnt;
reg stretch;
reg read;
initial
begin
scl_ena = 1'b0;
sda_int = 1'b1;
bit_cnt = 5'd7;
stretch = 1'b0;
count = 0;
state = `READY;
end
reg [1:0] count;
always @ (posedge I2C_clock) begin
if (reset_n) begin
stretch <= 1'b0;
count <= 0;
end
else begin
count <= count + 1;
case (count)
0: begin
scl_clk <= 1'bz;
data_clk <= 1'b0;
end
1: begin
scl_clk <= 1'b0;
data_clk <= 1'b1;
end
2: begin
scl_clk <= 1'b0;
data_clk <= 1'b1;
end
3: begin
scl_clk <= 1'bz;
data_clk <= 1'b0;
end
endcase
end
end
always @ (posedge data_clk)
begin
if (reset_n) begin
state <= `READY;
busy <= 1'b1;
scl_ena <= 1'b0;
sda_int <= 1'b1;
end
else begin
case (state)
`READY: begin
if (ena) begin
busy <= 1'b1;
addr_rw <= {addr, rw};
data_tx <= data_wr;
bit_cnt <= 7;
state <= `START;
end
else begin
busy <= 1'b0;
end
end
`START: begin
scl_ena <= 1'b1;
sda_int <= addr_rw[bit_cnt];
state <= `COMMAND;
end
`COMMAND: begin
if (bit_cnt == 0) begin
sda_int <= 1'b1;
bit_cnt <= 16;
state <= `HIGH_BYTE;
end
else begin
bit_cnt <= bit_cnt - 1;
sda_int <= addr_rw[bit_cnt - 1];
end
end
`HIGH_BYTE: begin
if (bit_cnt == 8) begin
if (rw) sda_int <= 1'b0;
else sda_int <= 1'b1;
state <= `LOW_BYTE;
end
else begin
if (!rw) sda_int <= data_tx[bit_cnt - 1];
bit_cnt <= bit_cnt - 1;
end
end
`LOW_BYTE: begin
if (bit_cnt == 0) begin
sda_int <= 1'b1;
if (rw) begin
sda_int <= 1'b0;
end
else sda_int <= 1'b1;
state <= `PRE_STOP;
end
else begin
if (rw) begin
sda_int = 1'b1;
end
else sda_int <= data_tx[bit_cnt - 1];
bit_cnt <= bit_cnt - 1;
end
end
`PRE_STOP: begin
sda_int <= 1'b1;
state <= `STOP;
end
`STOP: begin
busy <= 1'b0;
data_rd <= data_rx;
scl_ena <= 1'b0;
state <= `READY;
end
endcase
end
end
reg ack_flag;
reg [7:0] clk_count;
always @ (posedge scl)
begin
if (scl_ena) begin
if (rw) begin
if (clk_count == 27) begin
clk_count <= 0;
end
else begin
if (scl_ena) begin
if (clk_count >= 9 & clk_count <= 16) data_rx[24 - clk_count] <= sda;
if (clk_count >= 18 & clk_count <= 25) data_rx[25 - clk_count] <= sda;
clk_count <= clk_count + 1;
end
end
end
end
end
always @ (posedge I2C_clock)
begin
if (state == `START) sda_ena_n <= data_clk;
if (state == `STOP) sda_ena_n <= !data_clk;
if (state != `START & state != `STOP) sda_ena_n <= sda_int;
end
assign scl = (scl_ena) ? scl_clk : 1'bz;
assign sda = (!sda_ena_n) ? 1'b0 : 1'bz;
endmodule | module i2c_master (I2C_clock, reset_n, ena, addr, rw, data_wr, busy, data_rd, ack_error, sda, scl, probe); |
input wire I2C_clock;
input reg reset_n;
input reg ena;
input reg [6:0] addr;
input reg rw;
input reg [15:0] data_wr;
output reg busy;
output reg [15:0] data_rd;
output reg ack_error;
inout wire sda;
output wire scl;
output wire probe;
reg [6:0] state;
reg data_clk;
reg scl_clk;
reg scl_ena;
reg sda_int;
reg sda_ena_n;
reg [7:0] addr_rw;
reg [15:0] data_tx;
reg [15:0] data_rx;
reg [4:0] bit_cnt;
reg stretch;
reg read;
initial
begin
scl_ena = 1'b0;
sda_int = 1'b1;
bit_cnt = 5'd7;
stretch = 1'b0;
count = 0;
state = `READY;
end
reg [1:0] count;
always @ (posedge I2C_clock) begin
if (reset_n) begin
stretch <= 1'b0;
count <= 0;
end
else begin
count <= count + 1;
case (count)
0: begin
scl_clk <= 1'bz;
data_clk <= 1'b0;
end
1: begin
scl_clk <= 1'b0;
data_clk <= 1'b1;
end
2: begin
scl_clk <= 1'b0;
data_clk <= 1'b1;
end
3: begin
scl_clk <= 1'bz;
data_clk <= 1'b0;
end
endcase
end
end
always @ (posedge data_clk)
begin
if (reset_n) begin
state <= `READY;
busy <= 1'b1;
scl_ena <= 1'b0;
sda_int <= 1'b1;
end
else begin
case (state)
`READY: begin
if (ena) begin
busy <= 1'b1;
addr_rw <= {addr, rw};
data_tx <= data_wr;
bit_cnt <= 7;
state <= `START;
end
else begin
busy <= 1'b0;
end
end
`START: begin
scl_ena <= 1'b1;
sda_int <= addr_rw[bit_cnt];
state <= `COMMAND;
end
`COMMAND: begin
if (bit_cnt == 0) begin
sda_int <= 1'b1;
bit_cnt <= 16;
state <= `HIGH_BYTE;
end
else begin
bit_cnt <= bit_cnt - 1;
sda_int <= addr_rw[bit_cnt - 1];
end
end
`HIGH_BYTE: begin
if (bit_cnt == 8) begin
if (rw) sda_int <= 1'b0;
else sda_int <= 1'b1;
state <= `LOW_BYTE;
end
else begin
if (!rw) sda_int <= data_tx[bit_cnt - 1];
bit_cnt <= bit_cnt - 1;
end
end
`LOW_BYTE: begin
if (bit_cnt == 0) begin
sda_int <= 1'b1;
if (rw) begin
sda_int <= 1'b0;
end
else sda_int <= 1'b1;
state <= `PRE_STOP;
end
else begin
if (rw) begin
sda_int = 1'b1;
end
else sda_int <= data_tx[bit_cnt - 1];
bit_cnt <= bit_cnt - 1;
end
end
`PRE_STOP: begin
sda_int <= 1'b1;
state <= `STOP;
end
`STOP: begin
busy <= 1'b0;
data_rd <= data_rx;
scl_ena <= 1'b0;
state <= `READY;
end
endcase
end
end
reg ack_flag;
reg [7:0] clk_count;
always @ (posedge scl)
begin
if (scl_ena) begin
if (rw) begin
if (clk_count == 27) begin
clk_count <= 0;
end
else begin
if (scl_ena) begin
if (clk_count >= 9 & clk_count <= 16) data_rx[24 - clk_count] <= sda;
if (clk_count >= 18 & clk_count <= 25) data_rx[25 - clk_count] <= sda;
clk_count <= clk_count + 1;
end
end
end
end
end
always @ (posedge I2C_clock)
begin
if (state == `START) sda_ena_n <= data_clk;
if (state == `STOP) sda_ena_n <= !data_clk;
if (state != `START & state != `STOP) sda_ena_n <= sda_int;
end
assign scl = (scl_ena) ? scl_clk : 1'bz;
assign sda = (!sda_ena_n) ? 1'b0 : 1'bz;
endmodule | 17 |
138,871 | data/full_repos/permissive/86169941/Protocol 1/Metis/Source/Archive/Metis_v2.8/Tx_MAC.v | 86,169,941 | Tx_MAC.v | v | 1,474 | 175 | [] | ['general public license', 'free software foundation'] | [] | [(99, 1435)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941.sv\n 1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941\n 1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941.v\n 1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941.sv\n obj_dir/1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941\n obj_dir/1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941.v\n obj_dir/1/Metis/Source/Archive/Metis_v2.8,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Metis/Source/Archive/Metis_v2.8/Tx_MAC.v\n%Error: Exiting due to 3 error(s)\n' | 303,771 | module | module Tx_MAC (Tx_clock, Tx_clock_2, IF_rst, Send_ARP,ping_reply,
PHY_Tx_data, PHY_Tx_rdused, ping_data, LED, Tx_fifo_rdreq,
Tx_CTL, ARP_sent, ping_sent, TD, DHCP_discover, DHCP_discover_sent,
This_MAC,SIADDR, DHCP_request,
DHCP_request_sent, METIS_discovery, PC_IP, PC_MAC,
Port, This_IP, METIS_discover_sent, ARP_PC_MAC, ARP_PC_IP,
Ping_PC_MAC, Ping_PC_IP, Length, speed_100T, Tx_reset, run, wide_spectrum,
IP_valid, printf, IP_lease, DHCP_IP, DHCP_MAC, DHCP_request_renew, DHCP_request_renew_sent,
erase_done, erase_done_ACK, send_more, send_more_ACK, Metis_serialno,
sp_fifo_rddata, sp_fifo_rdreq, have_sp_data, AssignIP);
input Tx_clock;
input Tx_clock_2;
input IF_rst;
input Send_ARP;
input ping_reply;
input [7:0]PHY_Tx_data;
input [10:0]PHY_Tx_rdused;
input [7:0]ping_data[0:59];
input DHCP_discover;
input [47:0]This_MAC;
input [31:0]SIADDR;
input DHCP_request;
input METIS_discovery;
input [31:0]PC_IP;
input [47:0]PC_MAC;
input [15:0]Port;
input [31:0]This_IP;
input [47:0]ARP_PC_MAC;
input [31:0]ARP_PC_IP;
input [47:0]Ping_PC_MAC;
input [31:0]Ping_PC_IP;
input [15:0]Length;
input speed_100T;
input Tx_reset;
input run;
input wide_spectrum;
input IP_valid;
input printf;
input [31:0]IP_lease;
input [31:0]DHCP_IP;
input [47:0]DHCP_MAC;
input DHCP_request_renew;
input erase_done;
input send_more;
input [7:0]Metis_serialno;
input [7:0]sp_fifo_rddata;
input have_sp_data;
input [31:0]AssignIP;
output LED;
output Tx_fifo_rdreq;
output Tx_CTL;
output ARP_sent;
output ping_sent;
output [3:0]TD;
output DHCP_discover_sent;
output DHCP_request_sent;
output METIS_discover_sent;
output DHCP_request_renew_sent;
output erase_done_ACK;
output send_more_ACK;
output sp_fifo_rdreq;
parameter HPSDR_frame = 8'h01;
parameter HPSDR_IP_frame = 8'h03;
parameter Type_1 = 8'hEF;
parameter Type_2 = 8'hFE;
localparam TxPort = 16'd1024;
localparam IP_MAC = 48'h11_22_33_44_55_66;
localparam
RESET = 0,
UDP = 1,
METIS_DISCOVERY = 2,
ARP = 3,
PING1 = 4,
PING2 = 5,
DHCP_DISCOVER = 6,
DHCP_REQUEST = 7,
DHCP_REQUEST_RENEW = 8,
PRINTF = 9,
SPECTRUM = 10,
SENDIP = 11,
CRC = 12;
wire [31:0] CRC32;
reg [31:0] temp_CRC32 = 0;
reg [31:0] sequence_number = 0;
reg [31:0] spec_seq_number = 0;
reg [6:0] state_Tx;
reg [10:0] data_count;
reg [10:0] sp_data_count;
reg reset_CRC;
reg [7:0] Tx_data;
reg [4:0] gap_count;
reg ARP_sent;
reg LED;
reg erase_done_ACK;
reg send_more_ACK;
reg [31:0]Discovery_IP;
reg [47:0]Discovery_MAC;
reg [15:0]Discovery_Port;
reg [7:0]end_point;
wire have_sp_data;
reg [4:0]IP_count;
wire [31:0]IPchecksum1;
wire [31:0]IPchecksum2;
wire [15:0]IPchecksum3;
assign IPchecksum1 = 32'h0000C935 + This_IP[31:16] + This_IP[15:0] + PC_IP[31:16] + PC_IP[15:0];
assign IPchecksum2 = ((IPchecksum1 & 32'h0000FFFF) + (IPchecksum1 >> 16));
assign IPchecksum3 = ~((IPchecksum2 & 32'h0000FFFF) + (IPchecksum2 >> 16));
wire [31:0]DISchecksum1;
wire [31:0]DISchecksum2;
wire [15:0]DISchecksum3;
assign DISchecksum1 = 32'h00004500 + 32'h00000058 + 32'h00008011 + This_IP[31:16] + This_IP[15:0] +
Discovery_IP[31:16] + Discovery_IP[15:0];
assign DISchecksum2 = ((DISchecksum1 & 32'h0000FFFF) + (DISchecksum1 >> 16));
assign DISchecksum3 = ~((DISchecksum2 & 32'h0000FFFF) + (DISchecksum2 >> 16));
wire [31:0]ICMPchecksum1;
wire [31:0]ICMPchecksum2;
wire [15:0]ICMPchecksum3;
assign ICMPchecksum1 = 32'h00004500 + Length + 32'h00008001 + This_IP[31:16] + This_IP[15:0] +
Ping_PC_IP[31:16] + Ping_PC_IP[15:0];
assign ICMPchecksum2 = ((ICMPchecksum1 & 32'h0000FFFF) + (ICMPchecksum1 >> 16));
assign ICMPchecksum3 = ~((ICMPchecksum2 & 32'h0000FFFF) + (ICMPchecksum2 >> 16));
wire [31:0]DHCPchecksum1;
wire [31:0]DHCPchecksum2;
wire [15:0]DHCPchecksum3;
assign DHCPchecksum1 = 32'h00004500 + UDP_DHCP_length + 32'h00008011 + 32'h0000FFFF + 32'h0000FFFF;
assign DHCPchecksum2 = ((DHCPchecksum1 & 32'h0000FFFF) + (DHCPchecksum1 >> 16));
assign DHCPchecksum3 = ~((DHCPchecksum2 & 32'h0000FFFF) + (DHCPchecksum2 >> 16));
wire [31:0]DHCP_req_checksum1;
wire [31:0]DHCP_req_checksum2;
wire [15:0]DHCP_req_checksum3;
assign DHCP_req_checksum1 = 32'h00004500 + UDP_DHCP_req_length + 32'h00008011 + 32'h0000FFFF + 32'h0000FFFF;
assign DHCP_req_checksum2 = ((DHCP_req_checksum1 & 32'h0000FFFF) + (DHCP_req_checksum1 >> 16));
assign DHCP_req_checksum3 = ~((DHCP_req_checksum2 & 32'h0000FFFF) + (DHCP_req_checksum2 >> 16));
wire [31:0]DHCP_req_renew_checksum1;
wire [31:0]DHCP_req_renew_checksum2;
wire [15:0]DHCP_req_renew_checksum3;
assign DHCP_req_renew_checksum1 = 32'h00004500 + UDP_DHCP_req_renew_length + 32'h00008011 + This_IP[31:16] + This_IP[15:0] +
DHCP_IP[31:16] + DHCP_IP[15:0];
assign DHCP_req_renew_checksum2 = ((DHCP_req_renew_checksum1 & 32'h0000FFFF) + (DHCP_req_renew_checksum1 >> 16));
assign DHCP_req_renew_checksum3 = ~((DHCP_req_renew_checksum2 & 32'h0000FFFF) + (DHCP_req_renew_checksum2 >> 16));
wire [15:0]DHCP_length;
wire [15:0]UDP_DHCP_length;
wire [15:0]DHCP_req_length;
wire [15:0]UDP_DHCP_req_length;
wire [15:0]DHCP_req_renew_length;
wire [15:0]UDP_DHCP_req_renew_length;
reg [9:0] rdaddress;
reg [7:0] pkt_data;
reg [7:0] ck_count;
reg [31:0]ping_check_temp;
reg [15:0]ping_check_sum;
reg ping_sent;
reg [8:0] zero_count;
reg [3:0]interframe;
reg printf;
reg DHCP_request_renew_sent;
reg Metis_discover_sent;
reg [7:0] frame;
reg [31:0]temp_IP;
always @ *
case(rdaddress)
0 : pkt_data <= 8'h55;
1 : pkt_data <= 8'h55;
2 : pkt_data <= 8'h55;
3 : pkt_data <= 8'h55;
4 : pkt_data <= 8'h55;
5 : pkt_data <= 8'h55;
6 : pkt_data <= 8'h55;
7 : pkt_data <= 8'hD5;
8 : pkt_data <= PC_MAC[47:40];
9 : pkt_data <= PC_MAC[39:32];
10: pkt_data <= PC_MAC[31:24];
11: pkt_data <= PC_MAC[23:16];
12: pkt_data <= PC_MAC[15:8];
13: pkt_data <= PC_MAC[7:0];
14: pkt_data <= This_MAC[47:40];
15: pkt_data <= This_MAC[39:32];
16: pkt_data <= This_MAC[31:24];
17: pkt_data <= This_MAC[23:16];
18: pkt_data <= This_MAC[15:8];
19: pkt_data <= This_MAC[7:0];
20: pkt_data <= 8'h08;
21: pkt_data <= 8'h00;
22: pkt_data <= 8'h45;
23: pkt_data <= 8'h00;
24: pkt_data <= 8'h04;
25: pkt_data <= 8'h24;
26: pkt_data <= 8'h00;
27: pkt_data <= 8'h00;
28: pkt_data <= 8'h00;
29: pkt_data <= 8'h00;
30: pkt_data <= 8'h80;
31: pkt_data <= 8'h11;
32: pkt_data <= IPchecksum3[15:8];
33: pkt_data <= IPchecksum3[ 7:0];
34: pkt_data <= This_IP[31:24];
35: pkt_data <= This_IP[23:16];
36: pkt_data <= This_IP[15:8];
37: pkt_data <= This_IP[7:0];
38: pkt_data <= PC_IP[31:24];
39: pkt_data <= PC_IP[23:16];
40: pkt_data <= PC_IP[15:8];
41: pkt_data <= PC_IP[7:0];
42: pkt_data <= TxPort[15:8];
43: pkt_data <= TxPort[7:0];
44: pkt_data <= Port[15:8];
45: pkt_data <= Port[7:0];
46: pkt_data <= 8'h04;
47: pkt_data <= 8'h10;
48: pkt_data <= 8'h00;
49: pkt_data <= 8'h00;
50: pkt_data <= Type_1;
51: pkt_data <= Type_2;
52: pkt_data <= HPSDR_frame;
53: pkt_data <= end_point;
54: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[31:24] : sequence_number[31:24];
55: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[23:16] : sequence_number[23:16];
56: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[15:8] : sequence_number[15:8];
57: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[7:0] : sequence_number[7:0];
58: pkt_data <= temp_CRC32[15:8];
59: pkt_data <= temp_CRC32[23:16];
60: pkt_data <= temp_CRC32[31:24];
100: pkt_data <= 8'h55;
101: pkt_data <= 8'h55;
102: pkt_data <= 8'h55;
103: pkt_data <= 8'h55;
104: pkt_data <= 8'h55;
105: pkt_data <= 8'h55;
106: pkt_data <= 8'h55;
107: pkt_data <= 8'hD5;
108: pkt_data <= ARP_PC_MAC[47:40];
109: pkt_data <= ARP_PC_MAC[39:32];
110: pkt_data <= ARP_PC_MAC[31:24];
111: pkt_data <= ARP_PC_MAC[23:16];
112: pkt_data <= ARP_PC_MAC[15:8];
113: pkt_data <= ARP_PC_MAC[7:0];
114: pkt_data <= This_MAC[47:40];
115: pkt_data <= This_MAC[39:32];
116: pkt_data <= This_MAC[31:24];
117: pkt_data <= This_MAC[23:16];
118: pkt_data <= This_MAC[15:8];
119: pkt_data <= This_MAC[7:0];
120: pkt_data <= 8'h08;
121: pkt_data <= 8'h06;
122: pkt_data <= 8'h00;
123: pkt_data <= 8'h01;
124: pkt_data <= 8'h08;
125: pkt_data <= 8'h00;
126: pkt_data <= 8'h06;
127: pkt_data <= 8'h04;
128: pkt_data <= 8'h00;
129: pkt_data <= 8'h02;
130: pkt_data <= This_MAC[47:40];
131: pkt_data <= This_MAC[39:32];
132: pkt_data <= This_MAC[31:24];
133: pkt_data <= This_MAC[23:16];
134: pkt_data <= This_MAC[15:8];
135: pkt_data <= This_MAC[7:0];
136: pkt_data <= This_IP[31:24];
137: pkt_data <= This_IP[23:16];
138: pkt_data <= This_IP[15:8];
139: pkt_data <= This_IP[7:0];
140: pkt_data <= ARP_PC_MAC[47:40];
141: pkt_data <= ARP_PC_MAC[39:32];
142: pkt_data <= ARP_PC_MAC[31:24];
143: pkt_data <= ARP_PC_MAC[23:16];
144: pkt_data <= ARP_PC_MAC[15:8];
145: pkt_data <= ARP_PC_MAC[7:0];
146: pkt_data <= ARP_PC_IP[31:24];
147: pkt_data <= ARP_PC_IP[23:16];
148: pkt_data <= ARP_PC_IP[15:8];
149: pkt_data <= ARP_PC_IP[7:0];
200: pkt_data <= 8'h55;
201: pkt_data <= 8'h55;
202: pkt_data <= 8'h55;
203: pkt_data <= 8'h55;
204: pkt_data <= 8'h55;
205: pkt_data <= 8'h55;
206: pkt_data <= 8'h55;
207: pkt_data <= 8'hD5;
208: pkt_data <= Ping_PC_MAC[47:40];
209: pkt_data <= Ping_PC_MAC[39:32];
210: pkt_data <= Ping_PC_MAC[31:24];
211: pkt_data <= Ping_PC_MAC[23:16];
212: pkt_data <= Ping_PC_MAC[15:8];
213: pkt_data <= Ping_PC_MAC[7:0];
214: pkt_data <= This_MAC[47:40];
215: pkt_data <= This_MAC[39:32];
216: pkt_data <= This_MAC[31:24];
217: pkt_data <= This_MAC[23:16];
218: pkt_data <= This_MAC[15:8];
219: pkt_data <= This_MAC[7:0];
220: pkt_data <= 8'h08;
221: pkt_data <= 8'h00;
222: pkt_data <= 8'h45;
223: pkt_data <= 8'h00;
224: pkt_data <= Length[15:8];
225: pkt_data <= Length[7:0];
226: pkt_data <= 8'h00;
227: pkt_data <= 8'h00;
228: pkt_data <= 8'h00;
229: pkt_data <= 8'h00;
230: pkt_data <= 8'h80;
231: pkt_data <= 8'h01;
232: pkt_data <= ICMPchecksum3[15:8];
233: pkt_data <= ICMPchecksum3[ 7:0];
234: pkt_data <= This_IP[31:24];
235: pkt_data <= This_IP[23:16];
236: pkt_data <= This_IP[15:8];
237: pkt_data <= This_IP[7:0];
238: pkt_data <= Ping_PC_IP[31:24];
239: pkt_data <= Ping_PC_IP[23:16];
240: pkt_data <= Ping_PC_IP[15:8];
241: pkt_data <= Ping_PC_IP[7:0];
242: pkt_data <= 8'h00;
243: pkt_data <= 8'h00;
244: pkt_data <= ping_check_sum[15:8];
245: pkt_data <= ping_check_sum[7:0];
300: pkt_data <= 8'h55;
301: pkt_data <= 8'h55;
302: pkt_data <= 8'h55;
303: pkt_data <= 8'h55;
304: pkt_data <= 8'h55;
305: pkt_data <= 8'h55;
306: pkt_data <= 8'h55;
307: pkt_data <= 8'hD5;
308: pkt_data <= 8'hFF;
309: pkt_data <= 8'hFF;
310: pkt_data <= 8'hFF;
311: pkt_data <= 8'hFF;
312: pkt_data <= 8'hFF;
313: pkt_data <= 8'hFF;
314: pkt_data <= This_MAC[47:40];
315: pkt_data <= This_MAC[39:32];
316: pkt_data <= This_MAC[31:24];
317: pkt_data <= This_MAC[23:16];
318: pkt_data <= This_MAC[15:8];
319: pkt_data <= This_MAC[7:0];
320: pkt_data <= 8'h08;
321: pkt_data <= 8'h00;
322: pkt_data <= 8'h45;
323: pkt_data <= 8'h00;
324: pkt_data <= UDP_DHCP_length[15:8];
325: pkt_data <= UDP_DHCP_length[7:0];
326: pkt_data <= 8'h00;
327: pkt_data <= 8'h00;
328: pkt_data <= 8'h00;
329: pkt_data <= 8'h00;
330: pkt_data <= 8'h80;
331: pkt_data <= 8'h11;
332: pkt_data <= DHCPchecksum3[15:8];
333: pkt_data <= DHCPchecksum3[ 7:0];
334: pkt_data <= 8'h00;
335: pkt_data <= 8'h00;
336: pkt_data <= 8'h00;
337: pkt_data <= 8'h00;
338: pkt_data <= 8'hFF;
339: pkt_data <= 8'hFF;
340: pkt_data <= 8'hFF;
341: pkt_data <= 8'hFF;
342: pkt_data <= 8'h00;
343: pkt_data <= 8'h44;
344: pkt_data <= 8'h00;
345: pkt_data <= 8'h43;
346: pkt_data <= DHCP_length[15:8];
347: pkt_data <= DHCP_length[7:0];
348: pkt_data <= 8'h00;
349: pkt_data <= 8'h00;
350: pkt_data <= 8'h01;
351: pkt_data <= 8'h01;
352: pkt_data <= 8'h06;
353: pkt_data <= 8'h00;
354: pkt_data <= This_MAC[47:40];
355: pkt_data <= This_MAC[39:32];
356: pkt_data <= This_MAC[31:24];
357: pkt_data <= This_MAC[23:16];
358: pkt_data <= This_MAC[15:8];
359: pkt_data <= This_MAC[7:0];
360: pkt_data <= 8'h63;
361: pkt_data <= 8'h82;
362: pkt_data <= 8'h53;
363: pkt_data <= 8'h63;
364: pkt_data <= 8'h35;
365: pkt_data <= 8'h01;
366: pkt_data <= 8'h01;
367: pkt_data <= 8'hFF;
400: pkt_data <= 8'h55;
401: pkt_data <= 8'h55;
402: pkt_data <= 8'h55;
403: pkt_data <= 8'h55;
404: pkt_data <= 8'h55;
405: pkt_data <= 8'h55;
406: pkt_data <= 8'h55;
407: pkt_data <= 8'hD5;
408: pkt_data <= 8'hFF;
409: pkt_data <= 8'hFF;
410: pkt_data <= 8'hFF;
411: pkt_data <= 8'hFF;
412: pkt_data <= 8'hFF;
413: pkt_data <= 8'hFF;
414: pkt_data <= This_MAC[47:40];
415: pkt_data <= This_MAC[39:32];
416: pkt_data <= This_MAC[31:24];
417: pkt_data <= This_MAC[23:16];
418: pkt_data <= This_MAC[15:8];
419: pkt_data <= This_MAC[7:0];
420: pkt_data <= 8'h08;
421: pkt_data <= 8'h00;
422: pkt_data <= 8'h45;
423: pkt_data <= 8'h00;
424: pkt_data <= UDP_DHCP_req_length[15:8];
425: pkt_data <= UDP_DHCP_req_length[7:0];
426: pkt_data <= 8'h00;
427: pkt_data <= 8'h00;
428: pkt_data <= 8'h00;
429: pkt_data <= 8'h00;
430: pkt_data <= 8'h80;
431: pkt_data <= 8'h11;
432: pkt_data <= DHCP_req_checksum3[15:8];
433: pkt_data <= DHCP_req_checksum3[ 7:0];
434: pkt_data <= 8'h00;
435: pkt_data <= 8'h00;
436: pkt_data <= 8'h00;
437: pkt_data <= 8'h00;
438: pkt_data <= 8'hFF;
439: pkt_data <= 8'hFF;
440: pkt_data <= 8'hFF;
441: pkt_data <= 8'hFF;
442: pkt_data <= 8'h00;
443: pkt_data <= 8'h44;
444: pkt_data <= 8'h00;
445: pkt_data <= 8'h43;
446: pkt_data <= DHCP_req_length[15:8];
447: pkt_data <= DHCP_req_length[7:0];
448: pkt_data <= 8'h00;
449: pkt_data <= 8'h00;
450: pkt_data <= 8'h01;
451: pkt_data <= 8'h01;
452: pkt_data <= 8'h06;
453: pkt_data <= 8'h00;
454: pkt_data <= This_MAC[47:40];
455: pkt_data <= This_MAC[39:32];
456: pkt_data <= This_MAC[31:24];
457: pkt_data <= This_MAC[23:16];
458: pkt_data <= This_MAC[15:8];
459: pkt_data <= This_MAC[7:0];
460: pkt_data <= 8'h63;
461: pkt_data <= 8'h82;
462: pkt_data <= 8'h53;
463: pkt_data <= 8'h63;
464: pkt_data <= 8'h35;
465: pkt_data <= 8'h01;
466: pkt_data <= 8'h03;
467: pkt_data <= 8'h32;
468: pkt_data <= 8'h04;
469: pkt_data <= This_IP[31:24];
470: pkt_data <= This_IP[23:16];
471: pkt_data <= This_IP[15:8];
472: pkt_data <= This_IP[7:0];
473: pkt_data <= 8'h36;
474: pkt_data <= 8'h04;
475: pkt_data <= DHCP_IP[31:24];
476: pkt_data <= DHCP_IP[23:16];
477: pkt_data <= DHCP_IP[15:8];
478: pkt_data <= DHCP_IP[7:0];
479: pkt_data <= 8'hFF;
500: pkt_data <= 8'h55;
501: pkt_data <= 8'h55;
502: pkt_data <= 8'h55;
503: pkt_data <= 8'h55;
504: pkt_data <= 8'h55;
505: pkt_data <= 8'h55;
506: pkt_data <= 8'h55;
507: pkt_data <= 8'hD5;
508: pkt_data <= Discovery_MAC[47:40];
509: pkt_data <= Discovery_MAC[39:32];
510: pkt_data <= Discovery_MAC[31:24];
511: pkt_data <= Discovery_MAC[23:16];
512: pkt_data <= Discovery_MAC[15:8];
513: pkt_data <= Discovery_MAC[7:0];
514: pkt_data <= This_MAC[47:40];
515: pkt_data <= This_MAC[39:32];
516: pkt_data <= This_MAC[31:24];
517: pkt_data <= This_MAC[23:16];
518: pkt_data <= This_MAC[15:8];
519: pkt_data <= This_MAC[7:0];
520: pkt_data <= 8'h08;
521: pkt_data <= 8'h00;
522: pkt_data <= 8'h45;
523: pkt_data <= 8'h00;
524: pkt_data <= 8'h00;
525: pkt_data <= 8'h58;
526: pkt_data <= 8'h00;
527: pkt_data <= 8'h00;
528: pkt_data <= 8'h00;
529: pkt_data <= 8'h00;
530: pkt_data <= 8'h80;
531: pkt_data <= 8'h11;
532: pkt_data <= DISchecksum3[15:8];
533: pkt_data <= DISchecksum3[ 7:0];
534: pkt_data <= This_IP[31:24];
535: pkt_data <= This_IP[23:16];
536: pkt_data <= This_IP[15:8];
537: pkt_data <= This_IP[7:0];
538: pkt_data <= Discovery_IP[31:24];
539: pkt_data <= Discovery_IP[23:16];
540: pkt_data <= Discovery_IP[15:8];
541: pkt_data <= Discovery_IP[7:0];
542: pkt_data <= TxPort[15:8];
543: pkt_data <= TxPort[7:0];
544: pkt_data <= Discovery_Port[15:8];
545: pkt_data <= Discovery_Port[7:0];
546: pkt_data <= 8'h00;
547: pkt_data <= 8'h44;
548: pkt_data <= 8'h00;
549: pkt_data <= 8'h00;
550: pkt_data <= Type_1;
551: pkt_data <= Type_2;
552: pkt_data <= frame + run;
553: pkt_data <= This_MAC[47:40];
554: pkt_data <= This_MAC[39:32];
555: pkt_data <= This_MAC[31:24];
556: pkt_data <= This_MAC[23:16];
557: pkt_data <= This_MAC[15:8];
558: pkt_data <= This_MAC[7:0];
559: pkt_data <= Metis_serialno;
600 : pkt_data <= 8'h55;
601 : pkt_data <= 8'h55;
602 : pkt_data <= 8'h55;
603 : pkt_data <= 8'h55;
604 : pkt_data <= 8'h55;
605 : pkt_data <= 8'h55;
606 : pkt_data <= 8'h55;
607 : pkt_data <= 8'hD5;
608 : pkt_data <= 8'hFF;
609 : pkt_data <= 8'hFF;
610 : pkt_data <= 8'hFF;
611 : pkt_data <= 8'hFF;
612 : pkt_data <= 8'hFF;
613 : pkt_data <= 8'hFF;
614 : pkt_data <= This_MAC[47:40];
615 : pkt_data <= This_MAC[39:32];
616 : pkt_data <= This_MAC[31:24];
617 : pkt_data <= This_MAC[23:16];
618 : pkt_data <= This_MAC[15:8];
619 : pkt_data <= This_MAC[7:0];
620: pkt_data <= 8'hEF;
621: pkt_data <= 8'hFF;
622: pkt_data <= HPSDR_frame;
623: pkt_data <= 8'hFF;
624: pkt_data <= This_IP[31:24];
625: pkt_data <= This_IP[23:16];
626: pkt_data <= This_IP[15:8];
627: pkt_data <= This_IP[7:0];
628: pkt_data <= PC_IP[31:24];
629: pkt_data <= PC_IP[23:16];
630: pkt_data <= PC_IP[15:8];
631: pkt_data <= PC_IP[7:0];
632: pkt_data <= PC_MAC[47:40];
633: pkt_data <= PC_MAC[39:32];
634: pkt_data <= PC_MAC[31:24];
635: pkt_data <= PC_MAC[23:16];
636: pkt_data <= PC_MAC[15:8];
637: pkt_data <= PC_MAC[7:0];
638: pkt_data <= IP_lease[31:24];
639: pkt_data <= IP_lease[23:16];
640: pkt_data <= IP_lease[15:8];
641: pkt_data <= IP_lease[7:0];
642: pkt_data <= DHCP_IP[31:24];
643: pkt_data <= DHCP_IP[23:16];
644: pkt_data <= DHCP_IP[15:8];
645: pkt_data <= DHCP_IP[7:0];
646: pkt_data <= DHCP_MAC[47:40];
647: pkt_data <= DHCP_MAC[39:32];
648: pkt_data <= DHCP_MAC[31:24];
649: pkt_data <= DHCP_MAC[23:16];
650: pkt_data <= DHCP_MAC[15:8];
651: pkt_data <= DHCP_MAC[7:0];
700: pkt_data <= 8'h55;
701: pkt_data <= 8'h55;
702: pkt_data <= 8'h55;
703: pkt_data <= 8'h55;
704: pkt_data <= 8'h55;
705: pkt_data <= 8'h55;
706: pkt_data <= 8'h55;
707: pkt_data <= 8'hD5;
708: pkt_data <= DHCP_MAC[47:40];
709: pkt_data <= DHCP_MAC[39:32];
710: pkt_data <= DHCP_MAC[31:24];
711: pkt_data <= DHCP_MAC[23:16];
712: pkt_data <= DHCP_MAC[15:8];
713: pkt_data <= DHCP_MAC[7:0];
714: pkt_data <= This_MAC[47:40];
715: pkt_data <= This_MAC[39:32];
716: pkt_data <= This_MAC[31:24];
717: pkt_data <= This_MAC[23:16];
718: pkt_data <= This_MAC[15:8];
719: pkt_data <= This_MAC[7:0];
720: pkt_data <= 8'h08;
721: pkt_data <= 8'h00;
722: pkt_data <= 8'h45;
723: pkt_data <= 8'h00;
724: pkt_data <= UDP_DHCP_req_renew_length[15:8];
725: pkt_data <= UDP_DHCP_req_renew_length[7:0];
726: pkt_data <= 8'h00;
727: pkt_data <= 8'h00;
728: pkt_data <= 8'h00;
729: pkt_data <= 8'h00;
730: pkt_data <= 8'h80;
731: pkt_data <= 8'h11;
732: pkt_data <= DHCP_req_renew_checksum3[15:8];
733: pkt_data <= DHCP_req_renew_checksum3[ 7:0];
734: pkt_data <= This_IP[31:24];
735: pkt_data <= This_IP[23:16];
736: pkt_data <= This_IP[15:8];
737: pkt_data <= This_IP[7:0];
738: pkt_data <= DHCP_IP[31:24];
739: pkt_data <= DHCP_IP[23:16];
740: pkt_data <= DHCP_IP[15:8];
741: pkt_data <= DHCP_IP[7:0];
742: pkt_data <= 8'h00;
743: pkt_data <= 8'h44;
744: pkt_data <= 8'h00;
745: pkt_data <= 8'h43;
746: pkt_data <= DHCP_req_renew_length[15:8];
747: pkt_data <= DHCP_req_renew_length[7:0];
748: pkt_data <= 8'h00;
749: pkt_data <= 8'h00;
750: pkt_data <= 8'h01;
751: pkt_data <= 8'h01;
752: pkt_data <= 8'h06;
753: pkt_data <= 8'h00;
754: pkt_data <= 8'h00;
755: pkt_data <= 8'h00;
756: pkt_data <= 8'h00;
757: pkt_data <= 8'h00;
758: pkt_data <= 8'h00;
759: pkt_data <= 8'h00;
760: pkt_data <= 8'h00;
761: pkt_data <= 8'h00;
762: pkt_data <= This_IP[31:24];
763: pkt_data <= This_IP[23:16];
764: pkt_data <= This_IP[15:8];
765: pkt_data <= This_IP[7:0];
766: pkt_data <= This_MAC[47:40];
767: pkt_data <= This_MAC[39:32];
768: pkt_data <= This_MAC[31:24];
769: pkt_data <= This_MAC[23:16];
770: pkt_data <= This_MAC[15:8];
771: pkt_data <= This_MAC[7:0];
772: pkt_data <= 8'h63;
773: pkt_data <= 8'h82;
774: pkt_data <= 8'h53;
775: pkt_data <= 8'h63;
776: pkt_data <= 8'h35;
777: pkt_data <= 8'h01;
778: pkt_data <= 8'h03;
779: pkt_data <= 8'hFF;
default: pkt_data <= 0;
endcase
assign DHCP_length = 16'd8 + (16'd367 - 16'd350 + 16'd1) + 16'd24 + 16'd202;
assign UDP_DHCP_length = DHCP_length + 16'd20;
assign DHCP_req_length = 16'd8 + (16'd479 - 16'd450 + 16'd1) + 16'd24 + 16'd202;
assign UDP_DHCP_req_length = DHCP_req_length + 16'd20;
assign DHCP_req_renew_length = 16'd8 + (16'd779 - 16'd750 + 16'd1) + 16'd12 + 16'd202;
assign UDP_DHCP_req_renew_length = DHCP_req_renew_length + 16'd20;
always @ (negedge Tx_clock_2)
begin
case(state_Tx)
RESET:
begin
LED <= 1'b0;
sync_Tx_CTL <= 1'b0;
data_count <= 0;
reset_CRC <= 0;
rdaddress <= 0;
ARP_sent <= 0;
ping_sent <= 0;
ping_check_temp <= 0;
ck_count <= 0;
zero_count <= 0;
DHCP_discover_sent <= 0;
DHCP_request_sent <= 0;
METIS_discover_sent <= 0;
DHCP_request_renew_sent <= 0;
interframe <= 0;
erase_done_ACK <= 0;
send_more_ACK <= 0;
IP_count <= 0;
if (IF_rst)
state_Tx <= RESET;
else begin
if (run == 1'b0) begin
sequence_number <= 0;
spec_seq_number <= 0;
end
if (printf) begin
rdaddress <= 600;
state_Tx <= PRINTF;
end
else if (DHCP_discover) begin
rdaddress <= 300;
state_Tx <= DHCP_DISCOVER;
end
else if (DHCP_request) begin
rdaddress <= 400;
state_Tx <= DHCP_REQUEST;
end
else if (DHCP_request_renew) begin
rdaddress <= 700;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (Send_ARP) begin
rdaddress <= 100;
state_Tx <= ARP;
end
else if (ping_reply)begin
rdaddress <= 200;
state_Tx <= PING1;
end
else if (METIS_discovery && IP_valid) begin
Discovery_IP <= PC_IP;
Discovery_MAC <= PC_MAC;
Discovery_Port <= Port;
rdaddress <= 500;
frame <= 8'h02;
METIS_discover_sent <= 1'b1;
state_Tx <= METIS_DISCOVERY;
end
else if (erase_done && IP_valid) begin
erase_done_ACK <= 1'b1;
rdaddress <= 500;
frame <= 8'h03;
state_Tx <= METIS_DISCOVERY;
end
else if (send_more && IP_valid) begin
send_more_ACK <= 1'b1;
rdaddress <= 500;
frame <= 8'h04;
state_Tx <= METIS_DISCOVERY;
end
else if (PHY_Tx_rdused > 1023 && !Tx_reset && run) begin
rdaddress <= 0;
state_Tx <= UDP;
end
else if (have_sp_data && wide_spectrum) begin
rdaddress <= 0;
state_Tx <= SPECTRUM;
end
else state_Tx <= RESET;
end
end
UDP:
begin
end_point <= 8'h06;
if (rdaddress != 58)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= UDP;
end
else
begin
if (data_count != 1024) begin
Tx_data <= PHY_Tx_data;
data_count <= data_count + 1'b1;
state_Tx <= UDP;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
sequence_number <= sequence_number + 1'b1;
state_Tx <= CRC;
end
end
if (rdaddress == 57) Tx_fifo_rdreq <= 1'b1;
if (data_count == 1023) Tx_fifo_rdreq <= 1'b0;
if (rdaddress == 7)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
METIS_DISCOVERY:
begin
if (rdaddress != 560) begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= METIS_DISCOVERY;
end
else if (zero_count < 50)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= METIS_DISCOVERY;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 507)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
ARP:
begin
LED <= 1'b1;
if (rdaddress != 150) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= ARP;
end
else if (zero_count < 18)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= ARP;
end
else begin
ARP_sent <= 1'b1;
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 107)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
PING1:
begin
if (ck_count != (Length - 24)) begin
ping_check_temp <= ping_check_temp + {16'b0,ping_data[ck_count], ping_data[ck_count + 1]};
ck_count <= ck_count + 8'd2;
state_Tx <= PING1;
end
else if (ping_check_temp >> 16 != 0) begin
ping_check_temp <= ((ping_check_temp & 32'h0000FFFF) + (ping_check_temp >> 16));
state_Tx <= PING1;
end
else begin
ping_check_sum <= ~ping_check_temp[15:0];
state_Tx <= PING2;
end
end
PING2:
begin
if (rdaddress != 246)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= PING2;
end
else if (data_count != (Length - 24)) begin
Tx_data <= ping_data[data_count];
data_count <= data_count + 1'd1;
state_Tx <= PING2;
end
else begin
ping_sent <= 1'b1;
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 207)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
DHCP_DISCOVER:
begin
if (rdaddress < 354) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (zero_count < 24)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (rdaddress < 360) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (zero_count < 226)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (rdaddress < 368) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
DHCP_discover_sent <= 1'b1;
state_Tx <= CRC;
end
if (rdaddress == 307)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
DHCP_REQUEST:
begin
if (rdaddress < 454) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (zero_count < 24)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (rdaddress < 460) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (zero_count < 226)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (rdaddress < 480) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
DHCP_request_sent <= 1'b1;
state_Tx <= CRC;
end
if (rdaddress == 407)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
DHCP_REQUEST_RENEW:
begin
if (rdaddress < 766) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (zero_count < 12)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (rdaddress < 772) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (zero_count < 214)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (rdaddress < 780) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
DHCP_request_renew_sent <= 1'b1;
state_Tx <= CRC;
end
if (rdaddress == 707)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
PRINTF:
begin
if (rdaddress != 652)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= PRINTF;
end
else if (data_count != 60) begin
Tx_data <= 0;
data_count <= data_count + 1'b1;
state_Tx <= PRINTF;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 607)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
SPECTRUM:
begin
end_point <= 8'h04;
if (rdaddress != 58)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= SPECTRUM;
end
else
begin
if (sp_data_count != 1024) begin
Tx_data <= sp_fifo_rddata;
sp_data_count <= sp_data_count + 1'b1;
state_Tx <= SPECTRUM;
end
else begin
sp_data_count <= 0;
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
spec_seq_number <= spec_seq_number + 1'b1;
state_Tx <= CRC;
end
end
if (rdaddress == 57) sp_fifo_rdreq <= 1'b1;
if (sp_data_count == 1023) sp_fifo_rdreq <= 1'b0;
if (rdaddress == 7)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
CRC:
begin
if (rdaddress != 61) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= CRC;
end
else begin
sync_Tx_CTL <= 1'b0;
if (interframe == 10) begin
state_Tx <= RESET;
end
else interframe <= interframe + 1'b1;
end
end
endcase
end
CRC32 CRC32_inst(.rst(reset_CRC),.clk(Tx_clock_2), .data(Tx_data), .crc(CRC32));
reg [4:0]PHY_state;
reg sync_Tx_CTL;
reg [3:0] sync_TD;
always @ (negedge Tx_clock)
begin
case (PHY_state)
0: begin
if (sync_Tx_CTL) begin
sync_TD <= Tx_data[3:0];
PHY_state <= 1'b1;
end
else PHY_state <= 0;
end
1: begin
sync_TD <= Tx_data[7:4];
PHY_state <= 0;
end
endcase
end
always @ (posedge Tx_clock)
begin
TD <= sync_TD;
Tx_CTL <= sync_Tx_CTL;
end
reg [3:0]TD;
reg Tx_CTL;
endmodule | module Tx_MAC (Tx_clock, Tx_clock_2, IF_rst, Send_ARP,ping_reply,
PHY_Tx_data, PHY_Tx_rdused, ping_data, LED, Tx_fifo_rdreq,
Tx_CTL, ARP_sent, ping_sent, TD, DHCP_discover, DHCP_discover_sent,
This_MAC,SIADDR, DHCP_request,
DHCP_request_sent, METIS_discovery, PC_IP, PC_MAC,
Port, This_IP, METIS_discover_sent, ARP_PC_MAC, ARP_PC_IP,
Ping_PC_MAC, Ping_PC_IP, Length, speed_100T, Tx_reset, run, wide_spectrum,
IP_valid, printf, IP_lease, DHCP_IP, DHCP_MAC, DHCP_request_renew, DHCP_request_renew_sent,
erase_done, erase_done_ACK, send_more, send_more_ACK, Metis_serialno,
sp_fifo_rddata, sp_fifo_rdreq, have_sp_data, AssignIP); |
input Tx_clock;
input Tx_clock_2;
input IF_rst;
input Send_ARP;
input ping_reply;
input [7:0]PHY_Tx_data;
input [10:0]PHY_Tx_rdused;
input [7:0]ping_data[0:59];
input DHCP_discover;
input [47:0]This_MAC;
input [31:0]SIADDR;
input DHCP_request;
input METIS_discovery;
input [31:0]PC_IP;
input [47:0]PC_MAC;
input [15:0]Port;
input [31:0]This_IP;
input [47:0]ARP_PC_MAC;
input [31:0]ARP_PC_IP;
input [47:0]Ping_PC_MAC;
input [31:0]Ping_PC_IP;
input [15:0]Length;
input speed_100T;
input Tx_reset;
input run;
input wide_spectrum;
input IP_valid;
input printf;
input [31:0]IP_lease;
input [31:0]DHCP_IP;
input [47:0]DHCP_MAC;
input DHCP_request_renew;
input erase_done;
input send_more;
input [7:0]Metis_serialno;
input [7:0]sp_fifo_rddata;
input have_sp_data;
input [31:0]AssignIP;
output LED;
output Tx_fifo_rdreq;
output Tx_CTL;
output ARP_sent;
output ping_sent;
output [3:0]TD;
output DHCP_discover_sent;
output DHCP_request_sent;
output METIS_discover_sent;
output DHCP_request_renew_sent;
output erase_done_ACK;
output send_more_ACK;
output sp_fifo_rdreq;
parameter HPSDR_frame = 8'h01;
parameter HPSDR_IP_frame = 8'h03;
parameter Type_1 = 8'hEF;
parameter Type_2 = 8'hFE;
localparam TxPort = 16'd1024;
localparam IP_MAC = 48'h11_22_33_44_55_66;
localparam
RESET = 0,
UDP = 1,
METIS_DISCOVERY = 2,
ARP = 3,
PING1 = 4,
PING2 = 5,
DHCP_DISCOVER = 6,
DHCP_REQUEST = 7,
DHCP_REQUEST_RENEW = 8,
PRINTF = 9,
SPECTRUM = 10,
SENDIP = 11,
CRC = 12;
wire [31:0] CRC32;
reg [31:0] temp_CRC32 = 0;
reg [31:0] sequence_number = 0;
reg [31:0] spec_seq_number = 0;
reg [6:0] state_Tx;
reg [10:0] data_count;
reg [10:0] sp_data_count;
reg reset_CRC;
reg [7:0] Tx_data;
reg [4:0] gap_count;
reg ARP_sent;
reg LED;
reg erase_done_ACK;
reg send_more_ACK;
reg [31:0]Discovery_IP;
reg [47:0]Discovery_MAC;
reg [15:0]Discovery_Port;
reg [7:0]end_point;
wire have_sp_data;
reg [4:0]IP_count;
wire [31:0]IPchecksum1;
wire [31:0]IPchecksum2;
wire [15:0]IPchecksum3;
assign IPchecksum1 = 32'h0000C935 + This_IP[31:16] + This_IP[15:0] + PC_IP[31:16] + PC_IP[15:0];
assign IPchecksum2 = ((IPchecksum1 & 32'h0000FFFF) + (IPchecksum1 >> 16));
assign IPchecksum3 = ~((IPchecksum2 & 32'h0000FFFF) + (IPchecksum2 >> 16));
wire [31:0]DISchecksum1;
wire [31:0]DISchecksum2;
wire [15:0]DISchecksum3;
assign DISchecksum1 = 32'h00004500 + 32'h00000058 + 32'h00008011 + This_IP[31:16] + This_IP[15:0] +
Discovery_IP[31:16] + Discovery_IP[15:0];
assign DISchecksum2 = ((DISchecksum1 & 32'h0000FFFF) + (DISchecksum1 >> 16));
assign DISchecksum3 = ~((DISchecksum2 & 32'h0000FFFF) + (DISchecksum2 >> 16));
wire [31:0]ICMPchecksum1;
wire [31:0]ICMPchecksum2;
wire [15:0]ICMPchecksum3;
assign ICMPchecksum1 = 32'h00004500 + Length + 32'h00008001 + This_IP[31:16] + This_IP[15:0] +
Ping_PC_IP[31:16] + Ping_PC_IP[15:0];
assign ICMPchecksum2 = ((ICMPchecksum1 & 32'h0000FFFF) + (ICMPchecksum1 >> 16));
assign ICMPchecksum3 = ~((ICMPchecksum2 & 32'h0000FFFF) + (ICMPchecksum2 >> 16));
wire [31:0]DHCPchecksum1;
wire [31:0]DHCPchecksum2;
wire [15:0]DHCPchecksum3;
assign DHCPchecksum1 = 32'h00004500 + UDP_DHCP_length + 32'h00008011 + 32'h0000FFFF + 32'h0000FFFF;
assign DHCPchecksum2 = ((DHCPchecksum1 & 32'h0000FFFF) + (DHCPchecksum1 >> 16));
assign DHCPchecksum3 = ~((DHCPchecksum2 & 32'h0000FFFF) + (DHCPchecksum2 >> 16));
wire [31:0]DHCP_req_checksum1;
wire [31:0]DHCP_req_checksum2;
wire [15:0]DHCP_req_checksum3;
assign DHCP_req_checksum1 = 32'h00004500 + UDP_DHCP_req_length + 32'h00008011 + 32'h0000FFFF + 32'h0000FFFF;
assign DHCP_req_checksum2 = ((DHCP_req_checksum1 & 32'h0000FFFF) + (DHCP_req_checksum1 >> 16));
assign DHCP_req_checksum3 = ~((DHCP_req_checksum2 & 32'h0000FFFF) + (DHCP_req_checksum2 >> 16));
wire [31:0]DHCP_req_renew_checksum1;
wire [31:0]DHCP_req_renew_checksum2;
wire [15:0]DHCP_req_renew_checksum3;
assign DHCP_req_renew_checksum1 = 32'h00004500 + UDP_DHCP_req_renew_length + 32'h00008011 + This_IP[31:16] + This_IP[15:0] +
DHCP_IP[31:16] + DHCP_IP[15:0];
assign DHCP_req_renew_checksum2 = ((DHCP_req_renew_checksum1 & 32'h0000FFFF) + (DHCP_req_renew_checksum1 >> 16));
assign DHCP_req_renew_checksum3 = ~((DHCP_req_renew_checksum2 & 32'h0000FFFF) + (DHCP_req_renew_checksum2 >> 16));
wire [15:0]DHCP_length;
wire [15:0]UDP_DHCP_length;
wire [15:0]DHCP_req_length;
wire [15:0]UDP_DHCP_req_length;
wire [15:0]DHCP_req_renew_length;
wire [15:0]UDP_DHCP_req_renew_length;
reg [9:0] rdaddress;
reg [7:0] pkt_data;
reg [7:0] ck_count;
reg [31:0]ping_check_temp;
reg [15:0]ping_check_sum;
reg ping_sent;
reg [8:0] zero_count;
reg [3:0]interframe;
reg printf;
reg DHCP_request_renew_sent;
reg Metis_discover_sent;
reg [7:0] frame;
reg [31:0]temp_IP;
always @ *
case(rdaddress)
0 : pkt_data <= 8'h55;
1 : pkt_data <= 8'h55;
2 : pkt_data <= 8'h55;
3 : pkt_data <= 8'h55;
4 : pkt_data <= 8'h55;
5 : pkt_data <= 8'h55;
6 : pkt_data <= 8'h55;
7 : pkt_data <= 8'hD5;
8 : pkt_data <= PC_MAC[47:40];
9 : pkt_data <= PC_MAC[39:32];
10: pkt_data <= PC_MAC[31:24];
11: pkt_data <= PC_MAC[23:16];
12: pkt_data <= PC_MAC[15:8];
13: pkt_data <= PC_MAC[7:0];
14: pkt_data <= This_MAC[47:40];
15: pkt_data <= This_MAC[39:32];
16: pkt_data <= This_MAC[31:24];
17: pkt_data <= This_MAC[23:16];
18: pkt_data <= This_MAC[15:8];
19: pkt_data <= This_MAC[7:0];
20: pkt_data <= 8'h08;
21: pkt_data <= 8'h00;
22: pkt_data <= 8'h45;
23: pkt_data <= 8'h00;
24: pkt_data <= 8'h04;
25: pkt_data <= 8'h24;
26: pkt_data <= 8'h00;
27: pkt_data <= 8'h00;
28: pkt_data <= 8'h00;
29: pkt_data <= 8'h00;
30: pkt_data <= 8'h80;
31: pkt_data <= 8'h11;
32: pkt_data <= IPchecksum3[15:8];
33: pkt_data <= IPchecksum3[ 7:0];
34: pkt_data <= This_IP[31:24];
35: pkt_data <= This_IP[23:16];
36: pkt_data <= This_IP[15:8];
37: pkt_data <= This_IP[7:0];
38: pkt_data <= PC_IP[31:24];
39: pkt_data <= PC_IP[23:16];
40: pkt_data <= PC_IP[15:8];
41: pkt_data <= PC_IP[7:0];
42: pkt_data <= TxPort[15:8];
43: pkt_data <= TxPort[7:0];
44: pkt_data <= Port[15:8];
45: pkt_data <= Port[7:0];
46: pkt_data <= 8'h04;
47: pkt_data <= 8'h10;
48: pkt_data <= 8'h00;
49: pkt_data <= 8'h00;
50: pkt_data <= Type_1;
51: pkt_data <= Type_2;
52: pkt_data <= HPSDR_frame;
53: pkt_data <= end_point;
54: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[31:24] : sequence_number[31:24];
55: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[23:16] : sequence_number[23:16];
56: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[15:8] : sequence_number[15:8];
57: pkt_data <= (state_Tx == SPECTRUM) ? spec_seq_number[7:0] : sequence_number[7:0];
58: pkt_data <= temp_CRC32[15:8];
59: pkt_data <= temp_CRC32[23:16];
60: pkt_data <= temp_CRC32[31:24];
100: pkt_data <= 8'h55;
101: pkt_data <= 8'h55;
102: pkt_data <= 8'h55;
103: pkt_data <= 8'h55;
104: pkt_data <= 8'h55;
105: pkt_data <= 8'h55;
106: pkt_data <= 8'h55;
107: pkt_data <= 8'hD5;
108: pkt_data <= ARP_PC_MAC[47:40];
109: pkt_data <= ARP_PC_MAC[39:32];
110: pkt_data <= ARP_PC_MAC[31:24];
111: pkt_data <= ARP_PC_MAC[23:16];
112: pkt_data <= ARP_PC_MAC[15:8];
113: pkt_data <= ARP_PC_MAC[7:0];
114: pkt_data <= This_MAC[47:40];
115: pkt_data <= This_MAC[39:32];
116: pkt_data <= This_MAC[31:24];
117: pkt_data <= This_MAC[23:16];
118: pkt_data <= This_MAC[15:8];
119: pkt_data <= This_MAC[7:0];
120: pkt_data <= 8'h08;
121: pkt_data <= 8'h06;
122: pkt_data <= 8'h00;
123: pkt_data <= 8'h01;
124: pkt_data <= 8'h08;
125: pkt_data <= 8'h00;
126: pkt_data <= 8'h06;
127: pkt_data <= 8'h04;
128: pkt_data <= 8'h00;
129: pkt_data <= 8'h02;
130: pkt_data <= This_MAC[47:40];
131: pkt_data <= This_MAC[39:32];
132: pkt_data <= This_MAC[31:24];
133: pkt_data <= This_MAC[23:16];
134: pkt_data <= This_MAC[15:8];
135: pkt_data <= This_MAC[7:0];
136: pkt_data <= This_IP[31:24];
137: pkt_data <= This_IP[23:16];
138: pkt_data <= This_IP[15:8];
139: pkt_data <= This_IP[7:0];
140: pkt_data <= ARP_PC_MAC[47:40];
141: pkt_data <= ARP_PC_MAC[39:32];
142: pkt_data <= ARP_PC_MAC[31:24];
143: pkt_data <= ARP_PC_MAC[23:16];
144: pkt_data <= ARP_PC_MAC[15:8];
145: pkt_data <= ARP_PC_MAC[7:0];
146: pkt_data <= ARP_PC_IP[31:24];
147: pkt_data <= ARP_PC_IP[23:16];
148: pkt_data <= ARP_PC_IP[15:8];
149: pkt_data <= ARP_PC_IP[7:0];
200: pkt_data <= 8'h55;
201: pkt_data <= 8'h55;
202: pkt_data <= 8'h55;
203: pkt_data <= 8'h55;
204: pkt_data <= 8'h55;
205: pkt_data <= 8'h55;
206: pkt_data <= 8'h55;
207: pkt_data <= 8'hD5;
208: pkt_data <= Ping_PC_MAC[47:40];
209: pkt_data <= Ping_PC_MAC[39:32];
210: pkt_data <= Ping_PC_MAC[31:24];
211: pkt_data <= Ping_PC_MAC[23:16];
212: pkt_data <= Ping_PC_MAC[15:8];
213: pkt_data <= Ping_PC_MAC[7:0];
214: pkt_data <= This_MAC[47:40];
215: pkt_data <= This_MAC[39:32];
216: pkt_data <= This_MAC[31:24];
217: pkt_data <= This_MAC[23:16];
218: pkt_data <= This_MAC[15:8];
219: pkt_data <= This_MAC[7:0];
220: pkt_data <= 8'h08;
221: pkt_data <= 8'h00;
222: pkt_data <= 8'h45;
223: pkt_data <= 8'h00;
224: pkt_data <= Length[15:8];
225: pkt_data <= Length[7:0];
226: pkt_data <= 8'h00;
227: pkt_data <= 8'h00;
228: pkt_data <= 8'h00;
229: pkt_data <= 8'h00;
230: pkt_data <= 8'h80;
231: pkt_data <= 8'h01;
232: pkt_data <= ICMPchecksum3[15:8];
233: pkt_data <= ICMPchecksum3[ 7:0];
234: pkt_data <= This_IP[31:24];
235: pkt_data <= This_IP[23:16];
236: pkt_data <= This_IP[15:8];
237: pkt_data <= This_IP[7:0];
238: pkt_data <= Ping_PC_IP[31:24];
239: pkt_data <= Ping_PC_IP[23:16];
240: pkt_data <= Ping_PC_IP[15:8];
241: pkt_data <= Ping_PC_IP[7:0];
242: pkt_data <= 8'h00;
243: pkt_data <= 8'h00;
244: pkt_data <= ping_check_sum[15:8];
245: pkt_data <= ping_check_sum[7:0];
300: pkt_data <= 8'h55;
301: pkt_data <= 8'h55;
302: pkt_data <= 8'h55;
303: pkt_data <= 8'h55;
304: pkt_data <= 8'h55;
305: pkt_data <= 8'h55;
306: pkt_data <= 8'h55;
307: pkt_data <= 8'hD5;
308: pkt_data <= 8'hFF;
309: pkt_data <= 8'hFF;
310: pkt_data <= 8'hFF;
311: pkt_data <= 8'hFF;
312: pkt_data <= 8'hFF;
313: pkt_data <= 8'hFF;
314: pkt_data <= This_MAC[47:40];
315: pkt_data <= This_MAC[39:32];
316: pkt_data <= This_MAC[31:24];
317: pkt_data <= This_MAC[23:16];
318: pkt_data <= This_MAC[15:8];
319: pkt_data <= This_MAC[7:0];
320: pkt_data <= 8'h08;
321: pkt_data <= 8'h00;
322: pkt_data <= 8'h45;
323: pkt_data <= 8'h00;
324: pkt_data <= UDP_DHCP_length[15:8];
325: pkt_data <= UDP_DHCP_length[7:0];
326: pkt_data <= 8'h00;
327: pkt_data <= 8'h00;
328: pkt_data <= 8'h00;
329: pkt_data <= 8'h00;
330: pkt_data <= 8'h80;
331: pkt_data <= 8'h11;
332: pkt_data <= DHCPchecksum3[15:8];
333: pkt_data <= DHCPchecksum3[ 7:0];
334: pkt_data <= 8'h00;
335: pkt_data <= 8'h00;
336: pkt_data <= 8'h00;
337: pkt_data <= 8'h00;
338: pkt_data <= 8'hFF;
339: pkt_data <= 8'hFF;
340: pkt_data <= 8'hFF;
341: pkt_data <= 8'hFF;
342: pkt_data <= 8'h00;
343: pkt_data <= 8'h44;
344: pkt_data <= 8'h00;
345: pkt_data <= 8'h43;
346: pkt_data <= DHCP_length[15:8];
347: pkt_data <= DHCP_length[7:0];
348: pkt_data <= 8'h00;
349: pkt_data <= 8'h00;
350: pkt_data <= 8'h01;
351: pkt_data <= 8'h01;
352: pkt_data <= 8'h06;
353: pkt_data <= 8'h00;
354: pkt_data <= This_MAC[47:40];
355: pkt_data <= This_MAC[39:32];
356: pkt_data <= This_MAC[31:24];
357: pkt_data <= This_MAC[23:16];
358: pkt_data <= This_MAC[15:8];
359: pkt_data <= This_MAC[7:0];
360: pkt_data <= 8'h63;
361: pkt_data <= 8'h82;
362: pkt_data <= 8'h53;
363: pkt_data <= 8'h63;
364: pkt_data <= 8'h35;
365: pkt_data <= 8'h01;
366: pkt_data <= 8'h01;
367: pkt_data <= 8'hFF;
400: pkt_data <= 8'h55;
401: pkt_data <= 8'h55;
402: pkt_data <= 8'h55;
403: pkt_data <= 8'h55;
404: pkt_data <= 8'h55;
405: pkt_data <= 8'h55;
406: pkt_data <= 8'h55;
407: pkt_data <= 8'hD5;
408: pkt_data <= 8'hFF;
409: pkt_data <= 8'hFF;
410: pkt_data <= 8'hFF;
411: pkt_data <= 8'hFF;
412: pkt_data <= 8'hFF;
413: pkt_data <= 8'hFF;
414: pkt_data <= This_MAC[47:40];
415: pkt_data <= This_MAC[39:32];
416: pkt_data <= This_MAC[31:24];
417: pkt_data <= This_MAC[23:16];
418: pkt_data <= This_MAC[15:8];
419: pkt_data <= This_MAC[7:0];
420: pkt_data <= 8'h08;
421: pkt_data <= 8'h00;
422: pkt_data <= 8'h45;
423: pkt_data <= 8'h00;
424: pkt_data <= UDP_DHCP_req_length[15:8];
425: pkt_data <= UDP_DHCP_req_length[7:0];
426: pkt_data <= 8'h00;
427: pkt_data <= 8'h00;
428: pkt_data <= 8'h00;
429: pkt_data <= 8'h00;
430: pkt_data <= 8'h80;
431: pkt_data <= 8'h11;
432: pkt_data <= DHCP_req_checksum3[15:8];
433: pkt_data <= DHCP_req_checksum3[ 7:0];
434: pkt_data <= 8'h00;
435: pkt_data <= 8'h00;
436: pkt_data <= 8'h00;
437: pkt_data <= 8'h00;
438: pkt_data <= 8'hFF;
439: pkt_data <= 8'hFF;
440: pkt_data <= 8'hFF;
441: pkt_data <= 8'hFF;
442: pkt_data <= 8'h00;
443: pkt_data <= 8'h44;
444: pkt_data <= 8'h00;
445: pkt_data <= 8'h43;
446: pkt_data <= DHCP_req_length[15:8];
447: pkt_data <= DHCP_req_length[7:0];
448: pkt_data <= 8'h00;
449: pkt_data <= 8'h00;
450: pkt_data <= 8'h01;
451: pkt_data <= 8'h01;
452: pkt_data <= 8'h06;
453: pkt_data <= 8'h00;
454: pkt_data <= This_MAC[47:40];
455: pkt_data <= This_MAC[39:32];
456: pkt_data <= This_MAC[31:24];
457: pkt_data <= This_MAC[23:16];
458: pkt_data <= This_MAC[15:8];
459: pkt_data <= This_MAC[7:0];
460: pkt_data <= 8'h63;
461: pkt_data <= 8'h82;
462: pkt_data <= 8'h53;
463: pkt_data <= 8'h63;
464: pkt_data <= 8'h35;
465: pkt_data <= 8'h01;
466: pkt_data <= 8'h03;
467: pkt_data <= 8'h32;
468: pkt_data <= 8'h04;
469: pkt_data <= This_IP[31:24];
470: pkt_data <= This_IP[23:16];
471: pkt_data <= This_IP[15:8];
472: pkt_data <= This_IP[7:0];
473: pkt_data <= 8'h36;
474: pkt_data <= 8'h04;
475: pkt_data <= DHCP_IP[31:24];
476: pkt_data <= DHCP_IP[23:16];
477: pkt_data <= DHCP_IP[15:8];
478: pkt_data <= DHCP_IP[7:0];
479: pkt_data <= 8'hFF;
500: pkt_data <= 8'h55;
501: pkt_data <= 8'h55;
502: pkt_data <= 8'h55;
503: pkt_data <= 8'h55;
504: pkt_data <= 8'h55;
505: pkt_data <= 8'h55;
506: pkt_data <= 8'h55;
507: pkt_data <= 8'hD5;
508: pkt_data <= Discovery_MAC[47:40];
509: pkt_data <= Discovery_MAC[39:32];
510: pkt_data <= Discovery_MAC[31:24];
511: pkt_data <= Discovery_MAC[23:16];
512: pkt_data <= Discovery_MAC[15:8];
513: pkt_data <= Discovery_MAC[7:0];
514: pkt_data <= This_MAC[47:40];
515: pkt_data <= This_MAC[39:32];
516: pkt_data <= This_MAC[31:24];
517: pkt_data <= This_MAC[23:16];
518: pkt_data <= This_MAC[15:8];
519: pkt_data <= This_MAC[7:0];
520: pkt_data <= 8'h08;
521: pkt_data <= 8'h00;
522: pkt_data <= 8'h45;
523: pkt_data <= 8'h00;
524: pkt_data <= 8'h00;
525: pkt_data <= 8'h58;
526: pkt_data <= 8'h00;
527: pkt_data <= 8'h00;
528: pkt_data <= 8'h00;
529: pkt_data <= 8'h00;
530: pkt_data <= 8'h80;
531: pkt_data <= 8'h11;
532: pkt_data <= DISchecksum3[15:8];
533: pkt_data <= DISchecksum3[ 7:0];
534: pkt_data <= This_IP[31:24];
535: pkt_data <= This_IP[23:16];
536: pkt_data <= This_IP[15:8];
537: pkt_data <= This_IP[7:0];
538: pkt_data <= Discovery_IP[31:24];
539: pkt_data <= Discovery_IP[23:16];
540: pkt_data <= Discovery_IP[15:8];
541: pkt_data <= Discovery_IP[7:0];
542: pkt_data <= TxPort[15:8];
543: pkt_data <= TxPort[7:0];
544: pkt_data <= Discovery_Port[15:8];
545: pkt_data <= Discovery_Port[7:0];
546: pkt_data <= 8'h00;
547: pkt_data <= 8'h44;
548: pkt_data <= 8'h00;
549: pkt_data <= 8'h00;
550: pkt_data <= Type_1;
551: pkt_data <= Type_2;
552: pkt_data <= frame + run;
553: pkt_data <= This_MAC[47:40];
554: pkt_data <= This_MAC[39:32];
555: pkt_data <= This_MAC[31:24];
556: pkt_data <= This_MAC[23:16];
557: pkt_data <= This_MAC[15:8];
558: pkt_data <= This_MAC[7:0];
559: pkt_data <= Metis_serialno;
600 : pkt_data <= 8'h55;
601 : pkt_data <= 8'h55;
602 : pkt_data <= 8'h55;
603 : pkt_data <= 8'h55;
604 : pkt_data <= 8'h55;
605 : pkt_data <= 8'h55;
606 : pkt_data <= 8'h55;
607 : pkt_data <= 8'hD5;
608 : pkt_data <= 8'hFF;
609 : pkt_data <= 8'hFF;
610 : pkt_data <= 8'hFF;
611 : pkt_data <= 8'hFF;
612 : pkt_data <= 8'hFF;
613 : pkt_data <= 8'hFF;
614 : pkt_data <= This_MAC[47:40];
615 : pkt_data <= This_MAC[39:32];
616 : pkt_data <= This_MAC[31:24];
617 : pkt_data <= This_MAC[23:16];
618 : pkt_data <= This_MAC[15:8];
619 : pkt_data <= This_MAC[7:0];
620: pkt_data <= 8'hEF;
621: pkt_data <= 8'hFF;
622: pkt_data <= HPSDR_frame;
623: pkt_data <= 8'hFF;
624: pkt_data <= This_IP[31:24];
625: pkt_data <= This_IP[23:16];
626: pkt_data <= This_IP[15:8];
627: pkt_data <= This_IP[7:0];
628: pkt_data <= PC_IP[31:24];
629: pkt_data <= PC_IP[23:16];
630: pkt_data <= PC_IP[15:8];
631: pkt_data <= PC_IP[7:0];
632: pkt_data <= PC_MAC[47:40];
633: pkt_data <= PC_MAC[39:32];
634: pkt_data <= PC_MAC[31:24];
635: pkt_data <= PC_MAC[23:16];
636: pkt_data <= PC_MAC[15:8];
637: pkt_data <= PC_MAC[7:0];
638: pkt_data <= IP_lease[31:24];
639: pkt_data <= IP_lease[23:16];
640: pkt_data <= IP_lease[15:8];
641: pkt_data <= IP_lease[7:0];
642: pkt_data <= DHCP_IP[31:24];
643: pkt_data <= DHCP_IP[23:16];
644: pkt_data <= DHCP_IP[15:8];
645: pkt_data <= DHCP_IP[7:0];
646: pkt_data <= DHCP_MAC[47:40];
647: pkt_data <= DHCP_MAC[39:32];
648: pkt_data <= DHCP_MAC[31:24];
649: pkt_data <= DHCP_MAC[23:16];
650: pkt_data <= DHCP_MAC[15:8];
651: pkt_data <= DHCP_MAC[7:0];
700: pkt_data <= 8'h55;
701: pkt_data <= 8'h55;
702: pkt_data <= 8'h55;
703: pkt_data <= 8'h55;
704: pkt_data <= 8'h55;
705: pkt_data <= 8'h55;
706: pkt_data <= 8'h55;
707: pkt_data <= 8'hD5;
708: pkt_data <= DHCP_MAC[47:40];
709: pkt_data <= DHCP_MAC[39:32];
710: pkt_data <= DHCP_MAC[31:24];
711: pkt_data <= DHCP_MAC[23:16];
712: pkt_data <= DHCP_MAC[15:8];
713: pkt_data <= DHCP_MAC[7:0];
714: pkt_data <= This_MAC[47:40];
715: pkt_data <= This_MAC[39:32];
716: pkt_data <= This_MAC[31:24];
717: pkt_data <= This_MAC[23:16];
718: pkt_data <= This_MAC[15:8];
719: pkt_data <= This_MAC[7:0];
720: pkt_data <= 8'h08;
721: pkt_data <= 8'h00;
722: pkt_data <= 8'h45;
723: pkt_data <= 8'h00;
724: pkt_data <= UDP_DHCP_req_renew_length[15:8];
725: pkt_data <= UDP_DHCP_req_renew_length[7:0];
726: pkt_data <= 8'h00;
727: pkt_data <= 8'h00;
728: pkt_data <= 8'h00;
729: pkt_data <= 8'h00;
730: pkt_data <= 8'h80;
731: pkt_data <= 8'h11;
732: pkt_data <= DHCP_req_renew_checksum3[15:8];
733: pkt_data <= DHCP_req_renew_checksum3[ 7:0];
734: pkt_data <= This_IP[31:24];
735: pkt_data <= This_IP[23:16];
736: pkt_data <= This_IP[15:8];
737: pkt_data <= This_IP[7:0];
738: pkt_data <= DHCP_IP[31:24];
739: pkt_data <= DHCP_IP[23:16];
740: pkt_data <= DHCP_IP[15:8];
741: pkt_data <= DHCP_IP[7:0];
742: pkt_data <= 8'h00;
743: pkt_data <= 8'h44;
744: pkt_data <= 8'h00;
745: pkt_data <= 8'h43;
746: pkt_data <= DHCP_req_renew_length[15:8];
747: pkt_data <= DHCP_req_renew_length[7:0];
748: pkt_data <= 8'h00;
749: pkt_data <= 8'h00;
750: pkt_data <= 8'h01;
751: pkt_data <= 8'h01;
752: pkt_data <= 8'h06;
753: pkt_data <= 8'h00;
754: pkt_data <= 8'h00;
755: pkt_data <= 8'h00;
756: pkt_data <= 8'h00;
757: pkt_data <= 8'h00;
758: pkt_data <= 8'h00;
759: pkt_data <= 8'h00;
760: pkt_data <= 8'h00;
761: pkt_data <= 8'h00;
762: pkt_data <= This_IP[31:24];
763: pkt_data <= This_IP[23:16];
764: pkt_data <= This_IP[15:8];
765: pkt_data <= This_IP[7:0];
766: pkt_data <= This_MAC[47:40];
767: pkt_data <= This_MAC[39:32];
768: pkt_data <= This_MAC[31:24];
769: pkt_data <= This_MAC[23:16];
770: pkt_data <= This_MAC[15:8];
771: pkt_data <= This_MAC[7:0];
772: pkt_data <= 8'h63;
773: pkt_data <= 8'h82;
774: pkt_data <= 8'h53;
775: pkt_data <= 8'h63;
776: pkt_data <= 8'h35;
777: pkt_data <= 8'h01;
778: pkt_data <= 8'h03;
779: pkt_data <= 8'hFF;
default: pkt_data <= 0;
endcase
assign DHCP_length = 16'd8 + (16'd367 - 16'd350 + 16'd1) + 16'd24 + 16'd202;
assign UDP_DHCP_length = DHCP_length + 16'd20;
assign DHCP_req_length = 16'd8 + (16'd479 - 16'd450 + 16'd1) + 16'd24 + 16'd202;
assign UDP_DHCP_req_length = DHCP_req_length + 16'd20;
assign DHCP_req_renew_length = 16'd8 + (16'd779 - 16'd750 + 16'd1) + 16'd12 + 16'd202;
assign UDP_DHCP_req_renew_length = DHCP_req_renew_length + 16'd20;
always @ (negedge Tx_clock_2)
begin
case(state_Tx)
RESET:
begin
LED <= 1'b0;
sync_Tx_CTL <= 1'b0;
data_count <= 0;
reset_CRC <= 0;
rdaddress <= 0;
ARP_sent <= 0;
ping_sent <= 0;
ping_check_temp <= 0;
ck_count <= 0;
zero_count <= 0;
DHCP_discover_sent <= 0;
DHCP_request_sent <= 0;
METIS_discover_sent <= 0;
DHCP_request_renew_sent <= 0;
interframe <= 0;
erase_done_ACK <= 0;
send_more_ACK <= 0;
IP_count <= 0;
if (IF_rst)
state_Tx <= RESET;
else begin
if (run == 1'b0) begin
sequence_number <= 0;
spec_seq_number <= 0;
end
if (printf) begin
rdaddress <= 600;
state_Tx <= PRINTF;
end
else if (DHCP_discover) begin
rdaddress <= 300;
state_Tx <= DHCP_DISCOVER;
end
else if (DHCP_request) begin
rdaddress <= 400;
state_Tx <= DHCP_REQUEST;
end
else if (DHCP_request_renew) begin
rdaddress <= 700;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (Send_ARP) begin
rdaddress <= 100;
state_Tx <= ARP;
end
else if (ping_reply)begin
rdaddress <= 200;
state_Tx <= PING1;
end
else if (METIS_discovery && IP_valid) begin
Discovery_IP <= PC_IP;
Discovery_MAC <= PC_MAC;
Discovery_Port <= Port;
rdaddress <= 500;
frame <= 8'h02;
METIS_discover_sent <= 1'b1;
state_Tx <= METIS_DISCOVERY;
end
else if (erase_done && IP_valid) begin
erase_done_ACK <= 1'b1;
rdaddress <= 500;
frame <= 8'h03;
state_Tx <= METIS_DISCOVERY;
end
else if (send_more && IP_valid) begin
send_more_ACK <= 1'b1;
rdaddress <= 500;
frame <= 8'h04;
state_Tx <= METIS_DISCOVERY;
end
else if (PHY_Tx_rdused > 1023 && !Tx_reset && run) begin
rdaddress <= 0;
state_Tx <= UDP;
end
else if (have_sp_data && wide_spectrum) begin
rdaddress <= 0;
state_Tx <= SPECTRUM;
end
else state_Tx <= RESET;
end
end
UDP:
begin
end_point <= 8'h06;
if (rdaddress != 58)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= UDP;
end
else
begin
if (data_count != 1024) begin
Tx_data <= PHY_Tx_data;
data_count <= data_count + 1'b1;
state_Tx <= UDP;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
sequence_number <= sequence_number + 1'b1;
state_Tx <= CRC;
end
end
if (rdaddress == 57) Tx_fifo_rdreq <= 1'b1;
if (data_count == 1023) Tx_fifo_rdreq <= 1'b0;
if (rdaddress == 7)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
METIS_DISCOVERY:
begin
if (rdaddress != 560) begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= METIS_DISCOVERY;
end
else if (zero_count < 50)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= METIS_DISCOVERY;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 507)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
ARP:
begin
LED <= 1'b1;
if (rdaddress != 150) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= ARP;
end
else if (zero_count < 18)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= ARP;
end
else begin
ARP_sent <= 1'b1;
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 107)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
PING1:
begin
if (ck_count != (Length - 24)) begin
ping_check_temp <= ping_check_temp + {16'b0,ping_data[ck_count], ping_data[ck_count + 1]};
ck_count <= ck_count + 8'd2;
state_Tx <= PING1;
end
else if (ping_check_temp >> 16 != 0) begin
ping_check_temp <= ((ping_check_temp & 32'h0000FFFF) + (ping_check_temp >> 16));
state_Tx <= PING1;
end
else begin
ping_check_sum <= ~ping_check_temp[15:0];
state_Tx <= PING2;
end
end
PING2:
begin
if (rdaddress != 246)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= PING2;
end
else if (data_count != (Length - 24)) begin
Tx_data <= ping_data[data_count];
data_count <= data_count + 1'd1;
state_Tx <= PING2;
end
else begin
ping_sent <= 1'b1;
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 207)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
DHCP_DISCOVER:
begin
if (rdaddress < 354) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (zero_count < 24)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (rdaddress < 360) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (zero_count < 226)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else if (rdaddress < 368) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_DISCOVER;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
DHCP_discover_sent <= 1'b1;
state_Tx <= CRC;
end
if (rdaddress == 307)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
DHCP_REQUEST:
begin
if (rdaddress < 454) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (zero_count < 24)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (rdaddress < 460) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (zero_count < 226)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else if (rdaddress < 480) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
DHCP_request_sent <= 1'b1;
state_Tx <= CRC;
end
if (rdaddress == 407)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
DHCP_REQUEST_RENEW:
begin
if (rdaddress < 766) begin
sync_Tx_CTL <= 1'b1;
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (zero_count < 12)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (rdaddress < 772) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (zero_count < 214)begin
Tx_data <= 8'h00;
zero_count <= zero_count + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else if (rdaddress < 780) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= DHCP_REQUEST_RENEW;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
DHCP_request_renew_sent <= 1'b1;
state_Tx <= CRC;
end
if (rdaddress == 707)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
PRINTF:
begin
if (rdaddress != 652)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= PRINTF;
end
else if (data_count != 60) begin
Tx_data <= 0;
data_count <= data_count + 1'b1;
state_Tx <= PRINTF;
end
else begin
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
state_Tx <= CRC;
end
if (rdaddress == 607)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
SPECTRUM:
begin
end_point <= 8'h04;
if (rdaddress != 58)
begin
Tx_data <= pkt_data;
sync_Tx_CTL <= 1'b1;
rdaddress <= rdaddress + 1'b1;
state_Tx <= SPECTRUM;
end
else
begin
if (sp_data_count != 1024) begin
Tx_data <= sp_fifo_rddata;
sp_data_count <= sp_data_count + 1'b1;
state_Tx <= SPECTRUM;
end
else begin
sp_data_count <= 0;
temp_CRC32 <= CRC32;
Tx_data <= CRC32[7:0];
rdaddress <= 58;
spec_seq_number <= spec_seq_number + 1'b1;
state_Tx <= CRC;
end
end
if (rdaddress == 57) sp_fifo_rdreq <= 1'b1;
if (sp_data_count == 1023) sp_fifo_rdreq <= 1'b0;
if (rdaddress == 7)
reset_CRC <= 1'b1;
else
reset_CRC <= 1'b0;
end
CRC:
begin
if (rdaddress != 61) begin
Tx_data <= pkt_data;
rdaddress <= rdaddress + 1'b1;
state_Tx <= CRC;
end
else begin
sync_Tx_CTL <= 1'b0;
if (interframe == 10) begin
state_Tx <= RESET;
end
else interframe <= interframe + 1'b1;
end
end
endcase
end
CRC32 CRC32_inst(.rst(reset_CRC),.clk(Tx_clock_2), .data(Tx_data), .crc(CRC32));
reg [4:0]PHY_state;
reg sync_Tx_CTL;
reg [3:0] sync_TD;
always @ (negedge Tx_clock)
begin
case (PHY_state)
0: begin
if (sync_Tx_CTL) begin
sync_TD <= Tx_data[3:0];
PHY_state <= 1'b1;
end
else PHY_state <= 0;
end
1: begin
sync_TD <= Tx_data[7:4];
PHY_state <= 0;
end
endcase
end
always @ (posedge Tx_clock)
begin
TD <= sync_TD;
Tx_CTL <= sync_Tx_CTL;
end
reg [3:0]TD;
reg Tx_CTL;
endmodule | 17 |
138,872 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.1/ADC.v | 86,169,941 | ADC.v | v | 106 | 106 | [] | ['general public license', 'free software foundation'] | [] | [(31, 104)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.1,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.1/ADC.v\n%Error: Exiting due to 4 error(s)\n' | 303,812 | module | module ADC(clock, SCLK, nCS, MISO, MOSI, AIN5);
input wire clock;
output reg SCLK;
output reg nCS;
input wire MISO;
output reg MOSI;
output reg [11:0] AIN5;
wire [15:0] data;
reg [2:0] ADC_state;
reg [3:0] bit_cnt;
reg [11:0] temp_AIN5;
assign data = 16'b0010_0000_0000_0000;
always @ (posedge clock)
begin
case (ADC_state)
0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
ADC_state <= 1;
end
1:
begin
nCS <= 0;
MOSI <= data[bit_cnt];
ADC_state <= 2;
end
2:
begin
SCLK <= 1'b1;
ADC_state <= 3;
end
3:
begin
SCLK <= 1'b0;
ADC_state <= 4;
end
4:
begin
if (bit_cnt == 0)
ADC_state <= 0;
else
begin
bit_cnt <= bit_cnt - 1'b1;
ADC_state <= 1;
end
end
default:
ADC_state <= 0;
endcase
end
always @ (posedge clock)
begin
if (ADC_state == 0)
AIN5 <= temp_AIN5;
if (SCLK && (bit_cnt <= 11))
temp_AIN5[bit_cnt] <= MISO;
end
endmodule | module ADC(clock, SCLK, nCS, MISO, MOSI, AIN5); |
input wire clock;
output reg SCLK;
output reg nCS;
input wire MISO;
output reg MOSI;
output reg [11:0] AIN5;
wire [15:0] data;
reg [2:0] ADC_state;
reg [3:0] bit_cnt;
reg [11:0] temp_AIN5;
assign data = 16'b0010_0000_0000_0000;
always @ (posedge clock)
begin
case (ADC_state)
0:
begin
nCS <= 1'b1;
bit_cnt <= 4'd15;
ADC_state <= 1;
end
1:
begin
nCS <= 0;
MOSI <= data[bit_cnt];
ADC_state <= 2;
end
2:
begin
SCLK <= 1'b1;
ADC_state <= 3;
end
3:
begin
SCLK <= 1'b0;
ADC_state <= 4;
end
4:
begin
if (bit_cnt == 0)
ADC_state <= 0;
else
begin
bit_cnt <= bit_cnt - 1'b1;
ADC_state <= 1;
end
end
default:
ADC_state <= 0;
endcase
end
always @ (posedge clock)
begin
if (ADC_state == 0)
AIN5 <= temp_AIN5;
if (SCLK && (bit_cnt <= 11))
temp_AIN5[bit_cnt] <= MISO;
end
endmodule | 17 |
138,874 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.1/cordic.v | 86,169,941 | cordic.v | v | 200 | 94 | [] | [] | [] | [(52, 197)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.1,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.1/cordic.v\n%Error: Exiting due to 4 error(s)\n' | 303,815 | module | module cordic_16(i_in, q_in, iout, qout, ain, clk);
input [19:0] ain;
input [15:0] i_in, q_in;
output [17:0] iout, qout;
reg [17:0] iout, qout;
input clk;
reg [18:0] a0;
reg [17:0] a1;
reg [17:0] a2;
reg [16:0] a3;
reg [15:0] a4;
reg [14:0] a5;
reg [13:0] a6;
reg [12:0] a7;
reg [11:0] a8;
reg [10:0] a9;
reg [9:0] a10;
reg [8:0] a11;
reg [7:0] a12;
reg [6:0] a13;
reg [5:0] a14;
reg [4:0] a15;
reg [3:0] a16;
reg [19:0] i0,i1, i2, i3, i4, i5, i6, i7, i8, i9;
reg [19:0] i10, i11, i12, i13, i14, i15, i16, i17;
reg [19:0] q0, q1, q2, q3, q4, q5, q6, q7, q8, q9;
reg [19:0] q10, q11, q12, q13, q14, q15, q16, q17;
always @ (posedge clk)
begin
a0 <= ain[18:0];
case (ain[19:18])
2'b00,2'b11: begin
i0 <= {i_in[15],i_in,3'd0};
q0 <= {q_in[15],q_in,3'd0};
end
2'b01,2'b10: begin
i0 <= -{i_in[15],i_in,3'd0};
q0 <= -{q_in[15],q_in,3'd0};
end
endcase
a1 <= a0[18] ? a0[17:0] + 18'd131072 : a0[17:0] - 18'd131072;
i1 <= a0[18] ? i0 + q0 : i0 - q0;
q1 <= a0[18] ? q0 - i0 : q0 + i0;
a2 <= a1[17] ? a1 + 18'd77376 : a1 - 18'd77376;
i2 <= a1[17] ? i1 + {q1[19], q1[19:1]}: i1 - {q1[19], q1[19:1]};
q2 <= a1[17] ? q1 - {i1[19], i1[19:1]}: q1 + {i1[19], i1[19:1]};
a3 <= a2[17] ? a2[16:0] + 17'd40884 : a2[16:0] - 17'd40884;
i3 <= a2[17] ? i2 + {{2{q2[19]}}, q2[19:2]}: i2 - {{2{q2[19]}}, q2[19:2]};
q3 <= a2[17] ? q2 - {{2{i2[19]}}, i2[19:2]}: q2 + {{2{i2[19]}}, i2[19:2]};
a4 <= a3[16] ? a3[15:0] + 16'd20753 : a3[15:0] - 16'd20753;
i4 <= a3[16] ? i3 + {{3{q3[19]}}, q3[19:3]}: i3 - {{3{q3[19]}}, q3[19:3]};
q4 <= a3[16] ? q3 - {{3{i3[19]}}, i3[19:3]}: q3 + {{3{i3[19]}}, i3[19:3]};
a5 <= a4[15] ? a4[14:0] + 15'd10417 : a4[14:0] - 15'd10417;
i5 <= a4[15] ? i4 + {{4{q4[19]}}, q4[19:4]}: i4 - {{4{q4[19]}}, q4[19:4]};
q5 <= a4[15] ? q4 - {{4{i4[19]}}, i4[19:4]}: q4 + {{4{i4[19]}}, i4[19:4]};
a6 <= a5[14] ? a5[13:0] + 14'd5213 : a5[13:0] - 14'd5213;
i6 <= a5[14] ? i5 + {{5{q5[19]}}, q5[19:5]}: i5 - {{5{q5[19]}}, q5[19:5]};
q6 <= a5[14] ? q5 - {{5{i5[19]}}, i5[19:5]}: q5 + {{5{i5[19]}}, i5[19:5]};
a7 <= a6[13] ? a6[12:0] + 13'd2607 : a6[12:0] - 13'd2607;
i7 <= a6[13] ? i6 + {{6{q6[19]}}, q6[19:6]}: i6 - {{6{q6[19]}}, q6[19:6]};
q7 <= a6[13] ? q6 - {{6{i6[19]}}, i6[19:6]}: q6 + {{6{i6[19]}}, i6[19:6]};
a8 <= a7[12] ? a7[11:0] + 12'd1304 : a7[11:0] - 12'd1304;
i8 <= a7[12] ? i7 + {{7{q7[19]}}, q7[19:7]}: i7 - {{7{q7[19]}}, q7[19:7]};
q8 <= a7[12] ? q7 - {{7{i7[19]}}, i7[19:7]}: q7 + {{7{i7[19]}}, i7[19:7]};
a9 <= a8[11] ? a8[10:0] + 11'd652 : a8[10:0] - 11'd652;
i9 <= a8[11] ? i8 + {{8{q8[19]}}, q8[19:8]}: i8 - {{8{q8[19]}}, q8[19:8]};
q9 <= a8[11] ? q8 - {{8{i8[19]}}, i8[19:8]}: q8 + {{8{i8[19]}}, i8[19:8]};
a10 <= a9[10] ? a9[9:0] + 10'd326 : a9[9:0] - 10'd326;
i10 <= a9[10] ? i9 + {{9{q9[19]}}, q9[19:9]}: i9 - {{9{q9[19]}}, q9[19:9]};
q10 <= a9[10] ? q9 - {{9{i9[19]}}, i9[19:9]}: q9 + {{9{i9[19]}}, i9[19:9]};
a11 <= a10[9] ? a10[8:0] + 9'd163 : a10[8:0] - 9'd163;
i11 <= a10[9] ? i10 + {{10{q10[19]}}, q10[19:10]}: i10 - {{10{q10[19]}}, q10[19:10]};
q11 <= a10[9] ? q10 - {{10{i10[19]}}, i10[19:10]}: q10 + {{10{i10[19]}}, i10[19:10]};
a12 <= a11[8] ? a11[7:0] + 8'd81 : a11[7:0] - 8'd81;
i12 <= a11[8] ? i11 + {{11{q11[19]}}, q11[19:11]}: i11 - {{11{q11[19]}}, q11[19:11]};
q12 <= a11[8] ? q11 - {{11{i11[19]}}, i11[19:11]}: q11 + {{11{i11[19]}}, i11[19:11]};
a13 <= a12[7] ? a12[6:0] + 7'd41 : a12[6:0] - 7'd41;
i13 <= a12[7] ? i12 + {{12{q12[19]}}, q12[19:12]}: i12 - {{12{q12[19]}}, q12[19:12]};
q13 <= a12[7] ? q12 - {{12{i12[19]}}, i12[19:12]}: q12 + {{12{i12[19]}}, i12[19:12]};
a14 <= a13[6] ? a13[5:0] + 6'd20 : a13[5:0] - 6'd20;
i14 <= a13[6] ? i13 + {{13{q13[19]}}, q13[19:13]}: i13 - {{13{q13[19]}}, q13[19:13]};
q14 <= a13[6] ? q13 - {{13{i13[19]}}, i13[19:13]}: q13 + {{13{i13[19]}}, i13[19:13]};
i15 <= a14[5] ? i14 + {{14{q14[19]}}, q14[19:14]}: i14 - {{14{q14[19]}}, q14[19:14]};
q15 <= a14[5] ? q14 - {{14{i14[19]}}, i14[19:14]}: q14 + {{14{i14[19]}}, i14[19:14]};
iout[17:0] <= i15[19:2];
qout[17:0] <= q15[19:2];
end
endmodule | module cordic_16(i_in, q_in, iout, qout, ain, clk); |
input [19:0] ain;
input [15:0] i_in, q_in;
output [17:0] iout, qout;
reg [17:0] iout, qout;
input clk;
reg [18:0] a0;
reg [17:0] a1;
reg [17:0] a2;
reg [16:0] a3;
reg [15:0] a4;
reg [14:0] a5;
reg [13:0] a6;
reg [12:0] a7;
reg [11:0] a8;
reg [10:0] a9;
reg [9:0] a10;
reg [8:0] a11;
reg [7:0] a12;
reg [6:0] a13;
reg [5:0] a14;
reg [4:0] a15;
reg [3:0] a16;
reg [19:0] i0,i1, i2, i3, i4, i5, i6, i7, i8, i9;
reg [19:0] i10, i11, i12, i13, i14, i15, i16, i17;
reg [19:0] q0, q1, q2, q3, q4, q5, q6, q7, q8, q9;
reg [19:0] q10, q11, q12, q13, q14, q15, q16, q17;
always @ (posedge clk)
begin
a0 <= ain[18:0];
case (ain[19:18])
2'b00,2'b11: begin
i0 <= {i_in[15],i_in,3'd0};
q0 <= {q_in[15],q_in,3'd0};
end
2'b01,2'b10: begin
i0 <= -{i_in[15],i_in,3'd0};
q0 <= -{q_in[15],q_in,3'd0};
end
endcase
a1 <= a0[18] ? a0[17:0] + 18'd131072 : a0[17:0] - 18'd131072;
i1 <= a0[18] ? i0 + q0 : i0 - q0;
q1 <= a0[18] ? q0 - i0 : q0 + i0;
a2 <= a1[17] ? a1 + 18'd77376 : a1 - 18'd77376;
i2 <= a1[17] ? i1 + {q1[19], q1[19:1]}: i1 - {q1[19], q1[19:1]};
q2 <= a1[17] ? q1 - {i1[19], i1[19:1]}: q1 + {i1[19], i1[19:1]};
a3 <= a2[17] ? a2[16:0] + 17'd40884 : a2[16:0] - 17'd40884;
i3 <= a2[17] ? i2 + {{2{q2[19]}}, q2[19:2]}: i2 - {{2{q2[19]}}, q2[19:2]};
q3 <= a2[17] ? q2 - {{2{i2[19]}}, i2[19:2]}: q2 + {{2{i2[19]}}, i2[19:2]};
a4 <= a3[16] ? a3[15:0] + 16'd20753 : a3[15:0] - 16'd20753;
i4 <= a3[16] ? i3 + {{3{q3[19]}}, q3[19:3]}: i3 - {{3{q3[19]}}, q3[19:3]};
q4 <= a3[16] ? q3 - {{3{i3[19]}}, i3[19:3]}: q3 + {{3{i3[19]}}, i3[19:3]};
a5 <= a4[15] ? a4[14:0] + 15'd10417 : a4[14:0] - 15'd10417;
i5 <= a4[15] ? i4 + {{4{q4[19]}}, q4[19:4]}: i4 - {{4{q4[19]}}, q4[19:4]};
q5 <= a4[15] ? q4 - {{4{i4[19]}}, i4[19:4]}: q4 + {{4{i4[19]}}, i4[19:4]};
a6 <= a5[14] ? a5[13:0] + 14'd5213 : a5[13:0] - 14'd5213;
i6 <= a5[14] ? i5 + {{5{q5[19]}}, q5[19:5]}: i5 - {{5{q5[19]}}, q5[19:5]};
q6 <= a5[14] ? q5 - {{5{i5[19]}}, i5[19:5]}: q5 + {{5{i5[19]}}, i5[19:5]};
a7 <= a6[13] ? a6[12:0] + 13'd2607 : a6[12:0] - 13'd2607;
i7 <= a6[13] ? i6 + {{6{q6[19]}}, q6[19:6]}: i6 - {{6{q6[19]}}, q6[19:6]};
q7 <= a6[13] ? q6 - {{6{i6[19]}}, i6[19:6]}: q6 + {{6{i6[19]}}, i6[19:6]};
a8 <= a7[12] ? a7[11:0] + 12'd1304 : a7[11:0] - 12'd1304;
i8 <= a7[12] ? i7 + {{7{q7[19]}}, q7[19:7]}: i7 - {{7{q7[19]}}, q7[19:7]};
q8 <= a7[12] ? q7 - {{7{i7[19]}}, i7[19:7]}: q7 + {{7{i7[19]}}, i7[19:7]};
a9 <= a8[11] ? a8[10:0] + 11'd652 : a8[10:0] - 11'd652;
i9 <= a8[11] ? i8 + {{8{q8[19]}}, q8[19:8]}: i8 - {{8{q8[19]}}, q8[19:8]};
q9 <= a8[11] ? q8 - {{8{i8[19]}}, i8[19:8]}: q8 + {{8{i8[19]}}, i8[19:8]};
a10 <= a9[10] ? a9[9:0] + 10'd326 : a9[9:0] - 10'd326;
i10 <= a9[10] ? i9 + {{9{q9[19]}}, q9[19:9]}: i9 - {{9{q9[19]}}, q9[19:9]};
q10 <= a9[10] ? q9 - {{9{i9[19]}}, i9[19:9]}: q9 + {{9{i9[19]}}, i9[19:9]};
a11 <= a10[9] ? a10[8:0] + 9'd163 : a10[8:0] - 9'd163;
i11 <= a10[9] ? i10 + {{10{q10[19]}}, q10[19:10]}: i10 - {{10{q10[19]}}, q10[19:10]};
q11 <= a10[9] ? q10 - {{10{i10[19]}}, i10[19:10]}: q10 + {{10{i10[19]}}, i10[19:10]};
a12 <= a11[8] ? a11[7:0] + 8'd81 : a11[7:0] - 8'd81;
i12 <= a11[8] ? i11 + {{11{q11[19]}}, q11[19:11]}: i11 - {{11{q11[19]}}, q11[19:11]};
q12 <= a11[8] ? q11 - {{11{i11[19]}}, i11[19:11]}: q11 + {{11{i11[19]}}, i11[19:11]};
a13 <= a12[7] ? a12[6:0] + 7'd41 : a12[6:0] - 7'd41;
i13 <= a12[7] ? i12 + {{12{q12[19]}}, q12[19:12]}: i12 - {{12{q12[19]}}, q12[19:12]};
q13 <= a12[7] ? q12 - {{12{i12[19]}}, i12[19:12]}: q12 + {{12{i12[19]}}, i12[19:12]};
a14 <= a13[6] ? a13[5:0] + 6'd20 : a13[5:0] - 6'd20;
i14 <= a13[6] ? i13 + {{13{q13[19]}}, q13[19:13]}: i13 - {{13{q13[19]}}, q13[19:13]};
q14 <= a13[6] ? q13 - {{13{i13[19]}}, i13[19:13]}: q13 + {{13{i13[19]}}, i13[19:13]};
i15 <= a14[5] ? i14 + {{14{q14[19]}}, q14[19:14]}: i14 - {{14{q14[19]}}, q14[19:14]};
q15 <= a14[5] ? q14 - {{14{i14[19]}}, i14[19:14]}: q14 + {{14{i14[19]}}, i14[19:14]};
iout[17:0] <= i15[19:2];
qout[17:0] <= q15[19:2];
end
endmodule | 17 |
138,875 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.1/division.v | 86,169,941 | division.v | v | 67 | 92 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.1,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.1/division.v\n%Error: Exiting due to 4 error(s)\n' | 303,816 | module | module division(quotient,ready,dividend,divider,clk);
input [31:0] dividend;
input [31:0] divider;
input clk;
output [31:0] quotient;
output ready;
reg [95:0] qr;
reg [33:0] diff;
reg [31:0] quotient;
always @(negedge clk)
begin
if (ready)
quotient <= qr[31:0];
else
quotient <= quotient;
end
reg [7:0] bits;
wire ready = !bits;
always @(posedge clk)
if(ready) begin
bits = 64;
qr = {32'd0,dividend, 32'd0};
end else begin
diff = qr[95:63] - {1'b0,divider};
if(diff[32])
qr = {qr[94:0],1'd0};
else
qr = {diff[31:0],qr[62:0],1'd1};
bits = bits - 1'b1;
end
endmodule | module division(quotient,ready,dividend,divider,clk); |
input [31:0] dividend;
input [31:0] divider;
input clk;
output [31:0] quotient;
output ready;
reg [95:0] qr;
reg [33:0] diff;
reg [31:0] quotient;
always @(negedge clk)
begin
if (ready)
quotient <= qr[31:0];
else
quotient <= quotient;
end
reg [7:0] bits;
wire ready = !bits;
always @(posedge clk)
if(ready) begin
bits = 64;
qr = {32'd0,dividend, 32'd0};
end else begin
diff = qr[95:63] - {1'b0,divider};
if(diff[32])
qr = {qr[94:0],1'd0};
else
qr = {diff[31:0],qr[62:0],1'd1};
bits = bits - 1'b1;
end
endmodule | 17 |
138,879 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.1/sim.v | 86,169,941 | sim.v | v | 313 | 121 | [] | [] | [] | null | line:172: before: "(" | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.1,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.1/sim.v\n%Error: Exiting due to 4 error(s)\n' | 303,820 | module | module sim ();
reg _10MHZ;
wire ext_10MHZ;
reg _122MHZ;
reg RUN;
reg LROUT;
wire C4;
reg CBCLK;
wire C8;
reg CLRCLK;
wire C9;
reg C12;
reg C17;
reg PTT;
wire PTT_in;
reg CDOUT;
reg CC;
reg DCMISO;
wire LVDSTXE;
wire nLVDSRXE;
wire [13:0] DAC, DAC_orig;
assign C4 = LROUT;
assign C8 = CBCLK;
assign C9 = CLRCLK;
reg [58:0] CC_STREAM;
initial
begin
RUN = 1'b0;
P1.CMCLK_counter = 3'b0;
P1.PCLK_12MHZ = 1'b0;
P1.reset_count = 11'b0;
P1.IQ_state = 3'b0;
P1.CC_state = 2'b0;
P1.PTT_out = 1'b0;
P1.frequency_HZ = 0;
P1.clock_select = 4'b0;
P1.OC = 7'b0;
P1.div_dly = 4'b0;
P1.freq_changed = 1'b0;
P1.ALC_out = 0;
P1.I_data = 0;
P1.Q_data = 0;
P1.I_sync_data = 0;
P1.Q_sync_data = 0;
P1.cic_i = 0;
P1.cic_q = 0;
P2.CMCLK_counter = 3'b0;
P2.PCLK_12MHZ = 1'b0;
P2.reset_count = 11'b0;
P2.IQ_state = 3'b0;
P2.ALC = 1'b0;
P2.CC_state = 2'b0;
P2.PTT_out = 1'b0;
P2.frequency_HZ = 0;
P2.clock_select = 4'b0;
P2.OC = 7'b0;
P2.ALC_out = 0;
P2.ALC_in = 0;
P2.previous = 0;
P2.I_data = 0;
P2.Q_data = 0;
P2.I_sync_data = 0;
P2.Q_sync_data = 0;
P2.cic_i = 0;
P2.cic_q = 0;
PTT = 1'b0;
CC_STREAM = 0;
#500;
RUN = 1'b1;
#50;
if (_10MHZ === 1'bx)
begin
$display ("ERROR: _10MHZ clock not running");
$stop;
end
if (_122MHZ === 1'bx)
begin
$display ("ERROR: _122MHZ clock not running");
$stop;
end
if (ext_10MHZ === 1'bx)
begin
$display ("ERROR: ext_10MHZ clock not running");
$stop;
end
if (CBCLK === 1'bx)
begin
$display ("ERROR: CBCLK clock not running");
$stop;
end
if (CLRCLK === 1'bx)
begin
$display ("ERROR: CLRCLK clock not running");
$stop;
end
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
CC_STREAM = {1'b1, 4'b0, 32'd22000000, 4'b1010, 7'b1011010, 1'b1, 10'b0};
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
$display ("Succesful simulation completion");
$stop;
end
Penelope P1 (._10MHZ(_10MHZ), .ext_10MHZ(ext_10MHZ), ._122MHZ(_122MHZ), .A5(A5),.A11(A11),
.C4(C4), .C8(C8), .C9(C9), .C12(C12), .C17(C17), .LED2(LED2), .LED3(LED3),
.LED4(LED4), .LED5(LED5), .LED6(LED6), .LED7(LED7), .USEROUT0(USEROUT0),
.USEROUT1(USEROUT1), .USEROUT2(USEROUT2), .USEROUT3(USEROUT3), .USEROUT4(USEROUT4),
.USEROUT5(USEROUT5), .USEROUT6(USEROUT6), .DAC(DAC), .nLVDSRXE(nLVDSRXE),
.LVDSTXE(LVDSTXE), .FPGA_PLL(FPGA_PLL), .PTT(PTT), .PTT_in(PTT_in), .nCS(nCS), .CMODE(CMODE),
.CDOUT(CDOUT), .CBCLK(), .CLRCIN(CLRCIN), .CLRCOUT(CLRCOUT), .LROUT(),
.CMCLK(CMCLK), .CC(CC), .ADCMOSI(ADCMOSI), .ADCCLK(ADCCLK), .ADCMISO(ADCMISO),
.nADCCS(nADCCS), .PWM0(PWM0), .PWM1(PWM1), .PWM2(PWM2), .FPGA_PTT(FPGA_PTT)
);
Penelope_orig P2(._10MHZ(_10MHZ), .ext_10MHZ(ext_10MHZ_orig), ._122MHZ(_122MHZ), .A5(A5_orig),.A11(A11_orig),
.C4(C4), .C8(C8), .C9(C9), .C12(C12), .C17(C17), .LED2(LED2_orig), .LED3(LED3_orig),
.LED4(LED4_orig), .LED5(LED5_orig), .LED6(LED6_orig), .LED7(LED7_orig), .USEROUT0(USEROUT0_orig),
.USEROUT1(USEROUT1_orig), .USEROUT2(USEROUT2_orig), .USEROUT3(USEROUT3_orig), .USEROUT4(USEROUT4_orig),
.USEROUT5(USEROUT5_orig), .USEROUT6(USEROUT6_orig), .DAC(DAC_orig), .nLVDSRXE(nLVDSRXE_orig),
.LVDSTXE(LVDSTXE_orig), .FPGA_PLL(FPGA_PLL_orig), .PTT(PTT), .PTT_in(PTT_in_orig), .nCS(nCS_orig), .CMODE(CMODE_orig),
.CDOUT(CDOUT), .CBCLK(), .CLRCIN(CLRCIN_orig), .CLRCOUT(CLRCOUT_orig), .LROUT(),
.CMCLK(CMCLK_orig), .CC(CC), .ADCMOSI(ADCMOSI_orig), .ADCCLK(ADCCLK_orig), .ADCMISO(ADCMISO),
.nADCCS(nADCCS_orig), .PWM0(PWM0_orig), .PWM1(PWM1_orig), .PWM2(PWM2_orig), .FPGA_PTT(FPGA_PTT_orig)
);
reg [15:0] iqd;
initial
begin
#2000;
iqd = 0;
while(1)
begin
C12 = 1'bz;
@(negedge CLRCLK);
iqd = -10000;
IQ_DATA(iqd);
C12 = 1'bz;
@(posedge CLRCLK);
iqd = 10000;
IQ_DATA(iqd);
iqd = iqd + 16'h8001;
end
end
task IQ_DATA;
input [15:0] din;
integer iq_cnt;
begin
@(negedge CBCLK);
for (iq_cnt = 0; iq_cnt < 16; iq_cnt = iq_cnt + 1)
begin
C12 = din[15-iq_cnt];
@(negedge CBCLK);
end
end
endtask
reg [58:0] ccd;
initial
begin
#2000;
while(1)
begin
ccd <= CC_STREAM;
@(negedge CLRCLK);
CC_DATA(ccd);
end
end
task CC_DATA;
input [58:0] din;
integer acnt;
begin
@(negedge CBCLK);
for (acnt = 0; acnt < 59; acnt = acnt + 1)
begin
CC = din[58-acnt];
@(negedge CBCLK);
end
end
endtask
parameter CB_SPEED = 162.8;
initial
begin
CBCLK = 1'b0;
$display ("CBCLK started ");
#66;
wait(RUN);
forever
begin
#CB_SPEED CBCLK = 1'b1;
#CB_SPEED CBCLK = 1'b0;
end
end
integer k;
initial
begin
CLRCLK = 1'b0;
$display ("CLRCLK started ");
#3;
wait(RUN);
@ (posedge CBCLK);
forever
begin
@ (negedge CBCLK);
#15
CLRCLK = 1'b0;
for (k = 0; k < 32; k = k + 1)
@ (posedge CBCLK);
@ (negedge CBCLK);
#15
CLRCLK = 1'b1;
for (k = 0; k < 32; k = k + 1)
@ (posedge CBCLK);
end
end
parameter CLK10_SPEED = 50.0;
initial
begin
_10MHZ = 1'b0;
$display ("_10Mhz started ");
#5;
wait(RUN);
forever
begin
#CLK10_SPEED _10MHZ = 1'b1;
#CLK10_SPEED _10MHZ = 1'b0;
end
end
parameter CLK123_SPEED = 4.07;
initial
begin
$display ("_122MHZ started");
_122MHZ = 1'b0;
#15
forever
begin
#CLK123_SPEED _122MHZ = 1'b1;
#CLK123_SPEED _122MHZ = 1'b0;
end
end
parameter C17_SPEED = 40.7;
initial
begin
C17 = 1'b0;
$display ("C17 (i.e. CLK_MCLK) started");
#47;
wait(RUN);
forever
begin
#C17_SPEED C17 = 1'b1;
#C17_SPEED C17 = 1'b0;
end
end
endmodule | module sim (); |
reg _10MHZ;
wire ext_10MHZ;
reg _122MHZ;
reg RUN;
reg LROUT;
wire C4;
reg CBCLK;
wire C8;
reg CLRCLK;
wire C9;
reg C12;
reg C17;
reg PTT;
wire PTT_in;
reg CDOUT;
reg CC;
reg DCMISO;
wire LVDSTXE;
wire nLVDSRXE;
wire [13:0] DAC, DAC_orig;
assign C4 = LROUT;
assign C8 = CBCLK;
assign C9 = CLRCLK;
reg [58:0] CC_STREAM;
initial
begin
RUN = 1'b0;
P1.CMCLK_counter = 3'b0;
P1.PCLK_12MHZ = 1'b0;
P1.reset_count = 11'b0;
P1.IQ_state = 3'b0;
P1.CC_state = 2'b0;
P1.PTT_out = 1'b0;
P1.frequency_HZ = 0;
P1.clock_select = 4'b0;
P1.OC = 7'b0;
P1.div_dly = 4'b0;
P1.freq_changed = 1'b0;
P1.ALC_out = 0;
P1.I_data = 0;
P1.Q_data = 0;
P1.I_sync_data = 0;
P1.Q_sync_data = 0;
P1.cic_i = 0;
P1.cic_q = 0;
P2.CMCLK_counter = 3'b0;
P2.PCLK_12MHZ = 1'b0;
P2.reset_count = 11'b0;
P2.IQ_state = 3'b0;
P2.ALC = 1'b0;
P2.CC_state = 2'b0;
P2.PTT_out = 1'b0;
P2.frequency_HZ = 0;
P2.clock_select = 4'b0;
P2.OC = 7'b0;
P2.ALC_out = 0;
P2.ALC_in = 0;
P2.previous = 0;
P2.I_data = 0;
P2.Q_data = 0;
P2.I_sync_data = 0;
P2.Q_sync_data = 0;
P2.cic_i = 0;
P2.cic_q = 0;
PTT = 1'b0;
CC_STREAM = 0;
#500;
RUN = 1'b1;
#50;
if (_10MHZ === 1'bx)
begin
$display ("ERROR: _10MHZ clock not running");
$stop;
end
if (_122MHZ === 1'bx)
begin
$display ("ERROR: _122MHZ clock not running");
$stop;
end
if (ext_10MHZ === 1'bx)
begin
$display ("ERROR: ext_10MHZ clock not running");
$stop;
end
if (CBCLK === 1'bx)
begin
$display ("ERROR: CBCLK clock not running");
$stop;
end
if (CLRCLK === 1'bx)
begin
$display ("ERROR: CLRCLK clock not running");
$stop;
end
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
CC_STREAM = {1'b1, 4'b0, 32'd22000000, 4'b1010, 7'b1011010, 1'b1, 10'b0};
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
@(posedge CLRCLK);
$display ("Succesful simulation completion");
$stop;
end
Penelope P1 (._10MHZ(_10MHZ), .ext_10MHZ(ext_10MHZ), ._122MHZ(_122MHZ), .A5(A5),.A11(A11),
.C4(C4), .C8(C8), .C9(C9), .C12(C12), .C17(C17), .LED2(LED2), .LED3(LED3),
.LED4(LED4), .LED5(LED5), .LED6(LED6), .LED7(LED7), .USEROUT0(USEROUT0),
.USEROUT1(USEROUT1), .USEROUT2(USEROUT2), .USEROUT3(USEROUT3), .USEROUT4(USEROUT4),
.USEROUT5(USEROUT5), .USEROUT6(USEROUT6), .DAC(DAC), .nLVDSRXE(nLVDSRXE),
.LVDSTXE(LVDSTXE), .FPGA_PLL(FPGA_PLL), .PTT(PTT), .PTT_in(PTT_in), .nCS(nCS), .CMODE(CMODE),
.CDOUT(CDOUT), .CBCLK(), .CLRCIN(CLRCIN), .CLRCOUT(CLRCOUT), .LROUT(),
.CMCLK(CMCLK), .CC(CC), .ADCMOSI(ADCMOSI), .ADCCLK(ADCCLK), .ADCMISO(ADCMISO),
.nADCCS(nADCCS), .PWM0(PWM0), .PWM1(PWM1), .PWM2(PWM2), .FPGA_PTT(FPGA_PTT)
);
Penelope_orig P2(._10MHZ(_10MHZ), .ext_10MHZ(ext_10MHZ_orig), ._122MHZ(_122MHZ), .A5(A5_orig),.A11(A11_orig),
.C4(C4), .C8(C8), .C9(C9), .C12(C12), .C17(C17), .LED2(LED2_orig), .LED3(LED3_orig),
.LED4(LED4_orig), .LED5(LED5_orig), .LED6(LED6_orig), .LED7(LED7_orig), .USEROUT0(USEROUT0_orig),
.USEROUT1(USEROUT1_orig), .USEROUT2(USEROUT2_orig), .USEROUT3(USEROUT3_orig), .USEROUT4(USEROUT4_orig),
.USEROUT5(USEROUT5_orig), .USEROUT6(USEROUT6_orig), .DAC(DAC_orig), .nLVDSRXE(nLVDSRXE_orig),
.LVDSTXE(LVDSTXE_orig), .FPGA_PLL(FPGA_PLL_orig), .PTT(PTT), .PTT_in(PTT_in_orig), .nCS(nCS_orig), .CMODE(CMODE_orig),
.CDOUT(CDOUT), .CBCLK(), .CLRCIN(CLRCIN_orig), .CLRCOUT(CLRCOUT_orig), .LROUT(),
.CMCLK(CMCLK_orig), .CC(CC), .ADCMOSI(ADCMOSI_orig), .ADCCLK(ADCCLK_orig), .ADCMISO(ADCMISO),
.nADCCS(nADCCS_orig), .PWM0(PWM0_orig), .PWM1(PWM1_orig), .PWM2(PWM2_orig), .FPGA_PTT(FPGA_PTT_orig)
);
reg [15:0] iqd;
initial
begin
#2000;
iqd = 0;
while(1)
begin
C12 = 1'bz;
@(negedge CLRCLK);
iqd = -10000;
IQ_DATA(iqd);
C12 = 1'bz;
@(posedge CLRCLK);
iqd = 10000;
IQ_DATA(iqd);
iqd = iqd + 16'h8001;
end
end
task IQ_DATA;
input [15:0] din;
integer iq_cnt;
begin
@(negedge CBCLK);
for (iq_cnt = 0; iq_cnt < 16; iq_cnt = iq_cnt + 1)
begin
C12 = din[15-iq_cnt];
@(negedge CBCLK);
end
end
endtask
reg [58:0] ccd;
initial
begin
#2000;
while(1)
begin
ccd <= CC_STREAM;
@(negedge CLRCLK);
CC_DATA(ccd);
end
end
task CC_DATA;
input [58:0] din;
integer acnt;
begin
@(negedge CBCLK);
for (acnt = 0; acnt < 59; acnt = acnt + 1)
begin
CC = din[58-acnt];
@(negedge CBCLK);
end
end
endtask
parameter CB_SPEED = 162.8;
initial
begin
CBCLK = 1'b0;
$display ("CBCLK started ");
#66;
wait(RUN);
forever
begin
#CB_SPEED CBCLK = 1'b1;
#CB_SPEED CBCLK = 1'b0;
end
end
integer k;
initial
begin
CLRCLK = 1'b0;
$display ("CLRCLK started ");
#3;
wait(RUN);
@ (posedge CBCLK);
forever
begin
@ (negedge CBCLK);
#15
CLRCLK = 1'b0;
for (k = 0; k < 32; k = k + 1)
@ (posedge CBCLK);
@ (negedge CBCLK);
#15
CLRCLK = 1'b1;
for (k = 0; k < 32; k = k + 1)
@ (posedge CBCLK);
end
end
parameter CLK10_SPEED = 50.0;
initial
begin
_10MHZ = 1'b0;
$display ("_10Mhz started ");
#5;
wait(RUN);
forever
begin
#CLK10_SPEED _10MHZ = 1'b1;
#CLK10_SPEED _10MHZ = 1'b0;
end
end
parameter CLK123_SPEED = 4.07;
initial
begin
$display ("_122MHZ started");
_122MHZ = 1'b0;
#15
forever
begin
#CLK123_SPEED _122MHZ = 1'b1;
#CLK123_SPEED _122MHZ = 1'b0;
end
end
parameter C17_SPEED = 40.7;
initial
begin
C17 = 1'b0;
$display ("C17 (i.e. CLK_MCLK) started");
#47;
wait(RUN);
forever
begin
#C17_SPEED C17 = 1'b1;
#C17_SPEED C17 = 1'b0;
end
end
endmodule | 17 |
138,880 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.2/Penelope.v | 86,169,941 | Penelope.v | v | 733 | 119 | [] | ['general public license', 'free software foundation'] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.2/Penelope.v\n%Error: Exiting due to 4 error(s)\n' | 303,829 | module | module Penelope (
_10MHZ,ext_10MHZ,C122_clk,A11,C19,C22,LED2,LED3,LED4,LED5,LED6,LED7,
USEROUT0,USEROUT1,USEROUT2,USEROUT3,USEROUT4,USEROUT5,USEROUT6,DAC,nLVDSRXE,LVDSTXE,
FPGA_PLL,PTT,PTT_in,nCS,CMODE,TLV320_CDIN,TLV320_CDOUT,TLV320_CBCLK,TLV320_CLRCIN,TLV320_CLRCOUT,TLV320_CMCLK,
CC, ADCMOSI,ADCCLK,ADCMISO,nADCCS,PWM0,PWM1,PWM2,FPGA_PTT,A5
);
input wire _10MHZ;
inout tri ext_10MHZ;
input wire C122_clk;
output wire A11;
input wire C19;
output wire C22;
output wire LED2;
output wire LED3;
output wire LED4;
output wire LED5;
output wire LED6;
output wire LED7;
output wire USEROUT0;
output wire USEROUT1;
output wire USEROUT2;
output wire USEROUT3;
output wire USEROUT4;
output wire USEROUT5;
output wire USEROUT6;
output wire [13:0] DAC;
output wire nLVDSRXE;
output wire LVDSTXE;
output wire FPGA_PLL;
input wire PTT;
output tri PTT_in;
output wire nCS;
output wire CMODE;
output wire TLV320_CDIN;
input wire TLV320_CDOUT;
output wire TLV320_CBCLK;
output wire TLV320_CLRCIN;
output wire TLV320_CLRCOUT;
output wire TLV320_CMCLK;
input wire CC;
output wire ADCMOSI;
output wire ADCCLK;
input wire ADCMISO;
output wire nADCCS;
output wire PWM0;
output wire PWM1;
output wire PWM2;
output wire FPGA_PTT;
output wire A5;
wire source_122MHZ;
assign CMODE = 1'b0;
assign nCS = 1'b1;
localparam SERIAL = 8'd12;
localparam C122_TPD = 1.3;
reg C122_rst;
reg [10:0] C122_rst_cnt;
always @(posedge C122_clk)
begin
if (!C122_rst_cnt[10])
C122_rst_cnt <= #C122_TPD C122_rst_cnt + 1'b1;
C122_rst <= #C122_TPD C122_rst_cnt[10] ? 1'b0 : 1'b1;
end
localparam SPEED_48K = 2'b00;
reg C122_DFS1, C122_DFS0;
reg C122_cgen_rst;
reg [1:0] C122_SPEED;
clk_div TLVCLK (.reset(C122_rst), .clk_in(C122_clk), .clk_out(TLV320_CMCLK));
always @(posedge C122_clk)
begin
if (C122_rst)
C122_SPEED <= 2'b00;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_SPEED <= {C122_DFS1,C122_DFS0};
if (C122_rst)
C122_cgen_rst <= 1'b1;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_cgen_rst <= 1'b1;
else
C122_cgen_rst <= 1'b0;
end
wire C122_cbrise, C122_cbfall;
wire C122_CBCLK, CLRCLK;
clk_lrclk_gen clrgen
(.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(C122_CBCLK),
.Brise(C122_cbrise), .Bfall(C122_cbfall), .LRCLK(CLRCLK), .Speed(SPEED_48K));
assign TLV320_CBCLK = C122_CBCLK;
assign TLV320_CLRCIN = CLRCLK;
assign TLV320_CLRCOUT = CLRCLK;
wire LRfall;
clk_lrclk_gen lrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(), .LRCLK(),
.LRfall(LRfall), .Speed({C122_DFS1,C122_DFS0}));
assign nLVDSRXE = source_122MHZ ? 1'b1 : 1'b0;
assign LVDSTXE = source_122MHZ ? 1'b1 : 1'b0;
wire reference;
wire ref_ext;
assign reference = ref_ext ? _10MHZ : ext_10MHZ;
assign ext_10MHZ = ref_ext ? _10MHZ : 1'bz;
wire [11:0] AIN5;
ADC ADC_SPI(.clock(C122_CBCLK), .SCLK(ADCCLK), .nCS(nADCCS), .MISO(ADCMISO), .MOSI(ADCMOSI), .AIN5(AIN5));
reg [31:0] C122_frequency_HZ;
reg [31:0] C122_last_freq;
reg [31:0] C122_phase_word;
wire [63:0] C122_ratio;
localparam M2 = 32'd1172812403;
assign C122_ratio = C122_frequency_HZ * M2;
always @ (posedge C122_clk)
begin
if (C122_cbfall)
begin
C122_last_freq <= C122_frequency_HZ;
if (C122_last_freq != C122_frequency_HZ)
C122_phase_word <= C122_ratio[56:25];
end
end
localparam DEC_SEC = 2000;
localparam ATT_SEC = 10;
localparam CLK_RATE = 12288000/4/1000;
localparam DECAY_RANGE = (DEC_SEC*CLK_RATE)>>16;
localparam ATTACK_RANGE = (ATT_SEC*CLK_RATE)>>16;
localparam DR = clogb2(DECAY_RANGE);
localparam AR = clogb2(ATTACK_RANGE);
wire [15:0] ALC_in;
reg [15:0] ALC_out;
reg [DR:0] decay_cnt;
reg [AR:0] attack_cnt;
assign ALC_in = {AIN5, 4'b0};
always @ (posedge C122_clk)
begin
if (C122_cbfall)
begin
if ((ALC_in < ALC_out) || (attack_cnt == ATTACK_RANGE))
attack_cnt <= 0;
else
attack_cnt <= attack_cnt + 1'b1;
if ((ALC_in >= ALC_out) || (decay_cnt == DECAY_RANGE))
decay_cnt <= 0;
else
decay_cnt <= decay_cnt + 1'b1;
if ((ALC_in < ALC_out) && (decay_cnt == DECAY_RANGE))
ALC_out <= ALC_out - 1'b1;
else if ((ALC_in > ALC_out) && (attack_cnt == ATTACK_RANGE))
ALC_out <= ALC_out + 1'b1;
end
end
wire [15:0] PWM0_Data;
wire [15:0] PWM1_Data;
wire [15:0] PWM2_Data;
reg [15:0] C122_ALC_i;
reg [15:0] C122_ALC_q;
reg [11:0] C122_ain5;
always @(posedge C122_clk)
begin: CB_AIN5_TO_C122
reg [11:0] ain1, ain0;
{ain1, ain0} <= {ain0, AIN5};
if (C122_cbfall)
C122_ain5 <= ain1;
end
assign PWM0_Data = C122_ALC_i;
assign PWM1_Data = {1'b0,C122_ain5,3'd0};
assign PWM2_Data = {1'b0,ALC_out[15:1]};
wire [15:0] set_level;
wire [15:0] gain;
wire [15:0] ALC_level;
wire [15:0] C122_res_i, C122_res_q;
reg [15:0] C122_qx0;
reg [15:0] C122_ix0;
wire [15:0] I_sync_data;
wire [15:0] Q_sync_data;
assign set_level = 16'hCCCC;
assign ALC_level = {5'd0,ALC_out[15:5]};
assign gain = (set_level - ALC_level);
ALC ALC_I(.out(C122_res_i), .sample(I_sync_data), .multiply(gain));
ALC ALC_Q(.out(C122_res_q), .sample(Q_sync_data), .multiply(gain));
wire C122_ce_out_i;
wire C122_ce_out_q;
reg signed [15:0] C122_cic_i;
reg signed [15:0] C122_cic_q;
always @ (posedge C122_clk)
begin
if (C122_cbfall)
begin
C122_ALC_i <= C122_res_i;
C122_ALC_q <= C122_res_q;
end
if (C122_ce_out_i)
C122_cic_i <= C122_ALC_i;
if (C122_ce_out_q)
C122_cic_q <= C122_ALC_q;
end
wire [15:0] C122_cic_out_i;
wire [15:0] C122_cic_out_q;
cicint cic_I(.clk(C122_clk), .clk_enable(1'b1), .reset(C122_rst), .filter_in(C122_cic_i),
.filter_out(C122_cic_out_i), .ce_out(C122_ce_out_i));
cicint cic_Q(.clk(C122_clk), .clk_enable(1'b1), .reset(C122_rst), .filter_in(C122_cic_q),
.filter_out(C122_cic_out_q), .ce_out(C122_ce_out_q));
wire [17:0] C122_i_out;
wire [17:0] C122_q_out;
wire [31:0] C122_phase;
phase_accumulator rx_phase_accumulator
(.clk(C122_clk), .reset(C122_rst), .frequency(C122_phase_word), .phase_out(C122_phase));
cordic_16 tx_cordic
(.i_in(C122_cic_out_q), .q_in(C122_cic_out_i),
.iout(C122_i_out), .qout(C122_q_out), .ain(C122_phase[31:12]), .clk(C122_clk));
assign DAC[13:0] = {C122_i_out[17], C122_i_out[15:3]};
reg [15:0] PWM0_Data_in;
reg [15:0] PWM1_Data_in;
reg [15:0] PWM2_Data_in;
reg [16:0] PWM0_accumulator;
reg [16:0] PWM1_accumulator;
reg [16:0] PWM2_accumulator;
always @(posedge C122_clk)
begin
PWM0_Data_in <= PWM0_Data + 16'h8000;
PWM1_Data_in <= PWM1_Data + 16'h8000;
PWM2_Data_in <= PWM2_Data + 16'h8000;
PWM0_accumulator <= PWM0_accumulator[15:0] + PWM0_Data_in;
PWM1_accumulator <= PWM1_accumulator[15:0] + PWM1_Data_in;
PWM2_accumulator <= PWM2_accumulator[15:0] + PWM2_Data_in;
end
assign PWM0 = PWM0_accumulator[16];
assign PWM1 = PWM1_accumulator[16];
assign PWM2 = PWM2_accumulator[16];
wire [60:0] rcv_data;
wire rcv_rdy;
reg PTT_out;
reg [3:0] C122_clock_select;
reg [6:0] OC;
parameter PENNY_ADDR = 4'b0;
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
C122_DFS1 <= 1'b0;
C122_DFS0 <= 1'b0;
PTT_out <= 1'b0;
C122_frequency_HZ <= 32'b0;
C122_clock_select <= 4'b0000;
OC <= 7'b0;
end
else if (rcv_rdy)
begin
C122_DFS1 <= rcv_data[60];
C122_DFS0 <= rcv_data[59];
PTT_out <= rcv_data[58];
if (rcv_data[57:54] == PENNY_ADDR)
begin
C122_frequency_HZ <= rcv_data[53:22];
C122_clock_select <= rcv_data[21:18];
OC <= rcv_data[17:11];
end
end
end
NWire_rcv #(.DATA_BITS(61), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(500))
CCrcv (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_data(rcv_data), .xrcv_rdy(rcv_rdy), .xrcv_ack(rcv_rdy), .din(CC));
assign ref_ext = C122_clock_select[0];
assign source_122MHZ = (C122_clock_select[3:2] == 2'b00);
wire IQ_rdy;
NWire_rcv #(.DATA_BITS(32), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
IQPWM (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_rdy(IQ_rdy), .xrcv_ack(IQ_rdy), .xrcv_data({I_sync_data, Q_sync_data}),
.din(C19));
assign C22 = CLRCLK;
I2S_xmit #(.DATA_BITS(32))
IQD (.rst(C122_rst), .lrclk(CLRCLK), .clk(C122_clk), .CBrise(C122_cbrise),
.CBfall(C122_cbfall), .sample({I_sync_data,Q_sync_data}), .outbit(TLV320_CDIN));
reg [15:0] C122_mic_data;
wire C122_mic_rdy;
wire [31:0] C122_mic_LR;
NWire_xmit #(.SEND_FREQ(48000),.DATA_BITS(16), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .LOW_TIME(1'b0))
P_MIC (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(C122_mic_data), .xreq(LRfall), .xrdy(), .xack(), .dout(A11));
always @(posedge C122_clk)
begin
if (C122_mic_rdy)
C122_mic_data <= C122_mic_LR[31:16];
end
I2S_rcv #(32,2,1)
PJD (.xrst(C122_rst), .xclk(C122_clk), .xData(C122_mic_LR),
.xData_rdy(C122_mic_rdy), .BCLK(C122_CBCLK), .LRCLK(CLRCLK), .din(TLV320_CDOUT));
wire [19:0] xmit_data;
assign xmit_data = {SERIAL,ALC_in[15:4]};
NWire_xmit #(.DATA_BITS(20), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SEND_FREQ(1000))
ser_no (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(xmit_data), .xreq(1'b1), .xrdy(), .xack(), .dout(A5));
assign PTT_in = PTT ? 1'bz: 1'b1;
assign FPGA_PTT = PTT_out;
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge C122_clk)
begin
if (count_12288 == 767)
begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else
count_12288 <= count_12288 + 10'b1;
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
assign LED2 = (AIN5 > 250)? 1'b0 : 1'b1;
assign LED3 = (AIN5 > 500)? 1'b0 : 1'b1;
assign LED4 = (AIN5 > 1000)? 1'b0 : 1'b1;
assign LED5 = (AIN5 > 2000)? 1'b0 : 1'b1;
assign LED6 = (AIN5 > 3000)? 1'b0 : 1'b1;
assign LED7 = 0;
assign USEROUT0 = OC[0];
assign USEROUT1 = OC[1];
assign USEROUT2 = OC[2];
assign USEROUT3 = OC[3];
assign USEROUT4 = OC[4];
assign USEROUT5 = OC[5];
assign USEROUT6 = OC[6];
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | module Penelope (
_10MHZ,ext_10MHZ,C122_clk,A11,C19,C22,LED2,LED3,LED4,LED5,LED6,LED7,
USEROUT0,USEROUT1,USEROUT2,USEROUT3,USEROUT4,USEROUT5,USEROUT6,DAC,nLVDSRXE,LVDSTXE,
FPGA_PLL,PTT,PTT_in,nCS,CMODE,TLV320_CDIN,TLV320_CDOUT,TLV320_CBCLK,TLV320_CLRCIN,TLV320_CLRCOUT,TLV320_CMCLK,
CC, ADCMOSI,ADCCLK,ADCMISO,nADCCS,PWM0,PWM1,PWM2,FPGA_PTT,A5
); |
input wire _10MHZ;
inout tri ext_10MHZ;
input wire C122_clk;
output wire A11;
input wire C19;
output wire C22;
output wire LED2;
output wire LED3;
output wire LED4;
output wire LED5;
output wire LED6;
output wire LED7;
output wire USEROUT0;
output wire USEROUT1;
output wire USEROUT2;
output wire USEROUT3;
output wire USEROUT4;
output wire USEROUT5;
output wire USEROUT6;
output wire [13:0] DAC;
output wire nLVDSRXE;
output wire LVDSTXE;
output wire FPGA_PLL;
input wire PTT;
output tri PTT_in;
output wire nCS;
output wire CMODE;
output wire TLV320_CDIN;
input wire TLV320_CDOUT;
output wire TLV320_CBCLK;
output wire TLV320_CLRCIN;
output wire TLV320_CLRCOUT;
output wire TLV320_CMCLK;
input wire CC;
output wire ADCMOSI;
output wire ADCCLK;
input wire ADCMISO;
output wire nADCCS;
output wire PWM0;
output wire PWM1;
output wire PWM2;
output wire FPGA_PTT;
output wire A5;
wire source_122MHZ;
assign CMODE = 1'b0;
assign nCS = 1'b1;
localparam SERIAL = 8'd12;
localparam C122_TPD = 1.3;
reg C122_rst;
reg [10:0] C122_rst_cnt;
always @(posedge C122_clk)
begin
if (!C122_rst_cnt[10])
C122_rst_cnt <= #C122_TPD C122_rst_cnt + 1'b1;
C122_rst <= #C122_TPD C122_rst_cnt[10] ? 1'b0 : 1'b1;
end
localparam SPEED_48K = 2'b00;
reg C122_DFS1, C122_DFS0;
reg C122_cgen_rst;
reg [1:0] C122_SPEED;
clk_div TLVCLK (.reset(C122_rst), .clk_in(C122_clk), .clk_out(TLV320_CMCLK));
always @(posedge C122_clk)
begin
if (C122_rst)
C122_SPEED <= 2'b00;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_SPEED <= {C122_DFS1,C122_DFS0};
if (C122_rst)
C122_cgen_rst <= 1'b1;
else if (C122_SPEED != {C122_DFS1,C122_DFS0})
C122_cgen_rst <= 1'b1;
else
C122_cgen_rst <= 1'b0;
end
wire C122_cbrise, C122_cbfall;
wire C122_CBCLK, CLRCLK;
clk_lrclk_gen clrgen
(.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(C122_CBCLK),
.Brise(C122_cbrise), .Bfall(C122_cbfall), .LRCLK(CLRCLK), .Speed(SPEED_48K));
assign TLV320_CBCLK = C122_CBCLK;
assign TLV320_CLRCIN = CLRCLK;
assign TLV320_CLRCOUT = CLRCLK;
wire LRfall;
clk_lrclk_gen lrgen (.reset(C122_cgen_rst), .CLK_IN(C122_clk), .BCLK(), .LRCLK(),
.LRfall(LRfall), .Speed({C122_DFS1,C122_DFS0}));
assign nLVDSRXE = source_122MHZ ? 1'b1 : 1'b0;
assign LVDSTXE = source_122MHZ ? 1'b1 : 1'b0;
wire reference;
wire ref_ext;
assign reference = ref_ext ? _10MHZ : ext_10MHZ;
assign ext_10MHZ = ref_ext ? _10MHZ : 1'bz;
wire [11:0] AIN5;
ADC ADC_SPI(.clock(C122_CBCLK), .SCLK(ADCCLK), .nCS(nADCCS), .MISO(ADCMISO), .MOSI(ADCMOSI), .AIN5(AIN5));
reg [31:0] C122_frequency_HZ;
reg [31:0] C122_last_freq;
reg [31:0] C122_phase_word;
wire [63:0] C122_ratio;
localparam M2 = 32'd1172812403;
assign C122_ratio = C122_frequency_HZ * M2;
always @ (posedge C122_clk)
begin
if (C122_cbfall)
begin
C122_last_freq <= C122_frequency_HZ;
if (C122_last_freq != C122_frequency_HZ)
C122_phase_word <= C122_ratio[56:25];
end
end
localparam DEC_SEC = 2000;
localparam ATT_SEC = 10;
localparam CLK_RATE = 12288000/4/1000;
localparam DECAY_RANGE = (DEC_SEC*CLK_RATE)>>16;
localparam ATTACK_RANGE = (ATT_SEC*CLK_RATE)>>16;
localparam DR = clogb2(DECAY_RANGE);
localparam AR = clogb2(ATTACK_RANGE);
wire [15:0] ALC_in;
reg [15:0] ALC_out;
reg [DR:0] decay_cnt;
reg [AR:0] attack_cnt;
assign ALC_in = {AIN5, 4'b0};
always @ (posedge C122_clk)
begin
if (C122_cbfall)
begin
if ((ALC_in < ALC_out) || (attack_cnt == ATTACK_RANGE))
attack_cnt <= 0;
else
attack_cnt <= attack_cnt + 1'b1;
if ((ALC_in >= ALC_out) || (decay_cnt == DECAY_RANGE))
decay_cnt <= 0;
else
decay_cnt <= decay_cnt + 1'b1;
if ((ALC_in < ALC_out) && (decay_cnt == DECAY_RANGE))
ALC_out <= ALC_out - 1'b1;
else if ((ALC_in > ALC_out) && (attack_cnt == ATTACK_RANGE))
ALC_out <= ALC_out + 1'b1;
end
end
wire [15:0] PWM0_Data;
wire [15:0] PWM1_Data;
wire [15:0] PWM2_Data;
reg [15:0] C122_ALC_i;
reg [15:0] C122_ALC_q;
reg [11:0] C122_ain5;
always @(posedge C122_clk)
begin: CB_AIN5_TO_C122
reg [11:0] ain1, ain0;
{ain1, ain0} <= {ain0, AIN5};
if (C122_cbfall)
C122_ain5 <= ain1;
end
assign PWM0_Data = C122_ALC_i;
assign PWM1_Data = {1'b0,C122_ain5,3'd0};
assign PWM2_Data = {1'b0,ALC_out[15:1]};
wire [15:0] set_level;
wire [15:0] gain;
wire [15:0] ALC_level;
wire [15:0] C122_res_i, C122_res_q;
reg [15:0] C122_qx0;
reg [15:0] C122_ix0;
wire [15:0] I_sync_data;
wire [15:0] Q_sync_data;
assign set_level = 16'hCCCC;
assign ALC_level = {5'd0,ALC_out[15:5]};
assign gain = (set_level - ALC_level);
ALC ALC_I(.out(C122_res_i), .sample(I_sync_data), .multiply(gain));
ALC ALC_Q(.out(C122_res_q), .sample(Q_sync_data), .multiply(gain));
wire C122_ce_out_i;
wire C122_ce_out_q;
reg signed [15:0] C122_cic_i;
reg signed [15:0] C122_cic_q;
always @ (posedge C122_clk)
begin
if (C122_cbfall)
begin
C122_ALC_i <= C122_res_i;
C122_ALC_q <= C122_res_q;
end
if (C122_ce_out_i)
C122_cic_i <= C122_ALC_i;
if (C122_ce_out_q)
C122_cic_q <= C122_ALC_q;
end
wire [15:0] C122_cic_out_i;
wire [15:0] C122_cic_out_q;
cicint cic_I(.clk(C122_clk), .clk_enable(1'b1), .reset(C122_rst), .filter_in(C122_cic_i),
.filter_out(C122_cic_out_i), .ce_out(C122_ce_out_i));
cicint cic_Q(.clk(C122_clk), .clk_enable(1'b1), .reset(C122_rst), .filter_in(C122_cic_q),
.filter_out(C122_cic_out_q), .ce_out(C122_ce_out_q));
wire [17:0] C122_i_out;
wire [17:0] C122_q_out;
wire [31:0] C122_phase;
phase_accumulator rx_phase_accumulator
(.clk(C122_clk), .reset(C122_rst), .frequency(C122_phase_word), .phase_out(C122_phase));
cordic_16 tx_cordic
(.i_in(C122_cic_out_q), .q_in(C122_cic_out_i),
.iout(C122_i_out), .qout(C122_q_out), .ain(C122_phase[31:12]), .clk(C122_clk));
assign DAC[13:0] = {C122_i_out[17], C122_i_out[15:3]};
reg [15:0] PWM0_Data_in;
reg [15:0] PWM1_Data_in;
reg [15:0] PWM2_Data_in;
reg [16:0] PWM0_accumulator;
reg [16:0] PWM1_accumulator;
reg [16:0] PWM2_accumulator;
always @(posedge C122_clk)
begin
PWM0_Data_in <= PWM0_Data + 16'h8000;
PWM1_Data_in <= PWM1_Data + 16'h8000;
PWM2_Data_in <= PWM2_Data + 16'h8000;
PWM0_accumulator <= PWM0_accumulator[15:0] + PWM0_Data_in;
PWM1_accumulator <= PWM1_accumulator[15:0] + PWM1_Data_in;
PWM2_accumulator <= PWM2_accumulator[15:0] + PWM2_Data_in;
end
assign PWM0 = PWM0_accumulator[16];
assign PWM1 = PWM1_accumulator[16];
assign PWM2 = PWM2_accumulator[16];
wire [60:0] rcv_data;
wire rcv_rdy;
reg PTT_out;
reg [3:0] C122_clock_select;
reg [6:0] OC;
parameter PENNY_ADDR = 4'b0;
always @ (posedge C122_clk)
begin
if (C122_rst)
begin
C122_DFS1 <= 1'b0;
C122_DFS0 <= 1'b0;
PTT_out <= 1'b0;
C122_frequency_HZ <= 32'b0;
C122_clock_select <= 4'b0000;
OC <= 7'b0;
end
else if (rcv_rdy)
begin
C122_DFS1 <= rcv_data[60];
C122_DFS0 <= rcv_data[59];
PTT_out <= rcv_data[58];
if (rcv_data[57:54] == PENNY_ADDR)
begin
C122_frequency_HZ <= rcv_data[53:22];
C122_clock_select <= rcv_data[21:18];
OC <= rcv_data[17:11];
end
end
end
NWire_rcv #(.DATA_BITS(61), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(500))
CCrcv (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_data(rcv_data), .xrcv_rdy(rcv_rdy), .xrcv_ack(rcv_rdy), .din(CC));
assign ref_ext = C122_clock_select[0];
assign source_122MHZ = (C122_clock_select[3:2] == 2'b00);
wire IQ_rdy;
NWire_rcv #(.DATA_BITS(32), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SLOWEST_FREQ(10000))
IQPWM (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xrcv_rdy(IQ_rdy), .xrcv_ack(IQ_rdy), .xrcv_data({I_sync_data, Q_sync_data}),
.din(C19));
assign C22 = CLRCLK;
I2S_xmit #(.DATA_BITS(32))
IQD (.rst(C122_rst), .lrclk(CLRCLK), .clk(C122_clk), .CBrise(C122_cbrise),
.CBfall(C122_cbfall), .sample({I_sync_data,Q_sync_data}), .outbit(TLV320_CDIN));
reg [15:0] C122_mic_data;
wire C122_mic_rdy;
wire [31:0] C122_mic_LR;
NWire_xmit #(.SEND_FREQ(48000),.DATA_BITS(16), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .LOW_TIME(1'b0))
P_MIC (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(C122_mic_data), .xreq(LRfall), .xrdy(), .xack(), .dout(A11));
always @(posedge C122_clk)
begin
if (C122_mic_rdy)
C122_mic_data <= C122_mic_LR[31:16];
end
I2S_rcv #(32,2,1)
PJD (.xrst(C122_rst), .xclk(C122_clk), .xData(C122_mic_LR),
.xData_rdy(C122_mic_rdy), .BCLK(C122_CBCLK), .LRCLK(CLRCLK), .din(TLV320_CDOUT));
wire [19:0] xmit_data;
assign xmit_data = {SERIAL,ALC_in[15:4]};
NWire_xmit #(.DATA_BITS(20), .ICLK_FREQ(122880000), .XCLK_FREQ(122880000), .SEND_FREQ(1000))
ser_no (.irst(C122_rst), .iclk(C122_clk), .xrst(C122_rst), .xclk(C122_clk),
.xdata(xmit_data), .xreq(1'b1), .xrdy(), .xack(), .dout(A5));
assign PTT_in = PTT ? 1'bz: 1'b1;
assign FPGA_PTT = PTT_out;
wire ref_80khz;
reg osc_80khz;
oddClockDivider refClockDivider(reference, ref_80khz);
reg [9:0] count_12288;
always @ (posedge C122_clk)
begin
if (count_12288 == 767)
begin
count_12288 <= 0;
osc_80khz <= ~osc_80khz;
end
else
count_12288 <= count_12288 + 10'b1;
end
assign FPGA_PLL = ref_80khz ^ osc_80khz;
assign LED2 = (AIN5 > 250)? 1'b0 : 1'b1;
assign LED3 = (AIN5 > 500)? 1'b0 : 1'b1;
assign LED4 = (AIN5 > 1000)? 1'b0 : 1'b1;
assign LED5 = (AIN5 > 2000)? 1'b0 : 1'b1;
assign LED6 = (AIN5 > 3000)? 1'b0 : 1'b1;
assign LED7 = 0;
assign USEROUT0 = OC[0];
assign USEROUT1 = OC[1];
assign USEROUT2 = OC[2];
assign USEROUT3 = OC[3];
assign USEROUT4 = OC[4];
assign USEROUT5 = OC[5];
assign USEROUT6 = OC[6];
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | 17 |
138,881 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.2/Penelope.v | 86,169,941 | Penelope.v | v | 733 | 119 | [] | ['general public license', 'free software foundation'] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.2,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.2/Penelope.v\n%Error: Exiting due to 4 error(s)\n' | 303,829 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,883 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.3/common/I2S_xmit.v | 86,169,941 | I2S_xmit.v | v | 167 | 100 | [] | ['general public license', 'free software foundation'] | [] | [(38, 167)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.3/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.3/common/I2S_xmit.v\n%Error: Exiting due to 4 error(s)\n' | 303,851 | module | module I2S_xmit (rst, lrclk, clk, CBrise, CBfall, sample, outbit, xmit_rdy, xmit_ack);
parameter DATA_BITS = 32;
parameter TPD = 5;
localparam SB = DATA_BITS;
localparam NB = DATA_BITS/2;
localparam NS = clogb2(NB-1);
input wire rst;
input wire lrclk;
input wire clk;
input wire CBrise;
input wire CBfall;
input wire [SB-1:0] sample;
output reg outbit;
output reg xmit_rdy;
input wire xmit_ack;
reg [NB-1:0] data;
reg [SB-1:0] last_data;
reg [NS-1:0] bit_count;
reg [2:0] TLV_state;
reg [2:0] TLV_state_next;
reg obit;
localparam TLV_IDLE = 0,
TLV_WH = 1,
TLV_LR_LO = 2,
TLV_WL = 3,
TLV_LR_HI = 4;
always @(posedge clk)
begin
if (rst)
TLV_state <= #TPD TLV_IDLE;
else
TLV_state <= #TPD TLV_state_next;
if (rst)
xmit_rdy <= #TPD 1'b0;
else if (TLV_state == TLV_IDLE)
xmit_rdy <= #TPD 1'b1;
else if (xmit_ack)
xmit_rdy <= #TPD 1'b0;
if (rst)
last_data <= #TPD 1'b0;
else if (TLV_state == TLV_IDLE)
last_data <= #TPD sample;
if (TLV_state == TLV_WH)
data <= #TPD last_data[SB-1:NB];
else if (TLV_state == TLV_WL)
data <= #TPD last_data[NB-1:0];
else if (CBrise)
data <= #TPD data << 1;
if (CBrise)
obit <= #TPD data[NB-1];
if (CBfall)
outbit <= #TPD obit;
if ((TLV_state == TLV_WH) || (TLV_state == TLV_WL))
bit_count <= #TPD NB-1;
else if ((bit_count != 0) && CBrise)
bit_count <= #TPD bit_count - 1'b1;
end
always @*
begin
case(TLV_state)
TLV_IDLE:
begin
if (!lrclk)
TLV_state_next = TLV_IDLE;
else
TLV_state_next = TLV_WH;
end
TLV_WH:
begin
if (lrclk)
TLV_state_next = TLV_WH;
else
TLV_state_next = TLV_LR_LO;
end
TLV_LR_LO:
begin
if ((bit_count == 0) & CBrise)
TLV_state_next = TLV_WL;
else
TLV_state_next = TLV_LR_LO;
end
TLV_WL:
begin
if (!lrclk)
TLV_state_next = TLV_WL;
else
TLV_state_next = TLV_LR_HI;
end
TLV_LR_HI:
begin
if ((bit_count == 0) & CBrise)
TLV_state_next = TLV_IDLE;
else
TLV_state_next = TLV_LR_HI;
end
default:
TLV_state_next = TLV_IDLE;
endcase
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | module I2S_xmit (rst, lrclk, clk, CBrise, CBfall, sample, outbit, xmit_rdy, xmit_ack); |
parameter DATA_BITS = 32;
parameter TPD = 5;
localparam SB = DATA_BITS;
localparam NB = DATA_BITS/2;
localparam NS = clogb2(NB-1);
input wire rst;
input wire lrclk;
input wire clk;
input wire CBrise;
input wire CBfall;
input wire [SB-1:0] sample;
output reg outbit;
output reg xmit_rdy;
input wire xmit_ack;
reg [NB-1:0] data;
reg [SB-1:0] last_data;
reg [NS-1:0] bit_count;
reg [2:0] TLV_state;
reg [2:0] TLV_state_next;
reg obit;
localparam TLV_IDLE = 0,
TLV_WH = 1,
TLV_LR_LO = 2,
TLV_WL = 3,
TLV_LR_HI = 4;
always @(posedge clk)
begin
if (rst)
TLV_state <= #TPD TLV_IDLE;
else
TLV_state <= #TPD TLV_state_next;
if (rst)
xmit_rdy <= #TPD 1'b0;
else if (TLV_state == TLV_IDLE)
xmit_rdy <= #TPD 1'b1;
else if (xmit_ack)
xmit_rdy <= #TPD 1'b0;
if (rst)
last_data <= #TPD 1'b0;
else if (TLV_state == TLV_IDLE)
last_data <= #TPD sample;
if (TLV_state == TLV_WH)
data <= #TPD last_data[SB-1:NB];
else if (TLV_state == TLV_WL)
data <= #TPD last_data[NB-1:0];
else if (CBrise)
data <= #TPD data << 1;
if (CBrise)
obit <= #TPD data[NB-1];
if (CBfall)
outbit <= #TPD obit;
if ((TLV_state == TLV_WH) || (TLV_state == TLV_WL))
bit_count <= #TPD NB-1;
else if ((bit_count != 0) && CBrise)
bit_count <= #TPD bit_count - 1'b1;
end
always @*
begin
case(TLV_state)
TLV_IDLE:
begin
if (!lrclk)
TLV_state_next = TLV_IDLE;
else
TLV_state_next = TLV_WH;
end
TLV_WH:
begin
if (lrclk)
TLV_state_next = TLV_WH;
else
TLV_state_next = TLV_LR_LO;
end
TLV_LR_LO:
begin
if ((bit_count == 0) & CBrise)
TLV_state_next = TLV_WL;
else
TLV_state_next = TLV_LR_LO;
end
TLV_WL:
begin
if (!lrclk)
TLV_state_next = TLV_WL;
else
TLV_state_next = TLV_LR_HI;
end
TLV_LR_HI:
begin
if ((bit_count == 0) & CBrise)
TLV_state_next = TLV_IDLE;
else
TLV_state_next = TLV_LR_HI;
end
default:
TLV_state_next = TLV_IDLE;
endcase
end
function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule | 17 |
138,884 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Archive/Penelope V1.3/common/I2S_xmit.v | 86,169,941 | I2S_xmit.v | v | 167 | 100 | [] | ['general public license', 'free software foundation'] | [] | [(38, 167)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Archive/Penelope\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Archive/Penelope.sv\n 1/Penelope/Source/Archive/Penelope\n 1/Penelope/Source/Archive/Penelope.v\n 1/Penelope/Source/Archive/Penelope.sv\n obj_dir/1/Penelope/Source/Archive/Penelope\n obj_dir/1/Penelope/Source/Archive/Penelope.v\n obj_dir/1/Penelope/Source/Archive/Penelope.sv\n%Error: Cannot find file containing module: V1.3/common,data/full_repos/permissive/86169941\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: V1.3/common/I2S_xmit.v\n%Error: Exiting due to 4 error(s)\n' | 303,851 | function | function integer clogb2;
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | function integer clogb2; |
input [31:0] depth;
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction | 17 |
138,887 | data/full_repos/permissive/86169941/Protocol 1/Penelope/Source/Penelope_V1.8/common/I2C.v | 86,169,941 | I2C.v | v | 114 | 103 | [] | ['general public license', 'free software foundation'] | [] | [(31, 114)] | null | null | 1: b'%Error: Cannot find file containing module: 1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941\n ... Looked in:\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941.v\n data/full_repos/permissive/86169941/Protocol/1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941.sv\n 1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941\n 1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941.v\n 1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941.sv\n obj_dir/1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941\n obj_dir/1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941.v\n obj_dir/1/Penelope/Source/Penelope_V1.8/common,data/full_repos/permissive/86169941.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86169941/Protocol\n%Error: Cannot find file containing module: 1/Penelope/Source/Penelope_V1.8/common/I2C.v\n%Error: Exiting due to 3 error(s)\n' | 303,944 | module | module I2C(CLK, sda, scl, version_no, Penny_pwr_out, FWD, REV);
input CLK;
inout sda;
input scl;
input [7:0] version_no;
input [11:0] Penny_pwr_out;
input [11:0] FWD;
input [11:0] REV;
reg reset;
wire [7:0]int_reg0;
wire [7:0]int_reg1;
reg [7:0]rcv_reg0;
reg [7:0]rcv_reg1;
wire sda_out;
wire sda_oe;
wire dg_scl;
wire dg_sda;
reg [6:0] slave_addr;
parameter ver_addr = 7'h15;
parameter PWROUT_addr = 7'h16;
parameter FWD_addr = 7'h17;
parameter REV_addr = 7'h18;
always @ (posedge CLK) begin
if (slave_addr == ver_addr) begin
rcv_reg0 <= 8'b0;
rcv_reg1 <= {1'b0, version_no};
end
if (slave_addr == PWROUT_addr) begin
rcv_reg0 <= {4'b0, Penny_pwr_out[11:8]};
rcv_reg1 <= Penny_pwr_out[7:0];
end
if (slave_addr == FWD_addr) begin
rcv_reg0 <= {4'b0, FWD[11:8]};
rcv_reg1 <= FWD[7:0];
end
if (slave_addr == REV_addr) begin
rcv_reg0 <= {4'b0, REV[11:8]};
rcv_reg1 <= REV[7:0];
end
end
reg [5:0]reset_count;
always @ (posedge CLK)
begin
if (reset_count[5]) begin
reset <= 1'b1;
end
else begin
reset <= 0;
reset_count <= reset_count + 1'b1;
end
end
deglitch deglitch_scl(.clock(CLK), .in(scl),.out(dg_scl));
deglitch deglitch_sda(.clock(CLK), .in(sda),.out(dg_sda));
i2c_slave(.rst_n(reset), .slave_addr(slave_addr), .ver_addr(ver_addr),
.PWROUT_addr(PWROUT_addr), .FWD_addr(FWD_addr), .REV_addr(REV_addr), .sda_i(dg_sda),
.sda_out(sda_out),.sda_oe(sda_oe),.scl_in(dg_scl), .int_reg0(LED),.int_reg1(),
.rcv_reg0(rcv_reg0), .rcv_reg1(rcv_reg1));
assign sda = sda_oe ? (sda_out ? 1'bz : 1'b0) : 1'bz;
endmodule | module I2C(CLK, sda, scl, version_no, Penny_pwr_out, FWD, REV); |
input CLK;
inout sda;
input scl;
input [7:0] version_no;
input [11:0] Penny_pwr_out;
input [11:0] FWD;
input [11:0] REV;
reg reset;
wire [7:0]int_reg0;
wire [7:0]int_reg1;
reg [7:0]rcv_reg0;
reg [7:0]rcv_reg1;
wire sda_out;
wire sda_oe;
wire dg_scl;
wire dg_sda;
reg [6:0] slave_addr;
parameter ver_addr = 7'h15;
parameter PWROUT_addr = 7'h16;
parameter FWD_addr = 7'h17;
parameter REV_addr = 7'h18;
always @ (posedge CLK) begin
if (slave_addr == ver_addr) begin
rcv_reg0 <= 8'b0;
rcv_reg1 <= {1'b0, version_no};
end
if (slave_addr == PWROUT_addr) begin
rcv_reg0 <= {4'b0, Penny_pwr_out[11:8]};
rcv_reg1 <= Penny_pwr_out[7:0];
end
if (slave_addr == FWD_addr) begin
rcv_reg0 <= {4'b0, FWD[11:8]};
rcv_reg1 <= FWD[7:0];
end
if (slave_addr == REV_addr) begin
rcv_reg0 <= {4'b0, REV[11:8]};
rcv_reg1 <= REV[7:0];
end
end
reg [5:0]reset_count;
always @ (posedge CLK)
begin
if (reset_count[5]) begin
reset <= 1'b1;
end
else begin
reset <= 0;
reset_count <= reset_count + 1'b1;
end
end
deglitch deglitch_scl(.clock(CLK), .in(scl),.out(dg_scl));
deglitch deglitch_sda(.clock(CLK), .in(sda),.out(dg_sda));
i2c_slave(.rst_n(reset), .slave_addr(slave_addr), .ver_addr(ver_addr),
.PWROUT_addr(PWROUT_addr), .FWD_addr(FWD_addr), .REV_addr(REV_addr), .sda_i(dg_sda),
.sda_out(sda_out),.sda_oe(sda_oe),.scl_in(dg_scl), .int_reg0(LED),.int_reg1(),
.rcv_reg0(rcv_reg0), .rcv_reg1(rcv_reg1));
assign sda = sda_oe ? (sda_out ? 1'bz : 1'b0) : 1'bz;
endmodule | 17 |
138,888 | data/full_repos/permissive/86267182/xsr.v | 86,267,182 | xsr.v | v | 81 | 55 | [] | [] | [] | [(1, 80)] | null | data/verilator_xmls/808efd5b-0190-4111-8082-0a942ef72f7f.xml | null | 303,950 | module | module xsr(
input clk_i,
input reset_i,
input [5:0] bits_i,
input [63:0] baud_i,
input rxd_i,
input rxc_i,
input rxreg_oe_i,
input rxregr_oe_i,
output [63:0] dat_o,
output idle_o,
output sample_to
);
parameter SHIFT_REG_WIDTH=64;
parameter SRW = SHIFT_REG_WIDTH - 1;
reg [SRW:0] shiftRegister;
reg [63:0] sampleCtr;
reg [5:0] bitsLeft;
reg d0, d1, c0, c1;
wire edgeDetected = (d0 ^ d1) | (~c1 & c0);
wire sampleBit = ~idle_o && (sampleCtr == 0);
wire [SRW:0] shiftRegister_rev;
genvar i;
generate
for(i = 0; i <= SRW; i = i + 1) begin
assign shiftRegister_rev[i] = shiftRegister[SRW-i];
end
endgenerate
assign idle_o = (bitsLeft == 0);
assign dat_o = (rxreg_oe_i ? shiftRegister : 0)
| (rxregr_oe_i ? shiftRegister_rev : 0);
always @(posedge clk_i) begin
shiftRegister <= shiftRegister;
bitsLeft <= bitsLeft;
sampleCtr <= sampleCtr;
d1 <= d0;
d0 <= rxd_i;
c1 <= c0;
c0 <= rxc_i;
if(reset_i) begin
shiftRegister <= ~(0);
bitsLeft <= 0;
sampleCtr <= baud_i;
d0 <= 1;
d1 <= 1;
end
else begin
if(edgeDetected) begin
if(idle_o) begin
bitsLeft <= bits_i;
end
sampleCtr <= {1'b0, baud_i[63:1]};
end
else if(sampleBit) begin
sampleCtr <= baud_i;
bitsLeft <= bitsLeft - 1;
shiftRegister <= {d0, shiftRegister[SRW:1]};
end
else if(idle_o) begin
sampleCtr <= baud_i;
end
else begin
sampleCtr <= sampleCtr - 1;
end
end
end
assign sample_to = sampleBit;
endmodule | module xsr(
input clk_i,
input reset_i,
input [5:0] bits_i,
input [63:0] baud_i,
input rxd_i,
input rxc_i,
input rxreg_oe_i,
input rxregr_oe_i,
output [63:0] dat_o,
output idle_o,
output sample_to
); |
parameter SHIFT_REG_WIDTH=64;
parameter SRW = SHIFT_REG_WIDTH - 1;
reg [SRW:0] shiftRegister;
reg [63:0] sampleCtr;
reg [5:0] bitsLeft;
reg d0, d1, c0, c1;
wire edgeDetected = (d0 ^ d1) | (~c1 & c0);
wire sampleBit = ~idle_o && (sampleCtr == 0);
wire [SRW:0] shiftRegister_rev;
genvar i;
generate
for(i = 0; i <= SRW; i = i + 1) begin
assign shiftRegister_rev[i] = shiftRegister[SRW-i];
end
endgenerate
assign idle_o = (bitsLeft == 0);
assign dat_o = (rxreg_oe_i ? shiftRegister : 0)
| (rxregr_oe_i ? shiftRegister_rev : 0);
always @(posedge clk_i) begin
shiftRegister <= shiftRegister;
bitsLeft <= bitsLeft;
sampleCtr <= sampleCtr;
d1 <= d0;
d0 <= rxd_i;
c1 <= c0;
c0 <= rxc_i;
if(reset_i) begin
shiftRegister <= ~(0);
bitsLeft <= 0;
sampleCtr <= baud_i;
d0 <= 1;
d1 <= 1;
end
else begin
if(edgeDetected) begin
if(idle_o) begin
bitsLeft <= bits_i;
end
sampleCtr <= {1'b0, baud_i[63:1]};
end
else if(sampleBit) begin
sampleCtr <= baud_i;
bitsLeft <= bitsLeft - 1;
shiftRegister <= {d0, shiftRegister[SRW:1]};
end
else if(idle_o) begin
sampleCtr <= baud_i;
end
else begin
sampleCtr <= sampleCtr - 1;
end
end
end
assign sample_to = sampleBit;
endmodule | 1 |
138,889 | data/full_repos/permissive/86267182/xst.v | 86,267,182 | xst.v | v | 171 | 53 | [] | [] | [] | [(3, 169)] | null | null | 1: b"%Error: data/full_repos/permissive/86267182/xst.v:24: Duplicate declaration of signal: 'bits_o'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [5:0] bits_o;\n ^~~~~~\n data/full_repos/permissive/86267182/xst.v:21: ... Location of original declaration\n output [5:0] bits_o,\n ^~~~~~\n%Error: data/full_repos/permissive/86267182/xst.v:25: Duplicate declaration of signal: 'brg_o'\n reg [15:0] brg_o;\n ^~~~~\n data/full_repos/permissive/86267182/xst.v:20: ... Location of original declaration\n output [15:0] brg_o,\n ^~~~~\n%Error: data/full_repos/permissive/86267182/xst.v:27: Duplicate declaration of signal: 'txc_o'\n reg txc_o;\n ^~~~~\n data/full_repos/permissive/86267182/xst.v:18: ... Location of original declaration\n output txc_o,\n ^~~~~\n%Error: Exiting due to 3 error(s)\n" | 303,952 | module | module xst(
input clk_i,
input reset_i,
input rxd_i,
input [63:0] dat_i,
input txreg_we_i,
input txregr_we_i,
input txreg_oe_i,
input txregr_oe_i,
input [15:0] txbaud_i,
input [5:0] bits_i,
output txd_o,
output txc_o,
output idle_o,
output [15:0] brg_o,
output [5:0] bits_o,
output [63:0] dat_o
);
reg [5:0] bits_o;
reg [15:0] brg_o;
reg [63:0] shift_register;
reg txc_o;
assign txd_o = shift_register[0];
assign idle_o = ~|bits_o;
wire txreg_shift = ~|brg_o;
wire [15:1] halfbit = txbaud_i[15:1];
wire [63:0] shift_reg_rev = {
shift_register[0],
shift_register[1],
shift_register[2],
shift_register[3],
shift_register[4],
shift_register[5],
shift_register[6],
shift_register[7],
shift_register[8],
shift_register[9],
shift_register[10],
shift_register[11],
shift_register[12],
shift_register[13],
shift_register[14],
shift_register[15],
shift_register[16],
shift_register[17],
shift_register[18],
shift_register[19],
shift_register[20],
shift_register[21],
shift_register[22],
shift_register[23],
shift_register[24],
shift_register[25],
shift_register[26],
shift_register[27],
shift_register[28],
shift_register[29],
shift_register[30],
shift_register[31],
shift_register[32],
shift_register[33],
shift_register[34],
shift_register[35],
shift_register[36],
shift_register[37],
shift_register[38],
shift_register[39],
shift_register[40],
shift_register[41],
shift_register[42],
shift_register[43],
shift_register[44],
shift_register[45],
shift_register[46],
shift_register[47],
shift_register[48],
shift_register[49],
shift_register[50],
shift_register[51],
shift_register[52],
shift_register[53],
shift_register[54],
shift_register[55],
shift_register[56],
shift_register[57],
shift_register[58],
shift_register[59],
shift_register[60],
shift_register[61],
shift_register[62],
shift_register[63]
};
assign dat_o =
(txreg_oe_i ? shift_register : 0)
| (txregr_oe_i ? shift_reg_rev : 0);
always @(posedge clk_i) begin
shift_register <= shift_register;
brg_o <= brg_o;
txc_o <= txc_o;
bits_o <= bits_o;
if(reset_i) begin
shift_register <= ~(64'd0);
brg_o <= 0;
txc_o <= 0;
bits_o <= 0;
end
else if(txreg_we_i) begin
brg_o <= txbaud_i;
txc_o <= 1;
shift_register <= dat_i;
bits_o <= bits_i;
end
else if(txregr_we_i) begin
brg_o <= txbaud_i;
txc_o <= 1;
shift_register <= {
dat_i[0], dat_i[1], dat_i[2], dat_i[3],
dat_i[4], dat_i[5], dat_i[6], dat_i[7],
dat_i[8], dat_i[9],
dat_i[10], dat_i[11], dat_i[12], dat_i[13],
dat_i[14], dat_i[15], dat_i[16], dat_i[17],
dat_i[18], dat_i[19],
dat_i[20], dat_i[21], dat_i[22], dat_i[23],
dat_i[24], dat_i[25], dat_i[26], dat_i[27],
dat_i[28], dat_i[29],
dat_i[30], dat_i[31], dat_i[32], dat_i[33],
dat_i[34], dat_i[35], dat_i[36], dat_i[37],
dat_i[38], dat_i[39],
dat_i[40], dat_i[41], dat_i[42], dat_i[43],
dat_i[44], dat_i[45], dat_i[46], dat_i[47],
dat_i[48], dat_i[49],
dat_i[50], dat_i[51], dat_i[52], dat_i[53],
dat_i[54], dat_i[55], dat_i[56], dat_i[57],
dat_i[58], dat_i[59],
dat_i[60], dat_i[61], dat_i[62], dat_i[63]
};
bits_o <= bits_i;
end
else begin
if(txreg_shift & ~idle_o) begin
brg_o <= txbaud_i;
txc_o <= (bits_o != 6'd1);
shift_register <= {rxd_i, shift_register[63:1]};
bits_o <= bits_o - 1;
end
else if(~txreg_shift & ~idle_o) begin
brg_o <= brg_o - 1;
end
end
if(brg_o == {1'b0, halfbit}) begin
txc_o <= 0;
end
end
endmodule | module xst(
input clk_i,
input reset_i,
input rxd_i,
input [63:0] dat_i,
input txreg_we_i,
input txregr_we_i,
input txreg_oe_i,
input txregr_oe_i,
input [15:0] txbaud_i,
input [5:0] bits_i,
output txd_o,
output txc_o,
output idle_o,
output [15:0] brg_o,
output [5:0] bits_o,
output [63:0] dat_o
); |
reg [5:0] bits_o;
reg [15:0] brg_o;
reg [63:0] shift_register;
reg txc_o;
assign txd_o = shift_register[0];
assign idle_o = ~|bits_o;
wire txreg_shift = ~|brg_o;
wire [15:1] halfbit = txbaud_i[15:1];
wire [63:0] shift_reg_rev = {
shift_register[0],
shift_register[1],
shift_register[2],
shift_register[3],
shift_register[4],
shift_register[5],
shift_register[6],
shift_register[7],
shift_register[8],
shift_register[9],
shift_register[10],
shift_register[11],
shift_register[12],
shift_register[13],
shift_register[14],
shift_register[15],
shift_register[16],
shift_register[17],
shift_register[18],
shift_register[19],
shift_register[20],
shift_register[21],
shift_register[22],
shift_register[23],
shift_register[24],
shift_register[25],
shift_register[26],
shift_register[27],
shift_register[28],
shift_register[29],
shift_register[30],
shift_register[31],
shift_register[32],
shift_register[33],
shift_register[34],
shift_register[35],
shift_register[36],
shift_register[37],
shift_register[38],
shift_register[39],
shift_register[40],
shift_register[41],
shift_register[42],
shift_register[43],
shift_register[44],
shift_register[45],
shift_register[46],
shift_register[47],
shift_register[48],
shift_register[49],
shift_register[50],
shift_register[51],
shift_register[52],
shift_register[53],
shift_register[54],
shift_register[55],
shift_register[56],
shift_register[57],
shift_register[58],
shift_register[59],
shift_register[60],
shift_register[61],
shift_register[62],
shift_register[63]
};
assign dat_o =
(txreg_oe_i ? shift_register : 0)
| (txregr_oe_i ? shift_reg_rev : 0);
always @(posedge clk_i) begin
shift_register <= shift_register;
brg_o <= brg_o;
txc_o <= txc_o;
bits_o <= bits_o;
if(reset_i) begin
shift_register <= ~(64'd0);
brg_o <= 0;
txc_o <= 0;
bits_o <= 0;
end
else if(txreg_we_i) begin
brg_o <= txbaud_i;
txc_o <= 1;
shift_register <= dat_i;
bits_o <= bits_i;
end
else if(txregr_we_i) begin
brg_o <= txbaud_i;
txc_o <= 1;
shift_register <= {
dat_i[0], dat_i[1], dat_i[2], dat_i[3],
dat_i[4], dat_i[5], dat_i[6], dat_i[7],
dat_i[8], dat_i[9],
dat_i[10], dat_i[11], dat_i[12], dat_i[13],
dat_i[14], dat_i[15], dat_i[16], dat_i[17],
dat_i[18], dat_i[19],
dat_i[20], dat_i[21], dat_i[22], dat_i[23],
dat_i[24], dat_i[25], dat_i[26], dat_i[27],
dat_i[28], dat_i[29],
dat_i[30], dat_i[31], dat_i[32], dat_i[33],
dat_i[34], dat_i[35], dat_i[36], dat_i[37],
dat_i[38], dat_i[39],
dat_i[40], dat_i[41], dat_i[42], dat_i[43],
dat_i[44], dat_i[45], dat_i[46], dat_i[47],
dat_i[48], dat_i[49],
dat_i[50], dat_i[51], dat_i[52], dat_i[53],
dat_i[54], dat_i[55], dat_i[56], dat_i[57],
dat_i[58], dat_i[59],
dat_i[60], dat_i[61], dat_i[62], dat_i[63]
};
bits_o <= bits_i;
end
else begin
if(txreg_shift & ~idle_o) begin
brg_o <= txbaud_i;
txc_o <= (bits_o != 6'd1);
shift_register <= {rxd_i, shift_register[63:1]};
bits_o <= bits_o - 1;
end
else if(~txreg_shift & ~idle_o) begin
brg_o <= brg_o - 1;
end
end
if(brg_o == {1'b0, halfbit}) begin
txc_o <= 0;
end
end
endmodule | 1 |
138,891 | data/full_repos/permissive/86337678/rtl/AsyncReceiver.v | 86,337,678 | AsyncReceiver.v | v | 263 | 87 | [] | [] | [] | [(6, 88), (90, 261)] | null | data/verilator_xmls/7e990470-9a28-4628-9ff0-8370a239a765.xml | null | 303,961 | module | module Fifo (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input io_read,
input io_write,
output io_full,
output io_empty,
input clk,
input reset);
wire [7:0] _zz_5;
wire [4:0] _zz_6;
wire [4:0] _zz_7;
wire [7:0] _zz_8;
wire _zz_9;
reg [4:0] head;
reg [4:0] tail;
reg full;
reg empty;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg _zz_4;
reg [7:0] mem [0:31];
assign _zz_6 = (head + (5'b00001));
assign _zz_7 = (tail + (5'b00001));
assign _zz_8 = io_dataIn;
assign _zz_9 = ((! full) && io_write);
always @ (posedge clk) begin
if(_zz_9) begin
mem[head] <= _zz_8;
end
end
assign _zz_5 = mem[tail];
assign io_dataOut = _zz_5;
assign io_empty = empty;
assign io_full = full;
always @ (posedge clk or posedge reset) begin
if (reset) begin
head <= (5'b00000);
tail <= (5'b00000);
full <= 1'b0;
empty <= 1'b1;
end else begin
if(((io_write && (! _zz_1)) && (! io_read)))begin
if((! full))begin
head <= (head + (5'b00001));
full <= (_zz_6 == tail);
empty <= 1'b0;
end
end
if(((! io_write) && (io_read && (! _zz_2))))begin
if((! empty))begin
tail <= (tail + (5'b00001));
empty <= (_zz_7 == head);
full <= 1'b0;
end
end
if(((io_write && (! _zz_3)) && (io_read && (! _zz_4))))begin
if(full)begin
tail <= (tail + (5'b00001));
full <= 1'b0;
end
if(empty)begin
head <= (head + (5'b00001));
empty <= 1'b0;
end
if(((! full) && (! empty)))begin
tail <= (tail + (5'b00001));
head <= (head + (5'b00001));
end
end
end
end
always @ (posedge clk) begin
_zz_1 <= io_write;
_zz_2 <= io_read;
_zz_3 <= io_write;
_zz_4 <= io_read;
end
endmodule | module Fifo (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input io_read,
input io_write,
output io_full,
output io_empty,
input clk,
input reset); |
wire [7:0] _zz_5;
wire [4:0] _zz_6;
wire [4:0] _zz_7;
wire [7:0] _zz_8;
wire _zz_9;
reg [4:0] head;
reg [4:0] tail;
reg full;
reg empty;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg _zz_4;
reg [7:0] mem [0:31];
assign _zz_6 = (head + (5'b00001));
assign _zz_7 = (tail + (5'b00001));
assign _zz_8 = io_dataIn;
assign _zz_9 = ((! full) && io_write);
always @ (posedge clk) begin
if(_zz_9) begin
mem[head] <= _zz_8;
end
end
assign _zz_5 = mem[tail];
assign io_dataOut = _zz_5;
assign io_empty = empty;
assign io_full = full;
always @ (posedge clk or posedge reset) begin
if (reset) begin
head <= (5'b00000);
tail <= (5'b00000);
full <= 1'b0;
empty <= 1'b1;
end else begin
if(((io_write && (! _zz_1)) && (! io_read)))begin
if((! full))begin
head <= (head + (5'b00001));
full <= (_zz_6 == tail);
empty <= 1'b0;
end
end
if(((! io_write) && (io_read && (! _zz_2))))begin
if((! empty))begin
tail <= (tail + (5'b00001));
empty <= (_zz_7 == head);
full <= 1'b0;
end
end
if(((io_write && (! _zz_3)) && (io_read && (! _zz_4))))begin
if(full)begin
tail <= (tail + (5'b00001));
full <= 1'b0;
end
if(empty)begin
head <= (head + (5'b00001));
empty <= 1'b0;
end
if(((! full) && (! empty)))begin
tail <= (tail + (5'b00001));
head <= (head + (5'b00001));
end
end
end
end
always @ (posedge clk) begin
_zz_1 <= io_write;
_zz_2 <= io_read;
_zz_3 <= io_write;
_zz_4 <= io_read;
end
endmodule | 9 |
138,892 | data/full_repos/permissive/86337678/rtl/AsyncReceiver.v | 86,337,678 | AsyncReceiver.v | v | 263 | 87 | [] | [] | [] | [(6, 88), (90, 261)] | null | data/verilator_xmls/7e990470-9a28-4628-9ff0-8370a239a765.xml | null | 303,961 | module | module AsyncReceiver (
input io_enable,
input io_mem_valid,
output io_mem_ready,
input [3:0] io_mem_addr,
output [31:0] io_mem_rdata,
input io_baudClockX64,
input io_rx,
input clk,
input reset);
reg _zz_5;
reg _zz_6;
wire [7:0] _zz_7;
wire _zz_8;
wire _zz_9;
wire _zz_10;
wire _zz_11;
wire [31:0] _zz_12;
wire [0:0] _zz_13;
reg [1:0] state;
reg [5:0] bitTimer;
reg [2:0] bitCount;
reg [7:0] shifter;
reg baudClockX64Sync1;
reg baudClockX64Sync2;
reg rxSync1;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg [7:0] rdata;
reg ready;
wire busCycle;
reg _zz_4;
assign _zz_10 = (busCycle && (! _zz_4));
assign _zz_11 = (bitTimer == (6'b000000));
assign _zz_12 = {24'd0, rdata};
assign _zz_13 = (! _zz_9);
Fifo fifo_1 (
.io_dataIn(shifter),
.io_dataOut(_zz_7),
.io_read(_zz_5),
.io_write(_zz_6),
.io_full(_zz_8),
.io_empty(_zz_9),
.clk(clk),
.reset(reset)
);
always @ (*) begin
_zz_5 = 1'b0;
if(_zz_10)begin
case(io_mem_addr)
4'b0000 : begin
_zz_5 = 1'b1;
end
4'b0100 : begin
end
default : begin
end
endcase
end
end
always @ (*) begin
_zz_6 = 1'b0;
case(state)
2'b00 : begin
end
2'b01 : begin
end
2'b10 : begin
end
default : begin
if(_zz_11)begin
if((rxSync1 == 1'b1))begin
if((! _zz_8))begin
_zz_6 = 1'b1;
end
end
end
end
endcase
end
assign busCycle = (io_mem_valid && io_enable);
assign io_mem_rdata = (busCycle ? _zz_12 : (32'b00000000000000000000000000000000));
assign io_mem_ready = (busCycle ? ready : 1'b0);
always @ (posedge clk or posedge reset) begin
if (reset) begin
state <= (2'b00);
bitTimer <= (6'b000000);
bitCount <= (3'b000);
shifter <= (8'b00000000);
baudClockX64Sync1 <= 1'b0;
baudClockX64Sync2 <= 1'b0;
rxSync1 <= 1'b0;
rdata <= (8'b00000000);
ready <= 1'b0;
end else begin
baudClockX64Sync1 <= io_baudClockX64;
baudClockX64Sync2 <= baudClockX64Sync1;
rxSync1 <= io_rx;
if((baudClockX64Sync2 && (! _zz_1)))begin
bitTimer <= (bitTimer - (6'b000001));
end
case(state)
2'b00 : begin
state <= (2'b00);
if(((! rxSync1) && _zz_2))begin
state <= (2'b01);
bitTimer <= (6'b011111);
end
end
2'b01 : begin
state <= (2'b01);
if((bitTimer == (6'b000000)))begin
if((rxSync1 == 1'b0))begin
bitTimer <= (6'b111111);
state <= (2'b10);
end else begin
state <= (2'b00);
end
end
end
2'b10 : begin
state <= (2'b10);
if((baudClockX64Sync2 && (! _zz_3)))begin
if((bitTimer == (6'b000000)))begin
shifter[bitCount] <= rxSync1;
bitCount <= (bitCount + (3'b001));
if((bitCount == (3'b111)))begin
state <= (2'b11);
end
end
end
end
default : begin
state <= (2'b11);
if(_zz_11)begin
state <= (2'b00);
end
end
endcase
ready <= busCycle;
if(_zz_10)begin
case(io_mem_addr)
4'b0000 : begin
rdata <= _zz_7;
end
4'b0100 : begin
rdata <= {7'd0, _zz_13};
end
default : begin
end
endcase
end
end
end
always @ (posedge clk) begin
_zz_1 <= baudClockX64Sync2;
_zz_4 <= busCycle;
end
always @ (posedge clk) begin
_zz_2 <= rxSync1;
end
always @ (posedge clk) begin
_zz_3 <= baudClockX64Sync2;
end
endmodule | module AsyncReceiver (
input io_enable,
input io_mem_valid,
output io_mem_ready,
input [3:0] io_mem_addr,
output [31:0] io_mem_rdata,
input io_baudClockX64,
input io_rx,
input clk,
input reset); |
reg _zz_5;
reg _zz_6;
wire [7:0] _zz_7;
wire _zz_8;
wire _zz_9;
wire _zz_10;
wire _zz_11;
wire [31:0] _zz_12;
wire [0:0] _zz_13;
reg [1:0] state;
reg [5:0] bitTimer;
reg [2:0] bitCount;
reg [7:0] shifter;
reg baudClockX64Sync1;
reg baudClockX64Sync2;
reg rxSync1;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg [7:0] rdata;
reg ready;
wire busCycle;
reg _zz_4;
assign _zz_10 = (busCycle && (! _zz_4));
assign _zz_11 = (bitTimer == (6'b000000));
assign _zz_12 = {24'd0, rdata};
assign _zz_13 = (! _zz_9);
Fifo fifo_1 (
.io_dataIn(shifter),
.io_dataOut(_zz_7),
.io_read(_zz_5),
.io_write(_zz_6),
.io_full(_zz_8),
.io_empty(_zz_9),
.clk(clk),
.reset(reset)
);
always @ (*) begin
_zz_5 = 1'b0;
if(_zz_10)begin
case(io_mem_addr)
4'b0000 : begin
_zz_5 = 1'b1;
end
4'b0100 : begin
end
default : begin
end
endcase
end
end
always @ (*) begin
_zz_6 = 1'b0;
case(state)
2'b00 : begin
end
2'b01 : begin
end
2'b10 : begin
end
default : begin
if(_zz_11)begin
if((rxSync1 == 1'b1))begin
if((! _zz_8))begin
_zz_6 = 1'b1;
end
end
end
end
endcase
end
assign busCycle = (io_mem_valid && io_enable);
assign io_mem_rdata = (busCycle ? _zz_12 : (32'b00000000000000000000000000000000));
assign io_mem_ready = (busCycle ? ready : 1'b0);
always @ (posedge clk or posedge reset) begin
if (reset) begin
state <= (2'b00);
bitTimer <= (6'b000000);
bitCount <= (3'b000);
shifter <= (8'b00000000);
baudClockX64Sync1 <= 1'b0;
baudClockX64Sync2 <= 1'b0;
rxSync1 <= 1'b0;
rdata <= (8'b00000000);
ready <= 1'b0;
end else begin
baudClockX64Sync1 <= io_baudClockX64;
baudClockX64Sync2 <= baudClockX64Sync1;
rxSync1 <= io_rx;
if((baudClockX64Sync2 && (! _zz_1)))begin
bitTimer <= (bitTimer - (6'b000001));
end
case(state)
2'b00 : begin
state <= (2'b00);
if(((! rxSync1) && _zz_2))begin
state <= (2'b01);
bitTimer <= (6'b011111);
end
end
2'b01 : begin
state <= (2'b01);
if((bitTimer == (6'b000000)))begin
if((rxSync1 == 1'b0))begin
bitTimer <= (6'b111111);
state <= (2'b10);
end else begin
state <= (2'b00);
end
end
end
2'b10 : begin
state <= (2'b10);
if((baudClockX64Sync2 && (! _zz_3)))begin
if((bitTimer == (6'b000000)))begin
shifter[bitCount] <= rxSync1;
bitCount <= (bitCount + (3'b001));
if((bitCount == (3'b111)))begin
state <= (2'b11);
end
end
end
end
default : begin
state <= (2'b11);
if(_zz_11)begin
state <= (2'b00);
end
end
endcase
ready <= busCycle;
if(_zz_10)begin
case(io_mem_addr)
4'b0000 : begin
rdata <= _zz_7;
end
4'b0100 : begin
rdata <= {7'd0, _zz_13};
end
default : begin
end
endcase
end
end
end
always @ (posedge clk) begin
_zz_1 <= baudClockX64Sync2;
_zz_4 <= busCycle;
end
always @ (posedge clk) begin
_zz_2 <= rxSync1;
end
always @ (posedge clk) begin
_zz_3 <= baudClockX64Sync2;
end
endmodule | 9 |
138,893 | data/full_repos/permissive/86337678/rtl/busInterface.v | 86,337,678 | busInterface.v | v | 61 | 50 | [] | [] | [] | [(1, 58)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'enables'\n : ... In instance busInterface\n enables = 0;\n ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:37: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n 28'hffff000: mem_ready = mem_ready_memory;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n 28'hffff001: mem_ready = mem_ready_memory;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:39: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n 28'hffff002: mem_ready = mem_ready_uartRx;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:40: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n 28'hffff003: mem_ready = mem_ready_timer;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:41: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n 28'hffff004: mem_ready = mem_ready_uart;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:42: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n 28'hffff005: mem_ready = mem_ready_prng;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:43: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n 28'hffff006: mem_ready = mem_ready_gpio;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_ready'\n : ... In instance busInterface\n default: mem_ready = mem_ready_memory;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n 28'hffff000: mem_rdata = mem_rdata_memory;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:48: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n 28'hffff001: mem_rdata = mem_rdata_memory;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:49: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n 28'hffff002: mem_rdata = mem_rdata_uartRx;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:50: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n 28'hffff003: mem_rdata = mem_rdata_timer;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:51: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n 28'hffff004: mem_rdata = mem_rdata_uart;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n 28'hffff005: mem_rdata = mem_rdata_prng;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:53: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n 28'hffff006: mem_rdata = mem_rdata_gpio;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86337678/rtl/busInterface.v:54: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'mem_rdata'\n : ... In instance busInterface\n default: mem_rdata = mem_rdata_memory;\n ^~~~~~~~~\n%Error: Exiting due to 17 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 303,962 | module | module busInterface (
input wire [31:0] mem_addr,
input wire [31:0] mem_rdata_gpio,
input wire [31:0] mem_rdata_uart,
input wire [31:0] mem_rdata_uartRx,
input wire [31:0] mem_rdata_timer,
input wire [31:0] mem_rdata_prng,
input wire [31:0] mem_rdata_memory,
input wire mem_ready_gpio,
input wire mem_ready_uart,
input wire mem_ready_uartRx,
input wire mem_ready_timer,
input wire mem_ready_prng,
input wire mem_ready_memory,
output wire mem_ready,
output wire [31:0] mem_rdata,
output wire [7:0] enables
);
always @(*) begin
enables = 0;
case (mem_addr[31:4])
28'hffff000: enables[0] = 1'd1;
28'hffff001: enables[1] = 1'd1;
28'hffff002: enables[2] = 1'd1;
28'hffff003: enables[3] = 1'd1;
28'hffff004: enables[4] = 1'd1;
28'hffff005: enables[5] = 1'd1;
28'hffff006: enables[6] = 1'd1;
default: enables[7] = 1;
endcase
case (mem_addr[31:4])
28'hffff000: mem_ready = mem_ready_memory;
28'hffff001: mem_ready = mem_ready_memory;
28'hffff002: mem_ready = mem_ready_uartRx;
28'hffff003: mem_ready = mem_ready_timer;
28'hffff004: mem_ready = mem_ready_uart;
28'hffff005: mem_ready = mem_ready_prng;
28'hffff006: mem_ready = mem_ready_gpio;
default: mem_ready = mem_ready_memory;
endcase
case (mem_addr[31:4])
28'hffff000: mem_rdata = mem_rdata_memory;
28'hffff001: mem_rdata = mem_rdata_memory;
28'hffff002: mem_rdata = mem_rdata_uartRx;
28'hffff003: mem_rdata = mem_rdata_timer;
28'hffff004: mem_rdata = mem_rdata_uart;
28'hffff005: mem_rdata = mem_rdata_prng;
28'hffff006: mem_rdata = mem_rdata_gpio;
default: mem_rdata = mem_rdata_memory;
endcase
end
endmodule | module busInterface (
input wire [31:0] mem_addr,
input wire [31:0] mem_rdata_gpio,
input wire [31:0] mem_rdata_uart,
input wire [31:0] mem_rdata_uartRx,
input wire [31:0] mem_rdata_timer,
input wire [31:0] mem_rdata_prng,
input wire [31:0] mem_rdata_memory,
input wire mem_ready_gpio,
input wire mem_ready_uart,
input wire mem_ready_uartRx,
input wire mem_ready_timer,
input wire mem_ready_prng,
input wire mem_ready_memory,
output wire mem_ready,
output wire [31:0] mem_rdata,
output wire [7:0] enables
); |
always @(*) begin
enables = 0;
case (mem_addr[31:4])
28'hffff000: enables[0] = 1'd1;
28'hffff001: enables[1] = 1'd1;
28'hffff002: enables[2] = 1'd1;
28'hffff003: enables[3] = 1'd1;
28'hffff004: enables[4] = 1'd1;
28'hffff005: enables[5] = 1'd1;
28'hffff006: enables[6] = 1'd1;
default: enables[7] = 1;
endcase
case (mem_addr[31:4])
28'hffff000: mem_ready = mem_ready_memory;
28'hffff001: mem_ready = mem_ready_memory;
28'hffff002: mem_ready = mem_ready_uartRx;
28'hffff003: mem_ready = mem_ready_timer;
28'hffff004: mem_ready = mem_ready_uart;
28'hffff005: mem_ready = mem_ready_prng;
28'hffff006: mem_ready = mem_ready_gpio;
default: mem_ready = mem_ready_memory;
endcase
case (mem_addr[31:4])
28'hffff000: mem_rdata = mem_rdata_memory;
28'hffff001: mem_rdata = mem_rdata_memory;
28'hffff002: mem_rdata = mem_rdata_uartRx;
28'hffff003: mem_rdata = mem_rdata_timer;
28'hffff004: mem_rdata = mem_rdata_uart;
28'hffff005: mem_rdata = mem_rdata_prng;
28'hffff006: mem_rdata = mem_rdata_gpio;
default: mem_rdata = mem_rdata_memory;
endcase
end
endmodule | 9 |
138,895 | data/full_repos/permissive/86337678/rtl/gpio.v | 86,337,678 | gpio.v | v | 55 | 94 | [] | [] | [] | [(17, 62)] | null | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/gpio.v:7: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,964 | module | module gpio (
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata,
output reg [31:0] gpio
);
reg [7:0] q;
reg rdy;
always @(posedge clk) begin
if (!resetn) begin
rdy <= 0;
q <= 0;
gpio <= 0;
end else if (mem_valid & enable) begin
if (mem_wstrb[0])
gpio[7:0] <= mem_wdata[7:0];
if (mem_wstrb[1])
gpio[15:8] <= mem_wdata[15:8];
if (mem_wstrb[2])
gpio[23:16] <= mem_wdata[23:16];
if (mem_wstrb[3])
gpio[31:24] <= mem_wdata[31:24];
rdy <= 1;
end else begin
rdy <= 0;
end
q <= gpio;
end
assign mem_rdata = enable ? q : 1'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule | module gpio (
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata,
output reg [31:0] gpio
); |
reg [7:0] q;
reg rdy;
always @(posedge clk) begin
if (!resetn) begin
rdy <= 0;
q <= 0;
gpio <= 0;
end else if (mem_valid & enable) begin
if (mem_wstrb[0])
gpio[7:0] <= mem_wdata[7:0];
if (mem_wstrb[1])
gpio[15:8] <= mem_wdata[15:8];
if (mem_wstrb[2])
gpio[23:16] <= mem_wdata[23:16];
if (mem_wstrb[3])
gpio[31:24] <= mem_wdata[31:24];
rdy <= 1;
end else begin
rdy <= 0;
end
q <= gpio;
end
assign mem_rdata = enable ? q : 1'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule | 9 |
138,899 | data/full_repos/permissive/86337678/rtl/rom.v | 86,337,678 | rom.v | v | 36 | 70 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/rom.v:4: Cannot find include file: timescale.vh\n`include "timescale.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/timescale.vh.sv\n timescale.vh\n timescale.vh.v\n timescale.vh.sv\n obj_dir/timescale.vh\n obj_dir/timescale.vh.v\n obj_dir/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,969 | module | module rom
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=8)
(
input [(ADDR_WIDTH-1):0] addr,
input clk,
output reg [(DATA_WIDTH-1):0] q
);
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
initial
begin
$readmemh("rom.hex", rom);
end
always @ (posedge clk)
begin
q <= rom[addr];
end
endmodule | module rom
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=8)
(
input [(ADDR_WIDTH-1):0] addr,
input clk,
output reg [(DATA_WIDTH-1):0] q
); |
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
initial
begin
$readmemh("rom.hex", rom);
end
always @ (posedge clk)
begin
q <= rom[addr];
end
endmodule | 9 |
138,901 | data/full_repos/permissive/86337678/rtl/spi.v | 86,337,678 | spi.v | v | 82 | 89 | [] | [] | [] | [(3, 81)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/86337678/rtl/spi.v:54: Bit extraction of var[15:0] requires 4 bit index, not 16 bits.\n : ... In instance spi\n MOSI <= wrData[bitCount];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86337678/rtl/spi.v:61: Bit extraction of var[15:0] requires 4 bit index, not 16 bits.\n : ... In instance spi\n rdData[bitCount] <= MISO;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 303,971 | module | module spi (
input wire clk,
input wire resn,
input wire trig,
output wire done,
output reg [15:0] rdData,
input wire [15:0] wrData,
output reg SCLK,
output reg SS,
output reg MOSI,
input wire MISO
);
reg [3:0] state;
reg [15:0] bitCount;
reg [15:0] clkCounter;
always @ (posedge clk) begin
clkCounter = clkCounter + 1;
if (clkCounter == 33) begin
SCLK <= !SCLK;
end
end
always @ (SCLK) begin
if (!resn) begin
SS <= 1;
MOSI <= 0;
state <= 0;
bitCount <= 0;
end else begin
case (state)
0: begin
if (trig) begin
if (SCLK == 0) begin
SS <= 0;
state <= 1;
bitCount <= 15;
end
end
end
1: begin
if (SCLK == 0) begin
MOSI <= wrData[bitCount];
bitCount <= bitCount - 1;
if (bitCount == 0) begin
state <= 2;
end
end else begin
rdData[bitCount] <= MISO;
end
end
2: begin
if (SCLK == 1) begin
SS <= 1;
MOSI <= 0;
state <= 0;
bitCount <= 0;
end
end
default: ;
endcase
end
end
assign done = SS;
endmodule | module spi (
input wire clk,
input wire resn,
input wire trig,
output wire done,
output reg [15:0] rdData,
input wire [15:0] wrData,
output reg SCLK,
output reg SS,
output reg MOSI,
input wire MISO
); |
reg [3:0] state;
reg [15:0] bitCount;
reg [15:0] clkCounter;
always @ (posedge clk) begin
clkCounter = clkCounter + 1;
if (clkCounter == 33) begin
SCLK <= !SCLK;
end
end
always @ (SCLK) begin
if (!resn) begin
SS <= 1;
MOSI <= 0;
state <= 0;
bitCount <= 0;
end else begin
case (state)
0: begin
if (trig) begin
if (SCLK == 0) begin
SS <= 0;
state <= 1;
bitCount <= 15;
end
end
end
1: begin
if (SCLK == 0) begin
MOSI <= wrData[bitCount];
bitCount <= bitCount - 1;
if (bitCount == 0) begin
state <= 2;
end
end else begin
rdData[bitCount] <= MISO;
end
end
2: begin
if (SCLK == 1) begin
SS <= 1;
MOSI <= 0;
state <= 0;
bitCount <= 0;
end
end
default: ;
endcase
end
end
assign done = SS;
endmodule | 9 |
138,902 | data/full_repos/permissive/86337678/rtl/timer.v | 86,337,678 | timer.v | v | 41 | 46 | [] | [] | [] | [(14, 48)] | null | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/timer.v:4: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,972 | module | module timer (
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata
);
reg [31:0] count;
reg rdy;
always @(negedge clk) begin
if (!resetn) begin
rdy <= 0;
count <= 0;
end else begin
count <= count + 1;
if (mem_valid & enable) begin
rdy <= 1;
end else begin
rdy <= 0;
end
end
end
assign mem_rdata = enable ? count : 32'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule | module timer (
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata
); |
reg [31:0] count;
reg rdy;
always @(negedge clk) begin
if (!resetn) begin
rdy <= 0;
count <= 0;
end else begin
count <= count + 1;
if (mem_valid & enable) begin
rdy <= 1;
end else begin
rdy <= 0;
end
end
end
assign mem_rdata = enable ? count : 32'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule | 9 |
138,903 | data/full_repos/permissive/86337678/rtl/uartTx.v | 86,337,678 | uartTx.v | v | 177 | 85 | [] | [] | [] | [(20, 35), (38, 75), (78, 182)] | null | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/uartTx.v:9: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh"\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,973 | module | module EdgeDetect (
input io_in,
output io_q,
input clk,
input resetn);
reg old_in;
assign io_q = (io_in && (! old_in));
always @ (posedge clk or negedge resetn) begin
if (!resetn) begin
old_in <= 1'b0;
end else begin
old_in <= io_in;
end
end
endmodule | module EdgeDetect (
input io_in,
output io_q,
input clk,
input resetn); |
reg old_in;
assign io_q = (io_in && (! old_in));
always @ (posedge clk or negedge resetn) begin
if (!resetn) begin
old_in <= 1'b0;
end else begin
old_in <= io_in;
end
end
endmodule | 9 |
138,904 | data/full_repos/permissive/86337678/rtl/uartTx.v | 86,337,678 | uartTx.v | v | 177 | 85 | [] | [] | [] | [(20, 35), (38, 75), (78, 182)] | null | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/uartTx.v:9: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh"\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,973 | module | module BaudRateGenerator (
input wire clk,
input wire resetn,
input wire baudClock,
output wire bitStart,
output wire probe
);
wire baudClockEdge;
reg [3:0] baudClockcount;
EdgeDetect baudClockEdgeDetect(
.clk(clk),
.resetn(resetn),
.io_in(baudClock),
.io_q(baudClockEdge)
);
EdgeDetect bitClockEdgeDetect(
.clk(clk),
.resetn(resetn),
.io_in(baudRateClock),
.io_q(bitStart)
);
assign baudRateClock = baudClockcount[3];
assign probe = baudRateClock;
always @ (posedge clk or negedge resetn) begin
if (!resetn) begin
baudClockcount <= 7;
end else begin
if (baudClockEdge) begin
baudClockcount <= baudClockcount - 1;
end
end
end
endmodule | module BaudRateGenerator (
input wire clk,
input wire resetn,
input wire baudClock,
output wire bitStart,
output wire probe
); |
wire baudClockEdge;
reg [3:0] baudClockcount;
EdgeDetect baudClockEdgeDetect(
.clk(clk),
.resetn(resetn),
.io_in(baudClock),
.io_q(baudClockEdge)
);
EdgeDetect bitClockEdgeDetect(
.clk(clk),
.resetn(resetn),
.io_in(baudRateClock),
.io_q(bitStart)
);
assign baudRateClock = baudClockcount[3];
assign probe = baudRateClock;
always @ (posedge clk or negedge resetn) begin
if (!resetn) begin
baudClockcount <= 7;
end else begin
if (baudClockEdge) begin
baudClockcount <= baudClockcount - 1;
end
end
end
endmodule | 9 |
138,905 | data/full_repos/permissive/86337678/rtl/uartTx.v | 86,337,678 | uartTx.v | v | 177 | 85 | [] | [] | [] | [(20, 35), (38, 75), (78, 182)] | null | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/uartTx.v:9: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh"\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,973 | module | module uartTx (
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata,
input wire baudClock,
output wire probe,
output reg serialOut
);
reg [7:0] shifter;
reg [7:0] buffer;
reg [7:0] state;
reg [3:0] bitCount;
reg bufferEmpty;
reg rdy;
wire baudRateClock;
BaudRateGenerator baudRateGenerator(
.clk(clk),
.resetn(resetn),
.baudClock(baudClock),
.bitStart(bitStart),
.probe(probe)
);
always @ (posedge clk or negedge resetn) begin
if (!resetn) begin
state <= 0;
buffer <= 0;
bufferEmpty <= 1;
shifter <= 0;
serialOut <= 1;
bitCount <= 0;
rdy <= 0;
end else begin
if (mem_valid & enable) begin
if ((mem_wstrb[0] == 1) && (bufferEmpty == 1)) begin
buffer <= mem_wdata[7:0];
bufferEmpty <= 0;
end
rdy <= 1;
end else begin
rdy <= 0;
end
if (bitStart) begin
case (state)
0 : begin
if (bufferEmpty == 0) begin
shifter <= buffer;
bufferEmpty <= 1;
bitCount <= 8;
serialOut <= 0;
state <= 1;
end
end
1 : begin
if (bitCount > 0) begin
serialOut <= shifter[0];
bitCount <= bitCount - 4'd1;
shifter <= shifter >> 1;
end else begin
serialOut <= 1;
state <= 2;
end
end
2 : begin
serialOut <= 1;
state <= 0;
end
default : ;
endcase
end
end
end
assign mem_rdata = enable ? bufferEmpty : 1'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule | module uartTx (
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata,
input wire baudClock,
output wire probe,
output reg serialOut
); |
reg [7:0] shifter;
reg [7:0] buffer;
reg [7:0] state;
reg [3:0] bitCount;
reg bufferEmpty;
reg rdy;
wire baudRateClock;
BaudRateGenerator baudRateGenerator(
.clk(clk),
.resetn(resetn),
.baudClock(baudClock),
.bitStart(bitStart),
.probe(probe)
);
always @ (posedge clk or negedge resetn) begin
if (!resetn) begin
state <= 0;
buffer <= 0;
bufferEmpty <= 1;
shifter <= 0;
serialOut <= 1;
bitCount <= 0;
rdy <= 0;
end else begin
if (mem_valid & enable) begin
if ((mem_wstrb[0] == 1) && (bufferEmpty == 1)) begin
buffer <= mem_wdata[7:0];
bufferEmpty <= 0;
end
rdy <= 1;
end else begin
rdy <= 0;
end
if (bitStart) begin
case (state)
0 : begin
if (bufferEmpty == 0) begin
shifter <= buffer;
bufferEmpty <= 1;
bitCount <= 8;
serialOut <= 0;
state <= 1;
end
end
1 : begin
if (bitCount > 0) begin
serialOut <= shifter[0];
bitCount <= bitCount - 4'd1;
shifter <= shifter >> 1;
end else begin
serialOut <= 1;
state <= 2;
end
end
2 : begin
serialOut <= 1;
state <= 0;
end
default : ;
endcase
end
end
end
assign mem_rdata = enable ? bufferEmpty : 1'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule | 9 |
138,906 | data/full_repos/permissive/86337678/rtl/xoroshiro128plus.v | 86,337,678 | xoroshiro128plus.v | v | 25 | 68 | [] | [] | [] | [(16, 32)] | null | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/xoroshiro128plus.v:6: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,974 | module | module xoroshiro128plus (input resn, input clk, output [63:0] out);
reg [63:0] s0, s1, ss;
wire [63:0] sx = s0 ^ s1;
always @(posedge clk or negedge resn) begin
if (!resn) begin
s0 <= 64'b1;
s1 <= 64'b0;
ss <= 64'b0;
end else begin
s0 <= {s0[08:00], s0[63:09]} ^ sx ^ {sx[49:00], 14'b0};
s1 <= {sx[27:00], sx[63:28]};
ss <= s0 + s1;
end
end
assign out = ss[63:0];
endmodule | module xoroshiro128plus (input resn, input clk, output [63:0] out); |
reg [63:0] s0, s1, ss;
wire [63:0] sx = s0 ^ s1;
always @(posedge clk or negedge resn) begin
if (!resn) begin
s0 <= 64'b1;
s1 <= 64'b0;
ss <= 64'b0;
end else begin
s0 <= {s0[08:00], s0[63:09]} ^ sx ^ {sx[49:00], 14'b0};
s1 <= {sx[27:00], sx[63:28]};
ss <= s0 + s1;
end
end
assign out = ss[63:0];
endmodule | 9 |
138,907 | data/full_repos/permissive/86337678/rtl/xoro_top.v | 86,337,678 | xoro_top.v | v | 448 | 72 | [] | [] | [] | null | line:148: before: "[" | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/xoro_top.v:6: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh"\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,975 | module | module hundredMsTick (
input wire clk,
input wire resetn,
output wire tick
);
reg [31:0] timer;
always @(posedge clk) begin
if (!resetn) begin
timer <= 5000000;
end else begin
if (timer == 0) begin
timer <= 5000000;
end else begin
timer <= timer - 1;
end
end
end
assign tick = (timer == 0);
endmodule | module hundredMsTick (
input wire clk,
input wire resetn,
output wire tick
); |
reg [31:0] timer;
always @(posedge clk) begin
if (!resetn) begin
timer <= 5000000;
end else begin
if (timer == 0) begin
timer <= 5000000;
end else begin
timer <= timer - 1;
end
end
end
assign tick = (timer == 0);
endmodule | 9 |
138,908 | data/full_repos/permissive/86337678/rtl/xoro_top.v | 86,337,678 | xoro_top.v | v | 448 | 72 | [] | [] | [] | null | line:148: before: "[" | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/xoro_top.v:6: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh"\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,975 | module | module gpio_test (
input wire clk,
input wire resetn,
output wire mem_valid,
input wire mem_ready,
output wire mem_instr,
output wire [31:0] mem_addr,
output wire [3:0] mem_wstrb,
output wire [31:0] mem_wdata,
input wire [31:0] mem_rdata,
input wire tick
);
reg [3:0] counter;
always @(posedge clk) begin
if (!resetn) begin
counter <= 0;
end else begin
if (tick) begin
counter <= counter + 4'd1;
end
end
end
assign mem_valid = tick;
assign mem_instr = 1'b0;
assign mem_addr = tick ? 32'hffff0060 : 32'b0;
assign mem_wstrb = tick ? 4'b1 : 4'b0;
assign mem_wdata = tick ? counter : 32'b0;
endmodule | module gpio_test (
input wire clk,
input wire resetn,
output wire mem_valid,
input wire mem_ready,
output wire mem_instr,
output wire [31:0] mem_addr,
output wire [3:0] mem_wstrb,
output wire [31:0] mem_wdata,
input wire [31:0] mem_rdata,
input wire tick
); |
reg [3:0] counter;
always @(posedge clk) begin
if (!resetn) begin
counter <= 0;
end else begin
if (tick) begin
counter <= counter + 4'd1;
end
end
end
assign mem_valid = tick;
assign mem_instr = 1'b0;
assign mem_addr = tick ? 32'hffff0060 : 32'b0;
assign mem_wstrb = tick ? 4'b1 : 4'b0;
assign mem_wdata = tick ? counter : 32'b0;
endmodule | 9 |
138,909 | data/full_repos/permissive/86337678/rtl/xoro_top.v | 86,337,678 | xoro_top.v | v | 448 | 72 | [] | [] | [] | null | line:148: before: "[" | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/xoro_top.v:6: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh"\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,975 | module | module uart_test (
input wire clk,
input wire resetn,
output wire mem_valid,
input wire mem_ready,
output wire mem_instr,
output wire [31:0] mem_addr,
output wire [3:0] mem_wstrb,
output wire [31:0] mem_wdata,
input wire [31:0] mem_rdata,
input wire tick
);
wire [7:0] msg [0:15];
assign msg[0] = "H";
assign msg[1] = "e";
assign msg[2] = "l";
assign msg[3] = "l";
assign msg[4] = "o";
assign msg[5] = " ";
assign msg[6] = "W";
assign msg[7] = "o";
assign msg[8] = "r";
assign msg[9] = "l";
assign msg[10] = "d";
assign msg[11] = "!";
assign msg[12] = 8'h0a;
assign msg[13] = 8'h0d;
assign msg[14] = 8'h00;
assign msg[15] = 8'h00;
reg [3:0] index;
always @(posedge clk) begin
if (!resetn) begin
index <= 0;
end else begin
if (tick) begin
index <= index + 4'd1;
end
end
end
assign mem_valid = tick;
assign mem_instr = 1'b0;
assign mem_addr = tick ? 32'hffff0040 : 32'b0;
assign mem_wstrb = tick ? 4'b1 : 4'b0;
assign mem_wdata = tick ? msg[index] : 32'b0;
endmodule | module uart_test (
input wire clk,
input wire resetn,
output wire mem_valid,
input wire mem_ready,
output wire mem_instr,
output wire [31:0] mem_addr,
output wire [3:0] mem_wstrb,
output wire [31:0] mem_wdata,
input wire [31:0] mem_rdata,
input wire tick
); |
wire [7:0] msg [0:15];
assign msg[0] = "H";
assign msg[1] = "e";
assign msg[2] = "l";
assign msg[3] = "l";
assign msg[4] = "o";
assign msg[5] = " ";
assign msg[6] = "W";
assign msg[7] = "o";
assign msg[8] = "r";
assign msg[9] = "l";
assign msg[10] = "d";
assign msg[11] = "!";
assign msg[12] = 8'h0a;
assign msg[13] = 8'h0d;
assign msg[14] = 8'h00;
assign msg[15] = 8'h00;
reg [3:0] index;
always @(posedge clk) begin
if (!resetn) begin
index <= 0;
end else begin
if (tick) begin
index <= index + 4'd1;
end
end
end
assign mem_valid = tick;
assign mem_instr = 1'b0;
assign mem_addr = tick ? 32'hffff0040 : 32'b0;
assign mem_wstrb = tick ? 4'b1 : 4'b0;
assign mem_wdata = tick ? msg[index] : 32'b0;
endmodule | 9 |
138,910 | data/full_repos/permissive/86337678/rtl/xoro_top.v | 86,337,678 | xoro_top.v | v | 448 | 72 | [] | [] | [] | null | line:148: before: "[" | null | 1: b'%Error: data/full_repos/permissive/86337678/rtl/xoro_top.v:6: Cannot find include file: inc/timescale.vh\n`include "inc/timescale.vh"\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.v\n data/full_repos/permissive/86337678/rtl,data/full_repos/permissive/86337678/inc/timescale.vh.sv\n inc/timescale.vh\n inc/timescale.vh.v\n inc/timescale.vh.sv\n obj_dir/inc/timescale.vh\n obj_dir/inc/timescale.vh.v\n obj_dir/inc/timescale.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 303,975 | module | module xoro_top (input CLOCK_50,
input reset_btn,
output[7:0] LED,
output UART_TX,
input UART_RX,
output GPIO_1_D[33:0]
);
wire trap;
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire mem_la_read;
wire mem_la_write;
wire [31:0] mem_la_addr;
wire [31:0] mem_la_wdata;
wire [3:0] mem_la_wstrb;
wire pcpi_valid;
wire [31:0] pcpi_insn;
wire [31:0] pcpi_rs1;
wire [31:0] pcpi_rs2;
reg pcpi_wr;
reg [31:0] pcpi_rd;
reg pcpi_wait;
reg pcpi_ready;
reg [31:0] irq;
wire [31:0] eoi;
wire trace_valid;
wire [35:0] trace_data;
wire [7:0] enables;
reg resetn = 0;
reg [7:0] resetCount = 0;
wire CLOCK;
wire CLOCK_100;
wire CLOCK_7372800;
wire CLOCK_BAUD_18432000;
wire CLOCK_LOCKED;
always @(posedge CLOCK)
begin
resetCount <= resetCount + 8'd1;
if (resetCount == 100) resetn <= 1;
end
`ifndef SIMULATION
pll_sys pll_sys_inst (
.inclk0 (CLOCK_50),
.c0 (CLOCK_100),
.c1 (CLOCK_7372800),
.c2 (CLOCK_1843200),
.locked (CLOCK_LOCKED)
);
assign CLOCK = CLOCK_100;
`else
assign CLOCK = CLOCK_50;
`endif
wire probe;
assign GPIO_1_D[33] = probe;
assign GPIO_1_D[31] = UART_RX;
gpio gpio (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[6]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_gpio),
.mem_instr(mem_instr),
.mem_addr(mem_addr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_rdata(mem_rdata_gpio),
.gpio(LED)
);
uartTx uartTx (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[4]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_uart),
.mem_instr(mem_instr),
.mem_addr(mem_addr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_rdata(mem_rdata_uart),
.baudClock(CLOCK_1843200),
.probe(probe),
.serialOut(UART_TX)
);
AsyncReceiver uartRx (
.clk(CLOCK),
.reset(!resetn),
.io_enable(enables[2]),
.io_mem_valid(mem_valid),
.io_mem_ready(mem_ready_uartRx),
.io_mem_addr(mem_addr),
.io_mem_rdata(mem_rdata_uartRx),
.io_baudClockX64(CLOCK_7372800),
.io_rx(UART_RX)
);
wire testTick;
wire uartTestTick;
wire gpioTestTick;
hundredMsTick hundredMsTick (
.clk(CLOCK),
.resetn(resetn),
.tick(testTick)
);
Memory mem (
.clk(CLOCK),
.io_enable(enables[7]),
.io_mem_valid(mem_valid),
.io_mem_ready(mem_ready_memory),
.io_mem_instr(mem_instr),
.io_mem_wstrb(mem_wstrb),
.io_mem_wdata(mem_wdata),
.io_mem_addr(mem_addr),
.io_mem_rdata(mem_rdata_memory)
);
prng prng (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[5]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_prng),
.mem_instr(mem_instr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_addr(mem_addr),
.mem_rdata(mem_rdata_prng)
);
timer timer (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[3]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_timer),
.mem_instr(mem_instr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_addr(mem_addr),
.mem_rdata(mem_rdata_timer)
);
wire mem_ready_uartRx;
wire mem_ready_uart;
wire mem_ready_gpio;
wire mem_ready_prng;
wire mem_ready_timer;
wire mem_ready_memory;
wire [31:0] mem_rdata_uartRx;
wire [31:0] mem_rdata_uart;
wire [31:0] mem_rdata_gpio;
wire [31:0] mem_rdata_prng;
wire [31:0] mem_rdata_timer;
wire [31:0] mem_rdata_memory;
busInterface busInterface (
.mem_addr(mem_addr),
.mem_rdata_gpio(mem_rdata_gpio),
.mem_rdata_uart(mem_rdata_uart),
.mem_rdata_uartRx(mem_rdata_uartRx),
.mem_rdata_timer(mem_rdata_timer),
.mem_rdata_prng(mem_rdata_prng),
.mem_rdata_memory(mem_rdata_memory),
.mem_ready_gpio(mem_ready_gpio),
.mem_ready_uart(mem_ready_uart),
.mem_ready_uartRx(mem_ready_uartRx),
.mem_ready_timer(mem_ready_timer),
.mem_ready_prng(mem_ready_prng),
.mem_ready_memory(mem_ready_memory),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.enables(enables)
);
defparam cpu.ENABLE_COUNTERS = 0;
defparam cpu.ENABLE_COUNTERS64 = 0;
defparam cpu.BARREL_SHIFTER = 1;
defparam cpu.TWO_CYCLE_COMPARE = 0;
defparam cpu.TWO_CYCLE_ALU = 0;
defparam cpu.ENABLE_PCPI = 0;
defparam cpu.ENABLE_FAST_MUL = 1;
defparam cpu.ENABLE_DIV = 1;
picorv32 cpu (
.clk(CLOCK),
.resetn(resetn),
.trap(trap),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr(mem_addr),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata),
.mem_la_read(mem_la_read),
.mem_la_write(mem_la_write),
.mem_la_addr(mem_la_addr),
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb),
.pcpi_valid(pcpi_valid),
.pcpi_insn(pcpi_insn),
.pcpi_rs1(pcpi_rs1),
.pcpi_rs2(pcpi_rs2),
.pcpi_wr(pcpi_wr),
.pcpi_rd(pcpi_rd),
.pcpi_wait(pcpi_wait),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule | module xoro_top (input CLOCK_50,
input reset_btn,
output[7:0] LED,
output UART_TX,
input UART_RX,
output GPIO_1_D[33:0]
); |
wire trap;
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire mem_la_read;
wire mem_la_write;
wire [31:0] mem_la_addr;
wire [31:0] mem_la_wdata;
wire [3:0] mem_la_wstrb;
wire pcpi_valid;
wire [31:0] pcpi_insn;
wire [31:0] pcpi_rs1;
wire [31:0] pcpi_rs2;
reg pcpi_wr;
reg [31:0] pcpi_rd;
reg pcpi_wait;
reg pcpi_ready;
reg [31:0] irq;
wire [31:0] eoi;
wire trace_valid;
wire [35:0] trace_data;
wire [7:0] enables;
reg resetn = 0;
reg [7:0] resetCount = 0;
wire CLOCK;
wire CLOCK_100;
wire CLOCK_7372800;
wire CLOCK_BAUD_18432000;
wire CLOCK_LOCKED;
always @(posedge CLOCK)
begin
resetCount <= resetCount + 8'd1;
if (resetCount == 100) resetn <= 1;
end
`ifndef SIMULATION
pll_sys pll_sys_inst (
.inclk0 (CLOCK_50),
.c0 (CLOCK_100),
.c1 (CLOCK_7372800),
.c2 (CLOCK_1843200),
.locked (CLOCK_LOCKED)
);
assign CLOCK = CLOCK_100;
`else
assign CLOCK = CLOCK_50;
`endif
wire probe;
assign GPIO_1_D[33] = probe;
assign GPIO_1_D[31] = UART_RX;
gpio gpio (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[6]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_gpio),
.mem_instr(mem_instr),
.mem_addr(mem_addr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_rdata(mem_rdata_gpio),
.gpio(LED)
);
uartTx uartTx (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[4]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_uart),
.mem_instr(mem_instr),
.mem_addr(mem_addr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_rdata(mem_rdata_uart),
.baudClock(CLOCK_1843200),
.probe(probe),
.serialOut(UART_TX)
);
AsyncReceiver uartRx (
.clk(CLOCK),
.reset(!resetn),
.io_enable(enables[2]),
.io_mem_valid(mem_valid),
.io_mem_ready(mem_ready_uartRx),
.io_mem_addr(mem_addr),
.io_mem_rdata(mem_rdata_uartRx),
.io_baudClockX64(CLOCK_7372800),
.io_rx(UART_RX)
);
wire testTick;
wire uartTestTick;
wire gpioTestTick;
hundredMsTick hundredMsTick (
.clk(CLOCK),
.resetn(resetn),
.tick(testTick)
);
Memory mem (
.clk(CLOCK),
.io_enable(enables[7]),
.io_mem_valid(mem_valid),
.io_mem_ready(mem_ready_memory),
.io_mem_instr(mem_instr),
.io_mem_wstrb(mem_wstrb),
.io_mem_wdata(mem_wdata),
.io_mem_addr(mem_addr),
.io_mem_rdata(mem_rdata_memory)
);
prng prng (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[5]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_prng),
.mem_instr(mem_instr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_addr(mem_addr),
.mem_rdata(mem_rdata_prng)
);
timer timer (
.clk(CLOCK),
.resetn(resetn),
.enable(enables[3]),
.mem_valid(mem_valid),
.mem_ready(mem_ready_timer),
.mem_instr(mem_instr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_addr(mem_addr),
.mem_rdata(mem_rdata_timer)
);
wire mem_ready_uartRx;
wire mem_ready_uart;
wire mem_ready_gpio;
wire mem_ready_prng;
wire mem_ready_timer;
wire mem_ready_memory;
wire [31:0] mem_rdata_uartRx;
wire [31:0] mem_rdata_uart;
wire [31:0] mem_rdata_gpio;
wire [31:0] mem_rdata_prng;
wire [31:0] mem_rdata_timer;
wire [31:0] mem_rdata_memory;
busInterface busInterface (
.mem_addr(mem_addr),
.mem_rdata_gpio(mem_rdata_gpio),
.mem_rdata_uart(mem_rdata_uart),
.mem_rdata_uartRx(mem_rdata_uartRx),
.mem_rdata_timer(mem_rdata_timer),
.mem_rdata_prng(mem_rdata_prng),
.mem_rdata_memory(mem_rdata_memory),
.mem_ready_gpio(mem_ready_gpio),
.mem_ready_uart(mem_ready_uart),
.mem_ready_uartRx(mem_ready_uartRx),
.mem_ready_timer(mem_ready_timer),
.mem_ready_prng(mem_ready_prng),
.mem_ready_memory(mem_ready_memory),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.enables(enables)
);
defparam cpu.ENABLE_COUNTERS = 0;
defparam cpu.ENABLE_COUNTERS64 = 0;
defparam cpu.BARREL_SHIFTER = 1;
defparam cpu.TWO_CYCLE_COMPARE = 0;
defparam cpu.TWO_CYCLE_ALU = 0;
defparam cpu.ENABLE_PCPI = 0;
defparam cpu.ENABLE_FAST_MUL = 1;
defparam cpu.ENABLE_DIV = 1;
picorv32 cpu (
.clk(CLOCK),
.resetn(resetn),
.trap(trap),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr(mem_addr),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata),
.mem_la_read(mem_la_read),
.mem_la_write(mem_la_write),
.mem_la_addr(mem_la_addr),
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb),
.pcpi_valid(pcpi_valid),
.pcpi_insn(pcpi_insn),
.pcpi_rs1(pcpi_rs1),
.pcpi_rs2(pcpi_rs2),
.pcpi_wr(pcpi_wr),
.pcpi_rd(pcpi_rd),
.pcpi_wait(pcpi_wait),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule | 9 |
138,912 | data/full_repos/permissive/86337678/test_bench/uartTx_tb.v | 86,337,678 | uartTx_tb.v | v | 152 | 205 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:6: Cannot find include file: timescale.vh\n`include "timescale.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/test_bench,data/full_repos/permissive/86337678/timescale.vh\n data/full_repos/permissive/86337678/test_bench,data/full_repos/permissive/86337678/timescale.vh.v\n data/full_repos/permissive/86337678/test_bench,data/full_repos/permissive/86337678/timescale.vh.sv\n timescale.vh\n timescale.vh.v\n timescale.vh.sv\n obj_dir/timescale.vh\n obj_dir/timescale.vh.v\n obj_dir/timescale.vh.sv\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:59: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("uartTx_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:60: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:66: Unsupported or unknown PLI call: $monitor\n $monitor("\\t%b, \\t%b, \\t%b, \\t%b, \\t\\t%b, \\t\\t%b, \\t\\t%h, \\t%b\\t\\t%h\\t%h\\t%b", clk, resetn, enable, mem_valid, mem_ready, mem_instr, mem_addr, mem_wstrb, mem_wdata, mem_rdata, serialOut);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #5clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:74: Unsupported: event data types\n event reset_trigger;\n ^~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:75: Unsupported: event data types\n event reset_done_trigger;\n ^~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:79: syntax error, unexpected \'@\'\n @ (reset_trigger);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:82: syntax error, unexpected \'@\'\n @ (negedge clk);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:84: syntax error, unexpected ->\n -> reset_done_trigger;\n ^~\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:93: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:100: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:114: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:120: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:135: syntax error, unexpected ->\n #10 -> reset_trigger;\n ^~\n%Warning-STMTDLY: data/full_repos/permissive/86337678/test_bench/uartTx_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10 -> reset_trigger;\n ^\n%Error: Exiting due to 14 error(s), 2 warning(s)\n' | 303,977 | module | module uart_tb;
reg clk;
reg resetn;
reg enable;
reg mem_valid;
reg mem_instr;
reg [3:0] mem_wstrb;
reg [31:0] mem_wdata;
reg [31:0] mem_addr;
wire mem_ready;
wire [31:0] mem_rdata;
wire serialOut;
reg notEmpty = 1;
defparam uartTx.BAUD_DIVIDER = 10;
uartTx uartTx (
.clk(clk),
.resetn(resetn),
.enable(enable),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_addr(mem_addr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.serialOut(serialOut)
);
initial
begin
clk = 0;
resetn = 0;
enable = 0;
mem_valid = 0;
mem_instr = 0;
mem_wstrb = 0;
mem_wdata = 0;
mem_addr = 0;
end
initial begin
$dumpfile ("uartTx_tb.vcd");
$dumpvars;
end
initial begin
$display("\tclk,\tresetn,\tenable,\tmem_valid,\tmem_ready,\tmem_instr,\tmem_addr,\tmem_wstrb,\tmem_wdata,\tmem_rdata,\tserialOut");
$monitor("\t%b, \t%b, \t%b, \t%b, \t\t%b, \t\t%b, \t\t%h, \t%b\t\t%h\t%h\t%b", clk, resetn, enable, mem_valid, mem_ready, mem_instr, mem_addr, mem_wstrb, mem_wdata, mem_rdata, serialOut);
end
always
#5clk = !clk;
event reset_trigger;
event reset_done_trigger;
initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
resetn = 0;
@ (negedge clk);
resetn = 1;
-> reset_done_trigger;
end
end
task writeBus32;
input [31:0] address;
input [31:0] data;
begin
@(posedge clk);
enable = 1;
mem_valid = 1;
mem_instr = 0;
mem_wstrb = 4'b1111;
mem_wdata = data;
mem_addr = address;
@(posedge clk);
enable = 0;
mem_valid = 0;
mem_instr = 0;
mem_wstrb = 0;
mem_wdata = 0;
mem_addr = 0;
end
endtask
task readBus32;
input [31:0] address;
output [31:0] data;
begin
@(posedge clk);
enable = 1;
mem_valid = 1;
mem_instr = 0;
mem_wstrb = 4'b000;
mem_addr = address;
@(posedge clk);
enable = 0;
mem_valid = 0;
mem_instr = 0;
mem_wstrb = 0;
mem_wdata = 0;
mem_addr = 0;
data = mem_rdata;
end
endtask
reg bufferEmpty = 0;
initial
begin: TEST_CASE
#10 -> reset_trigger;
@ (reset_done_trigger);
$write("reset done\n");
$write("Transmit firts char.\n");
writeBus32(32'hffff0040, 8'haa);
while (1) begin
readBus32(32'hffff0040, bufferEmpty);
while (bufferEmpty != 1) begin
readBus32(32'hffff0040, bufferEmpty);
end
$write("Transmit following char.\n");
writeBus32(32'hffff0040, 8'h55);
end
end
endmodule | module uart_tb; |
reg clk;
reg resetn;
reg enable;
reg mem_valid;
reg mem_instr;
reg [3:0] mem_wstrb;
reg [31:0] mem_wdata;
reg [31:0] mem_addr;
wire mem_ready;
wire [31:0] mem_rdata;
wire serialOut;
reg notEmpty = 1;
defparam uartTx.BAUD_DIVIDER = 10;
uartTx uartTx (
.clk(clk),
.resetn(resetn),
.enable(enable),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_wstrb(mem_wstrb),
.mem_wdata(mem_wdata),
.mem_addr(mem_addr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.serialOut(serialOut)
);
initial
begin
clk = 0;
resetn = 0;
enable = 0;
mem_valid = 0;
mem_instr = 0;
mem_wstrb = 0;
mem_wdata = 0;
mem_addr = 0;
end
initial begin
$dumpfile ("uartTx_tb.vcd");
$dumpvars;
end
initial begin
$display("\tclk,\tresetn,\tenable,\tmem_valid,\tmem_ready,\tmem_instr,\tmem_addr,\tmem_wstrb,\tmem_wdata,\tmem_rdata,\tserialOut");
$monitor("\t%b, \t%b, \t%b, \t%b, \t\t%b, \t\t%b, \t\t%h, \t%b\t\t%h\t%h\t%b", clk, resetn, enable, mem_valid, mem_ready, mem_instr, mem_addr, mem_wstrb, mem_wdata, mem_rdata, serialOut);
end
always
#5clk = !clk;
event reset_trigger;
event reset_done_trigger;
initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
resetn = 0;
@ (negedge clk);
resetn = 1;
-> reset_done_trigger;
end
end
task writeBus32;
input [31:0] address;
input [31:0] data;
begin
@(posedge clk);
enable = 1;
mem_valid = 1;
mem_instr = 0;
mem_wstrb = 4'b1111;
mem_wdata = data;
mem_addr = address;
@(posedge clk);
enable = 0;
mem_valid = 0;
mem_instr = 0;
mem_wstrb = 0;
mem_wdata = 0;
mem_addr = 0;
end
endtask
task readBus32;
input [31:0] address;
output [31:0] data;
begin
@(posedge clk);
enable = 1;
mem_valid = 1;
mem_instr = 0;
mem_wstrb = 4'b000;
mem_addr = address;
@(posedge clk);
enable = 0;
mem_valid = 0;
mem_instr = 0;
mem_wstrb = 0;
mem_wdata = 0;
mem_addr = 0;
data = mem_rdata;
end
endtask
reg bufferEmpty = 0;
initial
begin: TEST_CASE
#10 -> reset_trigger;
@ (reset_done_trigger);
$write("reset done\n");
$write("Transmit firts char.\n");
writeBus32(32'hffff0040, 8'haa);
while (1) begin
readBus32(32'hffff0040, bufferEmpty);
while (bufferEmpty != 1) begin
readBus32(32'hffff0040, bufferEmpty);
end
$write("Transmit following char.\n");
writeBus32(32'hffff0040, 8'h55);
end
end
endmodule | 9 |
138,914 | data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v | 86,337,678 | xoro_top_tb.v | v | 71 | 157 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:4: Cannot find include file: timescale.vh\n`include "timescale.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86337678/test_bench,data/full_repos/permissive/86337678/timescale.vh\n data/full_repos/permissive/86337678/test_bench,data/full_repos/permissive/86337678/timescale.vh.v\n data/full_repos/permissive/86337678/test_bench,data/full_repos/permissive/86337678/timescale.vh.sv\n timescale.vh\n timescale.vh.v\n timescale.vh.sv\n obj_dir/timescale.vh\n obj_dir/timescale.vh.v\n obj_dir/timescale.vh.sv\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("xoro_top_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:44: Unsupported or unknown PLI call: $monitor\n $monitor("\\t%b,\\t%b,\\t%b,\\t%b,\\t%b,\\t\\t%h,\\t\\t%h,\\t\\t%b", clk, resn, leds, rnd, serialOut, xoro_top.mem_addr, xoro_top.mem_rdata, xoro_top.resetn);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:52: Unsupported: event data types\n event reset_trigger;\n ^~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:53: Unsupported: event data types\n event reset_done_trigger;\n ^~~~~\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:57: syntax error, unexpected \'@\'\n @ (reset_trigger);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:60: syntax error, unexpected \'@\'\n @ (negedge clk);\n ^\n%Error: data/full_repos/permissive/86337678/test_bench/xoro_top_tb.v:62: syntax error, unexpected ->\n -> reset_done_trigger;\n ^~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n' | 303,979 | module | module xoro_top_tb;
reg clk;
reg resn;
wire [3:0] leds;
wire [3:0] rnd;
wire serialOut;
xoro_top xoro_top (
.CLOCK_50(clk),
.reset_btn(resn),
.LED(leds),
.RND_OUT(rnd),
.UART_TX(serialOut)
);
initial
begin
clk = 0;
resn = 0;
end
initial begin
$dumpfile ("xoro_top_tb.vcd");
$dumpvars;
end
initial begin
$display("\tclk,\tresn,\tleds,\trnd,\tserialOut,\txoro_top.mem_addr, \txoro_top.mem_rdata,\txoro_top.resetn");
$monitor("\t%b,\t%b,\t%b,\t%b,\t%b,\t\t%h,\t\t%h,\t\t%b", clk, resn, leds, rnd, serialOut, xoro_top.mem_addr, xoro_top.mem_rdata, xoro_top.resetn);
end
always
#5clk = !clk;
event reset_trigger;
event reset_done_trigger;
initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
resn = 0;
@ (negedge clk);
resn = 1;
-> reset_done_trigger;
end
end
endmodule | module xoro_top_tb; |
reg clk;
reg resn;
wire [3:0] leds;
wire [3:0] rnd;
wire serialOut;
xoro_top xoro_top (
.CLOCK_50(clk),
.reset_btn(resn),
.LED(leds),
.RND_OUT(rnd),
.UART_TX(serialOut)
);
initial
begin
clk = 0;
resn = 0;
end
initial begin
$dumpfile ("xoro_top_tb.vcd");
$dumpvars;
end
initial begin
$display("\tclk,\tresn,\tleds,\trnd,\tserialOut,\txoro_top.mem_addr, \txoro_top.mem_rdata,\txoro_top.resetn");
$monitor("\t%b,\t%b,\t%b,\t%b,\t%b,\t\t%h,\t\t%h,\t\t%b", clk, resn, leds, rnd, serialOut, xoro_top.mem_addr, xoro_top.mem_rdata, xoro_top.resetn);
end
always
#5clk = !clk;
event reset_trigger;
event reset_done_trigger;
initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
resn = 0;
@ (negedge clk);
resn = 1;
-> reset_done_trigger;
end
end
endmodule | 9 |
138,915 | data/full_repos/permissive/86415694/ALU.v | 86,415,694 | ALU.v | v | 127 | 82 | [] | [] | [] | [(501, 625)] | null | null | 1: b'%Error: data/full_repos/permissive/86415694/ALU.v:1: Cannot find include file: Global_Macros.v\n`include "Global_Macros.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.sv\n Global_Macros.v\n Global_Macros.v.v\n Global_Macros.v.sv\n obj_dir/Global_Macros.v\n obj_dir/Global_Macros.v.v\n obj_dir/Global_Macros.v.sv\n%Error: data/full_repos/permissive/86415694/ALU.v:32: Define or directive not defined: \'`N\'\n assign status_o[`N] = (operation_i == `ALU_ITF) ? operand1_i[`N] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`N] = (operation_i == `ALU_ITF) ? operand1_i[`N] :\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:32: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`N] = (operation_i == `ALU_ITF) ? operand1_i[`N] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:32: Define or directive not defined: \'`N\'\n assign status_o[`N] = (operation_i == `ALU_ITF) ? operand1_i[`N] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:33: Define or directive not defined: \'`ALU_BRK\'\n (operation_i == `ALU_BRK) ? status_i[`N] : result_reg[7];\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:33: Define or directive not defined: \'`N\'\n (operation_i == `ALU_BRK) ? status_i[`N] : result_reg[7];\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:35: Define or directive not defined: \'`V\'\n assign status_o[`V] = (operation_i == `ALU_ITF) ? operand1_i[`V] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`V] = (operation_i == `ALU_ITF) ? operand1_i[`V] :\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:35: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`V] = (operation_i == `ALU_ITF) ? operand1_i[`V] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:35: Define or directive not defined: \'`V\'\n assign status_o[`V] = (operation_i == `ALU_ITF) ? operand1_i[`V] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:36: Define or directive not defined: \'`ALU_CLV\'\n (operation_i == `ALU_CLV) ? 1\'h0 : vflag_reg;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:38: Define or directive not defined: \'`P\'\n assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:38: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:38: Define or directive not defined: \'`P\'\n assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:38: Define or directive not defined: \'`P\'\n assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:40: Define or directive not defined: \'`B\'\n assign status_o[`B] = (operation_i == `ALU_ITF) ? operand1_i[`B] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`B] = (operation_i == `ALU_ITF) ? operand1_i[`B] :\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:40: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`B] = (operation_i == `ALU_ITF) ? operand1_i[`B] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:40: Define or directive not defined: \'`B\'\n assign status_o[`B] = (operation_i == `ALU_ITF) ? operand1_i[`B] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:41: Define or directive not defined: \'`ALU_BRK\'\n (operation_i == `ALU_BRK) ? 1\'h1 : status_i[`B];\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:41: Define or directive not defined: \'`B\'\n (operation_i == `ALU_BRK) ? 1\'h1 : status_i[`B];\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:43: Define or directive not defined: \'`D\'\n assign status_o[`D] = (operation_i == `ALU_ITF) ? operand1_i[`D] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`D] = (operation_i == `ALU_ITF) ? operand1_i[`D] :\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:43: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`D] = (operation_i == `ALU_ITF) ? operand1_i[`D] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:43: Define or directive not defined: \'`D\'\n assign status_o[`D] = (operation_i == `ALU_ITF) ? operand1_i[`D] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:44: Define or directive not defined: \'`ALU_CLD\'\n (operation_i == `ALU_CLD) ? 1\'h0 : \n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:45: Define or directive not defined: \'`ALU_SED\'\n (operation_i == `ALU_SED) ? 1\'h1 : status_i[`D];\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:45: Define or directive not defined: \'`D\'\n (operation_i == `ALU_SED) ? 1\'h1 : status_i[`D];\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:47: Define or directive not defined: \'`I\'\n assign status_o[`I] = (operation_i == `ALU_ITF) ? operand1_i[`I] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`I] = (operation_i == `ALU_ITF) ? operand1_i[`I] :\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:47: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`I] = (operation_i == `ALU_ITF) ? operand1_i[`I] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:47: Define or directive not defined: \'`I\'\n assign status_o[`I] = (operation_i == `ALU_ITF) ? operand1_i[`I] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:48: Define or directive not defined: \'`ALU_CLI\'\n (operation_i == `ALU_CLI) ? 1\'h0 :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:49: Define or directive not defined: \'`ALU_SEI\'\n (operation_i == `ALU_SEI) ? 1\'h1 :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:50: Define or directive not defined: \'`ALU_BRK\'\n (operation_i == `ALU_BRK) ? 1\'h1 : status_i[`I];\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:50: Define or directive not defined: \'`I\'\n (operation_i == `ALU_BRK) ? 1\'h1 : status_i[`I];\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:52: Define or directive not defined: \'`Z\'\n assign status_o[`Z] = (operation_i == `ALU_ITF) ? operand1_i[`Z] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`Z] = (operation_i == `ALU_ITF) ? operand1_i[`Z] :\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:52: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`Z] = (operation_i == `ALU_ITF) ? operand1_i[`Z] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:52: Define or directive not defined: \'`Z\'\n assign status_o[`Z] = (operation_i == `ALU_ITF) ? operand1_i[`Z] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:53: Define or directive not defined: \'`ALU_BRK\'\n (operation_i == `ALU_BRK) ? status_i[`Z] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:53: Define or directive not defined: \'`Z\'\n (operation_i == `ALU_BRK) ? status_i[`Z] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:56: Define or directive not defined: \'`C\'\n assign status_o[`C] = (operation_i == `ALU_ITF) ? operand1_i[`C] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign status_o[`C] = (operation_i == `ALU_ITF) ? operand1_i[`C] :\n ^\n%Error: data/full_repos/permissive/86415694/ALU.v:56: Define or directive not defined: \'`ALU_ITF\'\n assign status_o[`C] = (operation_i == `ALU_ITF) ? operand1_i[`C] :\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:56: Define or directive not defined: \'`C\'\n assign status_o[`C] = (operation_i == `ALU_ITF) ? operand1_i[`C] :\n ^~\n%Error: data/full_repos/permissive/86415694/ALU.v:57: Define or directive not defined: \'`ALU_CLC\'\n (operation_i == `ALU_CLC) ? 1\'h0 : \n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/ALU.v:58: Define or directive not defined: \'`ALU_SEC\'\n (operation_i == `ALU_SEC) ? 1\'h1 : cflag_reg;\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 303,980 | module | module ALU(
operation_i,
status_i,
operand1_i,
operand2_i,
status_o,
result_o
);
input wire [4:0] operation_i;
input wire [7:0] status_i;
input wire [15:0] operand1_i;
input wire [15:0] operand2_i;
output wire [7:0] status_o;
output wire [15:0] result_o;
reg [15:0] result_reg;
reg cflag_reg;
reg vflag_reg;
assign result_o = result_reg;
assign status_o[`N] = (operation_i == `ALU_ITF) ? operand1_i[`N] :
(operation_i == `ALU_BRK) ? status_i[`N] : result_reg[7];
assign status_o[`V] = (operation_i == `ALU_ITF) ? operand1_i[`V] :
(operation_i == `ALU_CLV) ? 1'h0 : vflag_reg;
assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];
assign status_o[`B] = (operation_i == `ALU_ITF) ? operand1_i[`B] :
(operation_i == `ALU_BRK) ? 1'h1 : status_i[`B];
assign status_o[`D] = (operation_i == `ALU_ITF) ? operand1_i[`D] :
(operation_i == `ALU_CLD) ? 1'h0 :
(operation_i == `ALU_SED) ? 1'h1 : status_i[`D];
assign status_o[`I] = (operation_i == `ALU_ITF) ? operand1_i[`I] :
(operation_i == `ALU_CLI) ? 1'h0 :
(operation_i == `ALU_SEI) ? 1'h1 :
(operation_i == `ALU_BRK) ? 1'h1 : status_i[`I];
assign status_o[`Z] = (operation_i == `ALU_ITF) ? operand1_i[`Z] :
(operation_i == `ALU_BRK) ? status_i[`Z] :
(result_reg[7:0] == 8'h0) ? 1'h1 : 1'h0;
assign status_o[`C] = (operation_i == `ALU_ITF) ? operand1_i[`C] :
(operation_i == `ALU_CLC) ? 1'h0 :
(operation_i == `ALU_SEC) ? 1'h1 : cflag_reg;
always @(operand1_i or operand2_i or operation_i or status_i[`C])
begin
case(operation_i)
`ALU_ADD : begin
result_reg = operand1_i + operand2_i + status_i[`C];
cflag_reg = result_reg[8];
vflag_reg = ( operand1_i[7] && operand2_i[7] && ~result_reg[7])||
(~operand1_i[7] && ~operand2_i[7] && result_reg[7]);
end
`ALU_AND : begin
result_reg = operand1_i & operand2_i;
end
`ALU_BRK : begin
result_reg = operand1_i;
end
`ALU_CMP : begin
result_reg = operand2_i - operand1_i;
cflag_reg = operand2_i < operand1_i ? 1'h1 : 1'h0;
end
`ALU_DEC : begin
result_reg = operand1_i - 16'h1;
end
`ALU_INC : begin
result_reg = operand1_i + 16'h1;
end
`ALU_ITO : begin
result_reg = operand1_i;
end
`ALU_ORA : begin
result_reg = operand1_i | operand2_i;
end
`ALU_ROL : begin
result_reg = operand1_i << 1;
result_reg[0] = cflag_reg;
cflag_reg = result_reg[8];
end
`ALU_ROR : begin
result_reg = operand1_i >> 1;
result_reg[7] = cflag_reg;
cflag_reg = operand1_i[0];
end
`ALU_SHL : begin
result_reg = operand1_i << 1;
cflag_reg = operand1_i[7];
end
`ALU_SHR : begin
result_reg = operand1_i >> 1;
cflag_reg = operand1_i[0];
end
`ALU_SUB : begin
result_reg = operand2_i - operand1_i - status_i[`C];
cflag_reg = operand2_i < (operand1_i + status_i[`C]) ? 1'h1 : 1'h0;
vflag_reg = ( operand1_i[7] && operand2_i[7] && ~result_reg[7]) ||
(~operand1_i[7] && ~operand2_i[7] && result_reg[7]);
end
`ALU_XOR : begin
result_reg = operand1_i ^ operand2_i;
end
default : begin
result_reg = result_reg;
cflag_reg = (operation_i == `ALU_CLC) ? 1'h0 :
(operation_i == `ALU_SEC) ? 1'h1 : status_i[`C];
vflag_reg = (operation_i == `ALU_CLV) ? 1'h0 : status_i[`V];
end
endcase
end
endmodule | module ALU(
operation_i,
status_i,
operand1_i,
operand2_i,
status_o,
result_o
); |
input wire [4:0] operation_i;
input wire [7:0] status_i;
input wire [15:0] operand1_i;
input wire [15:0] operand2_i;
output wire [7:0] status_o;
output wire [15:0] result_o;
reg [15:0] result_reg;
reg cflag_reg;
reg vflag_reg;
assign result_o = result_reg;
assign status_o[`N] = (operation_i == `ALU_ITF) ? operand1_i[`N] :
(operation_i == `ALU_BRK) ? status_i[`N] : result_reg[7];
assign status_o[`V] = (operation_i == `ALU_ITF) ? operand1_i[`V] :
(operation_i == `ALU_CLV) ? 1'h0 : vflag_reg;
assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];
assign status_o[`B] = (operation_i == `ALU_ITF) ? operand1_i[`B] :
(operation_i == `ALU_BRK) ? 1'h1 : status_i[`B];
assign status_o[`D] = (operation_i == `ALU_ITF) ? operand1_i[`D] :
(operation_i == `ALU_CLD) ? 1'h0 :
(operation_i == `ALU_SED) ? 1'h1 : status_i[`D];
assign status_o[`I] = (operation_i == `ALU_ITF) ? operand1_i[`I] :
(operation_i == `ALU_CLI) ? 1'h0 :
(operation_i == `ALU_SEI) ? 1'h1 :
(operation_i == `ALU_BRK) ? 1'h1 : status_i[`I];
assign status_o[`Z] = (operation_i == `ALU_ITF) ? operand1_i[`Z] :
(operation_i == `ALU_BRK) ? status_i[`Z] :
(result_reg[7:0] == 8'h0) ? 1'h1 : 1'h0;
assign status_o[`C] = (operation_i == `ALU_ITF) ? operand1_i[`C] :
(operation_i == `ALU_CLC) ? 1'h0 :
(operation_i == `ALU_SEC) ? 1'h1 : cflag_reg;
always @(operand1_i or operand2_i or operation_i or status_i[`C])
begin
case(operation_i)
`ALU_ADD : begin
result_reg = operand1_i + operand2_i + status_i[`C];
cflag_reg = result_reg[8];
vflag_reg = ( operand1_i[7] && operand2_i[7] && ~result_reg[7])||
(~operand1_i[7] && ~operand2_i[7] && result_reg[7]);
end
`ALU_AND : begin
result_reg = operand1_i & operand2_i;
end
`ALU_BRK : begin
result_reg = operand1_i;
end
`ALU_CMP : begin
result_reg = operand2_i - operand1_i;
cflag_reg = operand2_i < operand1_i ? 1'h1 : 1'h0;
end
`ALU_DEC : begin
result_reg = operand1_i - 16'h1;
end
`ALU_INC : begin
result_reg = operand1_i + 16'h1;
end
`ALU_ITO : begin
result_reg = operand1_i;
end
`ALU_ORA : begin
result_reg = operand1_i | operand2_i;
end
`ALU_ROL : begin
result_reg = operand1_i << 1;
result_reg[0] = cflag_reg;
cflag_reg = result_reg[8];
end
`ALU_ROR : begin
result_reg = operand1_i >> 1;
result_reg[7] = cflag_reg;
cflag_reg = operand1_i[0];
end
`ALU_SHL : begin
result_reg = operand1_i << 1;
cflag_reg = operand1_i[7];
end
`ALU_SHR : begin
result_reg = operand1_i >> 1;
cflag_reg = operand1_i[0];
end
`ALU_SUB : begin
result_reg = operand2_i - operand1_i - status_i[`C];
cflag_reg = operand2_i < (operand1_i + status_i[`C]) ? 1'h1 : 1'h0;
vflag_reg = ( operand1_i[7] && operand2_i[7] && ~result_reg[7]) ||
(~operand1_i[7] && ~operand2_i[7] && result_reg[7]);
end
`ALU_XOR : begin
result_reg = operand1_i ^ operand2_i;
end
default : begin
result_reg = result_reg;
cflag_reg = (operation_i == `ALU_CLC) ? 1'h0 :
(operation_i == `ALU_SEC) ? 1'h1 : status_i[`C];
vflag_reg = (operation_i == `ALU_CLV) ? 1'h0 : status_i[`V];
end
endcase
end
endmodule | 4 |
138,918 | data/full_repos/permissive/86415694/Effective_Address.v | 86,415,694 | Effective_Address.v | v | 874 | 133 | [] | [] | [] | [(512, 1372)] | null | null | 1: b'%Error: data/full_repos/permissive/86415694/Effective_Address.v:1: Cannot find include file: Global_Macros.v\n`include "Global_Macros.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.sv\n Global_Macros.v\n Global_Macros.v.v\n Global_Macros.v.sv\n obj_dir/Global_Macros.v\n obj_dir/Global_Macros.v.v\n obj_dir/Global_Macros.v.sv\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:52: Define or directive not defined: \'`decode_cntrl_o_width\'\n input wire [`decode_cntrl_o_width - 1:0] control_signal_i;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:59: Define or directive not defined: \'`effadr_cntrl_o_width\'\n output reg [`effadr_cntrl_o_width - 1:0] control_signal_o;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:80: Define or directive not defined: \'`effadr_cntrl_o_width\'\n reg [`effadr_cntrl_o_width - 1:0] control_signal_reg;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:95: Define or directive not defined: \'`cntrl_ea_adr_src\'\n assign final_mem_ea_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset1_o :\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:95: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n assign final_mem_ea_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset1_o :\n ^~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:95: Define or directive not defined: \'`EA_ADR\'\n assign final_mem_ea_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset1_o :\n ^~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:96: Define or directive not defined: \'`cntrl_ea_stack_op\'\n (`cntrl_ea_stack_op == `STACK_OP_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:96: Define or directive not defined: \'`STACK_OP_POP\'\n (`cntrl_ea_stack_op == `STACK_OP_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:97: Define or directive not defined: \'`cntrl_ea_stack_op\'\n (`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:97: Define or directive not defined: \'`STACK_OP_PC_POP\'\n (`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:98: Define or directive not defined: \'`cntrl_ea_stack_op\'\n (`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8\'h1, sp_reg + 8\'h1} : {8\'h1, sp_reg};\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:98: Define or directive not defined: \'`STACK_OP_P_PC_POP\'\n (`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8\'h1, sp_reg + 8\'h1} : {8\'h1, sp_reg};\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:99: Define or directive not defined: \'`cntrl_ea_adr_src\'\n assign final_eff_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset2_o :\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:99: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n assign final_eff_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset2_o :\n ^~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:99: Define or directive not defined: \'`EA_ADR\'\n assign final_eff_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset2_o :\n ^~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:100: Define or directive not defined: \'`cntrl_ea_stack_op\'\n (`cntrl_ea_stack_op == `STACK_OP_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:100: Define or directive not defined: \'`STACK_OP_POP\'\n (`cntrl_ea_stack_op == `STACK_OP_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:101: Define or directive not defined: \'`cntrl_ea_stack_op\'\n (`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:101: Define or directive not defined: \'`STACK_OP_PC_POP\'\n (`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8\'h1, sp_reg + 8\'h1} : \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:102: Define or directive not defined: \'`cntrl_ea_stack_op\'\n (`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8\'h1, sp_reg + 8\'h3} : {8\'h1, sp_reg};\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:102: Define or directive not defined: \'`STACK_OP_P_PC_POP\'\n (`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8\'h1, sp_reg + 8\'h3} : {8\'h1, sp_reg};\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:109: Define or directive not defined: \'`cntrl_ea_off_1\'\n MUX4x1 mux4x1_1(mux4x1_1_o, `cntrl_ea_off_1, forwd_i[7:0], x_i, y_i, 8\'h0);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:110: Define or directive not defined: \'`cntrl_ea_off_2\'\n MUX4x1 mux4x1_2(mux4x1_2_o, `cntrl_ea_off_2, forwd_i[7:0], x_i, y_i, 8\'h0);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:113: Define or directive not defined: \'`cntrl_ea_adr_mod\'\n MUX2x1 #(16) mux2x1_1(mux2x1_1_o, `cntrl_ea_adr_mod, offset1_o, final_mem_ea_dat);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:120: Define or directive not defined: \'`S_P_START\'\n : ... Suggested alternative: \'`SV_COV_START\'\n sp_reg <= `S_P_START;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:120: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n sp_reg <= `S_P_START;\n ^\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:140: Define or directive not defined: \'`cntrl_ea_stack_op\'\n case(`cntrl_ea_stack_op)\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:140: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n case(`cntrl_ea_stack_op)\n ^\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:141: Define or directive not defined: \'`STACK_OP_NONE\'\n `STACK_OP_NONE : sp_reg <= sp_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:142: Define or directive not defined: \'`STACK_OP_PUSH\'\n `STACK_OP_PUSH : sp_reg <= sp_reg - 8\'h1;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:143: Define or directive not defined: \'`STACK_OP_PC_PUSH\'\n `STACK_OP_PC_PUSH : sp_reg <= sp_reg - 8\'h2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:144: Define or directive not defined: \'`STACK_OP_P_PC_PUSH\'\n `STACK_OP_P_PC_PUSH : sp_reg <= sp_reg - 8\'h3;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:145: Define or directive not defined: \'`STACK_OP_POP\'\n `STACK_OP_POP : sp_reg <= sp_reg + 8\'h1;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:146: Define or directive not defined: \'`STACK_OP_PC_POP\'\n `STACK_OP_PC_POP : sp_reg <= sp_reg + 8\'h2;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:147: Define or directive not defined: \'`STACK_OP_P_PC_POP\'\n `STACK_OP_P_PC_POP : sp_reg <= sp_reg + 8\'h3;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:148: Define or directive not defined: \'`STACK_OP_X\'\n `STACK_OP_X : sp_reg <= x_i;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:149: Define or directive not defined: \'`STACK_OP_FORWD\'\n `STACK_OP_FORWD : sp_reg <= forwd_i[7:0];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:159: Define or directive not defined: \'`effadr_cntrl_o_width\'\n control_signal_o <= `effadr_cntrl_o_width\'h0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:160: Define or directive not defined: \'`P_C_START\'\n : ... Suggested alternative: \'`SV_COV_START\'\n jmp_adr_o <= `P_C_START;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:160: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n jmp_adr_o <= `P_C_START;\n ^\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:169: syntax error, unexpected else\n else if(gbl_stl_i == 1\'h1 || mem_stl_i == 1\'h1)\n ^~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:180: Define or directive not defined: \'`effadr_cntrl_o_width\'\n control_signal_o <= `effadr_cntrl_o_width\'h0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:186: Define or directive not defined: \'`effadr_cntrl_o_width\'\n control_signal_o <= `effadr_cntrl_o_width\'h0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:192: Define or directive not defined: \'`cntrl_wb_mem_wr\'\n if(`cntrl_wb_mem_wr == 1\'h1)\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:197: Define or directive not defined: \'`cntrl_wb_mem_wr_cnt\'\n history_cnt_wr_byt[1:0] <= `cntrl_wb_mem_wr_cnt;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:198: Define or directive not defined: \'`cntrl_ea_stack_op\'\n history_dst_wr_adr[15:0] <= (`cntrl_ea_stack_op == `STACK_OP_PUSH) ? {8\'h1, sp_reg} : \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:198: Define or directive not defined: \'`STACK_OP_PUSH\'\n history_dst_wr_adr[15:0] <= (`cntrl_ea_stack_op == `STACK_OP_PUSH) ? {8\'h1, sp_reg} : \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:199: Define or directive not defined: \'`cntrl_ea_stack_op\'\n (`cntrl_ea_stack_op == `STACK_OP_PC_PUSH) ? {8\'h1, sp_reg - 8\'h1} : \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86415694/Effective_Address.v:199: Define or directive not defined: \'`STACK_OP_PC_PUSH\'\n (`cntrl_ea_stack_op == `STACK_OP_PC_PUSH) ? {8\'h1, sp_reg - 8\'h1} : \n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 303,985 | module | module Effective_Address(
clk_i,
rst_i,
gbl_stl_i,
wait_to_fill_pipe_i,
wait_sig_i,
x_i,
y_i,
pc_i,
forwd_i,
operand_i,
control_signal_i,
mem_stl_i,
mem_ea_dat_i,
refill_pipe_o,
wait_sig_o,
control_signal_o,
dat_o,
jmp_adr_o,
eff_adr_o,
mem_ea_adr_o
`ifdef DEBUG
,debug_o
`endif
);
input wire clk_i;
input wire rst_i;
input wire gbl_stl_i;
input wire wait_to_fill_pipe_i;
input wire [1:0] wait_sig_i;
input wire [7:0] x_i;
input wire [7:0] y_i;
input wire [15:0] pc_i;
input wire [15:0] forwd_i;
input wire [15:0] operand_i;
input wire [`decode_cntrl_o_width - 1:0] control_signal_i;
input wire mem_stl_i;
input wire [15:0] mem_ea_dat_i;
output reg refill_pipe_o;
output reg [1:0] wait_sig_o;
output reg [`effadr_cntrl_o_width - 1:0] control_signal_o;
output reg [15:0] dat_o;
output reg [15:0] jmp_adr_o;
output reg [15:0] eff_adr_o;
output wire [15:0] mem_ea_adr_o;
`ifdef DEBUG
output wire [`EAD_DBG_WIDTH - 1:0] debug_o;
`endif
wire [7:0] mux4x1_1_o;
wire [7:0] mux4x1_2_o;
wire [15:0] mux2x1_1_o;
wire [15:0] offset1_o;
wire [15:0] offset2_o;
wire [15:0] final_mem_ea_adr;
wire [15:0] final_mem_ea_dat;
wire [15:0] final_eff_adr;
reg [`effadr_cntrl_o_width - 1:0] control_signal_reg;
reg [1:0] wait_tmp;
reg [1:0] mem_ea_dat_lo_need_forwd;
reg [1:0] mem_ea_dat_hi_need_forwd;
reg [5:0] history_cnt_wr_byt;
reg [7:0] sp_reg;
reg [50:0] history_dst_wr_adr;
assign mem_ea_adr_o = final_mem_ea_adr;
assign offset1_o = operand_i + {8'h0, mux4x1_1_o};
assign offset2_o = mux2x1_1_o + {8'h0, mux4x1_2_o};
assign final_mem_ea_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset1_o :
(`cntrl_ea_stack_op == `STACK_OP_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8'h1, sp_reg + 8'h1} : {8'h1, sp_reg};
assign final_eff_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset2_o :
(`cntrl_ea_stack_op == `STACK_OP_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8'h1, sp_reg + 8'h3} : {8'h1, sp_reg};
`ifdef DEBUG
assign debug_o = mem_ea_adr_o;
`endif
MUX4x1 mux4x1_1(mux4x1_1_o, `cntrl_ea_off_1, forwd_i[7:0], x_i, y_i, 8'h0);
MUX4x1 mux4x1_2(mux4x1_2_o, `cntrl_ea_off_2, forwd_i[7:0], x_i, y_i, 8'h0);
MUX4x1 mux4x1_dat_lo(final_mem_ea_dat[07:00], mem_ea_dat_lo_need_forwd, mem_ea_dat_i[07:00], forwd_i[7:0], forwd_i[15:08], 8'h0);
MUX4x1 mux4x1_dat_hi(final_mem_ea_dat[15:08], mem_ea_dat_hi_need_forwd, mem_ea_dat_i[15:08], forwd_i[7:0], forwd_i[15:08], 8'h0);
MUX2x1 #(16) mux2x1_1(mux2x1_1_o, `cntrl_ea_adr_mod, offset1_o, final_mem_ea_dat);
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
sp_reg <= `S_P_START;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
end
else if(wait_sig_o != 2'h0)
begin
end
else if(wait_sig_i - 2'h1 != 2'h3)
begin
end
else
begin
case(`cntrl_ea_stack_op)
`STACK_OP_NONE : sp_reg <= sp_reg;
`STACK_OP_PUSH : sp_reg <= sp_reg - 8'h1;
`STACK_OP_PC_PUSH : sp_reg <= sp_reg - 8'h2;
`STACK_OP_P_PC_PUSH : sp_reg <= sp_reg - 8'h3;
`STACK_OP_POP : sp_reg <= sp_reg + 8'h1;
`STACK_OP_PC_POP : sp_reg <= sp_reg + 8'h2;
`STACK_OP_P_PC_POP : sp_reg <= sp_reg + 8'h3;
`STACK_OP_X : sp_reg <= x_i;
`STACK_OP_FORWD : sp_reg <= forwd_i[7:0];
default : sp_reg <= sp_reg;
endcase
end
end
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
control_signal_o <= `effadr_cntrl_o_width'h0;
jmp_adr_o <= `P_C_START;
refill_pipe_o <= 1'h0;
mem_ea_dat_lo_need_forwd <= 1'h0;
mem_ea_dat_hi_need_forwd <= 1'h0;
`history_vld_1 <= 1'h0;
`history_vld_2 <= 1'h0;
`history_vld_3 <= 1'h0;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
refill_pipe_o <= 1'h0;
end
else if(wait_sig_o != 2'h0)
begin
wait_tmp <= wait_sig_o - 2'h1;
control_signal_o <= `effadr_cntrl_o_width'h0;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
end
else if(wait_sig_i - 2'h1 != 2'h3)
begin
control_signal_o <= `effadr_cntrl_o_width'h0;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
end
else
begin
if(`cntrl_wb_mem_wr == 1'h1)
begin
history_cnt_wr_byt <= history_cnt_wr_byt << 2'h2;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
`history_cnt_1 <= `cntrl_wb_mem_wr_cnt;
`history_adr_1 <= (`cntrl_ea_stack_op == `STACK_OP_PUSH) ? {8'h1, sp_reg} :
(`cntrl_ea_stack_op == `STACK_OP_PC_PUSH) ? {8'h1, sp_reg - 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_PUSH) ? {8'h1, sp_reg - 8'h2} : final_eff_adr;
`history_vld_1 <= 1'h1;
end
else
begin
history_cnt_wr_byt <= history_cnt_wr_byt << 2'h2;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
end
dat_o <= (`cntrl_ea_stack_op == `STACK_OP_PC_PUSH || `cntrl_ea_stack_op == `STACK_OP_P_PC_PUSH) ? pc_i + 16'h2 : operand_i;
jmp_adr_o <= (`cntrl_ea_stack_op == `STACK_OP_PC_POP || `cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? mem_ea_dat_i : final_eff_adr;
eff_adr_o <= (`cntrl_ea_stack_op == `STACK_OP_PUSH) ? {8'h1, sp_reg} :
(`cntrl_ea_stack_op == `STACK_OP_PC_PUSH) ? {8'h1, sp_reg - 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_PUSH) ? {8'h1, sp_reg - 8'h2} : final_eff_adr;
refill_pipe_o <= (`cntrl_ea_pc_jmp == 1'h1) ? 1'h1 : 1'h0;
control_signal_o <= control_signal_reg;
end
end
always @(*)
begin
if(rst_i == 1'h1)
begin
wait_sig_o = 2'h0;
end
else if(wait_sig_o != 2'h0)
begin
wait_sig_o = wait_tmp;
end
else if(`cntrl_ea_adr_mod == `MOD_INDIR)
begin
if(wait_sig_o == 2'h0 && `history_vld_1 == 1'h1)
begin
case(`history_cnt_1)
`ONE : begin
if(
`history_adr_1 + `ONE == final_mem_ea_adr
||
`history_adr_1 + `ONE == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_1 + `ONE == final_mem_ea_adr
||
`history_adr_1 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_1 + `TWO == final_mem_ea_adr
||
`history_adr_1 + `TWO == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_1 + `ONE == final_mem_ea_adr
||
`history_adr_1 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_1 + `TWO == final_mem_ea_adr
||
`history_adr_1 + `TWO == final_mem_ea_adr + 16'h1
||
`history_adr_1 + `THR == final_mem_ea_adr
||
`history_adr_1 + `THR == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_3 == 1'h1)
begin
case(`history_cnt_3)
`ONE : begin
if(
`history_adr_3 + `ONE == final_mem_ea_adr
||
`history_adr_3 + `ONE == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_3 + `ONE == final_mem_ea_adr
||
`history_adr_3 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_3 + `TWO == final_mem_ea_adr
||
`history_adr_3 + `TWO == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`THR : begin
if(
`history_adr_3 + `ONE == final_mem_ea_adr
||
`history_adr_3 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_3 + `TWO == final_mem_ea_adr
||
`history_adr_3 + `TWO == final_mem_ea_adr + 16'h1
||
`history_adr_3 + `THR == final_mem_ea_adr
||
`history_adr_3 + `THR == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_2 == 1'h1)
begin
case(`history_cnt_2)
`ONE : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
||
`history_adr_2 + `ONE == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
||
`history_adr_2 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_2 + `TWO == final_mem_ea_adr
||
`history_adr_2 + `TWO == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
||
`history_adr_2 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_2 + `TWO == final_mem_ea_adr
||
`history_adr_2 + `TWO == final_mem_ea_adr + 16'h1
||
`history_adr_2 + `THR == final_mem_ea_adr
||
`history_adr_2 + `THR == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_1 == 1'h1)
begin
case(`history_cnt_1)
`ONE : begin
if(
`history_adr_1 + `ONE == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_1 + `ONE == mem_ea_dat_i
||
`history_adr_1 + `TWO == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_1 + `ONE == mem_ea_dat_i
||
`history_adr_1 + `TWO == mem_ea_dat_i
||
`history_adr_1 + `THR == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_3 == 1'h1)
begin
case(`history_cnt_3)
`ONE : begin
if(
`history_adr_3 + `ONE == mem_ea_dat_i
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_3 + `ONE == mem_ea_dat_i
||
`history_adr_3 + `TWO == mem_ea_dat_i
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`THR : begin
if(
`history_adr_3 + `ONE == mem_ea_dat_i
||
`history_adr_3 + `TWO == mem_ea_dat_i
||
`history_adr_3 + `THR == mem_ea_dat_i
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_2 == 1'h1)
begin
case(`history_cnt_2)
`ONE : begin
if(
`history_adr_2 + `ONE == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_2 + `ONE == mem_ea_dat_i
||
`history_adr_2 + `TWO == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_2 + `ONE == mem_ea_dat_i
||
`history_adr_2 + `TWO == mem_ea_dat_i
||
`history_adr_2 + `THR == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
end
else
begin
end
if(rst_i == 1'h1)
begin
control_signal_reg = `effadr_cntrl_o_width'h0;
end
else if(`cntrl_rd_src == `TYPE_ADR)
begin
if(wait_sig_o == 2'h0 && `history_vld_2 == 1'h1)
begin
case(`history_cnt_2)
`ONE : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_2 + `ONE == final_eff_adr
||
`history_adr_2 + `TWO == final_eff_adr
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`THR : begin
if(
`history_adr_2 + `ONE == final_eff_adr
||
`history_adr_2 + `TWO == final_eff_adr
||
`history_adr_2 + `THR == final_eff_adr
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_3 == 1'h1)
begin
case(`history_cnt_3)
`ONE : begin
if(
`history_adr_3 + `ONE == final_eff_adr
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_3 + `ONE == final_eff_adr
||
`history_adr_3 + `TWO == final_eff_adr
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_3 + `ONE == final_eff_adr
||
`history_adr_3 + `TWO == final_eff_adr
||
`history_adr_3 + `THR == final_eff_adr
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_1 == 1'h1)
begin
case(`history_cnt_1)
`ONE : begin
if(
`history_adr_1 + `ONE == final_eff_adr
)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
`cntrl_rd_src_reg = `TYPE_FORWD;
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
`TWO : begin
if(
`history_adr_1 + `ONE == final_eff_adr
||
`history_adr_1 + `TWO == final_eff_adr
)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
`cntrl_rd_src_reg = `TYPE_FORWD;
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
`THR : begin
if(
`history_adr_1 + `ONE == final_eff_adr
||
`history_adr_1 + `TWO == final_eff_adr
||
`history_adr_1 + `THR == final_eff_adr
)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
`cntrl_rd_src_reg = `TYPE_FORWD;
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
default : begin
end
endcase
end
else if(wait_sig_o == 2'h0)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
else
begin
end
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
endmodule | module Effective_Address(
clk_i,
rst_i,
gbl_stl_i,
wait_to_fill_pipe_i,
wait_sig_i,
x_i,
y_i,
pc_i,
forwd_i,
operand_i,
control_signal_i,
mem_stl_i,
mem_ea_dat_i,
refill_pipe_o,
wait_sig_o,
control_signal_o,
dat_o,
jmp_adr_o,
eff_adr_o,
mem_ea_adr_o
`ifdef DEBUG
,debug_o
`endif
); |
input wire clk_i;
input wire rst_i;
input wire gbl_stl_i;
input wire wait_to_fill_pipe_i;
input wire [1:0] wait_sig_i;
input wire [7:0] x_i;
input wire [7:0] y_i;
input wire [15:0] pc_i;
input wire [15:0] forwd_i;
input wire [15:0] operand_i;
input wire [`decode_cntrl_o_width - 1:0] control_signal_i;
input wire mem_stl_i;
input wire [15:0] mem_ea_dat_i;
output reg refill_pipe_o;
output reg [1:0] wait_sig_o;
output reg [`effadr_cntrl_o_width - 1:0] control_signal_o;
output reg [15:0] dat_o;
output reg [15:0] jmp_adr_o;
output reg [15:0] eff_adr_o;
output wire [15:0] mem_ea_adr_o;
`ifdef DEBUG
output wire [`EAD_DBG_WIDTH - 1:0] debug_o;
`endif
wire [7:0] mux4x1_1_o;
wire [7:0] mux4x1_2_o;
wire [15:0] mux2x1_1_o;
wire [15:0] offset1_o;
wire [15:0] offset2_o;
wire [15:0] final_mem_ea_adr;
wire [15:0] final_mem_ea_dat;
wire [15:0] final_eff_adr;
reg [`effadr_cntrl_o_width - 1:0] control_signal_reg;
reg [1:0] wait_tmp;
reg [1:0] mem_ea_dat_lo_need_forwd;
reg [1:0] mem_ea_dat_hi_need_forwd;
reg [5:0] history_cnt_wr_byt;
reg [7:0] sp_reg;
reg [50:0] history_dst_wr_adr;
assign mem_ea_adr_o = final_mem_ea_adr;
assign offset1_o = operand_i + {8'h0, mux4x1_1_o};
assign offset2_o = mux2x1_1_o + {8'h0, mux4x1_2_o};
assign final_mem_ea_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset1_o :
(`cntrl_ea_stack_op == `STACK_OP_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8'h1, sp_reg + 8'h1} : {8'h1, sp_reg};
assign final_eff_adr = (`cntrl_ea_adr_src == `EA_ADR) ? offset2_o :
(`cntrl_ea_stack_op == `STACK_OP_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_PC_POP) ? {8'h1, sp_reg + 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? {8'h1, sp_reg + 8'h3} : {8'h1, sp_reg};
`ifdef DEBUG
assign debug_o = mem_ea_adr_o;
`endif
MUX4x1 mux4x1_1(mux4x1_1_o, `cntrl_ea_off_1, forwd_i[7:0], x_i, y_i, 8'h0);
MUX4x1 mux4x1_2(mux4x1_2_o, `cntrl_ea_off_2, forwd_i[7:0], x_i, y_i, 8'h0);
MUX4x1 mux4x1_dat_lo(final_mem_ea_dat[07:00], mem_ea_dat_lo_need_forwd, mem_ea_dat_i[07:00], forwd_i[7:0], forwd_i[15:08], 8'h0);
MUX4x1 mux4x1_dat_hi(final_mem_ea_dat[15:08], mem_ea_dat_hi_need_forwd, mem_ea_dat_i[15:08], forwd_i[7:0], forwd_i[15:08], 8'h0);
MUX2x1 #(16) mux2x1_1(mux2x1_1_o, `cntrl_ea_adr_mod, offset1_o, final_mem_ea_dat);
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
sp_reg <= `S_P_START;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
end
else if(wait_sig_o != 2'h0)
begin
end
else if(wait_sig_i - 2'h1 != 2'h3)
begin
end
else
begin
case(`cntrl_ea_stack_op)
`STACK_OP_NONE : sp_reg <= sp_reg;
`STACK_OP_PUSH : sp_reg <= sp_reg - 8'h1;
`STACK_OP_PC_PUSH : sp_reg <= sp_reg - 8'h2;
`STACK_OP_P_PC_PUSH : sp_reg <= sp_reg - 8'h3;
`STACK_OP_POP : sp_reg <= sp_reg + 8'h1;
`STACK_OP_PC_POP : sp_reg <= sp_reg + 8'h2;
`STACK_OP_P_PC_POP : sp_reg <= sp_reg + 8'h3;
`STACK_OP_X : sp_reg <= x_i;
`STACK_OP_FORWD : sp_reg <= forwd_i[7:0];
default : sp_reg <= sp_reg;
endcase
end
end
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
control_signal_o <= `effadr_cntrl_o_width'h0;
jmp_adr_o <= `P_C_START;
refill_pipe_o <= 1'h0;
mem_ea_dat_lo_need_forwd <= 1'h0;
mem_ea_dat_hi_need_forwd <= 1'h0;
`history_vld_1 <= 1'h0;
`history_vld_2 <= 1'h0;
`history_vld_3 <= 1'h0;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
refill_pipe_o <= 1'h0;
end
else if(wait_sig_o != 2'h0)
begin
wait_tmp <= wait_sig_o - 2'h1;
control_signal_o <= `effadr_cntrl_o_width'h0;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
end
else if(wait_sig_i - 2'h1 != 2'h3)
begin
control_signal_o <= `effadr_cntrl_o_width'h0;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
end
else
begin
if(`cntrl_wb_mem_wr == 1'h1)
begin
history_cnt_wr_byt <= history_cnt_wr_byt << 2'h2;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
`history_cnt_1 <= `cntrl_wb_mem_wr_cnt;
`history_adr_1 <= (`cntrl_ea_stack_op == `STACK_OP_PUSH) ? {8'h1, sp_reg} :
(`cntrl_ea_stack_op == `STACK_OP_PC_PUSH) ? {8'h1, sp_reg - 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_PUSH) ? {8'h1, sp_reg - 8'h2} : final_eff_adr;
`history_vld_1 <= 1'h1;
end
else
begin
history_cnt_wr_byt <= history_cnt_wr_byt << 2'h2;
history_dst_wr_adr <= history_dst_wr_adr << 5'h11;
end
dat_o <= (`cntrl_ea_stack_op == `STACK_OP_PC_PUSH || `cntrl_ea_stack_op == `STACK_OP_P_PC_PUSH) ? pc_i + 16'h2 : operand_i;
jmp_adr_o <= (`cntrl_ea_stack_op == `STACK_OP_PC_POP || `cntrl_ea_stack_op == `STACK_OP_P_PC_POP) ? mem_ea_dat_i : final_eff_adr;
eff_adr_o <= (`cntrl_ea_stack_op == `STACK_OP_PUSH) ? {8'h1, sp_reg} :
(`cntrl_ea_stack_op == `STACK_OP_PC_PUSH) ? {8'h1, sp_reg - 8'h1} :
(`cntrl_ea_stack_op == `STACK_OP_P_PC_PUSH) ? {8'h1, sp_reg - 8'h2} : final_eff_adr;
refill_pipe_o <= (`cntrl_ea_pc_jmp == 1'h1) ? 1'h1 : 1'h0;
control_signal_o <= control_signal_reg;
end
end
always @(*)
begin
if(rst_i == 1'h1)
begin
wait_sig_o = 2'h0;
end
else if(wait_sig_o != 2'h0)
begin
wait_sig_o = wait_tmp;
end
else if(`cntrl_ea_adr_mod == `MOD_INDIR)
begin
if(wait_sig_o == 2'h0 && `history_vld_1 == 1'h1)
begin
case(`history_cnt_1)
`ONE : begin
if(
`history_adr_1 + `ONE == final_mem_ea_adr
||
`history_adr_1 + `ONE == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_1 + `ONE == final_mem_ea_adr
||
`history_adr_1 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_1 + `TWO == final_mem_ea_adr
||
`history_adr_1 + `TWO == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_1 + `ONE == final_mem_ea_adr
||
`history_adr_1 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_1 + `TWO == final_mem_ea_adr
||
`history_adr_1 + `TWO == final_mem_ea_adr + 16'h1
||
`history_adr_1 + `THR == final_mem_ea_adr
||
`history_adr_1 + `THR == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_3 == 1'h1)
begin
case(`history_cnt_3)
`ONE : begin
if(
`history_adr_3 + `ONE == final_mem_ea_adr
||
`history_adr_3 + `ONE == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_3 + `ONE == final_mem_ea_adr
||
`history_adr_3 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_3 + `TWO == final_mem_ea_adr
||
`history_adr_3 + `TWO == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`THR : begin
if(
`history_adr_3 + `ONE == final_mem_ea_adr
||
`history_adr_3 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_3 + `TWO == final_mem_ea_adr
||
`history_adr_3 + `TWO == final_mem_ea_adr + 16'h1
||
`history_adr_3 + `THR == final_mem_ea_adr
||
`history_adr_3 + `THR == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_2 == 1'h1)
begin
case(`history_cnt_2)
`ONE : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
||
`history_adr_2 + `ONE == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
||
`history_adr_2 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_2 + `TWO == final_mem_ea_adr
||
`history_adr_2 + `TWO == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
||
`history_adr_2 + `ONE == final_mem_ea_adr + 16'h1
||
`history_adr_2 + `TWO == final_mem_ea_adr
||
`history_adr_2 + `TWO == final_mem_ea_adr + 16'h1
||
`history_adr_2 + `THR == final_mem_ea_adr
||
`history_adr_2 + `THR == final_mem_ea_adr + 16'h1
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_1 == 1'h1)
begin
case(`history_cnt_1)
`ONE : begin
if(
`history_adr_1 + `ONE == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_1 + `ONE == mem_ea_dat_i
||
`history_adr_1 + `TWO == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_1 + `ONE == mem_ea_dat_i
||
`history_adr_1 + `TWO == mem_ea_dat_i
||
`history_adr_1 + `THR == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_3 == 1'h1)
begin
case(`history_cnt_3)
`ONE : begin
if(
`history_adr_3 + `ONE == mem_ea_dat_i
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_3 + `ONE == mem_ea_dat_i
||
`history_adr_3 + `TWO == mem_ea_dat_i
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`THR : begin
if(
`history_adr_3 + `ONE == mem_ea_dat_i
||
`history_adr_3 + `TWO == mem_ea_dat_i
||
`history_adr_3 + `THR == mem_ea_dat_i
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_2 == 1'h1)
begin
case(`history_cnt_2)
`ONE : begin
if(
`history_adr_2 + `ONE == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_2 + `ONE == mem_ea_dat_i
||
`history_adr_2 + `TWO == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_2 + `ONE == mem_ea_dat_i
||
`history_adr_2 + `TWO == mem_ea_dat_i
||
`history_adr_2 + `THR == mem_ea_dat_i
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
end
else
begin
end
if(rst_i == 1'h1)
begin
control_signal_reg = `effadr_cntrl_o_width'h0;
end
else if(`cntrl_rd_src == `TYPE_ADR)
begin
if(wait_sig_o == 2'h0 && `history_vld_2 == 1'h1)
begin
case(`history_cnt_2)
`ONE : begin
if(
`history_adr_2 + `ONE == final_mem_ea_adr
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_2 + `ONE == final_eff_adr
||
`history_adr_2 + `TWO == final_eff_adr
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
`THR : begin
if(
`history_adr_2 + `ONE == final_eff_adr
||
`history_adr_2 + `TWO == final_eff_adr
||
`history_adr_2 + `THR == final_eff_adr
)
begin
wait_sig_o = 2'h2;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_3 == 1'h1)
begin
case(`history_cnt_3)
`ONE : begin
if(
`history_adr_3 + `ONE == final_eff_adr
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`TWO : begin
if(
`history_adr_3 + `ONE == final_eff_adr
||
`history_adr_3 + `TWO == final_eff_adr
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
`THR : begin
if(
`history_adr_3 + `ONE == final_eff_adr
||
`history_adr_3 + `TWO == final_eff_adr
||
`history_adr_3 + `THR == final_eff_adr
)
begin
wait_sig_o = 2'h1;
end
else
begin
end
end
default : begin
end
endcase
end
else
begin
end
if(wait_sig_o == 2'h0 && `history_vld_1 == 1'h1)
begin
case(`history_cnt_1)
`ONE : begin
if(
`history_adr_1 + `ONE == final_eff_adr
)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
`cntrl_rd_src_reg = `TYPE_FORWD;
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
`TWO : begin
if(
`history_adr_1 + `ONE == final_eff_adr
||
`history_adr_1 + `TWO == final_eff_adr
)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
`cntrl_rd_src_reg = `TYPE_FORWD;
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
`THR : begin
if(
`history_adr_1 + `ONE == final_eff_adr
||
`history_adr_1 + `TWO == final_eff_adr
||
`history_adr_1 + `THR == final_eff_adr
)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
`cntrl_rd_src_reg = `TYPE_FORWD;
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
default : begin
end
endcase
end
else if(wait_sig_o == 2'h0)
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
else
begin
end
end
else
begin
control_signal_reg = control_signal_i[`effadr_cntrl_o_width - 1:0];
end
end
endmodule | 4 |
138,920 | data/full_repos/permissive/86415694/Memory.v | 86,415,694 | Memory.v | v | 137 | 108 | [] | [] | [] | [(506, 635)] | null | null | 1: b'%Error: data/full_repos/permissive/86415694/Memory.v:1: Cannot find include file: Global_Macros.v\n`include "Global_Macros.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.sv\n Global_Macros.v\n Global_Macros.v.v\n Global_Macros.v.sv\n obj_dir/Global_Macros.v\n obj_dir/Global_Macros.v.v\n obj_dir/Global_Macros.v.sv\n%Error: data/full_repos/permissive/86415694/Memory.v:84: Define or directive not defined: \'`LDY_IME\'\n MEM[32814] = `LDY_IME;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32814] = `LDY_IME;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:86: Define or directive not defined: \'`LDA_IME\'\n MEM[32816] = `LDA_IME;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32816] = `LDA_IME;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:88: Define or directive not defined: \'`STA_ABS\'\n MEM[32818] = `STA_ABS;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32818] = `STA_ABS;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:91: Define or directive not defined: \'`LDA_IME\'\n MEM[32821] = `LDA_IME;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32821] = `LDA_IME;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:93: Define or directive not defined: \'`TAX\'\n MEM[32823] = `TAX;\n ^~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:93: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32823] = `TAX;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:94: Define or directive not defined: \'`ADC_ABS\'\n MEM[32824] = `ADC_ABS;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:94: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32824] = `ADC_ABS;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:97: Define or directive not defined: \'`STX_ABS\'\n MEM[32827] = `STX_ABS;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:97: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32827] = `STX_ABS;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:100: Define or directive not defined: \'`DEY\'\n MEM[32830] = `DEY;\n ^~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32830] = `DEY;\n ^\n%Error: data/full_repos/permissive/86415694/Memory.v:101: Define or directive not defined: \'`BNE\'\n MEM[32831] = `BNE;\n ^~~~\n%Error: data/full_repos/permissive/86415694/Memory.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n MEM[32831] = `BNE;\n ^\n%Error: Exiting due to 19 error(s)\n' | 303,988 | module | module Memory(
clk_i,
we_i,
if_cnt_i,
w_cnt_i,
w_dat_i,
w_adr_i,
inst_adr_i,
if_adr_i,
ea_adr_i,
rd_adr_i,
stl_o,
inst_o,
if_dat_o,
ea_dat_o,
rd_dat_o
`ifdef DEBUG
,debug_o
`endif
);
input wire clk_i;
input wire we_i;
input wire [1:0] if_cnt_i;
input wire [1:0] w_cnt_i;
input wire [3 * `DAT_WIDTH - 1:0] w_dat_i;
input wire [`ADR_WIDTH - 1:0] w_adr_i;
input wire [`ADR_WIDTH - 1:0] inst_adr_i;
input wire [`ADR_WIDTH - 1:0] if_adr_i;
input wire [`ADR_WIDTH - 1:0] ea_adr_i;
input wire [`ADR_WIDTH - 1:0] rd_adr_i;
output reg stl_o;
output wire [1 * `DAT_WIDTH - 1:0] inst_o;
output wire [3 * `DAT_WIDTH - 1:0] if_dat_o;
output wire [2 * `DAT_WIDTH - 1:0] ea_dat_o;
output wire [1 * `DAT_WIDTH - 1:0] rd_dat_o;
`ifdef DEBUG
output wire [`MEM_DBG_WIDTH - 1:0] debug_o;
`endif
reg [1:0] w_cnt;
reg [`ADR_WIDTH - 1:0] w_adr;
reg [3 * `DAT_WIDTH - 1:0] w_dat;
reg [`MEM_WIDTH - 1:0] MEM [0:`MEM_DEPTH - 1];
assign inst_o = MEM[inst_adr_i];
assign if_dat_o = (if_cnt_i == 2'h1) ? {16'hFFFF, MEM[if_adr_i]} :
(if_cnt_i == 2'h2) ? {8'hFF, MEM[if_adr_i + 1], MEM[if_adr_i]} :
(if_cnt_i == 2'h3) ? {MEM[if_adr_i + 2], MEM[if_adr_i + 1], MEM[if_adr_i]} : if_dat_o;
assign ea_dat_o = {MEM[ea_adr_i + 1], MEM[ea_adr_i]};
assign rd_dat_o = MEM[rd_adr_i];
`ifdef DEBUG
assign debug_o = {8'h0, MEM[inst_adr_i]};
`endif
initial
begin
MEM[65532] = 8'h2E;
MEM[65533] = 8'h80;
MEM[32814] = `LDY_IME;
MEM[32815] = 8'h07;
MEM[32816] = `LDA_IME;
MEM[32817] = 8'h00;
MEM[32818] = `STA_ABS;
MEM[32819] = 8'h03;
MEM[32820] = 8'h00;
MEM[32821] = `LDA_IME;
MEM[32822] = 8'h01;
MEM[32823] = `TAX;
MEM[32824] = `ADC_ABS;
MEM[32825] = 8'h03;
MEM[32826] = 8'h00;
MEM[32827] = `STX_ABS;
MEM[32828] = 8'h03;
MEM[32829] = 8'h00;
MEM[32830] = `DEY;
MEM[32831] = `BNE;
MEM[32832] = 8'hF6;
end
always @(posedge clk_i)
begin
if(we_i || stl_o)
begin
if(w_cnt_i > 2'h1 || stl_o == 1'h1)
begin
if(stl_o == 1'h0)
begin
stl_o <= 1'h1;
w_cnt <= w_cnt_i;
w_dat <= w_dat_i;
w_adr <= w_adr_i;
end
else if(w_cnt > 2'h1 && stl_o == 1'h1)
begin
w_cnt <= w_cnt - 2'h1;
w_dat <= w_dat >> 4'h8;
MEM[w_adr + w_cnt - 2'h1] <= w_dat[7:0];
end
else
begin
stl_o <= 1'h0;
MEM[w_adr + w_cnt - 2'h1] <= w_dat[7:0];
end
end
else
begin
stl_o <= 1'h0;
MEM[w_adr_i] <= w_dat_i;
end
end
end
endmodule | module Memory(
clk_i,
we_i,
if_cnt_i,
w_cnt_i,
w_dat_i,
w_adr_i,
inst_adr_i,
if_adr_i,
ea_adr_i,
rd_adr_i,
stl_o,
inst_o,
if_dat_o,
ea_dat_o,
rd_dat_o
`ifdef DEBUG
,debug_o
`endif
); |
input wire clk_i;
input wire we_i;
input wire [1:0] if_cnt_i;
input wire [1:0] w_cnt_i;
input wire [3 * `DAT_WIDTH - 1:0] w_dat_i;
input wire [`ADR_WIDTH - 1:0] w_adr_i;
input wire [`ADR_WIDTH - 1:0] inst_adr_i;
input wire [`ADR_WIDTH - 1:0] if_adr_i;
input wire [`ADR_WIDTH - 1:0] ea_adr_i;
input wire [`ADR_WIDTH - 1:0] rd_adr_i;
output reg stl_o;
output wire [1 * `DAT_WIDTH - 1:0] inst_o;
output wire [3 * `DAT_WIDTH - 1:0] if_dat_o;
output wire [2 * `DAT_WIDTH - 1:0] ea_dat_o;
output wire [1 * `DAT_WIDTH - 1:0] rd_dat_o;
`ifdef DEBUG
output wire [`MEM_DBG_WIDTH - 1:0] debug_o;
`endif
reg [1:0] w_cnt;
reg [`ADR_WIDTH - 1:0] w_adr;
reg [3 * `DAT_WIDTH - 1:0] w_dat;
reg [`MEM_WIDTH - 1:0] MEM [0:`MEM_DEPTH - 1];
assign inst_o = MEM[inst_adr_i];
assign if_dat_o = (if_cnt_i == 2'h1) ? {16'hFFFF, MEM[if_adr_i]} :
(if_cnt_i == 2'h2) ? {8'hFF, MEM[if_adr_i + 1], MEM[if_adr_i]} :
(if_cnt_i == 2'h3) ? {MEM[if_adr_i + 2], MEM[if_adr_i + 1], MEM[if_adr_i]} : if_dat_o;
assign ea_dat_o = {MEM[ea_adr_i + 1], MEM[ea_adr_i]};
assign rd_dat_o = MEM[rd_adr_i];
`ifdef DEBUG
assign debug_o = {8'h0, MEM[inst_adr_i]};
`endif
initial
begin
MEM[65532] = 8'h2E;
MEM[65533] = 8'h80;
MEM[32814] = `LDY_IME;
MEM[32815] = 8'h07;
MEM[32816] = `LDA_IME;
MEM[32817] = 8'h00;
MEM[32818] = `STA_ABS;
MEM[32819] = 8'h03;
MEM[32820] = 8'h00;
MEM[32821] = `LDA_IME;
MEM[32822] = 8'h01;
MEM[32823] = `TAX;
MEM[32824] = `ADC_ABS;
MEM[32825] = 8'h03;
MEM[32826] = 8'h00;
MEM[32827] = `STX_ABS;
MEM[32828] = 8'h03;
MEM[32829] = 8'h00;
MEM[32830] = `DEY;
MEM[32831] = `BNE;
MEM[32832] = 8'hF6;
end
always @(posedge clk_i)
begin
if(we_i || stl_o)
begin
if(w_cnt_i > 2'h1 || stl_o == 1'h1)
begin
if(stl_o == 1'h0)
begin
stl_o <= 1'h1;
w_cnt <= w_cnt_i;
w_dat <= w_dat_i;
w_adr <= w_adr_i;
end
else if(w_cnt > 2'h1 && stl_o == 1'h1)
begin
w_cnt <= w_cnt - 2'h1;
w_dat <= w_dat >> 4'h8;
MEM[w_adr + w_cnt - 2'h1] <= w_dat[7:0];
end
else
begin
stl_o <= 1'h0;
MEM[w_adr + w_cnt - 2'h1] <= w_dat[7:0];
end
end
else
begin
stl_o <= 1'h0;
MEM[w_adr_i] <= w_dat_i;
end
end
end
endmodule | 4 |
138,921 | data/full_repos/permissive/86415694/Other_Modules.v | 86,415,694 | Other_Modules.v | v | 83 | 41 | [] | [] | [] | [(1, 17), (22, 44), (49, 83)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/86415694/Other_Modules.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'MUX2x1\'\nmodule MUX2x1(\n ^~~~~~\n : ... Top module \'MUX4x1\'\nmodule MUX4x1(\n ^~~~~~\n : ... Top module \'MUX8x1\'\nmodule MUX8x1(\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/86415694/Other_Modules.v:15: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance MUX2x1\n assign out = (sel == 2\'h0) ? in0 : in1;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 303,989 | module | module MUX2x1(
out,
sel,
in0,
in1
);
parameter width = 8;
output wire [width - 1 : 0] out;
input wire sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
assign out = (sel == 2'h0) ? in0 : in1;
endmodule | module MUX2x1(
out,
sel,
in0,
in1
); |
parameter width = 8;
output wire [width - 1 : 0] out;
input wire sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
assign out = (sel == 2'h0) ? in0 : in1;
endmodule | 4 |
138,922 | data/full_repos/permissive/86415694/Other_Modules.v | 86,415,694 | Other_Modules.v | v | 83 | 41 | [] | [] | [] | [(1, 17), (22, 44), (49, 83)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/86415694/Other_Modules.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'MUX2x1\'\nmodule MUX2x1(\n ^~~~~~\n : ... Top module \'MUX4x1\'\nmodule MUX4x1(\n ^~~~~~\n : ... Top module \'MUX8x1\'\nmodule MUX8x1(\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/86415694/Other_Modules.v:15: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance MUX2x1\n assign out = (sel == 2\'h0) ? in0 : in1;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 303,989 | module | module MUX4x1(
out,
sel,
in0,
in1,
in2,
in3
);
parameter width = 8;
output wire [width - 1 : 0] out;
input wire [1:0] sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
input wire [width - 1 : 0] in2;
input wire [width - 1 : 0] in3;
assign out = (sel == 2'h0) ? in0 :
(sel == 2'h1) ? in1 :
(sel == 2'h2) ? in2 : in3;
endmodule | module MUX4x1(
out,
sel,
in0,
in1,
in2,
in3
); |
parameter width = 8;
output wire [width - 1 : 0] out;
input wire [1:0] sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
input wire [width - 1 : 0] in2;
input wire [width - 1 : 0] in3;
assign out = (sel == 2'h0) ? in0 :
(sel == 2'h1) ? in1 :
(sel == 2'h2) ? in2 : in3;
endmodule | 4 |
138,923 | data/full_repos/permissive/86415694/Other_Modules.v | 86,415,694 | Other_Modules.v | v | 83 | 41 | [] | [] | [] | [(1, 17), (22, 44), (49, 83)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/86415694/Other_Modules.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'MUX2x1\'\nmodule MUX2x1(\n ^~~~~~\n : ... Top module \'MUX4x1\'\nmodule MUX4x1(\n ^~~~~~\n : ... Top module \'MUX8x1\'\nmodule MUX8x1(\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/86415694/Other_Modules.v:15: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance MUX2x1\n assign out = (sel == 2\'h0) ? in0 : in1;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 303,989 | module | module MUX8x1(
out,
sel,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7
);
parameter width = 8;
output wire [width - 1 : 0] out;
input wire [2:0] sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
input wire [width - 1 : 0] in2;
input wire [width - 1 : 0] in3;
input wire [width - 1 : 0] in4;
input wire [width - 1 : 0] in5;
input wire [width - 1 : 0] in6;
input wire [width - 1 : 0] in7;
assign out = (sel == 3'h0) ? in0 :
(sel == 3'h1) ? in1 :
(sel == 3'h2) ? in2 :
(sel == 3'h3) ? in3 :
(sel == 3'h4) ? in4 :
(sel == 3'h5) ? in5 :
(sel == 3'h6) ? in6 : in7;
endmodule | module MUX8x1(
out,
sel,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7
); |
parameter width = 8;
output wire [width - 1 : 0] out;
input wire [2:0] sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
input wire [width - 1 : 0] in2;
input wire [width - 1 : 0] in3;
input wire [width - 1 : 0] in4;
input wire [width - 1 : 0] in5;
input wire [width - 1 : 0] in6;
input wire [width - 1 : 0] in7;
assign out = (sel == 3'h0) ? in0 :
(sel == 3'h1) ? in1 :
(sel == 3'h2) ? in2 :
(sel == 3'h3) ? in3 :
(sel == 3'h4) ? in4 :
(sel == 3'h5) ? in5 :
(sel == 3'h6) ? in6 : in7;
endmodule | 4 |
138,926 | data/full_repos/permissive/86415694/System.v | 86,415,694 | System.v | v | 132 | 58 | [] | [] | [] | [(501, 630)] | null | null | 1: b'%Error: data/full_repos/permissive/86415694/System.v:1: Cannot find include file: Global_Macros.v\n`include "Global_Macros.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.v\n data/full_repos/permissive/86415694,data/full_repos/permissive/86415694/Global_Macros.v.sv\n Global_Macros.v\n Global_Macros.v.v\n Global_Macros.v.sv\n obj_dir/Global_Macros.v\n obj_dir/Global_Macros.v.v\n obj_dir/Global_Macros.v.sv\n%Error: Exiting due to 1 error(s)\n' | 303,992 | module | module System(
clk_i,
rst_i,
irq_i,
nmi_i,
rdy_i,
mem_u_stl_o,
mem_u_if_dat_o,
mem_u_ea_dat_o,
mem_u_rd_dat_o,
mem_u_inst_o,
core_u_we_o,
core_u_if_cnt_o,
core_u_w_cnt_o,
core_u_w_dat_o,
core_u_w_adr_o,
core_u_inst_adr_o,
core_u_if_adr_o,
core_u_ea_adr_o,
core_u_rd_adr_o
`ifdef DEBUG
,core_u_a_o,
core_u_x_o,
core_u_y_o,
mem_u_dbg_o,
core_u_pf_u_dbg_o,
core_u_dec_u_dbg_o,
core_u_ea_u_dbg_o,
core_u_rd_u_dbg_o,
core_u_exe_u_dbg_o,
core_u_wb_u_dbg_o
`endif
);
input wire clk_i;
input wire rst_i;
input wire irq_i;
input wire nmi_i;
input wire rdy_i;
output wire mem_u_stl_o;
output wire [23:0] mem_u_if_dat_o;
output wire [15:0] mem_u_ea_dat_o;
output wire [7:0] mem_u_rd_dat_o;
output wire [7:0] mem_u_inst_o;
output wire core_u_we_o;
output wire [1:0] core_u_if_cnt_o;
output wire [1:0] core_u_w_cnt_o;
output wire [23:0] core_u_w_dat_o;
output wire [15:0] core_u_w_adr_o;
output wire [15:0] core_u_inst_adr_o;
output wire [15:0] core_u_if_adr_o;
output wire [15:0] core_u_ea_adr_o;
output wire [15:0] core_u_rd_adr_o;
`ifdef DEBUG
output wire [7:0] core_u_a_o;
output wire [7:0] core_u_x_o;
output wire [7:0] core_u_y_o;
output wire [`MEM_DBG_WIDTH - 1:0] mem_u_dbg_o;
output wire [`PRF_DBG_WIDTH - 1:0] core_u_pf_u_dbg_o;
output wire [`DEC_DBG_WIDTH - 1:0] core_u_dec_u_dbg_o;
output wire [`EAD_DBG_WIDTH - 1:0] core_u_ea_u_dbg_o;
output wire [`RDA_DBG_WIDTH - 1:0] core_u_rd_u_dbg_o;
output wire [`EXE_DBG_WIDTH - 1:0] core_u_exe_u_dbg_o;
output wire [`WRB_DBG_WIDTH - 1:0] core_u_wb_u_dbg_o;
`endif
Memory mem_u
(
.clk_i (clk_i),
.we_i (core_u_we_o),
.if_cnt_i (core_u_if_cnt_o),
.w_cnt_i (core_u_w_cnt_o),
.w_dat_i (core_u_w_dat_o),
.w_adr_i (core_u_w_adr_o),
.inst_adr_i (core_u_inst_adr_o),
.if_adr_i (core_u_if_adr_o),
.ea_adr_i (core_u_ea_adr_o),
.rd_adr_i (core_u_rd_adr_o),
.stl_o (mem_u_stl_o),
.if_dat_o (mem_u_if_dat_o),
.ea_dat_o (mem_u_ea_dat_o),
.rd_dat_o (mem_u_rd_dat_o),
.inst_o (mem_u_inst_o)
`ifdef DEBUG
,.debug_o (mem_u_dbg_o)
`endif
);
Core core_u
(
.clk_i (clk_i),
.rst_i (rst_i),
.irq_i (irq_i),
.nmi_i (nmi_i),
.rdy_i (rdy_i),
.stl_i (mem_u_stl_o),
.if_dat_i (mem_u_if_dat_o),
.ea_dat_i (mem_u_ea_dat_o),
.rd_dat_i (mem_u_rd_dat_o),
.inst_i (mem_u_inst_o),
.we_o (core_u_we_o),
.if_cnt_o (core_u_if_cnt_o),
.w_cnt_o (core_u_w_cnt_o),
.w_dat_o (core_u_w_dat_o),
.w_adr_o (core_u_w_adr_o),
.inst_adr_o (core_u_inst_adr_o),
.if_adr_o (core_u_if_adr_o),
.ea_adr_o (core_u_ea_adr_o),
.rd_adr_o (core_u_rd_adr_o)
`ifdef DEBUG
,.a_o (core_u_a_o),
.x_o (core_u_x_o),
.y_o (core_u_y_o),
.pf_u_dbg_o (core_u_pf_u_dbg_o),
.dec_u_dbg_o (core_u_dec_u_dbg_o),
.ea_u_dbg_o (core_u_ea_u_dbg_o),
.rd_u_dbg_o (core_u_rd_u_dbg_o),
.exe_u_dbg_o (core_u_exe_u_dbg_o),
.wb_u_dbg_o (core_u_wb_u_dbg_o)
`endif
);
endmodule | module System(
clk_i,
rst_i,
irq_i,
nmi_i,
rdy_i,
mem_u_stl_o,
mem_u_if_dat_o,
mem_u_ea_dat_o,
mem_u_rd_dat_o,
mem_u_inst_o,
core_u_we_o,
core_u_if_cnt_o,
core_u_w_cnt_o,
core_u_w_dat_o,
core_u_w_adr_o,
core_u_inst_adr_o,
core_u_if_adr_o,
core_u_ea_adr_o,
core_u_rd_adr_o
`ifdef DEBUG
,core_u_a_o,
core_u_x_o,
core_u_y_o,
mem_u_dbg_o,
core_u_pf_u_dbg_o,
core_u_dec_u_dbg_o,
core_u_ea_u_dbg_o,
core_u_rd_u_dbg_o,
core_u_exe_u_dbg_o,
core_u_wb_u_dbg_o
`endif
); |
input wire clk_i;
input wire rst_i;
input wire irq_i;
input wire nmi_i;
input wire rdy_i;
output wire mem_u_stl_o;
output wire [23:0] mem_u_if_dat_o;
output wire [15:0] mem_u_ea_dat_o;
output wire [7:0] mem_u_rd_dat_o;
output wire [7:0] mem_u_inst_o;
output wire core_u_we_o;
output wire [1:0] core_u_if_cnt_o;
output wire [1:0] core_u_w_cnt_o;
output wire [23:0] core_u_w_dat_o;
output wire [15:0] core_u_w_adr_o;
output wire [15:0] core_u_inst_adr_o;
output wire [15:0] core_u_if_adr_o;
output wire [15:0] core_u_ea_adr_o;
output wire [15:0] core_u_rd_adr_o;
`ifdef DEBUG
output wire [7:0] core_u_a_o;
output wire [7:0] core_u_x_o;
output wire [7:0] core_u_y_o;
output wire [`MEM_DBG_WIDTH - 1:0] mem_u_dbg_o;
output wire [`PRF_DBG_WIDTH - 1:0] core_u_pf_u_dbg_o;
output wire [`DEC_DBG_WIDTH - 1:0] core_u_dec_u_dbg_o;
output wire [`EAD_DBG_WIDTH - 1:0] core_u_ea_u_dbg_o;
output wire [`RDA_DBG_WIDTH - 1:0] core_u_rd_u_dbg_o;
output wire [`EXE_DBG_WIDTH - 1:0] core_u_exe_u_dbg_o;
output wire [`WRB_DBG_WIDTH - 1:0] core_u_wb_u_dbg_o;
`endif
Memory mem_u
(
.clk_i (clk_i),
.we_i (core_u_we_o),
.if_cnt_i (core_u_if_cnt_o),
.w_cnt_i (core_u_w_cnt_o),
.w_dat_i (core_u_w_dat_o),
.w_adr_i (core_u_w_adr_o),
.inst_adr_i (core_u_inst_adr_o),
.if_adr_i (core_u_if_adr_o),
.ea_adr_i (core_u_ea_adr_o),
.rd_adr_i (core_u_rd_adr_o),
.stl_o (mem_u_stl_o),
.if_dat_o (mem_u_if_dat_o),
.ea_dat_o (mem_u_ea_dat_o),
.rd_dat_o (mem_u_rd_dat_o),
.inst_o (mem_u_inst_o)
`ifdef DEBUG
,.debug_o (mem_u_dbg_o)
`endif
);
Core core_u
(
.clk_i (clk_i),
.rst_i (rst_i),
.irq_i (irq_i),
.nmi_i (nmi_i),
.rdy_i (rdy_i),
.stl_i (mem_u_stl_o),
.if_dat_i (mem_u_if_dat_o),
.ea_dat_i (mem_u_ea_dat_o),
.rd_dat_i (mem_u_rd_dat_o),
.inst_i (mem_u_inst_o),
.we_o (core_u_we_o),
.if_cnt_o (core_u_if_cnt_o),
.w_cnt_o (core_u_w_cnt_o),
.w_dat_o (core_u_w_dat_o),
.w_adr_o (core_u_w_adr_o),
.inst_adr_o (core_u_inst_adr_o),
.if_adr_o (core_u_if_adr_o),
.ea_adr_o (core_u_ea_adr_o),
.rd_adr_o (core_u_rd_adr_o)
`ifdef DEBUG
,.a_o (core_u_a_o),
.x_o (core_u_x_o),
.y_o (core_u_y_o),
.pf_u_dbg_o (core_u_pf_u_dbg_o),
.dec_u_dbg_o (core_u_dec_u_dbg_o),
.ea_u_dbg_o (core_u_ea_u_dbg_o),
.rd_u_dbg_o (core_u_rd_u_dbg_o),
.exe_u_dbg_o (core_u_exe_u_dbg_o),
.wb_u_dbg_o (core_u_wb_u_dbg_o)
`endif
);
endmodule | 4 |
138,928 | data/full_repos/permissive/86517789/comparator.v | 86,517,789 | comparator.v | v | 15 | 57 | [] | [] | [] | [(1, 14)] | null | data/verilator_xmls/b32561b6-66fb-4084-a267-492def486900.xml | null | 304,042 | module | module comparator
# (parameter W = 32)
(input [W-1:0] ival, input [W-1:0] yval, output reg gt);
always @ (*) begin
if (ival > yval)
gt =1;
else
gt =0;
end
endmodule | module comparator
# (parameter W = 32)
(input [W-1:0] ival, input [W-1:0] yval, output reg gt); |
always @ (*) begin
if (ival > yval)
gt =1;
else
gt =0;
end
endmodule | 0 |
138,929 | data/full_repos/permissive/86517789/contolfifo.v | 86,517,789 | contolfifo.v | v | 19 | 97 | [] | [] | [] | [(1, 18)] | null | data/verilator_xmls/a7d00f0c-e58e-4100-8c08-47e0cb29c0ee.xml | null | 304,043 | module | module controlfifo (input gt, input e1, input e2, output rd1, output rd2,output sel1,output wr);
wire w1,w2,w3,w4,w5,w6;
not n1(w1,gt),
n2(w2,e1),
n3(w3,e2);
and a3(w6,w2,w1);
or r1(w4,e2,w1),
r2(w5,e1,gt),
r3(wr,w2,w3),
r4(sel1,w6,e2);
and a1(rd1,w4,w2),
a2(rd2,w3,w5);
endmodule | module controlfifo (input gt, input e1, input e2, output rd1, output rd2,output sel1,output wr); |
wire w1,w2,w3,w4,w5,w6;
not n1(w1,gt),
n2(w2,e1),
n3(w3,e2);
and a3(w6,w2,w1);
or r1(w4,e2,w1),
r2(w5,e1,gt),
r3(wr,w2,w3),
r4(sel1,w6,e2);
and a1(rd1,w4,w2),
a2(rd2,w3,w5);
endmodule | 0 |
138,930 | data/full_repos/permissive/86517789/mux.v | 86,517,789 | mux.v | v | 17 | 76 | [] | [] | [] | [(1, 16)] | null | data/verilator_xmls/67a16b01-bae1-4e44-b503-a309bc8678b4.xml | null | 304,049 | module | module mux
# (parameter W = 32)
(input [W-1:0] in1, input [W-1:0] in2, input sel, output reg [W-1:0] out );
always @ (*) begin
if (sel)
out =in1;
else
out =in2;
end
endmodule | module mux
# (parameter W = 32)
(input [W-1:0] in1, input [W-1:0] in2, input sel, output reg [W-1:0] out ); |
always @ (*) begin
if (sel)
out =in1;
else
out =in2;
end
endmodule | 0 |
138,931 | data/full_repos/permissive/86517789/sortfsm.v | 86,517,789 | sortfsm.v | v | 61 | 85 | [] | [] | [] | [(1, 60)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/86517789/sortfsm.v:23: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance sortFsm\n ns = 2\'b01; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86517789/sortfsm.v:31: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance sortFsm\n ns = 2\'b10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86517789/sortfsm.v:39: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance sortFsm\n ns = 2\'b11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86517789/sortfsm.v:17: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance sortFsm\n case (cs)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86517789/sortfsm.v:17: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance sortFsm\n case (cs)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86517789/sortfsm.v:17: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance sortFsm\n case (cs)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86517789/sortfsm.v:17: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance sortFsm\n case (cs)\n ^~~~\n%Error: Exiting due to 7 warning(s)\n' | 304,050 | module | module sortFsm (input clk, input reset, input full, output reg wd1,output reg load,
output reg done);
reg [2:0] cs, ns;
always @ (posedge clk, posedge reset) begin
if (reset)
cs <= 0;
else
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
2'b00 : begin
$display ("START");
wd1=0;load=1;
done=0;
ns = 2'b01;
end
2'b01 : begin
$display ("working");
wd1=1;load=0;
done=0;
ns = 2'b10;
end
2'b10 : begin
$display ("working");
wd1=0;load=0;
done=0;
if (full)
ns = 2'b11;
end
2'b11 : begin
$display ("STOP");
wd1=0;
load=0;
done=1;
end
default : begin
$display ("default");
end
endcase
end
endmodule | module sortFsm (input clk, input reset, input full, output reg wd1,output reg load,
output reg done); |
reg [2:0] cs, ns;
always @ (posedge clk, posedge reset) begin
if (reset)
cs <= 0;
else
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
2'b00 : begin
$display ("START");
wd1=0;load=1;
done=0;
ns = 2'b01;
end
2'b01 : begin
$display ("working");
wd1=1;load=0;
done=0;
ns = 2'b10;
end
2'b10 : begin
$display ("working");
wd1=0;load=0;
done=0;
if (full)
ns = 2'b11;
end
2'b11 : begin
$display ("STOP");
wd1=0;
load=0;
done=1;
end
default : begin
$display ("default");
end
endcase
end
endmodule | 0 |
138,932 | data/full_repos/permissive/86517789/sortvals.v | 86,517,789 | sortvals.v | v | 292 | 200 | [] | [] | [] | [(1, 291)] | null | null | 1: b"%Error: data/full_repos/permissive/86517789/sortvals.v:59: Cannot find file containing module: 'fifo1'\nfifo1 fifoa11(array_intp[0],wd1,rd11,d1121,dcmp11,e11,clk,reset);\n^~~~~\n ... Looked in:\n data/full_repos/permissive/86517789,data/full_repos/permissive/86517789/fifo1\n data/full_repos/permissive/86517789,data/full_repos/permissive/86517789/fifo1.v\n data/full_repos/permissive/86517789,data/full_repos/permissive/86517789/fifo1.sv\n fifo1\n fifo1.v\n fifo1.sv\n obj_dir/fifo1\n obj_dir/fifo1.v\n obj_dir/fifo1.sv\n%Error: data/full_repos/permissive/86517789/sortvals.v:60: Cannot find file containing module: 'fifo1'\nfifo1 fifoa12(array_intp[1],wd1,rd12,d1221,dcmp12,e12,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:61: Cannot find file containing module: 'comparator'\ncomparator cmp11(dcmp11,dcmp12,gt11);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:62: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl11(gt11,e11,e12,rd11,rd12,sel11,wd21);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:63: Cannot find file containing module: 'mux'\nmux mux11(d1121,d1221,sel11,d21);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:65: Cannot find file containing module: 'fifo1'\nfifo1 fifoa13(array_intp[2],wd1,rd13,d1322,dcmp13,e13,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:66: Cannot find file containing module: 'fifo1'\nfifo1 fifoa14(array_intp[3],wd1,rd14,d1422,dcmp14,e14,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:67: Cannot find file containing module: 'comparator'\ncomparator cmp12(dcmp13,dcmp14,gt12);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:68: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl12(gt12,e13,e14,rd13,rd14,sel12,wd22);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:69: Cannot find file containing module: 'mux'\nmux mux12(d1322,d1422,sel12,d22);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:71: Cannot find file containing module: 'fifo1'\nfifo1 fifoa15(array_intp[4],wd1,rd15,d1523,dcmp15,e15,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:72: Cannot find file containing module: 'fifo1'\nfifo1 fifoa16(array_intp[5],wd1,rd16,d1623,dcmp16,e16,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:73: Cannot find file containing module: 'comparator'\ncomparator cmp13(dcmp15,dcmp16,gt13);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:74: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl13(gt13,e15,e16,rd15,rd16,sel13,wd23);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:75: Cannot find file containing module: 'mux'\nmux mux13(d1523,d1623,sel13,d23);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:77: Cannot find file containing module: 'fifo1'\nfifo1 fifoa17(array_intp[6],wd1,rd17,d1724,dcmp17,e17,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:78: Cannot find file containing module: 'fifo1'\nfifo1 fifoa18(array_intp[7],wd1,rd18,d1824,dcmp18,e18,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:79: Cannot find file containing module: 'comparator'\ncomparator cmp14(dcmp17,dcmp18,gt14);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:80: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl14(gt14,e17,e18,rd17,rd18,sel14,wd24);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:81: Cannot find file containing module: 'mux'\nmux mux14(d1724,d1824,sel14,d24);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:83: Cannot find file containing module: 'fifo1'\nfifo1 fifoa19(array_intp[8],wd1,rd19,d1925,dcmp19,e19,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:84: Cannot find file containing module: 'fifo1'\nfifo1 fifoa110(array_intp[9],wd1,rd110,d11025,dcmp110,e110,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:85: Cannot find file containing module: 'comparator'\ncomparator cmp15(dcmp19,dcmp110,gt15);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:86: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl15(gt15,e19,e110,rd19,rd110,sel15,wd25);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:87: Cannot find file containing module: 'mux'\nmux mux15(d1925,d11025,sel15,d25);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:89: Cannot find file containing module: 'fifo1'\nfifo1 fifoa111(array_intp[10],wd1,rd111,d11126,dcmp111,e111,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:90: Cannot find file containing module: 'fifo1'\nfifo1 fifoa112(array_intp[11],wd1,rd112,d11226,dcmp112,e112,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:91: Cannot find file containing module: 'comparator'\ncomparator cmp16(dcmp111,dcmp112,gt16);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:92: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl16(gt16,e111,e112,rd111,rd112,sel16,wd26);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:93: Cannot find file containing module: 'mux'\nmux mux16(d11126,d11226,sel16,d26);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:95: Cannot find file containing module: 'fifo1'\nfifo1 fifoa113(array_intp[12],wd1,rd113,d11327,dcmp113,e113,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:96: Cannot find file containing module: 'fifo1'\nfifo1 fifoa114(array_intp[13],wd1,rd114,d11427,dcmp114,e114,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:97: Cannot find file containing module: 'comparator'\ncomparator cmp17(dcmp113,dcmp114,gt17);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:98: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl17(gt17,e113,e114,rd113,rd114,sel17,wd27);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:99: Cannot find file containing module: 'mux'\nmux mux17(d11327,d11427,sel17,d27);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:101: Cannot find file containing module: 'fifo1'\nfifo1 fifoa115(array_intp[14],wd1,rd115,d11528,dcmp115,e115,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:102: Cannot find file containing module: 'fifo1'\nfifo1 fifoa116(array_intp[15],wd1,rd116,d11628,dcmp116,e116,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:103: Cannot find file containing module: 'comparator'\ncomparator cmp18(dcmp115,dcmp116,gt18);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:104: Cannot find file containing module: 'controlfifo'\ncontrolfifo cntrl18(gt18,e115,e116,rd115,rd116,sel18,wd28);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:105: Cannot find file containing module: 'mux'\nmux mux18(d11528,d11628,sel18,d28);\n^~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:107: Cannot find file containing module: 'fifo1'\nfifo1 fifoa117(array_intp[16],wd1,rd117,d11729,dcmp117,e117,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:108: Cannot find file containing module: 'fifo1'\nfifo1 fifoa118(array_intp[17],wd1,rd118,d11829,dcmp118,e118,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:109: Cannot find file containing module: 'fifo1'\nfifo1 fifoa119(array_intp[18],wd1,rd119,d119210,dcmp119,e119,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:110: Cannot find file containing module: 'fifo1'\nfifo1 fifoa120(array_intp[19],wd1,rd120,d120210,dcmp120,e120,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:111: Cannot find file containing module: 'fifo1'\nfifo1 fifoa121(array_intp[20],wd1,rd121,d121211,dcmp121,e121,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:112: Cannot find file containing module: 'fifo1'\nfifo1 fifoa122(array_intp[21],wd1,rd122,d122211,dcmp122,e122,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:113: Cannot find file containing module: 'fifo1'\nfifo1 fifoa123(array_intp[22],wd1,rd123,d123212,dcmp123,e123,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:114: Cannot find file containing module: 'fifo1'\nfifo1 fifoa124(array_intp[23],wd1,rd124,d124212,dcmp124,e124,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:115: Cannot find file containing module: 'fifo1'\nfifo1 fifoa125(array_intp[24],wd1,rd125,d125213,dcmp125,e125,clk,reset);\n^~~~~\n%Error: data/full_repos/permissive/86517789/sortvals.v:116: Cannot find file containing module: 'fifo1'\nfifo1 fifoa126(array_intp[25],wd1,rd126,d126213,dcmp126,e126,clk,reset);\n^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 304,051 | module | module sortvals
# (parameter DATA_WIDTH = 32, NUM_WORDS = 32)
( input [DATA_WIDTH*NUM_WORDS-1:0] array_in,
input clk,input reset,
output reg [DATA_WIDTH*NUM_WORDS-1:0] array_out,
output reg done );
reg [DATA_WIDTH-1:0] array_intp [NUM_WORDS-1:0];
reg [DATA_WIDTH-1:0] array_outp [NUM_WORDS-1:0];
integer j,k,l,m,n,q;
reg [NUM_WORDS-1:0]p=31;
wire wd1,wd21,wd22;
wire rd11,rd12,rd13,rd14,rd21,rd22;
wire e11,e12,e13,e14,e21,e22;
wire gt11,gt12,gt21;
wire wd51,rd51,e51,wd52,rd52,e52,gt51,sel51,wd61,wd31,rd31,e31,wd32,rd32,e32,wd33,rd33,e33,wd34,rd34,e34,wd35,
rd35,e35,wd36,rd36,e36,wd37,rd37,e37,wd38,rd38,e38,
gt31,gt32,gt33,gt34,sel31,sel32,sel33,sel34,wd41,rd41,e41,wd42,rd42,e42,wd43,rd43,e43,wd44,rd44,e44,gt41,gt42,
sel41,sel42,wd23,rd23,e23,wd24,rd24,e24,wd25,rd25,
e25,wd26,rd26,e26,wd27,rd27,e27,wd28,rd28,e28,wd29,rd29,e29,wd210,rd210,e210,
wd211,rd211,e211,wd212,rd212,e212,wd213,rd213,e213,wd214,rd214,e214,wd215,rd215,e215,wd216,rd216,e216,
gt22,gt23,gt24,gt25,gt26,gt27,gt28,sel22,sel23,sel24,sel25,sel26,sel27,sel28,rd15,e15,rd16,e16,rd17,e17,rd18,e18,rd19,e19,rd110,e110,rd111,e111,rd112,e112,rd113,e113,rd114,e114,rd115,e115,rd116,e116,
gt13,gt14,gt15,gt16,gt17,gt18,sel13,sel14,sel15,sel16,sel17,sel18;
wire rd117,e117,rd118,e118,rd119,e119,rd120,e120,rd121,e121,rd122,e122,rd123,e123,rd124,e124,rd125,e125,rd126,e126,
rd127,e127,rd128,e128,rd129,e129,rd130,e130,rd131,e131,rd132,e132,gt19,gt110,gt111,gt112,gt113,gt114,gt115,gt116,
sel19,sel110,sel111,sel112,sel113,sel114,sel115,sel116;
wire [DATA_WIDTH-1:0] d41,d42,d43,d44,d4141,d61,dcmp41,d4241,dcmp42,d4342,dcmp43,d4442,dcmp44,
d51,d52,d5161,dcmp51,d5261,dcmp52,d31,d3141,dcmp31,d32,d3241,dcmp32,d33,d3342,dcmp33,d34,d3442,dcmp34,d35,d3543,dcmp35,d36,d3643,dcmp36,d37,d3744,dcmp37,d38,d3844,dcmp38,
d23,d210,d2332,dcmp23,d21035,dcmp210,d24,d211,d2432,dcmp24,d21136,dcmp211,d25,d212,d2533,dcmp25,d21236,dcmp212,
d26,d213,d2633,dcmp26,d21337,dcmp213,d27,d214,d2734,dcmp27,d21437,dcmp214,d28,d215,d2834,dcmp28,d21538,dcmp215,
d29,d216,d2935,dcmp29,d21638,dcmp216,d11729,dcmp117,d11829,dcmp118,d119210,dcmp119,d120210,dcmp120,d121211,dcmp121,d122211,dcmp122,d123212,dcmp123
,d124212,dcmp124,d125213,dcmp125,d126213,dcmp126,d127214,dcmp127,d128214,dcmp128,d129215,dcmp129
,d130215,dcmp130,d131216,dcmp131,d132216,dcmp132,d1523,dcmp15,d11025,dcmp110,d1623,dcmp16,d11126,dcmp111,d1724,dcmp17,d11226,dcmp112,d1824,dcmp18,d11327,dcmp113,
d1925,dcmp19,d11427,dcmp114,d11528,dcmp115,d11628,dcmp116;
reg f1;
wire Done,load;
wire [DATA_WIDTH-1:0] d1121,d1221,d1322,d1422,d21,d22,d2131,d2231;
wire [DATA_WIDTH-1:0] dcmp11,dcmp12,dcmp13,dcmp14,dcmp21,dcmp22;
wire sel11,sel12,sel21;
fifo1 fifoa11(array_intp[0],wd1,rd11,d1121,dcmp11,e11,clk,reset);
fifo1 fifoa12(array_intp[1],wd1,rd12,d1221,dcmp12,e12,clk,reset);
comparator cmp11(dcmp11,dcmp12,gt11);
controlfifo cntrl11(gt11,e11,e12,rd11,rd12,sel11,wd21);
mux mux11(d1121,d1221,sel11,d21);
fifo1 fifoa13(array_intp[2],wd1,rd13,d1322,dcmp13,e13,clk,reset);
fifo1 fifoa14(array_intp[3],wd1,rd14,d1422,dcmp14,e14,clk,reset);
comparator cmp12(dcmp13,dcmp14,gt12);
controlfifo cntrl12(gt12,e13,e14,rd13,rd14,sel12,wd22);
mux mux12(d1322,d1422,sel12,d22);
fifo1 fifoa15(array_intp[4],wd1,rd15,d1523,dcmp15,e15,clk,reset);
fifo1 fifoa16(array_intp[5],wd1,rd16,d1623,dcmp16,e16,clk,reset);
comparator cmp13(dcmp15,dcmp16,gt13);
controlfifo cntrl13(gt13,e15,e16,rd15,rd16,sel13,wd23);
mux mux13(d1523,d1623,sel13,d23);
fifo1 fifoa17(array_intp[6],wd1,rd17,d1724,dcmp17,e17,clk,reset);
fifo1 fifoa18(array_intp[7],wd1,rd18,d1824,dcmp18,e18,clk,reset);
comparator cmp14(dcmp17,dcmp18,gt14);
controlfifo cntrl14(gt14,e17,e18,rd17,rd18,sel14,wd24);
mux mux14(d1724,d1824,sel14,d24);
fifo1 fifoa19(array_intp[8],wd1,rd19,d1925,dcmp19,e19,clk,reset);
fifo1 fifoa110(array_intp[9],wd1,rd110,d11025,dcmp110,e110,clk,reset);
comparator cmp15(dcmp19,dcmp110,gt15);
controlfifo cntrl15(gt15,e19,e110,rd19,rd110,sel15,wd25);
mux mux15(d1925,d11025,sel15,d25);
fifo1 fifoa111(array_intp[10],wd1,rd111,d11126,dcmp111,e111,clk,reset);
fifo1 fifoa112(array_intp[11],wd1,rd112,d11226,dcmp112,e112,clk,reset);
comparator cmp16(dcmp111,dcmp112,gt16);
controlfifo cntrl16(gt16,e111,e112,rd111,rd112,sel16,wd26);
mux mux16(d11126,d11226,sel16,d26);
fifo1 fifoa113(array_intp[12],wd1,rd113,d11327,dcmp113,e113,clk,reset);
fifo1 fifoa114(array_intp[13],wd1,rd114,d11427,dcmp114,e114,clk,reset);
comparator cmp17(dcmp113,dcmp114,gt17);
controlfifo cntrl17(gt17,e113,e114,rd113,rd114,sel17,wd27);
mux mux17(d11327,d11427,sel17,d27);
fifo1 fifoa115(array_intp[14],wd1,rd115,d11528,dcmp115,e115,clk,reset);
fifo1 fifoa116(array_intp[15],wd1,rd116,d11628,dcmp116,e116,clk,reset);
comparator cmp18(dcmp115,dcmp116,gt18);
controlfifo cntrl18(gt18,e115,e116,rd115,rd116,sel18,wd28);
mux mux18(d11528,d11628,sel18,d28);
fifo1 fifoa117(array_intp[16],wd1,rd117,d11729,dcmp117,e117,clk,reset);
fifo1 fifoa118(array_intp[17],wd1,rd118,d11829,dcmp118,e118,clk,reset);
fifo1 fifoa119(array_intp[18],wd1,rd119,d119210,dcmp119,e119,clk,reset);
fifo1 fifoa120(array_intp[19],wd1,rd120,d120210,dcmp120,e120,clk,reset);
fifo1 fifoa121(array_intp[20],wd1,rd121,d121211,dcmp121,e121,clk,reset);
fifo1 fifoa122(array_intp[21],wd1,rd122,d122211,dcmp122,e122,clk,reset);
fifo1 fifoa123(array_intp[22],wd1,rd123,d123212,dcmp123,e123,clk,reset);
fifo1 fifoa124(array_intp[23],wd1,rd124,d124212,dcmp124,e124,clk,reset);
fifo1 fifoa125(array_intp[24],wd1,rd125,d125213,dcmp125,e125,clk,reset);
fifo1 fifoa126(array_intp[25],wd1,rd126,d126213,dcmp126,e126,clk,reset);
fifo1 fifoa127(array_intp[26],wd1,rd127,d127214,dcmp127,e127,clk,reset);
fifo1 fifoa128(array_intp[27],wd1,rd128,d128214,dcmp128,e128,clk,reset);
fifo1 fifoa129(array_intp[28],wd1,rd129,d129215,dcmp129,e129,clk,reset);
fifo1 fifoa130(array_intp[29],wd1,rd130,d130215,dcmp130,e130,clk,reset);
fifo1 fifoa131(array_intp[30],wd1,rd131,d131216,dcmp131,e131,clk,reset);
fifo1 fifoa132(array_intp[31],wd1,rd132,d132216,dcmp132,e132,clk,reset);
comparator cmp19(dcmp117,dcmp118,gt19);
comparator cmp110(dcmp119,dcmp120,gt110);
comparator cmp111(dcmp121,dcmp122,gt111);
comparator cmp112(dcmp123,dcmp124,gt112);
comparator cmp113(dcmp125,dcmp126,gt113);
comparator cmp114(dcmp127,dcmp128,gt114);
comparator cmp115(dcmp129,dcmp130,gt115);
comparator cmp116(dcmp131,dcmp132,gt116);
controlfifo cntrl19(gt19,e117,e118,rd117,rd118,sel19,wd29);
controlfifo cntrl110(gt110,e119,e120,rd119,rd120,sel110,wd210);
controlfifo cntrl111(gt111,e121,e122,rd121,rd122,sel111,wd211);
controlfifo cntrl112(gt112,e123,e124,rd123,rd124,sel112,wd212);
controlfifo cntrl113(gt113,e125,e126,rd125,rd126,sel113,wd213);
controlfifo cntrl114(gt114,e127,e128,rd127,rd128,sel114,wd214);
controlfifo cntrl115(gt115,e129,e130,rd129,rd130,sel115,wd215);
controlfifo cntrl116(gt116,e131,e132,rd131,rd132,sel116,wd216);
mux mux19(d11729,d11829,sel19,d29);
mux mux110(d119210,d120210,sel110,d210);
mux mux111(d121211,d122211,sel111,d211);
mux mux112(d123212,d124212,sel112,d212);
mux mux113(d125213,d126213,sel113,d213);
mux mux114(d127214,d128214,sel114,d214);
mux mux115(d129215,d130215,sel115,d215);
mux mux116(d131216,d132216,sel116,d216);
fifo2 fifoa21(d21,wd21,rd21,d2131,dcmp21,e21,clk,reset);
fifo2 fifoa22(d22,wd22,rd22,d2231,dcmp22,e22,clk,reset);
comparator cmp21(dcmp21,dcmp22,gt21);
controlfifo cntrl21(gt21,e21,e22,rd21,rd22,sel21,wd31);
mux mux21(d2131,d2231,sel21,d31);
fifo2 fifoa23(d23,wd23,rd23,d2332,dcmp23,e23,clk,reset);
fifo2 fifoa24(d24,wd24,rd24,d2432,dcmp24,e24,clk,reset);
fifo2 fifoa25(d25,wd25,rd25,d2533,dcmp25,e25,clk,reset);
fifo2 fifoa26(d26,wd26,rd26,d2633,dcmp26,e26,clk,reset);
fifo2 fifoa27(d27,wd27,rd27,d2734,dcmp27,e27,clk,reset);
fifo2 fifoa28(d28,wd28,rd28,d2834,dcmp28,e28,clk,reset);
fifo2 fifoa29(d29,wd29,rd29,d2935,dcmp29,e29,clk,reset);
fifo2 fifoa210(d210,wd210,rd210,d21035,dcmp210,e210,clk,reset);
fifo2 fifoa211(d211,wd211,rd211,d21136,dcmp211,e211,clk,reset);
fifo2 fifoa212(d212,wd212,rd212,d21236,dcmp212,e212,clk,reset);
fifo2 fifoa213(d213,wd213,rd213,d21337,dcmp213,e213,clk,reset);
fifo2 fifoa214(d214,wd214,rd214,d21437,dcmp214,e214,clk,reset);
fifo2 fifoa215(d215,wd215,rd215,d21538,dcmp215,e215,clk,reset);
fifo2 fifoa216(d216,wd216,rd216,d21638,dcmp216,e216,clk,reset);
comparator cmp22(dcmp23,dcmp24,gt22);
comparator cmp23(dcmp25,dcmp26,gt23);
comparator cmp24(dcmp27,dcmp28,gt24);
comparator cmp25(dcmp29,dcmp210,gt25);
comparator cmp26(dcmp211,dcmp212,gt26);
comparator cmp27(dcmp213,dcmp214,gt27);
comparator cmp28(dcmp215,dcmp216,gt28);
controlfifo cntrl22(gt22,e23,e24,rd23,rd24,sel22,wd32);
controlfifo cntrl23(gt23,e25,e26,rd25,rd26,sel23,wd33);
controlfifo cntrl24(gt24,e27,e28,rd27,rd28,sel24,wd34);
controlfifo cntrl25(gt25,e29,e210,rd29,rd210,sel25,wd35);
controlfifo cntrl26(gt26,e211,e212,rd211,rd212,sel26,wd36);
controlfifo cntrl27(gt27,e213,e214,rd213,rd214,sel27,wd37);
controlfifo cntrl28(gt28,e215,e216,rd215,rd216,sel28,wd38);
mux mux22(d2332,d2432,sel22,d32);
mux mux23(d2533,d2633,sel23,d33);
mux mux24(d2734,d2834,sel24,d34);
mux mux25(d2935,d21035,sel25,d35);
mux mux26(d21136,d21236,sel26,d36);
mux mux27(d21337,d21437,sel27,d37);
mux mux28(d21538,d21638,sel28,d38);
fifo4 fifoa31(d31,wd31,rd31,d3141,dcmp31,e31,clk,reset);
fifo4 fifoa32(d32,wd32,rd32,d3241,dcmp32,e32,clk,reset);
fifo4 fifoa33(d33,wd33,rd33,d3342,dcmp33,e33,clk,reset);
fifo4 fifoa34(d34,wd34,rd34,d3442,dcmp34,e34,clk,reset);
fifo4 fifoa35(d35,wd35,rd35,d3543,dcmp35,e35,clk,reset);
fifo4 fifoa36(d36,wd36,rd36,d3643,dcmp36,e36,clk,reset);
fifo4 fifoa37(d37,wd37,rd37,d3744,dcmp37,e37,clk,reset);
fifo4 fifoa38(d38,wd38,rd38,d3844,dcmp38,e38,clk,reset);
comparator cmp31(dcmp31,dcmp32,gt31);
comparator cmp32(dcmp33,dcmp34,gt32);
comparator cmp33(dcmp35,dcmp36,gt33);
comparator cmp34(dcmp37,dcmp38,gt34);
controlfifo cntrl31(gt31,e31,e32,rd31,rd32,sel31,wd41);
controlfifo cntrl32(gt32,e33,e34,rd33,rd34,sel32,wd42);
controlfifo cntrl33(gt33,e35,e36,rd35,rd36,sel33,wd43);
controlfifo cntrl34(gt34,e37,e38,rd37,rd38,sel34,wd44);
mux mux31(d3141,d3241,sel31,d41);
mux mux32(d3342,d3442,sel32,d42);
mux mux33(d3543,d3643,sel33,d43);
mux mux34(d3744,d3844,sel34,d44);
fifo8 fifoa41(d41,wd41,rd41,d4141,dcmp41,e41,clk,reset);
fifo8 fifoa42(d42,wd42,rd42,d4241,dcmp42,e42,clk,reset);
fifo8 fifoa43(d43,wd43,rd43,d4342,dcmp43,e43,clk,reset);
fifo8 fifoa44(d44,wd44,rd44,d4442,dcmp44,e44,clk,reset);
comparator cmp41(dcmp41,dcmp42,gt41);
comparator cmp42(dcmp43,dcmp44,gt42);
controlfifo cntrl41(gt41,e41,e42,rd41,rd42,sel41,wd51);
controlfifo cntrl42(gt42,e43,e44,rd43,rd44,sel42,wd52);
mux mux41(d4141,d4241,sel41,d51);
mux mux42(d4342,d4442,sel42,d52);
fifo16 fifoa51(d51,wd51,rd51,d5161,dcmp51,e51,clk,reset);
fifo16 fifoa52(d52,wd52,rd52,d5261,dcmp52,e52,clk,reset);
comparator cmp51(dcmp51,dcmp52,gt51);
controlfifo cntrl51(gt51,e51,e52,rd51,rd52,sel51,wd61);
mux mux51(d5161,d5261,sel51,d61);
always@(posedge clk) begin
if (load) begin
l=0;
for (j=0; j<NUM_WORDS; j=j+1) begin
for (k=0; k<DATA_WIDTH; k=k+1)
begin
array_intp[j][k]<=array_in[l];
l=l+1;
end
end
end
end
always@(posedge clk) begin
if (wd61) begin
array_outp[p] = d61;
if (p==0)begin
f1=1;
$display("out");
m=0;
for (n=0; n<NUM_WORDS; n=n+1) begin
for (q=0; q<DATA_WIDTH; q=q+1)
begin
array_out [m] <= array_outp[n][q];
m=m+1;
end
end
end
p=p-1;
end
end
sortFsm sortfsmt(clk,reset,f1,wd1,load,Done);
always@(posedge clk) begin
done <= Done;
end
endmodule | module sortvals
# (parameter DATA_WIDTH = 32, NUM_WORDS = 32)
( input [DATA_WIDTH*NUM_WORDS-1:0] array_in,
input clk,input reset,
output reg [DATA_WIDTH*NUM_WORDS-1:0] array_out,
output reg done ); |
reg [DATA_WIDTH-1:0] array_intp [NUM_WORDS-1:0];
reg [DATA_WIDTH-1:0] array_outp [NUM_WORDS-1:0];
integer j,k,l,m,n,q;
reg [NUM_WORDS-1:0]p=31;
wire wd1,wd21,wd22;
wire rd11,rd12,rd13,rd14,rd21,rd22;
wire e11,e12,e13,e14,e21,e22;
wire gt11,gt12,gt21;
wire wd51,rd51,e51,wd52,rd52,e52,gt51,sel51,wd61,wd31,rd31,e31,wd32,rd32,e32,wd33,rd33,e33,wd34,rd34,e34,wd35,
rd35,e35,wd36,rd36,e36,wd37,rd37,e37,wd38,rd38,e38,
gt31,gt32,gt33,gt34,sel31,sel32,sel33,sel34,wd41,rd41,e41,wd42,rd42,e42,wd43,rd43,e43,wd44,rd44,e44,gt41,gt42,
sel41,sel42,wd23,rd23,e23,wd24,rd24,e24,wd25,rd25,
e25,wd26,rd26,e26,wd27,rd27,e27,wd28,rd28,e28,wd29,rd29,e29,wd210,rd210,e210,
wd211,rd211,e211,wd212,rd212,e212,wd213,rd213,e213,wd214,rd214,e214,wd215,rd215,e215,wd216,rd216,e216,
gt22,gt23,gt24,gt25,gt26,gt27,gt28,sel22,sel23,sel24,sel25,sel26,sel27,sel28,rd15,e15,rd16,e16,rd17,e17,rd18,e18,rd19,e19,rd110,e110,rd111,e111,rd112,e112,rd113,e113,rd114,e114,rd115,e115,rd116,e116,
gt13,gt14,gt15,gt16,gt17,gt18,sel13,sel14,sel15,sel16,sel17,sel18;
wire rd117,e117,rd118,e118,rd119,e119,rd120,e120,rd121,e121,rd122,e122,rd123,e123,rd124,e124,rd125,e125,rd126,e126,
rd127,e127,rd128,e128,rd129,e129,rd130,e130,rd131,e131,rd132,e132,gt19,gt110,gt111,gt112,gt113,gt114,gt115,gt116,
sel19,sel110,sel111,sel112,sel113,sel114,sel115,sel116;
wire [DATA_WIDTH-1:0] d41,d42,d43,d44,d4141,d61,dcmp41,d4241,dcmp42,d4342,dcmp43,d4442,dcmp44,
d51,d52,d5161,dcmp51,d5261,dcmp52,d31,d3141,dcmp31,d32,d3241,dcmp32,d33,d3342,dcmp33,d34,d3442,dcmp34,d35,d3543,dcmp35,d36,d3643,dcmp36,d37,d3744,dcmp37,d38,d3844,dcmp38,
d23,d210,d2332,dcmp23,d21035,dcmp210,d24,d211,d2432,dcmp24,d21136,dcmp211,d25,d212,d2533,dcmp25,d21236,dcmp212,
d26,d213,d2633,dcmp26,d21337,dcmp213,d27,d214,d2734,dcmp27,d21437,dcmp214,d28,d215,d2834,dcmp28,d21538,dcmp215,
d29,d216,d2935,dcmp29,d21638,dcmp216,d11729,dcmp117,d11829,dcmp118,d119210,dcmp119,d120210,dcmp120,d121211,dcmp121,d122211,dcmp122,d123212,dcmp123
,d124212,dcmp124,d125213,dcmp125,d126213,dcmp126,d127214,dcmp127,d128214,dcmp128,d129215,dcmp129
,d130215,dcmp130,d131216,dcmp131,d132216,dcmp132,d1523,dcmp15,d11025,dcmp110,d1623,dcmp16,d11126,dcmp111,d1724,dcmp17,d11226,dcmp112,d1824,dcmp18,d11327,dcmp113,
d1925,dcmp19,d11427,dcmp114,d11528,dcmp115,d11628,dcmp116;
reg f1;
wire Done,load;
wire [DATA_WIDTH-1:0] d1121,d1221,d1322,d1422,d21,d22,d2131,d2231;
wire [DATA_WIDTH-1:0] dcmp11,dcmp12,dcmp13,dcmp14,dcmp21,dcmp22;
wire sel11,sel12,sel21;
fifo1 fifoa11(array_intp[0],wd1,rd11,d1121,dcmp11,e11,clk,reset);
fifo1 fifoa12(array_intp[1],wd1,rd12,d1221,dcmp12,e12,clk,reset);
comparator cmp11(dcmp11,dcmp12,gt11);
controlfifo cntrl11(gt11,e11,e12,rd11,rd12,sel11,wd21);
mux mux11(d1121,d1221,sel11,d21);
fifo1 fifoa13(array_intp[2],wd1,rd13,d1322,dcmp13,e13,clk,reset);
fifo1 fifoa14(array_intp[3],wd1,rd14,d1422,dcmp14,e14,clk,reset);
comparator cmp12(dcmp13,dcmp14,gt12);
controlfifo cntrl12(gt12,e13,e14,rd13,rd14,sel12,wd22);
mux mux12(d1322,d1422,sel12,d22);
fifo1 fifoa15(array_intp[4],wd1,rd15,d1523,dcmp15,e15,clk,reset);
fifo1 fifoa16(array_intp[5],wd1,rd16,d1623,dcmp16,e16,clk,reset);
comparator cmp13(dcmp15,dcmp16,gt13);
controlfifo cntrl13(gt13,e15,e16,rd15,rd16,sel13,wd23);
mux mux13(d1523,d1623,sel13,d23);
fifo1 fifoa17(array_intp[6],wd1,rd17,d1724,dcmp17,e17,clk,reset);
fifo1 fifoa18(array_intp[7],wd1,rd18,d1824,dcmp18,e18,clk,reset);
comparator cmp14(dcmp17,dcmp18,gt14);
controlfifo cntrl14(gt14,e17,e18,rd17,rd18,sel14,wd24);
mux mux14(d1724,d1824,sel14,d24);
fifo1 fifoa19(array_intp[8],wd1,rd19,d1925,dcmp19,e19,clk,reset);
fifo1 fifoa110(array_intp[9],wd1,rd110,d11025,dcmp110,e110,clk,reset);
comparator cmp15(dcmp19,dcmp110,gt15);
controlfifo cntrl15(gt15,e19,e110,rd19,rd110,sel15,wd25);
mux mux15(d1925,d11025,sel15,d25);
fifo1 fifoa111(array_intp[10],wd1,rd111,d11126,dcmp111,e111,clk,reset);
fifo1 fifoa112(array_intp[11],wd1,rd112,d11226,dcmp112,e112,clk,reset);
comparator cmp16(dcmp111,dcmp112,gt16);
controlfifo cntrl16(gt16,e111,e112,rd111,rd112,sel16,wd26);
mux mux16(d11126,d11226,sel16,d26);
fifo1 fifoa113(array_intp[12],wd1,rd113,d11327,dcmp113,e113,clk,reset);
fifo1 fifoa114(array_intp[13],wd1,rd114,d11427,dcmp114,e114,clk,reset);
comparator cmp17(dcmp113,dcmp114,gt17);
controlfifo cntrl17(gt17,e113,e114,rd113,rd114,sel17,wd27);
mux mux17(d11327,d11427,sel17,d27);
fifo1 fifoa115(array_intp[14],wd1,rd115,d11528,dcmp115,e115,clk,reset);
fifo1 fifoa116(array_intp[15],wd1,rd116,d11628,dcmp116,e116,clk,reset);
comparator cmp18(dcmp115,dcmp116,gt18);
controlfifo cntrl18(gt18,e115,e116,rd115,rd116,sel18,wd28);
mux mux18(d11528,d11628,sel18,d28);
fifo1 fifoa117(array_intp[16],wd1,rd117,d11729,dcmp117,e117,clk,reset);
fifo1 fifoa118(array_intp[17],wd1,rd118,d11829,dcmp118,e118,clk,reset);
fifo1 fifoa119(array_intp[18],wd1,rd119,d119210,dcmp119,e119,clk,reset);
fifo1 fifoa120(array_intp[19],wd1,rd120,d120210,dcmp120,e120,clk,reset);
fifo1 fifoa121(array_intp[20],wd1,rd121,d121211,dcmp121,e121,clk,reset);
fifo1 fifoa122(array_intp[21],wd1,rd122,d122211,dcmp122,e122,clk,reset);
fifo1 fifoa123(array_intp[22],wd1,rd123,d123212,dcmp123,e123,clk,reset);
fifo1 fifoa124(array_intp[23],wd1,rd124,d124212,dcmp124,e124,clk,reset);
fifo1 fifoa125(array_intp[24],wd1,rd125,d125213,dcmp125,e125,clk,reset);
fifo1 fifoa126(array_intp[25],wd1,rd126,d126213,dcmp126,e126,clk,reset);
fifo1 fifoa127(array_intp[26],wd1,rd127,d127214,dcmp127,e127,clk,reset);
fifo1 fifoa128(array_intp[27],wd1,rd128,d128214,dcmp128,e128,clk,reset);
fifo1 fifoa129(array_intp[28],wd1,rd129,d129215,dcmp129,e129,clk,reset);
fifo1 fifoa130(array_intp[29],wd1,rd130,d130215,dcmp130,e130,clk,reset);
fifo1 fifoa131(array_intp[30],wd1,rd131,d131216,dcmp131,e131,clk,reset);
fifo1 fifoa132(array_intp[31],wd1,rd132,d132216,dcmp132,e132,clk,reset);
comparator cmp19(dcmp117,dcmp118,gt19);
comparator cmp110(dcmp119,dcmp120,gt110);
comparator cmp111(dcmp121,dcmp122,gt111);
comparator cmp112(dcmp123,dcmp124,gt112);
comparator cmp113(dcmp125,dcmp126,gt113);
comparator cmp114(dcmp127,dcmp128,gt114);
comparator cmp115(dcmp129,dcmp130,gt115);
comparator cmp116(dcmp131,dcmp132,gt116);
controlfifo cntrl19(gt19,e117,e118,rd117,rd118,sel19,wd29);
controlfifo cntrl110(gt110,e119,e120,rd119,rd120,sel110,wd210);
controlfifo cntrl111(gt111,e121,e122,rd121,rd122,sel111,wd211);
controlfifo cntrl112(gt112,e123,e124,rd123,rd124,sel112,wd212);
controlfifo cntrl113(gt113,e125,e126,rd125,rd126,sel113,wd213);
controlfifo cntrl114(gt114,e127,e128,rd127,rd128,sel114,wd214);
controlfifo cntrl115(gt115,e129,e130,rd129,rd130,sel115,wd215);
controlfifo cntrl116(gt116,e131,e132,rd131,rd132,sel116,wd216);
mux mux19(d11729,d11829,sel19,d29);
mux mux110(d119210,d120210,sel110,d210);
mux mux111(d121211,d122211,sel111,d211);
mux mux112(d123212,d124212,sel112,d212);
mux mux113(d125213,d126213,sel113,d213);
mux mux114(d127214,d128214,sel114,d214);
mux mux115(d129215,d130215,sel115,d215);
mux mux116(d131216,d132216,sel116,d216);
fifo2 fifoa21(d21,wd21,rd21,d2131,dcmp21,e21,clk,reset);
fifo2 fifoa22(d22,wd22,rd22,d2231,dcmp22,e22,clk,reset);
comparator cmp21(dcmp21,dcmp22,gt21);
controlfifo cntrl21(gt21,e21,e22,rd21,rd22,sel21,wd31);
mux mux21(d2131,d2231,sel21,d31);
fifo2 fifoa23(d23,wd23,rd23,d2332,dcmp23,e23,clk,reset);
fifo2 fifoa24(d24,wd24,rd24,d2432,dcmp24,e24,clk,reset);
fifo2 fifoa25(d25,wd25,rd25,d2533,dcmp25,e25,clk,reset);
fifo2 fifoa26(d26,wd26,rd26,d2633,dcmp26,e26,clk,reset);
fifo2 fifoa27(d27,wd27,rd27,d2734,dcmp27,e27,clk,reset);
fifo2 fifoa28(d28,wd28,rd28,d2834,dcmp28,e28,clk,reset);
fifo2 fifoa29(d29,wd29,rd29,d2935,dcmp29,e29,clk,reset);
fifo2 fifoa210(d210,wd210,rd210,d21035,dcmp210,e210,clk,reset);
fifo2 fifoa211(d211,wd211,rd211,d21136,dcmp211,e211,clk,reset);
fifo2 fifoa212(d212,wd212,rd212,d21236,dcmp212,e212,clk,reset);
fifo2 fifoa213(d213,wd213,rd213,d21337,dcmp213,e213,clk,reset);
fifo2 fifoa214(d214,wd214,rd214,d21437,dcmp214,e214,clk,reset);
fifo2 fifoa215(d215,wd215,rd215,d21538,dcmp215,e215,clk,reset);
fifo2 fifoa216(d216,wd216,rd216,d21638,dcmp216,e216,clk,reset);
comparator cmp22(dcmp23,dcmp24,gt22);
comparator cmp23(dcmp25,dcmp26,gt23);
comparator cmp24(dcmp27,dcmp28,gt24);
comparator cmp25(dcmp29,dcmp210,gt25);
comparator cmp26(dcmp211,dcmp212,gt26);
comparator cmp27(dcmp213,dcmp214,gt27);
comparator cmp28(dcmp215,dcmp216,gt28);
controlfifo cntrl22(gt22,e23,e24,rd23,rd24,sel22,wd32);
controlfifo cntrl23(gt23,e25,e26,rd25,rd26,sel23,wd33);
controlfifo cntrl24(gt24,e27,e28,rd27,rd28,sel24,wd34);
controlfifo cntrl25(gt25,e29,e210,rd29,rd210,sel25,wd35);
controlfifo cntrl26(gt26,e211,e212,rd211,rd212,sel26,wd36);
controlfifo cntrl27(gt27,e213,e214,rd213,rd214,sel27,wd37);
controlfifo cntrl28(gt28,e215,e216,rd215,rd216,sel28,wd38);
mux mux22(d2332,d2432,sel22,d32);
mux mux23(d2533,d2633,sel23,d33);
mux mux24(d2734,d2834,sel24,d34);
mux mux25(d2935,d21035,sel25,d35);
mux mux26(d21136,d21236,sel26,d36);
mux mux27(d21337,d21437,sel27,d37);
mux mux28(d21538,d21638,sel28,d38);
fifo4 fifoa31(d31,wd31,rd31,d3141,dcmp31,e31,clk,reset);
fifo4 fifoa32(d32,wd32,rd32,d3241,dcmp32,e32,clk,reset);
fifo4 fifoa33(d33,wd33,rd33,d3342,dcmp33,e33,clk,reset);
fifo4 fifoa34(d34,wd34,rd34,d3442,dcmp34,e34,clk,reset);
fifo4 fifoa35(d35,wd35,rd35,d3543,dcmp35,e35,clk,reset);
fifo4 fifoa36(d36,wd36,rd36,d3643,dcmp36,e36,clk,reset);
fifo4 fifoa37(d37,wd37,rd37,d3744,dcmp37,e37,clk,reset);
fifo4 fifoa38(d38,wd38,rd38,d3844,dcmp38,e38,clk,reset);
comparator cmp31(dcmp31,dcmp32,gt31);
comparator cmp32(dcmp33,dcmp34,gt32);
comparator cmp33(dcmp35,dcmp36,gt33);
comparator cmp34(dcmp37,dcmp38,gt34);
controlfifo cntrl31(gt31,e31,e32,rd31,rd32,sel31,wd41);
controlfifo cntrl32(gt32,e33,e34,rd33,rd34,sel32,wd42);
controlfifo cntrl33(gt33,e35,e36,rd35,rd36,sel33,wd43);
controlfifo cntrl34(gt34,e37,e38,rd37,rd38,sel34,wd44);
mux mux31(d3141,d3241,sel31,d41);
mux mux32(d3342,d3442,sel32,d42);
mux mux33(d3543,d3643,sel33,d43);
mux mux34(d3744,d3844,sel34,d44);
fifo8 fifoa41(d41,wd41,rd41,d4141,dcmp41,e41,clk,reset);
fifo8 fifoa42(d42,wd42,rd42,d4241,dcmp42,e42,clk,reset);
fifo8 fifoa43(d43,wd43,rd43,d4342,dcmp43,e43,clk,reset);
fifo8 fifoa44(d44,wd44,rd44,d4442,dcmp44,e44,clk,reset);
comparator cmp41(dcmp41,dcmp42,gt41);
comparator cmp42(dcmp43,dcmp44,gt42);
controlfifo cntrl41(gt41,e41,e42,rd41,rd42,sel41,wd51);
controlfifo cntrl42(gt42,e43,e44,rd43,rd44,sel42,wd52);
mux mux41(d4141,d4241,sel41,d51);
mux mux42(d4342,d4442,sel42,d52);
fifo16 fifoa51(d51,wd51,rd51,d5161,dcmp51,e51,clk,reset);
fifo16 fifoa52(d52,wd52,rd52,d5261,dcmp52,e52,clk,reset);
comparator cmp51(dcmp51,dcmp52,gt51);
controlfifo cntrl51(gt51,e51,e52,rd51,rd52,sel51,wd61);
mux mux51(d5161,d5261,sel51,d61);
always@(posedge clk) begin
if (load) begin
l=0;
for (j=0; j<NUM_WORDS; j=j+1) begin
for (k=0; k<DATA_WIDTH; k=k+1)
begin
array_intp[j][k]<=array_in[l];
l=l+1;
end
end
end
end
always@(posedge clk) begin
if (wd61) begin
array_outp[p] = d61;
if (p==0)begin
f1=1;
$display("out");
m=0;
for (n=0; n<NUM_WORDS; n=n+1) begin
for (q=0; q<DATA_WIDTH; q=q+1)
begin
array_out [m] <= array_outp[n][q];
m=m+1;
end
end
end
p=p-1;
end
end
sortFsm sortfsmt(clk,reset,f1,wd1,load,Done);
always@(posedge clk) begin
done <= Done;
end
endmodule | 0 |
138,933 | data/full_repos/permissive/86540631/Decoder/testbench_decoder.v | 86,540,631 | testbench_decoder.v | v | 21 | 76 | [] | [] | [] | null | line:18: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86540631/Decoder/testbench_decoder.v:9: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86540631/Decoder/testbench_decoder.v:11: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86540631/Decoder/testbench_decoder.v:13: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86540631/Decoder/testbench_decoder.v:15: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86540631/Decoder/testbench_decoder.v:17: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: data/full_repos/permissive/86540631/Decoder/testbench_decoder.v:5: Cannot find file containing module: \'decoder_dataflow\'\n decoder_dataflow U0(out, in); \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86540631/Decoder,data/full_repos/permissive/86540631/decoder_dataflow\n data/full_repos/permissive/86540631/Decoder,data/full_repos/permissive/86540631/decoder_dataflow.v\n data/full_repos/permissive/86540631/Decoder,data/full_repos/permissive/86540631/decoder_dataflow.sv\n decoder_dataflow\n decoder_dataflow.v\n decoder_dataflow.sv\n obj_dir/decoder_dataflow\n obj_dir/decoder_dataflow.v\n obj_dir/decoder_dataflow.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,055 | module | module test_decoder;
reg [1:0] in;
wire [3:0] out;
decoder_dataflow U0(out, in);
initial begin
#100
in = 2'b00;
#100
in = 2'b01;
#100
in = 2'b10;
#100
in = 2'b11;
#100
$finish;
end
endmodule | module test_decoder; |
reg [1:0] in;
wire [3:0] out;
decoder_dataflow U0(out, in);
initial begin
#100
in = 2'b00;
#100
in = 2'b01;
#100
in = 2'b10;
#100
in = 2'b11;
#100
$finish;
end
endmodule | 1 |
138,934 | data/full_repos/permissive/86540631/FAST-9 Feature Detection/FD_Datapath.v | 86,540,631 | FD_Datapath.v | v | 66 | 122 | [] | [] | [] | [(1, 66)] | null | null | 1: b'%Error: Cannot find file containing module: Feature\n ... Looked in:\n data/full_repos/permissive/86540631/FAST-9/Feature\n data/full_repos/permissive/86540631/FAST-9/Feature.v\n data/full_repos/permissive/86540631/FAST-9/Feature.sv\n Feature\n Feature.v\n Feature.sv\n obj_dir/Feature\n obj_dir/Feature.v\n obj_dir/Feature.sv\n%Error: Cannot find file containing module: Detection,data/full_repos/permissive/86540631\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/FAST-9\n%Error: Cannot find file containing module: Detection/FD_Datapath.v\n%Error: Exiting due to 4 error(s)\n' | 304,058 | module | module FD_Datapath(refPixel, adjPixel, thres, isCorner);
input [7:0] refPixel;
input [127:0] adjPixel;
input [7:0] thres;
output isCorner;
wire [8:0] lower;
wire [8:0] upper;
wire [31:0] compare;
assign lower = ((refPixel - thres) > 255) ? 8'd0 : (refPixel - thres);
assign upper = ((refPixel + thres) > 255) ? 8'd255 : (refPixel + thres);
assign compare[1:0] = ({1'b0, adjPixel[127:120]} < lower) ? 2'b01 : ({1'b0, adjPixel[127:120]} > upper) ? 2'b10 : 2'b00;
assign compare[3:2] = ({1'b0, adjPixel[119:112]} < lower) ? 2'b01 : ({1'b0, adjPixel[119:112]} > upper) ? 2'b10 : 2'b00;
assign compare[5:4] = ({1'b0, adjPixel[111:104]} < lower) ? 2'b01 : ({1'b0, adjPixel[111:104]} > upper) ? 2'b10 : 2'b00;
assign compare[7:6] = ({1'b0, adjPixel[103:96]} < lower) ? 2'b01 : ({1'b0, adjPixel[103:96]} > upper) ? 2'b10 : 2'b00;
assign compare[9:8] = ({1'b0, adjPixel[95:88]} < lower) ? 2'b01 : ({1'b0, adjPixel[95:88]} > upper) ? 2'b10 : 2'b00;
assign compare[11:10] = ({1'b0, adjPixel[87:80]} < lower) ? 2'b01 : ({1'b0, adjPixel[87:80]} > upper) ? 2'b10 : 2'b00;
assign compare[13:12] = ({1'b0, adjPixel[79:72]} < lower) ? 2'b01 : ({1'b0, adjPixel[79:72]} > upper) ? 2'b10 : 2'b00;
assign compare[15:14] = ({1'b0, adjPixel[71:64]} < lower) ? 2'b01 : ({1'b0, adjPixel[71:64]} > upper) ? 2'b10 : 2'b00;
assign compare[17:16] = ({1'b0, adjPixel[63:56]} < lower) ? 2'b01 : ({1'b0, adjPixel[63:56]} > upper) ? 2'b10 : 2'b00;
assign compare[19:18] = ({1'b0, adjPixel[55:48]} < lower) ? 2'b01 : ({1'b0, adjPixel[55:48]} > upper) ? 2'b10 : 2'b00;
assign compare[21:20] = ({1'b0, adjPixel[47:40]} < lower) ? 2'b01 : ({1'b0, adjPixel[47:40]} > upper) ? 2'b10 : 2'b00;
assign compare[23:22] = ({1'b0, adjPixel[39:32]} < lower) ? 2'b01 : ({1'b0, adjPixel[39:32]} > upper) ? 2'b10 : 2'b00;
assign compare[25:24] = ({1'b0, adjPixel[31:24]} < lower) ? 2'b01 : ({1'b0, adjPixel[31:24]} > upper) ? 2'b10 : 2'b00;
assign compare[27:26] = ({1'b0, adjPixel[23:16]} < lower) ? 2'b01 : ({1'b0, adjPixel[23:16]} > upper) ? 2'b10 : 2'b00;
assign compare[29:28] = ({1'b0, adjPixel[15:8]} < lower) ? 2'b01 : ({1'b0, adjPixel[15:8]} > upper) ? 2'b10 : 2'b00;
assign compare[31:30] = ({1'b0, adjPixel[7:0]} < lower) ? 2'b01 : ({1'b0, adjPixel[7:0]} > upper) ? 2'b10 : 2'b00;
assign isCorner =
(compare[31:14] == 18'h15555) ? 1'b1 :
(compare[31:14] == 18'h2AAAA) ? 1'b1 :
(compare[29:12] == 18'h15555) ? 1'b1 :
(compare[29:12] == 18'h2AAAA) ? 1'b1 :
(compare[27:10] == 18'h15555) ? 1'b1 :
(compare[27:10] == 18'h2AAAA) ? 1'b1 :
(compare[25:8] == 18'h15555) ? 1'b1 :
(compare[25:8] == 18'h2AAAA) ? 1'b1 :
(compare[23:6] == 18'h15555) ? 1'b1 :
(compare[23:6] == 18'h2AAAA) ? 1'b1 :
(compare[21:4] == 18'h15555) ? 1'b1 :
(compare[21:4] == 18'h2AAAA) ? 1'b1 :
(compare[19:2] == 18'h15555) ? 1'b1 :
(compare[19:2] == 18'h2AAAA) ? 1'b1 :
(compare[17:0] == 18'h15555) ? 1'b1 :
(compare[17:0] == 18'h2AAAA) ? 1'b1 :
((compare[31:30] == 2'b10) && (compare[15:0] == 16'hAAAA)) ? 1'b1 :
((compare[31:30] == 2'b01) && (compare[15:0] == 16'h5555)) ? 1'b1 :
((compare[31:28] == 4'hA) && (compare[13:0] == 14'h2AAA)) ? 1'b1 :
((compare[31:28] == 4'h5) && (compare[13:0] == 14'h1555)) ? 1'b1 :
((compare[31:26] == 6'h2A) && (compare[11:0] == 12'hAAA)) ? 1'b1 :
((compare[31:26] == 6'h15) && (compare[11:0] == 12'h555)) ? 1'b1 :
((compare[31:24] == 8'hAA) && (compare[9:0] == 10'h2AA)) ? 1'b1 :
((compare[31:24] == 8'h55) && (compare[9:0] == 10'h155)) ? 1'b1 :
((compare[31:22] == 10'h2AA) && (compare[7:0] == 8'hAA)) ? 1'b1 :
((compare[31:22] == 10'h155) && (compare[7:0] == 8'h55)) ? 1'b1 :
((compare[31:20] == 12'hAAA) && (compare[5:0] == 6'h2A)) ? 1'b1 :
((compare[31:20] == 12'h555) && (compare[5:0] == 6'h15)) ? 1'b1 :
((compare[31:18] == 14'h2AAA) && (compare[3:0] == 4'hA)) ? 1'b1 :
((compare[31:18] == 14'h1555) && (compare[3:0] == 4'h5)) ? 1'b1 :
((compare[31:16] == 16'hAAAA) && (compare[1:0] == 2'b10)) ? 1'b1 :
((compare[31:16] == 16'h5555) && (compare[1:0] == 2'b01)) ? 1'b1 : 1'b0;
endmodule | module FD_Datapath(refPixel, adjPixel, thres, isCorner); |
input [7:0] refPixel;
input [127:0] adjPixel;
input [7:0] thres;
output isCorner;
wire [8:0] lower;
wire [8:0] upper;
wire [31:0] compare;
assign lower = ((refPixel - thres) > 255) ? 8'd0 : (refPixel - thres);
assign upper = ((refPixel + thres) > 255) ? 8'd255 : (refPixel + thres);
assign compare[1:0] = ({1'b0, adjPixel[127:120]} < lower) ? 2'b01 : ({1'b0, adjPixel[127:120]} > upper) ? 2'b10 : 2'b00;
assign compare[3:2] = ({1'b0, adjPixel[119:112]} < lower) ? 2'b01 : ({1'b0, adjPixel[119:112]} > upper) ? 2'b10 : 2'b00;
assign compare[5:4] = ({1'b0, adjPixel[111:104]} < lower) ? 2'b01 : ({1'b0, adjPixel[111:104]} > upper) ? 2'b10 : 2'b00;
assign compare[7:6] = ({1'b0, adjPixel[103:96]} < lower) ? 2'b01 : ({1'b0, adjPixel[103:96]} > upper) ? 2'b10 : 2'b00;
assign compare[9:8] = ({1'b0, adjPixel[95:88]} < lower) ? 2'b01 : ({1'b0, adjPixel[95:88]} > upper) ? 2'b10 : 2'b00;
assign compare[11:10] = ({1'b0, adjPixel[87:80]} < lower) ? 2'b01 : ({1'b0, adjPixel[87:80]} > upper) ? 2'b10 : 2'b00;
assign compare[13:12] = ({1'b0, adjPixel[79:72]} < lower) ? 2'b01 : ({1'b0, adjPixel[79:72]} > upper) ? 2'b10 : 2'b00;
assign compare[15:14] = ({1'b0, adjPixel[71:64]} < lower) ? 2'b01 : ({1'b0, adjPixel[71:64]} > upper) ? 2'b10 : 2'b00;
assign compare[17:16] = ({1'b0, adjPixel[63:56]} < lower) ? 2'b01 : ({1'b0, adjPixel[63:56]} > upper) ? 2'b10 : 2'b00;
assign compare[19:18] = ({1'b0, adjPixel[55:48]} < lower) ? 2'b01 : ({1'b0, adjPixel[55:48]} > upper) ? 2'b10 : 2'b00;
assign compare[21:20] = ({1'b0, adjPixel[47:40]} < lower) ? 2'b01 : ({1'b0, adjPixel[47:40]} > upper) ? 2'b10 : 2'b00;
assign compare[23:22] = ({1'b0, adjPixel[39:32]} < lower) ? 2'b01 : ({1'b0, adjPixel[39:32]} > upper) ? 2'b10 : 2'b00;
assign compare[25:24] = ({1'b0, adjPixel[31:24]} < lower) ? 2'b01 : ({1'b0, adjPixel[31:24]} > upper) ? 2'b10 : 2'b00;
assign compare[27:26] = ({1'b0, adjPixel[23:16]} < lower) ? 2'b01 : ({1'b0, adjPixel[23:16]} > upper) ? 2'b10 : 2'b00;
assign compare[29:28] = ({1'b0, adjPixel[15:8]} < lower) ? 2'b01 : ({1'b0, adjPixel[15:8]} > upper) ? 2'b10 : 2'b00;
assign compare[31:30] = ({1'b0, adjPixel[7:0]} < lower) ? 2'b01 : ({1'b0, adjPixel[7:0]} > upper) ? 2'b10 : 2'b00;
assign isCorner =
(compare[31:14] == 18'h15555) ? 1'b1 :
(compare[31:14] == 18'h2AAAA) ? 1'b1 :
(compare[29:12] == 18'h15555) ? 1'b1 :
(compare[29:12] == 18'h2AAAA) ? 1'b1 :
(compare[27:10] == 18'h15555) ? 1'b1 :
(compare[27:10] == 18'h2AAAA) ? 1'b1 :
(compare[25:8] == 18'h15555) ? 1'b1 :
(compare[25:8] == 18'h2AAAA) ? 1'b1 :
(compare[23:6] == 18'h15555) ? 1'b1 :
(compare[23:6] == 18'h2AAAA) ? 1'b1 :
(compare[21:4] == 18'h15555) ? 1'b1 :
(compare[21:4] == 18'h2AAAA) ? 1'b1 :
(compare[19:2] == 18'h15555) ? 1'b1 :
(compare[19:2] == 18'h2AAAA) ? 1'b1 :
(compare[17:0] == 18'h15555) ? 1'b1 :
(compare[17:0] == 18'h2AAAA) ? 1'b1 :
((compare[31:30] == 2'b10) && (compare[15:0] == 16'hAAAA)) ? 1'b1 :
((compare[31:30] == 2'b01) && (compare[15:0] == 16'h5555)) ? 1'b1 :
((compare[31:28] == 4'hA) && (compare[13:0] == 14'h2AAA)) ? 1'b1 :
((compare[31:28] == 4'h5) && (compare[13:0] == 14'h1555)) ? 1'b1 :
((compare[31:26] == 6'h2A) && (compare[11:0] == 12'hAAA)) ? 1'b1 :
((compare[31:26] == 6'h15) && (compare[11:0] == 12'h555)) ? 1'b1 :
((compare[31:24] == 8'hAA) && (compare[9:0] == 10'h2AA)) ? 1'b1 :
((compare[31:24] == 8'h55) && (compare[9:0] == 10'h155)) ? 1'b1 :
((compare[31:22] == 10'h2AA) && (compare[7:0] == 8'hAA)) ? 1'b1 :
((compare[31:22] == 10'h155) && (compare[7:0] == 8'h55)) ? 1'b1 :
((compare[31:20] == 12'hAAA) && (compare[5:0] == 6'h2A)) ? 1'b1 :
((compare[31:20] == 12'h555) && (compare[5:0] == 6'h15)) ? 1'b1 :
((compare[31:18] == 14'h2AAA) && (compare[3:0] == 4'hA)) ? 1'b1 :
((compare[31:18] == 14'h1555) && (compare[3:0] == 4'h5)) ? 1'b1 :
((compare[31:16] == 16'hAAAA) && (compare[1:0] == 2'b10)) ? 1'b1 :
((compare[31:16] == 16'h5555) && (compare[1:0] == 2'b01)) ? 1'b1 : 1'b0;
endmodule | 1 |
138,936 | data/full_repos/permissive/86540631/FAST-9 Feature Detection/FD_Top.v | 86,540,631 | FD_Top.v | v | 61 | 77 | [] | [] | [] | [(1, 61)] | null | null | 1: b'%Error: Cannot find file containing module: Feature\n ... Looked in:\n data/full_repos/permissive/86540631/FAST-9/Feature\n data/full_repos/permissive/86540631/FAST-9/Feature.v\n data/full_repos/permissive/86540631/FAST-9/Feature.sv\n Feature\n Feature.v\n Feature.sv\n obj_dir/Feature\n obj_dir/Feature.v\n obj_dir/Feature.sv\n%Error: Cannot find file containing module: Detection,data/full_repos/permissive/86540631\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/FAST-9\n%Error: Cannot find file containing module: Detection/FD_Top.v\n%Error: Exiting due to 4 error(s)\n' | 304,061 | module | module FD_Top (clock, nReset, isCorner, refAddr, refPixel, adjPixel, thres);
input clock;
input nReset;
output isCorner;
output [14:0] refAddr;
output [7:0] refPixel;
output [127:0] adjPixel;
output [7:0] thres;
wire readen;
wire [4:0] adjNumber;
wire [4:0] regAddr;
wire [14:0] sramAddr;
wire [7:0] sramData;
FD_Controller controller(
.clock(clock),
.nReset(nReset),
.refAddr(refAddr),
.adjNumber(adjNumber),
.regAddr(regAddr),
.readen(readen)
);
FD_AddrCal addrCal(
.refAddr(refAddr),
.adjNumber(adjNumber),
.sramAddr(sramAddr)
);
SRAM sram(
.clock(clock),
.address(sramAddr),
.data(8'bx),
.wren(1'b0),
.q(sramData)
);
FD_Reg fd_reg(
.clock(clock),
.nReset(nReset),
.readen(readen),
.regAddr(regAddr),
.sramData(sramData),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres)
);
FD_Datapath datapath(
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres),
.isCorner(isCorner)
);
endmodule | module FD_Top (clock, nReset, isCorner, refAddr, refPixel, adjPixel, thres); |
input clock;
input nReset;
output isCorner;
output [14:0] refAddr;
output [7:0] refPixel;
output [127:0] adjPixel;
output [7:0] thres;
wire readen;
wire [4:0] adjNumber;
wire [4:0] regAddr;
wire [14:0] sramAddr;
wire [7:0] sramData;
FD_Controller controller(
.clock(clock),
.nReset(nReset),
.refAddr(refAddr),
.adjNumber(adjNumber),
.regAddr(regAddr),
.readen(readen)
);
FD_AddrCal addrCal(
.refAddr(refAddr),
.adjNumber(adjNumber),
.sramAddr(sramAddr)
);
SRAM sram(
.clock(clock),
.address(sramAddr),
.data(8'bx),
.wren(1'b0),
.q(sramData)
);
FD_Reg fd_reg(
.clock(clock),
.nReset(nReset),
.readen(readen),
.regAddr(regAddr),
.sramData(sramData),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres)
);
FD_Datapath datapath(
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres),
.isCorner(isCorner)
);
endmodule | 1 |
138,937 | data/full_repos/permissive/86540631/FAST-9 Feature Detection/Testbench_SramTest.v | 86,540,631 | Testbench_SramTest.v | v | 32 | 53 | [] | [] | [] | null | line:30: before: "$" | null | 1: b'%Error: Cannot find file containing module: Feature\n ... Looked in:\n data/full_repos/permissive/86540631/FAST-9/Feature\n data/full_repos/permissive/86540631/FAST-9/Feature.v\n data/full_repos/permissive/86540631/FAST-9/Feature.sv\n Feature\n Feature.v\n Feature.sv\n obj_dir/Feature\n obj_dir/Feature.v\n obj_dir/Feature.sv\n%Error: Cannot find file containing module: Detection,data/full_repos/permissive/86540631\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/FAST-9\n%Error: Cannot find file containing module: Detection/Testbench_SramTest.v\n%Error: Exiting due to 4 error(s)\n' | 304,063 | module | module Testbench_SramTest;
reg clock;
reg wren;
reg [14:0] address;
reg [7:0] data;
wire [7:0] read;
always begin
#50 clock = ~clock;
$display($time, "%d : %b : %h", read, read, read);
end
always @ (posedge clock)
address <= address + 1;
SRAM sram(
.clock(clock),
.address(address),
.data(data),
.wren(wren),
.q(read)
);
initial begin
wren = 1'b0;
clock = 1'b0;
address = 15'b0;
data = 8'b00110000;
#21600 $finish;
end
endmodule | module Testbench_SramTest; |
reg clock;
reg wren;
reg [14:0] address;
reg [7:0] data;
wire [7:0] read;
always begin
#50 clock = ~clock;
$display($time, "%d : %b : %h", read, read, read);
end
always @ (posedge clock)
address <= address + 1;
SRAM sram(
.clock(clock),
.address(address),
.data(data),
.wren(wren),
.q(read)
);
initial begin
wren = 1'b0;
clock = 1'b0;
address = 15'b0;
data = 8'b00110000;
#21600 $finish;
end
endmodule | 1 |
138,938 | data/full_repos/permissive/86540631/FAST-9 Feature Score/FAST9_Top.v | 86,540,631 | FAST9_Top.v | v | 35 | 49 | [] | [] | [] | [(1, 35)] | null | null | 1: b'%Error: Cannot find file containing module: Feature\n ... Looked in:\n data/full_repos/permissive/86540631/FAST-9/Feature\n data/full_repos/permissive/86540631/FAST-9/Feature.v\n data/full_repos/permissive/86540631/FAST-9/Feature.sv\n Feature\n Feature.v\n Feature.sv\n obj_dir/Feature\n obj_dir/Feature.v\n obj_dir/Feature.sv\n%Error: Cannot find file containing module: Score,data/full_repos/permissive/86540631\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/FAST-9\n%Error: Cannot find file containing module: Score/FAST9_Top.v\n%Error: Exiting due to 4 error(s)\n' | 304,064 | module | module FAST9_Top (clock, nReset);
input clock;
input nReset;
wire isCorner;
wire [31:0] compare;
wire [14:0] refAddr;
wire [7:0] refPixel;
wire [127:0] adjPixel;
wire [7:0] thres;
FD_Top fd(
.clock(clock),
.nReset(nReset),
.isCorner(isCorner),
.refAddr(refAddr),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres),
.compare(compare)
);
FS_Top fs(
.clock(clock),
.nReset(nReset),
.isCorner(isCorner),
.compare(compare),
.refAddr(refAddr),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres)
);
endmodule | module FAST9_Top (clock, nReset); |
input clock;
input nReset;
wire isCorner;
wire [31:0] compare;
wire [14:0] refAddr;
wire [7:0] refPixel;
wire [127:0] adjPixel;
wire [7:0] thres;
FD_Top fd(
.clock(clock),
.nReset(nReset),
.isCorner(isCorner),
.refAddr(refAddr),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres),
.compare(compare)
);
FS_Top fs(
.clock(clock),
.nReset(nReset),
.isCorner(isCorner),
.compare(compare),
.refAddr(refAddr),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres)
);
endmodule | 1 |
138,939 | data/full_repos/permissive/86540631/FAST-9 Feature Score/FS_Datapath.v | 86,540,631 | FS_Datapath.v | v | 121 | 98 | [] | [] | [] | [(5, 121)] | null | null | 1: b'%Error: Cannot find file containing module: Feature\n ... Looked in:\n data/full_repos/permissive/86540631/FAST-9/Feature\n data/full_repos/permissive/86540631/FAST-9/Feature.v\n data/full_repos/permissive/86540631/FAST-9/Feature.sv\n Feature\n Feature.v\n Feature.sv\n obj_dir/Feature\n obj_dir/Feature.v\n obj_dir/Feature.sv\n%Error: Cannot find file containing module: Score,data/full_repos/permissive/86540631\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/FAST-9\n%Error: Cannot find file containing module: Score/FS_Datapath.v\n%Error: Exiting due to 4 error(s)\n' | 304,065 | module | module FS_Datapath (isCorner, compare, refPixel, adjPixel, thres, wren, scoreValue);
input isCorner;
input [31:0] compare;
input [7:0] refPixel;
input [127:0] adjPixel;
input [7:0] thres;
output wren;
output [7:0] scoreValue;
wire [11:0] sBright;
wire [11:0] sDark;
assign sDark =
((compare[31:30] == `DARK) ?
(((refPixel - adjPixel[127:120]) > 255) ?
(adjPixel[127:120] - refPixel - thres) : (refPixel - adjPixel[127:120] - thres)) : 12'b0) +
((compare[29:28] == `DARK) ?
(((refPixel - adjPixel[119:112]) > 255) ?
(adjPixel[119:112] - refPixel - thres) : (refPixel - adjPixel[119:112] - thres)) : 12'b0) +
((compare[27:26] == `DARK) ?
(((refPixel - adjPixel[111:104]) > 255) ?
(adjPixel[111:104] - refPixel - thres) : (refPixel - adjPixel[111:104] - thres)) : 12'b0) +
((compare[25:24] == `DARK) ?
(((refPixel - adjPixel[103:96]) > 255) ?
(adjPixel[103:96] - refPixel - thres) : (refPixel - adjPixel[103:96] - thres)) : 12'b0) +
((compare[23:22] == `DARK) ?
(((refPixel - adjPixel[95:88]) > 255) ?
(adjPixel[95:88] - refPixel - thres) : (refPixel - adjPixel[95:88] - thres)) : 12'b0) +
((compare[21:20] == `DARK) ?
(((refPixel - adjPixel[87:80]) > 255) ?
(adjPixel[87:80] - refPixel - thres) : (refPixel - adjPixel[87:80] - thres)) : 12'b0) +
((compare[19:18] == `DARK) ?
(((refPixel - adjPixel[79:72]) > 255) ?
(adjPixel[79:72] - refPixel - thres) : (refPixel - adjPixel[79:72] - thres)) : 12'b0) +
((compare[17:16] == `DARK) ?
(((refPixel - adjPixel[71:64]) > 255) ?
(adjPixel[71:64] - refPixel - thres) : (refPixel - adjPixel[71:64] - thres)) : 12'b0) +
((compare[15:14] == `DARK) ?
(((refPixel - adjPixel[63:56]) > 255) ?
(adjPixel[63:56] - refPixel - thres) : (refPixel - adjPixel[63:56] - thres)) : 12'b0) +
((compare[13:12] == `DARK) ?
(((refPixel - adjPixel[55:48]) > 255) ?
(adjPixel[55:48] - refPixel - thres) : (refPixel - adjPixel[55:48] - thres)) : 12'b0) +
((compare[11:10] == `DARK) ?
(((refPixel - adjPixel[47:40]) > 255) ?
(adjPixel[47:40] - refPixel - thres) : (refPixel - adjPixel[47:40] - thres)) : 12'b0) +
((compare[9:8] == `DARK) ?
(((refPixel - adjPixel[39:32]) > 255) ?
(adjPixel[39:32] - refPixel - thres) : (refPixel - adjPixel[39:32] - thres)) : 12'b0) +
((compare[7:6] == `DARK) ?
(((refPixel - adjPixel[31:24]) > 255) ?
(adjPixel[31:24] - refPixel - thres) : (refPixel - adjPixel[31:24] - thres)) : 12'b0) +
((compare[5:4] == `DARK) ?
(((refPixel - adjPixel[23:16]) > 255) ?
(adjPixel[23:16] - refPixel - thres) : (refPixel - adjPixel[23:16] - thres)) : 12'b0) +
((compare[3:2] == `DARK) ?
(((refPixel - adjPixel[15:8]) > 255) ?
(adjPixel[15:8] - refPixel - thres) : (refPixel - adjPixel[15:8] - thres)) : 12'b0) +
((compare[1:0] == `DARK) ?
(((refPixel - adjPixel[7:0]) > 255) ?
(adjPixel[7:0] - refPixel - thres) : (refPixel - adjPixel[7:0] - thres)) : 12'b0);
assign sBright =
((compare[31:30] == `BRIGHT) ?
(((adjPixel[127:120] - refPixel) > 255) ?
(refPixel - adjPixel[127:120] - thres) : (adjPixel[127:120] - refPixel - thres)) : 12'b0) +
((compare[29:28] == `BRIGHT) ?
(((adjPixel[119:112] - refPixel) > 255) ?
(refPixel - adjPixel[119:112] - thres) : (adjPixel[119:112] - refPixel - thres)) : 12'b0) +
((compare[27:26] == `BRIGHT) ?
(((adjPixel[111:104] - refPixel) > 255) ?
(refPixel - adjPixel[111:104] - thres) : (adjPixel[111:104] - refPixel - thres)) : 12'b0) +
((compare[25:24] == `BRIGHT) ?
(((adjPixel[103:96] - refPixel) > 255) ?
(refPixel - adjPixel[103:96] - thres) : (adjPixel[103:96] - refPixel - thres)) : 12'b0) +
((compare[23:22] == `BRIGHT) ?
(((adjPixel[95:88] - refPixel) > 255) ?
(refPixel - adjPixel[95:88] - thres) : (adjPixel[95:88] - refPixel - thres)) : 12'b0) +
((compare[21:20] == `BRIGHT) ?
(((adjPixel[87:80] - refPixel) > 255) ?
(refPixel - adjPixel[87:80] - thres) : (adjPixel[87:80] - refPixel - thres)) : 12'b0) +
((compare[19:18] == `BRIGHT) ?
(((adjPixel[79:72] - refPixel) > 255) ?
(refPixel - adjPixel[79:72] - thres) : (adjPixel[79:72] - refPixel - thres)) : 12'b0) +
((compare[17:16] == `BRIGHT) ?
(((adjPixel[71:64] - refPixel) > 255) ?
(refPixel - adjPixel[71:64] - thres) : (adjPixel[71:64] - refPixel - thres)) : 12'b0) +
((compare[15:14] == `BRIGHT) ?
(((adjPixel[63:56] - refPixel) > 255) ?
(refPixel - adjPixel[63:56] - thres) : (adjPixel[63:56] - refPixel - thres)) : 12'b0) +
((compare[13:12] == `BRIGHT) ?
(((adjPixel[55:48] - refPixel) > 255) ?
(refPixel - adjPixel[55:48] - thres) : (adjPixel[55:48] - refPixel - thres)) : 12'b0) +
((compare[11:10] == `BRIGHT) ?
(((adjPixel[47:40] - refPixel) > 255) ?
(refPixel - adjPixel[47:40] - thres) : (adjPixel[47:40] - refPixel - thres)) : 12'b0) +
((compare[9:8] == `BRIGHT) ?
(((adjPixel[39:32] - refPixel) > 255) ?
(refPixel - adjPixel[39:32] - thres) : (adjPixel[39:32] - refPixel - thres)) : 12'b0) +
((compare[7:6] == `BRIGHT) ?
(((adjPixel[31:24] - refPixel) > 255) ?
(refPixel - adjPixel[31:24] - thres) : (adjPixel[31:24] - refPixel - thres)) : 12'b0) +
((compare[5:4] == `BRIGHT) ?
(((adjPixel[23:16] - refPixel) > 255) ?
(refPixel - adjPixel[23:16] - thres) : (adjPixel[23:16] - refPixel - thres)) : 12'b0) +
((compare[3:2] == `BRIGHT) ?
(((adjPixel[15:8] - refPixel) > 255) ?
(refPixel - adjPixel[15:8] - thres) : (adjPixel[15:8] - refPixel - thres)) : 12'b0) +
((compare[1:0] == `BRIGHT) ?
(((adjPixel[7:0] - refPixel) > 255) ?
(refPixel - adjPixel[7:0] - thres) : (adjPixel[7:0] - refPixel - thres)) : 12'b0);
assign scoreValue = (sBright >= sDark) ? sBright : sDark;
assign wren = isCorner;
endmodule | module FS_Datapath (isCorner, compare, refPixel, adjPixel, thres, wren, scoreValue); |
input isCorner;
input [31:0] compare;
input [7:0] refPixel;
input [127:0] adjPixel;
input [7:0] thres;
output wren;
output [7:0] scoreValue;
wire [11:0] sBright;
wire [11:0] sDark;
assign sDark =
((compare[31:30] == `DARK) ?
(((refPixel - adjPixel[127:120]) > 255) ?
(adjPixel[127:120] - refPixel - thres) : (refPixel - adjPixel[127:120] - thres)) : 12'b0) +
((compare[29:28] == `DARK) ?
(((refPixel - adjPixel[119:112]) > 255) ?
(adjPixel[119:112] - refPixel - thres) : (refPixel - adjPixel[119:112] - thres)) : 12'b0) +
((compare[27:26] == `DARK) ?
(((refPixel - adjPixel[111:104]) > 255) ?
(adjPixel[111:104] - refPixel - thres) : (refPixel - adjPixel[111:104] - thres)) : 12'b0) +
((compare[25:24] == `DARK) ?
(((refPixel - adjPixel[103:96]) > 255) ?
(adjPixel[103:96] - refPixel - thres) : (refPixel - adjPixel[103:96] - thres)) : 12'b0) +
((compare[23:22] == `DARK) ?
(((refPixel - adjPixel[95:88]) > 255) ?
(adjPixel[95:88] - refPixel - thres) : (refPixel - adjPixel[95:88] - thres)) : 12'b0) +
((compare[21:20] == `DARK) ?
(((refPixel - adjPixel[87:80]) > 255) ?
(adjPixel[87:80] - refPixel - thres) : (refPixel - adjPixel[87:80] - thres)) : 12'b0) +
((compare[19:18] == `DARK) ?
(((refPixel - adjPixel[79:72]) > 255) ?
(adjPixel[79:72] - refPixel - thres) : (refPixel - adjPixel[79:72] - thres)) : 12'b0) +
((compare[17:16] == `DARK) ?
(((refPixel - adjPixel[71:64]) > 255) ?
(adjPixel[71:64] - refPixel - thres) : (refPixel - adjPixel[71:64] - thres)) : 12'b0) +
((compare[15:14] == `DARK) ?
(((refPixel - adjPixel[63:56]) > 255) ?
(adjPixel[63:56] - refPixel - thres) : (refPixel - adjPixel[63:56] - thres)) : 12'b0) +
((compare[13:12] == `DARK) ?
(((refPixel - adjPixel[55:48]) > 255) ?
(adjPixel[55:48] - refPixel - thres) : (refPixel - adjPixel[55:48] - thres)) : 12'b0) +
((compare[11:10] == `DARK) ?
(((refPixel - adjPixel[47:40]) > 255) ?
(adjPixel[47:40] - refPixel - thres) : (refPixel - adjPixel[47:40] - thres)) : 12'b0) +
((compare[9:8] == `DARK) ?
(((refPixel - adjPixel[39:32]) > 255) ?
(adjPixel[39:32] - refPixel - thres) : (refPixel - adjPixel[39:32] - thres)) : 12'b0) +
((compare[7:6] == `DARK) ?
(((refPixel - adjPixel[31:24]) > 255) ?
(adjPixel[31:24] - refPixel - thres) : (refPixel - adjPixel[31:24] - thres)) : 12'b0) +
((compare[5:4] == `DARK) ?
(((refPixel - adjPixel[23:16]) > 255) ?
(adjPixel[23:16] - refPixel - thres) : (refPixel - adjPixel[23:16] - thres)) : 12'b0) +
((compare[3:2] == `DARK) ?
(((refPixel - adjPixel[15:8]) > 255) ?
(adjPixel[15:8] - refPixel - thres) : (refPixel - adjPixel[15:8] - thres)) : 12'b0) +
((compare[1:0] == `DARK) ?
(((refPixel - adjPixel[7:0]) > 255) ?
(adjPixel[7:0] - refPixel - thres) : (refPixel - adjPixel[7:0] - thres)) : 12'b0);
assign sBright =
((compare[31:30] == `BRIGHT) ?
(((adjPixel[127:120] - refPixel) > 255) ?
(refPixel - adjPixel[127:120] - thres) : (adjPixel[127:120] - refPixel - thres)) : 12'b0) +
((compare[29:28] == `BRIGHT) ?
(((adjPixel[119:112] - refPixel) > 255) ?
(refPixel - adjPixel[119:112] - thres) : (adjPixel[119:112] - refPixel - thres)) : 12'b0) +
((compare[27:26] == `BRIGHT) ?
(((adjPixel[111:104] - refPixel) > 255) ?
(refPixel - adjPixel[111:104] - thres) : (adjPixel[111:104] - refPixel - thres)) : 12'b0) +
((compare[25:24] == `BRIGHT) ?
(((adjPixel[103:96] - refPixel) > 255) ?
(refPixel - adjPixel[103:96] - thres) : (adjPixel[103:96] - refPixel - thres)) : 12'b0) +
((compare[23:22] == `BRIGHT) ?
(((adjPixel[95:88] - refPixel) > 255) ?
(refPixel - adjPixel[95:88] - thres) : (adjPixel[95:88] - refPixel - thres)) : 12'b0) +
((compare[21:20] == `BRIGHT) ?
(((adjPixel[87:80] - refPixel) > 255) ?
(refPixel - adjPixel[87:80] - thres) : (adjPixel[87:80] - refPixel - thres)) : 12'b0) +
((compare[19:18] == `BRIGHT) ?
(((adjPixel[79:72] - refPixel) > 255) ?
(refPixel - adjPixel[79:72] - thres) : (adjPixel[79:72] - refPixel - thres)) : 12'b0) +
((compare[17:16] == `BRIGHT) ?
(((adjPixel[71:64] - refPixel) > 255) ?
(refPixel - adjPixel[71:64] - thres) : (adjPixel[71:64] - refPixel - thres)) : 12'b0) +
((compare[15:14] == `BRIGHT) ?
(((adjPixel[63:56] - refPixel) > 255) ?
(refPixel - adjPixel[63:56] - thres) : (adjPixel[63:56] - refPixel - thres)) : 12'b0) +
((compare[13:12] == `BRIGHT) ?
(((adjPixel[55:48] - refPixel) > 255) ?
(refPixel - adjPixel[55:48] - thres) : (adjPixel[55:48] - refPixel - thres)) : 12'b0) +
((compare[11:10] == `BRIGHT) ?
(((adjPixel[47:40] - refPixel) > 255) ?
(refPixel - adjPixel[47:40] - thres) : (adjPixel[47:40] - refPixel - thres)) : 12'b0) +
((compare[9:8] == `BRIGHT) ?
(((adjPixel[39:32] - refPixel) > 255) ?
(refPixel - adjPixel[39:32] - thres) : (adjPixel[39:32] - refPixel - thres)) : 12'b0) +
((compare[7:6] == `BRIGHT) ?
(((adjPixel[31:24] - refPixel) > 255) ?
(refPixel - adjPixel[31:24] - thres) : (adjPixel[31:24] - refPixel - thres)) : 12'b0) +
((compare[5:4] == `BRIGHT) ?
(((adjPixel[23:16] - refPixel) > 255) ?
(refPixel - adjPixel[23:16] - thres) : (adjPixel[23:16] - refPixel - thres)) : 12'b0) +
((compare[3:2] == `BRIGHT) ?
(((adjPixel[15:8] - refPixel) > 255) ?
(refPixel - adjPixel[15:8] - thres) : (adjPixel[15:8] - refPixel - thres)) : 12'b0) +
((compare[1:0] == `BRIGHT) ?
(((adjPixel[7:0] - refPixel) > 255) ?
(refPixel - adjPixel[7:0] - thres) : (adjPixel[7:0] - refPixel - thres)) : 12'b0);
assign scoreValue = (sBright >= sDark) ? sBright : sDark;
assign wren = isCorner;
endmodule | 1 |
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