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141,935 | data/full_repos/permissive/9636384/apdtimer_all.v | 9,636,384 | apdtimer_all.v | v | 89 | 55 | [] | [] | [] | [(1, 88)] | null | null | 1: b"%Error: data/full_repos/permissive/9636384/apdtimer_all.v:23: Cannot find file containing module: 'register'\nregister #(.ADDR(8'h03)) apdtimer_reg(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9636384,data/full_repos/permissive/9636384/register\n data/full_repos/permissive/9636384,data/full_repos/permissive/9636384/register.v\n data/full_repos/permissive/9636384,data/full_repos/permissive/9636384/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: data/full_repos/permissive/9636384/apdtimer_all.v:36: Cannot find file containing module: 'register'\nregister #(.ADDR(8'h04)) strobe_operate_reg(\n^~~~~~~~\n%Error: data/full_repos/permissive/9636384/apdtimer_all.v:46: Cannot find file containing module: 'register'\nregister #(.ADDR(8'h05)) delta_operate_reg(\n^~~~~~~~\n%Error: data/full_repos/permissive/9636384/apdtimer_all.v:55: Cannot find file containing module: 'event_tagger'\nevent_tagger tagger(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9636384/apdtimer_all.v:67: Cannot find file containing module: 'strobe_latch'\nstrobe_latch latch0(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9636384/apdtimer_all.v:72: Cannot find file containing module: 'strobe_latch'\nstrobe_latch latch1(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9636384/apdtimer_all.v:77: Cannot find file containing module: 'strobe_latch'\nstrobe_latch latch2(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9636384/apdtimer_all.v:82: Cannot find file containing module: 'strobe_latch'\nstrobe_latch latch3(\n^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 312,801 | module | module apdtimer_all(
clk,
strobe_in, delta_in,
reg_clk, reg_addr, reg_data, reg_wr,
record_rdy, record
);
input clk;
input [3:0] strobe_in;
input [3:0] delta_in;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
output record_rdy;
output [46:0] record;
wire [3:0] strobe_chans;
wire [31:0] timer_reg;
register #(.ADDR(8'h03)) apdtimer_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(timer_reg)
);
wire capture_operate = timer_reg[0];
wire counter_operate = timer_reg[1];
wire reset_counter = timer_reg[2];
wire [31:0] strobe_operate;
register #(.ADDR(8'h04)) strobe_operate_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(strobe_operate)
);
wire [31:0] delta_operate;
register #(.ADDR(8'h05)) delta_operate_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(delta_operate)
);
event_tagger tagger(
.clk(clk),
.reset_counter(reset_counter),
.capture_operate(capture_operate),
.counter_operate(counter_operate),
.strobe_channels(strobe_chans & strobe_operate[3:0]),
.delta_channels(delta_in & delta_operate[3:0]),
.ready(record_rdy),
.data(record)
);
strobe_latch latch0(
.clk(clk),
.in(strobe_in[0]),
.out(strobe_chans[0])
);
strobe_latch latch1(
.clk(clk),
.in(strobe_in[1]),
.out(strobe_chans[1])
);
strobe_latch latch2(
.clk(clk),
.in(strobe_in[2]),
.out(strobe_chans[2])
);
strobe_latch latch3(
.clk(clk),
.in(strobe_in[3]),
.out(strobe_chans[3])
);
endmodule | module apdtimer_all(
clk,
strobe_in, delta_in,
reg_clk, reg_addr, reg_data, reg_wr,
record_rdy, record
); |
input clk;
input [3:0] strobe_in;
input [3:0] delta_in;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
output record_rdy;
output [46:0] record;
wire [3:0] strobe_chans;
wire [31:0] timer_reg;
register #(.ADDR(8'h03)) apdtimer_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(timer_reg)
);
wire capture_operate = timer_reg[0];
wire counter_operate = timer_reg[1];
wire reset_counter = timer_reg[2];
wire [31:0] strobe_operate;
register #(.ADDR(8'h04)) strobe_operate_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(strobe_operate)
);
wire [31:0] delta_operate;
register #(.ADDR(8'h05)) delta_operate_reg(
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(delta_operate)
);
event_tagger tagger(
.clk(clk),
.reset_counter(reset_counter),
.capture_operate(capture_operate),
.counter_operate(counter_operate),
.strobe_channels(strobe_chans & strobe_operate[3:0]),
.delta_channels(delta_in & delta_operate[3:0]),
.ready(record_rdy),
.data(record)
);
strobe_latch latch0(
.clk(clk),
.in(strobe_in[0]),
.out(strobe_chans[0])
);
strobe_latch latch1(
.clk(clk),
.in(strobe_in[1]),
.out(strobe_chans[1])
);
strobe_latch latch2(
.clk(clk),
.in(strobe_in[2]),
.out(strobe_chans[2])
);
strobe_latch latch3(
.clk(clk),
.in(strobe_in[3]),
.out(strobe_chans[3])
);
endmodule | 1 |
141,936 | data/full_repos/permissive/9636384/event_tagger.v | 9,636,384 | event_tagger.v | v | 69 | 74 | [] | [] | [] | [(6, 67)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9636384/event_tagger.v:28: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance event_tagger\nreg [3:0] old_delta = 3\'b0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9636384/event_tagger.v:41: Operator EQ expects 36 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance event_tagger\n data[46] <= (timer==1\'b0) ? 1\'b1 : 1\'b0; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/9636384/event_tagger.v:64: Operator ADD expects 36 bits on the RHS, but RHS\'s VARREF \'counter_operate\' generates 1 bits.\n : ... In instance event_tagger\n timer <= reset_counter ? 0 : timer + counter_operate;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 312,803 | module | module event_tagger(
strobe_channels,
delta_channels,
clk,
reset_counter,
capture_operate, counter_operate,
data,
ready
);
input [3:0] strobe_channels;
input [3:0] delta_channels;
input clk;
input reset_counter;
input capture_operate;
input counter_operate;
output ready;
output [46:0] data;
reg [35:0] timer = 36'b0;
reg [3:0] old_delta = 3'b0;
reg ready = 0;
reg [46:0] data = 47'b0;
always @(posedge clk)
begin
if (delta_channels != old_delta)
begin
data[35:0] <= timer[35:0];
data[39:36] <= delta_channels;
data[44:40] <= 0;
data[45] <= 1;
data[46] <= (timer==1'b0) ? 1'b1 : 1'b0;
ready <= capture_operate;
old_delta <= delta_channels;
end
else if (strobe_channels != 4'b0 || (timer == 36'b0 && counter_operate))
begin
data[35:0] <= timer[35:0];
data[39:36] <= strobe_channels;
data[44:40] <= 0;
data[45] <= 0;
data[46] <= (timer==36'b0) ? 1'b1 : 1'b0;
ready <= capture_operate;
end
else
begin
ready <= 0;
data <= 47'bX;
end
timer <= reset_counter ? 0 : timer + counter_operate;
end
endmodule | module event_tagger(
strobe_channels,
delta_channels,
clk,
reset_counter,
capture_operate, counter_operate,
data,
ready
); |
input [3:0] strobe_channels;
input [3:0] delta_channels;
input clk;
input reset_counter;
input capture_operate;
input counter_operate;
output ready;
output [46:0] data;
reg [35:0] timer = 36'b0;
reg [3:0] old_delta = 3'b0;
reg ready = 0;
reg [46:0] data = 47'b0;
always @(posedge clk)
begin
if (delta_channels != old_delta)
begin
data[35:0] <= timer[35:0];
data[39:36] <= delta_channels;
data[44:40] <= 0;
data[45] <= 1;
data[46] <= (timer==1'b0) ? 1'b1 : 1'b0;
ready <= capture_operate;
old_delta <= delta_channels;
end
else if (strobe_channels != 4'b0 || (timer == 36'b0 && counter_operate))
begin
data[35:0] <= timer[35:0];
data[39:36] <= strobe_channels;
data[44:40] <= 0;
data[45] <= 0;
data[46] <= (timer==36'b0) ? 1'b1 : 1'b0;
ready <= capture_operate;
end
else
begin
ready <= 0;
data <= 47'bX;
end
timer <= reset_counter ? 0 : timer + counter_operate;
end
endmodule | 1 |
141,942 | data/full_repos/permissive/9636384/fx2_timetag.v | 9,636,384 | fx2_timetag.v | v | 118 | 28 | [] | [] | [] | [(13, 126)] | null | null | 1: b'%Error: data/full_repos/permissive/9636384/fx2_timetag.v:1: Cannot find include file: config.v\n`include "config.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9636384,data/full_repos/permissive/9636384/config.v\n data/full_repos/permissive/9636384,data/full_repos/permissive/9636384/config.v.v\n data/full_repos/permissive/9636384,data/full_repos/permissive/9636384/config.v.sv\n config.v\n config.v.v\n config.v.sv\n obj_dir/config.v\n obj_dir/config.v.v\n obj_dir/config.v.sv\n%Error: Exiting due to 1 error(s)\n' | 312,807 | module | module fx2_timetag(
fx2_clk,
fx2_flags,
fx2_slwr,
fx2_slrd,
fx2_sloe,
fx2_wu2,
fx2_pktend,
fx2_fd,
fx2_fifoadr,
ext_clk,
delta_chs,
strobe_in,
led
);
input fx2_clk;
input [2:0] fx2_flags;
output fx2_slwr;
output fx2_slrd;
output fx2_sloe;
output fx2_wu2;
output fx2_pktend;
inout [7:0] fx2_fd;
output [1:0] fx2_fifoadr;
input ext_clk;
input [3:0] strobe_in;
output [3:0] delta_chs;
output [1:0] led;
wire clk;
wire cmd_rdy;
wire [7:0] cmd;
wire sample_rdy;
wire [7:0] sample;
wire sample_ack;
wire reply_rdy;
wire [7:0] reply;
wire reply_ack;
wire reply_end;
`ifdef USE_EXT_CLK
wire pll_locked;
altpll0 b2v_inst2(
.inclk0(ext_clk),
.c0(clk),
.locked(pll_locked)
);
`else
assign clk = fx2_clk;
`endif
timetag tagger(
.fx2_clk(fx2_clk),
.data_rdy(sample_rdy),
.data(sample),
.data_ack(sample_ack),
.cmd_wr(cmd_rdy),
.cmd_in(cmd),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end),
.clk(clk),
.strobe_in(strobe_in),
.delta_chs(delta_chs)
);
fx2_bidir fx2_if(
.fx2_clk(fx2_clk),
.fx2_fd(fx2_fd),
.fx2_flags(fx2_flags),
.fx2_slrd(fx2_slrd),
.fx2_slwr(fx2_slwr),
.fx2_sloe(fx2_sloe),
.fx2_wu2(fx2_wu2),
.fx2_pktend(fx2_pktend),
.fx2_fifoadr(fx2_fifoadr),
.sample(sample),
.sample_rdy(sample_rdy),
.sample_ack(sample_ack),
.cmd(cmd),
.cmd_wr(cmd_rdy),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end)
);
led_blinker cmd_rdy_led(
.clk(fx2_clk),
.in(cmd_wr),
.out(led[0])
);
led_blinker sample_rdy_led(
.clk(fx2_clk),
.in(sample_rdy),
.out(led[1])
);
endmodule | module fx2_timetag(
fx2_clk,
fx2_flags,
fx2_slwr,
fx2_slrd,
fx2_sloe,
fx2_wu2,
fx2_pktend,
fx2_fd,
fx2_fifoadr,
ext_clk,
delta_chs,
strobe_in,
led
); |
input fx2_clk;
input [2:0] fx2_flags;
output fx2_slwr;
output fx2_slrd;
output fx2_sloe;
output fx2_wu2;
output fx2_pktend;
inout [7:0] fx2_fd;
output [1:0] fx2_fifoadr;
input ext_clk;
input [3:0] strobe_in;
output [3:0] delta_chs;
output [1:0] led;
wire clk;
wire cmd_rdy;
wire [7:0] cmd;
wire sample_rdy;
wire [7:0] sample;
wire sample_ack;
wire reply_rdy;
wire [7:0] reply;
wire reply_ack;
wire reply_end;
`ifdef USE_EXT_CLK
wire pll_locked;
altpll0 b2v_inst2(
.inclk0(ext_clk),
.c0(clk),
.locked(pll_locked)
);
`else
assign clk = fx2_clk;
`endif
timetag tagger(
.fx2_clk(fx2_clk),
.data_rdy(sample_rdy),
.data(sample),
.data_ack(sample_ack),
.cmd_wr(cmd_rdy),
.cmd_in(cmd),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end),
.clk(clk),
.strobe_in(strobe_in),
.delta_chs(delta_chs)
);
fx2_bidir fx2_if(
.fx2_clk(fx2_clk),
.fx2_fd(fx2_fd),
.fx2_flags(fx2_flags),
.fx2_slrd(fx2_slrd),
.fx2_slwr(fx2_slwr),
.fx2_sloe(fx2_sloe),
.fx2_wu2(fx2_wu2),
.fx2_pktend(fx2_pktend),
.fx2_fifoadr(fx2_fifoadr),
.sample(sample),
.sample_rdy(sample_rdy),
.sample_ack(sample_ack),
.cmd(cmd),
.cmd_wr(cmd_rdy),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end)
);
led_blinker cmd_rdy_led(
.clk(fx2_clk),
.in(cmd_wr),
.out(led[0])
);
led_blinker sample_rdy_led(
.clk(fx2_clk),
.in(sample_rdy),
.out(led[1])
);
endmodule | 1 |
141,943 | data/full_repos/permissive/9636384/fx2_timetag_bench.v | 9,636,384 | fx2_timetag_bench.v | v | 227 | 96 | [] | [] | [] | null | line:123: before: "&&" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100 strobe_in[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #5 strobe_in[0] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #80 strobe_in[1] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #5 strobe_in[1] = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:111: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=8\'hAA; cmd_wr=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:112: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=write;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:113: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=addr[7:0];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:114: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=addr[15:8];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:115: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=value[7:0];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:116: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=value[15:8];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:117: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=value[23:16];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:118: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=value[31:24];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:119: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_wr=0; cmd_commit=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:120: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_commit=0;\n ^\n%Error: data/full_repos/permissive/9636384/fx2_timetag_bench.v:121: syntax error, unexpected \'@\'\n @(cmd_sent);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:137: Unsupported: Ignoring delay on this delayed statement.\n #100 ; \n ^\n%Error: data/full_repos/permissive/9636384/fx2_timetag_bench.v:139: syntax error, unexpected \'@\'\n @(posedge fx2_clk && sample_rdy);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:162: Unsupported: Ignoring delay on this delayed statement.\n #100 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:164: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=8\'hFF; cmd_wr=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:165: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=8\'hFF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:166: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd=8\'hFF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:167: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_wr=0; cmd_commit=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:168: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_commit=0;\n ^\n%Error: data/full_repos/permissive/9636384/fx2_timetag_bench.v:169: syntax error, unexpected \'@\'\n @(cmd_sent);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:171: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:175: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:179: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:183: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:187: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:193: Unsupported: Ignoring delay on this delayed statement.\n #4000 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:195: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:199: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:209: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:213: Unsupported: Ignoring delay on this delayed statement.\n #4000 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:215: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/fx2_timetag_bench.v:219: Unsupported: Ignoring delay on this delayed statement.\n #50 ;\n ^\n%Error: Exiting due to 3 error(s), 34 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,808 | module | module fx2_timetag_bench();
reg clk;
wire fx2_clk;
wire [7:0] fd;
wire [2:0] flags;
wire [1:0] fifoadr;
wire sloe, slrd, slwr, pktend;
reg [3:0] strobe_in;
wire [35:0] counter = uut.tagger.apdtimer.tagger.timer;
initial clk = 0;
always #2 clk = ~clk;
reg [31:0] strobe_count;
initial strobe_count = 0;
initial strobe_in = 0;
always begin
#100 strobe_in[0] = 1;
`ifdef LOG_EVENTS
$display($time, " Strobe channel 0 (event %d, counter=%d)", strobe_count, counter);
`endif
#5 strobe_in[0] = 0;
if (uut.tagger.apdtimer.capture_operate)
strobe_count = strobe_count + 1;
end
always begin
#80 strobe_in[1] = 1;
`ifdef LOG_EVENTS
$display($time, " Strobe channel 1 (event %d, counter=%d)", strobe_count, counter);
`endif
#5 strobe_in[1] = 0;
if (uut.tagger.apdtimer.capture_operate)
strobe_count = strobe_count + 1;
end
reg [31:0] delta_count;
initial delta_count = 0;
wire [3:0] delta_chs;
`ifdef LOG_EVENTS
always @(posedge delta_chs[0])
$display($time, " Delta channel event %d", delta_count);
`endif
reg [7:0] cmd;
reg cmd_wr, cmd_commit;
wire cmd_sent;
wire [7:0] reply_data;
wire reply_rdy;
wire [7:0] sample_data;
wire sample_rdy;
fx2_test_fixture fx2(
.ifclk(fx2_clk),
.fd(fd),
.slrd(slrd),
.slwr(slwr),
.sloe(sloe),
.fifoadr(fifoadr),
.pktend(pktend),
.flags(flags),
.cmd_data(cmd),
.cmd_wr(cmd_wr),
.cmd_commit(cmd_commit),
.cmd_sent(cmd_sent),
.reply_data(reply_data),
.reply_rdy(reply_rdy),
.data(sample_data),
.data_rdy(sample_rdy)
);
fx2_timetag uut(
.fx2_clk(fx2_clk),
.fx2_flags(flags),
.fx2_slwr(slwr),
.fx2_slrd(slrd),
.fx2_sloe(sloe),
.fx2_wu2(),
.fx2_pktend(pktend),
.fx2_fd(fd),
.fx2_fifoadr(fifoadr),
.ext_clk(clk),
.delta_chs(delta_chs),
.strobe_in(strobe_in),
.led()
);
reg [31:0] reply_buf;
task reg_cmd;
input write;
input [15:0] addr;
input [31:0] value;
begin
$display($time, " Register transaction on %04x with value %08x (wr=%d)", addr, value, write);
#12 cmd=8'hAA; cmd_wr=1;
#12 cmd=write;
#12 cmd=addr[7:0];
#12 cmd=addr[15:8];
#12 cmd=value[7:0];
#12 cmd=value[15:8];
#12 cmd=value[23:16];
#12 cmd=value[31:24];
#12 cmd_wr=0; cmd_commit=1;
#12 cmd_commit=0;
@(cmd_sent);
@(posedge fx2_clk && reply_rdy);
@(posedge fx2_clk && reply_rdy) reply_buf[7:0] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[15:8] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[23:16] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[31:24] = reply_data;
$display($time, " Register %04x = %08x", addr, reply_buf);
end
endtask
`ifdef LOG_SAMPLES
reg [47:0] sample_buf;
reg [31:0] sample_count;
initial sample_count = 0;
initial begin
#100 ;
forever begin
@(posedge fx2_clk && sample_rdy);
@(posedge fx2_clk && sample_rdy) sample_buf[47:40] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[39:32] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[31:24] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[23:16] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[15:8] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[7:0] = sample_data;
sample_count = sample_count + 1;
$display($time, " Sample #%d: %012x", sample_count, sample_buf);
end
end
`endif
initial begin
$display($time, " Starting...");
#100 ;
$display($time, " Starting with garbage");
#12 cmd=8'hFF; cmd_wr=1;
#12 cmd=8'hFF;
#12 cmd=8'hFF;
#12 cmd_wr=0; cmd_commit=1;
#12 cmd_commit=0;
@(cmd_sent);
#50 ;
$display($time, " Testing version register");
reg_cmd(0, 16'h1, 0);
#50 ;
$display($time, " Testing clockrate register");
reg_cmd(0, 16'h2, 0);
#50 ;
$display($time, " Resetting counter");
reg_cmd(1, 16'h3, 32'h04);
#50 ;
$display($time, " Enabling strobe channels");
reg_cmd(1, 16'h4, 32'h0f);
#50 ;
$display($time, " Starting capture");
reg_cmd(1, 16'h3, 32'h03);
$display($time, " Waiting for some data");
#4000 ;
#50 ;
$display($time, " Disabling strobe channels");
reg_cmd(1, 16'h4, 0);
#1000;
$display($time, " Setting up sequencer");
reg_cmd(1, 16'h28, 31'h03);
reg_cmd(1, 16'h29, 31'd40);
reg_cmd(1, 16'h2a, 31'd80);
reg_cmd(1, 16'h2b, 31'd60);
reg_cmd(1, 16'h20, 31'h02);
reg_cmd(1, 16'h20, 31'h01);
#50 ;
$display($time, " Enabling delta channels");
reg_cmd(1, 16'h5, 32'h0f);
#4000 ;
#50 ;
$display($time, " Disabling delta channels");
reg_cmd(1, 16'h5, 0);
#50 ;
$display($time, " Stopping capture");
reg_cmd(1, 16'h3, 32'h02);
end
endmodule | module fx2_timetag_bench(); |
reg clk;
wire fx2_clk;
wire [7:0] fd;
wire [2:0] flags;
wire [1:0] fifoadr;
wire sloe, slrd, slwr, pktend;
reg [3:0] strobe_in;
wire [35:0] counter = uut.tagger.apdtimer.tagger.timer;
initial clk = 0;
always #2 clk = ~clk;
reg [31:0] strobe_count;
initial strobe_count = 0;
initial strobe_in = 0;
always begin
#100 strobe_in[0] = 1;
`ifdef LOG_EVENTS
$display($time, " Strobe channel 0 (event %d, counter=%d)", strobe_count, counter);
`endif
#5 strobe_in[0] = 0;
if (uut.tagger.apdtimer.capture_operate)
strobe_count = strobe_count + 1;
end
always begin
#80 strobe_in[1] = 1;
`ifdef LOG_EVENTS
$display($time, " Strobe channel 1 (event %d, counter=%d)", strobe_count, counter);
`endif
#5 strobe_in[1] = 0;
if (uut.tagger.apdtimer.capture_operate)
strobe_count = strobe_count + 1;
end
reg [31:0] delta_count;
initial delta_count = 0;
wire [3:0] delta_chs;
`ifdef LOG_EVENTS
always @(posedge delta_chs[0])
$display($time, " Delta channel event %d", delta_count);
`endif
reg [7:0] cmd;
reg cmd_wr, cmd_commit;
wire cmd_sent;
wire [7:0] reply_data;
wire reply_rdy;
wire [7:0] sample_data;
wire sample_rdy;
fx2_test_fixture fx2(
.ifclk(fx2_clk),
.fd(fd),
.slrd(slrd),
.slwr(slwr),
.sloe(sloe),
.fifoadr(fifoadr),
.pktend(pktend),
.flags(flags),
.cmd_data(cmd),
.cmd_wr(cmd_wr),
.cmd_commit(cmd_commit),
.cmd_sent(cmd_sent),
.reply_data(reply_data),
.reply_rdy(reply_rdy),
.data(sample_data),
.data_rdy(sample_rdy)
);
fx2_timetag uut(
.fx2_clk(fx2_clk),
.fx2_flags(flags),
.fx2_slwr(slwr),
.fx2_slrd(slrd),
.fx2_sloe(sloe),
.fx2_wu2(),
.fx2_pktend(pktend),
.fx2_fd(fd),
.fx2_fifoadr(fifoadr),
.ext_clk(clk),
.delta_chs(delta_chs),
.strobe_in(strobe_in),
.led()
);
reg [31:0] reply_buf;
task reg_cmd;
input write;
input [15:0] addr;
input [31:0] value;
begin
$display($time, " Register transaction on %04x with value %08x (wr=%d)", addr, value, write);
#12 cmd=8'hAA; cmd_wr=1;
#12 cmd=write;
#12 cmd=addr[7:0];
#12 cmd=addr[15:8];
#12 cmd=value[7:0];
#12 cmd=value[15:8];
#12 cmd=value[23:16];
#12 cmd=value[31:24];
#12 cmd_wr=0; cmd_commit=1;
#12 cmd_commit=0;
@(cmd_sent);
@(posedge fx2_clk && reply_rdy);
@(posedge fx2_clk && reply_rdy) reply_buf[7:0] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[15:8] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[23:16] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[31:24] = reply_data;
$display($time, " Register %04x = %08x", addr, reply_buf);
end
endtask
`ifdef LOG_SAMPLES
reg [47:0] sample_buf;
reg [31:0] sample_count;
initial sample_count = 0;
initial begin
#100 ;
forever begin
@(posedge fx2_clk && sample_rdy);
@(posedge fx2_clk && sample_rdy) sample_buf[47:40] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[39:32] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[31:24] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[23:16] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[15:8] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[7:0] = sample_data;
sample_count = sample_count + 1;
$display($time, " Sample #%d: %012x", sample_count, sample_buf);
end
end
`endif
initial begin
$display($time, " Starting...");
#100 ;
$display($time, " Starting with garbage");
#12 cmd=8'hFF; cmd_wr=1;
#12 cmd=8'hFF;
#12 cmd=8'hFF;
#12 cmd_wr=0; cmd_commit=1;
#12 cmd_commit=0;
@(cmd_sent);
#50 ;
$display($time, " Testing version register");
reg_cmd(0, 16'h1, 0);
#50 ;
$display($time, " Testing clockrate register");
reg_cmd(0, 16'h2, 0);
#50 ;
$display($time, " Resetting counter");
reg_cmd(1, 16'h3, 32'h04);
#50 ;
$display($time, " Enabling strobe channels");
reg_cmd(1, 16'h4, 32'h0f);
#50 ;
$display($time, " Starting capture");
reg_cmd(1, 16'h3, 32'h03);
$display($time, " Waiting for some data");
#4000 ;
#50 ;
$display($time, " Disabling strobe channels");
reg_cmd(1, 16'h4, 0);
#1000;
$display($time, " Setting up sequencer");
reg_cmd(1, 16'h28, 31'h03);
reg_cmd(1, 16'h29, 31'd40);
reg_cmd(1, 16'h2a, 31'd80);
reg_cmd(1, 16'h2b, 31'd60);
reg_cmd(1, 16'h20, 31'h02);
reg_cmd(1, 16'h20, 31'h01);
#50 ;
$display($time, " Enabling delta channels");
reg_cmd(1, 16'h5, 32'h0f);
#4000 ;
#50 ;
$display($time, " Disabling delta channels");
reg_cmd(1, 16'h5, 0);
#50 ;
$display($time, " Stopping capture");
reg_cmd(1, 16'h3, 32'h02);
end
endmodule | 1 |
141,945 | data/full_repos/permissive/9636384/register.v | 9,636,384 | register.v | v | 82 | 66 | [] | [] | [] | [(4, 27), (30, 44), (47, 81)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9636384/register.v:30: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'register\'\nmodule register(\n ^~~~~~~~\n : ... Top module \'readonly_register\'\nmodule readonly_register(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'counter_register\'\nmodule counter_register(\n ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9636384/register.v:68: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'increment\' generates 1 bits.\n : ... In instance counter_register\n my_value <= reset ? 0 : my_value + increment;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,810 | module | module register(
reg_clk, reg_addr, reg_data, reg_wr,
clk, value
);
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input clk;
output [31:0] value;
reg [31:0] value;
initial value = 32'h0;
always @(posedge reg_clk)
if (reg_addr == ADDR && reg_wr)
value <= reg_data;
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule | module register(
reg_clk, reg_addr, reg_data, reg_wr,
clk, value
); |
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input clk;
output [31:0] value;
reg [31:0] value;
initial value = 32'h0;
always @(posedge reg_clk)
if (reg_addr == ADDR && reg_wr)
value <= reg_data;
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule | 1 |
141,946 | data/full_repos/permissive/9636384/register.v | 9,636,384 | register.v | v | 82 | 66 | [] | [] | [] | [(4, 27), (30, 44), (47, 81)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9636384/register.v:30: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'register\'\nmodule register(\n ^~~~~~~~\n : ... Top module \'readonly_register\'\nmodule readonly_register(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'counter_register\'\nmodule counter_register(\n ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9636384/register.v:68: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'increment\' generates 1 bits.\n : ... In instance counter_register\n my_value <= reset ? 0 : my_value + increment;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,810 | module | module readonly_register(
reg_clk, reg_addr, reg_data, reg_wr,
value
);
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input [31:0] value;
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule | module readonly_register(
reg_clk, reg_addr, reg_data, reg_wr,
value
); |
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input [31:0] value;
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule | 1 |
141,947 | data/full_repos/permissive/9636384/register.v | 9,636,384 | register.v | v | 82 | 66 | [] | [] | [] | [(4, 27), (30, 44), (47, 81)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9636384/register.v:30: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'register\'\nmodule register(\n ^~~~~~~~\n : ... Top module \'readonly_register\'\nmodule readonly_register(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'counter_register\'\nmodule counter_register(\n ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9636384/register.v:68: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'increment\' generates 1 bits.\n : ... In instance counter_register\n my_value <= reset ? 0 : my_value + increment;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,810 | module | module counter_register(
reg_clk, reg_addr, reg_data, reg_wr,
increment_clk, increment
);
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input increment_clk;
input increment;
reg [31:0] my_value;
initial my_value = 32'h0;
reg [31:0] value;
reg reset;
initial reset = 0;
always @(posedge increment_clk)
begin
my_value <= reset ? 0 : my_value + increment;
end
always @(posedge reg_clk)
begin
value <= my_value;
if (reg_addr == ADDR && reg_wr)
reset <= 1;
else if (reset)
reset <= 0;
end
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule | module counter_register(
reg_clk, reg_addr, reg_data, reg_wr,
increment_clk, increment
); |
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input increment_clk;
input increment;
reg [31:0] my_value;
initial my_value = 32'h0;
reg [31:0] value;
reg reset;
initial reset = 0;
always @(posedge increment_clk)
begin
my_value <= reset ? 0 : my_value + increment;
end
always @(posedge reg_clk)
begin
value <= my_value;
if (reg_addr == ADDR && reg_wr)
reset <= 1;
else if (reset)
reset <= 0;
end
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule | 1 |
141,955 | data/full_repos/permissive/9636384/timetag_bench.v | 9,636,384 | timetag_bench.v | v | 90 | 86 | [] | [] | [] | [(3, 88)] | null | null | 1: b'%Error: data/full_repos/permissive/9636384/timetag_bench.v:42: Unsupported or unknown PLI call: $monitor\n $monitor($time, " cmd(%b %x) data(%b %x) cmd_rdy=%b cmd_ack=%b cmd_data=%x state=",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:50: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:52: Unsupported: Ignoring delay on this delayed statement.\nalways #6 fx2_clk = ~fx2_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100 detectors[0] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:68: Unsupported: Ignoring delay on this delayed statement.\n #5 detectors[0] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:79: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_in=8\'hAA; cmd_wr=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:80: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_in=8\'h01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:81: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_in=8\'h01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:82: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_in=8\'h01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9636384/timetag_bench.v:83: Unsupported: Ignoring delay on this delayed statement.\n #12 cmd_wr=0;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,818 | module | module timetag_bench();
reg clk;
reg fx2_clk;
reg cmd_wr;
reg [7:0] cmd_in;
wire [15:0] length;
reg request_length;
wire [7:0] data;
wire data_rdy;
reg data_ack;
reg [3:0] detectors;
wire [3:0] laser_en;
wire running;
timetag uut(
.fx2_clk(fx2_clk),
.cmd_wr(cmd_wr),
.cmd_in(cmd_in),
.clk(clk),
.strobe_in(detectors),
.data_rdy(data_rdy),
.data(data),
.data_ack(data_ack)
);
initial
$monitor($time, " cmd(%b %x) data(%b %x) cmd_rdy=%b cmd_ack=%b cmd_data=%x state=",
cmd_wr, cmd_in,
data_rdy, data,
uut.reg_addr, uut.reg_data
);
initial clk = 0;
always #2 clk = ~clk;
initial fx2_clk = 0;
always #6 fx2_clk = ~fx2_clk;
initial detectors = 4'b0000;
`ifdef RANDOM_PHOTONS
initial begin
if ((4'b1111 & $random) == 4'b0)
begin
detectors[0] = 1'b1;
#10 detectors[0] = 1'b0;
end
end
`else
always begin
#100 detectors[0] = 1'b1;
#5 detectors[0] = 1'b0;
end
`endif
initial begin
$display($time, " Starting...");
$display($time, " Starting detectors");
#100 ;
#12 cmd_in=8'hAA; cmd_wr=1;
#12 cmd_in=8'h01;
#12 cmd_in=8'h01;
#12 cmd_in=8'h01;
#12 cmd_wr=0;
data_ack = 1;
end
endmodule | module timetag_bench(); |
reg clk;
reg fx2_clk;
reg cmd_wr;
reg [7:0] cmd_in;
wire [15:0] length;
reg request_length;
wire [7:0] data;
wire data_rdy;
reg data_ack;
reg [3:0] detectors;
wire [3:0] laser_en;
wire running;
timetag uut(
.fx2_clk(fx2_clk),
.cmd_wr(cmd_wr),
.cmd_in(cmd_in),
.clk(clk),
.strobe_in(detectors),
.data_rdy(data_rdy),
.data(data),
.data_ack(data_ack)
);
initial
$monitor($time, " cmd(%b %x) data(%b %x) cmd_rdy=%b cmd_ack=%b cmd_data=%x state=",
cmd_wr, cmd_in,
data_rdy, data,
uut.reg_addr, uut.reg_data
);
initial clk = 0;
always #2 clk = ~clk;
initial fx2_clk = 0;
always #6 fx2_clk = ~fx2_clk;
initial detectors = 4'b0000;
`ifdef RANDOM_PHOTONS
initial begin
if ((4'b1111 & $random) == 4'b0)
begin
detectors[0] = 1'b1;
#10 detectors[0] = 1'b0;
end
end
`else
always begin
#100 detectors[0] = 1'b1;
#5 detectors[0] = 1'b0;
end
`endif
initial begin
$display($time, " Starting...");
$display($time, " Starting detectors");
#100 ;
#12 cmd_in=8'hAA; cmd_wr=1;
#12 cmd_in=8'h01;
#12 cmd_in=8'h01;
#12 cmd_in=8'h01;
#12 cmd_wr=0;
data_ack = 1;
end
endmodule | 1 |
141,956 | data/full_repos/permissive/96394384/hdl/jt-sfg01.v | 96,394,384 | jt-sfg01.v | v | 128 | 100 | [] | [] | [] | [(1, 127)] | null | null | 1: b"%Error: data/full_repos/permissive/96394384/hdl/jt-sfg01.v:80: syntax error, unexpected '(', expecting IDENTIFIER\n .clk ( clk ), \n ^\n%Error: Exiting due to 1 error(s)\n" | 312,819 | module | module jt_sfg01(
input rst,
output [ 7:0] sfg_dbi,
input [ 7:0] sfg_dbo,
input [15:0] addr,
input clk,
input wr_n,
input rd_n,
input slt3_n,
input iorq_n,
input mi,
output int_n,
output wait_n,
output oe_n,
output [15:0] left,
output [15:0] right
);
wire ce_n = &addr[13:7];
wire ic106_4 = ~(addr[6] & ce_n);
wire ic106_2 = ~(addr[5] & addr[4]);
wire ic107_3 = ~(~ic106_4 & ~ic106_2);
wire ic107_4 = ~(~ic107_3 & ~addr[3]);
wire cs_n = ~(~ic107_4 & ~slt3_n);
assign busdir_n = ~(~iorq_n & ~mi);
assign wait_n = 1'b1;
wire opm_n = !(!cs_n && addr[2:1]==2'b00);
assign oe_n = !(!ce_n && !slt3_n);
jt51(
.clk ( clk ),
.rst ( rst ),
.cs_n ( opm_n ),
.wr_n ( wr_n ),
.a0 ( addr[0] ),
.d_in ( sfg_dbo ),
.d_out ( sfg_dbi ),
.irq_n ( int_n ),
.left ( left),
.right (right)
);
endmodule | module jt_sfg01(
input rst,
output [ 7:0] sfg_dbi,
input [ 7:0] sfg_dbo,
input [15:0] addr,
input clk,
input wr_n,
input rd_n,
input slt3_n,
input iorq_n,
input mi,
output int_n,
output wait_n,
output oe_n,
output [15:0] left,
output [15:0] right
); |
wire ce_n = &addr[13:7];
wire ic106_4 = ~(addr[6] & ce_n);
wire ic106_2 = ~(addr[5] & addr[4]);
wire ic107_3 = ~(~ic106_4 & ~ic106_2);
wire ic107_4 = ~(~ic107_3 & ~addr[3]);
wire cs_n = ~(~ic107_4 & ~slt3_n);
assign busdir_n = ~(~iorq_n & ~mi);
assign wait_n = 1'b1;
wire opm_n = !(!cs_n && addr[2:1]==2'b00);
assign oe_n = !(!ce_n && !slt3_n);
jt51(
.clk ( clk ),
.rst ( rst ),
.cs_n ( opm_n ),
.wr_n ( wr_n ),
.a0 ( addr[0] ),
.d_in ( sfg_dbo ),
.d_out ( sfg_dbi ),
.irq_n ( int_n ),
.left ( left),
.right (right)
);
endmodule | 2 |
141,957 | data/full_repos/permissive/96394384/hdl/jt2148.v | 96,394,384 | jt2148.v | v | 26 | 45 | [] | [] | [] | null | line:26: before: "/" | data/verilator_xmls/850a1090-2ec1-4032-991c-70ccaf3c7e23.xml | null | 312,820 | module | module jt2148(
input [2:0] addr,
input [7:0] din,
output [7:0] dout,
input midi_rx,
output midi_tx,
input cs_n,
output irq_n,
input ic_n,
input rd_n,
input wr_n,
output opm_n,
output [7:0] st,
input [7:0] sd
);
wire irq_rx_n = 1'b1;
wire irq_tx_n = 1'b1;
assign opm_n = !(!cs_n && addr[2:1]==2'b00);
assign irq_n = irq_rx_n | irq_tx_n;
endmodule | module jt2148(
input [2:0] addr,
input [7:0] din,
output [7:0] dout,
input midi_rx,
output midi_tx,
input cs_n,
output irq_n,
input ic_n,
input rd_n,
input wr_n,
output opm_n,
output [7:0] st,
input [7:0] sd
); |
wire irq_rx_n = 1'b1;
wire irq_tx_n = 1'b1;
assign opm_n = !(!cs_n && addr[2:1]==2'b00);
assign irq_n = irq_rx_n | irq_tx_n;
endmodule | 2 |
141,958 | data/full_repos/permissive/96399799/my_downsampler.srcs/sources_1/new/custom_clock.v | 96,399,799 | custom_clock.v | v | 28 | 83 | [] | [] | [] | [(23, 27)] | null | data/verilator_xmls/851812d6-371a-4f7b-a0ee-a3d77c9b6170.xml | null | 312,821 | module | module custom_clock(
input in_clk,
output out_clk
);
endmodule | module custom_clock(
input in_clk,
output out_clk
); |
endmodule | 0 |
141,959 | data/full_repos/permissive/96399799/my_downsampler.srcs/sources_1/new/MAR.v | 96,399,799 | MAR.v | v | 30 | 83 | [] | [] | [] | [(23, 29)] | null | data/verilator_xmls/6b3f1775-fc86-40e7-9019-ae3471ca59ab.xml | null | 312,822 | module | module MAR(
input clk,
input [15:0] from_c,
output [15:0] to_a,
input enable
);
endmodule | module MAR(
input clk,
input [15:0] from_c,
output [15:0] to_a,
input enable
); |
endmodule | 0 |
141,962 | data/full_repos/permissive/96478792/src/main.v | 96,478,792 | main.v | v | 313 | 84 | [] | [] | [] | null | line:192: before: ")" | null | 1: b'%Error: data/full_repos/permissive/96478792/src/main.v:4: Cannot find include file: rate_divider.v\n`include "rate_divider.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96478792/src,data/full_repos/permissive/96478792/rate_divider.v\n data/full_repos/permissive/96478792/src,data/full_repos/permissive/96478792/rate_divider.v.v\n data/full_repos/permissive/96478792/src,data/full_repos/permissive/96478792/rate_divider.v.sv\n rate_divider.v\n rate_divider.v.v\n rate_divider.v.sv\n obj_dir/rate_divider.v\n obj_dir/rate_divider.v.v\n obj_dir/rate_divider.v.sv\n%Error: data/full_repos/permissive/96478792/src/main.v:5: Cannot find include file: hex_decoder.v\n`include "hex_decoder.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/src/main.v:6: Cannot find include file: player2.v\n`include "player2.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/src/main.v:7: Cannot find include file: tumbler_vga.v\n`include "tumbler_vga.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/src/main.v:8: Cannot find include file: ram32x10.v\n`include "ram32x10.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/src/main.v:9: Cannot find include file: translator.v\n`include "translator.v" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n' | 312,825 | module | module main(
CLOCK_50,
KEY,
SW,
LEDR,
LEDG,
HEX0,
HEX2,
HEX3,
HEX4,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [17:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0, HEX2, HEX3, HEX4;
localparam ONE_HZ = 28'd50000000,
TWO_HZ = 28'd25000000;
wire user_input = KEY[0];
wire next_input = KEY[1];
wire done_input = KEY[2];
wire resetn = KEY[3];
wire clock = CLOCK_50;
wire clock_2hz;
rate_divider rate0(
.clock_in(clock),
.clock_out(clock_2hz),
.rate(TWO_HZ)
);
reg [3:0] current_state, next_state;
localparam S_START = 4'd0,
S_P1TURN = 4'd1,
S_P2TURN = 4'd2,
S_RESULT = 4'd3 ;
always @(*) begin: state_table
case (current_state)
S_START: next_state = done_input ? S_START : S_P1TURN;
S_P1TURN: next_state = done_input ? S_P1TURN : S_P2TURN;
S_P2TURN: next_state = done_input ? S_P2TURN : S_RESULT;
default: next_state = done_input ? S_RESULT : S_START;
endcase
end
hex_decoder hex0(
.hex_digit(current_state),
.segments(HEX0)
);
reg [2:0] input_mem;
assign LEDG[2:0] = input_mem;
always @(posedge clock_2hz) begin
if (user_input)
input_mem <= 3'b0;
else if (input_mem == 3'b111)
input_mem <= 3'b1;
else
input_mem <= { input_mem[1:0], 1'b1 };
end
wire game_over = (current_state == S_RESULT);
wire player1_turn = (current_state == S_P1TURN);
wire p1_clock = player1_turn ? clock_2hz : 1'b0;
wire p2_clock = (current_state == S_P2TURN) ? clock_2hz : 1'b0;
reg [3:0] p1_addr;
reg [3:0] p2_addr;
wire [3:0] ram_addr = player1_turn ? p1_addr : p2_addr;
hex_decoder hex2(
.hex_digit(p1_addr),
.segments(HEX2)
);
hex_decoder hex3(
.hex_digit(p2_addr),
.segments(HEX3)
);
hex_decoder hex4(
.hex_digit(ram_addr),
.segments(HEX4)
);
wire [9:0] p1_value;
wire [9:0] p2_value;
wire [9:0] p1_value_out;
wire p1_write;
wire p2_read;
reg [9:0] player1_value;
reg [9:0] p2_compare_value;
wire rwen = SW[1];
wire ram_clock = (current_state == S_P1TURN) ? p1_write : SW[0];
always @(posedge ram_clock) begin
case (current_state)
S_P1TURN: begin
player1_value <= p1_value;
p1_addr <= p1_addr + 1'b1;
end
S_P2TURN: begin
p2_addr <= p2_addr + 1'b1;
p2_compare_value <= p1_value_out;
end
default: begin
p1_addr <= 1'b0;
p2_addr <= 1'b0;
end
endcase
end
player1 player1_0(
.clock(p1_clock),
.user_input(user_input),
.next_input(~next_input),
.write(p1_write),
.q(p1_value)
);
ram32x10 ram0(
.address(ram_addr),
.clock(SW[0]),
.data(player1_value),
.wren(rwen),
.q(p1_value_out)
);
wire [1:0] p2_correct;
wire p2_complete;
player2 player2_0(
.clock(p2_clock),
.user_input(user_input),
.next_input(~next_input),
.p1_value(p2_compare_value),
.read(p2_read),
.correct(p2_correct),
.complete(p2_complete),
.q(p2_value)
);
wire abcd_kyle_signal = (current_state == S_P1TURN) && user_input;
assign LEDG[7] = p2_complete;
assign LEDG[6:5] = p2_correct;
assign LEDR[17] = rwen;
assign LEDR[16:10] = p2_value;
reg [9:0] ledr_value;
assign LEDR[9:0] = ledr_value;
always @(*) begin
case (current_state)
S_P1TURN: ledr_value <= p1_value;
S_P2TURN: ledr_value <= p2_compare_value;
default: ledr_value <= 10'b1111_1111_11;
endcase
end
always @(posedge clock_2hz) begin: state_FFs
current_state <= next_state;
end
reg vga_correct_hold;
always @(posedge abcd_kyle_signal) begin
vga_correct_hold <= p2_correct[0];
end
wire [7:0] x,y;
wire [2:0] colour;
wire draw_full_box;
translator trans0(
.correct(p2_correct),
.columns(p1_addr),
.selection(p2_value[1:0]),
.X(x),
.Y(y),
.colour(colour),
.draw_full(draw_full_box),
.reset(~game_over)
);
rate_divider rate2(
.clock_in(CLOCK_50),
.rate(28'b00011_00101_10111_00110_110),
.clock_out(refresh)
);
reg h;
always @(posedge refresh) begin
h <= ~h;
end
tumbler_vga tummy0(
.clock(CLOCK_50),
.colour_in(colour),
.draw_full(draw_full_box),
.draw(h),
.x_in(x),
.y_in(y),
.resetn(~game_over),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
defparam tummy0.BACKGROUND_IMAGE = "../res/spybackground.mif";
endmodule | module main(
CLOCK_50,
KEY,
SW,
LEDR,
LEDG,
HEX0,
HEX2,
HEX3,
HEX4,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [17:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0, HEX2, HEX3, HEX4;
localparam ONE_HZ = 28'd50000000,
TWO_HZ = 28'd25000000;
wire user_input = KEY[0];
wire next_input = KEY[1];
wire done_input = KEY[2];
wire resetn = KEY[3];
wire clock = CLOCK_50;
wire clock_2hz;
rate_divider rate0(
.clock_in(clock),
.clock_out(clock_2hz),
.rate(TWO_HZ)
);
reg [3:0] current_state, next_state;
localparam S_START = 4'd0,
S_P1TURN = 4'd1,
S_P2TURN = 4'd2,
S_RESULT = 4'd3 ;
always @(*) begin: state_table
case (current_state)
S_START: next_state = done_input ? S_START : S_P1TURN;
S_P1TURN: next_state = done_input ? S_P1TURN : S_P2TURN;
S_P2TURN: next_state = done_input ? S_P2TURN : S_RESULT;
default: next_state = done_input ? S_RESULT : S_START;
endcase
end
hex_decoder hex0(
.hex_digit(current_state),
.segments(HEX0)
);
reg [2:0] input_mem;
assign LEDG[2:0] = input_mem;
always @(posedge clock_2hz) begin
if (user_input)
input_mem <= 3'b0;
else if (input_mem == 3'b111)
input_mem <= 3'b1;
else
input_mem <= { input_mem[1:0], 1'b1 };
end
wire game_over = (current_state == S_RESULT);
wire player1_turn = (current_state == S_P1TURN);
wire p1_clock = player1_turn ? clock_2hz : 1'b0;
wire p2_clock = (current_state == S_P2TURN) ? clock_2hz : 1'b0;
reg [3:0] p1_addr;
reg [3:0] p2_addr;
wire [3:0] ram_addr = player1_turn ? p1_addr : p2_addr;
hex_decoder hex2(
.hex_digit(p1_addr),
.segments(HEX2)
);
hex_decoder hex3(
.hex_digit(p2_addr),
.segments(HEX3)
);
hex_decoder hex4(
.hex_digit(ram_addr),
.segments(HEX4)
);
wire [9:0] p1_value;
wire [9:0] p2_value;
wire [9:0] p1_value_out;
wire p1_write;
wire p2_read;
reg [9:0] player1_value;
reg [9:0] p2_compare_value;
wire rwen = SW[1];
wire ram_clock = (current_state == S_P1TURN) ? p1_write : SW[0];
always @(posedge ram_clock) begin
case (current_state)
S_P1TURN: begin
player1_value <= p1_value;
p1_addr <= p1_addr + 1'b1;
end
S_P2TURN: begin
p2_addr <= p2_addr + 1'b1;
p2_compare_value <= p1_value_out;
end
default: begin
p1_addr <= 1'b0;
p2_addr <= 1'b0;
end
endcase
end
player1 player1_0(
.clock(p1_clock),
.user_input(user_input),
.next_input(~next_input),
.write(p1_write),
.q(p1_value)
);
ram32x10 ram0(
.address(ram_addr),
.clock(SW[0]),
.data(player1_value),
.wren(rwen),
.q(p1_value_out)
);
wire [1:0] p2_correct;
wire p2_complete;
player2 player2_0(
.clock(p2_clock),
.user_input(user_input),
.next_input(~next_input),
.p1_value(p2_compare_value),
.read(p2_read),
.correct(p2_correct),
.complete(p2_complete),
.q(p2_value)
);
wire abcd_kyle_signal = (current_state == S_P1TURN) && user_input;
assign LEDG[7] = p2_complete;
assign LEDG[6:5] = p2_correct;
assign LEDR[17] = rwen;
assign LEDR[16:10] = p2_value;
reg [9:0] ledr_value;
assign LEDR[9:0] = ledr_value;
always @(*) begin
case (current_state)
S_P1TURN: ledr_value <= p1_value;
S_P2TURN: ledr_value <= p2_compare_value;
default: ledr_value <= 10'b1111_1111_11;
endcase
end
always @(posedge clock_2hz) begin: state_FFs
current_state <= next_state;
end
reg vga_correct_hold;
always @(posedge abcd_kyle_signal) begin
vga_correct_hold <= p2_correct[0];
end
wire [7:0] x,y;
wire [2:0] colour;
wire draw_full_box;
translator trans0(
.correct(p2_correct),
.columns(p1_addr),
.selection(p2_value[1:0]),
.X(x),
.Y(y),
.colour(colour),
.draw_full(draw_full_box),
.reset(~game_over)
);
rate_divider rate2(
.clock_in(CLOCK_50),
.rate(28'b00011_00101_10111_00110_110),
.clock_out(refresh)
);
reg h;
always @(posedge refresh) begin
h <= ~h;
end
tumbler_vga tummy0(
.clock(CLOCK_50),
.colour_in(colour),
.draw_full(draw_full_box),
.draw(h),
.x_in(x),
.y_in(y),
.resetn(~game_over),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
defparam tummy0.BACKGROUND_IMAGE = "../res/spybackground.mif";
endmodule | 2 |
141,963 | data/full_repos/permissive/96478792/src/morse_decoder.v | 96,478,792 | morse_decoder.v | v | 107 | 92 | [] | [] | [] | [(9, 106)] | null | data/verilator_xmls/1e0f8b53-2064-432d-91b2-ae4ab4cf13a9.xml | null | 312,826 | module | module morse_decoder(
clock,
user_input,
resetn,
ld_dot,
ld_line
);
input clock;
input user_input;
input resetn;
output ld_dot, ld_line;
reg morse_dot, morse_line;
reg [3:0] current_state, next_state;
localparam S_WAIT = 4'd0,
S_F1 = 4'd1,
S_F2 = 4'd2,
S_F3 = 4'd3,
S_DOT = 4'd4,
S_LINE = 4'd5 ;
always @(*) begin: state_table
case (current_state)
S_WAIT: next_state = user_input ? S_WAIT : S_F1;
S_F1: next_state = user_input ? S_DOT : S_F2;
S_F2: next_state = user_input ? S_WAIT : S_F3;
S_F3: next_state = user_input ? S_LINE : S_F1;
S_DOT: next_state = user_input ? S_WAIT : S_F1;
S_LINE: next_state = user_input ? S_WAIT : S_F1;
default: next_state = S_WAIT;
endcase
end
always @(*) begin: enable_signals
case (current_state)
S_DOT: begin
morse_dot <= 1'b1;
end
S_LINE: begin
morse_line <= 1'b1;
end
default: begin
morse_dot <= 1'b0;
morse_line <= 1'b0;
end
endcase
end
always@(posedge clock) begin: state_FFs
if (resetn)
current_state <= S_WAIT;
else
current_state <= next_state;
end
assign ld_dot = morse_dot;
assign ld_line = morse_line;
endmodule | module morse_decoder(
clock,
user_input,
resetn,
ld_dot,
ld_line
); |
input clock;
input user_input;
input resetn;
output ld_dot, ld_line;
reg morse_dot, morse_line;
reg [3:0] current_state, next_state;
localparam S_WAIT = 4'd0,
S_F1 = 4'd1,
S_F2 = 4'd2,
S_F3 = 4'd3,
S_DOT = 4'd4,
S_LINE = 4'd5 ;
always @(*) begin: state_table
case (current_state)
S_WAIT: next_state = user_input ? S_WAIT : S_F1;
S_F1: next_state = user_input ? S_DOT : S_F2;
S_F2: next_state = user_input ? S_WAIT : S_F3;
S_F3: next_state = user_input ? S_LINE : S_F1;
S_DOT: next_state = user_input ? S_WAIT : S_F1;
S_LINE: next_state = user_input ? S_WAIT : S_F1;
default: next_state = S_WAIT;
endcase
end
always @(*) begin: enable_signals
case (current_state)
S_DOT: begin
morse_dot <= 1'b1;
end
S_LINE: begin
morse_line <= 1'b1;
end
default: begin
morse_dot <= 1'b0;
morse_line <= 1'b0;
end
endcase
end
always@(posedge clock) begin: state_FFs
if (resetn)
current_state <= S_WAIT;
else
current_state <= next_state;
end
assign ld_dot = morse_dot;
assign ld_line = morse_line;
endmodule | 2 |
141,964 | data/full_repos/permissive/96478792/src/player1.v | 96,478,792 | player1.v | v | 69 | 64 | [] | [] | [] | null | line:124: before: ")" | null | 1: b'%Error: data/full_repos/permissive/96478792/src/player1.v:4: Cannot find include file: morse_decoder.v\n`include "morse_decoder.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96478792/src,data/full_repos/permissive/96478792/morse_decoder.v\n data/full_repos/permissive/96478792/src,data/full_repos/permissive/96478792/morse_decoder.v.v\n data/full_repos/permissive/96478792/src,data/full_repos/permissive/96478792/morse_decoder.v.sv\n morse_decoder.v\n morse_decoder.v.v\n morse_decoder.v.sv\n obj_dir/morse_decoder.v\n obj_dir/morse_decoder.v.v\n obj_dir/morse_decoder.v.sv\n%Error: data/full_repos/permissive/96478792/src/player1.v:19: syntax error, unexpected \')\', expecting \'[\'\n );\n ^\n%Error: data/full_repos/permissive/96478792/src/player1.v:41: syntax error, unexpected IDENTIFIER\n morse_decoder morse1(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 312,827 | module | module player1(
clock,
user_input,
next_input,
write,
q,
);
input clock;
input user_input;
input next_input;
output [9:0] q;
output reg write;
reg [9:0] p1_value;
wire ld_dot, ld_line;
reg [3:0] old_addr;
localparam MORSE_NONE = 2'b00,
MORSE_DOT = 2'b01,
MORSE_LINE = 2'b11 ;
morse_decoder morse1(
.clock(clock),
.user_input(user_input),
.resetn(1'b0),
.ld_dot(ld_dot),
.ld_line(ld_line)
);
always @(posedge clock) begin
if (write) begin
write <= 1'b0;
p1_value <= 10'b0;
end
else if (next_input) begin
write <= 1'b1;
end
else if (ld_dot)
p1_value <= { p1_value[7:0], MORSE_DOT };
else if (ld_line)
p1_value <= { p1_value[7:0], MORSE_LINE };
end
assign q = p1_value;
endmodule | module player1(
clock,
user_input,
next_input,
write,
q,
); |
input clock;
input user_input;
input next_input;
output [9:0] q;
output reg write;
reg [9:0] p1_value;
wire ld_dot, ld_line;
reg [3:0] old_addr;
localparam MORSE_NONE = 2'b00,
MORSE_DOT = 2'b01,
MORSE_LINE = 2'b11 ;
morse_decoder morse1(
.clock(clock),
.user_input(user_input),
.resetn(1'b0),
.ld_dot(ld_dot),
.ld_line(ld_line)
);
always @(posedge clock) begin
if (write) begin
write <= 1'b0;
p1_value <= 10'b0;
end
else if (next_input) begin
write <= 1'b1;
end
else if (ld_dot)
p1_value <= { p1_value[7:0], MORSE_DOT };
else if (ld_line)
p1_value <= { p1_value[7:0], MORSE_LINE };
end
assign q = p1_value;
endmodule | 2 |
141,967 | data/full_repos/permissive/96478792/src/rate_divider.v | 96,478,792 | rate_divider.v | v | 34 | 73 | [] | [] | [] | [(7, 33)] | null | data/verilator_xmls/e7706a99-cf8a-4924-b20c-26078ab01ab3.xml | null | 312,831 | module | module rate_divider(
clock_in,
rate,
clock_out);
input clock_in;
input [27:0] rate;
output clock_out;
reg [27:0] rate_counter;
always @(posedge clock_in) begin
if (rate_counter == rate)
rate_counter <= 0;
else
rate_counter <= rate_counter + 1'b1;
end
assign clock_out = (rate_counter == rate) ? 1'b1 : 1'b0;
endmodule | module rate_divider(
clock_in,
rate,
clock_out); |
input clock_in;
input [27:0] rate;
output clock_out;
reg [27:0] rate_counter;
always @(posedge clock_in) begin
if (rate_counter == rate)
rate_counter <= 0;
else
rate_counter <= rate_counter + 1'b1;
end
assign clock_out = (rate_counter == rate) ? 1'b1 : 1'b0;
endmodule | 2 |
141,971 | data/full_repos/permissive/96478792/test/tester.v | 96,478,792 | tester.v | v | 119 | 92 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/96478792/test/tester.v:4: Cannot find include file: rate_divider.v\n`include "rate_divider.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/rate_divider.v\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/rate_divider.v.v\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/rate_divider.v.sv\n rate_divider.v\n rate_divider.v.v\n rate_divider.v.sv\n obj_dir/rate_divider.v\n obj_dir/rate_divider.v.v\n obj_dir/rate_divider.v.sv\n%Error: data/full_repos/permissive/96478792/test/tester.v:5: Cannot find include file: hex_decoder.v\n`include "hex_decoder.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/test/tester.v:6: Cannot find include file: player2.v\n`include "player2.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/test/tester.v:7: Cannot find include file: tumbler_vga.v\n`include "tumbler_vga.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/test/tester.v:8: Cannot find include file: ram32x10.v\n`include "ram32x10.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/test/tester.v:9: Cannot find include file: translator.v\n`include "translator.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/test/tester.v:86: syntax error, unexpected \'(\', expecting IDENTIFIER\n .clock_in(CLOCK_50),\n ^\n%Error: Exiting due to 7 error(s)\n' | 312,838 | module | module tester(
CLOCK_50,
KEY,
SW,
LEDR,
LEDG,
HEX0,
HEX2,
HEX3,
HEX4,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [9:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0, HEX2, HEX3, HEX4;
wire p2_correct, p2_signal, draw_full_box, refresh;
wire [5:0] p1_addr;
wire [1:0] p2_value;
wire [7:0] x, y ;
wire [2:0] colour;
assign p2_correct = SW[17];
assign p2_signal = KEY[2];
assign p1_addr = 6'b000100;
assign p2_value = SW[1:0];
translator trans0(
.correct(p2_correct),
.signal(p2_signal),
.columns(p1_addr),
.selection(p2_value),
.X(x),
.Y(y),
.colour(colour),
.draw_full(draw_full_box),
.reset(KEY[3])
);
assign LEDR[2:0] = colour;
rate_divider(
.clock_in(CLOCK_50),
.rate(28'b00011_00101_10111_00110_110),
.clock_out(refresh));
reg h;
always @(posedge refresh) begin
if (h)
h <= 1'b0;
else
h <= 1'b1;
end
assign LEDR[4] = h;
tumbler_vga tummy0(
.clock(CLOCK_50),
.colour_in(colour),
.draw_full(draw_full_box),
.draw(h),
.x_in(x),
.y_in(y),
.resetn(KEY[3]),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
endmodule | module tester(
CLOCK_50,
KEY,
SW,
LEDR,
LEDG,
HEX0,
HEX2,
HEX3,
HEX4,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [9:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0, HEX2, HEX3, HEX4;
wire p2_correct, p2_signal, draw_full_box, refresh;
wire [5:0] p1_addr;
wire [1:0] p2_value;
wire [7:0] x, y ;
wire [2:0] colour;
assign p2_correct = SW[17];
assign p2_signal = KEY[2];
assign p1_addr = 6'b000100;
assign p2_value = SW[1:0];
translator trans0(
.correct(p2_correct),
.signal(p2_signal),
.columns(p1_addr),
.selection(p2_value),
.X(x),
.Y(y),
.colour(colour),
.draw_full(draw_full_box),
.reset(KEY[3])
);
assign LEDR[2:0] = colour;
rate_divider(
.clock_in(CLOCK_50),
.rate(28'b00011_00101_10111_00110_110),
.clock_out(refresh));
reg h;
always @(posedge refresh) begin
if (h)
h <= 1'b0;
else
h <= 1'b1;
end
assign LEDR[4] = h;
tumbler_vga tummy0(
.clock(CLOCK_50),
.colour_in(colour),
.draw_full(draw_full_box),
.draw(h),
.x_in(x),
.y_in(y),
.resetn(KEY[3]),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
endmodule | 2 |
141,974 | data/full_repos/permissive/96478792/test/test_ps2_keyboard.v | 96,478,792 | test_ps2_keyboard.v | v | 47 | 42 | [] | [] | [] | [(10, 50), (53, 79), (81, 120)] | null | null | 1: b'%Error: data/full_repos/permissive/96478792/test/test_ps2_keyboard.v:4: Cannot find include file: ../src/ps2_keyboard.v\n`include "../src/ps2_keyboard.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/../src/ps2_keyboard.v\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/../src/ps2_keyboard.v.v\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/../src/ps2_keyboard.v.sv\n ../src/ps2_keyboard.v\n ../src/ps2_keyboard.v.v\n ../src/ps2_keyboard.v.sv\n obj_dir/../src/ps2_keyboard.v\n obj_dir/../src/ps2_keyboard.v.v\n obj_dir/../src/ps2_keyboard.v.sv\n%Error: data/full_repos/permissive/96478792/test/test_ps2_keyboard.v:5: Cannot find include file: ../src/hex_decoder.v\n`include "../src/hex_decoder.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 312,841 | module | module test_ps2_keyboard(
PS2_CLK,
PS2_DAT,
HEX0,
HEX1
);
input PS2_CLK;
input PS2_DAT;
output [6:0] HEX0, HEX1;
wire [7:0] data_out;
wire data_complete;
reg [3:0] hex0_val, hex1_val;
ps2_keyboard keyboard_input(
.ps2_clock(PS2_CLK),
.ps2_data(PS2_DAT),
.data_out(data_out),
.data_complete(data_complete)
);
hex_decoder hex0(
.hex_digit(hex0_val),
.segments(HEX0)
);
hex_decoder hex1(
.hex_digit(hex1_val),
.segments(HEX1)
);
always @(posedge data_complete) begin
hex0_val = data_out[3:0];
hex1_val = data_out[7:4];
end
endmodule | module test_ps2_keyboard(
PS2_CLK,
PS2_DAT,
HEX0,
HEX1
); |
input PS2_CLK;
input PS2_DAT;
output [6:0] HEX0, HEX1;
wire [7:0] data_out;
wire data_complete;
reg [3:0] hex0_val, hex1_val;
ps2_keyboard keyboard_input(
.ps2_clock(PS2_CLK),
.ps2_data(PS2_DAT),
.data_out(data_out),
.data_complete(data_complete)
);
hex_decoder hex0(
.hex_digit(hex0_val),
.segments(HEX0)
);
hex_decoder hex1(
.hex_digit(hex1_val),
.segments(HEX1)
);
always @(posedge data_complete) begin
hex0_val = data_out[3:0];
hex1_val = data_out[7:4];
end
endmodule | 2 |
141,975 | data/full_repos/permissive/96478792/test/test_ram32x20.v | 96,478,792 | test_ram32x20.v | v | 44 | 39 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/96478792/test/test_ram32x20.v:4: Cannot find include file: ../src/player2.v\n`include "../src/player2.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/../src/player2.v\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/../src/player2.v.v\n data/full_repos/permissive/96478792/test,data/full_repos/permissive/96478792/../src/player2.v.sv\n ../src/player2.v\n ../src/player2.v.v\n ../src/player2.v.sv\n obj_dir/../src/player2.v\n obj_dir/../src/player2.v.v\n obj_dir/../src/player2.v.sv\n%Error: data/full_repos/permissive/96478792/test/test_ram32x20.v:5: Cannot find include file: ../src/rate_divider.v\n`include "../src/rate_divider.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/test/test_ram32x20.v:6: Cannot find include file: ../src/ram32x20.v\n`include "../src/ram32x20.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96478792/test/test_ram32x20.v:16: syntax error, unexpected \')\', expecting \'[\'\n );\n ^\n%Error: data/full_repos/permissive/96478792/test/test_ram32x20.v:27: syntax error, unexpected IDENTIFIER\n ram32x20 ram0(\n ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 312,842 | module | module test_ram32x20(
CLOCK_50,
KEY,
SW,
LEDR,
);
input CLOCK_50;
input [17:0] SW;
input [2:0] KEY;
output [17:0] LEDR;
wire [3:0] data_out;
reg [4:0] counter;
ram32x20 ram0(
.data(SW[16:0]),
.address(counter),
.wren(SW[17]),
.clock(KEY[0]),
.q(data_out)
);
always @(negedge KEY[0]) begin
if (!KEY[1])
counter <= 0;
else
counter <= counter + 1'b1;
end
assign LEDR = data_out;
endmodule | module test_ram32x20(
CLOCK_50,
KEY,
SW,
LEDR,
); |
input CLOCK_50;
input [17:0] SW;
input [2:0] KEY;
output [17:0] LEDR;
wire [3:0] data_out;
reg [4:0] counter;
ram32x20 ram0(
.data(SW[16:0]),
.address(counter),
.wren(SW[17]),
.clock(KEY[0]),
.q(data_out)
);
always @(negedge KEY[0]) begin
if (!KEY[1])
counter <= 0;
else
counter <= counter + 1'b1;
end
assign LEDR = data_out;
endmodule | 2 |
141,977 | data/full_repos/permissive/96654114/code/rtl/camera_module_demo/TOP_DEMO.v | 96,654,114 | TOP_DEMO.v | v | 80 | 104 | [] | [] | [] | null | line:9: before: "=" | null | 1: b'%Error: data/full_repos/permissive/96654114/code/rtl/camera_module_demo/TOP_DEMO.v:31: Cannot find include file: SCCB.v\n `include "SCCB.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96654114/code/rtl/camera_module_demo,data/full_repos/permissive/96654114/SCCB.v\n data/full_repos/permissive/96654114/code/rtl/camera_module_demo,data/full_repos/permissive/96654114/SCCB.v.v\n data/full_repos/permissive/96654114/code/rtl/camera_module_demo,data/full_repos/permissive/96654114/SCCB.v.sv\n SCCB.v\n SCCB.v.v\n SCCB.v.sv\n obj_dir/SCCB.v\n obj_dir/SCCB.v.v\n obj_dir/SCCB.v.sv\n%Error: data/full_repos/permissive/96654114/code/rtl/camera_module_demo/TOP_DEMO.v:36: syntax error, unexpected \'@\'\n repeat(400) @(posedge clk_50us);\n ^\n%Error: Exiting due to 2 error(s)\n' | 312,862 | module | module TOP_DEMO (
input sys_clk,
input rst_n,
output reg scl,
inout sda,
input d7, d6, d5, d4, d3, d2, d1, d0,
output reg rclk = 1'b1,
output reg wen = 1'b1,
output reg wrst = 1'b1,
output reg rrst = 1'b1,
input vsync
);
parameter SYS_CLK_FREQ = 100_000_000;
parameter DEVICE_ID = 8'h42;
localparam [11:0] cnt_50us = 12'd2500;
reg clk_50us = 1'b0;
reg[11:0] clk_cnt = cnt_50us;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) clk_cnt <= cnt_50us;
else if (!clk_cnt) clk_cnt <= cnt_50us;
else clk_cnt <= clk_cnt - 1'b1;
always @(posedge sys_clk) if (!clk_cnt) clk_50us <= ~clk_50us;
reg[7:0] conf[0:255];
initial $readmemh("CONF.hex", conf);
`include "SCCB.v"
reg success;
reg[7:0] addr;
initial begin
sccb_write_reg(8'h12, 8'h80, success);
repeat(400) @(posedge clk_50us);
for (addr = 8'h00; addr <= 8'hFF; addr = addr + 1'b1)
sccb_write_reg(addr, conf[addr], success);
end
reg[0:2] vsync_reg = 3'b0;
wire vsync_irq = vsync_reg[1] & ~vsync_reg[2];
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) vsync_reg <= 3'b0;
else vsync_reg <= {vsync, vsync_reg[0:1]};
reg new_frame = 1'b0;
reg frame_read = 1'b0;
reg[2:0] store_state = 3'd0;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) begin wen <= 1'b0; new_frame <= 1'b0; store_state <= 3'd0; end
else case (store_state)
3'd0: if (vsync_irq) if (new_frame) wen <= 1'b0; else store_state <= 3'd1;
3'd1: begin wrst <= 1'b0; store_state <= 3'd2; end
3'd2: begin wrst <= 1'b1; wen <= 1'b1; store_state <= 3'd3; end
3'd3: begin new_frame <= 1'b1; store_state <= 3'd4; end
3'd4: store_state <= 3'd5;
3'd5: if (frame_read) begin new_frame <= 1'b0; store_state <= 3'd0; end
default: store_state <= 3'd0;
endcase
wire[7:0] data = {d7, d6, d5, d4, d3, d2, d1, d0};
localparam [17:0] bytes = 320 * 240 * 2;
reg[17:0] byte_cnt = bytes;
reg[2:0] read_state = 3'd0;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) read_state <= 3'd0;
else case (read_state)
3'd0: if (new_frame) begin frame_read <= 1'b0; byte_cnt <= bytes; read_state <= 3'd1; end
3'd1: begin rclk <= 1'b0; rrst <= 1'b0; read_state <= 3'd2; end
3'd2: begin rclk <= 1'b1; read_state <= 3'd3; end
3'd3: begin rclk <= 1'b0; rrst <= 1'b1; read_state <= 3'd4; end
3'd4: begin rclk <= 1'b1; read_state <= 3'd5; end
3'd5: begin rclk <= 1'b0; byte_cnt <= byte_cnt - 1'b1; read_state <= 3'd6; end
3'd6: begin rclk <= 1'b1; read_state <= byte_cnt ? 3'd5 : 3'd7; end
3'd7: begin frame_read <= 1'b1; read_state <= 3'd0; end
endcase
endmodule | module TOP_DEMO (
input sys_clk,
input rst_n,
output reg scl,
inout sda,
input d7, d6, d5, d4, d3, d2, d1, d0,
output reg rclk = 1'b1,
output reg wen = 1'b1,
output reg wrst = 1'b1,
output reg rrst = 1'b1,
input vsync
); |
parameter SYS_CLK_FREQ = 100_000_000;
parameter DEVICE_ID = 8'h42;
localparam [11:0] cnt_50us = 12'd2500;
reg clk_50us = 1'b0;
reg[11:0] clk_cnt = cnt_50us;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) clk_cnt <= cnt_50us;
else if (!clk_cnt) clk_cnt <= cnt_50us;
else clk_cnt <= clk_cnt - 1'b1;
always @(posedge sys_clk) if (!clk_cnt) clk_50us <= ~clk_50us;
reg[7:0] conf[0:255];
initial $readmemh("CONF.hex", conf);
`include "SCCB.v"
reg success;
reg[7:0] addr;
initial begin
sccb_write_reg(8'h12, 8'h80, success);
repeat(400) @(posedge clk_50us);
for (addr = 8'h00; addr <= 8'hFF; addr = addr + 1'b1)
sccb_write_reg(addr, conf[addr], success);
end
reg[0:2] vsync_reg = 3'b0;
wire vsync_irq = vsync_reg[1] & ~vsync_reg[2];
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) vsync_reg <= 3'b0;
else vsync_reg <= {vsync, vsync_reg[0:1]};
reg new_frame = 1'b0;
reg frame_read = 1'b0;
reg[2:0] store_state = 3'd0;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) begin wen <= 1'b0; new_frame <= 1'b0; store_state <= 3'd0; end
else case (store_state)
3'd0: if (vsync_irq) if (new_frame) wen <= 1'b0; else store_state <= 3'd1;
3'd1: begin wrst <= 1'b0; store_state <= 3'd2; end
3'd2: begin wrst <= 1'b1; wen <= 1'b1; store_state <= 3'd3; end
3'd3: begin new_frame <= 1'b1; store_state <= 3'd4; end
3'd4: store_state <= 3'd5;
3'd5: if (frame_read) begin new_frame <= 1'b0; store_state <= 3'd0; end
default: store_state <= 3'd0;
endcase
wire[7:0] data = {d7, d6, d5, d4, d3, d2, d1, d0};
localparam [17:0] bytes = 320 * 240 * 2;
reg[17:0] byte_cnt = bytes;
reg[2:0] read_state = 3'd0;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) read_state <= 3'd0;
else case (read_state)
3'd0: if (new_frame) begin frame_read <= 1'b0; byte_cnt <= bytes; read_state <= 3'd1; end
3'd1: begin rclk <= 1'b0; rrst <= 1'b0; read_state <= 3'd2; end
3'd2: begin rclk <= 1'b1; read_state <= 3'd3; end
3'd3: begin rclk <= 1'b0; rrst <= 1'b1; read_state <= 3'd4; end
3'd4: begin rclk <= 1'b1; read_state <= 3'd5; end
3'd5: begin rclk <= 1'b0; byte_cnt <= byte_cnt - 1'b1; read_state <= 3'd6; end
3'd6: begin rclk <= 1'b1; read_state <= byte_cnt ? 3'd5 : 3'd7; end
3'd7: begin frame_read <= 1'b1; read_state <= 3'd0; end
endcase
endmodule | 0 |
141,978 | data/full_repos/permissive/96654114/code/rtl/serial_module_demo/CLK_GEN.v | 96,654,114 | CLK_GEN.v | v | 23 | 60 | [] | [] | [] | [(3, 23)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/96654114/code/rtl/serial_module_demo/CLK_GEN.v:14: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg[0:2] clk_reg = 3\'b0;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/serial_module_demo/CLK_GEN.v:17: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'clk_cnt\' generates 32 bits.\n : ... In instance CLK_GEN\n else if (clk_cnt) clk_cnt <= clk_cnt - 1\'b1;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 312,863 | module | module CLK_GEN #(
parameter SYS_CLK_FREQ = 100_000_000,
parameter BAUD_RATE = 115200
)(
input sys_clk,
input rst_n,
output clk
);
localparam max_cnt = SYS_CLK_FREQ / BAUD_RATE - 1;
localparam half_cnt = max_cnt >> 1;
reg[31:0] clk_cnt = max_cnt;
reg[0:2] clk_reg = 3'b0;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) clk_cnt <= max_cnt;
else if (clk_cnt) clk_cnt <= clk_cnt - 1'b1;
else clk_cnt <= max_cnt;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) clk_reg <= 3'b0;
else clk_reg <= {clk_cnt < half_cnt, clk_reg[0:1]};
assign clk = clk_reg[1] & ~clk_reg[2];
endmodule | module CLK_GEN #(
parameter SYS_CLK_FREQ = 100_000_000,
parameter BAUD_RATE = 115200
)(
input sys_clk,
input rst_n,
output clk
); |
localparam max_cnt = SYS_CLK_FREQ / BAUD_RATE - 1;
localparam half_cnt = max_cnt >> 1;
reg[31:0] clk_cnt = max_cnt;
reg[0:2] clk_reg = 3'b0;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) clk_cnt <= max_cnt;
else if (clk_cnt) clk_cnt <= clk_cnt - 1'b1;
else clk_cnt <= max_cnt;
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) clk_reg <= 3'b0;
else clk_reg <= {clk_cnt < half_cnt, clk_reg[0:1]};
assign clk = clk_reg[1] & ~clk_reg[2];
endmodule | 0 |
141,979 | data/full_repos/permissive/96654114/code/rtl/serial_module_demo/TOP_DEMO.v | 96,654,114 | TOP_DEMO.v | v | 28 | 83 | [] | [] | [] | [(3, 27)] | null | null | 1: b"%Error: data/full_repos/permissive/96654114/code/rtl/serial_module_demo/TOP_DEMO.v:13: Cannot find file containing module: 'CLK_GEN'\n CLK_GEN #(SYS_CLK_FREQ, BAUD_RATE) clk_gen(sys_clk, rst_n, clk);\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/96654114/code/rtl/serial_module_demo,data/full_repos/permissive/96654114/CLK_GEN\n data/full_repos/permissive/96654114/code/rtl/serial_module_demo,data/full_repos/permissive/96654114/CLK_GEN.v\n data/full_repos/permissive/96654114/code/rtl/serial_module_demo,data/full_repos/permissive/96654114/CLK_GEN.sv\n CLK_GEN\n CLK_GEN.v\n CLK_GEN.sv\n obj_dir/CLK_GEN\n obj_dir/CLK_GEN.v\n obj_dir/CLK_GEN.sv\n%Error: data/full_repos/permissive/96654114/code/rtl/serial_module_demo/TOP_DEMO.v:18: Cannot find file containing module: 'UART_RX'\n UART_RX rx(clk, rst_n, rx_pin, rx_error, rx_finish, rx_data);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/serial_module_demo/TOP_DEMO.v:23: Cannot find file containing module: 'UART_TX'\n UART_TX tx(clk, rst_n, tx_pin, tx_start, tx_finish, tx_data);\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 312,864 | module | module TOP_DEMO (
input sys_clk,
input rst_n,
input rx_pin,
output tx_pin
);
parameter SYS_CLK_FREQ = 100_000_000;
parameter BAUD_RATE = 115200;
wire clk;
CLK_GEN #(SYS_CLK_FREQ, BAUD_RATE) clk_gen(sys_clk, rst_n, clk);
wire rx_error;
wire rx_finish;
wire[7:0] rx_data;
UART_RX rx(clk, rst_n, rx_pin, rx_error, rx_finish, rx_data);
reg tx_start = 1'b0;
wire tx_finish;
reg[7:0] tx_data = 8'h00;
UART_TX tx(clk, rst_n, tx_pin, tx_start, tx_finish, tx_data);
always @(posedge sys_clk) begin tx_start <= rx_finish; tx_data <= rx_data; end
endmodule | module TOP_DEMO (
input sys_clk,
input rst_n,
input rx_pin,
output tx_pin
); |
parameter SYS_CLK_FREQ = 100_000_000;
parameter BAUD_RATE = 115200;
wire clk;
CLK_GEN #(SYS_CLK_FREQ, BAUD_RATE) clk_gen(sys_clk, rst_n, clk);
wire rx_error;
wire rx_finish;
wire[7:0] rx_data;
UART_RX rx(clk, rst_n, rx_pin, rx_error, rx_finish, rx_data);
reg tx_start = 1'b0;
wire tx_finish;
reg[7:0] tx_data = 8'h00;
UART_TX tx(clk, rst_n, tx_pin, tx_start, tx_finish, tx_data);
always @(posedge sys_clk) begin tx_start <= rx_finish; tx_data <= rx_data; end
endmodule | 0 |
141,980 | data/full_repos/permissive/96654114/code/rtl/TOP/DISPLAY.v | 96,654,114 | DISPLAY.v | v | 29 | 49 | [] | [] | [] | [(3, 28)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/96654114/code/rtl/TOP/DISPLAY.v:8: Little bit endian vector: MSB < LSB of bit range: 0:7\n output reg[0:7] Y\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/DISPLAY.v:26: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance DISPLAY\n default: Y <= 32\'hFFFFFFFF;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 312,868 | module | module DISPLAY (
input clk_250Hz,
input rst_n,
input [31:0] data,
output reg[3:0] AN,
output reg[0:7] Y
);
always @(posedge clk_250Hz or negedge rst_n)
if (!rst_n) AN <= 4'b1111;
else case (AN)
4'b0111: AN <= 4'b1011;
4'b1011: AN <= 4'b1101;
4'b1101: AN <= 4'b1110;
4'b1110: AN <= 4'b0111;
default: AN <= 4'b0111;
endcase
always @(AN or data)
case (AN)
4'b0111: Y <= data[31:24];
4'b1011: Y <= data[23:16];
4'b1101: Y <= data[15:8];
4'b1110: Y <= data[7:0];
default: Y <= 32'hFFFFFFFF;
endcase
endmodule | module DISPLAY (
input clk_250Hz,
input rst_n,
input [31:0] data,
output reg[3:0] AN,
output reg[0:7] Y
); |
always @(posedge clk_250Hz or negedge rst_n)
if (!rst_n) AN <= 4'b1111;
else case (AN)
4'b0111: AN <= 4'b1011;
4'b1011: AN <= 4'b1101;
4'b1101: AN <= 4'b1110;
4'b1110: AN <= 4'b0111;
default: AN <= 4'b0111;
endcase
always @(AN or data)
case (AN)
4'b0111: Y <= data[31:24];
4'b1011: Y <= data[23:16];
4'b1101: Y <= data[15:8];
4'b1110: Y <= data[7:0];
default: Y <= 32'hFFFFFFFF;
endcase
endmodule | 0 |
141,981 | data/full_repos/permissive/96654114/code/rtl/TOP/MOTOR.v | 96,654,114 | MOTOR.v | v | 26 | 80 | [] | [] | [] | [(3, 25)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/MOTOR.v:17: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'clk_cnt\' generates 10 bits.\n : ... In instance MOTOR\n end else if (clk_cnt) begin\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,869 | module | module MOTOR (
input clk_1MHz,
input rst_n,
input [1:0] direction,
output reg[1:0] en,
output reg pwm
);
localparam [9:0] max_cnt = 10'd1000;
reg[9:0] clk_cnt = max_cnt;
reg[9:0] pwm_cnt = 10'd500;
always @(posedge clk_1MHz or negedge rst_n)
if (!rst_n) begin
clk_cnt <= max_cnt;
en <= 2'b00; pwm <= 1'b0;
end else if (clk_cnt) begin
clk_cnt <= clk_cnt - 1'd1;
case (direction)
2'b11: begin en <= 2'b10; pwm <= clk_cnt < pwm_cnt; end
2'b00: begin en <= 2'b01; pwm <= clk_cnt < pwm_cnt; end
default: begin en <= 2'b00; pwm <= 1'b0; end
endcase
end else clk_cnt <= max_cnt;
endmodule | module MOTOR (
input clk_1MHz,
input rst_n,
input [1:0] direction,
output reg[1:0] en,
output reg pwm
); |
localparam [9:0] max_cnt = 10'd1000;
reg[9:0] clk_cnt = max_cnt;
reg[9:0] pwm_cnt = 10'd500;
always @(posedge clk_1MHz or negedge rst_n)
if (!rst_n) begin
clk_cnt <= max_cnt;
en <= 2'b00; pwm <= 1'b0;
end else if (clk_cnt) begin
clk_cnt <= clk_cnt - 1'd1;
case (direction)
2'b11: begin en <= 2'b10; pwm <= clk_cnt < pwm_cnt; end
2'b00: begin en <= 2'b01; pwm <= clk_cnt < pwm_cnt; end
default: begin en <= 2'b00; pwm <= 1'b0; end
endcase
end else clk_cnt <= max_cnt;
endmodule | 0 |
141,982 | data/full_repos/permissive/96654114/code/rtl/TOP/OV_INIT.v | 96,654,114 | OV_INIT.v | v | 279 | 112 | [] | [] | [] | null | line:8: before: "=" | null | 1: b'%Error: data/full_repos/permissive/96654114/code/rtl/TOP/OV_INIT.v:21: Unsupported: Replication to form \'logic[7:0]$[0:335]\' data type\n : ... In instance OV_INIT\n localparam [7:0] conf[0:conf_cnt-1] = {\n ^\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/OV_INIT.v:21: Operator VAR \'conf\' expects 8 bits on the Initial value, but Initial value\'s REPLICATE generates 2688 bits.\n : ... In instance OV_INIT\n localparam [7:0] conf[0:conf_cnt-1] = {\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,870 | module | module OV_INIT #(
parameter [7:0] DEVICE_ID = 8'h42
)(
input clk_100kHz,
input rst_n,
output reg scl = 1'b1,
inout sda,
output reg initialized = 1'b0,
output reg new_data = 1'b0,
output reg[7:0] data
);
wire sda_in = sda;
reg sda_out = 1'b1;
reg sda_oe = 1'b1;
assign sda = sda_oe ? sda_out : 1'bZ;
pullup(sda);
localparam [8:0] conf_cnt = 9'd336;
localparam [7:0] conf[0:conf_cnt-1] = {
8'h3A, 8'h04, 8'h40, 8'hD0, 8'h12, 8'h14, 8'h32, 8'h80, 8'h17, 8'h16, 8'h18, 8'h04, 8'h19, 8'h02,
8'h1A, 8'h7B, 8'h03, 8'h06, 8'h0C, 8'h00, 8'h15, 8'h00, 8'h3E, 8'h00, 8'h70, 8'h3A, 8'h71, 8'h35,
8'h72, 8'h11, 8'h73, 8'h00, 8'hA2, 8'h02, 8'h11, 8'h81, 8'h7A, 8'h20, 8'h7B, 8'h1C, 8'h7C, 8'h28,
8'h7D, 8'h3C, 8'h7E, 8'h55, 8'h7F, 8'h68, 8'h80, 8'h76, 8'h81, 8'h80, 8'h82, 8'h88, 8'h83, 8'h8F,
8'h84, 8'h96, 8'h85, 8'hA3, 8'h86, 8'hAF, 8'h87, 8'hC4, 8'h88, 8'hD7, 8'h89, 8'hE8, 8'h13, 8'hE0,
8'h00, 8'h00, 8'h10, 8'h00, 8'h0D, 8'h00, 8'h14, 8'h28, 8'hA5, 8'h05, 8'hAB, 8'h07, 8'h24, 8'h75,
8'h25, 8'h63, 8'h26, 8'hA5, 8'h9F, 8'h78, 8'hA0, 8'h68, 8'hA1, 8'h03, 8'hA6, 8'hDF, 8'hA7, 8'hDF,
8'hA8, 8'hF0, 8'hA9, 8'h90, 8'hAA, 8'h94, 8'h13, 8'hE5, 8'h0E, 8'h61, 8'h0F, 8'h4B, 8'h16, 8'h02,
8'h1E, 8'h27, 8'h21, 8'h02, 8'h22, 8'h91, 8'h29, 8'h07, 8'h33, 8'h0B, 8'h35, 8'h0B, 8'h37, 8'h1D,
8'h38, 8'h71, 8'h39, 8'h2A, 8'h3C, 8'h78, 8'h4D, 8'h40, 8'h4E, 8'h20, 8'h69, 8'h00, 8'h6B, 8'h40,
8'h74, 8'h19, 8'h8D, 8'h4F, 8'h8E, 8'h00, 8'h8F, 8'h00, 8'h90, 8'h00, 8'h91, 8'h00, 8'h92, 8'h00,
8'h96, 8'h00, 8'h9A, 8'h80, 8'hB0, 8'h84, 8'hB1, 8'h0C, 8'hB2, 8'h0E, 8'hB3, 8'h82, 8'hB8, 8'h0A,
8'h43, 8'h14, 8'h44, 8'hF0, 8'h45, 8'h34, 8'h46, 8'h58, 8'h47, 8'h28, 8'h48, 8'h3A, 8'h59, 8'h88,
8'h5A, 8'h88, 8'h5B, 8'h44, 8'h5C, 8'h67, 8'h5D, 8'h49, 8'h5E, 8'h0E, 8'h64, 8'h04, 8'h65, 8'h20,
8'h66, 8'h05, 8'h94, 8'h04, 8'h95, 8'h08, 8'h6C, 8'h0A, 8'h6D, 8'h55, 8'h4F, 8'h80, 8'h50, 8'h80,
8'h51, 8'h00, 8'h52, 8'h22, 8'h53, 8'h5E, 8'h54, 8'h80, 8'h09, 8'h03, 8'h6E, 8'h11, 8'h6F, 8'h9F,
8'h55, 8'h00, 8'h56, 8'h40, 8'h57, 8'h40, 8'h6A, 8'h40, 8'h01, 8'h40, 8'h02, 8'h40, 8'h13, 8'hE7,
8'h15, 8'h00, 8'h58, 8'h9E, 8'h41, 8'h08, 8'h3F, 8'h00, 8'h75, 8'h05, 8'h76, 8'hE1, 8'h4C, 8'h00,
8'h77, 8'h01, 8'h3D, 8'hC2, 8'h4B, 8'h09, 8'hC9, 8'h60, 8'h41, 8'h38, 8'h34, 8'h11, 8'h3B, 8'h02,
8'hA4, 8'h89, 8'h96, 8'h00, 8'h97, 8'h30, 8'h98, 8'h20, 8'h99, 8'h30, 8'h9A, 8'h84, 8'h9B, 8'h29,
8'h9C, 8'h03, 8'h9D, 8'h4C, 8'h9E, 8'h3F, 8'h78, 8'h04, 8'h79, 8'h01, 8'hC8, 8'hF0, 8'h79, 8'h0F,
8'hC8, 8'h00, 8'h79, 8'h10, 8'hC8, 8'h7E, 8'h79, 8'h0A, 8'hC8, 8'h80, 8'h79, 8'h0B, 8'hC8, 8'h01,
8'h79, 8'h0C, 8'hC8, 8'h0F, 8'h79, 8'h0D, 8'hC8, 8'h20, 8'h79, 8'h09, 8'hC8, 8'h80, 8'h79, 8'h02,
8'hC8, 8'hC0, 8'h79, 8'h03, 8'hC8, 8'h40, 8'h79, 8'h05, 8'hC8, 8'h30, 8'h79, 8'h26, 8'h09, 8'h00
};
localparam [8:0] cnt_50us = 9'd50_0;
localparam [9:0] cnt_100us = 10'd100_0;
localparam [14:0] cnt_2ms = 15'd2_000_0;
localparam [18:0] cnt_50ms = 19'd50_000_0;
reg[18:0] delay_cnt = cnt_50ms;
reg[2:0] bit_cnt = 1'd0;
reg[7:0] reg_data = 8'h00;
reg[8:0] idx = 1'd0;
reg[7:0] state = 8'h00;
always @(posedge clk_100kHz or negedge rst_n)
if (!rst_n) begin
scl <= 1'b1; sda_out <= 1'b1; sda_oe <= 1'b1;
initialized <= 1'b0;
delay_cnt <= 1'd0; state <= 8'h00;
end else if (delay_cnt) delay_cnt <= delay_cnt - 1'd1;
else if (!initialized)
case (state)
8'h00: begin sda_out <= 1'b1; state <= 8'h01; end
8'h01: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h02; end
8'h02: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h03; end
8'h03: begin scl <= 1'b0; state <= 8'h04; end
8'h04: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h05; end
8'h05: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h06; end
8'h06: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h07; end
8'h07: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h05 : 8'h08; end
8'h08: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h09; end
8'h09: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h0A; end
8'h0A: begin new_data <= 1'b1; data <= sda_in; state <= 8'h0B; end
8'h0B: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h0C; end
8'h0C: begin bit_cnt <= 3'd7; reg_data <= 8'h12; state <= 8'h0D; end
8'h0D: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h0E; end
8'h0E: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h0F; end
8'h0F: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h0D : 8'h10; end
8'h10: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h11; end
8'h11: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h12; end
8'h12: begin new_data <= 1'b1; data <= sda_in; state <= 8'h13; end
8'h13: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h14; end
8'h14: begin bit_cnt <= 3'd7; reg_data <= 8'h80; state <= 8'h15; end
8'h15: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h16; end
8'h16: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h17; end
8'h17: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h15 : 8'h18; end
8'h18: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h19; end
8'h19: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h1A; end
8'h1A: begin new_data <= 1'b1; data <= sda_in; state <= 8'h1B; end
8'h1B: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; state <= 8'h1C; end
8'h1C: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h1D; end
8'h1D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h1E; end
8'h1E: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h1F; end
8'h1F: begin delay_cnt <= cnt_50ms; state <= 8'h20; end
8'h20: begin sda_out <= 1'b1; state <= 8'h21; end
8'h21: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h22; end
8'h22: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h23; end
8'h23: begin scl <= 1'b0; state <= 8'h24; end
8'h24: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h25; end
8'h25: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h26; end
8'h26: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h27; end
8'h27: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h25 : 8'h28; end
8'h28: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h29; end
8'h29: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h2A; end
8'h2A: begin new_data <= 1'b1; data <= sda_in; state <= 8'h2B; end
8'h2B: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h2C; end
8'h2C: begin bit_cnt <= 3'd7; reg_data <= 8'h0B; state <= 8'h2D; end
8'h2D: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h2E; end
8'h2E: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h2F; end
8'h2F: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h2D : 8'h30; end
8'h30: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h31; end
8'h31: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h32; end
8'h32: begin new_data <= 1'b1; data <= sda_in; state <= 8'h33; end
8'h33: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h34; end
8'h34: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h35; end
8'h35: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h36; end
8'h36: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h37; end
8'h37: begin delay_cnt <= cnt_100us; state <= 8'h38; end
8'h38: begin sda_out <= 1'b1; state <= 8'h39; end
8'h39: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h3A; end
8'h3A: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h3B; end
8'h3B: begin scl <= 1'b0; state <= 8'h3C; end
8'h3C: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID | 1'b1; state <= 8'h3D; end
8'h3D: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h3E; end
8'h3E: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h3F; end
8'h3F: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h3D : 8'h40; end
8'h40: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h41; end
8'h41: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h42; end
8'h42: begin new_data <= 1'b1; data <= sda_in; state <= 8'h43; end
8'h43: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h44; end
8'h44: begin sda_oe <= 1'b0; bit_cnt <= 3'd7; delay_cnt <= cnt_50us; state <= 8'h45; end
8'h45: begin scl <= 1'b1; data[bit_cnt] <= sda_in; delay_cnt <= cnt_50us; state <= 8'h46; end
8'h46: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h47 : 8'h48; end
8'h47: begin delay_cnt <= cnt_50us; state <= 8'h45; end
8'h48: begin sda_oe <= 1'b1; state <= 8'h49; end
8'h49: begin new_data <= 1'b1; state <= 8'h4A; end
8'h4A: begin new_data <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h4B; end
8'h4B: begin sda_out <= 1'b1; state <= 8'h4C; end
8'h4C: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h4D; end
8'h4D: begin scl <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h4E; end
8'h4E: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h4F; end
8'h4F: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h51; end
8'h51: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h52; end
8'h52: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h53; end
8'h53: begin delay_cnt <= cnt_100us; state <= 8'h54; end
8'h54: begin sda_out <= 1'b1; state <= 8'h55; end
8'h55: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h56; end
8'h56: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h57; end
8'h57: begin scl <= 1'b0; state <= 8'h58; end
8'h58: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h59; end
8'h59: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h5A; end
8'h5A: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h5B; end
8'h5B: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h59 : 8'h5C; end
8'h5C: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h5D; end
8'h5D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h5E; end
8'h5E: begin new_data <= 1'b1; data <= sda_in; state <= 8'h5F; end
8'h5F: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h60; end
8'h60: begin bit_cnt <= 3'd7; reg_data <= 8'h0A; state <= 8'h61; end
8'h61: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h62; end
8'h62: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h63; end
8'h63: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h61 : 8'h64; end
8'h64: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h65; end
8'h65: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h66; end
8'h66: begin new_data <= 1'b1; data <= sda_in; state <= 8'h67; end
8'h67: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h68; end
8'h68: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h69; end
8'h69: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h6A; end
8'h6A: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h6B; end
8'h6B: begin delay_cnt <= cnt_100us; state <= 8'h6C; end
8'h6C: begin sda_out <= 1'b1; state <= 8'h6D; end
8'h6D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h6E; end
8'h6E: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h6F; end
8'h6F: begin scl <= 1'b0; state <= 8'h70; end
8'h70: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID | 1'b1; state <= 8'h71; end
8'h71: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h72; end
8'h72: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h73; end
8'h73: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h71 : 8'h74; end
8'h74: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h75; end
8'h75: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h76; end
8'h76: begin new_data <= 1'b1; data <= sda_in; state <= 8'h77; end
8'h77: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h78; end
8'h78: begin sda_oe <= 1'b0; bit_cnt <= 3'd7; delay_cnt <= cnt_50us; state <= 8'h79; end
8'h79: begin scl <= 1'b1; data[bit_cnt] <= sda_in; delay_cnt <= cnt_50us; state <= 8'h7A; end
8'h7A: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h7B : 8'h7C; end
8'h7B: begin delay_cnt <= cnt_50us; state <= 8'h79; end
8'h7C: begin sda_oe <= 1'b1; state <= 8'h7D; end
8'h7D: begin new_data <= 1'b1; state <= 8'h7E; end
8'h7E: begin new_data <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h7F; end
8'h7F: begin sda_out <= 1'b1; state <= 8'h80; end
8'h80: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h81; end
8'h81: begin scl <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h82; end
8'h82: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h83; end
8'h83: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h84; end
8'h84: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h85; end
8'h85: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h86; end
8'h86: begin delay_cnt <= cnt_100us; state <= 8'h87; end
8'h87: begin sda_out <= 1'b1; state <= 8'h88; end
8'h88: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h89; end
8'h89: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h8A; end
8'h8A: begin scl <= 1'b0; state <= 8'h8B; end
8'h8B: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h8C; end
8'h8C: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h8D; end
8'h8D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h8E; end
8'h8E: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h8C : 8'h8F; end
8'h8F: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h90; end
8'h90: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h91; end
8'h91: begin new_data <= 1'b1; data <= sda_in; state <= 8'h92; end
8'h92: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h93; end
8'h93: begin bit_cnt <= 3'd7; reg_data <= conf[idx]; idx <= idx + 1'd1; state <= 8'h94; end
8'h94: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h95; end
8'h95: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h96; end
8'h96: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h94 : 8'h97; end
8'h97: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h98; end
8'h98: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h99; end
8'h99: begin new_data <= 1'b1; data <= sda_in; state <= 8'h9A; end
8'h9A: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h9B; end
8'h9B: begin bit_cnt <= 3'd7; reg_data <= conf[idx]; idx <= idx + 1'd1; state <= 8'h9C; end
8'h9C: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h9D; end
8'h9D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h9E; end
8'h9E: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h9C : 8'h9F; end
8'h9F: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'hA0; end
8'hA0: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'hA1; end
8'hA1: begin new_data <= 1'b1; data <= sda_in; state <= 8'hA2; end
8'hA2: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; state <= 8'hA3; end
8'hA3: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'hA4; end
8'hA4: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'hA5; end
8'hA5: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'hA6; end
8'hA6: begin delay_cnt <= cnt_2ms; state <= idx == conf_cnt ? 8'hA7 : 8'h87; end
8'hA7: begin new_data <= 1'b1; data <= 8'h0D; state <= 8'hA8; end
8'hA8: begin new_data <= 1'b0; delay_cnt <= cnt_50us; state <= 8'hA9; end
8'hA9: begin new_data <= 1'b1; data <= 8'h0A; state <= 8'hAA; end
8'hAA: begin new_data <= 1'b0; delay_cnt <= cnt_50ms; state <= 8'hAB; end
8'hAB: initialized <= 1'b1;
default: state <= 8'h00;
endcase
endmodule | module OV_INIT #(
parameter [7:0] DEVICE_ID = 8'h42
)(
input clk_100kHz,
input rst_n,
output reg scl = 1'b1,
inout sda,
output reg initialized = 1'b0,
output reg new_data = 1'b0,
output reg[7:0] data
); |
wire sda_in = sda;
reg sda_out = 1'b1;
reg sda_oe = 1'b1;
assign sda = sda_oe ? sda_out : 1'bZ;
pullup(sda);
localparam [8:0] conf_cnt = 9'd336;
localparam [7:0] conf[0:conf_cnt-1] = {
8'h3A, 8'h04, 8'h40, 8'hD0, 8'h12, 8'h14, 8'h32, 8'h80, 8'h17, 8'h16, 8'h18, 8'h04, 8'h19, 8'h02,
8'h1A, 8'h7B, 8'h03, 8'h06, 8'h0C, 8'h00, 8'h15, 8'h00, 8'h3E, 8'h00, 8'h70, 8'h3A, 8'h71, 8'h35,
8'h72, 8'h11, 8'h73, 8'h00, 8'hA2, 8'h02, 8'h11, 8'h81, 8'h7A, 8'h20, 8'h7B, 8'h1C, 8'h7C, 8'h28,
8'h7D, 8'h3C, 8'h7E, 8'h55, 8'h7F, 8'h68, 8'h80, 8'h76, 8'h81, 8'h80, 8'h82, 8'h88, 8'h83, 8'h8F,
8'h84, 8'h96, 8'h85, 8'hA3, 8'h86, 8'hAF, 8'h87, 8'hC4, 8'h88, 8'hD7, 8'h89, 8'hE8, 8'h13, 8'hE0,
8'h00, 8'h00, 8'h10, 8'h00, 8'h0D, 8'h00, 8'h14, 8'h28, 8'hA5, 8'h05, 8'hAB, 8'h07, 8'h24, 8'h75,
8'h25, 8'h63, 8'h26, 8'hA5, 8'h9F, 8'h78, 8'hA0, 8'h68, 8'hA1, 8'h03, 8'hA6, 8'hDF, 8'hA7, 8'hDF,
8'hA8, 8'hF0, 8'hA9, 8'h90, 8'hAA, 8'h94, 8'h13, 8'hE5, 8'h0E, 8'h61, 8'h0F, 8'h4B, 8'h16, 8'h02,
8'h1E, 8'h27, 8'h21, 8'h02, 8'h22, 8'h91, 8'h29, 8'h07, 8'h33, 8'h0B, 8'h35, 8'h0B, 8'h37, 8'h1D,
8'h38, 8'h71, 8'h39, 8'h2A, 8'h3C, 8'h78, 8'h4D, 8'h40, 8'h4E, 8'h20, 8'h69, 8'h00, 8'h6B, 8'h40,
8'h74, 8'h19, 8'h8D, 8'h4F, 8'h8E, 8'h00, 8'h8F, 8'h00, 8'h90, 8'h00, 8'h91, 8'h00, 8'h92, 8'h00,
8'h96, 8'h00, 8'h9A, 8'h80, 8'hB0, 8'h84, 8'hB1, 8'h0C, 8'hB2, 8'h0E, 8'hB3, 8'h82, 8'hB8, 8'h0A,
8'h43, 8'h14, 8'h44, 8'hF0, 8'h45, 8'h34, 8'h46, 8'h58, 8'h47, 8'h28, 8'h48, 8'h3A, 8'h59, 8'h88,
8'h5A, 8'h88, 8'h5B, 8'h44, 8'h5C, 8'h67, 8'h5D, 8'h49, 8'h5E, 8'h0E, 8'h64, 8'h04, 8'h65, 8'h20,
8'h66, 8'h05, 8'h94, 8'h04, 8'h95, 8'h08, 8'h6C, 8'h0A, 8'h6D, 8'h55, 8'h4F, 8'h80, 8'h50, 8'h80,
8'h51, 8'h00, 8'h52, 8'h22, 8'h53, 8'h5E, 8'h54, 8'h80, 8'h09, 8'h03, 8'h6E, 8'h11, 8'h6F, 8'h9F,
8'h55, 8'h00, 8'h56, 8'h40, 8'h57, 8'h40, 8'h6A, 8'h40, 8'h01, 8'h40, 8'h02, 8'h40, 8'h13, 8'hE7,
8'h15, 8'h00, 8'h58, 8'h9E, 8'h41, 8'h08, 8'h3F, 8'h00, 8'h75, 8'h05, 8'h76, 8'hE1, 8'h4C, 8'h00,
8'h77, 8'h01, 8'h3D, 8'hC2, 8'h4B, 8'h09, 8'hC9, 8'h60, 8'h41, 8'h38, 8'h34, 8'h11, 8'h3B, 8'h02,
8'hA4, 8'h89, 8'h96, 8'h00, 8'h97, 8'h30, 8'h98, 8'h20, 8'h99, 8'h30, 8'h9A, 8'h84, 8'h9B, 8'h29,
8'h9C, 8'h03, 8'h9D, 8'h4C, 8'h9E, 8'h3F, 8'h78, 8'h04, 8'h79, 8'h01, 8'hC8, 8'hF0, 8'h79, 8'h0F,
8'hC8, 8'h00, 8'h79, 8'h10, 8'hC8, 8'h7E, 8'h79, 8'h0A, 8'hC8, 8'h80, 8'h79, 8'h0B, 8'hC8, 8'h01,
8'h79, 8'h0C, 8'hC8, 8'h0F, 8'h79, 8'h0D, 8'hC8, 8'h20, 8'h79, 8'h09, 8'hC8, 8'h80, 8'h79, 8'h02,
8'hC8, 8'hC0, 8'h79, 8'h03, 8'hC8, 8'h40, 8'h79, 8'h05, 8'hC8, 8'h30, 8'h79, 8'h26, 8'h09, 8'h00
};
localparam [8:0] cnt_50us = 9'd50_0;
localparam [9:0] cnt_100us = 10'd100_0;
localparam [14:0] cnt_2ms = 15'd2_000_0;
localparam [18:0] cnt_50ms = 19'd50_000_0;
reg[18:0] delay_cnt = cnt_50ms;
reg[2:0] bit_cnt = 1'd0;
reg[7:0] reg_data = 8'h00;
reg[8:0] idx = 1'd0;
reg[7:0] state = 8'h00;
always @(posedge clk_100kHz or negedge rst_n)
if (!rst_n) begin
scl <= 1'b1; sda_out <= 1'b1; sda_oe <= 1'b1;
initialized <= 1'b0;
delay_cnt <= 1'd0; state <= 8'h00;
end else if (delay_cnt) delay_cnt <= delay_cnt - 1'd1;
else if (!initialized)
case (state)
8'h00: begin sda_out <= 1'b1; state <= 8'h01; end
8'h01: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h02; end
8'h02: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h03; end
8'h03: begin scl <= 1'b0; state <= 8'h04; end
8'h04: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h05; end
8'h05: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h06; end
8'h06: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h07; end
8'h07: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h05 : 8'h08; end
8'h08: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h09; end
8'h09: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h0A; end
8'h0A: begin new_data <= 1'b1; data <= sda_in; state <= 8'h0B; end
8'h0B: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h0C; end
8'h0C: begin bit_cnt <= 3'd7; reg_data <= 8'h12; state <= 8'h0D; end
8'h0D: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h0E; end
8'h0E: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h0F; end
8'h0F: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h0D : 8'h10; end
8'h10: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h11; end
8'h11: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h12; end
8'h12: begin new_data <= 1'b1; data <= sda_in; state <= 8'h13; end
8'h13: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h14; end
8'h14: begin bit_cnt <= 3'd7; reg_data <= 8'h80; state <= 8'h15; end
8'h15: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h16; end
8'h16: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h17; end
8'h17: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h15 : 8'h18; end
8'h18: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h19; end
8'h19: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h1A; end
8'h1A: begin new_data <= 1'b1; data <= sda_in; state <= 8'h1B; end
8'h1B: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; state <= 8'h1C; end
8'h1C: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h1D; end
8'h1D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h1E; end
8'h1E: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h1F; end
8'h1F: begin delay_cnt <= cnt_50ms; state <= 8'h20; end
8'h20: begin sda_out <= 1'b1; state <= 8'h21; end
8'h21: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h22; end
8'h22: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h23; end
8'h23: begin scl <= 1'b0; state <= 8'h24; end
8'h24: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h25; end
8'h25: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h26; end
8'h26: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h27; end
8'h27: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h25 : 8'h28; end
8'h28: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h29; end
8'h29: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h2A; end
8'h2A: begin new_data <= 1'b1; data <= sda_in; state <= 8'h2B; end
8'h2B: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h2C; end
8'h2C: begin bit_cnt <= 3'd7; reg_data <= 8'h0B; state <= 8'h2D; end
8'h2D: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h2E; end
8'h2E: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h2F; end
8'h2F: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h2D : 8'h30; end
8'h30: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h31; end
8'h31: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h32; end
8'h32: begin new_data <= 1'b1; data <= sda_in; state <= 8'h33; end
8'h33: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h34; end
8'h34: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h35; end
8'h35: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h36; end
8'h36: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h37; end
8'h37: begin delay_cnt <= cnt_100us; state <= 8'h38; end
8'h38: begin sda_out <= 1'b1; state <= 8'h39; end
8'h39: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h3A; end
8'h3A: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h3B; end
8'h3B: begin scl <= 1'b0; state <= 8'h3C; end
8'h3C: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID | 1'b1; state <= 8'h3D; end
8'h3D: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h3E; end
8'h3E: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h3F; end
8'h3F: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h3D : 8'h40; end
8'h40: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h41; end
8'h41: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h42; end
8'h42: begin new_data <= 1'b1; data <= sda_in; state <= 8'h43; end
8'h43: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h44; end
8'h44: begin sda_oe <= 1'b0; bit_cnt <= 3'd7; delay_cnt <= cnt_50us; state <= 8'h45; end
8'h45: begin scl <= 1'b1; data[bit_cnt] <= sda_in; delay_cnt <= cnt_50us; state <= 8'h46; end
8'h46: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h47 : 8'h48; end
8'h47: begin delay_cnt <= cnt_50us; state <= 8'h45; end
8'h48: begin sda_oe <= 1'b1; state <= 8'h49; end
8'h49: begin new_data <= 1'b1; state <= 8'h4A; end
8'h4A: begin new_data <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h4B; end
8'h4B: begin sda_out <= 1'b1; state <= 8'h4C; end
8'h4C: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h4D; end
8'h4D: begin scl <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h4E; end
8'h4E: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h4F; end
8'h4F: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h51; end
8'h51: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h52; end
8'h52: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h53; end
8'h53: begin delay_cnt <= cnt_100us; state <= 8'h54; end
8'h54: begin sda_out <= 1'b1; state <= 8'h55; end
8'h55: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h56; end
8'h56: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h57; end
8'h57: begin scl <= 1'b0; state <= 8'h58; end
8'h58: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h59; end
8'h59: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h5A; end
8'h5A: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h5B; end
8'h5B: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h59 : 8'h5C; end
8'h5C: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h5D; end
8'h5D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h5E; end
8'h5E: begin new_data <= 1'b1; data <= sda_in; state <= 8'h5F; end
8'h5F: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h60; end
8'h60: begin bit_cnt <= 3'd7; reg_data <= 8'h0A; state <= 8'h61; end
8'h61: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h62; end
8'h62: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h63; end
8'h63: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h61 : 8'h64; end
8'h64: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h65; end
8'h65: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h66; end
8'h66: begin new_data <= 1'b1; data <= sda_in; state <= 8'h67; end
8'h67: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h68; end
8'h68: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h69; end
8'h69: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h6A; end
8'h6A: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h6B; end
8'h6B: begin delay_cnt <= cnt_100us; state <= 8'h6C; end
8'h6C: begin sda_out <= 1'b1; state <= 8'h6D; end
8'h6D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h6E; end
8'h6E: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h6F; end
8'h6F: begin scl <= 1'b0; state <= 8'h70; end
8'h70: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID | 1'b1; state <= 8'h71; end
8'h71: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h72; end
8'h72: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h73; end
8'h73: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h71 : 8'h74; end
8'h74: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h75; end
8'h75: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h76; end
8'h76: begin new_data <= 1'b1; data <= sda_in; state <= 8'h77; end
8'h77: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h78; end
8'h78: begin sda_oe <= 1'b0; bit_cnt <= 3'd7; delay_cnt <= cnt_50us; state <= 8'h79; end
8'h79: begin scl <= 1'b1; data[bit_cnt] <= sda_in; delay_cnt <= cnt_50us; state <= 8'h7A; end
8'h7A: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h7B : 8'h7C; end
8'h7B: begin delay_cnt <= cnt_50us; state <= 8'h79; end
8'h7C: begin sda_oe <= 1'b1; state <= 8'h7D; end
8'h7D: begin new_data <= 1'b1; state <= 8'h7E; end
8'h7E: begin new_data <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h7F; end
8'h7F: begin sda_out <= 1'b1; state <= 8'h80; end
8'h80: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h81; end
8'h81: begin scl <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h82; end
8'h82: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h83; end
8'h83: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h84; end
8'h84: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h85; end
8'h85: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h86; end
8'h86: begin delay_cnt <= cnt_100us; state <= 8'h87; end
8'h87: begin sda_out <= 1'b1; state <= 8'h88; end
8'h88: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h89; end
8'h89: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h8A; end
8'h8A: begin scl <= 1'b0; state <= 8'h8B; end
8'h8B: begin bit_cnt <= 3'd7; reg_data <= DEVICE_ID; state <= 8'h8C; end
8'h8C: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h8D; end
8'h8D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h8E; end
8'h8E: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h8C : 8'h8F; end
8'h8F: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h90; end
8'h90: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h91; end
8'h91: begin new_data <= 1'b1; data <= sda_in; state <= 8'h92; end
8'h92: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h93; end
8'h93: begin bit_cnt <= 3'd7; reg_data <= conf[idx]; idx <= idx + 1'd1; state <= 8'h94; end
8'h94: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h95; end
8'h95: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h96; end
8'h96: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h94 : 8'h97; end
8'h97: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'h98; end
8'h98: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h99; end
8'h99: begin new_data <= 1'b1; data <= sda_in; state <= 8'h9A; end
8'h9A: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; delay_cnt <= cnt_100us; state <= 8'h9B; end
8'h9B: begin bit_cnt <= 3'd7; reg_data <= conf[idx]; idx <= idx + 1'd1; state <= 8'h9C; end
8'h9C: begin sda_out <= reg_data[bit_cnt]; delay_cnt <= cnt_50us; state <= 8'h9D; end
8'h9D: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'h9E; end
8'h9E: begin scl <= 1'b0; bit_cnt <= bit_cnt - 1'd1; state <= bit_cnt ? 8'h9C : 8'h9F; end
8'h9F: begin sda_oe <= 1'b0; delay_cnt <= cnt_50us; state <= 8'hA0; end
8'hA0: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'hA1; end
8'hA1: begin new_data <= 1'b1; data <= sda_in; state <= 8'hA2; end
8'hA2: begin new_data <= 1'b0; scl <= 1'b0; sda_oe <= 1'b1; state <= 8'hA3; end
8'hA3: begin sda_out <= 1'b0; delay_cnt <= cnt_50us; state <= 8'hA4; end
8'hA4: begin scl <= 1'b1; delay_cnt <= cnt_50us; state <= 8'hA5; end
8'hA5: begin sda_out <= 1'b1; delay_cnt <= cnt_50us; state <= 8'hA6; end
8'hA6: begin delay_cnt <= cnt_2ms; state <= idx == conf_cnt ? 8'hA7 : 8'h87; end
8'hA7: begin new_data <= 1'b1; data <= 8'h0D; state <= 8'hA8; end
8'hA8: begin new_data <= 1'b0; delay_cnt <= cnt_50us; state <= 8'hA9; end
8'hA9: begin new_data <= 1'b1; data <= 8'h0A; state <= 8'hAA; end
8'hAA: begin new_data <= 1'b0; delay_cnt <= cnt_50ms; state <= 8'hAB; end
8'hAB: initialized <= 1'b1;
default: state <= 8'h00;
endcase
endmodule | 0 |
141,983 | data/full_repos/permissive/96654114/code/rtl/TOP/OV_READ.v | 96,654,114 | OV_READ.v | v | 58 | 80 | [] | [] | [] | null | line:8: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/OV_READ.v:16: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance OV_READ\n reg[8:0] delay_cnt = 1\'d0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/OV_READ.v:48: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'bytes_remaining\' generates 18 bits.\n : ... In instance OV_READ\n state <= bytes_remaining ? 4\'h7 : 4\'hA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/OV_READ.v:25: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'delay_cnt\' generates 9 bits.\n : ... In instance OV_READ\n end else if (delay_cnt) delay_cnt <= delay_cnt - 1\'d1;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,871 | module | module OV_READ (
input clk_24MHz,
input rst_n,
input initialized,
input [7:0] fifo_data,
output reg rclk = 1'b1,
output reg rrst = 1'b1,
input new_frame,
output reg frame_read = 1'b1,
output reg new_data = 1'b0,
output reg[7:0] data
);
localparam [8:0] cnt_15us = 9'd375;
reg[8:0] delay_cnt = 1'd0;
localparam [17:0] frame_bytes = 320 * 240 * 2;
reg[17:0] bytes_remaining = frame_bytes;
reg[3:0] state = 4'h0;
always @(posedge clk_24MHz or negedge rst_n)
if (!rst_n) begin
rclk <= 1'b1; rrst <= 1'b1;
frame_read = 1'b1;
state <= 4'h0;
end else if (delay_cnt) delay_cnt <= delay_cnt - 1'd1;
else if (initialized)
case (state)
4'h0: if (new_frame) begin
frame_read <= 1'b0;
bytes_remaining <= frame_bytes;
state <= 4'h1;
end
4'h1: begin rrst <= 1'b0; state <= 4'h2; end
4'h2: begin rclk <= 1'b0; state <= 4'h3; end
4'h3: begin rclk <= 1'b1; state <= 4'h4; end
4'h4: begin rclk <= 1'b0; state <= 4'h5; end
4'h5: begin rrst <= 1'b1; state <= 4'h6; end
4'h6: begin rclk <= 1'b1; state <= 4'h7; end
4'h7: begin rclk <= 1'b0; state <= 4'h8; end
4'h8: begin
new_data <= 1'b1; data <= fifo_data;
bytes_remaining <= bytes_remaining - 1'd1;
state <= 4'h9;
end
4'h9: begin
rclk <= 1'b1; new_data <= 1'b0;
delay_cnt <= cnt_15us;
state <= bytes_remaining ? 4'h7 : 4'hA;
end
4'hA: begin new_data <= 1'b1; data <= 8'h0D; state <= 4'hB; end
4'hB: begin new_data <= 1'b0; delay_cnt <= cnt_15us; state <= 4'hC; end
4'hC: begin new_data <= 1'b1; data <= 8'h0A; state <= 4'hD; end
4'hD: begin new_data <= 1'b0; delay_cnt <= cnt_15us; state <= 4'hE; end
4'hE: begin frame_read <= 1'b1; state <= 4'h0; end
default: state <= 4'h0;
endcase
endmodule | module OV_READ (
input clk_24MHz,
input rst_n,
input initialized,
input [7:0] fifo_data,
output reg rclk = 1'b1,
output reg rrst = 1'b1,
input new_frame,
output reg frame_read = 1'b1,
output reg new_data = 1'b0,
output reg[7:0] data
); |
localparam [8:0] cnt_15us = 9'd375;
reg[8:0] delay_cnt = 1'd0;
localparam [17:0] frame_bytes = 320 * 240 * 2;
reg[17:0] bytes_remaining = frame_bytes;
reg[3:0] state = 4'h0;
always @(posedge clk_24MHz or negedge rst_n)
if (!rst_n) begin
rclk <= 1'b1; rrst <= 1'b1;
frame_read = 1'b1;
state <= 4'h0;
end else if (delay_cnt) delay_cnt <= delay_cnt - 1'd1;
else if (initialized)
case (state)
4'h0: if (new_frame) begin
frame_read <= 1'b0;
bytes_remaining <= frame_bytes;
state <= 4'h1;
end
4'h1: begin rrst <= 1'b0; state <= 4'h2; end
4'h2: begin rclk <= 1'b0; state <= 4'h3; end
4'h3: begin rclk <= 1'b1; state <= 4'h4; end
4'h4: begin rclk <= 1'b0; state <= 4'h5; end
4'h5: begin rrst <= 1'b1; state <= 4'h6; end
4'h6: begin rclk <= 1'b1; state <= 4'h7; end
4'h7: begin rclk <= 1'b0; state <= 4'h8; end
4'h8: begin
new_data <= 1'b1; data <= fifo_data;
bytes_remaining <= bytes_remaining - 1'd1;
state <= 4'h9;
end
4'h9: begin
rclk <= 1'b1; new_data <= 1'b0;
delay_cnt <= cnt_15us;
state <= bytes_remaining ? 4'h7 : 4'hA;
end
4'hA: begin new_data <= 1'b1; data <= 8'h0D; state <= 4'hB; end
4'hB: begin new_data <= 1'b0; delay_cnt <= cnt_15us; state <= 4'hC; end
4'hC: begin new_data <= 1'b1; data <= 8'h0A; state <= 4'hD; end
4'hD: begin new_data <= 1'b0; delay_cnt <= cnt_15us; state <= 4'hE; end
4'hE: begin frame_read <= 1'b1; state <= 4'h0; end
default: state <= 4'h0;
endcase
endmodule | 0 |
141,984 | data/full_repos/permissive/96654114/code/rtl/TOP/OV_STORE.v | 96,654,114 | OV_STORE.v | v | 36 | 99 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/OV_STORE.v:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance OV_STORE\n reg[3:0] frame_cnt = 1\'d0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/OV_STORE.v:19: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance OV_STORE\n frame_cnt <= 1\'d0;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 312,872 | module | module OV_STORE (
input clk_24MHz,
input rst_n,
input initialized,
output reg wen = 1'b0,
output reg wrst = 1'b1,
input vsync,
output reg new_frame = 1'b0,
input frame_read
);
reg[3:0] frame_cnt = 1'd0;
reg[2:0] state = 3'd0;
always @(posedge clk_24MHz or negedge rst_n)
if (!rst_n) begin
wen <= 1'b0; wrst <= 1'b1;
new_frame <= 1'b0;
frame_cnt <= 1'd0;
state <= 3'd0;
end else if (initialized)
case (state)
3'd0: if (!vsync) state <= 3'd1;
3'd1: if (vsync) begin wrst <= 1'b0; state <= 3'd2; end
3'd2: begin wrst <= 1'b1; state <= 3'd3; end
3'd3: begin wen <= 1'b1; state <= 3'd4; end
3'd4: if (!vsync) state <= 3'd5;
3'd5: if (vsync) begin
wen <= 1'b0;
new_frame <= 1'b1; state <= 3'd6;
end
3'd6: if (!frame_read) state <= 3'd7;
3'd7: if (frame_read) begin new_frame <= 1'b0; state <= 3'd0; end
endcase
endmodule | module OV_STORE (
input clk_24MHz,
input rst_n,
input initialized,
output reg wen = 1'b0,
output reg wrst = 1'b1,
input vsync,
output reg new_frame = 1'b0,
input frame_read
); |
reg[3:0] frame_cnt = 1'd0;
reg[2:0] state = 3'd0;
always @(posedge clk_24MHz or negedge rst_n)
if (!rst_n) begin
wen <= 1'b0; wrst <= 1'b1;
new_frame <= 1'b0;
frame_cnt <= 1'd0;
state <= 3'd0;
end else if (initialized)
case (state)
3'd0: if (!vsync) state <= 3'd1;
3'd1: if (vsync) begin wrst <= 1'b0; state <= 3'd2; end
3'd2: begin wrst <= 1'b1; state <= 3'd3; end
3'd3: begin wen <= 1'b1; state <= 3'd4; end
3'd4: if (!vsync) state <= 3'd5;
3'd5: if (vsync) begin
wen <= 1'b0;
new_frame <= 1'b1; state <= 3'd6;
end
3'd6: if (!frame_read) state <= 3'd7;
3'd7: if (frame_read) begin new_frame <= 1'b0; state <= 3'd0; end
endcase
endmodule | 0 |
141,985 | data/full_repos/permissive/96654114/code/rtl/TOP/SERVO.v | 96,654,114 | SERVO.v | v | 18 | 50 | [] | [] | [] | [(3, 17)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/SERVO.v:15: Operator LT expects 11 bits on the RHS, but RHS\'s VARREF \'angle\' generates 8 bits.\n : ... In instance SERVO\n pwm <= clk_cnt < angle;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/SERVO.v:13: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'clk_cnt\' generates 11 bits.\n : ... In instance SERVO\n else if (clk_cnt) begin\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 312,873 | module | module SERVO (
input clk_100kHz,
input rst_n,
input [7:0] angle,
output reg pwm
);
localparam [10:0] max_cnt = 11'd2000;
reg[10:0] clk_cnt = max_cnt;
always @(posedge clk_100kHz or negedge rst_n)
if (!rst_n) clk_cnt <= max_cnt;
else if (clk_cnt) begin
clk_cnt <= clk_cnt - 1'd1;
pwm <= clk_cnt < angle;
end else clk_cnt <= max_cnt;
endmodule | module SERVO (
input clk_100kHz,
input rst_n,
input [7:0] angle,
output reg pwm
); |
localparam [10:0] max_cnt = 11'd2000;
reg[10:0] clk_cnt = max_cnt;
always @(posedge clk_100kHz or negedge rst_n)
if (!rst_n) clk_cnt <= max_cnt;
else if (clk_cnt) begin
clk_cnt <= clk_cnt - 1'd1;
pwm <= clk_cnt < angle;
end else clk_cnt <= max_cnt;
endmodule | 0 |
141,986 | data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v | 96,654,114 | TOP.v | v | 163 | 123 | [] | [] | [] | [(3, 162)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:23: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] Y\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:32: Cannot find file containing module: \'CLK_GEN\'\n CLK_GEN #(SYS_CLK_FREQ, BAUD_RATE) clk_gen_uart(sys_clk, rst_n, clk_uart);\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/96654114/code/rtl/TOP,data/full_repos/permissive/96654114/CLK_GEN\n data/full_repos/permissive/96654114/code/rtl/TOP,data/full_repos/permissive/96654114/CLK_GEN.v\n data/full_repos/permissive/96654114/code/rtl/TOP,data/full_repos/permissive/96654114/CLK_GEN.sv\n CLK_GEN\n CLK_GEN.v\n CLK_GEN.sv\n obj_dir/CLK_GEN\n obj_dir/CLK_GEN.v\n obj_dir/CLK_GEN.sv\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:33: Cannot find file containing module: \'CLK_GEN\'\n CLK_GEN #(SYS_CLK_FREQ, 100_000) clk_gen_100kHz(sys_clk, rst_n, clk_100kHz);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:34: Cannot find file containing module: \'CLK_GEN\'\n CLK_GEN #(SYS_CLK_FREQ, 1_000_000) clk_gen_1MHz(sys_clk, rst_n, clk_1MHz);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:35: Cannot find file containing module: \'CLK_GEN\'\n CLK_GEN #(SYS_CLK_FREQ, 24_000_000) clk_gen_24MHz(sys_clk, rst_n, clk_24MHz);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:36: Cannot find file containing module: \'CLK_GEN\'\n CLK_GEN #(SYS_CLK_FREQ, 250) clk_gen_250Hz(sys_clk, rst_n, clk_250Hz);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:37: Cannot find file containing module: \'CLK_GEN\'\n CLK_GEN #(SYS_CLK_FREQ, 2) clk_gen_2Hz(sys_clk, rst_n, clk_2Hz);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:46: Cannot find file containing module: \'SERVO\'\n SERVO servo(clk_100kHz, rst_n, angle, servo_pwm);\n ^~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:52: Cannot find file containing module: \'MOTOR\'\n MOTOR motor(clk_1MHz, rst_n, direction, motor_en, motor_pwm);\n ^~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:58: Cannot find file containing module: \'ULTRASONIC\'\n ULTRASONIC ultrasonic(clk_1MHz, rst_n, trig, echo, distance);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:66: Cannot find file containing module: \'UART_RX\'\n UART_RX rx(clk_uart, rst_n, rx_pin, rx_error, rx_finish, rx_data);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:71: Cannot find file containing module: \'UART_TX\'\n UART_TX tx(clk_uart, rst_n, tx_pin, tx_start, tx_finish, tx_data);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:81: Cannot find file containing module: \'OV_INIT\'\n OV_INIT #(DEVICE_ID) init(clk_100kHz, rst_n, scl, sda, initialized, new_init_data, init_data);\n ^~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:87: Cannot find file containing module: \'OV_STORE\'\n OV_STORE ov_s(clk_24MHz, rst_n, initialized, wen, wrst, vsync, new_frame, frame_read);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:88: Cannot find file containing module: \'OV_READ\'\n OV_READ ov_r(clk_24MHz, rst_n, initialized, fifo_data, rclk, rrst, new_frame, frame_read, new_frame_data, frame_data);\n ^~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:93: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg[0:2] rx_finish_reg = {3{1\'b0}};\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:118: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg[0:2] new_init_data_reg = {3{1\'b0}};\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:119: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg[0:2] new_frame_data_reg = {3{1\'b0}};\n ^\n%Error: data/full_repos/permissive/96654114/code/rtl/TOP/TOP.v:151: Cannot find file containing module: \'DISPLAY\'\n DISPLAY display(clk_250Hz, rst_n, display_data, AN, Y);\n ^~~~~~~\n%Error: Exiting due to 15 error(s), 4 warning(s)\n' | 312,874 | module | module TOP (
input sys_clk,
input rst_n,
output servo_pwm,
output [1:0] motor_en,
output motor_pwm,
output trig,
input echo,
input rx_pin,
output tx_pin,
output scl,
inout sda,
output wen,
output wrst,
input vsync,
input [7:0] fifo_data,
output rclk,
output rrst,
output [15:0] led,
output [3:0] AN,
output [0:7] Y
);
parameter SYS_CLK_FREQ = 100_000_000;
parameter BAUD_RATE = 921600;
wire clk_uart, clk_100kHz, clk_1MHz, clk_24MHz, clk_250Hz, clk_2Hz;
CLK_GEN #(SYS_CLK_FREQ, BAUD_RATE) clk_gen_uart(sys_clk, rst_n, clk_uart);
CLK_GEN #(SYS_CLK_FREQ, 100_000) clk_gen_100kHz(sys_clk, rst_n, clk_100kHz);
CLK_GEN #(SYS_CLK_FREQ, 1_000_000) clk_gen_1MHz(sys_clk, rst_n, clk_1MHz);
CLK_GEN #(SYS_CLK_FREQ, 24_000_000) clk_gen_24MHz(sys_clk, rst_n, clk_24MHz);
CLK_GEN #(SYS_CLK_FREQ, 250) clk_gen_250Hz(sys_clk, rst_n, clk_250Hz);
CLK_GEN #(SYS_CLK_FREQ, 2) clk_gen_2Hz(sys_clk, rst_n, clk_2Hz);
localparam [7:0] min_angle = 8'd150;
localparam [7:0] max_angle = 8'd250;
localparam [7:0] default_angle = 8'd200;
reg[7:0] angle = default_angle;
SERVO servo(clk_100kHz, rst_n, angle, servo_pwm);
reg[1:0] direction = 2'b01;
MOTOR motor(clk_1MHz, rst_n, direction, motor_en, motor_pwm);
reg[11:0] distance = 12'd0;
ULTRASONIC ultrasonic(clk_1MHz, rst_n, trig, echo, distance);
wire rx_error;
wire rx_finish;
wire[7:0] rx_data;
UART_RX rx(clk_uart, rst_n, rx_pin, rx_error, rx_finish, rx_data);
reg tx_start = 1'b0;
wire tx_finish;
reg[7:0] tx_data = 8'h00;
UART_TX tx(clk_uart, rst_n, tx_pin, tx_start, tx_finish, tx_data);
parameter [7:0] DEVICE_ID = 8'h42;
wire initialized;
wire new_init_data;
wire[7:0] init_data;
OV_INIT #(DEVICE_ID) init(clk_100kHz, rst_n, scl, sda, initialized, new_init_data, init_data);
wire new_frame;
wire frame_read;
wire new_frame_data;
wire[7:0] frame_data;
OV_STORE ov_s(clk_24MHz, rst_n, initialized, wen, wrst, vsync, new_frame, frame_read);
OV_READ ov_r(clk_24MHz, rst_n, initialized, fifo_data, rclk, rrst, new_frame, frame_read, new_frame_data, frame_data);
reg[0:2] rx_finish_reg = {3{1'b0}};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) rx_finish_reg <= {3{1'b0}};
else rx_finish_reg <= {rx_finish, rx_finish_reg[0:1]};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) angle <= default_angle;
else if (rx_finish_reg[1] & ~rx_finish_reg[2])
if ((rx_data & 8'h03) == 8'h00) begin
case (rx_data[7:5])
3'b011: direction <= 2'b11;
3'b110: direction <= 2'b00;
default: direction <= 2'b01;
endcase
case (rx_data[4:2])
3'b011: if (angle < max_angle) angle <= angle + 1'd1;
3'b110: if (angle > min_angle) angle <= angle - 1'd1;
3'b101: angle <= default_angle;
default: ;
endcase
end
reg[0:2] new_init_data_reg = {3{1'b0}};
reg[0:2] new_frame_data_reg = {3{1'b0}};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) begin new_init_data_reg = {3{1'b0}}; new_frame_data_reg = {3{1'b0}}; end
else if (!initialized) new_init_data_reg = {new_init_data, new_init_data_reg[0:1]};
else new_frame_data_reg = {new_frame_data, new_frame_data_reg[0:1]};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) tx_start <= 1'b0;
else if (tx_start) begin if (!tx_finish) tx_start <= 1'b0; end
else if (!initialized) begin tx_start <= new_init_data_reg[1] & ~new_init_data_reg[2]; tx_data <= init_data; end
else begin tx_start <= new_frame_data_reg[1] & ~new_frame_data_reg[2]; tx_data <= frame_data; end
assign led[0] = initialized;
assign led[15:6] = {
distance < 12'd1000,
distance < 12'd900,
distance < 12'd800,
distance < 12'd700,
distance < 12'd600,
distance < 12'd500,
distance < 12'd400,
distance < 12'd300,
distance < 12'd200,
distance < 12'd100
};
reg[31:0] display_data;
DISPLAY display(clk_250Hz, rst_n, display_data, AN, Y);
always @(posedge clk_2Hz or negedge rst_n)
if (!rst_n) display_data <= 32'hFFFFFFFF;
else case (display_data)
32'h9161E3E3: display_data <= 32'h61E3E303;
32'h61E3E303: display_data <= 32'hE3E303FF;
32'hE3E303FF: display_data <= 32'hE303FF91;
32'hE303FF91: display_data <= 32'h03FF9161;
32'h03FF9161: display_data <= 32'hFF9161E3;
default: display_data <= 32'h9161E3E3;
endcase
endmodule | module TOP (
input sys_clk,
input rst_n,
output servo_pwm,
output [1:0] motor_en,
output motor_pwm,
output trig,
input echo,
input rx_pin,
output tx_pin,
output scl,
inout sda,
output wen,
output wrst,
input vsync,
input [7:0] fifo_data,
output rclk,
output rrst,
output [15:0] led,
output [3:0] AN,
output [0:7] Y
); |
parameter SYS_CLK_FREQ = 100_000_000;
parameter BAUD_RATE = 921600;
wire clk_uart, clk_100kHz, clk_1MHz, clk_24MHz, clk_250Hz, clk_2Hz;
CLK_GEN #(SYS_CLK_FREQ, BAUD_RATE) clk_gen_uart(sys_clk, rst_n, clk_uart);
CLK_GEN #(SYS_CLK_FREQ, 100_000) clk_gen_100kHz(sys_clk, rst_n, clk_100kHz);
CLK_GEN #(SYS_CLK_FREQ, 1_000_000) clk_gen_1MHz(sys_clk, rst_n, clk_1MHz);
CLK_GEN #(SYS_CLK_FREQ, 24_000_000) clk_gen_24MHz(sys_clk, rst_n, clk_24MHz);
CLK_GEN #(SYS_CLK_FREQ, 250) clk_gen_250Hz(sys_clk, rst_n, clk_250Hz);
CLK_GEN #(SYS_CLK_FREQ, 2) clk_gen_2Hz(sys_clk, rst_n, clk_2Hz);
localparam [7:0] min_angle = 8'd150;
localparam [7:0] max_angle = 8'd250;
localparam [7:0] default_angle = 8'd200;
reg[7:0] angle = default_angle;
SERVO servo(clk_100kHz, rst_n, angle, servo_pwm);
reg[1:0] direction = 2'b01;
MOTOR motor(clk_1MHz, rst_n, direction, motor_en, motor_pwm);
reg[11:0] distance = 12'd0;
ULTRASONIC ultrasonic(clk_1MHz, rst_n, trig, echo, distance);
wire rx_error;
wire rx_finish;
wire[7:0] rx_data;
UART_RX rx(clk_uart, rst_n, rx_pin, rx_error, rx_finish, rx_data);
reg tx_start = 1'b0;
wire tx_finish;
reg[7:0] tx_data = 8'h00;
UART_TX tx(clk_uart, rst_n, tx_pin, tx_start, tx_finish, tx_data);
parameter [7:0] DEVICE_ID = 8'h42;
wire initialized;
wire new_init_data;
wire[7:0] init_data;
OV_INIT #(DEVICE_ID) init(clk_100kHz, rst_n, scl, sda, initialized, new_init_data, init_data);
wire new_frame;
wire frame_read;
wire new_frame_data;
wire[7:0] frame_data;
OV_STORE ov_s(clk_24MHz, rst_n, initialized, wen, wrst, vsync, new_frame, frame_read);
OV_READ ov_r(clk_24MHz, rst_n, initialized, fifo_data, rclk, rrst, new_frame, frame_read, new_frame_data, frame_data);
reg[0:2] rx_finish_reg = {3{1'b0}};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) rx_finish_reg <= {3{1'b0}};
else rx_finish_reg <= {rx_finish, rx_finish_reg[0:1]};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) angle <= default_angle;
else if (rx_finish_reg[1] & ~rx_finish_reg[2])
if ((rx_data & 8'h03) == 8'h00) begin
case (rx_data[7:5])
3'b011: direction <= 2'b11;
3'b110: direction <= 2'b00;
default: direction <= 2'b01;
endcase
case (rx_data[4:2])
3'b011: if (angle < max_angle) angle <= angle + 1'd1;
3'b110: if (angle > min_angle) angle <= angle - 1'd1;
3'b101: angle <= default_angle;
default: ;
endcase
end
reg[0:2] new_init_data_reg = {3{1'b0}};
reg[0:2] new_frame_data_reg = {3{1'b0}};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) begin new_init_data_reg = {3{1'b0}}; new_frame_data_reg = {3{1'b0}}; end
else if (!initialized) new_init_data_reg = {new_init_data, new_init_data_reg[0:1]};
else new_frame_data_reg = {new_frame_data, new_frame_data_reg[0:1]};
always @(posedge sys_clk or negedge rst_n)
if (!rst_n) tx_start <= 1'b0;
else if (tx_start) begin if (!tx_finish) tx_start <= 1'b0; end
else if (!initialized) begin tx_start <= new_init_data_reg[1] & ~new_init_data_reg[2]; tx_data <= init_data; end
else begin tx_start <= new_frame_data_reg[1] & ~new_frame_data_reg[2]; tx_data <= frame_data; end
assign led[0] = initialized;
assign led[15:6] = {
distance < 12'd1000,
distance < 12'd900,
distance < 12'd800,
distance < 12'd700,
distance < 12'd600,
distance < 12'd500,
distance < 12'd400,
distance < 12'd300,
distance < 12'd200,
distance < 12'd100
};
reg[31:0] display_data;
DISPLAY display(clk_250Hz, rst_n, display_data, AN, Y);
always @(posedge clk_2Hz or negedge rst_n)
if (!rst_n) display_data <= 32'hFFFFFFFF;
else case (display_data)
32'h9161E3E3: display_data <= 32'h61E3E303;
32'h61E3E303: display_data <= 32'hE3E303FF;
32'hE3E303FF: display_data <= 32'hE303FF91;
32'hE303FF91: display_data <= 32'h03FF9161;
32'h03FF9161: display_data <= 32'hFF9161E3;
default: display_data <= 32'h9161E3E3;
endcase
endmodule | 0 |
141,987 | data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v | 96,654,114 | UART_TX.v | v | 44 | 68 | [] | [] | [] | [(3, 43)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v:12: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 1 bits.\n : ... In instance UART_TX\n reg[1:0] state = IDLE;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v:19: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 1 bits.\n : ... In instance UART_TX\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v:29: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUSY\' generates 1 bits.\n : ... In instance UART_TX\n state <= BUSY;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v:38: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 1 bits.\n : ... In instance UART_TX\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v:35: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance UART_TX\n if (bits_remaining == 1\'d1) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v:22: Operator CASE expects 2 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 1 bits.\n : ... In instance UART_TX\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/UART_TX.v:22: Operator CASE expects 2 bits on the Case Item, but Case Item\'s VARREF \'BUSY\' generates 1 bits.\n : ... In instance UART_TX\n case (state)\n ^~~~\n%Error: Exiting due to 7 warning(s)\n' | 312,876 | module | module UART_TX (
input clk,
input rst_n,
output reg pin,
input start,
output reg finish,
input [7:0] data
);
localparam IDLE = 1'b0, BUSY = 1'b1;
reg[1:0] state = IDLE;
reg[3:0] bits_remaining = 4'd0;
reg[7:0] data_reg;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
pin <= 1'b1;
finish <= 1'b0;
state <= IDLE;
bits_remaining <= 4'd0;
end else
case (state)
IDLE: begin
pin <= 1'b1;
finish <= 1'b1;
if (start) begin
pin <= 1'b0;
finish <= 1'b0;
state <= BUSY;
bits_remaining <= 4'd9;
data_reg <= data;
end
end
BUSY: begin
if (bits_remaining == 1'd1) begin
pin <= 1'b1;
finish <= 1'b1;
state <= IDLE;
end else {data_reg, pin} <= {1'b0, data_reg};
bits_remaining <= bits_remaining - 1'd1;
end
endcase
endmodule | module UART_TX (
input clk,
input rst_n,
output reg pin,
input start,
output reg finish,
input [7:0] data
); |
localparam IDLE = 1'b0, BUSY = 1'b1;
reg[1:0] state = IDLE;
reg[3:0] bits_remaining = 4'd0;
reg[7:0] data_reg;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
pin <= 1'b1;
finish <= 1'b0;
state <= IDLE;
bits_remaining <= 4'd0;
end else
case (state)
IDLE: begin
pin <= 1'b1;
finish <= 1'b1;
if (start) begin
pin <= 1'b0;
finish <= 1'b0;
state <= BUSY;
bits_remaining <= 4'd9;
data_reg <= data;
end
end
BUSY: begin
if (bits_remaining == 1'd1) begin
pin <= 1'b1;
finish <= 1'b1;
state <= IDLE;
end else {data_reg, pin} <= {1'b0, data_reg};
bits_remaining <= bits_remaining - 1'd1;
end
endcase
endmodule | 0 |
141,988 | data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v | 96,654,114 | ULTRASONIC.v | v | 33 | 76 | [] | [] | [] | [(3, 32)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v:13: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance ULTRASONIC\n reg[16:0] delay_cnt = 1\'d0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v:14: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance ULTRASONIC\n reg[13:0] dist_cnt = 1\'d0;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v:20: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt_50us\' generates 6 bits.\n : ... In instance ULTRASONIC\n 3\'d0: begin trig <= 1\'b1; delay_cnt <= cnt_50us; state <= 3\'d1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v:22: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance ULTRASONIC\n 3\'d2: if (echo) begin dist_cnt <= 1\'d1; state <= 3\'d3; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v:26: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'dist_cnt\' generates 14 bits.\n : ... In instance ULTRASONIC\n if (!dist_cnt) state <= 3\'d4; \n ^\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v:28: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance ULTRASONIC\n 3\'d4: begin distance <= dist_cnt * 170 / 1000; state <= 3\'d5; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96654114/code/rtl/TOP/ULTRASONIC.v:18: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'delay_cnt\' generates 17 bits.\n : ... In instance ULTRASONIC\n else if (delay_cnt) delay_cnt <= delay_cnt - 1\'d1;\n ^~\n%Error: Exiting due to 7 warning(s)\n' | 312,877 | module | module ULTRASONIC (
input clk_1MHz,
input rst_n,
output reg trig,
input echo,
output reg[11:0] distance
);
pulldown(echo);
localparam [5:0] cnt_50us = 6'd50;
localparam [16:0] cnt_100ms = 17'd100_000;
reg[16:0] delay_cnt = 1'd0;
reg[13:0] dist_cnt = 1'd0;
reg[2:0] state = 3'd0;
always @(posedge clk_1MHz or negedge rst_n)
if (!rst_n) begin trig <= 1'b0; state <= 3'd0; end
else if (delay_cnt) delay_cnt <= delay_cnt - 1'd1;
else case (state)
3'd0: begin trig <= 1'b1; delay_cnt <= cnt_50us; state <= 3'd1; end
3'd1: begin trig <= 1'b0; state <= 3'd2; end
3'd2: if (echo) begin dist_cnt <= 1'd1; state <= 3'd3; end
3'd3: begin
dist_cnt <= dist_cnt + 1'd1;
if (!echo) state <= 3'd4;
if (!dist_cnt) state <= 3'd4;
end
3'd4: begin distance <= dist_cnt * 170 / 1000; state <= 3'd5; end
3'd5: begin delay_cnt <= cnt_100ms; state <= 3'd0; end
default: state <= 3'd0;
endcase
endmodule | module ULTRASONIC (
input clk_1MHz,
input rst_n,
output reg trig,
input echo,
output reg[11:0] distance
); |
pulldown(echo);
localparam [5:0] cnt_50us = 6'd50;
localparam [16:0] cnt_100ms = 17'd100_000;
reg[16:0] delay_cnt = 1'd0;
reg[13:0] dist_cnt = 1'd0;
reg[2:0] state = 3'd0;
always @(posedge clk_1MHz or negedge rst_n)
if (!rst_n) begin trig <= 1'b0; state <= 3'd0; end
else if (delay_cnt) delay_cnt <= delay_cnt - 1'd1;
else case (state)
3'd0: begin trig <= 1'b1; delay_cnt <= cnt_50us; state <= 3'd1; end
3'd1: begin trig <= 1'b0; state <= 3'd2; end
3'd2: if (echo) begin dist_cnt <= 1'd1; state <= 3'd3; end
3'd3: begin
dist_cnt <= dist_cnt + 1'd1;
if (!echo) state <= 3'd4;
if (!dist_cnt) state <= 3'd4;
end
3'd4: begin distance <= dist_cnt * 170 / 1000; state <= 3'd5; end
3'd5: begin delay_cnt <= cnt_100ms; state <= 3'd0; end
default: state <= 3'd0;
endcase
endmodule | 0 |
141,989 | data/full_repos/permissive/96664564/malproxy/malproxy.v | 96,664,564 | malproxy.v | v | 177 | 129 | [] | [] | [] | [(11, 176)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:92: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:101: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:108: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance malproxy_ahb_lite\n RTKCmd<=HWDATA[7:0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:109: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:112: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n else RTKState<=5\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:120: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h3\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:134: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h4\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h4;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:150: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h5\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h5;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:156: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:144: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h57\' generates 8 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKCmd) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:144: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h52\' generates 8 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKCmd) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:163: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h6\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h6;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:170: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n RTKState<=5\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:96: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKState)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:96: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKState)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:96: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h2\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKState)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:96: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h3\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKState)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:96: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h4\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKState)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:96: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h5\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKState)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/malproxy/malproxy.v:96: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h6\' generates 5 bits.\n : ... In instance malproxy_ahb_lite\n case (RTKState)\n ^~~~\n%Error: Exiting due to 20 warning(s)\n' | 312,896 | module | module malproxy_ahb_lite (
input wire HCLK,
input wire HRESETn ,
output wire [31:0] HADDR,
output wire HWRITE,
output wire [31:0] HWDATA,
output wire [2:0] HSIZE,
output wire [3:0] HPROT,
output wire [1:0] HTRANS,
output wire dHCLK,
input wire [31:0] dHADDR,
input wire [31:0] dHWDATA,
input wire [2:0] dHSIZE,
input wire [ 3:0] dHPROT,
input wire dHWRITE,
input wire [1:0] dHTRANS
);
reg RTKDeviated;
assign dHCLK=(RTKDeviated==0)?HCLK:1'h1;
reg [31:0] RTKAddr;
assign HADDR=(RTKDeviated==0)?dHADDR:RTKAddr;
reg [31:0] RTKData;
assign HWDATA=(RTKDeviated==0)?dHWDATA:RTKData;
assign HSIZE=(RTKDeviated==0)?dHSIZE:3'h2;
assign HPROT=(RTKDeviated==0)?dHPROT:4'h0;
reg RTKHWRITE;
assign HWRITE=(RTKDeviated==0)?dHWRITE:RTKHWRITE;
reg [1:0] RTKHTRANS;
assign HTRANS=(RTKDeviated==0)?dHTRANS:RTKHTRANS;
reg [5:0] RTKState;
reg [8:0] RTKCmd;
reg [3:0] RTKCount;
`define RTK_FIND_START 5'h0
`define RTK_FIND_CMD 5'h1
`define RTK_FIND_DATA 5'h2
`define RTK_FIND_ADDR 5'h3
`define RTK_EXEC 5'h4
`define RTK_EXEC2 5'h5
`define RTK_END 5'h6
`define RTK_CMD_WRITE "W"
`define RTK_CMD_READ "R"
`define RTK_COOKIE_1 32'h12345678
`define RTK_COOKIE_2 24'h434241
`define RTK_COOKIE_3 24'h2D2D2D
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
begin
RTKState<=`RTK_FIND_START;
RTKDeviated<=0;
end
else begin
case (RTKState)
`RTK_FIND_START:
if ( HWDATA ==`RTK_COOKIE_1)
begin
RTKState<=`RTK_FIND_CMD;
end
`RTK_FIND_CMD:
begin
if ( HWDATA[31:8] ==`RTK_COOKIE_2)
begin
RTKCmd<=HWDATA[7:0];
RTKState<=`RTK_FIND_DATA;
RTKCount<=0;
end
else RTKState<=`RTK_FIND_START;
end
`RTK_FIND_DATA:
begin
if ( HWDATA[31:8] ==`RTK_COOKIE_3)
begin
if (RTKCount==3)
begin
RTKState<=`RTK_FIND_ADDR;
RTKCount<=0;
end
else RTKCount<=RTKCount+4'h1;
RTKData[31:8]<=RTKData[23:0];
RTKData[7:0]<=HWDATA[7:0];
end
end
`RTK_FIND_ADDR:
begin
if ( HWDATA[31:8] ==`RTK_COOKIE_3)
begin
if (RTKCount==3)
begin
RTKState<=`RTK_EXEC;
RTKDeviated<=1;
end
else RTKCount<=RTKCount+4'h1;
RTKAddr[31:8]<=RTKAddr[23:0];
RTKAddr[7:0]<=HWDATA[7:0];
end
end
`RTK_EXEC:
begin
case (RTKCmd)
`RTK_CMD_WRITE:
begin
RTKHWRITE<=1;
RTKHTRANS<=2;
RTKState<=`RTK_EXEC2;
end
`RTK_CMD_READ:
begin
RTKState<=`RTK_FIND_START;
end
endcase
end
`RTK_EXEC2:
begin
RTKHWRITE<=0;
RTKState<=`RTK_END;
end
`RTK_END:
begin
$display("END");
RTKDeviated<=0;
RTKHWRITE<=0;
RTKState<=`RTK_FIND_START;
end
endcase
end
end
endmodule | module malproxy_ahb_lite (
input wire HCLK,
input wire HRESETn ,
output wire [31:0] HADDR,
output wire HWRITE,
output wire [31:0] HWDATA,
output wire [2:0] HSIZE,
output wire [3:0] HPROT,
output wire [1:0] HTRANS,
output wire dHCLK,
input wire [31:0] dHADDR,
input wire [31:0] dHWDATA,
input wire [2:0] dHSIZE,
input wire [ 3:0] dHPROT,
input wire dHWRITE,
input wire [1:0] dHTRANS
); |
reg RTKDeviated;
assign dHCLK=(RTKDeviated==0)?HCLK:1'h1;
reg [31:0] RTKAddr;
assign HADDR=(RTKDeviated==0)?dHADDR:RTKAddr;
reg [31:0] RTKData;
assign HWDATA=(RTKDeviated==0)?dHWDATA:RTKData;
assign HSIZE=(RTKDeviated==0)?dHSIZE:3'h2;
assign HPROT=(RTKDeviated==0)?dHPROT:4'h0;
reg RTKHWRITE;
assign HWRITE=(RTKDeviated==0)?dHWRITE:RTKHWRITE;
reg [1:0] RTKHTRANS;
assign HTRANS=(RTKDeviated==0)?dHTRANS:RTKHTRANS;
reg [5:0] RTKState;
reg [8:0] RTKCmd;
reg [3:0] RTKCount;
`define RTK_FIND_START 5'h0
`define RTK_FIND_CMD 5'h1
`define RTK_FIND_DATA 5'h2
`define RTK_FIND_ADDR 5'h3
`define RTK_EXEC 5'h4
`define RTK_EXEC2 5'h5
`define RTK_END 5'h6
`define RTK_CMD_WRITE "W"
`define RTK_CMD_READ "R"
`define RTK_COOKIE_1 32'h12345678
`define RTK_COOKIE_2 24'h434241
`define RTK_COOKIE_3 24'h2D2D2D
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
begin
RTKState<=`RTK_FIND_START;
RTKDeviated<=0;
end
else begin
case (RTKState)
`RTK_FIND_START:
if ( HWDATA ==`RTK_COOKIE_1)
begin
RTKState<=`RTK_FIND_CMD;
end
`RTK_FIND_CMD:
begin
if ( HWDATA[31:8] ==`RTK_COOKIE_2)
begin
RTKCmd<=HWDATA[7:0];
RTKState<=`RTK_FIND_DATA;
RTKCount<=0;
end
else RTKState<=`RTK_FIND_START;
end
`RTK_FIND_DATA:
begin
if ( HWDATA[31:8] ==`RTK_COOKIE_3)
begin
if (RTKCount==3)
begin
RTKState<=`RTK_FIND_ADDR;
RTKCount<=0;
end
else RTKCount<=RTKCount+4'h1;
RTKData[31:8]<=RTKData[23:0];
RTKData[7:0]<=HWDATA[7:0];
end
end
`RTK_FIND_ADDR:
begin
if ( HWDATA[31:8] ==`RTK_COOKIE_3)
begin
if (RTKCount==3)
begin
RTKState<=`RTK_EXEC;
RTKDeviated<=1;
end
else RTKCount<=RTKCount+4'h1;
RTKAddr[31:8]<=RTKAddr[23:0];
RTKAddr[7:0]<=HWDATA[7:0];
end
end
`RTK_EXEC:
begin
case (RTKCmd)
`RTK_CMD_WRITE:
begin
RTKHWRITE<=1;
RTKHTRANS<=2;
RTKState<=`RTK_EXEC2;
end
`RTK_CMD_READ:
begin
RTKState<=`RTK_FIND_START;
end
endcase
end
`RTK_EXEC2:
begin
RTKHWRITE<=0;
RTKState<=`RTK_END;
end
`RTK_END:
begin
$display("END");
RTKDeviated<=0;
RTKHWRITE<=0;
RTKState<=`RTK_FIND_START;
end
endcase
end
end
endmodule | 8 |
141,990 | data/full_repos/permissive/96664564/sorath/sorath.v | 96,664,564 | sorath.v | v | 58 | 189 | [] | [] | [] | [(9, 57)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96664564/sorath/sorath.v:36: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance sorath\n RTKState<=5\'h0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96664564/sorath/sorath.v:44: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n : ... In instance sorath\n RTKState<=5\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/sorath/sorath.v:52: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance sorath\n RTKState<=5\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96664564/sorath/sorath.v:40: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance sorath\n case (RTKState)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/96664564/sorath/sorath.v:40: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1\' generates 5 bits.\n : ... In instance sorath\n case (RTKState)\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 312,897 | module | module sorath (
input wire HCLK,
input wire HRESETn ,
input wire [31:0] HWDATA,
output reg SIGNAL_DETECTED
);
reg [5:0] RTKState;
reg [8:0] RTKCmd;
`define RTK_FIND_START 5'h0
`define RTK_FIND_2 5'h1
`define RTK_COOKIE_1 32'h12345678
`define RTK_COOKIE_2 32'h43424140
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
begin
RTKState<=`RTK_FIND_START;
SIGNAL_DETECTED<=0;
end
else begin
case (RTKState)
`RTK_FIND_START:
if ( HWDATA ==`RTK_COOKIE_1)
begin
RTKState<=`RTK_FIND_2;
end
`RTK_FIND_2:
begin
if ( HWDATA ==`RTK_COOKIE_2)
begin
SIGNAL_DETECTED<=1;
end
RTKState<=`RTK_FIND_START;
end
endcase
end
end
endmodule | module sorath (
input wire HCLK,
input wire HRESETn ,
input wire [31:0] HWDATA,
output reg SIGNAL_DETECTED
); |
reg [5:0] RTKState;
reg [8:0] RTKCmd;
`define RTK_FIND_START 5'h0
`define RTK_FIND_2 5'h1
`define RTK_COOKIE_1 32'h12345678
`define RTK_COOKIE_2 32'h43424140
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
begin
RTKState<=`RTK_FIND_START;
SIGNAL_DETECTED<=0;
end
else begin
case (RTKState)
`RTK_FIND_START:
if ( HWDATA ==`RTK_COOKIE_1)
begin
RTKState<=`RTK_FIND_2;
end
`RTK_FIND_2:
begin
if ( HWDATA ==`RTK_COOKIE_2)
begin
SIGNAL_DETECTED<=1;
end
RTKState<=`RTK_FIND_START;
end
endcase
end
end
endmodule | 8 |
141,993 | data/full_repos/permissive/96903963/fpga/clkdiv.v | 96,903,963 | clkdiv.v | v | 27 | 31 | [] | [] | [] | null | line:8: before: "=" | data/verilator_xmls/bb29e227-f62d-4303-821c-7c061524f03f.xml | null | 312,900 | module | module clkdiv #(
parameter DIV = 1
) (
input wire nreset,
input wire clk,
output reg out = 0
);
reg[$clog2(DIV):0] cnt = 0;
always @(posedge clk) begin
if (!nreset) begin
cnt <= 0;
end else begin
if (cnt == (DIV - 1)) begin
cnt <= 0;
out = !out;
end else begin
cnt <= cnt + 1;
end
end
end
endmodule | module clkdiv #(
parameter DIV = 1
) (
input wire nreset,
input wire clk,
output reg out = 0
); |
reg[$clog2(DIV):0] cnt = 0;
always @(posedge clk) begin
if (!nreset) begin
cnt <= 0;
end else begin
if (cnt == (DIV - 1)) begin
cnt <= 0;
out = !out;
end else begin
cnt <= cnt + 1;
end
end
end
endmodule | 1 |
141,995 | data/full_repos/permissive/96903963/fpga/cmdparser.v | 96,903,963 | cmdparser.v | v | 94 | 99 | [] | [] | [] | null | line:8: before: "=" | data/verilator_xmls/500676fd-1a07-4cac-a54c-92017a7c0215.xml | null | 312,902 | module | module cmdparser (
input wire nreset,
input wire clk,
output reg[7:0] address = 0,
inout wire[7:0] data,
output reg rd = 0,
output reg wr = 0,
input wire[7:0] in_data,
input wire in_valid,
output wire in_ack,
output reg[7:0] out_data = 0,
output reg out_valid = 0
);
localparam S_IDLE = 0, S_READ_A = 1, S_READ_D = 2, S_WRITE_A = 3, S_WRITE_D = 4,
S_END = 9;
localparam CMD_WRITE = 8'haa, CMD_READ = 8'h55;
reg[7:0] state = S_IDLE;
reg[7:0] data_out = 0;
assign data = !rd ? data_out : 8'hZZ;
assign in_ack = state == S_IDLE || state == S_READ_A || state == S_WRITE_A || state == S_WRITE_D;
always @(posedge clk) begin
if (!nreset) begin
state <= S_IDLE;
address = 0;
data_out = 0;
rd = 0;
wr = 0;
end else begin
case (state)
S_IDLE: begin
rd <= 0;
wr <= 0;
if (in_valid) begin
case (in_data)
CMD_READ: begin
state <= S_READ_A;
end
CMD_WRITE: begin
state <= S_WRITE_A;
end
endcase
end
end
S_READ_A: begin
if (in_valid) begin
address <= in_data;
rd <= 1;
state <= S_READ_D;
end
end
S_READ_D: begin
rd <= 0;
out_data <= data;
out_valid <= 1;
state <= S_END;
end
S_WRITE_A: begin
if (in_valid) begin
address <= in_data;
state <= S_WRITE_D;
end
end
S_WRITE_D: begin
if (in_valid) begin
data_out <= in_data;
wr <= 1;
state <= S_END;
end
end
S_END: begin
rd <= 0;
wr <= 0;
out_valid <= 0;
state <= S_IDLE;
end
endcase
end
end
endmodule | module cmdparser (
input wire nreset,
input wire clk,
output reg[7:0] address = 0,
inout wire[7:0] data,
output reg rd = 0,
output reg wr = 0,
input wire[7:0] in_data,
input wire in_valid,
output wire in_ack,
output reg[7:0] out_data = 0,
output reg out_valid = 0
); |
localparam S_IDLE = 0, S_READ_A = 1, S_READ_D = 2, S_WRITE_A = 3, S_WRITE_D = 4,
S_END = 9;
localparam CMD_WRITE = 8'haa, CMD_READ = 8'h55;
reg[7:0] state = S_IDLE;
reg[7:0] data_out = 0;
assign data = !rd ? data_out : 8'hZZ;
assign in_ack = state == S_IDLE || state == S_READ_A || state == S_WRITE_A || state == S_WRITE_D;
always @(posedge clk) begin
if (!nreset) begin
state <= S_IDLE;
address = 0;
data_out = 0;
rd = 0;
wr = 0;
end else begin
case (state)
S_IDLE: begin
rd <= 0;
wr <= 0;
if (in_valid) begin
case (in_data)
CMD_READ: begin
state <= S_READ_A;
end
CMD_WRITE: begin
state <= S_WRITE_A;
end
endcase
end
end
S_READ_A: begin
if (in_valid) begin
address <= in_data;
rd <= 1;
state <= S_READ_D;
end
end
S_READ_D: begin
rd <= 0;
out_data <= data;
out_valid <= 1;
state <= S_END;
end
S_WRITE_A: begin
if (in_valid) begin
address <= in_data;
state <= S_WRITE_D;
end
end
S_WRITE_D: begin
if (in_valid) begin
data_out <= in_data;
wr <= 1;
state <= S_END;
end
end
S_END: begin
rd <= 0;
wr <= 0;
out_valid <= 0;
state <= S_IDLE;
end
endcase
end
end
endmodule | 1 |
141,996 | data/full_repos/permissive/96903963/fpga/cmdparser_tb.v | 96,903,963 | cmdparser_tb.v | v | 71 | 71 | [] | [] | [] | null | line:51: before: "@" | null | 1: b'%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("cmdparser_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(clk);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #2 clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:51: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:54: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:56: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:59: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:62: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:64: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/cmdparser_tb.v:66: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: Exiting due to 9 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,903 | module | module cmdparser_tb();
reg nreset = 1;
reg clk = 0;
initial begin
$dumpfile("cmdparser_tb.vcd");
$dumpvars(clk);
end
always begin
#2 clk <= !clk;
end
register #(.ADDRESS(8'hab), .INITVAL(8'h10), .MASK(8'h0f)) register (
.nreset(nreset),
.clk(clk),
.maskvals(8'h04)
);
reg[7:0] fifo_in = 0;
reg fifo_wr = 0;
fifo8_short fifo (
.clock(clk),
.data(fifo_in),
.wrreq(fifo_wr)
);
cmdparser cmdparser (
.nreset(nreset),
.clk(clk),
.address(register.address),
.data(register.data),
.rd(register.rd),
.wr(register.wr),
.in_data(fifo.q),
.in_valid(!fifo.empty),
.in_ack(fifo.rdreq)
);
initial begin
#20
@(posedge clk);
fifo_wr = 1;
fifo_in = 8'h55;
@(posedge clk);
fifo_in = 8'hab;
@(posedge clk);
fifo_wr = 0;
#100
@(posedge clk);
fifo_wr = 1;
fifo_in = 8'haa;
@(posedge clk);
fifo_in = 8'hab;
@(posedge clk);
fifo_in = 8'h50;
@(posedge clk);
fifo_wr = 0;
end
endmodule | module cmdparser_tb(); |
reg nreset = 1;
reg clk = 0;
initial begin
$dumpfile("cmdparser_tb.vcd");
$dumpvars(clk);
end
always begin
#2 clk <= !clk;
end
register #(.ADDRESS(8'hab), .INITVAL(8'h10), .MASK(8'h0f)) register (
.nreset(nreset),
.clk(clk),
.maskvals(8'h04)
);
reg[7:0] fifo_in = 0;
reg fifo_wr = 0;
fifo8_short fifo (
.clock(clk),
.data(fifo_in),
.wrreq(fifo_wr)
);
cmdparser cmdparser (
.nreset(nreset),
.clk(clk),
.address(register.address),
.data(register.data),
.rd(register.rd),
.wr(register.wr),
.in_data(fifo.q),
.in_valid(!fifo.empty),
.in_ack(fifo.rdreq)
);
initial begin
#20
@(posedge clk);
fifo_wr = 1;
fifo_in = 8'h55;
@(posedge clk);
fifo_in = 8'hab;
@(posedge clk);
fifo_wr = 0;
#100
@(posedge clk);
fifo_wr = 1;
fifo_in = 8'haa;
@(posedge clk);
fifo_in = 8'hab;
@(posedge clk);
fifo_in = 8'h50;
@(posedge clk);
fifo_wr = 0;
end
endmodule | 1 |
141,998 | data/full_repos/permissive/96903963/fpga/ft232.v | 96,903,963 | ft232.v | v | 111 | 72 | [] | [] | [] | [(3, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/96903963/fpga/ft232.v:36: Cannot find file containing module: 'ft232_fifo'\n ft232_fifo wrfifo (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/ft232_fifo\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/ft232_fifo.v\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/ft232_fifo.sv\n ft232_fifo\n ft232_fifo.v\n ft232_fifo.sv\n obj_dir/ft232_fifo\n obj_dir/ft232_fifo.v\n obj_dir/ft232_fifo.sv\n%Error: data/full_repos/permissive/96903963/fpga/ft232.v:54: Cannot find file containing module: 'ft232_fifo_short'\n ft232_fifo_short rdfifo (\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,908 | module | module ft232 (
input wire nreset,
input wire clk,
input wire ft_clk,
input wire ft_nrxf,
inout wire[7:0] ft_data,
output wire ft_noe,
output wire ft_nrd,
output wire ft_nwr,
input wire ft_ntxe,
input wire[7:0] wrdata,
input wire wrreq,
output wire[7:0] rddata,
input wire rdreq,
output wire rdempty,
output wire test
);
localparam S_IDLE = 0, S_WRITE = 1, S_TURN = 2, S_READ = 3, S_END = 4;
reg[7:0] state = S_IDLE;
wire wrfifo_rdreq;
wire wrfifo_rdempty;
wire[7:0] wrfifo_q;
wire[15:0] wrfifo_rdusedw;
ft232_fifo wrfifo (
.aclr(!nreset),
.wrclk(clk),
.data(wrdata),
.wrreq(wrreq),
.rdclk(ft_clk),
.rdreq(wrfifo_rdreq),
.rdempty(wrfifo_rdempty),
.rdusedw(wrfifo_rdusedw),
.q(wrfifo_q)
);
wire[7:0] rdfifo_data;
wire rdfifo_wrreq;
wire rdfifo_wrfull;
ft232_fifo_short rdfifo (
.rdclk(clk),
.q(rddata),
.rdreq(rdreq),
.rdempty(rdempty),
.wrclk(ft_clk),
.data(ft_data),
.wrreq(rdfifo_wrreq),
.wrfull(rdfifo_wrfull)
);
assign ft_data = ft_noe ? wrfifo_q : 8'hZZ;
assign ft_nwr = !(!wrfifo_rdempty && state == S_WRITE && !ft_ntxe);
assign wrfifo_rdreq = !ft_nwr;
assign ft_noe = !(state == S_TURN || state == S_READ);
assign ft_nrd = !(state == S_READ);
assign rdfifo_wrreq = !ft_nrd && !ft_nrxf;
reg[15:0] timeout = 0;
assign test = rdempty;
always @(posedge ft_clk) begin
timeout <= timeout + 1;
case (state)
S_IDLE: begin
if (!ft_nrxf && !rdfifo_wrfull) begin
state <= S_TURN;
end else if (!ft_ntxe &&
(wrfifo_rdusedw > 512 || (!wrfifo_rdempty && timeout == 0))) begin
state <= S_WRITE;
end
end
S_WRITE: begin
if (wrfifo_rdempty || ft_ntxe) begin
state <= S_END;
end
end
S_TURN: begin
state <= S_READ;
end
S_READ: begin
if (rdfifo_wrfull || ft_nrxf) begin
state <= S_END;
end
end
S_END: begin
state <= S_IDLE;
end
endcase
end
endmodule | module ft232 (
input wire nreset,
input wire clk,
input wire ft_clk,
input wire ft_nrxf,
inout wire[7:0] ft_data,
output wire ft_noe,
output wire ft_nrd,
output wire ft_nwr,
input wire ft_ntxe,
input wire[7:0] wrdata,
input wire wrreq,
output wire[7:0] rddata,
input wire rdreq,
output wire rdempty,
output wire test
); |
localparam S_IDLE = 0, S_WRITE = 1, S_TURN = 2, S_READ = 3, S_END = 4;
reg[7:0] state = S_IDLE;
wire wrfifo_rdreq;
wire wrfifo_rdempty;
wire[7:0] wrfifo_q;
wire[15:0] wrfifo_rdusedw;
ft232_fifo wrfifo (
.aclr(!nreset),
.wrclk(clk),
.data(wrdata),
.wrreq(wrreq),
.rdclk(ft_clk),
.rdreq(wrfifo_rdreq),
.rdempty(wrfifo_rdempty),
.rdusedw(wrfifo_rdusedw),
.q(wrfifo_q)
);
wire[7:0] rdfifo_data;
wire rdfifo_wrreq;
wire rdfifo_wrfull;
ft232_fifo_short rdfifo (
.rdclk(clk),
.q(rddata),
.rdreq(rdreq),
.rdempty(rdempty),
.wrclk(ft_clk),
.data(ft_data),
.wrreq(rdfifo_wrreq),
.wrfull(rdfifo_wrfull)
);
assign ft_data = ft_noe ? wrfifo_q : 8'hZZ;
assign ft_nwr = !(!wrfifo_rdempty && state == S_WRITE && !ft_ntxe);
assign wrfifo_rdreq = !ft_nwr;
assign ft_noe = !(state == S_TURN || state == S_READ);
assign ft_nrd = !(state == S_READ);
assign rdfifo_wrreq = !ft_nrd && !ft_nrxf;
reg[15:0] timeout = 0;
assign test = rdempty;
always @(posedge ft_clk) begin
timeout <= timeout + 1;
case (state)
S_IDLE: begin
if (!ft_nrxf && !rdfifo_wrfull) begin
state <= S_TURN;
end else if (!ft_ntxe &&
(wrfifo_rdusedw > 512 || (!wrfifo_rdempty && timeout == 0))) begin
state <= S_WRITE;
end
end
S_WRITE: begin
if (wrfifo_rdempty || ft_ntxe) begin
state <= S_END;
end
end
S_TURN: begin
state <= S_READ;
end
S_READ: begin
if (rdfifo_wrfull || ft_nrxf) begin
state <= S_END;
end
end
S_END: begin
state <= S_IDLE;
end
endcase
end
endmodule | 1 |
142,001 | data/full_repos/permissive/96903963/fpga/i2c_tb.v | 96,903,963 | i2c_tb.v | v | 95 | 46 | [] | [] | [] | null | line:68: before: "@" | null | 1: b'%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:17: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("i2c_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:18: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(clk);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:26: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:31: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:43: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:46: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:65: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/96903963/fpga/i2c_tb.v:68: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/i2c_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/i2c_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #15\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/i2c_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #3000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/i2c_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #2 clk <= !clk;\n ^\n%Error: Exiting due to 8 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,915 | module | module i2c_tb();
reg nreset = 1;
reg clk = 0;
reg[7:0] address = 0;
reg[7:0] data_out = 0;
reg data_oe = 0;
wire[7:0] data = data_oe ? data_out : 8'hZZ;
reg rd = 0;
reg wr = 0;
initial begin
$dumpfile("i2c_tb.vcd");
$dumpvars(clk);
end
task write;
input[7:0] to;
input[7:0] val;
begin
@(posedge clk);
wr = 1;
address = to;
data_oe = 1;
data_out = val;
@(posedge clk);
wr = 0;
address = 0;
data_oe = 0;
data_out = 0;
end
endtask
task read;
input[7:0] from;
begin
@(posedge clk);
rd = 1;
address = from;
@(posedge clk);
rd = 0;
address = 0;
end
endtask
i2c #(.BASEADDR(0), .CLKDIV(5)) i2c (
.nreset(nreset),
.clk(clk),
.address(address),
.data(data),
.rd(rd),
.wr(wr)
);
reg[7:0] test;
initial begin
@(posedge clk);
nreset = 0;
#10
@(posedge clk);
nreset = 1;
#15
write(1, 8'h80 | 2);
write(1, 8'b10101010);
write(1, 8'b00110010);
write(1, 8'b00010001);
write(1, 8'h80 | 2);
write(1, 8'b11011010);
write(1, 8'b10100110);
write(1, 8'b01010001);
#3000
write(1, 3);
write(1, 8'b11010011);
end
always begin
#2 clk <= !clk;
end
endmodule | module i2c_tb(); |
reg nreset = 1;
reg clk = 0;
reg[7:0] address = 0;
reg[7:0] data_out = 0;
reg data_oe = 0;
wire[7:0] data = data_oe ? data_out : 8'hZZ;
reg rd = 0;
reg wr = 0;
initial begin
$dumpfile("i2c_tb.vcd");
$dumpvars(clk);
end
task write;
input[7:0] to;
input[7:0] val;
begin
@(posedge clk);
wr = 1;
address = to;
data_oe = 1;
data_out = val;
@(posedge clk);
wr = 0;
address = 0;
data_oe = 0;
data_out = 0;
end
endtask
task read;
input[7:0] from;
begin
@(posedge clk);
rd = 1;
address = from;
@(posedge clk);
rd = 0;
address = 0;
end
endtask
i2c #(.BASEADDR(0), .CLKDIV(5)) i2c (
.nreset(nreset),
.clk(clk),
.address(address),
.data(data),
.rd(rd),
.wr(wr)
);
reg[7:0] test;
initial begin
@(posedge clk);
nreset = 0;
#10
@(posedge clk);
nreset = 1;
#15
write(1, 8'h80 | 2);
write(1, 8'b10101010);
write(1, 8'b00110010);
write(1, 8'b00010001);
write(1, 8'h80 | 2);
write(1, 8'b11011010);
write(1, 8'b10100110);
write(1, 8'b01010001);
#3000
write(1, 3);
write(1, 8'b11010011);
end
always begin
#2 clk <= !clk;
end
endmodule | 1 |
142,003 | data/full_repos/permissive/96903963/fpga/packeter_tb.v | 96,903,963 | packeter_tb.v | v | 64 | 47 | [] | [] | [] | [(5, 63)] | null | null | 1: b'%Error: data/full_repos/permissive/96903963/fpga/packeter_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("packeter_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/packeter_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(clk);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/packeter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #2 clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,917 | module | module packeter_tb ();
reg nreset = 1;
reg clk = 0;
initial begin
$dumpfile("packeter_tb.vcd");
$dumpvars(clk);
end
always begin
#2 clk <= !clk;
end
wire adc_packer_valid;
wire[11:0] adc_packer_data;
adc #(.DIV(40), .BITS(12)) adc (
.nreset(1'b1),
.clk(clk),
.pattern(1'b1),
.out(adc_packer_data),
.valid(adc_packer_valid)
);
wire packer_packeter_valid;
wire[7:0] packer_packeter_data;
packer_12to8 packer (
.nreset(1'b1),
.clk(clk),
.in_valid(adc_packer_valid),
.in_data(adc_packer_data),
.out_valid(packer_packeter_valid),
.out_data(packer_packeter_data)
);
wire packeter_ftdi_valid;
wire[7:0] packeter_ftdi_data;
packeter packeter (
.nreset(1'b1),
.clk(clk),
.sample_valid(packer_packeter_valid),
.sample_data(packer_packeter_data),
.event_valid(1'b0),
.event_data(8'h00),
.out_valid(packeter_ftdi_valid),
.out_data(packeter_ftdi_data)
);
endmodule | module packeter_tb (); |
reg nreset = 1;
reg clk = 0;
initial begin
$dumpfile("packeter_tb.vcd");
$dumpvars(clk);
end
always begin
#2 clk <= !clk;
end
wire adc_packer_valid;
wire[11:0] adc_packer_data;
adc #(.DIV(40), .BITS(12)) adc (
.nreset(1'b1),
.clk(clk),
.pattern(1'b1),
.out(adc_packer_data),
.valid(adc_packer_valid)
);
wire packer_packeter_valid;
wire[7:0] packer_packeter_data;
packer_12to8 packer (
.nreset(1'b1),
.clk(clk),
.in_valid(adc_packer_valid),
.in_data(adc_packer_data),
.out_valid(packer_packeter_valid),
.out_data(packer_packeter_data)
);
wire packeter_ftdi_valid;
wire[7:0] packeter_ftdi_data;
packeter packeter (
.nreset(1'b1),
.clk(clk),
.sample_valid(packer_packeter_valid),
.sample_data(packer_packeter_data),
.event_valid(1'b0),
.event_data(8'h00),
.out_valid(packeter_ftdi_valid),
.out_data(packeter_ftdi_data)
);
endmodule | 1 |
142,005 | data/full_repos/permissive/96903963/fpga/ppsin_tb.v | 96,903,963 | ppsin_tb.v | v | 31 | 23 | [] | [] | [] | [(5, 30)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/ppsin_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #2 clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/ppsin_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96903963/fpga/ppsin_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #900\n ^\n%Error: data/full_repos/permissive/96903963/fpga/ppsin_tb.v:22: Cannot find file containing module: \'ppsin\'\n ppsin ppsin (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/ppsin\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/ppsin.v\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/ppsin.sv\n ppsin\n ppsin.v\n ppsin.sv\n obj_dir/ppsin\n obj_dir/ppsin.v\n obj_dir/ppsin.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,921 | module | module ppsin_tb();
reg nreset = 1;
reg clk = 0;
reg pps = 0;
always begin
#2 clk <= !clk;
end
always begin
#100
pps = 0;
#900
pps = 1;
end
ppsin ppsin (
.nreset(nreset),
.clk(clk),
.pps(pps)
);
endmodule | module ppsin_tb(); |
reg nreset = 1;
reg clk = 0;
reg pps = 0;
always begin
#2 clk <= !clk;
end
always begin
#100
pps = 0;
#900
pps = 1;
end
ppsin ppsin (
.nreset(nreset),
.clk(clk),
.pps(pps)
);
endmodule | 1 |
142,007 | data/full_repos/permissive/96903963/fpga/register.v | 96,903,963 | register.v | v | 129 | 59 | [] | [] | [] | [(2, 43), (45, 59), (61, 98), (100, 128)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/96903963/fpga/register.v:45: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'register\'\nmodule register #(\n ^~~~~~~~\n : ... Top module \'register_constant\'\nmodule register_constant #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_rd\'\nmodule register_fifo_rd #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_wr\'\nmodule register_fifo_wr #(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/register.v:116: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.v\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.sv\n fifo8_short\n fifo8_short.v\n fifo8_short.sv\n obj_dir/fifo8_short\n obj_dir/fifo8_short.v\n obj_dir/fifo8_short.sv\n%Error: data/full_repos/permissive/96903963/fpga/register.v:84: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 312,923 | module | module register #(
parameter ADDRESS = 8'h00,
parameter INITVAL = 8'h00,
parameter MASK = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
inout wire[7:0] data,
input wire rd,
input wire wr,
input wire set_force,
input wire[7:0] set_data,
input wire[7:0] maskvals,
output wire[7:0] out
);
reg[7:0] value = INITVAL;
assign out = (value & ~MASK) | (maskvals & MASK);
wire selected = address == ADDRESS;
assign data = (rd && selected) ? out : 8'hZZ;
always @(posedge clk) begin
if (!nreset) begin
value <= INITVAL;
end else begin
if (set_force) begin
value <= set_data;
end else if (wr && selected) begin
value <= data;
end
end
end
endmodule | module register #(
parameter ADDRESS = 8'h00,
parameter INITVAL = 8'h00,
parameter MASK = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
inout wire[7:0] data,
input wire rd,
input wire wr,
input wire set_force,
input wire[7:0] set_data,
input wire[7:0] maskvals,
output wire[7:0] out
); |
reg[7:0] value = INITVAL;
assign out = (value & ~MASK) | (maskvals & MASK);
wire selected = address == ADDRESS;
assign data = (rd && selected) ? out : 8'hZZ;
always @(posedge clk) begin
if (!nreset) begin
value <= INITVAL;
end else begin
if (set_force) begin
value <= set_data;
end else if (wr && selected) begin
value <= data;
end
end
end
endmodule | 1 |
142,008 | data/full_repos/permissive/96903963/fpga/register.v | 96,903,963 | register.v | v | 129 | 59 | [] | [] | [] | [(2, 43), (45, 59), (61, 98), (100, 128)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/96903963/fpga/register.v:45: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'register\'\nmodule register #(\n ^~~~~~~~\n : ... Top module \'register_constant\'\nmodule register_constant #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_rd\'\nmodule register_fifo_rd #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_wr\'\nmodule register_fifo_wr #(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/register.v:116: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.v\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.sv\n fifo8_short\n fifo8_short.v\n fifo8_short.sv\n obj_dir/fifo8_short\n obj_dir/fifo8_short.v\n obj_dir/fifo8_short.sv\n%Error: data/full_repos/permissive/96903963/fpga/register.v:84: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 312,923 | module | module register_constant #(
parameter ADDRESS = 8'h00,
parameter VALUE = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
inout wire[7:0] data,
input wire rd
);
assign data = (address == ADDRESS && rd) ? VALUE : 8'hZZ;
endmodule | module register_constant #(
parameter ADDRESS = 8'h00,
parameter VALUE = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
inout wire[7:0] data,
input wire rd
); |
assign data = (address == ADDRESS && rd) ? VALUE : 8'hZZ;
endmodule | 1 |
142,009 | data/full_repos/permissive/96903963/fpga/register.v | 96,903,963 | register.v | v | 129 | 59 | [] | [] | [] | [(2, 43), (45, 59), (61, 98), (100, 128)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/96903963/fpga/register.v:45: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'register\'\nmodule register #(\n ^~~~~~~~\n : ... Top module \'register_constant\'\nmodule register_constant #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_rd\'\nmodule register_fifo_rd #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_wr\'\nmodule register_fifo_wr #(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/register.v:116: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.v\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.sv\n fifo8_short\n fifo8_short.v\n fifo8_short.sv\n obj_dir/fifo8_short\n obj_dir/fifo8_short.v\n obj_dir/fifo8_short.sv\n%Error: data/full_repos/permissive/96903963/fpga/register.v:84: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 312,923 | module | module register_fifo_rd #(
parameter ADDRESS = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
inout wire[7:0] data,
input wire rd,
input wire wr,
input wire [7:0] wrdata,
input wire wrreq,
output wire empty,
output wire full
);
wire read = address == ADDRESS && rd ;
wire[7:0] fifo_out;
assign data = read ? fifo_out : 8'hZZ;
fifo8_short fifo (
.sclr(!nreset),
.clock(clk),
.rdreq(read),
.q(fifo_out),
.wrreq(wrreq),
.data(wrdata),
.empty(empty),
.full(full)
);
endmodule | module register_fifo_rd #(
parameter ADDRESS = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
inout wire[7:0] data,
input wire rd,
input wire wr,
input wire [7:0] wrdata,
input wire wrreq,
output wire empty,
output wire full
); |
wire read = address == ADDRESS && rd ;
wire[7:0] fifo_out;
assign data = read ? fifo_out : 8'hZZ;
fifo8_short fifo (
.sclr(!nreset),
.clock(clk),
.rdreq(read),
.q(fifo_out),
.wrreq(wrreq),
.data(wrdata),
.empty(empty),
.full(full)
);
endmodule | 1 |
142,010 | data/full_repos/permissive/96903963/fpga/register.v | 96,903,963 | register.v | v | 129 | 59 | [] | [] | [] | [(2, 43), (45, 59), (61, 98), (100, 128)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/96903963/fpga/register.v:45: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'register\'\nmodule register #(\n ^~~~~~~~\n : ... Top module \'register_constant\'\nmodule register_constant #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_rd\'\nmodule register_fifo_rd #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'register_fifo_wr\'\nmodule register_fifo_wr #(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/register.v:116: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.v\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/fifo8_short.sv\n fifo8_short\n fifo8_short.v\n fifo8_short.sv\n obj_dir/fifo8_short\n obj_dir/fifo8_short.v\n obj_dir/fifo8_short.sv\n%Error: data/full_repos/permissive/96903963/fpga/register.v:84: Cannot find file containing module: \'fifo8_short\'\n fifo8_short fifo (\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 312,923 | module | module register_fifo_wr #(
parameter ADDRESS = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
input wire[7:0] data,
input wire rd,
input wire wr,
output wire[7:0] rddata,
input wire rdreq,
output wire[9:0] usedw
);
fifo8_short fifo (
.sclr(!nreset),
.clock(clk),
.rdreq(rdreq),
.q(rddata),
.usedw(usedw),
.wrreq(address == ADDRESS && wr),
.data(data)
);
endmodule | module register_fifo_wr #(
parameter ADDRESS = 8'h00
) (
input wire nreset,
input wire clk,
input wire[7:0] address,
input wire[7:0] data,
input wire rd,
input wire wr,
output wire[7:0] rddata,
input wire rdreq,
output wire[9:0] usedw
); |
fifo8_short fifo (
.sclr(!nreset),
.clock(clk),
.rdreq(rdreq),
.q(rddata),
.usedw(usedw),
.wrreq(address == ADDRESS && wr),
.data(data)
);
endmodule | 1 |
142,013 | data/full_repos/permissive/96903963/fpga/toplevel.v | 96,903,963 | toplevel.v | v | 247 | 74 | [] | [] | [] | null | line:227: before: ")" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/96903963/fpga/toplevel.v:186: Signal definition not found, creating implicitly: \'LED2\'\n : ... Suggested alternative: \'LED1\'\n assign LED2 = pps_synced;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:51: Cannot find file containing module: \'pll\'\n pll pll (\n ^~~\n ... Looked in:\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/pll\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/pll.v\n data/full_repos/permissive/96903963/fpga,data/full_repos/permissive/96903963/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:57: Cannot find file containing module: \'sync\'\n sync rstsync (\n ^~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:76: Cannot find file containing module: \'Registers\'\n Registers registers(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:89: Cannot find file containing module: \'i2c\'\n i2c #(.BASEADDR(8\'h10), .CLKDIV(250)) i2c (\n ^~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:105: Cannot find file containing module: \'ADCReader\'\n ADCReader adcreader (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:121: Cannot find file containing module: \'PatternSawtooth\'\n PatternSawtooth patternsawtooth (\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:151: Cannot find file containing module: \'Packer12to8\'\n Packer12to8 packer (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:168: Cannot find file containing module: \'sync\'\n sync pssync (\n ^~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:177: Cannot find file containing module: \'ppsin\'\n ppsin ppsin (\n ^~~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:188: Cannot find file containing module: \'packeter\'\n packeter packeter (\n ^~~~~~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:209: Cannot find file containing module: \'ft232\'\n ft232 ftdi (\n ^~~~~\n%Error: data/full_repos/permissive/96903963/fpga/toplevel.v:229: Cannot find file containing module: \'cmdparser\'\n cmdparser cmdparser (\n ^~~~~~~~~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n' | 312,926 | module | module toplevel (
input wire ADC_D13,
input wire ADC_D12,
input wire ADC_D11,
input wire ADC_D10,
input wire ADC_D9,
input wire ADC_D8,
input wire ADC_D7,
input wire ADC_D6,
input wire ADC_D5,
input wire ADC_D4,
input wire ADC_D3,
input wire ADC_D2,
input wire ADC_D1,
input wire ADC_D0,
output wire ADC_CLK,
inout wire FT_D7,
inout wire FT_D6,
inout wire FT_D5,
inout wire FT_D4,
inout wire FT_D3,
inout wire FT_D2,
inout wire FT_D1,
inout wire FT_D0,
input wire FT_nRXF,
input wire FT_nTXE,
output wire FT_nRD,
output wire FT_nWR,
output wire FT_nOE,
input wire FT_CLK,
input wire FT_RST,
input wire PPS,
input wire CLK_EXT,
input wire CLK_INT,
inout wire SCL,
inout wire SDA,
output wire LED1,
output wire LED_DATA,
output wire TUNER_CLK
);
wire clk;
pll pll (
.inclk0(CLK_INT),
.c0(clk)
);
wire ft_rst_sync;
sync rstsync (
.in(FT_RST),
.out(ft_rst_sync),
.outclk(clk)
);
wire nreset = !ft_rst_sync;
assign LED1 = FT_RST;
assign TUNER_CLK = CLK_EXT;
wire[7:0] bus_address;
wire[7:0] bus_data;
wire bus_rd;
wire bus_wr;
wire reg_adctl_enable;
wire[1:0] reg_adctl_mode;
Registers registers(
.reset(!nreset),
.clock(clk),
.io_bus_address(bus_address),
.io_bus_data(bus_data),
.io_bus_rd(bus_rd),
.io_bus_wr(bus_wr),
.io_adc_enable(reg_adctl_enable),
.io_adc_mode(reg_adctl_mode)
);
i2c #(.BASEADDR(8'h10), .CLKDIV(250)) i2c (
.nreset(nreset),
.clk(clk),
.address(bus_address),
.data(bus_data),
.rd(bus_rd),
.wr(bus_wr),
.scl(SCL),
.sda(SDA)
);
wire adc_packer_valid;
wire[11:0] adc_packer_data;
ADCReader adcreader (
.reset(!nreset),
.clock(clk),
.io_enable(reg_adctl_enable),
.io_adc_data({ADC_D11, ADC_D10, ADC_D9, ADC_D8, ADC_D7, ADC_D6, ADC_D5,
ADC_D4, ADC_D3, ADC_D2, ADC_D1, ADC_D0}),
.io_adc_clock(ADC_CLK),
.io_out_valid(adc_packer_valid),
.io_out_bits(adc_packer_data)
);
wire sawtooth_packer_valid;
wire[11:0] sawtooth_packer_data;
PatternSawtooth patternsawtooth (
.reset(!nreset),
.clock(clk),
.io_enable(reg_adctl_enable),
.io_out_valid(sawtooth_packer_valid),
.io_out_bits(sawtooth_packer_data)
);
reg packer_valid;
reg[11:0] packer_data;
always @* begin
if (reg_adctl_mode == 0) begin
packer_valid = adc_packer_valid;
packer_data = adc_packer_data;
end else if (reg_adctl_mode == 1) begin
packer_valid = sawtooth_packer_valid;
packer_data = sawtooth_packer_data;
end else begin
packer_valid = 1'b0;
end
end
assign LED1 = reg_adctl_mode == 1;
wire packer_packeter_valid;
wire[7:0] packer_packeter_data;
Packer12to8 packer (
.reset(!nreset),
.clock(clk),
.io_in_valid(packer_valid),
.io_in_bits(packer_data),
.io_out_valid(packer_packeter_valid),
.io_out_bits(packer_packeter_data)
);
wire packeter_ftdi_valid;
wire[7:0] packeter_ftdi_data;
wire cmdparser_packeter_valid;
wire[7:0] cmdparser_packeter_data;
wire pps_synced;
sync pssync (
.outclk(clk),
.in(PPS),
.out(pps_synced)
);
wire ppsin_packeter_valid;
wire[7:0] ppsin_packeter_data;
ppsin ppsin (
.nreset(nreset),
.clk(clk),
.pps(pps_synced),
.pps_valid(ppsin_packeter_valid),
.pps_data(ppsin_packeter_data)
);
assign LED2 = pps_synced;
packeter packeter (
.nreset(nreset),
.clk(clk),
.sample_valid(packer_packeter_valid),
.sample_data(packer_packeter_data),
.pps_valid(ppsin_packeter_valid),
.pps_data(ppsin_packeter_data),
.out_valid(packeter_ftdi_valid),
.out_data(packeter_ftdi_data),
.resp_valid(cmdparser_packeter_valid),
.resp_data(cmdparser_packeter_data)
);
wire[7:0] ftdi_rddata;
wire ftdi_rdreq;
wire ftdi_rdempty;
ft232 ftdi (
.nreset(nreset),
.clk(clk),
.ft_clk(FT_CLK),
.ft_nrxf(FT_nRXF),
.ft_data({FT_D7, FT_D6, FT_D5, FT_D4, FT_D3, FT_D2, FT_D1, FT_D0}),
.ft_noe(FT_nOE),
.ft_nrd(FT_nRD),
.ft_nwr(FT_nWR),
.ft_ntxe(FT_nTXE),
.wrreq(packeter_ftdi_valid),
.wrdata(packeter_ftdi_data),
.rddata(ftdi_rddata),
.rdreq(ftdi_rdreq),
.rdempty(ftdi_rdempty),
);
cmdparser cmdparser (
.nreset(nreset),
.clk(clk),
.address(bus_address),
.data(bus_data),
.rd(bus_rd),
.wr(bus_wr),
.in_data(ftdi_rddata),
.in_valid(!ftdi_rdempty),
.in_ack(ftdi_rdreq),
.out_valid(cmdparser_packeter_valid),
.out_data(cmdparser_packeter_data)
);
endmodule | module toplevel (
input wire ADC_D13,
input wire ADC_D12,
input wire ADC_D11,
input wire ADC_D10,
input wire ADC_D9,
input wire ADC_D8,
input wire ADC_D7,
input wire ADC_D6,
input wire ADC_D5,
input wire ADC_D4,
input wire ADC_D3,
input wire ADC_D2,
input wire ADC_D1,
input wire ADC_D0,
output wire ADC_CLK,
inout wire FT_D7,
inout wire FT_D6,
inout wire FT_D5,
inout wire FT_D4,
inout wire FT_D3,
inout wire FT_D2,
inout wire FT_D1,
inout wire FT_D0,
input wire FT_nRXF,
input wire FT_nTXE,
output wire FT_nRD,
output wire FT_nWR,
output wire FT_nOE,
input wire FT_CLK,
input wire FT_RST,
input wire PPS,
input wire CLK_EXT,
input wire CLK_INT,
inout wire SCL,
inout wire SDA,
output wire LED1,
output wire LED_DATA,
output wire TUNER_CLK
); |
wire clk;
pll pll (
.inclk0(CLK_INT),
.c0(clk)
);
wire ft_rst_sync;
sync rstsync (
.in(FT_RST),
.out(ft_rst_sync),
.outclk(clk)
);
wire nreset = !ft_rst_sync;
assign LED1 = FT_RST;
assign TUNER_CLK = CLK_EXT;
wire[7:0] bus_address;
wire[7:0] bus_data;
wire bus_rd;
wire bus_wr;
wire reg_adctl_enable;
wire[1:0] reg_adctl_mode;
Registers registers(
.reset(!nreset),
.clock(clk),
.io_bus_address(bus_address),
.io_bus_data(bus_data),
.io_bus_rd(bus_rd),
.io_bus_wr(bus_wr),
.io_adc_enable(reg_adctl_enable),
.io_adc_mode(reg_adctl_mode)
);
i2c #(.BASEADDR(8'h10), .CLKDIV(250)) i2c (
.nreset(nreset),
.clk(clk),
.address(bus_address),
.data(bus_data),
.rd(bus_rd),
.wr(bus_wr),
.scl(SCL),
.sda(SDA)
);
wire adc_packer_valid;
wire[11:0] adc_packer_data;
ADCReader adcreader (
.reset(!nreset),
.clock(clk),
.io_enable(reg_adctl_enable),
.io_adc_data({ADC_D11, ADC_D10, ADC_D9, ADC_D8, ADC_D7, ADC_D6, ADC_D5,
ADC_D4, ADC_D3, ADC_D2, ADC_D1, ADC_D0}),
.io_adc_clock(ADC_CLK),
.io_out_valid(adc_packer_valid),
.io_out_bits(adc_packer_data)
);
wire sawtooth_packer_valid;
wire[11:0] sawtooth_packer_data;
PatternSawtooth patternsawtooth (
.reset(!nreset),
.clock(clk),
.io_enable(reg_adctl_enable),
.io_out_valid(sawtooth_packer_valid),
.io_out_bits(sawtooth_packer_data)
);
reg packer_valid;
reg[11:0] packer_data;
always @* begin
if (reg_adctl_mode == 0) begin
packer_valid = adc_packer_valid;
packer_data = adc_packer_data;
end else if (reg_adctl_mode == 1) begin
packer_valid = sawtooth_packer_valid;
packer_data = sawtooth_packer_data;
end else begin
packer_valid = 1'b0;
end
end
assign LED1 = reg_adctl_mode == 1;
wire packer_packeter_valid;
wire[7:0] packer_packeter_data;
Packer12to8 packer (
.reset(!nreset),
.clock(clk),
.io_in_valid(packer_valid),
.io_in_bits(packer_data),
.io_out_valid(packer_packeter_valid),
.io_out_bits(packer_packeter_data)
);
wire packeter_ftdi_valid;
wire[7:0] packeter_ftdi_data;
wire cmdparser_packeter_valid;
wire[7:0] cmdparser_packeter_data;
wire pps_synced;
sync pssync (
.outclk(clk),
.in(PPS),
.out(pps_synced)
);
wire ppsin_packeter_valid;
wire[7:0] ppsin_packeter_data;
ppsin ppsin (
.nreset(nreset),
.clk(clk),
.pps(pps_synced),
.pps_valid(ppsin_packeter_valid),
.pps_data(ppsin_packeter_data)
);
assign LED2 = pps_synced;
packeter packeter (
.nreset(nreset),
.clk(clk),
.sample_valid(packer_packeter_valid),
.sample_data(packer_packeter_data),
.pps_valid(ppsin_packeter_valid),
.pps_data(ppsin_packeter_data),
.out_valid(packeter_ftdi_valid),
.out_data(packeter_ftdi_data),
.resp_valid(cmdparser_packeter_valid),
.resp_data(cmdparser_packeter_data)
);
wire[7:0] ftdi_rddata;
wire ftdi_rdreq;
wire ftdi_rdempty;
ft232 ftdi (
.nreset(nreset),
.clk(clk),
.ft_clk(FT_CLK),
.ft_nrxf(FT_nRXF),
.ft_data({FT_D7, FT_D6, FT_D5, FT_D4, FT_D3, FT_D2, FT_D1, FT_D0}),
.ft_noe(FT_nOE),
.ft_nrd(FT_nRD),
.ft_nwr(FT_nWR),
.ft_ntxe(FT_nTXE),
.wrreq(packeter_ftdi_valid),
.wrdata(packeter_ftdi_data),
.rddata(ftdi_rddata),
.rdreq(ftdi_rdreq),
.rdempty(ftdi_rdempty),
);
cmdparser cmdparser (
.nreset(nreset),
.clk(clk),
.address(bus_address),
.data(bus_data),
.rd(bus_rd),
.wr(bus_wr),
.in_data(ftdi_rddata),
.in_valid(!ftdi_rdempty),
.in_ack(ftdi_rdreq),
.out_valid(cmdparser_packeter_valid),
.out_data(cmdparser_packeter_data)
);
endmodule | 1 |
142,015 | data/full_repos/permissive/96918430/main.v | 96,918,430 | main.v | v | 90 | 94 | [] | [] | [] | [(1, 90)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96918430/main.v:44: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'B\' generates 4 bits.\n : ... In instance ticket_shop\n A2Bmoney = 5 * ( B - A + 1 ) ;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96918430/main.v:44: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'A\' generates 4 bits.\n : ... In instance ticket_shop\n A2Bmoney = 5 * ( B - A + 1 ) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/96918430/main.v:47: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 4 bits.\n : ... In instance ticket_shop\n A2Bmoney = 5 * ( A - B + 1 ) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/96918430/main.v:47: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'B\' generates 4 bits.\n : ... In instance ticket_shop\n A2Bmoney = 5 * ( A - B + 1 ) ;\n ^\n%Error: Exiting due to 4 warning(s)\n' | 312,929 | module | module ticket_shop( out_cash, out_num, A, B, num, reset, cancel, money, clock, give );
output reg [31:0]out_cash, out_num;
input [3:0]A ;
input [3:0]B ;
input [31:0]num, money ;
input reset, cancel, clock, give ;
parameter S0 = 4'd0,
S1 = 4'd1,
S2 = 4'd2,
S3 = 4'd3 ;
reg [3:0] state ;
reg [3:0] next_state ;
reg [3:0] Aname ;
reg [3:0] Bname ;
reg [31:0] A2Bmoney ;
reg [31:0] moneyGive ;
reg [31:0] moneymoney ;
always @( posedge clock ) begin
if ( reset ) begin
next_state = S0 ;
A2Bmoney = 0 ;
moneyGive = 0 ;
moneymoney = 0 ;
end
else
state = next_state ;
end
always @( give ) begin
moneymoney = money ;
end
always @( state or give ) begin
case ( state )
S0: begin
Aname = A ;
Bname = B ;
$display( "%d: The ticket you chose is S%d to S%d", $time/10, Aname, Bname ) ;
if ( A < B ) begin
A2Bmoney = 5 * ( B - A + 1 ) ;
end
else begin
A2Bmoney = 5 * ( A - B + 1 ) ;
$display( "%d: A ticket's price is %d TWD.", $time/10, A2Bmoney ) ;
end
next_state = S1 ;
end
S1: begin
$display( "%d: You chose %d tickets.", $time/10, num ) ;
A2Bmoney = A2Bmoney * num ;
next_state = S2 ;
end
S2: begin
$display( "%d: You give me %d TWD.", $time/10, moneymoney ) ;
moneyGive = moneyGive + moneymoney ;
$display( "%d: You have given me %d TWD.", $time/10, moneyGive ) ;
$display( "%d: You have to give me more than %d TWD.", $time/10, A2Bmoney - moneyGive ) ;
if ( cancel )
next_state = S3 ;
else if ( A2Bmoney > moneyGive )
next_state = S2 ;
else
next_state = S3 ;
end
S3: begin
if ( cancel ) begin
$display( "%d: You cancel the step.", $time/10 ) ;
$display( "%d: The money you have given is %d.\n", $time/10, moneyGive ) ;
end
else begin
out_num = num ;
$display( "%d: These are your %d tickets(S%d to S%d).", $time/10, out_num, Aname, Bname ) ;
out_cash = moneyGive - A2Bmoney ;
$display( "%d: And your cash is [%d].\n", $time/10, out_cash ) ;
end
next_state = S0 ;
A2Bmoney = 0 ;
moneyGive = 0 ;
moneymoney = 0 ;
end
default: next_state = S0 ;
endcase
end
endmodule | module ticket_shop( out_cash, out_num, A, B, num, reset, cancel, money, clock, give ); |
output reg [31:0]out_cash, out_num;
input [3:0]A ;
input [3:0]B ;
input [31:0]num, money ;
input reset, cancel, clock, give ;
parameter S0 = 4'd0,
S1 = 4'd1,
S2 = 4'd2,
S3 = 4'd3 ;
reg [3:0] state ;
reg [3:0] next_state ;
reg [3:0] Aname ;
reg [3:0] Bname ;
reg [31:0] A2Bmoney ;
reg [31:0] moneyGive ;
reg [31:0] moneymoney ;
always @( posedge clock ) begin
if ( reset ) begin
next_state = S0 ;
A2Bmoney = 0 ;
moneyGive = 0 ;
moneymoney = 0 ;
end
else
state = next_state ;
end
always @( give ) begin
moneymoney = money ;
end
always @( state or give ) begin
case ( state )
S0: begin
Aname = A ;
Bname = B ;
$display( "%d: The ticket you chose is S%d to S%d", $time/10, Aname, Bname ) ;
if ( A < B ) begin
A2Bmoney = 5 * ( B - A + 1 ) ;
end
else begin
A2Bmoney = 5 * ( A - B + 1 ) ;
$display( "%d: A ticket's price is %d TWD.", $time/10, A2Bmoney ) ;
end
next_state = S1 ;
end
S1: begin
$display( "%d: You chose %d tickets.", $time/10, num ) ;
A2Bmoney = A2Bmoney * num ;
next_state = S2 ;
end
S2: begin
$display( "%d: You give me %d TWD.", $time/10, moneymoney ) ;
moneyGive = moneyGive + moneymoney ;
$display( "%d: You have given me %d TWD.", $time/10, moneyGive ) ;
$display( "%d: You have to give me more than %d TWD.", $time/10, A2Bmoney - moneyGive ) ;
if ( cancel )
next_state = S3 ;
else if ( A2Bmoney > moneyGive )
next_state = S2 ;
else
next_state = S3 ;
end
S3: begin
if ( cancel ) begin
$display( "%d: You cancel the step.", $time/10 ) ;
$display( "%d: The money you have given is %d.\n", $time/10, moneyGive ) ;
end
else begin
out_num = num ;
$display( "%d: These are your %d tickets(S%d to S%d).", $time/10, out_num, Aname, Bname ) ;
out_cash = moneyGive - A2Bmoney ;
$display( "%d: And your cash is [%d].\n", $time/10, out_cash ) ;
end
next_state = S0 ;
A2Bmoney = 0 ;
moneyGive = 0 ;
moneymoney = 0 ;
end
default: next_state = S0 ;
endcase
end
endmodule | 0 |
142,016 | data/full_repos/permissive/96918430/stimulate.v | 96,918,430 | stimulate.v | v | 40 | 92 | [] | [] | [] | [(1, 40)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/96918430/stimulate.v:19: Unsupported: Ignoring delay on this delayed statement.\n forever #5 clock = ~clock ; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/96918430/stimulate.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1\'b0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96918430/stimulate.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 A = 4\'d1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96918430/stimulate.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 num = 3 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96918430/stimulate.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10 give = ~give ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96918430/stimulate.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 give = ~give ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/96918430/stimulate.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 give = ~give ;\n ^\n%Error: data/full_repos/permissive/96918430/stimulate.v:9: Cannot find file containing module: \'ticket_shop\'\nticket_shop ticket_shop( out_cash, out_num, A, B, num, reset, cancel, money, clock, give );\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96918430,data/full_repos/permissive/96918430/ticket_shop\n data/full_repos/permissive/96918430,data/full_repos/permissive/96918430/ticket_shop.v\n data/full_repos/permissive/96918430,data/full_repos/permissive/96918430/ticket_shop.sv\n ticket_shop\n ticket_shop.v\n ticket_shop.sv\n obj_dir/ticket_shop\n obj_dir/ticket_shop.v\n obj_dir/ticket_shop.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,930 | module | module stimulate() ;
wire [31:0]out_cash, out_num;
reg [3:0]A ;
reg [3:0]B ;
reg [31:0]num, money ;
reg reset, cancel, clock, give ;
ticket_shop ticket_shop( out_cash, out_num, A, B, num, reset, cancel, money, clock, give );
initial begin
A = 0 ;
B = 0 ;
num = 0 ;
cancel = 0 ;
money = 10 ;
give = 1'b1 ;
clock = 1'b1 ;
forever #5 clock = ~clock ;
end
initial begin
reset = 1'b1 ;
#5 reset = 1'b0 ;
end
initial begin
#10 A = 4'd1 ;
B = 4'd2 ;
#10 num = 3 ;
#10 give = ~give ;
money = 10 ;
#10 give = ~give ;
money = 10 ;
#10 give = ~give ;
money = 10 ;
end
endmodule | module stimulate() ; |
wire [31:0]out_cash, out_num;
reg [3:0]A ;
reg [3:0]B ;
reg [31:0]num, money ;
reg reset, cancel, clock, give ;
ticket_shop ticket_shop( out_cash, out_num, A, B, num, reset, cancel, money, clock, give );
initial begin
A = 0 ;
B = 0 ;
num = 0 ;
cancel = 0 ;
money = 10 ;
give = 1'b1 ;
clock = 1'b1 ;
forever #5 clock = ~clock ;
end
initial begin
reset = 1'b1 ;
#5 reset = 1'b0 ;
end
initial begin
#10 A = 4'd1 ;
B = 4'd2 ;
#10 num = 3 ;
#10 give = ~give ;
money = 10 ;
#10 give = ~give ;
money = 10 ;
#10 give = ~give ;
money = 10 ;
end
endmodule | 0 |
142,018 | data/full_repos/permissive/9697899/prescaler.v | 9,697,899 | prescaler.v | v | 72 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(30, 71)] | null | data/verilator_xmls/4126b532-0b4d-4093-9e41-029fbacea3b5.xml | null | 312,947 | module | module prescaler (clock, reset, div, scaled);
parameter [31:0] SCALE = 28;
input clock;
input reset;
input [1:0] div;
output scaled;
wire scaled = 1'b1;
endmodule | module prescaler (clock, reset, div, scaled); |
parameter [31:0] SCALE = 28;
input clock;
input reset;
input [1:0] div;
output scaled;
wire scaled = 1'b1;
endmodule | 4 |
142,021 | data/full_repos/permissive/9699476/rtl/cdc.v | 9,699,476 | cdc.v | v | 233 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:59: before: "[" | null | 1: b'%Error: data/full_repos/permissive/9699476/rtl/cdc.v:59: Unsupported: wor\n output wor [DW-1:0] ffo_dat, \n ^~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,978 | module | module cdc #(
parameter integer DW = 1,
parameter integer FF = 4,
parameter integer SS = 2,
parameter RI = 1,
parameter RO = 1
)(
input wire ffi_clk,
input wire ffi_rst,
input wire [DW-1:0] ffi_dat,
input wire ffi_vld,
output wire ffi_rdy,
input wire ffo_clk,
input wire ffo_rst,
output wor [DW-1:0] ffo_dat,
output wire ffo_vld,
input wire ffo_rdy
);
`ifdef XC3S250E
function integer clog2 (input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction
localparam CW = clog2(FF)+1;
`else
localparam CW = $clog2(FF)+1;
`endif
localparam G0 = {1'b1,{CW-1{1'b0}}};
function [CW-1:0] int2gry (input [CW-1:0] val);
integer i;
begin
for (i=0; i<CW-1; i=i+1) int2gry[i] = val[i+1] ^ val[i];
int2gry[CW-1] = val[CW-1];
end
endfunction
function [CW-1:0] gry2int (input [CW-1:0] val);
integer i;
begin
gry2int[CW-1] = val[CW-1];
for (i=CW-1; i>0; i=i-1) gry2int[i-1] = val[i-1] ^ gry2int[i];
end
endfunction
function [CW-1:0] gry_inc (input [CW-1:0] gry_gry);
begin
gry_inc = int2gry (gry2int (gry_gry) + 'd1);
end
endfunction
wire ffi_trn;
wire ffi_end;
reg [CW-1:0] ffi_ref;
reg [CW-1:0] ffi_gry;
reg [CW-1:0] ffi_syn [SS-1:0];
reg [DW-1:0] cdc_mem [0:FF-1];
wire ffo_trn;
wire ffo_end;
reg [CW-1:0] ffo_gry;
reg [CW-1:0] ffo_syn [SS-1:0];
genvar i;
assign ffi_trn = ffi_vld & ffi_rdy;
generate for (i=0; i<SS; i=i+1) begin : ffi_cdc
if (i==0) begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffo_gry;
end else begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffi_syn [i-1];
end
end endgenerate
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_gry <= {CW{1'b0}};
else if (ffi_trn) ffi_gry <= ffi_end ? ffi_gry ^ G0 : gry_inc (ffi_gry);
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_ref <= int2gry(-FF);
else if (ffi_trn) ffi_ref <= ffi_end ? ffi_ref ^ G0 : gry_inc (ffi_ref);
assign ffi_rdy = ffi_syn [SS-1] != ffi_ref;
reg [CW-2:0] ffi_cnt;
assign ffi_end = ffi_cnt == (FF-1);
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_cnt <= 'b0;
else if (ffi_trn) ffi_cnt <= ffi_end ? 'b0 : ffi_cnt + 'b1;
always @ (posedge ffi_clk)
if (ffi_trn) cdc_mem [ffi_cnt] <= ffi_dat;
reg [CW-2:0] ffo_cnt;
assign ffo_end = ffo_cnt == (FF-1);
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_cnt <= 'b0;
else if (ffo_trn) ffo_cnt <= ffo_end ? 'b0 : ffo_cnt + 'b1;
assign ffo_dat = cdc_mem [ffo_cnt];
assign ffo_trn = ffo_vld & ffo_rdy;
generate for (i=0; i<SS; i=i+1) begin : ffo_cdc
if (i==0) begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffi_gry;
end else begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffo_syn [i-1];
end
end endgenerate
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_gry <= {CW{1'b0}};
else if (ffo_trn) ffo_gry <= ffo_end ? ffo_gry ^ G0 : gry_inc (ffo_gry);
assign ffo_vld = ffo_syn [SS-1] != ffo_gry;
endmodule | module cdc #(
parameter integer DW = 1,
parameter integer FF = 4,
parameter integer SS = 2,
parameter RI = 1,
parameter RO = 1
)(
input wire ffi_clk,
input wire ffi_rst,
input wire [DW-1:0] ffi_dat,
input wire ffi_vld,
output wire ffi_rdy,
input wire ffo_clk,
input wire ffo_rst,
output wor [DW-1:0] ffo_dat,
output wire ffo_vld,
input wire ffo_rdy
); |
`ifdef XC3S250E
function integer clog2 (input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction
localparam CW = clog2(FF)+1;
`else
localparam CW = $clog2(FF)+1;
`endif
localparam G0 = {1'b1,{CW-1{1'b0}}};
function [CW-1:0] int2gry (input [CW-1:0] val);
integer i;
begin
for (i=0; i<CW-1; i=i+1) int2gry[i] = val[i+1] ^ val[i];
int2gry[CW-1] = val[CW-1];
end
endfunction
function [CW-1:0] gry2int (input [CW-1:0] val);
integer i;
begin
gry2int[CW-1] = val[CW-1];
for (i=CW-1; i>0; i=i-1) gry2int[i-1] = val[i-1] ^ gry2int[i];
end
endfunction
function [CW-1:0] gry_inc (input [CW-1:0] gry_gry);
begin
gry_inc = int2gry (gry2int (gry_gry) + 'd1);
end
endfunction
wire ffi_trn;
wire ffi_end;
reg [CW-1:0] ffi_ref;
reg [CW-1:0] ffi_gry;
reg [CW-1:0] ffi_syn [SS-1:0];
reg [DW-1:0] cdc_mem [0:FF-1];
wire ffo_trn;
wire ffo_end;
reg [CW-1:0] ffo_gry;
reg [CW-1:0] ffo_syn [SS-1:0];
genvar i;
assign ffi_trn = ffi_vld & ffi_rdy;
generate for (i=0; i<SS; i=i+1) begin : ffi_cdc
if (i==0) begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffo_gry;
end else begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffi_syn [i-1];
end
end endgenerate
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_gry <= {CW{1'b0}};
else if (ffi_trn) ffi_gry <= ffi_end ? ffi_gry ^ G0 : gry_inc (ffi_gry);
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_ref <= int2gry(-FF);
else if (ffi_trn) ffi_ref <= ffi_end ? ffi_ref ^ G0 : gry_inc (ffi_ref);
assign ffi_rdy = ffi_syn [SS-1] != ffi_ref;
reg [CW-2:0] ffi_cnt;
assign ffi_end = ffi_cnt == (FF-1);
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_cnt <= 'b0;
else if (ffi_trn) ffi_cnt <= ffi_end ? 'b0 : ffi_cnt + 'b1;
always @ (posedge ffi_clk)
if (ffi_trn) cdc_mem [ffi_cnt] <= ffi_dat;
reg [CW-2:0] ffo_cnt;
assign ffo_end = ffo_cnt == (FF-1);
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_cnt <= 'b0;
else if (ffo_trn) ffo_cnt <= ffo_end ? 'b0 : ffo_cnt + 'b1;
assign ffo_dat = cdc_mem [ffo_cnt];
assign ffo_trn = ffo_vld & ffo_rdy;
generate for (i=0; i<SS; i=i+1) begin : ffo_cdc
if (i==0) begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffi_gry;
end else begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffo_syn [i-1];
end
end endgenerate
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_gry <= {CW{1'b0}};
else if (ffo_trn) ffo_gry <= ffo_end ? ffo_gry ^ G0 : gry_inc (ffo_gry);
assign ffo_vld = ffo_syn [SS-1] != ffo_gry;
endmodule | 6 |
142,022 | data/full_repos/permissive/9699476/rtl/cdc.v | 9,699,476 | cdc.v | v | 233 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:59: before: "[" | null | 1: b'%Error: data/full_repos/permissive/9699476/rtl/cdc.v:59: Unsupported: wor\n output wor [DW-1:0] ffo_dat, \n ^~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,978 | function | function integer clog2 (input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction | function integer clog2 (input integer value); | begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction | 6 |
142,023 | data/full_repos/permissive/9699476/rtl/cdc.v | 9,699,476 | cdc.v | v | 233 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:59: before: "[" | null | 1: b'%Error: data/full_repos/permissive/9699476/rtl/cdc.v:59: Unsupported: wor\n output wor [DW-1:0] ffo_dat, \n ^~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,978 | function | function [CW-1:0] int2gry (input [CW-1:0] val);
integer i;
begin
for (i=0; i<CW-1; i=i+1) int2gry[i] = val[i+1] ^ val[i];
int2gry[CW-1] = val[CW-1];
end
endfunction | function [CW-1:0] int2gry (input [CW-1:0] val); |
integer i;
begin
for (i=0; i<CW-1; i=i+1) int2gry[i] = val[i+1] ^ val[i];
int2gry[CW-1] = val[CW-1];
end
endfunction | 6 |
142,024 | data/full_repos/permissive/9699476/rtl/cdc.v | 9,699,476 | cdc.v | v | 233 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:59: before: "[" | null | 1: b'%Error: data/full_repos/permissive/9699476/rtl/cdc.v:59: Unsupported: wor\n output wor [DW-1:0] ffo_dat, \n ^~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,978 | function | function [CW-1:0] gry2int (input [CW-1:0] val);
integer i;
begin
gry2int[CW-1] = val[CW-1];
for (i=CW-1; i>0; i=i-1) gry2int[i-1] = val[i-1] ^ gry2int[i];
end
endfunction | function [CW-1:0] gry2int (input [CW-1:0] val); |
integer i;
begin
gry2int[CW-1] = val[CW-1];
for (i=CW-1; i>0; i=i-1) gry2int[i-1] = val[i-1] ^ gry2int[i];
end
endfunction | 6 |
142,025 | data/full_repos/permissive/9699476/rtl/cdc.v | 9,699,476 | cdc.v | v | 233 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:59: before: "[" | null | 1: b'%Error: data/full_repos/permissive/9699476/rtl/cdc.v:59: Unsupported: wor\n output wor [DW-1:0] ffo_dat, \n ^~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,978 | function | function [CW-1:0] gry_inc (input [CW-1:0] gry_gry);
begin
gry_inc = int2gry (gry2int (gry_gry) + 'd1);
end
endfunction | function [CW-1:0] gry_inc (input [CW-1:0] gry_gry); |
begin
gry_inc = int2gry (gry2int (gry_gry) + 'd1);
end
endfunction | 6 |
142,026 | data/full_repos/permissive/9699476/rtl/core.v | 9,699,476 | core.v | v | 421 | 116 | [] | ['general public license', 'free software foundation'] | [] | [(40, 419)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/9699476/rtl/core.v:142: Signal definition not found, creating implicitly: \'sampled_extTriggerIn\'\nassign run = run_basic | run_adv | sampled_extTriggerIn;\n ^~~~~~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/9699476/rtl/core.v:319: Signal definition not found, creating implicitly: \'capture_basic\'\n : ... Suggested alternative: \'arm_basic\'\nwire capture = capture_basic || capture_adv;\n ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/9699476/rtl/core.v:319: Signal definition not found, creating implicitly: \'capture_adv\'\n : ... Suggested alternative: \'capture\'\nwire capture = capture_basic || capture_adv;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:115: Cannot find file containing module: \'reset_sync\'\nreset_sync reset_sync_core (sys_clk, reset , reset_core ); \n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/reset_sync\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/reset_sync.v\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/reset_sync.sv\n reset_sync\n reset_sync.v\n reset_sync.sv\n obj_dir/reset_sync\n obj_dir/reset_sync.v\n obj_dir/reset_sync.sv\n%Error: data/full_repos/permissive/9699476/rtl/core.v:116: Cannot find file containing module: \'reset_sync\'\nreset_sync reset_sync_sample (sti_clk, reset_core, sti_rst);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:139: Cannot find file containing module: \'dly_signal\'\ndly_signal extTriggerIn_reg (sys_clk, extTriggerIn, sampled_extTriggerIn);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:140: Cannot find file containing module: \'dly_signal\'\ndly_signal extTriggerOut_reg (sys_clk, run, extTriggerOut);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:171: Cannot find file containing module: \'decoder\'\ndecoder decoder(\n^~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:193: Cannot find file containing module: \'flags\'\nflags flags(\n^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:205: Cannot find file containing module: \'sync\'\nsync #(\n^~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:228: Cannot find file containing module: \'cdc\'\ncdc #(\n^~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:252: Cannot find file containing module: \'sampler\'\nsampler #(\n^~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:275: Cannot find file containing module: \'trigger\'\ntrigger #(\n^~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:299: Cannot find file containing module: \'trigger_adv\'\ntrigger_adv #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:324: Cannot find file containing module: \'delay_fifo\'\ndelay_fifo #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:342: Cannot find file containing module: \'data_align\'\ndata_align data_align (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:360: Cannot find file containing module: \'rle_enc\'\nrle_enc rle_enc (\n^~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:381: Cannot find file containing module: \'pipeline_stall\'\npipeline_stall #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:390: Cannot find file containing module: \'pipeline_stall\'\npipeline_stall #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/core.v:401: Cannot find file containing module: \'controller\'\ncontroller controller(\n^~~~~~~~~~\n%Error: Exiting due to 17 error(s), 3 warning(s)\n' | 312,980 | module | module core #(
parameter integer SDW = 32,
parameter integer MDW = 32
)(
input wire sys_clk,
input wire sys_rst,
input wire [7:0] opcode,
input wire [31:0] config_data,
input wire execute,
input wire outputBusy,
input wire extTriggerIn,
output wire sampleReady50,
output wire outputSend,
output wire extTriggerOut,
output reg armLEDnn,
output reg triggerLEDnn,
output wire wrFlags,
output wire extClock_mode,
output wire extTestMode,
input wire sti_clk,
input wire [SDW-1:0] sti_data_p,
input wire [SDW-1:0] sti_data_n,
output wire [SDW-1:0] stableInput,
output wire [MDW-1:0] memoryWrData,
output wire memoryRead,
output wire memoryWrite,
output wire memoryLastWrite
);
wire sync_valid;
wire [SDW-1:0] sync_data;
wire sync_ready;
wire cdc_valid;
wire [SDW-1:0] cdc_data;
wire cdc_ready;
wire sample_valid;
wire [SDW-1:0] sample_data;
wire delay_valid;
wire [SDW-1:0] delay_data;
wire align_valid;
wire [SDW-1:0] align_data;
wire rle_valid;
wire [SDW-1:0] rle_data;
wire [3:0] wrtrigmask;
wire [3:0] wrtrigval;
wire [3:0] wrtrigcfg;
wire wrDivider;
wire wrsize;
wire arm_basic, arm_adv;
wire arm = arm_basic | arm_adv;
wire reset_core;
wire sti_rst;
wire resetCmd;
wire reset = sys_rst | resetCmd;
reset_sync reset_sync_core (sys_clk, reset , reset_core );
reset_sync reset_sync_sample (sti_clk, reset_core, sti_rst);
wire [31:0] flags_reg;
wire demux_mode = flags_reg[0];
wire filter_mode = flags_reg[1];
wire [3:0] disabledGroups = flags_reg[5:2];
assign extClock_mode = flags_reg[6];
wire falling_edge = flags_reg[7];
wire rleEnable = flags_reg[8];
wire numberScheme = flags_reg[9];
assign extTestMode = flags_reg[10] && !numberScheme;
wire intTestMode = flags_reg[11];
wire [1:0] rle_mode = flags_reg[15:14];
wire run_basic, run_adv, run;
dly_signal extTriggerIn_reg (sys_clk, extTriggerIn, sampled_extTriggerIn);
dly_signal extTriggerOut_reg (sys_clk, run, extTriggerOut);
assign run = run_basic | run_adv | sampled_extTriggerIn;
`ifdef HEARTBEAT
reg [31:0] hcount;
initial hcount=0;
always @ (posedge sys_clk)
hcount <= (~|hcount) ? 100000000 : (hcount-1'b1);
always @ (posedge sys_clk)
if (~|hcount) armLEDnn <= !armLEDnn;
`else
always @ (posedge sys_clk)
if (arm) armLEDnn <= ~1'b1;
else if (run) armLEDnn <= ~1'b0;
`endif
always @(posedge sys_clk)
if (run) triggerLEDnn <= ~1'b1;
else if (arm) triggerLEDnn <= ~1'b0;
decoder decoder(
.clock (sys_clk),
.execute (execute),
.opcode (opcode),
.wrtrigmask (wrtrigmask),
.wrtrigval (wrtrigval),
.wrtrigcfg (wrtrigcfg),
.wrspeed (wrDivider),
.wrsize (wrsize),
.wrFlags (wrFlags),
.wrTrigSelect (wrTrigSelect),
.wrTrigChain (wrTrigChain),
.finish_now (finish_now),
.arm_basic (arm_basic),
.arm_adv (arm_adv),
.resetCmd (resetCmd)
);
flags flags(
.clock (sys_clk),
.wrFlags (wrFlags),
.config_data (config_data),
.finish_now (finish_now),
.flags_reg (flags_reg)
);
sync #(
.DW (SDW)
) sync (
.intTestMode (intTestMode),
.numberScheme (numberScheme),
.filter_mode (filter_mode),
.demux_mode (demux_mode),
.falling_edge (falling_edge),
.sti_clk (sti_clk),
.sti_rst (sti_rst),
.sti_data_p (sti_data_p),
.sti_data_n (sti_data_n),
.sto_data (sync_data),
.sto_valid (sync_valid)
);
cdc #(
.DW (SDW),
.FF (8)
) cdc (
.ffi_clk (sti_clk),
.ffi_rst (sti_rst),
.ffi_dat (sync_data),
.ffi_vld (sync_valid),
.ffi_rdy (sync_ready),
.ffo_clk (sys_clk),
.ffo_rst (reset_core),
.ffo_dat (cdc_data),
.ffo_vld (cdc_valid),
.ffo_rdy (cdc_ready)
);
assign cdc_ready = 1'b1;
assign stableInput = cdc_data;
sampler #(
.DW (SDW)
) sampler (
.clk (sys_clk),
.rst (reset_core),
.extClock_mode (extClock_mode),
.wrDivider (wrDivider),
.config_data (config_data[23:0]),
.sti_valid (cdc_valid),
.sti_data (cdc_data ),
.sto_valid (sample_valid),
.sto_data (sample_data ),
.ready50 (sampleReady50)
);
trigger #(
.DW (SDW)
) trigger (
.clk (sys_clk),
.rst (reset_core),
.wrMask (wrtrigmask),
.wrValue (wrtrigval),
.wrConfig (wrtrigcfg),
.config_data (config_data),
.arm (arm_basic),
.demux_mode (demux_mode),
.sti_valid (sample_valid),
.sti_data (sample_data),
.run (run_basic),
.capture (capture_basic)
);
trigger_adv #(
.DW (SDW)
) trigger_adv (
.clk (sys_clk),
.rst (reset_core),
.wrSelect (wrTrigSelect),
.wrChain (wrTrigChain),
.config_data (config_data),
.arm (arm_adv),
.finish_now (finish_now),
.sti_valid (sample_valid),
.sti_data (sample_data),
.run (run_adv),
.capture (capture_adv)
);
wire capture = capture_basic || capture_adv;
delay_fifo #(
.DLY (3),
.DW (SDW)
) delay_fifo (
.clk (sys_clk),
.rst (reset_core),
.sti_valid (sample_valid),
.sti_data (sample_data),
.sto_valid (delay_valid),
.sto_data (delay_data)
);
data_align data_align (
.clk (sys_clk),
.rst (reset_core),
.disabledGroups (disabledGroups),
.sti_valid (delay_valid && capture),
.sti_data (delay_data),
.sto_valid (align_valid),
.sto_data (align_data)
);
rle_enc rle_enc (
.clk (sys_clk),
.rst (reset_core),
.enable (rleEnable),
.arm (arm),
.rle_mode (rle_mode),
.disabledGroups (disabledGroups),
.sti_valid (align_valid),
.sti_data (align_data),
.sto_valid (rle_valid),
.sto_data (rle_data)
);
pipeline_stall #(
.DELAY (2)
) dly_arm_reg (
.clk (sys_clk),
.reset (reset_core),
.datain (arm),
.dataout (dly_arm)
);
pipeline_stall #(
.DELAY (1)
) dly_run_reg (
.clk (sys_clk),
.reset (reset_core),
.datain (run),
.dataout (dly_run));
controller controller(
.clock (sys_clk),
.reset (reset_core),
.run (dly_run),
.wrSize (wrsize),
.config_data (config_data),
.arm (dly_arm),
.busy (outputBusy),
.validIn (rle_valid),
.dataIn (rle_data),
.send (outputSend),
.memoryWrData (memoryWrData),
.memoryRead (memoryRead),
.memoryWrite (memoryWrite),
.memoryLastWrite (memoryLastWrite));
endmodule | module core #(
parameter integer SDW = 32,
parameter integer MDW = 32
)(
input wire sys_clk,
input wire sys_rst,
input wire [7:0] opcode,
input wire [31:0] config_data,
input wire execute,
input wire outputBusy,
input wire extTriggerIn,
output wire sampleReady50,
output wire outputSend,
output wire extTriggerOut,
output reg armLEDnn,
output reg triggerLEDnn,
output wire wrFlags,
output wire extClock_mode,
output wire extTestMode,
input wire sti_clk,
input wire [SDW-1:0] sti_data_p,
input wire [SDW-1:0] sti_data_n,
output wire [SDW-1:0] stableInput,
output wire [MDW-1:0] memoryWrData,
output wire memoryRead,
output wire memoryWrite,
output wire memoryLastWrite
); |
wire sync_valid;
wire [SDW-1:0] sync_data;
wire sync_ready;
wire cdc_valid;
wire [SDW-1:0] cdc_data;
wire cdc_ready;
wire sample_valid;
wire [SDW-1:0] sample_data;
wire delay_valid;
wire [SDW-1:0] delay_data;
wire align_valid;
wire [SDW-1:0] align_data;
wire rle_valid;
wire [SDW-1:0] rle_data;
wire [3:0] wrtrigmask;
wire [3:0] wrtrigval;
wire [3:0] wrtrigcfg;
wire wrDivider;
wire wrsize;
wire arm_basic, arm_adv;
wire arm = arm_basic | arm_adv;
wire reset_core;
wire sti_rst;
wire resetCmd;
wire reset = sys_rst | resetCmd;
reset_sync reset_sync_core (sys_clk, reset , reset_core );
reset_sync reset_sync_sample (sti_clk, reset_core, sti_rst);
wire [31:0] flags_reg;
wire demux_mode = flags_reg[0];
wire filter_mode = flags_reg[1];
wire [3:0] disabledGroups = flags_reg[5:2];
assign extClock_mode = flags_reg[6];
wire falling_edge = flags_reg[7];
wire rleEnable = flags_reg[8];
wire numberScheme = flags_reg[9];
assign extTestMode = flags_reg[10] && !numberScheme;
wire intTestMode = flags_reg[11];
wire [1:0] rle_mode = flags_reg[15:14];
wire run_basic, run_adv, run;
dly_signal extTriggerIn_reg (sys_clk, extTriggerIn, sampled_extTriggerIn);
dly_signal extTriggerOut_reg (sys_clk, run, extTriggerOut);
assign run = run_basic | run_adv | sampled_extTriggerIn;
`ifdef HEARTBEAT
reg [31:0] hcount;
initial hcount=0;
always @ (posedge sys_clk)
hcount <= (~|hcount) ? 100000000 : (hcount-1'b1);
always @ (posedge sys_clk)
if (~|hcount) armLEDnn <= !armLEDnn;
`else
always @ (posedge sys_clk)
if (arm) armLEDnn <= ~1'b1;
else if (run) armLEDnn <= ~1'b0;
`endif
always @(posedge sys_clk)
if (run) triggerLEDnn <= ~1'b1;
else if (arm) triggerLEDnn <= ~1'b0;
decoder decoder(
.clock (sys_clk),
.execute (execute),
.opcode (opcode),
.wrtrigmask (wrtrigmask),
.wrtrigval (wrtrigval),
.wrtrigcfg (wrtrigcfg),
.wrspeed (wrDivider),
.wrsize (wrsize),
.wrFlags (wrFlags),
.wrTrigSelect (wrTrigSelect),
.wrTrigChain (wrTrigChain),
.finish_now (finish_now),
.arm_basic (arm_basic),
.arm_adv (arm_adv),
.resetCmd (resetCmd)
);
flags flags(
.clock (sys_clk),
.wrFlags (wrFlags),
.config_data (config_data),
.finish_now (finish_now),
.flags_reg (flags_reg)
);
sync #(
.DW (SDW)
) sync (
.intTestMode (intTestMode),
.numberScheme (numberScheme),
.filter_mode (filter_mode),
.demux_mode (demux_mode),
.falling_edge (falling_edge),
.sti_clk (sti_clk),
.sti_rst (sti_rst),
.sti_data_p (sti_data_p),
.sti_data_n (sti_data_n),
.sto_data (sync_data),
.sto_valid (sync_valid)
);
cdc #(
.DW (SDW),
.FF (8)
) cdc (
.ffi_clk (sti_clk),
.ffi_rst (sti_rst),
.ffi_dat (sync_data),
.ffi_vld (sync_valid),
.ffi_rdy (sync_ready),
.ffo_clk (sys_clk),
.ffo_rst (reset_core),
.ffo_dat (cdc_data),
.ffo_vld (cdc_valid),
.ffo_rdy (cdc_ready)
);
assign cdc_ready = 1'b1;
assign stableInput = cdc_data;
sampler #(
.DW (SDW)
) sampler (
.clk (sys_clk),
.rst (reset_core),
.extClock_mode (extClock_mode),
.wrDivider (wrDivider),
.config_data (config_data[23:0]),
.sti_valid (cdc_valid),
.sti_data (cdc_data ),
.sto_valid (sample_valid),
.sto_data (sample_data ),
.ready50 (sampleReady50)
);
trigger #(
.DW (SDW)
) trigger (
.clk (sys_clk),
.rst (reset_core),
.wrMask (wrtrigmask),
.wrValue (wrtrigval),
.wrConfig (wrtrigcfg),
.config_data (config_data),
.arm (arm_basic),
.demux_mode (demux_mode),
.sti_valid (sample_valid),
.sti_data (sample_data),
.run (run_basic),
.capture (capture_basic)
);
trigger_adv #(
.DW (SDW)
) trigger_adv (
.clk (sys_clk),
.rst (reset_core),
.wrSelect (wrTrigSelect),
.wrChain (wrTrigChain),
.config_data (config_data),
.arm (arm_adv),
.finish_now (finish_now),
.sti_valid (sample_valid),
.sti_data (sample_data),
.run (run_adv),
.capture (capture_adv)
);
wire capture = capture_basic || capture_adv;
delay_fifo #(
.DLY (3),
.DW (SDW)
) delay_fifo (
.clk (sys_clk),
.rst (reset_core),
.sti_valid (sample_valid),
.sti_data (sample_data),
.sto_valid (delay_valid),
.sto_data (delay_data)
);
data_align data_align (
.clk (sys_clk),
.rst (reset_core),
.disabledGroups (disabledGroups),
.sti_valid (delay_valid && capture),
.sti_data (delay_data),
.sto_valid (align_valid),
.sto_data (align_data)
);
rle_enc rle_enc (
.clk (sys_clk),
.rst (reset_core),
.enable (rleEnable),
.arm (arm),
.rle_mode (rle_mode),
.disabledGroups (disabledGroups),
.sti_valid (align_valid),
.sti_data (align_data),
.sto_valid (rle_valid),
.sto_data (rle_data)
);
pipeline_stall #(
.DELAY (2)
) dly_arm_reg (
.clk (sys_clk),
.reset (reset_core),
.datain (arm),
.dataout (dly_arm)
);
pipeline_stall #(
.DELAY (1)
) dly_run_reg (
.clk (sys_clk),
.reset (reset_core),
.datain (run),
.dataout (dly_run));
controller controller(
.clock (sys_clk),
.reset (reset_core),
.run (dly_run),
.wrSize (wrsize),
.config_data (config_data),
.arm (dly_arm),
.busy (outputBusy),
.validIn (rle_valid),
.dataIn (rle_data),
.send (outputSend),
.memoryWrData (memoryWrData),
.memoryRead (memoryRead),
.memoryWrite (memoryWrite),
.memoryLastWrite (memoryLastWrite));
endmodule | 6 |
142,027 | data/full_repos/permissive/9699476/rtl/data_align.v | 9,699,476 | data_align.v | v | 131 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(42, 130)] | null | data/verilator_xmls/dab64b94-53df-4c44-8cdd-d27d2f86736a.xml | null | 312,981 | module | module data_align #(
parameter integer DW = 32,
parameter integer KW = DW/8
)(
input wire clk,
input wire rst,
input wire [3:0] disabledGroups,
input wire sti_valid,
input wire [31:0] sti_data,
output reg sto_valid,
output reg [31:0] sto_data
);
reg [1:0] insel0;
reg [1:0] insel1;
reg insel2;
always @ (posedge clk)
begin
case (insel0[1:0])
2'h3 : sto_data[ 7: 0] <= sti_data[31:24];
2'h2 : sto_data[ 7: 0] <= sti_data[23:16];
2'h1 : sto_data[ 7: 0] <= sti_data[15: 8];
default : sto_data[ 7: 0] <= sti_data[ 7: 0];
endcase
case (insel1[1:0])
2'h2 : sto_data[15: 8] <= sti_data[31:24];
2'h1 : sto_data[15: 8] <= sti_data[23:16];
default : sto_data[15: 8] <= sti_data[15: 8];
endcase
case (insel2)
1'b1 : sto_data[23:16] <= sti_data[31:24];
default : sto_data[23:16] <= sti_data[23:16];
endcase
sto_data[31:24] <= sti_data[31:24];
end
always @(posedge clk)
begin
case (disabledGroups)
4'b0001 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0010 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b0100 : begin insel2 <= 1'b1; insel1 <= 2'h0; insel0 <= 2'h0; end
4'b0011 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h2; end
4'b0101 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h1; end
4'b1001 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0110 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h0; end
4'b1010 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b1100 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
4'b0111 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h3; end
4'b1011 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h2; end
4'b1101 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h1; end
default : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
endcase
end
always @(posedge clk, posedge rst)
if (rst) sto_valid <= 1'b0;
else sto_valid <= sti_valid;
endmodule | module data_align #(
parameter integer DW = 32,
parameter integer KW = DW/8
)(
input wire clk,
input wire rst,
input wire [3:0] disabledGroups,
input wire sti_valid,
input wire [31:0] sti_data,
output reg sto_valid,
output reg [31:0] sto_data
); |
reg [1:0] insel0;
reg [1:0] insel1;
reg insel2;
always @ (posedge clk)
begin
case (insel0[1:0])
2'h3 : sto_data[ 7: 0] <= sti_data[31:24];
2'h2 : sto_data[ 7: 0] <= sti_data[23:16];
2'h1 : sto_data[ 7: 0] <= sti_data[15: 8];
default : sto_data[ 7: 0] <= sti_data[ 7: 0];
endcase
case (insel1[1:0])
2'h2 : sto_data[15: 8] <= sti_data[31:24];
2'h1 : sto_data[15: 8] <= sti_data[23:16];
default : sto_data[15: 8] <= sti_data[15: 8];
endcase
case (insel2)
1'b1 : sto_data[23:16] <= sti_data[31:24];
default : sto_data[23:16] <= sti_data[23:16];
endcase
sto_data[31:24] <= sti_data[31:24];
end
always @(posedge clk)
begin
case (disabledGroups)
4'b0001 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0010 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b0100 : begin insel2 <= 1'b1; insel1 <= 2'h0; insel0 <= 2'h0; end
4'b0011 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h2; end
4'b0101 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h1; end
4'b1001 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0110 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h0; end
4'b1010 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b1100 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
4'b0111 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h3; end
4'b1011 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h2; end
4'b1101 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h1; end
default : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
endcase
end
always @(posedge clk, posedge rst)
if (rst) sto_valid <= 1'b0;
else sto_valid <= sti_valid;
endmodule | 6 |
142,031 | data/full_repos/permissive/9699476/rtl/flags.v | 9,699,476 | flags.v | v | 57 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(33, 55)] | null | data/verilator_xmls/fb721e22-0871-404c-82ac-49672bf70446.xml | null | 312,985 | module | module flags (
input wire clock,
input wire wrFlags,
input wire [31:0] config_data,
input wire finish_now,
output reg [31:0] flags_reg
);
reg [31:0] next_flags_reg;
initial flags_reg = 0;
always @(posedge clock)
flags_reg <= next_flags_reg;
always @*
begin
next_flags_reg = (wrFlags) ? config_data : flags_reg;
if (finish_now) next_flags_reg[8] = 1'b0;
end
endmodule | module flags (
input wire clock,
input wire wrFlags,
input wire [31:0] config_data,
input wire finish_now,
output reg [31:0] flags_reg
); |
reg [31:0] next_flags_reg;
initial flags_reg = 0;
always @(posedge clock)
flags_reg <= next_flags_reg;
always @*
begin
next_flags_reg = (wrFlags) ? config_data : flags_reg;
if (finish_now) next_flags_reg[8] = 1'b0;
end
endmodule | 6 |
142,033 | data/full_repos/permissive/9699476/rtl/meta.v | 9,699,476 | meta.v | v | 131 | 128 | [] | ['general public license', 'free software foundation'] | [] | [(31, 130)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/meta.v:78: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n : ... In instance meta_handler\n METADATA_LEN = i;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/meta.v:94: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance meta_handler\n metasel <= 3\'h0;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 312,987 | module | module meta_handler (
input wire clock,
input wire extReset,
input wire query_metadata,
input wire xmit_idle,
output reg writeMeta,
output wire [7:0] meta_data
);
reg [5:0] metasel, next_metasel;
`define ADDBYTE(cmd) meta_rom[i]=cmd; i=i+1
`define ADDSHORT(cmd,b0) meta_rom[i]=cmd; meta_rom[i+1]=b0; i=i+2
`define ADDLONG(cmd,b0,b1,b2,b3) meta_rom[i]=cmd; meta_rom[i+1]=b0; meta_rom[i+2]=b1; meta_rom[i+3]=b2; meta_rom[i+4]=b3; i=i+5
reg [5:0] METADATA_LEN;
reg [7:0] meta_rom[63:0];
assign meta_data = meta_rom[metasel];
initial
begin : meta
integer i;
i=0;
`ADDLONG(8'h01, "O", "p", "e", "n");
`ADDLONG(" ", "L", "o", "g", "i");
`ADDLONG("c", " ", "S", "n", "i");
`ADDLONG("f", "f", "e", "r", " ");
`ADDLONG("v", "1", ".", "0", "1");
`ADDBYTE(0);
`ADDLONG(8'h02, "3", ".", "0", "7");
`ADDBYTE(0);
`ADDLONG(8'h21,8'h00,8'h00,8'h60,8'h00);
`ADDLONG(8'h23,8'h0B,8'hEB,8'hC2,8'h00);
`ADDSHORT(8'h40,8'h20);
`ADDSHORT(8'h41,8'h02);
`ADDBYTE(0);
METADATA_LEN = i;
for (i=i; i<64; i=i+1) meta_rom[i]=0;
end
parameter [1:0] IDLE = 0, METASEND = 1, METAPOLL = 2;
reg [1:0] state, next_state;
initial state = IDLE;
always @(posedge clock, posedge extReset)
if (extReset) begin
state <= IDLE;
metasel <= 3'h0;
end else begin
state <= next_state;
metasel <= next_metasel;
end
always @*
begin
next_state = state;
next_metasel = metasel;
writeMeta = 1'b0;
case (state)
IDLE :
begin
next_metasel = 0;
next_state = (query_metadata && xmit_idle) ? METASEND : IDLE;
end
METASEND :
begin
writeMeta = 1'b1;
next_metasel = metasel+1'b1;
next_state = METAPOLL;
end
METAPOLL :
begin
if (xmit_idle)
next_state = (metasel==METADATA_LEN) ? IDLE : METASEND;
end
default : next_state = IDLE;
endcase
end
endmodule | module meta_handler (
input wire clock,
input wire extReset,
input wire query_metadata,
input wire xmit_idle,
output reg writeMeta,
output wire [7:0] meta_data
); |
reg [5:0] metasel, next_metasel;
`define ADDBYTE(cmd) meta_rom[i]=cmd; i=i+1
`define ADDSHORT(cmd,b0) meta_rom[i]=cmd; meta_rom[i+1]=b0; i=i+2
`define ADDLONG(cmd,b0,b1,b2,b3) meta_rom[i]=cmd; meta_rom[i+1]=b0; meta_rom[i+2]=b1; meta_rom[i+3]=b2; meta_rom[i+4]=b3; i=i+5
reg [5:0] METADATA_LEN;
reg [7:0] meta_rom[63:0];
assign meta_data = meta_rom[metasel];
initial
begin : meta
integer i;
i=0;
`ADDLONG(8'h01, "O", "p", "e", "n");
`ADDLONG(" ", "L", "o", "g", "i");
`ADDLONG("c", " ", "S", "n", "i");
`ADDLONG("f", "f", "e", "r", " ");
`ADDLONG("v", "1", ".", "0", "1");
`ADDBYTE(0);
`ADDLONG(8'h02, "3", ".", "0", "7");
`ADDBYTE(0);
`ADDLONG(8'h21,8'h00,8'h00,8'h60,8'h00);
`ADDLONG(8'h23,8'h0B,8'hEB,8'hC2,8'h00);
`ADDSHORT(8'h40,8'h20);
`ADDSHORT(8'h41,8'h02);
`ADDBYTE(0);
METADATA_LEN = i;
for (i=i; i<64; i=i+1) meta_rom[i]=0;
end
parameter [1:0] IDLE = 0, METASEND = 1, METAPOLL = 2;
reg [1:0] state, next_state;
initial state = IDLE;
always @(posedge clock, posedge extReset)
if (extReset) begin
state <= IDLE;
metasel <= 3'h0;
end else begin
state <= next_state;
metasel <= next_metasel;
end
always @*
begin
next_state = state;
next_metasel = metasel;
writeMeta = 1'b0;
case (state)
IDLE :
begin
next_metasel = 0;
next_state = (query_metadata && xmit_idle) ? METASEND : IDLE;
end
METASEND :
begin
writeMeta = 1'b1;
next_metasel = metasel+1'b1;
next_state = METAPOLL;
end
METAPOLL :
begin
if (xmit_idle)
next_state = (metasel==METADATA_LEN) ? IDLE : METASEND;
end
default : next_state = IDLE;
endcase
end
endmodule | 6 |
142,034 | data/full_repos/permissive/9699476/rtl/prescaler.v | 9,699,476 | prescaler.v | v | 70 | 83 | [] | ['general public license', 'free software foundation'] | [] | null | line:33: before: ";" | null | 1: b"%Error: data/full_repos/permissive/9699476/rtl/prescaler.v:33: syntax error, unexpected ';', expecting ')' or ','\n input wire clock;\n ^\n%Error: data/full_repos/permissive/9699476/rtl/prescaler.v:35: syntax error, unexpected input\n input wire [1:0] div;\n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/prescaler.v:36: syntax error, unexpected output\n output reg scaled;\n ^~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/prescaler.v:37: syntax error, unexpected ')'\n);\n^\n%Error: Exiting due to 4 error(s)\n" | 312,988 | module | module prescaler #(
parameter [31:0] SCALE = 28
)(
input wire clock;
input wire reset;
input wire [1:0] div;
output reg scaled;
);
always @ (*)
scaled = 1'b1;
endmodule | module prescaler #(
parameter [31:0] SCALE = 28
)(
input wire clock; |
input wire reset;
input wire [1:0] div;
output reg scaled;
);
always @ (*)
scaled = 1'b1;
endmodule | 6 |
142,035 | data/full_repos/permissive/9699476/rtl/regs.v | 9,699,476 | regs.v | v | 66 | 66 | [] | [] | [] | [(4, 12), (17, 31), (38, 47), (52, 65)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9699476/rtl/regs.v:38: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dly_signal\'\nmodule dly_signal #(\n ^~~~~~~~~~\n : ... Top module \'full_synchronizer\'\nmodule full_synchronizer #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_sync\'\nmodule reset_sync (\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:30: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n : ... In instance full_synchronizer.sync\n else dly_datain <= {dly_datain, datain};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance reset_sync\nelse reset_reg <= {reset_reg,1\'b0};\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,990 | module | module dly_signal #(
parameter WIDTH = 1
)(
input wire clk,
input wire [WIDTH-1:0] indata,
output reg [WIDTH-1:0] outdata
);
always @(posedge clk) outdata <= indata;
endmodule | module dly_signal #(
parameter WIDTH = 1
)(
input wire clk,
input wire [WIDTH-1:0] indata,
output reg [WIDTH-1:0] outdata
); |
always @(posedge clk) outdata <= indata;
endmodule | 6 |
142,036 | data/full_repos/permissive/9699476/rtl/regs.v | 9,699,476 | regs.v | v | 66 | 66 | [] | [] | [] | [(4, 12), (17, 31), (38, 47), (52, 65)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9699476/rtl/regs.v:38: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dly_signal\'\nmodule dly_signal #(\n ^~~~~~~~~~\n : ... Top module \'full_synchronizer\'\nmodule full_synchronizer #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_sync\'\nmodule reset_sync (\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:30: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n : ... In instance full_synchronizer.sync\n else dly_datain <= {dly_datain, datain};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance reset_sync\nelse reset_reg <= {reset_reg,1\'b0};\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,990 | module | module pipeline_stall #(
parameter WIDTH = 1,
parameter DELAY = 1
)(
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
);
reg [(WIDTH*DELAY)-1:0] dly_datain = 0;
assign dataout = dly_datain[(WIDTH*DELAY)-1 : WIDTH*(DELAY-1)];
always @ (posedge clk, posedge reset)
if (reset) dly_datain <= 0;
else dly_datain <= {dly_datain, datain};
endmodule | module pipeline_stall #(
parameter WIDTH = 1,
parameter DELAY = 1
)(
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
); |
reg [(WIDTH*DELAY)-1:0] dly_datain = 0;
assign dataout = dly_datain[(WIDTH*DELAY)-1 : WIDTH*(DELAY-1)];
always @ (posedge clk, posedge reset)
if (reset) dly_datain <= 0;
else dly_datain <= {dly_datain, datain};
endmodule | 6 |
142,037 | data/full_repos/permissive/9699476/rtl/regs.v | 9,699,476 | regs.v | v | 66 | 66 | [] | [] | [] | [(4, 12), (17, 31), (38, 47), (52, 65)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9699476/rtl/regs.v:38: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dly_signal\'\nmodule dly_signal #(\n ^~~~~~~~~~\n : ... Top module \'full_synchronizer\'\nmodule full_synchronizer #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_sync\'\nmodule reset_sync (\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:30: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n : ... In instance full_synchronizer.sync\n else dly_datain <= {dly_datain, datain};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance reset_sync\nelse reset_reg <= {reset_reg,1\'b0};\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,990 | module | module full_synchronizer #(
parameter WIDTH = 1
)(
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
);
pipeline_stall #(WIDTH,2) sync (clk, reset, datain, dataout);
endmodule | module full_synchronizer #(
parameter WIDTH = 1
)(
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
); |
pipeline_stall #(WIDTH,2) sync (clk, reset, datain, dataout);
endmodule | 6 |
142,038 | data/full_repos/permissive/9699476/rtl/regs.v | 9,699,476 | regs.v | v | 66 | 66 | [] | [] | [] | [(4, 12), (17, 31), (38, 47), (52, 65)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9699476/rtl/regs.v:38: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dly_signal\'\nmodule dly_signal #(\n ^~~~~~~~~~\n : ... Top module \'full_synchronizer\'\nmodule full_synchronizer #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_sync\'\nmodule reset_sync (\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:30: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n : ... In instance full_synchronizer.sync\n else dly_datain <= {dly_datain, datain};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/regs.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance reset_sync\nelse reset_reg <= {reset_reg,1\'b0};\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,990 | module | module reset_sync (
input wire clk,
input wire hardreset,
output wire reset
);
reg [3:0] reset_reg = 4'hF;
assign reset = reset_reg[3];
always @ (posedge clk, posedge hardreset)
if (hardreset) reset_reg <= 4'hF;
else reset_reg <= {reset_reg,1'b0};
endmodule | module reset_sync (
input wire clk,
input wire hardreset,
output wire reset
); |
reg [3:0] reset_reg = 4'hF;
assign reset = reset_reg[3];
always @ (posedge clk, posedge hardreset)
if (hardreset) reset_reg <= 4'hF;
else reset_reg <= {reset_reg,1'b0};
endmodule | 6 |
142,040 | data/full_repos/permissive/9699476/rtl/sampler.v | 9,699,476 | sampler.v | v | 140 | 92 | [] | ['general public license', 'free software foundation'] | [] | [(43, 139)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/sampler.v:135: Operator EQ expects 24 bits on the RHS, but RHS\'s SEL generates 23 bits.\n : ... In instance sampler\n else if (counter == divider[CW-1:1])\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,992 | module | module sampler #(
parameter integer DW = 32,
parameter integer CW = 24
)(
input wire clk,
input wire rst,
input wire extClock_mode,
input wire wrDivider,
input wire [CW-1:0] config_data,
input wire sti_valid,
input wire [DW-1:0] sti_data,
output reg sto_valid,
output reg [DW-1:0] sto_data,
output reg ready50
);
reg next_sto_valid;
reg [DW-1:0] next_sto_data;
reg [CW-1:0] divider, next_divider;
reg [CW-1:0] counter, next_counter;
wire counter_zero = ~|counter;
initial
begin
divider = 0;
counter = 0;
sto_valid = 0;
sto_data = 0;
end
always @ (posedge clk)
begin
divider <= next_divider;
counter <= next_counter;
sto_valid <= next_sto_valid;
sto_data <= next_sto_data;
end
always @*
begin
next_divider = divider;
next_counter = counter;
next_sto_valid = 1'b0;
next_sto_data = sto_data;
if (extClock_mode)
begin
next_sto_valid = sti_valid;
next_sto_data = sti_data;
end
else if (sti_valid && counter_zero)
begin
next_sto_valid = 1'b1;
next_sto_data = sti_data;
end
if (wrDivider)
begin
next_divider = config_data[CW-1:0];
next_counter = next_divider;
next_sto_valid = 1'b0;
end
else if (sti_valid)
if (counter_zero)
next_counter = divider;
else next_counter = counter-1'b1;
end
always @(posedge clk)
begin
if (wrDivider)
ready50 <= 1'b0;
else if (counter_zero)
ready50 <= 1'b1;
else if (counter == divider[CW-1:1])
ready50 <= 1'b0;
end
endmodule | module sampler #(
parameter integer DW = 32,
parameter integer CW = 24
)(
input wire clk,
input wire rst,
input wire extClock_mode,
input wire wrDivider,
input wire [CW-1:0] config_data,
input wire sti_valid,
input wire [DW-1:0] sti_data,
output reg sto_valid,
output reg [DW-1:0] sto_data,
output reg ready50
); |
reg next_sto_valid;
reg [DW-1:0] next_sto_data;
reg [CW-1:0] divider, next_divider;
reg [CW-1:0] counter, next_counter;
wire counter_zero = ~|counter;
initial
begin
divider = 0;
counter = 0;
sto_valid = 0;
sto_data = 0;
end
always @ (posedge clk)
begin
divider <= next_divider;
counter <= next_counter;
sto_valid <= next_sto_valid;
sto_data <= next_sto_data;
end
always @*
begin
next_divider = divider;
next_counter = counter;
next_sto_valid = 1'b0;
next_sto_data = sto_data;
if (extClock_mode)
begin
next_sto_valid = sti_valid;
next_sto_data = sti_data;
end
else if (sti_valid && counter_zero)
begin
next_sto_valid = 1'b1;
next_sto_data = sti_data;
end
if (wrDivider)
begin
next_divider = config_data[CW-1:0];
next_counter = next_divider;
next_sto_valid = 1'b0;
end
else if (sti_valid)
if (counter_zero)
next_counter = divider;
else next_counter = counter-1'b1;
end
always @(posedge clk)
begin
if (wrDivider)
ready50 <= 1'b0;
else if (counter_zero)
ready50 <= 1'b1;
else if (counter == divider[CW-1:1])
ready50 <= 1'b0;
end
endmodule | 6 |
142,041 | data/full_repos/permissive/9699476/rtl/shifter.v | 9,699,476 | shifter.v | v | 95 | 99 | [] | ['general public license', 'free software foundation'] | [] | null | line:53: before: "[" | null | 1: b'%Warning-SELRANGE: data/full_repos/permissive/9699476/rtl/shifter.v:83: Selection index out of range: 7:7 outside 4:0\n : ... In instance shifter\n if (ctl_ena) pipe_data[l][b] <= shift[b][l] ? pipe_data[l-1][(b+l)%DW] : pipe_data[l-1][b];\n ^\n ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/9699476/rtl/shifter.v:83: Selection index out of range: 7:7 outside 4:0\n : ... In instance shifter\n if (ctl_ena) pipe_data[l][b] <= shift[b][l] ? pipe_data[l-1][(b+l)%DW] : pipe_data[l-1][b];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,993 | module | module shifter #(
parameter integer DW = 32
)(
input wire clk,
input wire rst,
input wire ctl_clr,
input wire ctl_ena,
input wire [DW-1:0] cfg_mask,
input wire sti_valid,
output wire sti_ready,
input wire [DW-1:0] sti_data,
output wire sto_valid,
input wire sto_ready,
output wire [DW-1:0] sto_data
);
localparam DL = $clog2(DW);
wire sti_transfer;
assign sti_transfer = sti_valid & sti_ready;
reg [DL-1:0] [DW-1:0] pipe_data;
reg [DL-1:0] pipe_valid = {DL{1'b0}};
wire [DL-1:0] pipe_ready;
reg [DW-1:0] [DL-1:0] shift;
always @ (posedge clk, posedge rst)
if (rst) begin
pipe_valid <= {DL{1'b0}};
end else if (ctl_ena) begin
pipe_valid <= {pipe_valid [DL-2:0], sti_valid};
end
genvar l, b;
generate
for (l=0; l<DL; l=l+1) begin: layer
for (b=0; b<DW; b=b+1) begin: dbit
always @ (posedge clk)
if (ctl_ena) pipe_data[l][b] <= shift[b][l] ? pipe_data[l-1][(b+l)%DW] : pipe_data[l-1][b];
end
end
endgenerate
assign sto_valid = !ctl_ena ? sti_valid : pipe_valid[DL-1];
assign sto_data = !ctl_ena ? sti_data : pipe_data [DL-1];
assign sti_ready = !ctl_ena ? sto_ready : pipe_ready[0] | ~pipe_valid[0];
endmodule | module shifter #(
parameter integer DW = 32
)(
input wire clk,
input wire rst,
input wire ctl_clr,
input wire ctl_ena,
input wire [DW-1:0] cfg_mask,
input wire sti_valid,
output wire sti_ready,
input wire [DW-1:0] sti_data,
output wire sto_valid,
input wire sto_ready,
output wire [DW-1:0] sto_data
); |
localparam DL = $clog2(DW);
wire sti_transfer;
assign sti_transfer = sti_valid & sti_ready;
reg [DL-1:0] [DW-1:0] pipe_data;
reg [DL-1:0] pipe_valid = {DL{1'b0}};
wire [DL-1:0] pipe_ready;
reg [DW-1:0] [DL-1:0] shift;
always @ (posedge clk, posedge rst)
if (rst) begin
pipe_valid <= {DL{1'b0}};
end else if (ctl_ena) begin
pipe_valid <= {pipe_valid [DL-2:0], sti_valid};
end
genvar l, b;
generate
for (l=0; l<DL; l=l+1) begin: layer
for (b=0; b<DW; b=b+1) begin: dbit
always @ (posedge clk)
if (ctl_ena) pipe_data[l][b] <= shift[b][l] ? pipe_data[l-1][(b+l)%DW] : pipe_data[l-1][b];
end
end
endgenerate
assign sto_valid = !ctl_ena ? sti_valid : pipe_valid[DL-1];
assign sto_data = !ctl_ena ? sti_data : pipe_data [DL-1];
assign sti_ready = !ctl_ena ? sto_ready : pipe_ready[0] | ~pipe_valid[0];
endmodule | 6 |
142,044 | data/full_repos/permissive/9699476/rtl/sram_interface.v | 9,699,476 | sram_interface.v | v | 244 | 108 | [] | ['general public license', 'free software foundation'] | [] | [(40, 243)] | null | data/verilator_xmls/4501acbd-f8f7-4260-83c4-a66c3d3db047.xml | null | 312,997 | module | module sram_interface #(
parameter MSZ = 6*1024,
parameter MAW = 13,
parameter MDW = 32
)(
input wire clk,
input wire rst,
input wire wrFlags,
input wire [3:0] config_data,
input wire write,
input wire lastwrite,
input wire [MDW-1:0] wrdata,
input wire rd_ready,
output reg rd_valid,
output reg [3:0] rd_keep,
output wire [MDW-1:0] rd_data
);
reg init, next_init;
reg [1:0] mode, next_mode;
reg [3:0] validmask, next_validmask;
reg [3:0] clkenb, next_clkenb;
reg [MAW-1:0] address, next_address;
reg [3:0] next_rd_keep;
wire maxaddr = &address[MAW-1-2:0] & address[MAW-1];
wire addrzero = ~|address;
initial
begin
init = 1'b0;
mode = 2'b00;
validmask = 4'hF;
clkenb = 4'b1111;
address = 0;
rd_keep = 4'b0000;
rd_valid = 1'b0;
end
always @ (posedge clk)
begin
init <= next_init;
mode <= next_mode;
validmask <= next_validmask;
clkenb <= next_clkenb;
address <= next_address;
rd_keep <= next_rd_keep;
rd_valid <=|next_rd_keep;
end
always @*
begin
next_init = 1'b0;
next_mode = mode;
next_validmask = validmask;
next_clkenb = clkenb;
next_address = address;
next_rd_keep = clkenb & validmask;
if (wrFlags)
begin
next_init = 1'b1;
next_mode = 0;
case (config_data)
4'b1100, 4'b0011, 4'b0110, 4'b1001, 4'b1010, 4'b0101 : next_mode = 2'b10;
4'b1110, 4'b1101, 4'b1011, 4'b0111 : next_mode = 2'b01;
endcase
next_validmask = 4'hF;
case (config_data)
4'b0001, 4'b0010, 4'b0100, 4'b1000 : next_validmask = 4'h7;
endcase
end
casex ({write && !lastwrite, rd_ready})
2'b1x :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[2:0],clkenb[3]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[3]) next_address = (maxaddr) ? 0 : address+1'b1;
end
2'bx1 :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[0],clkenb[3:1]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[0]) next_address = (addrzero) ? MSZ-1 : address-1'b1;
end
endcase
if (init)
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = 4'b0001;
2'b1x : next_clkenb = 4'b0011;
endcase
next_address = 0;
end
end
reg [MDW-1:0] ram_datain;
always @*
begin
ram_datain = wrdata;
casex (mode[1:0])
2'bx1 : ram_datain[31:0] = {wrdata[7:0],wrdata[7:0],wrdata[7:0],wrdata[7:0]};
2'b1x : ram_datain[31:0] = {wrdata[15:0],wrdata[15:0]};
endcase
end
`ifdef XC3S250E
genvar i;
generate
for (i=0; i<4; i=i+1) begin : mem
reg [8-1:0] mem1 [0:2048-1];
reg [8-1:0] mem0 [0:4096-1];
reg [8-1:0] rd_data1;
reg [8-1:0] rd_data0;
reg adr_reg;
always @ (posedge clk) if (write & clkenb[i] & address[12]) mem1 [address[10:0]] <= ram_datain[i*8+:8];
always @ (posedge clk) if (write & clkenb[i] & ~address[12]) mem0 [address[10:0]] <= ram_datain[i*8+:8];
always @ (posedge clk) rd_data1 <= mem1 [address[10:0]];
always @ (posedge clk) rd_data0 <= mem0 [address[11:0]];
always @ (posedge clk) adr_reg <= address[12];
assign rd_data [i*8+:8] = adr_reg ? rd_data1 : rd_data0;
end
endgenerate
`else
genvar i;
generate
for (i=0; i<4; i=i+1) begin : mem
reg [8-1:0] mem [0:MSZ-1];
reg [8-1:0] mem_rdt;
always @ (posedge clk)
if (write & clkenb[i]) mem [address] <= ram_datain[i*8+:8];
always @ (posedge clk)
mem_rdt <= mem [address];
assign rd_data [i*8+:8] = mem_rdt;
end
endgenerate
`endif
endmodule | module sram_interface #(
parameter MSZ = 6*1024,
parameter MAW = 13,
parameter MDW = 32
)(
input wire clk,
input wire rst,
input wire wrFlags,
input wire [3:0] config_data,
input wire write,
input wire lastwrite,
input wire [MDW-1:0] wrdata,
input wire rd_ready,
output reg rd_valid,
output reg [3:0] rd_keep,
output wire [MDW-1:0] rd_data
); |
reg init, next_init;
reg [1:0] mode, next_mode;
reg [3:0] validmask, next_validmask;
reg [3:0] clkenb, next_clkenb;
reg [MAW-1:0] address, next_address;
reg [3:0] next_rd_keep;
wire maxaddr = &address[MAW-1-2:0] & address[MAW-1];
wire addrzero = ~|address;
initial
begin
init = 1'b0;
mode = 2'b00;
validmask = 4'hF;
clkenb = 4'b1111;
address = 0;
rd_keep = 4'b0000;
rd_valid = 1'b0;
end
always @ (posedge clk)
begin
init <= next_init;
mode <= next_mode;
validmask <= next_validmask;
clkenb <= next_clkenb;
address <= next_address;
rd_keep <= next_rd_keep;
rd_valid <=|next_rd_keep;
end
always @*
begin
next_init = 1'b0;
next_mode = mode;
next_validmask = validmask;
next_clkenb = clkenb;
next_address = address;
next_rd_keep = clkenb & validmask;
if (wrFlags)
begin
next_init = 1'b1;
next_mode = 0;
case (config_data)
4'b1100, 4'b0011, 4'b0110, 4'b1001, 4'b1010, 4'b0101 : next_mode = 2'b10;
4'b1110, 4'b1101, 4'b1011, 4'b0111 : next_mode = 2'b01;
endcase
next_validmask = 4'hF;
case (config_data)
4'b0001, 4'b0010, 4'b0100, 4'b1000 : next_validmask = 4'h7;
endcase
end
casex ({write && !lastwrite, rd_ready})
2'b1x :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[2:0],clkenb[3]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[3]) next_address = (maxaddr) ? 0 : address+1'b1;
end
2'bx1 :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[0],clkenb[3:1]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[0]) next_address = (addrzero) ? MSZ-1 : address-1'b1;
end
endcase
if (init)
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = 4'b0001;
2'b1x : next_clkenb = 4'b0011;
endcase
next_address = 0;
end
end
reg [MDW-1:0] ram_datain;
always @*
begin
ram_datain = wrdata;
casex (mode[1:0])
2'bx1 : ram_datain[31:0] = {wrdata[7:0],wrdata[7:0],wrdata[7:0],wrdata[7:0]};
2'b1x : ram_datain[31:0] = {wrdata[15:0],wrdata[15:0]};
endcase
end
`ifdef XC3S250E
genvar i;
generate
for (i=0; i<4; i=i+1) begin : mem
reg [8-1:0] mem1 [0:2048-1];
reg [8-1:0] mem0 [0:4096-1];
reg [8-1:0] rd_data1;
reg [8-1:0] rd_data0;
reg adr_reg;
always @ (posedge clk) if (write & clkenb[i] & address[12]) mem1 [address[10:0]] <= ram_datain[i*8+:8];
always @ (posedge clk) if (write & clkenb[i] & ~address[12]) mem0 [address[10:0]] <= ram_datain[i*8+:8];
always @ (posedge clk) rd_data1 <= mem1 [address[10:0]];
always @ (posedge clk) rd_data0 <= mem0 [address[11:0]];
always @ (posedge clk) adr_reg <= address[12];
assign rd_data [i*8+:8] = adr_reg ? rd_data1 : rd_data0;
end
endgenerate
`else
genvar i;
generate
for (i=0; i<4; i=i+1) begin : mem
reg [8-1:0] mem [0:MSZ-1];
reg [8-1:0] mem_rdt;
always @ (posedge clk)
if (write & clkenb[i]) mem [address] <= ram_datain[i*8+:8];
always @ (posedge clk)
mem_rdt <= mem [address];
assign rd_data [i*8+:8] = mem_rdt;
end
endgenerate
`endif
endmodule | 6 |
142,045 | data/full_repos/permissive/9699476/rtl/stage.v | 9,699,476 | stage.v | v | 203 | 107 | [] | ['general public license', 'free software foundation'] | [] | [(50, 202)] | null | null | 1: b'%Error: data/full_repos/permissive/9699476/rtl/stage.v:109: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte0 (testValue[ 3: 0], clk, wrenb, din[0], dout[0], matchLUT[0]);\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/trigterm_4bit\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/trigterm_4bit.v\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/trigterm_4bit.sv\n trigterm_4bit\n trigterm_4bit.v\n trigterm_4bit.sv\n obj_dir/trigterm_4bit\n obj_dir/trigterm_4bit.v\n obj_dir/trigterm_4bit.sv\n%Error: data/full_repos/permissive/9699476/rtl/stage.v:110: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte1 (testValue[ 7: 4], clk, wrenb, din[1], dout[1], matchLUT[1]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/stage.v:111: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte2 (testValue[11: 8], clk, wrenb, din[2], dout[2], matchLUT[2]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/stage.v:112: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte3 (testValue[15:12], clk, wrenb, din[3], dout[3], matchLUT[3]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/stage.v:113: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte4 (testValue[19:16], clk, wrenb, din[4], dout[4], matchLUT[4]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/stage.v:114: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte5 (testValue[23:20], clk, wrenb, din[5], dout[5], matchLUT[5]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/stage.v:115: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte6 (testValue[27:24], clk, wrenb, din[6], dout[6], matchLUT[6]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/stage.v:116: Cannot find file containing module: \'trigterm_4bit\'\ntrigterm_4bit byte7 (testValue[31:28], clk, wrenb, din[7], dout[7], matchLUT[7]);\n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/stage.v:138: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 34 bits.\n : ... In instance stage\n if (demux_mode) shiftRegister <= {shiftRegister, serialChannelH16, serialChannelL16};\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9699476/rtl/stage.v:139: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n : ... In instance stage\n else shiftRegister <= {shiftRegister, (cfgChannel[4]) ? serialChannelH16 : serialChannelL16};\n ^~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n' | 312,998 | module | module stage(
input wire clk,
input wire rst,
input wire validIn,
input wire [31:0] dataIn,
input wire wrenb,
input wire [7:0] din,
input wire wrConfig,
input wire [31:0] config_data,
input wire arm,
input wire demux_mode,
input wire [1:0] level,
output reg run,
output reg match
);
localparam TRUE = 1'b1;
localparam FALSE = 1'b0;
reg [27:0] configRegister;
reg [15:0] counter, next_counter;
reg [31:0] shiftRegister;
reg match32Register;
reg next_run;
reg next_match;
wire cfgStart = configRegister[27];
wire cfgSerial = configRegister[26];
wire [4:0] cfgChannel = configRegister[24:20];
wire [1:0] cfgLevel = configRegister[17:16];
wire [15:0] cfgDelay = configRegister[15:0];
always @ (posedge clk)
configRegister <= (wrConfig) ? config_data[27:0] : configRegister;
wire [31:0] testValue = (cfgSerial) ? shiftRegister : dataIn;
wire [7:0] dout;
wire [7:0] matchLUT;
trigterm_4bit byte0 (testValue[ 3: 0], clk, wrenb, din[0], dout[0], matchLUT[0]);
trigterm_4bit byte1 (testValue[ 7: 4], clk, wrenb, din[1], dout[1], matchLUT[1]);
trigterm_4bit byte2 (testValue[11: 8], clk, wrenb, din[2], dout[2], matchLUT[2]);
trigterm_4bit byte3 (testValue[15:12], clk, wrenb, din[3], dout[3], matchLUT[3]);
trigterm_4bit byte4 (testValue[19:16], clk, wrenb, din[4], dout[4], matchLUT[4]);
trigterm_4bit byte5 (testValue[23:20], clk, wrenb, din[5], dout[5], matchLUT[5]);
trigterm_4bit byte6 (testValue[27:24], clk, wrenb, din[6], dout[6], matchLUT[6]);
trigterm_4bit byte7 (testValue[31:28], clk, wrenb, din[7], dout[7], matchLUT[7]);
wire matchL16 = &matchLUT[3:0];
wire matchH16 = &matchLUT[7:4];
always @(posedge clk)
if (demux_mode) match32Register <= matchH16 | matchL16;
else match32Register <= matchH16 & matchL16;
wire serialChannelL16 = dataIn[{1'b0,cfgChannel[3:0]}];
wire serialChannelH16 = dataIn[{1'b1,cfgChannel[3:0]}];
always @(posedge clk)
if (validIn) begin
if (demux_mode) shiftRegister <= {shiftRegister, serialChannelH16, serialChannelL16};
else shiftRegister <= {shiftRegister, (cfgChannel[4]) ? serialChannelH16 : serialChannelL16};
end
localparam [1:0]
OFF = 2'h0,
ARMED = 2'h1,
MATCHED = 2'h2;
reg [1:0] state, next_state;
initial state = OFF;
always @(posedge clk, posedge rst)
if (rst) begin
state <= OFF;
counter <= 0;
match <= FALSE;
run <= FALSE;
end else begin
state <= next_state;
counter <= next_counter;
match <= next_match;
run <= next_run;
end
always @*
begin
next_state = state;
next_counter = counter;
next_match = FALSE;
next_run = FALSE;
case (state)
OFF :
begin
if (arm) next_state = ARMED;
end
ARMED :
begin
next_counter = cfgDelay;
if (match32Register && (level >= cfgLevel))
next_state = MATCHED;
end
MATCHED :
begin
if (validIn)
begin
next_counter = counter-1'b1;
if (~|counter)
begin
next_run = cfgStart;
next_match = ~cfgStart;
next_state = OFF;
end
end
end
endcase
end
endmodule | module stage(
input wire clk,
input wire rst,
input wire validIn,
input wire [31:0] dataIn,
input wire wrenb,
input wire [7:0] din,
input wire wrConfig,
input wire [31:0] config_data,
input wire arm,
input wire demux_mode,
input wire [1:0] level,
output reg run,
output reg match
); |
localparam TRUE = 1'b1;
localparam FALSE = 1'b0;
reg [27:0] configRegister;
reg [15:0] counter, next_counter;
reg [31:0] shiftRegister;
reg match32Register;
reg next_run;
reg next_match;
wire cfgStart = configRegister[27];
wire cfgSerial = configRegister[26];
wire [4:0] cfgChannel = configRegister[24:20];
wire [1:0] cfgLevel = configRegister[17:16];
wire [15:0] cfgDelay = configRegister[15:0];
always @ (posedge clk)
configRegister <= (wrConfig) ? config_data[27:0] : configRegister;
wire [31:0] testValue = (cfgSerial) ? shiftRegister : dataIn;
wire [7:0] dout;
wire [7:0] matchLUT;
trigterm_4bit byte0 (testValue[ 3: 0], clk, wrenb, din[0], dout[0], matchLUT[0]);
trigterm_4bit byte1 (testValue[ 7: 4], clk, wrenb, din[1], dout[1], matchLUT[1]);
trigterm_4bit byte2 (testValue[11: 8], clk, wrenb, din[2], dout[2], matchLUT[2]);
trigterm_4bit byte3 (testValue[15:12], clk, wrenb, din[3], dout[3], matchLUT[3]);
trigterm_4bit byte4 (testValue[19:16], clk, wrenb, din[4], dout[4], matchLUT[4]);
trigterm_4bit byte5 (testValue[23:20], clk, wrenb, din[5], dout[5], matchLUT[5]);
trigterm_4bit byte6 (testValue[27:24], clk, wrenb, din[6], dout[6], matchLUT[6]);
trigterm_4bit byte7 (testValue[31:28], clk, wrenb, din[7], dout[7], matchLUT[7]);
wire matchL16 = &matchLUT[3:0];
wire matchH16 = &matchLUT[7:4];
always @(posedge clk)
if (demux_mode) match32Register <= matchH16 | matchL16;
else match32Register <= matchH16 & matchL16;
wire serialChannelL16 = dataIn[{1'b0,cfgChannel[3:0]}];
wire serialChannelH16 = dataIn[{1'b1,cfgChannel[3:0]}];
always @(posedge clk)
if (validIn) begin
if (demux_mode) shiftRegister <= {shiftRegister, serialChannelH16, serialChannelL16};
else shiftRegister <= {shiftRegister, (cfgChannel[4]) ? serialChannelH16 : serialChannelL16};
end
localparam [1:0]
OFF = 2'h0,
ARMED = 2'h1,
MATCHED = 2'h2;
reg [1:0] state, next_state;
initial state = OFF;
always @(posedge clk, posedge rst)
if (rst) begin
state <= OFF;
counter <= 0;
match <= FALSE;
run <= FALSE;
end else begin
state <= next_state;
counter <= next_counter;
match <= next_match;
run <= next_run;
end
always @*
begin
next_state = state;
next_counter = counter;
next_match = FALSE;
next_run = FALSE;
case (state)
OFF :
begin
if (arm) next_state = ARMED;
end
ARMED :
begin
next_counter = cfgDelay;
if (match32Register && (level >= cfgLevel))
next_state = MATCHED;
end
MATCHED :
begin
if (validIn)
begin
next_counter = counter-1'b1;
if (~|counter)
begin
next_run = cfgStart;
next_match = ~cfgStart;
next_state = OFF;
end
end
end
endcase
end
endmodule | 6 |
142,047 | data/full_repos/permissive/9699476/rtl/transmitter.v | 9,699,476 | transmitter.v | v | 200 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:36: before: ";" | null | 1: b"%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:36: syntax error, unexpected ';', expecting ')' or ','\n parameter [31:0] FREQ = 100000000;\n ^\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:39: syntax error, unexpected ')'\n)(\n^\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire trxClock,\n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire reset,\n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:43: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [3:0] disabledGroups,\n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire write, \n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:45: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [31:0] wrdata, \n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:46: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire id, \n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:47: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire xon, \n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:48: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire xoff, \n ^~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:49: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire tx, \n ^~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:50: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg busy \n ^~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:68: syntax error, unexpected assign\nassign tx = txBuffer[0];\n^~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:79: syntax error, unexpected byte, expecting IDENTIFIER or '=' or do or final\nreg [7:0] byte;\n ^~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:81: syntax error, unexpected always\nalways\n^~~~~~\n%Error: data/full_repos/permissive/9699476/rtl/transmitter.v:138: syntax error, unexpected always\nalways @ (posedge clock or posedge reset) \n^~~~~~\n%Error: Exiting due to 16 error(s)\n" | 313,001 | module | module transmitter #(
parameter [31:0] FREQ = 100000000;
parameter [31:0] BAUDRATE = 115200;
parameter BITLENGTH = FREQ / BAUDRATE;
)(
input wire clock,
input wire trxClock,
input wire reset,
input wire [3:0] disabledGroups,
input wire write,
input wire [31:0] wrdata,
input wire id,
input wire xon,
input wire xoff,
output wire tx,
output reg busy
);
localparam TRUE = 1'b1;
localparam FALSE = 1'b0;
reg [31:0] sampled_wrdata, next_sampled_wrdata;
reg [3:0] sampled_disabledGroups, next_sampled_disabledGroups;
reg [3:0] bits, next_bits;
reg [2:0] bytesel, next_bytesel;
reg paused, next_paused;
reg byteDone, next_byteDone;
reg next_busy;
reg [9:0] txBuffer, next_txBuffer;
assign tx = txBuffer[0];
reg [9:0] counter, next_counter;
wire counter_zero = ~|counter;
reg writeByte;
reg [7:0] byte;
reg disabled;
always
begin
byte = 0;
disabled = 0;
case (bytesel[1:0])
2'h0 : begin byte = sampled_wrdata[ 7: 0]; disabled = sampled_disabledGroups[0]; end
2'h1 : begin byte = sampled_wrdata[15: 8]; disabled = sampled_disabledGroups[1]; end
2'h2 : begin byte = sampled_wrdata[23:16]; disabled = sampled_disabledGroups[2]; end
2'h3 : begin byte = sampled_wrdata[31:24]; disabled = sampled_disabledGroups[3]; end
endcase
end
always @ (posedge clock)
begin
counter <= next_counter;
bits <= next_bits;
byteDone <= next_byteDone;
txBuffer <= next_txBuffer;
end
always
begin
next_bits = bits;
next_byteDone = byteDone;
next_txBuffer = txBuffer;
next_counter = counter;
if (writeByte)
begin
next_counter = BITLENGTH;
next_bits = 0;
next_byteDone = FALSE;
next_txBuffer = {1'b1,byte,1'b0};
end
else if (counter_zero)
begin
next_counter = BITLENGTH;
next_txBuffer = {1'b1,txBuffer[9:1]};
if (bits == 4'hA)
next_byteDone = TRUE;
else next_bits = bits + 1'b1;
end
else if (trxClock)
next_counter = counter + 1'b1;
end
parameter [1:0] IDLE = 0, SEND = 1, POLL = 2;
reg [1:0] state, next_state;
always @ (posedge clock or posedge reset)
if (reset) begin
state <= IDLE;
sampled_wrdata <= 32'h0;
sampled_disabledGroups <= 4'h0;
bytesel <= 3'h0;
busy <= FALSE;
paused <= FALSE;
end else begin
state <= next_state;
sampled_wrdata <= next_sampled_wrdata;
sampled_disabledGroups <= next_sampled_disabledGroups;
bytesel <= next_bytesel;
busy <= next_busy;
paused <= next_paused;
end
always
begin
next_state = state;
next_sampled_wrdata = sampled_wrdata;
next_sampled_disabledGroups = sampled_disabledGroups;
next_bytesel = bytesel;
next_busy = (state != IDLE) || write || paused;
next_paused = xoff | (paused & !xon);
writeByte = FALSE;
case(state)
IDLE :
begin
next_sampled_wrdata = wrdata;
next_sampled_disabledGroups = disabledGroups;
next_bytesel = 2'h0;
if (write)
next_state = SEND;
else if (id)
begin
next_sampled_wrdata = 32'h534c4131;
next_sampled_disabledGroups = 4'b0000;
next_state = SEND;
end
end
SEND :
begin
writeByte = TRUE;
next_bytesel = bytesel+1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone && !paused)
next_state = (bytesel[2]) ? IDLE : SEND;
end
endcase
end
endmodule | module transmitter #(
parameter [31:0] FREQ = 100000000; |
parameter [31:0] BAUDRATE = 115200;
parameter BITLENGTH = FREQ / BAUDRATE;
)(
input wire clock,
input wire trxClock,
input wire reset,
input wire [3:0] disabledGroups,
input wire write,
input wire [31:0] wrdata,
input wire id,
input wire xon,
input wire xoff,
output wire tx,
output reg busy
);
localparam TRUE = 1'b1;
localparam FALSE = 1'b0;
reg [31:0] sampled_wrdata, next_sampled_wrdata;
reg [3:0] sampled_disabledGroups, next_sampled_disabledGroups;
reg [3:0] bits, next_bits;
reg [2:0] bytesel, next_bytesel;
reg paused, next_paused;
reg byteDone, next_byteDone;
reg next_busy;
reg [9:0] txBuffer, next_txBuffer;
assign tx = txBuffer[0];
reg [9:0] counter, next_counter;
wire counter_zero = ~|counter;
reg writeByte;
reg [7:0] byte;
reg disabled;
always
begin
byte = 0;
disabled = 0;
case (bytesel[1:0])
2'h0 : begin byte = sampled_wrdata[ 7: 0]; disabled = sampled_disabledGroups[0]; end
2'h1 : begin byte = sampled_wrdata[15: 8]; disabled = sampled_disabledGroups[1]; end
2'h2 : begin byte = sampled_wrdata[23:16]; disabled = sampled_disabledGroups[2]; end
2'h3 : begin byte = sampled_wrdata[31:24]; disabled = sampled_disabledGroups[3]; end
endcase
end
always @ (posedge clock)
begin
counter <= next_counter;
bits <= next_bits;
byteDone <= next_byteDone;
txBuffer <= next_txBuffer;
end
always
begin
next_bits = bits;
next_byteDone = byteDone;
next_txBuffer = txBuffer;
next_counter = counter;
if (writeByte)
begin
next_counter = BITLENGTH;
next_bits = 0;
next_byteDone = FALSE;
next_txBuffer = {1'b1,byte,1'b0};
end
else if (counter_zero)
begin
next_counter = BITLENGTH;
next_txBuffer = {1'b1,txBuffer[9:1]};
if (bits == 4'hA)
next_byteDone = TRUE;
else next_bits = bits + 1'b1;
end
else if (trxClock)
next_counter = counter + 1'b1;
end
parameter [1:0] IDLE = 0, SEND = 1, POLL = 2;
reg [1:0] state, next_state;
always @ (posedge clock or posedge reset)
if (reset) begin
state <= IDLE;
sampled_wrdata <= 32'h0;
sampled_disabledGroups <= 4'h0;
bytesel <= 3'h0;
busy <= FALSE;
paused <= FALSE;
end else begin
state <= next_state;
sampled_wrdata <= next_sampled_wrdata;
sampled_disabledGroups <= next_sampled_disabledGroups;
bytesel <= next_bytesel;
busy <= next_busy;
paused <= next_paused;
end
always
begin
next_state = state;
next_sampled_wrdata = sampled_wrdata;
next_sampled_disabledGroups = sampled_disabledGroups;
next_bytesel = bytesel;
next_busy = (state != IDLE) || write || paused;
next_paused = xoff | (paused & !xon);
writeByte = FALSE;
case(state)
IDLE :
begin
next_sampled_wrdata = wrdata;
next_sampled_disabledGroups = disabledGroups;
next_bytesel = 2'h0;
if (write)
next_state = SEND;
else if (id)
begin
next_sampled_wrdata = 32'h534c4131;
next_sampled_disabledGroups = 4'b0000;
next_state = SEND;
end
end
SEND :
begin
writeByte = TRUE;
next_bytesel = bytesel+1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone && !paused)
next_state = (bytesel[2]) ? IDLE : SEND;
end
endcase
end
endmodule | 6 |
142,048 | data/full_repos/permissive/9699476/rtl/trigger.v | 9,699,476 | trigger.v | v | 209 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(38, 208)] | null | null | 1: b"%Error: data/full_repos/permissive/9699476/rtl/trigger.v:174: Cannot find file containing module: 'stage'\nstage stage [3:0] (\n^~~~~\n ... Looked in:\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/stage\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/stage.v\n data/full_repos/permissive/9699476/rtl,data/full_repos/permissive/9699476/stage.sv\n stage\n stage.v\n stage.sv\n obj_dir/stage\n obj_dir/stage.v\n obj_dir/stage.sv\n%Error: Exiting due to 1 error(s)\n" | 313,002 | module | module trigger #(
parameter integer DW = 32
)(
input wire clk,
input wire rst,
input wire [3:0] wrMask,
input wire [3:0] wrValue,
input wire [3:0] wrConfig,
input wire [31:0] config_data,
input wire arm,
input wire demux_mode,
input wire sti_valid,
input wire [DW-1:0] sti_data,
output reg capture,
output wire run
);
reg [1:0] levelReg = 2'b00;
wire [3:0] stageRun;
assign run = |stageRun;
reg [DW-1:0] maskRegister;
reg [DW-1:0] valueRegister;
reg [3:0] wrcount = 0;
reg [3:0] wrenb = 4'b0;
wire [7:0] wrdata;
always @ (posedge clk)
begin
maskRegister <= (|wrMask ) ? config_data : maskRegister;
valueRegister <= (|wrValue) ? config_data : valueRegister;
end
always @ (posedge clk, posedge rst)
if (rst) begin
wrcount <= 0;
wrenb <= 4'h0;
end else begin
if (|wrenb) begin
wrcount <= wrcount + 'b1;
if (&wrcount) wrenb <= 4'h0;
end else begin
wrcount <= 0;
wrenb <= wrenb | wrValue;
end
end
assign wrdata = {
~|((~wrcount^valueRegister[31:28])&maskRegister[31:28]),
~|((~wrcount^valueRegister[27:24])&maskRegister[27:24]),
~|((~wrcount^valueRegister[23:20])&maskRegister[23:20]),
~|((~wrcount^valueRegister[19:16])&maskRegister[19:16]),
~|((~wrcount^valueRegister[15:12])&maskRegister[15:12]),
~|((~wrcount^valueRegister[11: 8])&maskRegister[11: 8]),
~|((~wrcount^valueRegister[7 : 4])&maskRegister[ 7: 4]),
~|((~wrcount^valueRegister[3 : 0])&maskRegister[ 3: 0])
};
wire [3:0] stageMatch;
stage stage [3:0] (
.clk (clk),
.rst (rst),
.dataIn (sti_data),
.validIn (sti_valid),
.wrenb (wrenb),
.din (wrdata),
.wrConfig (wrConfig),
.config_data(config_data),
.arm (arm),
.level (levelReg),
.demux_mode (demux_mode),
.run (stageRun),
.match (stageMatch)
);
always @(posedge clk, posedge rst)
begin : P2
if (rst) begin
capture <= 1'b0;
levelReg <= 2'b00;
end else begin
capture <= arm | capture;
if (|stageMatch) levelReg <= levelReg + 'b1;
end
end
endmodule | module trigger #(
parameter integer DW = 32
)(
input wire clk,
input wire rst,
input wire [3:0] wrMask,
input wire [3:0] wrValue,
input wire [3:0] wrConfig,
input wire [31:0] config_data,
input wire arm,
input wire demux_mode,
input wire sti_valid,
input wire [DW-1:0] sti_data,
output reg capture,
output wire run
); |
reg [1:0] levelReg = 2'b00;
wire [3:0] stageRun;
assign run = |stageRun;
reg [DW-1:0] maskRegister;
reg [DW-1:0] valueRegister;
reg [3:0] wrcount = 0;
reg [3:0] wrenb = 4'b0;
wire [7:0] wrdata;
always @ (posedge clk)
begin
maskRegister <= (|wrMask ) ? config_data : maskRegister;
valueRegister <= (|wrValue) ? config_data : valueRegister;
end
always @ (posedge clk, posedge rst)
if (rst) begin
wrcount <= 0;
wrenb <= 4'h0;
end else begin
if (|wrenb) begin
wrcount <= wrcount + 'b1;
if (&wrcount) wrenb <= 4'h0;
end else begin
wrcount <= 0;
wrenb <= wrenb | wrValue;
end
end
assign wrdata = {
~|((~wrcount^valueRegister[31:28])&maskRegister[31:28]),
~|((~wrcount^valueRegister[27:24])&maskRegister[27:24]),
~|((~wrcount^valueRegister[23:20])&maskRegister[23:20]),
~|((~wrcount^valueRegister[19:16])&maskRegister[19:16]),
~|((~wrcount^valueRegister[15:12])&maskRegister[15:12]),
~|((~wrcount^valueRegister[11: 8])&maskRegister[11: 8]),
~|((~wrcount^valueRegister[7 : 4])&maskRegister[ 7: 4]),
~|((~wrcount^valueRegister[3 : 0])&maskRegister[ 3: 0])
};
wire [3:0] stageMatch;
stage stage [3:0] (
.clk (clk),
.rst (rst),
.dataIn (sti_data),
.validIn (sti_valid),
.wrenb (wrenb),
.din (wrdata),
.wrConfig (wrConfig),
.config_data(config_data),
.arm (arm),
.level (levelReg),
.demux_mode (demux_mode),
.run (stageRun),
.match (stageMatch)
);
always @(posedge clk, posedge rst)
begin : P2
if (rst) begin
capture <= 1'b0;
levelReg <= 2'b00;
end else begin
capture <= arm | capture;
if (|stageMatch) levelReg <= levelReg + 'b1;
end
end
endmodule | 6 |
142,060 | data/full_repos/permissive/9699476/tbn/axi4stream.sv | 9,699,476 | axi4stream.sv | sv | 73 | 59 | [] | [] | [] | null | line:1: before: "package" | null | 1: b"%Error: data/full_repos/permissive/9699476/tbn/axi4stream.sv:40: syntax error, unexpected '@'\n while (~tready) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/axi4stream.sv:65: syntax error, unexpected '@'\n while (~tvalid) @ (posedge clk);\n ^\n%Error: Exiting due to 2 error(s)\n" | 313,004 | module | module str_src #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
input logic tvalid,
output logic tready,
input logic [DW-1:0] tvalue
);
task trn (input [VW-1:0] value,
);
begin
tvalue <= value;
tvalid <= 1'b1;
while (~tready) @ (posedge clk);
tvalid <= 1'b0;
end
endtask: trn
endmodule | module str_src #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
input logic tvalid,
output logic tready,
input logic [DW-1:0] tvalue
); |
task trn (input [VW-1:0] value,
);
begin
tvalue <= value;
tvalid <= 1'b1;
while (~tready) @ (posedge clk);
tvalid <= 1'b0;
end
endtask: trn
endmodule | 6 |
142,061 | data/full_repos/permissive/9699476/tbn/axi4stream.sv | 9,699,476 | axi4stream.sv | sv | 73 | 59 | [] | [] | [] | null | line:1: before: "package" | null | 1: b"%Error: data/full_repos/permissive/9699476/tbn/axi4stream.sv:40: syntax error, unexpected '@'\n while (~tready) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/axi4stream.sv:65: syntax error, unexpected '@'\n while (~tvalid) @ (posedge clk);\n ^\n%Error: Exiting due to 2 error(s)\n" | 313,004 | module | module str_drn #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
input logic tvalid,
output logic tready,
input logic [VW-1:0] tvalue
);
task trn (output [DW-1:0] value);
begin
tready <= 1'b1;
while (~tvalid) @ (posedge clk);
tready <= 1'b0;
value <= tvalue;
end
endtask: trn
endmodule | module str_drn #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
input logic tvalid,
output logic tready,
input logic [VW-1:0] tvalue
); |
task trn (output [DW-1:0] value);
begin
tready <= 1'b1;
while (~tvalid) @ (posedge clk);
tready <= 1'b0;
value <= tvalue;
end
endtask: trn
endmodule | 6 |
142,063 | data/full_repos/permissive/9699476/tbn/str.sv | 9,699,476 | str.sv | sv | 57 | 40 | [] | [] | [] | null | line:4: before: "VW" | null | 1: b"%Error: data/full_repos/permissive/9699476/tbn/str.sv:22: syntax error, unexpected '@'\n @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/str.sv:23: syntax error, unexpected '@'\n while (~tready) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/str.sv:48: syntax error, unexpected '@'\n @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/str.sv:49: syntax error, unexpected '@'\n while (~tvalid) @ (posedge clk);\n ^\n%Error: Exiting due to 4 error(s)\n" | 313,006 | module | module str_src #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
output logic tvalid = 1'b0,
input logic tready,
output logic [VW-1:0] tvalue
);
task trn (input [VW-1:0] value);
begin
tvalid = 1'b1;
tvalue = value;
@ (posedge clk);
while (~tready) @ (posedge clk);
tvalid = 1'b0;
end
endtask: trn
endmodule | module str_src #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
output logic tvalid = 1'b0,
input logic tready,
output logic [VW-1:0] tvalue
); |
task trn (input [VW-1:0] value);
begin
tvalid = 1'b1;
tvalue = value;
@ (posedge clk);
while (~tready) @ (posedge clk);
tvalid = 1'b0;
end
endtask: trn
endmodule | 6 |
142,064 | data/full_repos/permissive/9699476/tbn/str.sv | 9,699,476 | str.sv | sv | 57 | 40 | [] | [] | [] | null | line:4: before: "VW" | null | 1: b"%Error: data/full_repos/permissive/9699476/tbn/str.sv:22: syntax error, unexpected '@'\n @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/str.sv:23: syntax error, unexpected '@'\n while (~tready) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/str.sv:48: syntax error, unexpected '@'\n @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/str.sv:49: syntax error, unexpected '@'\n while (~tvalid) @ (posedge clk);\n ^\n%Error: Exiting due to 4 error(s)\n" | 313,006 | module | module str_drn #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
input logic tvalid,
output logic tready = 1'b0,
input logic [VW-1:0] tvalue
);
task trn (output [VW-1:0] value);
begin
tready = 1'b1;
@ (posedge clk);
while (~tvalid) @ (posedge clk);
tready = 1'b0;
value = tvalue;
end
endtask: trn
endmodule | module str_drn #(
parameter int VW = 32
)(
input logic clk,
input logic rst,
input logic tvalid,
output logic tready = 1'b0,
input logic [VW-1:0] tvalue
); |
task trn (output [VW-1:0] value);
begin
tready = 1'b1;
@ (posedge clk);
while (~tvalid) @ (posedge clk);
tready = 1'b0;
value = tvalue;
end
endtask: trn
endmodule | 6 |
142,065 | data/full_repos/permissive/9699476/tbn/tb_shifter.sv | 9,699,476 | tb_shifter.sv | sv | 148 | 86 | [] | [] | [] | null | line:4: before: "DW" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:11: Unsupported: Ignoring delay on this delayed statement.\nalways #5ns clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:39: Unsupported: fork statements\nfork\n^~~~\n%Error: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:44: syntax error, unexpected \'@\'\n repeat (2) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:48: syntax error, unexpected \'@\'\n repeat (2) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:57: syntax error, unexpected \'@\'\n repeat (128) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:69: syntax error, unexpected \'@\'\n repeat (2) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:70: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/9699476/tbn/tb_shifter.sv:139: Unsupported or unknown PLI call: $timeformat\ninitial $timeformat (-9,1," ns",0);\n ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,007 | module | module tb_shifter #(
parameter int DW = 32
);
logic clk = 1;
logic rst = 1;
always #5ns clk = ~clk;
logic ctl_ena = 1'b0;
logic ctl_clr = 1'b0;
logic [DW-1:0] cfg_mask = {DW{1'b1}};
logic [DW-1:0] sti_data;
logic sti_valid;
logic sti_ready;
logic [DW-1:0] sto_data;
logic sto_valid;
logic sto_ready;
logic [DW-1:0] value;
int unsigned error = 0;
int unsigned src_i;
int unsigned drn_i;
initial
begin
fork
begin
repeat (2) @ (posedge clk);
rst = 1'b0;
test_bypass;
repeat (2) @ (posedge clk);
if (error) $display ("FAILURE: there were %d errors during simulation.", error);
else $display ("SUCESS: there were no errors during simulation.");
$finish();
end
begin
repeat (128) @ (posedge clk);
$display ("FAILURE: simulation ended due to timeout.");
$finish();
end
join
end
task test_bypass;
begin
ctl_ena = 0;
repeat (2) @ (posedge clk);
fork
begin
for (src_i=0; src_i<16; src_i++) begin
src.trn ({8{src_i[3:0]}});
end
end
begin
for (drn_i=0; drn_i<16; drn_i++) begin
drn.trn (value); if (value != {8{drn_i[3:0]}}) error++;
end
end
join
end
endtask: test_bypass
str_src #(.VW (DW)) src (
.clk (clk),
.rst (rst),
.tvalid (sti_valid),
.tready (sti_ready),
.tvalue (sti_data )
);
str_drn #(.VW (DW)) drn (
.clk (clk),
.rst (rst),
.tvalid (sto_valid),
.tready (sto_ready),
.tvalue (sto_data )
);
shifter shifter (
.clk (clk),
.rst (rst),
.ctl_ena (ctl_ena),
.ctl_clr (ctl_clr),
.cfg_mask (cfg_mask),
.sti_data (sti_data ),
.sti_valid (sti_valid),
.sti_ready (sti_ready),
.sto_data (sto_data ),
.sto_valid (sto_valid),
.sto_ready (sto_ready)
);
initial $timeformat (-9,1," ns",0);
`ifdef WAVE
initial begin
$dumpfile ("waves.dump");
$dumpvars(0);
end
`endif
endmodule | module tb_shifter #(
parameter int DW = 32
); |
logic clk = 1;
logic rst = 1;
always #5ns clk = ~clk;
logic ctl_ena = 1'b0;
logic ctl_clr = 1'b0;
logic [DW-1:0] cfg_mask = {DW{1'b1}};
logic [DW-1:0] sti_data;
logic sti_valid;
logic sti_ready;
logic [DW-1:0] sto_data;
logic sto_valid;
logic sto_ready;
logic [DW-1:0] value;
int unsigned error = 0;
int unsigned src_i;
int unsigned drn_i;
initial
begin
fork
begin
repeat (2) @ (posedge clk);
rst = 1'b0;
test_bypass;
repeat (2) @ (posedge clk);
if (error) $display ("FAILURE: there were %d errors during simulation.", error);
else $display ("SUCESS: there were no errors during simulation.");
$finish();
end
begin
repeat (128) @ (posedge clk);
$display ("FAILURE: simulation ended due to timeout.");
$finish();
end
join
end
task test_bypass;
begin
ctl_ena = 0;
repeat (2) @ (posedge clk);
fork
begin
for (src_i=0; src_i<16; src_i++) begin
src.trn ({8{src_i[3:0]}});
end
end
begin
for (drn_i=0; drn_i<16; drn_i++) begin
drn.trn (value); if (value != {8{drn_i[3:0]}}) error++;
end
end
join
end
endtask: test_bypass
str_src #(.VW (DW)) src (
.clk (clk),
.rst (rst),
.tvalid (sti_valid),
.tready (sti_ready),
.tvalue (sti_data )
);
str_drn #(.VW (DW)) drn (
.clk (clk),
.rst (rst),
.tvalid (sto_valid),
.tready (sto_ready),
.tvalue (sto_data )
);
shifter shifter (
.clk (clk),
.rst (rst),
.ctl_ena (ctl_ena),
.ctl_clr (ctl_clr),
.cfg_mask (cfg_mask),
.sti_data (sti_data ),
.sti_valid (sti_valid),
.sti_ready (sti_ready),
.sto_data (sto_data ),
.sto_valid (sto_valid),
.sto_ready (sto_ready)
);
initial $timeformat (-9,1," ns",0);
`ifdef WAVE
initial begin
$dumpfile ("waves.dump");
$dumpvars(0);
end
`endif
endmodule | 6 |
142,066 | data/full_repos/permissive/9699476/tbn/testbench.sv | 9,699,476 | testbench.sv | sv | 332 | 97 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9699476/tbn/testbench.sv:8: Unsupported: Ignoring delay on this delayed statement.\nalways #10 bf_clock = ~bf_clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:82: syntax error, unexpected \'@\'\n while (!dataReady) @(posedge dataReady);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:115: syntax error, unexpected \'@\'\n repeat (5) @(posedge bf_clock); \n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:167: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:174: syntax error, unexpected \'@\'\n repeat (5) @(posedge bf_clock); \n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:178: syntax error, unexpected \'@\'\n repeat (20) @(posedge bf_clock); \n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:182: syntax error, unexpected \'@\'\n repeat (1) @(posedge bf_clock); \n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:184: syntax error, unexpected \'@\'\n repeat (5) @(posedge bf_clock); \n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:186: syntax error, unexpected \'@\'\n repeat (5) @(posedge bf_clock); \n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:192: syntax error, unexpected \'@\'\n @(posedge bf_clock);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:194: syntax error, unexpected \'@\'\n @(negedge bf_clock);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:199: syntax error, unexpected \'@\'\n repeat (80) @(posedge bf_clock);\n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:228: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:235: syntax error, unexpected \'@\'\n repeat (5) @(posedge bf_clock); \n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:239: syntax error, unexpected \'@\'\n repeat (1) @(posedge bf_clock); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/9699476/tbn/testbench.sv:241: Unsupported: Ignoring delay on this delayed statement.\n #5; extData_reg = extData_reg+1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9699476/tbn/testbench.sv:255: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/9699476/tbn/testbench.sv:318: Unsupported or unknown PLI call: $timeformat\ninitial $timeformat (-9,1," ns",0);\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9699476/tbn/testbench.sv:329: Unsupported: Ignoring delay on this delayed statement.\nalways #10000 $display ("%t",$realtime);\n ^\n%Error: Exiting due to 15 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,008 | module | module testbench();
logic bf_clock;
initial bf_clock = 1'b0;
always #10 bf_clock = ~bf_clock;
wire spi_sclk;
wire spi_cs_n;
wire spi_mosi;
wire spi_miso;
logic extClockIn = 1'b0;
logic extTriggerIn = 1'b0;
wire [31:0] extData;
logic [31:0] extData_reg;
assign extData = extData_reg;
Logic_Sniffer sniffer (
.bf_clock (bf_clock),
.extClockIn (extClockIn),
.extClockOut (extClockOut),
.extTriggerIn (extTriggerIn),
.extTriggerOut (extTriggerOut),
.extData (extData),
.dataReady (dataReady),
.armLEDnn (armLEDnn),
.triggerLEDnn (triggerLEDnn),
.spi_cs_n (spi_cs_n),
.spi_sclk (spi_sclk),
.spi_miso (spi_miso),
.spi_mosi (spi_mosi)
);
spi_master #(
.PERIOD (100)
) spi_master (
.cs_n (spi_cs_n),
.sclk (spi_sclk),
.miso (spi_miso),
.mosi (spi_mosi)
);
task write_cmd (input logic [7:0] dmosi);
logic [7:0] dmiso;
begin
spi_master.cycle (dmosi, dmiso);
$display ("%t: SPI: (0x%02x) '%c'",$realtime, dmiso, dmiso);
end
endtask: write_cmd
task write_longcmd (
input [7:0] opcode,
input [31:0] value
);
begin
write_cmd (opcode);
write_cmd (value[ 7: 0]);
write_cmd (value[15: 8]);
write_cmd (value[23:16]);
write_cmd (value[31:24]);
end
endtask: write_longcmd
task wait4fpga;
begin
while (!dataReady) @(posedge dataReady);
while ( dataReady) write_cmd(8'h7F);
end
endtask: wait4fpga
task setup_divider;
begin
$display ("%t: Reset for TEST_DIVIDER...", $realtime);
write_cmd (8'h00);
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h000000FF);
write_longcmd (8'hC1, 32'h00000040);
write_longcmd (8'hC2, 32'h08000000);
$display ("%t: Flags... (int testmode, sample all channels)", $realtime);
write_longcmd (8'h82, 32'h00000800);
$display ("%t: Divider... (sample every 3rd clock)", $realtime);
write_longcmd (8'h80, 32'h00000002);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h000f000f);
$display ("%t: Starting TEST1...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
repeat (5) @(posedge bf_clock);
$finish;
end
endtask: setup_divider
task setup_channel;
input [3:0] channel_disable;
begin
$display ("%t: Reset for channel test 4'b%b...", $realtime, channel_disable);
write_cmd (8'h00);
$display ("%t: Flags... (internal_testmode. channel_disable=%b)", $realtime,channel_disable);
write_longcmd (8'h82, 32'h00000800 | {channel_disable,2'b00});
$display ("%t: Divider... (100Mhz sampling)", $realtime);
write_longcmd (8'h80, 32'h00000000);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h00040004);
$display ("%t: Starting channel test...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
end
endtask: setup_channel
task setup_rle_test;
begin
$display ("%t: Reset for TEST_RLE...", $realtime);
write_cmd (8'h00);
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h00000000);
write_longcmd (8'hC1, 32'h00000000);
write_longcmd (8'hC2, 32'h08000000);
$display ("%t: Flags... 8-bit & rle", $realtime);
write_longcmd (8'h82, 32'h00000100 | {4'hE,2'b00});
$display ("%t: Divider... (max sample rate)", $realtime);
write_longcmd (8'h80, 32'h00000000);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h000f000f);
extData_reg = 0;
fork
begin
$display ("%t: Starting 5%% buffer prefetch test...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
repeat (5) @(posedge bf_clock);
$display ("%t: Test clearing of rle mask_flag on reset...", $realtime);
write_cmd (8'h00);
repeat (20) @(posedge bf_clock);
$finish;
end
begin
repeat (1) @(posedge bf_clock);
repeat (1000) begin
repeat (5) @(posedge bf_clock);
extData_reg[2] = 1;
repeat (5) @(posedge bf_clock);
extData_reg[2] = 0;
end
end
begin
repeat (5000) begin
@(posedge bf_clock);
extData_reg[7] = bf_clock;
@(negedge bf_clock);
extData_reg[7] = bf_clock;
end
end
begin
repeat (80) @(posedge bf_clock);
$display ("%t: Test RLE-mode cancel command...", $realtime);
write_cmd (8'h05);
end
join
end
endtask: setup_rle_test
task setup_maxsamplerate_test;
begin
$display ("%t: Reset for TEST_MAXRATE...", $realtime);
write_cmd (8'h00);
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h00000000);
write_longcmd (8'hC1, 32'h00000000);
write_longcmd (8'hC2, 32'h08000000);
$display ("%t: Flags... Demux mode (DDR sample rate)", $realtime);
write_longcmd (8'h82, 32'h00000000 | {4'hA,2'b01});
$display ("%t: Divider... (max sample rate)", $realtime);
write_longcmd (8'h80, 32'h00000000);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h000f000f);
fork
begin
$display ("%t: Starting DDR max sample rate test...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
repeat (5) @(posedge bf_clock);
$finish;
end
begin
repeat (1) @(posedge bf_clock);
repeat (2000) begin
#5; extData_reg = extData_reg+1;
end
end
join
end
endtask: setup_maxsamplerate_test
initial
begin
extData_reg = 0;
#100;
$display ("%t: Reset...", $realtime);
repeat (5)
write_cmd (8'h00);
$display ("%t: Query ID...", $realtime);
write_cmd (8'h02); wait4fpga();
`ifdef TEST_META
$display ("%t: Query Meta data...", $realtime);
write_cmd (8'h04);
wait4fpga();
repeat (5) @(posedge bf_clock);
$finish;
`endif
`ifdef TEST_RLE
setup_rle_test;
`endif
`ifdef TEST_MAXRATE
setup_maxsamplerate_test;
`endif
`ifdef TEST_DIVIDER
setup_divider;
`endif
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h000000FF);
write_longcmd (8'hC1, 32'h00000040);
write_longcmd (8'hC2, 32'h08000000);
setup_channel(4'hE);
setup_channel(4'hD);
setup_channel(4'hB);
setup_channel(4'h7);
setup_channel(4'hC);
setup_channel(4'hA);
setup_channel(4'h6);
setup_channel(4'h9);
setup_channel(4'h5);
setup_channel(4'h3);
setup_channel(4'h8);
setup_channel(4'h4);
setup_channel(4'h2);
setup_channel(4'h1);
$finish;
end
initial $timeformat (-9,1," ns",0);
`ifdef WAVE
initial
begin
$display ("%t: Starting wave dump...",$realtime);
$dumpfile ("waves.dump");
$dumpvars(0);
end
`endif
always #10000 $display ("%t",$realtime);
endmodule | module testbench(); |
logic bf_clock;
initial bf_clock = 1'b0;
always #10 bf_clock = ~bf_clock;
wire spi_sclk;
wire spi_cs_n;
wire spi_mosi;
wire spi_miso;
logic extClockIn = 1'b0;
logic extTriggerIn = 1'b0;
wire [31:0] extData;
logic [31:0] extData_reg;
assign extData = extData_reg;
Logic_Sniffer sniffer (
.bf_clock (bf_clock),
.extClockIn (extClockIn),
.extClockOut (extClockOut),
.extTriggerIn (extTriggerIn),
.extTriggerOut (extTriggerOut),
.extData (extData),
.dataReady (dataReady),
.armLEDnn (armLEDnn),
.triggerLEDnn (triggerLEDnn),
.spi_cs_n (spi_cs_n),
.spi_sclk (spi_sclk),
.spi_miso (spi_miso),
.spi_mosi (spi_mosi)
);
spi_master #(
.PERIOD (100)
) spi_master (
.cs_n (spi_cs_n),
.sclk (spi_sclk),
.miso (spi_miso),
.mosi (spi_mosi)
);
task write_cmd (input logic [7:0] dmosi);
logic [7:0] dmiso;
begin
spi_master.cycle (dmosi, dmiso);
$display ("%t: SPI: (0x%02x) '%c'",$realtime, dmiso, dmiso);
end
endtask: write_cmd
task write_longcmd (
input [7:0] opcode,
input [31:0] value
);
begin
write_cmd (opcode);
write_cmd (value[ 7: 0]);
write_cmd (value[15: 8]);
write_cmd (value[23:16]);
write_cmd (value[31:24]);
end
endtask: write_longcmd
task wait4fpga;
begin
while (!dataReady) @(posedge dataReady);
while ( dataReady) write_cmd(8'h7F);
end
endtask: wait4fpga
task setup_divider;
begin
$display ("%t: Reset for TEST_DIVIDER...", $realtime);
write_cmd (8'h00);
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h000000FF);
write_longcmd (8'hC1, 32'h00000040);
write_longcmd (8'hC2, 32'h08000000);
$display ("%t: Flags... (int testmode, sample all channels)", $realtime);
write_longcmd (8'h82, 32'h00000800);
$display ("%t: Divider... (sample every 3rd clock)", $realtime);
write_longcmd (8'h80, 32'h00000002);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h000f000f);
$display ("%t: Starting TEST1...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
repeat (5) @(posedge bf_clock);
$finish;
end
endtask: setup_divider
task setup_channel;
input [3:0] channel_disable;
begin
$display ("%t: Reset for channel test 4'b%b...", $realtime, channel_disable);
write_cmd (8'h00);
$display ("%t: Flags... (internal_testmode. channel_disable=%b)", $realtime,channel_disable);
write_longcmd (8'h82, 32'h00000800 | {channel_disable,2'b00});
$display ("%t: Divider... (100Mhz sampling)", $realtime);
write_longcmd (8'h80, 32'h00000000);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h00040004);
$display ("%t: Starting channel test...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
end
endtask: setup_channel
task setup_rle_test;
begin
$display ("%t: Reset for TEST_RLE...", $realtime);
write_cmd (8'h00);
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h00000000);
write_longcmd (8'hC1, 32'h00000000);
write_longcmd (8'hC2, 32'h08000000);
$display ("%t: Flags... 8-bit & rle", $realtime);
write_longcmd (8'h82, 32'h00000100 | {4'hE,2'b00});
$display ("%t: Divider... (max sample rate)", $realtime);
write_longcmd (8'h80, 32'h00000000);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h000f000f);
extData_reg = 0;
fork
begin
$display ("%t: Starting 5%% buffer prefetch test...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
repeat (5) @(posedge bf_clock);
$display ("%t: Test clearing of rle mask_flag on reset...", $realtime);
write_cmd (8'h00);
repeat (20) @(posedge bf_clock);
$finish;
end
begin
repeat (1) @(posedge bf_clock);
repeat (1000) begin
repeat (5) @(posedge bf_clock);
extData_reg[2] = 1;
repeat (5) @(posedge bf_clock);
extData_reg[2] = 0;
end
end
begin
repeat (5000) begin
@(posedge bf_clock);
extData_reg[7] = bf_clock;
@(negedge bf_clock);
extData_reg[7] = bf_clock;
end
end
begin
repeat (80) @(posedge bf_clock);
$display ("%t: Test RLE-mode cancel command...", $realtime);
write_cmd (8'h05);
end
join
end
endtask: setup_rle_test
task setup_maxsamplerate_test;
begin
$display ("%t: Reset for TEST_MAXRATE...", $realtime);
write_cmd (8'h00);
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h00000000);
write_longcmd (8'hC1, 32'h00000000);
write_longcmd (8'hC2, 32'h08000000);
$display ("%t: Flags... Demux mode (DDR sample rate)", $realtime);
write_longcmd (8'h82, 32'h00000000 | {4'hA,2'b01});
$display ("%t: Divider... (max sample rate)", $realtime);
write_longcmd (8'h80, 32'h00000000);
$display ("%t: Read & Delay Count...", $realtime);
write_longcmd (8'h81, 32'h000f000f);
fork
begin
$display ("%t: Starting DDR max sample rate test...", $realtime);
$display ("%t: RUN...", $realtime);
write_cmd (8'h01);
wait4fpga();
repeat (5) @(posedge bf_clock);
$finish;
end
begin
repeat (1) @(posedge bf_clock);
repeat (2000) begin
#5; extData_reg = extData_reg+1;
end
end
join
end
endtask: setup_maxsamplerate_test
initial
begin
extData_reg = 0;
#100;
$display ("%t: Reset...", $realtime);
repeat (5)
write_cmd (8'h00);
$display ("%t: Query ID...", $realtime);
write_cmd (8'h02); wait4fpga();
`ifdef TEST_META
$display ("%t: Query Meta data...", $realtime);
write_cmd (8'h04);
wait4fpga();
repeat (5) @(posedge bf_clock);
$finish;
`endif
`ifdef TEST_RLE
setup_rle_test;
`endif
`ifdef TEST_MAXRATE
setup_maxsamplerate_test;
`endif
`ifdef TEST_DIVIDER
setup_divider;
`endif
$display ("%t: Default Setup Trigger 0...", $realtime);
write_longcmd (8'hC0, 32'h000000FF);
write_longcmd (8'hC1, 32'h00000040);
write_longcmd (8'hC2, 32'h08000000);
setup_channel(4'hE);
setup_channel(4'hD);
setup_channel(4'hB);
setup_channel(4'h7);
setup_channel(4'hC);
setup_channel(4'hA);
setup_channel(4'h6);
setup_channel(4'h9);
setup_channel(4'h5);
setup_channel(4'h3);
setup_channel(4'h8);
setup_channel(4'h4);
setup_channel(4'h2);
setup_channel(4'h1);
$finish;
end
initial $timeformat (-9,1," ns",0);
`ifdef WAVE
initial
begin
$display ("%t: Starting wave dump...",$realtime);
$dumpfile ("waves.dump");
$dumpvars(0);
end
`endif
always #10000 $display ("%t",$realtime);
endmodule | 6 |
142,069 | data/full_repos/permissive/97045669/lib/HashCAM.v | 97,045,669 | HashCAM.v | v | 248 | 123 | [] | [] | [] | [(14, 247)] | null | null | 1: b'%Error: data/full_repos/permissive/97045669/lib/HashCAM.v:89: Cannot find file containing module: \'PearsonHash\'\nPearsonHash\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/lib,data/full_repos/permissive/97045669/PearsonHash\n data/full_repos/permissive/97045669/lib,data/full_repos/permissive/97045669/PearsonHash.v\n data/full_repos/permissive/97045669/lib,data/full_repos/permissive/97045669/PearsonHash.sv\n PearsonHash\n PearsonHash.v\n PearsonHash.sv\n obj_dir/PearsonHash\n obj_dir/PearsonHash.v\n obj_dir/PearsonHash.sv\n%Error: data/full_repos/permissive/97045669/lib/HashCAM.v:161: Cannot find file containing module: \'PearsonHash\'\nPearsonHash\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM.v:189: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'value_in\' generates 8 bits.\n : ... In instance HashCAM\n wr_captured_value_in <= value_in;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM.v:216: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'wr_captured_value_in\' generates 16 bits.\n : ... In instance HashCAM\n mejda[wr_block_hash][wr_lookup_idx][((((0 + 1) + (KEY_WIDTH_IN_OCTETS * 8) - 1) + 1) + VALUE_WIDTH_IN_BITS - 1):(((0 + 1) + (KEY_WIDTH_IN_OCTETS * 8) - 1) + 1)] <= wr_captured_value_in;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM.v:231: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'wr_captured_value_in\' generates 16 bits.\n : ... In instance HashCAM\n mejda[wr_block_hash][wr_vacant_idx][((((0 + 1) + (KEY_WIDTH_IN_OCTETS * 8) - 1) + 1) + VALUE_WIDTH_IN_BITS - 1):(((0 + 1) + (KEY_WIDTH_IN_OCTETS * 8) - 1) + 1)] <= wr_captured_value_in;\n ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 313,013 | module | module HashCAM
#(parameter KEY_WIDTH_IN_OCTETS = 2,
parameter VALUE_WIDTH_IN_BITS = 8,
parameter MAX_BUCKET_SIZE = 10)
(
input wire reset,
input wire lookup_enable,
output reg lookup_ready,
input wire write_enable,
output reg write_ready,
output reg match,
output reg full,
input wire [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] key_in,
input wire [VALUE_WIDTH_IN_BITS - 1 : 0] value_in,
output reg [VALUE_WIDTH_IN_BITS - 1 : 0] value_out);
reg live_F;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] key_F;
reg [VALUE_WIDTH_IN_BITS - 1 : 0] value_F;
`define LIVE_F_LSB 0
`define LIVE_F_MSB 0
`define LIVE_F_WORD `LIVE_F_MSB:`LIVE_F_LSB
`define KEY_F_LSB (`LIVE_F_MSB + 1)
`define KEY_F_MSB (`KEY_F_LSB + (KEY_WIDTH_IN_OCTETS * 8) - 1)
`define KEY_F_WORD `KEY_F_MSB:`KEY_F_LSB
`define VALUE_F_LSB (`KEY_F_MSB + 1)
`define VALUE_F_MSB (`VALUE_F_LSB + VALUE_WIDTH_IN_BITS - 1)
`define VALUE_F_WORD `VALUE_F_MSB:`VALUE_F_LSB
reg [`VALUE_F_MSB:`LIVE_F_LSB] mejda [255:0] [MAX_BUCKET_SIZE:0];
wire block_ready;
wire [7:0] block_hash;
reg block_enable = 0;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] block_in;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] captured_key_in;
integer i;
integer j;
always @(posedge reset) begin
full <= 0;
lookup_ready <= 0;
write_ready <= 0;
match <= 0;
value_out <= 0;
for (i = 0; i < 256; i = i + 1) begin
for (j = 0; j < MAX_BUCKET_SIZE; j = j + 1) begin
mejda[i][j] = 0;
end
end
end
PearsonHash
#(.BLOCK_SIZE_IN_OCTETS(KEY_WIDTH_IN_OCTETS))
ph_read
(.reset(reset),
.write_enable( ),
.write_ready( ),
.encipher_enable( ),
.encipher_ready( ),
.init_hash_enable( ),
.init_hash_ready( ),
.idx_in( ),
.key_byte_in( ),
.data_in( ),
.cipher_out( ),
.block_ready(block_ready),
.block_hash(block_hash),
.block_in(block_in),
.block_enable(block_enable));
always @(posedge lookup_enable) begin
if (!block_ready && !block_enable && !lookup_ready && !reset) begin
block_in <= key_in;
captured_key_in <= key_in;
block_enable <= 1;
end
end
integer lookup_idx;
reg found;
always @(posedge block_ready) begin
if (lookup_enable
&& !lookup_ready && !reset) begin
lookup_idx = 0;
found = 0;
while (lookup_idx < MAX_BUCKET_SIZE && !found) begin
if (mejda[block_hash][lookup_idx][`LIVE_F_WORD] &&
(mejda[block_hash][lookup_idx][`KEY_F_WORD] == captured_key_in)) begin
found = 1;
match <= 1;
value_out <= mejda[block_hash][lookup_idx][`VALUE_F_WORD];
end
lookup_idx = lookup_idx + 1;
end
block_enable <= 0;
lookup_ready <= 1;
end
end
always @(negedge lookup_enable) begin
match <= 0;
lookup_ready <= 0;
end
wire wr_block_ready;
wire [7:0] wr_block_hash;
reg wr_block_enable = 0;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] wr_block_in;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] wr_captured_key_in;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] wr_captured_value_in;
PearsonHash
#(.BLOCK_SIZE_IN_OCTETS(KEY_WIDTH_IN_OCTETS))
ph_write
(.reset(reset),
.write_enable( ),
.write_ready( ),
.encipher_enable( ),
.encipher_ready( ),
.init_hash_enable( ),
.init_hash_ready( ),
.idx_in( ),
.key_byte_in( ),
.data_in( ),
.cipher_out( ),
.block_ready(wr_block_ready),
.block_hash(wr_block_hash),
.block_in(wr_block_in),
.block_enable(wr_block_enable));
always @(posedge write_enable) begin
if (!wr_block_ready && !wr_block_enable && !write_ready && !reset) begin
wr_block_in <= key_in;
wr_captured_key_in <= key_in;
wr_captured_value_in <= value_in;
wr_block_enable <= 1;
end
end
integer wr_lookup_idx;
reg wr_found;
integer wr_vacant_idx;
reg wr_found_vacant;
always @(posedge wr_block_ready) begin
if (write_enable
&& !write_ready && !reset) begin
wr_lookup_idx = 0;
wr_found = 0;
wr_found_vacant = 0;
while (wr_lookup_idx < MAX_BUCKET_SIZE && !wr_found) begin
if (!mejda[wr_block_hash][wr_lookup_idx][`LIVE_F_WORD]) begin
wr_vacant_idx = wr_lookup_idx;
wr_found_vacant = 1;
end else if (mejda[wr_block_hash][wr_lookup_idx][`LIVE_F_WORD] &&
(mejda[wr_block_hash][wr_lookup_idx][`KEY_F_WORD] == wr_captured_key_in)) begin
wr_found = 1;
mejda[wr_block_hash][wr_lookup_idx][`VALUE_F_WORD] <= wr_captured_value_in;
match <= 1;
value_out <= mejda[wr_block_hash][wr_lookup_idx][`VALUE_F_WORD];
end
wr_lookup_idx = wr_lookup_idx + 1;
end
if (!wr_found) begin
if (!wr_found_vacant)
full <= 1;
else begin
mejda[wr_block_hash][wr_vacant_idx][`LIVE_F_WORD] <= 1;
mejda[wr_block_hash][wr_vacant_idx][`KEY_F_WORD] <= wr_captured_key_in;
mejda[wr_block_hash][wr_vacant_idx][`VALUE_F_WORD] <= wr_captured_value_in;
end
end
wr_block_enable <= 0;
write_ready <= 1;
end
end
always @(negedge write_enable) begin
match <= 0;
write_ready <= 0;
end
endmodule | module HashCAM
#(parameter KEY_WIDTH_IN_OCTETS = 2,
parameter VALUE_WIDTH_IN_BITS = 8,
parameter MAX_BUCKET_SIZE = 10)
(
input wire reset,
input wire lookup_enable,
output reg lookup_ready,
input wire write_enable,
output reg write_ready,
output reg match,
output reg full,
input wire [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] key_in,
input wire [VALUE_WIDTH_IN_BITS - 1 : 0] value_in,
output reg [VALUE_WIDTH_IN_BITS - 1 : 0] value_out); |
reg live_F;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] key_F;
reg [VALUE_WIDTH_IN_BITS - 1 : 0] value_F;
`define LIVE_F_LSB 0
`define LIVE_F_MSB 0
`define LIVE_F_WORD `LIVE_F_MSB:`LIVE_F_LSB
`define KEY_F_LSB (`LIVE_F_MSB + 1)
`define KEY_F_MSB (`KEY_F_LSB + (KEY_WIDTH_IN_OCTETS * 8) - 1)
`define KEY_F_WORD `KEY_F_MSB:`KEY_F_LSB
`define VALUE_F_LSB (`KEY_F_MSB + 1)
`define VALUE_F_MSB (`VALUE_F_LSB + VALUE_WIDTH_IN_BITS - 1)
`define VALUE_F_WORD `VALUE_F_MSB:`VALUE_F_LSB
reg [`VALUE_F_MSB:`LIVE_F_LSB] mejda [255:0] [MAX_BUCKET_SIZE:0];
wire block_ready;
wire [7:0] block_hash;
reg block_enable = 0;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] block_in;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] captured_key_in;
integer i;
integer j;
always @(posedge reset) begin
full <= 0;
lookup_ready <= 0;
write_ready <= 0;
match <= 0;
value_out <= 0;
for (i = 0; i < 256; i = i + 1) begin
for (j = 0; j < MAX_BUCKET_SIZE; j = j + 1) begin
mejda[i][j] = 0;
end
end
end
PearsonHash
#(.BLOCK_SIZE_IN_OCTETS(KEY_WIDTH_IN_OCTETS))
ph_read
(.reset(reset),
.write_enable( ),
.write_ready( ),
.encipher_enable( ),
.encipher_ready( ),
.init_hash_enable( ),
.init_hash_ready( ),
.idx_in( ),
.key_byte_in( ),
.data_in( ),
.cipher_out( ),
.block_ready(block_ready),
.block_hash(block_hash),
.block_in(block_in),
.block_enable(block_enable));
always @(posedge lookup_enable) begin
if (!block_ready && !block_enable && !lookup_ready && !reset) begin
block_in <= key_in;
captured_key_in <= key_in;
block_enable <= 1;
end
end
integer lookup_idx;
reg found;
always @(posedge block_ready) begin
if (lookup_enable
&& !lookup_ready && !reset) begin
lookup_idx = 0;
found = 0;
while (lookup_idx < MAX_BUCKET_SIZE && !found) begin
if (mejda[block_hash][lookup_idx][`LIVE_F_WORD] &&
(mejda[block_hash][lookup_idx][`KEY_F_WORD] == captured_key_in)) begin
found = 1;
match <= 1;
value_out <= mejda[block_hash][lookup_idx][`VALUE_F_WORD];
end
lookup_idx = lookup_idx + 1;
end
block_enable <= 0;
lookup_ready <= 1;
end
end
always @(negedge lookup_enable) begin
match <= 0;
lookup_ready <= 0;
end
wire wr_block_ready;
wire [7:0] wr_block_hash;
reg wr_block_enable = 0;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] wr_block_in;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] wr_captured_key_in;
reg [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] wr_captured_value_in;
PearsonHash
#(.BLOCK_SIZE_IN_OCTETS(KEY_WIDTH_IN_OCTETS))
ph_write
(.reset(reset),
.write_enable( ),
.write_ready( ),
.encipher_enable( ),
.encipher_ready( ),
.init_hash_enable( ),
.init_hash_ready( ),
.idx_in( ),
.key_byte_in( ),
.data_in( ),
.cipher_out( ),
.block_ready(wr_block_ready),
.block_hash(wr_block_hash),
.block_in(wr_block_in),
.block_enable(wr_block_enable));
always @(posedge write_enable) begin
if (!wr_block_ready && !wr_block_enable && !write_ready && !reset) begin
wr_block_in <= key_in;
wr_captured_key_in <= key_in;
wr_captured_value_in <= value_in;
wr_block_enable <= 1;
end
end
integer wr_lookup_idx;
reg wr_found;
integer wr_vacant_idx;
reg wr_found_vacant;
always @(posedge wr_block_ready) begin
if (write_enable
&& !write_ready && !reset) begin
wr_lookup_idx = 0;
wr_found = 0;
wr_found_vacant = 0;
while (wr_lookup_idx < MAX_BUCKET_SIZE && !wr_found) begin
if (!mejda[wr_block_hash][wr_lookup_idx][`LIVE_F_WORD]) begin
wr_vacant_idx = wr_lookup_idx;
wr_found_vacant = 1;
end else if (mejda[wr_block_hash][wr_lookup_idx][`LIVE_F_WORD] &&
(mejda[wr_block_hash][wr_lookup_idx][`KEY_F_WORD] == wr_captured_key_in)) begin
wr_found = 1;
mejda[wr_block_hash][wr_lookup_idx][`VALUE_F_WORD] <= wr_captured_value_in;
match <= 1;
value_out <= mejda[wr_block_hash][wr_lookup_idx][`VALUE_F_WORD];
end
wr_lookup_idx = wr_lookup_idx + 1;
end
if (!wr_found) begin
if (!wr_found_vacant)
full <= 1;
else begin
mejda[wr_block_hash][wr_vacant_idx][`LIVE_F_WORD] <= 1;
mejda[wr_block_hash][wr_vacant_idx][`KEY_F_WORD] <= wr_captured_key_in;
mejda[wr_block_hash][wr_vacant_idx][`VALUE_F_WORD] <= wr_captured_value_in;
end
end
wr_block_enable <= 0;
write_ready <= 1;
end
end
always @(negedge write_enable) begin
match <= 0;
write_ready <= 0;
end
endmodule | 3 |
142,071 | data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v | 97,045,669 | HashCAM_KL_Test.v | v | 750 | 327 | [] | [] | [] | null | line:29: before: "signed" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:72: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:86: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:90: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:91: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:92: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_lookup_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:94: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:95: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:170: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:171: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:180: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:181: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:190: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:191: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:200: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:201: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:210: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:211: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:220: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:221: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:230: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:231: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h0\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:241: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:242: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:248: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:249: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:255: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:256: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:262: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:263: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:269: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:270: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:276: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:277: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:283: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:284: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:362: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:376: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:385: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:394: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:403: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:412: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:421: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:430: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:436: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:442: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:448: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:454: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:460: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:466: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:474: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_4_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:475: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:481: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_8_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:482: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:488: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:489: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_14_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:490: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:496: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_18_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:497: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:503: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:504: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_24_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:505: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:511: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_28_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:512: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:518: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:519: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_34_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:520: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:526: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_38_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:533: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:534: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_44_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:535: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:541: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_48_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:542: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:548: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:549: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_54_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:550: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:556: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_58_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:557: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:563: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:564: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_64_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:565: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:571: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:572: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_1_5_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:573: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:580: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:581: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(32\'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Error: Exiting due to 88 warning(s)\n' | 313,015 | module | module HashCAM_KL_Test( output reg HC_write_enable,
input HC_write_ready,
output reg HC_lookup_enable,
input HC_lookup_ready,
input HC_match,
input HC_full,
output reg [15:0] HC_key_in,
output reg [7:0] HC_value_in,
input [7:0] HC_value_out,
input clk,
input reset);
function rtl_unsigned_bitextract2;
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[0:0]);
endfunction
function signed [63:0] rtl_sign_extend0;
input [31:0] arg;
rtl_sign_extend0 = { {32{arg[31]}}, arg[31:0] };
endfunction
function [63:0] rtl_unsigned_extend1;
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction
reg HashCAM_matched;
reg HashCAM_is_full;
wire [31:0] ktop18;
reg [63:0] T403_HashCAM_Write_1_5_V_0;
reg [63:0] T403_HashCAM_Write_0_64_V_0;
reg [63:0] T403_HashCAM_Read_0_58_V_0;
reg [63:0] T403_HashCAM_Write_0_54_V_0;
reg [63:0] T403_HashCAM_Read_0_48_V_0;
reg [63:0] T403_HashCAM_Write_0_44_V_0;
reg [63:0] T403_HashCAM_Read_0_38_V_0;
reg [63:0] T403_HashCAM_Write_0_34_V_0;
reg [63:0] T403_HashCAM_Read_0_28_V_0;
reg [63:0] T403_HashCAM_Write_0_24_V_0;
reg [63:0] T403_HashCAM_Read_0_18_V_0;
reg [63:0] T403_HashCAM_Write_0_14_V_0;
reg [63:0] T403_HashCAM_Read_0_8_V_0;
reg [63:0] T403_HashCAM_Read_0_4_V_0;
integer HashCAM_KL_Test_T403_Main_T403_Main_V_0;
wire [31:0] ktop16;
wire [31:0] ktop14;
reg System_BitConverter_IsLittleEndian;
wire [31:0] ktop12;
reg [63:0] KiwiSystem_Kiwi_tnow;
reg [31:0] KiwiSystem_Kiwi_old_pausemode_value;
wire [31:0] ktop10;
reg [6:0] xpc10;
reg xpc12;
always @(posedge clk ) begin
if (reset) begin
KiwiSystem_Kiwi_tnow <= 64'd0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'd0;
System_BitConverter_IsLittleEndian <= 32'd0;
T403_HashCAM_Read_0_4_V_0 <= 64'd0;
T403_HashCAM_Read_0_8_V_0 <= 64'd0;
T403_HashCAM_Write_0_14_V_0 <= 64'd0;
T403_HashCAM_Read_0_18_V_0 <= 64'd0;
T403_HashCAM_Write_0_24_V_0 <= 64'd0;
T403_HashCAM_Read_0_28_V_0 <= 64'd0;
T403_HashCAM_Write_0_34_V_0 <= 64'd0;
T403_HashCAM_Read_0_38_V_0 <= 64'd0;
T403_HashCAM_Write_0_44_V_0 <= 64'd0;
T403_HashCAM_Read_0_48_V_0 <= 64'd0;
T403_HashCAM_Write_0_54_V_0 <= 64'd0;
T403_HashCAM_Read_0_58_V_0 <= 64'd0;
T403_HashCAM_Write_0_64_V_0 <= 64'd0;
HashCAM_is_full <= 32'd0;
HashCAM_matched <= 32'd0;
T403_HashCAM_Write_1_5_V_0 <= 64'd0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'd0;
HC_write_enable <= 32'd0;
HC_value_in <= 32'd0;
xpc10 <= 32'd0;
HC_lookup_enable <= 32'd0;
HC_key_in <= 32'd0;
xpc12 <= 32'd0;
end
else begin
if ((HashCAM_KL_Test_T403_Main_T403_Main_V_0>=32'sd299) && (xpc10==7'sd43)) $finish(32'sd0);
if (HC_write_ready)
case (xpc10)
7'sd6: begin
xpc10 <= 7'sd67;
T403_HashCAM_Write_0_14_V_0 <= 64'h0;
end
7'sd7: xpc10 <= 7'sd8;
7'sd12: begin
xpc10 <= 7'sd63;
T403_HashCAM_Write_0_24_V_0 <= 64'h0;
end
7'sd13: xpc10 <= 7'sd14;
7'sd18: begin
xpc10 <= 7'sd59;
T403_HashCAM_Write_0_34_V_0 <= 64'h0;
end
7'sd19: xpc10 <= 7'sd20;
7'sd24: begin
xpc10 <= 7'sd55;
T403_HashCAM_Write_0_44_V_0 <= 64'h0;
end
7'sd25: xpc10 <= 7'sd26;
7'sd30: begin
xpc10 <= 7'sd51;
T403_HashCAM_Write_0_54_V_0 <= 64'h0;
end
7'sd31: xpc10 <= 7'sd32;
7'sd36: begin
xpc10 <= 7'sd47;
T403_HashCAM_Write_0_64_V_0 <= 64'h0;
end
7'sd37: xpc10 <= 7'sd38;
7'sd39: begin
xpc10 <= 7'sd44;
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd0;
end
7'sd40: xpc10 <= 7'sd41;
7'sd45: xpc10 <= 7'sd41;
7'sd46: xpc10 <= 7'sd38;
7'sd50: xpc10 <= 7'sd32;
7'sd54: xpc10 <= 7'sd26;
7'sd58: xpc10 <= 7'sd20;
7'sd62: xpc10 <= 7'sd14;
7'sd66: xpc10 <= 7'sd8;
endcase
else
case (xpc10)
7'sd6: begin
xpc10 <= 7'sd7;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_14_V_0 <= 64'h0;
end
7'sd7: xpc10 <= 7'sd66;
7'sd12: begin
xpc10 <= 7'sd13;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_24_V_0 <= 64'h0;
end
7'sd13: xpc10 <= 7'sd62;
7'sd18: begin
xpc10 <= 7'sd19;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_34_V_0 <= 64'h0;
end
7'sd19: xpc10 <= 7'sd58;
7'sd24: begin
xpc10 <= 7'sd25;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h8;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_44_V_0 <= 64'h0;
end
7'sd25: xpc10 <= 7'sd54;
7'sd30: begin
xpc10 <= 7'sd31;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_54_V_0 <= 64'h0;
end
7'sd31: xpc10 <= 7'sd50;
7'sd36: begin
xpc10 <= 7'sd37;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h9;
HC_key_in <= 64'hc;
T403_HashCAM_Write_0_64_V_0 <= 64'h0;
end
7'sd37: xpc10 <= 7'sd46;
7'sd39: begin
xpc10 <= 7'sd40;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h1;
HC_key_in <= 64'h0;
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd0;
end
7'sd40: xpc10 <= 7'sd45;
7'sd44: begin
xpc10 <= 7'sd40;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h1;
HC_key_in <= $signed(rtl_sign_extend0(HashCAM_KL_Test_T403_Main_T403_Main_V_0));
end
7'sd47: begin
xpc10 <= 7'sd37;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h9;
HC_key_in <= 64'hc;
end
7'sd51: begin
xpc10 <= 7'sd31;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
7'sd55: begin
xpc10 <= 7'sd25;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h8;
HC_key_in <= 64'ha;
end
7'sd59: begin
xpc10 <= 7'sd19;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
7'sd63: begin
xpc10 <= 7'sd13;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
7'sd67: begin
xpc10 <= 7'sd7;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
endcase
if (HC_lookup_ready)
case (xpc10)
7'sd0: begin
xpc10 <= 7'sd71;
T403_HashCAM_Read_0_4_V_0 <= 64'h0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
7'sd1: xpc10 <= 7'sd2;
7'sd3: begin
xpc10 <= 7'sd69;
T403_HashCAM_Read_0_8_V_0 <= 64'h0;
end
7'sd4: xpc10 <= 7'sd5;
7'sd9: begin
xpc10 <= 7'sd65;
T403_HashCAM_Read_0_18_V_0 <= 64'h0;
end
7'sd10: xpc10 <= 7'sd11;
7'sd15: begin
xpc10 <= 7'sd61;
T403_HashCAM_Read_0_28_V_0 <= 64'h0;
end
7'sd16: xpc10 <= 7'sd17;
7'sd21: begin
xpc10 <= 7'sd57;
T403_HashCAM_Read_0_38_V_0 <= 64'h0;
end
7'sd22: xpc10 <= 7'sd23;
7'sd27: begin
xpc10 <= 7'sd53;
T403_HashCAM_Read_0_48_V_0 <= 64'h0;
end
7'sd28: xpc10 <= 7'sd29;
7'sd33: begin
xpc10 <= 7'sd49;
T403_HashCAM_Read_0_58_V_0 <= 64'h0;
end
7'sd34: xpc10 <= 7'sd35;
7'sd48: xpc10 <= 7'sd35;
7'sd52: xpc10 <= 7'sd29;
7'sd56: xpc10 <= 7'sd23;
7'sd60: xpc10 <= 7'sd17;
7'sd64: xpc10 <= 7'sd11;
7'sd68: xpc10 <= 7'sd5;
7'sd70: xpc10 <= 7'sd2;
endcase
else
case (xpc10)
7'sd0: begin
xpc10 <= 7'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_4_V_0 <= 64'h0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
7'sd1: xpc10 <= 7'sd70;
7'sd3: begin
xpc10 <= 7'sd4;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_8_V_0 <= 64'h0;
end
7'sd4: xpc10 <= 7'sd68;
7'sd9: begin
xpc10 <= 7'sd10;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_18_V_0 <= 64'h0;
end
7'sd10: xpc10 <= 7'sd64;
7'sd15: begin
xpc10 <= 7'sd16;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_28_V_0 <= 64'h0;
end
7'sd16: xpc10 <= 7'sd60;
7'sd21: begin
xpc10 <= 7'sd22;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_38_V_0 <= 64'h0;
end
7'sd22: xpc10 <= 7'sd56;
7'sd27: begin
xpc10 <= 7'sd28;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_48_V_0 <= 64'h0;
end
7'sd28: xpc10 <= 7'sd52;
7'sd33: begin
xpc10 <= 7'sd34;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hb;
T403_HashCAM_Read_0_58_V_0 <= 64'h0;
end
7'sd34: xpc10 <= 7'sd48;
7'sd49: begin
xpc10 <= 7'sd34;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hb;
end
7'sd53: begin
xpc10 <= 7'sd28;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd57: begin
xpc10 <= 7'sd22;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd61: begin
xpc10 <= 7'sd16;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd65: begin
xpc10 <= 7'sd10;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd69: begin
xpc10 <= 7'sd4;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd71: begin
xpc10 <= 7'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
endcase
case (xpc10)
7'sd2: begin
xpc10 <= 7'sd3;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_4_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd5: begin
xpc10 <= 7'sd6;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_8_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd8: begin
xpc10 <= 7'sd9;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_14_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd11: begin
xpc10 <= 7'sd12;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_18_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd14: begin
xpc10 <= 7'sd15;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_24_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd17: begin
xpc10 <= 7'sd18;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_28_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd20: begin
xpc10 <= 7'sd21;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_34_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd23: begin
xpc10 <= 7'sd24;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_38_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd26: begin
xpc10 <= 7'sd27;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_44_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd29: begin
xpc10 <= 7'sd30;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_48_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd32: begin
xpc10 <= 7'sd33;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_54_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd35: begin
xpc10 <= 7'sd36;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_58_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd38: begin
xpc10 <= 7'sd39;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_64_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd41: begin
xpc10 <= 7'sd42;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_1_5_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd43: begin
if (!HC_write_ready && (HashCAM_KL_Test_T403_Main_T403_Main_V_0<32'sd299)) begin
xpc10 <= 7'sd40;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h1;
HC_key_in <= $signed(rtl_sign_extend0(32'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0));
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0;
end
if (HC_write_ready && (HashCAM_KL_Test_T403_Main_T403_Main_V_0<32'sd299)) begin
xpc10 <= 7'sd44;
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0;
end
if ((HashCAM_KL_Test_T403_Main_T403_Main_V_0>=32'sd299)) HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd1
+HashCAM_KL_Test_T403_Main_T403_Main_V_0;
end
endcase
if ((xpc12==1'sd0)) xpc12 <= 1'sd1;
if ((xpc10==7'sd42)) xpc10 <= 7'sd43;
end
end
endmodule | module HashCAM_KL_Test( output reg HC_write_enable,
input HC_write_ready,
output reg HC_lookup_enable,
input HC_lookup_ready,
input HC_match,
input HC_full,
output reg [15:0] HC_key_in,
output reg [7:0] HC_value_in,
input [7:0] HC_value_out,
input clk,
input reset); |
function rtl_unsigned_bitextract2;
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[0:0]);
endfunction
function signed [63:0] rtl_sign_extend0;
input [31:0] arg;
rtl_sign_extend0 = { {32{arg[31]}}, arg[31:0] };
endfunction
function [63:0] rtl_unsigned_extend1;
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction
reg HashCAM_matched;
reg HashCAM_is_full;
wire [31:0] ktop18;
reg [63:0] T403_HashCAM_Write_1_5_V_0;
reg [63:0] T403_HashCAM_Write_0_64_V_0;
reg [63:0] T403_HashCAM_Read_0_58_V_0;
reg [63:0] T403_HashCAM_Write_0_54_V_0;
reg [63:0] T403_HashCAM_Read_0_48_V_0;
reg [63:0] T403_HashCAM_Write_0_44_V_0;
reg [63:0] T403_HashCAM_Read_0_38_V_0;
reg [63:0] T403_HashCAM_Write_0_34_V_0;
reg [63:0] T403_HashCAM_Read_0_28_V_0;
reg [63:0] T403_HashCAM_Write_0_24_V_0;
reg [63:0] T403_HashCAM_Read_0_18_V_0;
reg [63:0] T403_HashCAM_Write_0_14_V_0;
reg [63:0] T403_HashCAM_Read_0_8_V_0;
reg [63:0] T403_HashCAM_Read_0_4_V_0;
integer HashCAM_KL_Test_T403_Main_T403_Main_V_0;
wire [31:0] ktop16;
wire [31:0] ktop14;
reg System_BitConverter_IsLittleEndian;
wire [31:0] ktop12;
reg [63:0] KiwiSystem_Kiwi_tnow;
reg [31:0] KiwiSystem_Kiwi_old_pausemode_value;
wire [31:0] ktop10;
reg [6:0] xpc10;
reg xpc12;
always @(posedge clk ) begin
if (reset) begin
KiwiSystem_Kiwi_tnow <= 64'd0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'd0;
System_BitConverter_IsLittleEndian <= 32'd0;
T403_HashCAM_Read_0_4_V_0 <= 64'd0;
T403_HashCAM_Read_0_8_V_0 <= 64'd0;
T403_HashCAM_Write_0_14_V_0 <= 64'd0;
T403_HashCAM_Read_0_18_V_0 <= 64'd0;
T403_HashCAM_Write_0_24_V_0 <= 64'd0;
T403_HashCAM_Read_0_28_V_0 <= 64'd0;
T403_HashCAM_Write_0_34_V_0 <= 64'd0;
T403_HashCAM_Read_0_38_V_0 <= 64'd0;
T403_HashCAM_Write_0_44_V_0 <= 64'd0;
T403_HashCAM_Read_0_48_V_0 <= 64'd0;
T403_HashCAM_Write_0_54_V_0 <= 64'd0;
T403_HashCAM_Read_0_58_V_0 <= 64'd0;
T403_HashCAM_Write_0_64_V_0 <= 64'd0;
HashCAM_is_full <= 32'd0;
HashCAM_matched <= 32'd0;
T403_HashCAM_Write_1_5_V_0 <= 64'd0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'd0;
HC_write_enable <= 32'd0;
HC_value_in <= 32'd0;
xpc10 <= 32'd0;
HC_lookup_enable <= 32'd0;
HC_key_in <= 32'd0;
xpc12 <= 32'd0;
end
else begin
if ((HashCAM_KL_Test_T403_Main_T403_Main_V_0>=32'sd299) && (xpc10==7'sd43)) $finish(32'sd0);
if (HC_write_ready)
case (xpc10)
7'sd6: begin
xpc10 <= 7'sd67;
T403_HashCAM_Write_0_14_V_0 <= 64'h0;
end
7'sd7: xpc10 <= 7'sd8;
7'sd12: begin
xpc10 <= 7'sd63;
T403_HashCAM_Write_0_24_V_0 <= 64'h0;
end
7'sd13: xpc10 <= 7'sd14;
7'sd18: begin
xpc10 <= 7'sd59;
T403_HashCAM_Write_0_34_V_0 <= 64'h0;
end
7'sd19: xpc10 <= 7'sd20;
7'sd24: begin
xpc10 <= 7'sd55;
T403_HashCAM_Write_0_44_V_0 <= 64'h0;
end
7'sd25: xpc10 <= 7'sd26;
7'sd30: begin
xpc10 <= 7'sd51;
T403_HashCAM_Write_0_54_V_0 <= 64'h0;
end
7'sd31: xpc10 <= 7'sd32;
7'sd36: begin
xpc10 <= 7'sd47;
T403_HashCAM_Write_0_64_V_0 <= 64'h0;
end
7'sd37: xpc10 <= 7'sd38;
7'sd39: begin
xpc10 <= 7'sd44;
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd0;
end
7'sd40: xpc10 <= 7'sd41;
7'sd45: xpc10 <= 7'sd41;
7'sd46: xpc10 <= 7'sd38;
7'sd50: xpc10 <= 7'sd32;
7'sd54: xpc10 <= 7'sd26;
7'sd58: xpc10 <= 7'sd20;
7'sd62: xpc10 <= 7'sd14;
7'sd66: xpc10 <= 7'sd8;
endcase
else
case (xpc10)
7'sd6: begin
xpc10 <= 7'sd7;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_14_V_0 <= 64'h0;
end
7'sd7: xpc10 <= 7'sd66;
7'sd12: begin
xpc10 <= 7'sd13;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_24_V_0 <= 64'h0;
end
7'sd13: xpc10 <= 7'sd62;
7'sd18: begin
xpc10 <= 7'sd19;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_34_V_0 <= 64'h0;
end
7'sd19: xpc10 <= 7'sd58;
7'sd24: begin
xpc10 <= 7'sd25;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h8;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_44_V_0 <= 64'h0;
end
7'sd25: xpc10 <= 7'sd54;
7'sd30: begin
xpc10 <= 7'sd31;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
T403_HashCAM_Write_0_54_V_0 <= 64'h0;
end
7'sd31: xpc10 <= 7'sd50;
7'sd36: begin
xpc10 <= 7'sd37;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h9;
HC_key_in <= 64'hc;
T403_HashCAM_Write_0_64_V_0 <= 64'h0;
end
7'sd37: xpc10 <= 7'sd46;
7'sd39: begin
xpc10 <= 7'sd40;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h1;
HC_key_in <= 64'h0;
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd0;
end
7'sd40: xpc10 <= 7'sd45;
7'sd44: begin
xpc10 <= 7'sd40;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h1;
HC_key_in <= $signed(rtl_sign_extend0(HashCAM_KL_Test_T403_Main_T403_Main_V_0));
end
7'sd47: begin
xpc10 <= 7'sd37;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h9;
HC_key_in <= 64'hc;
end
7'sd51: begin
xpc10 <= 7'sd31;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
7'sd55: begin
xpc10 <= 7'sd25;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h8;
HC_key_in <= 64'ha;
end
7'sd59: begin
xpc10 <= 7'sd19;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
7'sd63: begin
xpc10 <= 7'sd13;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
7'sd67: begin
xpc10 <= 7'sd7;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h7;
HC_key_in <= 64'ha;
end
endcase
if (HC_lookup_ready)
case (xpc10)
7'sd0: begin
xpc10 <= 7'sd71;
T403_HashCAM_Read_0_4_V_0 <= 64'h0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
7'sd1: xpc10 <= 7'sd2;
7'sd3: begin
xpc10 <= 7'sd69;
T403_HashCAM_Read_0_8_V_0 <= 64'h0;
end
7'sd4: xpc10 <= 7'sd5;
7'sd9: begin
xpc10 <= 7'sd65;
T403_HashCAM_Read_0_18_V_0 <= 64'h0;
end
7'sd10: xpc10 <= 7'sd11;
7'sd15: begin
xpc10 <= 7'sd61;
T403_HashCAM_Read_0_28_V_0 <= 64'h0;
end
7'sd16: xpc10 <= 7'sd17;
7'sd21: begin
xpc10 <= 7'sd57;
T403_HashCAM_Read_0_38_V_0 <= 64'h0;
end
7'sd22: xpc10 <= 7'sd23;
7'sd27: begin
xpc10 <= 7'sd53;
T403_HashCAM_Read_0_48_V_0 <= 64'h0;
end
7'sd28: xpc10 <= 7'sd29;
7'sd33: begin
xpc10 <= 7'sd49;
T403_HashCAM_Read_0_58_V_0 <= 64'h0;
end
7'sd34: xpc10 <= 7'sd35;
7'sd48: xpc10 <= 7'sd35;
7'sd52: xpc10 <= 7'sd29;
7'sd56: xpc10 <= 7'sd23;
7'sd60: xpc10 <= 7'sd17;
7'sd64: xpc10 <= 7'sd11;
7'sd68: xpc10 <= 7'sd5;
7'sd70: xpc10 <= 7'sd2;
endcase
else
case (xpc10)
7'sd0: begin
xpc10 <= 7'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_4_V_0 <= 64'h0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
7'sd1: xpc10 <= 7'sd70;
7'sd3: begin
xpc10 <= 7'sd4;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_8_V_0 <= 64'h0;
end
7'sd4: xpc10 <= 7'sd68;
7'sd9: begin
xpc10 <= 7'sd10;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_18_V_0 <= 64'h0;
end
7'sd10: xpc10 <= 7'sd64;
7'sd15: begin
xpc10 <= 7'sd16;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_28_V_0 <= 64'h0;
end
7'sd16: xpc10 <= 7'sd60;
7'sd21: begin
xpc10 <= 7'sd22;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_38_V_0 <= 64'h0;
end
7'sd22: xpc10 <= 7'sd56;
7'sd27: begin
xpc10 <= 7'sd28;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
T403_HashCAM_Read_0_48_V_0 <= 64'h0;
end
7'sd28: xpc10 <= 7'sd52;
7'sd33: begin
xpc10 <= 7'sd34;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hb;
T403_HashCAM_Read_0_58_V_0 <= 64'h0;
end
7'sd34: xpc10 <= 7'sd48;
7'sd49: begin
xpc10 <= 7'sd34;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hb;
end
7'sd53: begin
xpc10 <= 7'sd28;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd57: begin
xpc10 <= 7'sd22;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd61: begin
xpc10 <= 7'sd16;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd65: begin
xpc10 <= 7'sd10;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd69: begin
xpc10 <= 7'sd4;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
7'sd71: begin
xpc10 <= 7'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'ha;
end
endcase
case (xpc10)
7'sd2: begin
xpc10 <= 7'sd3;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_4_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd5: begin
xpc10 <= 7'sd6;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_8_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd8: begin
xpc10 <= 7'sd9;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_14_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd11: begin
xpc10 <= 7'sd12;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_18_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd14: begin
xpc10 <= 7'sd15;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_24_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd17: begin
xpc10 <= 7'sd18;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_28_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd20: begin
xpc10 <= 7'sd21;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_34_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd23: begin
xpc10 <= 7'sd24;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_38_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd26: begin
xpc10 <= 7'sd27;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_44_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd29: begin
xpc10 <= 7'sd30;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_48_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd32: begin
xpc10 <= 7'sd33;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_54_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd35: begin
xpc10 <= 7'sd36;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_58_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd38: begin
xpc10 <= 7'sd39;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_0_64_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd41: begin
xpc10 <= 7'sd42;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);
T403_HashCAM_Write_1_5_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);
end
7'sd43: begin
if (!HC_write_ready && (HashCAM_KL_Test_T403_Main_T403_Main_V_0<32'sd299)) begin
xpc10 <= 7'sd40;
HC_write_enable <= 1'h1;
HC_value_in <= 64'h1;
HC_key_in <= $signed(rtl_sign_extend0(32'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0));
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0;
end
if (HC_write_ready && (HashCAM_KL_Test_T403_Main_T403_Main_V_0<32'sd299)) begin
xpc10 <= 7'sd44;
T403_HashCAM_Write_1_5_V_0 <= 64'h0;
HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0;
end
if ((HashCAM_KL_Test_T403_Main_T403_Main_V_0>=32'sd299)) HashCAM_KL_Test_T403_Main_T403_Main_V_0 <= 32'sd1
+HashCAM_KL_Test_T403_Main_T403_Main_V_0;
end
endcase
if ((xpc12==1'sd0)) xpc12 <= 1'sd1;
if ((xpc10==7'sd42)) xpc10 <= 7'sd43;
end
end
endmodule | 3 |
142,072 | data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v | 97,045,669 | HashCAM_KL_Test.v | v | 750 | 327 | [] | [] | [] | null | line:29: before: "signed" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:72: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:86: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:90: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:91: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:92: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_lookup_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:94: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:95: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:170: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:171: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:180: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:181: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:190: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:191: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:200: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:201: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:210: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:211: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:220: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:221: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:230: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:231: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h0\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:241: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:242: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:248: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:249: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:255: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:256: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:262: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:263: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:269: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:270: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:276: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:277: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:283: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:284: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:362: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:376: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:385: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:394: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:403: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:412: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:421: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:430: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:436: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:442: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:448: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:454: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:460: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:466: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:474: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_4_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:475: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:481: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_8_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:482: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:488: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:489: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_14_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:490: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:496: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_18_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:497: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:503: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:504: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_24_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:505: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:511: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_28_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:512: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:518: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:519: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_34_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:520: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:526: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_38_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:533: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:534: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_44_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:535: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:541: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_48_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:542: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:548: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:549: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_54_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:550: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:556: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_58_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:557: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:563: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:564: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_64_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:565: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:571: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:572: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_1_5_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:573: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:580: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:581: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(32\'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Error: Exiting due to 88 warning(s)\n' | 313,015 | function | function rtl_unsigned_bitextract2;
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[0:0]);
endfunction | function rtl_unsigned_bitextract2; |
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[0:0]);
endfunction | 3 |
142,073 | data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v | 97,045,669 | HashCAM_KL_Test.v | v | 750 | 327 | [] | [] | [] | null | line:29: before: "signed" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:72: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:86: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:90: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:91: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:92: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_lookup_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:94: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:95: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:170: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:171: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:180: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:181: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:190: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:191: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:200: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:201: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:210: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:211: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:220: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:221: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:230: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:231: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h0\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:241: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:242: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:248: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:249: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:255: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:256: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:262: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:263: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:269: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:270: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:276: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:277: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:283: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:284: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:362: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:376: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:385: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:394: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:403: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:412: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:421: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:430: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:436: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:442: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:448: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:454: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:460: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:466: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:474: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_4_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:475: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:481: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_8_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:482: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:488: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:489: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_14_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:490: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:496: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_18_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:497: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:503: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:504: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_24_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:505: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:511: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_28_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:512: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:518: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:519: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_34_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:520: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:526: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_38_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:533: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:534: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_44_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:535: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:541: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_48_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:542: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:548: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:549: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_54_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:550: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:556: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_58_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:557: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:563: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:564: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_64_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:565: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:571: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:572: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_1_5_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:573: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:580: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:581: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(32\'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Error: Exiting due to 88 warning(s)\n' | 313,015 | function | function signed [63:0] rtl_sign_extend0;
input [31:0] arg;
rtl_sign_extend0 = { {32{arg[31]}}, arg[31:0] };
endfunction | function signed [63:0] rtl_sign_extend0; |
input [31:0] arg;
rtl_sign_extend0 = { {32{arg[31]}}, arg[31:0] };
endfunction | 3 |
142,074 | data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v | 97,045,669 | HashCAM_KL_Test.v | v | 750 | 327 | [] | [] | [] | null | line:29: before: "signed" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:72: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:86: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:90: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:91: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:92: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_lookup_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:94: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:95: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance HashCAM_KL_Test\n xpc12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:170: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:171: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:180: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:181: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:190: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:191: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:200: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:201: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:210: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:211: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:220: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:221: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:230: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:231: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h0\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:241: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:242: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:248: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h9\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h9;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:249: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hc\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:255: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:256: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:262: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h8\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:263: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:269: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:270: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:276: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:277: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:283: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h7\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h7;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:284: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:362: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:376: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:385: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:394: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:403: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:412: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:421: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:430: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hb\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'hb;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:436: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:442: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:448: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:454: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:460: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:466: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'ha\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= 64\'ha;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:474: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_4_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:475: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:481: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_8_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:482: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:488: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:489: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_14_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:490: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:496: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_18_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:497: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:503: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:504: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_24_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:505: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:511: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_28_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:512: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:518: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:519: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_34_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:520: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:526: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_38_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:533: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:534: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_44_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:535: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:541: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_48_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:542: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:548: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:549: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_54_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:550: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:556: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Read_0_58_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:557: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:563: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:564: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_0_64_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:565: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:571: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_is_full <= rtl_unsigned_bitextract2(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:572: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance HashCAM_KL_Test\n T403_HashCAM_Write_1_5_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:573: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance HashCAM_KL_Test\n HashCAM_matched <= rtl_unsigned_bitextract2(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:580: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1\' generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_value_in <= 64\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/HashCAM_KL_Test.v:581: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 64 bits.\n : ... In instance HashCAM_KL_Test\n HC_key_in <= $signed(rtl_sign_extend0(32\'sd1+HashCAM_KL_Test_T403_Main_T403_Main_V_0));\n ^~\n%Error: Exiting due to 88 warning(s)\n' | 313,015 | function | function [63:0] rtl_unsigned_extend1;
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction | function [63:0] rtl_unsigned_extend1; |
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction | 3 |
142,076 | data/full_repos/permissive/97045669/lib/LRU.v | 97,045,669 | LRU.v | v | 824 | 325 | [] | [] | [] | [(11, 667)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:85: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:86: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HashCAM_is_full <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:103: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HashCAM_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:104: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:108: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:109: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_value_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:110: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_data_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:111: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:112: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_idx_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:113: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_command <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:114: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:115: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_lookup_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:116: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_key_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:117: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:118: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc14 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:196: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:197: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:205: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:206: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:216: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h14\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h14;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:217: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:227: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:228: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:238: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:239: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:247: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:248: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:254: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:255: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:261: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:262: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:268: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:269: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:275: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h14\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h14;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:282: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:283: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:289: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:297: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:355: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:374: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:388: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:403: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:409: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:415: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:422: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:423: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:425: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:431: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:439: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:445: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:457: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'NaughtyQ_idx_out_nv\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= NaughtyQ_idx_out_nv;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:489: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:499: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'NaughtyQ_idx_out_nv\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= NaughtyQ_idx_out_nv;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:500: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:510: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Cache_0_15_V_0\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= T403_LRU_Cache_0_15_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:511: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:517: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Cache_0_10_V_0\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= T403_LRU_Cache_0_10_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:518: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:525: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:526: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:528: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:534: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:540: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:541: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:544: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:551: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:558: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:559: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:561: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:569: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:570: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:576: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:582: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:583: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_idx_out\' generates 4 bits.\n : ... In instance LRU\n NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:589: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance LRU\n HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:590: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:591: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:597: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:598: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_idx_out\' generates 4 bits.\n : ... In instance LRU\n NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:604: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance LRU\n HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:605: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:606: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:612: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:613: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:619: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:625: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:626: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:633: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:638: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:646: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 96 warning(s)\n' | 313,017 | module | module LRU( output reg NQ_enable,
input NQ_ready,
input NQ_crashed,
output reg [3:0] NQ_command,
input [3:0] NQ_idx_out,
input [7:0] NQ_data_out,
output reg [3:0] NQ_idx_in,
output reg [7:0] NQ_data_in,
output reg HC_write_enable,
input HC_write_ready,
output reg HC_lookup_enable,
input HC_lookup_ready,
input HC_match,
input HC_full,
output reg [15:0] HC_key_in,
output reg [7:0] HC_value_in,
input [7:0] HC_value_out,
input clk,
input reset);
function rtl_unsigned_bitextract0;
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[0:0]);
endfunction
function [63:0] rtl_unsigned_extend1;
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction
reg [63:0] NaughtyQ_idx_out_nv;
reg [63:0] NaughtyQ_data_out_nv;
reg HashCAM_matched;
reg HashCAM_is_full;
wire [31:0] ktop20;
wire [31:0] ktop18;
reg [31:0] LRU_Lookup_CZ_0_1_blockrefxxnewobj14;
reg [63:0] T403_LRU_Lookup_0_22_V_1;
reg [31:0] T403_LRU_Lookup_0_22_V_0;
reg [31:0] LRU_Lookup_CZ_0_1_blockrefxxnewobj12;
reg [63:0] T403_LRU_Lookup_0_18_V_1;
reg [31:0] T403_LRU_Lookup_0_18_V_0;
reg [63:0] T403_LRU_Cache_0_15_V_0;
reg [63:0] T403_HashCAM_Write_0_6_V_0;
reg [63:0] T403_LRU_Cache_0_10_V_0;
reg [63:0] T403_HashCAM_Read_0_7_V_0;
reg [31:0] LRU_Lookup_CZ_0_1_blockrefxxnewobj10;
reg [63:0] T403_LRU_Lookup_0_4_V_1;
reg [31:0] T403_LRU_Lookup_0_4_V_0;
reg [31:0] LRU_T403_Main_T403_Main_V_0;
wire [31:0] ktop16;
wire [31:0] ktop14;
reg System_BitConverter_IsLittleEndian;
wire [31:0] ktop12;
reg [63:0] KiwiSystem_Kiwi_tnow;
reg [31:0] KiwiSystem_Kiwi_old_pausemode_value;
wire [31:0] ktop10;
reg A_BOOL_CC_SCALbx16_matched;
reg A_BOOL_CC_SCALbx18_matched;
reg A_BOOL_CC_SCALbx20_matched;
reg [63:0] A_64_US_CC_SCALbx16_result;
reg [63:0] A_64_US_CC_SCALbx18_result;
reg [63:0] A_64_US_CC_SCALbx20_result;
reg [5:0] xpc10;
reg xpc12;
reg xpc14;
always @(posedge clk ) begin
if (reset) begin
T403_LRU_Lookup_0_4_V_0 <= 32'd0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj10 <= 32'd0;
KiwiSystem_Kiwi_tnow <= 64'd0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'd0;
System_BitConverter_IsLittleEndian <= 32'd0;
A_BOOL_CC_SCALbx20_matched <= 32'd0;
T403_LRU_Lookup_0_4_V_1 <= 64'd0;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'd0;
T403_LRU_Cache_0_10_V_0 <= 64'd0;
NaughtyQ_idx_out_nv <= 64'd0;
T403_LRU_Cache_0_15_V_0 <= 64'd0;
HashCAM_is_full <= 32'd0;
T403_HashCAM_Write_0_6_V_0 <= 64'd0;
T403_LRU_Lookup_0_18_V_0 <= 32'd0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj12 <= 32'd0;
A_BOOL_CC_SCALbx18_matched <= 32'd0;
T403_LRU_Lookup_0_18_V_1 <= 64'd0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'd0;
T403_HashCAM_Read_0_7_V_0 <= 64'd0;
HashCAM_matched <= 32'd0;
A_BOOL_CC_SCALbx16_matched <= 32'd0;
T403_LRU_Lookup_0_22_V_1 <= 64'd0;
NaughtyQ_data_out_nv <= 64'd0;
A_64_US_CC_SCALbx16_result <= 64'd0;
HC_write_enable <= 32'd0;
HC_value_in <= 32'd0;
NQ_data_in <= 32'd0;
NQ_enable <= 32'd0;
NQ_idx_in <= 32'd0;
NQ_command <= 32'd0;
xpc10 <= 32'd0;
HC_lookup_enable <= 32'd0;
HC_key_in <= 32'd0;
xpc12 <= 32'd0;
xpc14 <= 32'd0;
end
else begin
if (!HashCAM_matched && (xpc10==6'sd31)) $finish(32'sd0);
if ((xpc10==6'sd36)) $finish(32'sd0);
if (NQ_ready)
case (xpc10)
6'sd4: begin
xpc10 <= 6'sd5;
NQ_enable <= 1'h0;
end
6'sd5: xpc10 <= 6'sd58;
6'sd6: xpc10 <= 6'sd7;
6'sd8: begin
xpc10 <= 6'sd56;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= NaughtyQ_data_out_nv;
end
6'sd9: xpc10 <= 6'sd10;
6'sd14: xpc10 <= 6'sd52;
6'sd15: xpc10 <= 6'sd16;
6'sd24: begin
xpc10 <= 6'sd25;
NQ_enable <= 1'h0;
end
6'sd25: xpc10 <= 6'sd44;
6'sd26: xpc10 <= 6'sd27;
6'sd32: begin
xpc10 <= 6'sd33;
NQ_enable <= 1'h0;
end
6'sd33: xpc10 <= 6'sd38;
6'sd34: xpc10 <= 6'sd35;
6'sd37: xpc10 <= 6'sd35;
6'sd39: begin
xpc10 <= 6'sd33;
NQ_enable <= 1'h0;
end
6'sd43: xpc10 <= 6'sd27;
6'sd45: begin
xpc10 <= 6'sd25;
NQ_enable <= 1'h0;
end
6'sd51: xpc10 <= 6'sd16;
6'sd55: xpc10 <= 6'sd10;
6'sd57: xpc10 <= 6'sd7;
6'sd59: begin
xpc10 <= 6'sd5;
NQ_enable <= 1'h0;
end
endcase
else
case (xpc10)
6'sd4: xpc10 <= 6'sd59;
6'sd5: begin
xpc10 <= 6'sd6;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;
NQ_command <= 8'h3;
end
6'sd6: xpc10 <= 6'sd57;
6'sd8: begin
xpc10 <= 6'sd9;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h2;
NQ_command <= 8'h1;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= NaughtyQ_data_out_nv;
end
6'sd9: xpc10 <= 6'sd55;
6'sd14: begin
xpc10 <= 6'sd15;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h14;
NQ_command <= 8'h1;
end
6'sd15: xpc10 <= 6'sd51;
6'sd24: xpc10 <= 6'sd45;
6'sd25: begin
xpc10 <= 6'sd26;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;
NQ_command <= 8'h3;
end
6'sd26: xpc10 <= 6'sd43;
6'sd32: xpc10 <= 6'sd39;
6'sd33: begin
xpc10 <= 6'sd34;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;
NQ_command <= 8'h3;
end
6'sd34: xpc10 <= 6'sd37;
6'sd38: begin
xpc10 <= 6'sd34;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;
NQ_command <= 8'h3;
end
6'sd40: begin
xpc10 <= 6'sd32;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;
NQ_command <= 8'h2;
end
6'sd44: begin
xpc10 <= 6'sd26;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;
NQ_command <= 8'h3;
end
6'sd46: begin
xpc10 <= 6'sd24;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;
NQ_command <= 8'h2;
end
6'sd52: begin
xpc10 <= 6'sd15;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h14;
NQ_command <= 8'h1;
end
6'sd56: begin
xpc10 <= 6'sd9;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h2;
NQ_command <= 8'h1;
end
6'sd58: begin
xpc10 <= 6'sd6;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;
NQ_command <= 8'h3;
end
6'sd60: begin
xpc10 <= 6'sd4;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;
NQ_command <= 8'h2;
end
endcase
if (HC_lookup_ready)
case (xpc10)
6'sd0: begin
xpc10 <= 6'sd62;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_4_V_1 <= 64'h0;
T403_LRU_Lookup_0_4_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj10 <= 32'd0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
6'sd1: xpc10 <= 6'sd2;
6'sd20: begin
xpc10 <= 6'sd48;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_18_V_1 <= 64'h0;
T403_LRU_Lookup_0_18_V_0 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj12 <= 32'd0;
end
6'sd21: xpc10 <= 6'sd22;
6'sd28: begin
xpc10 <= 6'sd42;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= NaughtyQ_data_out_nv;
end
6'sd29: xpc10 <= 6'sd30;
6'sd41: xpc10 <= 6'sd30;
6'sd47: xpc10 <= 6'sd22;
6'sd61: xpc10 <= 6'sd2;
endcase
else
case (xpc10)
6'sd0: begin
xpc10 <= 6'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_4_V_1 <= 64'h0;
T403_LRU_Lookup_0_4_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj10 <= 32'd0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
6'sd1: xpc10 <= 6'sd61;
6'sd20: begin
xpc10 <= 6'sd21;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_18_V_1 <= 64'h0;
T403_LRU_Lookup_0_18_V_0 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj12 <= 32'd0;
end
6'sd21: xpc10 <= 6'sd47;
6'sd28: begin
xpc10 <= 6'sd29;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= NaughtyQ_data_out_nv;
end
6'sd29: xpc10 <= 6'sd41;
6'sd42: begin
xpc10 <= 6'sd29;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
end
6'sd48: begin
xpc10 <= 6'sd21;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
end
6'sd62: begin
xpc10 <= 6'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
end
endcase
if ((xpc10==6'sd23)) begin
if (HashCAM_matched && !NQ_ready) begin
xpc10 <= 6'sd24;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;
NQ_command <= 8'h2;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HC_lookup_ready && !HashCAM_matched) begin
xpc10 <= 6'sd29;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd46;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (HC_lookup_ready && !HashCAM_matched) begin
xpc10 <= 6'sd42;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
end
if (HC_write_ready)
case (xpc10)
6'sd11: begin
xpc10 <= 6'sd54;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_10_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd12: xpc10 <= 6'sd13;
6'sd17: begin
xpc10 <= 6'sd50;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_15_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd18: xpc10 <= 6'sd19;
6'sd49: xpc10 <= 6'sd19;
6'sd53: xpc10 <= 6'sd13;
endcase
else
case (xpc10)
6'sd11: begin
xpc10 <= 6'sd12;
HC_write_enable <= 1'h1;
HC_value_in <= NaughtyQ_idx_out_nv;
HC_key_in <= 64'hd;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_10_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd12: xpc10 <= 6'sd53;
6'sd17: begin
xpc10 <= 6'sd18;
HC_write_enable <= 1'h1;
HC_value_in <= NaughtyQ_idx_out_nv;
HC_key_in <= 64'hd;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_15_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd18: xpc10 <= 6'sd49;
6'sd50: begin
xpc10 <= 6'sd18;
HC_write_enable <= 1'h1;
HC_value_in <= T403_LRU_Cache_0_15_V_0;
HC_key_in <= 64'hd;
end
6'sd54: begin
xpc10 <= 6'sd12;
HC_write_enable <= 1'h1;
HC_value_in <= T403_LRU_Cache_0_10_V_0;
HC_key_in <= 64'hd;
end
endcase
if ((xpc10==6'sd3)) begin
if (HashCAM_matched && !NQ_ready) begin
xpc10 <= 6'sd4;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;
NQ_command <= 8'h2;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd60;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HashCAM_matched && !NQ_ready) begin
xpc10 <= 6'sd9;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h2;
NQ_command <= 8'h1;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd56;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
end
if (HashCAM_matched && !NQ_ready && (xpc10==6'sd31)) begin
xpc10 <= 6'sd32;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;
NQ_command <= 8'h2;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_22_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
case (xpc10)
6'sd2: begin
xpc10 <= 6'sd3;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd7: begin
xpc10 <= 6'sd8;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
end
6'sd10: begin
xpc10 <= 6'sd11;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);
end
6'sd13: begin
xpc10 <= 6'sd14;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);
T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd16: begin
xpc10 <= 6'sd17;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);
end
6'sd19: begin
xpc10 <= 6'sd20;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);
T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd22: begin
xpc10 <= 6'sd23;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd27: begin
xpc10 <= 6'sd28;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
end
6'sd30: begin
xpc10 <= 6'sd31;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd31: begin
if (HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd40;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_22_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HashCAM_matched) begin
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_22_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
end
6'sd35: begin
xpc10 <= 6'sd36;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
end
6'sd36: A_64_US_CC_SCALbx16_result <= NaughtyQ_data_out_nv;
endcase
if ((xpc14==1'sd0)) xpc14 <= 1'sd1;
if ((xpc12==1'sd0)) xpc12 <= 1'sd1;
end
end
endmodule | module LRU( output reg NQ_enable,
input NQ_ready,
input NQ_crashed,
output reg [3:0] NQ_command,
input [3:0] NQ_idx_out,
input [7:0] NQ_data_out,
output reg [3:0] NQ_idx_in,
output reg [7:0] NQ_data_in,
output reg HC_write_enable,
input HC_write_ready,
output reg HC_lookup_enable,
input HC_lookup_ready,
input HC_match,
input HC_full,
output reg [15:0] HC_key_in,
output reg [7:0] HC_value_in,
input [7:0] HC_value_out,
input clk,
input reset); |
function rtl_unsigned_bitextract0;
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[0:0]);
endfunction
function [63:0] rtl_unsigned_extend1;
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction
reg [63:0] NaughtyQ_idx_out_nv;
reg [63:0] NaughtyQ_data_out_nv;
reg HashCAM_matched;
reg HashCAM_is_full;
wire [31:0] ktop20;
wire [31:0] ktop18;
reg [31:0] LRU_Lookup_CZ_0_1_blockrefxxnewobj14;
reg [63:0] T403_LRU_Lookup_0_22_V_1;
reg [31:0] T403_LRU_Lookup_0_22_V_0;
reg [31:0] LRU_Lookup_CZ_0_1_blockrefxxnewobj12;
reg [63:0] T403_LRU_Lookup_0_18_V_1;
reg [31:0] T403_LRU_Lookup_0_18_V_0;
reg [63:0] T403_LRU_Cache_0_15_V_0;
reg [63:0] T403_HashCAM_Write_0_6_V_0;
reg [63:0] T403_LRU_Cache_0_10_V_0;
reg [63:0] T403_HashCAM_Read_0_7_V_0;
reg [31:0] LRU_Lookup_CZ_0_1_blockrefxxnewobj10;
reg [63:0] T403_LRU_Lookup_0_4_V_1;
reg [31:0] T403_LRU_Lookup_0_4_V_0;
reg [31:0] LRU_T403_Main_T403_Main_V_0;
wire [31:0] ktop16;
wire [31:0] ktop14;
reg System_BitConverter_IsLittleEndian;
wire [31:0] ktop12;
reg [63:0] KiwiSystem_Kiwi_tnow;
reg [31:0] KiwiSystem_Kiwi_old_pausemode_value;
wire [31:0] ktop10;
reg A_BOOL_CC_SCALbx16_matched;
reg A_BOOL_CC_SCALbx18_matched;
reg A_BOOL_CC_SCALbx20_matched;
reg [63:0] A_64_US_CC_SCALbx16_result;
reg [63:0] A_64_US_CC_SCALbx18_result;
reg [63:0] A_64_US_CC_SCALbx20_result;
reg [5:0] xpc10;
reg xpc12;
reg xpc14;
always @(posedge clk ) begin
if (reset) begin
T403_LRU_Lookup_0_4_V_0 <= 32'd0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj10 <= 32'd0;
KiwiSystem_Kiwi_tnow <= 64'd0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'd0;
System_BitConverter_IsLittleEndian <= 32'd0;
A_BOOL_CC_SCALbx20_matched <= 32'd0;
T403_LRU_Lookup_0_4_V_1 <= 64'd0;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'd0;
T403_LRU_Cache_0_10_V_0 <= 64'd0;
NaughtyQ_idx_out_nv <= 64'd0;
T403_LRU_Cache_0_15_V_0 <= 64'd0;
HashCAM_is_full <= 32'd0;
T403_HashCAM_Write_0_6_V_0 <= 64'd0;
T403_LRU_Lookup_0_18_V_0 <= 32'd0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj12 <= 32'd0;
A_BOOL_CC_SCALbx18_matched <= 32'd0;
T403_LRU_Lookup_0_18_V_1 <= 64'd0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'd0;
T403_HashCAM_Read_0_7_V_0 <= 64'd0;
HashCAM_matched <= 32'd0;
A_BOOL_CC_SCALbx16_matched <= 32'd0;
T403_LRU_Lookup_0_22_V_1 <= 64'd0;
NaughtyQ_data_out_nv <= 64'd0;
A_64_US_CC_SCALbx16_result <= 64'd0;
HC_write_enable <= 32'd0;
HC_value_in <= 32'd0;
NQ_data_in <= 32'd0;
NQ_enable <= 32'd0;
NQ_idx_in <= 32'd0;
NQ_command <= 32'd0;
xpc10 <= 32'd0;
HC_lookup_enable <= 32'd0;
HC_key_in <= 32'd0;
xpc12 <= 32'd0;
xpc14 <= 32'd0;
end
else begin
if (!HashCAM_matched && (xpc10==6'sd31)) $finish(32'sd0);
if ((xpc10==6'sd36)) $finish(32'sd0);
if (NQ_ready)
case (xpc10)
6'sd4: begin
xpc10 <= 6'sd5;
NQ_enable <= 1'h0;
end
6'sd5: xpc10 <= 6'sd58;
6'sd6: xpc10 <= 6'sd7;
6'sd8: begin
xpc10 <= 6'sd56;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= NaughtyQ_data_out_nv;
end
6'sd9: xpc10 <= 6'sd10;
6'sd14: xpc10 <= 6'sd52;
6'sd15: xpc10 <= 6'sd16;
6'sd24: begin
xpc10 <= 6'sd25;
NQ_enable <= 1'h0;
end
6'sd25: xpc10 <= 6'sd44;
6'sd26: xpc10 <= 6'sd27;
6'sd32: begin
xpc10 <= 6'sd33;
NQ_enable <= 1'h0;
end
6'sd33: xpc10 <= 6'sd38;
6'sd34: xpc10 <= 6'sd35;
6'sd37: xpc10 <= 6'sd35;
6'sd39: begin
xpc10 <= 6'sd33;
NQ_enable <= 1'h0;
end
6'sd43: xpc10 <= 6'sd27;
6'sd45: begin
xpc10 <= 6'sd25;
NQ_enable <= 1'h0;
end
6'sd51: xpc10 <= 6'sd16;
6'sd55: xpc10 <= 6'sd10;
6'sd57: xpc10 <= 6'sd7;
6'sd59: begin
xpc10 <= 6'sd5;
NQ_enable <= 1'h0;
end
endcase
else
case (xpc10)
6'sd4: xpc10 <= 6'sd59;
6'sd5: begin
xpc10 <= 6'sd6;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;
NQ_command <= 8'h3;
end
6'sd6: xpc10 <= 6'sd57;
6'sd8: begin
xpc10 <= 6'sd9;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h2;
NQ_command <= 8'h1;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= NaughtyQ_data_out_nv;
end
6'sd9: xpc10 <= 6'sd55;
6'sd14: begin
xpc10 <= 6'sd15;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h14;
NQ_command <= 8'h1;
end
6'sd15: xpc10 <= 6'sd51;
6'sd24: xpc10 <= 6'sd45;
6'sd25: begin
xpc10 <= 6'sd26;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;
NQ_command <= 8'h3;
end
6'sd26: xpc10 <= 6'sd43;
6'sd32: xpc10 <= 6'sd39;
6'sd33: begin
xpc10 <= 6'sd34;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;
NQ_command <= 8'h3;
end
6'sd34: xpc10 <= 6'sd37;
6'sd38: begin
xpc10 <= 6'sd34;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;
NQ_command <= 8'h3;
end
6'sd40: begin
xpc10 <= 6'sd32;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;
NQ_command <= 8'h2;
end
6'sd44: begin
xpc10 <= 6'sd26;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;
NQ_command <= 8'h3;
end
6'sd46: begin
xpc10 <= 6'sd24;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;
NQ_command <= 8'h2;
end
6'sd52: begin
xpc10 <= 6'sd15;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h14;
NQ_command <= 8'h1;
end
6'sd56: begin
xpc10 <= 6'sd9;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h2;
NQ_command <= 8'h1;
end
6'sd58: begin
xpc10 <= 6'sd6;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;
NQ_command <= 8'h3;
end
6'sd60: begin
xpc10 <= 6'sd4;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;
NQ_command <= 8'h2;
end
endcase
if (HC_lookup_ready)
case (xpc10)
6'sd0: begin
xpc10 <= 6'sd62;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_4_V_1 <= 64'h0;
T403_LRU_Lookup_0_4_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj10 <= 32'd0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
6'sd1: xpc10 <= 6'sd2;
6'sd20: begin
xpc10 <= 6'sd48;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_18_V_1 <= 64'h0;
T403_LRU_Lookup_0_18_V_0 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj12 <= 32'd0;
end
6'sd21: xpc10 <= 6'sd22;
6'sd28: begin
xpc10 <= 6'sd42;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= NaughtyQ_data_out_nv;
end
6'sd29: xpc10 <= 6'sd30;
6'sd41: xpc10 <= 6'sd30;
6'sd47: xpc10 <= 6'sd22;
6'sd61: xpc10 <= 6'sd2;
endcase
else
case (xpc10)
6'sd0: begin
xpc10 <= 6'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_4_V_1 <= 64'h0;
T403_LRU_Lookup_0_4_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj10 <= 32'd0;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
HashCAM_is_full <= 1'h0;
HashCAM_matched <= 1'h0;
end
6'sd1: xpc10 <= 6'sd61;
6'sd20: begin
xpc10 <= 6'sd21;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_18_V_1 <= 64'h0;
T403_LRU_Lookup_0_18_V_0 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj12 <= 32'd0;
end
6'sd21: xpc10 <= 6'sd47;
6'sd28: begin
xpc10 <= 6'sd29;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= NaughtyQ_data_out_nv;
end
6'sd29: xpc10 <= 6'sd41;
6'sd42: begin
xpc10 <= 6'sd29;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
end
6'sd48: begin
xpc10 <= 6'sd21;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
end
6'sd62: begin
xpc10 <= 6'sd1;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
end
endcase
if ((xpc10==6'sd23)) begin
if (HashCAM_matched && !NQ_ready) begin
xpc10 <= 6'sd24;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;
NQ_command <= 8'h2;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HC_lookup_ready && !HashCAM_matched) begin
xpc10 <= 6'sd29;
HC_lookup_enable <= 1'h1;
HC_key_in <= 64'hd;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd46;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (HC_lookup_ready && !HashCAM_matched) begin
xpc10 <= 6'sd42;
T403_HashCAM_Read_0_7_V_0 <= 64'h0;
T403_LRU_Lookup_0_22_V_1 <= 64'h0;
T403_LRU_Lookup_0_22_V_0 <= 32'd0;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= 1'h0;
LRU_Lookup_CZ_0_1_blockrefxxnewobj14 <= 32'd0;
A_64_US_CC_SCALbx18_result <= 64'h0;
A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_18_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
end
if (HC_write_ready)
case (xpc10)
6'sd11: begin
xpc10 <= 6'sd54;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_10_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd12: xpc10 <= 6'sd13;
6'sd17: begin
xpc10 <= 6'sd50;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_15_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd18: xpc10 <= 6'sd19;
6'sd49: xpc10 <= 6'sd19;
6'sd53: xpc10 <= 6'sd13;
endcase
else
case (xpc10)
6'sd11: begin
xpc10 <= 6'sd12;
HC_write_enable <= 1'h1;
HC_value_in <= NaughtyQ_idx_out_nv;
HC_key_in <= 64'hd;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_10_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd12: xpc10 <= 6'sd53;
6'sd17: begin
xpc10 <= 6'sd18;
HC_write_enable <= 1'h1;
HC_value_in <= NaughtyQ_idx_out_nv;
HC_key_in <= 64'hd;
T403_HashCAM_Write_0_6_V_0 <= 64'h0;
T403_LRU_Cache_0_15_V_0 <= NaughtyQ_idx_out_nv;
end
6'sd18: xpc10 <= 6'sd49;
6'sd50: begin
xpc10 <= 6'sd18;
HC_write_enable <= 1'h1;
HC_value_in <= T403_LRU_Cache_0_15_V_0;
HC_key_in <= 64'hd;
end
6'sd54: begin
xpc10 <= 6'sd12;
HC_write_enable <= 1'h1;
HC_value_in <= T403_LRU_Cache_0_10_V_0;
HC_key_in <= 64'hd;
end
endcase
if ((xpc10==6'sd3)) begin
if (HashCAM_matched && !NQ_ready) begin
xpc10 <= 6'sd4;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;
NQ_command <= 8'h2;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd60;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HashCAM_matched && !NQ_ready) begin
xpc10 <= 6'sd9;
NQ_enable <= 1'h1;
NQ_data_in <= 64'h2;
NQ_command <= 8'h1;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd56;
LRU_T403_Main_T403_Main_V_0 <= 32'd0;
A_64_US_CC_SCALbx20_result <= 64'h0;
A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_4_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
end
if (HashCAM_matched && !NQ_ready && (xpc10==6'sd31)) begin
xpc10 <= 6'sd32;
NQ_enable <= 1'h1;
NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;
NQ_command <= 8'h2;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_22_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
case (xpc10)
6'sd2: begin
xpc10 <= 6'sd3;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd7: begin
xpc10 <= 6'sd8;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
end
6'sd10: begin
xpc10 <= 6'sd11;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);
end
6'sd13: begin
xpc10 <= 6'sd14;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);
T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd16: begin
xpc10 <= 6'sd17;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);
end
6'sd19: begin
xpc10 <= 6'sd20;
HC_write_enable <= 1'h0;
HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);
T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd22: begin
xpc10 <= 6'sd23;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd27: begin
xpc10 <= 6'sd28;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
end
6'sd30: begin
xpc10 <= 6'sd31;
HC_lookup_enable <= 1'h0;
T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);
HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);
end
6'sd31: begin
if (HashCAM_matched && NQ_ready) begin
xpc10 <= 6'sd40;
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_22_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
if (!HashCAM_matched) begin
A_64_US_CC_SCALbx16_result <= 64'h0;
A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);
T403_LRU_Lookup_0_22_V_1 <= T403_HashCAM_Read_0_7_V_0;
end
end
6'sd35: begin
xpc10 <= 6'sd36;
NQ_enable <= 1'h0;
NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);
end
6'sd36: A_64_US_CC_SCALbx16_result <= NaughtyQ_data_out_nv;
endcase
if ((xpc14==1'sd0)) xpc14 <= 1'sd1;
if ((xpc12==1'sd0)) xpc12 <= 1'sd1;
end
end
endmodule | 3 |
142,077 | data/full_repos/permissive/97045669/lib/LRU.v | 97,045,669 | LRU.v | v | 824 | 325 | [] | [] | [] | [(11, 667)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:85: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:86: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HashCAM_is_full <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:103: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HashCAM_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:104: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:108: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:109: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_value_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:110: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_data_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:111: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:112: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_idx_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:113: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_command <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:114: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:115: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_lookup_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:116: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_key_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:117: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:118: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc14 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:196: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:197: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:205: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:206: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:216: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h14\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h14;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:217: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:227: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:228: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:238: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:239: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:247: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:248: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:254: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:255: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:261: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:262: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:268: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:269: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:275: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h14\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h14;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:282: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:283: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:289: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:297: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:355: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:374: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:388: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:403: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:409: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:415: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:422: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:423: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:425: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:431: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:439: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:445: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:457: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'NaughtyQ_idx_out_nv\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= NaughtyQ_idx_out_nv;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:489: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:499: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'NaughtyQ_idx_out_nv\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= NaughtyQ_idx_out_nv;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:500: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:510: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Cache_0_15_V_0\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= T403_LRU_Cache_0_15_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:511: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:517: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Cache_0_10_V_0\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= T403_LRU_Cache_0_10_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:518: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:525: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:526: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:528: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:534: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:540: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:541: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:544: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:551: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:558: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:559: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:561: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:569: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:570: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:576: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:582: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:583: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_idx_out\' generates 4 bits.\n : ... In instance LRU\n NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:589: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance LRU\n HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:590: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:591: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:597: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:598: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_idx_out\' generates 4 bits.\n : ... In instance LRU\n NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:604: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance LRU\n HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:605: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:606: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:612: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:613: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:619: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:625: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:626: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:633: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:638: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:646: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 96 warning(s)\n' | 313,017 | function | function rtl_unsigned_bitextract0;
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[0:0]);
endfunction | function rtl_unsigned_bitextract0; |
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[0:0]);
endfunction | 3 |
142,078 | data/full_repos/permissive/97045669/lib/LRU.v | 97,045,669 | LRU.v | v | 824 | 325 | [] | [] | [] | [(11, 667)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:85: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:86: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HashCAM_is_full <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:103: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HashCAM_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:104: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:108: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:109: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_value_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:110: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_data_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:111: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:112: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_idx_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:113: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n NQ_command <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:114: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:115: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_lookup_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:116: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n HC_key_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:117: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:118: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance LRU\n xpc14 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:196: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:197: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:205: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:206: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:216: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h14\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h14;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:217: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:227: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:228: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:238: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:239: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:247: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:248: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:254: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_22_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_22_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:255: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:261: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:262: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:268: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_18_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_18_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:269: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:275: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h14\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h14;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:282: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:283: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:289: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Lookup_0_4_V_1\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_LRU_Lookup_0_4_V_1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:297: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:355: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:374: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:388: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:403: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:409: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:415: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:422: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:423: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:425: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:431: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:439: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:445: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:457: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx18_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'NaughtyQ_idx_out_nv\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= NaughtyQ_idx_out_nv;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:489: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:499: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'NaughtyQ_idx_out_nv\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= NaughtyQ_idx_out_nv;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:500: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:510: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Cache_0_15_V_0\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= T403_LRU_Cache_0_15_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:511: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:517: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_LRU_Cache_0_10_V_0\' generates 64 bits.\n : ... In instance LRU\n HC_value_in <= T403_LRU_Cache_0_10_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:518: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hd\' generates 64 bits.\n : ... In instance LRU\n HC_key_in <= 64\'hd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:525: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:526: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:528: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:534: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:540: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h2\' generates 64 bits.\n : ... In instance LRU\n NQ_data_in <= 64\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:541: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:544: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:551: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx20_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:558: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'T403_HashCAM_Read_0_7_V_0\' generates 64 bits.\n : ... In instance LRU\n NQ_idx_in <= T403_HashCAM_Read_0_7_V_0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:559: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance LRU\n NQ_command <= 8\'h2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:561: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:569: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:570: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:576: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:582: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:583: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_idx_out\' generates 4 bits.\n : ... In instance LRU\n NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:589: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance LRU\n HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:590: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:591: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:597: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:598: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_idx_out\' generates 4 bits.\n : ... In instance LRU\n NaughtyQ_idx_out_nv <= rtl_unsigned_extend1(NQ_idx_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:604: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_full\' generates 1 bits.\n : ... In instance LRU\n HashCAM_is_full <= rtl_unsigned_bitextract0(HC_full);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:605: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Write_0_6_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:606: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:612: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:613: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:619: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:625: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_value_out\' generates 8 bits.\n : ... In instance LRU\n T403_HashCAM_Read_0_7_V_0 <= rtl_unsigned_extend1(HC_value_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:626: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HC_match\' generates 1 bits.\n : ... In instance LRU\n HashCAM_matched <= rtl_unsigned_bitextract0(HC_match);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:633: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:638: Operator FUNCREF \'rtl_unsigned_bitextract0\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'HashCAM_matched\' generates 1 bits.\n : ... In instance LRU\n A_BOOL_CC_SCALbx16_matched <= rtl_unsigned_bitextract0(HashCAM_matched);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/LRU.v:646: Operator FUNCREF \'rtl_unsigned_extend1\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'NQ_data_out\' generates 8 bits.\n : ... In instance LRU\n NaughtyQ_data_out_nv <= rtl_unsigned_extend1(NQ_data_out);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 96 warning(s)\n' | 313,017 | function | function [63:0] rtl_unsigned_extend1;
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction | function [63:0] rtl_unsigned_extend1; |
input [31:0] arg;
rtl_unsigned_extend1 = { 32'b0, arg[31:0] };
endfunction | 3 |
142,079 | data/full_repos/permissive/97045669/lib/lru_test.v | 97,045,669 | lru_test.v | v | 111 | 85 | [] | [] | [] | [(15, 110)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/97045669/lib/lru_test.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97045669/lib/lru_test.v:100: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("lru_test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97045669/lib/lru_test.v:101: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, lru_test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/97045669/lib/lru_test.v:103: Unsupported: Ignoring delay on this delayed statement.\n #16\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97045669/lib/lru_test.v:105: Unsupported: Ignoring delay on this delayed statement.\n #4\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,018 | module | module lru_test;
reg clk = 0;
always #1 clk = !clk;
reg reset;
localparam NQ_DEPTH_IDX_WIDTH = 2;
localparam KEY_WIDTH_IN_OCTETS = 2;
localparam VALUE_WIDTH_IN_BITS = 8;
localparam MAX_BUCKET_SIZE = 1;
wire HC_lookup_ready;
wire HC_write_ready;
wire HC_match;
wire HC_full;
wire [VALUE_WIDTH_IN_BITS - 1 : 0] HC_value_out;
wire HC_lookup_enable;
wire HC_write_enable;
wire [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] HC_key_in;
wire [VALUE_WIDTH_IN_BITS - 1 : 0] HC_value_in;
wire NQ_ready;
wire NQ_crashed;
wire [NQ_DEPTH_IDX_WIDTH-1:0] NQ_idx_out;
wire [VALUE_WIDTH_IN_BITS-1:0] NQ_data_out;
wire [`NQ_COMMAND_WIDTH:0] NQ_command;
wire NQ_enable;
wire [NQ_DEPTH_IDX_WIDTH-1:0] NQ_idx_in;
wire [VALUE_WIDTH_IN_BITS-1:0] NQ_data_in;
HashCAM
#(.KEY_WIDTH_IN_OCTETS(KEY_WIDTH_IN_OCTETS),
.VALUE_WIDTH_IN_BITS(VALUE_WIDTH_IN_BITS),
.MAX_BUCKET_SIZE(MAX_BUCKET_SIZE))
hc
(.reset(reset),
.lookup_enable(HC_lookup_enable),
.lookup_ready(HC_lookup_ready),
.write_enable(HC_write_enable),
.write_ready(HC_write_ready),
.match(HC_match),
.full(HC_full),
.key_in(HC_key_in),
.value_in(HC_value_in),
.value_out(HC_value_out));
NaughtyQ
#(.IDX_WIDTH(NQ_DEPTH_IDX_WIDTH),
.DATA_WIDTH(VALUE_WIDTH_IN_BITS))
nq
(.clock(clk),
.reset(reset),
.command(NQ_command),
.enable(NQ_enable),
.ready(NQ_ready),
.crashed(NQ_crashed),
.idx_in(NQ_idx_in),
.data_in(NQ_data_in),
.idx_out(NQ_idx_out),
.data_out(NQ_data_out));
LRU lru
(.NQ_enable(NQ_enable),
.NQ_ready(NQ_ready),
.NQ_crashed(NQ_crashed),
.NQ_command(NQ_command),
.NQ_idx_out(NQ_idx_out),
.NQ_data_out(NQ_data_out),
.NQ_idx_in(NQ_idx_in),
.NQ_data_in(NQ_data_in),
.HC_write_enable(HC_write_enable),
.HC_write_ready(HC_write_ready),
.HC_lookup_enable(HC_lookup_enable),
.HC_lookup_ready(HC_lookup_ready),
.HC_match(HC_match),
.HC_full(HC_full),
.HC_key_in(HC_key_in),
.HC_value_in(HC_value_in),
.HC_value_out(HC_value_out),
.clk(clk),
.reset(reset));
initial begin
$dumpfile("lru_test.vcd");
$dumpvars(0, lru_test);
#16
reset = 1;
#4
reset = 0;
end
endmodule | module lru_test; |
reg clk = 0;
always #1 clk = !clk;
reg reset;
localparam NQ_DEPTH_IDX_WIDTH = 2;
localparam KEY_WIDTH_IN_OCTETS = 2;
localparam VALUE_WIDTH_IN_BITS = 8;
localparam MAX_BUCKET_SIZE = 1;
wire HC_lookup_ready;
wire HC_write_ready;
wire HC_match;
wire HC_full;
wire [VALUE_WIDTH_IN_BITS - 1 : 0] HC_value_out;
wire HC_lookup_enable;
wire HC_write_enable;
wire [(KEY_WIDTH_IN_OCTETS * 8) - 1 : 0] HC_key_in;
wire [VALUE_WIDTH_IN_BITS - 1 : 0] HC_value_in;
wire NQ_ready;
wire NQ_crashed;
wire [NQ_DEPTH_IDX_WIDTH-1:0] NQ_idx_out;
wire [VALUE_WIDTH_IN_BITS-1:0] NQ_data_out;
wire [`NQ_COMMAND_WIDTH:0] NQ_command;
wire NQ_enable;
wire [NQ_DEPTH_IDX_WIDTH-1:0] NQ_idx_in;
wire [VALUE_WIDTH_IN_BITS-1:0] NQ_data_in;
HashCAM
#(.KEY_WIDTH_IN_OCTETS(KEY_WIDTH_IN_OCTETS),
.VALUE_WIDTH_IN_BITS(VALUE_WIDTH_IN_BITS),
.MAX_BUCKET_SIZE(MAX_BUCKET_SIZE))
hc
(.reset(reset),
.lookup_enable(HC_lookup_enable),
.lookup_ready(HC_lookup_ready),
.write_enable(HC_write_enable),
.write_ready(HC_write_ready),
.match(HC_match),
.full(HC_full),
.key_in(HC_key_in),
.value_in(HC_value_in),
.value_out(HC_value_out));
NaughtyQ
#(.IDX_WIDTH(NQ_DEPTH_IDX_WIDTH),
.DATA_WIDTH(VALUE_WIDTH_IN_BITS))
nq
(.clock(clk),
.reset(reset),
.command(NQ_command),
.enable(NQ_enable),
.ready(NQ_ready),
.crashed(NQ_crashed),
.idx_in(NQ_idx_in),
.data_in(NQ_data_in),
.idx_out(NQ_idx_out),
.data_out(NQ_data_out));
LRU lru
(.NQ_enable(NQ_enable),
.NQ_ready(NQ_ready),
.NQ_crashed(NQ_crashed),
.NQ_command(NQ_command),
.NQ_idx_out(NQ_idx_out),
.NQ_data_out(NQ_data_out),
.NQ_idx_in(NQ_idx_in),
.NQ_data_in(NQ_data_in),
.HC_write_enable(HC_write_enable),
.HC_write_ready(HC_write_ready),
.HC_lookup_enable(HC_lookup_enable),
.HC_lookup_ready(HC_lookup_ready),
.HC_match(HC_match),
.HC_full(HC_full),
.HC_key_in(HC_key_in),
.HC_value_in(HC_value_in),
.HC_value_out(HC_value_out),
.clk(clk),
.reset(reset));
initial begin
$dumpfile("lru_test.vcd");
$dumpvars(0, lru_test);
#16
reset = 1;
#4
reset = 0;
end
endmodule | 3 |
142,087 | data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v | 97,045,669 | PearsonHash_KL_Test.v | v | 662 | 339 | [] | [] | [] | [(11, 547)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:68: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:73: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:74: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:76: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:77: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:78: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:79: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:80: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_block_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:82: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_encipher_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:83: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:84: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_key_byte_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:85: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_idx_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:86: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_init_hash_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:88: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_data_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:449: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:455: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:461: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:467: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:478: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:509: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:515: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:521: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 27 warning(s)\n' | 313,025 | module | module PearsonHash_KL_Test( output [7:0] PH_block_hash,
input PH_block_ready,
output reg PH_block_enable,
output reg [63:0] PH_block_in,
output [7:0] PH_cipher_out,
input PH_encipher_ready,
output reg PH_encipher_enable,
input PH_write_ready,
output reg PH_write_enable,
output reg [7:0] PH_key_byte_in,
output reg [7:0] PH_idx_in,
input PH_init_hash_ready,
output reg PH_init_hash_enable,
output reg [7:0] PH_data_in,
input clk,
input reset);
function [7:0] rtl_unsigned_bitextract2;
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[7:0]);
endfunction
function [7:0] rtl_unsigned_bitextract0;
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[7:0]);
endfunction
function [31:0] rtl_unsigned_extend1;
input [7:0] arg;
rtl_unsigned_extend1 = { 24'b0, arg[7:0] };
endfunction
reg [7:0] T402_PearsonHash_BlockHash_6_14_V_0;
reg [7:0] T402_PearsonHash_BlockHash_6_10_V_0;
reg [7:0] T402_PearsonHash_BlockHash_6_6_V_0;
reg [7:0] T402_PearsonHash_BlockHash_6_2_V_0;
reg [7:0] T402_PearsonHash_StreamHash_4_3_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_16_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_13_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_10_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_7_V_0;
integer PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
integer PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
wire [31:0] ktop14;
reg System_BitConverter_IsLittleEndian;
wire [31:0] ktop12;
reg [63:0] KiwiSystem_Kiwi_tnow;
reg [31:0] KiwiSystem_Kiwi_old_pausemode_value;
wire [31:0] ktop10;
reg [6:0] xpc10;
always @(posedge clk ) begin
if (reset) begin
KiwiSystem_Kiwi_tnow <= 64'd0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'd0;
System_BitConverter_IsLittleEndian <= 32'd0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_7_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_10_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_13_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_16_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_4_3_V_0 <= 32'd0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'd0;
T402_PearsonHash_BlockHash_6_2_V_0 <= 32'd0;
T402_PearsonHash_BlockHash_6_6_V_0 <= 32'd0;
T402_PearsonHash_BlockHash_6_10_V_0 <= 32'd0;
T402_PearsonHash_BlockHash_6_14_V_0 <= 32'd0;
PH_block_enable <= 32'd0;
PH_block_in <= 64'd0;
PH_encipher_enable <= 32'd0;
PH_write_enable <= 32'd0;
PH_key_byte_in <= 32'd0;
PH_idx_in <= 32'd0;
xpc10 <= 32'd0;
PH_init_hash_enable <= 32'd0;
PH_data_in <= 32'd0;
end
else begin
if ((xpc10==7'sd46)) $finish(32'sd0);
if (PH_encipher_ready)
case (xpc10)
7'sd15: xpc10 <= 7'sd66;
7'sd16: xpc10 <= 7'sd17;
7'sd18: xpc10 <= 7'sd64;
7'sd19: xpc10 <= 7'sd20;
7'sd21: xpc10 <= 7'sd62;
7'sd22: xpc10 <= 7'sd23;
7'sd24: xpc10 <= 7'sd60;
7'sd25: xpc10 <= 7'sd26;
7'sd30: begin
xpc10 <= 7'sd55;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd0;
end
7'sd31: xpc10 <= 7'sd32;
7'sd56: xpc10 <= 7'sd32;
7'sd59: xpc10 <= 7'sd26;
7'sd61: xpc10 <= 7'sd23;
7'sd63: xpc10 <= 7'sd20;
7'sd65: xpc10 <= 7'sd17;
endcase
else
case (xpc10)
7'sd15: begin
xpc10 <= 7'sd16;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h0;
end
7'sd16: xpc10 <= 7'sd65;
7'sd18: begin
xpc10 <= 7'sd19;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h1;
end
7'sd19: xpc10 <= 7'sd63;
7'sd21: begin
xpc10 <= 7'sd22;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h2;
end
7'sd22: xpc10 <= 7'sd61;
7'sd24: begin
xpc10 <= 7'sd25;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h3;
end
7'sd25: xpc10 <= 7'sd59;
7'sd30: begin
xpc10 <= 7'sd31;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd0;
end
7'sd31: xpc10 <= 7'sd56;
7'sd55: begin
xpc10 <= 7'sd31;
PH_encipher_enable <= 1'h1;
PH_data_in <= rtl_unsigned_bitextract0(PearsonHash_KL_Test_T402_Main_T402_Main_V_1);
end
7'sd60: begin
xpc10 <= 7'sd25;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h3;
end
7'sd62: begin
xpc10 <= 7'sd22;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h2;
end
7'sd64: begin
xpc10 <= 7'sd19;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h1;
end
7'sd66: begin
xpc10 <= 7'sd16;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h0;
end
endcase
if (PH_block_ready)
case (xpc10)
7'sd35: xpc10 <= 7'sd36;
7'sd37: xpc10 <= 7'sd52;
7'sd38: xpc10 <= 7'sd39;
7'sd40: xpc10 <= 7'sd50;
7'sd41: xpc10 <= 7'sd42;
7'sd43: xpc10 <= 7'sd48;
7'sd44: xpc10 <= 7'sd45;
7'sd47: xpc10 <= 7'sd45;
7'sd49: xpc10 <= 7'sd42;
7'sd51: xpc10 <= 7'sd39;
7'sd53: xpc10 <= 7'sd36;
endcase
else
case (xpc10)
7'sd35: xpc10 <= 7'sd53;
7'sd37: begin
xpc10 <= 7'sd38;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd38: xpc10 <= 7'sd51;
7'sd40: begin
xpc10 <= 7'sd41;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
end
7'sd41: xpc10 <= 7'sd49;
7'sd43: begin
xpc10 <= 7'sd44;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd44: xpc10 <= 7'sd47;
7'sd48: begin
xpc10 <= 7'sd44;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd50: begin
xpc10 <= 7'sd41;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
end
7'sd52: begin
xpc10 <= 7'sd38;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd54: begin
xpc10 <= 7'sd35;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
end
endcase
if (PH_write_ready)
case (xpc10)
7'sd5: begin
xpc10 <= 7'sd71;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd0;
end
7'sd6: xpc10 <= 7'sd7;
7'sd10: xpc10 <= 7'sd11;
7'sd12: xpc10 <= 7'sd68;
7'sd13: xpc10 <= 7'sd14;
7'sd67: xpc10 <= 7'sd14;
7'sd69: xpc10 <= 7'sd11;
7'sd72: xpc10 <= 7'sd7;
endcase
else
case (xpc10)
7'sd5: begin
xpc10 <= 7'sd6;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'hff;
PH_idx_in <= 8'h0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd0;
end
7'sd6: xpc10 <= 7'sd72;
7'sd10: xpc10 <= 7'sd69;
7'sd12: begin
xpc10 <= 7'sd13;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'ha;
PH_idx_in <= 8'h14;
end
7'sd13: xpc10 <= 7'sd67;
7'sd68: begin
xpc10 <= 7'sd13;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'ha;
PH_idx_in <= 8'h14;
end
7'sd70: begin
xpc10 <= 7'sd10;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'h14;
PH_idx_in <= 8'ha;
end
7'sd71: begin
xpc10 <= 7'sd6;
PH_write_enable <= 1'h1;
PH_key_byte_in <= rtl_unsigned_bitextract0(rtl_unsigned_extend1(8'd255)+(0-PearsonHash_KL_Test_T402_Main_T402_Main_V_0
));
PH_idx_in <= rtl_unsigned_bitextract0(PearsonHash_KL_Test_T402_Main_T402_Main_V_0);
end
endcase
if (PH_init_hash_ready)
case (xpc10)
7'sd1: xpc10 <= 7'sd74;
7'sd2: xpc10 <= 7'sd3;
7'sd27: xpc10 <= 7'sd58;
7'sd28: xpc10 <= 7'sd29;
7'sd57: xpc10 <= 7'sd29;
7'sd73: xpc10 <= 7'sd3;
endcase
else
case (xpc10)
7'sd1: begin
xpc10 <= 7'sd2;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'ha;
end
7'sd2: xpc10 <= 7'sd73;
7'sd27: begin
xpc10 <= 7'sd28;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'h8;
end
7'sd28: xpc10 <= 7'sd57;
7'sd58: begin
xpc10 <= 7'sd28;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'h8;
end
7'sd74: begin
xpc10 <= 7'sd2;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'ha;
end
endcase
case (xpc10)
7'sd0: begin
xpc10 <= 7'sd1;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
end
7'sd3: begin
xpc10 <= 7'sd4;
PH_init_hash_enable <= 1'h0;
end
7'sd4: xpc10 <= 7'sd5;
7'sd7: begin
xpc10 <= 7'sd8;
PH_write_enable <= 1'h0;
end
7'sd8: xpc10 <= 7'sd9;
7'sd9: begin
if (!PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0>=32'sd255)) begin
xpc10 <= 7'sd10;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'h14;
PH_idx_in <= 8'ha;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
if (!PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0<32'sd255)) begin
xpc10 <= 7'sd6;
PH_write_enable <= 1'h1;
PH_key_byte_in <= rtl_unsigned_bitextract0(rtl_unsigned_extend1(8'd254)+(0-PearsonHash_KL_Test_T402_Main_T402_Main_V_0
));
PH_idx_in <= rtl_unsigned_bitextract0(32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0);
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
if (PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0>=32'sd255)) begin
xpc10 <= 7'sd70;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
if (PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0<32'sd255)) begin
xpc10 <= 7'sd71;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
end
7'sd11: begin
xpc10 <= 7'sd12;
PH_write_enable <= 1'h0;
end
7'sd14: begin
xpc10 <= 7'sd15;
PH_write_enable <= 1'h0;
end
7'sd17: begin
xpc10 <= 7'sd18;
T402_PearsonHash_StreamHash_3_7_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd20: begin
xpc10 <= 7'sd21;
T402_PearsonHash_StreamHash_3_10_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd23: begin
xpc10 <= 7'sd24;
T402_PearsonHash_StreamHash_3_13_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd26: begin
xpc10 <= 7'sd27;
T402_PearsonHash_StreamHash_3_16_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd29: begin
xpc10 <= 7'sd30;
PH_init_hash_enable <= 1'h0;
end
7'sd32: begin
xpc10 <= 7'sd33;
T402_PearsonHash_StreamHash_4_3_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd33: xpc10 <= 7'sd34;
7'sd34: begin
if (!PH_block_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1>=32'sd255)) begin
xpc10 <= 7'sd35;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
if (!PH_encipher_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1<32'sd255)) begin
xpc10 <= 7'sd31;
PH_encipher_enable <= 1'h1;
PH_data_in <= rtl_unsigned_bitextract0(32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1);
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
if (PH_block_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1>=32'sd255)) begin
xpc10 <= 7'sd54;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
if (PH_encipher_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1<32'sd255)) begin
xpc10 <= 7'sd55;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
end
7'sd36: begin
xpc10 <= 7'sd37;
T402_PearsonHash_BlockHash_6_2_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
7'sd39: begin
xpc10 <= 7'sd40;
T402_PearsonHash_BlockHash_6_6_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
7'sd42: begin
xpc10 <= 7'sd43;
T402_PearsonHash_BlockHash_6_10_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
7'sd45: begin
xpc10 <= 7'sd46;
T402_PearsonHash_BlockHash_6_14_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
endcase
end
end
endmodule | module PearsonHash_KL_Test( output [7:0] PH_block_hash,
input PH_block_ready,
output reg PH_block_enable,
output reg [63:0] PH_block_in,
output [7:0] PH_cipher_out,
input PH_encipher_ready,
output reg PH_encipher_enable,
input PH_write_ready,
output reg PH_write_enable,
output reg [7:0] PH_key_byte_in,
output reg [7:0] PH_idx_in,
input PH_init_hash_ready,
output reg PH_init_hash_enable,
output reg [7:0] PH_data_in,
input clk,
input reset); |
function [7:0] rtl_unsigned_bitextract2;
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[7:0]);
endfunction
function [7:0] rtl_unsigned_bitextract0;
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[7:0]);
endfunction
function [31:0] rtl_unsigned_extend1;
input [7:0] arg;
rtl_unsigned_extend1 = { 24'b0, arg[7:0] };
endfunction
reg [7:0] T402_PearsonHash_BlockHash_6_14_V_0;
reg [7:0] T402_PearsonHash_BlockHash_6_10_V_0;
reg [7:0] T402_PearsonHash_BlockHash_6_6_V_0;
reg [7:0] T402_PearsonHash_BlockHash_6_2_V_0;
reg [7:0] T402_PearsonHash_StreamHash_4_3_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_16_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_13_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_10_V_0;
reg [7:0] T402_PearsonHash_StreamHash_3_7_V_0;
integer PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
integer PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
wire [31:0] ktop14;
reg System_BitConverter_IsLittleEndian;
wire [31:0] ktop12;
reg [63:0] KiwiSystem_Kiwi_tnow;
reg [31:0] KiwiSystem_Kiwi_old_pausemode_value;
wire [31:0] ktop10;
reg [6:0] xpc10;
always @(posedge clk ) begin
if (reset) begin
KiwiSystem_Kiwi_tnow <= 64'd0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'd0;
System_BitConverter_IsLittleEndian <= 32'd0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_7_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_10_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_13_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_3_16_V_0 <= 32'd0;
T402_PearsonHash_StreamHash_4_3_V_0 <= 32'd0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'd0;
T402_PearsonHash_BlockHash_6_2_V_0 <= 32'd0;
T402_PearsonHash_BlockHash_6_6_V_0 <= 32'd0;
T402_PearsonHash_BlockHash_6_10_V_0 <= 32'd0;
T402_PearsonHash_BlockHash_6_14_V_0 <= 32'd0;
PH_block_enable <= 32'd0;
PH_block_in <= 64'd0;
PH_encipher_enable <= 32'd0;
PH_write_enable <= 32'd0;
PH_key_byte_in <= 32'd0;
PH_idx_in <= 32'd0;
xpc10 <= 32'd0;
PH_init_hash_enable <= 32'd0;
PH_data_in <= 32'd0;
end
else begin
if ((xpc10==7'sd46)) $finish(32'sd0);
if (PH_encipher_ready)
case (xpc10)
7'sd15: xpc10 <= 7'sd66;
7'sd16: xpc10 <= 7'sd17;
7'sd18: xpc10 <= 7'sd64;
7'sd19: xpc10 <= 7'sd20;
7'sd21: xpc10 <= 7'sd62;
7'sd22: xpc10 <= 7'sd23;
7'sd24: xpc10 <= 7'sd60;
7'sd25: xpc10 <= 7'sd26;
7'sd30: begin
xpc10 <= 7'sd55;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd0;
end
7'sd31: xpc10 <= 7'sd32;
7'sd56: xpc10 <= 7'sd32;
7'sd59: xpc10 <= 7'sd26;
7'sd61: xpc10 <= 7'sd23;
7'sd63: xpc10 <= 7'sd20;
7'sd65: xpc10 <= 7'sd17;
endcase
else
case (xpc10)
7'sd15: begin
xpc10 <= 7'sd16;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h0;
end
7'sd16: xpc10 <= 7'sd65;
7'sd18: begin
xpc10 <= 7'sd19;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h1;
end
7'sd19: xpc10 <= 7'sd63;
7'sd21: begin
xpc10 <= 7'sd22;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h2;
end
7'sd22: xpc10 <= 7'sd61;
7'sd24: begin
xpc10 <= 7'sd25;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h3;
end
7'sd25: xpc10 <= 7'sd59;
7'sd30: begin
xpc10 <= 7'sd31;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd0;
end
7'sd31: xpc10 <= 7'sd56;
7'sd55: begin
xpc10 <= 7'sd31;
PH_encipher_enable <= 1'h1;
PH_data_in <= rtl_unsigned_bitextract0(PearsonHash_KL_Test_T402_Main_T402_Main_V_1);
end
7'sd60: begin
xpc10 <= 7'sd25;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h3;
end
7'sd62: begin
xpc10 <= 7'sd22;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h2;
end
7'sd64: begin
xpc10 <= 7'sd19;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h1;
end
7'sd66: begin
xpc10 <= 7'sd16;
PH_encipher_enable <= 1'h1;
PH_data_in <= 8'h0;
end
endcase
if (PH_block_ready)
case (xpc10)
7'sd35: xpc10 <= 7'sd36;
7'sd37: xpc10 <= 7'sd52;
7'sd38: xpc10 <= 7'sd39;
7'sd40: xpc10 <= 7'sd50;
7'sd41: xpc10 <= 7'sd42;
7'sd43: xpc10 <= 7'sd48;
7'sd44: xpc10 <= 7'sd45;
7'sd47: xpc10 <= 7'sd45;
7'sd49: xpc10 <= 7'sd42;
7'sd51: xpc10 <= 7'sd39;
7'sd53: xpc10 <= 7'sd36;
endcase
else
case (xpc10)
7'sd35: xpc10 <= 7'sd53;
7'sd37: begin
xpc10 <= 7'sd38;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd38: xpc10 <= 7'sd51;
7'sd40: begin
xpc10 <= 7'sd41;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
end
7'sd41: xpc10 <= 7'sd49;
7'sd43: begin
xpc10 <= 7'sd44;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd44: xpc10 <= 7'sd47;
7'sd48: begin
xpc10 <= 7'sd44;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd50: begin
xpc10 <= 7'sd41;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
end
7'sd52: begin
xpc10 <= 7'sd38;
PH_block_enable <= 1'h1;
PH_block_in <= 64'ha;
end
7'sd54: begin
xpc10 <= 7'sd35;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
end
endcase
if (PH_write_ready)
case (xpc10)
7'sd5: begin
xpc10 <= 7'sd71;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd0;
end
7'sd6: xpc10 <= 7'sd7;
7'sd10: xpc10 <= 7'sd11;
7'sd12: xpc10 <= 7'sd68;
7'sd13: xpc10 <= 7'sd14;
7'sd67: xpc10 <= 7'sd14;
7'sd69: xpc10 <= 7'sd11;
7'sd72: xpc10 <= 7'sd7;
endcase
else
case (xpc10)
7'sd5: begin
xpc10 <= 7'sd6;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'hff;
PH_idx_in <= 8'h0;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd0;
end
7'sd6: xpc10 <= 7'sd72;
7'sd10: xpc10 <= 7'sd69;
7'sd12: begin
xpc10 <= 7'sd13;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'ha;
PH_idx_in <= 8'h14;
end
7'sd13: xpc10 <= 7'sd67;
7'sd68: begin
xpc10 <= 7'sd13;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'ha;
PH_idx_in <= 8'h14;
end
7'sd70: begin
xpc10 <= 7'sd10;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'h14;
PH_idx_in <= 8'ha;
end
7'sd71: begin
xpc10 <= 7'sd6;
PH_write_enable <= 1'h1;
PH_key_byte_in <= rtl_unsigned_bitextract0(rtl_unsigned_extend1(8'd255)+(0-PearsonHash_KL_Test_T402_Main_T402_Main_V_0
));
PH_idx_in <= rtl_unsigned_bitextract0(PearsonHash_KL_Test_T402_Main_T402_Main_V_0);
end
endcase
if (PH_init_hash_ready)
case (xpc10)
7'sd1: xpc10 <= 7'sd74;
7'sd2: xpc10 <= 7'sd3;
7'sd27: xpc10 <= 7'sd58;
7'sd28: xpc10 <= 7'sd29;
7'sd57: xpc10 <= 7'sd29;
7'sd73: xpc10 <= 7'sd3;
endcase
else
case (xpc10)
7'sd1: begin
xpc10 <= 7'sd2;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'ha;
end
7'sd2: xpc10 <= 7'sd73;
7'sd27: begin
xpc10 <= 7'sd28;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'h8;
end
7'sd28: xpc10 <= 7'sd57;
7'sd58: begin
xpc10 <= 7'sd28;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'h8;
end
7'sd74: begin
xpc10 <= 7'sd2;
PH_init_hash_enable <= 1'h1;
PH_data_in <= 8'ha;
end
endcase
case (xpc10)
7'sd0: begin
xpc10 <= 7'sd1;
KiwiSystem_Kiwi_tnow <= 64'h0;
KiwiSystem_Kiwi_old_pausemode_value <= 32'h2;
System_BitConverter_IsLittleEndian <= 1'h1;
end
7'sd3: begin
xpc10 <= 7'sd4;
PH_init_hash_enable <= 1'h0;
end
7'sd4: xpc10 <= 7'sd5;
7'sd7: begin
xpc10 <= 7'sd8;
PH_write_enable <= 1'h0;
end
7'sd8: xpc10 <= 7'sd9;
7'sd9: begin
if (!PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0>=32'sd255)) begin
xpc10 <= 7'sd10;
PH_write_enable <= 1'h1;
PH_key_byte_in <= 8'h14;
PH_idx_in <= 8'ha;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
if (!PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0<32'sd255)) begin
xpc10 <= 7'sd6;
PH_write_enable <= 1'h1;
PH_key_byte_in <= rtl_unsigned_bitextract0(rtl_unsigned_extend1(8'd254)+(0-PearsonHash_KL_Test_T402_Main_T402_Main_V_0
));
PH_idx_in <= rtl_unsigned_bitextract0(32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0);
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
if (PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0>=32'sd255)) begin
xpc10 <= 7'sd70;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
if (PH_write_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_0<32'sd255)) begin
xpc10 <= 7'sd71;
PearsonHash_KL_Test_T402_Main_T402_Main_V_0 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_0;
end
end
7'sd11: begin
xpc10 <= 7'sd12;
PH_write_enable <= 1'h0;
end
7'sd14: begin
xpc10 <= 7'sd15;
PH_write_enable <= 1'h0;
end
7'sd17: begin
xpc10 <= 7'sd18;
T402_PearsonHash_StreamHash_3_7_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd20: begin
xpc10 <= 7'sd21;
T402_PearsonHash_StreamHash_3_10_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd23: begin
xpc10 <= 7'sd24;
T402_PearsonHash_StreamHash_3_13_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd26: begin
xpc10 <= 7'sd27;
T402_PearsonHash_StreamHash_3_16_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd29: begin
xpc10 <= 7'sd30;
PH_init_hash_enable <= 1'h0;
end
7'sd32: begin
xpc10 <= 7'sd33;
T402_PearsonHash_StreamHash_4_3_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);
PH_encipher_enable <= 1'h0;
end
7'sd33: xpc10 <= 7'sd34;
7'sd34: begin
if (!PH_block_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1>=32'sd255)) begin
xpc10 <= 7'sd35;
PH_block_enable <= 1'h1;
PH_block_in <= 64'hd_c07a;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
if (!PH_encipher_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1<32'sd255)) begin
xpc10 <= 7'sd31;
PH_encipher_enable <= 1'h1;
PH_data_in <= rtl_unsigned_bitextract0(32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1);
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
if (PH_block_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1>=32'sd255)) begin
xpc10 <= 7'sd54;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
if (PH_encipher_ready && (PearsonHash_KL_Test_T402_Main_T402_Main_V_1<32'sd255)) begin
xpc10 <= 7'sd55;
PearsonHash_KL_Test_T402_Main_T402_Main_V_1 <= 32'sd1+PearsonHash_KL_Test_T402_Main_T402_Main_V_1;
end
end
7'sd36: begin
xpc10 <= 7'sd37;
T402_PearsonHash_BlockHash_6_2_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
7'sd39: begin
xpc10 <= 7'sd40;
T402_PearsonHash_BlockHash_6_6_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
7'sd42: begin
xpc10 <= 7'sd43;
T402_PearsonHash_BlockHash_6_10_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
7'sd45: begin
xpc10 <= 7'sd46;
T402_PearsonHash_BlockHash_6_14_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);
PH_block_enable <= 1'h0;
end
endcase
end
end
endmodule | 3 |
142,088 | data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v | 97,045,669 | PearsonHash_KL_Test.v | v | 662 | 339 | [] | [] | [] | [(11, 547)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:68: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:73: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:74: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:76: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:77: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:78: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:79: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:80: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_block_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:82: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_encipher_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:83: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:84: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_key_byte_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:85: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_idx_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:86: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_init_hash_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:88: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_data_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:449: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:455: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:461: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:467: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:478: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:509: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:515: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:521: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 27 warning(s)\n' | 313,025 | function | function [7:0] rtl_unsigned_bitextract2;
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[7:0]);
endfunction | function [7:0] rtl_unsigned_bitextract2; |
input [31:0] arg;
rtl_unsigned_bitextract2 = $unsigned(arg[7:0]);
endfunction | 3 |
142,089 | data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v | 97,045,669 | PearsonHash_KL_Test.v | v | 662 | 339 | [] | [] | [] | [(11, 547)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:68: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:73: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:74: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:76: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:77: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:78: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:79: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:80: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_block_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:82: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_encipher_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:83: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:84: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_key_byte_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:85: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_idx_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:86: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_init_hash_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:88: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_data_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:449: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:455: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:461: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:467: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:478: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:509: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:515: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:521: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 27 warning(s)\n' | 313,025 | function | function [7:0] rtl_unsigned_bitextract0;
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[7:0]);
endfunction | function [7:0] rtl_unsigned_bitextract0; |
input [31:0] arg;
rtl_unsigned_bitextract0 = $unsigned(arg[7:0]);
endfunction | 3 |
142,090 | data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v | 97,045,669 | PearsonHash_KL_Test.v | v | 662 | 339 | [] | [] | [] | [(11, 547)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:68: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n System_BitConverter_IsLittleEndian <= 32\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:73: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:74: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:76: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:77: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:78: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:79: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:80: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_block_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:82: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_encipher_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:83: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_write_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:84: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_key_byte_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:85: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_idx_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:86: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n xpc10 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_init_hash_enable <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:88: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance PearsonHash_KL_Test\n PH_data_in <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:449: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_7_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:455: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_10_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:461: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_13_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:467: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_3_16_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:478: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_cipher_out\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_StreamHash_4_3_V_0 <= rtl_unsigned_bitextract2(PH_cipher_out);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:509: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_2_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:515: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_6_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:521: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_10_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/lib/PearsonHash_KL_Test.v:527: Operator FUNCREF \'rtl_unsigned_bitextract2\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'PH_block_hash\' generates 8 bits.\n : ... In instance PearsonHash_KL_Test\n T402_PearsonHash_BlockHash_6_14_V_0 <= rtl_unsigned_bitextract2(PH_block_hash);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 27 warning(s)\n' | 313,025 | function | function [31:0] rtl_unsigned_extend1;
input [7:0] arg;
rtl_unsigned_extend1 = { 24'b0, arg[7:0] };
endfunction | function [31:0] rtl_unsigned_extend1; |
input [7:0] arg;
rtl_unsigned_extend1 = { 24'b0, arg[7:0] };
endfunction | 3 |
142,091 | data/full_repos/permissive/97045669/lib/ph_test.v | 97,045,669 | ph_test.v | v | 158 | 81 | [] | [] | [] | [(15, 157)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/97045669/lib/ph_test.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97045669/lib/ph_test.v:93: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ph_test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97045669/lib/ph_test.v:94: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ph_test);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97045669/lib/ph_test.v:97: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ph_test.ph.mejda[idx]);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/97045669/lib/ph_test.v:101: Unsupported: Ignoring delay on this delayed statement.\n #16\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97045669/lib/ph_test.v:103: Unsupported: Ignoring delay on this delayed statement.\n #4\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,026 | module | module ph_test;
reg clk = 0;
always #1 clk = !clk;
reg reset;
localparam BLOCK_SIZE_IN_OCTETS = 8;
wire write_ready;
wire encipher_ready;
wire init_hash_ready;
wire block_ready;
wire [7:0] cipher_out;
wire [7:0] block_hash;
`ifdef K_DRIVEN
wire write_enable;
wire encipher_enable;
wire init_hash_enable;
wire block_enable;
wire [7:0] idx_in;
wire [7:0] key_byte_in;
wire [7:0] data_in;
wire [(BLOCK_SIZE_IN_OCTETS * 8) - 1:0] block_in;
`elsif V_DRIVEN
reg write_enable = 0;
reg encipher_enable = 0;
reg init_hash_enable = 0;
reg block_enable = 0;
reg [7:0] idx_in;
reg [7:0] key_byte_in;
reg [7:0] data_in;
reg [(BLOCK_SIZE_IN_OCTETS * 8) - 1:0] block_in;
`endif
PearsonHash
#(.BLOCK_SIZE_IN_OCTETS(BLOCK_SIZE_IN_OCTETS))
ph
(.reset(reset),
.write_enable(write_enable),
.encipher_enable(encipher_enable),
.write_ready(write_ready),
.encipher_ready(encipher_ready),
.init_hash_enable(init_hash_enable),
.init_hash_ready(init_hash_ready),
.idx_in(idx_in),
.key_byte_in(key_byte_in),
.data_in(data_in),
.cipher_out(cipher_out),
.block_ready(block_ready),
.block_hash(block_hash),
.block_in(block_in),
.block_enable(block_enable));
`ifdef K_DRIVEN
PearsonHash_KL_Test ph_kl_test
(.PH_cipher_out(cipher_out),
.PH_encipher_ready(encipher_ready),
.PH_encipher_enable(encipher_enable),
.PH_data_in(data_in),
.PH_write_ready(write_ready),
.PH_write_enable(write_enable),
.PH_init_hash_enable(init_hash_enable),
.PH_init_hash_ready(init_hash_ready),
.PH_key_byte_in(key_byte_in),
.PH_idx_in(idx_in),
.clk(clk),
.reset(reset),
.PH_block_ready(block_ready),
.PH_block_hash(block_hash),
.PH_block_in(block_in),
.PH_block_enable(block_enable));
`endif
integer idx;
initial begin
$dumpfile("ph_test.vcd");
$dumpvars(0,ph_test);
for (idx = 0; idx < 256; idx = idx + 1) begin
$dumpvars(0,ph_test.ph.mejda[idx]);
end
`ifdef K_DRIVEN
#16
reset = 1;
#4
reset = 0;
`elsif V_DRIVEN
#2
data_in = 8'd10;
reset = 1;
#4 reset = 0;
for (idx = 0; idx < 256; idx = idx + 1) begin
#1 idx_in <= idx;
key_byte_in <= 255 - idx;
write_enable <= 1;
#1 write_enable <= 0;
end
#1 data_in <= 8'd0;
init_hash_enable <= 1;
#1 init_hash_enable <= 0;
for (idx = 0; idx < 256; idx = idx + 1) begin
#1 data_in <= idx;
encipher_enable <= 1;
#1 encipher_enable <= 0;
end
for (idx = 0; idx < 256; idx = idx + 1) begin
#1 data_in <= idx;
encipher_enable <= 1;
#1 encipher_enable <= 0;
end
#1 block_in <= 64'd901242;
block_enable <= 1;
#1 block_enable <= 0;
#1 block_in <= 64'd10;
block_enable <= 1;
#1 block_enable <= 0;
#1 block_in <= 64'd901242;
block_enable <= 1;
#1 block_enable <= 0;
#1 block_in <= 64'd10;
block_enable <= 1;
#1 block_enable <= 0;
#20 $finish;
`endif
end
endmodule | module ph_test; |
reg clk = 0;
always #1 clk = !clk;
reg reset;
localparam BLOCK_SIZE_IN_OCTETS = 8;
wire write_ready;
wire encipher_ready;
wire init_hash_ready;
wire block_ready;
wire [7:0] cipher_out;
wire [7:0] block_hash;
`ifdef K_DRIVEN
wire write_enable;
wire encipher_enable;
wire init_hash_enable;
wire block_enable;
wire [7:0] idx_in;
wire [7:0] key_byte_in;
wire [7:0] data_in;
wire [(BLOCK_SIZE_IN_OCTETS * 8) - 1:0] block_in;
`elsif V_DRIVEN
reg write_enable = 0;
reg encipher_enable = 0;
reg init_hash_enable = 0;
reg block_enable = 0;
reg [7:0] idx_in;
reg [7:0] key_byte_in;
reg [7:0] data_in;
reg [(BLOCK_SIZE_IN_OCTETS * 8) - 1:0] block_in;
`endif
PearsonHash
#(.BLOCK_SIZE_IN_OCTETS(BLOCK_SIZE_IN_OCTETS))
ph
(.reset(reset),
.write_enable(write_enable),
.encipher_enable(encipher_enable),
.write_ready(write_ready),
.encipher_ready(encipher_ready),
.init_hash_enable(init_hash_enable),
.init_hash_ready(init_hash_ready),
.idx_in(idx_in),
.key_byte_in(key_byte_in),
.data_in(data_in),
.cipher_out(cipher_out),
.block_ready(block_ready),
.block_hash(block_hash),
.block_in(block_in),
.block_enable(block_enable));
`ifdef K_DRIVEN
PearsonHash_KL_Test ph_kl_test
(.PH_cipher_out(cipher_out),
.PH_encipher_ready(encipher_ready),
.PH_encipher_enable(encipher_enable),
.PH_data_in(data_in),
.PH_write_ready(write_ready),
.PH_write_enable(write_enable),
.PH_init_hash_enable(init_hash_enable),
.PH_init_hash_ready(init_hash_ready),
.PH_key_byte_in(key_byte_in),
.PH_idx_in(idx_in),
.clk(clk),
.reset(reset),
.PH_block_ready(block_ready),
.PH_block_hash(block_hash),
.PH_block_in(block_in),
.PH_block_enable(block_enable));
`endif
integer idx;
initial begin
$dumpfile("ph_test.vcd");
$dumpvars(0,ph_test);
for (idx = 0; idx < 256; idx = idx + 1) begin
$dumpvars(0,ph_test.ph.mejda[idx]);
end
`ifdef K_DRIVEN
#16
reset = 1;
#4
reset = 0;
`elsif V_DRIVEN
#2
data_in = 8'd10;
reset = 1;
#4 reset = 0;
for (idx = 0; idx < 256; idx = idx + 1) begin
#1 idx_in <= idx;
key_byte_in <= 255 - idx;
write_enable <= 1;
#1 write_enable <= 0;
end
#1 data_in <= 8'd0;
init_hash_enable <= 1;
#1 init_hash_enable <= 0;
for (idx = 0; idx < 256; idx = idx + 1) begin
#1 data_in <= idx;
encipher_enable <= 1;
#1 encipher_enable <= 0;
end
for (idx = 0; idx < 256; idx = idx + 1) begin
#1 data_in <= idx;
encipher_enable <= 1;
#1 encipher_enable <= 0;
end
#1 block_in <= 64'd901242;
block_enable <= 1;
#1 block_enable <= 0;
#1 block_in <= 64'd10;
block_enable <= 1;
#1 block_enable <= 0;
#1 block_in <= 64'd901242;
block_enable <= 1;
#1 block_enable <= 0;
#1 block_in <= 64'd10;
block_enable <= 1;
#1 block_enable <= 0;
#20 $finish;
`endif
end
endmodule | 3 |
142,092 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v | 97,045,669 | emu_output_port_lookup_AXIS256.v | v | 292 | 219 | [] | ['netfpga'] | ['all rights reserved'] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:54: Cannot find include file: output_port_lookup_cpu_regs_defines.v\n`include "output_port_lookup_cpu_regs_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.sv\n output_port_lookup_cpu_regs_defines.v\n output_port_lookup_cpu_regs_defines.v.v\n output_port_lookup_cpu_regs_defines.v.sv\n obj_dir/output_port_lookup_cpu_regs_defines.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.sv\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:116: Define or directive not defined: \'`REG_ID_BITS\'\n reg [`REG_ID_BITS] id_reg;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:116: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_ID_BITS] id_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:117: Define or directive not defined: \'`REG_VERSION_BITS\'\n reg [`REG_VERSION_BITS] version_reg;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_VERSION_BITS] version_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:118: Define or directive not defined: \'`REG_RESET_BITS\'\n wire [`REG_RESET_BITS] reset_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_RESET_BITS] reset_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:119: Define or directive not defined: \'`REG_FLIP_BITS\'\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:120: Define or directive not defined: \'`REG_FLIP_BITS\'\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:120: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:121: Define or directive not defined: \'`REG_PKTIN_BITS\'\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:123: Define or directive not defined: \'`REG_PKTOUT_BITS\'\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:123: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:125: Define or directive not defined: \'`REG_DEBUG_BITS\'\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:126: Define or directive not defined: \'`REG_DEBUG_BITS\'\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:270: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:270: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:271: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:271: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:272: Define or directive not defined: \'`REG_FLIP_DEFAULT\'\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:272: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:273: Define or directive not defined: \'`REG_PKTIN_DEFAULT\'\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:273: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:274: Define or directive not defined: \'`REG_PKTOUT_DEFAULT\'\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:274: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:275: Define or directive not defined: \'`REG_DEBUG_DEFAULT\'\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:275: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:278: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:278: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:279: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:279: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:281: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:281: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:282: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:282: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:283: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:283: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:285: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:285: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:286: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:286: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:286: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:287: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n 1\'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 47 error(s)\n' | 313,029 | module | module emu_output_port_lookup
#(
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter SRC_PORT_POS=16,
parameter DST_PORT_POS=24,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h00000000
)
(
input axis_aclk,
input axis_resetn,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast,
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output [1 : 0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1 :0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY
);
reg [`REG_ID_BITS] id_reg;
reg [`REG_VERSION_BITS] version_reg;
wire [`REG_RESET_BITS] reset_reg;
reg [`REG_FLIP_BITS] ip2cpu_flip_reg;
wire [`REG_FLIP_BITS] cpu2ip_flip_reg;
reg [`REG_PKTIN_BITS] pktin_reg;
wire pktin_reg_clear;
reg [`REG_PKTOUT_BITS] pktout_reg;
wire pktout_reg_clear;
reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;
wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;
wire clear_counters;
wire reset_registers;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
localparam MODULE_HEADER = 0;
localparam IN_PACKET = 1;
wire [63:0] m_axis_tdata_256;
wire [7:0] m_axis_tkeep_256;
wire m_axis_tlast_256;
wire m_axis_tvalid_256;
wire m_axis_tready_256;
wire [63:0] m_axis_tuser_hi_256;
wire [63:0] m_axis_tuser_low_256;
wire [63:0] s_axis_tdata_256;
wire [7:0] s_axis_tkeep_256;
wire s_axis_tlast_256;
wire s_axis_tvalid_256;
wire s_axis_tready_256;
wire [63:0] s_axis_tuser_hi_256;
wire [63:0] s_axis_tuser_low_256;
wire cam_busy;
wire cam_match;
wire [7:0] cam_match_addr;
wire [63:0] cam_cmp_din;
wire [63:0] cam_din;
wire cam_we;
wire [7:0] cam_wr_addr;
reg reset;
always @(posedge axis_aclk) reset <= #1 ~axis_resetn;
Emu the_Emu
(
.reset(reset),
.clk(axis_aclk),
.s_axis_tdata_0(s_axis_tdata[63:0]),
.s_axis_tdata_1(s_axis_tdata[127:64]),
.s_axis_tdata_2(s_axis_tdata[191:128]),
.s_axis_tdata_3(s_axis_tdata[255:192]),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tuser_hi(s_axis_tuser[127:64]),
.s_axis_tuser_low(s_axis_tuser[63:0]),
.m_axis_tdata_0(m_axis_tdata[63:0]),
.m_axis_tdata_1(m_axis_tdata[127:64]),
.m_axis_tdata_2(m_axis_tdata[191:128]),
.m_axis_tdata_3(m_axis_tdata[255:192]),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tuser_hi(m_axis_tuser[127:64]),
.m_axis_tuser_low(m_axis_tuser[63:0])
);
output_port_lookup_cpu_regs
#(
.C_BASE_ADDRESS (C_BASEADDR),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH)
)
opl_cpu_regs_inst
(
.clk (axis_aclk),
.resetn (axis_resetn),
.S_AXI_ACLK (S_AXI_ACLK),
.S_AXI_ARESETN (S_AXI_ARESETN),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_RREADY (S_AXI_RREADY),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.id_reg (id_reg),
.version_reg (version_reg),
.reset_reg (reset_reg),
.ip2cpu_flip_reg (ip2cpu_flip_reg),
.cpu2ip_flip_reg (cpu2ip_flip_reg),
.pktin_reg (pktin_reg),
.pktin_reg_clear (pktin_reg_clear),
.pktout_reg (pktout_reg),
.pktout_reg_clear (pktout_reg_clear),
.ip2cpu_debug_reg (ip2cpu_debug_reg),
.cpu2ip_debug_reg (cpu2ip_debug_reg),
.cpu_resetn_soft(),
.resetn_soft (),
.resetn_sync (resetn_sync)
);
assign clear_counters = reset_reg[0];
assign reset_registers = reset_reg[4];
always @(posedge axis_aclk)
if (~resetn_sync | reset_registers) begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;
pktin_reg <= #1 `REG_PKTIN_DEFAULT;
pktout_reg <= #1 `REG_PKTOUT_DEFAULT;
ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;
end
else begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 ~cpu2ip_flip_reg;
pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;
pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1'h0 : pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready)
> {(`REG_PKTIN_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];
pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;
pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1'b1}} ?
1'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];
ip2cpu_debug_reg <= #1 cpu2ip_debug_reg;
end
endmodule | module emu_output_port_lookup
#(
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter SRC_PORT_POS=16,
parameter DST_PORT_POS=24,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h00000000
)
(
input axis_aclk,
input axis_resetn,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast,
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output [1 : 0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1 :0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY
); |
reg [`REG_ID_BITS] id_reg;
reg [`REG_VERSION_BITS] version_reg;
wire [`REG_RESET_BITS] reset_reg;
reg [`REG_FLIP_BITS] ip2cpu_flip_reg;
wire [`REG_FLIP_BITS] cpu2ip_flip_reg;
reg [`REG_PKTIN_BITS] pktin_reg;
wire pktin_reg_clear;
reg [`REG_PKTOUT_BITS] pktout_reg;
wire pktout_reg_clear;
reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;
wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;
wire clear_counters;
wire reset_registers;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
localparam MODULE_HEADER = 0;
localparam IN_PACKET = 1;
wire [63:0] m_axis_tdata_256;
wire [7:0] m_axis_tkeep_256;
wire m_axis_tlast_256;
wire m_axis_tvalid_256;
wire m_axis_tready_256;
wire [63:0] m_axis_tuser_hi_256;
wire [63:0] m_axis_tuser_low_256;
wire [63:0] s_axis_tdata_256;
wire [7:0] s_axis_tkeep_256;
wire s_axis_tlast_256;
wire s_axis_tvalid_256;
wire s_axis_tready_256;
wire [63:0] s_axis_tuser_hi_256;
wire [63:0] s_axis_tuser_low_256;
wire cam_busy;
wire cam_match;
wire [7:0] cam_match_addr;
wire [63:0] cam_cmp_din;
wire [63:0] cam_din;
wire cam_we;
wire [7:0] cam_wr_addr;
reg reset;
always @(posedge axis_aclk) reset <= #1 ~axis_resetn;
Emu the_Emu
(
.reset(reset),
.clk(axis_aclk),
.s_axis_tdata_0(s_axis_tdata[63:0]),
.s_axis_tdata_1(s_axis_tdata[127:64]),
.s_axis_tdata_2(s_axis_tdata[191:128]),
.s_axis_tdata_3(s_axis_tdata[255:192]),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tuser_hi(s_axis_tuser[127:64]),
.s_axis_tuser_low(s_axis_tuser[63:0]),
.m_axis_tdata_0(m_axis_tdata[63:0]),
.m_axis_tdata_1(m_axis_tdata[127:64]),
.m_axis_tdata_2(m_axis_tdata[191:128]),
.m_axis_tdata_3(m_axis_tdata[255:192]),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tuser_hi(m_axis_tuser[127:64]),
.m_axis_tuser_low(m_axis_tuser[63:0])
);
output_port_lookup_cpu_regs
#(
.C_BASE_ADDRESS (C_BASEADDR),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH)
)
opl_cpu_regs_inst
(
.clk (axis_aclk),
.resetn (axis_resetn),
.S_AXI_ACLK (S_AXI_ACLK),
.S_AXI_ARESETN (S_AXI_ARESETN),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_RREADY (S_AXI_RREADY),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.id_reg (id_reg),
.version_reg (version_reg),
.reset_reg (reset_reg),
.ip2cpu_flip_reg (ip2cpu_flip_reg),
.cpu2ip_flip_reg (cpu2ip_flip_reg),
.pktin_reg (pktin_reg),
.pktin_reg_clear (pktin_reg_clear),
.pktout_reg (pktout_reg),
.pktout_reg_clear (pktout_reg_clear),
.ip2cpu_debug_reg (ip2cpu_debug_reg),
.cpu2ip_debug_reg (cpu2ip_debug_reg),
.cpu_resetn_soft(),
.resetn_soft (),
.resetn_sync (resetn_sync)
);
assign clear_counters = reset_reg[0];
assign reset_registers = reset_reg[4];
always @(posedge axis_aclk)
if (~resetn_sync | reset_registers) begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;
pktin_reg <= #1 `REG_PKTIN_DEFAULT;
pktout_reg <= #1 `REG_PKTOUT_DEFAULT;
ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;
end
else begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 ~cpu2ip_flip_reg;
pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;
pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1'h0 : pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready)
> {(`REG_PKTIN_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];
pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;
pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1'b1}} ?
1'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];
ip2cpu_debug_reg <= #1 cpu2ip_debug_reg;
end
endmodule | 3 |
142,093 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v | 97,045,669 | emu_output_port_lookup_AXIS256.v | v | 292 | 219 | [] | ['netfpga'] | ['all rights reserved'] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:54: Cannot find include file: output_port_lookup_cpu_regs_defines.v\n`include "output_port_lookup_cpu_regs_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.sv\n output_port_lookup_cpu_regs_defines.v\n output_port_lookup_cpu_regs_defines.v.v\n output_port_lookup_cpu_regs_defines.v.sv\n obj_dir/output_port_lookup_cpu_regs_defines.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.sv\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:116: Define or directive not defined: \'`REG_ID_BITS\'\n reg [`REG_ID_BITS] id_reg;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:116: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_ID_BITS] id_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:117: Define or directive not defined: \'`REG_VERSION_BITS\'\n reg [`REG_VERSION_BITS] version_reg;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_VERSION_BITS] version_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:118: Define or directive not defined: \'`REG_RESET_BITS\'\n wire [`REG_RESET_BITS] reset_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_RESET_BITS] reset_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:119: Define or directive not defined: \'`REG_FLIP_BITS\'\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:120: Define or directive not defined: \'`REG_FLIP_BITS\'\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:120: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:121: Define or directive not defined: \'`REG_PKTIN_BITS\'\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:123: Define or directive not defined: \'`REG_PKTOUT_BITS\'\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:123: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:125: Define or directive not defined: \'`REG_DEBUG_BITS\'\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:126: Define or directive not defined: \'`REG_DEBUG_BITS\'\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:270: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:270: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:271: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:271: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:272: Define or directive not defined: \'`REG_FLIP_DEFAULT\'\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:272: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:273: Define or directive not defined: \'`REG_PKTIN_DEFAULT\'\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:273: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:274: Define or directive not defined: \'`REG_PKTOUT_DEFAULT\'\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:274: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:275: Define or directive not defined: \'`REG_DEBUG_DEFAULT\'\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:275: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:278: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:278: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:279: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:279: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:281: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:281: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:282: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:282: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:283: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:283: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:285: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:285: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:286: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:286: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:286: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256.v:287: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n 1\'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 47 error(s)\n' | 313,029 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 3 |
142,094 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v | 97,045,669 | emu_output_port_lookup_AXIS256_CAM_THREADS.v | v | 429 | 219 | [] | ['netfpga'] | ['all rights reserved'] | null | 'utf-8' codec can't decode bytes in position 6142-6143: unexpected end of data | null | 1: b'%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:54: Cannot find include file: output_port_lookup_cpu_regs_defines.v\n`include "output_port_lookup_cpu_regs_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.sv\n output_port_lookup_cpu_regs_defines.v\n output_port_lookup_cpu_regs_defines.v.v\n output_port_lookup_cpu_regs_defines.v.sv\n obj_dir/output_port_lookup_cpu_regs_defines.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.sv\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:114: Define or directive not defined: \'`REG_ID_BITS\'\n reg [`REG_ID_BITS] id_reg;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:114: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_ID_BITS] id_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:115: Define or directive not defined: \'`REG_VERSION_BITS\'\n reg [`REG_VERSION_BITS] version_reg;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:115: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_VERSION_BITS] version_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:116: Define or directive not defined: \'`REG_RESET_BITS\'\n wire [`REG_RESET_BITS] reset_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:116: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_RESET_BITS] reset_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:117: Define or directive not defined: \'`REG_FLIP_BITS\'\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:118: Define or directive not defined: \'`REG_FLIP_BITS\'\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:119: Define or directive not defined: \'`REG_PKTIN_BITS\'\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:121: Define or directive not defined: \'`REG_PKTOUT_BITS\'\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:123: Define or directive not defined: \'`REG_DEBUG_BITS\'\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:123: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:124: Define or directive not defined: \'`REG_DEBUG_BITS\'\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:124: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:407: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:407: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:408: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:408: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:409: Define or directive not defined: \'`REG_FLIP_DEFAULT\'\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:409: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:410: Define or directive not defined: \'`REG_PKTIN_DEFAULT\'\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:410: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:411: Define or directive not defined: \'`REG_PKTOUT_DEFAULT\'\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:411: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:412: Define or directive not defined: \'`REG_DEBUG_DEFAULT\'\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:412: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:415: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:415: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:416: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:416: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:418: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:418: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:419: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:419: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:420: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:420: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:422: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:422: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:423: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:423: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:423: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:424: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n 1\'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 47 error(s)\n' | 313,031 | module | module emu_output_port_lookup
#(
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter SRC_PORT_POS=16,
parameter DST_PORT_POS=24,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h00000000
)
(
input axis_aclk,
input axis_resetn,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast,
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output [1 : 0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1 :0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY
);
reg [`REG_ID_BITS] id_reg;
reg [`REG_VERSION_BITS] version_reg;
wire [`REG_RESET_BITS] reset_reg;
reg [`REG_FLIP_BITS] ip2cpu_flip_reg;
wire [`REG_FLIP_BITS] cpu2ip_flip_reg;
reg [`REG_PKTIN_BITS] pktin_reg;
wire pktin_reg_clear;
reg [`REG_PKTOUT_BITS] pktout_reg;
wire pktout_reg_clear;
reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;
wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;
wire clear_counters;
wire reset_registers;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
localparam MODULE_HEADER = 0;
localparam IN_PACKET = 1;
localparam CAM_DEPTH = 16;
localparam CAM_WIDTH = 64;
localparam CAM_DEPTH_BITS = log2(CAM_DEPTH);
wire cam_busy;
wire cam_match;
wire [CAM_DEPTH_BITS-1:0] cam_match_addr;
wire [63:0] cam_cmp_din;
wire [63:0] cam_din;
wire cam_we;
wire [CAM_DEPTH_BITS-1:0] cam_wr_addr;
wire cam_busy_learn;
wire cam_match_learn;
wire [CAM_DEPTH_BITS-1:0] cam_match_addr_learn;
wire [63:0] cam_cmp_din_learn;
wire [63:0] cam_din_learn;
wire cam_we_learn;
wire [CAM_DEPTH_BITS-1:0] cam_wr_addr_learn;
wire fifo_nearly_full;
wire fifo_empty;
wire fifo_rd_en;
wire fifo_wr_en;
wire [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser_fifo;
wire [64-1:0] dst_ports;
wire lookup_done;
wire dst_port_rd;
wire dst_port_fifo_nearly_full;
wire dst_port_fifo_empty;
reg reset;
wire m_axis_tvalid_emu;
wire s_axis_tready_emu;
always @(posedge axis_aclk) reset <= #1 ~axis_resetn;
assign fifo_wr_en = s_axis_tvalid & s_axis_tready;
assign s_axis_tready = ~fifo_nearly_full & s_axis_tready_emu;
assign m_axis_tuser[127:64] = 64'b0;
assign m_axis_tvalid = ~fifo_empty & m_axis_tvalid_emu;
assign fifo_rd_en = m_axis_tready & m_axis_tvalid;
fallthrough_small_fifo #(.WIDTH(C_M_AXIS_DATA_WIDTH+C_M_AXIS_TUSER_WIDTH+C_M_AXIS_DATA_WIDTH/8+1), .MAX_DEPTH_BITS(6))
input_fifo
( .din ({s_axis_tlast, s_axis_tuser, s_axis_tkeep, s_axis_tdata}),
.wr_en (fifo_wr_en),
.rd_en (fifo_rd_en),
.dout ({m_axis_tlast, m_axis_tuser_fifo , m_axis_tkeep, m_axis_tdata}),
.full (),
.prog_full (),
.nearly_full (fifo_nearly_full),
.empty (fifo_empty),
.reset (reset),
.clk (axis_aclk)
);
fallthrough_small_fifo #(.WIDTH(64), .MAX_DEPTH_BITS(4))
dst_port_fifo
( .din (dst_ports),
.wr_en (lookup_done),
.rd_en (dst_port_rd),
.dout (m_axis_tuser[63:0]),
.full (),
.prog_full (),
.nearly_full (),
.empty (dst_port_fifo_empty),
.reset (reset),
.clk (axis_aclk)
);
Emu the_Emu
(
.reset(reset),
.clk(axis_aclk),
.s_axis_tdata_0(s_axis_tdata[63:0]),
.s_axis_tdata_1(s_axis_tdata[127:64]),
.s_axis_tdata_2(s_axis_tdata[191:128]),
.s_axis_tdata_3(s_axis_tdata[255:192]),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready_emu),
.s_axis_tuser_hi(s_axis_tuser[127:64]),
.s_axis_tuser_low(s_axis_tuser[63:0]),
.m_axis_tdata_0(),
.m_axis_tdata_1(),
.m_axis_tdata_2(),
.m_axis_tdata_3(),
.m_axis_tkeep(),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid_emu),
.m_axis_tready(m_axis_tready),
.m_axis_tuser_hi(),
.m_axis_tuser_low(),
.cam_busy(cam_busy),
.cam_match(cam_match),
.cam_match_addr({{4{1'b0}},cam_match_addr[CAM_DEPTH_BITS-1:0]}),
.cam_cmp_din(cam_cmp_din[CAM_WIDTH-1:0]),
.cam_din(cam_din[CAM_WIDTH-1:0]),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr[CAM_DEPTH_BITS-1:0]),
.cam_busy_learn(cam_busy_learn),
.cam_match_learn(cam_match_learn),
.cam_match_addr_learn({{4{1'b0}},cam_match_addr_learn[CAM_DEPTH_BITS-1:0]}),
.cam_cmp_din_learn(cam_cmp_din_learn[CAM_WIDTH-1:0]),
.cam_din_learn(cam_din_learn[CAM_WIDTH-1:0]),
.cam_we_learn(cam_we_learn),
.cam_wr_addr_learn(cam_wr_addr_learn[CAM_DEPTH_BITS-1:0]),
.dst_ports(dst_ports),
.dst_port_rd(dst_port_rd),
.lookup_done(lookup_done),
.dst_port_fifo_empty(dst_port_fifo_empty),
.fifo_wr_en(),
.fifo_rd_en(),
.fifo_nearly_full(fifo_nearly_full),
.fifo_empty(fifo_empty)
);
cam
#(
.C_TCAM_ADDR_WIDTH (CAM_DEPTH_BITS),
.C_TCAM_DATA_WIDTH (CAM_WIDTH),
.C_TCAM_ADDR_TYPE (0),
.C_TCAM_MATCH_ADDR_WIDTH(CAM_DEPTH_BITS)
)
src_mac_cam
(
(* box_type = "user_black_box" *)
.BUSY (cam_busy_learn),
.MATCH (cam_match_learn),
.MATCH_ADDR (cam_match_addr_learn[CAM_DEPTH_BITS-1:0]),
.CLK (axis_aclk),
.CMP_DIN (cam_cmp_din_learn[CAM_WIDTH-1:0]),
.DIN (cam_din_learn[CAM_WIDTH-1:0]),
.WE (cam_we_learn),
.ADDR_WR (cam_wr_addr_learn[CAM_DEPTH_BITS-1:0])
);
cam
#(
.C_TCAM_ADDR_WIDTH (CAM_DEPTH_BITS),
.C_TCAM_DATA_WIDTH (CAM_WIDTH),
.C_TCAM_ADDR_TYPE (0),
.C_TCAM_MATCH_ADDR_WIDTH(CAM_DEPTH_BITS)
)
dst_mac_cam
(
(* box_type = "user_black_box" *)
.BUSY (cam_busy),
.MATCH (cam_match),
.MATCH_ADDR (cam_match_addr[CAM_DEPTH_BITS-1:0]),
.CLK (axis_aclk),
.CMP_DIN (cam_cmp_din[CAM_WIDTH-1:0]),
.DIN (cam_din[CAM_WIDTH-1:0]),
.WE (cam_we),
.ADDR_WR (cam_wr_addr[CAM_DEPTH_BITS-1:0])
);
output_port_lookup_cpu_regs
#(
.C_BASE_ADDRESS (C_BASEADDR),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH)
)
opl_cpu_regs_inst
(
.clk (axis_aclk),
.resetn (axis_resetn),
.S_AXI_ACLK (S_AXI_ACLK),
.S_AXI_ARESETN (S_AXI_ARESETN),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_RREADY (S_AXI_RREADY),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.id_reg (id_reg),
.version_reg (version_reg),
.reset_reg (reset_reg),
.ip2cpu_flip_reg (ip2cpu_flip_reg),
.cpu2ip_flip_reg (cpu2ip_flip_reg),
.pktin_reg (pktin_reg),
.pktin_reg_clear (pktin_reg_clear),
.pktout_reg (pktout_reg),
.pktout_reg_clear (pktout_reg_clear),
.ip2cpu_debug_reg (ip2cpu_debug_reg),
.cpu2ip_debug_reg (cpu2ip_debug_reg),
.cpu_resetn_soft (),
.resetn_soft (),
.resetn_sync (resetn_sync)
);
assign clear_counters = reset_reg[0];
assign reset_registers = reset_reg[4];
always @(posedge axis_aclk)
if (~resetn_sync | reset_registers) begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;
pktin_reg <= #1 `REG_PKTIN_DEFAULT;
pktout_reg <= #1 `REG_PKTOUT_DEFAULT;
ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;
end
else begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 ~cpu2ip_flip_reg;
pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;
pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1'h0 : pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready)
> {(`REG_PKTIN_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];
pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;
pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1'b1}} ?
1'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];
ip2cpu_debug_reg <= #1 cpu2ip_debug_reg;
end
endmodule | module emu_output_port_lookup
#(
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter SRC_PORT_POS=16,
parameter DST_PORT_POS=24,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h00000000
)
(
input axis_aclk,
input axis_resetn,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast,
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output [1 : 0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1 :0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY
); |
reg [`REG_ID_BITS] id_reg;
reg [`REG_VERSION_BITS] version_reg;
wire [`REG_RESET_BITS] reset_reg;
reg [`REG_FLIP_BITS] ip2cpu_flip_reg;
wire [`REG_FLIP_BITS] cpu2ip_flip_reg;
reg [`REG_PKTIN_BITS] pktin_reg;
wire pktin_reg_clear;
reg [`REG_PKTOUT_BITS] pktout_reg;
wire pktout_reg_clear;
reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;
wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;
wire clear_counters;
wire reset_registers;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
localparam MODULE_HEADER = 0;
localparam IN_PACKET = 1;
localparam CAM_DEPTH = 16;
localparam CAM_WIDTH = 64;
localparam CAM_DEPTH_BITS = log2(CAM_DEPTH);
wire cam_busy;
wire cam_match;
wire [CAM_DEPTH_BITS-1:0] cam_match_addr;
wire [63:0] cam_cmp_din;
wire [63:0] cam_din;
wire cam_we;
wire [CAM_DEPTH_BITS-1:0] cam_wr_addr;
wire cam_busy_learn;
wire cam_match_learn;
wire [CAM_DEPTH_BITS-1:0] cam_match_addr_learn;
wire [63:0] cam_cmp_din_learn;
wire [63:0] cam_din_learn;
wire cam_we_learn;
wire [CAM_DEPTH_BITS-1:0] cam_wr_addr_learn;
wire fifo_nearly_full;
wire fifo_empty;
wire fifo_rd_en;
wire fifo_wr_en;
wire [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser_fifo;
wire [64-1:0] dst_ports;
wire lookup_done;
wire dst_port_rd;
wire dst_port_fifo_nearly_full;
wire dst_port_fifo_empty;
reg reset;
wire m_axis_tvalid_emu;
wire s_axis_tready_emu;
always @(posedge axis_aclk) reset <= #1 ~axis_resetn;
assign fifo_wr_en = s_axis_tvalid & s_axis_tready;
assign s_axis_tready = ~fifo_nearly_full & s_axis_tready_emu;
assign m_axis_tuser[127:64] = 64'b0;
assign m_axis_tvalid = ~fifo_empty & m_axis_tvalid_emu;
assign fifo_rd_en = m_axis_tready & m_axis_tvalid;
fallthrough_small_fifo #(.WIDTH(C_M_AXIS_DATA_WIDTH+C_M_AXIS_TUSER_WIDTH+C_M_AXIS_DATA_WIDTH/8+1), .MAX_DEPTH_BITS(6))
input_fifo
( .din ({s_axis_tlast, s_axis_tuser, s_axis_tkeep, s_axis_tdata}),
.wr_en (fifo_wr_en),
.rd_en (fifo_rd_en),
.dout ({m_axis_tlast, m_axis_tuser_fifo , m_axis_tkeep, m_axis_tdata}),
.full (),
.prog_full (),
.nearly_full (fifo_nearly_full),
.empty (fifo_empty),
.reset (reset),
.clk (axis_aclk)
);
fallthrough_small_fifo #(.WIDTH(64), .MAX_DEPTH_BITS(4))
dst_port_fifo
( .din (dst_ports),
.wr_en (lookup_done),
.rd_en (dst_port_rd),
.dout (m_axis_tuser[63:0]),
.full (),
.prog_full (),
.nearly_full (),
.empty (dst_port_fifo_empty),
.reset (reset),
.clk (axis_aclk)
);
Emu the_Emu
(
.reset(reset),
.clk(axis_aclk),
.s_axis_tdata_0(s_axis_tdata[63:0]),
.s_axis_tdata_1(s_axis_tdata[127:64]),
.s_axis_tdata_2(s_axis_tdata[191:128]),
.s_axis_tdata_3(s_axis_tdata[255:192]),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready_emu),
.s_axis_tuser_hi(s_axis_tuser[127:64]),
.s_axis_tuser_low(s_axis_tuser[63:0]),
.m_axis_tdata_0(),
.m_axis_tdata_1(),
.m_axis_tdata_2(),
.m_axis_tdata_3(),
.m_axis_tkeep(),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid_emu),
.m_axis_tready(m_axis_tready),
.m_axis_tuser_hi(),
.m_axis_tuser_low(),
.cam_busy(cam_busy),
.cam_match(cam_match),
.cam_match_addr({{4{1'b0}},cam_match_addr[CAM_DEPTH_BITS-1:0]}),
.cam_cmp_din(cam_cmp_din[CAM_WIDTH-1:0]),
.cam_din(cam_din[CAM_WIDTH-1:0]),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr[CAM_DEPTH_BITS-1:0]),
.cam_busy_learn(cam_busy_learn),
.cam_match_learn(cam_match_learn),
.cam_match_addr_learn({{4{1'b0}},cam_match_addr_learn[CAM_DEPTH_BITS-1:0]}),
.cam_cmp_din_learn(cam_cmp_din_learn[CAM_WIDTH-1:0]),
.cam_din_learn(cam_din_learn[CAM_WIDTH-1:0]),
.cam_we_learn(cam_we_learn),
.cam_wr_addr_learn(cam_wr_addr_learn[CAM_DEPTH_BITS-1:0]),
.dst_ports(dst_ports),
.dst_port_rd(dst_port_rd),
.lookup_done(lookup_done),
.dst_port_fifo_empty(dst_port_fifo_empty),
.fifo_wr_en(),
.fifo_rd_en(),
.fifo_nearly_full(fifo_nearly_full),
.fifo_empty(fifo_empty)
);
cam
#(
.C_TCAM_ADDR_WIDTH (CAM_DEPTH_BITS),
.C_TCAM_DATA_WIDTH (CAM_WIDTH),
.C_TCAM_ADDR_TYPE (0),
.C_TCAM_MATCH_ADDR_WIDTH(CAM_DEPTH_BITS)
)
src_mac_cam
(
(* box_type = "user_black_box" *)
.BUSY (cam_busy_learn),
.MATCH (cam_match_learn),
.MATCH_ADDR (cam_match_addr_learn[CAM_DEPTH_BITS-1:0]),
.CLK (axis_aclk),
.CMP_DIN (cam_cmp_din_learn[CAM_WIDTH-1:0]),
.DIN (cam_din_learn[CAM_WIDTH-1:0]),
.WE (cam_we_learn),
.ADDR_WR (cam_wr_addr_learn[CAM_DEPTH_BITS-1:0])
);
cam
#(
.C_TCAM_ADDR_WIDTH (CAM_DEPTH_BITS),
.C_TCAM_DATA_WIDTH (CAM_WIDTH),
.C_TCAM_ADDR_TYPE (0),
.C_TCAM_MATCH_ADDR_WIDTH(CAM_DEPTH_BITS)
)
dst_mac_cam
(
(* box_type = "user_black_box" *)
.BUSY (cam_busy),
.MATCH (cam_match),
.MATCH_ADDR (cam_match_addr[CAM_DEPTH_BITS-1:0]),
.CLK (axis_aclk),
.CMP_DIN (cam_cmp_din[CAM_WIDTH-1:0]),
.DIN (cam_din[CAM_WIDTH-1:0]),
.WE (cam_we),
.ADDR_WR (cam_wr_addr[CAM_DEPTH_BITS-1:0])
);
output_port_lookup_cpu_regs
#(
.C_BASE_ADDRESS (C_BASEADDR),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH)
)
opl_cpu_regs_inst
(
.clk (axis_aclk),
.resetn (axis_resetn),
.S_AXI_ACLK (S_AXI_ACLK),
.S_AXI_ARESETN (S_AXI_ARESETN),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_RREADY (S_AXI_RREADY),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.id_reg (id_reg),
.version_reg (version_reg),
.reset_reg (reset_reg),
.ip2cpu_flip_reg (ip2cpu_flip_reg),
.cpu2ip_flip_reg (cpu2ip_flip_reg),
.pktin_reg (pktin_reg),
.pktin_reg_clear (pktin_reg_clear),
.pktout_reg (pktout_reg),
.pktout_reg_clear (pktout_reg_clear),
.ip2cpu_debug_reg (ip2cpu_debug_reg),
.cpu2ip_debug_reg (cpu2ip_debug_reg),
.cpu_resetn_soft (),
.resetn_soft (),
.resetn_sync (resetn_sync)
);
assign clear_counters = reset_reg[0];
assign reset_registers = reset_reg[4];
always @(posedge axis_aclk)
if (~resetn_sync | reset_registers) begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;
pktin_reg <= #1 `REG_PKTIN_DEFAULT;
pktout_reg <= #1 `REG_PKTOUT_DEFAULT;
ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;
end
else begin
id_reg <= #1 `REG_ID_DEFAULT;
version_reg <= #1 `REG_VERSION_DEFAULT;
ip2cpu_flip_reg <= #1 ~cpu2ip_flip_reg;
pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;
pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1'h0 : pktin_reg_clear ? 'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready)
> {(`REG_PKTIN_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];
pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;
pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? 'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1'b1}} ?
1'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];
ip2cpu_debug_reg <= #1 cpu2ip_debug_reg;
end
endmodule | 3 |
142,095 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v | 97,045,669 | emu_output_port_lookup_AXIS256_CAM_THREADS.v | v | 429 | 219 | [] | ['netfpga'] | ['all rights reserved'] | null | 'utf-8' codec can't decode bytes in position 6142-6143: unexpected end of data | null | 1: b'%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:54: Cannot find include file: output_port_lookup_cpu_regs_defines.v\n`include "output_port_lookup_cpu_regs_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.sv\n output_port_lookup_cpu_regs_defines.v\n output_port_lookup_cpu_regs_defines.v.v\n output_port_lookup_cpu_regs_defines.v.sv\n obj_dir/output_port_lookup_cpu_regs_defines.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.sv\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:114: Define or directive not defined: \'`REG_ID_BITS\'\n reg [`REG_ID_BITS] id_reg;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:114: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_ID_BITS] id_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:115: Define or directive not defined: \'`REG_VERSION_BITS\'\n reg [`REG_VERSION_BITS] version_reg;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:115: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_VERSION_BITS] version_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:116: Define or directive not defined: \'`REG_RESET_BITS\'\n wire [`REG_RESET_BITS] reset_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:116: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_RESET_BITS] reset_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:117: Define or directive not defined: \'`REG_FLIP_BITS\'\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:118: Define or directive not defined: \'`REG_FLIP_BITS\'\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:119: Define or directive not defined: \'`REG_PKTIN_BITS\'\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:121: Define or directive not defined: \'`REG_PKTOUT_BITS\'\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:123: Define or directive not defined: \'`REG_DEBUG_BITS\'\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:123: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:124: Define or directive not defined: \'`REG_DEBUG_BITS\'\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:124: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:407: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:407: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:408: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:408: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:409: Define or directive not defined: \'`REG_FLIP_DEFAULT\'\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:409: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_flip_reg <= #1 `REG_FLIP_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:410: Define or directive not defined: \'`REG_PKTIN_DEFAULT\'\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:410: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktin_reg <= #1 `REG_PKTIN_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:411: Define or directive not defined: \'`REG_PKTOUT_DEFAULT\'\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:411: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pktout_reg <= #1 `REG_PKTOUT_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:412: Define or directive not defined: \'`REG_DEBUG_DEFAULT\'\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:412: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ip2cpu_debug_reg <= #1 `REG_DEBUG_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:415: Define or directive not defined: \'`REG_ID_DEFAULT\'\n id_reg <= #1 `REG_ID_DEFAULT;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:415: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_reg <= #1 `REG_ID_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:416: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:416: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n version_reg <= #1 `REG_VERSION_DEFAULT;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:418: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:418: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1 clear_counters | pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:419: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:419: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0 : pktin_reg_clear ? \'h0 : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:420: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:420: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:422: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:422: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) ;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:423: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:423: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:423: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1 clear_counters | pktout_reg_clear ? \'h0 : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tlast && m_axis_tvalid && m_axis_tready) > {(`REG_PKTOUT_WIDTH-1){1\'b1}} ?\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_CAM_THREADS.v:424: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n 1\'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 47 error(s)\n' | 313,031 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 3 |
142,098 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v | 97,045,669 | emu_output_port_lookup_AXIS256_gadget_PDF.v | v | 196 | 108 | [] | ['netfpga'] | ['all rights reserved'] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:54: Cannot find include file: output_port_lookup_cpu_regs_defines.v\n`include "output_port_lookup_cpu_regs_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.sv\n output_port_lookup_cpu_regs_defines.v\n output_port_lookup_cpu_regs_defines.v.v\n output_port_lookup_cpu_regs_defines.v.sv\n obj_dir/output_port_lookup_cpu_regs_defines.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.sv\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:116: Define or directive not defined: \'`REG_ID_BITS\'\n reg [`REG_ID_BITS] id_reg;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:116: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_ID_BITS] id_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:117: Define or directive not defined: \'`REG_VERSION_BITS\'\n reg [`REG_VERSION_BITS] version_reg;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_VERSION_BITS] version_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:118: Define or directive not defined: \'`REG_RESET_BITS\'\n wire [`REG_RESET_BITS] reset_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_RESET_BITS] reset_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:119: Define or directive not defined: \'`REG_FLIP_BITS\'\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:120: Define or directive not defined: \'`REG_FLIP_BITS\'\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:120: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:121: Define or directive not defined: \'`REG_PKTIN_BITS\'\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:123: Define or directive not defined: \'`REG_PKTOUT_BITS\'\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:123: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:125: Define or directive not defined: \'`REG_DEBUG_BITS\'\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:126: Define or directive not defined: \'`REG_DEBUG_BITS\'\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^\n%Error: Exiting due to 19 error(s)\n' | 313,033 | module | module emu_output_port_lookup
#(
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter SRC_PORT_POS=16,
parameter DST_PORT_POS=24,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h00000000
)
(
input axis_aclk,
input axis_resetn,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast,
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output [1 : 0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1 :0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY
);
reg [`REG_ID_BITS] id_reg;
reg [`REG_VERSION_BITS] version_reg;
wire [`REG_RESET_BITS] reset_reg;
reg [`REG_FLIP_BITS] ip2cpu_flip_reg;
wire [`REG_FLIP_BITS] cpu2ip_flip_reg;
reg [`REG_PKTIN_BITS] pktin_reg;
wire pktin_reg_clear;
reg [`REG_PKTOUT_BITS] pktout_reg;
wire pktout_reg_clear;
reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;
wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;
wire clear_counters;
wire reset_registers;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
localparam CAM_DEPTH = 16;
localparam CAM_WIDTH = 104;
localparam CAM_DEPTH_BITS = log2(CAM_DEPTH);
wire [63:0] m_axis_tdata_256;
wire [7:0] m_axis_tkeep_256;
wire m_axis_tlast_256;
wire m_axis_tvalid_256;
wire m_axis_tready_256;
wire [63:0] m_axis_tuser_hi_256;
wire [63:0] m_axis_tuser_low_256;
wire [63:0] s_axis_tdata_256;
wire [7:0] s_axis_tkeep_256;
wire s_axis_tlast_256;
wire s_axis_tvalid_256;
wire s_axis_tready_256;
wire [63:0] s_axis_tuser_hi_256;
wire [63:0] s_axis_tuser_low_256;
reg reset;
always @(posedge axis_aclk) reset <= #1 ~axis_resetn;
Emu the_Emu
(
.reset(reset),
.clk(axis_aclk),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tuser_hi(s_axis_tuser[127:64]),
.s_axis_tuser_low(s_axis_tuser[63:0]),
.raw_bw_mem(),
.processed_bw_mem(),
.total_entries(),
.timer_resolution(32'd100),
.bw_resolution(32'd4),
.rst(reset),
.clear()
);
endmodule | module emu_output_port_lookup
#(
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter SRC_PORT_POS=16,
parameter DST_PORT_POS=24,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h00000000
)
(
input axis_aclk,
input axis_resetn,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast,
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output [1 : 0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1 :0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY
); |
reg [`REG_ID_BITS] id_reg;
reg [`REG_VERSION_BITS] version_reg;
wire [`REG_RESET_BITS] reset_reg;
reg [`REG_FLIP_BITS] ip2cpu_flip_reg;
wire [`REG_FLIP_BITS] cpu2ip_flip_reg;
reg [`REG_PKTIN_BITS] pktin_reg;
wire pktin_reg_clear;
reg [`REG_PKTOUT_BITS] pktout_reg;
wire pktout_reg_clear;
reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;
wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;
wire clear_counters;
wire reset_registers;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
localparam CAM_DEPTH = 16;
localparam CAM_WIDTH = 104;
localparam CAM_DEPTH_BITS = log2(CAM_DEPTH);
wire [63:0] m_axis_tdata_256;
wire [7:0] m_axis_tkeep_256;
wire m_axis_tlast_256;
wire m_axis_tvalid_256;
wire m_axis_tready_256;
wire [63:0] m_axis_tuser_hi_256;
wire [63:0] m_axis_tuser_low_256;
wire [63:0] s_axis_tdata_256;
wire [7:0] s_axis_tkeep_256;
wire s_axis_tlast_256;
wire s_axis_tvalid_256;
wire s_axis_tready_256;
wire [63:0] s_axis_tuser_hi_256;
wire [63:0] s_axis_tuser_low_256;
reg reset;
always @(posedge axis_aclk) reset <= #1 ~axis_resetn;
Emu the_Emu
(
.reset(reset),
.clk(axis_aclk),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tuser_hi(s_axis_tuser[127:64]),
.s_axis_tuser_low(s_axis_tuser[63:0]),
.raw_bw_mem(),
.processed_bw_mem(),
.total_entries(),
.timer_resolution(32'd100),
.bw_resolution(32'd4),
.rst(reset),
.clear()
);
endmodule | 3 |
142,099 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v | 97,045,669 | emu_output_port_lookup_AXIS256_gadget_PDF.v | v | 196 | 108 | [] | ['netfpga'] | ['all rights reserved'] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:54: Cannot find include file: output_port_lookup_cpu_regs_defines.v\n`include "output_port_lookup_cpu_regs_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper,data/full_repos/permissive/97045669/output_port_lookup_cpu_regs_defines.v.sv\n output_port_lookup_cpu_regs_defines.v\n output_port_lookup_cpu_regs_defines.v.v\n output_port_lookup_cpu_regs_defines.v.sv\n obj_dir/output_port_lookup_cpu_regs_defines.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.v\n obj_dir/output_port_lookup_cpu_regs_defines.v.sv\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:116: Define or directive not defined: \'`REG_ID_BITS\'\n reg [`REG_ID_BITS] id_reg;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:116: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_ID_BITS] id_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:117: Define or directive not defined: \'`REG_VERSION_BITS\'\n reg [`REG_VERSION_BITS] version_reg;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_VERSION_BITS] version_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:118: Define or directive not defined: \'`REG_RESET_BITS\'\n wire [`REG_RESET_BITS] reset_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_RESET_BITS] reset_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:119: Define or directive not defined: \'`REG_FLIP_BITS\'\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_FLIP_BITS] ip2cpu_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:120: Define or directive not defined: \'`REG_FLIP_BITS\'\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:120: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_FLIP_BITS] cpu2ip_flip_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:121: Define or directive not defined: \'`REG_PKTIN_BITS\'\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTIN_BITS] pktin_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:123: Define or directive not defined: \'`REG_PKTOUT_BITS\'\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:123: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_PKTOUT_BITS] pktout_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:125: Define or directive not defined: \'`REG_DEBUG_BITS\'\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`REG_DEBUG_BITS] ip2cpu_debug_reg;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:126: Define or directive not defined: \'`REG_DEBUG_BITS\'\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/opl_wrapper/emu_output_port_lookup_AXIS256_gadget_PDF.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`REG_DEBUG_BITS] cpu2ip_debug_reg;\n ^\n%Error: Exiting due to 19 error(s)\n' | 313,033 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 3 |
142,100 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl/top_tb_bd.v | 97,045,669 | top_tb_bd.v | v | 71 | 108 | [] | ['netfpga'] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl/top_tb_bd.v:53: Unsupported: Ignoring delay on this delayed statement.\n #(HALF_CORE_PERIOD * 2*200);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl/top_tb_bd.v:62: Unsupported: Ignoring delay on this delayed statement.\n #(HALF_CORE_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl/top_tb_bd.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(HALF_CORE_PERIOD) fpga_sysclk = ~fpga_sysclk;\n ^\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl/top_tb_bd.v:43: Cannot find file containing module: \'reference_emu_wrapper\'\n reference_emu_wrapper top_sim_bd_wrapper\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl,data/full_repos/permissive/97045669/reference_emu_wrapper\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl,data/full_repos/permissive/97045669/reference_emu_wrapper.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_bd/hdl,data/full_repos/permissive/97045669/reference_emu_wrapper.sv\n reference_emu_wrapper\n reference_emu_wrapper.v\n reference_emu_wrapper.sv\n obj_dir/reference_emu_wrapper\n obj_dir/reference_emu_wrapper.v\n obj_dir/reference_emu_wrapper.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,036 | module | module top_tb_bd ();
localparam HALF_CORE_PERIOD = 2.5;
reg reset;
reg fpga_sysclk;
wire fpga_sysclk_p, fpga_sysclk_n;
reference_emu_wrapper top_sim_bd_wrapper
( .fpga_sysclk_n (fpga_sysclk_p),
.fpga_sysclk_p (fpga_sysclk_n),
.reset (reset)
);
initial begin
reset = 1'b1;
#(HALF_CORE_PERIOD * 2*200);
reset = 1'b0;
$display("Reset Deasserted");
end
initial begin
fpga_sysclk = 1'b0;
#(HALF_CORE_PERIOD);
forever
#(HALF_CORE_PERIOD) fpga_sysclk = ~fpga_sysclk;
end
assign fpga_sysclk_p = fpga_sysclk;
assign fpga_sysclk_n = ~fpga_sysclk;
endmodule | module top_tb_bd (); |
localparam HALF_CORE_PERIOD = 2.5;
reg reset;
reg fpga_sysclk;
wire fpga_sysclk_p, fpga_sysclk_n;
reference_emu_wrapper top_sim_bd_wrapper
( .fpga_sysclk_n (fpga_sysclk_p),
.fpga_sysclk_p (fpga_sysclk_n),
.reset (reset)
);
initial begin
reset = 1'b1;
#(HALF_CORE_PERIOD * 2*200);
reset = 1'b0;
$display("Reset Deasserted");
end
initial begin
fpga_sysclk = 1'b0;
#(HALF_CORE_PERIOD);
forever
#(HALF_CORE_PERIOD) fpga_sysclk = ~fpga_sysclk;
end
assign fpga_sysclk_p = fpga_sysclk;
assign fpga_sysclk_n = ~fpga_sysclk;
endmodule | 3 |
142,102 | data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v | 97,045,669 | top.v | v | 1,270 | 126 | [] | ['netfpga'] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:459: Cannot find file containing module: \'OBUF\'\nOBUF led_0_obuf (\n^~~~\n ... Looked in:\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl,data/full_repos/permissive/97045669/OBUF\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl,data/full_repos/permissive/97045669/OBUF.v\n data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl,data/full_repos/permissive/97045669/OBUF.sv\n OBUF\n OBUF.v\n OBUF.sv\n obj_dir/OBUF\n obj_dir/OBUF.v\n obj_dir/OBUF.sv\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:465: Cannot find file containing module: \'OBUF\'\nOBUF led_1_obuf (\n^~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:472: Cannot find file containing module: \'IBUF\'\nIBUF sys_reset_n_ibuf( \n^~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:477: Cannot find file containing module: \'IBUFDS_GTE2\'\nIBUFDS_GTE2 #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:489: Cannot find file containing module: \'IOBUF\'\nIOBUF i2c_scl_iobuf (\n^~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:496: Cannot find file containing module: \'IOBUF\'\nIOBUF i2c_sda_iobuf (\n^~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:503: Cannot find file containing module: \'axi_clocking\'\naxi_clocking axi_clocking_i (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:512: Cannot find file containing module: \'BUFG\'\nBUFG axi_lite_bufg0 (\n^~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:520: Cannot find file containing module: \'proc_sys_reset_ip\'\nproc_sys_reset_ip proc_sys_reset_i (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:555: Cannot find file containing module: \'nf_datapath\'\nnf_datapath \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:697: Cannot find file containing module: \'control_sub\'\ncontrol_sub control_sub_i\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:909: Cannot find file containing module: \'nf_10g_interface_shared_ip\'\nnf_10g_interface_shared_ip nf_10g_interface_0\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:991: Cannot find file containing module: \'nf_10g_interface_ip\'\nnf_10g_interface_ip nf_10g_interface_1\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:1069: Cannot find file containing module: \'nf_10g_interface_ip\'\nnf_10g_interface_ip nf_10g_interface_2\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:1149: Cannot find file containing module: \'nf_10g_interface_ip\'\nnf_10g_interface_ip nf_10g_interface_3\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:1227: Cannot find file containing module: \'identifier_ip\'\nidentifier_ip identifier (\n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:1256: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'sfp_clk100_count\' generates 28 bits.\n : ... In instance top\n if (!sfp_clk100_count) begin\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/netfpga_src/NetFPGA-SUME/project/reference_emu/hw_vb/hdl/top.v:1264: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'sfp_clk156_count\' generates 28 bits.\n : ... In instance top\n if (!sfp_clk156_count) begin\n ^\n%Error: Exiting due to 16 error(s), 2 warning(s)\n' | 313,039 | module | module top # (
parameter C_DATA_WIDTH = 256,
parameter C_TUSER_WIDTH = 128
) (
input [7:0]pcie_7x_mgt_rxn,
input [7:0]pcie_7x_mgt_rxp,
output [7:0]pcie_7x_mgt_txn,
output [7:0]pcie_7x_mgt_txp,
input sfp0_rx_p,
input sfp0_rx_n,
output sfp0_tx_p,
output sfp0_tx_n,
input sfp0_tx_fault,
input sfp0_tx_abs,
output sfp0_tx_disable,
input sfp1_rx_p,
input sfp1_rx_n,
output sfp1_tx_p,
output sfp1_tx_n,
input sfp1_tx_fault,
input sfp1_tx_abs,
output sfp1_tx_disable,
input sfp2_rx_p,
input sfp2_rx_n,
output sfp2_tx_p,
output sfp2_tx_n,
input sfp2_tx_fault,
input sfp2_tx_abs,
output sfp2_tx_disable,
input sfp3_rx_p,
input sfp3_rx_n,
output sfp3_tx_p,
output sfp3_tx_n,
input sfp3_tx_fault,
input sfp3_tx_abs,
output sfp3_tx_disable,
input sys_clkp,
input sys_clkn,
input fpga_sysclk_p,
input fpga_sysclk_n,
input xphy_refclk_p,
input xphy_refclk_n,
output [1:0] leds,
output sfp0_tx_led,
output sfp1_tx_led,
output sfp2_tx_led,
output sfp3_tx_led,
output sfp0_rx_led,
output sfp1_rx_led,
output sfp2_rx_led,
output sfp3_rx_led,
inout i2c_clk,
inout i2c_data,
output [1:0] i2c_reset,
input uart_rxd,
output uart_txd,
input sys_reset_n
);
wire sys_clk;
wire clk_200;
wire sys_rst_n_c;
wire clk_200_locked;
wire[C_DATA_WIDTH-1:0] axis_i_0_tdata;
wire axis_i_0_tvalid;
wire axis_i_0_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_0_tuser;
wire[(C_DATA_WIDTH/8)-1:0] axis_i_0_tkeep;
wire axis_i_0_tready;
wire[C_DATA_WIDTH-1:0] axis_o_0_tdata;
wire axis_o_0_tvalid;
wire axis_o_0_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_0_tuser;
wire[(C_DATA_WIDTH/8)-1:0] axis_o_0_tkeep;
wire axis_o_0_tready;
wire[C_DATA_WIDTH-1:0] axis_i_1_tdata;
wire axis_i_1_tvalid;
wire axis_i_1_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_1_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_i_1_tkeep;
wire axis_i_1_tready;
wire[C_DATA_WIDTH-1:0] axis_o_1_tdata;
wire axis_o_1_tvalid;
wire axis_o_1_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_1_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_o_1_tkeep;
wire axis_o_1_tready;
wire[C_DATA_WIDTH-1:0] axis_i_2_tdata;
wire axis_i_2_tvalid;
wire axis_i_2_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_2_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_i_2_tkeep;
wire axis_i_2_tready;
wire[C_DATA_WIDTH-1:0] axis_o_2_tdata;
wire axis_o_2_tvalid;
wire axis_o_2_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_2_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_o_2_tkeep;
wire axis_o_2_tready;
wire[C_DATA_WIDTH-1:0] axis_i_3_tdata;
wire axis_i_3_tvalid;
wire axis_i_3_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_3_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_i_3_tkeep;
wire axis_i_3_tready;
wire[C_DATA_WIDTH-1:0] axis_o_3_tdata;
wire axis_o_3_tvalid;
wire axis_o_3_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_3_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_o_3_tkeep;
wire axis_o_3_tready;
wire [255:0] axis_dma_i_tdata ;
wire [31:0] axis_dma_i_tkeep ;
wire axis_dma_i_tlast ;
wire axis_dma_i_tready;
wire [255:0] axis_dma_i_tuser ;
wire axis_dma_i_tvalid;
wire [255:0] axis_dma_o_tdata;
wire [31:0] axis_dma_o_tkeep;
wire axis_dma_o_tlast;
wire axis_dma_o_tready;
wire [127:0] axis_dma_o_tuser;
wire axis_dma_o_tvalid;
wire [11:0] M00_AXI_araddr;
wire [2:0] M00_AXI_arprot;
wire [0:0] M00_AXI_arready;
wire [0:0] M00_AXI_arvalid;
wire [11:0] M00_AXI_awaddr;
wire [2:0] M00_AXI_awprot;
wire [0:0] M00_AXI_awready;
wire [0:0] M00_AXI_awvalid;
wire [0:0] M00_AXI_bready;
wire [1:0] M00_AXI_bresp;
wire [0:0] M00_AXI_bvalid;
wire [31:0] M00_AXI_rdata;
wire [0:0] M00_AXI_rready;
wire [1:0] M00_AXI_rresp;
wire [0:0] M00_AXI_rvalid;
wire [31:0] M00_AXI_wdata;
wire [0:0] M00_AXI_wready;
wire [3:0] M00_AXI_wstrb;
wire [0:0] M00_AXI_wvalid;
wire [11:0] M01_AXI_araddr;
wire [2:0] M01_AXI_arprot;
wire [0:0] M01_AXI_arready;
wire [0:0] M01_AXI_arvalid;
wire [11:0] M01_AXI_awaddr;
wire [2:0] M01_AXI_awprot;
wire [0:0] M01_AXI_awready;
wire [0:0] M01_AXI_awvalid;
wire [0:0] M01_AXI_bready;
wire [1:0] M01_AXI_bresp;
wire [0:0] M01_AXI_bvalid;
wire [31:0] M01_AXI_rdata;
wire [0:0] M01_AXI_rready;
wire [1:0] M01_AXI_rresp;
wire [0:0] M01_AXI_rvalid;
wire [31:0] M01_AXI_wdata;
wire [0:0] M01_AXI_wready;
wire [3:0] M01_AXI_wstrb;
wire [0:0] M01_AXI_wvalid;
wire [11:0] M02_AXI_araddr;
wire [2:0] M02_AXI_arprot;
wire [0:0] M02_AXI_arready;
wire [0:0] M02_AXI_arvalid;
wire [11:0] M02_AXI_awaddr;
wire [2:0] M02_AXI_awprot;
wire [0:0] M02_AXI_awready;
wire [0:0] M02_AXI_awvalid;
wire [0:0] M02_AXI_bready;
wire [1:0] M02_AXI_bresp;
wire [0:0] M02_AXI_bvalid;
wire [31:0] M02_AXI_rdata;
wire [0:0] M02_AXI_rready;
wire [1:0] M02_AXI_rresp;
wire [0:0] M02_AXI_rvalid;
wire [31:0] M02_AXI_wdata;
wire [0:0] M02_AXI_wready;
wire [3:0] M02_AXI_wstrb;
wire [0:0] M02_AXI_wvalid;
wire [11:0] M03_AXI_araddr;
wire [2:0] M03_AXI_arprot;
wire [0:0] M03_AXI_arready;
wire [0:0] M03_AXI_arvalid;
wire [11:0] M03_AXI_awaddr;
wire [2:0] M03_AXI_awprot;
wire [0:0] M03_AXI_awready;
wire [0:0] M03_AXI_awvalid;
wire [0:0] M03_AXI_bready;
wire [1:0] M03_AXI_bresp;
wire [0:0] M03_AXI_bvalid;
wire [31:0] M03_AXI_rdata;
wire [0:0] M03_AXI_rready;
wire [1:0] M03_AXI_rresp;
wire [0:0] M03_AXI_rvalid;
wire [31:0] M03_AXI_wdata;
wire [0:0] M03_AXI_wready;
wire [3:0] M03_AXI_wstrb;
wire [0:0] M03_AXI_wvalid;
wire [11:0] M04_AXI_araddr;
wire [2:0] M04_AXI_arprot;
wire [0:0] M04_AXI_arready;
wire [0:0] M04_AXI_arvalid;
wire [11:0] M04_AXI_awaddr;
wire [2:0] M04_AXI_awprot;
wire [0:0] M04_AXI_awready;
wire [0:0] M04_AXI_awvalid;
wire [0:0] M04_AXI_bready;
wire [1:0] M04_AXI_bresp;
wire [0:0] M04_AXI_bvalid;
wire [31:0] M04_AXI_rdata;
wire [0:0] M04_AXI_rready;
wire [1:0] M04_AXI_rresp;
wire [0:0] M04_AXI_rvalid;
wire [31:0] M04_AXI_wdata;
wire [0:0] M04_AXI_wready;
wire [3:0] M04_AXI_wstrb;
wire [0:0] M04_AXI_wvalid;
wire [11:0] M05_AXI_araddr;
wire [2:0] M05_AXI_arprot;
wire [0:0] M05_AXI_arready;
wire [0:0] M05_AXI_arvalid;
wire [11:0] M05_AXI_awaddr;
wire [2:0] M05_AXI_awprot;
wire [0:0] M05_AXI_awready;
wire [0:0] M05_AXI_awvalid;
wire [0:0] M05_AXI_bready;
wire [1:0] M05_AXI_bresp;
wire [0:0] M05_AXI_bvalid;
wire [31:0] M05_AXI_rdata;
wire [0:0] M05_AXI_rready;
wire [1:0] M05_AXI_rresp;
wire [0:0] M05_AXI_rvalid;
wire [31:0] M05_AXI_wdata;
wire [0:0] M05_AXI_wready;
wire [3:0] M05_AXI_wstrb;
wire [0:0] M05_AXI_wvalid;
wire [11:0] M06_AXI_araddr;
wire [2:0] M06_AXI_arprot;
wire [0:0] M06_AXI_arready;
wire [0:0] M06_AXI_arvalid;
wire [11:0] M06_AXI_awaddr;
wire [2:0] M06_AXI_awprot;
wire [0:0] M06_AXI_awready;
wire [0:0] M06_AXI_awvalid;
wire [0:0] M06_AXI_bready;
wire [1:0] M06_AXI_bresp;
wire [0:0] M06_AXI_bvalid;
wire [31:0] M06_AXI_rdata;
wire [0:0] M06_AXI_rready;
wire [1:0] M06_AXI_rresp;
wire [0:0] M06_AXI_rvalid;
wire [31:0] M06_AXI_wdata;
wire [0:0] M06_AXI_wready;
wire [3:0] M06_AXI_wstrb;
wire [0:0] M06_AXI_wvalid;
wire [11:0] M07_AXI_araddr;
wire [2:0] M07_AXI_arprot;
wire [0:0] M07_AXI_arready;
wire [0:0] M07_AXI_arvalid;
wire [11:0] M07_AXI_awaddr;
wire [2:0] M07_AXI_awprot;
wire [0:0] M07_AXI_awready;
wire [0:0] M07_AXI_awvalid;
wire [0:0] M07_AXI_bready;
wire [1:0] M07_AXI_bresp;
wire [0:0] M07_AXI_bvalid;
wire [31:0] M07_AXI_rdata;
wire [0:0] M07_AXI_rready;
wire [1:0] M07_AXI_rresp;
wire [0:0] M07_AXI_rvalid;
wire [31:0] M07_AXI_wdata;
wire [0:0] M07_AXI_wready;
wire [3:0] M07_AXI_wstrb;
wire [0:0] M07_AXI_wvalid;
wire sfp_qplllock ;
wire sfp_qplloutrefclk;
wire sfp_qplloutclk ;
wire sfp_clk156;
wire sfp_areset_clk156;
wire sfp_gttxreset;
wire sfp_gtrxreset;
wire sfp_txuserrdy;
wire sfp_txusrclk;
wire sfp_txusrclk2;
wire sfp_reset_counter_done;
wire sfp_tx_axis_areset;
wire sfp_tx_axis_aresetn;
wire sfp_rx_axis_aresetn;
wire port0_ready;
wire block0_lock;
wire sfp0_resetdone;
wire sfp0_txclk322;
wire port1_ready;
wire block1_lock;
wire sfp1_tx_resetdone;
wire sfp1_rx_resetdone;
wire sfp1_txclk322;
wire port2_ready;
wire block2_lock;
wire sfp2_tx_resetdone;
wire sfp2_rx_resetdone;
wire sfp2_txclk322;
wire port3_ready;
wire block3_lock;
wire sfp3_tx_resetdone;
wire sfp3_rx_resetdone;
wire sfp3_txclk322;
wire i2c_scl_o;
wire i2c_scl_i;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_i;
wire i2c_sda_t;
wire axi_clk;
wire axi_aresetn;
wire sys_reset;
(* ASYNC_REG = "TRUE" *) reg [3:0] core200_reset_sync_n;
wire axis_resetn;
wire axi_datapath_resetn;
wire peripheral_reset;
localparam IF_SFP0 = 8'b00000001;
localparam IF_SFP1 = 8'b00000100;
localparam IF_SFP2 = 8'b00010000;
localparam IF_SFP3 = 8'b01000000;
reg [27:0] sfp_clk156_count;
reg [27:0] sfp_clk100_count;
reg [1:0] led;
OBUF led_0_obuf (
.O (leds[0]),
.I (led[0])
);
OBUF led_1_obuf (
.O (leds[1]),
.I (led[1])
);
IBUF sys_reset_n_ibuf(
.O (sys_rst_n_c),
.I (sys_reset_n)
);
IBUFDS_GTE2 #(
.CLKCM_CFG ("TRUE"),
.CLKRCV_TRST ("TRUE"),
.CLKSWING_CFG (2'b11)
) IBUFDS_GTE2_inst (
.O (sys_clk),
.ODIV2 (),
.CEB (1'b0),
.I (sys_clkp),
.IB (sys_clkn)
);
IOBUF i2c_scl_iobuf (
.I (i2c_scl_o),
.IO (i2c_clk),
.O (i2c_scl_i),
.T (i2c_scl_t)
);
IOBUF i2c_sda_iobuf (
.I (i2c_sda_o),
.IO (i2c_data),
.O (i2c_sda_i),
.T (i2c_sda_t)
);
axi_clocking axi_clocking_i (
.clk_in_p (fpga_sysclk_p),
.clk_in_n (fpga_sysclk_n),
.clk_200 (clk_200),
.locked (clk_200_locked),
.resetn (sys_rst_n_c)
);
BUFG axi_lite_bufg0 (
.I (sys_clk),
.O (axi_clk)
);
proc_sys_reset_ip proc_sys_reset_i (
.slowest_sync_clk(clk_200),
.ext_reset_in(sys_rst_n_c),
.aux_reset_in(1'b1),
.mb_debug_sys_rst(1'b0),
.dcm_locked(clk_200_locked),
.mb_reset(),
.bus_struct_reset(),
.peripheral_reset(peripheral_reset),
.interconnect_aresetn(),
.peripheral_aresetn(axis_resetn)
);
assign sys_reset = !sys_rst_n_c;
always @ (posedge clk_200) begin
if (!sys_rst_n_c)
core200_reset_sync_n <= 4'h0;
else
core200_reset_sync_n <= #1 {core200_reset_sync_n[2:0],sys_rst_n_c};
end
assign axi_aresetn = axis_resetn;
assign axi_datapath_resetn = axis_resetn;
nf_datapath
#(
.C_M_AXIS_DATA_WIDTH (C_DATA_WIDTH),
.C_S_AXIS_DATA_WIDTH (C_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH (12),
.C_M_AXIS_TUSER_WIDTH (128),
.C_S_AXIS_TUSER_WIDTH (128),
.NUM_QUEUES (5)
)
nf_datapath_0
(
.axis_aclk (clk_200),
.axis_resetn (axis_resetn),
.axi_aclk (clk_200),
.axi_resetn (axi_datapath_resetn),
.s_axis_0_tdata (axis_i_0_tdata),
.s_axis_0_tkeep (axis_i_0_tkeep),
.s_axis_0_tuser (axis_i_0_tuser),
.s_axis_0_tvalid (axis_i_0_tvalid),
.s_axis_0_tready (axis_i_0_tready),
.s_axis_0_tlast (axis_i_0_tlast),
.s_axis_1_tdata (axis_i_1_tdata),
.s_axis_1_tkeep (axis_i_1_tkeep),
.s_axis_1_tuser (axis_i_1_tuser),
.s_axis_1_tvalid (axis_i_1_tvalid),
.s_axis_1_tready (axis_i_1_tready),
.s_axis_1_tlast (axis_i_1_tlast),
.s_axis_2_tdata (axis_i_2_tdata),
.s_axis_2_tkeep (axis_i_2_tkeep),
.s_axis_2_tuser (axis_i_2_tuser),
.s_axis_2_tvalid (axis_i_2_tvalid),
.s_axis_2_tready (axis_i_2_tready),
.s_axis_2_tlast (axis_i_2_tlast),
.s_axis_3_tdata (axis_i_3_tdata),
.s_axis_3_tkeep (axis_i_3_tkeep),
.s_axis_3_tuser (axis_i_3_tuser),
.s_axis_3_tvalid (axis_i_3_tvalid),
.s_axis_3_tready (axis_i_3_tready),
.s_axis_3_tlast (axis_i_3_tlast),
.s_axis_4_tdata (axis_dma_i_tdata ),
.s_axis_4_tkeep (axis_dma_i_tkeep ),
.s_axis_4_tuser (axis_dma_i_tuser[127:0] ),
.s_axis_4_tvalid (axis_dma_i_tvalid),
.s_axis_4_tready (axis_dma_i_tready ),
.s_axis_4_tlast (axis_dma_i_tlast),
.m_axis_0_tdata (axis_o_0_tdata),
.m_axis_0_tkeep (axis_o_0_tkeep),
.m_axis_0_tuser (axis_o_0_tuser),
.m_axis_0_tvalid (axis_o_0_tvalid),
.m_axis_0_tready (axis_o_0_tready),
.m_axis_0_tlast (axis_o_0_tlast),
.m_axis_1_tdata (axis_o_1_tdata),
.m_axis_1_tkeep (axis_o_1_tkeep),
.m_axis_1_tuser (axis_o_1_tuser),
.m_axis_1_tvalid (axis_o_1_tvalid),
.m_axis_1_tready (axis_o_1_tready),
.m_axis_1_tlast (axis_o_1_tlast),
.m_axis_2_tdata (axis_o_2_tdata),
.m_axis_2_tkeep (axis_o_2_tkeep),
.m_axis_2_tuser (axis_o_2_tuser),
.m_axis_2_tvalid (axis_o_2_tvalid),
.m_axis_2_tready (axis_o_2_tready),
.m_axis_2_tlast (axis_o_2_tlast),
.m_axis_3_tdata (axis_o_3_tdata ),
.m_axis_3_tkeep (axis_o_3_tkeep ),
.m_axis_3_tuser (axis_o_3_tuser ),
.m_axis_3_tvalid (axis_o_3_tvalid),
.m_axis_3_tready (axis_o_3_tready),
.m_axis_3_tlast (axis_o_3_tlast ),
.m_axis_4_tdata (axis_dma_o_tdata ),
.m_axis_4_tkeep (axis_dma_o_tkeep ),
.m_axis_4_tuser (axis_dma_o_tuser ),
.m_axis_4_tvalid (axis_dma_o_tvalid),
.m_axis_4_tready (axis_dma_o_tready ),
.m_axis_4_tlast (axis_dma_o_tlast),
.S0_AXI_AWADDR (M01_AXI_awaddr),
.S0_AXI_AWVALID (M01_AXI_awvalid),
.S0_AXI_WDATA (M01_AXI_wdata),
.S0_AXI_WSTRB (M01_AXI_wstrb),
.S0_AXI_WVALID (M01_AXI_wvalid),
.S0_AXI_BREADY (M01_AXI_bready),
.S0_AXI_ARADDR (M01_AXI_araddr),
.S0_AXI_ARVALID (M01_AXI_arvalid),
.S0_AXI_RREADY (M01_AXI_rready),
.S0_AXI_ARREADY (M01_AXI_arready),
.S0_AXI_RDATA (M01_AXI_rdata),
.S0_AXI_RRESP (M01_AXI_rresp),
.S0_AXI_RVALID (M01_AXI_rvalid),
.S0_AXI_WREADY (M01_AXI_wready),
.S0_AXI_BRESP (M01_AXI_bresp),
.S0_AXI_BVALID (M01_AXI_bvalid),
.S0_AXI_AWREADY (M01_AXI_awready),
.S1_AXI_AWADDR (M02_AXI_awaddr),
.S1_AXI_AWVALID (M02_AXI_awvalid),
.S1_AXI_WDATA (M02_AXI_wdata),
.S1_AXI_WSTRB (M02_AXI_wstrb),
.S1_AXI_WVALID (M02_AXI_wvalid),
.S1_AXI_BREADY (M02_AXI_bready),
.S1_AXI_ARADDR (M02_AXI_araddr),
.S1_AXI_ARVALID (M02_AXI_arvalid),
.S1_AXI_RREADY (M02_AXI_rready),
.S1_AXI_ARREADY (M02_AXI_arready),
.S1_AXI_RDATA (M02_AXI_rdata),
.S1_AXI_RRESP (M02_AXI_rresp),
.S1_AXI_RVALID (M02_AXI_rvalid),
.S1_AXI_WREADY (M02_AXI_wready),
.S1_AXI_BRESP (M02_AXI_bresp),
.S1_AXI_BVALID (M02_AXI_bvalid),
.S1_AXI_AWREADY (M02_AXI_awready),
.S2_AXI_AWADDR (M03_AXI_awaddr),
.S2_AXI_AWVALID (M03_AXI_awvalid),
.S2_AXI_WDATA (M03_AXI_wdata),
.S2_AXI_WSTRB (M03_AXI_wstrb),
.S2_AXI_WVALID (M03_AXI_wvalid),
.S2_AXI_BREADY (M03_AXI_bready),
.S2_AXI_ARADDR (M03_AXI_araddr),
.S2_AXI_ARVALID (M03_AXI_arvalid),
.S2_AXI_RREADY (M03_AXI_rready),
.S2_AXI_ARREADY (M03_AXI_arready),
.S2_AXI_RDATA (M03_AXI_rdata),
.S2_AXI_RRESP (M03_AXI_rresp),
.S2_AXI_RVALID (M03_AXI_rvalid),
.S2_AXI_WREADY (M03_AXI_wready),
.S2_AXI_BRESP (M03_AXI_bresp),
.S2_AXI_BVALID (M03_AXI_bvalid),
.S2_AXI_AWREADY (M03_AXI_awready)
);
control_sub control_sub_i
(
.M00_AXI_araddr (M00_AXI_araddr ),
.M00_AXI_arprot (M00_AXI_arprot ),
.M00_AXI_arready (M00_AXI_arready ),
.M00_AXI_arvalid (M00_AXI_arvalid ),
.M00_AXI_awaddr (M00_AXI_awaddr ),
.M00_AXI_awprot (M00_AXI_awprot ),
.M00_AXI_awready (M00_AXI_awready ),
.M00_AXI_awvalid (M00_AXI_awvalid ),
.M00_AXI_bready (M00_AXI_bready ),
.M00_AXI_bresp (M00_AXI_bresp ),
.M00_AXI_bvalid (M00_AXI_bvalid ),
.M00_AXI_rdata (M00_AXI_rdata ),
.M00_AXI_rready (M00_AXI_rready ),
.M00_AXI_rresp (M00_AXI_rresp ),
.M00_AXI_rvalid (M00_AXI_rvalid ),
.M00_AXI_wdata (M00_AXI_wdata ),
.M00_AXI_wready (M00_AXI_wready ),
.M00_AXI_wstrb (M00_AXI_wstrb ),
.M00_AXI_wvalid (M00_AXI_wvalid ),
.M01_AXI_araddr (M01_AXI_araddr ),
.M01_AXI_arprot (M01_AXI_arprot ),
.M01_AXI_arready (M01_AXI_arready ),
.M01_AXI_arvalid (M01_AXI_arvalid ),
.M01_AXI_awaddr (M01_AXI_awaddr ),
.M01_AXI_awprot (M01_AXI_awprot ),
.M01_AXI_awready (M01_AXI_awready ),
.M01_AXI_awvalid (M01_AXI_awvalid ),
.M01_AXI_bready (M01_AXI_bready ),
.M01_AXI_bresp (M01_AXI_bresp ),
.M01_AXI_bvalid (M01_AXI_bvalid ),
.M01_AXI_rdata (M01_AXI_rdata ),
.M01_AXI_rready (M01_AXI_rready ),
.M01_AXI_rresp (M01_AXI_rresp ),
.M01_AXI_rvalid (M01_AXI_rvalid ),
.M01_AXI_wdata (M01_AXI_wdata ),
.M01_AXI_wready (M01_AXI_wready ),
.M01_AXI_wstrb (M01_AXI_wstrb ),
.M01_AXI_wvalid (M01_AXI_wvalid ),
.M02_AXI_araddr (M02_AXI_araddr ),
.M02_AXI_arprot (M02_AXI_arprot ),
.M02_AXI_arready (M02_AXI_arready ),
.M02_AXI_arvalid (M02_AXI_arvalid ),
.M02_AXI_awaddr (M02_AXI_awaddr ),
.M02_AXI_awprot (M02_AXI_awprot ),
.M02_AXI_awready (M02_AXI_awready ),
.M02_AXI_awvalid (M02_AXI_awvalid ),
.M02_AXI_bready (M02_AXI_bready ),
.M02_AXI_bresp (M02_AXI_bresp ),
.M02_AXI_bvalid (M02_AXI_bvalid ),
.M02_AXI_rdata (M02_AXI_rdata ),
.M02_AXI_rready (M02_AXI_rready ),
.M02_AXI_rresp (M02_AXI_rresp ),
.M02_AXI_rvalid (M02_AXI_rvalid ),
.M02_AXI_wdata (M02_AXI_wdata ),
.M02_AXI_wready (M02_AXI_wready ),
.M02_AXI_wstrb (M02_AXI_wstrb ),
.M02_AXI_wvalid (M02_AXI_wvalid ),
.M03_AXI_araddr (M03_AXI_araddr ),
.M03_AXI_arprot (M03_AXI_arprot ),
.M03_AXI_arready (M03_AXI_arready),
.M03_AXI_arvalid (M03_AXI_arvalid),
.M03_AXI_awaddr (M03_AXI_awaddr ),
.M03_AXI_awprot (M03_AXI_awprot ),
.M03_AXI_awready (M03_AXI_awready),
.M03_AXI_awvalid (M03_AXI_awvalid),
.M03_AXI_bready (M03_AXI_bready ),
.M03_AXI_bresp (M03_AXI_bresp ),
.M03_AXI_bvalid (M03_AXI_bvalid ),
.M03_AXI_rdata (M03_AXI_rdata ),
.M03_AXI_rready (M03_AXI_rready ),
.M03_AXI_rresp (M03_AXI_rresp ),
.M03_AXI_rvalid (M03_AXI_rvalid ),
.M03_AXI_wdata (M03_AXI_wdata ),
.M03_AXI_wready (M03_AXI_wready ),
.M03_AXI_wstrb (M03_AXI_wstrb ),
.M03_AXI_wvalid (M03_AXI_wvalid ),
.M04_AXI_araddr (M04_AXI_araddr ),
.M04_AXI_arprot (M04_AXI_arprot ),
.M04_AXI_arready (M04_AXI_arready),
.M04_AXI_arvalid (M04_AXI_arvalid),
.M04_AXI_awaddr (M04_AXI_awaddr ),
.M04_AXI_awprot (M04_AXI_awprot ),
.M04_AXI_awready (M04_AXI_awready),
.M04_AXI_awvalid (M04_AXI_awvalid),
.M04_AXI_bready (M04_AXI_bready ),
.M04_AXI_bresp (M04_AXI_bresp ),
.M04_AXI_bvalid (M04_AXI_bvalid ),
.M04_AXI_rdata (M04_AXI_rdata ),
.M04_AXI_rready (M04_AXI_rready ),
.M04_AXI_rresp (M04_AXI_rresp ),
.M04_AXI_rvalid (M04_AXI_rvalid ),
.M04_AXI_wdata (M04_AXI_wdata ),
.M04_AXI_wready (M04_AXI_wready ),
.M04_AXI_wstrb (M04_AXI_wstrb ),
.M04_AXI_wvalid (M04_AXI_wvalid ),
.M05_AXI_araddr (M05_AXI_araddr ),
.M05_AXI_arprot (M05_AXI_arprot ),
.M05_AXI_arready (M05_AXI_arready),
.M05_AXI_arvalid (M05_AXI_arvalid),
.M05_AXI_awaddr (M05_AXI_awaddr ),
.M05_AXI_awprot (M05_AXI_awprot ),
.M05_AXI_awready (M05_AXI_awready),
.M05_AXI_awvalid (M05_AXI_awvalid),
.M05_AXI_bready (M05_AXI_bready ),
.M05_AXI_bresp (M05_AXI_bresp ),
.M05_AXI_bvalid (M05_AXI_bvalid ),
.M05_AXI_rdata (M05_AXI_rdata ),
.M05_AXI_rready (M05_AXI_rready ),
.M05_AXI_rresp (M05_AXI_rresp ),
.M05_AXI_rvalid (M05_AXI_rvalid ),
.M05_AXI_wdata (M05_AXI_wdata ),
.M05_AXI_wready (M05_AXI_wready ),
.M05_AXI_wstrb (M05_AXI_wstrb ),
.M05_AXI_wvalid (M05_AXI_wvalid ),
.M06_AXI_araddr (M06_AXI_araddr ),
.M06_AXI_arprot (M06_AXI_arprot ),
.M06_AXI_arready (M06_AXI_arready),
.M06_AXI_arvalid (M06_AXI_arvalid),
.M06_AXI_awaddr (M06_AXI_awaddr ),
.M06_AXI_awprot (M06_AXI_awprot ),
.M06_AXI_awready (M06_AXI_awready),
.M06_AXI_awvalid (M06_AXI_awvalid),
.M06_AXI_bready (M06_AXI_bready ),
.M06_AXI_bresp (M06_AXI_bresp ),
.M06_AXI_bvalid (M06_AXI_bvalid ),
.M06_AXI_rdata (M06_AXI_rdata ),
.M06_AXI_rready (M06_AXI_rready ),
.M06_AXI_rresp (M06_AXI_rresp ),
.M06_AXI_rvalid (M06_AXI_rvalid ),
.M06_AXI_wdata (M06_AXI_wdata ),
.M06_AXI_wready (M06_AXI_wready ),
.M06_AXI_wstrb (M06_AXI_wstrb ),
.M06_AXI_wvalid (M06_AXI_wvalid ),
.M07_AXI_araddr (M07_AXI_araddr ),
.M07_AXI_arprot (M07_AXI_arprot ),
.M07_AXI_arready (M07_AXI_arready),
.M07_AXI_arvalid (M07_AXI_arvalid),
.M07_AXI_awaddr (M07_AXI_awaddr ),
.M07_AXI_awprot (M07_AXI_awprot ),
.M07_AXI_awready (M07_AXI_awready),
.M07_AXI_awvalid (M07_AXI_awvalid),
.M07_AXI_bready (M07_AXI_bready ),
.M07_AXI_bresp (M07_AXI_bresp ),
.M07_AXI_bvalid (M07_AXI_bvalid ),
.M07_AXI_rdata (M07_AXI_rdata ),
.M07_AXI_rready (M07_AXI_rready ),
.M07_AXI_rresp (M07_AXI_rresp ),
.M07_AXI_rvalid (M07_AXI_rvalid ),
.M07_AXI_wdata (M07_AXI_wdata ),
.M07_AXI_wready (M07_AXI_wready ),
.M07_AXI_wstrb (M07_AXI_wstrb ),
.M07_AXI_wvalid (M07_AXI_wvalid ),
.iic_fpga_scl_i(i2c_scl_i),
.iic_fpga_scl_o(i2c_scl_o),
.iic_fpga_scl_t(i2c_scl_t),
.iic_fpga_sda_i(i2c_sda_i),
.iic_fpga_sda_o(i2c_sda_o),
.iic_fpga_sda_t(i2c_sda_t),
.iic_reset (i2c_reset),
.uart_txd (uart_txd),
.uart_rxd (uart_rxd),
.axi_lite_aclk (axi_clk),
.axi_lite_aresetn (axi_aresetn),
.axis_datapath_aclk (clk_200),
.axis_datapath_aresetn (axis_resetn),
.m_axis_dma_tx_tdata (axis_dma_i_tdata),
.m_axis_dma_tx_tkeep (axis_dma_i_tkeep),
.m_axis_dma_tx_tlast (axis_dma_i_tlast),
.m_axis_dma_tx_tready (axis_dma_i_tready),
.m_axis_dma_tx_tuser (axis_dma_i_tuser),
.m_axis_dma_tx_tvalid (axis_dma_i_tvalid),
.s_axis_dma_rx_tdata (axis_dma_o_tdata),
.s_axis_dma_rx_tkeep (axis_dma_o_tkeep),
.s_axis_dma_rx_tlast (axis_dma_o_tlast),
.s_axis_dma_rx_tready (axis_dma_o_tready),
.s_axis_dma_rx_tuser ({128'h0,axis_dma_o_tuser}),
.s_axis_dma_rx_tvalid (axis_dma_o_tvalid),
.pcie_7x_mgt_rxn (pcie_7x_mgt_rxn),
.pcie_7x_mgt_rxp (pcie_7x_mgt_rxp),
.pcie_7x_mgt_txn (pcie_7x_mgt_txn),
.pcie_7x_mgt_txp (pcie_7x_mgt_txp),
.sys_clk (sys_clk),
.sys_reset (sys_reset)
);
nf_10g_interface_shared_ip nf_10g_interface_0
(
.core_clk (clk_200 ),
.refclk_n (xphy_refclk_n),
.refclk_p (xphy_refclk_p),
.rst (peripheral_reset ),
.core_resetn (axis_resetn),
.clk156_out (sfp_clk156 ),
.gtrxreset_out (sfp_gtrxreset ),
.gttxreset_out (sfp_gttxreset ),
.qplllock_out (sfp_qplllock ),
.qplloutclk_out (sfp_qplloutclk ),
.qplloutrefclk_out (sfp_qplloutrefclk ),
.txuserrdy_out (sfp_txuserrdy ),
.txusrclk_out (sfp_txusrclk ),
.txusrclk2_out (sfp_txusrclk2 ),
.areset_clk156_out (sfp_areset_clk156 ),
.reset_counter_done_out (sfp_reset_counter_done),
.resetdone (sfp0_resetdone ),
.tx_fault (sfp0_tx_fault ),
.tx_abs (sfp0_tx_abs ),
.tx_disable (sfp0_tx_disable ),
.m_axis_tdata (axis_i_0_tdata ),
.m_axis_tkeep (axis_i_0_tkeep ),
.m_axis_tuser (axis_i_0_tuser ),
.m_axis_tvalid (axis_i_0_tvalid ),
.m_axis_tready (axis_i_0_tready ),
.m_axis_tlast (axis_i_0_tlast ),
.s_axis_tdata (axis_o_0_tdata ),
.s_axis_tkeep (axis_o_0_tkeep ),
.s_axis_tuser (axis_o_0_tuser ),
.s_axis_tvalid (axis_o_0_tvalid ),
.s_axis_tready (axis_o_0_tready ),
.s_axis_tlast (axis_o_0_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M04_AXI_awaddr),
.S_AXI_AWVALID (M04_AXI_awvalid),
.S_AXI_WDATA (M04_AXI_wdata),
.S_AXI_WSTRB (M04_AXI_wstrb),
.S_AXI_WVALID (M04_AXI_wvalid),
.S_AXI_BREADY (M04_AXI_bready),
.S_AXI_ARADDR (M04_AXI_araddr),
.S_AXI_ARVALID (M04_AXI_arvalid),
.S_AXI_RREADY (M04_AXI_rready),
.S_AXI_ARREADY (M04_AXI_arready),
.S_AXI_RDATA (M04_AXI_rdata),
.S_AXI_RRESP (M04_AXI_rresp),
.S_AXI_RVALID (M04_AXI_rvalid),
.S_AXI_WREADY (M04_AXI_wready),
.S_AXI_BRESP (M04_AXI_bresp),
.S_AXI_BVALID (M04_AXI_bvalid),
.S_AXI_AWREADY (M04_AXI_awready),
.rxn (sfp0_rx_n ),
.rxp (sfp0_rx_p ),
.txn (sfp0_tx_n ),
.txp (sfp0_tx_p ),
.interface_number (IF_SFP0 )
);
assign sfp0_tx_led = sfp0_resetdone ;
assign sfp0_rx_led = sfp0_resetdone ;
nf_10g_interface_ip nf_10g_interface_1
(
.core_clk (clk_200),
.core_resetn (axis_resetn),
.clk156 (sfp_clk156 ),
.qplllock (sfp_qplllock ),
.qplloutclk (sfp_qplloutclk ),
.qplloutrefclk (sfp_qplloutrefclk ),
.txuserrdy (sfp_txuserrdy ),
.txusrclk (sfp_txusrclk ),
.txusrclk2 (sfp_txusrclk2 ),
.areset_clk156 (sfp_areset_clk156 ),
.reset_counter_done (sfp_reset_counter_done),
.tx_abs (sfp1_tx_abs ),
.tx_disable (sfp1_tx_disable ),
.tx_fault (sfp1_tx_fault ),
.tx_resetdone (sfp1_tx_resetdone ),
.rx_resetdone (sfp1_rx_resetdone ),
.gtrxreset (sfp_gtrxreset ),
.gttxreset (sfp_gttxreset ),
.m_axis_tdata (axis_i_1_tdata ),
.m_axis_tkeep (axis_i_1_tkeep ),
.m_axis_tuser (axis_i_1_tuser ),
.m_axis_tvalid (axis_i_1_tvalid),
.m_axis_tready (axis_i_1_tready),
.m_axis_tlast (axis_i_1_tlast ),
.s_axis_tdata (axis_o_1_tdata ),
.s_axis_tkeep (axis_o_1_tkeep ),
.s_axis_tuser (axis_o_1_tuser ),
.s_axis_tvalid (axis_o_1_tvalid),
.s_axis_tready (axis_o_1_tready),
.s_axis_tlast (axis_o_1_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M05_AXI_awaddr),
.S_AXI_AWVALID (M05_AXI_awvalid),
.S_AXI_WDATA (M05_AXI_wdata),
.S_AXI_WSTRB (M05_AXI_wstrb),
.S_AXI_WVALID (M05_AXI_wvalid),
.S_AXI_BREADY (M05_AXI_bready),
.S_AXI_ARADDR (M05_AXI_araddr),
.S_AXI_ARVALID (M05_AXI_arvalid),
.S_AXI_RREADY (M05_AXI_rready),
.S_AXI_ARREADY (M05_AXI_arready),
.S_AXI_RDATA (M05_AXI_rdata),
.S_AXI_RRESP (M05_AXI_rresp),
.S_AXI_RVALID (M05_AXI_rvalid),
.S_AXI_WREADY (M05_AXI_wready),
.S_AXI_BRESP (M05_AXI_bresp),
.S_AXI_BVALID (M05_AXI_bvalid),
.S_AXI_AWREADY (M05_AXI_awready),
.txp (sfp1_tx_p),
.txn (sfp1_tx_n),
.rxp (sfp1_rx_p),
.rxn (sfp1_rx_n),
.interface_number (IF_SFP1)
);
assign sfp1_tx_led = sfp1_tx_resetdone ;
assign sfp1_rx_led = sfp1_rx_resetdone ;
nf_10g_interface_ip nf_10g_interface_2
(
.core_clk (clk_200),
.core_resetn (axis_resetn),
.clk156 (sfp_clk156 ),
.qplllock (sfp_qplllock ),
.qplloutclk (sfp_qplloutclk ),
.qplloutrefclk (sfp_qplloutrefclk ),
.txuserrdy (sfp_txuserrdy ),
.txusrclk (sfp_txusrclk ),
.txusrclk2 (sfp_txusrclk2 ),
.areset_clk156 (sfp_areset_clk156 ),
.reset_counter_done (sfp_reset_counter_done),
.gtrxreset (sfp_gtrxreset ),
.gttxreset (sfp_gttxreset ),
.tx_abs (sfp2_tx_abs ),
.tx_disable (sfp2_tx_disable ),
.tx_fault (sfp2_tx_fault ),
.tx_resetdone (sfp2_tx_resetdone ),
.rx_resetdone (sfp2_rx_resetdone ),
.m_axis_tdata (axis_i_2_tdata ),
.m_axis_tkeep (axis_i_2_tkeep ),
.m_axis_tuser (axis_i_2_tuser ),
.m_axis_tvalid (axis_i_2_tvalid),
.m_axis_tready (axis_i_2_tready),
.m_axis_tlast (axis_i_2_tlast ),
.s_axis_tdata (axis_o_2_tdata ),
.s_axis_tkeep (axis_o_2_tkeep ),
.s_axis_tuser (axis_o_2_tuser ),
.s_axis_tvalid (axis_o_2_tvalid),
.s_axis_tready (axis_o_2_tready),
.s_axis_tlast (axis_o_2_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M06_AXI_awaddr),
.S_AXI_AWVALID (M06_AXI_awvalid),
.S_AXI_WDATA (M06_AXI_wdata),
.S_AXI_WSTRB (M06_AXI_wstrb),
.S_AXI_WVALID (M06_AXI_wvalid),
.S_AXI_BREADY (M06_AXI_bready),
.S_AXI_ARADDR (M06_AXI_araddr),
.S_AXI_ARVALID (M06_AXI_arvalid),
.S_AXI_RREADY (M06_AXI_rready),
.S_AXI_ARREADY (M06_AXI_arready),
.S_AXI_RDATA (M06_AXI_rdata),
.S_AXI_RRESP (M06_AXI_rresp),
.S_AXI_RVALID (M06_AXI_rvalid),
.S_AXI_WREADY (M06_AXI_wready),
.S_AXI_BRESP (M06_AXI_bresp),
.S_AXI_BVALID (M06_AXI_bvalid),
.S_AXI_AWREADY (M06_AXI_awready),
.txp (sfp2_tx_p),
.txn (sfp2_tx_n),
.rxp (sfp2_rx_p),
.rxn (sfp2_rx_n),
.interface_number (IF_SFP2)
);
assign sfp2_tx_led = sfp2_tx_resetdone ;
assign sfp2_rx_led = sfp2_rx_resetdone ;
nf_10g_interface_ip nf_10g_interface_3
(
.core_clk (clk_200),
.core_resetn (axis_resetn),
.clk156 (sfp_clk156 ),
.qplllock (sfp_qplllock ),
.qplloutclk (sfp_qplloutclk ),
.qplloutrefclk (sfp_qplloutrefclk ),
.txuserrdy (sfp_txuserrdy ),
.txusrclk (sfp_txusrclk ),
.txusrclk2 (sfp_txusrclk2 ),
.areset_clk156 (sfp_areset_clk156 ),
.reset_counter_done (sfp_reset_counter_done),
.gtrxreset (sfp_gtrxreset ),
.gttxreset (sfp_gttxreset ),
.tx_abs (sfp3_tx_abs ),
.tx_disable (sfp3_tx_disable ),
.tx_fault (sfp3_tx_fault ),
.tx_resetdone (sfp3_tx_resetdone ),
.rx_resetdone (sfp3_rx_resetdone ),
.m_axis_tdata (axis_i_3_tdata ),
.m_axis_tkeep (axis_i_3_tkeep ),
.m_axis_tuser (axis_i_3_tuser ),
.m_axis_tvalid (axis_i_3_tvalid),
.m_axis_tready (axis_i_3_tready),
.m_axis_tlast (axis_i_3_tlast ),
.s_axis_tdata (axis_o_3_tdata ),
.s_axis_tkeep (axis_o_3_tkeep ),
.s_axis_tuser (axis_o_3_tuser ),
.s_axis_tvalid (axis_o_3_tvalid),
.s_axis_tready (axis_o_3_tready),
.s_axis_tlast (axis_o_3_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M07_AXI_awaddr),
.S_AXI_AWVALID (M07_AXI_awvalid),
.S_AXI_WDATA (M07_AXI_wdata),
.S_AXI_WSTRB (M07_AXI_wstrb),
.S_AXI_WVALID (M07_AXI_wvalid),
.S_AXI_BREADY (M07_AXI_bready),
.S_AXI_ARADDR (M07_AXI_araddr),
.S_AXI_ARVALID (M07_AXI_arvalid),
.S_AXI_RREADY (M07_AXI_rready),
.S_AXI_ARREADY (M07_AXI_arready),
.S_AXI_RDATA (M07_AXI_rdata),
.S_AXI_RRESP (M07_AXI_rresp),
.S_AXI_RVALID (M07_AXI_rvalid),
.S_AXI_WREADY (M07_AXI_wready),
.S_AXI_BRESP (M07_AXI_bresp),
.S_AXI_BVALID (M07_AXI_bvalid),
.S_AXI_AWREADY (M07_AXI_awready),
.txp (sfp3_tx_p),
.txn (sfp3_tx_n),
.rxp (sfp3_rx_p),
.rxn (sfp3_rx_n),
.interface_number (IF_SFP3)
);
assign sfp3_tx_led = sfp3_tx_resetdone ;
assign sfp3_rx_led = sfp3_rx_resetdone ;
identifier_ip identifier (
.s_aclk (clk_200),
.s_aresetn (axi_datapath_resetn),
.s_axi_awaddr (M00_AXI_awaddr),
.s_axi_awvalid(M00_AXI_awvalid),
.s_axi_awready(M00_AXI_awready),
.s_axi_wdata (M00_AXI_wdata),
.s_axi_wstrb (M00_AXI_wstrb),
.s_axi_wvalid (M00_AXI_wvalid),
.s_axi_wready (M00_AXI_wready),
.s_axi_bresp (M00_AXI_bresp),
.s_axi_bvalid (M00_AXI_bvalid),
.s_axi_bready (M00_AXI_bready),
.s_axi_araddr (M00_AXI_araddr ),
.s_axi_arvalid(M00_AXI_arvalid),
.s_axi_arready(M00_AXI_arready),
.s_axi_rdata (M00_AXI_rdata),
.s_axi_rresp (M00_AXI_rresp),
.s_axi_rvalid (M00_AXI_rvalid),
.s_axi_rready (M00_AXI_rready)
);
always @ (posedge axi_clk) begin
sfp_clk100_count <= sfp_clk100_count + 1'b1;
if (!sfp_clk100_count) begin
led[1] <= ~led[1];
end
end
always @ (posedge sfp_clk156) begin
sfp_clk156_count <= sfp_clk156_count + 1'b1;
if (!sfp_clk156_count) begin
led[0] <= ~led[0];
end
end
endmodule | module top # (
parameter C_DATA_WIDTH = 256,
parameter C_TUSER_WIDTH = 128
) (
input [7:0]pcie_7x_mgt_rxn,
input [7:0]pcie_7x_mgt_rxp,
output [7:0]pcie_7x_mgt_txn,
output [7:0]pcie_7x_mgt_txp,
input sfp0_rx_p,
input sfp0_rx_n,
output sfp0_tx_p,
output sfp0_tx_n,
input sfp0_tx_fault,
input sfp0_tx_abs,
output sfp0_tx_disable,
input sfp1_rx_p,
input sfp1_rx_n,
output sfp1_tx_p,
output sfp1_tx_n,
input sfp1_tx_fault,
input sfp1_tx_abs,
output sfp1_tx_disable,
input sfp2_rx_p,
input sfp2_rx_n,
output sfp2_tx_p,
output sfp2_tx_n,
input sfp2_tx_fault,
input sfp2_tx_abs,
output sfp2_tx_disable,
input sfp3_rx_p,
input sfp3_rx_n,
output sfp3_tx_p,
output sfp3_tx_n,
input sfp3_tx_fault,
input sfp3_tx_abs,
output sfp3_tx_disable,
input sys_clkp,
input sys_clkn,
input fpga_sysclk_p,
input fpga_sysclk_n,
input xphy_refclk_p,
input xphy_refclk_n,
output [1:0] leds,
output sfp0_tx_led,
output sfp1_tx_led,
output sfp2_tx_led,
output sfp3_tx_led,
output sfp0_rx_led,
output sfp1_rx_led,
output sfp2_rx_led,
output sfp3_rx_led,
inout i2c_clk,
inout i2c_data,
output [1:0] i2c_reset,
input uart_rxd,
output uart_txd,
input sys_reset_n
); |
wire sys_clk;
wire clk_200;
wire sys_rst_n_c;
wire clk_200_locked;
wire[C_DATA_WIDTH-1:0] axis_i_0_tdata;
wire axis_i_0_tvalid;
wire axis_i_0_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_0_tuser;
wire[(C_DATA_WIDTH/8)-1:0] axis_i_0_tkeep;
wire axis_i_0_tready;
wire[C_DATA_WIDTH-1:0] axis_o_0_tdata;
wire axis_o_0_tvalid;
wire axis_o_0_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_0_tuser;
wire[(C_DATA_WIDTH/8)-1:0] axis_o_0_tkeep;
wire axis_o_0_tready;
wire[C_DATA_WIDTH-1:0] axis_i_1_tdata;
wire axis_i_1_tvalid;
wire axis_i_1_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_1_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_i_1_tkeep;
wire axis_i_1_tready;
wire[C_DATA_WIDTH-1:0] axis_o_1_tdata;
wire axis_o_1_tvalid;
wire axis_o_1_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_1_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_o_1_tkeep;
wire axis_o_1_tready;
wire[C_DATA_WIDTH-1:0] axis_i_2_tdata;
wire axis_i_2_tvalid;
wire axis_i_2_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_2_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_i_2_tkeep;
wire axis_i_2_tready;
wire[C_DATA_WIDTH-1:0] axis_o_2_tdata;
wire axis_o_2_tvalid;
wire axis_o_2_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_2_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_o_2_tkeep;
wire axis_o_2_tready;
wire[C_DATA_WIDTH-1:0] axis_i_3_tdata;
wire axis_i_3_tvalid;
wire axis_i_3_tlast;
wire[C_TUSER_WIDTH-1:0] axis_i_3_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_i_3_tkeep;
wire axis_i_3_tready;
wire[C_DATA_WIDTH-1:0] axis_o_3_tdata;
wire axis_o_3_tvalid;
wire axis_o_3_tlast;
wire [C_TUSER_WIDTH-1:0] axis_o_3_tuser;
wire[C_DATA_WIDTH/8-1:0] axis_o_3_tkeep;
wire axis_o_3_tready;
wire [255:0] axis_dma_i_tdata ;
wire [31:0] axis_dma_i_tkeep ;
wire axis_dma_i_tlast ;
wire axis_dma_i_tready;
wire [255:0] axis_dma_i_tuser ;
wire axis_dma_i_tvalid;
wire [255:0] axis_dma_o_tdata;
wire [31:0] axis_dma_o_tkeep;
wire axis_dma_o_tlast;
wire axis_dma_o_tready;
wire [127:0] axis_dma_o_tuser;
wire axis_dma_o_tvalid;
wire [11:0] M00_AXI_araddr;
wire [2:0] M00_AXI_arprot;
wire [0:0] M00_AXI_arready;
wire [0:0] M00_AXI_arvalid;
wire [11:0] M00_AXI_awaddr;
wire [2:0] M00_AXI_awprot;
wire [0:0] M00_AXI_awready;
wire [0:0] M00_AXI_awvalid;
wire [0:0] M00_AXI_bready;
wire [1:0] M00_AXI_bresp;
wire [0:0] M00_AXI_bvalid;
wire [31:0] M00_AXI_rdata;
wire [0:0] M00_AXI_rready;
wire [1:0] M00_AXI_rresp;
wire [0:0] M00_AXI_rvalid;
wire [31:0] M00_AXI_wdata;
wire [0:0] M00_AXI_wready;
wire [3:0] M00_AXI_wstrb;
wire [0:0] M00_AXI_wvalid;
wire [11:0] M01_AXI_araddr;
wire [2:0] M01_AXI_arprot;
wire [0:0] M01_AXI_arready;
wire [0:0] M01_AXI_arvalid;
wire [11:0] M01_AXI_awaddr;
wire [2:0] M01_AXI_awprot;
wire [0:0] M01_AXI_awready;
wire [0:0] M01_AXI_awvalid;
wire [0:0] M01_AXI_bready;
wire [1:0] M01_AXI_bresp;
wire [0:0] M01_AXI_bvalid;
wire [31:0] M01_AXI_rdata;
wire [0:0] M01_AXI_rready;
wire [1:0] M01_AXI_rresp;
wire [0:0] M01_AXI_rvalid;
wire [31:0] M01_AXI_wdata;
wire [0:0] M01_AXI_wready;
wire [3:0] M01_AXI_wstrb;
wire [0:0] M01_AXI_wvalid;
wire [11:0] M02_AXI_araddr;
wire [2:0] M02_AXI_arprot;
wire [0:0] M02_AXI_arready;
wire [0:0] M02_AXI_arvalid;
wire [11:0] M02_AXI_awaddr;
wire [2:0] M02_AXI_awprot;
wire [0:0] M02_AXI_awready;
wire [0:0] M02_AXI_awvalid;
wire [0:0] M02_AXI_bready;
wire [1:0] M02_AXI_bresp;
wire [0:0] M02_AXI_bvalid;
wire [31:0] M02_AXI_rdata;
wire [0:0] M02_AXI_rready;
wire [1:0] M02_AXI_rresp;
wire [0:0] M02_AXI_rvalid;
wire [31:0] M02_AXI_wdata;
wire [0:0] M02_AXI_wready;
wire [3:0] M02_AXI_wstrb;
wire [0:0] M02_AXI_wvalid;
wire [11:0] M03_AXI_araddr;
wire [2:0] M03_AXI_arprot;
wire [0:0] M03_AXI_arready;
wire [0:0] M03_AXI_arvalid;
wire [11:0] M03_AXI_awaddr;
wire [2:0] M03_AXI_awprot;
wire [0:0] M03_AXI_awready;
wire [0:0] M03_AXI_awvalid;
wire [0:0] M03_AXI_bready;
wire [1:0] M03_AXI_bresp;
wire [0:0] M03_AXI_bvalid;
wire [31:0] M03_AXI_rdata;
wire [0:0] M03_AXI_rready;
wire [1:0] M03_AXI_rresp;
wire [0:0] M03_AXI_rvalid;
wire [31:0] M03_AXI_wdata;
wire [0:0] M03_AXI_wready;
wire [3:0] M03_AXI_wstrb;
wire [0:0] M03_AXI_wvalid;
wire [11:0] M04_AXI_araddr;
wire [2:0] M04_AXI_arprot;
wire [0:0] M04_AXI_arready;
wire [0:0] M04_AXI_arvalid;
wire [11:0] M04_AXI_awaddr;
wire [2:0] M04_AXI_awprot;
wire [0:0] M04_AXI_awready;
wire [0:0] M04_AXI_awvalid;
wire [0:0] M04_AXI_bready;
wire [1:0] M04_AXI_bresp;
wire [0:0] M04_AXI_bvalid;
wire [31:0] M04_AXI_rdata;
wire [0:0] M04_AXI_rready;
wire [1:0] M04_AXI_rresp;
wire [0:0] M04_AXI_rvalid;
wire [31:0] M04_AXI_wdata;
wire [0:0] M04_AXI_wready;
wire [3:0] M04_AXI_wstrb;
wire [0:0] M04_AXI_wvalid;
wire [11:0] M05_AXI_araddr;
wire [2:0] M05_AXI_arprot;
wire [0:0] M05_AXI_arready;
wire [0:0] M05_AXI_arvalid;
wire [11:0] M05_AXI_awaddr;
wire [2:0] M05_AXI_awprot;
wire [0:0] M05_AXI_awready;
wire [0:0] M05_AXI_awvalid;
wire [0:0] M05_AXI_bready;
wire [1:0] M05_AXI_bresp;
wire [0:0] M05_AXI_bvalid;
wire [31:0] M05_AXI_rdata;
wire [0:0] M05_AXI_rready;
wire [1:0] M05_AXI_rresp;
wire [0:0] M05_AXI_rvalid;
wire [31:0] M05_AXI_wdata;
wire [0:0] M05_AXI_wready;
wire [3:0] M05_AXI_wstrb;
wire [0:0] M05_AXI_wvalid;
wire [11:0] M06_AXI_araddr;
wire [2:0] M06_AXI_arprot;
wire [0:0] M06_AXI_arready;
wire [0:0] M06_AXI_arvalid;
wire [11:0] M06_AXI_awaddr;
wire [2:0] M06_AXI_awprot;
wire [0:0] M06_AXI_awready;
wire [0:0] M06_AXI_awvalid;
wire [0:0] M06_AXI_bready;
wire [1:0] M06_AXI_bresp;
wire [0:0] M06_AXI_bvalid;
wire [31:0] M06_AXI_rdata;
wire [0:0] M06_AXI_rready;
wire [1:0] M06_AXI_rresp;
wire [0:0] M06_AXI_rvalid;
wire [31:0] M06_AXI_wdata;
wire [0:0] M06_AXI_wready;
wire [3:0] M06_AXI_wstrb;
wire [0:0] M06_AXI_wvalid;
wire [11:0] M07_AXI_araddr;
wire [2:0] M07_AXI_arprot;
wire [0:0] M07_AXI_arready;
wire [0:0] M07_AXI_arvalid;
wire [11:0] M07_AXI_awaddr;
wire [2:0] M07_AXI_awprot;
wire [0:0] M07_AXI_awready;
wire [0:0] M07_AXI_awvalid;
wire [0:0] M07_AXI_bready;
wire [1:0] M07_AXI_bresp;
wire [0:0] M07_AXI_bvalid;
wire [31:0] M07_AXI_rdata;
wire [0:0] M07_AXI_rready;
wire [1:0] M07_AXI_rresp;
wire [0:0] M07_AXI_rvalid;
wire [31:0] M07_AXI_wdata;
wire [0:0] M07_AXI_wready;
wire [3:0] M07_AXI_wstrb;
wire [0:0] M07_AXI_wvalid;
wire sfp_qplllock ;
wire sfp_qplloutrefclk;
wire sfp_qplloutclk ;
wire sfp_clk156;
wire sfp_areset_clk156;
wire sfp_gttxreset;
wire sfp_gtrxreset;
wire sfp_txuserrdy;
wire sfp_txusrclk;
wire sfp_txusrclk2;
wire sfp_reset_counter_done;
wire sfp_tx_axis_areset;
wire sfp_tx_axis_aresetn;
wire sfp_rx_axis_aresetn;
wire port0_ready;
wire block0_lock;
wire sfp0_resetdone;
wire sfp0_txclk322;
wire port1_ready;
wire block1_lock;
wire sfp1_tx_resetdone;
wire sfp1_rx_resetdone;
wire sfp1_txclk322;
wire port2_ready;
wire block2_lock;
wire sfp2_tx_resetdone;
wire sfp2_rx_resetdone;
wire sfp2_txclk322;
wire port3_ready;
wire block3_lock;
wire sfp3_tx_resetdone;
wire sfp3_rx_resetdone;
wire sfp3_txclk322;
wire i2c_scl_o;
wire i2c_scl_i;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_i;
wire i2c_sda_t;
wire axi_clk;
wire axi_aresetn;
wire sys_reset;
(* ASYNC_REG = "TRUE" *) reg [3:0] core200_reset_sync_n;
wire axis_resetn;
wire axi_datapath_resetn;
wire peripheral_reset;
localparam IF_SFP0 = 8'b00000001;
localparam IF_SFP1 = 8'b00000100;
localparam IF_SFP2 = 8'b00010000;
localparam IF_SFP3 = 8'b01000000;
reg [27:0] sfp_clk156_count;
reg [27:0] sfp_clk100_count;
reg [1:0] led;
OBUF led_0_obuf (
.O (leds[0]),
.I (led[0])
);
OBUF led_1_obuf (
.O (leds[1]),
.I (led[1])
);
IBUF sys_reset_n_ibuf(
.O (sys_rst_n_c),
.I (sys_reset_n)
);
IBUFDS_GTE2 #(
.CLKCM_CFG ("TRUE"),
.CLKRCV_TRST ("TRUE"),
.CLKSWING_CFG (2'b11)
) IBUFDS_GTE2_inst (
.O (sys_clk),
.ODIV2 (),
.CEB (1'b0),
.I (sys_clkp),
.IB (sys_clkn)
);
IOBUF i2c_scl_iobuf (
.I (i2c_scl_o),
.IO (i2c_clk),
.O (i2c_scl_i),
.T (i2c_scl_t)
);
IOBUF i2c_sda_iobuf (
.I (i2c_sda_o),
.IO (i2c_data),
.O (i2c_sda_i),
.T (i2c_sda_t)
);
axi_clocking axi_clocking_i (
.clk_in_p (fpga_sysclk_p),
.clk_in_n (fpga_sysclk_n),
.clk_200 (clk_200),
.locked (clk_200_locked),
.resetn (sys_rst_n_c)
);
BUFG axi_lite_bufg0 (
.I (sys_clk),
.O (axi_clk)
);
proc_sys_reset_ip proc_sys_reset_i (
.slowest_sync_clk(clk_200),
.ext_reset_in(sys_rst_n_c),
.aux_reset_in(1'b1),
.mb_debug_sys_rst(1'b0),
.dcm_locked(clk_200_locked),
.mb_reset(),
.bus_struct_reset(),
.peripheral_reset(peripheral_reset),
.interconnect_aresetn(),
.peripheral_aresetn(axis_resetn)
);
assign sys_reset = !sys_rst_n_c;
always @ (posedge clk_200) begin
if (!sys_rst_n_c)
core200_reset_sync_n <= 4'h0;
else
core200_reset_sync_n <= #1 {core200_reset_sync_n[2:0],sys_rst_n_c};
end
assign axi_aresetn = axis_resetn;
assign axi_datapath_resetn = axis_resetn;
nf_datapath
#(
.C_M_AXIS_DATA_WIDTH (C_DATA_WIDTH),
.C_S_AXIS_DATA_WIDTH (C_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH (12),
.C_M_AXIS_TUSER_WIDTH (128),
.C_S_AXIS_TUSER_WIDTH (128),
.NUM_QUEUES (5)
)
nf_datapath_0
(
.axis_aclk (clk_200),
.axis_resetn (axis_resetn),
.axi_aclk (clk_200),
.axi_resetn (axi_datapath_resetn),
.s_axis_0_tdata (axis_i_0_tdata),
.s_axis_0_tkeep (axis_i_0_tkeep),
.s_axis_0_tuser (axis_i_0_tuser),
.s_axis_0_tvalid (axis_i_0_tvalid),
.s_axis_0_tready (axis_i_0_tready),
.s_axis_0_tlast (axis_i_0_tlast),
.s_axis_1_tdata (axis_i_1_tdata),
.s_axis_1_tkeep (axis_i_1_tkeep),
.s_axis_1_tuser (axis_i_1_tuser),
.s_axis_1_tvalid (axis_i_1_tvalid),
.s_axis_1_tready (axis_i_1_tready),
.s_axis_1_tlast (axis_i_1_tlast),
.s_axis_2_tdata (axis_i_2_tdata),
.s_axis_2_tkeep (axis_i_2_tkeep),
.s_axis_2_tuser (axis_i_2_tuser),
.s_axis_2_tvalid (axis_i_2_tvalid),
.s_axis_2_tready (axis_i_2_tready),
.s_axis_2_tlast (axis_i_2_tlast),
.s_axis_3_tdata (axis_i_3_tdata),
.s_axis_3_tkeep (axis_i_3_tkeep),
.s_axis_3_tuser (axis_i_3_tuser),
.s_axis_3_tvalid (axis_i_3_tvalid),
.s_axis_3_tready (axis_i_3_tready),
.s_axis_3_tlast (axis_i_3_tlast),
.s_axis_4_tdata (axis_dma_i_tdata ),
.s_axis_4_tkeep (axis_dma_i_tkeep ),
.s_axis_4_tuser (axis_dma_i_tuser[127:0] ),
.s_axis_4_tvalid (axis_dma_i_tvalid),
.s_axis_4_tready (axis_dma_i_tready ),
.s_axis_4_tlast (axis_dma_i_tlast),
.m_axis_0_tdata (axis_o_0_tdata),
.m_axis_0_tkeep (axis_o_0_tkeep),
.m_axis_0_tuser (axis_o_0_tuser),
.m_axis_0_tvalid (axis_o_0_tvalid),
.m_axis_0_tready (axis_o_0_tready),
.m_axis_0_tlast (axis_o_0_tlast),
.m_axis_1_tdata (axis_o_1_tdata),
.m_axis_1_tkeep (axis_o_1_tkeep),
.m_axis_1_tuser (axis_o_1_tuser),
.m_axis_1_tvalid (axis_o_1_tvalid),
.m_axis_1_tready (axis_o_1_tready),
.m_axis_1_tlast (axis_o_1_tlast),
.m_axis_2_tdata (axis_o_2_tdata),
.m_axis_2_tkeep (axis_o_2_tkeep),
.m_axis_2_tuser (axis_o_2_tuser),
.m_axis_2_tvalid (axis_o_2_tvalid),
.m_axis_2_tready (axis_o_2_tready),
.m_axis_2_tlast (axis_o_2_tlast),
.m_axis_3_tdata (axis_o_3_tdata ),
.m_axis_3_tkeep (axis_o_3_tkeep ),
.m_axis_3_tuser (axis_o_3_tuser ),
.m_axis_3_tvalid (axis_o_3_tvalid),
.m_axis_3_tready (axis_o_3_tready),
.m_axis_3_tlast (axis_o_3_tlast ),
.m_axis_4_tdata (axis_dma_o_tdata ),
.m_axis_4_tkeep (axis_dma_o_tkeep ),
.m_axis_4_tuser (axis_dma_o_tuser ),
.m_axis_4_tvalid (axis_dma_o_tvalid),
.m_axis_4_tready (axis_dma_o_tready ),
.m_axis_4_tlast (axis_dma_o_tlast),
.S0_AXI_AWADDR (M01_AXI_awaddr),
.S0_AXI_AWVALID (M01_AXI_awvalid),
.S0_AXI_WDATA (M01_AXI_wdata),
.S0_AXI_WSTRB (M01_AXI_wstrb),
.S0_AXI_WVALID (M01_AXI_wvalid),
.S0_AXI_BREADY (M01_AXI_bready),
.S0_AXI_ARADDR (M01_AXI_araddr),
.S0_AXI_ARVALID (M01_AXI_arvalid),
.S0_AXI_RREADY (M01_AXI_rready),
.S0_AXI_ARREADY (M01_AXI_arready),
.S0_AXI_RDATA (M01_AXI_rdata),
.S0_AXI_RRESP (M01_AXI_rresp),
.S0_AXI_RVALID (M01_AXI_rvalid),
.S0_AXI_WREADY (M01_AXI_wready),
.S0_AXI_BRESP (M01_AXI_bresp),
.S0_AXI_BVALID (M01_AXI_bvalid),
.S0_AXI_AWREADY (M01_AXI_awready),
.S1_AXI_AWADDR (M02_AXI_awaddr),
.S1_AXI_AWVALID (M02_AXI_awvalid),
.S1_AXI_WDATA (M02_AXI_wdata),
.S1_AXI_WSTRB (M02_AXI_wstrb),
.S1_AXI_WVALID (M02_AXI_wvalid),
.S1_AXI_BREADY (M02_AXI_bready),
.S1_AXI_ARADDR (M02_AXI_araddr),
.S1_AXI_ARVALID (M02_AXI_arvalid),
.S1_AXI_RREADY (M02_AXI_rready),
.S1_AXI_ARREADY (M02_AXI_arready),
.S1_AXI_RDATA (M02_AXI_rdata),
.S1_AXI_RRESP (M02_AXI_rresp),
.S1_AXI_RVALID (M02_AXI_rvalid),
.S1_AXI_WREADY (M02_AXI_wready),
.S1_AXI_BRESP (M02_AXI_bresp),
.S1_AXI_BVALID (M02_AXI_bvalid),
.S1_AXI_AWREADY (M02_AXI_awready),
.S2_AXI_AWADDR (M03_AXI_awaddr),
.S2_AXI_AWVALID (M03_AXI_awvalid),
.S2_AXI_WDATA (M03_AXI_wdata),
.S2_AXI_WSTRB (M03_AXI_wstrb),
.S2_AXI_WVALID (M03_AXI_wvalid),
.S2_AXI_BREADY (M03_AXI_bready),
.S2_AXI_ARADDR (M03_AXI_araddr),
.S2_AXI_ARVALID (M03_AXI_arvalid),
.S2_AXI_RREADY (M03_AXI_rready),
.S2_AXI_ARREADY (M03_AXI_arready),
.S2_AXI_RDATA (M03_AXI_rdata),
.S2_AXI_RRESP (M03_AXI_rresp),
.S2_AXI_RVALID (M03_AXI_rvalid),
.S2_AXI_WREADY (M03_AXI_wready),
.S2_AXI_BRESP (M03_AXI_bresp),
.S2_AXI_BVALID (M03_AXI_bvalid),
.S2_AXI_AWREADY (M03_AXI_awready)
);
control_sub control_sub_i
(
.M00_AXI_araddr (M00_AXI_araddr ),
.M00_AXI_arprot (M00_AXI_arprot ),
.M00_AXI_arready (M00_AXI_arready ),
.M00_AXI_arvalid (M00_AXI_arvalid ),
.M00_AXI_awaddr (M00_AXI_awaddr ),
.M00_AXI_awprot (M00_AXI_awprot ),
.M00_AXI_awready (M00_AXI_awready ),
.M00_AXI_awvalid (M00_AXI_awvalid ),
.M00_AXI_bready (M00_AXI_bready ),
.M00_AXI_bresp (M00_AXI_bresp ),
.M00_AXI_bvalid (M00_AXI_bvalid ),
.M00_AXI_rdata (M00_AXI_rdata ),
.M00_AXI_rready (M00_AXI_rready ),
.M00_AXI_rresp (M00_AXI_rresp ),
.M00_AXI_rvalid (M00_AXI_rvalid ),
.M00_AXI_wdata (M00_AXI_wdata ),
.M00_AXI_wready (M00_AXI_wready ),
.M00_AXI_wstrb (M00_AXI_wstrb ),
.M00_AXI_wvalid (M00_AXI_wvalid ),
.M01_AXI_araddr (M01_AXI_araddr ),
.M01_AXI_arprot (M01_AXI_arprot ),
.M01_AXI_arready (M01_AXI_arready ),
.M01_AXI_arvalid (M01_AXI_arvalid ),
.M01_AXI_awaddr (M01_AXI_awaddr ),
.M01_AXI_awprot (M01_AXI_awprot ),
.M01_AXI_awready (M01_AXI_awready ),
.M01_AXI_awvalid (M01_AXI_awvalid ),
.M01_AXI_bready (M01_AXI_bready ),
.M01_AXI_bresp (M01_AXI_bresp ),
.M01_AXI_bvalid (M01_AXI_bvalid ),
.M01_AXI_rdata (M01_AXI_rdata ),
.M01_AXI_rready (M01_AXI_rready ),
.M01_AXI_rresp (M01_AXI_rresp ),
.M01_AXI_rvalid (M01_AXI_rvalid ),
.M01_AXI_wdata (M01_AXI_wdata ),
.M01_AXI_wready (M01_AXI_wready ),
.M01_AXI_wstrb (M01_AXI_wstrb ),
.M01_AXI_wvalid (M01_AXI_wvalid ),
.M02_AXI_araddr (M02_AXI_araddr ),
.M02_AXI_arprot (M02_AXI_arprot ),
.M02_AXI_arready (M02_AXI_arready ),
.M02_AXI_arvalid (M02_AXI_arvalid ),
.M02_AXI_awaddr (M02_AXI_awaddr ),
.M02_AXI_awprot (M02_AXI_awprot ),
.M02_AXI_awready (M02_AXI_awready ),
.M02_AXI_awvalid (M02_AXI_awvalid ),
.M02_AXI_bready (M02_AXI_bready ),
.M02_AXI_bresp (M02_AXI_bresp ),
.M02_AXI_bvalid (M02_AXI_bvalid ),
.M02_AXI_rdata (M02_AXI_rdata ),
.M02_AXI_rready (M02_AXI_rready ),
.M02_AXI_rresp (M02_AXI_rresp ),
.M02_AXI_rvalid (M02_AXI_rvalid ),
.M02_AXI_wdata (M02_AXI_wdata ),
.M02_AXI_wready (M02_AXI_wready ),
.M02_AXI_wstrb (M02_AXI_wstrb ),
.M02_AXI_wvalid (M02_AXI_wvalid ),
.M03_AXI_araddr (M03_AXI_araddr ),
.M03_AXI_arprot (M03_AXI_arprot ),
.M03_AXI_arready (M03_AXI_arready),
.M03_AXI_arvalid (M03_AXI_arvalid),
.M03_AXI_awaddr (M03_AXI_awaddr ),
.M03_AXI_awprot (M03_AXI_awprot ),
.M03_AXI_awready (M03_AXI_awready),
.M03_AXI_awvalid (M03_AXI_awvalid),
.M03_AXI_bready (M03_AXI_bready ),
.M03_AXI_bresp (M03_AXI_bresp ),
.M03_AXI_bvalid (M03_AXI_bvalid ),
.M03_AXI_rdata (M03_AXI_rdata ),
.M03_AXI_rready (M03_AXI_rready ),
.M03_AXI_rresp (M03_AXI_rresp ),
.M03_AXI_rvalid (M03_AXI_rvalid ),
.M03_AXI_wdata (M03_AXI_wdata ),
.M03_AXI_wready (M03_AXI_wready ),
.M03_AXI_wstrb (M03_AXI_wstrb ),
.M03_AXI_wvalid (M03_AXI_wvalid ),
.M04_AXI_araddr (M04_AXI_araddr ),
.M04_AXI_arprot (M04_AXI_arprot ),
.M04_AXI_arready (M04_AXI_arready),
.M04_AXI_arvalid (M04_AXI_arvalid),
.M04_AXI_awaddr (M04_AXI_awaddr ),
.M04_AXI_awprot (M04_AXI_awprot ),
.M04_AXI_awready (M04_AXI_awready),
.M04_AXI_awvalid (M04_AXI_awvalid),
.M04_AXI_bready (M04_AXI_bready ),
.M04_AXI_bresp (M04_AXI_bresp ),
.M04_AXI_bvalid (M04_AXI_bvalid ),
.M04_AXI_rdata (M04_AXI_rdata ),
.M04_AXI_rready (M04_AXI_rready ),
.M04_AXI_rresp (M04_AXI_rresp ),
.M04_AXI_rvalid (M04_AXI_rvalid ),
.M04_AXI_wdata (M04_AXI_wdata ),
.M04_AXI_wready (M04_AXI_wready ),
.M04_AXI_wstrb (M04_AXI_wstrb ),
.M04_AXI_wvalid (M04_AXI_wvalid ),
.M05_AXI_araddr (M05_AXI_araddr ),
.M05_AXI_arprot (M05_AXI_arprot ),
.M05_AXI_arready (M05_AXI_arready),
.M05_AXI_arvalid (M05_AXI_arvalid),
.M05_AXI_awaddr (M05_AXI_awaddr ),
.M05_AXI_awprot (M05_AXI_awprot ),
.M05_AXI_awready (M05_AXI_awready),
.M05_AXI_awvalid (M05_AXI_awvalid),
.M05_AXI_bready (M05_AXI_bready ),
.M05_AXI_bresp (M05_AXI_bresp ),
.M05_AXI_bvalid (M05_AXI_bvalid ),
.M05_AXI_rdata (M05_AXI_rdata ),
.M05_AXI_rready (M05_AXI_rready ),
.M05_AXI_rresp (M05_AXI_rresp ),
.M05_AXI_rvalid (M05_AXI_rvalid ),
.M05_AXI_wdata (M05_AXI_wdata ),
.M05_AXI_wready (M05_AXI_wready ),
.M05_AXI_wstrb (M05_AXI_wstrb ),
.M05_AXI_wvalid (M05_AXI_wvalid ),
.M06_AXI_araddr (M06_AXI_araddr ),
.M06_AXI_arprot (M06_AXI_arprot ),
.M06_AXI_arready (M06_AXI_arready),
.M06_AXI_arvalid (M06_AXI_arvalid),
.M06_AXI_awaddr (M06_AXI_awaddr ),
.M06_AXI_awprot (M06_AXI_awprot ),
.M06_AXI_awready (M06_AXI_awready),
.M06_AXI_awvalid (M06_AXI_awvalid),
.M06_AXI_bready (M06_AXI_bready ),
.M06_AXI_bresp (M06_AXI_bresp ),
.M06_AXI_bvalid (M06_AXI_bvalid ),
.M06_AXI_rdata (M06_AXI_rdata ),
.M06_AXI_rready (M06_AXI_rready ),
.M06_AXI_rresp (M06_AXI_rresp ),
.M06_AXI_rvalid (M06_AXI_rvalid ),
.M06_AXI_wdata (M06_AXI_wdata ),
.M06_AXI_wready (M06_AXI_wready ),
.M06_AXI_wstrb (M06_AXI_wstrb ),
.M06_AXI_wvalid (M06_AXI_wvalid ),
.M07_AXI_araddr (M07_AXI_araddr ),
.M07_AXI_arprot (M07_AXI_arprot ),
.M07_AXI_arready (M07_AXI_arready),
.M07_AXI_arvalid (M07_AXI_arvalid),
.M07_AXI_awaddr (M07_AXI_awaddr ),
.M07_AXI_awprot (M07_AXI_awprot ),
.M07_AXI_awready (M07_AXI_awready),
.M07_AXI_awvalid (M07_AXI_awvalid),
.M07_AXI_bready (M07_AXI_bready ),
.M07_AXI_bresp (M07_AXI_bresp ),
.M07_AXI_bvalid (M07_AXI_bvalid ),
.M07_AXI_rdata (M07_AXI_rdata ),
.M07_AXI_rready (M07_AXI_rready ),
.M07_AXI_rresp (M07_AXI_rresp ),
.M07_AXI_rvalid (M07_AXI_rvalid ),
.M07_AXI_wdata (M07_AXI_wdata ),
.M07_AXI_wready (M07_AXI_wready ),
.M07_AXI_wstrb (M07_AXI_wstrb ),
.M07_AXI_wvalid (M07_AXI_wvalid ),
.iic_fpga_scl_i(i2c_scl_i),
.iic_fpga_scl_o(i2c_scl_o),
.iic_fpga_scl_t(i2c_scl_t),
.iic_fpga_sda_i(i2c_sda_i),
.iic_fpga_sda_o(i2c_sda_o),
.iic_fpga_sda_t(i2c_sda_t),
.iic_reset (i2c_reset),
.uart_txd (uart_txd),
.uart_rxd (uart_rxd),
.axi_lite_aclk (axi_clk),
.axi_lite_aresetn (axi_aresetn),
.axis_datapath_aclk (clk_200),
.axis_datapath_aresetn (axis_resetn),
.m_axis_dma_tx_tdata (axis_dma_i_tdata),
.m_axis_dma_tx_tkeep (axis_dma_i_tkeep),
.m_axis_dma_tx_tlast (axis_dma_i_tlast),
.m_axis_dma_tx_tready (axis_dma_i_tready),
.m_axis_dma_tx_tuser (axis_dma_i_tuser),
.m_axis_dma_tx_tvalid (axis_dma_i_tvalid),
.s_axis_dma_rx_tdata (axis_dma_o_tdata),
.s_axis_dma_rx_tkeep (axis_dma_o_tkeep),
.s_axis_dma_rx_tlast (axis_dma_o_tlast),
.s_axis_dma_rx_tready (axis_dma_o_tready),
.s_axis_dma_rx_tuser ({128'h0,axis_dma_o_tuser}),
.s_axis_dma_rx_tvalid (axis_dma_o_tvalid),
.pcie_7x_mgt_rxn (pcie_7x_mgt_rxn),
.pcie_7x_mgt_rxp (pcie_7x_mgt_rxp),
.pcie_7x_mgt_txn (pcie_7x_mgt_txn),
.pcie_7x_mgt_txp (pcie_7x_mgt_txp),
.sys_clk (sys_clk),
.sys_reset (sys_reset)
);
nf_10g_interface_shared_ip nf_10g_interface_0
(
.core_clk (clk_200 ),
.refclk_n (xphy_refclk_n),
.refclk_p (xphy_refclk_p),
.rst (peripheral_reset ),
.core_resetn (axis_resetn),
.clk156_out (sfp_clk156 ),
.gtrxreset_out (sfp_gtrxreset ),
.gttxreset_out (sfp_gttxreset ),
.qplllock_out (sfp_qplllock ),
.qplloutclk_out (sfp_qplloutclk ),
.qplloutrefclk_out (sfp_qplloutrefclk ),
.txuserrdy_out (sfp_txuserrdy ),
.txusrclk_out (sfp_txusrclk ),
.txusrclk2_out (sfp_txusrclk2 ),
.areset_clk156_out (sfp_areset_clk156 ),
.reset_counter_done_out (sfp_reset_counter_done),
.resetdone (sfp0_resetdone ),
.tx_fault (sfp0_tx_fault ),
.tx_abs (sfp0_tx_abs ),
.tx_disable (sfp0_tx_disable ),
.m_axis_tdata (axis_i_0_tdata ),
.m_axis_tkeep (axis_i_0_tkeep ),
.m_axis_tuser (axis_i_0_tuser ),
.m_axis_tvalid (axis_i_0_tvalid ),
.m_axis_tready (axis_i_0_tready ),
.m_axis_tlast (axis_i_0_tlast ),
.s_axis_tdata (axis_o_0_tdata ),
.s_axis_tkeep (axis_o_0_tkeep ),
.s_axis_tuser (axis_o_0_tuser ),
.s_axis_tvalid (axis_o_0_tvalid ),
.s_axis_tready (axis_o_0_tready ),
.s_axis_tlast (axis_o_0_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M04_AXI_awaddr),
.S_AXI_AWVALID (M04_AXI_awvalid),
.S_AXI_WDATA (M04_AXI_wdata),
.S_AXI_WSTRB (M04_AXI_wstrb),
.S_AXI_WVALID (M04_AXI_wvalid),
.S_AXI_BREADY (M04_AXI_bready),
.S_AXI_ARADDR (M04_AXI_araddr),
.S_AXI_ARVALID (M04_AXI_arvalid),
.S_AXI_RREADY (M04_AXI_rready),
.S_AXI_ARREADY (M04_AXI_arready),
.S_AXI_RDATA (M04_AXI_rdata),
.S_AXI_RRESP (M04_AXI_rresp),
.S_AXI_RVALID (M04_AXI_rvalid),
.S_AXI_WREADY (M04_AXI_wready),
.S_AXI_BRESP (M04_AXI_bresp),
.S_AXI_BVALID (M04_AXI_bvalid),
.S_AXI_AWREADY (M04_AXI_awready),
.rxn (sfp0_rx_n ),
.rxp (sfp0_rx_p ),
.txn (sfp0_tx_n ),
.txp (sfp0_tx_p ),
.interface_number (IF_SFP0 )
);
assign sfp0_tx_led = sfp0_resetdone ;
assign sfp0_rx_led = sfp0_resetdone ;
nf_10g_interface_ip nf_10g_interface_1
(
.core_clk (clk_200),
.core_resetn (axis_resetn),
.clk156 (sfp_clk156 ),
.qplllock (sfp_qplllock ),
.qplloutclk (sfp_qplloutclk ),
.qplloutrefclk (sfp_qplloutrefclk ),
.txuserrdy (sfp_txuserrdy ),
.txusrclk (sfp_txusrclk ),
.txusrclk2 (sfp_txusrclk2 ),
.areset_clk156 (sfp_areset_clk156 ),
.reset_counter_done (sfp_reset_counter_done),
.tx_abs (sfp1_tx_abs ),
.tx_disable (sfp1_tx_disable ),
.tx_fault (sfp1_tx_fault ),
.tx_resetdone (sfp1_tx_resetdone ),
.rx_resetdone (sfp1_rx_resetdone ),
.gtrxreset (sfp_gtrxreset ),
.gttxreset (sfp_gttxreset ),
.m_axis_tdata (axis_i_1_tdata ),
.m_axis_tkeep (axis_i_1_tkeep ),
.m_axis_tuser (axis_i_1_tuser ),
.m_axis_tvalid (axis_i_1_tvalid),
.m_axis_tready (axis_i_1_tready),
.m_axis_tlast (axis_i_1_tlast ),
.s_axis_tdata (axis_o_1_tdata ),
.s_axis_tkeep (axis_o_1_tkeep ),
.s_axis_tuser (axis_o_1_tuser ),
.s_axis_tvalid (axis_o_1_tvalid),
.s_axis_tready (axis_o_1_tready),
.s_axis_tlast (axis_o_1_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M05_AXI_awaddr),
.S_AXI_AWVALID (M05_AXI_awvalid),
.S_AXI_WDATA (M05_AXI_wdata),
.S_AXI_WSTRB (M05_AXI_wstrb),
.S_AXI_WVALID (M05_AXI_wvalid),
.S_AXI_BREADY (M05_AXI_bready),
.S_AXI_ARADDR (M05_AXI_araddr),
.S_AXI_ARVALID (M05_AXI_arvalid),
.S_AXI_RREADY (M05_AXI_rready),
.S_AXI_ARREADY (M05_AXI_arready),
.S_AXI_RDATA (M05_AXI_rdata),
.S_AXI_RRESP (M05_AXI_rresp),
.S_AXI_RVALID (M05_AXI_rvalid),
.S_AXI_WREADY (M05_AXI_wready),
.S_AXI_BRESP (M05_AXI_bresp),
.S_AXI_BVALID (M05_AXI_bvalid),
.S_AXI_AWREADY (M05_AXI_awready),
.txp (sfp1_tx_p),
.txn (sfp1_tx_n),
.rxp (sfp1_rx_p),
.rxn (sfp1_rx_n),
.interface_number (IF_SFP1)
);
assign sfp1_tx_led = sfp1_tx_resetdone ;
assign sfp1_rx_led = sfp1_rx_resetdone ;
nf_10g_interface_ip nf_10g_interface_2
(
.core_clk (clk_200),
.core_resetn (axis_resetn),
.clk156 (sfp_clk156 ),
.qplllock (sfp_qplllock ),
.qplloutclk (sfp_qplloutclk ),
.qplloutrefclk (sfp_qplloutrefclk ),
.txuserrdy (sfp_txuserrdy ),
.txusrclk (sfp_txusrclk ),
.txusrclk2 (sfp_txusrclk2 ),
.areset_clk156 (sfp_areset_clk156 ),
.reset_counter_done (sfp_reset_counter_done),
.gtrxreset (sfp_gtrxreset ),
.gttxreset (sfp_gttxreset ),
.tx_abs (sfp2_tx_abs ),
.tx_disable (sfp2_tx_disable ),
.tx_fault (sfp2_tx_fault ),
.tx_resetdone (sfp2_tx_resetdone ),
.rx_resetdone (sfp2_rx_resetdone ),
.m_axis_tdata (axis_i_2_tdata ),
.m_axis_tkeep (axis_i_2_tkeep ),
.m_axis_tuser (axis_i_2_tuser ),
.m_axis_tvalid (axis_i_2_tvalid),
.m_axis_tready (axis_i_2_tready),
.m_axis_tlast (axis_i_2_tlast ),
.s_axis_tdata (axis_o_2_tdata ),
.s_axis_tkeep (axis_o_2_tkeep ),
.s_axis_tuser (axis_o_2_tuser ),
.s_axis_tvalid (axis_o_2_tvalid),
.s_axis_tready (axis_o_2_tready),
.s_axis_tlast (axis_o_2_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M06_AXI_awaddr),
.S_AXI_AWVALID (M06_AXI_awvalid),
.S_AXI_WDATA (M06_AXI_wdata),
.S_AXI_WSTRB (M06_AXI_wstrb),
.S_AXI_WVALID (M06_AXI_wvalid),
.S_AXI_BREADY (M06_AXI_bready),
.S_AXI_ARADDR (M06_AXI_araddr),
.S_AXI_ARVALID (M06_AXI_arvalid),
.S_AXI_RREADY (M06_AXI_rready),
.S_AXI_ARREADY (M06_AXI_arready),
.S_AXI_RDATA (M06_AXI_rdata),
.S_AXI_RRESP (M06_AXI_rresp),
.S_AXI_RVALID (M06_AXI_rvalid),
.S_AXI_WREADY (M06_AXI_wready),
.S_AXI_BRESP (M06_AXI_bresp),
.S_AXI_BVALID (M06_AXI_bvalid),
.S_AXI_AWREADY (M06_AXI_awready),
.txp (sfp2_tx_p),
.txn (sfp2_tx_n),
.rxp (sfp2_rx_p),
.rxn (sfp2_rx_n),
.interface_number (IF_SFP2)
);
assign sfp2_tx_led = sfp2_tx_resetdone ;
assign sfp2_rx_led = sfp2_rx_resetdone ;
nf_10g_interface_ip nf_10g_interface_3
(
.core_clk (clk_200),
.core_resetn (axis_resetn),
.clk156 (sfp_clk156 ),
.qplllock (sfp_qplllock ),
.qplloutclk (sfp_qplloutclk ),
.qplloutrefclk (sfp_qplloutrefclk ),
.txuserrdy (sfp_txuserrdy ),
.txusrclk (sfp_txusrclk ),
.txusrclk2 (sfp_txusrclk2 ),
.areset_clk156 (sfp_areset_clk156 ),
.reset_counter_done (sfp_reset_counter_done),
.gtrxreset (sfp_gtrxreset ),
.gttxreset (sfp_gttxreset ),
.tx_abs (sfp3_tx_abs ),
.tx_disable (sfp3_tx_disable ),
.tx_fault (sfp3_tx_fault ),
.tx_resetdone (sfp3_tx_resetdone ),
.rx_resetdone (sfp3_rx_resetdone ),
.m_axis_tdata (axis_i_3_tdata ),
.m_axis_tkeep (axis_i_3_tkeep ),
.m_axis_tuser (axis_i_3_tuser ),
.m_axis_tvalid (axis_i_3_tvalid),
.m_axis_tready (axis_i_3_tready),
.m_axis_tlast (axis_i_3_tlast ),
.s_axis_tdata (axis_o_3_tdata ),
.s_axis_tkeep (axis_o_3_tkeep ),
.s_axis_tuser (axis_o_3_tuser ),
.s_axis_tvalid (axis_o_3_tvalid),
.s_axis_tready (axis_o_3_tready),
.s_axis_tlast (axis_o_3_tlast ),
.S_AXI_ACLK (clk_200 ),
.S_AXI_ARESETN (axi_datapath_resetn),
.S_AXI_AWADDR (M07_AXI_awaddr),
.S_AXI_AWVALID (M07_AXI_awvalid),
.S_AXI_WDATA (M07_AXI_wdata),
.S_AXI_WSTRB (M07_AXI_wstrb),
.S_AXI_WVALID (M07_AXI_wvalid),
.S_AXI_BREADY (M07_AXI_bready),
.S_AXI_ARADDR (M07_AXI_araddr),
.S_AXI_ARVALID (M07_AXI_arvalid),
.S_AXI_RREADY (M07_AXI_rready),
.S_AXI_ARREADY (M07_AXI_arready),
.S_AXI_RDATA (M07_AXI_rdata),
.S_AXI_RRESP (M07_AXI_rresp),
.S_AXI_RVALID (M07_AXI_rvalid),
.S_AXI_WREADY (M07_AXI_wready),
.S_AXI_BRESP (M07_AXI_bresp),
.S_AXI_BVALID (M07_AXI_bvalid),
.S_AXI_AWREADY (M07_AXI_awready),
.txp (sfp3_tx_p),
.txn (sfp3_tx_n),
.rxp (sfp3_rx_p),
.rxn (sfp3_rx_n),
.interface_number (IF_SFP3)
);
assign sfp3_tx_led = sfp3_tx_resetdone ;
assign sfp3_rx_led = sfp3_rx_resetdone ;
identifier_ip identifier (
.s_aclk (clk_200),
.s_aresetn (axi_datapath_resetn),
.s_axi_awaddr (M00_AXI_awaddr),
.s_axi_awvalid(M00_AXI_awvalid),
.s_axi_awready(M00_AXI_awready),
.s_axi_wdata (M00_AXI_wdata),
.s_axi_wstrb (M00_AXI_wstrb),
.s_axi_wvalid (M00_AXI_wvalid),
.s_axi_wready (M00_AXI_wready),
.s_axi_bresp (M00_AXI_bresp),
.s_axi_bvalid (M00_AXI_bvalid),
.s_axi_bready (M00_AXI_bready),
.s_axi_araddr (M00_AXI_araddr ),
.s_axi_arvalid(M00_AXI_arvalid),
.s_axi_arready(M00_AXI_arready),
.s_axi_rdata (M00_AXI_rdata),
.s_axi_rresp (M00_AXI_rresp),
.s_axi_rvalid (M00_AXI_rvalid),
.s_axi_rready (M00_AXI_rready)
);
always @ (posedge axi_clk) begin
sfp_clk100_count <= sfp_clk100_count + 1'b1;
if (!sfp_clk100_count) begin
led[1] <= ~led[1];
end
end
always @ (posedge sfp_clk156) begin
sfp_clk156_count <= sfp_clk156_count + 1'b1;
if (!sfp_clk156_count) begin
led[0] <= ~led[0];
end
end
endmodule | 3 |
142,103 | data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v | 97,045,669 | EthernetEcho_DNS.v | v | 1,220 | 211 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:197: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n xpc10 <= 1\'d1 ;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:199: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:200: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:204: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:212: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksumIP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:213: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:221: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n cam_din <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:222: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n cam_cmp_din <= 32\'h_ffff_ffff;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:226: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_UINT_CC_SCALbx22_ARA0[2\'d3] <= 32\'h300_a8c0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:227: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_UINT_CC_SCALbx22_ARA0[2\'d2] <= 32\'h200_a8c0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:228: Bit extraction of array[6:0] requires 3 bit index, not 1 bits.\n : ... In instance EthernetEcho\n A_UINT_CC_SCALbx22_ARA0[1\'d1] <= 32\'h100_a8c0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:233: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[2\'d3] <= 64\'h1_0000_6d6f_6303;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:234: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[2\'d2] <= 64\'h100_0100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:235: Bit extraction of array[6:0] requires 3 bit index, not 1 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[1\'d1] <= 64\'h100_0100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:240: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx18_ARE0[2\'d3] <= 64\'h_6563_6976_7265_736e;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:241: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx18_ARE0[2\'d2] <= 64\'h6b_7502_6361_026d;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:242: Bit extraction of array[6:0] requires 3 bit index, not 1 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx18_ARE0[1\'d1] <= 64\'h6d_6f63_036b_6f6f;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:247: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx20_ARF0[2\'d3] <= 64\'h_6f64_6e6f_6c0c_7777;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:248: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx20_ARF0[2\'d2] <= 64\'h_6163_036c_6302_7777;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:249: Bit extraction of array[6:0] requires 3 bit index, not 1 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx20_ARF0[1\'d1] <= 64\'h_6265_6361_6608_7777;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:255: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:261: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLERe1_1_V_5 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:267: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:273: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLERe1_1_V_5 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:279: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:283: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLERe1_1_V_5 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:310: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d3 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:320: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:326: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:331: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:337: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:343: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:345: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[32\'hffffffff&TLERe1_1_V_1] <= 64\'hffffffffffffffff&32\'h_ffff_ffff&TLERe1_1_V_5\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:351: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:359: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:367: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:318: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h7f\' generates 7 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:377: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:374: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6!=3\'d7 ) && (TLERe1_1_V_6!=4\'d15 ) && (TLERe1_1_V_6!=5\'d31 ) && (TLERe1_1_V_6\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:374: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6!=3\'d7 ) && (TLERe1_1_V_6!=4\'d15 ) && (TLERe1_1_V_6!=5\'d31 ) && (TLERe1_1_V_6\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:374: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6!=3\'d7 ) && (TLERe1_1_V_6!=4\'d15 ) && (TLERe1_1_V_6!=5\'d31 ) && (TLERe1_1_V_6\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:375: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:375: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h7f\' generates 7 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:375: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:375: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:376: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n (TLERe1_1_V_6!=2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:383: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:404: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d9 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:408: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksumIP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:409: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:410: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_12 <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:415: Operator AND expects 112 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:415: Operator AND expects 112 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:415: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 112 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:400: Operator LT expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if (LoEthernetEcho_one_question && LoEthernetEcho_std_query && (3\'d4<(8\'hff&8\'d1+TLEca6_0_V_0)) && 1\'h1&(0 ==\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:401: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n (64\'hffffffffffffffff&64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:420: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d7 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:421: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8\'hff&8\'d1+TLEca6_0_V_0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:419: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((2\'d2 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:430: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d7 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:431: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:428: Operator GTE expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca6_0_V_0)) && (2\'d2 !=(8\'hff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:428: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca6_0_V_0)) && (2\'d2 !=(8\'hff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:428: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca6_0_V_0)) && (2\'d2 !=(8\'hff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:429: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n &8\'d1+TLEca6_0_V_0)) && (2\'d3 !=(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:439: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d7 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:440: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8\'hff&8\'d1+TLEca6_0_V_0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:438: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((2\'d3 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:448: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d7 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:449: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64\'d4], 48\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:449: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 112 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64\'d4], 48\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:447: Operator GTE expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (3\'d4 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:447: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (3\'d4 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:457: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d7 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:458: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d48);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:456: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((1\'d1 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:470: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksumIP <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:474: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_12 <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:465: Operator LT expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4<(8\'hff&8\'d1+TLEca6_0_V_0)) && !(1\'h1&(0 ==(64\'hffffffffffffffff&64\'h_ffff&32\'h_ffff_ffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:465: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((3\'d4<(8\'hff&8\'d1+TLEca6_0_V_0)) && !(1\'h1&(0 ==(64\'hffffffffffffffff&64\'h_ffff&32\'h_ffff_ffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:485: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksumIP <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:489: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_12 <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:480: Operator LT expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if (!LoEthernetEcho_one_question && (3\'d4<(8\'hff&8\'d1+TLEca6_0_V_0)) && 1\'h1&(0 ==(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:481: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n &64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_6\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:500: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksumIP <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:504: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_12 <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:495: Operator LT expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if (LoEthernetEcho_one_question && !LoEthernetEcho_std_query && (3\'d4<(8\'hff&8\'d1+TLEca6_0_V_0)) && 1\'h1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:496: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n &(0 ==(64\'hffffffffffffffff&64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:514: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp4 <= A_64_US_CC_SCALbx14_ARC0[64\'d8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:521: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d20 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:522: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3\'d5];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:523: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw1_1_V_10 <= 64\'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:520: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_tmp==LoEthernetEcho_tmp1) && (TLEsw1_1_V_9!=4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:528: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d20 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:529: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3\'d5];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:530: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw1_1_V_10 <= 64\'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:534: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h13\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d19 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:535: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp5 <= A_64_US_CC_SCALbx14_ARC0[64\'d9];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:533: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_tmp==LoEthernetEcho_tmp1) && (TLEsw1_1_V_9==4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:541: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d30 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:542: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_1 <= A_64_US_CC_SCALbx14_ARC0[8\'hff&8\'d1+TLEca27_14_V_0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:540: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((2\'d2 ==(8\'hff&8\'d1+TLEca27_14_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:551: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d30 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:552: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_1 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:549: Operator GTE expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca27_14_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca27_14_V_0)) && (2\'d2 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:549: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca27_14_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca27_14_V_0)) && (2\'d2 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:549: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca27_14_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca27_14_V_0)) && (2\'d2 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:550: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n (8\'hff&8\'d1+TLEca27_14_V_0)) && (2\'d3 !=(8\'hff&8\'d1+TLEca27_14_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:560: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d30 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:561: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_1 <= A_64_US_CC_SCALbx14_ARC0[8\'hff&8\'d1+TLEca27_14_V_0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:559: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((2\'d3 ==(8\'hff&8\'d1+TLEca27_14_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:569: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d30 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:570: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64\'d4], 48\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:570: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 112 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64\'d4], 48\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:568: Operator GTE expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca27_14_V_0)) && (3\'d4 ==(8\'hff&8\'d1+TLEca27_14_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:568: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca27_14_V_0)) && (3\'d4 ==(8\'hff&8\'d1+TLEca27_14_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:578: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d30 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:579: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d48);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:577: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((1\'d1 ==(8\'hff&8\'d1+TLEca27_14_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:588: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksumIP <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca27_14_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:592: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_12 <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca27_14_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:586: Operator LT expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4<(8\'hff&8\'d1+TLEca27_14_V_0))) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:605: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:606: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:608: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:616: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[64\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:618: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n : ... In instance EthernetEcho\n m_axis_tkeep <= A_8_US_CC_SCALbx24_ARA0[8\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:625: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:626: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:628: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:637: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n xpc10 <= 1\'d1 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:639: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:640: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:644: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:647: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:659: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:660: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:662: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:669: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[64\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:679: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:679: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:680: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp3 <= 64\'h_1100|(-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:687: Operator EQ expects 32 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && (3\'d4 ==(32\'hffffffff&32\'d1+TLEsw1_1_V_4\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:697: Operator NEQ expects 32 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && (3\'d4 !=(32\'hffffffff&32\'d1+TLEsw1_1_V_4\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:717: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:717: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:710: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d4 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:732: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_UDP <= 1\'h1&(5\'d17 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:735: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_ICMP <= 1\'h1&(1\'d1 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:727: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:738: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:743: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:743: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:737: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d4 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:746: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:758: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:758: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:758: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:752: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:753: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n (4\'d8 !=(64\'h_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d32)))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:767: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_IPv4 <= 1\'h1&(3\'d4 ==(64\'d15&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d52)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:768: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:768: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:768: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:762: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:763: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n (4\'d8 ==(64\'h_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d32)))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:773: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:776: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_UDP <= 1\'h1&(5\'d17 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:779: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_ICMP <= 1\'h1&(1\'d1 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:772: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:786: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_ip <= 32\'h_ffff_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d16);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:781: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:793: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_one_question <= 1\'h1&(1\'d1 ==((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:788: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:797: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:800: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:800: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:800: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:795: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:796: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n (4\'d8 !=(64\'h_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d32)))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:806: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:808: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_IPv4 <= 1\'h1&(3\'d4 ==(64\'d15&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d52)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:809: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:809: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:809: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:804: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:805: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n (4\'d8 ==(64\'h_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d32)))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:814: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:817: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_ip <= 32\'h_ffff_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d16);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:813: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:820: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:823: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_one_question <= 1\'h1&(1\'d1 ==((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:819: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:829: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'15\'h7703\' generates 15 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_start_parsing <= 1\'h1&(15\'d30467 ==((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d48\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:825: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d6 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:834: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:836: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'15\'h7703\' generates 15 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_start_parsing <= 1\'h1&(15\'d30467 ==((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d48\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:833: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_9<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d6 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:841: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:841: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:841: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:842: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:842: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:843: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:852: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:849: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:849: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:849: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:850: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:850: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:851: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:195: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:195: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:195: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:195: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:195: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:195: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'5\'h12\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:195: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:858: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d20 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:859: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3\'d5];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:860: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw1_1_V_10 <= 64\'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:857: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h13\' generates 5 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_tmp2==LoEthernetEcho_tmp4)) begin if ((xpc10==5\'d19 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:866: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d20 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:867: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3\'d5];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:868: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw1_1_V_10 <= 64\'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:865: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h13\' generates 5 bits.\n : ... In instance EthernetEcho\n else if ((xpc10==5\'d19 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:875: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:883: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d7 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:884: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d48);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:886: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:887: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_7 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:888: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_6 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:895: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:901: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d10 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:902: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d1])|(LoEthernetEcho_dst_mac>>5\'d16);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:906: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d11 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:907: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d1] <= 64\'hffffffffffffffff&TLEsw9_10_V_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:911: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hc\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d12 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:912: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[64\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:912: Operator AND expects 112 bits on the LHS, but LHS\'s CONST \'64\'hffff\' generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[64\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:912: Operator AND expects 112 bits on the RHS, but RHS\'s ARRAYSEL generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[64\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:912: Operator OR expects 112 bits on the RHS, but RHS\'s REPLICATE generates 80 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[64\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:912: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 112 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[64\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:918: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hd\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d13 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:919: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d3] <= 64\'hffffffffffffffff&TLEsw9_10_V_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:924: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d14 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:925: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4])|(LoEthernetEcho_src_ip>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:930: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d14 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:931: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4])|(LoEthernetEcho_src_ip>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:931: Operator NEGATE expects 96 bits on the LHS, but LHS\'s CONST \'64\'h1000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4])|(LoEthernetEcho_src_ip>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:931: Operator AND expects 96 bits on the RHS, but RHS\'s ARRAYSEL generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4])|(LoEthernetEcho_src_ip>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:931: Operator SHIFTR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4])|(LoEthernetEcho_src_ip>>5\'d16\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:932: Operator OR expects 96 bits on the RHS, but RHS\'s REPLICATE generates 80 bits.\n : ... In instance EthernetEcho\n )|{LoEthernetEcho_app_src_port, 32\'d0}|{LoEthernetEcho_app_dst_port, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:931: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4])|(LoEthernetEcho_src_ip>>5\'d16\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:936: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d14 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:937: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEsw9_10_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4])|(LoEthernetEcho_src_ip>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:941: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n if (!TLEsw9_10_V_1 && !TLEsw9_10_V_2) xpc10 <= 4\'d14 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:945: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d15 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:946: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&TLEsw9_10_V_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:950: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d17 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:951: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= A_64_US_CC_SCALbx14_ARC0[64\'d7];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:955: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h12\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d18 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:956: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp4 <= A_64_US_CC_SCALbx14_ARC0[64\'d8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:965: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h15\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d21 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:966: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&64\'h80_0000_0000|LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:973: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&64\'h380_0000_0000|LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:978: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&64\'h380_0000_0000|LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:981: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h16\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d22 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:982: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3\'d6];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:987: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h17\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d23 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:988: Operator AND expects 64 bits on the RHS, but RHS\'s ARRAYSEL generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h400_100e|{64\'hffffffffffffffff&A_UINT_CC_SCALbx22_ARA0[32\'hffffffff&TLEsw1_1_V_5], 32\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:988: Operator OR expects 96 bits on the LHS, but LHS\'s CONST \'64\'h400100e\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h400_100e|{64\'hffffffffffffffff&A_UINT_CC_SCALbx22_ARA0[32\'hffffffff&TLEsw1_1_V_5], 32\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:988: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h400_100e|{64\'hffffffffffffffff&A_UINT_CC_SCALbx22_ARA0[32\'hffffffff&TLEsw1_1_V_5], 32\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:992: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&64\'d256|LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:997: Operator AND expects 8 bits on the LHS, but LHS\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx14_ARC0[32\'hffffffff&TLEsw1_1_V_9]|(64\'h100_0100_0cc0<<(6\'d63&4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1003: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h18\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d24 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:995: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_last_tkeep\' generates 8 bits.\n : ... In instance EthernetEcho\n 5\'d23 : if (!(!LoEthernetEcho_last_tkeep)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1008: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h19\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d25 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1014: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1a\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d26 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1015: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64\'d2];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1016: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1016: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1021: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1b\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d27 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1022: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_ffff_ffff_ffff&A_64_US_CC_SCALbx14_ARC0[64\'d4];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1023: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_UDP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (LoEthernetEcho_UDP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_UDP_total_length, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1023: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (LoEthernetEcho_UDP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_UDP_total_length, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1025: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d2] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1025: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d2] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1025: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d2] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1025: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d2] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1025: Operator ADD expects 72 bits on the LHS, but LHS\'s CONST \'64\'h10\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d2] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1025: Operator ADD expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d2] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1025: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d2] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1031: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1c\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d28 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1032: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64\'d3];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1035: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&(64\'hffffffffffffffff&64\'d16+TLEsw1_1_V_10)|{LoEthernetEcho_src_port\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1035: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&(64\'hffffffffffffffff&64\'d16+TLEsw1_1_V_10)|{LoEthernetEcho_src_port\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1035: Operator ADD expects 88 bits on the LHS, but LHS\'s CONST \'64\'h10\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&(64\'hffffffffffffffff&64\'d16+TLEsw1_1_V_10)|{LoEthernetEcho_src_port\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1035: Operator ADD expects 88 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_10\' generates 32 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&(64\'hffffffffffffffff&64\'d16+TLEsw1_1_V_10)|{LoEthernetEcho_src_port\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1036: Operator OR expects 88 bits on the RHS, but RHS\'s REPLICATE generates 80 bits.\n : ... In instance EthernetEcho\n , 24\'d0}|{LoEthernetEcho_src_port, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1035: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 88 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&(64\'hffffffffffffffff&64\'d16+TLEsw1_1_V_10)|{LoEthernetEcho_src_port\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1038: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|{((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1038: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|{((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1038: Operator ADD expects 72 bits on the LHS, but LHS\'s CONST \'64\'h10\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|{((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1038: Operator ADD expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|{((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1038: Operator AND expects 120 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|{((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1038: Operator AND expects 120 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|{((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1038: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 120 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|{((64\'hffffffffffffffff&64\'d16+LoEthernetEcho_tmp\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1044: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1d\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d29 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1045: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d3] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1049: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d30 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1050: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d48);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1052: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1053: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_7 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1054: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca27_14_V_6 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1058: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d31 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1065: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d3] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(LoEthernetEcho_chksumIP>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1065: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d3] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(LoEthernetEcho_chksumIP>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1065: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d3] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(LoEthernetEcho_chksumIP>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1065: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_chksumIP\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d3] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(LoEthernetEcho_chksumIP>>4\'d8)|{64\'d255\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1065: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[64\'d3] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(LoEthernetEcho_chksumIP>>4\'d8)|{64\'d255\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1072: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= A_64_US_CC_SCALbx14_ARC0[3\'d5];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1077: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1077: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1078: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp3 <= 64\'h_1100|(-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64\'d4]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1119: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_ffff&32\'h_ffff_ffff^LoEthernetEcho_chksum_UDP;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1124: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp3 <= {64\'d255&LoEthernetEcho_tmp2, 8\'d0}|(LoEthernetEcho_tmp2>>4\'d8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1124: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp3 <= {64\'d255&LoEthernetEcho_tmp2, 8\'d0}|(LoEthernetEcho_tmp2>>4\'d8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1125: Bit extraction of array[63:0] requires 6 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1125: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1125: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1125: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1126: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n , 8\'d0}|(LoEthernetEcho_tmp2>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1125: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1145: Operator AND expects 32 or 8 bits on the LHS, but LHS\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[32\'hffffffff&32\'d1+TLEsw1_1_V_9] <= 64\'hffffffffffffffff&(64\'h100_0100_0cc0>>(6\'d63&4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1146: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n *(4\'d8+(0-LoEthernetEcho_last_tkeep))))|(LoEthernetEcho_tmp2<<(6\'d63&4\'d8*LoEthernetEcho_last_tkeep));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1146: Operator AND expects 8 bits on the LHS, but LHS\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n *(4\'d8+(0-LoEthernetEcho_last_tkeep))))|(LoEthernetEcho_tmp2<<(6\'d63&4\'d8*LoEthernetEcho_last_tkeep));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1152: Operator AND expects 32 or 8 bits on the LHS, but LHS\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n A_8_US_CC_SCALbx24_ARA0[32\'hffffffff&32\'d2+TLEsw1_1_V_9] <= 8\'hff&(8\'d255>>>(5\'d31&4\'d8+(0-LoEthernetEcho_last_tkeep\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1152: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n A_8_US_CC_SCALbx24_ARA0[32\'hffffffff&32\'d2+TLEsw1_1_V_9] <= 8\'hff&(8\'d255>>>(5\'d31&4\'d8+(0-LoEthernetEcho_last_tkeep\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1156: Operator AND expects 32 or 8 bits on the LHS, but LHS\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n &4\'d8*(4\'d8+(0-LoEthernetEcho_last_tkeep))));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1156: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n &4\'d8*(4\'d8+(0-LoEthernetEcho_last_tkeep))));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1161: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1a\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d26 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1162: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64\'d2];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1163: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1163: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1167: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1c\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d28 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1168: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64\'d3];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1169: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp5|{LoEthernetEcho_src_port, 24\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1169: Operator AND expects 88 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp5\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp5|{LoEthernetEcho_src_port, 24\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1169: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 88 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp5|{LoEthernetEcho_src_port, 24\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h14\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h15\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h16\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h17\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h18\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h19\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1a\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1b\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1c\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1d\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:873: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1172: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n if ((xpc10==4\'d15 )) xpc10 <= 5\'d16 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1172: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((xpc10==4\'d15 )) xpc10 <= 5\'d16 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1180: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin161810 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1180: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin161810 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1180: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin161810 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1180: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin161810 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1181: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>5\'d16))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1181: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\n), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>5\'d16))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1180: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin161810 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1183: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin162310 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1183: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin162310 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1183: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin162310 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1183: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin162310 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1184: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n&(TLEca6_0_V_1>>6\'d48), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d48))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1184: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\n&(TLEca6_0_V_1>>6\'d48), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d48))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1183: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin162310 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1186: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin176810 = (64\'hffffffffffffffff&{64\'d255&TLEca27_14_V_1, 8\'d0}|((64\'h_ff00&TLEca27_14_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1186: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin176810 = (64\'hffffffffffffffff&{64\'d255&TLEca27_14_V_1, 8\'d0}|((64\'h_ff00&TLEca27_14_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1186: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'TLEca27_14_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin176810 = (64\'hffffffffffffffff&{64\'d255&TLEca27_14_V_1, 8\'d0}|((64\'h_ff00&TLEca27_14_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1186: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin176810 = (64\'hffffffffffffffff&{64\'d255&TLEca27_14_V_1, 8\'d0}|((64\'h_ff00&TLEca27_14_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1187: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>5\'d16))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1187: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca27_14_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>5\'d16))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1186: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin176810 = (64\'hffffffffffffffff&{64\'d255&TLEca27_14_V_1, 8\'d0}|((64\'h_ff00&TLEca27_14_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1189: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin177310 = (64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1189: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin177310 = (64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1189: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca27_14_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin177310 = (64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1189: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin177310 = (64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1190: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n&(TLEca27_14_V_1>>6\'d48), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>6\'d48))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1190: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca27_14_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\n&(TLEca27_14_V_1>>6\'d48), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>6\'d48))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1189: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin177310 = (64\'hffffffffffffffff&{64\'d255&(TLEca27_14_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca27_14_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1192: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin182110 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp3, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp3)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1192: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin182110 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp3, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp3)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1192: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp3\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin182110 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp3, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp3)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1192: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin182110 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp3, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp3)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1193: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>5\'d16))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1193: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp3\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>5\'d16))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1192: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin182110 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp3, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp3)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1195: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin182610 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1195: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin182610 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1195: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp3\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin182610 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1196: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp3>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>6\'d48))>>4\'d8));\n^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1196: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp3>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>6\'d48))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1196: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp3\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp3>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>6\'d48))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1195: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin182610 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp3>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp3>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1198: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin184210 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1198: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin184210 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1198: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin184210 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1198: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin184210 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1199: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>5\'d16))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1199: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>5\'d16))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1198: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin184210 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1201: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin184710 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1201: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin184710 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1201: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin184710 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1202: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp2>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d48))>>4\'d8));\n^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1202: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp2>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d48))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1202: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp2>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d48))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:1201: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin184710 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:382: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n 3\'d4 : if (((32\'hffffffff&TLERe1_1_V_1)<32\'d0)) begin \n ^\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:601: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (!m_axis_tready && ((32\'hffffffff&TLEsw1_1_V_9)>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:612: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (m_axis_tready && ((32\'hffffffff&TLEsw1_1_V_9)>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/EthernetEcho_DNS.v:623: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (((32\'hffffffff&TLEsw1_1_V_9)<32\'d0)) begin \n ^\n%Error: Exiting due to 441 warning(s)\n' | 313,043 | module | module EthernetEcho( input [63:0] s_axis_tdata,
input [7:0] s_axis_tkeep,
input s_axis_tlast,
input s_axis_tvalid,
output reg s_axis_tready,
input [63:0] s_axis_tuser_hi,
input [63:0] s_axis_tuser_low,
output reg [63:0] m_axis_tdata,
output reg [7:0] m_axis_tkeep,
output reg m_axis_tlast,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tuser_hi,
output reg [63:0] m_axis_tuser_low,
input cam_busy,
input cam_match,
input [7:0] cam_match_addr,
output reg [63:0] cam_cmp_din,
output reg [63:0] cam_din,
output reg cam_we,
output reg [7:0] cam_wr_addr,
input clk,
input reset);
reg LoEthernetEcho_IPv4;
reg LoEthernetEcho_proto_UDP;
reg LoEthernetEcho_proto_ICMP;
reg [7:0] LoEthernetEcho_last_tkeep;
reg LoEthernetEcho_exist_rest;
reg [63:0] LoEthernetEcho_chksum_UDP;
reg [63:0] LoEthernetEcho_chksumIP;
reg [63:0] TLEsw1_1_V_2;
reg [63:0] TLEsw1_1_V_3;
reg [31:0] TLEsw1_1_V_4;
reg [31:0] TLEsw1_1_V_5;
reg [31:0] TLEsw1_1_V_9;
reg [31:0] TLEsw1_1_V_10;
reg TLEsw1_1_V_11;
reg TLEsw1_1_V_12;
reg TLEsw1_1_V_13;
reg [31:0] TLERe1_1_V_0;
reg [31:0] TLERe1_1_V_1;
reg TLERe1_1_V_3;
reg [63:0] TLERe1_1_V_5;
reg [7:0] TLERe1_1_V_6;
reg [7:0] TLEca6_0_V_0;
reg [63:0] TLEca6_0_V_1;
reg [63:0] TLEca6_0_V_6;
reg [63:0] TLEca6_0_V_7;
reg [63:0] TLEca6_0_V_12;
reg [63:0] TLEsw9_10_V_0;
reg TLEsw9_10_V_1;
reg TLEsw9_10_V_2;
reg [7:0] TLEca27_14_V_0;
reg [63:0] TLEca27_14_V_1;
reg [63:0] TLEca27_14_V_6;
reg [63:0] TLEca27_14_V_7;
reg [63:0] TLEca27_14_V_12;
reg [63:0] TLEca31_5_V_4;
reg [63:0] TLEca31_5_V_5;
reg [63:0] TLEca31_5_V_7;
reg [63:0] TLEca33_17_V_4;
reg [63:0] TLEca33_17_V_5;
reg [63:0] TLEca33_17_V_7;
reg [63:0] TLEca33_20_V_4;
reg [63:0] TLEca33_20_V_5;
reg [63:0] TLEca33_20_V_7;
reg [31:0] TLESe34_3_V_0;
reg [31:0] TLESe34_3_V_1;
reg LoEthernetEcho_one_question;
reg LoEthernetEcho_std_query;
reg [63:0] LoEthernetEcho_dst_mac;
reg [63:0] LoEthernetEcho_src_mac;
reg [63:0] LoEthernetEcho_dst_ip;
reg [63:0] LoEthernetEcho_src_ip;
reg [63:0] LoEthernetEcho_app_src_port;
reg [63:0] LoEthernetEcho_app_dst_port;
reg [63:0] LoEthernetEcho_tmp;
reg [63:0] LoEthernetEcho_tmp1;
reg [63:0] LoEthernetEcho_tmp2;
reg [63:0] LoEthernetEcho_tmp3;
reg [63:0] LoEthernetEcho_tmp4;
reg [63:0] LoEthernetEcho_tmp5;
reg LoEthernetEcho_start_parsing;
reg [63:0] LoEthernetEcho_IP_total_length;
reg [63:0] LoEthernetEcho_UDP_total_length;
reg [63:0] LoEthernetEcho_src_port;
reg [7:0] A_8_US_CC_SCALbx24_ARA0[63:0];
reg [31:0] A_UINT_CC_SCALbx22_ARA0[6:0];
reg [63:0] A_64_US_CC_SCALbx10_ARA0[63:0];
reg [63:0] A_64_US_CC_SCALbx12_ARB0[63:0];
reg [63:0] A_64_US_CC_SCALbx14_ARC0[63:0];
reg [63:0] A_64_US_CC_SCALbx16_ARD0[6:0];
reg [63:0] A_64_US_CC_SCALbx18_ARE0[6:0];
reg [63:0] A_64_US_CC_SCALbx20_ARF0[6:0];
reg [5:0] xpc10;
wire [63:0] hprpin161810;
wire [63:0] hprpin162310;
wire [63:0] hprpin176810;
wire [63:0] hprpin177310;
wire [63:0] hprpin182110;
wire [63:0] hprpin182610;
wire [63:0] hprpin184210;
wire [63:0] hprpin184710;
always @(posedge clk ) begin
if (reset) begin
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 64'd0;
cam_cmp_din <= 64'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 64'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
LoEthernetEcho_last_tkeep <= 8'd0;
TLERe1_1_V_0 <= 32'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEsw1_1_V_11 <= 1'd0;
TLEca6_0_V_7 <= 64'd0;
TLEca6_0_V_6 <= 64'd0;
TLEsw9_10_V_2 <= 1'd0;
TLEsw9_10_V_1 <= 1'd0;
TLEca6_0_V_1 <= 64'd0;
TLEca6_0_V_0 <= 8'd0;
TLEca6_0_V_12 <= 64'd0;
TLEsw9_10_V_0 <= 64'd0;
LoEthernetEcho_tmp4 <= 64'd0;
TLEsw1_1_V_10 <= 32'd0;
TLEsw1_1_V_5 <= 32'd0;
LoEthernetEcho_tmp5 <= 64'd0;
LoEthernetEcho_tmp1 <= 64'd0;
TLEca27_14_V_7 <= 64'd0;
TLEca27_14_V_6 <= 64'd0;
LoEthernetEcho_chksumIP <= 64'd0;
TLEca27_14_V_1 <= 64'd0;
TLEca27_14_V_0 <= 8'd0;
TLEca27_14_V_12 <= 64'd0;
TLEca33_17_V_5 <= 64'd0;
TLEca33_17_V_4 <= 64'd0;
TLEca33_17_V_7 <= 64'd0;
TLEca33_20_V_5 <= 64'd0;
TLEca33_20_V_4 <= 64'd0;
TLEca33_20_V_7 <= 64'd0;
TLESe34_3_V_1 <= 32'd0;
s_axis_tready <= 1'd0;
LoEthernetEcho_exist_rest <= 1'd0;
TLEsw1_1_V_9 <= 32'd0;
m_axis_tvalid <= 1'd0;
TLESe34_3_V_0 <= 32'd0;
m_axis_tuser_low <= 64'd0;
m_axis_tuser_hi <= 64'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 64'd0;
TLEca31_5_V_5 <= 64'd0;
TLEca31_5_V_4 <= 64'd0;
TLEca31_5_V_7 <= 64'd0;
LoEthernetEcho_tmp3 <= 64'd0;
LoEthernetEcho_chksum_UDP <= 64'd0;
LoEthernetEcho_tmp2 <= 64'd0;
LoEthernetEcho_tmp <= 64'd0;
LoEthernetEcho_start_parsing <= 1'd0;
LoEthernetEcho_std_query <= 1'd0;
LoEthernetEcho_one_question <= 1'd0;
LoEthernetEcho_UDP_total_length <= 64'd0;
LoEthernetEcho_app_dst_port <= 64'd0;
LoEthernetEcho_app_src_port <= 64'd0;
LoEthernetEcho_dst_ip <= 64'd0;
LoEthernetEcho_src_ip <= 64'd0;
LoEthernetEcho_IP_total_length <= 64'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
xpc10 <= 6'd0;
TLEsw1_1_V_3 <= 64'd0;
TLEsw1_1_V_2 <= 64'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_src_port <= 64'd0;
LoEthernetEcho_src_mac <= 64'd0;
LoEthernetEcho_dst_mac <= 64'd0;
end
else begin
case (xpc10)
0: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEsw1_1_V_11 <= 1'd0;
TLEsw1_1_V_10 <= 32'd0;
TLEsw1_1_V_9 <= 32'd0;
TLEsw1_1_V_5 <= 32'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_chksumIP <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_exist_rest <= 1'd0;
LoEthernetEcho_last_tkeep <= 8'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 32'd0;
cam_cmp_din <= 32'h_ffff_ffff;
A_UINT_CC_SCALbx22_ARA0[3'd6] <= 32'h600_a8c0;
A_UINT_CC_SCALbx22_ARA0[3'd5] <= 32'h500_a8c0;
A_UINT_CC_SCALbx22_ARA0[3'd4] <= 32'h400_a8c0;
A_UINT_CC_SCALbx22_ARA0[2'd3] <= 32'h300_a8c0;
A_UINT_CC_SCALbx22_ARA0[2'd2] <= 32'h200_a8c0;
A_UINT_CC_SCALbx22_ARA0[1'd1] <= 32'h100_a8c0;
A_UINT_CC_SCALbx22_ARA0[0] <= 32'h_a8c0;
A_64_US_CC_SCALbx16_ARD0[3'd6] <= 64'h1_0000_6772_6f03;
A_64_US_CC_SCALbx16_ARD0[3'd5] <= 64'd0;
A_64_US_CC_SCALbx16_ARD0[3'd4] <= 64'h1_0001_0000_6b75;
A_64_US_CC_SCALbx16_ARD0[2'd3] <= 64'h1_0000_6d6f_6303;
A_64_US_CC_SCALbx16_ARD0[2'd2] <= 64'h100_0100;
A_64_US_CC_SCALbx16_ARD0[1'd1] <= 64'h100_0100;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'd256;
A_64_US_CC_SCALbx18_ARE0[3'd6] <= 64'h_6566_696c_646c_6977;
A_64_US_CC_SCALbx18_ARE0[3'd5] <= 64'h1_0100;
A_64_US_CC_SCALbx18_ARE0[3'd4] <= 64'h263_6f02_6567_6469;
A_64_US_CC_SCALbx18_ARE0[2'd3] <= 64'h_6563_6976_7265_736e;
A_64_US_CC_SCALbx18_ARE0[2'd2] <= 64'h6b_7502_6361_026d;
A_64_US_CC_SCALbx18_ARE0[1'd1] <= 64'h6d_6f63_036b_6f6f;
A_64_US_CC_SCALbx18_ARE0[0] <= 64'h100_006d_6f63_0365;
A_64_US_CC_SCALbx20_ARF0[3'd6] <= 64'h_646c_726f_770c_7777;
A_64_US_CC_SCALbx20_ARF0[3'd5] <= 64'h_7267_026e_6902_7777;
A_64_US_CC_SCALbx20_ARF0[3'd4] <= 64'h_7262_6d61_6309_7777;
A_64_US_CC_SCALbx20_ARF0[2'd3] <= 64'h_6f64_6e6f_6c0c_7777;
A_64_US_CC_SCALbx20_ARF0[2'd2] <= 64'h_6163_036c_6302_7777;
A_64_US_CC_SCALbx20_ARF0[1'd1] <= 64'h_6265_6361_6608_7777;
A_64_US_CC_SCALbx20_ARF0[0] <= 64'h_6c67_6f6f_6706_7777;
end
1'd1: begin
if (s_axis_tvalid && s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_8_US_CC_SCALbx24_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_8_US_CC_SCALbx24_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!s_axis_tvalid) begin
xpc10 <= 2'd2;
TLERe1_1_V_3 <= 1'd1;
TLERe1_1_V_0 <= 32'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
TLERe1_1_V_1 <= 32'd0;
end
end
2'd2: begin
if (s_axis_tvalid && s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!TLERe1_1_V_3) begin
xpc10 <= 2'd3;
TLERe1_1_V_6 <= A_8_US_CC_SCALbx24_ARA0[8'h1*(32'hffffffff&TLERe1_1_V_1)];
TLERe1_1_V_5 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1];
end
end
2'd3: begin
case (TLERe1_1_V_6)
1'd1: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd1;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'd255&TLERe1_1_V_5;
end
2'd2: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd0;
end
2'd3: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd2;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff&TLERe1_1_V_5;
end
3'd7: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd3;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff&TLERe1_1_V_5;
end
4'd15: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&32'h_ffff_ffff&TLERe1_1_V_5
;
end
5'd31: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd5;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff&TLERe1_1_V_5
;
end
6'd63: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd6;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff_ffff_ffff&TLERe1_1_V_5
;
end
7'd127: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd7;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff_ffff&TLERe1_1_V_5
;
end
endcase
if ((TLERe1_1_V_6!=3'd7) && (TLERe1_1_V_6!=4'd15) && (TLERe1_1_V_6!=5'd31) && (TLERe1_1_V_6
!=6'd63) && (TLERe1_1_V_6!=7'd127) && (TLERe1_1_V_6!=1'd1) && (TLERe1_1_V_6!=2'd2) &&
(TLERe1_1_V_6!=2'd3)) begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd0;
end
end
3'd4: if (((32'hffffffff&TLERe1_1_V_1)<32'd0)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_9 <= TLERe1_1_V_1;
TLERe1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
else begin
xpc10 <= 6'd51;
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'd0];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_9 <= TLERe1_1_V_1;
TLERe1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
4'd8: begin
if (LoEthernetEcho_one_question && LoEthernetEcho_std_query && (3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && 1'h1&(0==
(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16))))) begin
xpc10 <= 4'd9;
TLEsw9_10_V_2 <= 1'h1&TLEsw1_1_V_13;
TLEsw9_10_V_1 <= 1'h1&TLEsw1_1_V_12;
LoEthernetEcho_exist_rest <= 1'd0;
LoEthernetEcho_chksumIP <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
A_64_US_CC_SCALbx14_ARC0[0] <= 64'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48'd0
};
end
if ((2'd2==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (1'd1!=(8'hff&8'd1+TLEca6_0_V_0)) && (2'd2!=(8'hff
&8'd1+TLEca6_0_V_0)) && (2'd3!=(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= 32'd0;
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((2'd3==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (3'd4==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64'd4], 48'd0};
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((1'd1==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && !(1'h1&(0==(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff
^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6
+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6
+TLEca6_0_V_7>>5'd16))>>5'd16)))))) begin
xpc10 <= 6'd41;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
if (!LoEthernetEcho_one_question && (3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && 1'h1&(0==(64'hffffffffffffffff
&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6
+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6
+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16))))) begin
xpc10 <= 6'd41;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
if (LoEthernetEcho_one_question && !LoEthernetEcho_std_query && (3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && 1'h1
&(0==(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16))))) begin
xpc10 <= 6'd41;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
end
5'd18: begin
if ((LoEthernetEcho_tmp!=LoEthernetEcho_tmp1) && ((32'hffffffff&32'd1+TLEsw1_1_V_4)<3'd7)) begin
LoEthernetEcho_tmp4 <= A_64_US_CC_SCALbx14_ARC0[64'd8];
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx16_ARD0[32'hffffffff&32'd1+TLEsw1_1_V_4];
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx18_ARE0[32'hffffffff&32'd1+TLEsw1_1_V_4];
LoEthernetEcho_tmp1 <= A_64_US_CC_SCALbx20_ARF0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_tmp==LoEthernetEcho_tmp1) && (TLEsw1_1_V_9!=4'd9)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_5 <= TLEsw1_1_V_4;
LoEthernetEcho_exist_rest <= 1'h1&(LoEthernetEcho_tmp2==LoEthernetEcho_tmp4);
end
if ((LoEthernetEcho_tmp!=LoEthernetEcho_tmp1) && ((32'hffffffff&32'd1+TLEsw1_1_V_4)>=3'd7)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_tmp==LoEthernetEcho_tmp1) && (TLEsw1_1_V_9==4'd9)) begin
xpc10 <= 5'd19;
LoEthernetEcho_tmp5 <= A_64_US_CC_SCALbx14_ARC0[64'd9];
end
end
5'd31: begin
if ((2'd2==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca27_14_V_0];
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca27_14_V_0)) && (1'd1!=(8'hff&8'd1+TLEca27_14_V_0)) && (2'd2!=
(8'hff&8'd1+TLEca27_14_V_0)) && (2'd3!=(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= 32'd0;
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((2'd3==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca27_14_V_0];
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca27_14_V_0)) && (3'd4==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64'd4], 48'd0};
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((1'd1==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((3'd4<(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 6'd32;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16));
TLEca27_14_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16));
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
end
end
6'd41: begin
if (!m_axis_tready && ((32'hffffffff&TLEsw1_1_V_9)>=32'd0)) begin
xpc10 <= 6'd43;
TLESe34_3_V_1 <= TLEsw1_1_V_9;
TLESe34_3_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
end
if (m_axis_tready && ((32'hffffffff&TLEsw1_1_V_9)>=32'd0)) begin
xpc10 <= 6'd43;
TLESe34_3_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[64'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_9==0);
m_axis_tkeep <= A_8_US_CC_SCALbx24_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLESe34_3_V_1 <= TLEsw1_1_V_9;
m_axis_tvalid <= 1'd1;
end
if (((32'hffffffff&TLEsw1_1_V_9)<32'd0)) begin
xpc10 <= 6'd42;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe34_3_V_1 <= TLEsw1_1_V_9;
TLESe34_3_V_0 <= 32'd0;
end
end
6'd42: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
LoEthernetEcho_exist_rest <= 1'd0;
TLEsw1_1_V_9 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_start_parsing <= 1'd0;
LoEthernetEcho_std_query <= 1'd0;
LoEthernetEcho_one_question <= 1'd0;
end
6'd43: begin
if ((TLESe34_3_V_1<TLESe34_3_V_0)) begin
xpc10 <= 6'd42;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
end
if (m_axis_tready && (TLESe34_3_V_1>=TLESe34_3_V_0)) begin
TLESe34_3_V_0 <= 32'd1+TLESe34_3_V_0;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[64'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_9==TLESe34_3_V_0);
m_axis_tkeep <= A_8_US_CC_SCALbx24_ARA0[8'h1*(32'hffffffff&TLESe34_3_V_0)];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLESe34_3_V_0];
end
end
6'd45: begin
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd35;
LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp3 <= 64'h_1100|(-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4]);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+TLEca31_5_V_5
)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16)))+(TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+
TLEca31_5_V_5)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4==(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd44;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4]>>5'd16);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+TLEca31_5_V_5
)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16)))+(TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+
TLEca31_5_V_5)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4!=(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd44;
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+TLEca31_5_V_5
)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16)))+(TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+
TLEca31_5_V_5)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16))>>5'd16);
end
end
6'd51: begin
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_UDP_total_length <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==0)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_UDP_total_length <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==0)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8!=(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8==(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_std_query <= 1'h1&(0==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd36)));
LoEthernetEcho_one_question <= 1'h1&(1'd1==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56));
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8!=(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8==(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_std_query <= 1'h1&(0==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd36)));
LoEthernetEcho_one_question <= 1'h1&(1'd1==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56));
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_start_parsing <= 1'h1&(15'd30467==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48
));
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_start_parsing <= 1'h1&(15'd30467==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48
));
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)!=0) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)!=0) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
end
endcase
if ((LoEthernetEcho_tmp2==LoEthernetEcho_tmp4)) begin if ((xpc10==5'd19)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_5 <= TLEsw1_1_V_4;
LoEthernetEcho_exist_rest <= 1'h1&(LoEthernetEcho_tmp3==LoEthernetEcho_tmp5);
end
end
else if ((xpc10==5'd19)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_5 <= TLEsw1_1_V_4;
LoEthernetEcho_exist_rest <= 1'd0;
end
case (xpc10)
3'd5: begin
xpc10 <= 3'd6;
TLEsw1_1_V_13 <= 1'h1&LoEthernetEcho_proto_ICMP;
TLEsw1_1_V_12 <= 1'h1&LoEthernetEcho_proto_UDP;
TLEsw1_1_V_11 <= 1'h1&LoEthernetEcho_IPv4;
end
3'd6: begin
if (TLEsw1_1_V_11 && TLEsw1_1_V_12) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1;
TLEca6_0_V_12 <= 32'd0;
TLEca6_0_V_7 <= 32'd0;
TLEca6_0_V_6 <= 32'd0;
end
if (TLEsw1_1_V_11 && !TLEsw1_1_V_12) xpc10 <= 6'd41;
if (!TLEsw1_1_V_11) xpc10 <= 6'd41;
end
3'd7: begin
xpc10 <= 4'd8;
TLEca6_0_V_7 <= (64'h_ffff&hprpin162310)+(hprpin162310>>5'd16);
TLEca6_0_V_6 <= (64'h_ffff&hprpin161810)+(hprpin161810>>5'd16);
end
4'd9: begin
xpc10 <= 4'd10;
TLEsw9_10_V_0 <= (-64'h1_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd1])|(LoEthernetEcho_dst_mac>>5'd16);
end
4'd10: begin
xpc10 <= 4'd11;
A_64_US_CC_SCALbx14_ARC0[64'd1] <= 64'hffffffffffffffff&TLEsw9_10_V_0;
end
4'd11: begin
xpc10 <= 4'd12;
TLEsw9_10_V_0 <= (64'h_ffff&A_64_US_CC_SCALbx14_ARC0[64'd3])|{LoEthernetEcho_dst_ip, 16'd0}|{LoEthernetEcho_src_ip
, 48'd0};
end
4'd12: begin
xpc10 <= 4'd13;
A_64_US_CC_SCALbx14_ARC0[64'd3] <= 64'hffffffffffffffff&TLEsw9_10_V_0;
end
4'd13: begin
if (!TLEsw9_10_V_1 && TLEsw9_10_V_2) begin
xpc10 <= 4'd14;
TLEsw9_10_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4])|(LoEthernetEcho_src_ip>>5'd16
);
end
if (TLEsw9_10_V_1 && !TLEsw9_10_V_2) begin
xpc10 <= 4'd14;
TLEsw9_10_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4])|(LoEthernetEcho_src_ip>>5'd16
)|{LoEthernetEcho_app_src_port, 32'd0}|{LoEthernetEcho_app_dst_port, 16'd0};
end
if (TLEsw9_10_V_1 && TLEsw9_10_V_2) begin
xpc10 <= 4'd14;
TLEsw9_10_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4])|(LoEthernetEcho_src_ip>>5'd16
);
end
if (!TLEsw9_10_V_1 && !TLEsw9_10_V_2) xpc10 <= 4'd14;
end
4'd14: begin
xpc10 <= 4'd15;
A_64_US_CC_SCALbx14_ARC0[64'd4] <= 64'hffffffffffffffff&TLEsw9_10_V_0;
end
5'd16: begin
xpc10 <= 5'd17;
LoEthernetEcho_tmp <= A_64_US_CC_SCALbx14_ARC0[64'd7];
end
5'd17: begin
xpc10 <= 5'd18;
LoEthernetEcho_tmp4 <= A_64_US_CC_SCALbx14_ARC0[64'd8];
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx16_ARD0[32'd0];
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx18_ARE0[32'd0];
LoEthernetEcho_tmp1 <= A_64_US_CC_SCALbx20_ARF0[32'd0];
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_5 <= 32'd7;
end
5'd20: begin
xpc10 <= 5'd21;
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&64'h80_0000_0000|LoEthernetEcho_tmp;
end
5'd21: begin
if (!LoEthernetEcho_start_parsing) begin
xpc10 <= 6'd50;
LoEthernetEcho_tmp5 <= A_64_US_CC_SCALbx10_ARA0[0];
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&64'h380_0000_0000|LoEthernetEcho_tmp;
end
if (LoEthernetEcho_start_parsing && !LoEthernetEcho_exist_rest) begin
xpc10 <= 6'd50;
LoEthernetEcho_tmp5 <= A_64_US_CC_SCALbx10_ARA0[0];
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&64'h380_0000_0000|LoEthernetEcho_tmp;
end
if (LoEthernetEcho_start_parsing && LoEthernetEcho_exist_rest) begin
xpc10 <= 5'd22;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd6];
end
end
5'd22: begin
xpc10 <= 5'd23;
LoEthernetEcho_tmp2 <= 64'h400_100e|{64'hffffffffffffffff&A_UINT_CC_SCALbx22_ARA0[32'hffffffff&TLEsw1_1_V_5], 32'd0
};
LoEthernetEcho_tmp1 <= 64'h100_0100_0cc0;
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&64'd256|LoEthernetEcho_tmp;
end
5'd23: if (!(!LoEthernetEcho_last_tkeep)) begin
xpc10 <= 6'd46;
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLEsw1_1_V_9]|(64'h100_0100_0cc0<<(6'd63&4'd8
*LoEthernetEcho_last_tkeep));
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&TLEsw1_1_V_9] <= 8'd255;
end
else begin
xpc10 <= 5'd24;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 64'h100_0100_0cc0;
end
5'd24: begin
xpc10 <= 5'd25;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 8'd255;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2;
end
5'd25: begin
xpc10 <= 5'd26;
LoEthernetEcho_tmp2 <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd2];
LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0};
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 8'd255;
end
5'd26: begin
xpc10 <= 5'd27;
LoEthernetEcho_tmp2 <= 64'h_ffff_ffff_ffff&A_64_US_CC_SCALbx14_ARC0[64'd4];
LoEthernetEcho_tmp <= (LoEthernetEcho_UDP_total_length>>4'd8)|{64'd255&LoEthernetEcho_UDP_total_length, 8'd0};
LoEthernetEcho_IP_total_length <= 64'd16+LoEthernetEcho_tmp;
A_64_US_CC_SCALbx14_ARC0[64'd2] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2|((64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp
)>>4'd8)|{64'd255&64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp, 8'd0};
end
5'd27: begin
xpc10 <= 5'd28;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd3];
TLEsw1_1_V_9 <= 32'd2+TLEsw1_1_V_9;
LoEthernetEcho_UDP_total_length <= 64'd16+LoEthernetEcho_tmp;
A_64_US_CC_SCALbx10_ARA0[0] <= 64'hffffffffffffffff&(64'hffffffffffffffff&64'd16+TLEsw1_1_V_10)|{LoEthernetEcho_src_port
, 24'd0}|{LoEthernetEcho_src_port, 16'd0};
A_64_US_CC_SCALbx14_ARC0[64'd4] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2|{((64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp
)>>4'd8)|{64'd255&64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp, 8'd0}, 48'd0};
end
5'd28: begin
xpc10 <= 5'd29;
A_64_US_CC_SCALbx14_ARC0[64'd3] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
5'd29: begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca27_14_V_0 <= 8'd1;
TLEca27_14_V_12 <= 32'd0;
TLEca27_14_V_7 <= 32'd0;
TLEca27_14_V_6 <= 32'd0;
end
5'd30: begin
xpc10 <= 5'd31;
TLEca27_14_V_7 <= (64'h_ffff&hprpin177310)+(hprpin177310>>5'd16);
TLEca27_14_V_6 <= (64'h_ffff&hprpin176810)+(hprpin176810>>5'd16);
end
6'd32: begin
xpc10 <= 6'd33;
A_64_US_CC_SCALbx14_ARC0[64'd3] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|(LoEthernetEcho_chksumIP>>4'd8)|{64'd255
&LoEthernetEcho_chksumIP, 8'd0};
end
6'd33: begin
xpc10 <= 6'd34;
LoEthernetEcho_tmp <= A_64_US_CC_SCALbx14_ARC0[3'd5];
end
6'd34: if ((TLEsw1_1_V_9<32'd4)) begin
xpc10 <= 6'd35;
LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp3 <= 64'h_1100|(-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4]);
TLEsw1_1_V_4 <= 32'd4;
end
else begin
xpc10 <= 6'd44;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'd4]>>5'd16);
TLEsw1_1_V_4 <= 32'd4;
end
6'd35: begin
xpc10 <= 6'd36;
TLEca33_17_V_5 <= (64'h_ffff&hprpin182610)+(hprpin182610>>5'd16);
TLEca33_17_V_4 <= (64'h_ffff&hprpin182110)+(hprpin182110>>5'd16);
TLEca33_17_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd36: begin
xpc10 <= 6'd37;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca33_17_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_17_V_4+TLEca33_17_V_5
)+(TLEca33_17_V_4+TLEca33_17_V_5>>5'd16)))+(TLEca33_17_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_17_V_4+TLEca33_17_V_5
)+(TLEca33_17_V_4+TLEca33_17_V_5>>5'd16))>>5'd16);
end
6'd37: begin
xpc10 <= 6'd38;
TLEca33_20_V_5 <= (64'h_ffff&hprpin184710)+(hprpin184710>>5'd16);
TLEca33_20_V_4 <= (64'h_ffff&hprpin184210)+(hprpin184210>>5'd16);
TLEca33_20_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd38: begin
xpc10 <= 6'd39;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca33_20_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_20_V_4+TLEca33_20_V_5
)+(TLEca33_20_V_4+TLEca33_20_V_5>>5'd16)))+(TLEca33_20_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_20_V_4+TLEca33_20_V_5
)+(TLEca33_20_V_4+TLEca33_20_V_5>>5'd16))>>5'd16);
end
6'd39: begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= 64'h_ffff&32'h_ffff_ffff^LoEthernetEcho_chksum_UDP;
end
6'd40: begin
xpc10 <= 6'd41;
LoEthernetEcho_tmp3 <= {64'd255&LoEthernetEcho_tmp2, 8'd0}|(LoEthernetEcho_tmp2>>4'd8);
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|(64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp2
, 8'd0}|(LoEthernetEcho_tmp2>>4'd8));
end
6'd44: begin
xpc10 <= 6'd45;
TLEca31_5_V_5 <= (64'h_ffff&hprpin184710)+(hprpin184710>>5'd16);
TLEca31_5_V_4 <= (64'h_ffff&hprpin184210)+(hprpin184210>>5'd16);
TLEca31_5_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd46: begin
xpc10 <= 6'd47;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLEsw1_1_V_9] <= 64'hffffffffffffffff&LoEthernetEcho_tmp3;
end
6'd47: begin
xpc10 <= 6'd48;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 8'd255;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 64'hffffffffffffffff&(64'h100_0100_0cc0>>(6'd63&4'd8
*(4'd8+(0-LoEthernetEcho_last_tkeep))))|(LoEthernetEcho_tmp2<<(6'd63&4'd8*LoEthernetEcho_last_tkeep));
end
6'd48: begin
xpc10 <= 6'd49;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 8'hff&(8'd255>>>(5'd31&4'd8+(0-LoEthernetEcho_last_tkeep
)));
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 64'hffffffffffffffff&(LoEthernetEcho_tmp2>>(6'd63
&4'd8*(4'd8+(0-LoEthernetEcho_last_tkeep))));
end
6'd49: begin
xpc10 <= 5'd26;
LoEthernetEcho_tmp2 <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd2];
LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0};
end
6'd50: begin
xpc10 <= 5'd28;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd3];
A_64_US_CC_SCALbx10_ARA0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp5|{LoEthernetEcho_src_port, 24'd0};
end
endcase
if ((xpc10==4'd15)) xpc10 <= 5'd16;
end
end
assign hprpin161810 = (64'hffffffffffffffff&{64'd255&TLEca6_0_V_1, 8'd0}|((64'h_ff00&TLEca6_0_V_1)>>4'd8))+(64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>5'd16
), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>5'd16))>>4'd8));
assign hprpin162310 = (64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>6'd32), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd32))>>4'd8))+(64'hffffffffffffffff&{64'd255
&(TLEca6_0_V_1>>6'd48), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd48))>>4'd8));
assign hprpin176810 = (64'hffffffffffffffff&{64'd255&TLEca27_14_V_1, 8'd0}|((64'h_ff00&TLEca27_14_V_1)>>4'd8))+(64'hffffffffffffffff&{64'd255&(TLEca27_14_V_1
>>5'd16), 8'd0}|((64'h_ff00&(TLEca27_14_V_1>>5'd16))>>4'd8));
assign hprpin177310 = (64'hffffffffffffffff&{64'd255&(TLEca27_14_V_1>>6'd32), 8'd0}|((64'h_ff00&(TLEca27_14_V_1>>6'd32))>>4'd8))+(64'hffffffffffffffff&{64'd255
&(TLEca27_14_V_1>>6'd48), 8'd0}|((64'h_ff00&(TLEca27_14_V_1>>6'd48))>>4'd8));
assign hprpin182110 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp3, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp3)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp3
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp3>>5'd16))>>4'd8));
assign hprpin182610 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp3>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp3>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp3>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp3>>6'd48))>>4'd8));
assign hprpin184210 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp2, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp2)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>5'd16))>>4'd8));
assign hprpin184710 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp2>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd48))>>4'd8));
endmodule | module EthernetEcho( input [63:0] s_axis_tdata,
input [7:0] s_axis_tkeep,
input s_axis_tlast,
input s_axis_tvalid,
output reg s_axis_tready,
input [63:0] s_axis_tuser_hi,
input [63:0] s_axis_tuser_low,
output reg [63:0] m_axis_tdata,
output reg [7:0] m_axis_tkeep,
output reg m_axis_tlast,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tuser_hi,
output reg [63:0] m_axis_tuser_low,
input cam_busy,
input cam_match,
input [7:0] cam_match_addr,
output reg [63:0] cam_cmp_din,
output reg [63:0] cam_din,
output reg cam_we,
output reg [7:0] cam_wr_addr,
input clk,
input reset); |
reg LoEthernetEcho_IPv4;
reg LoEthernetEcho_proto_UDP;
reg LoEthernetEcho_proto_ICMP;
reg [7:0] LoEthernetEcho_last_tkeep;
reg LoEthernetEcho_exist_rest;
reg [63:0] LoEthernetEcho_chksum_UDP;
reg [63:0] LoEthernetEcho_chksumIP;
reg [63:0] TLEsw1_1_V_2;
reg [63:0] TLEsw1_1_V_3;
reg [31:0] TLEsw1_1_V_4;
reg [31:0] TLEsw1_1_V_5;
reg [31:0] TLEsw1_1_V_9;
reg [31:0] TLEsw1_1_V_10;
reg TLEsw1_1_V_11;
reg TLEsw1_1_V_12;
reg TLEsw1_1_V_13;
reg [31:0] TLERe1_1_V_0;
reg [31:0] TLERe1_1_V_1;
reg TLERe1_1_V_3;
reg [63:0] TLERe1_1_V_5;
reg [7:0] TLERe1_1_V_6;
reg [7:0] TLEca6_0_V_0;
reg [63:0] TLEca6_0_V_1;
reg [63:0] TLEca6_0_V_6;
reg [63:0] TLEca6_0_V_7;
reg [63:0] TLEca6_0_V_12;
reg [63:0] TLEsw9_10_V_0;
reg TLEsw9_10_V_1;
reg TLEsw9_10_V_2;
reg [7:0] TLEca27_14_V_0;
reg [63:0] TLEca27_14_V_1;
reg [63:0] TLEca27_14_V_6;
reg [63:0] TLEca27_14_V_7;
reg [63:0] TLEca27_14_V_12;
reg [63:0] TLEca31_5_V_4;
reg [63:0] TLEca31_5_V_5;
reg [63:0] TLEca31_5_V_7;
reg [63:0] TLEca33_17_V_4;
reg [63:0] TLEca33_17_V_5;
reg [63:0] TLEca33_17_V_7;
reg [63:0] TLEca33_20_V_4;
reg [63:0] TLEca33_20_V_5;
reg [63:0] TLEca33_20_V_7;
reg [31:0] TLESe34_3_V_0;
reg [31:0] TLESe34_3_V_1;
reg LoEthernetEcho_one_question;
reg LoEthernetEcho_std_query;
reg [63:0] LoEthernetEcho_dst_mac;
reg [63:0] LoEthernetEcho_src_mac;
reg [63:0] LoEthernetEcho_dst_ip;
reg [63:0] LoEthernetEcho_src_ip;
reg [63:0] LoEthernetEcho_app_src_port;
reg [63:0] LoEthernetEcho_app_dst_port;
reg [63:0] LoEthernetEcho_tmp;
reg [63:0] LoEthernetEcho_tmp1;
reg [63:0] LoEthernetEcho_tmp2;
reg [63:0] LoEthernetEcho_tmp3;
reg [63:0] LoEthernetEcho_tmp4;
reg [63:0] LoEthernetEcho_tmp5;
reg LoEthernetEcho_start_parsing;
reg [63:0] LoEthernetEcho_IP_total_length;
reg [63:0] LoEthernetEcho_UDP_total_length;
reg [63:0] LoEthernetEcho_src_port;
reg [7:0] A_8_US_CC_SCALbx24_ARA0[63:0];
reg [31:0] A_UINT_CC_SCALbx22_ARA0[6:0];
reg [63:0] A_64_US_CC_SCALbx10_ARA0[63:0];
reg [63:0] A_64_US_CC_SCALbx12_ARB0[63:0];
reg [63:0] A_64_US_CC_SCALbx14_ARC0[63:0];
reg [63:0] A_64_US_CC_SCALbx16_ARD0[6:0];
reg [63:0] A_64_US_CC_SCALbx18_ARE0[6:0];
reg [63:0] A_64_US_CC_SCALbx20_ARF0[6:0];
reg [5:0] xpc10;
wire [63:0] hprpin161810;
wire [63:0] hprpin162310;
wire [63:0] hprpin176810;
wire [63:0] hprpin177310;
wire [63:0] hprpin182110;
wire [63:0] hprpin182610;
wire [63:0] hprpin184210;
wire [63:0] hprpin184710;
always @(posedge clk ) begin
if (reset) begin
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 64'd0;
cam_cmp_din <= 64'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 64'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
LoEthernetEcho_last_tkeep <= 8'd0;
TLERe1_1_V_0 <= 32'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEsw1_1_V_11 <= 1'd0;
TLEca6_0_V_7 <= 64'd0;
TLEca6_0_V_6 <= 64'd0;
TLEsw9_10_V_2 <= 1'd0;
TLEsw9_10_V_1 <= 1'd0;
TLEca6_0_V_1 <= 64'd0;
TLEca6_0_V_0 <= 8'd0;
TLEca6_0_V_12 <= 64'd0;
TLEsw9_10_V_0 <= 64'd0;
LoEthernetEcho_tmp4 <= 64'd0;
TLEsw1_1_V_10 <= 32'd0;
TLEsw1_1_V_5 <= 32'd0;
LoEthernetEcho_tmp5 <= 64'd0;
LoEthernetEcho_tmp1 <= 64'd0;
TLEca27_14_V_7 <= 64'd0;
TLEca27_14_V_6 <= 64'd0;
LoEthernetEcho_chksumIP <= 64'd0;
TLEca27_14_V_1 <= 64'd0;
TLEca27_14_V_0 <= 8'd0;
TLEca27_14_V_12 <= 64'd0;
TLEca33_17_V_5 <= 64'd0;
TLEca33_17_V_4 <= 64'd0;
TLEca33_17_V_7 <= 64'd0;
TLEca33_20_V_5 <= 64'd0;
TLEca33_20_V_4 <= 64'd0;
TLEca33_20_V_7 <= 64'd0;
TLESe34_3_V_1 <= 32'd0;
s_axis_tready <= 1'd0;
LoEthernetEcho_exist_rest <= 1'd0;
TLEsw1_1_V_9 <= 32'd0;
m_axis_tvalid <= 1'd0;
TLESe34_3_V_0 <= 32'd0;
m_axis_tuser_low <= 64'd0;
m_axis_tuser_hi <= 64'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 64'd0;
TLEca31_5_V_5 <= 64'd0;
TLEca31_5_V_4 <= 64'd0;
TLEca31_5_V_7 <= 64'd0;
LoEthernetEcho_tmp3 <= 64'd0;
LoEthernetEcho_chksum_UDP <= 64'd0;
LoEthernetEcho_tmp2 <= 64'd0;
LoEthernetEcho_tmp <= 64'd0;
LoEthernetEcho_start_parsing <= 1'd0;
LoEthernetEcho_std_query <= 1'd0;
LoEthernetEcho_one_question <= 1'd0;
LoEthernetEcho_UDP_total_length <= 64'd0;
LoEthernetEcho_app_dst_port <= 64'd0;
LoEthernetEcho_app_src_port <= 64'd0;
LoEthernetEcho_dst_ip <= 64'd0;
LoEthernetEcho_src_ip <= 64'd0;
LoEthernetEcho_IP_total_length <= 64'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
xpc10 <= 6'd0;
TLEsw1_1_V_3 <= 64'd0;
TLEsw1_1_V_2 <= 64'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_src_port <= 64'd0;
LoEthernetEcho_src_mac <= 64'd0;
LoEthernetEcho_dst_mac <= 64'd0;
end
else begin
case (xpc10)
0: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEsw1_1_V_11 <= 1'd0;
TLEsw1_1_V_10 <= 32'd0;
TLEsw1_1_V_9 <= 32'd0;
TLEsw1_1_V_5 <= 32'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_chksumIP <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_exist_rest <= 1'd0;
LoEthernetEcho_last_tkeep <= 8'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 32'd0;
cam_cmp_din <= 32'h_ffff_ffff;
A_UINT_CC_SCALbx22_ARA0[3'd6] <= 32'h600_a8c0;
A_UINT_CC_SCALbx22_ARA0[3'd5] <= 32'h500_a8c0;
A_UINT_CC_SCALbx22_ARA0[3'd4] <= 32'h400_a8c0;
A_UINT_CC_SCALbx22_ARA0[2'd3] <= 32'h300_a8c0;
A_UINT_CC_SCALbx22_ARA0[2'd2] <= 32'h200_a8c0;
A_UINT_CC_SCALbx22_ARA0[1'd1] <= 32'h100_a8c0;
A_UINT_CC_SCALbx22_ARA0[0] <= 32'h_a8c0;
A_64_US_CC_SCALbx16_ARD0[3'd6] <= 64'h1_0000_6772_6f03;
A_64_US_CC_SCALbx16_ARD0[3'd5] <= 64'd0;
A_64_US_CC_SCALbx16_ARD0[3'd4] <= 64'h1_0001_0000_6b75;
A_64_US_CC_SCALbx16_ARD0[2'd3] <= 64'h1_0000_6d6f_6303;
A_64_US_CC_SCALbx16_ARD0[2'd2] <= 64'h100_0100;
A_64_US_CC_SCALbx16_ARD0[1'd1] <= 64'h100_0100;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'd256;
A_64_US_CC_SCALbx18_ARE0[3'd6] <= 64'h_6566_696c_646c_6977;
A_64_US_CC_SCALbx18_ARE0[3'd5] <= 64'h1_0100;
A_64_US_CC_SCALbx18_ARE0[3'd4] <= 64'h263_6f02_6567_6469;
A_64_US_CC_SCALbx18_ARE0[2'd3] <= 64'h_6563_6976_7265_736e;
A_64_US_CC_SCALbx18_ARE0[2'd2] <= 64'h6b_7502_6361_026d;
A_64_US_CC_SCALbx18_ARE0[1'd1] <= 64'h6d_6f63_036b_6f6f;
A_64_US_CC_SCALbx18_ARE0[0] <= 64'h100_006d_6f63_0365;
A_64_US_CC_SCALbx20_ARF0[3'd6] <= 64'h_646c_726f_770c_7777;
A_64_US_CC_SCALbx20_ARF0[3'd5] <= 64'h_7267_026e_6902_7777;
A_64_US_CC_SCALbx20_ARF0[3'd4] <= 64'h_7262_6d61_6309_7777;
A_64_US_CC_SCALbx20_ARF0[2'd3] <= 64'h_6f64_6e6f_6c0c_7777;
A_64_US_CC_SCALbx20_ARF0[2'd2] <= 64'h_6163_036c_6302_7777;
A_64_US_CC_SCALbx20_ARF0[1'd1] <= 64'h_6265_6361_6608_7777;
A_64_US_CC_SCALbx20_ARF0[0] <= 64'h_6c67_6f6f_6706_7777;
end
1'd1: begin
if (s_axis_tvalid && s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_8_US_CC_SCALbx24_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_8_US_CC_SCALbx24_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!s_axis_tvalid) begin
xpc10 <= 2'd2;
TLERe1_1_V_3 <= 1'd1;
TLERe1_1_V_0 <= 32'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
TLERe1_1_V_1 <= 32'd0;
end
end
2'd2: begin
if (s_axis_tvalid && s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!TLERe1_1_V_3) begin
xpc10 <= 2'd3;
TLERe1_1_V_6 <= A_8_US_CC_SCALbx24_ARA0[8'h1*(32'hffffffff&TLERe1_1_V_1)];
TLERe1_1_V_5 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1];
end
end
2'd3: begin
case (TLERe1_1_V_6)
1'd1: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd1;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'd255&TLERe1_1_V_5;
end
2'd2: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd0;
end
2'd3: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd2;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff&TLERe1_1_V_5;
end
3'd7: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd3;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff&TLERe1_1_V_5;
end
4'd15: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&32'h_ffff_ffff&TLERe1_1_V_5
;
end
5'd31: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd5;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff&TLERe1_1_V_5
;
end
6'd63: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd6;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff_ffff_ffff&TLERe1_1_V_5
;
end
7'd127: begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd7;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff_ffff&TLERe1_1_V_5
;
end
endcase
if ((TLERe1_1_V_6!=3'd7) && (TLERe1_1_V_6!=4'd15) && (TLERe1_1_V_6!=5'd31) && (TLERe1_1_V_6
!=6'd63) && (TLERe1_1_V_6!=7'd127) && (TLERe1_1_V_6!=1'd1) && (TLERe1_1_V_6!=2'd2) &&
(TLERe1_1_V_6!=2'd3)) begin
xpc10 <= 3'd4;
LoEthernetEcho_last_tkeep <= 8'd0;
end
end
3'd4: if (((32'hffffffff&TLERe1_1_V_1)<32'd0)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_9 <= TLERe1_1_V_1;
TLERe1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
else begin
xpc10 <= 6'd51;
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'd0];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_9 <= TLERe1_1_V_1;
TLERe1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
4'd8: begin
if (LoEthernetEcho_one_question && LoEthernetEcho_std_query && (3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && 1'h1&(0==
(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16))))) begin
xpc10 <= 4'd9;
TLEsw9_10_V_2 <= 1'h1&TLEsw1_1_V_13;
TLEsw9_10_V_1 <= 1'h1&TLEsw1_1_V_12;
LoEthernetEcho_exist_rest <= 1'd0;
LoEthernetEcho_chksumIP <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
A_64_US_CC_SCALbx14_ARC0[0] <= 64'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48'd0
};
end
if ((2'd2==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (1'd1!=(8'hff&8'd1+TLEca6_0_V_0)) && (2'd2!=(8'hff
&8'd1+TLEca6_0_V_0)) && (2'd3!=(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= 32'd0;
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((2'd3==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (3'd4==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64'd4], 48'd0};
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((1'd1==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && !(1'h1&(0==(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff
^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6
+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6
+TLEca6_0_V_7>>5'd16))>>5'd16)))))) begin
xpc10 <= 6'd41;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
if (!LoEthernetEcho_one_question && (3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && 1'h1&(0==(64'hffffffffffffffff
&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6
+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6
+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16))))) begin
xpc10 <= 6'd41;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
if (LoEthernetEcho_one_question && !LoEthernetEcho_std_query && (3'd4<(8'hff&8'd1+TLEca6_0_V_0)) && 1'h1
&(0==(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16))))) begin
xpc10 <= 6'd41;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
end
5'd18: begin
if ((LoEthernetEcho_tmp!=LoEthernetEcho_tmp1) && ((32'hffffffff&32'd1+TLEsw1_1_V_4)<3'd7)) begin
LoEthernetEcho_tmp4 <= A_64_US_CC_SCALbx14_ARC0[64'd8];
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx16_ARD0[32'hffffffff&32'd1+TLEsw1_1_V_4];
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx18_ARE0[32'hffffffff&32'd1+TLEsw1_1_V_4];
LoEthernetEcho_tmp1 <= A_64_US_CC_SCALbx20_ARF0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_tmp==LoEthernetEcho_tmp1) && (TLEsw1_1_V_9!=4'd9)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_5 <= TLEsw1_1_V_4;
LoEthernetEcho_exist_rest <= 1'h1&(LoEthernetEcho_tmp2==LoEthernetEcho_tmp4);
end
if ((LoEthernetEcho_tmp!=LoEthernetEcho_tmp1) && ((32'hffffffff&32'd1+TLEsw1_1_V_4)>=3'd7)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_tmp==LoEthernetEcho_tmp1) && (TLEsw1_1_V_9==4'd9)) begin
xpc10 <= 5'd19;
LoEthernetEcho_tmp5 <= A_64_US_CC_SCALbx14_ARC0[64'd9];
end
end
5'd31: begin
if ((2'd2==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca27_14_V_0];
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca27_14_V_0)) && (1'd1!=(8'hff&8'd1+TLEca27_14_V_0)) && (2'd2!=
(8'hff&8'd1+TLEca27_14_V_0)) && (2'd3!=(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= 32'd0;
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((2'd3==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca27_14_V_0];
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca27_14_V_0)) && (3'd4==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= {A_64_US_CC_SCALbx14_ARC0[64'd4], 48'd0};
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((1'd1==(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
TLEca27_14_V_12 <= (64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7
)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_6
+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16);
end
if ((3'd4<(8'hff&8'd1+TLEca27_14_V_0))) begin
xpc10 <= 6'd32;
LoEthernetEcho_chksumIP <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16));
TLEca27_14_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16)))+(TLEca27_14_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca27_14_V_6+TLEca27_14_V_7)+(TLEca27_14_V_6+TLEca27_14_V_7>>5'd16))>>5'd16));
TLEca27_14_V_0 <= 8'd1+TLEca27_14_V_0;
end
end
6'd41: begin
if (!m_axis_tready && ((32'hffffffff&TLEsw1_1_V_9)>=32'd0)) begin
xpc10 <= 6'd43;
TLESe34_3_V_1 <= TLEsw1_1_V_9;
TLESe34_3_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
end
if (m_axis_tready && ((32'hffffffff&TLEsw1_1_V_9)>=32'd0)) begin
xpc10 <= 6'd43;
TLESe34_3_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[64'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_9==0);
m_axis_tkeep <= A_8_US_CC_SCALbx24_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLESe34_3_V_1 <= TLEsw1_1_V_9;
m_axis_tvalid <= 1'd1;
end
if (((32'hffffffff&TLEsw1_1_V_9)<32'd0)) begin
xpc10 <= 6'd42;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe34_3_V_1 <= TLEsw1_1_V_9;
TLESe34_3_V_0 <= 32'd0;
end
end
6'd42: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
LoEthernetEcho_exist_rest <= 1'd0;
TLEsw1_1_V_9 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_start_parsing <= 1'd0;
LoEthernetEcho_std_query <= 1'd0;
LoEthernetEcho_one_question <= 1'd0;
end
6'd43: begin
if ((TLESe34_3_V_1<TLESe34_3_V_0)) begin
xpc10 <= 6'd42;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
end
if (m_axis_tready && (TLESe34_3_V_1>=TLESe34_3_V_0)) begin
TLESe34_3_V_0 <= 32'd1+TLESe34_3_V_0;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[64'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_9==TLESe34_3_V_0);
m_axis_tkeep <= A_8_US_CC_SCALbx24_ARA0[8'h1*(32'hffffffff&TLESe34_3_V_0)];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLESe34_3_V_0];
end
end
6'd45: begin
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd35;
LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp3 <= 64'h_1100|(-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4]);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+TLEca31_5_V_5
)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16)))+(TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+
TLEca31_5_V_5)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4==(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd44;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4]>>5'd16);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+TLEca31_5_V_5
)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16)))+(TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+
TLEca31_5_V_5)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4!=(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd44;
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+TLEca31_5_V_5
)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16)))+(TLEca31_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca31_5_V_4+
TLEca31_5_V_5)+(TLEca31_5_V_4+TLEca31_5_V_5>>5'd16))>>5'd16);
end
end
6'd51: begin
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_UDP_total_length <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==0)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_UDP_total_length <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==0)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8!=(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8==(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_std_query <= 1'h1&(0==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd36)));
LoEthernetEcho_one_question <= 1'h1&(1'd1==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56));
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8!=(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) &&
(4'd8==(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_std_query <= 1'h1&(0==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd36)));
LoEthernetEcho_one_question <= 1'h1&(1'd1==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56));
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_start_parsing <= 1'h1&(15'd30467==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48
));
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_start_parsing <= 1'h1&(15'd30467==((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48
));
end
if ((TLEsw1_1_V_9>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)!=0) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((TLEsw1_1_V_9<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)!=0) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6)) begin
xpc10 <= 3'd5;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
end
endcase
if ((LoEthernetEcho_tmp2==LoEthernetEcho_tmp4)) begin if ((xpc10==5'd19)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_5 <= TLEsw1_1_V_4;
LoEthernetEcho_exist_rest <= 1'h1&(LoEthernetEcho_tmp3==LoEthernetEcho_tmp5);
end
end
else if ((xpc10==5'd19)) begin
xpc10 <= 5'd20;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
TLEsw1_1_V_10 <= 64'h_ffff&A_64_US_CC_SCALbx10_ARA0[0];
TLEsw1_1_V_5 <= TLEsw1_1_V_4;
LoEthernetEcho_exist_rest <= 1'd0;
end
case (xpc10)
3'd5: begin
xpc10 <= 3'd6;
TLEsw1_1_V_13 <= 1'h1&LoEthernetEcho_proto_ICMP;
TLEsw1_1_V_12 <= 1'h1&LoEthernetEcho_proto_UDP;
TLEsw1_1_V_11 <= 1'h1&LoEthernetEcho_IPv4;
end
3'd6: begin
if (TLEsw1_1_V_11 && TLEsw1_1_V_12) begin
xpc10 <= 3'd7;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1;
TLEca6_0_V_12 <= 32'd0;
TLEca6_0_V_7 <= 32'd0;
TLEca6_0_V_6 <= 32'd0;
end
if (TLEsw1_1_V_11 && !TLEsw1_1_V_12) xpc10 <= 6'd41;
if (!TLEsw1_1_V_11) xpc10 <= 6'd41;
end
3'd7: begin
xpc10 <= 4'd8;
TLEca6_0_V_7 <= (64'h_ffff&hprpin162310)+(hprpin162310>>5'd16);
TLEca6_0_V_6 <= (64'h_ffff&hprpin161810)+(hprpin161810>>5'd16);
end
4'd9: begin
xpc10 <= 4'd10;
TLEsw9_10_V_0 <= (-64'h1_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd1])|(LoEthernetEcho_dst_mac>>5'd16);
end
4'd10: begin
xpc10 <= 4'd11;
A_64_US_CC_SCALbx14_ARC0[64'd1] <= 64'hffffffffffffffff&TLEsw9_10_V_0;
end
4'd11: begin
xpc10 <= 4'd12;
TLEsw9_10_V_0 <= (64'h_ffff&A_64_US_CC_SCALbx14_ARC0[64'd3])|{LoEthernetEcho_dst_ip, 16'd0}|{LoEthernetEcho_src_ip
, 48'd0};
end
4'd12: begin
xpc10 <= 4'd13;
A_64_US_CC_SCALbx14_ARC0[64'd3] <= 64'hffffffffffffffff&TLEsw9_10_V_0;
end
4'd13: begin
if (!TLEsw9_10_V_1 && TLEsw9_10_V_2) begin
xpc10 <= 4'd14;
TLEsw9_10_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4])|(LoEthernetEcho_src_ip>>5'd16
);
end
if (TLEsw9_10_V_1 && !TLEsw9_10_V_2) begin
xpc10 <= 4'd14;
TLEsw9_10_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4])|(LoEthernetEcho_src_ip>>5'd16
)|{LoEthernetEcho_app_src_port, 32'd0}|{LoEthernetEcho_app_dst_port, 16'd0};
end
if (TLEsw9_10_V_1 && TLEsw9_10_V_2) begin
xpc10 <= 4'd14;
TLEsw9_10_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4])|(LoEthernetEcho_src_ip>>5'd16
);
end
if (!TLEsw9_10_V_1 && !TLEsw9_10_V_2) xpc10 <= 4'd14;
end
4'd14: begin
xpc10 <= 4'd15;
A_64_US_CC_SCALbx14_ARC0[64'd4] <= 64'hffffffffffffffff&TLEsw9_10_V_0;
end
5'd16: begin
xpc10 <= 5'd17;
LoEthernetEcho_tmp <= A_64_US_CC_SCALbx14_ARC0[64'd7];
end
5'd17: begin
xpc10 <= 5'd18;
LoEthernetEcho_tmp4 <= A_64_US_CC_SCALbx14_ARC0[64'd8];
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx16_ARD0[32'd0];
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx18_ARE0[32'd0];
LoEthernetEcho_tmp1 <= A_64_US_CC_SCALbx20_ARF0[32'd0];
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_5 <= 32'd7;
end
5'd20: begin
xpc10 <= 5'd21;
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&64'h80_0000_0000|LoEthernetEcho_tmp;
end
5'd21: begin
if (!LoEthernetEcho_start_parsing) begin
xpc10 <= 6'd50;
LoEthernetEcho_tmp5 <= A_64_US_CC_SCALbx10_ARA0[0];
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&64'h380_0000_0000|LoEthernetEcho_tmp;
end
if (LoEthernetEcho_start_parsing && !LoEthernetEcho_exist_rest) begin
xpc10 <= 6'd50;
LoEthernetEcho_tmp5 <= A_64_US_CC_SCALbx10_ARA0[0];
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&64'h380_0000_0000|LoEthernetEcho_tmp;
end
if (LoEthernetEcho_start_parsing && LoEthernetEcho_exist_rest) begin
xpc10 <= 5'd22;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[3'd6];
end
end
5'd22: begin
xpc10 <= 5'd23;
LoEthernetEcho_tmp2 <= 64'h400_100e|{64'hffffffffffffffff&A_UINT_CC_SCALbx22_ARA0[32'hffffffff&TLEsw1_1_V_5], 32'd0
};
LoEthernetEcho_tmp1 <= 64'h100_0100_0cc0;
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&64'd256|LoEthernetEcho_tmp;
end
5'd23: if (!(!LoEthernetEcho_last_tkeep)) begin
xpc10 <= 6'd46;
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLEsw1_1_V_9]|(64'h100_0100_0cc0<<(6'd63&4'd8
*LoEthernetEcho_last_tkeep));
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&TLEsw1_1_V_9] <= 8'd255;
end
else begin
xpc10 <= 5'd24;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 64'h100_0100_0cc0;
end
5'd24: begin
xpc10 <= 5'd25;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 8'd255;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2;
end
5'd25: begin
xpc10 <= 5'd26;
LoEthernetEcho_tmp2 <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd2];
LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0};
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 8'd255;
end
5'd26: begin
xpc10 <= 5'd27;
LoEthernetEcho_tmp2 <= 64'h_ffff_ffff_ffff&A_64_US_CC_SCALbx14_ARC0[64'd4];
LoEthernetEcho_tmp <= (LoEthernetEcho_UDP_total_length>>4'd8)|{64'd255&LoEthernetEcho_UDP_total_length, 8'd0};
LoEthernetEcho_IP_total_length <= 64'd16+LoEthernetEcho_tmp;
A_64_US_CC_SCALbx14_ARC0[64'd2] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2|((64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp
)>>4'd8)|{64'd255&64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp, 8'd0};
end
5'd27: begin
xpc10 <= 5'd28;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd3];
TLEsw1_1_V_9 <= 32'd2+TLEsw1_1_V_9;
LoEthernetEcho_UDP_total_length <= 64'd16+LoEthernetEcho_tmp;
A_64_US_CC_SCALbx10_ARA0[0] <= 64'hffffffffffffffff&(64'hffffffffffffffff&64'd16+TLEsw1_1_V_10)|{LoEthernetEcho_src_port
, 24'd0}|{LoEthernetEcho_src_port, 16'd0};
A_64_US_CC_SCALbx14_ARC0[64'd4] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2|{((64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp
)>>4'd8)|{64'd255&64'hffffffffffffffff&64'd16+LoEthernetEcho_tmp, 8'd0}, 48'd0};
end
5'd28: begin
xpc10 <= 5'd29;
A_64_US_CC_SCALbx14_ARC0[64'd3] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
5'd29: begin
xpc10 <= 5'd30;
TLEca27_14_V_1 <= (A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd48);
TLEca27_14_V_0 <= 8'd1;
TLEca27_14_V_12 <= 32'd0;
TLEca27_14_V_7 <= 32'd0;
TLEca27_14_V_6 <= 32'd0;
end
5'd30: begin
xpc10 <= 5'd31;
TLEca27_14_V_7 <= (64'h_ffff&hprpin177310)+(hprpin177310>>5'd16);
TLEca27_14_V_6 <= (64'h_ffff&hprpin176810)+(hprpin176810>>5'd16);
end
6'd32: begin
xpc10 <= 6'd33;
A_64_US_CC_SCALbx14_ARC0[64'd3] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|(LoEthernetEcho_chksumIP>>4'd8)|{64'd255
&LoEthernetEcho_chksumIP, 8'd0};
end
6'd33: begin
xpc10 <= 6'd34;
LoEthernetEcho_tmp <= A_64_US_CC_SCALbx14_ARC0[3'd5];
end
6'd34: if ((TLEsw1_1_V_9<32'd4)) begin
xpc10 <= 6'd35;
LoEthernetEcho_tmp2 <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp3 <= 64'h_1100|(-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[64'd4]);
TLEsw1_1_V_4 <= 32'd4;
end
else begin
xpc10 <= 6'd44;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'd4]>>5'd16);
TLEsw1_1_V_4 <= 32'd4;
end
6'd35: begin
xpc10 <= 6'd36;
TLEca33_17_V_5 <= (64'h_ffff&hprpin182610)+(hprpin182610>>5'd16);
TLEca33_17_V_4 <= (64'h_ffff&hprpin182110)+(hprpin182110>>5'd16);
TLEca33_17_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd36: begin
xpc10 <= 6'd37;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca33_17_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_17_V_4+TLEca33_17_V_5
)+(TLEca33_17_V_4+TLEca33_17_V_5>>5'd16)))+(TLEca33_17_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_17_V_4+TLEca33_17_V_5
)+(TLEca33_17_V_4+TLEca33_17_V_5>>5'd16))>>5'd16);
end
6'd37: begin
xpc10 <= 6'd38;
TLEca33_20_V_5 <= (64'h_ffff&hprpin184710)+(hprpin184710>>5'd16);
TLEca33_20_V_4 <= (64'h_ffff&hprpin184210)+(hprpin184210>>5'd16);
TLEca33_20_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd38: begin
xpc10 <= 6'd39;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca33_20_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_20_V_4+TLEca33_20_V_5
)+(TLEca33_20_V_4+TLEca33_20_V_5>>5'd16)))+(TLEca33_20_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca33_20_V_4+TLEca33_20_V_5
)+(TLEca33_20_V_4+TLEca33_20_V_5>>5'd16))>>5'd16);
end
6'd39: begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= 64'h_ffff&32'h_ffff_ffff^LoEthernetEcho_chksum_UDP;
end
6'd40: begin
xpc10 <= 6'd41;
LoEthernetEcho_tmp3 <= {64'd255&LoEthernetEcho_tmp2, 8'd0}|(LoEthernetEcho_tmp2>>4'd8);
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|(64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp2
, 8'd0}|(LoEthernetEcho_tmp2>>4'd8));
end
6'd44: begin
xpc10 <= 6'd45;
TLEca31_5_V_5 <= (64'h_ffff&hprpin184710)+(hprpin184710>>5'd16);
TLEca31_5_V_4 <= (64'h_ffff&hprpin184210)+(hprpin184210>>5'd16);
TLEca31_5_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd46: begin
xpc10 <= 6'd47;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLEsw1_1_V_9] <= 64'hffffffffffffffff&LoEthernetEcho_tmp3;
end
6'd47: begin
xpc10 <= 6'd48;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 8'd255;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_9] <= 64'hffffffffffffffff&(64'h100_0100_0cc0>>(6'd63&4'd8
*(4'd8+(0-LoEthernetEcho_last_tkeep))))|(LoEthernetEcho_tmp2<<(6'd63&4'd8*LoEthernetEcho_last_tkeep));
end
6'd48: begin
xpc10 <= 6'd49;
A_8_US_CC_SCALbx24_ARA0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 8'hff&(8'd255>>>(5'd31&4'd8+(0-LoEthernetEcho_last_tkeep
)));
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd2+TLEsw1_1_V_9] <= 64'hffffffffffffffff&(LoEthernetEcho_tmp2>>(6'd63
&4'd8*(4'd8+(0-LoEthernetEcho_last_tkeep))));
end
6'd49: begin
xpc10 <= 5'd26;
LoEthernetEcho_tmp2 <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd2];
LoEthernetEcho_tmp <= (LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0};
end
6'd50: begin
xpc10 <= 5'd28;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx14_ARC0[64'd3];
A_64_US_CC_SCALbx10_ARA0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp5|{LoEthernetEcho_src_port, 24'd0};
end
endcase
if ((xpc10==4'd15)) xpc10 <= 5'd16;
end
end
assign hprpin161810 = (64'hffffffffffffffff&{64'd255&TLEca6_0_V_1, 8'd0}|((64'h_ff00&TLEca6_0_V_1)>>4'd8))+(64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>5'd16
), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>5'd16))>>4'd8));
assign hprpin162310 = (64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>6'd32), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd32))>>4'd8))+(64'hffffffffffffffff&{64'd255
&(TLEca6_0_V_1>>6'd48), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd48))>>4'd8));
assign hprpin176810 = (64'hffffffffffffffff&{64'd255&TLEca27_14_V_1, 8'd0}|((64'h_ff00&TLEca27_14_V_1)>>4'd8))+(64'hffffffffffffffff&{64'd255&(TLEca27_14_V_1
>>5'd16), 8'd0}|((64'h_ff00&(TLEca27_14_V_1>>5'd16))>>4'd8));
assign hprpin177310 = (64'hffffffffffffffff&{64'd255&(TLEca27_14_V_1>>6'd32), 8'd0}|((64'h_ff00&(TLEca27_14_V_1>>6'd32))>>4'd8))+(64'hffffffffffffffff&{64'd255
&(TLEca27_14_V_1>>6'd48), 8'd0}|((64'h_ff00&(TLEca27_14_V_1>>6'd48))>>4'd8));
assign hprpin182110 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp3, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp3)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp3
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp3>>5'd16))>>4'd8));
assign hprpin182610 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp3>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp3>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp3>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp3>>6'd48))>>4'd8));
assign hprpin184210 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp2, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp2)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>5'd16))>>4'd8));
assign hprpin184710 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp2>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd48))>>4'd8));
endmodule | 3 |
142,105 | data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v | 97,045,669 | Reference_Switch_Lite_Middlebox.v | v | 691 | 211 | [] | [] | [] | null | line:105 column:38: Illegal character "'" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:92: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n xpc10 <= 1\'d1 ;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:94: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:95: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:98: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:105: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n cam_cmp_din <= 32\'h_ffff_ffff;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:114: Bit extraction of array[15:0] requires 4 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[3\'d7] <= 64\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:115: Bit extraction of array[15:0] requires 4 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[3\'d6] <= 64\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:116: Bit extraction of array[15:0] requires 4 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[3\'d5] <= 64\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:117: Bit extraction of array[15:0] requires 4 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[3\'d4] <= 64\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:118: Bit extraction of array[15:0] requires 4 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[2\'d3] <= 64\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:119: Bit extraction of array[15:0] requires 4 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[2\'d2] <= 64\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:120: Bit extraction of array[15:0] requires 4 bit index, not 1 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx16_ARD0[1\'d1] <= 64\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:126: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:139: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:152: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:170: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&s_axis_tdata, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:170: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&s_axis_tdata, 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:161: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==3\'d5 )) \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:161: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==3\'d5 )) \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:185: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&s_axis_tdata, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:185: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&s_axis_tdata, 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:176: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:177: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n ==3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:191: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:192: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ==3\'d4 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:204: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:205: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ==3\'d4 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:224: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_UDP <= 1\'h1&(5\'d17 ==(64\'d255&(s_axis_tdata>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:217: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n ==2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:237: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_UDP <= 1\'h1&(5\'d17 ==(64\'d255&(s_axis_tdata>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:230: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:231: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n ==2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:243: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:244: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ==1\'d1 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:256: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:257: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ==1\'d1 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:269: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:270: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n !=1\'d1 ) && (LoEthernetEcho_segm_num!=2\'d2 ) && (LoEthernetEcho_segm_num!=2\'d3 ) && (LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:270: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n !=1\'d1 ) && (LoEthernetEcho_segm_num!=2\'d2 ) && (LoEthernetEcho_segm_num!=2\'d3 ) && (LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:270: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n !=1\'d1 ) && (LoEthernetEcho_segm_num!=2\'d2 ) && (LoEthernetEcho_segm_num!=2\'d3 ) && (LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:271: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n !=3\'d4 ) && (LoEthernetEcho_segm_num!=3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:271: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n !=3\'d4 ) && (LoEthernetEcho_segm_num!=3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:282: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:283: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n !=1\'d1 ) && (LoEthernetEcho_segm_num!=2\'d2 ) && (LoEthernetEcho_segm_num!=2\'d3 ) && (LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:283: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n !=1\'d1 ) && (LoEthernetEcho_segm_num!=2\'d2 ) && (LoEthernetEcho_segm_num!=2\'d3 ) && (LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:283: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n !=1\'d1 ) && (LoEthernetEcho_segm_num!=2\'d2 ) && (LoEthernetEcho_segm_num!=2\'d3 ) && (LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:284: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n !=3\'d4 ) && (LoEthernetEcho_segm_num!=3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:284: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n !=3\'d4 ) && (LoEthernetEcho_segm_num!=3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:295: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && (4\'d8 !=(64\'h_ffff&(s_axis_tdata>>6\'d32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:295: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && (4\'d8 !=(64\'h_ffff&(s_axis_tdata>>6\'d32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:296: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n ) && (LoEthernetEcho_segm_num==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:307: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && (4\'d8 !=(64\'h_ffff&(s_axis_tdata>>6\'d32))) && !s_axis_tlast && TLERe1_3_V_3 && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:308: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2\'d2 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:308: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:319: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && (4\'d8 ==(64\'h_ffff&(s_axis_tdata>>6\'d32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:319: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && (4\'d8 ==(64\'h_ffff&(s_axis_tdata>>6\'d32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:320: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n ) && (LoEthernetEcho_segm_num==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:331: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && (4\'d8 ==(64\'h_ffff&(s_axis_tdata>>6\'d32))) && !s_axis_tlast && TLERe1_3_V_3 && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:332: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2\'d2 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:332: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:343: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !LoEthernetEcho_segm_num) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:354: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_segm_num\' generates 32 bits.\n : ... In instance EthernetEcho\n if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !LoEthernetEcho_segm_num) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:366: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:374: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:378: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_broadcast_ports <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|{((64\'h55_0000^A_64_US_CC_SCALbx10_ARA0[64\'d0])>>\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:378: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_broadcast_ports <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|{((64\'h55_0000^A_64_US_CC_SCALbx10_ARA0[64\'d0])>>\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:378: Operator OR expects 80 bits on the LHS, but LHS\'s ARRAYSEL generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_broadcast_ports <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|{((64\'h55_0000^A_64_US_CC_SCALbx10_ARA0[64\'d0])>>\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:378: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_broadcast_ports <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|{((64\'h55_0000^A_64_US_CC_SCALbx10_ARA0[64\'d0])>>\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:381: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_mac <= {A_64_US_CC_SCALbx14_ARC0[64\'d0], 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:381: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_mac <= {A_64_US_CC_SCALbx14_ARC0[64\'d0], 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:386: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d16 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:387: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|(64\'hffffffffffffffff&{LoEthernetEcho_tmp2, 24\'d0});\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:387: Operator OR expects 88 bits on the LHS, but LHS\'s ARRAYSEL generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|(64\'hffffffffffffffff&{LoEthernetEcho_tmp2, 24\'d0});\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:387: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|(64\'hffffffffffffffff&{LoEthernetEcho_tmp2, 24\'d0});\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:387: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 88 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= A_64_US_CC_SCALbx10_ARA0[64\'d0]|(64\'hffffffffffffffff&{LoEthernetEcho_tmp2, 24\'d0});\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:389: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 88 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_OQ <= {LoEthernetEcho_tmp2, 24\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:391: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0)<64\'d16)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:391: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0)<64\'d16)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:391: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0)<64\'d16)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:398: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d16 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:399: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_broadcast_ports|A_64_US_CC_SCALbx10_ARA0[64\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:396: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && !LoEthernetEcho_LUT_hit && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:396: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && !LoEthernetEcho_LUT_hit && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:396: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && !LoEthernetEcho_LUT_hit && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:404: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d16 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:405: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_OQ|A_64_US_CC_SCALbx10_ARA0[64\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:402: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && LoEthernetEcho_LUT_hit && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:402: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && LoEthernetEcho_LUT_hit && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:402: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && LoEthernetEcho_LUT_hit && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:413: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:414: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[64\'d0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:411: Operator NEQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:412: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:411: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:412: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:412: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:412: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:412: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:419: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:420: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[64\'d0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:416: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}<64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:416: Operator LT expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}<64\'h_1e00_0000_0000_0000\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:417: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:417: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:417: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:417: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:417: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:417: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:425: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:426: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[64\'d0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:422: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:422: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:423: Operator LT expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:424: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:423: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:424: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:424: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:424: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:424: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:432: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:433: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[64\'d0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:428: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:428: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:429: Operator GTE expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}<64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:429: Operator LT expects 112 bits on the RHS, but RHS\'s CONST \'64\'h3200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}<64\'h_3200_0000_0000_0000\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:430: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:430: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:430: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:430: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:430: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:430: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:439: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:440: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[64\'d0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:435: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:435: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:436: Operator GTE expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}>=64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:436: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h3200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}>=64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:437: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&1\'h1&LoEthernetEcho_proto_UDP&1\'h1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:437: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 ==(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&1\'h1&LoEthernetEcho_proto_UDP&1\'h1\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:438: Operator LT expects 80 bits on the LHS, but LHS\'s CONST \'64\'h3400000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n &(0 ==(64\'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16\'d0}))) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:445: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n &(0 ==(64\'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16\'d0}))) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:442: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:442: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:443: Operator GTE expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}>=64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:443: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h3200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}>=64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:444: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&1\'h1&LoEthernetEcho_proto_UDP&1\'h1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:444: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&1\'h1&LoEthernetEcho_proto_UDP&1\'h1\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:445: Operator LT expects 80 bits on the LHS, but LHS\'s CONST \'64\'h3400000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n &(0 ==(64\'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16\'d0}))) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:449: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n })))) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:446: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:446: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:447: Operator GTE expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}>=64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:447: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h3200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}>=64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:448: Operator LT expects 80 bits on the LHS, but LHS\'s CONST \'64\'h3400000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&1\'h1&LoEthernetEcho_proto_UDP&1\'h1&(0 ==(64\'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:453: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n ) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:450: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:450: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:451: Operator GTE expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}<64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:451: Operator LT expects 112 bits on the RHS, but RHS\'s CONST \'64\'h3200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}<64\'h_3200_0000_0000_0000\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:452: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:452: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:452: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:452: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:452: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:452: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:456: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:454: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:454: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:455: Operator GTE expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}<64\'h_3200_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:455: Operator LT expects 112 bits on the RHS, but RHS\'s CONST \'64\'h3200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16\'d0}) && ({LoEthernetEcho_app_dst_port, 48\'d0}<64\'h_3200_0000_0000_0000\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:456: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:456: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:456: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:456: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:459: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:457: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:457: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:458: Operator LT expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:459: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:458: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:459: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:459: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:459: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:459: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:462: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n ) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:460: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:460: Operator GTE expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}>=64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:461: Operator LT expects 80 bits on the LHS, but LHS\'s CONST \'64\'h2200000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:461: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:461: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:461: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:461: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n ) && (64\'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:465: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n ) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:463: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}<64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:463: Operator LT expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}<64\'h_1e00_0000_0000_0000\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:464: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:464: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:464: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:464: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:464: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:464: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n ) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:467: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:466: Operator EQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}<64\'h_1e00_0000_0000_0000\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:466: Operator LT expects 112 bits on the RHS, but RHS\'s CONST \'64\'h1e00000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32\'d0}) && ({LoEthernetEcho_app_src_port, 48\'d0}<64\'h_1e00_0000_0000_0000\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:467: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:467: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:467: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:467: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n ) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:469: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:468: Operator NEQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:469: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:468: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && (4\'d8 !=(64\'h_ffff&(A_64_US_CC_SCALbx14_ARC0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:469: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:469: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:469: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:469: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n [64\'d1]>>6\'d32))) && 1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:471: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n <= 6\'d32 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:470: Operator NEQ expects 96 bits on the LHS, but LHS\'s CONST \'64\'h404afc000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:470: Operator AND expects 32 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:470: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:470: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_proto_UDP\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:470: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s AND generates 32 bits.\n : ... In instance EthernetEcho\n if ((64\'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32\'d0}) && !(1\'h1&32\'d0&1\'h1&LoEthernetEcho_proto_UDP)) xpc10\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:476: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h40\' generates 7 bits.\n : ... In instance EthernetEcho\n xpc10 <= 7\'d64 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:477: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (64\'d255&(A_64_US_CC_SCALbx10_ARA0[64\'d0]>>5\'d16))|{(A_64_US_CC_SCALbx14_ARC0[64\'d0]>>6\'d48), 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:477: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (64\'d255&(A_64_US_CC_SCALbx10_ARA0[64\'d0]>>5\'d16))|{(A_64_US_CC_SCALbx14_ARC0[64\'d0]>>6\'d48), 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:477: Operator AND expects 80 bits on the LHS, but LHS\'s CONST \'64\'hff\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (64\'d255&(A_64_US_CC_SCALbx10_ARA0[64\'d0]>>5\'d16))|{(A_64_US_CC_SCALbx14_ARC0[64\'d0]>>6\'d48), 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:477: Operator SHIFTR expects 80 bits on the LHS, but LHS\'s ARRAYSEL generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (64\'d255&(A_64_US_CC_SCALbx10_ARA0[64\'d0]>>5\'d16))|{(A_64_US_CC_SCALbx14_ARC0[64\'d0]>>6\'d48), 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:477: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= (64\'d255&(A_64_US_CC_SCALbx10_ARA0[64\'d0]>>5\'d16))|{(A_64_US_CC_SCALbx14_ARC0[64\'d0]>>6\'d48), 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:486: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:487: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:489: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:492: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:492: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:492: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:500: Bit extraction of array[29:0] requires 5 bit index, not 8 bits.\n : ... In instance EthernetEcho\n m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:503: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:503: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:503: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:506: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h100\' generates 9 bits.\n : ... In instance EthernetEcho\n xpc10 <= 9\'d256 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:507: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:508: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:510: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:514: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:514: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:514: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:517: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h80\' generates 8 bits.\n : ... In instance EthernetEcho\n xpc10 <= 8\'d128 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:520: Bit extraction of array[29:0] requires 5 bit index, not 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:520: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:520: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64\'d1], 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:529: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:530: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:532: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:526: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:526: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:526: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:545: Bit extraction of array[29:0] requires 5 bit index, not 8 bits.\n : ... In instance EthernetEcho\n m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:539: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:539: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:539: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:553: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h100\' generates 9 bits.\n : ... In instance EthernetEcho\n xpc10 <= 9\'d256 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:554: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:555: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:557: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:551: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n if (!TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:551: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n if (!TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:551: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n if (!TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:568: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:569: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:571: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:565: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:565: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:565: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:583: Bit extraction of array[29:0] requires 5 bit index, not 8 bits.\n : ... In instance EthernetEcho\n m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:577: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:577: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:577: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:590: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h100\' generates 9 bits.\n : ... In instance EthernetEcho\n xpc10 <= 9\'d256 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:591: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:592: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:594: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:588: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n if (TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:588: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n if (TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:588: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n if (TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:604: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:605: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:607: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:619: Bit extraction of array[29:0] requires 5 bit index, not 8 bits.\n : ... In instance EthernetEcho\n m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8\'d0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:625: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h100\' generates 9 bits.\n : ... In instance EthernetEcho\n xpc10 <= 9\'d256 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:626: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:627: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:629: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:635: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0)<64\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:635: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0)<64\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:635: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_0\' generates 32 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32\'hffffffff&32\'d1+TLEsw1_1_V_0)<64\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:640: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n xpc10 <= 1\'d1 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:642: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:643: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:646: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:653: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h100\' generates 9 bits.\n : ... In instance EthernetEcho\n xpc10 <= 9\'d256 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:654: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:655: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:657: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'7\'h40\' generates 7 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'8\'h80\' generates 8 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:90: Operator CASE expects 32 or 10 bits on the Case Item, but Case Item\'s CONST \'9\'h100\' generates 9 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:483: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (LoEthernetEcho_LUT_hit && !m_axis_tready && (TLEsw1_1_V_2>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:494: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (LoEthernetEcho_LUT_hit && m_axis_tready && (TLEsw1_1_V_2>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:505: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (LoEthernetEcho_LUT_hit && (TLEsw1_1_V_2<32\'d0)) begin \n ^\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:526: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:539: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:552: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n )>=64\'d16) && (TLEsw1_1_V_2<32\'d0)) begin \n ^\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:565: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:577: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_0)>=64\'d16) && (TLEsw1_1_V_2>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:589: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n )>=64\'d16) && (TLEsw1_1_V_2<32\'d0)) begin \n ^\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:600: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (!m_axis_tready && (LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2>=32\'d0)) \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:612: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (m_axis_tready && (LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2>=32\'d0)) \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/Reference_Switch_Lite_Middlebox.v:624: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2<32\'d0)) begin \n ^\n%Error: Exiting due to 324 warning(s)\n' | 313,046 | module | module EthernetEcho( input [63:0] s_axis_tdata,
input [7:0] s_axis_tkeep,
input s_axis_tlast,
input s_axis_tvalid,
output reg s_axis_tready,
input [63:0] s_axis_tuser_hi,
input [63:0] s_axis_tuser_low,
output reg [63:0] m_axis_tdata,
output reg [7:0] m_axis_tkeep,
output reg m_axis_tlast,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tuser_hi,
output reg [63:0] m_axis_tuser_low,
input cam_busy,
input cam_match,
input [7:0] cam_match_addr,
output reg [63:0] cam_cmp_din,
output [63:0] cam_din,
output cam_we,
output [7:0] cam_wr_addr,
input clk,
input reset);
reg LoEthernetEcho_proto_UDP;
reg LoEthernetEcho_LUT_hit;
integer TLEsw1_1_V_0;
reg [31:0] TLEsw1_1_V_2;
reg TLEsw1_1_V_3;
reg [31:0] TLERe1_3_V_0;
reg [31:0] TLERe1_3_V_1;
reg TLERe1_3_V_3;
reg [31:0] TLESe23_2_V_0;
reg [31:0] LoEthernetEcho_segm_num;
reg [63:0] LoEthernetEcho_dst_mac;
reg [63:0] LoEthernetEcho_broadcast_ports;
reg [63:0] LoEthernetEcho_tmp;
reg [63:0] LoEthernetEcho_tmp2;
reg [63:0] LoEthernetEcho_OQ;
reg [63:0] LoEthernetEcho_dst_ip;
reg [63:0] LoEthernetEcho_app_src_port;
reg [63:0] LoEthernetEcho_app_dst_port;
reg [7:0] A_8_US_CC_SCALbx18_ARA0[29:0];
reg [63:0] A_64_US_CC_SCALbx10_ARA0[29:0];
reg [63:0] A_64_US_CC_SCALbx12_ARB0[29:0];
reg [63:0] A_64_US_CC_SCALbx14_ARC0[29:0];
reg [63:0] A_64_US_CC_SCALbx16_ARD0[15:0];
reg [9:0] xpc10;
always @(posedge clk ) begin
if (reset) begin
cam_cmp_din <= 64'd0;
TLEsw1_1_V_2 <= 32'd0;
LoEthernetEcho_app_dst_port <= 64'd0;
LoEthernetEcho_app_src_port <= 64'd0;
LoEthernetEcho_dst_ip <= 64'd0;
TLERe1_3_V_3 <= 1'd0;
TLERe1_3_V_1 <= 32'd0;
TLERe1_3_V_0 <= 32'd0;
LoEthernetEcho_broadcast_ports <= 64'd0;
LoEthernetEcho_dst_mac <= 64'd0;
LoEthernetEcho_OQ <= 64'd0;
LoEthernetEcho_tmp2 <= 64'd0;
LoEthernetEcho_LUT_hit <= 1'd0;
LoEthernetEcho_tmp <= 64'd0;
TLEsw1_1_V_3 <= 1'd0;
TLEsw1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
LoEthernetEcho_segm_num <= 32'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
xpc10 <= 10'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 64'd0;
m_axis_tuser_hi <= 64'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 64'd0;
end
else
case (xpc10)
0: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
LoEthernetEcho_segm_num <= 32'd0;
TLEsw1_1_V_3 <= 1'd0;
TLEsw1_1_V_2 <= 32'd0;
TLEsw1_1_V_0 <= 32'd0;
LoEthernetEcho_LUT_hit <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
cam_cmp_din <= 32'h_ffff_ffff;
A_64_US_CC_SCALbx16_ARD0[4'd15] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd14] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd13] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd12] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd11] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd10] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd9] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd8] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd7] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd6] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd5] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd4] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[2'd3] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[2'd2] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[1'd1] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'd1;
end
1'd1: begin
if (s_axis_tvalid && s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd2;
TLERe1_3_V_1 <= 32'd0;
TLERe1_3_V_0 <= 32'd1;
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd2;
TLERe1_3_V_1 <= 32'd0;
TLERe1_3_V_0 <= 32'd1;
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!s_axis_tvalid) begin
xpc10 <= 2'd2;
TLERe1_3_V_3 <= 1'd1;
LoEthernetEcho_segm_num <= 32'd1;
TLERe1_3_V_0 <= 32'd0;
TLERe1_3_V_1 <= 32'd0;
end
end
2'd2: begin
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==3'd5))
begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_app_dst_port <= 64'h_ffff&(s_axis_tdata>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&(s_axis_tdata>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&s_axis_tdata, 16'd0};
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==3'd5)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_app_dst_port <= 64'h_ffff&(s_axis_tdata>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&(s_axis_tdata>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&s_axis_tdata, 16'd0};
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==3'd4)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_ip <= 64'h_ffff&(s_axis_tdata>>6'd48);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==3'd4)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_ip <= 64'h_ffff&(s_axis_tdata>>6'd48);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==2'd3)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&(s_axis_tdata>>6'd56)));
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==2'd3)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&(s_axis_tdata>>6'd56)));
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==1'd1)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==1'd1)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
!=1'd1) && (LoEthernetEcho_segm_num!=2'd2) && (LoEthernetEcho_segm_num!=2'd3) && (LoEthernetEcho_segm_num
!=3'd4) && (LoEthernetEcho_segm_num!=3'd5)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
!=1'd1) && (LoEthernetEcho_segm_num!=2'd2) && (LoEthernetEcho_segm_num!=2'd3) && (LoEthernetEcho_segm_num
!=3'd4) && (LoEthernetEcho_segm_num!=3'd5)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8!=(64'h_ffff&(s_axis_tdata>>6'd32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num
) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8!=(64'h_ffff&(s_axis_tdata>>6'd32))) && !s_axis_tlast && TLERe1_3_V_3 &&
!(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8==(64'h_ffff&(s_axis_tdata>>6'd32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num
) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8==(64'h_ffff&(s_axis_tdata>>6'd32))) && !s_axis_tlast && TLERe1_3_V_3 &&
!(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !LoEthernetEcho_segm_num) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !LoEthernetEcho_segm_num) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!TLERe1_3_V_3) begin
xpc10 <= 3'd4;
TLEsw1_1_V_2 <= TLERe1_3_V_1;
TLERe1_3_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
end
3'd4: begin
xpc10 <= 4'd8;
LoEthernetEcho_tmp2 <= 64'h_ffff&A_64_US_CC_SCALbx16_ARD0[32'd0];
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx16_ARD0[32'd0];
TLEsw1_1_V_0 <= 32'd0;
LoEthernetEcho_broadcast_ports <= A_64_US_CC_SCALbx10_ARA0[64'd0]|{((64'h55_0000^A_64_US_CC_SCALbx10_ARA0[64'd0])>>
4'd8), 16'd0};
LoEthernetEcho_dst_mac <= {A_64_US_CC_SCALbx14_ARC0[64'd0], 16'd0};
end
4'd8: begin
if ((LoEthernetEcho_dst_mac==LoEthernetEcho_tmp)) begin
xpc10 <= 5'd16;
LoEthernetEcho_tmp <= A_64_US_CC_SCALbx10_ARA0[64'd0]|(64'hffffffffffffffff&{LoEthernetEcho_tmp2, 24'd0});
LoEthernetEcho_LUT_hit <= 1'd1;
LoEthernetEcho_OQ <= {LoEthernetEcho_tmp2, 24'd0};
end
if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && ((32'hffffffff&32'd1+TLEsw1_1_V_0)<64'd16)) begin
LoEthernetEcho_tmp2 <= 64'h_ffff&A_64_US_CC_SCALbx16_ARD0[32'hffffffff&32'd1+TLEsw1_1_V_0];
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx16_ARD0[32'hffffffff&32'd1+TLEsw1_1_V_0];
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && !LoEthernetEcho_LUT_hit && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16)) begin
xpc10 <= 5'd16;
LoEthernetEcho_tmp <= LoEthernetEcho_broadcast_ports|A_64_US_CC_SCALbx10_ARA0[64'd0];
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && LoEthernetEcho_LUT_hit && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16)) begin
xpc10 <= 5'd16;
LoEthernetEcho_tmp <= LoEthernetEcho_OQ|A_64_US_CC_SCALbx10_ARA0[64'd0];
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
end
5'd16: begin
if ((64'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32'd0}) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}<64'h_1e00_0000_0000_0000
) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16'd0}) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}<64'h_3200_0000_0000_0000
) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}>=64'h_3200_0000_0000_0000
) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&1'h1&LoEthernetEcho_proto_UDP&1'h1
&(0==(64'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16'd0}))) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}>=64'h_3200_0000_0000_0000
) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&1'h1&LoEthernetEcho_proto_UDP&1'h1
&(0==(64'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16'd0}))) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}>=64'h_3200_0000_0000_0000
) && !(1'h1&1'h1&LoEthernetEcho_proto_UDP&1'h1&(0==(64'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16'd0
})))) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}<64'h_3200_0000_0000_0000
) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}<64'h_3200_0000_0000_0000
) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16'd0}) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16'd0}) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)
) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}<64'h_1e00_0000_0000_0000
) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}<64'h_1e00_0000_0000_0000
) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32'd0}) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32'd0}) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)) xpc10
<= 6'd32;
end
6'd32: begin
xpc10 <= 7'd64;
LoEthernetEcho_tmp <= (64'd255&(A_64_US_CC_SCALbx10_ARA0[64'd0]>>5'd16))|{(A_64_US_CC_SCALbx14_ARC0[64'd0]>>6'd48), 16'd0
};
end
7'd64: begin
if (LoEthernetEcho_LUT_hit && !m_axis_tready && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
if (LoEthernetEcho_LUT_hit && m_axis_tready && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
if (LoEthernetEcho_LUT_hit && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
if (!LoEthernetEcho_LUT_hit) begin
xpc10 <= 8'd128;
TLEsw1_1_V_0 <= 32'd0;
LoEthernetEcho_LUT_hit <= 1'd0;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
end
8'd128: begin
if (!TLEsw1_1_V_3 && !m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if (!TLEsw1_1_V_3 && m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if (!TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16) && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if (TLEsw1_1_V_3 && !m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if (TLEsw1_1_V_3 && m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if (TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16) && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if (!m_axis_tready && (LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2>=32'd0))
begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_3 <= 1'd1;
end
if (m_axis_tready && (LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2>=32'd0))
begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_3 <= 1'd1;
end
if ((LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
TLEsw1_1_V_3 <= 1'd1;
end
if ((LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff&32'd1+TLEsw1_1_V_0)<64'd16
)) TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
9'd256: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
LoEthernetEcho_segm_num <= 32'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
end
10'd512: begin
if ((TLEsw1_1_V_2<TLESe23_2_V_0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
end
if (m_axis_tready && (TLEsw1_1_V_2>=TLESe23_2_V_0)) begin
TLESe23_2_V_0 <= 32'd1+TLESe23_2_V_0;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLESe23_2_V_0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLESe23_2_V_0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==TLESe23_2_V_0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'h1*(32'hffffffff&TLESe23_2_V_0)];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLESe23_2_V_0];
end
end
endcase
end
endmodule | module EthernetEcho( input [63:0] s_axis_tdata,
input [7:0] s_axis_tkeep,
input s_axis_tlast,
input s_axis_tvalid,
output reg s_axis_tready,
input [63:0] s_axis_tuser_hi,
input [63:0] s_axis_tuser_low,
output reg [63:0] m_axis_tdata,
output reg [7:0] m_axis_tkeep,
output reg m_axis_tlast,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tuser_hi,
output reg [63:0] m_axis_tuser_low,
input cam_busy,
input cam_match,
input [7:0] cam_match_addr,
output reg [63:0] cam_cmp_din,
output [63:0] cam_din,
output cam_we,
output [7:0] cam_wr_addr,
input clk,
input reset); |
reg LoEthernetEcho_proto_UDP;
reg LoEthernetEcho_LUT_hit;
integer TLEsw1_1_V_0;
reg [31:0] TLEsw1_1_V_2;
reg TLEsw1_1_V_3;
reg [31:0] TLERe1_3_V_0;
reg [31:0] TLERe1_3_V_1;
reg TLERe1_3_V_3;
reg [31:0] TLESe23_2_V_0;
reg [31:0] LoEthernetEcho_segm_num;
reg [63:0] LoEthernetEcho_dst_mac;
reg [63:0] LoEthernetEcho_broadcast_ports;
reg [63:0] LoEthernetEcho_tmp;
reg [63:0] LoEthernetEcho_tmp2;
reg [63:0] LoEthernetEcho_OQ;
reg [63:0] LoEthernetEcho_dst_ip;
reg [63:0] LoEthernetEcho_app_src_port;
reg [63:0] LoEthernetEcho_app_dst_port;
reg [7:0] A_8_US_CC_SCALbx18_ARA0[29:0];
reg [63:0] A_64_US_CC_SCALbx10_ARA0[29:0];
reg [63:0] A_64_US_CC_SCALbx12_ARB0[29:0];
reg [63:0] A_64_US_CC_SCALbx14_ARC0[29:0];
reg [63:0] A_64_US_CC_SCALbx16_ARD0[15:0];
reg [9:0] xpc10;
always @(posedge clk ) begin
if (reset) begin
cam_cmp_din <= 64'd0;
TLEsw1_1_V_2 <= 32'd0;
LoEthernetEcho_app_dst_port <= 64'd0;
LoEthernetEcho_app_src_port <= 64'd0;
LoEthernetEcho_dst_ip <= 64'd0;
TLERe1_3_V_3 <= 1'd0;
TLERe1_3_V_1 <= 32'd0;
TLERe1_3_V_0 <= 32'd0;
LoEthernetEcho_broadcast_ports <= 64'd0;
LoEthernetEcho_dst_mac <= 64'd0;
LoEthernetEcho_OQ <= 64'd0;
LoEthernetEcho_tmp2 <= 64'd0;
LoEthernetEcho_LUT_hit <= 1'd0;
LoEthernetEcho_tmp <= 64'd0;
TLEsw1_1_V_3 <= 1'd0;
TLEsw1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
LoEthernetEcho_segm_num <= 32'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
xpc10 <= 10'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 64'd0;
m_axis_tuser_hi <= 64'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 64'd0;
end
else
case (xpc10)
0: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
LoEthernetEcho_segm_num <= 32'd0;
TLEsw1_1_V_3 <= 1'd0;
TLEsw1_1_V_2 <= 32'd0;
TLEsw1_1_V_0 <= 32'd0;
LoEthernetEcho_LUT_hit <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
cam_cmp_din <= 32'h_ffff_ffff;
A_64_US_CC_SCALbx16_ARD0[4'd15] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd14] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd13] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd12] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd11] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd10] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd9] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[4'd8] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd7] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd6] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd5] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[3'd4] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[2'd3] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[2'd2] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[1'd1] <= 64'd1;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'd1;
end
1'd1: begin
if (s_axis_tvalid && s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd2;
TLERe1_3_V_1 <= 32'd0;
TLERe1_3_V_0 <= 32'd1;
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd2;
TLERe1_3_V_1 <= 32'd0;
TLERe1_3_V_0 <= 32'd1;
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!s_axis_tvalid) begin
xpc10 <= 2'd2;
TLERe1_3_V_3 <= 1'd1;
LoEthernetEcho_segm_num <= 32'd1;
TLERe1_3_V_0 <= 32'd0;
TLERe1_3_V_1 <= 32'd0;
end
end
2'd2: begin
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==3'd5))
begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_app_dst_port <= 64'h_ffff&(s_axis_tdata>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&(s_axis_tdata>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&s_axis_tdata, 16'd0};
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==3'd5)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_app_dst_port <= 64'h_ffff&(s_axis_tdata>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&(s_axis_tdata>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&s_axis_tdata, 16'd0};
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==3'd4)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_ip <= 64'h_ffff&(s_axis_tdata>>6'd48);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==3'd4)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_ip <= 64'h_ffff&(s_axis_tdata>>6'd48);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==2'd3)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&(s_axis_tdata>>6'd56)));
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==2'd3)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&(s_axis_tdata>>6'd56)));
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==1'd1)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
==1'd1)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&s_axis_tdata;
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
!=1'd1) && (LoEthernetEcho_segm_num!=2'd2) && (LoEthernetEcho_segm_num!=2'd3) && (LoEthernetEcho_segm_num
!=3'd4) && (LoEthernetEcho_segm_num!=3'd5)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num
!=1'd1) && (LoEthernetEcho_segm_num!=2'd2) && (LoEthernetEcho_segm_num!=2'd3) && (LoEthernetEcho_segm_num
!=3'd4) && (LoEthernetEcho_segm_num!=3'd5)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8!=(64'h_ffff&(s_axis_tdata>>6'd32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num
) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8!=(64'h_ffff&(s_axis_tdata>>6'd32))) && !s_axis_tlast && TLERe1_3_V_3 &&
!(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8==(64'h_ffff&(s_axis_tdata>>6'd32))) && s_axis_tlast && TLERe1_3_V_3 && !(!LoEthernetEcho_segm_num
) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && (4'd8==(64'h_ffff&(s_axis_tdata>>6'd32))) && !s_axis_tlast && TLERe1_3_V_3 &&
!(!LoEthernetEcho_segm_num) && (LoEthernetEcho_segm_num==2'd2)) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && s_axis_tlast && TLERe1_3_V_3 && !LoEthernetEcho_segm_num) begin
s_axis_tready <= 1'd0;
TLERe1_3_V_3 <= 1'd0;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_3_V_3 && !LoEthernetEcho_segm_num) begin
s_axis_tready <= 1'd1;
TLERe1_3_V_3 <= 1'h1&s_axis_tvalid;
LoEthernetEcho_segm_num <= 32'd1+LoEthernetEcho_segm_num;
TLERe1_3_V_1 <= TLERe1_3_V_0;
TLERe1_3_V_0 <= 32'd1+(32'hffffffff&TLERe1_3_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx18_ARA0[32'hffffffff&TLERe1_3_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_3_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!TLERe1_3_V_3) begin
xpc10 <= 3'd4;
TLEsw1_1_V_2 <= TLERe1_3_V_1;
TLERe1_3_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
end
3'd4: begin
xpc10 <= 4'd8;
LoEthernetEcho_tmp2 <= 64'h_ffff&A_64_US_CC_SCALbx16_ARD0[32'd0];
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx16_ARD0[32'd0];
TLEsw1_1_V_0 <= 32'd0;
LoEthernetEcho_broadcast_ports <= A_64_US_CC_SCALbx10_ARA0[64'd0]|{((64'h55_0000^A_64_US_CC_SCALbx10_ARA0[64'd0])>>
4'd8), 16'd0};
LoEthernetEcho_dst_mac <= {A_64_US_CC_SCALbx14_ARC0[64'd0], 16'd0};
end
4'd8: begin
if ((LoEthernetEcho_dst_mac==LoEthernetEcho_tmp)) begin
xpc10 <= 5'd16;
LoEthernetEcho_tmp <= A_64_US_CC_SCALbx10_ARA0[64'd0]|(64'hffffffffffffffff&{LoEthernetEcho_tmp2, 24'd0});
LoEthernetEcho_LUT_hit <= 1'd1;
LoEthernetEcho_OQ <= {LoEthernetEcho_tmp2, 24'd0};
end
if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && ((32'hffffffff&32'd1+TLEsw1_1_V_0)<64'd16)) begin
LoEthernetEcho_tmp2 <= 64'h_ffff&A_64_US_CC_SCALbx16_ARD0[32'hffffffff&32'd1+TLEsw1_1_V_0];
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff_0000&A_64_US_CC_SCALbx16_ARD0[32'hffffffff&32'd1+TLEsw1_1_V_0];
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && !LoEthernetEcho_LUT_hit && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16)) begin
xpc10 <= 5'd16;
LoEthernetEcho_tmp <= LoEthernetEcho_broadcast_ports|A_64_US_CC_SCALbx10_ARA0[64'd0];
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if ((LoEthernetEcho_dst_mac!=LoEthernetEcho_tmp) && LoEthernetEcho_LUT_hit && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16)) begin
xpc10 <= 5'd16;
LoEthernetEcho_tmp <= LoEthernetEcho_OQ|A_64_US_CC_SCALbx10_ARA0[64'd0];
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
end
5'd16: begin
if ((64'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32'd0}) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}<64'h_1e00_0000_0000_0000
) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16'd0}) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}<64'h_3200_0000_0000_0000
) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}>=64'h_3200_0000_0000_0000
) && (4'd8==(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&1'h1&LoEthernetEcho_proto_UDP&1'h1
&(0==(64'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16'd0}))) begin
xpc10 <= 6'd32;
A_64_US_CC_SCALbx10_ARA0[64'd0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}>=64'h_3200_0000_0000_0000
) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&1'h1&LoEthernetEcho_proto_UDP&1'h1
&(0==(64'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16'd0}))) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}>=64'h_3200_0000_0000_0000
) && !(1'h1&1'h1&LoEthernetEcho_proto_UDP&1'h1&(0==(64'h_3400_0000_0000_0000<{LoEthernetEcho_app_dst_port, 16'd0
})))) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}<64'h_3200_0000_0000_0000
) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000>={LoEthernetEcho_app_src_port, 16'd0}) && ({LoEthernetEcho_app_dst_port, 48'd0}<64'h_3200_0000_0000_0000
) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16'd0}) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}>=64'h_1e00_0000_0000_0000
) && (64'h_2200_0000_0000_0000<{LoEthernetEcho_app_src_port, 16'd0}) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)
) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}<64'h_1e00_0000_0000_0000
) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP
) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000=={LoEthernetEcho_dst_ip, 32'd0}) && ({LoEthernetEcho_app_src_port, 48'd0}<64'h_1e00_0000_0000_0000
) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32'd0}) && (4'd8!=(64'h_ffff&(A_64_US_CC_SCALbx14_ARC0
[64'd1]>>6'd32))) && 1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP) xpc10 <= 6'd32;
if ((64'h404_afc0_0000_0000!={LoEthernetEcho_dst_ip, 32'd0}) && !(1'h1&32'd0&1'h1&LoEthernetEcho_proto_UDP)) xpc10
<= 6'd32;
end
6'd32: begin
xpc10 <= 7'd64;
LoEthernetEcho_tmp <= (64'd255&(A_64_US_CC_SCALbx10_ARA0[64'd0]>>5'd16))|{(A_64_US_CC_SCALbx14_ARC0[64'd0]>>6'd48), 16'd0
};
end
7'd64: begin
if (LoEthernetEcho_LUT_hit && !m_axis_tready && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
if (LoEthernetEcho_LUT_hit && m_axis_tready && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
if (LoEthernetEcho_LUT_hit && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
if (!LoEthernetEcho_LUT_hit) begin
xpc10 <= 8'd128;
TLEsw1_1_V_0 <= 32'd0;
LoEthernetEcho_LUT_hit <= 1'd0;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|{A_64_US_CC_SCALbx14_ARC0[64'd1], 32'd0};
end
end
8'd128: begin
if (!TLEsw1_1_V_3 && !m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if (!TLEsw1_1_V_3 && m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if (!TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16) && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
A_64_US_CC_SCALbx16_ARD0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
if (TLEsw1_1_V_3 && !m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if (TLEsw1_1_V_3 && m_axis_tready && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff
&32'd1+TLEsw1_1_V_0)>=64'd16) && (TLEsw1_1_V_2>=32'd0)) begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if (TLEsw1_1_V_3 && (LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff&32'd1+TLEsw1_1_V_0
)>=64'd16) && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
if (!m_axis_tready && (LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2>=32'd0))
begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_3 <= 1'd1;
end
if (m_axis_tready && (LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2>=32'd0))
begin
xpc10 <= 10'd512;
TLESe23_2_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
m_axis_tvalid <= 1'd1;
TLEsw1_1_V_3 <= 1'd1;
end
if ((LoEthernetEcho_tmp==A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && (TLEsw1_1_V_2<32'd0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe23_2_V_0 <= 32'd0;
TLEsw1_1_V_3 <= 1'd1;
end
if ((LoEthernetEcho_tmp!=A_64_US_CC_SCALbx16_ARD0[TLEsw1_1_V_0]) && ((32'hffffffff&32'd1+TLEsw1_1_V_0)<64'd16
)) TLEsw1_1_V_0 <= 32'd1+TLEsw1_1_V_0;
end
9'd256: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
LoEthernetEcho_segm_num <= 32'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
end
10'd512: begin
if ((TLEsw1_1_V_2<TLESe23_2_V_0)) begin
xpc10 <= 9'd256;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
end
if (m_axis_tready && (TLEsw1_1_V_2>=TLESe23_2_V_0)) begin
TLESe23_2_V_0 <= 32'd1+TLESe23_2_V_0;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLESe23_2_V_0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLESe23_2_V_0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_2==TLESe23_2_V_0);
m_axis_tkeep <= A_8_US_CC_SCALbx18_ARA0[8'h1*(32'hffffffff&TLESe23_2_V_0)];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLESe23_2_V_0];
end
end
endcase
end
endmodule | 3 |
142,106 | data/full_repos/permissive/97045669/out/TCP_Ping.v | 97,045,669 | TCP_Ping.v | v | 1,156 | 211 | [] | [] | [] | null | line:214 column:42: Illegal character "'" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:189: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n xpc10 <= 1\'d1 ;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:191: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:192: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:196: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:205: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:213: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n cam_din <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:214: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n cam_cmp_din <= 32\'h_ffff_ffff;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:219: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:225: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLERe1_1_V_5 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:232: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:238: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLERe1_1_V_5 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:245: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d2 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:249: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLERe1_1_V_5 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:276: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n xpc10 <= 2\'d3 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:286: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:291: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:296: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:301: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:302: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[32\'hffffffff&TLERe1_1_V_1] <= 64\'hffffffffffffffff&32\'h_ffff_ffff&TLERe1_1_V_5\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:308: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:315: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:322: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:284: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:284: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:284: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:284: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:284: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:284: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:284: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h7f\' generates 7 bits.\n : ... In instance EthernetEcho\n case (TLERe1_1_V_6)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:330: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n (TLERe1_1_V_6!=2\'d3 )) xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:328: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6!=3\'d7 ) && (TLERe1_1_V_6!=4\'d15 ) && (TLERe1_1_V_6!=5\'d31 ) && (TLERe1_1_V_6\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:328: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6!=3\'d7 ) && (TLERe1_1_V_6!=4\'d15 ) && (TLERe1_1_V_6!=5\'d31 ) && (TLERe1_1_V_6\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:328: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6!=3\'d7 ) && (TLERe1_1_V_6!=4\'d15 ) && (TLERe1_1_V_6!=5\'d31 ) && (TLERe1_1_V_6\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:329: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:329: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h7f\' generates 7 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:329: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:329: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n !=6\'d63 ) && (TLERe1_1_V_6!=7\'d127 ) && (TLERe1_1_V_6!=1\'d1 ) && (TLERe1_1_V_6!=2\'d2 ) && \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:330: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n (TLERe1_1_V_6!=2\'d3 )) xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:331: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6==2\'d2 )) xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:331: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((TLERe1_1_V_6==2\'d2 )) xpc10 <= 3\'d4 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:340: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_TCP <= 1\'h1&(3\'d6 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:341: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_UDP <= 1\'h1&(5\'d17 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:344: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_ICMP <= 1\'h1&(1\'d1 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:335: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:335: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:353: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:353: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:346: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d4 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:346: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d4 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:359: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_opcode <= 64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d24);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_magic_num <= 64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d16);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:361: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_TCP_seq_num\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:361: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:364: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_SYN_flag <= 1\'h1&(2\'d2 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:355: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:355: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:368: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if (((32\'hffffffff&TLEsw1_1_V_4)==0 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:377: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:380: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_TCP <= 1\'h1&(3\'d6 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:381: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_UDP <= 1\'h1&(5\'d17 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:384: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_proto_ICMP <= 1\'h1&(1\'d1 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:376: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d2 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:376: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d2 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:387: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:392: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:392: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:386: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d4 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:386: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d4 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:395: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:397: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_opcode <= 64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d24);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:398: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_magic_num <= 64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d16);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:399: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_TCP_seq_num\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:399: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64\'h_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:402: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_SYN_flag <= 1\'h1&(2\'d2 ==(64\'d255&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d56\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:394: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d5 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:394: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d5 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:407: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:406: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if (((32\'hffffffff&TLEsw1_1_V_4)==0 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4))) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:419: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:419: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:419: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:413: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:413: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:413: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:428: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_IPv4 <= 1\'h1&(3\'d4 ==(64\'d15&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d52)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:429: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:429: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:429: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:423: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 ==\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:423: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 ==\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:423: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 ==\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:438: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_ip <= 32\'h_ffff_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d16);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:433: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:433: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:442: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:445: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:445: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:445: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:440: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 !=\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:440: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:440: Operator NEQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 !=\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:451: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:453: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_IPv4 <= 1\'h1&(3\'d4 ==(64\'d15&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>6\'d52)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:454: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:454: Operator OR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:454: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 80 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32\'h_ffff_ffff&64\'hffffffffffffffff&TLEsw1_1_V_2, 16\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:449: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 ==\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:449: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 ==\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:449: Operator EQ expects 64 bits on the LHS, but LHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==1\'d1 ) && (4\'d8 ==\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:459: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:462: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_src_ip <= 32\'h_ffff_ffff&((64\'hffffffffffffffff&TLEsw1_1_V_2)>>5\'d16);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:458: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d3 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:458: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==2\'d3 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:464: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d6 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:464: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d6 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:469: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d7 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:469: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d7 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:474: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num!=8\'d128 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:475: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:480: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:480: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:481: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:481: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:486: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:486: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:487: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:487: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:492: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !(!LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:492: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !(!LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:493: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && (LoEthernetEcho_opcode!=3\'d4 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:493: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (LoEthernetEcho_opcode!=3\'d4 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:494: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n )==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:499: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !(!LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:499: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !(!LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:500: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:500: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:505: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && !(!LoEthernetEcho_opcode) && (LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:506: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ==3\'d4 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:506: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ==3\'d4 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:506: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ==3\'d4 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:511: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num!=8\'d128 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:512: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)==4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:517: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:517: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:518: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:523: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:523: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:524: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:529: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num!=8\'d128 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:530: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)==4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:535: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:535: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:536: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:541: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:541: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10>=(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:542: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:547: Operator GTE expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if (((32\'hffffffff&TLEsw1_1_V_4)!=0 ) && (4\'d10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:548: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:548: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:548: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:549: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:549: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:550: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d7 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:550: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d7 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:550: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d7 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:551: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d9 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:551: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d9 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:557: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:556: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d6 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:556: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d6 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:561: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:560: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d7 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:560: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==3\'d7 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:566: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:564: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num!=8\'d128 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:565: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:571: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:569: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:569: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:570: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:570: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:576: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:574: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:574: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:575: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:575: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:582: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:579: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !(!LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:579: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && !(!LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:580: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && (LoEthernetEcho_opcode!=3\'d4 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:580: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (LoEthernetEcho_opcode!=3\'d4 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:581: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n )==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:587: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:585: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !(!LoEthernetEcho_opcode\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:585: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && !(!LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:586: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:586: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:592: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:590: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'LoEthernetEcho_opcode\' generates 8 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && !(!LoEthernetEcho_opcode) && (LoEthernetEcho_opcode\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:591: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ==3\'d4 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:591: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ==3\'d4 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:591: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n ==3\'d4 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d8 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:597: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:595: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num!=8\'d128 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:596: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)==4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:602: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:600: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10<(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:600: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10<(32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:601: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:607: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:605: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10<(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:605: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10<(32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:606: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d9 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:612: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:610: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num!=8\'d128 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:611: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)==4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:617: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:615: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10<(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:615: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode!=1\'d1 ) && (4\'d10<(32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:616: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:622: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:620: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10<(32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:620: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if ((LoEthernetEcho_magic_num==8\'d128 ) && (LoEthernetEcho_opcode==1\'d1 ) && (4\'d10<(32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:621: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n &32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff&TLEsw1_1_V_4)==4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:630: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d6 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:625: Operator LT expects 32 bits on the LHS, but LHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n if (((32\'hffffffff&TLEsw1_1_V_4)!=0 ) && (4\'d10<(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && ((32\'hffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:626: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:626: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:626: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=1\'d1 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d2 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=2\'d3\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:627: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:627: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d4 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d5 ) && ((32\'hffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:628: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d7 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:628: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d7 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:628: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_4)!=3\'d6 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=3\'d7 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:629: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d9 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:629: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d9 ) && ((32\'hffffffff&TLEsw1_1_V_4)!=4\'d10 )) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:637: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:636: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((2\'d2 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:647: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:648: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:645: Operator GTE expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca6_0_V_0)) && (2\'d2 !=(8\'hff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:645: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca6_0_V_0)) && (2\'d2 !=(8\'hff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:645: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (1\'d1 !=(8\'hff&8\'d1+TLEca6_0_V_0)) && (2\'d2 !=(8\'hff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:646: Operator NEQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n &8\'d1+TLEca6_0_V_0)) && (2\'d3 !=(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:656: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:655: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n if ((2\'d3 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:665: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:666: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[3\'d4], 48\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:666: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 112 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[3\'d4], 48\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:664: Operator GTE expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (3\'d4 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:664: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4>=(8\'hff&8\'d1+TLEca6_0_V_0)) && (3\'d4 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:674: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:675: Bit extraction of array[255:0] requires 8 bit index, not 1 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[1\'d1]>>6\'d48);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:673: Operator EQ expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n if ((1\'d1 ==(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:683: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d10 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:684: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEsw1_1_V_20 <= 1\'h1&(0 ==(64\'hffffffffffffffff&64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:689: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_12 <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_0_V_12+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:682: Operator LT expects 8 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((3\'d4<(8\'hff&8\'d1+TLEca6_0_V_0))) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:702: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:703: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:705: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:722: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:723: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:725: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:734: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n xpc10 <= 1\'d1 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:736: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:737: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:741: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:743: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:187: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:187: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:187: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:187: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:187: Operator CASE expects 32 or 6 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:754: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d15 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:764: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff&32\'h_ffff_ffff^LoEthernetEcho_chksum_UDP;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:766: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:752: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:785: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:770: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:791: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d5 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:801: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n xpc10 <= 3\'d7 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:810: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d8 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:811: Bit extraction of array[255:0] requires 8 bit index, not 1 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[1\'d1]>>6\'d48);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:813: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_12 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:814: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_7 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:815: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n TLEca6_0_V_6 <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:822: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d9 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:828: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d11 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:830: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff\' generates 64 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:830: Operator AND expects 72 bits on the RHS, but RHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:831: Operator ADD expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffec\' generates 64 bits.\n : ... In instance EthernetEcho\n +((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}), 8\'d0}, 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:831: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n +((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}), 8\'d0}, 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:829: Operator AND expects 80 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:829: Operator AND expects 80 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:829: Operator ADD expects 80 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffec\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:830: Operator SHIFTR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:830: Operator OR expects 80 bits on the RHS, but RHS\'s REPLICATE generates 72 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:829: Operator OR expects 112 bits on the LHS, but LHS\'s CONST \'64\'h600\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:829: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 112 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:833: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:833: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:834: Operator ADD expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffec\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:834: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:834: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:840: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hc\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d12 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:846: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hd\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d13 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:847: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= (64\'h_ffff&32\'d0+(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_46_V_4+TLEca6_46_V_5)+(TLEca6_46_V_4\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:848: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n +TLEca6_46_V_5>>5\'d16)))+(32\'d0+(64\'hffffffffffffffff&(64\'h_ffff&TLEca6_46_V_4+TLEca6_46_V_5)+(TLEca6_46_V_4+TLEca6_46_V_5\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:854: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'he\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d14 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:862: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d16 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:865: Operator AND expects 112 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:865: Operator AND expects 112 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_src_mac\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48\'d0\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:865: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 112 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48\'d0\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:877: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d17 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:878: Bit extraction of array[255:0] requires 8 bit index, not 1 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (-64\'h1_0000_0000&A_64_US_CC_SCALbx14_ARC0[1\'d1])|(LoEthernetEcho_dst_mac>>5\'d16);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:882: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h12\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d18 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:883: Bit extraction of array[255:0] requires 8 bit index, not 1 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[1\'d1] <= 64\'hffffffffffffffff&TLEsw15_4_V_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:887: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h13\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d19 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:888: Bit extraction of array[255:0] requires 8 bit index, not 2 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[2\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:888: Operator AND expects 112 bits on the LHS, but LHS\'s CONST \'64\'hffff\' generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[2\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:888: Operator AND expects 112 bits on the RHS, but RHS\'s ARRAYSEL generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[2\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:888: Operator OR expects 112 bits on the RHS, but RHS\'s REPLICATE generates 80 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[2\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:888: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 112 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (64\'h_ffff&A_64_US_CC_SCALbx14_ARC0[2\'d3])|{LoEthernetEcho_dst_ip, 16\'d0}|{LoEthernetEcho_src_ip\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:894: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d20 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:895: Bit extraction of array[255:0] requires 8 bit index, not 2 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[2\'d3] <= 64\'hffffffffffffffff&TLEsw15_4_V_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:900: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h15\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d21 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:901: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3\'d4])|(LoEthernetEcho_src_ip>>5\'d16);\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:904: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h15\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d21 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:905: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3\'d4])|(LoEthernetEcho_src_ip>>5\'d16)|\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:905: Operator NEGATE expects 96 bits on the LHS, but LHS\'s CONST \'64\'h1000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3\'d4])|(LoEthernetEcho_src_ip>>5\'d16)|\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:905: Operator AND expects 96 bits on the RHS, but RHS\'s ARRAYSEL generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3\'d4])|(LoEthernetEcho_src_ip>>5\'d16)|\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:905: Operator SHIFTR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_src_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3\'d4])|(LoEthernetEcho_src_ip>>5\'d16)|\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:906: Operator OR expects 96 bits on the RHS, but RHS\'s REPLICATE generates 80 bits.\n : ... In instance EthernetEcho\n {LoEthernetEcho_app_src_port, 32\'d0}|{LoEthernetEcho_app_dst_port, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:905: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n TLEsw15_4_V_0 <= (-64\'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3\'d4])|(LoEthernetEcho_src_ip>>5\'d16)|\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:909: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h15\' generates 5 bits.\n : ... In instance EthernetEcho\n if (!TLEsw15_4_V_1 && !TLEsw15_4_V_2) xpc10 <= 5\'d21 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:913: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h16\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d22 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:914: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d4] <= 64\'hffffffffffffffff&TLEsw15_4_V_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:918: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h17\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d23 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:919: Operator ADD expects 88 bits on the LHS, but LHS\'s CONST \'32\'h1\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 32\'d1+((LoEthernetEcho_TCP_seq_num>>5\'d24)|((64\'hff_0000&LoEthernetEcho_TCP_seq_num)>>4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:919: Operator SHIFTR expects 88 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_TCP_seq_num\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 32\'d1+((LoEthernetEcho_TCP_seq_num>>5\'d24)|((64\'hff_0000&LoEthernetEcho_TCP_seq_num)>>4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:919: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hff0000\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 32\'d1+((LoEthernetEcho_TCP_seq_num>>5\'d24)|((64\'hff_0000&LoEthernetEcho_TCP_seq_num)>>4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:919: Operator AND expects 88 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_TCP_seq_num\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 32\'d1+((LoEthernetEcho_TCP_seq_num>>5\'d24)|((64\'hff_0000&LoEthernetEcho_TCP_seq_num)>>4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:920: Operator OR expects 88 bits on the RHS, but RHS\'s REPLICATE generates 72 bits.\n : ... In instance EthernetEcho\n )|{64\'h_ff00&LoEthernetEcho_TCP_seq_num, 8\'d0}|{64\'d255&LoEthernetEcho_TCP_seq_num, 24\'d0});\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:919: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 88 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 32\'d1+((LoEthernetEcho_TCP_seq_num>>5\'d24)|((64\'hff_0000&LoEthernetEcho_TCP_seq_num)>>4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:922: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:926: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h18\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d24 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:927: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp3 <= 64\'hff_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3\'d5];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:929: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_19, 8\'d0})|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:929: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_19, 8\'d0})|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:929: Operator SHIFTR expects 88 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp1\' generates 64 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_19, 8\'d0})|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:929: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hff0000\' generates 64 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_19, 8\'d0})|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:929: Operator AND expects 88 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp1\' generates 64 bits.\n : ... In instance EthernetEcho\n &TLEsw1_1_V_19, 8\'d0})|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:930: Operator OR expects 88 bits on the RHS, but RHS\'s REPLICATE generates 72 bits.\n : ... In instance EthernetEcho\n )|{64\'h_ff00&LoEthernetEcho_tmp1, 8\'d0}|{64\'d255&LoEthernetEcho_tmp1, 24\'d0}, 16\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:928: Operator OR expects 104 bits on the LHS, but LHS\'s CONST \'64\'h1400000000000000\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_1400_0000_0000_0000|(64\'hffffffffffffffff&((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:928: Operator AND expects 104 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_1400_0000_0000_0000|(64\'hffffffffffffffff&((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:928: Operator AND expects 104 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_1400_0000_0000_0000|(64\'hffffffffffffffff&((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:928: Operator AND expects 104 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_1400_0000_0000_0000|(64\'hffffffffffffffff&((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:928: Operator OR expects 104 bits on the RHS, but RHS\'s REPLICATE generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_1400_0000_0000_0000|(64\'hffffffffffffffff&((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:928: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 104 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'h_1400_0000_0000_0000|(64\'hffffffffffffffff&((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:932: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= ((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255&TLEsw1_1_V_19, 8\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:932: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= ((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255&TLEsw1_1_V_19, 8\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:932: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= ((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255&TLEsw1_1_V_19, 8\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:932: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= ((64\'h_ff00&TLEsw1_1_V_19)>>4\'d8)|{64\'d255&TLEsw1_1_V_19, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:933: Operator SHIFTR expects 88 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp1\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= (LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8)|{64\'h_ff00\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:933: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hff0000\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= (LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8)|{64\'h_ff00\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:933: Operator AND expects 88 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp1\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= (LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8)|{64\'h_ff00\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:933: Operator OR expects 88 bits on the RHS, but RHS\'s REPLICATE generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= (LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8)|{64\'h_ff00\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:933: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 88 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_TCP_seq_num <= (LoEthernetEcho_tmp1>>5\'d24)|((64\'hff_0000&LoEthernetEcho_tmp1)>>4\'d8)|{64\'h_ff00\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:939: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h19\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d25 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:941: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d5] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp2|LoEthernetEcho_tmp3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:945: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1a\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d26 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:946: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= 64\'h_ffff_ffff_ffff&A_64_US_CC_SCALbx14_ARC0[3\'d4];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:950: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1b\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d27 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:951: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|(64\'hffffffffffffffff&(64\'hff_0000&TLEsw1_1_V_19)|(-64\'h100_0000&TLEsw1_1_V_19\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:951: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_tmp|(64\'hffffffffffffffff&(64\'hff_0000&TLEsw1_1_V_19)|(-64\'h100_0000&TLEsw1_1_V_19\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:954: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(64\'hffffffffffffffff&(64\'hff_0000&TLEsw1_1_V_19\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:954: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d4] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|(64\'hffffffffffffffff&(64\'hff_0000&TLEsw1_1_V_19\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:955: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'TLEsw1_1_V_19\' generates 32 bits.\n : ... In instance EthernetEcho\n )|(-64\'h100_0000&TLEsw1_1_V_19));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:960: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1c\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d28 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:962: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff\' generates 64 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:962: Operator AND expects 72 bits on the RHS, but RHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:963: Operator ADD expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffec\' generates 64 bits.\n : ... In instance EthernetEcho\n +((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}), 8\'d0}, 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:963: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n +((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}), 8\'d0}, 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:961: Operator AND expects 80 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:961: Operator AND expects 80 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:961: Operator ADD expects 80 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffec\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:962: Operator SHIFTR expects 80 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:962: Operator OR expects 80 bits on the RHS, but RHS\'s REPLICATE generates 72 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length, 8\'d0}))>>4\'d8)|{64\'d255&64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:961: Operator OR expects 112 bits on the LHS, but LHS\'s CONST \'64\'h600\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:961: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 112 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= 64\'d1536|{64\'hffffffffffffffff&((64\'hffffffffffffffff&64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:965: Operator OR expects 96 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_dst_ip\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:965: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 96 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:966: Operator ADD expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffec\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:966: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_IP_total_length\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:966: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4\'d8)|{64\'d255&LoEthernetEcho_IP_total_length\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:972: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1d\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d29 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:978: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d30 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:979: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_chksum_UDP <= (64\'h_ffff&32\'d0+(64\'hffffffffffffffff&(64\'h_ffff&TLEca15_166_V_4+TLEca15_166_V_5\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:980: Operator ADD expects 64 bits on the LHS, but LHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n )+(TLEca15_166_V_4+TLEca15_166_V_5>>5\'d16)))+(32\'d0+(64\'hffffffffffffffff&(64\'h_ffff&TLEca15_166_V_4+TLEca15_166_V_5\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:986: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n xpc10 <= 5\'d31 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:994: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp <= -64\'h_ffff_0001&A_64_US_CC_SCALbx14_ARC0[3\'d6];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1004: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp1\' generates 64 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= (LoEthernetEcho_tmp1>>4\'d8)|{64\'d255&LoEthernetEcho_tmp1, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1004: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 72 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp2 <= (LoEthernetEcho_tmp1>>4\'d8)|{64\'d255&LoEthernetEcho_tmp1, 8\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1005: Bit extraction of array[255:0] requires 8 bit index, not 3 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1005: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1006: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp1\' generates 64 bits.\n : ... In instance EthernetEcho\n >>4\'d8)|{64\'d255&LoEthernetEcho_tmp1, 8\'d0}, 16\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1005: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1005: Operator AND expects 88 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1005: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 88 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx14_ARC0[3\'d6] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp|{64\'hffffffffffffffff&(LoEthernetEcho_tmp1\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1013: Operator AND expects 88 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp3|{LoEthernetEcho_src_port, 24\'d0}|{LoEthernetEcho_src_port\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1013: Operator AND expects 88 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp3\' generates 64 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp3|{LoEthernetEcho_src_port, 24\'d0}|{LoEthernetEcho_src_port\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1013: Operator OR expects 88 bits on the RHS, but RHS\'s REPLICATE generates 80 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp3|{LoEthernetEcho_src_port, 24\'d0}|{LoEthernetEcho_src_port\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1013: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s OR generates 88 bits.\n : ... In instance EthernetEcho\n A_64_US_CC_SCALbx10_ARA0[0] <= 64\'hffffffffffffffff&LoEthernetEcho_tmp3|{LoEthernetEcho_src_port, 24\'d0}|{LoEthernetEcho_src_port\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1021: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_low <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1022: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tuser_hi <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1024: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance EthernetEcho\n m_axis_tdata <= 32\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1046: Operator EQ expects 32 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && (3\'d4 ==(32\'hffffffff&32\'d1+TLEsw1_1_V_4))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1055: Operator NEQ expects 32 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && (3\'d4 !=(32\'hffffffff&32\'d1+TLEsw1_1_V_4\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1067: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n : ... In instance EthernetEcho\n LoEthernetEcho_tmp1 <= 64\'h_ffff&32\'h_ffff_ffff^(64\'hffffffffffffffff&(64\'h_ffff&TLEca19_5_V_7+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1087: Operator EQ expects 32 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && (3\'d4 ==(32\'hffffffff&32\'d1+TLEsw1_1_V_4))) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1096: Operator NEQ expects 32 bits on the LHS, but LHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n if ((TLEsw1_1_V_10>=(32\'hffffffff&32\'d1+TLEsw1_1_V_4)) && (3\'d4 !=(32\'hffffffff&32\'d1+TLEsw1_1_V_4\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1107: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n xpc10 <= 4\'d15 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h11\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h12\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h13\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h14\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h15\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h16\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h17\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h18\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h19\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1a\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1b\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1c\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1d\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1e\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:789: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h1f\' generates 5 bits.\n : ... In instance EthernetEcho\n case (xpc10)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1123: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134410 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1123: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134410 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1123: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134410 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1123: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134410 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1124: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>5\'d16))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1124: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\n), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>5\'d16))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1123: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin134410 = (64\'hffffffffffffffff&{64\'d255&TLEca6_0_V_1, 8\'d0}|((64\'h_ff00&TLEca6_0_V_1)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>5\'d16\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1126: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134910 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1126: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134910 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1126: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134910 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1126: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin134910 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1127: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n&(TLEca6_0_V_1>>6\'d48), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d48))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1127: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'TLEca6_0_V_1\' generates 64 bits.\n : ... In instance EthernetEcho\n&(TLEca6_0_V_1>>6\'d48), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d48))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1126: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin134910 = (64\'hffffffffffffffff&{64\'d255&(TLEca6_0_V_1>>6\'d32), 8\'d0}|((64\'h_ff00&(TLEca6_0_V_1>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff&{64\'d255\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1129: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin139510 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1129: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin139510 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1129: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin139510 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1129: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin139510 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1130: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>5\'d16))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1130: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>5\'d16))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1129: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin139510 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp2, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp2)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1132: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin140010 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1132: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin140010 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1132: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin140010 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1133: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp2>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d48))>>4\'d8));\n^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1133: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp2>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d48))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1133: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp2\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp2>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d48))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1132: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin140010 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp2>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp2>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1135: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin141610 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1135: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin141610 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1135: Operator AND expects 72 bits on the RHS, but RHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin141610 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1135: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin141610 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1136: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>5\'d16))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1136: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n>>5\'d16), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>5\'d16))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1135: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin141610 = (64\'hffffffffffffffff&{64\'d255&LoEthernetEcho_tmp, 8\'d0}|((64\'h_ff00&LoEthernetEcho_tmp)>>4\'d8))+(64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1138: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin142110 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1138: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin142110 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1138: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\nassign hprpin142110 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1139: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hffffffffffffffff\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>6\'d48))>>4\'d8));\n^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1139: Operator AND expects 72 bits on the LHS, but LHS\'s CONST \'64\'hff00\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>6\'d48))>>4\'d8));\n ^\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1139: Operator SHIFTR expects 72 bits on the LHS, but LHS\'s VARREF \'LoEthernetEcho_tmp\' generates 64 bits.\n : ... In instance EthernetEcho\n&{64\'d255&(LoEthernetEcho_tmp>>6\'d48), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>6\'d48))>>4\'d8));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97045669/out/TCP_Ping.v:1138: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 72 bits.\n : ... In instance EthernetEcho\nassign hprpin142110 = (64\'hffffffffffffffff&{64\'d255&(LoEthernetEcho_tmp>>6\'d32), 8\'d0}|((64\'h_ff00&(LoEthernetEcho_tmp>>6\'d32))>>4\'d8))+(64\'hffffffffffffffff\n ^\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/TCP_Ping.v:698: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (!m_axis_tready && ((32\'hffffffff&TLEsw1_1_V_10)>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/TCP_Ping.v:709: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (m_axis_tready && ((32\'hffffffff&TLEsw1_1_V_10)>=32\'d0)) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/97045669/out/TCP_Ping.v:720: Comparison is constant due to unsigned arithmetic\n : ... In instance EthernetEcho\n if (((32\'hffffffff&TLEsw1_1_V_10)<32\'d0)) begin \n ^\n%Error: Exiting due to 493 warning(s)\n' | 313,047 | module | module EthernetEcho( input [63:0] s_axis_tdata,
input [7:0] s_axis_tkeep,
input s_axis_tlast,
input s_axis_tvalid,
output reg s_axis_tready,
input [63:0] s_axis_tuser_hi,
input [63:0] s_axis_tuser_low,
output reg [63:0] m_axis_tdata,
output reg [7:0] m_axis_tkeep,
output reg m_axis_tlast,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tuser_hi,
output reg [63:0] m_axis_tuser_low,
input cam_busy,
input cam_match,
input [7:0] cam_match_addr,
output reg [63:0] cam_cmp_din,
output reg [63:0] cam_din,
output reg cam_we,
output reg [7:0] cam_wr_addr,
input clk,
input reset);
reg LoEthernetEcho_IPv4;
reg LoEthernetEcho_proto_UDP;
reg LoEthernetEcho_proto_ICMP;
reg LoEthernetEcho_proto_TCP;
reg LoEthernetEcho_TCP_SYN_flag;
reg [63:0] LoEthernetEcho_chksum_UDP;
reg [63:0] TLEsw1_1_V_2;
reg [63:0] TLEsw1_1_V_3;
reg [31:0] TLEsw1_1_V_4;
reg [31:0] TLEsw1_1_V_10;
reg TLEsw1_1_V_12;
reg TLEsw1_1_V_13;
reg TLEsw1_1_V_14;
reg TLEsw1_1_V_15;
reg [31:0] TLEsw1_1_V_19;
reg TLEsw1_1_V_20;
reg [31:0] TLERe1_1_V_0;
reg [31:0] TLERe1_1_V_1;
reg TLERe1_1_V_3;
reg [63:0] TLERe1_1_V_5;
reg [7:0] TLERe1_1_V_6;
reg [7:0] TLEca6_0_V_0;
reg [63:0] TLEca6_0_V_1;
reg [63:0] TLEca6_0_V_6;
reg [63:0] TLEca6_0_V_7;
reg [63:0] TLEca6_0_V_12;
reg [63:0] TLEca6_46_V_4;
reg [63:0] TLEca6_46_V_5;
reg [63:0] TLEca6_49_V_4;
reg [63:0] TLEca6_49_V_5;
reg [63:0] TLEca6_49_V_7;
reg [63:0] TLEca10_5_V_4;
reg [63:0] TLEca10_5_V_5;
reg [63:0] TLEca10_5_V_7;
reg [63:0] TLEsw15_4_V_0;
reg TLEsw15_4_V_1;
reg TLEsw15_4_V_2;
reg [63:0] TLEca15_166_V_4;
reg [63:0] TLEca15_166_V_5;
reg [63:0] TLEca15_169_V_4;
reg [63:0] TLEca15_169_V_5;
reg [63:0] TLEca15_169_V_7;
reg [63:0] TLEca19_5_V_4;
reg [63:0] TLEca19_5_V_5;
reg [63:0] TLEca19_5_V_7;
reg [31:0] TLESe22_3_V_0;
reg [31:0] TLESe22_3_V_1;
reg [7:0] LoEthernetEcho_magic_num;
reg [7:0] LoEthernetEcho_opcode;
reg [63:0] LoEthernetEcho_IP_total_length;
reg [63:0] LoEthernetEcho_tmp1;
reg [63:0] LoEthernetEcho_src_ip;
reg [63:0] LoEthernetEcho_dst_ip;
reg [63:0] LoEthernetEcho_tmp;
reg [63:0] LoEthernetEcho_tmp2;
reg [63:0] LoEthernetEcho_dst_mac;
reg [63:0] LoEthernetEcho_src_mac;
reg [63:0] LoEthernetEcho_app_src_port;
reg [63:0] LoEthernetEcho_app_dst_port;
reg [63:0] LoEthernetEcho_TCP_seq_num;
reg [63:0] LoEthernetEcho_tmp3;
reg [63:0] LoEthernetEcho_src_port;
reg [7:0] A_8_US_CC_SCALbx16_ARA0[255:0];
reg [63:0] A_64_US_CC_SCALbx10_ARA0[255:0];
reg [63:0] A_64_US_CC_SCALbx12_ARB0[255:0];
reg [63:0] A_64_US_CC_SCALbx14_ARC0[255:0];
reg [5:0] xpc10;
wire [63:0] hprpin134410;
wire [63:0] hprpin134910;
wire [63:0] hprpin139510;
wire [63:0] hprpin140010;
wire [63:0] hprpin141610;
wire [63:0] hprpin142110;
always @(posedge clk ) begin
if (reset) begin
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 64'd0;
cam_cmp_din <= 64'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 64'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd0;
LoEthernetEcho_opcode <= 8'd0;
LoEthernetEcho_magic_num <= 8'd0;
LoEthernetEcho_app_dst_port <= 64'd0;
LoEthernetEcho_app_src_port <= 64'd0;
LoEthernetEcho_dst_ip <= 64'd0;
LoEthernetEcho_src_ip <= 64'd0;
LoEthernetEcho_IP_total_length <= 64'd0;
TLEsw1_1_V_3 <= 64'd0;
TLEsw1_1_V_2 <= 64'd0;
LoEthernetEcho_src_port <= 64'd0;
LoEthernetEcho_src_mac <= 64'd0;
LoEthernetEcho_dst_mac <= 64'd0;
TLEsw1_1_V_15 <= 1'd0;
TLEsw1_1_V_14 <= 1'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEca6_0_V_7 <= 64'd0;
TLEca6_0_V_6 <= 64'd0;
TLEsw1_1_V_20 <= 1'd0;
TLEca6_0_V_1 <= 64'd0;
TLEca6_0_V_0 <= 8'd0;
TLEca6_0_V_12 <= 64'd0;
TLEca6_46_V_5 <= 64'd0;
TLEca6_46_V_4 <= 64'd0;
TLEca6_49_V_5 <= 64'd0;
TLEca6_49_V_4 <= 64'd0;
TLEca6_49_V_7 <= 64'd0;
TLEsw15_4_V_2 <= 1'd0;
TLEsw15_4_V_1 <= 1'd0;
TLEsw15_4_V_0 <= 64'd0;
LoEthernetEcho_TCP_seq_num <= 64'd0;
TLEca15_166_V_5 <= 64'd0;
TLEca15_166_V_4 <= 64'd0;
TLEca15_169_V_5 <= 64'd0;
TLEca15_169_V_4 <= 64'd0;
TLEca15_169_V_7 <= 64'd0;
LoEthernetEcho_tmp <= 64'd0;
LoEthernetEcho_tmp3 <= 64'd0;
TLEsw1_1_V_19 <= 32'd0;
TLESe22_3_V_1 <= 32'd0;
s_axis_tready <= 1'd0;
TLEsw1_1_V_10 <= 32'd0;
LoEthernetEcho_TCP_SYN_flag <= 1'd0;
LoEthernetEcho_proto_TCP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe22_3_V_0 <= 32'd0;
m_axis_tuser_low <= 64'd0;
m_axis_tuser_hi <= 64'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 64'd0;
TLEca19_5_V_5 <= 64'd0;
TLEca19_5_V_4 <= 64'd0;
TLEca19_5_V_7 <= 64'd0;
LoEthernetEcho_tmp1 <= 64'd0;
TLEca10_5_V_5 <= 64'd0;
TLEca10_5_V_4 <= 64'd0;
TLEca10_5_V_7 <= 64'd0;
xpc10 <= 6'd0;
LoEthernetEcho_tmp2 <= 64'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 64'd0;
end
else begin
case (xpc10)
0: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
TLEsw1_1_V_19 <= 32'd100;
TLEsw1_1_V_20 <= 1'd0;
TLEsw1_1_V_15 <= 1'd0;
TLEsw1_1_V_14 <= 1'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEsw1_1_V_10 <= 32'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_TCP_SYN_flag <= 1'd0;
LoEthernetEcho_proto_TCP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 32'd0;
cam_cmp_din <= 32'h_ffff_ffff;
end
1'd1: begin
if (s_axis_tvalid && s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!s_axis_tvalid) begin
xpc10 <= 2'd2;
TLERe1_1_V_3 <= 1'd1;
TLERe1_1_V_0 <= 32'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
TLERe1_1_V_1 <= 32'd0;
end
end
2'd2: begin
if (s_axis_tvalid && s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!TLERe1_1_V_3) begin
xpc10 <= 2'd3;
TLERe1_1_V_6 <= A_8_US_CC_SCALbx16_ARA0[8'h1*(32'hffffffff&TLERe1_1_V_1)];
TLERe1_1_V_5 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1];
end
end
2'd3: begin
case (TLERe1_1_V_6)
1'd1: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'd255&TLERe1_1_V_5;
end
2'd3: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff&TLERe1_1_V_5;
end
3'd7: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff&TLERe1_1_V_5;
end
4'd15: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&32'h_ffff_ffff&TLERe1_1_V_5
;
end
5'd31: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff&TLERe1_1_V_5
;
end
6'd63: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff_ffff_ffff&TLERe1_1_V_5
;
end
7'd127: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff_ffff&TLERe1_1_V_5
;
end
endcase
if ((TLERe1_1_V_6!=3'd7) && (TLERe1_1_V_6!=4'd15) && (TLERe1_1_V_6!=5'd31) && (TLERe1_1_V_6
!=6'd63) && (TLERe1_1_V_6!=7'd127) && (TLERe1_1_V_6!=1'd1) && (TLERe1_1_V_6!=2'd2) &&
(TLERe1_1_V_6!=2'd3)) xpc10 <= 3'd4;
if ((TLERe1_1_V_6==2'd2)) xpc10 <= 3'd4;
end
3'd5: begin
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_TCP <= 1'h1&(3'd6==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_TCP_seq_num <= ((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_opcode <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd24);
LoEthernetEcho_magic_num <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
LoEthernetEcho_TCP_SYN_flag <= 1'h1&(2'd2==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
end
if (((32'hffffffff&TLEsw1_1_V_4)==0) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_TCP <= 1'h1&(3'd6==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_TCP_seq_num <= ((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_opcode <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd24);
LoEthernetEcho_magic_num <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
LoEthernetEcho_TCP_SYN_flag <= 1'h1&(2'd2==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
end
if (((32'hffffffff&TLEsw1_1_V_4)==0) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8!=
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8==
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8!=
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8==
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd7)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !LoEthernetEcho_opcode
&& (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !LoEthernetEcho_opcode
&& (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !(!LoEthernetEcho_opcode
) && (LoEthernetEcho_opcode!=3'd4) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4
)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !(!LoEthernetEcho_opcode
) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && !(!LoEthernetEcho_opcode) && (LoEthernetEcho_opcode
==3'd4) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd9)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if (((32'hffffffff&TLEsw1_1_V_4)!=0) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd7) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd8
) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd9) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd7)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !LoEthernetEcho_opcode
&& (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !LoEthernetEcho_opcode
&& (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !(!LoEthernetEcho_opcode
) && (LoEthernetEcho_opcode!=3'd4) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4
)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !(!LoEthernetEcho_opcode
) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && !(!LoEthernetEcho_opcode) && (LoEthernetEcho_opcode
==3'd4) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd9)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if (((32'hffffffff&TLEsw1_1_V_4)!=0) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd7) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd8
) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd9) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
end
4'd9: begin
if ((2'd2==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (1'd1!=(8'hff&8'd1+TLEca6_0_V_0)) && (2'd2!=(8'hff
&8'd1+TLEca6_0_V_0)) && (2'd3!=(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= 32'd0;
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((2'd3==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (3'd4==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[3'd4], 48'd0};
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((1'd1==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[1'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4<(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd10;
TLEsw1_1_V_20 <= 1'h1&(0==(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7
>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7
>>5'd16))>>5'd16))));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
end
6'd35: begin
if (!m_axis_tready && ((32'hffffffff&TLEsw1_1_V_10)>=32'd0)) begin
xpc10 <= 6'd37;
TLESe22_3_V_1 <= TLEsw1_1_V_10;
TLESe22_3_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
end
if (m_axis_tready && ((32'hffffffff&TLEsw1_1_V_10)>=32'd0)) begin
xpc10 <= 6'd37;
TLESe22_3_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_10==0);
m_axis_tkeep <= A_8_US_CC_SCALbx16_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLESe22_3_V_1 <= TLEsw1_1_V_10;
m_axis_tvalid <= 1'd1;
end
if (((32'hffffffff&TLEsw1_1_V_10)<32'd0)) begin
xpc10 <= 6'd36;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe22_3_V_1 <= TLEsw1_1_V_10;
TLESe22_3_V_0 <= 32'd0;
end
end
6'd36: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
TLEsw1_1_V_10 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_TCP_SYN_flag <= 1'd0;
LoEthernetEcho_proto_TCP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
end
endcase
if ((TLEsw1_1_V_10<32'd4))
case (xpc10)
4'd14: begin
xpc10 <= 4'd15;
TLEsw1_1_V_4 <= 32'd4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16)))+(TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16))>>5'd16);
end
6'd32: begin
xpc10 <= 6'd33;
LoEthernetEcho_tmp1 <= 64'h_ffff&32'h_ffff_ffff^LoEthernetEcho_chksum_UDP;
TLEsw1_1_V_4 <= 32'd4;
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
endcase
else
case (xpc10)
4'd14: begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'd4]>>5'd16);
TLEsw1_1_V_4 <= 32'd4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16)))+(TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16))>>5'd16);
end
6'd32: begin
xpc10 <= 6'd38;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'd4]>>5'd16);
TLEsw1_1_V_4 <= 32'd4;
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
endcase
case (xpc10)
3'd4: begin
xpc10 <= 3'd5;
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'd0];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_10 <= TLERe1_1_V_1;
TLERe1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
3'd6: begin
xpc10 <= 3'd7;
TLEsw1_1_V_15 <= 1'h1&LoEthernetEcho_proto_TCP;
TLEsw1_1_V_14 <= 1'h1&LoEthernetEcho_proto_ICMP;
TLEsw1_1_V_13 <= 1'h1&LoEthernetEcho_proto_UDP;
TLEsw1_1_V_12 <= 1'h1&LoEthernetEcho_IPv4;
end
3'd7: begin
if (TLEsw1_1_V_12 && TLEsw1_1_V_15) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[1'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1;
TLEca6_0_V_12 <= 32'd0;
TLEca6_0_V_7 <= 32'd0;
TLEca6_0_V_6 <= 32'd0;
end
if (TLEsw1_1_V_12 && !TLEsw1_1_V_15) xpc10 <= 6'd35;
if (!TLEsw1_1_V_12) xpc10 <= 6'd35;
end
4'd8: begin
xpc10 <= 4'd9;
TLEca6_0_V_7 <= (64'h_ffff&hprpin134910)+(hprpin134910>>5'd16);
TLEca6_0_V_6 <= (64'h_ffff&hprpin134410)+(hprpin134410>>5'd16);
end
4'd10: begin
xpc10 <= 4'd11;
LoEthernetEcho_tmp2 <= 64'd1536|{64'hffffffffffffffff&((64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length
>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}))>>4'd8)|{64'd255&64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec
+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}), 8'd0}, 32'd0};
LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp1 <= 64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length
, 8'd0});
end
4'd11: begin
xpc10 <= 4'd12;
TLEca6_46_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca6_46_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
end
4'd12: begin
xpc10 <= 4'd13;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca6_46_V_4+TLEca6_46_V_5)+(TLEca6_46_V_4
+TLEca6_46_V_5>>5'd16)))+(32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca6_46_V_4+TLEca6_46_V_5)+(TLEca6_46_V_4+TLEca6_46_V_5
>>5'd16))>>5'd16);
end
4'd13: begin
xpc10 <= 4'd14;
TLEca6_49_V_5 <= (64'h_ffff&hprpin142110)+(hprpin142110>>5'd16);
TLEca6_49_V_4 <= (64'h_ffff&hprpin141610)+(hprpin141610>>5'd16);
TLEca6_49_V_7 <= LoEthernetEcho_chksum_UDP;
end
4'd15: begin
if ((64'h_ffff==LoEthernetEcho_chksum_UDP) && LoEthernetEcho_TCP_SYN_flag && TLEsw1_1_V_20) begin
xpc10 <= 5'd16;
TLEsw15_4_V_2 <= 1'h1&TLEsw1_1_V_14;
TLEsw15_4_V_1 <= 1'h1&TLEsw1_1_V_13|TLEsw1_1_V_15;
A_64_US_CC_SCALbx14_ARC0[0] <= 64'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48'd0
};
end
if ((64'h_ffff!=LoEthernetEcho_chksum_UDP) && LoEthernetEcho_TCP_SYN_flag && TLEsw1_1_V_20) xpc10 <= 6'd35
;
if (LoEthernetEcho_TCP_SYN_flag && !TLEsw1_1_V_20) xpc10 <= 6'd35;
if (!LoEthernetEcho_TCP_SYN_flag) xpc10 <= 6'd35;
end
5'd16: begin
xpc10 <= 5'd17;
TLEsw15_4_V_0 <= (-64'h1_0000_0000&A_64_US_CC_SCALbx14_ARC0[1'd1])|(LoEthernetEcho_dst_mac>>5'd16);
end
5'd17: begin
xpc10 <= 5'd18;
A_64_US_CC_SCALbx14_ARC0[1'd1] <= 64'hffffffffffffffff&TLEsw15_4_V_0;
end
5'd18: begin
xpc10 <= 5'd19;
TLEsw15_4_V_0 <= (64'h_ffff&A_64_US_CC_SCALbx14_ARC0[2'd3])|{LoEthernetEcho_dst_ip, 16'd0}|{LoEthernetEcho_src_ip
, 48'd0};
end
5'd19: begin
xpc10 <= 5'd20;
A_64_US_CC_SCALbx14_ARC0[2'd3] <= 64'hffffffffffffffff&TLEsw15_4_V_0;
end
5'd20: begin
if (!TLEsw15_4_V_1 && TLEsw15_4_V_2) begin
xpc10 <= 5'd21;
TLEsw15_4_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3'd4])|(LoEthernetEcho_src_ip>>5'd16);
end
if (TLEsw15_4_V_1) begin
xpc10 <= 5'd21;
TLEsw15_4_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3'd4])|(LoEthernetEcho_src_ip>>5'd16)|
{LoEthernetEcho_app_src_port, 32'd0}|{LoEthernetEcho_app_dst_port, 16'd0};
end
if (!TLEsw15_4_V_1 && !TLEsw15_4_V_2) xpc10 <= 5'd21;
end
5'd21: begin
xpc10 <= 5'd22;
A_64_US_CC_SCALbx14_ARC0[3'd4] <= 64'hffffffffffffffff&TLEsw15_4_V_0;
end
5'd22: begin
xpc10 <= 5'd23;
LoEthernetEcho_tmp1 <= 32'd1+((LoEthernetEcho_TCP_seq_num>>5'd24)|((64'hff_0000&LoEthernetEcho_TCP_seq_num)>>4'd8
)|{64'h_ff00&LoEthernetEcho_TCP_seq_num, 8'd0}|{64'd255&LoEthernetEcho_TCP_seq_num, 24'd0});
LoEthernetEcho_chksum_UDP <= 32'd0;
end
5'd23: begin
xpc10 <= 5'd24;
LoEthernetEcho_tmp3 <= 64'hff_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
LoEthernetEcho_tmp2 <= 64'h_1400_0000_0000_0000|(64'hffffffffffffffff&((64'h_ff00&TLEsw1_1_V_19)>>4'd8)|{64'd255
&TLEsw1_1_V_19, 8'd0})|{64'hffffffffffffffff&(LoEthernetEcho_tmp1>>5'd24)|((64'hff_0000&LoEthernetEcho_tmp1)>>4'd8
)|{64'h_ff00&LoEthernetEcho_tmp1, 8'd0}|{64'd255&LoEthernetEcho_tmp1, 24'd0}, 16'd0};
LoEthernetEcho_tmp <= ((64'h_ff00&TLEsw1_1_V_19)>>4'd8)|{64'd255&TLEsw1_1_V_19, 8'd0};
LoEthernetEcho_TCP_seq_num <= (LoEthernetEcho_tmp1>>5'd24)|((64'hff_0000&LoEthernetEcho_tmp1)>>4'd8)|{64'h_ff00
&LoEthernetEcho_tmp1, 8'd0}|{64'd255&LoEthernetEcho_tmp1, 24'd0};
end
5'd24: begin
xpc10 <= 5'd25;
LoEthernetEcho_tmp3 <= LoEthernetEcho_tmp2|LoEthernetEcho_tmp3;
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2|LoEthernetEcho_tmp3;
end
5'd25: begin
xpc10 <= 5'd26;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff&A_64_US_CC_SCALbx14_ARC0[3'd4];
end
5'd26: begin
xpc10 <= 5'd27;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|(64'hffffffffffffffff&(64'hff_0000&TLEsw1_1_V_19)|(-64'h100_0000&TLEsw1_1_V_19
));
A_64_US_CC_SCALbx14_ARC0[3'd4] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|(64'hffffffffffffffff&(64'hff_0000&TLEsw1_1_V_19
)|(-64'h100_0000&TLEsw1_1_V_19));
end
5'd27: begin
xpc10 <= 5'd28;
LoEthernetEcho_tmp2 <= 64'd1536|{64'hffffffffffffffff&((64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length
>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}))>>4'd8)|{64'd255&64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec
+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}), 8'd0}, 32'd0};
LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp1 <= 64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length
, 8'd0});
end
5'd28: begin
xpc10 <= 5'd29;
TLEca15_166_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca15_166_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
end
5'd29: begin
xpc10 <= 5'd30;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca15_166_V_4+TLEca15_166_V_5
)+(TLEca15_166_V_4+TLEca15_166_V_5>>5'd16)))+(32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca15_166_V_4+TLEca15_166_V_5
)+(TLEca15_166_V_4+TLEca15_166_V_5>>5'd16))>>5'd16);
end
5'd30: begin
xpc10 <= 5'd31;
TLEca15_169_V_5 <= (64'h_ffff&hprpin142110)+(hprpin142110>>5'd16);
TLEca15_169_V_4 <= (64'h_ffff&hprpin141610)+(hprpin141610>>5'd16);
TLEca15_169_V_7 <= LoEthernetEcho_chksum_UDP;
end
5'd31: begin
xpc10 <= 6'd32;
LoEthernetEcho_tmp <= -64'h_ffff_0001&A_64_US_CC_SCALbx14_ARC0[3'd6];
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca15_169_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca15_169_V_4+TLEca15_169_V_5
)+(TLEca15_169_V_4+TLEca15_169_V_5>>5'd16)))+(TLEca15_169_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca15_169_V_4+
TLEca15_169_V_5)+(TLEca15_169_V_4+TLEca15_169_V_5>>5'd16))>>5'd16);
end
6'd33: begin
xpc10 <= 6'd34;
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx10_ARA0[0];
LoEthernetEcho_tmp2 <= (LoEthernetEcho_tmp1>>4'd8)|{64'd255&LoEthernetEcho_tmp1, 8'd0};
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|{64'hffffffffffffffff&(LoEthernetEcho_tmp1
>>4'd8)|{64'd255&LoEthernetEcho_tmp1, 8'd0}, 16'd0};
end
6'd34: begin
xpc10 <= 6'd35;
TLEsw1_1_V_19 <= 32'd1+TLEsw1_1_V_19;
A_64_US_CC_SCALbx10_ARA0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp3|{LoEthernetEcho_src_port, 24'd0}|{LoEthernetEcho_src_port
, 16'd0};
end
6'd37: begin
if ((TLESe22_3_V_1<TLESe22_3_V_0)) begin
xpc10 <= 6'd36;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
end
if (m_axis_tready && (TLESe22_3_V_1>=TLESe22_3_V_0)) begin
TLESe22_3_V_0 <= 32'd1+TLESe22_3_V_0;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLESe22_3_V_0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLESe22_3_V_0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_10==TLESe22_3_V_0);
m_axis_tkeep <= A_8_US_CC_SCALbx16_ARA0[8'h1*(32'hffffffff&TLESe22_3_V_0)];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLESe22_3_V_0];
end
end
6'd38: begin
xpc10 <= 6'd39;
TLEca19_5_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca19_5_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
TLEca19_5_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd39: begin
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4==(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd38;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4]>>5'd16);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5
)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+
TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4!=(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd38;
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5
)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+
TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd33;
LoEthernetEcho_tmp1 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff
&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff
&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16));
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5
)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+
TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16);
end
end
6'd40: begin
xpc10 <= 6'd41;
TLEca10_5_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca10_5_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
TLEca10_5_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd41: begin
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4==(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4]>>5'd16);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+TLEca10_5_V_5
)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16)))+(TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+
TLEca10_5_V_5)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4!=(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+TLEca10_5_V_5
)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16)))+(TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+
TLEca10_5_V_5)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 4'd15;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+TLEca10_5_V_5
)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16)))+(TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+
TLEca10_5_V_5)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16))>>5'd16);
end
end
endcase
end
end
assign hprpin134410 = (64'hffffffffffffffff&{64'd255&TLEca6_0_V_1, 8'd0}|((64'h_ff00&TLEca6_0_V_1)>>4'd8))+(64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>5'd16
), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>5'd16))>>4'd8));
assign hprpin134910 = (64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>6'd32), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd32))>>4'd8))+(64'hffffffffffffffff&{64'd255
&(TLEca6_0_V_1>>6'd48), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd48))>>4'd8));
assign hprpin139510 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp2, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp2)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>5'd16))>>4'd8));
assign hprpin140010 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp2>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd48))>>4'd8));
assign hprpin141610 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp>>5'd16))>>4'd8));
assign hprpin142110 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp>>6'd48))>>4'd8));
endmodule | module EthernetEcho( input [63:0] s_axis_tdata,
input [7:0] s_axis_tkeep,
input s_axis_tlast,
input s_axis_tvalid,
output reg s_axis_tready,
input [63:0] s_axis_tuser_hi,
input [63:0] s_axis_tuser_low,
output reg [63:0] m_axis_tdata,
output reg [7:0] m_axis_tkeep,
output reg m_axis_tlast,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tuser_hi,
output reg [63:0] m_axis_tuser_low,
input cam_busy,
input cam_match,
input [7:0] cam_match_addr,
output reg [63:0] cam_cmp_din,
output reg [63:0] cam_din,
output reg cam_we,
output reg [7:0] cam_wr_addr,
input clk,
input reset); |
reg LoEthernetEcho_IPv4;
reg LoEthernetEcho_proto_UDP;
reg LoEthernetEcho_proto_ICMP;
reg LoEthernetEcho_proto_TCP;
reg LoEthernetEcho_TCP_SYN_flag;
reg [63:0] LoEthernetEcho_chksum_UDP;
reg [63:0] TLEsw1_1_V_2;
reg [63:0] TLEsw1_1_V_3;
reg [31:0] TLEsw1_1_V_4;
reg [31:0] TLEsw1_1_V_10;
reg TLEsw1_1_V_12;
reg TLEsw1_1_V_13;
reg TLEsw1_1_V_14;
reg TLEsw1_1_V_15;
reg [31:0] TLEsw1_1_V_19;
reg TLEsw1_1_V_20;
reg [31:0] TLERe1_1_V_0;
reg [31:0] TLERe1_1_V_1;
reg TLERe1_1_V_3;
reg [63:0] TLERe1_1_V_5;
reg [7:0] TLERe1_1_V_6;
reg [7:0] TLEca6_0_V_0;
reg [63:0] TLEca6_0_V_1;
reg [63:0] TLEca6_0_V_6;
reg [63:0] TLEca6_0_V_7;
reg [63:0] TLEca6_0_V_12;
reg [63:0] TLEca6_46_V_4;
reg [63:0] TLEca6_46_V_5;
reg [63:0] TLEca6_49_V_4;
reg [63:0] TLEca6_49_V_5;
reg [63:0] TLEca6_49_V_7;
reg [63:0] TLEca10_5_V_4;
reg [63:0] TLEca10_5_V_5;
reg [63:0] TLEca10_5_V_7;
reg [63:0] TLEsw15_4_V_0;
reg TLEsw15_4_V_1;
reg TLEsw15_4_V_2;
reg [63:0] TLEca15_166_V_4;
reg [63:0] TLEca15_166_V_5;
reg [63:0] TLEca15_169_V_4;
reg [63:0] TLEca15_169_V_5;
reg [63:0] TLEca15_169_V_7;
reg [63:0] TLEca19_5_V_4;
reg [63:0] TLEca19_5_V_5;
reg [63:0] TLEca19_5_V_7;
reg [31:0] TLESe22_3_V_0;
reg [31:0] TLESe22_3_V_1;
reg [7:0] LoEthernetEcho_magic_num;
reg [7:0] LoEthernetEcho_opcode;
reg [63:0] LoEthernetEcho_IP_total_length;
reg [63:0] LoEthernetEcho_tmp1;
reg [63:0] LoEthernetEcho_src_ip;
reg [63:0] LoEthernetEcho_dst_ip;
reg [63:0] LoEthernetEcho_tmp;
reg [63:0] LoEthernetEcho_tmp2;
reg [63:0] LoEthernetEcho_dst_mac;
reg [63:0] LoEthernetEcho_src_mac;
reg [63:0] LoEthernetEcho_app_src_port;
reg [63:0] LoEthernetEcho_app_dst_port;
reg [63:0] LoEthernetEcho_TCP_seq_num;
reg [63:0] LoEthernetEcho_tmp3;
reg [63:0] LoEthernetEcho_src_port;
reg [7:0] A_8_US_CC_SCALbx16_ARA0[255:0];
reg [63:0] A_64_US_CC_SCALbx10_ARA0[255:0];
reg [63:0] A_64_US_CC_SCALbx12_ARB0[255:0];
reg [63:0] A_64_US_CC_SCALbx14_ARC0[255:0];
reg [5:0] xpc10;
wire [63:0] hprpin134410;
wire [63:0] hprpin134910;
wire [63:0] hprpin139510;
wire [63:0] hprpin140010;
wire [63:0] hprpin141610;
wire [63:0] hprpin142110;
always @(posedge clk ) begin
if (reset) begin
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 64'd0;
cam_cmp_din <= 64'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 64'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd0;
LoEthernetEcho_opcode <= 8'd0;
LoEthernetEcho_magic_num <= 8'd0;
LoEthernetEcho_app_dst_port <= 64'd0;
LoEthernetEcho_app_src_port <= 64'd0;
LoEthernetEcho_dst_ip <= 64'd0;
LoEthernetEcho_src_ip <= 64'd0;
LoEthernetEcho_IP_total_length <= 64'd0;
TLEsw1_1_V_3 <= 64'd0;
TLEsw1_1_V_2 <= 64'd0;
LoEthernetEcho_src_port <= 64'd0;
LoEthernetEcho_src_mac <= 64'd0;
LoEthernetEcho_dst_mac <= 64'd0;
TLEsw1_1_V_15 <= 1'd0;
TLEsw1_1_V_14 <= 1'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEca6_0_V_7 <= 64'd0;
TLEca6_0_V_6 <= 64'd0;
TLEsw1_1_V_20 <= 1'd0;
TLEca6_0_V_1 <= 64'd0;
TLEca6_0_V_0 <= 8'd0;
TLEca6_0_V_12 <= 64'd0;
TLEca6_46_V_5 <= 64'd0;
TLEca6_46_V_4 <= 64'd0;
TLEca6_49_V_5 <= 64'd0;
TLEca6_49_V_4 <= 64'd0;
TLEca6_49_V_7 <= 64'd0;
TLEsw15_4_V_2 <= 1'd0;
TLEsw15_4_V_1 <= 1'd0;
TLEsw15_4_V_0 <= 64'd0;
LoEthernetEcho_TCP_seq_num <= 64'd0;
TLEca15_166_V_5 <= 64'd0;
TLEca15_166_V_4 <= 64'd0;
TLEca15_169_V_5 <= 64'd0;
TLEca15_169_V_4 <= 64'd0;
TLEca15_169_V_7 <= 64'd0;
LoEthernetEcho_tmp <= 64'd0;
LoEthernetEcho_tmp3 <= 64'd0;
TLEsw1_1_V_19 <= 32'd0;
TLESe22_3_V_1 <= 32'd0;
s_axis_tready <= 1'd0;
TLEsw1_1_V_10 <= 32'd0;
LoEthernetEcho_TCP_SYN_flag <= 1'd0;
LoEthernetEcho_proto_TCP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe22_3_V_0 <= 32'd0;
m_axis_tuser_low <= 64'd0;
m_axis_tuser_hi <= 64'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 64'd0;
TLEca19_5_V_5 <= 64'd0;
TLEca19_5_V_4 <= 64'd0;
TLEca19_5_V_7 <= 64'd0;
LoEthernetEcho_tmp1 <= 64'd0;
TLEca10_5_V_5 <= 64'd0;
TLEca10_5_V_4 <= 64'd0;
TLEca10_5_V_7 <= 64'd0;
xpc10 <= 6'd0;
LoEthernetEcho_tmp2 <= 64'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 64'd0;
end
else begin
case (xpc10)
0: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
TLEsw1_1_V_19 <= 32'd100;
TLEsw1_1_V_20 <= 1'd0;
TLEsw1_1_V_15 <= 1'd0;
TLEsw1_1_V_14 <= 1'd0;
TLEsw1_1_V_13 <= 1'd0;
TLEsw1_1_V_12 <= 1'd0;
TLEsw1_1_V_10 <= 32'd0;
TLEsw1_1_V_4 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_TCP_SYN_flag <= 1'd0;
LoEthernetEcho_proto_TCP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
cam_wr_addr <= 8'd0;
cam_we <= 1'd0;
cam_din <= 32'd0;
cam_cmp_din <= 32'h_ffff_ffff;
end
1'd1: begin
if (s_axis_tvalid && s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast) begin
xpc10 <= 2'd2;
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= 32'd0;
TLERe1_1_V_0 <= 32'd1;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
A_64_US_CC_SCALbx10_ARA0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'd0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'd0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'd0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!s_axis_tvalid) begin
xpc10 <= 2'd2;
TLERe1_1_V_3 <= 1'd1;
TLERe1_1_V_0 <= 32'd0;
TLERe1_1_V_6 <= 8'd0;
TLERe1_1_V_5 <= 32'd0;
TLERe1_1_V_1 <= 32'd0;
end
end
2'd2: begin
if (s_axis_tvalid && s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd0;
TLERe1_1_V_3 <= 1'd0;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (s_axis_tvalid && !s_axis_tlast && TLERe1_1_V_3) begin
s_axis_tready <= 1'd1;
TLERe1_1_V_3 <= 1'h1&s_axis_tvalid;
TLERe1_1_V_1 <= TLERe1_1_V_0;
TLERe1_1_V_0 <= 32'd1+(32'hffffffff&TLERe1_1_V_0);
A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_low;
A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tuser_hi;
A_8_US_CC_SCALbx16_ARA0[32'hffffffff&TLERe1_1_V_0] <= 8'hff&s_axis_tkeep;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_0] <= 64'hffffffffffffffff&s_axis_tdata;
end
if (!TLERe1_1_V_3) begin
xpc10 <= 2'd3;
TLERe1_1_V_6 <= A_8_US_CC_SCALbx16_ARA0[8'h1*(32'hffffffff&TLERe1_1_V_1)];
TLERe1_1_V_5 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1];
end
end
2'd3: begin
case (TLERe1_1_V_6)
1'd1: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'd255&TLERe1_1_V_5;
end
2'd3: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff&TLERe1_1_V_5;
end
3'd7: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff&TLERe1_1_V_5;
end
4'd15: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&32'h_ffff_ffff&TLERe1_1_V_5
;
end
5'd31: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff&TLERe1_1_V_5
;
end
6'd63: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'h_ffff_ffff_ffff&TLERe1_1_V_5
;
end
7'd127: begin
xpc10 <= 3'd4;
A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLERe1_1_V_1] <= 64'hffffffffffffffff&64'hff_ffff_ffff_ffff&TLERe1_1_V_5
;
end
endcase
if ((TLERe1_1_V_6!=3'd7) && (TLERe1_1_V_6!=4'd15) && (TLERe1_1_V_6!=5'd31) && (TLERe1_1_V_6
!=6'd63) && (TLERe1_1_V_6!=7'd127) && (TLERe1_1_V_6!=1'd1) && (TLERe1_1_V_6!=2'd2) &&
(TLERe1_1_V_6!=2'd3)) xpc10 <= 3'd4;
if ((TLERe1_1_V_6==2'd2)) xpc10 <= 3'd4;
end
3'd5: begin
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_TCP <= 1'h1&(3'd6==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_TCP_seq_num <= ((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_opcode <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd24);
LoEthernetEcho_magic_num <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
LoEthernetEcho_TCP_SYN_flag <= 1'h1&(2'd2==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
end
if (((32'hffffffff&TLEsw1_1_V_4)==0) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd2)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IP_total_length <= 64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
LoEthernetEcho_proto_TCP <= 1'h1&(3'd6==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
LoEthernetEcho_proto_UDP <= 1'h1&(5'd17==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
LoEthernetEcho_proto_ICMP <= 1'h1&(1'd1==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56)));
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd4)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_TCP_seq_num <= ((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_app_dst_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32);
LoEthernetEcho_app_src_port <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_dst_ip <= LoEthernetEcho_dst_ip|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0};
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd5)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_opcode <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd24);
LoEthernetEcho_magic_num <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
LoEthernetEcho_TCP_seq_num <= LoEthernetEcho_TCP_seq_num|{64'h_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
LoEthernetEcho_TCP_SYN_flag <= 1'h1&(2'd2==(64'd255&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd56
)));
end
if (((32'hffffffff&TLEsw1_1_V_4)==0) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_src_port <= 64'd255&((64'hffffffffffffffff&TLEsw1_1_V_3)>>5'd16);
LoEthernetEcho_src_mac <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_dst_mac <= 64'h_ffff_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2;
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8!=
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8==
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8!=
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'd0;
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==1'd1) && (4'd8==
(64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd32)))) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_IPv4 <= 1'h1&(3'd4==(64'd15&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd52)));
LoEthernetEcho_src_mac <= LoEthernetEcho_src_mac|{32'h_ffff_ffff&64'hffffffffffffffff&TLEsw1_1_V_2, 16'd0
};
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==2'd3)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_dst_ip <= 64'h_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>6'd48);
LoEthernetEcho_src_ip <= 32'h_ffff_ffff&((64'hffffffffffffffff&TLEsw1_1_V_2)>>5'd16);
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd7)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !LoEthernetEcho_opcode
&& (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !LoEthernetEcho_opcode
&& (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !(!LoEthernetEcho_opcode
) && (LoEthernetEcho_opcode!=3'd4) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4
)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !(!LoEthernetEcho_opcode
) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && !(!LoEthernetEcho_opcode) && (LoEthernetEcho_opcode
==3'd4) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd9)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10>=(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if (((32'hffffffff&TLEsw1_1_V_4)!=0) && (4'd10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd7) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd8
) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd9) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd10)) begin
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd6)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==3'd7)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !LoEthernetEcho_opcode
&& (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !LoEthernetEcho_opcode
&& (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && !(!LoEthernetEcho_opcode
) && (LoEthernetEcho_opcode!=3'd4) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4
)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && !(!LoEthernetEcho_opcode
) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && !(!LoEthernetEcho_opcode) && (LoEthernetEcho_opcode
==3'd4) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd8)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd9)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd9)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num!=8'd128) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)==4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode!=1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if ((LoEthernetEcho_magic_num==8'd128) && (LoEthernetEcho_opcode==1'd1) && (4'd10<(32'hffffffff
&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff&TLEsw1_1_V_4)==4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
if (((32'hffffffff&TLEsw1_1_V_4)!=0) && (4'd10<(32'hffffffff&32'd1+TLEsw1_1_V_4)) && ((32'hffffffff
&TLEsw1_1_V_4)!=1'd1) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd2) && ((32'hffffffff&TLEsw1_1_V_4)!=2'd3
) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd4) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd5) && ((32'hffffffff
&TLEsw1_1_V_4)!=3'd6) && ((32'hffffffff&TLEsw1_1_V_4)!=3'd7) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd8
) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd9) && ((32'hffffffff&TLEsw1_1_V_4)!=4'd10)) begin
xpc10 <= 3'd6;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
end
end
4'd9: begin
if ((2'd2==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (1'd1!=(8'hff&8'd1+TLEca6_0_V_0)) && (2'd2!=(8'hff
&8'd1+TLEca6_0_V_0)) && (2'd3!=(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= 32'd0;
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((2'd3==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= A_64_US_CC_SCALbx14_ARC0[8'hff&8'd1+TLEca6_0_V_0];
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4>=(8'hff&8'd1+TLEca6_0_V_0)) && (3'd4==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= {A_64_US_CC_SCALbx14_ARC0[3'd4], 48'd0};
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((1'd1==(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[1'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
TLEca6_0_V_12 <= (64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+
(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7
)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16);
end
if ((3'd4<(8'hff&8'd1+TLEca6_0_V_0))) begin
xpc10 <= 4'd10;
TLEsw1_1_V_20 <= 1'h1&(0==(64'hffffffffffffffff&64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7
>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7
>>5'd16))>>5'd16))));
TLEca6_0_V_12 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16)))+(TLEca6_0_V_12+(64'hffffffffffffffff
&(64'h_ffff&TLEca6_0_V_6+TLEca6_0_V_7)+(TLEca6_0_V_6+TLEca6_0_V_7>>5'd16))>>5'd16));
TLEca6_0_V_0 <= 8'd1+TLEca6_0_V_0;
end
end
6'd35: begin
if (!m_axis_tready && ((32'hffffffff&TLEsw1_1_V_10)>=32'd0)) begin
xpc10 <= 6'd37;
TLESe22_3_V_1 <= TLEsw1_1_V_10;
TLESe22_3_V_0 <= 32'd0;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd1;
end
if (m_axis_tready && ((32'hffffffff&TLEsw1_1_V_10)>=32'd0)) begin
xpc10 <= 6'd37;
TLESe22_3_V_0 <= 32'd1;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'd0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'd0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_10==0);
m_axis_tkeep <= A_8_US_CC_SCALbx16_ARA0[8'd0];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLESe22_3_V_1 <= TLEsw1_1_V_10;
m_axis_tvalid <= 1'd1;
end
if (((32'hffffffff&TLEsw1_1_V_10)<32'd0)) begin
xpc10 <= 6'd36;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
TLESe22_3_V_1 <= TLEsw1_1_V_10;
TLESe22_3_V_0 <= 32'd0;
end
end
6'd36: begin
xpc10 <= 1'd1;
s_axis_tready <= 1'd1;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tvalid <= 1'd0;
m_axis_tlast <= 1'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
TLEsw1_1_V_10 <= 32'd0;
LoEthernetEcho_chksum_UDP <= 32'd0;
LoEthernetEcho_TCP_SYN_flag <= 1'd0;
LoEthernetEcho_proto_TCP <= 1'd0;
LoEthernetEcho_proto_ICMP <= 1'd0;
LoEthernetEcho_proto_UDP <= 1'd0;
LoEthernetEcho_IPv4 <= 1'd0;
end
endcase
if ((TLEsw1_1_V_10<32'd4))
case (xpc10)
4'd14: begin
xpc10 <= 4'd15;
TLEsw1_1_V_4 <= 32'd4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16)))+(TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16))>>5'd16);
end
6'd32: begin
xpc10 <= 6'd33;
LoEthernetEcho_tmp1 <= 64'h_ffff&32'h_ffff_ffff^LoEthernetEcho_chksum_UDP;
TLEsw1_1_V_4 <= 32'd4;
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
endcase
else
case (xpc10)
4'd14: begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'd4]>>5'd16);
TLEsw1_1_V_4 <= 32'd4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16)))+(TLEca6_49_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca6_49_V_4+TLEca6_49_V_5
)+(TLEca6_49_V_4+TLEca6_49_V_5>>5'd16))>>5'd16);
end
6'd32: begin
xpc10 <= 6'd38;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'd4]>>5'd16);
TLEsw1_1_V_4 <= 32'd4;
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&LoEthernetEcho_tmp;
end
endcase
case (xpc10)
3'd4: begin
xpc10 <= 3'd5;
TLEsw1_1_V_3 <= A_64_US_CC_SCALbx10_ARA0[32'd0];
TLEsw1_1_V_2 <= A_64_US_CC_SCALbx14_ARC0[32'd0];
TLEsw1_1_V_4 <= 32'd0;
TLEsw1_1_V_10 <= TLERe1_1_V_1;
TLERe1_1_V_0 <= 32'd0;
s_axis_tready <= 1'd0;
end
3'd6: begin
xpc10 <= 3'd7;
TLEsw1_1_V_15 <= 1'h1&LoEthernetEcho_proto_TCP;
TLEsw1_1_V_14 <= 1'h1&LoEthernetEcho_proto_ICMP;
TLEsw1_1_V_13 <= 1'h1&LoEthernetEcho_proto_UDP;
TLEsw1_1_V_12 <= 1'h1&LoEthernetEcho_IPv4;
end
3'd7: begin
if (TLEsw1_1_V_12 && TLEsw1_1_V_15) begin
xpc10 <= 4'd8;
TLEca6_0_V_1 <= (A_64_US_CC_SCALbx14_ARC0[1'd1]>>6'd48);
TLEca6_0_V_0 <= 8'd1;
TLEca6_0_V_12 <= 32'd0;
TLEca6_0_V_7 <= 32'd0;
TLEca6_0_V_6 <= 32'd0;
end
if (TLEsw1_1_V_12 && !TLEsw1_1_V_15) xpc10 <= 6'd35;
if (!TLEsw1_1_V_12) xpc10 <= 6'd35;
end
4'd8: begin
xpc10 <= 4'd9;
TLEca6_0_V_7 <= (64'h_ffff&hprpin134910)+(hprpin134910>>5'd16);
TLEca6_0_V_6 <= (64'h_ffff&hprpin134410)+(hprpin134410>>5'd16);
end
4'd10: begin
xpc10 <= 4'd11;
LoEthernetEcho_tmp2 <= 64'd1536|{64'hffffffffffffffff&((64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length
>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}))>>4'd8)|{64'd255&64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec
+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}), 8'd0}, 32'd0};
LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp1 <= 64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length
, 8'd0});
end
4'd11: begin
xpc10 <= 4'd12;
TLEca6_46_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca6_46_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
end
4'd12: begin
xpc10 <= 4'd13;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca6_46_V_4+TLEca6_46_V_5)+(TLEca6_46_V_4
+TLEca6_46_V_5>>5'd16)))+(32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca6_46_V_4+TLEca6_46_V_5)+(TLEca6_46_V_4+TLEca6_46_V_5
>>5'd16))>>5'd16);
end
4'd13: begin
xpc10 <= 4'd14;
TLEca6_49_V_5 <= (64'h_ffff&hprpin142110)+(hprpin142110>>5'd16);
TLEca6_49_V_4 <= (64'h_ffff&hprpin141610)+(hprpin141610>>5'd16);
TLEca6_49_V_7 <= LoEthernetEcho_chksum_UDP;
end
4'd15: begin
if ((64'h_ffff==LoEthernetEcho_chksum_UDP) && LoEthernetEcho_TCP_SYN_flag && TLEsw1_1_V_20) begin
xpc10 <= 5'd16;
TLEsw15_4_V_2 <= 1'h1&TLEsw1_1_V_14;
TLEsw15_4_V_1 <= 1'h1&TLEsw1_1_V_13|TLEsw1_1_V_15;
A_64_US_CC_SCALbx14_ARC0[0] <= 64'hffffffffffffffff&LoEthernetEcho_src_mac|{LoEthernetEcho_dst_mac, 48'd0
};
end
if ((64'h_ffff!=LoEthernetEcho_chksum_UDP) && LoEthernetEcho_TCP_SYN_flag && TLEsw1_1_V_20) xpc10 <= 6'd35
;
if (LoEthernetEcho_TCP_SYN_flag && !TLEsw1_1_V_20) xpc10 <= 6'd35;
if (!LoEthernetEcho_TCP_SYN_flag) xpc10 <= 6'd35;
end
5'd16: begin
xpc10 <= 5'd17;
TLEsw15_4_V_0 <= (-64'h1_0000_0000&A_64_US_CC_SCALbx14_ARC0[1'd1])|(LoEthernetEcho_dst_mac>>5'd16);
end
5'd17: begin
xpc10 <= 5'd18;
A_64_US_CC_SCALbx14_ARC0[1'd1] <= 64'hffffffffffffffff&TLEsw15_4_V_0;
end
5'd18: begin
xpc10 <= 5'd19;
TLEsw15_4_V_0 <= (64'h_ffff&A_64_US_CC_SCALbx14_ARC0[2'd3])|{LoEthernetEcho_dst_ip, 16'd0}|{LoEthernetEcho_src_ip
, 48'd0};
end
5'd19: begin
xpc10 <= 5'd20;
A_64_US_CC_SCALbx14_ARC0[2'd3] <= 64'hffffffffffffffff&TLEsw15_4_V_0;
end
5'd20: begin
if (!TLEsw15_4_V_1 && TLEsw15_4_V_2) begin
xpc10 <= 5'd21;
TLEsw15_4_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3'd4])|(LoEthernetEcho_src_ip>>5'd16);
end
if (TLEsw15_4_V_1) begin
xpc10 <= 5'd21;
TLEsw15_4_V_0 <= (-64'h1_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3'd4])|(LoEthernetEcho_src_ip>>5'd16)|
{LoEthernetEcho_app_src_port, 32'd0}|{LoEthernetEcho_app_dst_port, 16'd0};
end
if (!TLEsw15_4_V_1 && !TLEsw15_4_V_2) xpc10 <= 5'd21;
end
5'd21: begin
xpc10 <= 5'd22;
A_64_US_CC_SCALbx14_ARC0[3'd4] <= 64'hffffffffffffffff&TLEsw15_4_V_0;
end
5'd22: begin
xpc10 <= 5'd23;
LoEthernetEcho_tmp1 <= 32'd1+((LoEthernetEcho_TCP_seq_num>>5'd24)|((64'hff_0000&LoEthernetEcho_TCP_seq_num)>>4'd8
)|{64'h_ff00&LoEthernetEcho_TCP_seq_num, 8'd0}|{64'd255&LoEthernetEcho_TCP_seq_num, 24'd0});
LoEthernetEcho_chksum_UDP <= 32'd0;
end
5'd23: begin
xpc10 <= 5'd24;
LoEthernetEcho_tmp3 <= 64'hff_0000_0000_0000&A_64_US_CC_SCALbx14_ARC0[3'd5];
LoEthernetEcho_tmp2 <= 64'h_1400_0000_0000_0000|(64'hffffffffffffffff&((64'h_ff00&TLEsw1_1_V_19)>>4'd8)|{64'd255
&TLEsw1_1_V_19, 8'd0})|{64'hffffffffffffffff&(LoEthernetEcho_tmp1>>5'd24)|((64'hff_0000&LoEthernetEcho_tmp1)>>4'd8
)|{64'h_ff00&LoEthernetEcho_tmp1, 8'd0}|{64'd255&LoEthernetEcho_tmp1, 24'd0}, 16'd0};
LoEthernetEcho_tmp <= ((64'h_ff00&TLEsw1_1_V_19)>>4'd8)|{64'd255&TLEsw1_1_V_19, 8'd0};
LoEthernetEcho_TCP_seq_num <= (LoEthernetEcho_tmp1>>5'd24)|((64'hff_0000&LoEthernetEcho_tmp1)>>4'd8)|{64'h_ff00
&LoEthernetEcho_tmp1, 8'd0}|{64'd255&LoEthernetEcho_tmp1, 24'd0};
end
5'd24: begin
xpc10 <= 5'd25;
LoEthernetEcho_tmp3 <= LoEthernetEcho_tmp2|LoEthernetEcho_tmp3;
A_64_US_CC_SCALbx14_ARC0[3'd5] <= 64'hffffffffffffffff&LoEthernetEcho_tmp2|LoEthernetEcho_tmp3;
end
5'd25: begin
xpc10 <= 5'd26;
LoEthernetEcho_tmp <= 64'h_ffff_ffff_ffff&A_64_US_CC_SCALbx14_ARC0[3'd4];
end
5'd26: begin
xpc10 <= 5'd27;
LoEthernetEcho_tmp <= LoEthernetEcho_tmp|(64'hffffffffffffffff&(64'hff_0000&TLEsw1_1_V_19)|(-64'h100_0000&TLEsw1_1_V_19
));
A_64_US_CC_SCALbx14_ARC0[3'd4] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|(64'hffffffffffffffff&(64'hff_0000&TLEsw1_1_V_19
)|(-64'h100_0000&TLEsw1_1_V_19));
end
5'd27: begin
xpc10 <= 5'd28;
LoEthernetEcho_tmp2 <= 64'd1536|{64'hffffffffffffffff&((64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length
>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}))>>4'd8)|{64'd255&64'hffffffffffffffff&64'h_ffff_ffff_ffff_ffec
+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length, 8'd0}), 8'd0}, 32'd0};
LoEthernetEcho_tmp <= LoEthernetEcho_dst_ip|{LoEthernetEcho_src_ip, 32'd0};
LoEthernetEcho_tmp1 <= 64'h_ffff_ffff_ffff_ffec+((LoEthernetEcho_IP_total_length>>4'd8)|{64'd255&LoEthernetEcho_IP_total_length
, 8'd0});
end
5'd28: begin
xpc10 <= 5'd29;
TLEca15_166_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca15_166_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
end
5'd29: begin
xpc10 <= 5'd30;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca15_166_V_4+TLEca15_166_V_5
)+(TLEca15_166_V_4+TLEca15_166_V_5>>5'd16)))+(32'd0+(64'hffffffffffffffff&(64'h_ffff&TLEca15_166_V_4+TLEca15_166_V_5
)+(TLEca15_166_V_4+TLEca15_166_V_5>>5'd16))>>5'd16);
end
5'd30: begin
xpc10 <= 5'd31;
TLEca15_169_V_5 <= (64'h_ffff&hprpin142110)+(hprpin142110>>5'd16);
TLEca15_169_V_4 <= (64'h_ffff&hprpin141610)+(hprpin141610>>5'd16);
TLEca15_169_V_7 <= LoEthernetEcho_chksum_UDP;
end
5'd31: begin
xpc10 <= 6'd32;
LoEthernetEcho_tmp <= -64'h_ffff_0001&A_64_US_CC_SCALbx14_ARC0[3'd6];
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca15_169_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca15_169_V_4+TLEca15_169_V_5
)+(TLEca15_169_V_4+TLEca15_169_V_5>>5'd16)))+(TLEca15_169_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca15_169_V_4+
TLEca15_169_V_5)+(TLEca15_169_V_4+TLEca15_169_V_5>>5'd16))>>5'd16);
end
6'd33: begin
xpc10 <= 6'd34;
LoEthernetEcho_tmp3 <= A_64_US_CC_SCALbx10_ARA0[0];
LoEthernetEcho_tmp2 <= (LoEthernetEcho_tmp1>>4'd8)|{64'd255&LoEthernetEcho_tmp1, 8'd0};
A_64_US_CC_SCALbx14_ARC0[3'd6] <= 64'hffffffffffffffff&LoEthernetEcho_tmp|{64'hffffffffffffffff&(LoEthernetEcho_tmp1
>>4'd8)|{64'd255&LoEthernetEcho_tmp1, 8'd0}, 16'd0};
end
6'd34: begin
xpc10 <= 6'd35;
TLEsw1_1_V_19 <= 32'd1+TLEsw1_1_V_19;
A_64_US_CC_SCALbx10_ARA0[0] <= 64'hffffffffffffffff&LoEthernetEcho_tmp3|{LoEthernetEcho_src_port, 24'd0}|{LoEthernetEcho_src_port
, 16'd0};
end
6'd37: begin
if ((TLESe22_3_V_1<TLESe22_3_V_0)) begin
xpc10 <= 6'd36;
m_axis_tuser_low <= 32'd0;
m_axis_tuser_hi <= 32'd0;
m_axis_tkeep <= 8'd0;
m_axis_tdata <= 32'd0;
m_axis_tlast <= 1'd0;
m_axis_tvalid <= 1'd0;
end
if (m_axis_tready && (TLESe22_3_V_1>=TLESe22_3_V_0)) begin
TLESe22_3_V_0 <= 32'd1+TLESe22_3_V_0;
m_axis_tuser_low <= A_64_US_CC_SCALbx10_ARA0[32'hffffffff&TLESe22_3_V_0];
m_axis_tuser_hi <= A_64_US_CC_SCALbx12_ARB0[32'hffffffff&TLESe22_3_V_0];
m_axis_tlast <= 1'h1&(TLEsw1_1_V_10==TLESe22_3_V_0);
m_axis_tkeep <= A_8_US_CC_SCALbx16_ARA0[8'h1*(32'hffffffff&TLESe22_3_V_0)];
m_axis_tdata <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&TLESe22_3_V_0];
end
end
6'd38: begin
xpc10 <= 6'd39;
TLEca19_5_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca19_5_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
TLEca19_5_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd39: begin
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4==(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd38;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4]>>5'd16);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5
)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+
TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4!=(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd38;
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5
)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+
TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd33;
LoEthernetEcho_tmp1 <= 64'h_ffff&32'h_ffff_ffff^(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff
&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff
&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16));
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+TLEca19_5_V_5
)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16)))+(TLEca19_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca19_5_V_4+
TLEca19_5_V_5)+(TLEca19_5_V_4+TLEca19_5_V_5>>5'd16))>>5'd16);
end
end
6'd40: begin
xpc10 <= 6'd41;
TLEca10_5_V_5 <= (64'h_ffff&hprpin140010)+(hprpin140010>>5'd16);
TLEca10_5_V_4 <= (64'h_ffff&hprpin139510)+(hprpin139510>>5'd16);
TLEca10_5_V_7 <= LoEthernetEcho_chksum_UDP;
end
6'd41: begin
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4==(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= (A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4]>>5'd16);
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+TLEca10_5_V_5
)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16)))+(TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+
TLEca10_5_V_5)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10>=(32'hffffffff&32'd1+TLEsw1_1_V_4)) && (3'd4!=(32'hffffffff&32'd1+TLEsw1_1_V_4
))) begin
xpc10 <= 6'd40;
LoEthernetEcho_tmp2 <= A_64_US_CC_SCALbx14_ARC0[32'hffffffff&32'd1+TLEsw1_1_V_4];
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+TLEca10_5_V_5
)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16)))+(TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+
TLEca10_5_V_5)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16))>>5'd16);
end
if ((TLEsw1_1_V_10<(32'hffffffff&32'd1+TLEsw1_1_V_4))) begin
xpc10 <= 4'd15;
TLEsw1_1_V_4 <= 32'd1+TLEsw1_1_V_4;
LoEthernetEcho_chksum_UDP <= (64'h_ffff&TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+TLEca10_5_V_5
)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16)))+(TLEca10_5_V_7+(64'hffffffffffffffff&(64'h_ffff&TLEca10_5_V_4+
TLEca10_5_V_5)+(TLEca10_5_V_4+TLEca10_5_V_5>>5'd16))>>5'd16);
end
end
endcase
end
end
assign hprpin134410 = (64'hffffffffffffffff&{64'd255&TLEca6_0_V_1, 8'd0}|((64'h_ff00&TLEca6_0_V_1)>>4'd8))+(64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>5'd16
), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>5'd16))>>4'd8));
assign hprpin134910 = (64'hffffffffffffffff&{64'd255&(TLEca6_0_V_1>>6'd32), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd32))>>4'd8))+(64'hffffffffffffffff&{64'd255
&(TLEca6_0_V_1>>6'd48), 8'd0}|((64'h_ff00&(TLEca6_0_V_1>>6'd48))>>4'd8));
assign hprpin139510 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp2, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp2)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>5'd16))>>4'd8));
assign hprpin140010 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp2>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp2>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp2>>6'd48))>>4'd8));
assign hprpin141610 = (64'hffffffffffffffff&{64'd255&LoEthernetEcho_tmp, 8'd0}|((64'h_ff00&LoEthernetEcho_tmp)>>4'd8))+(64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp
>>5'd16), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp>>5'd16))>>4'd8));
assign hprpin142110 = (64'hffffffffffffffff&{64'd255&(LoEthernetEcho_tmp>>6'd32), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp>>6'd32))>>4'd8))+(64'hffffffffffffffff
&{64'd255&(LoEthernetEcho_tmp>>6'd48), 8'd0}|((64'h_ff00&(LoEthernetEcho_tmp>>6'd48))>>4'd8));
endmodule | 3 |
142,107 | data/full_repos/permissive/9705033/common/basics.v | 9,705,033 | basics.v | v | 134 | 80 | [] | ['general public license', 'free software foundation'] | [] | [(21, 36), (39, 69), (72, 83), (86, 96), (99, 116), (119, 133)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:112: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:113: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics.v:72: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'CC_Delay\'\nmodule CC_Delay(clk, reset, d, q);\n ^~~~~~~~\n : ... Top module \'CC_DLatch\'\nmodule CC_DLatch(en, d, q);\n ^~~~~~~~~\n : ... Top module \'CC_Bidir\'\nmodule CC_Bidir(sel_in, io, in, out);\n ^~~~~~~~\n : ... Top module \'CC_MuxReg\'\nmodule CC_MuxReg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n : ... Top module \'CC_Decoder\'\nmodule CC_Decoder(in, out);\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:112: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_a\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:113: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_b\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 313,055 | module | module CC_DFlipFlop(clk, en, reset, d, q);
parameter WIDTH=1;
input clk;
input en;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @ (posedge clk or posedge reset)
if (reset)
q <= 0;
else if (en)
q <= d;
endmodule | module CC_DFlipFlop(clk, en, reset, d, q); |
parameter WIDTH=1;
input clk;
input en;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @ (posedge clk or posedge reset)
if (reset)
q <= 0;
else if (en)
q <= d;
endmodule | 0 |
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