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141,774 | data/full_repos/permissive/95987710/rtl/a1csah/a1csah64bits.v | 95,987,710 | a1csah64bits.v | v | 45 | 76 | [] | ['apache license'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah64bits.v:35: Cannot find file containing module: 'a1csah32bits'\n a1csah32bits a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah32bits\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah32bits.v\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah32bits.sv\n a1csah32bits\n a1csah32bits.v\n a1csah32bits.sv\n obj_dir/a1csah32bits\n obj_dir/a1csah32bits.v\n obj_dir/a1csah32bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah64bits.v:37: Cannot find file containing module: 'a1csah32bits'\n a1csah32bits a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,495 | module | module a1csah64bits (cin,a,b,s,gen,prop,cout);
parameter n = 64;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire prop0,gen0,prop1,gen1,cout0,cout1,sel;
a1csah32bits a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
a1csah32bits a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign sel = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | module a1csah64bits (cin,a,b,s,gen,prop,cout); |
parameter n = 64;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire prop0,gen0,prop1,gen1,cout0,cout1,sel;
a1csah32bits a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
a1csah32bits a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign sel = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | 0 |
141,775 | data/full_repos/permissive/95987710/rtl/a1csah/a1csah8.v | 95,987,710 | a1csah8.v | v | 41 | 93 | [] | ['apache license'] | [] | [(22, 40)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah8.v:34: Cannot find file containing module: 'a1csah'\n a1csah a1csah_0 (.sel(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.gen(gen0),.prop(prop0));\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah.v\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah.sv\n a1csah\n a1csah.v\n a1csah.sv\n obj_dir/a1csah\n obj_dir/a1csah.v\n obj_dir/a1csah.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah8.v:35: Cannot find file containing module: 'a1csah'\n a1csah a1csah_1 (.sel(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.gen(gen1),.prop(prop1));\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,496 | module | module a1csah8 (cin,a,b,s,gen,prop);
parameter n = 8;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire prop0,gen0,prop1,gen1,sel;
a1csah a1csah_0 (.sel(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.gen(gen0),.prop(prop0));
a1csah a1csah_1 (.sel(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.gen(gen1),.prop(prop1));
assign sel = gen0 | (prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | module a1csah8 (cin,a,b,s,gen,prop); |
parameter n = 8;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire prop0,gen0,prop1,gen1,sel;
a1csah a1csah_0 (.sel(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.gen(gen0),.prop(prop0));
a1csah a1csah_1 (.sel(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.gen(gen1),.prop(prop1));
assign sel = gen0 | (prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | 0 |
141,776 | data/full_repos/permissive/95987710/rtl/cla/c1.v | 95,987,710 | c1.v | v | 30 | 76 | [] | ['apache license'] | [] | [(22, 29)] | null | data/verilator_xmls/0f368286-f240-4ea3-9bd6-2dd137874acc.xml | null | 312,502 | module | module c1 (cin,g,p,carry);
parameter n = 1;
input cin;
input [n-1:0] g;
input [n-1:0] p;
output carry;
assign carry= g[0] | (p[0] & cin);
endmodule | module c1 (cin,g,p,carry); |
parameter n = 1;
input cin;
input [n-1:0] g;
input [n-1:0] p;
output carry;
assign carry= g[0] | (p[0] & cin);
endmodule | 0 |
141,777 | data/full_repos/permissive/95987710/rtl/cla/c2cin0.v | 95,987,710 | c2cin0.v | v | 33 | 76 | [] | ['apache license'] | [] | [(22, 32)] | null | data/verilator_xmls/c16cd11c-90a9-49fd-83ca-fa5c9899659d.xml | null | 312,504 | module | module c2cin0 (g,p,carry);
parameter n = 2;
input [n-1:0] g;
input [n-2:0] p;
output carry;
wire [n-2:0]c;
assign c[0]= g[0];
assign carry= g[1] | (p[0] & c[0]);
endmodule | module c2cin0 (g,p,carry); |
parameter n = 2;
input [n-1:0] g;
input [n-2:0] p;
output carry;
wire [n-2:0]c;
assign c[0]= g[0];
assign carry= g[1] | (p[0] & c[0]);
endmodule | 0 |
141,778 | data/full_repos/permissive/95987710/rtl/cla/c3cin0.v | 95,987,710 | c3cin0.v | v | 34 | 76 | [] | ['apache license'] | [] | [(22, 33)] | null | data/verilator_xmls/3bde9d03-5630-4099-bad8-a4279580be7c.xml | null | 312,506 | module | module c3cin0 (g,p,carry);
parameter n = 3;
input [n-1:0] g;
input [n-2:0] p;
output carry;
wire [n-2:0]c;
assign c[0]= g[0];
assign c[1]= g[1] | (p[0] & c[0]);
assign carry= g[2] | (p[1] & c[1]);
endmodule | module c3cin0 (g,p,carry); |
parameter n = 3;
input [n-1:0] g;
input [n-2:0] p;
output carry;
wire [n-2:0]c;
assign c[0]= g[0];
assign c[1]= g[1] | (p[0] & c[0]);
assign carry= g[2] | (p[1] & c[1]);
endmodule | 0 |
141,779 | data/full_repos/permissive/95987710/rtl/cla/cla.v | 95,987,710 | cla.v | v | 57 | 76 | [] | ['apache license'] | [] | [(22, 56)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:34: Cannot find file containing module: 'gen_unit'\n gen_unit gu0 (.a(a[0]),.b(b[0]),.g(g[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/gen_unit\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/gen_unit.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/gen_unit.sv\n gen_unit\n gen_unit.v\n gen_unit.sv\n obj_dir/gen_unit\n obj_dir/gen_unit.v\n obj_dir/gen_unit.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:35: Cannot find file containing module: 'gen_unit'\n gen_unit gu1 (.a(a[1]),.b(b[1]),.g(g[1]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:36: Cannot find file containing module: 'gen_unit'\n gen_unit gu2 (.a(a[2]),.b(b[2]),.g(g[2]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:37: Cannot find file containing module: 'gen_unit'\n gen_unit gu3 (.a(a[3]),.b(b[3]),.g(g[3]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:39: Cannot find file containing module: 'prop_unit'\n prop_unit pu0 (.a(a[0]),.b(b[0]),.p(p[0]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:40: Cannot find file containing module: 'prop_unit'\n prop_unit pu1 (.a(a[1]),.b(b[1]),.p(p[1]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:41: Cannot find file containing module: 'prop_unit'\n prop_unit pu2 (.a(a[2]),.b(b[2]),.p(p[2]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:42: Cannot find file containing module: 'prop_unit'\n prop_unit pu3 (.a(a[3]),.b(b[3]),.p(p[3]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:44: Cannot find file containing module: 'c1'\n c1 carry1 (.cin(cin),.g(g[0]),.p(p[0]),.carry(carry[0]));\n ^~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:45: Cannot find file containing module: 'c2'\n c2 carry2 (.cin(cin),.g(g[1:0]),.p(p[1:0]),.carry(carry[1]));\n ^~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:46: Cannot find file containing module: 'c3'\n c3 carry3 (.cin(cin),.g(g[2:0]),.p(p[2:0]),.carry(carry[2]));\n ^~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:48: Cannot find file containing module: 'gen_signal'\n gen_signal gen_sum (.g(g[n-1:0]), .p(p[n-1:1]), .carry(gen));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:50: Cannot find file containing module: 'prop_signal'\n prop_signal prop_sum (.p(p[n-1:0]),.prop(prop));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:52: Cannot find file containing module: 'sum'\n sum sum0 (.a(cin),.b(p[0]),.s(s[0]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:53: Cannot find file containing module: 'sum'\n sum sum1 (.a(carry[0]),.b(p[1]),.s(s[1]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:54: Cannot find file containing module: 'sum'\n sum sum2 (.a(carry[1]),.b(p[2]),.s(s[2]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla.v:55: Cannot find file containing module: 'sum'\n sum sum3 (.a(carry[2]),.b(p[3]),.s(s[3]));\n ^~~\n%Error: Exiting due to 17 error(s)\n" | 312,507 | module | module cla (cin,a,b,s,gen,prop);
parameter n = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-2:0] carry;
wire [n-1:0] g,p;
gen_unit gu0 (.a(a[0]),.b(b[0]),.g(g[0]));
gen_unit gu1 (.a(a[1]),.b(b[1]),.g(g[1]));
gen_unit gu2 (.a(a[2]),.b(b[2]),.g(g[2]));
gen_unit gu3 (.a(a[3]),.b(b[3]),.g(g[3]));
prop_unit pu0 (.a(a[0]),.b(b[0]),.p(p[0]));
prop_unit pu1 (.a(a[1]),.b(b[1]),.p(p[1]));
prop_unit pu2 (.a(a[2]),.b(b[2]),.p(p[2]));
prop_unit pu3 (.a(a[3]),.b(b[3]),.p(p[3]));
c1 carry1 (.cin(cin),.g(g[0]),.p(p[0]),.carry(carry[0]));
c2 carry2 (.cin(cin),.g(g[1:0]),.p(p[1:0]),.carry(carry[1]));
c3 carry3 (.cin(cin),.g(g[2:0]),.p(p[2:0]),.carry(carry[2]));
gen_signal gen_sum (.g(g[n-1:0]), .p(p[n-1:1]), .carry(gen));
prop_signal prop_sum (.p(p[n-1:0]),.prop(prop));
sum sum0 (.a(cin),.b(p[0]),.s(s[0]));
sum sum1 (.a(carry[0]),.b(p[1]),.s(s[1]));
sum sum2 (.a(carry[1]),.b(p[2]),.s(s[2]));
sum sum3 (.a(carry[2]),.b(p[3]),.s(s[3]));
endmodule | module cla (cin,a,b,s,gen,prop); |
parameter n = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-2:0] carry;
wire [n-1:0] g,p;
gen_unit gu0 (.a(a[0]),.b(b[0]),.g(g[0]));
gen_unit gu1 (.a(a[1]),.b(b[1]),.g(g[1]));
gen_unit gu2 (.a(a[2]),.b(b[2]),.g(g[2]));
gen_unit gu3 (.a(a[3]),.b(b[3]),.g(g[3]));
prop_unit pu0 (.a(a[0]),.b(b[0]),.p(p[0]));
prop_unit pu1 (.a(a[1]),.b(b[1]),.p(p[1]));
prop_unit pu2 (.a(a[2]),.b(b[2]),.p(p[2]));
prop_unit pu3 (.a(a[3]),.b(b[3]),.p(p[3]));
c1 carry1 (.cin(cin),.g(g[0]),.p(p[0]),.carry(carry[0]));
c2 carry2 (.cin(cin),.g(g[1:0]),.p(p[1:0]),.carry(carry[1]));
c3 carry3 (.cin(cin),.g(g[2:0]),.p(p[2:0]),.carry(carry[2]));
gen_signal gen_sum (.g(g[n-1:0]), .p(p[n-1:1]), .carry(gen));
prop_signal prop_sum (.p(p[n-1:0]),.prop(prop));
sum sum0 (.a(cin),.b(p[0]),.s(s[0]));
sum sum1 (.a(carry[0]),.b(p[1]),.s(s[1]));
sum sum2 (.a(carry[1]),.b(p[2]),.s(s[2]));
sum sum3 (.a(carry[2]),.b(p[3]),.s(s[3]));
endmodule | 0 |
141,780 | data/full_repos/permissive/95987710/rtl/cla/cla128bits.v | 95,987,710 | cla128bits.v | v | 45 | 76 | [] | ['apache license'] | [] | [(22, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla128bits.v:35: Cannot find file containing module: 'cla64bits'\n cla64bits cla128bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla64bits\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla64bits.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla64bits.sv\n cla64bits\n cla64bits.v\n cla64bits.sv\n obj_dir/cla64bits\n obj_dir/cla64bits.v\n obj_dir/cla64bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla128bits.v:37: Cannot find file containing module: 'cla64bits'\n cla64bits cla128bits_1 (.cin(c64),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,508 | module | module cla128bits (cin,a,b,s,gen,prop,cout);
parameter n = 128;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c64,cout0,cout1;
cla64bits cla128bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla64bits cla128bits_1 (.cin(c64),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c64 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | module cla128bits (cin,a,b,s,gen,prop,cout); |
parameter n = 128;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c64,cout0,cout1;
cla64bits cla128bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla64bits cla128bits_1 (.cin(c64),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c64 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | 0 |
141,781 | data/full_repos/permissive/95987710/rtl/cla/cla16bits.v | 95,987,710 | cla16bits.v | v | 45 | 76 | [] | ['apache license'] | [] | [(22, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla16bits.v:35: Cannot find file containing module: 'cla8bits'\n cla8bits cla16bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla8bits\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla8bits.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla8bits.sv\n cla8bits\n cla8bits.v\n cla8bits.sv\n obj_dir/cla8bits\n obj_dir/cla8bits.v\n obj_dir/cla8bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla16bits.v:37: Cannot find file containing module: 'cla8bits'\n cla8bits cla16bits_1 (.cin(c8),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,509 | module | module cla16bits (cin,a,b,s,gen,prop,cout);
parameter n = 16;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c8,cout0,cout1;
cla8bits cla16bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla8bits cla16bits_1 (.cin(c8),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c8 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | module cla16bits (cin,a,b,s,gen,prop,cout); |
parameter n = 16;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c8,cout0,cout1;
cla8bits cla16bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla8bits cla16bits_1 (.cin(c8),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c8 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | 0 |
141,782 | data/full_repos/permissive/95987710/rtl/cla/cla256bits.v | 95,987,710 | cla256bits.v | v | 45 | 76 | [] | ['apache license'] | [] | [(22, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla256bits.v:35: Cannot find file containing module: 'cla128bits'\n cla128bits cla256bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla128bits\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla128bits.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla128bits.sv\n cla128bits\n cla128bits.v\n cla128bits.sv\n obj_dir/cla128bits\n obj_dir/cla128bits.v\n obj_dir/cla128bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla256bits.v:37: Cannot find file containing module: 'cla128bits'\n cla128bits cla256bits_1 (.cin(c128),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,510 | module | module cla256bits (cin,a,b,s,gen,prop,cout);
parameter n = 256;
parameter m = 128;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c128,cout0,cout1;
cla128bits cla256bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla128bits cla256bits_1 (.cin(c128),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c128 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | module cla256bits (cin,a,b,s,gen,prop,cout); |
parameter n = 256;
parameter m = 128;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c128,cout0,cout1;
cla128bits cla256bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla128bits cla256bits_1 (.cin(c128),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c128 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | 0 |
141,783 | data/full_repos/permissive/95987710/rtl/cla/cla32bits.v | 95,987,710 | cla32bits.v | v | 45 | 76 | [] | ['apache license'] | [] | [(22, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla32bits.v:35: Cannot find file containing module: 'cla16bits'\n cla16bits cla32bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla16bits\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla16bits.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla16bits.sv\n cla16bits\n cla16bits.v\n cla16bits.sv\n obj_dir/cla16bits\n obj_dir/cla16bits.v\n obj_dir/cla16bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla32bits.v:37: Cannot find file containing module: 'cla16bits'\n cla16bits cla32bits_1 (.cin(c16),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,511 | module | module cla32bits (cin,a,b,s,gen,prop,cout);
parameter n = 32;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c16,cout0,cout1;
cla16bits cla32bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla16bits cla32bits_1 (.cin(c16),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c16 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | module cla32bits (cin,a,b,s,gen,prop,cout); |
parameter n = 32;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c16,cout0,cout1;
cla16bits cla32bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla16bits cla32bits_1 (.cin(c16),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c16 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | 0 |
141,784 | data/full_repos/permissive/95987710/rtl/cla/cla4bits.v | 95,987,710 | cla4bits.v | v | 40 | 76 | [] | ['apache license'] | [] | [(22, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla4bits.v:34: Cannot find file containing module: 'cla'\n cla cla4bits_0 (.cin(cin),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla.sv\n cla\n cla.v\n cla.sv\n obj_dir/cla\n obj_dir/cla.v\n obj_dir/cla.sv\n%Error: Exiting due to 1 error(s)\n" | 312,512 | module | module cla4bits (cin,a,b,s,gen,prop,cout);
parameter n = 4;
parameter m = 0;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0;
cla cla4bits_0 (.cin(cin),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen0),.prop(prop0));
assign cout = gen0 | (prop0 & cin);
assign prop = prop0;
assign gen = gen0;
endmodule | module cla4bits (cin,a,b,s,gen,prop,cout); |
parameter n = 4;
parameter m = 0;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0;
cla cla4bits_0 (.cin(cin),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen0),.prop(prop0));
assign cout = gen0 | (prop0 & cin);
assign prop = prop0;
assign gen = gen0;
endmodule | 0 |
141,785 | data/full_repos/permissive/95987710/rtl/cla/cla64bits.v | 95,987,710 | cla64bits.v | v | 45 | 76 | [] | ['apache license'] | [] | [(22, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla64bits.v:35: Cannot find file containing module: 'cla32bits'\n cla32bits cla64bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla32bits\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla32bits.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla32bits.sv\n cla32bits\n cla32bits.v\n cla32bits.sv\n obj_dir/cla32bits\n obj_dir/cla32bits.v\n obj_dir/cla32bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla64bits.v:37: Cannot find file containing module: 'cla32bits'\n cla32bits cla64bits_1 (.cin(c32),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,513 | module | module cla64bits (cin,a,b,s,gen,prop,cout);
parameter n = 64;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c32,cout0,cout1;
cla32bits cla64bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla32bits cla64bits_1 (.cin(c32),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c32 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | module cla64bits (cin,a,b,s,gen,prop,cout); |
parameter n = 64;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c32,cout0,cout1;
cla32bits cla64bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla32bits cla64bits_1 (.cin(c32),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c32 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | 0 |
141,786 | data/full_repos/permissive/95987710/rtl/cla/cla8bits.v | 95,987,710 | cla8bits.v | v | 45 | 76 | [] | ['apache license'] | [] | [(22, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/cla8bits.v:35: Cannot find file containing module: 'cla4bits'\n cla4bits cla8bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla4bits\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla4bits.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/cla4bits.sv\n cla4bits\n cla4bits.v\n cla4bits.sv\n obj_dir/cla4bits\n obj_dir/cla4bits.v\n obj_dir/cla4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/cla8bits.v:37: Cannot find file containing module: 'cla4bits'\n cla4bits cla8bits_1 (.cin(c4),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,514 | module | module cla8bits (cin,a,b,s,gen,prop,cout);
parameter n = 8;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c4,cout0,cout1;
cla4bits cla8bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla4bits cla8bits_1 (.cin(c4),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c4 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | module cla8bits (cin,a,b,s,gen,prop,cout); |
parameter n = 8;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire gen0,prop0, prop1,gen1,c4,cout0,cout1;
cla4bits cla8bits_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
cla4bits cla8bits_1 (.cin(c4),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign c4 = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign prop = prop1 & prop0;
assign gen = gen1 | (prop1 & gen0);
endmodule | 0 |
141,787 | data/full_repos/permissive/95987710/rtl/cla/clacin0.v | 95,987,710 | clacin0.v | v | 56 | 76 | [] | ['apache license'] | [] | [(22, 55)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:33: Cannot find file containing module: 'gen_unit'\n gen_unit gu0 (.a(a[0]),.b(b[0]),.g(g[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/gen_unit\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/gen_unit.v\n data/full_repos/permissive/95987710/rtl/cla,data/full_repos/permissive/95987710/gen_unit.sv\n gen_unit\n gen_unit.v\n gen_unit.sv\n obj_dir/gen_unit\n obj_dir/gen_unit.v\n obj_dir/gen_unit.sv\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:34: Cannot find file containing module: 'gen_unit'\n gen_unit gu1 (.a(a[1]),.b(b[1]),.g(g[1]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:35: Cannot find file containing module: 'gen_unit'\n gen_unit gu2 (.a(a[2]),.b(b[2]),.g(g[2]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:36: Cannot find file containing module: 'gen_unit'\n gen_unit gu3 (.a(a[3]),.b(b[3]),.g(g[3]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:38: Cannot find file containing module: 'prop_unit'\n prop_unit pu0 (.a(a[0]),.b(b[0]),.p(p[0]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:39: Cannot find file containing module: 'prop_unit'\n prop_unit pu1 (.a(a[1]),.b(b[1]),.p(p[1]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:40: Cannot find file containing module: 'prop_unit'\n prop_unit pu2 (.a(a[2]),.b(b[2]),.p(p[2]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:41: Cannot find file containing module: 'prop_unit'\n prop_unit pu3 (.a(a[3]),.b(b[3]),.p(p[3]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:44: Cannot find file containing module: 'c2cin0'\n c2cin0 carry2 (.g(g[1:0]),.p(p[1:1]),.carry(carry[1]));\n ^~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:45: Cannot find file containing module: 'c3cin0'\n c3cin0 carry3 (.g(g[2:0]),.p(p[2:1]),.carry(carry[2]));\n ^~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:47: Cannot find file containing module: 'gen_signal'\n gen_signal gen_sum (.g(g[n-1:0]), .p(p[n-1:1]), .carry(gen));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:49: Cannot find file containing module: 'prop_signal'\n prop_signal prop_sum (.p(p[n-1:0]),.prop(prop));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:52: Cannot find file containing module: 'sum'\n sum sum1 (.a(carry[0]),.b(p[1]),.s(s[1]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:53: Cannot find file containing module: 'sum'\n sum sum2 (.a(carry[1]),.b(p[2]),.s(s[2]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/cla/clacin0.v:54: Cannot find file containing module: 'sum'\n sum sum3 (.a(carry[2]),.b(p[3]),.s(s[3]));\n ^~~\n%Error: Exiting due to 15 error(s)\n" | 312,515 | module | module clacin0 (a,b,s,gen,prop);
parameter n = 4;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-2:0] carry;
wire [n-1:0] g,p;
gen_unit gu0 (.a(a[0]),.b(b[0]),.g(g[0]));
gen_unit gu1 (.a(a[1]),.b(b[1]),.g(g[1]));
gen_unit gu2 (.a(a[2]),.b(b[2]),.g(g[2]));
gen_unit gu3 (.a(a[3]),.b(b[3]),.g(g[3]));
prop_unit pu0 (.a(a[0]),.b(b[0]),.p(p[0]));
prop_unit pu1 (.a(a[1]),.b(b[1]),.p(p[1]));
prop_unit pu2 (.a(a[2]),.b(b[2]),.p(p[2]));
prop_unit pu3 (.a(a[3]),.b(b[3]),.p(p[3]));
assign carry[0] = g[0];
c2cin0 carry2 (.g(g[1:0]),.p(p[1:1]),.carry(carry[1]));
c3cin0 carry3 (.g(g[2:0]),.p(p[2:1]),.carry(carry[2]));
gen_signal gen_sum (.g(g[n-1:0]), .p(p[n-1:1]), .carry(gen));
prop_signal prop_sum (.p(p[n-1:0]),.prop(prop));
assign s[0] = p[0];
sum sum1 (.a(carry[0]),.b(p[1]),.s(s[1]));
sum sum2 (.a(carry[1]),.b(p[2]),.s(s[2]));
sum sum3 (.a(carry[2]),.b(p[3]),.s(s[3]));
endmodule | module clacin0 (a,b,s,gen,prop); |
parameter n = 4;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-2:0] carry;
wire [n-1:0] g,p;
gen_unit gu0 (.a(a[0]),.b(b[0]),.g(g[0]));
gen_unit gu1 (.a(a[1]),.b(b[1]),.g(g[1]));
gen_unit gu2 (.a(a[2]),.b(b[2]),.g(g[2]));
gen_unit gu3 (.a(a[3]),.b(b[3]),.g(g[3]));
prop_unit pu0 (.a(a[0]),.b(b[0]),.p(p[0]));
prop_unit pu1 (.a(a[1]),.b(b[1]),.p(p[1]));
prop_unit pu2 (.a(a[2]),.b(b[2]),.p(p[2]));
prop_unit pu3 (.a(a[3]),.b(b[3]),.p(p[3]));
assign carry[0] = g[0];
c2cin0 carry2 (.g(g[1:0]),.p(p[1:1]),.carry(carry[1]));
c3cin0 carry3 (.g(g[2:0]),.p(p[2:1]),.carry(carry[2]));
gen_signal gen_sum (.g(g[n-1:0]), .p(p[n-1:1]), .carry(gen));
prop_signal prop_sum (.p(p[n-1:0]),.prop(prop));
assign s[0] = p[0];
sum sum1 (.a(carry[0]),.b(p[1]),.s(s[1]));
sum sum2 (.a(carry[1]),.b(p[2]),.s(s[2]));
sum sum3 (.a(carry[2]),.b(p[3]),.s(s[3]));
endmodule | 0 |
141,788 | data/full_repos/permissive/95987710/rtl/cla/gen_unit.v | 95,987,710 | gen_unit.v | v | 28 | 76 | [] | ['apache license'] | [] | [(22, 27)] | null | data/verilator_xmls/db2e6226-4b91-4e2d-86fd-a74976bfd443.xml | null | 312,517 | module | module gen_unit (a,b,g);
input a;
input b;
output g;
assign g = a & b;
endmodule | module gen_unit (a,b,g); |
input a;
input b;
output g;
assign g = a & b;
endmodule | 0 |
141,789 | data/full_repos/permissive/95987710/rtl/cla/prop_signal.v | 95,987,710 | prop_signal.v | v | 28 | 76 | [] | ['apache license'] | [] | [(22, 27)] | null | data/verilator_xmls/e2f4ee47-9b21-4e58-806f-b1dd19ae5626.xml | null | 312,518 | module | module prop_signal (p,prop);
parameter n=4;
input [n-1:0]p;
output prop;
assign prop = p[0] & p[1] & p[2] & p[3];
endmodule | module prop_signal (p,prop); |
parameter n=4;
input [n-1:0]p;
output prop;
assign prop = p[0] & p[1] & p[2] & p[3];
endmodule | 0 |
141,790 | data/full_repos/permissive/95987710/rtl/cla/prop_unit.v | 95,987,710 | prop_unit.v | v | 28 | 76 | [] | ['apache license'] | [] | [(22, 27)] | null | data/verilator_xmls/a859276a-9ae3-4839-86b0-2aa52e67336e.xml | null | 312,519 | module | module prop_unit (a,b,p);
input a;
input b;
output p;
assign p = a ^ b;
endmodule | module prop_unit (a,b,p); |
input a;
input b;
output p;
assign p = a ^ b;
endmodule | 0 |
141,791 | data/full_repos/permissive/95987710/rtl/cla/sum.v | 95,987,710 | sum.v | v | 28 | 76 | [] | ['apache license'] | [] | [(22, 27)] | null | data/verilator_xmls/c098632c-0617-4da8-851b-c5ef6c23832c.xml | null | 312,520 | module | module sum (a,b,s);
input a;
input b;
output s;
assign s = a ^ b;
endmodule | module sum (a,b,s); |
input a;
input b;
output s;
assign s = a ^ b;
endmodule | 0 |
141,792 | data/full_repos/permissive/95987710/rtl/cra/cra128bits.v | 95,987,710 | cra128bits.v | v | 36 | 82 | [] | ['apache license'] | [] | [(22, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cra/cra128bits.v:33: Cannot find file containing module: 'cra64bits'\n cra64bits cra128_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra64bits\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra64bits.v\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra64bits.sv\n cra64bits\n cra64bits.v\n cra64bits.sv\n obj_dir/cra64bits\n obj_dir/cra64bits.v\n obj_dir/cra64bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra128bits.v:34: Cannot find file containing module: 'cra64bits'\n cra64bits cra128_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,521 | module | module cra128bits (cin,a,b,s,cout);
parameter n = 128;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra64bits cra128_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra64bits cra128_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | module cra128bits (cin,a,b,s,cout); |
parameter n = 128;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra64bits cra128_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra64bits cra128_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | 0 |
141,793 | data/full_repos/permissive/95987710/rtl/cra/cra16bits.v | 95,987,710 | cra16bits.v | v | 36 | 80 | [] | ['apache license'] | [] | [(22, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cra/cra16bits.v:33: Cannot find file containing module: 'cra8bits'\n cra8bits cra16_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra8bits\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra8bits.v\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra8bits.sv\n cra8bits\n cra8bits.v\n cra8bits.sv\n obj_dir/cra8bits\n obj_dir/cra8bits.v\n obj_dir/cra8bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra16bits.v:34: Cannot find file containing module: 'cra8bits'\n cra8bits cra16_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,522 | module | module cra16bits (cin,a,b,s,cout);
parameter n = 16;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra8bits cra16_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra8bits cra16_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | module cra16bits (cin,a,b,s,cout); |
parameter n = 16;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra8bits cra16_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra8bits cra16_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | 0 |
141,794 | data/full_repos/permissive/95987710/rtl/cra/cra256bits.v | 95,987,710 | cra256bits.v | v | 36 | 83 | [] | ['apache license'] | [] | [(22, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cra/cra256bits.v:33: Cannot find file containing module: 'cra128bits'\n cra128bits cra256_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra128bits\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra128bits.v\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra128bits.sv\n cra128bits\n cra128bits.v\n cra128bits.sv\n obj_dir/cra128bits\n obj_dir/cra128bits.v\n obj_dir/cra128bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra256bits.v:34: Cannot find file containing module: 'cra128bits'\n cra128bits cra256_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,523 | module | module cra256bits (cin,a,b,s,cout);
parameter n = 256;
parameter m = 128;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra128bits cra256_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra128bits cra256_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | module cra256bits (cin,a,b,s,cout); |
parameter n = 256;
parameter m = 128;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra128bits cra256_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra128bits cra256_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | 0 |
141,795 | data/full_repos/permissive/95987710/rtl/cra/cra32bits.v | 95,987,710 | cra32bits.v | v | 36 | 81 | [] | ['apache license'] | [] | [(22, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cra/cra32bits.v:33: Cannot find file containing module: 'cra16bits'\n cra16bits cra32_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra16bits\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra16bits.v\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra16bits.sv\n cra16bits\n cra16bits.v\n cra16bits.sv\n obj_dir/cra16bits\n obj_dir/cra16bits.v\n obj_dir/cra16bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra32bits.v:34: Cannot find file containing module: 'cra16bits'\n cra16bits cra32_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,524 | module | module cra32bits (cin,a,b,s,cout);
parameter n = 32;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra16bits cra32_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra16bits cra32_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | module cra32bits (cin,a,b,s,cout); |
parameter n = 32;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra16bits cra32_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra16bits cra32_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | 0 |
141,796 | data/full_repos/permissive/95987710/rtl/cra/cra4bitscin0.v | 95,987,710 | cra4bitscin0.v | v | 36 | 76 | [] | ['apache license'] | [] | [(22, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cra/cra4bitscin0.v:31: Cannot find file containing module: 'half_adder'\n half_adder cra4_0 (.a(a[0]),.b(b[0]),.s(s[0]),.cout(c[0]));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/half_adder\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/half_adder.v\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/half_adder.sv\n half_adder\n half_adder.v\n half_adder.sv\n obj_dir/half_adder\n obj_dir/half_adder.v\n obj_dir/half_adder.sv\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra4bitscin0.v:32: Cannot find file containing module: 'full_adder'\n full_adder cra4_1 (.cin(c[0]),.a(a[1]),.b(b[1]),.s(s[1]),.cout(c[1]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra4bitscin0.v:33: Cannot find file containing module: 'full_adder'\n full_adder cra4_2 (.cin(c[1]),.a(a[2]),.b(b[2]),.s(s[2]),.cout(c[2]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra4bitscin0.v:34: Cannot find file containing module: 'full_adder'\n full_adder cra4_3 (.cin(c[2]),.a(a[3]),.b(b[3]),.s(s[3]),.cout(cout));\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 312,526 | module | module cra4bitscin0 (a,b,s,cout);
parameter n = 4;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [n-2:0] c;
half_adder cra4_0 (.a(a[0]),.b(b[0]),.s(s[0]),.cout(c[0]));
full_adder cra4_1 (.cin(c[0]),.a(a[1]),.b(b[1]),.s(s[1]),.cout(c[1]));
full_adder cra4_2 (.cin(c[1]),.a(a[2]),.b(b[2]),.s(s[2]),.cout(c[2]));
full_adder cra4_3 (.cin(c[2]),.a(a[3]),.b(b[3]),.s(s[3]),.cout(cout));
endmodule | module cra4bitscin0 (a,b,s,cout); |
parameter n = 4;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [n-2:0] c;
half_adder cra4_0 (.a(a[0]),.b(b[0]),.s(s[0]),.cout(c[0]));
full_adder cra4_1 (.cin(c[0]),.a(a[1]),.b(b[1]),.s(s[1]),.cout(c[1]));
full_adder cra4_2 (.cin(c[1]),.a(a[2]),.b(b[2]),.s(s[2]),.cout(c[2]));
full_adder cra4_3 (.cin(c[2]),.a(a[3]),.b(b[3]),.s(s[3]),.cout(cout));
endmodule | 0 |
141,797 | data/full_repos/permissive/95987710/rtl/cra/cra64bits.v | 95,987,710 | cra64bits.v | v | 36 | 81 | [] | ['apache license'] | [] | [(22, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cra/cra64bits.v:33: Cannot find file containing module: 'cra32bits'\n cra32bits cra64_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra32bits\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra32bits.v\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra32bits.sv\n cra32bits\n cra32bits.v\n cra32bits.sv\n obj_dir/cra32bits\n obj_dir/cra32bits.v\n obj_dir/cra32bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra64bits.v:34: Cannot find file containing module: 'cra32bits'\n cra32bits cra64_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,528 | module | module cra64bits (cin,a,b,s,cout);
parameter n = 64;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra32bits cra64_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra32bits cra64_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | module cra64bits (cin,a,b,s,cout); |
parameter n = 64;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra32bits cra64_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra32bits cra64_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | 0 |
141,798 | data/full_repos/permissive/95987710/rtl/cra/cra8bits.v | 95,987,710 | cra8bits.v | v | 36 | 79 | [] | ['apache license'] | [] | [(22, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/cra/cra8bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits cra8_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/cra,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/cra/cra8bits.v:34: Cannot find file containing module: 'cra4bits'\n cra4bits cra8_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,529 | module | module cra8bits (cin,a,b,s,cout);
parameter n = 8;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra4bits cra8_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra4bits cra8_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | module cra8bits (cin,a,b,s,cout); |
parameter n = 8;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire c;
cra4bits cra8_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.cout(c));
cra4bits cra8_1 (.cin(c),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.cout(cout));
endmodule | 0 |
141,799 | data/full_repos/permissive/95987710/rtl/cra/full_adder.v | 95,987,710 | full_adder.v | v | 28 | 76 | [] | ['apache license'] | [] | [(22, 27)] | null | data/verilator_xmls/9ce8b2aa-f760-465c-b50c-ff5eb77ec7c1.xml | null | 312,530 | module | module full_adder (cin,a,b,s,cout);
input cin,a,b;
output s,cout;
assign s = (a ^ b) ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule | module full_adder (cin,a,b,s,cout); |
input cin,a,b;
output s,cout;
assign s = (a ^ b) ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule | 0 |
141,800 | data/full_repos/permissive/95987710/rtl/cra/half_addercin1.v | 95,987,710 | half_addercin1.v | v | 28 | 76 | [] | ['apache license'] | [] | [(22, 27)] | null | data/verilator_xmls/1ecfb6e3-9f23-428e-88d8-b8481168f419.xml | null | 312,532 | module | module half_addercin1 (a,b,s,cout);
input a,b;
output s,cout;
assign s = ~(a ^ b);
assign cout = a | b ;
endmodule | module half_addercin1 (a,b,s,cout); |
input a,b;
output s,cout;
assign s = ~(a ^ b);
assign cout = a | b ;
endmodule | 0 |
141,801 | data/full_repos/permissive/95987710/rtl/csa/csa.v | 95,987,710 | csa.v | v | 41 | 76 | [] | ['apache license'] | [] | [(22, 40)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/csa/csa.v:33: Cannot find file containing module: 'cra4bitscin0'\n cra4bitscin0 csa_0 (.a(a[n-1:0]),.b(b[n-1:0]),.s(sum0[n-1:0]),.cout(c0));\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bitscin0\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bitscin0.v\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bitscin0.sv\n cra4bitscin0\n cra4bitscin0.v\n cra4bitscin0.sv\n obj_dir/cra4bitscin0\n obj_dir/cra4bitscin0.v\n obj_dir/cra4bitscin0.sv\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa.v:34: Cannot find file containing module: 'cra4bitscin1'\n cra4bitscin1 csa_1 (.a(a[n-1:0]),.b(b[n-1:0]),.s(sum1[n-1:0]),.cout(c1));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa.v:36: Cannot find file containing module: 'mux2to1'\n mux2to1 m1 (.sel(sel),.a(sum1[0]),.b(sum0[0]),.out(s[0]));\n ^~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa.v:37: Cannot find file containing module: 'mux2to1'\n mux2to1 m2 (.sel(sel),.a(sum1[1]),.b(sum0[1]),.out(s[1]));\n ^~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa.v:38: Cannot find file containing module: 'mux2to1'\n mux2to1 m3 (.sel(sel),.a(sum1[2]),.b(sum0[2]),.out(s[2]));\n ^~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa.v:39: Cannot find file containing module: 'mux2to1'\n mux2to1 m4 (.sel(sel),.a(sum1[3]),.b(sum0[3]),.out(s[3]));\n ^~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 312,533 | module | module csa (sel,a,b,s,c0,c1);
parameter n = 4;
input sel;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output c0;
output c1;
wire [n-1:0] sum0,sum1;
cra4bitscin0 csa_0 (.a(a[n-1:0]),.b(b[n-1:0]),.s(sum0[n-1:0]),.cout(c0));
cra4bitscin1 csa_1 (.a(a[n-1:0]),.b(b[n-1:0]),.s(sum1[n-1:0]),.cout(c1));
mux2to1 m1 (.sel(sel),.a(sum1[0]),.b(sum0[0]),.out(s[0]));
mux2to1 m2 (.sel(sel),.a(sum1[1]),.b(sum0[1]),.out(s[1]));
mux2to1 m3 (.sel(sel),.a(sum1[2]),.b(sum0[2]),.out(s[2]));
mux2to1 m4 (.sel(sel),.a(sum1[3]),.b(sum0[3]),.out(s[3]));
endmodule | module csa (sel,a,b,s,c0,c1); |
parameter n = 4;
input sel;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output c0;
output c1;
wire [n-1:0] sum0,sum1;
cra4bitscin0 csa_0 (.a(a[n-1:0]),.b(b[n-1:0]),.s(sum0[n-1:0]),.cout(c0));
cra4bitscin1 csa_1 (.a(a[n-1:0]),.b(b[n-1:0]),.s(sum1[n-1:0]),.cout(c1));
mux2to1 m1 (.sel(sel),.a(sum1[0]),.b(sum0[0]),.out(s[0]));
mux2to1 m2 (.sel(sel),.a(sum1[1]),.b(sum0[1]),.out(s[1]));
mux2to1 m3 (.sel(sel),.a(sum1[2]),.b(sum0[2]),.out(s[2]));
mux2to1 m4 (.sel(sel),.a(sum1[3]),.b(sum0[3]),.out(s[3]));
endmodule | 0 |
141,802 | data/full_repos/permissive/95987710/rtl/csa/csa128bits.v | 95,987,710 | csa128bits.v | v | 129 | 84 | [] | ['apache license'] | [] | [(21, 128)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:34: Cannot find file containing module: 'csa'\n csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:36: Cannot find file containing module: 'csa'\n csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:38: Cannot find file containing module: 'csa'\n csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:40: Cannot find file containing module: 'csa'\n csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:42: Cannot find file containing module: 'csa'\n csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:44: Cannot find file containing module: 'csa'\n csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:46: Cannot find file containing module: 'csa'\n csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:48: Cannot find file containing module: 'csa'\n csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:50: Cannot find file containing module: 'csa'\n csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:52: Cannot find file containing module: 'csa'\n csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:54: Cannot find file containing module: 'csa'\n csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:56: Cannot find file containing module: 'csa'\n csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:58: Cannot find file containing module: 'csa'\n csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:60: Cannot find file containing module: 'csa'\n csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:62: Cannot find file containing module: 'csa'\n csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:64: Cannot find file containing module: 'csa'\n csa csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64]),.c0(c0[15])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:66: Cannot find file containing module: 'csa'\n csa csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68]),.c0(c0[16])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:68: Cannot find file containing module: 'csa'\n csa csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72]),.c0(c0[17])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:70: Cannot find file containing module: 'csa'\n csa csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76]),.c0(c0[18])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:72: Cannot find file containing module: 'csa'\n csa csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80]),.c0(c0[19])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:74: Cannot find file containing module: 'csa'\n csa csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84]),.c0(c0[20])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:76: Cannot find file containing module: 'csa'\n csa csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88]),.c0(c0[21])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:78: Cannot find file containing module: 'csa'\n csa csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92]),.c0(c0[22])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:80: Cannot find file containing module: 'csa'\n csa csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96]),.c0(c0[23])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:82: Cannot find file containing module: 'csa'\n csa csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100]),.c0(c0[24])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:84: Cannot find file containing module: 'csa'\n csa csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104]),.c0(c0[25])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:86: Cannot find file containing module: 'csa'\n csa csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108]),.c0(c0[26])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:88: Cannot find file containing module: 'csa'\n csa csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112]),.c0(c0[27])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:90: Cannot find file containing module: 'csa'\n csa csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116]),.c0(c0[28])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:92: Cannot find file containing module: 'csa'\n csa csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120]),.c0(c0[29])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa128bits.v:94: Cannot find file containing module: 'csa'\n csa csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124]),.c0(c0[30])\n ^~~\n%Error: Exiting due to 32 error(s)\n" | 312,534 | module | module csa128bits (cin,a,b,s,cout);
parameter n = 128;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])
,.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])
,.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])
,.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])
,.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])
,.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])
,.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])
,.c1(c1[6]));
csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])
,.c1(c1[7]));
csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])
,.c1(c1[8]));
csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])
,.c1(c1[9]));
csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])
,.c1(c1[10]));
csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])
,.c1(c1[11]));
csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])
,.c1(c1[12]));
csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])
,.c1(c1[13]));
csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])
,.c1(c1[14]));
csa csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64]),.c0(c0[15])
,.c1(c1[15]));
csa csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68]),.c0(c0[16])
,.c1(c1[16]));
csa csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72]),.c0(c0[17])
,.c1(c1[17]));
csa csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76]),.c0(c0[18])
,.c1(c1[18]));
csa csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80]),.c0(c0[19])
,.c1(c1[19]));
csa csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84]),.c0(c0[20])
,.c1(c1[20]));
csa csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88]),.c0(c0[21])
,.c1(c1[21]));
csa csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92]),.c0(c0[22])
,.c1(c1[22]));
csa csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96]),.c0(c0[23])
,.c1(c1[23]));
csa csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100]),.c0(c0[24])
,.c1(c1[24]));
csa csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104]),.c0(c0[25])
,.c1(c1[25]));
csa csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108]),.c0(c0[26])
,.c1(c1[26]));
csa csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112]),.c0(c0[27])
,.c1(c1[27]));
csa csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116]),.c0(c0[28])
,.c1(c1[28]));
csa csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120]),.c0(c0[29])
,.c1(c1[29]));
csa csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124]),.c0(c0[30])
,.c1(c1[30]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign sel[7] = c0[6] | (c1[6] & sel[6]);
assign sel[8] = c0[7] | (c1[7] & sel[7]);
assign sel[9] = c0[8] | (c1[8] & sel[8]);
assign sel[10] = c0[9] | (c1[9] & sel[9]);
assign sel[11] = c0[10] | (c1[10] & sel[10]);
assign sel[12] = c0[11] | (c1[11] & sel[11]);
assign sel[13] = c0[12] | (c1[12] & sel[12]);
assign sel[14] = c0[13] | (c1[13] & sel[13]);
assign sel[15] = c0[14] | (c1[14] & sel[14]);
assign sel[16] = c0[15] | (c1[15] & sel[15]);
assign sel[17] = c0[16] | (c1[16] & sel[16]);
assign sel[18] = c0[17] | (c1[17] & sel[17]);
assign sel[19] = c0[18] | (c1[18] & sel[18]);
assign sel[20] = c0[19] | (c1[19] & sel[19]);
assign sel[21] = c0[20] | (c1[20] & sel[20]);
assign sel[22] = c0[21] | (c1[21] & sel[21]);
assign sel[23] = c0[22] | (c1[22] & sel[22]);
assign sel[24] = c0[23] | (c1[23] & sel[23]);
assign sel[25] = c0[24] | (c1[24] & sel[24]);
assign sel[26] = c0[25] | (c1[25] & sel[25]);
assign sel[27] = c0[26] | (c1[26] & sel[26]);
assign sel[28] = c0[27] | (c1[27] & sel[27]);
assign sel[29] = c0[28] | (c1[28] & sel[28]);
assign sel[30] = c0[29] | (c1[29] & sel[29]);
assign cout = c0[30] | (c1[30] & sel[30]);
endmodule | module csa128bits (cin,a,b,s,cout); |
parameter n = 128;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])
,.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])
,.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])
,.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])
,.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])
,.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])
,.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])
,.c1(c1[6]));
csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])
,.c1(c1[7]));
csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])
,.c1(c1[8]));
csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])
,.c1(c1[9]));
csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])
,.c1(c1[10]));
csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])
,.c1(c1[11]));
csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])
,.c1(c1[12]));
csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])
,.c1(c1[13]));
csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])
,.c1(c1[14]));
csa csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64]),.c0(c0[15])
,.c1(c1[15]));
csa csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68]),.c0(c0[16])
,.c1(c1[16]));
csa csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72]),.c0(c0[17])
,.c1(c1[17]));
csa csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76]),.c0(c0[18])
,.c1(c1[18]));
csa csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80]),.c0(c0[19])
,.c1(c1[19]));
csa csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84]),.c0(c0[20])
,.c1(c1[20]));
csa csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88]),.c0(c0[21])
,.c1(c1[21]));
csa csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92]),.c0(c0[22])
,.c1(c1[22]));
csa csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96]),.c0(c0[23])
,.c1(c1[23]));
csa csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100]),.c0(c0[24])
,.c1(c1[24]));
csa csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104]),.c0(c0[25])
,.c1(c1[25]));
csa csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108]),.c0(c0[26])
,.c1(c1[26]));
csa csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112]),.c0(c0[27])
,.c1(c1[27]));
csa csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116]),.c0(c0[28])
,.c1(c1[28]));
csa csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120]),.c0(c0[29])
,.c1(c1[29]));
csa csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124]),.c0(c0[30])
,.c1(c1[30]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign sel[7] = c0[6] | (c1[6] & sel[6]);
assign sel[8] = c0[7] | (c1[7] & sel[7]);
assign sel[9] = c0[8] | (c1[8] & sel[8]);
assign sel[10] = c0[9] | (c1[9] & sel[9]);
assign sel[11] = c0[10] | (c1[10] & sel[10]);
assign sel[12] = c0[11] | (c1[11] & sel[11]);
assign sel[13] = c0[12] | (c1[12] & sel[12]);
assign sel[14] = c0[13] | (c1[13] & sel[13]);
assign sel[15] = c0[14] | (c1[14] & sel[14]);
assign sel[16] = c0[15] | (c1[15] & sel[15]);
assign sel[17] = c0[16] | (c1[16] & sel[16]);
assign sel[18] = c0[17] | (c1[17] & sel[17]);
assign sel[19] = c0[18] | (c1[18] & sel[18]);
assign sel[20] = c0[19] | (c1[19] & sel[19]);
assign sel[21] = c0[20] | (c1[20] & sel[20]);
assign sel[22] = c0[21] | (c1[21] & sel[21]);
assign sel[23] = c0[22] | (c1[22] & sel[22]);
assign sel[24] = c0[23] | (c1[23] & sel[23]);
assign sel[25] = c0[24] | (c1[24] & sel[24]);
assign sel[26] = c0[25] | (c1[25] & sel[25]);
assign sel[27] = c0[26] | (c1[26] & sel[26]);
assign sel[28] = c0[27] | (c1[27] & sel[27]);
assign sel[29] = c0[28] | (c1[28] & sel[28]);
assign sel[30] = c0[29] | (c1[29] & sel[29]);
assign cout = c0[30] | (c1[30] & sel[30]);
endmodule | 0 |
141,803 | data/full_repos/permissive/95987710/rtl/csa/csa16bits.v | 95,987,710 | csa16bits.v | v | 42 | 88 | [] | ['apache license'] | [] | [(21, 41)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/csa/csa16bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa16bits.v:34: Cannot find file containing module: 'csa'\n csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa16bits.v:35: Cannot find file containing module: 'csa'\n csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1]),.c1(c1[1]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa16bits.v:36: Cannot find file containing module: 'csa'\n csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2]),.c1(c1[2]));\n ^~~\n%Error: Exiting due to 4 error(s)\n" | 312,535 | module | module csa16bits (cin,a,b,s,cout);
parameter n = 16;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1]),.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2]),.c1(c1[2]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign cout = c0[2] | (c1[2] & sel[2]);
endmodule | module csa16bits (cin,a,b,s,cout); |
parameter n = 16;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1]),.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2]),.c1(c1[2]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign cout = c0[2] | (c1[2] & sel[2]);
endmodule | 0 |
141,804 | data/full_repos/permissive/95987710/rtl/csa/csa256bits.v | 95,987,710 | csa256bits.v | v | 225 | 84 | [] | ['apache license'] | [] | [(21, 224)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:34: Cannot find file containing module: 'csa'\n csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:36: Cannot find file containing module: 'csa'\n csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:38: Cannot find file containing module: 'csa'\n csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:40: Cannot find file containing module: 'csa'\n csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:42: Cannot find file containing module: 'csa'\n csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:44: Cannot find file containing module: 'csa'\n csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:46: Cannot find file containing module: 'csa'\n csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:48: Cannot find file containing module: 'csa'\n csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:50: Cannot find file containing module: 'csa'\n csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:52: Cannot find file containing module: 'csa'\n csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:54: Cannot find file containing module: 'csa'\n csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:56: Cannot find file containing module: 'csa'\n csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:58: Cannot find file containing module: 'csa'\n csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:60: Cannot find file containing module: 'csa'\n csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:62: Cannot find file containing module: 'csa'\n csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:64: Cannot find file containing module: 'csa'\n csa csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64]),.c0(c0[15])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:66: Cannot find file containing module: 'csa'\n csa csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68]),.c0(c0[16])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:68: Cannot find file containing module: 'csa'\n csa csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72]),.c0(c0[17])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:70: Cannot find file containing module: 'csa'\n csa csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76]),.c0(c0[18])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:72: Cannot find file containing module: 'csa'\n csa csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80]),.c0(c0[19])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:74: Cannot find file containing module: 'csa'\n csa csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84]),.c0(c0[20])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:76: Cannot find file containing module: 'csa'\n csa csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88]),.c0(c0[21])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:78: Cannot find file containing module: 'csa'\n csa csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92]),.c0(c0[22])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:80: Cannot find file containing module: 'csa'\n csa csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96]),.c0(c0[23])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:82: Cannot find file containing module: 'csa'\n csa csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100]),.c0(c0[24])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:84: Cannot find file containing module: 'csa'\n csa csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104]),.c0(c0[25])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:86: Cannot find file containing module: 'csa'\n csa csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108]),.c0(c0[26])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:88: Cannot find file containing module: 'csa'\n csa csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112]),.c0(c0[27])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:90: Cannot find file containing module: 'csa'\n csa csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116]),.c0(c0[28])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:92: Cannot find file containing module: 'csa'\n csa csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120]),.c0(c0[29])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:94: Cannot find file containing module: 'csa'\n csa csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124]),.c0(c0[30])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:96: Cannot find file containing module: 'csa'\n csa csa_32 (.sel(sel[31]),.a(a[131:128]),.b(b[131:128]),.s(s[131:128]),.c0(c0[31])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:98: Cannot find file containing module: 'csa'\n csa csa_33 (.sel(sel[32]),.a(a[135:132]),.b(b[135:132]),.s(s[135:132]),.c0(c0[32])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:100: Cannot find file containing module: 'csa'\n csa csa_34 (.sel(sel[33]),.a(a[139:136]),.b(b[139:136]),.s(s[139:136]),.c0(c0[33])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:102: Cannot find file containing module: 'csa'\n csa csa_35 (.sel(sel[34]),.a(a[143:140]),.b(b[143:140]),.s(s[143:140]),.c0(c0[34])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:104: Cannot find file containing module: 'csa'\n csa csa_36 (.sel(sel[35]),.a(a[147:144]),.b(b[147:144]),.s(s[147:144]),.c0(c0[35])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:106: Cannot find file containing module: 'csa'\n csa csa_37 (.sel(sel[36]),.a(a[151:148]),.b(b[151:148]),.s(s[151:148]),.c0(c0[36])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:108: Cannot find file containing module: 'csa'\n csa csa_38 (.sel(sel[37]),.a(a[155:152]),.b(b[155:152]),.s(s[155:152]),.c0(c0[37])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:110: Cannot find file containing module: 'csa'\n csa csa_39 (.sel(sel[38]),.a(a[159:156]),.b(b[159:156]),.s(s[159:156]),.c0(c0[38])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:112: Cannot find file containing module: 'csa'\n csa csa_40 (.sel(sel[39]),.a(a[163:160]),.b(b[163:160]),.s(s[163:160]),.c0(c0[39])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:114: Cannot find file containing module: 'csa'\n csa csa_41 (.sel(sel[40]),.a(a[167:164]),.b(b[167:164]),.s(s[167:164]),.c0(c0[40])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:116: Cannot find file containing module: 'csa'\n csa csa_42 (.sel(sel[41]),.a(a[171:168]),.b(b[171:168]),.s(s[171:168]),.c0(c0[41])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:118: Cannot find file containing module: 'csa'\n csa csa_43 (.sel(sel[42]),.a(a[175:172]),.b(b[175:172]),.s(s[175:172]),.c0(c0[42])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:120: Cannot find file containing module: 'csa'\n csa csa_44 (.sel(sel[43]),.a(a[179:176]),.b(b[179:176]),.s(s[179:176]),.c0(c0[43])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:122: Cannot find file containing module: 'csa'\n csa csa_45 (.sel(sel[44]),.a(a[183:180]),.b(b[183:180]),.s(s[183:180]),.c0(c0[44])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:124: Cannot find file containing module: 'csa'\n csa csa_46 (.sel(sel[45]),.a(a[187:184]),.b(b[187:184]),.s(s[187:184]),.c0(c0[45])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:126: Cannot find file containing module: 'csa'\n csa csa_47 (.sel(sel[46]),.a(a[191:188]),.b(b[191:188]),.s(s[191:188]),.c0(c0[46])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:128: Cannot find file containing module: 'csa'\n csa csa_48 (.sel(sel[47]),.a(a[195:192]),.b(b[195:192]),.s(s[195:192]),.c0(c0[47])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa256bits.v:130: Cannot find file containing module: 'csa'\n csa csa_49 (.sel(sel[48]),.a(a[199:196]),.b(b[199:196]),.s(s[199:196]),.c0(c0[48])\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 312,536 | module | module csa256bits (cin,a,b,s,cout);
parameter n = 256;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])
,.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])
,.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])
,.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])
,.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])
,.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])
,.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])
,.c1(c1[6]));
csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])
,.c1(c1[7]));
csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])
,.c1(c1[8]));
csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])
,.c1(c1[9]));
csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])
,.c1(c1[10]));
csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])
,.c1(c1[11]));
csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])
,.c1(c1[12]));
csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])
,.c1(c1[13]));
csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])
,.c1(c1[14]));
csa csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64]),.c0(c0[15])
,.c1(c1[15]));
csa csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68]),.c0(c0[16])
,.c1(c1[16]));
csa csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72]),.c0(c0[17])
,.c1(c1[17]));
csa csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76]),.c0(c0[18])
,.c1(c1[18]));
csa csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80]),.c0(c0[19])
,.c1(c1[19]));
csa csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84]),.c0(c0[20])
,.c1(c1[20]));
csa csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88]),.c0(c0[21])
,.c1(c1[21]));
csa csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92]),.c0(c0[22])
,.c1(c1[22]));
csa csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96]),.c0(c0[23])
,.c1(c1[23]));
csa csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100]),.c0(c0[24])
,.c1(c1[24]));
csa csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104]),.c0(c0[25])
,.c1(c1[25]));
csa csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108]),.c0(c0[26])
,.c1(c1[26]));
csa csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112]),.c0(c0[27])
,.c1(c1[27]));
csa csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116]),.c0(c0[28])
,.c1(c1[28]));
csa csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120]),.c0(c0[29])
,.c1(c1[29]));
csa csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124]),.c0(c0[30])
,.c1(c1[30]));
csa csa_32 (.sel(sel[31]),.a(a[131:128]),.b(b[131:128]),.s(s[131:128]),.c0(c0[31])
,.c1(c1[31]));
csa csa_33 (.sel(sel[32]),.a(a[135:132]),.b(b[135:132]),.s(s[135:132]),.c0(c0[32])
,.c1(c1[32]));
csa csa_34 (.sel(sel[33]),.a(a[139:136]),.b(b[139:136]),.s(s[139:136]),.c0(c0[33])
,.c1(c1[33]));
csa csa_35 (.sel(sel[34]),.a(a[143:140]),.b(b[143:140]),.s(s[143:140]),.c0(c0[34])
,.c1(c1[34]));
csa csa_36 (.sel(sel[35]),.a(a[147:144]),.b(b[147:144]),.s(s[147:144]),.c0(c0[35])
,.c1(c1[35]));
csa csa_37 (.sel(sel[36]),.a(a[151:148]),.b(b[151:148]),.s(s[151:148]),.c0(c0[36])
,.c1(c1[36]));
csa csa_38 (.sel(sel[37]),.a(a[155:152]),.b(b[155:152]),.s(s[155:152]),.c0(c0[37])
,.c1(c1[37]));
csa csa_39 (.sel(sel[38]),.a(a[159:156]),.b(b[159:156]),.s(s[159:156]),.c0(c0[38])
,.c1(c1[38]));
csa csa_40 (.sel(sel[39]),.a(a[163:160]),.b(b[163:160]),.s(s[163:160]),.c0(c0[39])
,.c1(c1[39]));
csa csa_41 (.sel(sel[40]),.a(a[167:164]),.b(b[167:164]),.s(s[167:164]),.c0(c0[40])
,.c1(c1[40]));
csa csa_42 (.sel(sel[41]),.a(a[171:168]),.b(b[171:168]),.s(s[171:168]),.c0(c0[41])
,.c1(c1[41]));
csa csa_43 (.sel(sel[42]),.a(a[175:172]),.b(b[175:172]),.s(s[175:172]),.c0(c0[42])
,.c1(c1[42]));
csa csa_44 (.sel(sel[43]),.a(a[179:176]),.b(b[179:176]),.s(s[179:176]),.c0(c0[43])
,.c1(c1[43]));
csa csa_45 (.sel(sel[44]),.a(a[183:180]),.b(b[183:180]),.s(s[183:180]),.c0(c0[44])
,.c1(c1[44]));
csa csa_46 (.sel(sel[45]),.a(a[187:184]),.b(b[187:184]),.s(s[187:184]),.c0(c0[45])
,.c1(c1[45]));
csa csa_47 (.sel(sel[46]),.a(a[191:188]),.b(b[191:188]),.s(s[191:188]),.c0(c0[46])
,.c1(c1[46]));
csa csa_48 (.sel(sel[47]),.a(a[195:192]),.b(b[195:192]),.s(s[195:192]),.c0(c0[47])
,.c1(c1[47]));
csa csa_49 (.sel(sel[48]),.a(a[199:196]),.b(b[199:196]),.s(s[199:196]),.c0(c0[48])
,.c1(c1[48]));
csa csa_50 (.sel(sel[49]),.a(a[203:200]),.b(b[203:200]),.s(s[203:200]),.c0(c0[49])
,.c1(c1[49]));
csa csa_51 (.sel(sel[50]),.a(a[207:204]),.b(b[207:204]),.s(s[207:204]),.c0(c0[50])
,.c1(c1[50]));
csa csa_52 (.sel(sel[51]),.a(a[211:208]),.b(b[211:208]),.s(s[211:208]),.c0(c0[51])
,.c1(c1[51]));
csa csa_53 (.sel(sel[52]),.a(a[215:212]),.b(b[215:212]),.s(s[215:212]),.c0(c0[52])
,.c1(c1[52]));
csa csa_54 (.sel(sel[53]),.a(a[219:216]),.b(b[219:216]),.s(s[219:216]),.c0(c0[53])
,.c1(c1[53]));
csa csa_55 (.sel(sel[54]),.a(a[223:220]),.b(b[223:220]),.s(s[223:220]),.c0(c0[54])
,.c1(c1[54]));
csa csa_56 (.sel(sel[55]),.a(a[227:224]),.b(b[227:224]),.s(s[227:224]),.c0(c0[55])
,.c1(c1[55]));
csa csa_57 (.sel(sel[56]),.a(a[231:228]),.b(b[231:228]),.s(s[231:228]),.c0(c0[56])
,.c1(c1[56]));
csa csa_58 (.sel(sel[57]),.a(a[235:232]),.b(b[235:232]),.s(s[235:232]),.c0(c0[57])
,.c1(c1[57]));
csa csa_59 (.sel(sel[58]),.a(a[239:236]),.b(b[239:236]),.s(s[239:236]),.c0(c0[58])
,.c1(c1[58]));
csa csa_60 (.sel(sel[59]),.a(a[243:240]),.b(b[243:240]),.s(s[243:240]),.c0(c0[59])
,.c1(c1[59]));
csa csa_61 (.sel(sel[60]),.a(a[247:244]),.b(b[247:244]),.s(s[247:244]),.c0(c0[60])
,.c1(c1[60]));
csa csa_62 (.sel(sel[61]),.a(a[251:248]),.b(b[251:248]),.s(s[251:248]),.c0(c0[61])
,.c1(c1[61]));
csa csa_63 (.sel(sel[62]),.a(a[255:252]),.b(b[255:252]),.s(s[255:252]),.c0(c0[62])
,.c1(c1[62]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign sel[7] = c0[6] | (c1[6] & sel[6]);
assign sel[8] = c0[7] | (c1[7] & sel[7]);
assign sel[9] = c0[8] | (c1[8] & sel[8]);
assign sel[10] = c0[9] | (c1[9] & sel[9]);
assign sel[11] = c0[10] | (c1[10] & sel[10]);
assign sel[12] = c0[11] | (c1[11] & sel[11]);
assign sel[13] = c0[12] | (c1[12] & sel[12]);
assign sel[14] = c0[13] | (c1[13] & sel[13]);
assign sel[15] = c0[14] | (c1[14] & sel[14]);
assign sel[16] = c0[15] | (c1[15] & sel[15]);
assign sel[17] = c0[16] | (c1[16] & sel[16]);
assign sel[18] = c0[17] | (c1[17] & sel[17]);
assign sel[19] = c0[18] | (c1[18] & sel[18]);
assign sel[20] = c0[19] | (c1[19] & sel[19]);
assign sel[21] = c0[20] | (c1[20] & sel[20]);
assign sel[22] = c0[21] | (c1[21] & sel[21]);
assign sel[23] = c0[22] | (c1[22] & sel[22]);
assign sel[24] = c0[23] | (c1[23] & sel[23]);
assign sel[25] = c0[24] | (c1[24] & sel[24]);
assign sel[26] = c0[25] | (c1[25] & sel[25]);
assign sel[27] = c0[26] | (c1[26] & sel[26]);
assign sel[28] = c0[27] | (c1[27] & sel[27]);
assign sel[29] = c0[28] | (c1[28] & sel[28]);
assign sel[30] = c0[29] | (c1[29] & sel[29]);
assign sel[31] = c0[30] | (c1[30] & sel[30]);
assign sel[32] = c0[31] | (c1[31] & sel[31]);
assign sel[33] = c0[32] | (c1[32] & sel[32]);
assign sel[34] = c0[33] | (c1[33] & sel[33]);
assign sel[35] = c0[34] | (c1[34] & sel[34]);
assign sel[36] = c0[35] | (c1[35] & sel[35]);
assign sel[37] = c0[36] | (c1[36] & sel[36]);
assign sel[38] = c0[37] | (c1[37] & sel[37]);
assign sel[39] = c0[38] | (c1[38] & sel[38]);
assign sel[40] = c0[39] | (c1[39] & sel[39]);
assign sel[41] = c0[40] | (c1[40] & sel[40]);
assign sel[42] = c0[41] | (c1[41] & sel[41]);
assign sel[43] = c0[42] | (c1[42] & sel[42]);
assign sel[44] = c0[43] | (c1[43] & sel[43]);
assign sel[45] = c0[44] | (c1[44] & sel[44]);
assign sel[46] = c0[45] | (c1[45] & sel[45]);
assign sel[47] = c0[46] | (c1[46] & sel[46]);
assign sel[48] = c0[47] | (c1[47] & sel[47]);
assign sel[49] = c0[48] | (c1[48] & sel[48]);
assign sel[50] = c0[49] | (c1[49] & sel[49]);
assign sel[51] = c0[50] | (c1[50] & sel[50]);
assign sel[52] = c0[51] | (c1[51] & sel[51]);
assign sel[53] = c0[52] | (c1[52] & sel[52]);
assign sel[54] = c0[53] | (c1[53] & sel[53]);
assign sel[55] = c0[54] | (c1[54] & sel[54]);
assign sel[56] = c0[55] | (c1[55] & sel[55]);
assign sel[57] = c0[56] | (c1[56] & sel[56]);
assign sel[58] = c0[57] | (c1[57] & sel[57]);
assign sel[59] = c0[58] | (c1[58] & sel[58]);
assign sel[60] = c0[59] | (c1[59] & sel[59]);
assign sel[61] = c0[60] | (c1[60] & sel[60]);
assign sel[62] = c0[61] | (c1[61] & sel[61]);
assign cout = c0[62] | (c1[62] & sel[62]);
endmodule | module csa256bits (cin,a,b,s,cout); |
parameter n = 256;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])
,.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])
,.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])
,.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])
,.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])
,.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])
,.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])
,.c1(c1[6]));
csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])
,.c1(c1[7]));
csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])
,.c1(c1[8]));
csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])
,.c1(c1[9]));
csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])
,.c1(c1[10]));
csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])
,.c1(c1[11]));
csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])
,.c1(c1[12]));
csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])
,.c1(c1[13]));
csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])
,.c1(c1[14]));
csa csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64]),.c0(c0[15])
,.c1(c1[15]));
csa csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68]),.c0(c0[16])
,.c1(c1[16]));
csa csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72]),.c0(c0[17])
,.c1(c1[17]));
csa csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76]),.c0(c0[18])
,.c1(c1[18]));
csa csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80]),.c0(c0[19])
,.c1(c1[19]));
csa csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84]),.c0(c0[20])
,.c1(c1[20]));
csa csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88]),.c0(c0[21])
,.c1(c1[21]));
csa csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92]),.c0(c0[22])
,.c1(c1[22]));
csa csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96]),.c0(c0[23])
,.c1(c1[23]));
csa csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100]),.c0(c0[24])
,.c1(c1[24]));
csa csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104]),.c0(c0[25])
,.c1(c1[25]));
csa csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108]),.c0(c0[26])
,.c1(c1[26]));
csa csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112]),.c0(c0[27])
,.c1(c1[27]));
csa csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116]),.c0(c0[28])
,.c1(c1[28]));
csa csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120]),.c0(c0[29])
,.c1(c1[29]));
csa csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124]),.c0(c0[30])
,.c1(c1[30]));
csa csa_32 (.sel(sel[31]),.a(a[131:128]),.b(b[131:128]),.s(s[131:128]),.c0(c0[31])
,.c1(c1[31]));
csa csa_33 (.sel(sel[32]),.a(a[135:132]),.b(b[135:132]),.s(s[135:132]),.c0(c0[32])
,.c1(c1[32]));
csa csa_34 (.sel(sel[33]),.a(a[139:136]),.b(b[139:136]),.s(s[139:136]),.c0(c0[33])
,.c1(c1[33]));
csa csa_35 (.sel(sel[34]),.a(a[143:140]),.b(b[143:140]),.s(s[143:140]),.c0(c0[34])
,.c1(c1[34]));
csa csa_36 (.sel(sel[35]),.a(a[147:144]),.b(b[147:144]),.s(s[147:144]),.c0(c0[35])
,.c1(c1[35]));
csa csa_37 (.sel(sel[36]),.a(a[151:148]),.b(b[151:148]),.s(s[151:148]),.c0(c0[36])
,.c1(c1[36]));
csa csa_38 (.sel(sel[37]),.a(a[155:152]),.b(b[155:152]),.s(s[155:152]),.c0(c0[37])
,.c1(c1[37]));
csa csa_39 (.sel(sel[38]),.a(a[159:156]),.b(b[159:156]),.s(s[159:156]),.c0(c0[38])
,.c1(c1[38]));
csa csa_40 (.sel(sel[39]),.a(a[163:160]),.b(b[163:160]),.s(s[163:160]),.c0(c0[39])
,.c1(c1[39]));
csa csa_41 (.sel(sel[40]),.a(a[167:164]),.b(b[167:164]),.s(s[167:164]),.c0(c0[40])
,.c1(c1[40]));
csa csa_42 (.sel(sel[41]),.a(a[171:168]),.b(b[171:168]),.s(s[171:168]),.c0(c0[41])
,.c1(c1[41]));
csa csa_43 (.sel(sel[42]),.a(a[175:172]),.b(b[175:172]),.s(s[175:172]),.c0(c0[42])
,.c1(c1[42]));
csa csa_44 (.sel(sel[43]),.a(a[179:176]),.b(b[179:176]),.s(s[179:176]),.c0(c0[43])
,.c1(c1[43]));
csa csa_45 (.sel(sel[44]),.a(a[183:180]),.b(b[183:180]),.s(s[183:180]),.c0(c0[44])
,.c1(c1[44]));
csa csa_46 (.sel(sel[45]),.a(a[187:184]),.b(b[187:184]),.s(s[187:184]),.c0(c0[45])
,.c1(c1[45]));
csa csa_47 (.sel(sel[46]),.a(a[191:188]),.b(b[191:188]),.s(s[191:188]),.c0(c0[46])
,.c1(c1[46]));
csa csa_48 (.sel(sel[47]),.a(a[195:192]),.b(b[195:192]),.s(s[195:192]),.c0(c0[47])
,.c1(c1[47]));
csa csa_49 (.sel(sel[48]),.a(a[199:196]),.b(b[199:196]),.s(s[199:196]),.c0(c0[48])
,.c1(c1[48]));
csa csa_50 (.sel(sel[49]),.a(a[203:200]),.b(b[203:200]),.s(s[203:200]),.c0(c0[49])
,.c1(c1[49]));
csa csa_51 (.sel(sel[50]),.a(a[207:204]),.b(b[207:204]),.s(s[207:204]),.c0(c0[50])
,.c1(c1[50]));
csa csa_52 (.sel(sel[51]),.a(a[211:208]),.b(b[211:208]),.s(s[211:208]),.c0(c0[51])
,.c1(c1[51]));
csa csa_53 (.sel(sel[52]),.a(a[215:212]),.b(b[215:212]),.s(s[215:212]),.c0(c0[52])
,.c1(c1[52]));
csa csa_54 (.sel(sel[53]),.a(a[219:216]),.b(b[219:216]),.s(s[219:216]),.c0(c0[53])
,.c1(c1[53]));
csa csa_55 (.sel(sel[54]),.a(a[223:220]),.b(b[223:220]),.s(s[223:220]),.c0(c0[54])
,.c1(c1[54]));
csa csa_56 (.sel(sel[55]),.a(a[227:224]),.b(b[227:224]),.s(s[227:224]),.c0(c0[55])
,.c1(c1[55]));
csa csa_57 (.sel(sel[56]),.a(a[231:228]),.b(b[231:228]),.s(s[231:228]),.c0(c0[56])
,.c1(c1[56]));
csa csa_58 (.sel(sel[57]),.a(a[235:232]),.b(b[235:232]),.s(s[235:232]),.c0(c0[57])
,.c1(c1[57]));
csa csa_59 (.sel(sel[58]),.a(a[239:236]),.b(b[239:236]),.s(s[239:236]),.c0(c0[58])
,.c1(c1[58]));
csa csa_60 (.sel(sel[59]),.a(a[243:240]),.b(b[243:240]),.s(s[243:240]),.c0(c0[59])
,.c1(c1[59]));
csa csa_61 (.sel(sel[60]),.a(a[247:244]),.b(b[247:244]),.s(s[247:244]),.c0(c0[60])
,.c1(c1[60]));
csa csa_62 (.sel(sel[61]),.a(a[251:248]),.b(b[251:248]),.s(s[251:248]),.c0(c0[61])
,.c1(c1[61]));
csa csa_63 (.sel(sel[62]),.a(a[255:252]),.b(b[255:252]),.s(s[255:252]),.c0(c0[62])
,.c1(c1[62]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign sel[7] = c0[6] | (c1[6] & sel[6]);
assign sel[8] = c0[7] | (c1[7] & sel[7]);
assign sel[9] = c0[8] | (c1[8] & sel[8]);
assign sel[10] = c0[9] | (c1[9] & sel[9]);
assign sel[11] = c0[10] | (c1[10] & sel[10]);
assign sel[12] = c0[11] | (c1[11] & sel[11]);
assign sel[13] = c0[12] | (c1[12] & sel[12]);
assign sel[14] = c0[13] | (c1[13] & sel[13]);
assign sel[15] = c0[14] | (c1[14] & sel[14]);
assign sel[16] = c0[15] | (c1[15] & sel[15]);
assign sel[17] = c0[16] | (c1[16] & sel[16]);
assign sel[18] = c0[17] | (c1[17] & sel[17]);
assign sel[19] = c0[18] | (c1[18] & sel[18]);
assign sel[20] = c0[19] | (c1[19] & sel[19]);
assign sel[21] = c0[20] | (c1[20] & sel[20]);
assign sel[22] = c0[21] | (c1[21] & sel[21]);
assign sel[23] = c0[22] | (c1[22] & sel[22]);
assign sel[24] = c0[23] | (c1[23] & sel[23]);
assign sel[25] = c0[24] | (c1[24] & sel[24]);
assign sel[26] = c0[25] | (c1[25] & sel[25]);
assign sel[27] = c0[26] | (c1[26] & sel[26]);
assign sel[28] = c0[27] | (c1[27] & sel[27]);
assign sel[29] = c0[28] | (c1[28] & sel[28]);
assign sel[30] = c0[29] | (c1[29] & sel[29]);
assign sel[31] = c0[30] | (c1[30] & sel[30]);
assign sel[32] = c0[31] | (c1[31] & sel[31]);
assign sel[33] = c0[32] | (c1[32] & sel[32]);
assign sel[34] = c0[33] | (c1[33] & sel[33]);
assign sel[35] = c0[34] | (c1[34] & sel[34]);
assign sel[36] = c0[35] | (c1[35] & sel[35]);
assign sel[37] = c0[36] | (c1[36] & sel[36]);
assign sel[38] = c0[37] | (c1[37] & sel[37]);
assign sel[39] = c0[38] | (c1[38] & sel[38]);
assign sel[40] = c0[39] | (c1[39] & sel[39]);
assign sel[41] = c0[40] | (c1[40] & sel[40]);
assign sel[42] = c0[41] | (c1[41] & sel[41]);
assign sel[43] = c0[42] | (c1[42] & sel[42]);
assign sel[44] = c0[43] | (c1[43] & sel[43]);
assign sel[45] = c0[44] | (c1[44] & sel[44]);
assign sel[46] = c0[45] | (c1[45] & sel[45]);
assign sel[47] = c0[46] | (c1[46] & sel[46]);
assign sel[48] = c0[47] | (c1[47] & sel[47]);
assign sel[49] = c0[48] | (c1[48] & sel[48]);
assign sel[50] = c0[49] | (c1[49] & sel[49]);
assign sel[51] = c0[50] | (c1[50] & sel[50]);
assign sel[52] = c0[51] | (c1[51] & sel[51]);
assign sel[53] = c0[52] | (c1[52] & sel[52]);
assign sel[54] = c0[53] | (c1[53] & sel[53]);
assign sel[55] = c0[54] | (c1[54] & sel[54]);
assign sel[56] = c0[55] | (c1[55] & sel[55]);
assign sel[57] = c0[56] | (c1[56] & sel[56]);
assign sel[58] = c0[57] | (c1[57] & sel[57]);
assign sel[59] = c0[58] | (c1[58] & sel[58]);
assign sel[60] = c0[59] | (c1[59] & sel[59]);
assign sel[61] = c0[60] | (c1[60] & sel[60]);
assign sel[62] = c0[61] | (c1[61] & sel[61]);
assign cout = c0[62] | (c1[62] & sel[62]);
endmodule | 0 |
141,805 | data/full_repos/permissive/95987710/rtl/csa/csa32bits.v | 95,987,710 | csa32bits.v | v | 50 | 88 | [] | ['apache license'] | [] | [(21, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:34: Cannot find file containing module: 'csa'\n csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:35: Cannot find file containing module: 'csa'\n csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1]),.c1(c1[1]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:36: Cannot find file containing module: 'csa'\n csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2]),.c1(c1[2]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:37: Cannot find file containing module: 'csa'\n csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3]),.c1(c1[3]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:38: Cannot find file containing module: 'csa'\n csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4]),.c1(c1[4]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:39: Cannot find file containing module: 'csa'\n csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5]),.c1(c1[5]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa32bits.v:40: Cannot find file containing module: 'csa'\n csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6]),.c1(c1[6]));\n ^~~\n%Error: Exiting due to 8 error(s)\n" | 312,537 | module | module csa32bits (cin,a,b,s,cout);
parameter n = 32;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1]),.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2]),.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3]),.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4]),.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5]),.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6]),.c1(c1[6]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign cout = c0[6] | (c1[6] & sel[6]);
endmodule | module csa32bits (cin,a,b,s,cout); |
parameter n = 32;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1]),.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2]),.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3]),.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4]),.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5]),.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6]),.c1(c1[6]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign cout = c0[6] | (c1[6] & sel[6]);
endmodule | 0 |
141,806 | data/full_repos/permissive/95987710/rtl/csa/csa64bits.v | 95,987,710 | csa64bits.v | v | 81 | 78 | [] | ['apache license'] | [] | [(21, 80)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:34: Cannot find file containing module: 'csa'\n csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:36: Cannot find file containing module: 'csa'\n csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:38: Cannot find file containing module: 'csa'\n csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:40: Cannot find file containing module: 'csa'\n csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:42: Cannot find file containing module: 'csa'\n csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:44: Cannot find file containing module: 'csa'\n csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:46: Cannot find file containing module: 'csa'\n csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:48: Cannot find file containing module: 'csa'\n csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:50: Cannot find file containing module: 'csa'\n csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:52: Cannot find file containing module: 'csa'\n csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:54: Cannot find file containing module: 'csa'\n csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:56: Cannot find file containing module: 'csa'\n csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:58: Cannot find file containing module: 'csa'\n csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:60: Cannot find file containing module: 'csa'\n csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa64bits.v:62: Cannot find file containing module: 'csa'\n csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])\n ^~~\n%Error: Exiting due to 16 error(s)\n" | 312,538 | module | module csa64bits (cin,a,b,s,cout);
parameter n = 64;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])
,.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])
,.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])
,.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])
,.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])
,.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])
,.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])
,.c1(c1[6]));
csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])
,.c1(c1[7]));
csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])
,.c1(c1[8]));
csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])
,.c1(c1[9]));
csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])
,.c1(c1[10]));
csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])
,.c1(c1[11]));
csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])
,.c1(c1[12]));
csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])
,.c1(c1[13]));
csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])
,.c1(c1[14]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign sel[7] = c0[6] | (c1[6] & sel[6]);
assign sel[8] = c0[7] | (c1[7] & sel[7]);
assign sel[9] = c0[8] | (c1[8] & sel[8]);
assign sel[10] = c0[9] | (c1[9] & sel[9]);
assign sel[11] = c0[10] | (c1[10] & sel[10]);
assign sel[12] = c0[11] | (c1[11] & sel[11]);
assign sel[13] = c0[12] | (c1[12] & sel[12]);
assign sel[14] = c0[13] | (c1[13] & sel[13]);
assign cout = c0[14] | (c1[14] & sel[14]);
endmodule | module csa64bits (cin,a,b,s,cout); |
parameter n = 64;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0])
,.c1(c1[0]));
csa csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8]),.c0(c0[1])
,.c1(c1[1]));
csa csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12]),.c0(c0[2])
,.c1(c1[2]));
csa csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16]),.c0(c0[3])
,.c1(c1[3]));
csa csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20]),.c0(c0[4])
,.c1(c1[4]));
csa csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24]),.c0(c0[5])
,.c1(c1[5]));
csa csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28]),.c0(c0[6])
,.c1(c1[6]));
csa csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32]),.c0(c0[7])
,.c1(c1[7]));
csa csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36]),.c0(c0[8])
,.c1(c1[8]));
csa csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40]),.c0(c0[9])
,.c1(c1[9]));
csa csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44]),.c0(c0[10])
,.c1(c1[10]));
csa csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48]),.c0(c0[11])
,.c1(c1[11]));
csa csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52]),.c0(c0[12])
,.c1(c1[12]));
csa csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56]),.c0(c0[13])
,.c1(c1[13]));
csa csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60]),.c0(c0[14])
,.c1(c1[14]));
assign sel[1] = c0[0] | (c1[0] & sel[0]);
assign sel[2] = c0[1] | (c1[1] & sel[1]);
assign sel[3] = c0[2] | (c1[2] & sel[2]);
assign sel[4] = c0[3] | (c1[3] & sel[3]);
assign sel[5] = c0[4] | (c1[4] & sel[4]);
assign sel[6] = c0[5] | (c1[5] & sel[5]);
assign sel[7] = c0[6] | (c1[6] & sel[6]);
assign sel[8] = c0[7] | (c1[7] & sel[7]);
assign sel[9] = c0[8] | (c1[8] & sel[8]);
assign sel[10] = c0[9] | (c1[9] & sel[9]);
assign sel[11] = c0[10] | (c1[10] & sel[10]);
assign sel[12] = c0[11] | (c1[11] & sel[11]);
assign sel[13] = c0[12] | (c1[12] & sel[12]);
assign sel[14] = c0[13] | (c1[13] & sel[13]);
assign cout = c0[14] | (c1[14] & sel[14]);
endmodule | 0 |
141,807 | data/full_repos/permissive/95987710/rtl/csa/csa8bits.v | 95,987,710 | csa8bits.v | v | 38 | 82 | [] | ['apache license'] | [] | [(21, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/csa/csa8bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/csa/csa8bits.v:34: Cannot find file containing module: 'csa'\n csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));\n ^~~\n%Error: Exiting due to 2 error(s)\n" | 312,539 | module | module csa8bits (cin,a,b,s,cout);
parameter n = 8;
parameter m = 2;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));
assign cout = c0[0] | (c1[0] & sel[0]);
endmodule | module csa8bits (cin,a,b,s,cout); |
parameter n = 8;
parameter m = 2;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] c0,c1,sel;
cra4bits csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
csa csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.c0(c0[0]),.c1(c1[0]));
assign cout = c0[0] | (c1[0] & sel[0]);
endmodule | 0 |
141,808 | data/full_repos/permissive/95987710/rtl/csa/mux2to1.v | 95,987,710 | mux2to1.v | v | 26 | 76 | [] | ['apache license'] | [] | [(21, 25)] | null | data/verilator_xmls/088b7ac1-f479-4a41-a8c8-d016ba7efb73.xml | null | 312,540 | module | module mux2to1(sel,a, b,out);
input a, b, sel ;
output out;
assign out = (sel) ? a : b;
endmodule | module mux2to1(sel,a, b,out); |
input a, b, sel ;
output out;
assign out = (sel) ? a : b;
endmodule | 0 |
141,809 | data/full_repos/permissive/95987710/testbench/files/comp.v | 95,987,710 | comp.v | v | 57 | 178 | [] | ['apache license'] | [] | [(23, 56)] | null | null | 1: b'%Error: data/full_repos/permissive/95987710/testbench/files/comp.v:25: syntax error, unexpected \'=\', expecting IDENTIFIER\n parameter type=0; \n ^\n%Error: data/full_repos/permissive/95987710/testbench/files/comp.v:34: syntax error, unexpected ==, expecting \'(\'\n if(type==0)\n ^~\n%Error: data/full_repos/permissive/95987710/testbench/files/comp.v:41: syntax error, unexpected ==, expecting \'(\'\n if(type==0)\n ^~\n%Error: data/full_repos/permissive/95987710/testbench/files/comp.v:51: syntax error, unexpected $display\n $display("Error at Gen: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d prop_ref=%b prop_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,prop_ref,prop_duv,gen_ref,gen_duv);\n ^~~~~~~~\n%Error: Cannot continue\n' | 312,541 | module | module comp (clk,cin,a,b,cout_ref,cout_duv,s_ref,s_duv,prop_ref,gen_ref,prop_duv,gen_duv);
parameter n=0;
parameter type=0;
input clk,cout_ref,cout_duv,prop_ref,gen_ref,cin,prop_duv,gen_duv;
input [n-1:0] s_ref,s_duv,a,b;
always @(posedge clk)
begin
if(s_ref!=s_duv)
begin
if(type==0)
$display("Error at Sum: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
else
$display("Error at Sum: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d prop_ref=%b prop_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,prop_ref,prop_duv,gen_ref,gen_duv);
end
if(type==0)
begin
if(cout_ref!=cout_duv)
$display("Error at Cout: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
end
else
begin
if(prop_ref!=prop_duv)
$display("Error at Prop: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d prop_ref=%b prop_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,prop_ref,prop_duv,gen_ref,gen_duv);
if(gen_ref!=gen_duv)
$display("Error at Gen: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d prop_ref=%b prop_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,prop_ref,prop_duv,gen_ref,gen_duv);
end
end
endmodule | module comp (clk,cin,a,b,cout_ref,cout_duv,s_ref,s_duv,prop_ref,gen_ref,prop_duv,gen_duv); |
parameter n=0;
parameter type=0;
input clk,cout_ref,cout_duv,prop_ref,gen_ref,cin,prop_duv,gen_duv;
input [n-1:0] s_ref,s_duv,a,b;
always @(posedge clk)
begin
if(s_ref!=s_duv)
begin
if(type==0)
$display("Error at Sum: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
else
$display("Error at Sum: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d prop_ref=%b prop_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,prop_ref,prop_duv,gen_ref,gen_duv);
end
if(type==0)
begin
if(cout_ref!=cout_duv)
$display("Error at Cout: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
end
else
begin
if(prop_ref!=prop_duv)
$display("Error at Prop: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d prop_ref=%b prop_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,prop_ref,prop_duv,gen_ref,gen_duv);
if(gen_ref!=gen_duv)
$display("Error at Gen: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d prop_ref=%b prop_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,prop_ref,prop_duv,gen_ref,gen_duv);
end
end
endmodule | 0 |
141,810 | data/full_repos/permissive/95987710/testbench/files/gen_table.v | 95,987,710 | gen_table.v | v | 79 | 76 | [] | ['apache license'] | [] | [(22, 78)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95987710/testbench/files/gen_table.v:67: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 32 bits.\n : ... In instance gen_table\n temp_a=k;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95987710/testbench/files/gen_table.v:68: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n : ... In instance gen_table\n temp_b=j;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95987710/testbench/files/gen_table.v:69: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n : ... In instance gen_table\n temp_cin=i;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 312,542 | module | module gen_table (clk,cin,a,b);
parameter n = 4;
parameter file_size=100;
parameter tam="2";
input clk;
output cin;
output [n-1:0]a,b;
reg temp_cin;
reg [n-1:0] temp_a,temp_b;
integer i,j,k,n_vector;
initial begin
n_vector=1;
for(i=0;i<n;i=i+1) begin
n_vector=2*n_vector;
end
i=0;
j=0;
k=0;
end
always @ (negedge clk)
begin
if(i==1) begin
if((j+1)==n_vector) begin
if(k==n_vector) begin
$finish;
end
end
end
if(i==500)
$finish;
if(k==n_vector) begin
k=0;
j=j+1;
end
if(j==n_vector) begin
j=0;
i=i+1;
end
temp_a=k;
temp_b=j;
temp_cin=i;
k=k+1;
end
assign cin=temp_cin;
assign a=temp_a;
assign b=temp_b;
endmodule | module gen_table (clk,cin,a,b); |
parameter n = 4;
parameter file_size=100;
parameter tam="2";
input clk;
output cin;
output [n-1:0]a,b;
reg temp_cin;
reg [n-1:0] temp_a,temp_b;
integer i,j,k,n_vector;
initial begin
n_vector=1;
for(i=0;i<n;i=i+1) begin
n_vector=2*n_vector;
end
i=0;
j=0;
k=0;
end
always @ (negedge clk)
begin
if(i==1) begin
if((j+1)==n_vector) begin
if(k==n_vector) begin
$finish;
end
end
end
if(i==500)
$finish;
if(k==n_vector) begin
k=0;
j=j+1;
end
if(j==n_vector) begin
j=0;
i=i+1;
end
temp_a=k;
temp_b=j;
temp_cin=i;
k=k+1;
end
assign cin=temp_cin;
assign a=temp_a;
assign b=temp_b;
endmodule | 0 |
141,811 | data/full_repos/permissive/95987710/testbench/files/in.v | 95,987,710 | in.v | v | 63 | 76 | [] | ['apache license'] | [] | [(22, 62)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95987710/testbench/files/in.v:49: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 5 bits.\n : ... In instance in\n temp_a=data[i];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95987710/testbench/files/in.v:51: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 5 bits.\n : ... In instance in\n temp_b=data[i];\n ^\n%Warning-WIDTH: data/full_repos/permissive/95987710/testbench/files/in.v:53: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 5 bits.\n : ... In instance in\n temp_cin=data[i];\n ^\n%Error: Exiting due to 3 warning(s)\n' | 312,543 | module | module in (clk,cin,a,b);
parameter n = 4;
parameter file_size=100;
parameter tam="2";
reg [n:0] data [file_size-1:0];
input clk;
output cin;
output [n-1:0]a,b;
reg temp_cin;
reg [n-1:0] temp_a,temp_b;
integer i;
initial begin
i=0;
$readmemh( {"stimulus/random_stimulus_",tam,"bits"},data);
end
always @ (negedge clk)
begin
if(i==file_size)
$finish;
temp_a=data[i];
i=i+1;
temp_b=data[i];
i=i+1;
temp_cin=data[i];
i=i+1;
end
assign cin=temp_cin;
assign a=temp_a;
assign b=temp_b;
endmodule | module in (clk,cin,a,b); |
parameter n = 4;
parameter file_size=100;
parameter tam="2";
reg [n:0] data [file_size-1:0];
input clk;
output cin;
output [n-1:0]a,b;
reg temp_cin;
reg [n-1:0] temp_a,temp_b;
integer i;
initial begin
i=0;
$readmemh( {"stimulus/random_stimulus_",tam,"bits"},data);
end
always @ (negedge clk)
begin
if(i==file_size)
$finish;
temp_a=data[i];
i=i+1;
temp_b=data[i];
i=i+1;
temp_cin=data[i];
i=i+1;
end
assign cin=temp_cin;
assign a=temp_a;
assign b=temp_b;
endmodule | 0 |
141,812 | data/full_repos/permissive/95987710/testbench/files/out.v | 95,987,710 | out.v | v | 47 | 103 | [] | ['apache license'] | [] | [(22, 46)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/testbench/files/out.v:24: syntax error, unexpected '=', expecting IDENTIFIER\n parameter type=0; \n ^\n%Error: data/full_repos/permissive/95987710/testbench/files/out.v:40: syntax error, unexpected ==, expecting '('\n if(type==1)\n ^~\n%Error: Exiting due to 2 error(s)\n" | 312,544 | module | module out (clk,cin,a,b,cout_ref,cout_duv,s_ref,s_duv,prop_ref,gen_ref,prop_duv,gen_duv);
parameter n = 4;
parameter type=0;
parameter design_path = "a";
input clk,cout_ref,cout_duv,prop_ref,gen_ref,cin,prop_duv,gen_duv;
input [n-1:0] s_ref,s_duv,a,b;
integer file;
initial begin
file=$fopen(design_path,"w");
end
always @ (posedge clk)
begin
$fwrite(file,"@%t#cin=%b#a=%d#b=%d#s_ref=%d#s_duv=%d",$time, cin,a,b,s_ref,s_duv);
$fwrite(file,"#cout_ref=%b#cout_duv=%b",cout_ref,cout_duv);
if(type==1)
$fwrite(file,"#prop_ref=%b#prop_duv=%b#gen_ref=%b#gen_duv=%b\n",prop_ref,prop_duv,gen_ref,gen_duv);
else
$fwrite(file,"\n");
end
endmodule | module out (clk,cin,a,b,cout_ref,cout_duv,s_ref,s_duv,prop_ref,gen_ref,prop_duv,gen_duv); |
parameter n = 4;
parameter type=0;
parameter design_path = "a";
input clk,cout_ref,cout_duv,prop_ref,gen_ref,cin,prop_duv,gen_duv;
input [n-1:0] s_ref,s_duv,a,b;
integer file;
initial begin
file=$fopen(design_path,"w");
end
always @ (posedge clk)
begin
$fwrite(file,"@%t#cin=%b#a=%d#b=%d#s_ref=%d#s_duv=%d",$time, cin,a,b,s_ref,s_duv);
$fwrite(file,"#cout_ref=%b#cout_duv=%b",cout_ref,cout_duv);
if(type==1)
$fwrite(file,"#prop_ref=%b#prop_duv=%b#gen_ref=%b#gen_duv=%b\n",prop_ref,prop_duv,gen_ref,gen_duv);
else
$fwrite(file,"\n");
end
endmodule | 0 |
141,813 | data/full_repos/permissive/95987710/testbench/files/ref_adder.v | 95,987,710 | ref_adder.v | v | 51 | 76 | [] | ['apache license'] | [] | [(22, 50)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95987710/testbench/files/ref_adder.v:33: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n : ... In instance ref_adder\n assign temp = a + b + cin;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,545 | module | module ref_adder (cin,a,b,s,cout,prop,gen);
parameter n = 4;
integer i;
input cin;
input [n-1:0] a, b;
output [n-1:0] s;
output cout,prop,gen;
wire [n:0]temp,temp2;
reg p;
assign temp = a + b + cin;
assign s = temp[n-1:0];
assign cout = temp[n];
assign temp2 = a + b;
assign gen=temp2[n];
assign prop=p;
always @(cin or a or b) begin
p=1'b1;
for (i = 0; i < n; i = i +1) begin
p=p & (a[i] ^ b[i]);
end
end
endmodule | module ref_adder (cin,a,b,s,cout,prop,gen); |
parameter n = 4;
integer i;
input cin;
input [n-1:0] a, b;
output [n-1:0] s;
output cout,prop,gen;
wire [n:0]temp,temp2;
reg p;
assign temp = a + b + cin;
assign s = temp[n-1:0];
assign cout = temp[n];
assign temp2 = a + b;
assign gen=temp2[n];
assign prop=p;
always @(cin or a or b) begin
p=1'b1;
for (i = 0; i < n; i = i +1) begin
p=p & (a[i] ^ b[i]);
end
end
endmodule | 0 |
141,814 | data/full_repos/permissive/95987710/testbench/files/testbench.v | 95,987,710 | testbench.v | v | 73 | 189 | [] | ['apache license'] | [] | null | line:34: before: "." | null | 1: b'%Error: data/full_repos/permissive/95987710/testbench/files/testbench.v:25: syntax error, unexpected \'=\', expecting IDENTIFIER\n parameter type=0; \n ^\n%Error: data/full_repos/permissive/95987710/testbench/files/testbench.v:34: syntax error, unexpected ref, expecting IDENTIFIER\n defparam ref.n=n;\n ^~~\n%Error: data/full_repos/permissive/95987710/testbench/files/testbench.v:37: syntax error, unexpected type, expecting IDENTIFIER\n defparam write.type=type;\n ^~~~\n%Error: data/full_repos/permissive/95987710/testbench/files/testbench.v:41: syntax error, unexpected ref, expecting IDENTIFIER\n ref_adder ref (.cin(cin),.a(a),.b(b),.s(s_ref),.cout(cout_ref),.prop(prop_ref),.gen(gen_ref));\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/95987710/testbench/files/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/95987710/testbench/files/testbench.v:63: syntax error, unexpected ==, expecting \'(\'\n if(type==1)\n ^~\n%Error: data/full_repos/permissive/95987710/testbench/files/testbench.v:70: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 312,546 | module | module testbench ();
parameter n = 2;
parameter type=0;
integer i;
wire cin,cout_ref,cout_duv,prop_ref,gen_ref,prop_duv,gen_duv,prop,gen;
wire [n-1:0] a,b,s_ref,s_duv;
reg clk;
defparam ref.n=n;
defparam duv.n=n;
defparam write.n=n;
defparam write.type=type;
defparam read.n=n;
defparam read.file_size=96;
ref_adder ref (.cin(cin),.a(a),.b(b),.s(s_ref),.cout(cout_ref),.prop(prop_ref),.gen(gen_ref));
cra2bits duv (.cin(cin),.a(a),.b(b),.s(s_duv),.cout(cout_duv));
in read(.clk(clk),.cin(cin),.a(a),.b(b));
out write(.clk(clk),.cin(cin),.a(a),.b(b),.cout_ref(cout_ref),.cout_duv(cout_duv),.s_ref(s_ref),.s_duv(s_duv),.prop_ref(prop_ref),.gen_ref(gen_ref),.prop_duv(prop_duv),.gen_duv(gen_duv));
always #50 clk = ~clk;
initial begin
read.path_file={"stimulus/stimulus_","2bits"};
write.path={"log/log_","cra","2bits"};
clk = 1'b0;
end
always @(posedge clk)
begin
if(s_ref!=s_duv)
$display("Error at Sum: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
if(cout_ref!=cout_duv)
$display("Error at Cout: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
if(type==1)
begin
if(prop_ref!=prop_duv)
$display("Error at Prop: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b prop_ref=%b prop_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv,prop_ref,prop_duv);
if(gen_ref!=gen_duv)
$display("Error at Gen: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv,gen_ref,gen_duv);
end
end
endmodule | module testbench (); |
parameter n = 2;
parameter type=0;
integer i;
wire cin,cout_ref,cout_duv,prop_ref,gen_ref,prop_duv,gen_duv,prop,gen;
wire [n-1:0] a,b,s_ref,s_duv;
reg clk;
defparam ref.n=n;
defparam duv.n=n;
defparam write.n=n;
defparam write.type=type;
defparam read.n=n;
defparam read.file_size=96;
ref_adder ref (.cin(cin),.a(a),.b(b),.s(s_ref),.cout(cout_ref),.prop(prop_ref),.gen(gen_ref));
cra2bits duv (.cin(cin),.a(a),.b(b),.s(s_duv),.cout(cout_duv));
in read(.clk(clk),.cin(cin),.a(a),.b(b));
out write(.clk(clk),.cin(cin),.a(a),.b(b),.cout_ref(cout_ref),.cout_duv(cout_duv),.s_ref(s_ref),.s_duv(s_duv),.prop_ref(prop_ref),.gen_ref(gen_ref),.prop_duv(prop_duv),.gen_duv(gen_duv));
always #50 clk = ~clk;
initial begin
read.path_file={"stimulus/stimulus_","2bits"};
write.path={"log/log_","cra","2bits"};
clk = 1'b0;
end
always @(posedge clk)
begin
if(s_ref!=s_duv)
$display("Error at Sum: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
if(cout_ref!=cout_duv)
$display("Error at Cout: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv);
if(type==1)
begin
if(prop_ref!=prop_duv)
$display("Error at Prop: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b prop_ref=%b prop_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv,prop_ref,prop_duv);
if(gen_ref!=gen_duv)
$display("Error at Gen: t=%t cin=%b a=%d b=%d s_ref=%d s_duv=%d cout_ref=%b cout_duv=%b gen_ref=%b gen_duv=%b",$time,cin,a,b,s_ref,s_duv,cout_ref,cout_duv,gen_ref,gen_duv);
end
end
endmodule | 0 |
141,815 | data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v | 95,987,710 | testbench_a1csah256bits.v | v | 65 | 195 | [] | ['apache license'] | [] | null | line:43: before: "." | null | 1: b'%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:26: Unsupported: Verilog 2001-config reserved word not implemented: \'design\'\n parameter design = "a1csah";\n ^~~~~~\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:26: syntax error, unexpected \'=\', expecting \'[\'\n parameter design = "a1csah";\n ^\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:27: syntax error, unexpected \'=\', expecting IDENTIFIER\n parameter type=1; \n ^\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:37: syntax error, unexpected ref, expecting IDENTIFIER\n ref_adder ref (.cin(cin),.a(a),.b(b),.s(s_ref),.cout(cout_ref),.prop(prop_ref),.gen(gen_ref));\n ^~~\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:43: syntax error, unexpected ref, expecting IDENTIFIER\n defparam ref.n=n;\n ^~~\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:46: syntax error, unexpected type, expecting IDENTIFIER\n defparam write.type=type;\n ^~~~\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:47: Unsupported: Verilog 2001-config reserved word not implemented: \'design\'\n defparam write.design_path={"log/log_",design,tam,"bits"};\n ^~~~~~\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:47: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n defparam write.design_path={"log/log_",design,tam,"bits"};\n ^\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:52: syntax error, unexpected type, expecting IDENTIFIER\n defparam comp.type=type;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:55: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:60: Unsupported or unknown PLI call: $dumpfile\n $dumpfile({"switch_activity/",design,tam,"bits.vcd"});\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:60: Unsupported: Verilog 2001-config reserved word not implemented: \'design\'\n $dumpfile({"switch_activity/",design,tam,"bits.vcd"});\n ^~~~~~\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:60: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n $dumpfile({"switch_activity/",design,tam,"bits.vcd"});\n ^\n%Error: data/full_repos/permissive/95987710/testbench/files/a1csah/testbench_a1csah256bits.v:61: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(10,testbench_a1csah256bits.a1csah256bits);\n ^~~~~~~~~\n%Error: Exiting due to 13 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,555 | module | module testbench_a1csah256bits ();
parameter n = 256;
parameter tam = "256";
parameter design = "a1csah";
parameter type=1;
parameter file_size=30000;
wire cin,cout_ref,cout_duv,prop_ref,gen_ref,prop_duv,gen_duv,prop,gen;
wire [n-1:0] a,b,s_ref,s_duv;
reg clk;
a1csah256bits a1csah256bits (.cin(cin),.a(a),.b(b),.s(s_duv),.gen(gen_duv),.prop(prop_duv),.cout(cout_duv));
ref_adder ref (.cin(cin),.a(a),.b(b),.s(s_ref),.cout(cout_ref),.prop(prop_ref),.gen(gen_ref));
in read(.clk(clk),.cin(cin),.a(a),.b(b));
out write(.clk(clk),.cin(cin),.a(a),.b(b),.cout_ref(cout_ref),.cout_duv(cout_duv),.s_ref(s_ref),.s_duv(s_duv),.prop_ref(prop_ref),.gen_ref(gen_ref),.prop_duv(prop_duv),.gen_duv(gen_duv));
comp comparator(.clk(clk),.cin(cin),.a(a),.b(b),.cout_ref(cout_ref),.cout_duv(cout_duv),.s_ref(s_ref),.s_duv(s_duv),.prop_ref(prop_ref),.gen_ref(gen_ref),.prop_duv(prop_duv),.gen_duv(gen_duv));
defparam ref.n=n;
defparam a1csah256bits.n=n;
defparam write.n=n;
defparam write.type=type;
defparam write.design_path={"log/log_",design,tam,"bits"};
defparam read.n=n;
defparam read.file_size=file_size;
defparam read.tam=tam;
defparam comp.n=n;
defparam comp.type=type;
always #50 clk = ~clk;
integer i;
initial begin
$dumpfile({"switch_activity/",design,tam,"bits.vcd"});
$dumpvars(10,testbench_a1csah256bits.a1csah256bits);
clk = 1'b0;
end
endmodule | module testbench_a1csah256bits (); |
parameter n = 256;
parameter tam = "256";
parameter design = "a1csah";
parameter type=1;
parameter file_size=30000;
wire cin,cout_ref,cout_duv,prop_ref,gen_ref,prop_duv,gen_duv,prop,gen;
wire [n-1:0] a,b,s_ref,s_duv;
reg clk;
a1csah256bits a1csah256bits (.cin(cin),.a(a),.b(b),.s(s_duv),.gen(gen_duv),.prop(prop_duv),.cout(cout_duv));
ref_adder ref (.cin(cin),.a(a),.b(b),.s(s_ref),.cout(cout_ref),.prop(prop_ref),.gen(gen_ref));
in read(.clk(clk),.cin(cin),.a(a),.b(b));
out write(.clk(clk),.cin(cin),.a(a),.b(b),.cout_ref(cout_ref),.cout_duv(cout_duv),.s_ref(s_ref),.s_duv(s_duv),.prop_ref(prop_ref),.gen_ref(gen_ref),.prop_duv(prop_duv),.gen_duv(gen_duv));
comp comparator(.clk(clk),.cin(cin),.a(a),.b(b),.cout_ref(cout_ref),.cout_duv(cout_duv),.s_ref(s_ref),.s_duv(s_duv),.prop_ref(prop_ref),.gen_ref(gen_ref),.prop_duv(prop_duv),.gen_duv(gen_duv));
defparam ref.n=n;
defparam a1csah256bits.n=n;
defparam write.n=n;
defparam write.type=type;
defparam write.design_path={"log/log_",design,tam,"bits"};
defparam read.n=n;
defparam read.file_size=file_size;
defparam read.tam=tam;
defparam comp.n=n;
defparam comp.type=type;
always #50 clk = ~clk;
integer i;
initial begin
$dumpfile({"switch_activity/",design,tam,"bits.vcd"});
$dumpvars(10,testbench_a1csah256bits.a1csah256bits);
clk = 1'b0;
end
endmodule | 0 |
141,818 | data/full_repos/permissive/9603186/src/Control.v | 9,603,186 | Control.v | v | 27 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/994b0279-f1c0-43ce-b543-48dbf157e55d.xml | null | 312,583 | module | module Control(
);
endmodule | module Control(
); |
endmodule | 5 |
141,819 | data/full_repos/permissive/9603186/src/CPU.v | 9,603,186 | CPU.v | v | 36 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/9603186/src/CPU.v:34: Cannot find file containing module: 'DataPath'\n DataPath DataPath();\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/DataPath\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/DataPath.v\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/DataPath.sv\n DataPath\n DataPath.v\n DataPath.sv\n obj_dir/DataPath\n obj_dir/DataPath.v\n obj_dir/DataPath.sv\n%Error: Exiting due to 1 error(s)\n" | 312,584 | module | module CPU(
input wire clock,
input wire reset,
input wire CS_Branch,
input wire CS_RegWrite,
input wire [4:0] RegDisplay,
output wire [31:0] RegDispData
);
DataPath DataPath();
endmodule | module CPU(
input wire clock,
input wire reset,
input wire CS_Branch,
input wire CS_RegWrite,
input wire [4:0] RegDisplay,
output wire [31:0] RegDispData
); |
DataPath DataPath();
endmodule | 5 |
141,820 | data/full_repos/permissive/9603186/src/DataPath.v | 9,603,186 | DataPath.v | v | 167 | 83 | [] | [] | [] | null | line:156: before: ")" | null | 1: b"%Error: data/full_repos/permissive/9603186/src/DataPath.v:25: Cannot find file containing module: 'Registers'\n Registers Registers(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/Registers\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/Registers.v\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/Registers.sv\n Registers\n Registers.v\n Registers.sv\n obj_dir/Registers\n obj_dir/Registers.v\n obj_dir/Registers.sv\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:40: Cannot find file containing module: 'Stage_IF'\n Stage_IF Stage_IF(\n ^~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:57: Cannot find file containing module: 'PipelineReg_IFID'\n PipelineReg_IFID PipelineReg_IFID(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:72: Cannot find file containing module: 'Stage_ID'\n Stage_ID Stage_ID(\n ^~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:93: Cannot find file containing module: 'PipelineReg_IDEX'\n PipelineReg_IDEX PipelineReg_IDEX(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:114: Cannot find file containing module: 'Stage_EX'\n Stage_EX Stage_EX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:133: Cannot find file containing module: 'PipelineReg_EXMEM'\n PipelineReg_EXMEM PipelineReg_EXMEM(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:158: Cannot find file containing module: 'Stage_MEM'\n Stage_MEM Stage_MEM(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:161: Cannot find file containing module: 'PipelineReg_MEMWB'\n PipelineReg_MEMWB PipelineReg_MEMWB(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/DataPath.v:164: Cannot find file containing module: 'Stage_WB'\n Stage_WB Stage_WB(\n ^~~~~~~~\n%Error: Exiting due to 10 error(s)\n" | 312,585 | module | module DataPath(
);
Registers Registers(
.clock(clock),
.reset(reset),
.rs(RegAdd_rs),
.rt(RegAdd_rt),
.rd(RegAdd_rd),
.rdin(),
.we(CS_RegWrite),
.douts(RegData_rs),
.doutt(RegData_rt),
.rdisp(RegDisplay),
.ddisp(RegDispData)
);
Stage_IF Stage_IF(
.clock(clock),
.reset(reset),
.PR_EXMEM_ALUOutput(ToWB_ALUOutput),
.CS_Branch(CS_Branch),
.EndStageIF_PC(FromIF_PC),
.EndStageIF_NewPC(FromIF_NewPC),
.EndStageIF_Inst(FromIF_Inst),
.EndStageIF_InstNum(FromIF_InstNum),
.EndStageIF_InstType(FromIF_InstType)
);
wire [3:0] StageID_InstNum;
wire [3:0] StageID_InstType;
PipelineReg_IFID PipelineReg_IFID(
.clock(clock),
.reset(reset),
.FromIF_Inst(FromIF_Inst),
.FromIF_NewPC(FromIF_NewPC),
.FromIF_InstNum(FromIF_InstNum),
.FromIF_InstType(FromIF_InstType),
.ToID_Inst(ToID_Inst),
.ToID_NewPC(ToID_NewPC),
.ToID_InstNum(StageID_InstNum),
.ToID_InstType(StageID_InstType)
);
Stage_ID Stage_ID(
.clock(clock),
.reset(reset),
.BeginStageID_Inst(ToID_Inst),
.BeginStageID_NewPC(ToID_NewPC),
.RegAdd_rs(RegAdd_rs),
.RegAdd_rt(RegAdd_rt),
.RegData_rs(RegData_rs),
.RegData_rt(RegData_rt),
.EndStageID_Inst(FromID_Inst),
.EndStageID_RegDataA(FromID_RegDataA),
.EndStageID_RegDataB(FromID_RegDataB),
.EndStageID_Imm(FromID_Imm)
);
wire [3:0] StageEX_InstNum;
wire [3:0] StageEX_InstType;
PipelineReg_IDEX PipelineReg_IDEX(
.clock(clock),
.reset(reset),
.FromID_Inst(FromID_Inst),
.FromID_NewPC(ToID_NewPC),
.FromID_RegDataA(FromID_RegDataA),
.FromID_RegDataB(FromID_RegDataB),
.FromID_Imm(FromID_Imm),
.FromID_InstNum(StageID_InstNum),
.FromID_InstType(StageID_InstType),
.ToEX_Inst(ToEX_Inst),
.ToEX_NewPC(ToEX_NewPC),
.ToEX_RegDataA(ToEX_RegDataA),
.ToEX_RegDataB(ToEX_RegDataB),
.ToEX_Imm(ToEX_Imm),
.ToEX_InstNum(StageEX_InstNum),
.ToEX_InstType(StageEX_InstType)
);
Stage_EX Stage_EX(
.BeginStageEX_Inst(ToEX_Inst),
.BeginStageEX_NewPC(ToEX_NewPC),
.BeginStageEX_RegDataA(ToEX_RegDataA),
.BeginStageEX_RegDataB(ToEX_RegDataB),
.BeginStageEX_Imm(ToEX_Imm),
.EndStageEX_Inst(FromEX_Inst),
.EndStageEX_NewPC(FromEX_NewPC),
.EndStageEX_RegDataA(FromEX_RegDataA),
.EndStageEX_RegDataB(FromEX_RegDataB),
.EndStageEX_Imm(FromEX_Imm),
.EndStageEX_ALUOutput(FromEX_ALUOutput),
.EndStageEX_Condition(FromEX_Condition)
);
wire [3:0] StageMEM_InstNum;
wire [3:0] StageMEM_InstType;
PipelineReg_EXMEM PipelineReg_EXMEM(
.clock(clock),
.reset(reset),
.FromEX_Inst(FromEX_Inst),
.FromEX_NewPC(FromEX_NewPC),
.FromEX_RegDataA(FromEX_RegDataA),
.FromEX_RegDataB(FromEX_RegDataB),
.FromEX_Imm(FromEX_Imm),
.FromEX_ALUOutput(FromEX_ALUOutput),
.FromEX_Condition(FromEX_Condition),
.FromEX_InstNum(StageEX_InstNum),
.FromEX_InstType(StageEX_InstType),
.ToMEM_Inst(ToMEM_Inst),
.ToMEM_NewPC(ToMEM_NewPC),
.ToMEM_RegDataA(ToMEM_RegDataA),
.ToMEM_RegDataB(ToMEM_RegDataB),
.ToMEM_Imm(ToMEM_Imm),
.ToMEM_ALUOutput(ToMEM_ALUOutput),
.ToMEM_Condition(ToMEM_Cond),
.ToMEM_InstNum(StageMEM_InstNum),
.ToMEM_InstType(StageMEM_InstType),
);
Stage_MEM Stage_MEM(
);
PipelineReg_MEMWB PipelineReg_MEMWB(
);
Stage_WB Stage_WB(
);
endmodule | module DataPath(
); |
Registers Registers(
.clock(clock),
.reset(reset),
.rs(RegAdd_rs),
.rt(RegAdd_rt),
.rd(RegAdd_rd),
.rdin(),
.we(CS_RegWrite),
.douts(RegData_rs),
.doutt(RegData_rt),
.rdisp(RegDisplay),
.ddisp(RegDispData)
);
Stage_IF Stage_IF(
.clock(clock),
.reset(reset),
.PR_EXMEM_ALUOutput(ToWB_ALUOutput),
.CS_Branch(CS_Branch),
.EndStageIF_PC(FromIF_PC),
.EndStageIF_NewPC(FromIF_NewPC),
.EndStageIF_Inst(FromIF_Inst),
.EndStageIF_InstNum(FromIF_InstNum),
.EndStageIF_InstType(FromIF_InstType)
);
wire [3:0] StageID_InstNum;
wire [3:0] StageID_InstType;
PipelineReg_IFID PipelineReg_IFID(
.clock(clock),
.reset(reset),
.FromIF_Inst(FromIF_Inst),
.FromIF_NewPC(FromIF_NewPC),
.FromIF_InstNum(FromIF_InstNum),
.FromIF_InstType(FromIF_InstType),
.ToID_Inst(ToID_Inst),
.ToID_NewPC(ToID_NewPC),
.ToID_InstNum(StageID_InstNum),
.ToID_InstType(StageID_InstType)
);
Stage_ID Stage_ID(
.clock(clock),
.reset(reset),
.BeginStageID_Inst(ToID_Inst),
.BeginStageID_NewPC(ToID_NewPC),
.RegAdd_rs(RegAdd_rs),
.RegAdd_rt(RegAdd_rt),
.RegData_rs(RegData_rs),
.RegData_rt(RegData_rt),
.EndStageID_Inst(FromID_Inst),
.EndStageID_RegDataA(FromID_RegDataA),
.EndStageID_RegDataB(FromID_RegDataB),
.EndStageID_Imm(FromID_Imm)
);
wire [3:0] StageEX_InstNum;
wire [3:0] StageEX_InstType;
PipelineReg_IDEX PipelineReg_IDEX(
.clock(clock),
.reset(reset),
.FromID_Inst(FromID_Inst),
.FromID_NewPC(ToID_NewPC),
.FromID_RegDataA(FromID_RegDataA),
.FromID_RegDataB(FromID_RegDataB),
.FromID_Imm(FromID_Imm),
.FromID_InstNum(StageID_InstNum),
.FromID_InstType(StageID_InstType),
.ToEX_Inst(ToEX_Inst),
.ToEX_NewPC(ToEX_NewPC),
.ToEX_RegDataA(ToEX_RegDataA),
.ToEX_RegDataB(ToEX_RegDataB),
.ToEX_Imm(ToEX_Imm),
.ToEX_InstNum(StageEX_InstNum),
.ToEX_InstType(StageEX_InstType)
);
Stage_EX Stage_EX(
.BeginStageEX_Inst(ToEX_Inst),
.BeginStageEX_NewPC(ToEX_NewPC),
.BeginStageEX_RegDataA(ToEX_RegDataA),
.BeginStageEX_RegDataB(ToEX_RegDataB),
.BeginStageEX_Imm(ToEX_Imm),
.EndStageEX_Inst(FromEX_Inst),
.EndStageEX_NewPC(FromEX_NewPC),
.EndStageEX_RegDataA(FromEX_RegDataA),
.EndStageEX_RegDataB(FromEX_RegDataB),
.EndStageEX_Imm(FromEX_Imm),
.EndStageEX_ALUOutput(FromEX_ALUOutput),
.EndStageEX_Condition(FromEX_Condition)
);
wire [3:0] StageMEM_InstNum;
wire [3:0] StageMEM_InstType;
PipelineReg_EXMEM PipelineReg_EXMEM(
.clock(clock),
.reset(reset),
.FromEX_Inst(FromEX_Inst),
.FromEX_NewPC(FromEX_NewPC),
.FromEX_RegDataA(FromEX_RegDataA),
.FromEX_RegDataB(FromEX_RegDataB),
.FromEX_Imm(FromEX_Imm),
.FromEX_ALUOutput(FromEX_ALUOutput),
.FromEX_Condition(FromEX_Condition),
.FromEX_InstNum(StageEX_InstNum),
.FromEX_InstType(StageEX_InstType),
.ToMEM_Inst(ToMEM_Inst),
.ToMEM_NewPC(ToMEM_NewPC),
.ToMEM_RegDataA(ToMEM_RegDataA),
.ToMEM_RegDataB(ToMEM_RegDataB),
.ToMEM_Imm(ToMEM_Imm),
.ToMEM_ALUOutput(ToMEM_ALUOutput),
.ToMEM_Condition(ToMEM_Cond),
.ToMEM_InstNum(StageMEM_InstNum),
.ToMEM_InstType(StageMEM_InstType),
);
Stage_MEM Stage_MEM(
);
PipelineReg_MEMWB PipelineReg_MEMWB(
);
Stage_WB Stage_WB(
);
endmodule | 5 |
141,821 | data/full_repos/permissive/9603186/src/PipelineReg_EXMEM.v | 9,603,186 | PipelineReg_EXMEM.v | v | 70 | 83 | [] | [] | [] | [(21, 69)] | null | data/verilator_xmls/1e34cade-f29d-4ae2-a209-950707bc3be5.xml | null | 312,586 | module | module PipelineReg_EXMEM(
input wire clock,
input wire reset,
input wire [31:0] FromEX_Inst,
input wire [31:0] FromEX_NewPC,
input wire [31:0] FromEX_RegDataA,
input wire [31:0] FromEX_RegDataB,
input wire [31:0] FromEX_Imm,
input wire [31:0] FromEX_ALUOutput,
input wire FromEX_Condition,
input wire [3:0] FromEX_InstNum,
input wire [3:0] FromEX_InstType,
output reg [31:0] ToMEM_Inst,
output reg [31:0] ToMEM_NewPC,
output reg [31:0] ToMEM_RegDataA,
output reg [31:0] ToMEM_RegDataB,
output reg [31:0] ToMEM_Imm,
output reg [31:0] ToMEM_ALUOutput,
output reg ToMEM_Condition,
output reg [3:0] ToMEM_InstNum,
output reg [3:0] ToMEM_InstType
);
always @ (posedge clock or posedge reset) begin
if (reset == 1) begin
ToMEM_Inst <= 32'b0;
ToMEM_NewPC <= 32'b0;
ToMEM_RegDataA <= 32'b0;
ToMEM_RegDataB <= 32'b0;
ToMEM_Imm <= 32'b0;
ToMEM_InstNum <= 4'b0;
ToMEM_InstType <= 4'b0;
end
else begin
ToMEM_Inst <= FromEX_Inst;
ToMEM_NewPC <= FromEX_NewPC;
ToMEM_RegDataA <= FromEX_RegDataA;
ToMEM_RegDataB <= FromEX_RegDataB;
ToMEM_Imm <= FromEX_Imm;
ToMEM_ALUOutput <= FromEX_ALUOutput;
ToMEM_Condition <= FromEX_Condition;
ToMEM_InstNum <= FromEX_InstNum;
ToMEM_InstType <= FromEX_InstType;
end
end
endmodule | module PipelineReg_EXMEM(
input wire clock,
input wire reset,
input wire [31:0] FromEX_Inst,
input wire [31:0] FromEX_NewPC,
input wire [31:0] FromEX_RegDataA,
input wire [31:0] FromEX_RegDataB,
input wire [31:0] FromEX_Imm,
input wire [31:0] FromEX_ALUOutput,
input wire FromEX_Condition,
input wire [3:0] FromEX_InstNum,
input wire [3:0] FromEX_InstType,
output reg [31:0] ToMEM_Inst,
output reg [31:0] ToMEM_NewPC,
output reg [31:0] ToMEM_RegDataA,
output reg [31:0] ToMEM_RegDataB,
output reg [31:0] ToMEM_Imm,
output reg [31:0] ToMEM_ALUOutput,
output reg ToMEM_Condition,
output reg [3:0] ToMEM_InstNum,
output reg [3:0] ToMEM_InstType
); |
always @ (posedge clock or posedge reset) begin
if (reset == 1) begin
ToMEM_Inst <= 32'b0;
ToMEM_NewPC <= 32'b0;
ToMEM_RegDataA <= 32'b0;
ToMEM_RegDataB <= 32'b0;
ToMEM_Imm <= 32'b0;
ToMEM_InstNum <= 4'b0;
ToMEM_InstType <= 4'b0;
end
else begin
ToMEM_Inst <= FromEX_Inst;
ToMEM_NewPC <= FromEX_NewPC;
ToMEM_RegDataA <= FromEX_RegDataA;
ToMEM_RegDataB <= FromEX_RegDataB;
ToMEM_Imm <= FromEX_Imm;
ToMEM_ALUOutput <= FromEX_ALUOutput;
ToMEM_Condition <= FromEX_Condition;
ToMEM_InstNum <= FromEX_InstNum;
ToMEM_InstType <= FromEX_InstType;
end
end
endmodule | 5 |
141,823 | data/full_repos/permissive/9603186/src/PipelineReg_IFID.v | 9,603,186 | PipelineReg_IFID.v | v | 52 | 83 | [] | [] | [] | [(21, 51)] | null | data/verilator_xmls/bb91dce3-f5da-48de-ba23-cff0ab2cb658.xml | null | 312,588 | module | module PipelineReg_IFID(
input wire clock,
input wire reset,
input wire [31:0] FromIF_Inst,
input wire [31:0] FromIF_NewPC,
input wire [3:0] FromIF_InstNum,
input wire [3:0] FromIF_InstType,
output reg [31:0] ToID_Inst,
output reg [31:0] ToID_NewPC,
output reg [3:0] ToID_InstNum,
output reg [3:0] ToID_InstType
);
always @ (posedge clock or posedge reset) begin
if (reset == 1) begin
ToID_Inst <= 32'b0;
ToID_NewPC <= 32'b0;
ToID_InstNum <= 4'b0;
ToID_InstType <= 4'b0;
end
else begin
ToID_Inst <= FromIF_Inst;
ToID_NewPC <= FromIF_NewPC;
ToID_InstNum <= FromIF_InstNum;
ToID_InstType <= FromIF_InstType;
end
end
endmodule | module PipelineReg_IFID(
input wire clock,
input wire reset,
input wire [31:0] FromIF_Inst,
input wire [31:0] FromIF_NewPC,
input wire [3:0] FromIF_InstNum,
input wire [3:0] FromIF_InstType,
output reg [31:0] ToID_Inst,
output reg [31:0] ToID_NewPC,
output reg [3:0] ToID_InstNum,
output reg [3:0] ToID_InstType
); |
always @ (posedge clock or posedge reset) begin
if (reset == 1) begin
ToID_Inst <= 32'b0;
ToID_NewPC <= 32'b0;
ToID_InstNum <= 4'b0;
ToID_InstType <= 4'b0;
end
else begin
ToID_Inst <= FromIF_Inst;
ToID_NewPC <= FromIF_NewPC;
ToID_InstNum <= FromIF_InstNum;
ToID_InstType <= FromIF_InstType;
end
end
endmodule | 5 |
141,826 | data/full_repos/permissive/9603186/src/Registers.v | 9,603,186 | Registers.v | v | 69 | 83 | [] | [] | [] | [(21, 68)] | null | data/verilator_xmls/d5853c61-145b-430e-b8de-91d933d58fe0.xml | null | 312,591 | module | module Registers(
input wire clock,
input wire reset,
input wire [4:0] rs,
input wire [4:0] rt,
input wire [4:0] rd,
input wire [31:0] din,
input wire we,
output reg [31:0] douts,
output reg [31:0] doutt,
input wire [4:0] rdisp,
output reg [31:0] ddisp
);
reg [31:0] register[1:31];
integer i;
initial begin
for (i=1; i<32; i=i+1)
register[i] <= 32'b0;
end
always @ (negedge clock or posedge reset) begin
if (reset) begin
for (i=1; i<32; i=i+1)
register[i] <= 32'b0;
end
else if ((rd != 0) && (we == 1))
register[rd] <= din;
end
always @ (clock) begin
if (clock == 0) begin
douts = (rs == 0) ? 32'b0: register[rs];
doutt = (rt == 0) ? 32'b0: register[rt];
end
end
always @ (clock or rdisp) begin
ddisp <= (rdisp == 0) ? 32'b0: register[rdisp];
end
endmodule | module Registers(
input wire clock,
input wire reset,
input wire [4:0] rs,
input wire [4:0] rt,
input wire [4:0] rd,
input wire [31:0] din,
input wire we,
output reg [31:0] douts,
output reg [31:0] doutt,
input wire [4:0] rdisp,
output reg [31:0] ddisp
); |
reg [31:0] register[1:31];
integer i;
initial begin
for (i=1; i<32; i=i+1)
register[i] <= 32'b0;
end
always @ (negedge clock or posedge reset) begin
if (reset) begin
for (i=1; i<32; i=i+1)
register[i] <= 32'b0;
end
else if ((rd != 0) && (we == 1))
register[rd] <= din;
end
always @ (clock) begin
if (clock == 0) begin
douts = (rs == 0) ? 32'b0: register[rs];
doutt = (rt == 0) ? 32'b0: register[rt];
end
end
always @ (clock or rdisp) begin
ddisp <= (rdisp == 0) ? 32'b0: register[rdisp];
end
endmodule | 5 |
141,829 | data/full_repos/permissive/9603186/src/Stage_IF.v | 9,603,186 | Stage_IF.v | v | 64 | 83 | [] | [] | [] | [(146, 184)] | null | null | 1: b'%Error: data/full_repos/permissive/9603186/src/Stage_IF.v:22: Cannot find include file: includes/MIPS32_Instruction_Set.vh\n`include "includes/MIPS32_Instruction_Set.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/includes/MIPS32_Instruction_Set.vh\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/includes/MIPS32_Instruction_Set.vh.v\n data/full_repos/permissive/9603186/src,data/full_repos/permissive/9603186/includes/MIPS32_Instruction_Set.vh.sv\n includes/MIPS32_Instruction_Set.vh\n includes/MIPS32_Instruction_Set.vh.v\n includes/MIPS32_Instruction_Set.vh.sv\n obj_dir/includes/MIPS32_Instruction_Set.vh\n obj_dir/includes/MIPS32_Instruction_Set.vh.v\n obj_dir/includes/MIPS32_Instruction_Set.vh.sv\n%Error: data/full_repos/permissive/9603186/src/Stage_IF.v:23: Cannot find include file: includes/DisplayData.vh\n`include "includes/DisplayData.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/Stage_IF.v:56: Define or directive not defined: \'`INST_TYPE_NONE\'\n assign EndStageIF_InstType = `INST_TYPE_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9603186/src/Stage_IF.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n assign EndStageIF_InstType = `INST_TYPE_NONE;\n ^\n%Error: Exiting due to 4 error(s)\n' | 312,594 | module | module Stage_IF(
input wire clock,
input wire reset,
input wire [31:0] FromMEM_NewPC,
input wire Stall,
output wire [31:0] EndStageIF_NewPC,
output wire [31:0] EndStageIF_Inst,
output reg [3:0] EndStageIF_InstNum,
output wire [3:0] EndStageIF_InstType
);
reg [31:0] NowPC;
always @ (posedge clock) begin
if (reset || Stall) begin
if (reset) begin
NowPC[31:0] <= 32'b0;
end
EndStageIF_InstNum <= 4'b0000;
EndStageIF_InstType <= 4'b0000;
end
else begin
if (!Stall) begin
NowPC[31:0] = FromMEM_NewPC[31:0];
end
end
end
assign EndStageIF_NewPC = NowPC + 1;
assign EndStageIF_InstType = `INST_TYPE_NONE;
always @ (posedge clock) begin
EndStageIF_InstNum = EndStageIF_InstNum + 1;
end
endmodule | module Stage_IF(
input wire clock,
input wire reset,
input wire [31:0] FromMEM_NewPC,
input wire Stall,
output wire [31:0] EndStageIF_NewPC,
output wire [31:0] EndStageIF_Inst,
output reg [3:0] EndStageIF_InstNum,
output wire [3:0] EndStageIF_InstType
); |
reg [31:0] NowPC;
always @ (posedge clock) begin
if (reset || Stall) begin
if (reset) begin
NowPC[31:0] <= 32'b0;
end
EndStageIF_InstNum <= 4'b0000;
EndStageIF_InstType <= 4'b0000;
end
else begin
if (!Stall) begin
NowPC[31:0] = FromMEM_NewPC[31:0];
end
end
end
assign EndStageIF_NewPC = NowPC + 1;
assign EndStageIF_InstType = `INST_TYPE_NONE;
always @ (posedge clock) begin
EndStageIF_InstNum = EndStageIF_InstNum + 1;
end
endmodule | 5 |
141,833 | data/full_repos/permissive/96032875/crp16_components/crp16_alu/crp16_alu.v | 96,032,875 | crp16_alu.v | v | 90 | 80 | [] | [] | [] | [(7, 87)] | null | data/verilator_xmls/9a767d05-eab4-42e6-b5e8-aac1d8370730.xml | null | 312,598 | module | module crp16_alu (
input [15:0] op_a,
input [15:0] op_b,
input [2:0] op_sel,
output reg [15:0] alu_out,
output reg v,
output reg c,
output n,
output z
);
assign n = alu_out[15];
assign z = ~(|alu_out);
always @(*)
begin
case (op_sel[2:0])
3'b000:
begin
{c, alu_out} = {1'b0, op_a} + {1'b0, op_b};
v = (~(op_a[15] ^ op_b[15])) & (op_a[15] ^ alu_out[15]);
end
3'b001:
begin
{c, alu_out} = {1'b0, op_a} + {1'b0, ~op_b} + 17'b1;
v = (op_a[15] ^ op_b[15]) & (~(op_b[15] ^ alu_out[15]));
end
3'b010:
begin
alu_out = op_a >> (16'b1111 & op_b);
c = 0;
v = 0;
end
3'b011:
begin
alu_out = $signed(op_a) >>> (16'b1111 & op_b);
c = 0;
v = 0;
end
3'b100:
begin
alu_out = op_a << (16'b1111 & op_b);
c = 0;
v = 0;
end
3'b101:
begin
alu_out = op_a & op_b;
c = 0;
v = 0;
end
3'b110:
begin
alu_out = op_a | op_b;
c = 0;
v = 0;
end
3'b111:
begin
alu_out = op_a ^ op_b;
c = 0;
v = 0;
end
endcase
end
endmodule | module crp16_alu (
input [15:0] op_a,
input [15:0] op_b,
input [2:0] op_sel,
output reg [15:0] alu_out,
output reg v,
output reg c,
output n,
output z
); |
assign n = alu_out[15];
assign z = ~(|alu_out);
always @(*)
begin
case (op_sel[2:0])
3'b000:
begin
{c, alu_out} = {1'b0, op_a} + {1'b0, op_b};
v = (~(op_a[15] ^ op_b[15])) & (op_a[15] ^ alu_out[15]);
end
3'b001:
begin
{c, alu_out} = {1'b0, op_a} + {1'b0, ~op_b} + 17'b1;
v = (op_a[15] ^ op_b[15]) & (~(op_b[15] ^ alu_out[15]));
end
3'b010:
begin
alu_out = op_a >> (16'b1111 & op_b);
c = 0;
v = 0;
end
3'b011:
begin
alu_out = $signed(op_a) >>> (16'b1111 & op_b);
c = 0;
v = 0;
end
3'b100:
begin
alu_out = op_a << (16'b1111 & op_b);
c = 0;
v = 0;
end
3'b101:
begin
alu_out = op_a & op_b;
c = 0;
v = 0;
end
3'b110:
begin
alu_out = op_a | op_b;
c = 0;
v = 0;
end
3'b111:
begin
alu_out = op_a ^ op_b;
c = 0;
v = 0;
end
endcase
end
endmodule | 0 |
141,834 | data/full_repos/permissive/96032875/crp16_components/crp16_datapath/crp16_datapath.v | 96,032,875 | crp16_datapath.v | v | 273 | 82 | [] | [] | [] | [(28, 108), (117, 161), (174, 189), (191, 434)] | null | null | 1: b'%Error: data/full_repos/permissive/96032875/crp16_components/crp16_datapath/crp16_datapath.v:22: Cannot find include file: ../crp16_alu/crp16_alu.v\n`include "../crp16_alu/crp16_alu.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96032875/crp16_components/crp16_datapath,data/full_repos/permissive/96032875/../crp16_alu/crp16_alu.v\n data/full_repos/permissive/96032875/crp16_components/crp16_datapath,data/full_repos/permissive/96032875/../crp16_alu/crp16_alu.v.v\n data/full_repos/permissive/96032875/crp16_components/crp16_datapath,data/full_repos/permissive/96032875/../crp16_alu/crp16_alu.v.sv\n ../crp16_alu/crp16_alu.v\n ../crp16_alu/crp16_alu.v.v\n ../crp16_alu/crp16_alu.v.sv\n obj_dir/../crp16_alu/crp16_alu.v\n obj_dir/../crp16_alu/crp16_alu.v.v\n obj_dir/../crp16_alu/crp16_alu.v.sv\n%Error: data/full_repos/permissive/96032875/crp16_components/crp16_datapath/crp16_datapath.v:23: Cannot find include file: ../crp16_register_file/crp16_register_file.v\n`include "../crp16_register_file/crp16_register_file.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96032875/crp16_components/crp16_datapath/crp16_datapath.v:24: Cannot find include file: ../../crp16_subcomponents/register/register.v\n`include "../../crp16_subcomponents/register/register.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 312,599 | module | module crp16_datapath (
input clock,
input reset,
output [15:0] address_a,
output [15:0] address_b,
output [15:0] data_a,
output [15:0] data_b,
output wren_a,
output wren_b,
input [15:0] q_a,
input [15:0] q_b,
output mem_clock,
input [2:0] reg_sel,
output [15:0] reg_view,
output [15:0] instr_view,
output [15:0] pc_view,
output [15:0] counter
);
`define ALU_I(instr) (instr[1:0] == 2'b11)
`define CALL_I(instr) (instr[3:0] == 4'b1010)
`define JUMPC_I(instr) (instr[2:0] == 3'b110)
`define JUMPUC_I(instr) (instr[3:0] == 4'b0010)
`define BRANCH_I(instr) (`CALL_I(instr) | `JUMPC_I(instr) | \
`JUMPUC_I(instr))
`define GT_I(instr) (instr[3:0] == 4'b1100)
`define LT_I(instr) (instr[3:0] == 4'b0100)
`define CMP_I(instr) (`GT_I(instr) | `LT_I(instr))
`define LOAD_I(instr) (instr[5:0] == 6'b000001)
`define LOADHI_I(instr) (instr[4:0] == 5'b10001)
`define LOADIMM_I(instr) (instr[3:0] == 4'b1001)
`define STORE_I(instr) (instr[5:0] == 6'b100001)
`define STOP_I(instr) (instr[15:0] == 16'h8000)
`define ALUOP(instr) (instr[4:2])
`define BRANCHCOND(instr) (instr[3])
`define BRANCHREG(instr) (~instr[4])
`define BYTEWORD(instr) (instr[6])
`define IMM(instr) (instr[5])
`define LINK(instr) (instr[3])
`define LOADSIGNED(instr) (instr[7])
`define REGA(instr) (instr[12:10])
`define REGB(instr) (instr[9:7])
`define REGD(instr) (instr[15:13])
`define SIGNED(instr) (instr[4])
`define HI8(instr) ({instr[12:5], 8'b0})
`define SE4(instr) ({{12{instr[9]}}, instr[9:6]})
`define SE8(instr) ({{8{instr[12]}}, instr[12:5]})
`define SE11(instr) ({{5{instr[15]}}, instr[15:5]})
`define ZE4(instr) ({12'b0, instr[9:6]})
`define ZE8(instr) ({8'b0, instr[12:5]})
localparam LINK_REG = 3'b111;
wire stop;
wire [15:0] if_pc;
wire [15:0] if_branch_addr, if_mem_addr, if_next_addr;
wire if_pc_src;
register #(16) if_pc_r(if_next_addr, if_pc, ~stop, clock, reset);
wire [15:0] dc_instr, dc_pc;
wire [2:0] dc_rf_a_sel, dc_rf_b_sel;
wire [15:0] dc_rf_a_out, dc_rf_b_out;
wire [15:0] dc_reg_a_fwd, dc_reg_b_fwd, dc_imm;
wire [15:0] dc_em_alu_a_in, dc_em_alu_b_in;
wire dc_em_mem_wren;
register #(16) dc_pc_r(if_next_addr, dc_pc, ~stop, clock, reset);
wire [15:0] em_instr, em_pc;
wire [15:0] dc_em_alu_a, dc_em_alu_b, dc_em_mem_addr, dc_em_mem_data;
wire [15:0] em_alu_out, em_cmp_out;
wire [2:0] em_alu_op;
wire v, c, n, z;
wire [15:0] dc_em_mem_q;
wire [15:0] em_reg_d_data;
wire [2:0] em_reg_d_sel;
wire em_reg_wren;
register #(16) em_instr_r(dc_instr, em_instr, ~stop, clock, reset);
register #(16) em_pc_r(dc_pc, em_pc, ~stop, clock, reset);
register #(16) dc_em_alu_a_r(dc_em_alu_a_in, dc_em_alu_a, ~stop,
clock, reset);
register #(16) dc_em_alu_b_r(dc_em_alu_b_in, dc_em_alu_b, ~stop,
clock, reset);
assign stop = `STOP_I(em_instr);
assign instr_view = em_instr;
assign pc_view = em_pc - 16'd1;
register #(16) counter_r(counter + 16'd1, counter, ~stop, clock, reset);
crp16_alu alu (
.op_a(dc_em_alu_a), .op_b(dc_em_alu_b),
.op_sel(em_alu_op), .alu_out(em_alu_out),
.v(v), .c(c), .n(n), .z(z)
);
crp16_register_file register_file (
.clock(clock), .reset(reset),
.a_sel(dc_rf_a_sel), .a_val(dc_rf_a_out),
.b_sel(dc_rf_b_sel), .b_val(dc_rf_b_out),
.c_sel(reg_sel), .c_val(reg_view),
.write_sel(em_reg_d_sel), .write_val(em_reg_d_data),
.write(em_reg_wren)
);
assign mem_clock = clock;
assign address_a = if_mem_addr;
assign address_b = dc_reg_a_fwd;
assign data_b = dc_reg_b_fwd;
assign wren_b = dc_em_mem_wren;
assign dc_instr = q_a;
assign dc_em_mem_q = q_b;
assign if_next_addr = if_mem_addr + 16'd1;
assign if_mem_addr = if_pc_src ? if_branch_addr : if_pc;
assign dc_imm = `LOADIMM_I(dc_instr) ?
(`SIGNED(dc_instr) ? `SE8(dc_instr) : `ZE8(dc_instr)) :
`ALU_I(dc_instr) | `CMP_I(dc_instr) ?
(`SIGNED(dc_instr) ? `SE4(dc_instr) : `ZE4(dc_instr)) :
16'h0;
assign dc_rf_a_sel = `REGA(dc_instr);
assign dc_rf_b_sel = `JUMPC_I(dc_instr) | `LOADHI_I(dc_instr) |
`STORE_I(dc_instr) ?
`REGD(dc_instr) : `REGB(dc_instr);
assign dc_reg_a_fwd = em_reg_wren & (em_reg_d_sel == dc_rf_a_sel) ?
em_reg_d_data : dc_rf_a_out;
assign dc_reg_b_fwd = em_reg_wren & (em_reg_d_sel == dc_rf_b_sel) ?
em_reg_d_data : dc_rf_b_out;
assign dc_em_alu_a_in = `LOADHI_I(dc_instr) ? `HI8(dc_instr) :
`LOADIMM_I(dc_instr) ? 16'b0 :
dc_reg_a_fwd;
assign dc_em_alu_b_in = `LOADHI_I(dc_instr) ? dc_reg_b_fwd[7:0] :
`LOADIMM_I(dc_instr) | `IMM(dc_instr) ? dc_imm :
dc_reg_b_fwd;
assign dc_em_mem_wren = ~stop & `STORE_I(dc_instr);
assign if_branch_addr = ~`BRANCH_I(dc_instr) ? 16'hdead :
`BRANCHREG(dc_instr) ? dc_reg_a_fwd :
`JUMPC_I(dc_instr) ? dc_pc + `SE8(dc_instr) :
dc_pc + `SE11(dc_instr);
assign if_pc_src = `CALL_I(dc_instr) | `JUMPUC_I(dc_instr) |
(`JUMPC_I(dc_instr) &
(`BRANCHCOND(dc_instr) == (|dc_reg_b_fwd)));
assign em_alu_op = `ALU_I(em_instr) ? `ALUOP(em_instr) :
`CMP_I(em_instr) ? 3'b001 :
3'b000;
assign em_cmp_out = {15'b0,
(`GT_I(em_instr) ?
(`SIGNED(em_instr) ? (n == v) & (~z) : c & (~z)) :
`LT_I(em_instr) ?
(`SIGNED(em_instr) ? (n ^ v) : ~c) :
1'b0)};
assign em_reg_d_sel = `CALL_I(em_instr) ? LINK_REG : `REGD(em_instr);
assign em_reg_d_data = `CALL_I(em_instr) ? em_pc :
`LOAD_I(em_instr) ? dc_em_mem_q :
`CMP_I(em_instr) ? em_cmp_out :
(`ALU_I(em_instr) | `LOADIMM_I(em_instr) |
`LOADHI_I(em_instr)) ? em_alu_out :
16'hdead;
assign em_reg_wren = ~stop &
(`ALU_I(em_instr) | `LOADIMM_I(em_instr) |
`LOAD_I(em_instr) | `LOADHI_I(em_instr) |
`CALL_I(em_instr) | `CMP_I(em_instr));
endmodule | module crp16_datapath (
input clock,
input reset,
output [15:0] address_a,
output [15:0] address_b,
output [15:0] data_a,
output [15:0] data_b,
output wren_a,
output wren_b,
input [15:0] q_a,
input [15:0] q_b,
output mem_clock,
input [2:0] reg_sel,
output [15:0] reg_view,
output [15:0] instr_view,
output [15:0] pc_view,
output [15:0] counter
); |
`define ALU_I(instr) (instr[1:0] == 2'b11)
`define CALL_I(instr) (instr[3:0] == 4'b1010)
`define JUMPC_I(instr) (instr[2:0] == 3'b110)
`define JUMPUC_I(instr) (instr[3:0] == 4'b0010)
`define BRANCH_I(instr) (`CALL_I(instr) | `JUMPC_I(instr) | \
`JUMPUC_I(instr))
`define GT_I(instr) (instr[3:0] == 4'b1100)
`define LT_I(instr) (instr[3:0] == 4'b0100)
`define CMP_I(instr) (`GT_I(instr) | `LT_I(instr))
`define LOAD_I(instr) (instr[5:0] == 6'b000001)
`define LOADHI_I(instr) (instr[4:0] == 5'b10001)
`define LOADIMM_I(instr) (instr[3:0] == 4'b1001)
`define STORE_I(instr) (instr[5:0] == 6'b100001)
`define STOP_I(instr) (instr[15:0] == 16'h8000)
`define ALUOP(instr) (instr[4:2])
`define BRANCHCOND(instr) (instr[3])
`define BRANCHREG(instr) (~instr[4])
`define BYTEWORD(instr) (instr[6])
`define IMM(instr) (instr[5])
`define LINK(instr) (instr[3])
`define LOADSIGNED(instr) (instr[7])
`define REGA(instr) (instr[12:10])
`define REGB(instr) (instr[9:7])
`define REGD(instr) (instr[15:13])
`define SIGNED(instr) (instr[4])
`define HI8(instr) ({instr[12:5], 8'b0})
`define SE4(instr) ({{12{instr[9]}}, instr[9:6]})
`define SE8(instr) ({{8{instr[12]}}, instr[12:5]})
`define SE11(instr) ({{5{instr[15]}}, instr[15:5]})
`define ZE4(instr) ({12'b0, instr[9:6]})
`define ZE8(instr) ({8'b0, instr[12:5]})
localparam LINK_REG = 3'b111;
wire stop;
wire [15:0] if_pc;
wire [15:0] if_branch_addr, if_mem_addr, if_next_addr;
wire if_pc_src;
register #(16) if_pc_r(if_next_addr, if_pc, ~stop, clock, reset);
wire [15:0] dc_instr, dc_pc;
wire [2:0] dc_rf_a_sel, dc_rf_b_sel;
wire [15:0] dc_rf_a_out, dc_rf_b_out;
wire [15:0] dc_reg_a_fwd, dc_reg_b_fwd, dc_imm;
wire [15:0] dc_em_alu_a_in, dc_em_alu_b_in;
wire dc_em_mem_wren;
register #(16) dc_pc_r(if_next_addr, dc_pc, ~stop, clock, reset);
wire [15:0] em_instr, em_pc;
wire [15:0] dc_em_alu_a, dc_em_alu_b, dc_em_mem_addr, dc_em_mem_data;
wire [15:0] em_alu_out, em_cmp_out;
wire [2:0] em_alu_op;
wire v, c, n, z;
wire [15:0] dc_em_mem_q;
wire [15:0] em_reg_d_data;
wire [2:0] em_reg_d_sel;
wire em_reg_wren;
register #(16) em_instr_r(dc_instr, em_instr, ~stop, clock, reset);
register #(16) em_pc_r(dc_pc, em_pc, ~stop, clock, reset);
register #(16) dc_em_alu_a_r(dc_em_alu_a_in, dc_em_alu_a, ~stop,
clock, reset);
register #(16) dc_em_alu_b_r(dc_em_alu_b_in, dc_em_alu_b, ~stop,
clock, reset);
assign stop = `STOP_I(em_instr);
assign instr_view = em_instr;
assign pc_view = em_pc - 16'd1;
register #(16) counter_r(counter + 16'd1, counter, ~stop, clock, reset);
crp16_alu alu (
.op_a(dc_em_alu_a), .op_b(dc_em_alu_b),
.op_sel(em_alu_op), .alu_out(em_alu_out),
.v(v), .c(c), .n(n), .z(z)
);
crp16_register_file register_file (
.clock(clock), .reset(reset),
.a_sel(dc_rf_a_sel), .a_val(dc_rf_a_out),
.b_sel(dc_rf_b_sel), .b_val(dc_rf_b_out),
.c_sel(reg_sel), .c_val(reg_view),
.write_sel(em_reg_d_sel), .write_val(em_reg_d_data),
.write(em_reg_wren)
);
assign mem_clock = clock;
assign address_a = if_mem_addr;
assign address_b = dc_reg_a_fwd;
assign data_b = dc_reg_b_fwd;
assign wren_b = dc_em_mem_wren;
assign dc_instr = q_a;
assign dc_em_mem_q = q_b;
assign if_next_addr = if_mem_addr + 16'd1;
assign if_mem_addr = if_pc_src ? if_branch_addr : if_pc;
assign dc_imm = `LOADIMM_I(dc_instr) ?
(`SIGNED(dc_instr) ? `SE8(dc_instr) : `ZE8(dc_instr)) :
`ALU_I(dc_instr) | `CMP_I(dc_instr) ?
(`SIGNED(dc_instr) ? `SE4(dc_instr) : `ZE4(dc_instr)) :
16'h0;
assign dc_rf_a_sel = `REGA(dc_instr);
assign dc_rf_b_sel = `JUMPC_I(dc_instr) | `LOADHI_I(dc_instr) |
`STORE_I(dc_instr) ?
`REGD(dc_instr) : `REGB(dc_instr);
assign dc_reg_a_fwd = em_reg_wren & (em_reg_d_sel == dc_rf_a_sel) ?
em_reg_d_data : dc_rf_a_out;
assign dc_reg_b_fwd = em_reg_wren & (em_reg_d_sel == dc_rf_b_sel) ?
em_reg_d_data : dc_rf_b_out;
assign dc_em_alu_a_in = `LOADHI_I(dc_instr) ? `HI8(dc_instr) :
`LOADIMM_I(dc_instr) ? 16'b0 :
dc_reg_a_fwd;
assign dc_em_alu_b_in = `LOADHI_I(dc_instr) ? dc_reg_b_fwd[7:0] :
`LOADIMM_I(dc_instr) | `IMM(dc_instr) ? dc_imm :
dc_reg_b_fwd;
assign dc_em_mem_wren = ~stop & `STORE_I(dc_instr);
assign if_branch_addr = ~`BRANCH_I(dc_instr) ? 16'hdead :
`BRANCHREG(dc_instr) ? dc_reg_a_fwd :
`JUMPC_I(dc_instr) ? dc_pc + `SE8(dc_instr) :
dc_pc + `SE11(dc_instr);
assign if_pc_src = `CALL_I(dc_instr) | `JUMPUC_I(dc_instr) |
(`JUMPC_I(dc_instr) &
(`BRANCHCOND(dc_instr) == (|dc_reg_b_fwd)));
assign em_alu_op = `ALU_I(em_instr) ? `ALUOP(em_instr) :
`CMP_I(em_instr) ? 3'b001 :
3'b000;
assign em_cmp_out = {15'b0,
(`GT_I(em_instr) ?
(`SIGNED(em_instr) ? (n == v) & (~z) : c & (~z)) :
`LT_I(em_instr) ?
(`SIGNED(em_instr) ? (n ^ v) : ~c) :
1'b0)};
assign em_reg_d_sel = `CALL_I(em_instr) ? LINK_REG : `REGD(em_instr);
assign em_reg_d_data = `CALL_I(em_instr) ? em_pc :
`LOAD_I(em_instr) ? dc_em_mem_q :
`CMP_I(em_instr) ? em_cmp_out :
(`ALU_I(em_instr) | `LOADIMM_I(em_instr) |
`LOADHI_I(em_instr)) ? em_alu_out :
16'hdead;
assign em_reg_wren = ~stop &
(`ALU_I(em_instr) | `LOADIMM_I(em_instr) |
`LOAD_I(em_instr) | `LOADHI_I(em_instr) |
`CALL_I(em_instr) | `CMP_I(em_instr));
endmodule | 0 |
141,835 | data/full_repos/permissive/96032875/crp16_components/crp16_processor/crp16_processor.v | 96,032,875 | crp16_processor.v | v | 106 | 81 | [] | [] | [] | [(40, 120), (129, 173), (186, 201), (203, 446), (452, 470), (472, 527), (533, 558)] | null | null | 1: b'%Error: data/full_repos/permissive/96032875/crp16_components/crp16_processor/crp16_processor.v:13: Cannot find include file: ../crp16_datapath/crp16_datapath.v\n`include "../crp16_datapath/crp16_datapath.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96032875/crp16_components/crp16_processor,data/full_repos/permissive/96032875/../crp16_datapath/crp16_datapath.v\n data/full_repos/permissive/96032875/crp16_components/crp16_processor,data/full_repos/permissive/96032875/../crp16_datapath/crp16_datapath.v.v\n data/full_repos/permissive/96032875/crp16_components/crp16_processor,data/full_repos/permissive/96032875/../crp16_datapath/crp16_datapath.v.sv\n ../crp16_datapath/crp16_datapath.v\n ../crp16_datapath/crp16_datapath.v.v\n ../crp16_datapath/crp16_datapath.v.sv\n obj_dir/../crp16_datapath/crp16_datapath.v\n obj_dir/../crp16_datapath/crp16_datapath.v.v\n obj_dir/../crp16_datapath/crp16_datapath.v.sv\n%Error: data/full_repos/permissive/96032875/crp16_components/crp16_processor/crp16_processor.v:14: Cannot find include file: ../../crp16_subcomponents/hex_decoder/hex_decoder.v\n`include "../../crp16_subcomponents/hex_decoder/hex_decoder.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 312,600 | module | module crp16_processor (
input [3:0] KEY,
input [9:0] SW,
input CLOCK_50,
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5
);
wire [15:0] address_a, address_b, data_a, data_b, q_a, q_b;
wire wren_a, wren_b, mem_clock, clock, reset;
wire [15:0] hex_in, counter, reg_view, instr_view, pc_view;
clock_controller clock_ctrl(CLOCK_50, KEY[2], clock, SW[9:5]);
assign reset = ~KEY[1];
dual_mem memory (
.clock(clock),
.address_a(address_a), .address_b(address_b),
.data_a(data_a), .data_b(data_b),
.wren_a(wren_a), .wren_b(wren_b),
.q_a(q_a), .q_b(q_b)
);
crp16_datapath datapath (
.clock(clock), .reset(reset),
.address_a(address_a), .address_b(address_b),
.data_a(data_a), .data_b(data_b),
.wren_a(wren_a), .wren_b(wren_b),
.q_a(q_a), .q_b(q_b),
.mem_clock(mem_clock),
.reg_sel(SW[2:0]), .reg_view(reg_view),
.instr_view(instr_view), .pc_view(pc_view),
.counter(counter)
);
hex_decoder addrlo(pc_view[3:0], HEX4);
hex_decoder addrhi(pc_view[7:4], HEX5);
hex_decoder h0(hex_in[3:0], HEX0);
hex_decoder h1(hex_in[7:4], HEX1);
hex_decoder h2(hex_in[11:8], HEX2);
hex_decoder h3(hex_in[15:12], HEX3);
assign hex_in = SW[4] ? counter :
SW[3] ? reg_view :
instr_view;
endmodule | module crp16_processor (
input [3:0] KEY,
input [9:0] SW,
input CLOCK_50,
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5
); |
wire [15:0] address_a, address_b, data_a, data_b, q_a, q_b;
wire wren_a, wren_b, mem_clock, clock, reset;
wire [15:0] hex_in, counter, reg_view, instr_view, pc_view;
clock_controller clock_ctrl(CLOCK_50, KEY[2], clock, SW[9:5]);
assign reset = ~KEY[1];
dual_mem memory (
.clock(clock),
.address_a(address_a), .address_b(address_b),
.data_a(data_a), .data_b(data_b),
.wren_a(wren_a), .wren_b(wren_b),
.q_a(q_a), .q_b(q_b)
);
crp16_datapath datapath (
.clock(clock), .reset(reset),
.address_a(address_a), .address_b(address_b),
.data_a(data_a), .data_b(data_b),
.wren_a(wren_a), .wren_b(wren_b),
.q_a(q_a), .q_b(q_b),
.mem_clock(mem_clock),
.reg_sel(SW[2:0]), .reg_view(reg_view),
.instr_view(instr_view), .pc_view(pc_view),
.counter(counter)
);
hex_decoder addrlo(pc_view[3:0], HEX4);
hex_decoder addrhi(pc_view[7:4], HEX5);
hex_decoder h0(hex_in[3:0], HEX0);
hex_decoder h1(hex_in[7:4], HEX1);
hex_decoder h2(hex_in[11:8], HEX2);
hex_decoder h3(hex_in[15:12], HEX3);
assign hex_in = SW[4] ? counter :
SW[3] ? reg_view :
instr_view;
endmodule | 0 |
141,836 | data/full_repos/permissive/96032875/crp16_components/crp16_processor/crp16_processor.v | 96,032,875 | crp16_processor.v | v | 106 | 81 | [] | [] | [] | [(40, 120), (129, 173), (186, 201), (203, 446), (452, 470), (472, 527), (533, 558)] | null | null | 1: b'%Error: data/full_repos/permissive/96032875/crp16_components/crp16_processor/crp16_processor.v:13: Cannot find include file: ../crp16_datapath/crp16_datapath.v\n`include "../crp16_datapath/crp16_datapath.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96032875/crp16_components/crp16_processor,data/full_repos/permissive/96032875/../crp16_datapath/crp16_datapath.v\n data/full_repos/permissive/96032875/crp16_components/crp16_processor,data/full_repos/permissive/96032875/../crp16_datapath/crp16_datapath.v.v\n data/full_repos/permissive/96032875/crp16_components/crp16_processor,data/full_repos/permissive/96032875/../crp16_datapath/crp16_datapath.v.sv\n ../crp16_datapath/crp16_datapath.v\n ../crp16_datapath/crp16_datapath.v.v\n ../crp16_datapath/crp16_datapath.v.sv\n obj_dir/../crp16_datapath/crp16_datapath.v\n obj_dir/../crp16_datapath/crp16_datapath.v.v\n obj_dir/../crp16_datapath/crp16_datapath.v.sv\n%Error: data/full_repos/permissive/96032875/crp16_components/crp16_processor/crp16_processor.v:14: Cannot find include file: ../../crp16_subcomponents/hex_decoder/hex_decoder.v\n`include "../../crp16_subcomponents/hex_decoder/hex_decoder.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 312,600 | module | module clock_controller (
input clock_in,
input clock_toggle,
output clock_out,
input [4:0] scale
);
reg clock_run = 0;
reg [4:0] clock_scaler = 0;
reg [30:0] clock_counter = 0;
wire [31:0] clock_src = {clock_counter, clock_in};
assign clock_out = clock_src[clock_scaler] & clock_run;
always @(posedge clock_in)
begin
clock_counter <= clock_counter + 31'b1;
end
always @(posedge clock_toggle)
begin
clock_scaler <= scale;
clock_run <= clock_run ^ 1'b1;
end
endmodule | module clock_controller (
input clock_in,
input clock_toggle,
output clock_out,
input [4:0] scale
); |
reg clock_run = 0;
reg [4:0] clock_scaler = 0;
reg [30:0] clock_counter = 0;
wire [31:0] clock_src = {clock_counter, clock_in};
assign clock_out = clock_src[clock_scaler] & clock_run;
always @(posedge clock_in)
begin
clock_counter <= clock_counter + 31'b1;
end
always @(posedge clock_toggle)
begin
clock_scaler <= scale;
clock_run <= clock_run ^ 1'b1;
end
endmodule | 0 |
141,837 | data/full_repos/permissive/96032875/crp16_components/crp16_register_file/crp16_register_file.v | 96,032,875 | crp16_register_file.v | v | 54 | 59 | [] | [] | [] | [(7, 51)] | null | data/verilator_xmls/f988d2ec-ebce-4b7d-b734-dcbae656e02a.xml | null | 312,603 | module | module crp16_register_file (
input clock,
input reset,
input [2:0] a_sel,
input [2:0] b_sel,
input [2:0] c_sel,
input [2:0] d_sel,
output [15:0] a_val,
output [15:0] b_val,
output [15:0] c_val,
output [15:0] d_val,
input write,
input [2:0] write_sel,
input [15:0] write_val
);
reg [15:0] registers [0:7];
assign a_val = registers[a_sel];
assign b_val = registers[b_sel];
assign c_val = registers[c_sel];
assign d_val = registers[d_sel];
always @(posedge clock, posedge reset)
begin
if (reset)
begin
registers[0] <= 16'b0;
registers[1] <= 16'b0;
registers[2] <= 16'b0;
registers[3] <= 16'b0;
registers[4] <= 16'b0;
registers[5] <= 16'b0;
registers[6] <= 16'b0;
registers[7] <= 16'b0;
end
else if (write) registers[write_sel] <= write_val;
end
endmodule | module crp16_register_file (
input clock,
input reset,
input [2:0] a_sel,
input [2:0] b_sel,
input [2:0] c_sel,
input [2:0] d_sel,
output [15:0] a_val,
output [15:0] b_val,
output [15:0] c_val,
output [15:0] d_val,
input write,
input [2:0] write_sel,
input [15:0] write_val
); |
reg [15:0] registers [0:7];
assign a_val = registers[a_sel];
assign b_val = registers[b_sel];
assign c_val = registers[c_sel];
assign d_val = registers[d_sel];
always @(posedge clock, posedge reset)
begin
if (reset)
begin
registers[0] <= 16'b0;
registers[1] <= 16'b0;
registers[2] <= 16'b0;
registers[3] <= 16'b0;
registers[4] <= 16'b0;
registers[5] <= 16'b0;
registers[6] <= 16'b0;
registers[7] <= 16'b0;
end
else if (write) registers[write_sel] <= write_val;
end
endmodule | 0 |
141,838 | data/full_repos/permissive/96032875/crp16_subcomponents/hex_decoder/hex_decoder.v | 96,032,875 | hex_decoder.v | v | 21 | 95 | [] | [] | [] | [(3, 21)] | null | data/verilator_xmls/f0203aab-be42-41fe-834d-6d1dbb7a66ec.xml | null | 312,604 | module | module hex_decoder(SW, HEX0);
input [3:0] SW;
output [6:0] HEX0;
assign HEX0[0] = (~SW[2] | ~SW[1]) & (~SW[3] | SW[0]) & (~SW[3] | SW[2] | SW[1])
& (SW[2] | SW[0]) & (SW[3] | ~SW[2] | ~SW[0]) & (SW[3] | SW[2] | ~SW[1]);
assign HEX0[1] = (SW[3] | SW[2]) & (SW[2] | SW[0]) & (~SW[3] | SW[1] | ~SW[0])
& (SW[3] | SW[1] | SW[0]) & (SW[3] | ~SW[1] | ~SW[0]);
assign HEX0[2] = (SW[3] | ~SW[2]) & (~SW[3] | SW[2]) & (SW[2] | ~SW[0])
& (SW[3] | SW[1]) & (SW[1] | ~SW[0]);
assign HEX0[3] = (~SW[3] | SW[1]) & (SW[3] | SW[2] | SW[0]) & (SW[2] | ~SW[1] | ~SW[0])
& (~SW[2] | ~SW[1] | SW[0]) & (~SW[2] | SW[1] | ~SW[0]);
assign HEX0[4] = (~SW[3] | ~SW[2]) & (~SW[1] | SW[0]) & (SW[2] | SW[0])
& (~SW[3] | ~SW[1]);
assign HEX0[5] = (SW[1] | SW[0]) & (~SW[3] | SW[2]) & (~SW[2] | SW[0]) & (~SW[3] | ~SW[1])
& (SW[3] | ~SW[2] | SW[1]);
assign HEX0[6] = (~SW[3] | SW[2]) & (SW[2] | ~SW[1]) & (~SW[1] | SW[0])
& (~SW[3] | ~SW[0]) & (SW[3] | ~SW[2] | SW[1]);
endmodule | module hex_decoder(SW, HEX0); |
input [3:0] SW;
output [6:0] HEX0;
assign HEX0[0] = (~SW[2] | ~SW[1]) & (~SW[3] | SW[0]) & (~SW[3] | SW[2] | SW[1])
& (SW[2] | SW[0]) & (SW[3] | ~SW[2] | ~SW[0]) & (SW[3] | SW[2] | ~SW[1]);
assign HEX0[1] = (SW[3] | SW[2]) & (SW[2] | SW[0]) & (~SW[3] | SW[1] | ~SW[0])
& (SW[3] | SW[1] | SW[0]) & (SW[3] | ~SW[1] | ~SW[0]);
assign HEX0[2] = (SW[3] | ~SW[2]) & (~SW[3] | SW[2]) & (SW[2] | ~SW[0])
& (SW[3] | SW[1]) & (SW[1] | ~SW[0]);
assign HEX0[3] = (~SW[3] | SW[1]) & (SW[3] | SW[2] | SW[0]) & (SW[2] | ~SW[1] | ~SW[0])
& (~SW[2] | ~SW[1] | SW[0]) & (~SW[2] | SW[1] | ~SW[0]);
assign HEX0[4] = (~SW[3] | ~SW[2]) & (~SW[1] | SW[0]) & (SW[2] | SW[0])
& (~SW[3] | ~SW[1]);
assign HEX0[5] = (SW[1] | SW[0]) & (~SW[3] | SW[2]) & (~SW[2] | SW[0]) & (~SW[3] | ~SW[1])
& (SW[3] | ~SW[2] | SW[1]);
assign HEX0[6] = (~SW[3] | SW[2]) & (SW[2] | ~SW[1]) & (~SW[1] | SW[0])
& (~SW[3] | ~SW[0]) & (SW[3] | ~SW[2] | SW[1]);
endmodule | 0 |
141,839 | data/full_repos/permissive/96032875/crp16_subcomponents/register/register.v | 96,032,875 | register.v | v | 26 | 60 | [] | [] | [] | [(11, 26)] | null | data/verilator_xmls/5f25cb5c-204f-40cb-926b-43a9e5c805e6.xml | null | 312,605 | module | module register(data, q, wren, clock, reset);
parameter width = 1;
input [(width-1):0] data;
output [(width-1):0] q;
input wren, clock, reset;
reg [(width-1):0] data_reg = 0;
assign q = data_reg;
always @(posedge clock, posedge reset)
begin
if (reset) data_reg <= 0;
else if (wren) data_reg <= data;
end
endmodule | module register(data, q, wren, clock, reset); |
parameter width = 1;
input [(width-1):0] data;
output [(width-1):0] q;
input wren, clock, reset;
reg [(width-1):0] data_reg = 0;
assign q = data_reg;
always @(posedge clock, posedge reset)
begin
if (reset) data_reg <= 0;
else if (wren) data_reg <= data;
end
endmodule | 0 |
141,844 | data/full_repos/permissive/96068636/AES_rounds.v | 96,068,636 | AES_rounds.v | v | 311 | 138 | [] | [] | [] | null | line:44: before: "(" | null | 1: b"%Error: data/full_repos/permissive/96068636/AES_rounds.v:285: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.v\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.sv\n AES_sbox\n AES_sbox.v\n AES_sbox.sv\n obj_dir/AES_sbox\n obj_dir/AES_sbox.v\n obj_dir/AES_sbox.sv\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:286: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:287: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:288: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:290: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:291: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:292: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:293: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:295: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:296: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:297: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:298: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:300: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:301: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:302: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:303: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:305: Cannot find file containing module: 'rising_edge'\n rising_edge U2 (clk, rst,start,start_re); \n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 312,608 | module | module AES_rounds (
input clk,
input rst,
input start,
input [127:0] plaintext,
input pause,
input [127:0] key_1,
input [127:0] key_2,
input [127:0] key_3,
input [127:0] key_4,
input [127:0] key_5,
input [127:0] key_6,
input [127:0] key_7,
input [127:0] key_8,
input [127:0] key_9,
input [127:0] key_10,
input [127:0] key_11,
output reg [127:0] data_out,
output reg ready
);
parameter DEBUG = 0;
localparam IDLE = 4'h0;
localparam INITIAL_ROUND = 4'h1;
localparam REPEAT_ROUND = 4'h2;
localparam FINAL_ROUND = 4'h3;
localparam AES128_ROUNDS = 4'h9;
function [127:0] shift_rows (input [127:0] data_in);
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = {word0[31 : 24], word1[23 : 16], word2[15 : 08], word3[07 : 00]};
word_shift1 = {word1[31 : 24], word2[23 : 16], word3[15 : 08], word0[07 : 00]};
word_shift2 = {word2[31 : 24], word3[23 : 16], word0[15 : 08], word1[07 : 00]};
word_shift3 = {word3[31 : 24], word0[23 : 16], word1[15 : 08], word2[07 : 00]};
shift_rows = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction
function [31 : 0] mix_word(input [31 : 0] word_in);
reg [7 : 0] byte0, byte1, byte2, byte3;
reg [7 : 0] mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3;
begin
byte0 = word_in[31 : 24];
byte1 = word_in[23 : 16];
byte2 = word_in[15 : 08];
byte3 = word_in[07 : 00];
mixed_byte0 = Mul_2(byte0) ^ Mul_3(byte1) ^ byte2 ^ byte3;
mixed_byte1 = byte0 ^ Mul_2(byte1) ^ Mul_3(byte2) ^ byte3;
mixed_byte2 = byte0 ^ byte1 ^ Mul_2(byte2) ^ Mul_3(byte3);
mixed_byte3 = Mul_3(byte0) ^ byte1 ^ byte2 ^ Mul_2(byte3);
mix_word = {mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3};
end
endfunction
function [127 : 0] mix_columns (input [127 : 0] data_in);
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = mix_word (word0);
word_shift1 = mix_word (word1);
word_shift2 = mix_word (word2);
word_shift3 = mix_word (word3);
mix_columns = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction
function [7 : 0] Mul_2(input [7 : 0] Din);
begin Mul_2 = {Din[6 : 0], 1'b0} ^ (8'h1b & {8{Din[7]}}); end
endfunction
function [7 : 0] Mul_3(input [7 : 0] Din);
begin Mul_3 = Mul_2(Din) ^ Din; end
endfunction
reg [3:0] state_count;
reg [3:0] state_machine;
reg [127:0] state_round;
reg [127:0] state_round_old;
wire [127:0] state_round_new;
wire start_re;
always@(posedge clk or posedge rst)
begin : AES_rounds_state_machine
if(rst)
begin
ready = 0;
state_count = 'b0;
state_round_old = 'b0;
state_machine = IDLE;
end
else
begin
if (!pause)
begin
case (state_machine)
IDLE :
if (start_re)
begin
ready = 0;
state_count = 'b0;
state_machine = INITIAL_ROUND;
end
else
state_machine = IDLE;
INITIAL_ROUND:
if (start_re)
state_machine = IDLE;
else
begin
state_machine = REPEAT_ROUND;
state_round_old = key_1 ^ plaintext;
if (DEBUG == 1) $display("\n\nKeyAddition = 0x%032x\n\n", state_round_old);
end
REPEAT_ROUND :
if (start_re)
state_machine = IDLE;
else
begin
state_count = (state_count + 1);
if (state_count == AES128_ROUNDS)
begin
ready = 1;
state_machine = FINAL_ROUND;
end
else
state_machine = REPEAT_ROUND;
state_round_old = state_round;
if (DEBUG == 1) $display("\n........ROUNDS = %d", state_count);
end
FINAL_ROUND: begin
ready = 1;
state_machine = IDLE;
end
default :
begin
end
endcase
end
end
end
always@(*)
begin : AES_rounds_state_count
if(rst)
begin
state_round = 'b0;
data_out = 'b0;
end
else
begin
case(state_count)
4'h0 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_2);
if (DEBUG == 1) $display("ROUND : 1 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h1 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_3);
if (DEBUG == 1) $display("ROUND : 2 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h2 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_4);
if (DEBUG == 1) $display("ROUND : 3 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h3 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_5);
if (DEBUG == 1) $display("ROUND : 4 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h4 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_6);
if (DEBUG == 1) $display("ROUND : 5 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h5 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_7);
if (DEBUG == 1) $display("ROUND : 6 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h6 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_8);
if (DEBUG == 1) $display("ROUND : 7 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h7 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_9);
if (DEBUG == 1) $display("ROUND : 8 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h8 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_10);
if (DEBUG == 1) $display("ROUND : 9 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h9 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_11);
data_out = ((shift_rows(state_round_new)) ^ key_11);
if (DEBUG == 1) $display("ROUND : 10 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'ha : begin
state_round = (mix_columns(shift_rows(state_round_new)) );
if (DEBUG == 1) $display("ROUND : 11 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
default :
begin
data_out = 'b0;
end
endcase
end
end
AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);
AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);
AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);
AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);
AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);
AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);
AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);
AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);
AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);
AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);
AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);
AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);
AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);
AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);
AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);
AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);
rising_edge U2 (clk, rst,start,start_re);
endmodule | module AES_rounds (
input clk,
input rst,
input start,
input [127:0] plaintext,
input pause,
input [127:0] key_1,
input [127:0] key_2,
input [127:0] key_3,
input [127:0] key_4,
input [127:0] key_5,
input [127:0] key_6,
input [127:0] key_7,
input [127:0] key_8,
input [127:0] key_9,
input [127:0] key_10,
input [127:0] key_11,
output reg [127:0] data_out,
output reg ready
); |
parameter DEBUG = 0;
localparam IDLE = 4'h0;
localparam INITIAL_ROUND = 4'h1;
localparam REPEAT_ROUND = 4'h2;
localparam FINAL_ROUND = 4'h3;
localparam AES128_ROUNDS = 4'h9;
function [127:0] shift_rows (input [127:0] data_in);
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = {word0[31 : 24], word1[23 : 16], word2[15 : 08], word3[07 : 00]};
word_shift1 = {word1[31 : 24], word2[23 : 16], word3[15 : 08], word0[07 : 00]};
word_shift2 = {word2[31 : 24], word3[23 : 16], word0[15 : 08], word1[07 : 00]};
word_shift3 = {word3[31 : 24], word0[23 : 16], word1[15 : 08], word2[07 : 00]};
shift_rows = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction
function [31 : 0] mix_word(input [31 : 0] word_in);
reg [7 : 0] byte0, byte1, byte2, byte3;
reg [7 : 0] mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3;
begin
byte0 = word_in[31 : 24];
byte1 = word_in[23 : 16];
byte2 = word_in[15 : 08];
byte3 = word_in[07 : 00];
mixed_byte0 = Mul_2(byte0) ^ Mul_3(byte1) ^ byte2 ^ byte3;
mixed_byte1 = byte0 ^ Mul_2(byte1) ^ Mul_3(byte2) ^ byte3;
mixed_byte2 = byte0 ^ byte1 ^ Mul_2(byte2) ^ Mul_3(byte3);
mixed_byte3 = Mul_3(byte0) ^ byte1 ^ byte2 ^ Mul_2(byte3);
mix_word = {mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3};
end
endfunction
function [127 : 0] mix_columns (input [127 : 0] data_in);
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = mix_word (word0);
word_shift1 = mix_word (word1);
word_shift2 = mix_word (word2);
word_shift3 = mix_word (word3);
mix_columns = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction
function [7 : 0] Mul_2(input [7 : 0] Din);
begin Mul_2 = {Din[6 : 0], 1'b0} ^ (8'h1b & {8{Din[7]}}); end
endfunction
function [7 : 0] Mul_3(input [7 : 0] Din);
begin Mul_3 = Mul_2(Din) ^ Din; end
endfunction
reg [3:0] state_count;
reg [3:0] state_machine;
reg [127:0] state_round;
reg [127:0] state_round_old;
wire [127:0] state_round_new;
wire start_re;
always@(posedge clk or posedge rst)
begin : AES_rounds_state_machine
if(rst)
begin
ready = 0;
state_count = 'b0;
state_round_old = 'b0;
state_machine = IDLE;
end
else
begin
if (!pause)
begin
case (state_machine)
IDLE :
if (start_re)
begin
ready = 0;
state_count = 'b0;
state_machine = INITIAL_ROUND;
end
else
state_machine = IDLE;
INITIAL_ROUND:
if (start_re)
state_machine = IDLE;
else
begin
state_machine = REPEAT_ROUND;
state_round_old = key_1 ^ plaintext;
if (DEBUG == 1) $display("\n\nKeyAddition = 0x%032x\n\n", state_round_old);
end
REPEAT_ROUND :
if (start_re)
state_machine = IDLE;
else
begin
state_count = (state_count + 1);
if (state_count == AES128_ROUNDS)
begin
ready = 1;
state_machine = FINAL_ROUND;
end
else
state_machine = REPEAT_ROUND;
state_round_old = state_round;
if (DEBUG == 1) $display("\n........ROUNDS = %d", state_count);
end
FINAL_ROUND: begin
ready = 1;
state_machine = IDLE;
end
default :
begin
end
endcase
end
end
end
always@(*)
begin : AES_rounds_state_count
if(rst)
begin
state_round = 'b0;
data_out = 'b0;
end
else
begin
case(state_count)
4'h0 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_2);
if (DEBUG == 1) $display("ROUND : 1 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h1 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_3);
if (DEBUG == 1) $display("ROUND : 2 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h2 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_4);
if (DEBUG == 1) $display("ROUND : 3 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h3 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_5);
if (DEBUG == 1) $display("ROUND : 4 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h4 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_6);
if (DEBUG == 1) $display("ROUND : 5 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h5 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_7);
if (DEBUG == 1) $display("ROUND : 6 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h6 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_8);
if (DEBUG == 1) $display("ROUND : 7 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h7 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_9);
if (DEBUG == 1) $display("ROUND : 8 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h8 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_10);
if (DEBUG == 1) $display("ROUND : 9 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'h9 : begin
state_round = (mix_columns(shift_rows(state_round_new)) ^ key_11);
data_out = ((shift_rows(state_round_new)) ^ key_11);
if (DEBUG == 1) $display("ROUND : 10 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
4'ha : begin
state_round = (mix_columns(shift_rows(state_round_new)) );
if (DEBUG == 1) $display("ROUND : 11 Substitution =0x%032x, ShiftRow =0x%032x, MixColumn ==0x%032x, KeyAddition ==0x%032x ",
state_round_new, shift_rows(state_round_new) , mix_columns(shift_rows(state_round_new)) ,state_round );
end
default :
begin
data_out = 'b0;
end
endcase
end
end
AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);
AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);
AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);
AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);
AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);
AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);
AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);
AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);
AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);
AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);
AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);
AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);
AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);
AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);
AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);
AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);
rising_edge U2 (clk, rst,start,start_re);
endmodule | 1 |
141,845 | data/full_repos/permissive/96068636/AES_rounds.v | 96,068,636 | AES_rounds.v | v | 311 | 138 | [] | [] | [] | null | line:44: before: "(" | null | 1: b"%Error: data/full_repos/permissive/96068636/AES_rounds.v:285: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.v\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.sv\n AES_sbox\n AES_sbox.v\n AES_sbox.sv\n obj_dir/AES_sbox\n obj_dir/AES_sbox.v\n obj_dir/AES_sbox.sv\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:286: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:287: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:288: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:290: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:291: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:292: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:293: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:295: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:296: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:297: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:298: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:300: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:301: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:302: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:303: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:305: Cannot find file containing module: 'rising_edge'\n rising_edge U2 (clk, rst,start,start_re); \n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 312,608 | function | function [127:0] shift_rows (input [127:0] data_in);
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = {word0[31 : 24], word1[23 : 16], word2[15 : 08], word3[07 : 00]};
word_shift1 = {word1[31 : 24], word2[23 : 16], word3[15 : 08], word0[07 : 00]};
word_shift2 = {word2[31 : 24], word3[23 : 16], word0[15 : 08], word1[07 : 00]};
word_shift3 = {word3[31 : 24], word0[23 : 16], word1[15 : 08], word2[07 : 00]};
shift_rows = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction | function [127:0] shift_rows (input [127:0] data_in); |
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = {word0[31 : 24], word1[23 : 16], word2[15 : 08], word3[07 : 00]};
word_shift1 = {word1[31 : 24], word2[23 : 16], word3[15 : 08], word0[07 : 00]};
word_shift2 = {word2[31 : 24], word3[23 : 16], word0[15 : 08], word1[07 : 00]};
word_shift3 = {word3[31 : 24], word0[23 : 16], word1[15 : 08], word2[07 : 00]};
shift_rows = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction | 1 |
141,846 | data/full_repos/permissive/96068636/AES_rounds.v | 96,068,636 | AES_rounds.v | v | 311 | 138 | [] | [] | [] | null | line:44: before: "(" | null | 1: b"%Error: data/full_repos/permissive/96068636/AES_rounds.v:285: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.v\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.sv\n AES_sbox\n AES_sbox.v\n AES_sbox.sv\n obj_dir/AES_sbox\n obj_dir/AES_sbox.v\n obj_dir/AES_sbox.sv\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:286: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:287: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:288: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:290: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:291: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:292: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:293: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:295: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:296: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:297: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:298: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:300: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:301: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:302: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:303: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:305: Cannot find file containing module: 'rising_edge'\n rising_edge U2 (clk, rst,start,start_re); \n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 312,608 | function | function [31 : 0] mix_word(input [31 : 0] word_in);
reg [7 : 0] byte0, byte1, byte2, byte3;
reg [7 : 0] mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3;
begin
byte0 = word_in[31 : 24];
byte1 = word_in[23 : 16];
byte2 = word_in[15 : 08];
byte3 = word_in[07 : 00];
mixed_byte0 = Mul_2(byte0) ^ Mul_3(byte1) ^ byte2 ^ byte3;
mixed_byte1 = byte0 ^ Mul_2(byte1) ^ Mul_3(byte2) ^ byte3;
mixed_byte2 = byte0 ^ byte1 ^ Mul_2(byte2) ^ Mul_3(byte3);
mixed_byte3 = Mul_3(byte0) ^ byte1 ^ byte2 ^ Mul_2(byte3);
mix_word = {mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3};
end
endfunction | function [31 : 0] mix_word(input [31 : 0] word_in); |
reg [7 : 0] byte0, byte1, byte2, byte3;
reg [7 : 0] mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3;
begin
byte0 = word_in[31 : 24];
byte1 = word_in[23 : 16];
byte2 = word_in[15 : 08];
byte3 = word_in[07 : 00];
mixed_byte0 = Mul_2(byte0) ^ Mul_3(byte1) ^ byte2 ^ byte3;
mixed_byte1 = byte0 ^ Mul_2(byte1) ^ Mul_3(byte2) ^ byte3;
mixed_byte2 = byte0 ^ byte1 ^ Mul_2(byte2) ^ Mul_3(byte3);
mixed_byte3 = Mul_3(byte0) ^ byte1 ^ byte2 ^ Mul_2(byte3);
mix_word = {mixed_byte0, mixed_byte1, mixed_byte2, mixed_byte3};
end
endfunction | 1 |
141,847 | data/full_repos/permissive/96068636/AES_rounds.v | 96,068,636 | AES_rounds.v | v | 311 | 138 | [] | [] | [] | null | line:44: before: "(" | null | 1: b"%Error: data/full_repos/permissive/96068636/AES_rounds.v:285: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.v\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.sv\n AES_sbox\n AES_sbox.v\n AES_sbox.sv\n obj_dir/AES_sbox\n obj_dir/AES_sbox.v\n obj_dir/AES_sbox.sv\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:286: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:287: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:288: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:290: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:291: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:292: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:293: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:295: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:296: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:297: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:298: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:300: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:301: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:302: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:303: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:305: Cannot find file containing module: 'rising_edge'\n rising_edge U2 (clk, rst,start,start_re); \n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 312,608 | function | function [127 : 0] mix_columns (input [127 : 0] data_in);
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = mix_word (word0);
word_shift1 = mix_word (word1);
word_shift2 = mix_word (word2);
word_shift3 = mix_word (word3);
mix_columns = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction | function [127 : 0] mix_columns (input [127 : 0] data_in); |
reg [31:0] word0,word1,word2,word3;
reg [31:0] word_shift0,word_shift1,word_shift2,word_shift3;
begin
word0 = data_in[127 : 096];
word1 = data_in[095 : 064];
word2 = data_in[063 : 032];
word3 = data_in[031 : 000];
word_shift0 = mix_word (word0);
word_shift1 = mix_word (word1);
word_shift2 = mix_word (word2);
word_shift3 = mix_word (word3);
mix_columns = {word_shift0, word_shift1, word_shift2, word_shift3};
end
endfunction | 1 |
141,848 | data/full_repos/permissive/96068636/AES_rounds.v | 96,068,636 | AES_rounds.v | v | 311 | 138 | [] | [] | [] | null | line:44: before: "(" | null | 1: b"%Error: data/full_repos/permissive/96068636/AES_rounds.v:285: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.v\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.sv\n AES_sbox\n AES_sbox.v\n AES_sbox.sv\n obj_dir/AES_sbox\n obj_dir/AES_sbox.v\n obj_dir/AES_sbox.sv\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:286: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:287: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:288: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:290: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:291: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:292: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:293: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:295: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:296: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:297: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:298: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:300: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:301: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:302: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:303: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:305: Cannot find file containing module: 'rising_edge'\n rising_edge U2 (clk, rst,start,start_re); \n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 312,608 | function | function [7 : 0] Mul_2(input [7 : 0] Din);
begin Mul_2 = {Din[6 : 0], 1'b0} ^ (8'h1b & {8{Din[7]}}); end
endfunction | function [7 : 0] Mul_2(input [7 : 0] Din); |
begin Mul_2 = {Din[6 : 0], 1'b0} ^ (8'h1b & {8{Din[7]}}); end
endfunction | 1 |
141,849 | data/full_repos/permissive/96068636/AES_rounds.v | 96,068,636 | AES_rounds.v | v | 311 | 138 | [] | [] | [] | null | line:44: before: "(" | null | 1: b"%Error: data/full_repos/permissive/96068636/AES_rounds.v:285: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB5 (state_round_old[127:120],state_round_new[127:120]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.v\n data/full_repos/permissive/96068636,data/full_repos/permissive/96068636/AES_sbox.sv\n AES_sbox\n AES_sbox.v\n AES_sbox.sv\n obj_dir/AES_sbox\n obj_dir/AES_sbox.v\n obj_dir/AES_sbox.sv\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:286: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB6 (state_round_old[119:112],state_round_new[119:112]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:287: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB7 (state_round_old[111:104],state_round_new[111:104]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:288: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB8 (state_round_old[103:096],state_round_new[103:096]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:290: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB9 (state_round_old[095:088],state_round_new[095:088]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:291: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB10 (state_round_old[087:080],state_round_new[087:080]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:292: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB11 (state_round_old[079:072],state_round_new[079:072]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:293: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB12 (state_round_old[071:064],state_round_new[071:064]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:295: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB13 (state_round_old[063:056],state_round_new[063:056]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:296: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB14 (state_round_old[055:048],state_round_new[055:048]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:297: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB15 (state_round_old[047:040],state_round_new[047:040]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:298: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB16 (state_round_old[039:032],state_round_new[039:032]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:300: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB17 (state_round_old[031:024],state_round_new[031:024]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:301: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB18 (state_round_old[023:016],state_round_new[023:016]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:302: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB19 (state_round_old[015:008],state_round_new[015:008]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:303: Cannot find file containing module: 'AES_sbox'\n AES_sbox SB20 (state_round_old[007:000],state_round_new[007:000]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/96068636/AES_rounds.v:305: Cannot find file containing module: 'rising_edge'\n rising_edge U2 (clk, rst,start,start_re); \n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 312,608 | function | function [7 : 0] Mul_3(input [7 : 0] Din);
begin Mul_3 = Mul_2(Din) ^ Din; end
endfunction | function [7 : 0] Mul_3(input [7 : 0] Din); |
begin Mul_3 = Mul_2(Din) ^ Din; end
endfunction | 1 |
141,850 | data/full_repos/permissive/96068636/AES_sbox.v | 96,068,636 | AES_sbox.v | v | 280 | 73 | [] | [] | [] | null | line:280: before: "/" | data/verilator_xmls/e259a849-df2a-414c-abee-e550ffd33b8b.xml | null | 312,609 | module | module AES_sbox(
input [7:0] a,
output reg [7:0] s
);
always@(*)
case (a)
8'h00 : s <= 8'h63;
8'h01 : s <= 8'h7c;
8'h02 : s <= 8'h77;
8'h03 : s <= 8'h7b;
8'h04 : s <= 8'hf2;
8'h05 : s <= 8'h6b;
8'h06 : s <= 8'h6f;
8'h07 : s <= 8'hc5;
8'h08 : s <= 8'h30;
8'h09 : s <= 8'h01;
8'h0a : s <= 8'h67;
8'h0b : s <= 8'h2b;
8'h0c : s <= 8'hfe;
8'h0d : s <= 8'hd7;
8'h0e : s <= 8'hab;
8'h0f : s <= 8'h76;
8'h10 : s <= 8'hca;
8'h11 : s <= 8'h82;
8'h12 : s <= 8'hc9;
8'h13 : s <= 8'h7d;
8'h14 : s <= 8'hfa;
8'h15 : s <= 8'h59;
8'h16 : s <= 8'h47;
8'h17 : s <= 8'hf0;
8'h18 : s <= 8'had;
8'h19 : s <= 8'hd4;
8'h1a : s <= 8'ha2;
8'h1b : s <= 8'haf;
8'h1c : s <= 8'h9c;
8'h1d : s <= 8'ha4;
8'h1e : s <= 8'h72;
8'h1f : s <= 8'hc0;
8'h20 : s <= 8'hb7;
8'h21 : s <= 8'hfd;
8'h22 : s <= 8'h93;
8'h23 : s <= 8'h26;
8'h24 : s <= 8'h36;
8'h25 : s <= 8'h3f;
8'h26 : s <= 8'hf7;
8'h27 : s <= 8'hcc;
8'h28 : s <= 8'h34;
8'h29 : s <= 8'ha5;
8'h2a : s <= 8'he5;
8'h2b : s <= 8'hf1;
8'h2c : s <= 8'h71;
8'h2d : s <= 8'hd8;
8'h2e : s <= 8'h31;
8'h2f : s <= 8'h15;
8'h30 : s <= 8'h04;
8'h31 : s <= 8'hc7;
8'h32 : s <= 8'h23;
8'h33 : s <= 8'hc3;
8'h34 : s <= 8'h18;
8'h35 : s <= 8'h96;
8'h36 : s <= 8'h05;
8'h37 : s <= 8'h9a;
8'h38 : s <= 8'h07;
8'h39 : s <= 8'h12;
8'h3a : s <= 8'h80;
8'h3b : s <= 8'he2;
8'h3c : s <= 8'heb;
8'h3d : s <= 8'h27;
8'h3e : s <= 8'hb2;
8'h3f : s <= 8'h75;
8'h40 : s <= 8'h09;
8'h41 : s <= 8'h83;
8'h42 : s <= 8'h2c;
8'h43 : s <= 8'h1a;
8'h44 : s <= 8'h1b;
8'h45 : s <= 8'h6e;
8'h46 : s <= 8'h5a;
8'h47 : s <= 8'ha0;
8'h48 : s <= 8'h52;
8'h49 : s <= 8'h3b;
8'h4a : s <= 8'hd6;
8'h4b : s <= 8'hb3;
8'h4c : s <= 8'h29;
8'h4d : s <= 8'he3;
8'h4e : s <= 8'h2f;
8'h4f : s <= 8'h84;
8'h50 : s <= 8'h53;
8'h51 : s <= 8'hd1;
8'h52 : s <= 8'h00;
8'h53 : s <= 8'hed;
8'h54 : s <= 8'h20;
8'h55 : s <= 8'hfc;
8'h56 : s <= 8'hb1;
8'h57 : s <= 8'h5b;
8'h58 : s <= 8'h6a;
8'h59 : s <= 8'hcb;
8'h5a : s <= 8'hbe;
8'h5b : s <= 8'h39;
8'h5c : s <= 8'h4a;
8'h5d : s <= 8'h4c;
8'h5e : s <= 8'h58;
8'h5f : s <= 8'hcf;
8'h60 : s <= 8'hd0;
8'h61 : s <= 8'hef;
8'h62 : s <= 8'haa;
8'h63 : s <= 8'hfb;
8'h64 : s <= 8'h43;
8'h65 : s <= 8'h4d;
8'h66 : s <= 8'h33;
8'h67 : s <= 8'h85;
8'h68 : s <= 8'h45;
8'h69 : s <= 8'hf9;
8'h6a : s <= 8'h02;
8'h6b : s <= 8'h7f;
8'h6c : s <= 8'h50;
8'h6d : s <= 8'h3c;
8'h6e : s <= 8'h9f;
8'h6f : s <= 8'ha8;
8'h70 : s <= 8'h51;
8'h71 : s <= 8'ha3;
8'h72 : s <= 8'h40;
8'h73 : s <= 8'h8f;
8'h74 : s <= 8'h92;
8'h75 : s <= 8'h9d;
8'h76 : s <= 8'h38;
8'h77 : s <= 8'hf5;
8'h78 : s <= 8'hbc;
8'h79 : s <= 8'hb6;
8'h7a : s <= 8'hda;
8'h7b : s <= 8'h21;
8'h7c : s <= 8'h10;
8'h7d : s <= 8'hff;
8'h7e : s <= 8'hf3;
8'h7f : s <= 8'hd2;
8'h80 : s <= 8'hcd;
8'h81 : s <= 8'h0c;
8'h82 : s <= 8'h13;
8'h83 : s <= 8'hec;
8'h84 : s <= 8'h5f;
8'h85 : s <= 8'h97;
8'h86 : s <= 8'h44;
8'h87 : s <= 8'h17;
8'h88 : s <= 8'hc4;
8'h89 : s <= 8'ha7;
8'h8a : s <= 8'h7e;
8'h8b : s <= 8'h3d;
8'h8c : s <= 8'h64;
8'h8d : s <= 8'h5d;
8'h8e : s <= 8'h19;
8'h8f : s <= 8'h73;
8'h90 : s <= 8'h60;
8'h91 : s <= 8'h81;
8'h92 : s <= 8'h4f;
8'h93 : s <= 8'hdc;
8'h94 : s <= 8'h22;
8'h95 : s <= 8'h2a;
8'h96 : s <= 8'h90;
8'h97 : s <= 8'h88;
8'h98 : s <= 8'h46;
8'h99 : s <= 8'hee;
8'h9a : s <= 8'hb8;
8'h9b : s <= 8'h14;
8'h9c : s <= 8'hde;
8'h9d : s <= 8'h5e;
8'h9e : s <= 8'h0b;
8'h9f : s <= 8'hdb;
8'ha0 : s <= 8'he0;
8'ha1 : s <= 8'h32;
8'ha2 : s <= 8'h3a;
8'ha3 : s <= 8'h0a;
8'ha4 : s <= 8'h49;
8'ha5 : s <= 8'h06;
8'ha6 : s <= 8'h24;
8'ha7 : s <= 8'h5c;
8'ha8 : s <= 8'hc2;
8'ha9 : s <= 8'hd3;
8'haa : s <= 8'hac;
8'hab : s <= 8'h62;
8'hac : s <= 8'h91;
8'had : s <= 8'h95;
8'hae : s <= 8'he4;
8'haf : s <= 8'h79;
8'hb0 : s <= 8'he7;
8'hb1 : s <= 8'hc8;
8'hb2 : s <= 8'h37;
8'hb3 : s <= 8'h6d;
8'hb4 : s <= 8'h8d;
8'hb5 : s <= 8'hd5;
8'hb6 : s <= 8'h4e;
8'hb7 : s <= 8'ha9;
8'hb8 : s <= 8'h6c;
8'hb9 : s <= 8'h56;
8'hba : s <= 8'hf4;
8'hbb : s <= 8'hea;
8'hbc : s <= 8'h65;
8'hbd : s <= 8'h7a;
8'hbe : s <= 8'hae;
8'hbf : s <= 8'h08;
8'hc0 : s <= 8'hba;
8'hc1 : s <= 8'h78;
8'hc2 : s <= 8'h25;
8'hc3 : s <= 8'h2e;
8'hc4 : s <= 8'h1c;
8'hc5 : s <= 8'ha6;
8'hc6 : s <= 8'hb4;
8'hc7 : s <= 8'hc6;
8'hc8 : s <= 8'he8;
8'hc9 : s <= 8'hdd;
8'hca : s <= 8'h74;
8'hcb : s <= 8'h1f;
8'hcc : s <= 8'h4b;
8'hcd : s <= 8'hbd;
8'hce : s <= 8'h8b;
8'hcf : s <= 8'h8a;
8'hd0 : s <= 8'h70;
8'hd1 : s <= 8'h3e;
8'hd2 : s <= 8'hb5;
8'hd3 : s <= 8'h66;
8'hd4 : s <= 8'h48;
8'hd5 : s <= 8'h03;
8'hd6 : s <= 8'hf6;
8'hd7 : s <= 8'h0e;
8'hd8 : s <= 8'h61;
8'hd9 : s <= 8'h35;
8'hda : s <= 8'h57;
8'hdb : s <= 8'hb9;
8'hdc : s <= 8'h86;
8'hdd : s <= 8'hc1;
8'hde : s <= 8'h1d;
8'hdf : s <= 8'h9e;
8'he0 : s <= 8'he1;
8'he1 : s <= 8'hf8;
8'he2 : s <= 8'h98;
8'he3 : s <= 8'h11;
8'he4 : s <= 8'h69;
8'he5 : s <= 8'hd9;
8'he6 : s <= 8'h8e;
8'he7 : s <= 8'h94;
8'he8 : s <= 8'h9b;
8'he9 : s <= 8'h1e;
8'hea : s <= 8'h87;
8'heb : s <= 8'he9;
8'hec : s <= 8'hce;
8'hed : s <= 8'h55;
8'hee : s <= 8'h28;
8'hef : s <= 8'hdf;
8'hf0 : s <= 8'h8c;
8'hf1 : s <= 8'ha1;
8'hf2 : s <= 8'h89;
8'hf3 : s <= 8'h0d;
8'hf4 : s <= 8'hbf;
8'hf5 : s <= 8'he6;
8'hf6 : s <= 8'h42;
8'hf7 : s <= 8'h68;
8'hf8 : s <= 8'h41;
8'hf9 : s <= 8'h99;
8'hfa : s <= 8'h2d;
8'hfb : s <= 8'h0f;
8'hfc : s <= 8'hb0;
8'hfd : s <= 8'h54;
8'hfe : s <= 8'hbb;
8'hff : s <= 8'h16;
default : s <= 8'h00;
endcase
endmodule | module AES_sbox(
input [7:0] a,
output reg [7:0] s
); |
always@(*)
case (a)
8'h00 : s <= 8'h63;
8'h01 : s <= 8'h7c;
8'h02 : s <= 8'h77;
8'h03 : s <= 8'h7b;
8'h04 : s <= 8'hf2;
8'h05 : s <= 8'h6b;
8'h06 : s <= 8'h6f;
8'h07 : s <= 8'hc5;
8'h08 : s <= 8'h30;
8'h09 : s <= 8'h01;
8'h0a : s <= 8'h67;
8'h0b : s <= 8'h2b;
8'h0c : s <= 8'hfe;
8'h0d : s <= 8'hd7;
8'h0e : s <= 8'hab;
8'h0f : s <= 8'h76;
8'h10 : s <= 8'hca;
8'h11 : s <= 8'h82;
8'h12 : s <= 8'hc9;
8'h13 : s <= 8'h7d;
8'h14 : s <= 8'hfa;
8'h15 : s <= 8'h59;
8'h16 : s <= 8'h47;
8'h17 : s <= 8'hf0;
8'h18 : s <= 8'had;
8'h19 : s <= 8'hd4;
8'h1a : s <= 8'ha2;
8'h1b : s <= 8'haf;
8'h1c : s <= 8'h9c;
8'h1d : s <= 8'ha4;
8'h1e : s <= 8'h72;
8'h1f : s <= 8'hc0;
8'h20 : s <= 8'hb7;
8'h21 : s <= 8'hfd;
8'h22 : s <= 8'h93;
8'h23 : s <= 8'h26;
8'h24 : s <= 8'h36;
8'h25 : s <= 8'h3f;
8'h26 : s <= 8'hf7;
8'h27 : s <= 8'hcc;
8'h28 : s <= 8'h34;
8'h29 : s <= 8'ha5;
8'h2a : s <= 8'he5;
8'h2b : s <= 8'hf1;
8'h2c : s <= 8'h71;
8'h2d : s <= 8'hd8;
8'h2e : s <= 8'h31;
8'h2f : s <= 8'h15;
8'h30 : s <= 8'h04;
8'h31 : s <= 8'hc7;
8'h32 : s <= 8'h23;
8'h33 : s <= 8'hc3;
8'h34 : s <= 8'h18;
8'h35 : s <= 8'h96;
8'h36 : s <= 8'h05;
8'h37 : s <= 8'h9a;
8'h38 : s <= 8'h07;
8'h39 : s <= 8'h12;
8'h3a : s <= 8'h80;
8'h3b : s <= 8'he2;
8'h3c : s <= 8'heb;
8'h3d : s <= 8'h27;
8'h3e : s <= 8'hb2;
8'h3f : s <= 8'h75;
8'h40 : s <= 8'h09;
8'h41 : s <= 8'h83;
8'h42 : s <= 8'h2c;
8'h43 : s <= 8'h1a;
8'h44 : s <= 8'h1b;
8'h45 : s <= 8'h6e;
8'h46 : s <= 8'h5a;
8'h47 : s <= 8'ha0;
8'h48 : s <= 8'h52;
8'h49 : s <= 8'h3b;
8'h4a : s <= 8'hd6;
8'h4b : s <= 8'hb3;
8'h4c : s <= 8'h29;
8'h4d : s <= 8'he3;
8'h4e : s <= 8'h2f;
8'h4f : s <= 8'h84;
8'h50 : s <= 8'h53;
8'h51 : s <= 8'hd1;
8'h52 : s <= 8'h00;
8'h53 : s <= 8'hed;
8'h54 : s <= 8'h20;
8'h55 : s <= 8'hfc;
8'h56 : s <= 8'hb1;
8'h57 : s <= 8'h5b;
8'h58 : s <= 8'h6a;
8'h59 : s <= 8'hcb;
8'h5a : s <= 8'hbe;
8'h5b : s <= 8'h39;
8'h5c : s <= 8'h4a;
8'h5d : s <= 8'h4c;
8'h5e : s <= 8'h58;
8'h5f : s <= 8'hcf;
8'h60 : s <= 8'hd0;
8'h61 : s <= 8'hef;
8'h62 : s <= 8'haa;
8'h63 : s <= 8'hfb;
8'h64 : s <= 8'h43;
8'h65 : s <= 8'h4d;
8'h66 : s <= 8'h33;
8'h67 : s <= 8'h85;
8'h68 : s <= 8'h45;
8'h69 : s <= 8'hf9;
8'h6a : s <= 8'h02;
8'h6b : s <= 8'h7f;
8'h6c : s <= 8'h50;
8'h6d : s <= 8'h3c;
8'h6e : s <= 8'h9f;
8'h6f : s <= 8'ha8;
8'h70 : s <= 8'h51;
8'h71 : s <= 8'ha3;
8'h72 : s <= 8'h40;
8'h73 : s <= 8'h8f;
8'h74 : s <= 8'h92;
8'h75 : s <= 8'h9d;
8'h76 : s <= 8'h38;
8'h77 : s <= 8'hf5;
8'h78 : s <= 8'hbc;
8'h79 : s <= 8'hb6;
8'h7a : s <= 8'hda;
8'h7b : s <= 8'h21;
8'h7c : s <= 8'h10;
8'h7d : s <= 8'hff;
8'h7e : s <= 8'hf3;
8'h7f : s <= 8'hd2;
8'h80 : s <= 8'hcd;
8'h81 : s <= 8'h0c;
8'h82 : s <= 8'h13;
8'h83 : s <= 8'hec;
8'h84 : s <= 8'h5f;
8'h85 : s <= 8'h97;
8'h86 : s <= 8'h44;
8'h87 : s <= 8'h17;
8'h88 : s <= 8'hc4;
8'h89 : s <= 8'ha7;
8'h8a : s <= 8'h7e;
8'h8b : s <= 8'h3d;
8'h8c : s <= 8'h64;
8'h8d : s <= 8'h5d;
8'h8e : s <= 8'h19;
8'h8f : s <= 8'h73;
8'h90 : s <= 8'h60;
8'h91 : s <= 8'h81;
8'h92 : s <= 8'h4f;
8'h93 : s <= 8'hdc;
8'h94 : s <= 8'h22;
8'h95 : s <= 8'h2a;
8'h96 : s <= 8'h90;
8'h97 : s <= 8'h88;
8'h98 : s <= 8'h46;
8'h99 : s <= 8'hee;
8'h9a : s <= 8'hb8;
8'h9b : s <= 8'h14;
8'h9c : s <= 8'hde;
8'h9d : s <= 8'h5e;
8'h9e : s <= 8'h0b;
8'h9f : s <= 8'hdb;
8'ha0 : s <= 8'he0;
8'ha1 : s <= 8'h32;
8'ha2 : s <= 8'h3a;
8'ha3 : s <= 8'h0a;
8'ha4 : s <= 8'h49;
8'ha5 : s <= 8'h06;
8'ha6 : s <= 8'h24;
8'ha7 : s <= 8'h5c;
8'ha8 : s <= 8'hc2;
8'ha9 : s <= 8'hd3;
8'haa : s <= 8'hac;
8'hab : s <= 8'h62;
8'hac : s <= 8'h91;
8'had : s <= 8'h95;
8'hae : s <= 8'he4;
8'haf : s <= 8'h79;
8'hb0 : s <= 8'he7;
8'hb1 : s <= 8'hc8;
8'hb2 : s <= 8'h37;
8'hb3 : s <= 8'h6d;
8'hb4 : s <= 8'h8d;
8'hb5 : s <= 8'hd5;
8'hb6 : s <= 8'h4e;
8'hb7 : s <= 8'ha9;
8'hb8 : s <= 8'h6c;
8'hb9 : s <= 8'h56;
8'hba : s <= 8'hf4;
8'hbb : s <= 8'hea;
8'hbc : s <= 8'h65;
8'hbd : s <= 8'h7a;
8'hbe : s <= 8'hae;
8'hbf : s <= 8'h08;
8'hc0 : s <= 8'hba;
8'hc1 : s <= 8'h78;
8'hc2 : s <= 8'h25;
8'hc3 : s <= 8'h2e;
8'hc4 : s <= 8'h1c;
8'hc5 : s <= 8'ha6;
8'hc6 : s <= 8'hb4;
8'hc7 : s <= 8'hc6;
8'hc8 : s <= 8'he8;
8'hc9 : s <= 8'hdd;
8'hca : s <= 8'h74;
8'hcb : s <= 8'h1f;
8'hcc : s <= 8'h4b;
8'hcd : s <= 8'hbd;
8'hce : s <= 8'h8b;
8'hcf : s <= 8'h8a;
8'hd0 : s <= 8'h70;
8'hd1 : s <= 8'h3e;
8'hd2 : s <= 8'hb5;
8'hd3 : s <= 8'h66;
8'hd4 : s <= 8'h48;
8'hd5 : s <= 8'h03;
8'hd6 : s <= 8'hf6;
8'hd7 : s <= 8'h0e;
8'hd8 : s <= 8'h61;
8'hd9 : s <= 8'h35;
8'hda : s <= 8'h57;
8'hdb : s <= 8'hb9;
8'hdc : s <= 8'h86;
8'hdd : s <= 8'hc1;
8'hde : s <= 8'h1d;
8'hdf : s <= 8'h9e;
8'he0 : s <= 8'he1;
8'he1 : s <= 8'hf8;
8'he2 : s <= 8'h98;
8'he3 : s <= 8'h11;
8'he4 : s <= 8'h69;
8'he5 : s <= 8'hd9;
8'he6 : s <= 8'h8e;
8'he7 : s <= 8'h94;
8'he8 : s <= 8'h9b;
8'he9 : s <= 8'h1e;
8'hea : s <= 8'h87;
8'heb : s <= 8'he9;
8'hec : s <= 8'hce;
8'hed : s <= 8'h55;
8'hee : s <= 8'h28;
8'hef : s <= 8'hdf;
8'hf0 : s <= 8'h8c;
8'hf1 : s <= 8'ha1;
8'hf2 : s <= 8'h89;
8'hf3 : s <= 8'h0d;
8'hf4 : s <= 8'hbf;
8'hf5 : s <= 8'he6;
8'hf6 : s <= 8'h42;
8'hf7 : s <= 8'h68;
8'hf8 : s <= 8'h41;
8'hf9 : s <= 8'h99;
8'hfa : s <= 8'h2d;
8'hfb : s <= 8'h0f;
8'hfc : s <= 8'hb0;
8'hfd : s <= 8'h54;
8'hfe : s <= 8'hbb;
8'hff : s <= 8'h16;
default : s <= 8'h00;
endcase
endmodule | 1 |
141,851 | data/full_repos/permissive/96068636/rising_edge.v | 96,068,636 | rising_edge.v | v | 38 | 73 | [] | [] | [] | [(8, 34)] | null | data/verilator_xmls/f81054ce-d158-4ed3-9358-ab82e2c028be.xml | null | 312,610 | module | module rising_edge(
input clk,
input rst,
input signal_in,
output signal_out
);
assign signal_out = signal_in & (~ signal);
reg signal;
always@(posedge clk or posedge rst)
begin : rising_edge_detect
if(rst) signal <= 'b0;
else signal <= signal_in;
end
endmodule | module rising_edge(
input clk,
input rst,
input signal_in,
output signal_out
); |
assign signal_out = signal_in & (~ signal);
reg signal;
always@(posedge clk or posedge rst)
begin : rising_edge_detect
if(rst) signal <= 'b0;
else signal <= signal_in;
end
endmodule | 1 |
141,880 | data/full_repos/permissive/96126106/sp_tb.v | 96,126,106 | sp_tb.v | v | 54 | 169 | [] | [] | [] | null | line:42: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/96126106/sp_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=!clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/96126106/sp_tb.v:44: syntax error, unexpected \'@\'\n @(posedge micClk);\n ^\n%Error: data/full_repos/permissive/96126106/sp_tb.v:46: Unsupported or unknown PLI call: $monitor\n $monitor ("x[0][16] = %b ",uut.x[0][16],"x[1][16] = %b ",uut.x[1][16],"x[2][16] = %b ",uut.x[2][16], "x[3][16] = %b ",uut.x[3][16],"x[4][16] = %b\\n ",uut.x[4][16],\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/96126106/sp_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,614 | module | module sp_tb();
reg clk,micData;
wire micLRSel,ampSD;
wire ampPWM;
wire micClk;
sp uut (.clk(clk),.micClk(micClk),.micData(micData),.micLRSel(micLRSel),.ampPWM(ampPWM),.ampSD(ampSD));
initial
begin
clk=0;
forever
begin
#5 clk=!clk;
end
end
initial
begin
micData = 1;
repeat(64)
begin
@(posedge micClk);
micData = !micData;
$monitor ("x[0][16] = %b ",uut.x[0][16],"x[1][16] = %b ",uut.x[1][16],"x[2][16] = %b ",uut.x[2][16], "x[3][16] = %b ",uut.x[3][16],"x[4][16] = %b\n ",uut.x[4][16],
"y[0][16] = %b ",uut.y[0][16],"y[1][16] = %b ",uut.y[1][16],"y[2][16] = %b ",uut.y[2][16], "y[3][16] = %b ",uut.y[3][16],"y[4][16] = %b\n ",uut.y[4][16],
"z[0][16] = %b ",uut.z[0][19],"z[1][16] = %b ",uut.z[1][19],"z[2][16] = %b ",uut.z[2][19], "z[3][16] = %b ",uut.z[3][19],"z[4][16] = %b\n ",uut.z[4][19]);
end
#10 $finish;
end
endmodule | module sp_tb(); |
reg clk,micData;
wire micLRSel,ampSD;
wire ampPWM;
wire micClk;
sp uut (.clk(clk),.micClk(micClk),.micData(micData),.micLRSel(micLRSel),.ampPWM(ampPWM),.ampSD(ampSD));
initial
begin
clk=0;
forever
begin
#5 clk=!clk;
end
end
initial
begin
micData = 1;
repeat(64)
begin
@(posedge micClk);
micData = !micData;
$monitor ("x[0][16] = %b ",uut.x[0][16],"x[1][16] = %b ",uut.x[1][16],"x[2][16] = %b ",uut.x[2][16], "x[3][16] = %b ",uut.x[3][16],"x[4][16] = %b\n ",uut.x[4][16],
"y[0][16] = %b ",uut.y[0][16],"y[1][16] = %b ",uut.y[1][16],"y[2][16] = %b ",uut.y[2][16], "y[3][16] = %b ",uut.y[3][16],"y[4][16] = %b\n ",uut.y[4][16],
"z[0][16] = %b ",uut.z[0][19],"z[1][16] = %b ",uut.z[1][19],"z[2][16] = %b ",uut.z[2][19], "z[3][16] = %b ",uut.z[3][19],"z[4][16] = %b\n ",uut.z[4][19]);
end
#10 $finish;
end
endmodule | 1 |
141,881 | data/full_repos/permissive/96181301/quartus/arlet6502/top.v | 96,181,301 | top.v | v | 35 | 28 | [] | [] | [] | null | line:13: before: "]" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/arlet6502/top.v:17: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n mem[abus] <= din;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/arlet6502/top.v:18: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n data <= mem[abus];\n ^\n%Error: data/full_repos/permissive/96181301/quartus/arlet6502/top.v:22: Cannot find file containing module: \'cpu\'\ncpu cpu (\n^~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/arlet6502,data/full_repos/permissive/96181301/cpu\n data/full_repos/permissive/96181301/quartus/arlet6502,data/full_repos/permissive/96181301/cpu.v\n data/full_repos/permissive/96181301/quartus/arlet6502,data/full_repos/permissive/96181301/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 312,617 | module | module top (
input clk, reset
);
wire [15:0] abus;
wire [7:0] din;
wire [7:0] dout;
wire irq = 1'b0;
wire nmi = 1'b0;
wire rdy = 1'b0;
wire we;
reg [7:0] mem [8192];
reg [7:0] data;
always @(posedge clk) begin
if (we)
mem[abus] <= din;
data <= mem[abus];
end
assign dout = data;
cpu cpu (
.clk(clk),
.reset(reset),
.AB(abus),
.DI(din),
.DO(dout),
.WE(we),
.IRQ(irq),
.NMI(nmi),
.RDY(rdy)
);
endmodule | module top (
input clk, reset
); |
wire [15:0] abus;
wire [7:0] din;
wire [7:0] dout;
wire irq = 1'b0;
wire nmi = 1'b0;
wire rdy = 1'b0;
wire we;
reg [7:0] mem [8192];
reg [7:0] data;
always @(posedge clk) begin
if (we)
mem[abus] <= din;
data <= mem[abus];
end
assign dout = data;
cpu cpu (
.clk(clk),
.reset(reset),
.AB(abus),
.DI(din),
.DO(dout),
.WE(we),
.IRQ(irq),
.NMI(nmi),
.RDY(rdy)
);
endmodule | 0 |
141,882 | data/full_repos/permissive/96181301/quartus/edgeSim/top.v | 96,181,301 | top.v | v | 19 | 28 | [] | [] | [] | [(1, 18)] | null | data/verilator_xmls/43c43109-ceef-42e8-84f4-9afae28666b6.xml | null | 312,618 | module | module top (
input clk,
output out
);
reg [3:0] counter;
always @(posedge clk)
counter <= counter + 1;
wire in = counter[3];
reg inPrev;
always @(posedge clk)
inPrev <= in;
assign out = ~in & inPrev;
endmodule | module top (
input clk,
output out
); |
reg [3:0] counter;
always @(posedge clk)
counter <= counter + 1;
wire in = counter[3];
reg inPrev;
always @(posedge clk)
inPrev <= in;
assign out = ~in & inPrev;
endmodule | 0 |
141,883 | data/full_repos/permissive/96181301/quartus/fourHex/top.v | 96,181,301 | top.v | v | 53 | 52 | [] | [] | [] | [(1, 52)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/fourHex/top.v:20: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance top\n case (count[19:18]+1) \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,619 | module | module top (
input clk,
output ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8,
output an0, an1, an2, an3
);
reg [31:0] count;
always @(posedge clk) count <= count + 1;
reg [3:0] digits;
reg [7:0] segments;
always @(*) begin
case (count[19:18])
0: digits = 4'b0111;
1: digits = 4'b1011;
2: digits = 4'b1101;
3: digits = 4'b1110;
default: digits = 4'b1111;
endcase
case (count[19:18]+1)
0: segments = 8'b00000011;
1: segments = 8'b10011111;
2: segments = 8'b00100101;
3: segments = 8'b00001101;
4: segments = 8'b10011001;
5: segments = 8'b01001001;
6: segments = 8'b01000001;
7: segments = 8'b00011111;
8: segments = 8'b00000001;
9: segments = 8'b00001001;
10: segments = 8'b00010001;
11: segments = 8'b11000001;
12: segments = 8'b01100011;
13: segments = 8'b10000101;
14: segments = 8'b01100001;
15: segments = 8'b01110001;
default: segments = 8'b00000000;
endcase
end
assign { an0,an1,an2,an3 } = digits;
assign ld1 = !segments[7];
assign ld2 = !segments[6];
assign ld3 = !segments[5];
assign ld4 = !segments[4];
assign ld5 = !segments[3];
assign ld6 = !segments[2];
assign ld7 = !segments[1];
assign ld8 = !segments[0];
endmodule | module top (
input clk,
output ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8,
output an0, an1, an2, an3
); |
reg [31:0] count;
always @(posedge clk) count <= count + 1;
reg [3:0] digits;
reg [7:0] segments;
always @(*) begin
case (count[19:18])
0: digits = 4'b0111;
1: digits = 4'b1011;
2: digits = 4'b1101;
3: digits = 4'b1110;
default: digits = 4'b1111;
endcase
case (count[19:18]+1)
0: segments = 8'b00000011;
1: segments = 8'b10011111;
2: segments = 8'b00100101;
3: segments = 8'b00001101;
4: segments = 8'b10011001;
5: segments = 8'b01001001;
6: segments = 8'b01000001;
7: segments = 8'b00011111;
8: segments = 8'b00000001;
9: segments = 8'b00001001;
10: segments = 8'b00010001;
11: segments = 8'b11000001;
12: segments = 8'b01100011;
13: segments = 8'b10000101;
14: segments = 8'b01100001;
15: segments = 8'b01110001;
default: segments = 8'b00000000;
endcase
end
assign { an0,an1,an2,an3 } = digits;
assign ld1 = !segments[7];
assign ld2 = !segments[6];
assign ld3 = !segments[5];
assign ld4 = !segments[4];
assign ld5 = !segments[3];
assign ld6 = !segments[2];
assign ld7 = !segments[1];
assign ld8 = !segments[0];
endmodule | 0 |
141,884 | data/full_repos/permissive/96181301/quartus/grayLeds/top.v | 96,181,301 | top.v | v | 27 | 42 | [] | [] | [] | [(1, 26)] | null | data/verilator_xmls/f6d1b429-c95e-4e13-8b2a-8fe17aea5067.xml | null | 312,620 | module | module top (
input clk,
output led0,
output led1,
output led2,
output led3,
output led4,
output led5,
output led6,
output led7
);
reg [31:0] count;
always @(posedge clk) count <= count + 1;
assign led0 = count[24] ^ count[25];
assign led1 = count[25] ^ count[26];
assign led2 = count[26] ^ count[27];
assign led3 = count[27] ^ count[28];
assign led4 = count[28] ^ count[29];
assign led5 = count[29] ^ count[30];
assign led6 = count[30] ^ count[31];
assign led7 = count[31];
endmodule | module top (
input clk,
output led0,
output led1,
output led2,
output led3,
output led4,
output led5,
output led6,
output led7
); |
reg [31:0] count;
always @(posedge clk) count <= count + 1;
assign led0 = count[24] ^ count[25];
assign led1 = count[25] ^ count[26];
assign led2 = count[26] ^ count[27];
assign led3 = count[27] ^ count[28];
assign led4 = count[28] ^ count[29];
assign led5 = count[29] ^ count[30];
assign led6 = count[30] ^ count[31];
assign led7 = count[31];
endmodule | 0 |
141,885 | data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v | 96,181,301 | j1a.v | v | 342 | 96 | [] | [] | [] | [(5, 30), (32, 53), (55, 69), (71, 341)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:147: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n myMem[mem_addr] <= dout;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:150: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n insn <= myMem[mem_addr];\n ^\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:153: Cannot find file containing module: \'j1\'\n j1 _j1(\n ^~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.v\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.sv\n j1\n j1.v\n j1.sv\n obj_dir/j1\n obj_dir/j1.v\n obj_dir/j1.sv\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:200: Input port connection \'wd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'dout_\' generates 16 bits.\n : ... In instance top\n .wd(dout_),\n ^~\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:236: Cannot find file containing module: \'buart\'\n buart _uart0 (\n ^~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 312,622 | module | module ioport(
input clk,
inout [7:0] pins,
input we,
input [7:0] wd,
output [7:0] rd,
input [7:0] dir);
assign rd = wd;
endmodule | module ioport(
input clk,
inout [7:0] pins,
input we,
input [7:0] wd,
output [7:0] rd,
input [7:0] dir); |
assign rd = wd;
endmodule | 0 |
141,886 | data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v | 96,181,301 | j1a.v | v | 342 | 96 | [] | [] | [] | [(5, 30), (32, 53), (55, 69), (71, 341)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:147: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n myMem[mem_addr] <= dout;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:150: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n insn <= myMem[mem_addr];\n ^\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:153: Cannot find file containing module: \'j1\'\n j1 _j1(\n ^~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.v\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.sv\n j1\n j1.v\n j1.sv\n obj_dir/j1\n obj_dir/j1.v\n obj_dir/j1.sv\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:200: Input port connection \'wd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'dout_\' generates 16 bits.\n : ... In instance top\n .wd(dout_),\n ^~\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:236: Cannot find file containing module: \'buart\'\n buart _uart0 (\n ^~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 312,622 | module | module outpin(
input clk,
output reg pin,
input we,
input wd,
output reg rd);
always @(posedge clk)
if (we)
pin <= wd;
else
rd <= pin;
endmodule | module outpin(
input clk,
output reg pin,
input we,
input wd,
output reg rd); |
always @(posedge clk)
if (we)
pin <= wd;
else
rd <= pin;
endmodule | 0 |
141,887 | data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v | 96,181,301 | j1a.v | v | 342 | 96 | [] | [] | [] | [(5, 30), (32, 53), (55, 69), (71, 341)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:147: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n myMem[mem_addr] <= dout;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:150: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n insn <= myMem[mem_addr];\n ^\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:153: Cannot find file containing module: \'j1\'\n j1 _j1(\n ^~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.v\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.sv\n j1\n j1.v\n j1.sv\n obj_dir/j1\n obj_dir/j1.v\n obj_dir/j1.sv\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:200: Input port connection \'wd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'dout_\' generates 16 bits.\n : ... In instance top\n .wd(dout_),\n ^~\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:236: Cannot find file containing module: \'buart\'\n buart _uart0 (\n ^~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 312,622 | module | module inpin(
input clk,
input pin,
output reg rd);
always @(posedge clk)
rd <= pin;
endmodule | module inpin(
input clk,
input pin,
output reg rd); |
always @(posedge clk)
rd <= pin;
endmodule | 0 |
141,888 | data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v | 96,181,301 | j1a.v | v | 342 | 96 | [] | [] | [] | [(5, 30), (32, 53), (55, 69), (71, 341)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:147: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n myMem[mem_addr] <= dout;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:150: Bit extraction of array[8191:0] requires 13 bit index, not 16 bits.\n : ... In instance top\n insn <= myMem[mem_addr];\n ^\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:153: Cannot find file containing module: \'j1\'\n j1 _j1(\n ^~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.v\n data/full_repos/permissive/96181301/quartus/j1aMin,data/full_repos/permissive/96181301/j1.sv\n j1\n j1.v\n j1.sv\n obj_dir/j1\n obj_dir/j1.v\n obj_dir/j1.sv\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:200: Input port connection \'wd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'dout_\' generates 16 bits.\n : ... In instance top\n .wd(dout_),\n ^~\n%Error: data/full_repos/permissive/96181301/quartus/j1aMin/j1a.v:236: Cannot find file containing module: \'buart\'\n buart _uart0 (\n ^~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 312,622 | module | module top(input pclk, output D1, output D2, output D3, output D4, output D5,
output TXD,
input RXD,
output PIOS_00,
input PIOS_01,
output PIOS_02,
output PIOS_03,
inout PIO1_02,
inout PIO1_03,
inout PIO1_04,
inout PIO1_05,
inout PIO1_06,
inout PIO1_07,
inout PIO1_08,
inout PIO1_09,
inout PIO0_02,
inout PIO0_03,
inout PIO0_04,
inout PIO0_05,
inout PIO0_06,
inout PIO0_07,
inout PIO0_08,
inout PIO0_09,
inout PIO2_10,
inout PIO2_11,
inout PIO2_12,
inout PIO2_13,
inout PIO2_14,
inout PIO2_15,
inout PIO2_16,
inout PIO2_17,
output PIO1_18,
input PIO1_19,
output PIO1_20,
input resetq
);
localparam MHZ = 50;
wire clk = pclk;
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
wire [15:0] dout;
wire [15:0] io_din;
wire [12:0] code_addr;
reg [15:0] myMem [8191:0];
reg [15:0] insn;
always @(posedge clk) begin
if (mem_wr) begin
myMem[mem_addr] <= dout;
insn <= dout;
end else
insn <= myMem[mem_addr];
end
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn));
`define EASE_IO_TIMING
`ifdef EASE_IO_TIMING
reg io_wr_, io_rd_;
reg [15:0] dout_;
reg [15:0] io_addr_;
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
`else
wire io_wr_ = io_wr, io_rd_ = io_rd;
wire [15:0] dout_ = dout;
wire [15:0] io_addr_ = mem_addr;
`endif
reg [7:0] pmod_dir;
wire [7:0] pmod_in;
ioport _mod (.clk(clk),
.pins({PIO1_09, PIO1_08, PIO1_07, PIO1_06, PIO1_05, PIO1_04, PIO1_03, PIO1_02}),
.we(io_wr_ & io_addr_[0]),
.wd(dout_),
.rd(pmod_in),
.dir(pmod_dir));
reg [7:0] hdr1_dir;
wire [7:0] hdr1_in;
ioport _hdr1 (.clk(clk),
.pins({PIO0_09, PIO0_08, PIO0_07, PIO0_06, PIO0_05, PIO0_04, PIO0_03, PIO0_02}),
.we(io_wr_ & io_addr_[4]),
.wd(dout_[7:0]),
.rd(hdr1_in),
.dir(hdr1_dir));
reg [7:0] hdr2_dir;
wire [7:0] hdr2_in;
ioport _hdr2 (.clk(clk),
.pins({PIO2_17, PIO2_16, PIO2_15, PIO2_14, PIO2_13, PIO2_12, PIO2_11, PIO2_10}),
.we(io_wr_ & io_addr_[6]),
.wd(dout_[7:0]),
.rd(hdr2_in),
.dir(hdr2_dir));
wire uart0_valid, uart0_busy;
wire [7:0] uart0_data;
wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
wire uart_RXD;
inpin _rcxd(.clk(clk), .pin(RXD), .rd(uart_RXD));
buart _uart0 (
.clk(clk),
.resetq(1'b1),
.rx(uart_RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(dout_[7:0]),
.rx_data(uart0_data));
wire [4:0] LEDS;
wire w4 = io_wr_ & io_addr_[2];
outpin led0 (.clk(clk), .we(w4), .pin(D5), .wd(dout_[0]), .rd(LEDS[0]));
outpin led1 (.clk(clk), .we(w4), .pin(D4), .wd(dout_[1]), .rd(LEDS[1]));
outpin led2 (.clk(clk), .we(w4), .pin(D3), .wd(dout_[2]), .rd(LEDS[2]));
outpin led3 (.clk(clk), .we(w4), .pin(D2), .wd(dout_[3]), .rd(LEDS[3]));
outpin led4 (.clk(clk), .we(w4), .pin(D1), .wd(dout_[4]), .rd(LEDS[4]));
wire [4:0] PIOS;
wire w8 = io_wr_ & io_addr_[3];
outpin pio0 (.clk(clk), .we(w8), .pin(PIOS_03), .wd(dout_[0]), .rd(PIOS[0]));
outpin pio1 (.clk(clk), .we(w8), .pin(PIOS_02), .wd(dout_[1]), .rd(PIOS[1]));
outpin pio2 (.clk(clk), .we(w8), .pin(PIOS_00), .wd(dout_[2]), .rd(PIOS[2]));
outpin pio3 (.clk(clk), .we(w8), .pin(PIO1_18), .wd(dout_[3]), .rd(PIOS[3]));
outpin pio4 (.clk(clk), .we(w8), .pin(PIO1_20), .wd(dout_[4]), .rd(PIOS[4]));
wire random = 1'b0;
assign io_din =
(io_addr_[ 0] ? {8'd0, pmod_in} : 16'd0) |
(io_addr_[ 1] ? {8'd0, pmod_dir} : 16'd0) |
(io_addr_[ 2] ? {11'd0, LEDS} : 16'd0) |
(io_addr_[ 3] ? {11'd0, PIOS} : 16'd0) |
(io_addr_[ 4] ? {8'd0, hdr1_in} : 16'd0) |
(io_addr_[ 5] ? {8'd0, hdr1_dir} : 16'd0) |
(io_addr_[ 6] ? {8'd0, hdr2_in} : 16'd0) |
(io_addr_[ 7] ? {8'd0, hdr2_dir} : 16'd0) |
(io_addr_[12] ? {8'd0, uart0_data} : 16'd0) |
(io_addr_[13] ? {11'd0, random, PIO1_19, PIOS_01, uart0_valid, !uart0_busy} : 16'd0);
reg boot, s0, s1;
always @(posedge clk) begin
if (io_wr_ & io_addr_[1])
pmod_dir <= dout_[7:0];
if (io_wr_ & io_addr_[5])
hdr1_dir <= dout_[7:0];
if (io_wr_ & io_addr_[7])
hdr2_dir <= dout_[7:0];
if (io_wr_ & io_addr_[11])
{boot, s1, s0} <= dout_[2:0];
end
endmodule | module top(input pclk, output D1, output D2, output D3, output D4, output D5,
output TXD,
input RXD,
output PIOS_00,
input PIOS_01,
output PIOS_02,
output PIOS_03,
inout PIO1_02,
inout PIO1_03,
inout PIO1_04,
inout PIO1_05,
inout PIO1_06,
inout PIO1_07,
inout PIO1_08,
inout PIO1_09,
inout PIO0_02,
inout PIO0_03,
inout PIO0_04,
inout PIO0_05,
inout PIO0_06,
inout PIO0_07,
inout PIO0_08,
inout PIO0_09,
inout PIO2_10,
inout PIO2_11,
inout PIO2_12,
inout PIO2_13,
inout PIO2_14,
inout PIO2_15,
inout PIO2_16,
inout PIO2_17,
output PIO1_18,
input PIO1_19,
output PIO1_20,
input resetq
); |
localparam MHZ = 50;
wire clk = pclk;
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
wire [15:0] dout;
wire [15:0] io_din;
wire [12:0] code_addr;
reg [15:0] myMem [8191:0];
reg [15:0] insn;
always @(posedge clk) begin
if (mem_wr) begin
myMem[mem_addr] <= dout;
insn <= dout;
end else
insn <= myMem[mem_addr];
end
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn));
`define EASE_IO_TIMING
`ifdef EASE_IO_TIMING
reg io_wr_, io_rd_;
reg [15:0] dout_;
reg [15:0] io_addr_;
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
`else
wire io_wr_ = io_wr, io_rd_ = io_rd;
wire [15:0] dout_ = dout;
wire [15:0] io_addr_ = mem_addr;
`endif
reg [7:0] pmod_dir;
wire [7:0] pmod_in;
ioport _mod (.clk(clk),
.pins({PIO1_09, PIO1_08, PIO1_07, PIO1_06, PIO1_05, PIO1_04, PIO1_03, PIO1_02}),
.we(io_wr_ & io_addr_[0]),
.wd(dout_),
.rd(pmod_in),
.dir(pmod_dir));
reg [7:0] hdr1_dir;
wire [7:0] hdr1_in;
ioport _hdr1 (.clk(clk),
.pins({PIO0_09, PIO0_08, PIO0_07, PIO0_06, PIO0_05, PIO0_04, PIO0_03, PIO0_02}),
.we(io_wr_ & io_addr_[4]),
.wd(dout_[7:0]),
.rd(hdr1_in),
.dir(hdr1_dir));
reg [7:0] hdr2_dir;
wire [7:0] hdr2_in;
ioport _hdr2 (.clk(clk),
.pins({PIO2_17, PIO2_16, PIO2_15, PIO2_14, PIO2_13, PIO2_12, PIO2_11, PIO2_10}),
.we(io_wr_ & io_addr_[6]),
.wd(dout_[7:0]),
.rd(hdr2_in),
.dir(hdr2_dir));
wire uart0_valid, uart0_busy;
wire [7:0] uart0_data;
wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
wire uart_RXD;
inpin _rcxd(.clk(clk), .pin(RXD), .rd(uart_RXD));
buart _uart0 (
.clk(clk),
.resetq(1'b1),
.rx(uart_RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(dout_[7:0]),
.rx_data(uart0_data));
wire [4:0] LEDS;
wire w4 = io_wr_ & io_addr_[2];
outpin led0 (.clk(clk), .we(w4), .pin(D5), .wd(dout_[0]), .rd(LEDS[0]));
outpin led1 (.clk(clk), .we(w4), .pin(D4), .wd(dout_[1]), .rd(LEDS[1]));
outpin led2 (.clk(clk), .we(w4), .pin(D3), .wd(dout_[2]), .rd(LEDS[2]));
outpin led3 (.clk(clk), .we(w4), .pin(D2), .wd(dout_[3]), .rd(LEDS[3]));
outpin led4 (.clk(clk), .we(w4), .pin(D1), .wd(dout_[4]), .rd(LEDS[4]));
wire [4:0] PIOS;
wire w8 = io_wr_ & io_addr_[3];
outpin pio0 (.clk(clk), .we(w8), .pin(PIOS_03), .wd(dout_[0]), .rd(PIOS[0]));
outpin pio1 (.clk(clk), .we(w8), .pin(PIOS_02), .wd(dout_[1]), .rd(PIOS[1]));
outpin pio2 (.clk(clk), .we(w8), .pin(PIOS_00), .wd(dout_[2]), .rd(PIOS[2]));
outpin pio3 (.clk(clk), .we(w8), .pin(PIO1_18), .wd(dout_[3]), .rd(PIOS[3]));
outpin pio4 (.clk(clk), .we(w8), .pin(PIO1_20), .wd(dout_[4]), .rd(PIOS[4]));
wire random = 1'b0;
assign io_din =
(io_addr_[ 0] ? {8'd0, pmod_in} : 16'd0) |
(io_addr_[ 1] ? {8'd0, pmod_dir} : 16'd0) |
(io_addr_[ 2] ? {11'd0, LEDS} : 16'd0) |
(io_addr_[ 3] ? {11'd0, PIOS} : 16'd0) |
(io_addr_[ 4] ? {8'd0, hdr1_in} : 16'd0) |
(io_addr_[ 5] ? {8'd0, hdr1_dir} : 16'd0) |
(io_addr_[ 6] ? {8'd0, hdr2_in} : 16'd0) |
(io_addr_[ 7] ? {8'd0, hdr2_dir} : 16'd0) |
(io_addr_[12] ? {8'd0, uart0_data} : 16'd0) |
(io_addr_[13] ? {11'd0, random, PIO1_19, PIOS_01, uart0_valid, !uart0_busy} : 16'd0);
reg boot, s0, s1;
always @(posedge clk) begin
if (io_wr_ & io_addr_[1])
pmod_dir <= dout_[7:0];
if (io_wr_ & io_addr_[5])
hdr1_dir <= dout_[7:0];
if (io_wr_ & io_addr_[7])
hdr2_dir <= dout_[7:0];
if (io_wr_ & io_addr_[11])
{boot, s1, s0} <= dout_[2:0];
end
endmodule | 0 |
141,889 | data/full_repos/permissive/96181301/quartus/lite8080/intr_ctrl.v | 96,181,301 | intr_ctrl.v | v | 168 | 90 | [] | [] | [] | [(35, 164)] | null | data/verilator_xmls/9a3be7ec-35eb-466b-9f27-d27561ec207e.xml | null | 312,625 | module | module intr_ctrl
(
clock, reset,
ext_intr, cpu_intr,
cpu_inte, cpu_inta,
cpu_rd, cpu_inst,
intr_ena
);
input clock;
input reset;
input [3:0] ext_intr;
output cpu_intr;
input cpu_inte;
input cpu_inta;
input cpu_rd;
output [7:0] cpu_inst;
input [3:0] intr_ena;
`define RST_1_INST 8'hcf
`define RST_3_INST 8'hdf
`define RST_5_INST 8'hef
`define RST_7_INST 8'hff
reg [7:0] cpu_inst;
reg [1:0] intSq, intSel;
reg [3:0] act_int, int_clr;
reg [7:0] int_vec;
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
intSq <= 2'b0;
intSel <= 2'b0;
cpu_inst <= 8'b0;
end
else
begin
case (intSq)
2'd0:
if ((act_int != 4'b0) && cpu_inte)
begin
if (act_int[0]) intSel <= 2'd0;
else if (act_int[2]) intSel <= 2'd1;
else if (act_int[3]) intSel <= 2'd2;
else intSel <= 2'd3;
intSq <= 2'd1;
end
2'd1:
if (cpu_inta && cpu_rd)
begin
cpu_inst <= int_vec;
intSq <= 2'd2;
end
default:
if (!cpu_inta)
begin
intSq <= 2'b0;
cpu_inst <= 8'b0;
end
endcase
end
end
always @ (intSel)
begin
case (intSel)
2'd0: int_vec <= `RST_1_INST;
2'd1: int_vec <= `RST_3_INST;
2'd2: int_vec <= `RST_5_INST;
2'd3: int_vec <= `RST_7_INST;
endcase
end
always @ (posedge reset or posedge clock)
begin
if (reset)
act_int <= 4'b0;
else
act_int <= (act_int & ~int_clr) | (ext_intr & intr_ena);
end
assign cpu_intr = |act_int;
always @ (cpu_inta or cpu_rd or intSq or intSel)
begin
if (cpu_inta && cpu_rd && (intSq == 2'd1))
begin
case (intSel)
2'd0: int_clr <= 4'b0001;
2'd1: int_clr <= 4'b0010;
2'd2: int_clr <= 4'b0100;
2'd3: int_clr <= 4'b1000;
endcase
end
else
int_clr <= 4'b0;
end
endmodule | module intr_ctrl
(
clock, reset,
ext_intr, cpu_intr,
cpu_inte, cpu_inta,
cpu_rd, cpu_inst,
intr_ena
); |
input clock;
input reset;
input [3:0] ext_intr;
output cpu_intr;
input cpu_inte;
input cpu_inta;
input cpu_rd;
output [7:0] cpu_inst;
input [3:0] intr_ena;
`define RST_1_INST 8'hcf
`define RST_3_INST 8'hdf
`define RST_5_INST 8'hef
`define RST_7_INST 8'hff
reg [7:0] cpu_inst;
reg [1:0] intSq, intSel;
reg [3:0] act_int, int_clr;
reg [7:0] int_vec;
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
intSq <= 2'b0;
intSel <= 2'b0;
cpu_inst <= 8'b0;
end
else
begin
case (intSq)
2'd0:
if ((act_int != 4'b0) && cpu_inte)
begin
if (act_int[0]) intSel <= 2'd0;
else if (act_int[2]) intSel <= 2'd1;
else if (act_int[3]) intSel <= 2'd2;
else intSel <= 2'd3;
intSq <= 2'd1;
end
2'd1:
if (cpu_inta && cpu_rd)
begin
cpu_inst <= int_vec;
intSq <= 2'd2;
end
default:
if (!cpu_inta)
begin
intSq <= 2'b0;
cpu_inst <= 8'b0;
end
endcase
end
end
always @ (intSel)
begin
case (intSel)
2'd0: int_vec <= `RST_1_INST;
2'd1: int_vec <= `RST_3_INST;
2'd2: int_vec <= `RST_5_INST;
2'd3: int_vec <= `RST_7_INST;
endcase
end
always @ (posedge reset or posedge clock)
begin
if (reset)
act_int <= 4'b0;
else
act_int <= (act_int & ~int_clr) | (ext_intr & intr_ena);
end
assign cpu_intr = |act_int;
always @ (cpu_inta or cpu_rd or intSq or intSel)
begin
if (cpu_inta && cpu_rd && (intSq == 2'd1))
begin
case (intSel)
2'd0: int_clr <= 4'b0001;
2'd1: int_clr <= 4'b0010;
2'd2: int_clr <= 4'b0100;
2'd3: int_clr <= 4'b1000;
endcase
end
else
int_clr <= 4'b0;
end
endmodule | 0 |
141,890 | data/full_repos/permissive/96181301/quartus/lite8080/light8080.v | 96,181,301 | light8080.v | v | 829 | 106 | [] | [] | [] | [(61, 826)] | null | null | 1: b'%Error: data/full_repos/permissive/96181301/quartus/lite8080/light8080.v:378: Cannot find file containing module: \'micro_rom\'\nmicro_rom rom \n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/lite8080,data/full_repos/permissive/96181301/micro_rom\n data/full_repos/permissive/96181301/quartus/lite8080,data/full_repos/permissive/96181301/micro_rom.v\n data/full_repos/permissive/96181301/quartus/lite8080,data/full_repos/permissive/96181301/micro_rom.sv\n micro_rom\n micro_rom.v\n micro_rom.sv\n obj_dir/micro_rom\n obj_dir/micro_rom.v\n obj_dir/micro_rom.sv\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/lite8080/light8080.v:624: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'cy_in_sgn\' generates 1 bits.\n : ... In instance light8080\nassign arith_res = arith_op1 + arith_op2_sgn + cy_in_sgn;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 312,626 | module | module light8080
(
clk, reset,
addr_out, vma,
io, rd,
wr, fetch,
data_in, data_out,
inta, inte,
halt, intr
);
input clk;
input reset;
output [15:0] addr_out;
output vma;
output io;
output rd;
output wr;
output fetch;
input [7:0] data_in;
output [7:0] data_out;
output inta;
output inte;
output halt;
input intr;
reg [7:0] addr_low;
reg [7:0] IR;
wire [2:0] s_field;
wire [2:0] d_field;
wire [1:0] p_field;
wire rbh;
wire [3:0] alu_op;
reg [7:0] uc_addr;
reg [8:0] next_uc_addr;
wire [7:0] uc_jmp_addr;
reg [7:0] uc_ret_addr;
wire [7:0] addr_plus_1;
reg do_reset;
wire [2:0] uc_flags1;
wire [2:0] uc_flags2;
wire [3:0] uc_addr_sel;
wire uc_jsr;
wire uc_tjsr;
wire uc_decode;
wire uc_end;
reg condition_reg;
reg condition;
wire uc_do_jmp;
wire uc_do_ret;
wire uc_halt_flag;
wire uc_halt;
reg halt_reg;
wire uc_ei;
wire uc_di;
reg inte_reg;
reg int_pending;
reg inta_reg;
wire clr_t1;
wire do_clr_t1;
wire clr_t2;
wire do_clr_t2;
wire [31:0] ucode;
reg [24:0] ucode_field2;
reg delayed_ei;
wire load_al;
wire load_addr;
wire load_t1;
wire load_t2;
wire mux_in;
wire load_do;
wire [1:0] rb_addr_sel;
wire [3:0] ra_field;
wire [7:0] rbank_data;
reg [7:0] alu_output;
wire [7:0] data_output;
reg [7:0] T1;
reg [7:0] T2;
wire [7:0] alu_input;
wire we_rb;
wire inhibit_pc_increment;
reg [3:0] rbank_rd_addr;
wire [3:0] rbank_wr_addr;
reg [7:0] DO;
reg [7:0] rbank[0:15];
reg [7:0] flag_reg;
wire [1:0] flag_pattern;
wire flag_s;
wire flag_z;
wire flag_p;
wire flag_cy;
wire flag_cy_1;
wire flag_cy_2;
wire do_cy_op;
wire do_cy_op_d;
wire do_cpc;
wire do_cpc_d;
wire do_daa;
wire clear_cy;
wire clear_ac;
wire set_ac;
wire flag_ac;
wire flag_aux_cy;
wire load_psw;
wire use_aux;
wire use_aux_cy;
reg reg_aux_cy;
wire aux_cy_in;
wire set_aux_cy;
wire set_aux;
wire [1:0] alu_fn;
wire use_logic;
wire [1:0] mux_fn;
wire use_psw;
wire [8:0] arith_op1;
wire [8:0] arith_op2;
wire [8:0] arith_op2_sgn;
wire [8:0] arith_res;
wire [7:0] arith_res8;
wire [8:0] daa_res;
reg [8:0] daa_res9;
wire daa_test1;
wire daa_test1a;
wire daa_test2;
wire [7:0] arith_daa_res;
wire cy_daa;
wire cy_in_sgn;
wire cy_in;
wire cy_in_gated;
wire cy_adder;
wire cy_arith;
wire cy_shifter;
reg [7:0] logic_res;
wire [7:0] shift_res;
wire [7:0] alu_mux1;
always @ (posedge clk)
begin
if (uc_decode)
IR <= data_in;
end
assign s_field = IR[2:0];
assign d_field = IR[5:3];
assign p_field = IR[5:4];
always @ (posedge clk)
do_reset <= reset;
assign uc_flags1 = ucode[31:29];
assign uc_flags2 = ucode[28:26];
assign uc_do_ret = ((uc_flags2 == 3'b011) && !do_reset) ? 1'b1 : 1'b0;
assign uc_jsr = ((uc_flags2 == 3'b010) && !do_reset) ? 1'b1 : 1'b0;
assign uc_tjsr = ((uc_flags2 == 3'b100) && !do_reset) ? 1'b1 : 1'b0;
assign uc_decode = ((uc_flags1 == 3'b001) && !do_reset) ? 1'b1 : 1'b0;
assign uc_end = (((uc_flags2 == 3'b001) || (uc_tjsr && !condition_reg)) && !do_reset) ? 1'b1 : 1'b0;
assign uc_halt_flag = (uc_flags1 == 3'b111) ? 1'b1 : 1'b0;
assign uc_halt = (uc_halt_flag && !inta_reg) ? 1'b1 : 1'b0;
assign uc_ei = (uc_flags1 == 3'b011) ? 1'b1 : 1'b0;
assign uc_di = ((uc_flags1 == 3'b010) || inta_reg) ? 1'b1 : 1'b0;
assign clr_t2 = (uc_flags2 == 3'b001) ? 1'b1 : 1'b0;
assign clr_t1 = (uc_flags1 == 3'b110) ? 1'b1 : 1'b0;
assign use_aux = (uc_flags1 == 3'b101) ? 1'b1 : 1'b0;
assign set_aux = (uc_flags2 == 3'b111) ? 1'b1 : 1'b0;
assign load_al = ucode[24];
assign load_addr = ucode[25];
assign do_cy_op_d = (ucode[5:2] == 4'b1011) ? 1'b1 : 1'b0;
assign do_cpc_d = ucode[0];
assign uc_do_jmp = uc_jsr | (uc_tjsr & condition_reg);
assign vma = load_addr;
assign fetch = ((uc_addr[7:4] == 4'b0) && load_addr) ? 1'b1 : 1'b0;
assign io = (uc_flags1 == 3'b100) ? 1'b1 : 1'b0;
assign rd = (uc_flags2 == 3'b101) ? 1'b1 : 1'b0;
assign wr = (uc_flags2 == 3'b110) ? 1'b1 : 1'b0;
assign uc_jmp_addr = {ucode[11:10], ucode[5:0]};
assign uc_addr_sel = {uc_do_ret, uc_do_jmp, uc_decode, uc_end};
assign addr_plus_1 = uc_addr + 8'd1;
always @ (*)
begin
case (uc_addr_sel)
4'b1000: next_uc_addr <= {1'b0, uc_ret_addr};
4'b0100: next_uc_addr <= {1'b0, uc_jmp_addr};
4'b0000: next_uc_addr <= {1'b0, addr_plus_1};
4'b0001: next_uc_addr <= {6'b0, uc_halt, 2'b11};
default: next_uc_addr <= {1'b1, data_in};
endcase
end
micro_rom rom
(
.clock(clk),
.uc_addr(next_uc_addr),
.uc_dout(ucode)
);
always @ (posedge clk)
begin
if (reset)
uc_addr <= 8'h0;
else
uc_addr <= next_uc_addr[7:0];
end
always @ (posedge clk)
begin
if (reset)
uc_ret_addr <= 8'h0;
else if (uc_do_jmp)
uc_ret_addr <= addr_plus_1;
end
assign alu_op = ucode[3:0];
always @ (posedge clk)
begin
ucode_field2 <= {do_cy_op_d, do_cpc_d, clr_t2, clr_t1,
set_aux, use_aux, rbank_rd_addr, ucode[14:4], alu_op};
end
always @ (posedge clk)
begin
if (reset || int_pending)
halt_reg <= 1'b0;
else if (uc_halt)
halt_reg <= 1'b1;
end
assign halt = halt_reg;
always @ (posedge clk)
begin
if (reset)
begin
inte_reg <= 1'b0;
delayed_ei <= 1'b0;
end
else
begin
if ((uc_di || uc_ei) && uc_end)
begin
delayed_ei <= uc_ei;
end
if (uc_end)
begin
if (uc_di)
inte_reg <= 1'b0;
else
inte_reg <= delayed_ei;
end
end
end
assign inte = inte_reg;
always @ (posedge clk)
begin
if (reset)
int_pending <= 1'b0;
else
begin
if (intr && inte_reg && !int_pending && !inta_reg)
int_pending <= 1'b1;
else if (inte_reg && uc_end)
int_pending <= 1'b0;
end
end
always @ (posedge clk)
begin
if (reset)
inta_reg <= 1'b0;
else if (int_pending && uc_end)
inta_reg <= 1'b1;
else if (uc_end && !uc_halt_flag)
inta_reg <= 1'b0;
end
assign inta = inta_reg;
assign ra_field = ucode[18:15];
assign load_t1 = ucode[23];
assign load_t2 = ucode[22];
assign mux_in = ucode[21];
assign rb_addr_sel = ucode[20:19];
assign load_do = ucode_field2[7];
assign set_aux_cy = ucode_field2[20];
assign do_clr_t1 = ucode_field2[21];
assign do_clr_t2 = ucode_field2[22];
always @ (posedge clk)
begin
if (reset || uc_decode || do_clr_t1)
T1 <= 8'h0;
else if (load_t1)
T1 <= alu_input;
end
always @ (posedge clk)
begin
if (reset || uc_decode || do_clr_t2)
T2 <= 8'h0;
else if (load_t2)
T2 <= alu_input;
end
assign alu_input = mux_in ? rbank_data : data_in;
assign rbh = (p_field == 2'b11) ? 1'b1 : 1'b0;
always @ (*)
begin
case (rb_addr_sel)
2'b00: rbank_rd_addr <= ra_field;
2'b01: rbank_rd_addr <= {1'b0, s_field};
2'b10: rbank_rd_addr <= {1'b0, d_field};
2'b11: rbank_rd_addr <= {rbh, p_field, ra_field[0]};
endcase
end
assign inhibit_pc_increment = (inta_reg && use_aux_cy && (rbank_wr_addr[3:1] == 3'b100)) ? 1'b1 : 1'b0;
assign we_rb = ucode_field2[6] & ~inhibit_pc_increment;
assign rbank_wr_addr = ucode_field2[18:15];
always @ (posedge clk)
begin
if (we_rb)
rbank[rbank_wr_addr] <= alu_output;
end
assign rbank_data = rbank[rbank_rd_addr];
assign use_psw = (ucode_field2[5:4] == 2'b11) ? 1'b1 : 1'b0;
assign data_output = use_psw ? flag_reg : alu_output;
always @ (posedge clk)
begin
if (load_do)
DO <= data_output;
end
assign alu_fn = ucode_field2[1:0];
assign use_logic = ucode_field2[2];
assign mux_fn = ucode_field2[4:3];
assign flag_pattern = ucode_field2[9:8];
assign use_aux_cy = ucode_field2[19];
assign do_cpc = ucode_field2[23];
assign do_cy_op = ucode_field2[24];
assign do_daa = (ucode_field2[5:2] == 4'b1010) ? 1'b1 : 1'b0;
assign clear_cy = ucode_field2[14];
assign clear_ac = (ucode_field2[14] && (ucode_field2[5:0] != 6'b000100)) ? 1'b1 : 1'b0;
assign set_ac = (ucode_field2[14] && (ucode_field2[5:0] == 6'b000100)) ? 1'b1 : 1'b0;
assign aux_cy_in = (!set_aux_cy) ? reg_aux_cy : 1'b1;
assign cy_in = (!use_aux_cy) ? flag_reg[0] : aux_cy_in;
assign cy_in_gated = cy_in & alu_fn[0];
assign arith_op1 = {1'b0, T2};
assign arith_op2 = {1'b0, T1};
assign arith_op2_sgn = (!alu_fn[1]) ? arith_op2 : ~arith_op2;
assign cy_in_sgn = (!alu_fn[1]) ? cy_in_gated : ~cy_in_gated;
assign arith_res = arith_op1 + arith_op2_sgn + cy_in_sgn;
assign arith_res8 = arith_res[7:0];
assign cy_adder = arith_res[8];
assign daa_test1a = arith_op2[3] & (arith_op2[2] | arith_op2[1] | arith_op2[0]);
assign daa_test1 = (flag_reg[4] || daa_test1a) ? 1'b1 : 1'b0;
always @ (posedge clk)
begin
if (reset)
daa_res9 <= 9'b0;
else if (daa_test1)
daa_res9 <= arith_op2 + 9'd6;
else
daa_res9 <= arith_op2;
end
assign daa_test2 = (flag_reg[0] || daa_test1a) ? 1'b1 : 1'b0;
assign daa_res = daa_test2 ? ({1'b0, daa_res9[7:0]} + 9'h60) : daa_res9;
assign cy_daa = daa_res[8];
assign arith_daa_res = do_daa ? daa_res[7:0] : arith_res8;
assign cy_arith = do_daa ? cy_daa : cy_adder;
always @ (*)
begin
case (alu_fn)
2'b00: logic_res <= T1 & T2;
2'b01: logic_res <= T1 ^ T2;
2'b10: logic_res <= T1 | T2;
2'b11: logic_res <= ~T1;
endcase
end
assign shift_res[6:1] = (!alu_fn[0]) ? T1[5:0] : T1[7:2];
assign shift_res[0] = (alu_fn == 2'b00) ? T1[7] :
(alu_fn == 2'b10) ? cy_in :
T1[1];
assign shift_res[7] = (alu_fn == 2'b01) ? T1[0] :
(alu_fn == 2'b11) ? cy_in :
T1[6];
assign cy_shifter = (!alu_fn[0]) ? T1[7] :
T1[0];
assign alu_mux1 = use_logic ? logic_res : shift_res;
always @ (*)
begin
case (mux_fn)
2'b00: alu_output <= alu_mux1;
2'b01: alu_output <= arith_daa_res;
2'b10: alu_output <= ~alu_mux1;
2'b11: alu_output <= {2'b0, d_field, 3'b0};
endcase
end
assign flag_s = alu_output[7];
assign flag_p = ~(^alu_output);
assign flag_z = (alu_output == 8'h0) ? 1'b1 : 1'b0;
assign flag_ac = set_ac ? 1'b1 :
clear_ac ? 1'b0 :
(arith_op1[4] ^ arith_op2_sgn[4] ^ alu_output[4]);
assign flag_cy_1 = clear_cy ? 1'b0 :
use_logic ? cy_arith :
cy_shifter;
assign flag_cy_2 = (!do_cpc) ? ~flag_reg[0] : 1'b1;
assign flag_cy = (!do_cy_op) ? flag_cy_1 : flag_cy_2;
assign flag_aux_cy = cy_adder;
always @ (posedge clk)
begin
if (reset || uc_decode)
reg_aux_cy <= 1'b1;
else
reg_aux_cy <= flag_aux_cy;
end
assign load_psw = (we_rb && (rbank_wr_addr == 4'b0110)) ? 1'b1 : 1'b0;
always @ (posedge clk)
begin
if (reset)
begin
flag_reg[7] <= 1'b0;
flag_reg[6] <= 1'b0;
flag_reg[5] <= 1'b0;
flag_reg[4] <= 1'b0;
flag_reg[3] <= 1'b0;
flag_reg[2] <= 1'b0;
flag_reg[1] <= 1'b1;
flag_reg[0] <= 1'b0;
end
else
begin
if (flag_pattern[1])
begin
if (load_psw)
begin
flag_reg[7] <= alu_output[7];
flag_reg[6] <= alu_output[6];
flag_reg[4] <= alu_output[4];
flag_reg[2] <= alu_output[2];
end
else
begin
flag_reg[7] <= flag_s;
flag_reg[6] <= flag_z;
flag_reg[4] <= flag_ac;
flag_reg[2] <= flag_p;
end
end
if (flag_pattern[0])
begin
if (load_psw)
flag_reg[0] <= alu_output[0];
else
flag_reg[0] <= flag_cy;
end
flag_reg[5] <= 1'b0;
flag_reg[3] <= 1'b0;
flag_reg[1] <= 1'b1;
end
end
always @ (*)
begin
case (d_field[2:0])
3'b000: condition <= ~flag_reg[6];
3'b001: condition <= flag_reg[6];
3'b010: condition <= ~flag_reg[0];
3'b011: condition <= flag_reg[0];
3'b100: condition <= ~flag_reg[2];
3'b101: condition <= flag_reg[2];
3'b110: condition <= ~flag_reg[7];
3'b111: condition <= flag_reg[7];
endcase
end
always @ (posedge clk)
begin
if (reset)
condition_reg <= 1'b0;
else
condition_reg <= condition;
end
always @ (posedge clk)
begin
if (reset)
addr_low <= 8'h0;
else if (load_al)
addr_low <= rbank_data;
end
assign addr_out = {rbank_data, addr_low};
assign data_out = DO;
endmodule | module light8080
(
clk, reset,
addr_out, vma,
io, rd,
wr, fetch,
data_in, data_out,
inta, inte,
halt, intr
); |
input clk;
input reset;
output [15:0] addr_out;
output vma;
output io;
output rd;
output wr;
output fetch;
input [7:0] data_in;
output [7:0] data_out;
output inta;
output inte;
output halt;
input intr;
reg [7:0] addr_low;
reg [7:0] IR;
wire [2:0] s_field;
wire [2:0] d_field;
wire [1:0] p_field;
wire rbh;
wire [3:0] alu_op;
reg [7:0] uc_addr;
reg [8:0] next_uc_addr;
wire [7:0] uc_jmp_addr;
reg [7:0] uc_ret_addr;
wire [7:0] addr_plus_1;
reg do_reset;
wire [2:0] uc_flags1;
wire [2:0] uc_flags2;
wire [3:0] uc_addr_sel;
wire uc_jsr;
wire uc_tjsr;
wire uc_decode;
wire uc_end;
reg condition_reg;
reg condition;
wire uc_do_jmp;
wire uc_do_ret;
wire uc_halt_flag;
wire uc_halt;
reg halt_reg;
wire uc_ei;
wire uc_di;
reg inte_reg;
reg int_pending;
reg inta_reg;
wire clr_t1;
wire do_clr_t1;
wire clr_t2;
wire do_clr_t2;
wire [31:0] ucode;
reg [24:0] ucode_field2;
reg delayed_ei;
wire load_al;
wire load_addr;
wire load_t1;
wire load_t2;
wire mux_in;
wire load_do;
wire [1:0] rb_addr_sel;
wire [3:0] ra_field;
wire [7:0] rbank_data;
reg [7:0] alu_output;
wire [7:0] data_output;
reg [7:0] T1;
reg [7:0] T2;
wire [7:0] alu_input;
wire we_rb;
wire inhibit_pc_increment;
reg [3:0] rbank_rd_addr;
wire [3:0] rbank_wr_addr;
reg [7:0] DO;
reg [7:0] rbank[0:15];
reg [7:0] flag_reg;
wire [1:0] flag_pattern;
wire flag_s;
wire flag_z;
wire flag_p;
wire flag_cy;
wire flag_cy_1;
wire flag_cy_2;
wire do_cy_op;
wire do_cy_op_d;
wire do_cpc;
wire do_cpc_d;
wire do_daa;
wire clear_cy;
wire clear_ac;
wire set_ac;
wire flag_ac;
wire flag_aux_cy;
wire load_psw;
wire use_aux;
wire use_aux_cy;
reg reg_aux_cy;
wire aux_cy_in;
wire set_aux_cy;
wire set_aux;
wire [1:0] alu_fn;
wire use_logic;
wire [1:0] mux_fn;
wire use_psw;
wire [8:0] arith_op1;
wire [8:0] arith_op2;
wire [8:0] arith_op2_sgn;
wire [8:0] arith_res;
wire [7:0] arith_res8;
wire [8:0] daa_res;
reg [8:0] daa_res9;
wire daa_test1;
wire daa_test1a;
wire daa_test2;
wire [7:0] arith_daa_res;
wire cy_daa;
wire cy_in_sgn;
wire cy_in;
wire cy_in_gated;
wire cy_adder;
wire cy_arith;
wire cy_shifter;
reg [7:0] logic_res;
wire [7:0] shift_res;
wire [7:0] alu_mux1;
always @ (posedge clk)
begin
if (uc_decode)
IR <= data_in;
end
assign s_field = IR[2:0];
assign d_field = IR[5:3];
assign p_field = IR[5:4];
always @ (posedge clk)
do_reset <= reset;
assign uc_flags1 = ucode[31:29];
assign uc_flags2 = ucode[28:26];
assign uc_do_ret = ((uc_flags2 == 3'b011) && !do_reset) ? 1'b1 : 1'b0;
assign uc_jsr = ((uc_flags2 == 3'b010) && !do_reset) ? 1'b1 : 1'b0;
assign uc_tjsr = ((uc_flags2 == 3'b100) && !do_reset) ? 1'b1 : 1'b0;
assign uc_decode = ((uc_flags1 == 3'b001) && !do_reset) ? 1'b1 : 1'b0;
assign uc_end = (((uc_flags2 == 3'b001) || (uc_tjsr && !condition_reg)) && !do_reset) ? 1'b1 : 1'b0;
assign uc_halt_flag = (uc_flags1 == 3'b111) ? 1'b1 : 1'b0;
assign uc_halt = (uc_halt_flag && !inta_reg) ? 1'b1 : 1'b0;
assign uc_ei = (uc_flags1 == 3'b011) ? 1'b1 : 1'b0;
assign uc_di = ((uc_flags1 == 3'b010) || inta_reg) ? 1'b1 : 1'b0;
assign clr_t2 = (uc_flags2 == 3'b001) ? 1'b1 : 1'b0;
assign clr_t1 = (uc_flags1 == 3'b110) ? 1'b1 : 1'b0;
assign use_aux = (uc_flags1 == 3'b101) ? 1'b1 : 1'b0;
assign set_aux = (uc_flags2 == 3'b111) ? 1'b1 : 1'b0;
assign load_al = ucode[24];
assign load_addr = ucode[25];
assign do_cy_op_d = (ucode[5:2] == 4'b1011) ? 1'b1 : 1'b0;
assign do_cpc_d = ucode[0];
assign uc_do_jmp = uc_jsr | (uc_tjsr & condition_reg);
assign vma = load_addr;
assign fetch = ((uc_addr[7:4] == 4'b0) && load_addr) ? 1'b1 : 1'b0;
assign io = (uc_flags1 == 3'b100) ? 1'b1 : 1'b0;
assign rd = (uc_flags2 == 3'b101) ? 1'b1 : 1'b0;
assign wr = (uc_flags2 == 3'b110) ? 1'b1 : 1'b0;
assign uc_jmp_addr = {ucode[11:10], ucode[5:0]};
assign uc_addr_sel = {uc_do_ret, uc_do_jmp, uc_decode, uc_end};
assign addr_plus_1 = uc_addr + 8'd1;
always @ (*)
begin
case (uc_addr_sel)
4'b1000: next_uc_addr <= {1'b0, uc_ret_addr};
4'b0100: next_uc_addr <= {1'b0, uc_jmp_addr};
4'b0000: next_uc_addr <= {1'b0, addr_plus_1};
4'b0001: next_uc_addr <= {6'b0, uc_halt, 2'b11};
default: next_uc_addr <= {1'b1, data_in};
endcase
end
micro_rom rom
(
.clock(clk),
.uc_addr(next_uc_addr),
.uc_dout(ucode)
);
always @ (posedge clk)
begin
if (reset)
uc_addr <= 8'h0;
else
uc_addr <= next_uc_addr[7:0];
end
always @ (posedge clk)
begin
if (reset)
uc_ret_addr <= 8'h0;
else if (uc_do_jmp)
uc_ret_addr <= addr_plus_1;
end
assign alu_op = ucode[3:0];
always @ (posedge clk)
begin
ucode_field2 <= {do_cy_op_d, do_cpc_d, clr_t2, clr_t1,
set_aux, use_aux, rbank_rd_addr, ucode[14:4], alu_op};
end
always @ (posedge clk)
begin
if (reset || int_pending)
halt_reg <= 1'b0;
else if (uc_halt)
halt_reg <= 1'b1;
end
assign halt = halt_reg;
always @ (posedge clk)
begin
if (reset)
begin
inte_reg <= 1'b0;
delayed_ei <= 1'b0;
end
else
begin
if ((uc_di || uc_ei) && uc_end)
begin
delayed_ei <= uc_ei;
end
if (uc_end)
begin
if (uc_di)
inte_reg <= 1'b0;
else
inte_reg <= delayed_ei;
end
end
end
assign inte = inte_reg;
always @ (posedge clk)
begin
if (reset)
int_pending <= 1'b0;
else
begin
if (intr && inte_reg && !int_pending && !inta_reg)
int_pending <= 1'b1;
else if (inte_reg && uc_end)
int_pending <= 1'b0;
end
end
always @ (posedge clk)
begin
if (reset)
inta_reg <= 1'b0;
else if (int_pending && uc_end)
inta_reg <= 1'b1;
else if (uc_end && !uc_halt_flag)
inta_reg <= 1'b0;
end
assign inta = inta_reg;
assign ra_field = ucode[18:15];
assign load_t1 = ucode[23];
assign load_t2 = ucode[22];
assign mux_in = ucode[21];
assign rb_addr_sel = ucode[20:19];
assign load_do = ucode_field2[7];
assign set_aux_cy = ucode_field2[20];
assign do_clr_t1 = ucode_field2[21];
assign do_clr_t2 = ucode_field2[22];
always @ (posedge clk)
begin
if (reset || uc_decode || do_clr_t1)
T1 <= 8'h0;
else if (load_t1)
T1 <= alu_input;
end
always @ (posedge clk)
begin
if (reset || uc_decode || do_clr_t2)
T2 <= 8'h0;
else if (load_t2)
T2 <= alu_input;
end
assign alu_input = mux_in ? rbank_data : data_in;
assign rbh = (p_field == 2'b11) ? 1'b1 : 1'b0;
always @ (*)
begin
case (rb_addr_sel)
2'b00: rbank_rd_addr <= ra_field;
2'b01: rbank_rd_addr <= {1'b0, s_field};
2'b10: rbank_rd_addr <= {1'b0, d_field};
2'b11: rbank_rd_addr <= {rbh, p_field, ra_field[0]};
endcase
end
assign inhibit_pc_increment = (inta_reg && use_aux_cy && (rbank_wr_addr[3:1] == 3'b100)) ? 1'b1 : 1'b0;
assign we_rb = ucode_field2[6] & ~inhibit_pc_increment;
assign rbank_wr_addr = ucode_field2[18:15];
always @ (posedge clk)
begin
if (we_rb)
rbank[rbank_wr_addr] <= alu_output;
end
assign rbank_data = rbank[rbank_rd_addr];
assign use_psw = (ucode_field2[5:4] == 2'b11) ? 1'b1 : 1'b0;
assign data_output = use_psw ? flag_reg : alu_output;
always @ (posedge clk)
begin
if (load_do)
DO <= data_output;
end
assign alu_fn = ucode_field2[1:0];
assign use_logic = ucode_field2[2];
assign mux_fn = ucode_field2[4:3];
assign flag_pattern = ucode_field2[9:8];
assign use_aux_cy = ucode_field2[19];
assign do_cpc = ucode_field2[23];
assign do_cy_op = ucode_field2[24];
assign do_daa = (ucode_field2[5:2] == 4'b1010) ? 1'b1 : 1'b0;
assign clear_cy = ucode_field2[14];
assign clear_ac = (ucode_field2[14] && (ucode_field2[5:0] != 6'b000100)) ? 1'b1 : 1'b0;
assign set_ac = (ucode_field2[14] && (ucode_field2[5:0] == 6'b000100)) ? 1'b1 : 1'b0;
assign aux_cy_in = (!set_aux_cy) ? reg_aux_cy : 1'b1;
assign cy_in = (!use_aux_cy) ? flag_reg[0] : aux_cy_in;
assign cy_in_gated = cy_in & alu_fn[0];
assign arith_op1 = {1'b0, T2};
assign arith_op2 = {1'b0, T1};
assign arith_op2_sgn = (!alu_fn[1]) ? arith_op2 : ~arith_op2;
assign cy_in_sgn = (!alu_fn[1]) ? cy_in_gated : ~cy_in_gated;
assign arith_res = arith_op1 + arith_op2_sgn + cy_in_sgn;
assign arith_res8 = arith_res[7:0];
assign cy_adder = arith_res[8];
assign daa_test1a = arith_op2[3] & (arith_op2[2] | arith_op2[1] | arith_op2[0]);
assign daa_test1 = (flag_reg[4] || daa_test1a) ? 1'b1 : 1'b0;
always @ (posedge clk)
begin
if (reset)
daa_res9 <= 9'b0;
else if (daa_test1)
daa_res9 <= arith_op2 + 9'd6;
else
daa_res9 <= arith_op2;
end
assign daa_test2 = (flag_reg[0] || daa_test1a) ? 1'b1 : 1'b0;
assign daa_res = daa_test2 ? ({1'b0, daa_res9[7:0]} + 9'h60) : daa_res9;
assign cy_daa = daa_res[8];
assign arith_daa_res = do_daa ? daa_res[7:0] : arith_res8;
assign cy_arith = do_daa ? cy_daa : cy_adder;
always @ (*)
begin
case (alu_fn)
2'b00: logic_res <= T1 & T2;
2'b01: logic_res <= T1 ^ T2;
2'b10: logic_res <= T1 | T2;
2'b11: logic_res <= ~T1;
endcase
end
assign shift_res[6:1] = (!alu_fn[0]) ? T1[5:0] : T1[7:2];
assign shift_res[0] = (alu_fn == 2'b00) ? T1[7] :
(alu_fn == 2'b10) ? cy_in :
T1[1];
assign shift_res[7] = (alu_fn == 2'b01) ? T1[0] :
(alu_fn == 2'b11) ? cy_in :
T1[6];
assign cy_shifter = (!alu_fn[0]) ? T1[7] :
T1[0];
assign alu_mux1 = use_logic ? logic_res : shift_res;
always @ (*)
begin
case (mux_fn)
2'b00: alu_output <= alu_mux1;
2'b01: alu_output <= arith_daa_res;
2'b10: alu_output <= ~alu_mux1;
2'b11: alu_output <= {2'b0, d_field, 3'b0};
endcase
end
assign flag_s = alu_output[7];
assign flag_p = ~(^alu_output);
assign flag_z = (alu_output == 8'h0) ? 1'b1 : 1'b0;
assign flag_ac = set_ac ? 1'b1 :
clear_ac ? 1'b0 :
(arith_op1[4] ^ arith_op2_sgn[4] ^ alu_output[4]);
assign flag_cy_1 = clear_cy ? 1'b0 :
use_logic ? cy_arith :
cy_shifter;
assign flag_cy_2 = (!do_cpc) ? ~flag_reg[0] : 1'b1;
assign flag_cy = (!do_cy_op) ? flag_cy_1 : flag_cy_2;
assign flag_aux_cy = cy_adder;
always @ (posedge clk)
begin
if (reset || uc_decode)
reg_aux_cy <= 1'b1;
else
reg_aux_cy <= flag_aux_cy;
end
assign load_psw = (we_rb && (rbank_wr_addr == 4'b0110)) ? 1'b1 : 1'b0;
always @ (posedge clk)
begin
if (reset)
begin
flag_reg[7] <= 1'b0;
flag_reg[6] <= 1'b0;
flag_reg[5] <= 1'b0;
flag_reg[4] <= 1'b0;
flag_reg[3] <= 1'b0;
flag_reg[2] <= 1'b0;
flag_reg[1] <= 1'b1;
flag_reg[0] <= 1'b0;
end
else
begin
if (flag_pattern[1])
begin
if (load_psw)
begin
flag_reg[7] <= alu_output[7];
flag_reg[6] <= alu_output[6];
flag_reg[4] <= alu_output[4];
flag_reg[2] <= alu_output[2];
end
else
begin
flag_reg[7] <= flag_s;
flag_reg[6] <= flag_z;
flag_reg[4] <= flag_ac;
flag_reg[2] <= flag_p;
end
end
if (flag_pattern[0])
begin
if (load_psw)
flag_reg[0] <= alu_output[0];
else
flag_reg[0] <= flag_cy;
end
flag_reg[5] <= 1'b0;
flag_reg[3] <= 1'b0;
flag_reg[1] <= 1'b1;
end
end
always @ (*)
begin
case (d_field[2:0])
3'b000: condition <= ~flag_reg[6];
3'b001: condition <= flag_reg[6];
3'b010: condition <= ~flag_reg[0];
3'b011: condition <= flag_reg[0];
3'b100: condition <= ~flag_reg[2];
3'b101: condition <= flag_reg[2];
3'b110: condition <= ~flag_reg[7];
3'b111: condition <= flag_reg[7];
endcase
end
always @ (posedge clk)
begin
if (reset)
condition_reg <= 1'b0;
else
condition_reg <= condition;
end
always @ (posedge clk)
begin
if (reset)
addr_low <= 8'h0;
else if (load_al)
addr_low <= rbank_data;
end
assign addr_out = {rbank_data, addr_low};
assign data_out = DO;
endmodule | 0 |
141,891 | data/full_repos/permissive/96181301/quartus/lite8080/micro_rom.v | 96,181,301 | micro_rom.v | v | 553 | 90 | [] | [] | [] | [(9, 550)] | null | data/verilator_xmls/b25ef6fc-36c2-4424-9bc7-874e5b353a8c.xml | null | 312,627 | module | module micro_rom
(
clock,
uc_addr,
uc_dout
);
input clock;
input [8:0] uc_addr;
output [31:0] uc_dout;
reg [31:0] uc_dat, uc_dout;
always @ (uc_addr)
begin
case (uc_addr)
9'h000: uc_dat <= 32'b00000000000000000000000000000000;
9'h001: uc_dat <= 32'b00000000000001001000000001000100;
9'h002: uc_dat <= 32'b00000000000001000000000001000100;
9'h003: uc_dat <= 32'b10111101101001001000000001001101;
9'h004: uc_dat <= 32'b10110110101001000000000001001101;
9'h005: uc_dat <= 32'b00100000000000000000000000000000;
9'h006: uc_dat <= 32'b00000000000000000000000000000000;
9'h007: uc_dat <= 32'b11100100000000000000000000000000;
9'h008: uc_dat <= 32'b00000000101010000000000000000000;
9'h009: uc_dat <= 32'b00000100000100000000000001010111;
9'h00a: uc_dat <= 32'b00001000000000000000110000011001;
9'h00b: uc_dat <= 32'b00000100000100000000000001010111;
9'h00c: uc_dat <= 32'b00000000101010000000000010010111;
9'h00d: uc_dat <= 32'b00001000000000000000110000011100;
9'h00e: uc_dat <= 32'b00001000000000000000110000011111;
9'h00f: uc_dat <= 32'b00000100000100000000000001010111;
9'h010: uc_dat <= 32'b00001000000000000000110000011111;
9'h011: uc_dat <= 32'b00001000000000000000110000011100;
9'h012: uc_dat <= 32'b00001000000000000000110000011111;
9'h013: uc_dat <= 32'b00000000000110001000000001010111;
9'h014: uc_dat <= 32'b00001000000000000000110000011111;
9'h015: uc_dat <= 32'b00000100000110000000000001010111;
9'h016: uc_dat <= 32'b00001000000000000000110000101110;
9'h017: uc_dat <= 32'b00001000000000000000110000100010;
9'h018: uc_dat <= 32'b00000100000000111000000001010111;
9'h019: uc_dat <= 32'b00001000000000000000110000101110;
9'h01a: uc_dat <= 32'b00000000101000111000000010010111;
9'h01b: uc_dat <= 32'b00001000000000000000110000100101;
9'h01c: uc_dat <= 32'b00001000000000000000110000101110;
9'h01d: uc_dat <= 32'b10111101101001100000000001001101;
9'h01e: uc_dat <= 32'b10110110101001101000000001001101;
9'h01f: uc_dat <= 32'b00000000100000101000000001010111;
9'h020: uc_dat <= 32'b00001000000000000000110000100010;
9'h021: uc_dat <= 32'b00000100000000100000000001010111;
9'h022: uc_dat <= 32'b00001000000000000000110000101110;
9'h023: uc_dat <= 32'b00000000101000101000000010010111;
9'h024: uc_dat <= 32'b10111101101001100000000001001101;
9'h025: uc_dat <= 32'b10111010101001101000000001001101;
9'h026: uc_dat <= 32'b00000000101000100000000010010111;
9'h027: uc_dat <= 32'b00001000000000000000110000100101;
9'h028: uc_dat <= 32'b00001000000000000000110000101000;
9'h029: uc_dat <= 32'b00000100000000111000000001010111;
9'h02a: uc_dat <= 32'b00000000101000111000000010010111;
9'h02b: uc_dat <= 32'b00001000000000000000110000101011;
9'h02c: uc_dat <= 32'b00000000101000010000000000000000;
9'h02d: uc_dat <= 32'b00000000000001010000000001010111;
9'h02e: uc_dat <= 32'b00000000101000011000000000000000;
9'h02f: uc_dat <= 32'b00000000000001011000000001010111;
9'h030: uc_dat <= 32'b00000000101000100000000000000000;
9'h031: uc_dat <= 32'b00000000000000010000000001010111;
9'h032: uc_dat <= 32'b00000000101000101000000000000000;
9'h033: uc_dat <= 32'b00000000000000011000000001010111;
9'h034: uc_dat <= 32'b00000000101001010000000000000000;
9'h035: uc_dat <= 32'b00000000000000100000000001010111;
9'h036: uc_dat <= 32'b00000000101001011000000000000000;
9'h037: uc_dat <= 32'b00000100000000101000000001010111;
9'h038: uc_dat <= 32'b00001000000000000000110000011111;
9'h039: uc_dat <= 32'b00000100011000111000001101001100;
9'h03a: uc_dat <= 32'b00001000000000000000110000011111;
9'h03b: uc_dat <= 32'b00000100011000111000001101001101;
9'h03c: uc_dat <= 32'b00001000000000000000110000011111;
9'h03d: uc_dat <= 32'b00000100011000111000001101001110;
9'h03e: uc_dat <= 32'b00001000000000000000110000011111;
9'h03f: uc_dat <= 32'b00000100011000111000001101001111;
9'h040: uc_dat <= 32'b00001000000000000000110000011111;
9'h041: uc_dat <= 32'b00000100011000111100001101000100;
9'h042: uc_dat <= 32'b00001000000000000000110000011111;
9'h043: uc_dat <= 32'b00000100011000111100001101000101;
9'h044: uc_dat <= 32'b00001000000000000000110000011111;
9'h045: uc_dat <= 32'b00000100011000111100001101000110;
9'h046: uc_dat <= 32'b00001000000000000000110000011111;
9'h047: uc_dat <= 32'b00000100011000111000001110001110;
9'h048: uc_dat <= 32'b00000000101010000000000000000000;
9'h049: uc_dat <= 32'b00000100011000111000001101001100;
9'h04a: uc_dat <= 32'b00000000101010000000000000000000;
9'h04b: uc_dat <= 32'b00000100011000111000001101001101;
9'h04c: uc_dat <= 32'b00000000101010000000000000000000;
9'h04d: uc_dat <= 32'b00000100011000111000001101001110;
9'h04e: uc_dat <= 32'b00000000101010000000000000000000;
9'h04f: uc_dat <= 32'b00000100011000111000001101001111;
9'h050: uc_dat <= 32'b00000000101010000000000000000000;
9'h051: uc_dat <= 32'b00000100011000111100001101000100;
9'h052: uc_dat <= 32'b00000000101010000000000000000000;
9'h053: uc_dat <= 32'b00000100011000111100001101000101;
9'h054: uc_dat <= 32'b00000000101010000000000000000000;
9'h055: uc_dat <= 32'b00000100011000111100001101000110;
9'h056: uc_dat <= 32'b00000000101010000000000000000000;
9'h057: uc_dat <= 32'b00000100011000111000001110001110;
9'h058: uc_dat <= 32'b00001000000000000000110000011001;
9'h059: uc_dat <= 32'b00000100011000111000001101001100;
9'h05a: uc_dat <= 32'b00001000000000000000110000011001;
9'h05b: uc_dat <= 32'b00000100011000111000001101001101;
9'h05c: uc_dat <= 32'b00001000000000000000110000011001;
9'h05d: uc_dat <= 32'b00000100011000111000001101001110;
9'h05e: uc_dat <= 32'b00001000000000000000110000011001;
9'h05f: uc_dat <= 32'b00000100011000111000001101001111;
9'h060: uc_dat <= 32'b00001000000000000000110000011001;
9'h061: uc_dat <= 32'b00000100011000111100001101000100;
9'h062: uc_dat <= 32'b00001000000000000000110000011001;
9'h063: uc_dat <= 32'b00000100011000111100001101000101;
9'h064: uc_dat <= 32'b00001000000000000000110000011001;
9'h065: uc_dat <= 32'b00000100011000111100001101000110;
9'h066: uc_dat <= 32'b00001000000000000000110000011001;
9'h067: uc_dat <= 32'b00000100011000111000001110001110;
9'h068: uc_dat <= 32'b10111100101100000000001001001101;
9'h069: uc_dat <= 32'b00000100000000000000000000000000;
9'h06a: uc_dat <= 32'b00001000000000000000110000011001;
9'h06b: uc_dat <= 32'b10111100000000000000001010001101;
9'h06c: uc_dat <= 32'b00001000000000000000110000011100;
9'h06d: uc_dat <= 32'b10111100011100000000001001001111;
9'h06e: uc_dat <= 32'b00000100000000000000000000000000;
9'h06f: uc_dat <= 32'b00001000000000000000110000011001;
9'h070: uc_dat <= 32'b11000000000000000000000000000000;
9'h071: uc_dat <= 32'b10111100011001010000001010001111;
9'h072: uc_dat <= 32'b00001000000000000000110000011100;
9'h073: uc_dat <= 32'b10111100101110001000000001001101;
9'h074: uc_dat <= 32'b10100100101110000000000001001101;
9'h075: uc_dat <= 32'b10111100011110001000000001001111;
9'h076: uc_dat <= 32'b10100100011110000000000001001111;
9'h077: uc_dat <= 32'b00000000011110001000000000000000;
9'h078: uc_dat <= 32'b00000000101000101000000101001100;
9'h079: uc_dat <= 32'b00000000011110000000000000000000;
9'h07a: uc_dat <= 32'b00000100101000100000000101001101;
9'h07b: uc_dat <= 32'b00000000101000111000000010101000;
9'h07c: uc_dat <= 32'b00000100101000111000001101101000;
9'h07d: uc_dat <= 32'b00000100101000111000000101000000;
9'h07e: uc_dat <= 32'b00000100101000111000000101000001;
9'h07f: uc_dat <= 32'b00000100101000111000000101000010;
9'h080: uc_dat <= 32'b00000100101000111000000101000011;
9'h081: uc_dat <= 32'b00000100101000111000000001000111;
9'h082: uc_dat <= 32'b00000100000000000000000100101100;
9'h083: uc_dat <= 32'b00000100000000000000000100101101;
9'h084: uc_dat <= 32'b00001000000000000000110000101110;
9'h085: uc_dat <= 32'b00000000101001100000000000000000;
9'h086: uc_dat <= 32'b00000000000001001000000001010111;
9'h087: uc_dat <= 32'b00000000101001101000000000000000;
9'h088: uc_dat <= 32'b00000100000001000000000001010111;
9'h089: uc_dat <= 32'b00000100000000000000000000000000;
9'h08a: uc_dat <= 32'b00001000000000000000110000101110;
9'h08b: uc_dat <= 32'b00010000000000000000100000000101;
9'h08c: uc_dat <= 32'b00001000000000000000110000101110;
9'h08d: uc_dat <= 32'b11000000101001000000000010010111;
9'h08e: uc_dat <= 32'b00001000000000000000110000110100;
9'h08f: uc_dat <= 32'b11000000101001001000000010010111;
9'h090: uc_dat <= 32'b00001000000000000000110000110100;
9'h091: uc_dat <= 32'b00000000101001100000000000000000;
9'h092: uc_dat <= 32'b00000000000001001000000001010111;
9'h093: uc_dat <= 32'b00000000101001101000000000000000;
9'h094: uc_dat <= 32'b00000100000001000000000001010111;
9'h095: uc_dat <= 32'b00001000000000000000110000101110;
9'h096: uc_dat <= 32'b00010000000000000000100000001101;
9'h097: uc_dat <= 32'b00001000000000000000110000111001;
9'h098: uc_dat <= 32'b00000000000001001000000001010111;
9'h099: uc_dat <= 32'b00001000000000000000110000111001;
9'h09a: uc_dat <= 32'b00000100000001000000000001010111;
9'h09b: uc_dat <= 32'b00010000000000000000100000010111;
9'h09c: uc_dat <= 32'b11000000101001000000000010010111;
9'h09d: uc_dat <= 32'b00001000000000000000110000110100;
9'h09e: uc_dat <= 32'b11000000101001001000000010010111;
9'h09f: uc_dat <= 32'b00001000000000000000110000110100;
9'h0a0: uc_dat <= 32'b11000000000001001000000001011111;
9'h0a1: uc_dat <= 32'b00000100000001000000000001000100;
9'h0a2: uc_dat <= 32'b00000000101000101000000000000000;
9'h0a3: uc_dat <= 32'b00000000000001001000000001010111;
9'h0a4: uc_dat <= 32'b00000000101000100000000000000000;
9'h0a5: uc_dat <= 32'b00000100000001000000000001010111;
9'h0a6: uc_dat <= 32'b11000000101110000000000010010111;
9'h0a7: uc_dat <= 32'b00001000000000000000110000110100;
9'h0a8: uc_dat <= 32'b11000000101110001000000010010111;
9'h0a9: uc_dat <= 32'b00001000000000000000110000110100;
9'h0aa: uc_dat <= 32'b00000100000000000000000000000000;
9'h0ab: uc_dat <= 32'b11000000101000111000000010010111;
9'h0ac: uc_dat <= 32'b00001000000000000000110000110100;
9'h0ad: uc_dat <= 32'b11000000000000000000000010110000;
9'h0ae: uc_dat <= 32'b00001000000000000000110000110100;
9'h0af: uc_dat <= 32'b00000100000000000000000000000000;
9'h0b0: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b1: uc_dat <= 32'b00000000000110001000000001010111;
9'h0b2: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b3: uc_dat <= 32'b00000100000110000000000001010111;
9'h0b4: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b5: uc_dat <= 32'b00000000000000110000001101010111;
9'h0b6: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b7: uc_dat <= 32'b00000100000000111000000001010111;
9'h0b8: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b9: uc_dat <= 32'b00000000000001100000000001010111;
9'h0ba: uc_dat <= 32'b00001000000000000000110000111001;
9'h0bb: uc_dat <= 32'b00000000000001101000000001010111;
9'h0bc: uc_dat <= 32'b11000000101000100000000010010111;
9'h0bd: uc_dat <= 32'b00001000000000000000110000110100;
9'h0be: uc_dat <= 32'b11000000101000101000000010010111;
9'h0bf: uc_dat <= 32'b00001000000000000000110000110100;
9'h0c0: uc_dat <= 32'b00000000101001100000000000000000;
9'h0c1: uc_dat <= 32'b00000000000000101000000001010111;
9'h0c2: uc_dat <= 32'b00000000101001101000000000000000;
9'h0c3: uc_dat <= 32'b00000100000000100000000001010111;
9'h0c4: uc_dat <= 32'b00000000101000101000000000000000;
9'h0c5: uc_dat <= 32'b00000000000001111000000001010111;
9'h0c6: uc_dat <= 32'b00000000101000100000000000000000;
9'h0c7: uc_dat <= 32'b00000100000001110000000001010111;
9'h0c8: uc_dat <= 32'b01100100000000000000000000000000;
9'h0c9: uc_dat <= 32'b01000100000000000000000000000000;
9'h0ca: uc_dat <= 32'b00000000000001101000000001010111;
9'h0cb: uc_dat <= 32'b00001000000000000000110000011111;
9'h0cc: uc_dat <= 32'b00000000000001100000000001010111;
9'h0cd: uc_dat <= 32'b00000000000000000000000000000000;
9'h0ce: uc_dat <= 32'b00000001101001100000000000000000;
9'h0cf: uc_dat <= 32'b10010110101001101000000000000000;
9'h0d0: uc_dat <= 32'b00000100100000111000000001010111;
9'h0d1: uc_dat <= 32'b00000000000001101000000001010111;
9'h0d2: uc_dat <= 32'b00001000000000000000110000011111;
9'h0d3: uc_dat <= 32'b00000000000001100000000001010111;
9'h0d4: uc_dat <= 32'b00000000101000111000000010010111;
9'h0d5: uc_dat <= 32'b00000001101001100000000000000000;
9'h0d6: uc_dat <= 32'b10011010101001101000000000000000;
9'h0d7: uc_dat <= 32'b00000100000000000000000000000000;
9'h0d8: uc_dat <= 32'b11100100000000000000000000000000;
9'h0d9: uc_dat <= 32'b00000001101000101000000000000000;
9'h0da: uc_dat <= 32'b00010110101000100000000000000000;
9'h0db: uc_dat <= 32'b00001100100001010000000001010111;
9'h0dc: uc_dat <= 32'b00000001101000101000000000000000;
9'h0dd: uc_dat <= 32'b00011010101000100000000000000000;
9'h0de: uc_dat <= 32'b00000100000000000000000000000000;
9'h0df: uc_dat <= 32'b10111101101001001000000001001101;
9'h0e0: uc_dat <= 32'b10110110101001000000000001001101;
9'h0e1: uc_dat <= 32'b00001100100000000000000010010111;
9'h0e2: uc_dat <= 32'b00000001101001100000000000000000;
9'h0e3: uc_dat <= 32'b00010110101001101000000000000000;
9'h0e4: uc_dat <= 32'b00001100100000000000000000000000;
9'h0e5: uc_dat <= 32'b00000001101001100000000000000000;
9'h0e6: uc_dat <= 32'b00011010101001101000000000000000;
9'h0e7: uc_dat <= 32'b00000100000000000000000000000000;
9'h0e8: uc_dat <= 32'b00000001101110001000000000000000;
9'h0e9: uc_dat <= 32'b00010110101110000000000000000000;
9'h0ea: uc_dat <= 32'b00001100100000000000000000000000;
9'h0eb: uc_dat <= 32'b00000001101110001000000000000000;
9'h0ec: uc_dat <= 32'b00011010101110000000000000000000;
9'h0ed: uc_dat <= 32'b00000100000000000000000000000000;
9'h0ee: uc_dat <= 32'b10111101101001001000000001001101;
9'h0ef: uc_dat <= 32'b10110110101001000000000001001101;
9'h0f0: uc_dat <= 32'b00000000100001100000000001010111;
9'h0f1: uc_dat <= 32'b10111101101001001000000001001101;
9'h0f2: uc_dat <= 32'b10110110101001000000000001001101;
9'h0f3: uc_dat <= 32'b00001100100001101000000001010111;
9'h0f4: uc_dat <= 32'b10111100011001111000000001001111;
9'h0f5: uc_dat <= 32'b10100000011001110000000001001111;
9'h0f6: uc_dat <= 32'b00000001101001111000000000000000;
9'h0f7: uc_dat <= 32'b00011010101001110000000000000000;
9'h0f8: uc_dat <= 32'b00001100000000000000000000000000;
9'h0f9: uc_dat <= 32'b10111101101001111000000001001101;
9'h0fa: uc_dat <= 32'b10110110101001110000000001001101;
9'h0fb: uc_dat <= 32'b00001100100000000000000000000000;
9'h0fc: uc_dat <= 32'b00000100000000000000000000000000;
9'h0fd: uc_dat <= 32'b00000100000000000000000000000000;
9'h0fe: uc_dat <= 32'b00000100000000000000000000000000;
9'h0ff: uc_dat <= 32'b00000100000000000000000000000000;
9'h100: uc_dat <= 32'b00001000000000000000100000001001;
9'h101: uc_dat <= 32'b00001000000000000000000000010010;
9'h102: uc_dat <= 32'b00001000000000000000000000101010;
9'h103: uc_dat <= 32'b00001000000000000000010000110011;
9'h104: uc_dat <= 32'b00001000000000000000010000101000;
9'h105: uc_dat <= 32'b00001000000000000000010000101101;
9'h106: uc_dat <= 32'b00001000000000000000000000001110;
9'h107: uc_dat <= 32'b00001000000000000000010000111101;
9'h108: uc_dat <= 32'b00001000000000000000000000000000;
9'h109: uc_dat <= 32'b00001000000000000000010000110111;
9'h10a: uc_dat <= 32'b00001000000000000000000000101000;
9'h10b: uc_dat <= 32'b00001000000000000000010000110101;
9'h10c: uc_dat <= 32'b00001000000000000000010000101000;
9'h10d: uc_dat <= 32'b00001000000000000000010000101101;
9'h10e: uc_dat <= 32'b00001000000000000000000000001110;
9'h10f: uc_dat <= 32'b00001000000000000000010000111110;
9'h110: uc_dat <= 32'b00001000000000000000000000000000;
9'h111: uc_dat <= 32'b00001000000000000000000000010010;
9'h112: uc_dat <= 32'b00001000000000000000000000101010;
9'h113: uc_dat <= 32'b00001000000000000000010000110011;
9'h114: uc_dat <= 32'b00001000000000000000010000101000;
9'h115: uc_dat <= 32'b00001000000000000000010000101101;
9'h116: uc_dat <= 32'b00001000000000000000000000001110;
9'h117: uc_dat <= 32'b00001000000000000000010000111111;
9'h118: uc_dat <= 32'b00001000000000000000000000000000;
9'h119: uc_dat <= 32'b00001000000000000000010000110111;
9'h11a: uc_dat <= 32'b00001000000000000000000000101000;
9'h11b: uc_dat <= 32'b00001000000000000000010000110101;
9'h11c: uc_dat <= 32'b00001000000000000000010000101000;
9'h11d: uc_dat <= 32'b00001000000000000000010000101101;
9'h11e: uc_dat <= 32'b00001000000000000000000000001110;
9'h11f: uc_dat <= 32'b00001000000000000000100000000000;
9'h120: uc_dat <= 32'b00001000000000000000000000000000;
9'h121: uc_dat <= 32'b00001000000000000000000000010010;
9'h122: uc_dat <= 32'b00001000000000000000000000100010;
9'h123: uc_dat <= 32'b00001000000000000000010000110011;
9'h124: uc_dat <= 32'b00001000000000000000010000101000;
9'h125: uc_dat <= 32'b00001000000000000000010000101101;
9'h126: uc_dat <= 32'b00001000000000000000000000001110;
9'h127: uc_dat <= 32'b00001000000000000000010000111011;
9'h128: uc_dat <= 32'b00001000000000000000000000000000;
9'h129: uc_dat <= 32'b00001000000000000000010000110111;
9'h12a: uc_dat <= 32'b00001000000000000000000000011100;
9'h12b: uc_dat <= 32'b00001000000000000000010000110101;
9'h12c: uc_dat <= 32'b00001000000000000000010000101000;
9'h12d: uc_dat <= 32'b00001000000000000000010000101101;
9'h12e: uc_dat <= 32'b00001000000000000000000000001110;
9'h12f: uc_dat <= 32'b00001000000000000000100000000001;
9'h130: uc_dat <= 32'b00001000000000000000000000000000;
9'h131: uc_dat <= 32'b00001000000000000000000000010010;
9'h132: uc_dat <= 32'b00001000000000000000000000011001;
9'h133: uc_dat <= 32'b00001000000000000000010000110011;
9'h134: uc_dat <= 32'b00001000000000000000010000101010;
9'h135: uc_dat <= 32'b00001000000000000000010000101111;
9'h136: uc_dat <= 32'b00001000000000000000000000010000;
9'h137: uc_dat <= 32'b00001000000000000000100000000011;
9'h138: uc_dat <= 32'b00001000000000000000000000000000;
9'h139: uc_dat <= 32'b00001000000000000000010000110111;
9'h13a: uc_dat <= 32'b00001000000000000000000000010110;
9'h13b: uc_dat <= 32'b00001000000000000000010000110101;
9'h13c: uc_dat <= 32'b00001000000000000000010000101000;
9'h13d: uc_dat <= 32'b00001000000000000000010000101101;
9'h13e: uc_dat <= 32'b00001000000000000000000000001110;
9'h13f: uc_dat <= 32'b00001000000000000000100000000010;
9'h140: uc_dat <= 32'b00001000000000000000000000001000;
9'h141: uc_dat <= 32'b00001000000000000000000000001000;
9'h142: uc_dat <= 32'b00001000000000000000000000001000;
9'h143: uc_dat <= 32'b00001000000000000000000000001000;
9'h144: uc_dat <= 32'b00001000000000000000000000001000;
9'h145: uc_dat <= 32'b00001000000000000000000000001000;
9'h146: uc_dat <= 32'b00001000000000000000000000001010;
9'h147: uc_dat <= 32'b00001000000000000000000000001000;
9'h148: uc_dat <= 32'b00001000000000000000000000001000;
9'h149: uc_dat <= 32'b00001000000000000000000000001000;
9'h14a: uc_dat <= 32'b00001000000000000000000000001000;
9'h14b: uc_dat <= 32'b00001000000000000000000000001000;
9'h14c: uc_dat <= 32'b00001000000000000000000000001000;
9'h14d: uc_dat <= 32'b00001000000000000000000000001000;
9'h14e: uc_dat <= 32'b00001000000000000000000000001010;
9'h14f: uc_dat <= 32'b00001000000000000000000000001000;
9'h150: uc_dat <= 32'b00001000000000000000000000001000;
9'h151: uc_dat <= 32'b00001000000000000000000000001000;
9'h152: uc_dat <= 32'b00001000000000000000000000001000;
9'h153: uc_dat <= 32'b00001000000000000000000000001000;
9'h154: uc_dat <= 32'b00001000000000000000000000001000;
9'h155: uc_dat <= 32'b00001000000000000000000000001000;
9'h156: uc_dat <= 32'b00001000000000000000000000001010;
9'h157: uc_dat <= 32'b00001000000000000000000000001000;
9'h158: uc_dat <= 32'b00001000000000000000000000001000;
9'h159: uc_dat <= 32'b00001000000000000000000000001000;
9'h15a: uc_dat <= 32'b00001000000000000000000000001000;
9'h15b: uc_dat <= 32'b00001000000000000000000000001000;
9'h15c: uc_dat <= 32'b00001000000000000000000000001000;
9'h15d: uc_dat <= 32'b00001000000000000000000000001000;
9'h15e: uc_dat <= 32'b00001000000000000000000000001010;
9'h15f: uc_dat <= 32'b00001000000000000000000000001000;
9'h160: uc_dat <= 32'b00001000000000000000000000001000;
9'h161: uc_dat <= 32'b00001000000000000000000000001000;
9'h162: uc_dat <= 32'b00001000000000000000000000001000;
9'h163: uc_dat <= 32'b00001000000000000000000000001000;
9'h164: uc_dat <= 32'b00001000000000000000000000001000;
9'h165: uc_dat <= 32'b00001000000000000000000000001000;
9'h166: uc_dat <= 32'b00001000000000000000000000001010;
9'h167: uc_dat <= 32'b00001000000000000000000000001000;
9'h168: uc_dat <= 32'b00001000000000000000000000001000;
9'h169: uc_dat <= 32'b00001000000000000000000000001000;
9'h16a: uc_dat <= 32'b00001000000000000000000000001000;
9'h16b: uc_dat <= 32'b00001000000000000000000000001000;
9'h16c: uc_dat <= 32'b00001000000000000000000000001000;
9'h16d: uc_dat <= 32'b00001000000000000000000000001000;
9'h16e: uc_dat <= 32'b00001000000000000000000000001010;
9'h16f: uc_dat <= 32'b00001000000000000000000000001000;
9'h170: uc_dat <= 32'b00001000000000000000000000001100;
9'h171: uc_dat <= 32'b00001000000000000000000000001100;
9'h172: uc_dat <= 32'b00001000000000000000000000001100;
9'h173: uc_dat <= 32'b00001000000000000000000000001100;
9'h174: uc_dat <= 32'b00001000000000000000000000001100;
9'h175: uc_dat <= 32'b00001000000000000000000000001100;
9'h176: uc_dat <= 32'b00001000000000000000110000011000;
9'h177: uc_dat <= 32'b00001000000000000000000000001100;
9'h178: uc_dat <= 32'b00001000000000000000000000001000;
9'h179: uc_dat <= 32'b00001000000000000000000000001000;
9'h17a: uc_dat <= 32'b00001000000000000000000000001000;
9'h17b: uc_dat <= 32'b00001000000000000000000000001000;
9'h17c: uc_dat <= 32'b00001000000000000000000000001000;
9'h17d: uc_dat <= 32'b00001000000000000000000000001000;
9'h17e: uc_dat <= 32'b00001000000000000000000000001010;
9'h17f: uc_dat <= 32'b00001000000000000000000000001000;
9'h180: uc_dat <= 32'b00001000000000000000010000001000;
9'h181: uc_dat <= 32'b00001000000000000000010000001000;
9'h182: uc_dat <= 32'b00001000000000000000010000001000;
9'h183: uc_dat <= 32'b00001000000000000000010000001000;
9'h184: uc_dat <= 32'b00001000000000000000010000001000;
9'h185: uc_dat <= 32'b00001000000000000000010000001000;
9'h186: uc_dat <= 32'b00001000000000000000010000011000;
9'h187: uc_dat <= 32'b00001000000000000000010000001000;
9'h188: uc_dat <= 32'b00001000000000000000010000001010;
9'h189: uc_dat <= 32'b00001000000000000000010000001010;
9'h18a: uc_dat <= 32'b00001000000000000000010000001010;
9'h18b: uc_dat <= 32'b00001000000000000000010000001010;
9'h18c: uc_dat <= 32'b00001000000000000000010000001010;
9'h18d: uc_dat <= 32'b00001000000000000000010000001010;
9'h18e: uc_dat <= 32'b00001000000000000000010000011010;
9'h18f: uc_dat <= 32'b00001000000000000000010000001010;
9'h190: uc_dat <= 32'b00001000000000000000010000001100;
9'h191: uc_dat <= 32'b00001000000000000000010000001100;
9'h192: uc_dat <= 32'b00001000000000000000010000001100;
9'h193: uc_dat <= 32'b00001000000000000000010000001100;
9'h194: uc_dat <= 32'b00001000000000000000010000001100;
9'h195: uc_dat <= 32'b00001000000000000000010000001100;
9'h196: uc_dat <= 32'b00001000000000000000010000011100;
9'h197: uc_dat <= 32'b00001000000000000000010000001100;
9'h198: uc_dat <= 32'b00001000000000000000010000001110;
9'h199: uc_dat <= 32'b00001000000000000000010000001110;
9'h19a: uc_dat <= 32'b00001000000000000000010000001110;
9'h19b: uc_dat <= 32'b00001000000000000000010000001110;
9'h19c: uc_dat <= 32'b00001000000000000000010000001110;
9'h19d: uc_dat <= 32'b00001000000000000000010000001110;
9'h19e: uc_dat <= 32'b00001000000000000000010000011110;
9'h19f: uc_dat <= 32'b00001000000000000000010000001110;
9'h1a0: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a1: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a2: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a3: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a4: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a5: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a6: uc_dat <= 32'b00001000000000000000010000100000;
9'h1a7: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a8: uc_dat <= 32'b00001000000000000000010000010010;
9'h1a9: uc_dat <= 32'b00001000000000000000010000010010;
9'h1aa: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ab: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ac: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ad: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ae: uc_dat <= 32'b00001000000000000000010000100010;
9'h1af: uc_dat <= 32'b00001000000000000000010000010010;
9'h1b0: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b1: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b2: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b3: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b4: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b5: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b6: uc_dat <= 32'b00001000000000000000010000100100;
9'h1b7: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b8: uc_dat <= 32'b00001000000000000000010000010110;
9'h1b9: uc_dat <= 32'b00001000000000000000010000010110;
9'h1ba: uc_dat <= 32'b00001000000000000000010000010110;
9'h1bb: uc_dat <= 32'b00001000000000000000010000010110;
9'h1bc: uc_dat <= 32'b00001000000000000000010000010110;
9'h1bd: uc_dat <= 32'b00001000000000000000010000010110;
9'h1be: uc_dat <= 32'b00001000000000000000010000100110;
9'h1bf: uc_dat <= 32'b00001000000000000000010000010110;
9'h1c0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1c1: uc_dat <= 32'b00001000000000000000100000110000;
9'h1c2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1c3: uc_dat <= 32'b00001000000000000000100000000100;
9'h1c4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1c5: uc_dat <= 32'b00001000000000000000100000100110;
9'h1c6: uc_dat <= 32'b00001000000000000000000000111000;
9'h1c7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1c8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1c9: uc_dat <= 32'b00001000000000000000100000010111;
9'h1ca: uc_dat <= 32'b00001000000000000000100000001010;
9'h1cb: uc_dat <= 32'b00001000000000000000000000000000;
9'h1cc: uc_dat <= 32'b00001000000000000000100000010101;
9'h1cd: uc_dat <= 32'b00001000000000000000100000001100;
9'h1ce: uc_dat <= 32'b00001000000000000000000000111010;
9'h1cf: uc_dat <= 32'b00001000000000000000100000011100;
9'h1d0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1d1: uc_dat <= 32'b00001000000000000000100000110000;
9'h1d2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1d3: uc_dat <= 32'b00001000000000000000110000010001;
9'h1d4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1d5: uc_dat <= 32'b00001000000000000000100000100110;
9'h1d6: uc_dat <= 32'b00001000000000000000000000111100;
9'h1d7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1d8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1d9: uc_dat <= 32'b00001000000000000000000000000000;
9'h1da: uc_dat <= 32'b00001000000000000000100000001010;
9'h1db: uc_dat <= 32'b00001000000000000000110000001010;
9'h1dc: uc_dat <= 32'b00001000000000000000100000010101;
9'h1dd: uc_dat <= 32'b00001000000000000000000000000000;
9'h1de: uc_dat <= 32'b00001000000000000000000000111110;
9'h1df: uc_dat <= 32'b00001000000000000000100000011100;
9'h1e0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1e1: uc_dat <= 32'b00001000000000000000100000110000;
9'h1e2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1e3: uc_dat <= 32'b00001000000000000000100000111000;
9'h1e4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1e5: uc_dat <= 32'b00001000000000000000100000100110;
9'h1e6: uc_dat <= 32'b00001000000000000000010000000000;
9'h1e7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1e8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1e9: uc_dat <= 32'b00001000000000000000100000100010;
9'h1ea: uc_dat <= 32'b00001000000000000000100000001010;
9'h1eb: uc_dat <= 32'b00001000000000000000000000101100;
9'h1ec: uc_dat <= 32'b00001000000000000000100000010101;
9'h1ed: uc_dat <= 32'b00001000000000000000000000000000;
9'h1ee: uc_dat <= 32'b00001000000000000000010000000010;
9'h1ef: uc_dat <= 32'b00001000000000000000100000011100;
9'h1f0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1f1: uc_dat <= 32'b00001000000000000000100000110100;
9'h1f2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1f3: uc_dat <= 32'b00001000000000000000110000001001;
9'h1f4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1f5: uc_dat <= 32'b00001000000000000000100000101011;
9'h1f6: uc_dat <= 32'b00001000000000000000010000000100;
9'h1f7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1f8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1f9: uc_dat <= 32'b00001000000000000000110000000100;
9'h1fa: uc_dat <= 32'b00001000000000000000100000001010;
9'h1fb: uc_dat <= 32'b00001000000000000000110000001000;
9'h1fc: uc_dat <= 32'b00001000000000000000100000010101;
9'h1fd: uc_dat <= 32'b00001000000000000000000000000000;
9'h1fe: uc_dat <= 32'b00001000000000000000010000000110;
9'h1ff: uc_dat <= 32'b00001000000000000000100000011100;
endcase
end
always @ (posedge clock)
begin
uc_dout <= uc_dat;
end
endmodule | module micro_rom
(
clock,
uc_addr,
uc_dout
); |
input clock;
input [8:0] uc_addr;
output [31:0] uc_dout;
reg [31:0] uc_dat, uc_dout;
always @ (uc_addr)
begin
case (uc_addr)
9'h000: uc_dat <= 32'b00000000000000000000000000000000;
9'h001: uc_dat <= 32'b00000000000001001000000001000100;
9'h002: uc_dat <= 32'b00000000000001000000000001000100;
9'h003: uc_dat <= 32'b10111101101001001000000001001101;
9'h004: uc_dat <= 32'b10110110101001000000000001001101;
9'h005: uc_dat <= 32'b00100000000000000000000000000000;
9'h006: uc_dat <= 32'b00000000000000000000000000000000;
9'h007: uc_dat <= 32'b11100100000000000000000000000000;
9'h008: uc_dat <= 32'b00000000101010000000000000000000;
9'h009: uc_dat <= 32'b00000100000100000000000001010111;
9'h00a: uc_dat <= 32'b00001000000000000000110000011001;
9'h00b: uc_dat <= 32'b00000100000100000000000001010111;
9'h00c: uc_dat <= 32'b00000000101010000000000010010111;
9'h00d: uc_dat <= 32'b00001000000000000000110000011100;
9'h00e: uc_dat <= 32'b00001000000000000000110000011111;
9'h00f: uc_dat <= 32'b00000100000100000000000001010111;
9'h010: uc_dat <= 32'b00001000000000000000110000011111;
9'h011: uc_dat <= 32'b00001000000000000000110000011100;
9'h012: uc_dat <= 32'b00001000000000000000110000011111;
9'h013: uc_dat <= 32'b00000000000110001000000001010111;
9'h014: uc_dat <= 32'b00001000000000000000110000011111;
9'h015: uc_dat <= 32'b00000100000110000000000001010111;
9'h016: uc_dat <= 32'b00001000000000000000110000101110;
9'h017: uc_dat <= 32'b00001000000000000000110000100010;
9'h018: uc_dat <= 32'b00000100000000111000000001010111;
9'h019: uc_dat <= 32'b00001000000000000000110000101110;
9'h01a: uc_dat <= 32'b00000000101000111000000010010111;
9'h01b: uc_dat <= 32'b00001000000000000000110000100101;
9'h01c: uc_dat <= 32'b00001000000000000000110000101110;
9'h01d: uc_dat <= 32'b10111101101001100000000001001101;
9'h01e: uc_dat <= 32'b10110110101001101000000001001101;
9'h01f: uc_dat <= 32'b00000000100000101000000001010111;
9'h020: uc_dat <= 32'b00001000000000000000110000100010;
9'h021: uc_dat <= 32'b00000100000000100000000001010111;
9'h022: uc_dat <= 32'b00001000000000000000110000101110;
9'h023: uc_dat <= 32'b00000000101000101000000010010111;
9'h024: uc_dat <= 32'b10111101101001100000000001001101;
9'h025: uc_dat <= 32'b10111010101001101000000001001101;
9'h026: uc_dat <= 32'b00000000101000100000000010010111;
9'h027: uc_dat <= 32'b00001000000000000000110000100101;
9'h028: uc_dat <= 32'b00001000000000000000110000101000;
9'h029: uc_dat <= 32'b00000100000000111000000001010111;
9'h02a: uc_dat <= 32'b00000000101000111000000010010111;
9'h02b: uc_dat <= 32'b00001000000000000000110000101011;
9'h02c: uc_dat <= 32'b00000000101000010000000000000000;
9'h02d: uc_dat <= 32'b00000000000001010000000001010111;
9'h02e: uc_dat <= 32'b00000000101000011000000000000000;
9'h02f: uc_dat <= 32'b00000000000001011000000001010111;
9'h030: uc_dat <= 32'b00000000101000100000000000000000;
9'h031: uc_dat <= 32'b00000000000000010000000001010111;
9'h032: uc_dat <= 32'b00000000101000101000000000000000;
9'h033: uc_dat <= 32'b00000000000000011000000001010111;
9'h034: uc_dat <= 32'b00000000101001010000000000000000;
9'h035: uc_dat <= 32'b00000000000000100000000001010111;
9'h036: uc_dat <= 32'b00000000101001011000000000000000;
9'h037: uc_dat <= 32'b00000100000000101000000001010111;
9'h038: uc_dat <= 32'b00001000000000000000110000011111;
9'h039: uc_dat <= 32'b00000100011000111000001101001100;
9'h03a: uc_dat <= 32'b00001000000000000000110000011111;
9'h03b: uc_dat <= 32'b00000100011000111000001101001101;
9'h03c: uc_dat <= 32'b00001000000000000000110000011111;
9'h03d: uc_dat <= 32'b00000100011000111000001101001110;
9'h03e: uc_dat <= 32'b00001000000000000000110000011111;
9'h03f: uc_dat <= 32'b00000100011000111000001101001111;
9'h040: uc_dat <= 32'b00001000000000000000110000011111;
9'h041: uc_dat <= 32'b00000100011000111100001101000100;
9'h042: uc_dat <= 32'b00001000000000000000110000011111;
9'h043: uc_dat <= 32'b00000100011000111100001101000101;
9'h044: uc_dat <= 32'b00001000000000000000110000011111;
9'h045: uc_dat <= 32'b00000100011000111100001101000110;
9'h046: uc_dat <= 32'b00001000000000000000110000011111;
9'h047: uc_dat <= 32'b00000100011000111000001110001110;
9'h048: uc_dat <= 32'b00000000101010000000000000000000;
9'h049: uc_dat <= 32'b00000100011000111000001101001100;
9'h04a: uc_dat <= 32'b00000000101010000000000000000000;
9'h04b: uc_dat <= 32'b00000100011000111000001101001101;
9'h04c: uc_dat <= 32'b00000000101010000000000000000000;
9'h04d: uc_dat <= 32'b00000100011000111000001101001110;
9'h04e: uc_dat <= 32'b00000000101010000000000000000000;
9'h04f: uc_dat <= 32'b00000100011000111000001101001111;
9'h050: uc_dat <= 32'b00000000101010000000000000000000;
9'h051: uc_dat <= 32'b00000100011000111100001101000100;
9'h052: uc_dat <= 32'b00000000101010000000000000000000;
9'h053: uc_dat <= 32'b00000100011000111100001101000101;
9'h054: uc_dat <= 32'b00000000101010000000000000000000;
9'h055: uc_dat <= 32'b00000100011000111100001101000110;
9'h056: uc_dat <= 32'b00000000101010000000000000000000;
9'h057: uc_dat <= 32'b00000100011000111000001110001110;
9'h058: uc_dat <= 32'b00001000000000000000110000011001;
9'h059: uc_dat <= 32'b00000100011000111000001101001100;
9'h05a: uc_dat <= 32'b00001000000000000000110000011001;
9'h05b: uc_dat <= 32'b00000100011000111000001101001101;
9'h05c: uc_dat <= 32'b00001000000000000000110000011001;
9'h05d: uc_dat <= 32'b00000100011000111000001101001110;
9'h05e: uc_dat <= 32'b00001000000000000000110000011001;
9'h05f: uc_dat <= 32'b00000100011000111000001101001111;
9'h060: uc_dat <= 32'b00001000000000000000110000011001;
9'h061: uc_dat <= 32'b00000100011000111100001101000100;
9'h062: uc_dat <= 32'b00001000000000000000110000011001;
9'h063: uc_dat <= 32'b00000100011000111100001101000101;
9'h064: uc_dat <= 32'b00001000000000000000110000011001;
9'h065: uc_dat <= 32'b00000100011000111100001101000110;
9'h066: uc_dat <= 32'b00001000000000000000110000011001;
9'h067: uc_dat <= 32'b00000100011000111000001110001110;
9'h068: uc_dat <= 32'b10111100101100000000001001001101;
9'h069: uc_dat <= 32'b00000100000000000000000000000000;
9'h06a: uc_dat <= 32'b00001000000000000000110000011001;
9'h06b: uc_dat <= 32'b10111100000000000000001010001101;
9'h06c: uc_dat <= 32'b00001000000000000000110000011100;
9'h06d: uc_dat <= 32'b10111100011100000000001001001111;
9'h06e: uc_dat <= 32'b00000100000000000000000000000000;
9'h06f: uc_dat <= 32'b00001000000000000000110000011001;
9'h070: uc_dat <= 32'b11000000000000000000000000000000;
9'h071: uc_dat <= 32'b10111100011001010000001010001111;
9'h072: uc_dat <= 32'b00001000000000000000110000011100;
9'h073: uc_dat <= 32'b10111100101110001000000001001101;
9'h074: uc_dat <= 32'b10100100101110000000000001001101;
9'h075: uc_dat <= 32'b10111100011110001000000001001111;
9'h076: uc_dat <= 32'b10100100011110000000000001001111;
9'h077: uc_dat <= 32'b00000000011110001000000000000000;
9'h078: uc_dat <= 32'b00000000101000101000000101001100;
9'h079: uc_dat <= 32'b00000000011110000000000000000000;
9'h07a: uc_dat <= 32'b00000100101000100000000101001101;
9'h07b: uc_dat <= 32'b00000000101000111000000010101000;
9'h07c: uc_dat <= 32'b00000100101000111000001101101000;
9'h07d: uc_dat <= 32'b00000100101000111000000101000000;
9'h07e: uc_dat <= 32'b00000100101000111000000101000001;
9'h07f: uc_dat <= 32'b00000100101000111000000101000010;
9'h080: uc_dat <= 32'b00000100101000111000000101000011;
9'h081: uc_dat <= 32'b00000100101000111000000001000111;
9'h082: uc_dat <= 32'b00000100000000000000000100101100;
9'h083: uc_dat <= 32'b00000100000000000000000100101101;
9'h084: uc_dat <= 32'b00001000000000000000110000101110;
9'h085: uc_dat <= 32'b00000000101001100000000000000000;
9'h086: uc_dat <= 32'b00000000000001001000000001010111;
9'h087: uc_dat <= 32'b00000000101001101000000000000000;
9'h088: uc_dat <= 32'b00000100000001000000000001010111;
9'h089: uc_dat <= 32'b00000100000000000000000000000000;
9'h08a: uc_dat <= 32'b00001000000000000000110000101110;
9'h08b: uc_dat <= 32'b00010000000000000000100000000101;
9'h08c: uc_dat <= 32'b00001000000000000000110000101110;
9'h08d: uc_dat <= 32'b11000000101001000000000010010111;
9'h08e: uc_dat <= 32'b00001000000000000000110000110100;
9'h08f: uc_dat <= 32'b11000000101001001000000010010111;
9'h090: uc_dat <= 32'b00001000000000000000110000110100;
9'h091: uc_dat <= 32'b00000000101001100000000000000000;
9'h092: uc_dat <= 32'b00000000000001001000000001010111;
9'h093: uc_dat <= 32'b00000000101001101000000000000000;
9'h094: uc_dat <= 32'b00000100000001000000000001010111;
9'h095: uc_dat <= 32'b00001000000000000000110000101110;
9'h096: uc_dat <= 32'b00010000000000000000100000001101;
9'h097: uc_dat <= 32'b00001000000000000000110000111001;
9'h098: uc_dat <= 32'b00000000000001001000000001010111;
9'h099: uc_dat <= 32'b00001000000000000000110000111001;
9'h09a: uc_dat <= 32'b00000100000001000000000001010111;
9'h09b: uc_dat <= 32'b00010000000000000000100000010111;
9'h09c: uc_dat <= 32'b11000000101001000000000010010111;
9'h09d: uc_dat <= 32'b00001000000000000000110000110100;
9'h09e: uc_dat <= 32'b11000000101001001000000010010111;
9'h09f: uc_dat <= 32'b00001000000000000000110000110100;
9'h0a0: uc_dat <= 32'b11000000000001001000000001011111;
9'h0a1: uc_dat <= 32'b00000100000001000000000001000100;
9'h0a2: uc_dat <= 32'b00000000101000101000000000000000;
9'h0a3: uc_dat <= 32'b00000000000001001000000001010111;
9'h0a4: uc_dat <= 32'b00000000101000100000000000000000;
9'h0a5: uc_dat <= 32'b00000100000001000000000001010111;
9'h0a6: uc_dat <= 32'b11000000101110000000000010010111;
9'h0a7: uc_dat <= 32'b00001000000000000000110000110100;
9'h0a8: uc_dat <= 32'b11000000101110001000000010010111;
9'h0a9: uc_dat <= 32'b00001000000000000000110000110100;
9'h0aa: uc_dat <= 32'b00000100000000000000000000000000;
9'h0ab: uc_dat <= 32'b11000000101000111000000010010111;
9'h0ac: uc_dat <= 32'b00001000000000000000110000110100;
9'h0ad: uc_dat <= 32'b11000000000000000000000010110000;
9'h0ae: uc_dat <= 32'b00001000000000000000110000110100;
9'h0af: uc_dat <= 32'b00000100000000000000000000000000;
9'h0b0: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b1: uc_dat <= 32'b00000000000110001000000001010111;
9'h0b2: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b3: uc_dat <= 32'b00000100000110000000000001010111;
9'h0b4: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b5: uc_dat <= 32'b00000000000000110000001101010111;
9'h0b6: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b7: uc_dat <= 32'b00000100000000111000000001010111;
9'h0b8: uc_dat <= 32'b00001000000000000000110000111001;
9'h0b9: uc_dat <= 32'b00000000000001100000000001010111;
9'h0ba: uc_dat <= 32'b00001000000000000000110000111001;
9'h0bb: uc_dat <= 32'b00000000000001101000000001010111;
9'h0bc: uc_dat <= 32'b11000000101000100000000010010111;
9'h0bd: uc_dat <= 32'b00001000000000000000110000110100;
9'h0be: uc_dat <= 32'b11000000101000101000000010010111;
9'h0bf: uc_dat <= 32'b00001000000000000000110000110100;
9'h0c0: uc_dat <= 32'b00000000101001100000000000000000;
9'h0c1: uc_dat <= 32'b00000000000000101000000001010111;
9'h0c2: uc_dat <= 32'b00000000101001101000000000000000;
9'h0c3: uc_dat <= 32'b00000100000000100000000001010111;
9'h0c4: uc_dat <= 32'b00000000101000101000000000000000;
9'h0c5: uc_dat <= 32'b00000000000001111000000001010111;
9'h0c6: uc_dat <= 32'b00000000101000100000000000000000;
9'h0c7: uc_dat <= 32'b00000100000001110000000001010111;
9'h0c8: uc_dat <= 32'b01100100000000000000000000000000;
9'h0c9: uc_dat <= 32'b01000100000000000000000000000000;
9'h0ca: uc_dat <= 32'b00000000000001101000000001010111;
9'h0cb: uc_dat <= 32'b00001000000000000000110000011111;
9'h0cc: uc_dat <= 32'b00000000000001100000000001010111;
9'h0cd: uc_dat <= 32'b00000000000000000000000000000000;
9'h0ce: uc_dat <= 32'b00000001101001100000000000000000;
9'h0cf: uc_dat <= 32'b10010110101001101000000000000000;
9'h0d0: uc_dat <= 32'b00000100100000111000000001010111;
9'h0d1: uc_dat <= 32'b00000000000001101000000001010111;
9'h0d2: uc_dat <= 32'b00001000000000000000110000011111;
9'h0d3: uc_dat <= 32'b00000000000001100000000001010111;
9'h0d4: uc_dat <= 32'b00000000101000111000000010010111;
9'h0d5: uc_dat <= 32'b00000001101001100000000000000000;
9'h0d6: uc_dat <= 32'b10011010101001101000000000000000;
9'h0d7: uc_dat <= 32'b00000100000000000000000000000000;
9'h0d8: uc_dat <= 32'b11100100000000000000000000000000;
9'h0d9: uc_dat <= 32'b00000001101000101000000000000000;
9'h0da: uc_dat <= 32'b00010110101000100000000000000000;
9'h0db: uc_dat <= 32'b00001100100001010000000001010111;
9'h0dc: uc_dat <= 32'b00000001101000101000000000000000;
9'h0dd: uc_dat <= 32'b00011010101000100000000000000000;
9'h0de: uc_dat <= 32'b00000100000000000000000000000000;
9'h0df: uc_dat <= 32'b10111101101001001000000001001101;
9'h0e0: uc_dat <= 32'b10110110101001000000000001001101;
9'h0e1: uc_dat <= 32'b00001100100000000000000010010111;
9'h0e2: uc_dat <= 32'b00000001101001100000000000000000;
9'h0e3: uc_dat <= 32'b00010110101001101000000000000000;
9'h0e4: uc_dat <= 32'b00001100100000000000000000000000;
9'h0e5: uc_dat <= 32'b00000001101001100000000000000000;
9'h0e6: uc_dat <= 32'b00011010101001101000000000000000;
9'h0e7: uc_dat <= 32'b00000100000000000000000000000000;
9'h0e8: uc_dat <= 32'b00000001101110001000000000000000;
9'h0e9: uc_dat <= 32'b00010110101110000000000000000000;
9'h0ea: uc_dat <= 32'b00001100100000000000000000000000;
9'h0eb: uc_dat <= 32'b00000001101110001000000000000000;
9'h0ec: uc_dat <= 32'b00011010101110000000000000000000;
9'h0ed: uc_dat <= 32'b00000100000000000000000000000000;
9'h0ee: uc_dat <= 32'b10111101101001001000000001001101;
9'h0ef: uc_dat <= 32'b10110110101001000000000001001101;
9'h0f0: uc_dat <= 32'b00000000100001100000000001010111;
9'h0f1: uc_dat <= 32'b10111101101001001000000001001101;
9'h0f2: uc_dat <= 32'b10110110101001000000000001001101;
9'h0f3: uc_dat <= 32'b00001100100001101000000001010111;
9'h0f4: uc_dat <= 32'b10111100011001111000000001001111;
9'h0f5: uc_dat <= 32'b10100000011001110000000001001111;
9'h0f6: uc_dat <= 32'b00000001101001111000000000000000;
9'h0f7: uc_dat <= 32'b00011010101001110000000000000000;
9'h0f8: uc_dat <= 32'b00001100000000000000000000000000;
9'h0f9: uc_dat <= 32'b10111101101001111000000001001101;
9'h0fa: uc_dat <= 32'b10110110101001110000000001001101;
9'h0fb: uc_dat <= 32'b00001100100000000000000000000000;
9'h0fc: uc_dat <= 32'b00000100000000000000000000000000;
9'h0fd: uc_dat <= 32'b00000100000000000000000000000000;
9'h0fe: uc_dat <= 32'b00000100000000000000000000000000;
9'h0ff: uc_dat <= 32'b00000100000000000000000000000000;
9'h100: uc_dat <= 32'b00001000000000000000100000001001;
9'h101: uc_dat <= 32'b00001000000000000000000000010010;
9'h102: uc_dat <= 32'b00001000000000000000000000101010;
9'h103: uc_dat <= 32'b00001000000000000000010000110011;
9'h104: uc_dat <= 32'b00001000000000000000010000101000;
9'h105: uc_dat <= 32'b00001000000000000000010000101101;
9'h106: uc_dat <= 32'b00001000000000000000000000001110;
9'h107: uc_dat <= 32'b00001000000000000000010000111101;
9'h108: uc_dat <= 32'b00001000000000000000000000000000;
9'h109: uc_dat <= 32'b00001000000000000000010000110111;
9'h10a: uc_dat <= 32'b00001000000000000000000000101000;
9'h10b: uc_dat <= 32'b00001000000000000000010000110101;
9'h10c: uc_dat <= 32'b00001000000000000000010000101000;
9'h10d: uc_dat <= 32'b00001000000000000000010000101101;
9'h10e: uc_dat <= 32'b00001000000000000000000000001110;
9'h10f: uc_dat <= 32'b00001000000000000000010000111110;
9'h110: uc_dat <= 32'b00001000000000000000000000000000;
9'h111: uc_dat <= 32'b00001000000000000000000000010010;
9'h112: uc_dat <= 32'b00001000000000000000000000101010;
9'h113: uc_dat <= 32'b00001000000000000000010000110011;
9'h114: uc_dat <= 32'b00001000000000000000010000101000;
9'h115: uc_dat <= 32'b00001000000000000000010000101101;
9'h116: uc_dat <= 32'b00001000000000000000000000001110;
9'h117: uc_dat <= 32'b00001000000000000000010000111111;
9'h118: uc_dat <= 32'b00001000000000000000000000000000;
9'h119: uc_dat <= 32'b00001000000000000000010000110111;
9'h11a: uc_dat <= 32'b00001000000000000000000000101000;
9'h11b: uc_dat <= 32'b00001000000000000000010000110101;
9'h11c: uc_dat <= 32'b00001000000000000000010000101000;
9'h11d: uc_dat <= 32'b00001000000000000000010000101101;
9'h11e: uc_dat <= 32'b00001000000000000000000000001110;
9'h11f: uc_dat <= 32'b00001000000000000000100000000000;
9'h120: uc_dat <= 32'b00001000000000000000000000000000;
9'h121: uc_dat <= 32'b00001000000000000000000000010010;
9'h122: uc_dat <= 32'b00001000000000000000000000100010;
9'h123: uc_dat <= 32'b00001000000000000000010000110011;
9'h124: uc_dat <= 32'b00001000000000000000010000101000;
9'h125: uc_dat <= 32'b00001000000000000000010000101101;
9'h126: uc_dat <= 32'b00001000000000000000000000001110;
9'h127: uc_dat <= 32'b00001000000000000000010000111011;
9'h128: uc_dat <= 32'b00001000000000000000000000000000;
9'h129: uc_dat <= 32'b00001000000000000000010000110111;
9'h12a: uc_dat <= 32'b00001000000000000000000000011100;
9'h12b: uc_dat <= 32'b00001000000000000000010000110101;
9'h12c: uc_dat <= 32'b00001000000000000000010000101000;
9'h12d: uc_dat <= 32'b00001000000000000000010000101101;
9'h12e: uc_dat <= 32'b00001000000000000000000000001110;
9'h12f: uc_dat <= 32'b00001000000000000000100000000001;
9'h130: uc_dat <= 32'b00001000000000000000000000000000;
9'h131: uc_dat <= 32'b00001000000000000000000000010010;
9'h132: uc_dat <= 32'b00001000000000000000000000011001;
9'h133: uc_dat <= 32'b00001000000000000000010000110011;
9'h134: uc_dat <= 32'b00001000000000000000010000101010;
9'h135: uc_dat <= 32'b00001000000000000000010000101111;
9'h136: uc_dat <= 32'b00001000000000000000000000010000;
9'h137: uc_dat <= 32'b00001000000000000000100000000011;
9'h138: uc_dat <= 32'b00001000000000000000000000000000;
9'h139: uc_dat <= 32'b00001000000000000000010000110111;
9'h13a: uc_dat <= 32'b00001000000000000000000000010110;
9'h13b: uc_dat <= 32'b00001000000000000000010000110101;
9'h13c: uc_dat <= 32'b00001000000000000000010000101000;
9'h13d: uc_dat <= 32'b00001000000000000000010000101101;
9'h13e: uc_dat <= 32'b00001000000000000000000000001110;
9'h13f: uc_dat <= 32'b00001000000000000000100000000010;
9'h140: uc_dat <= 32'b00001000000000000000000000001000;
9'h141: uc_dat <= 32'b00001000000000000000000000001000;
9'h142: uc_dat <= 32'b00001000000000000000000000001000;
9'h143: uc_dat <= 32'b00001000000000000000000000001000;
9'h144: uc_dat <= 32'b00001000000000000000000000001000;
9'h145: uc_dat <= 32'b00001000000000000000000000001000;
9'h146: uc_dat <= 32'b00001000000000000000000000001010;
9'h147: uc_dat <= 32'b00001000000000000000000000001000;
9'h148: uc_dat <= 32'b00001000000000000000000000001000;
9'h149: uc_dat <= 32'b00001000000000000000000000001000;
9'h14a: uc_dat <= 32'b00001000000000000000000000001000;
9'h14b: uc_dat <= 32'b00001000000000000000000000001000;
9'h14c: uc_dat <= 32'b00001000000000000000000000001000;
9'h14d: uc_dat <= 32'b00001000000000000000000000001000;
9'h14e: uc_dat <= 32'b00001000000000000000000000001010;
9'h14f: uc_dat <= 32'b00001000000000000000000000001000;
9'h150: uc_dat <= 32'b00001000000000000000000000001000;
9'h151: uc_dat <= 32'b00001000000000000000000000001000;
9'h152: uc_dat <= 32'b00001000000000000000000000001000;
9'h153: uc_dat <= 32'b00001000000000000000000000001000;
9'h154: uc_dat <= 32'b00001000000000000000000000001000;
9'h155: uc_dat <= 32'b00001000000000000000000000001000;
9'h156: uc_dat <= 32'b00001000000000000000000000001010;
9'h157: uc_dat <= 32'b00001000000000000000000000001000;
9'h158: uc_dat <= 32'b00001000000000000000000000001000;
9'h159: uc_dat <= 32'b00001000000000000000000000001000;
9'h15a: uc_dat <= 32'b00001000000000000000000000001000;
9'h15b: uc_dat <= 32'b00001000000000000000000000001000;
9'h15c: uc_dat <= 32'b00001000000000000000000000001000;
9'h15d: uc_dat <= 32'b00001000000000000000000000001000;
9'h15e: uc_dat <= 32'b00001000000000000000000000001010;
9'h15f: uc_dat <= 32'b00001000000000000000000000001000;
9'h160: uc_dat <= 32'b00001000000000000000000000001000;
9'h161: uc_dat <= 32'b00001000000000000000000000001000;
9'h162: uc_dat <= 32'b00001000000000000000000000001000;
9'h163: uc_dat <= 32'b00001000000000000000000000001000;
9'h164: uc_dat <= 32'b00001000000000000000000000001000;
9'h165: uc_dat <= 32'b00001000000000000000000000001000;
9'h166: uc_dat <= 32'b00001000000000000000000000001010;
9'h167: uc_dat <= 32'b00001000000000000000000000001000;
9'h168: uc_dat <= 32'b00001000000000000000000000001000;
9'h169: uc_dat <= 32'b00001000000000000000000000001000;
9'h16a: uc_dat <= 32'b00001000000000000000000000001000;
9'h16b: uc_dat <= 32'b00001000000000000000000000001000;
9'h16c: uc_dat <= 32'b00001000000000000000000000001000;
9'h16d: uc_dat <= 32'b00001000000000000000000000001000;
9'h16e: uc_dat <= 32'b00001000000000000000000000001010;
9'h16f: uc_dat <= 32'b00001000000000000000000000001000;
9'h170: uc_dat <= 32'b00001000000000000000000000001100;
9'h171: uc_dat <= 32'b00001000000000000000000000001100;
9'h172: uc_dat <= 32'b00001000000000000000000000001100;
9'h173: uc_dat <= 32'b00001000000000000000000000001100;
9'h174: uc_dat <= 32'b00001000000000000000000000001100;
9'h175: uc_dat <= 32'b00001000000000000000000000001100;
9'h176: uc_dat <= 32'b00001000000000000000110000011000;
9'h177: uc_dat <= 32'b00001000000000000000000000001100;
9'h178: uc_dat <= 32'b00001000000000000000000000001000;
9'h179: uc_dat <= 32'b00001000000000000000000000001000;
9'h17a: uc_dat <= 32'b00001000000000000000000000001000;
9'h17b: uc_dat <= 32'b00001000000000000000000000001000;
9'h17c: uc_dat <= 32'b00001000000000000000000000001000;
9'h17d: uc_dat <= 32'b00001000000000000000000000001000;
9'h17e: uc_dat <= 32'b00001000000000000000000000001010;
9'h17f: uc_dat <= 32'b00001000000000000000000000001000;
9'h180: uc_dat <= 32'b00001000000000000000010000001000;
9'h181: uc_dat <= 32'b00001000000000000000010000001000;
9'h182: uc_dat <= 32'b00001000000000000000010000001000;
9'h183: uc_dat <= 32'b00001000000000000000010000001000;
9'h184: uc_dat <= 32'b00001000000000000000010000001000;
9'h185: uc_dat <= 32'b00001000000000000000010000001000;
9'h186: uc_dat <= 32'b00001000000000000000010000011000;
9'h187: uc_dat <= 32'b00001000000000000000010000001000;
9'h188: uc_dat <= 32'b00001000000000000000010000001010;
9'h189: uc_dat <= 32'b00001000000000000000010000001010;
9'h18a: uc_dat <= 32'b00001000000000000000010000001010;
9'h18b: uc_dat <= 32'b00001000000000000000010000001010;
9'h18c: uc_dat <= 32'b00001000000000000000010000001010;
9'h18d: uc_dat <= 32'b00001000000000000000010000001010;
9'h18e: uc_dat <= 32'b00001000000000000000010000011010;
9'h18f: uc_dat <= 32'b00001000000000000000010000001010;
9'h190: uc_dat <= 32'b00001000000000000000010000001100;
9'h191: uc_dat <= 32'b00001000000000000000010000001100;
9'h192: uc_dat <= 32'b00001000000000000000010000001100;
9'h193: uc_dat <= 32'b00001000000000000000010000001100;
9'h194: uc_dat <= 32'b00001000000000000000010000001100;
9'h195: uc_dat <= 32'b00001000000000000000010000001100;
9'h196: uc_dat <= 32'b00001000000000000000010000011100;
9'h197: uc_dat <= 32'b00001000000000000000010000001100;
9'h198: uc_dat <= 32'b00001000000000000000010000001110;
9'h199: uc_dat <= 32'b00001000000000000000010000001110;
9'h19a: uc_dat <= 32'b00001000000000000000010000001110;
9'h19b: uc_dat <= 32'b00001000000000000000010000001110;
9'h19c: uc_dat <= 32'b00001000000000000000010000001110;
9'h19d: uc_dat <= 32'b00001000000000000000010000001110;
9'h19e: uc_dat <= 32'b00001000000000000000010000011110;
9'h19f: uc_dat <= 32'b00001000000000000000010000001110;
9'h1a0: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a1: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a2: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a3: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a4: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a5: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a6: uc_dat <= 32'b00001000000000000000010000100000;
9'h1a7: uc_dat <= 32'b00001000000000000000010000010000;
9'h1a8: uc_dat <= 32'b00001000000000000000010000010010;
9'h1a9: uc_dat <= 32'b00001000000000000000010000010010;
9'h1aa: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ab: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ac: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ad: uc_dat <= 32'b00001000000000000000010000010010;
9'h1ae: uc_dat <= 32'b00001000000000000000010000100010;
9'h1af: uc_dat <= 32'b00001000000000000000010000010010;
9'h1b0: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b1: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b2: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b3: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b4: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b5: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b6: uc_dat <= 32'b00001000000000000000010000100100;
9'h1b7: uc_dat <= 32'b00001000000000000000010000010100;
9'h1b8: uc_dat <= 32'b00001000000000000000010000010110;
9'h1b9: uc_dat <= 32'b00001000000000000000010000010110;
9'h1ba: uc_dat <= 32'b00001000000000000000010000010110;
9'h1bb: uc_dat <= 32'b00001000000000000000010000010110;
9'h1bc: uc_dat <= 32'b00001000000000000000010000010110;
9'h1bd: uc_dat <= 32'b00001000000000000000010000010110;
9'h1be: uc_dat <= 32'b00001000000000000000010000100110;
9'h1bf: uc_dat <= 32'b00001000000000000000010000010110;
9'h1c0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1c1: uc_dat <= 32'b00001000000000000000100000110000;
9'h1c2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1c3: uc_dat <= 32'b00001000000000000000100000000100;
9'h1c4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1c5: uc_dat <= 32'b00001000000000000000100000100110;
9'h1c6: uc_dat <= 32'b00001000000000000000000000111000;
9'h1c7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1c8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1c9: uc_dat <= 32'b00001000000000000000100000010111;
9'h1ca: uc_dat <= 32'b00001000000000000000100000001010;
9'h1cb: uc_dat <= 32'b00001000000000000000000000000000;
9'h1cc: uc_dat <= 32'b00001000000000000000100000010101;
9'h1cd: uc_dat <= 32'b00001000000000000000100000001100;
9'h1ce: uc_dat <= 32'b00001000000000000000000000111010;
9'h1cf: uc_dat <= 32'b00001000000000000000100000011100;
9'h1d0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1d1: uc_dat <= 32'b00001000000000000000100000110000;
9'h1d2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1d3: uc_dat <= 32'b00001000000000000000110000010001;
9'h1d4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1d5: uc_dat <= 32'b00001000000000000000100000100110;
9'h1d6: uc_dat <= 32'b00001000000000000000000000111100;
9'h1d7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1d8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1d9: uc_dat <= 32'b00001000000000000000000000000000;
9'h1da: uc_dat <= 32'b00001000000000000000100000001010;
9'h1db: uc_dat <= 32'b00001000000000000000110000001010;
9'h1dc: uc_dat <= 32'b00001000000000000000100000010101;
9'h1dd: uc_dat <= 32'b00001000000000000000000000000000;
9'h1de: uc_dat <= 32'b00001000000000000000000000111110;
9'h1df: uc_dat <= 32'b00001000000000000000100000011100;
9'h1e0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1e1: uc_dat <= 32'b00001000000000000000100000110000;
9'h1e2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1e3: uc_dat <= 32'b00001000000000000000100000111000;
9'h1e4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1e5: uc_dat <= 32'b00001000000000000000100000100110;
9'h1e6: uc_dat <= 32'b00001000000000000000010000000000;
9'h1e7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1e8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1e9: uc_dat <= 32'b00001000000000000000100000100010;
9'h1ea: uc_dat <= 32'b00001000000000000000100000001010;
9'h1eb: uc_dat <= 32'b00001000000000000000000000101100;
9'h1ec: uc_dat <= 32'b00001000000000000000100000010101;
9'h1ed: uc_dat <= 32'b00001000000000000000000000000000;
9'h1ee: uc_dat <= 32'b00001000000000000000010000000010;
9'h1ef: uc_dat <= 32'b00001000000000000000100000011100;
9'h1f0: uc_dat <= 32'b00001000000000000000100000011011;
9'h1f1: uc_dat <= 32'b00001000000000000000100000110100;
9'h1f2: uc_dat <= 32'b00001000000000000000100000001010;
9'h1f3: uc_dat <= 32'b00001000000000000000110000001001;
9'h1f4: uc_dat <= 32'b00001000000000000000100000010101;
9'h1f5: uc_dat <= 32'b00001000000000000000100000101011;
9'h1f6: uc_dat <= 32'b00001000000000000000010000000100;
9'h1f7: uc_dat <= 32'b00001000000000000000100000011100;
9'h1f8: uc_dat <= 32'b00001000000000000000100000011011;
9'h1f9: uc_dat <= 32'b00001000000000000000110000000100;
9'h1fa: uc_dat <= 32'b00001000000000000000100000001010;
9'h1fb: uc_dat <= 32'b00001000000000000000110000001000;
9'h1fc: uc_dat <= 32'b00001000000000000000100000010101;
9'h1fd: uc_dat <= 32'b00001000000000000000000000000000;
9'h1fe: uc_dat <= 32'b00001000000000000000010000000110;
9'h1ff: uc_dat <= 32'b00001000000000000000100000011100;
endcase
end
always @ (posedge clock)
begin
uc_dout <= uc_dat;
end
endmodule | 0 |
141,892 | data/full_repos/permissive/96181301/quartus/lite8080/ram_image.v | 96,181,301 | ram_image.v | v | 316 | 81 | [] | [] | [] | [(6, 314)] | null | data/verilator_xmls/bdadd8f2-f690-4393-a63c-b0855fb45d01.xml | null | 312,628 | module | module ram_image
(
clk, addr,
we, din, dout
);
input clk;
input [11:0] addr;
input we;
input [7:0] din;
output [7:0] dout;
reg [7:0] dout;
reg [7:0] ram [4095:0];
initial
begin
ram[0] = 8'h21; ram[1] = 8'h00; ram[2] = 8'h0c; ram[3] = 8'hf9;
ram[4] = 8'hcd; ram[5] = 8'h30; ram[6] = 8'h03; ram[7] = 8'h00;
ram[8] = 8'hf5; ram[9] = 8'hc5; ram[10] = 8'hd5; ram[11] = 8'he5;
ram[12] = 8'hcd; ram[13] = 8'h24; ram[14] = 8'h03; ram[15] = 8'he1;
ram[16] = 8'hd1; ram[17] = 8'hc1; ram[18] = 8'hf1; ram[19] = 8'hfb;
ram[20] = 8'hc9; ram[21] = 8'h00; ram[22] = 8'h00; ram[23] = 8'h00;
ram[24] = 8'hf5; ram[25] = 8'hc5; ram[26] = 8'hd5; ram[27] = 8'he5;
ram[28] = 8'he1; ram[29] = 8'hd1; ram[30] = 8'hc1; ram[31] = 8'hf1;
ram[32] = 8'hfb; ram[33] = 8'hc9; ram[34] = 8'h00; ram[35] = 8'h00;
ram[36] = 8'h00; ram[37] = 8'h00; ram[38] = 8'h00; ram[39] = 8'h00;
ram[40] = 8'hf5; ram[41] = 8'hc5; ram[42] = 8'hd5; ram[43] = 8'he5;
ram[44] = 8'he1; ram[45] = 8'hd1; ram[46] = 8'hc1; ram[47] = 8'hf1;
ram[48] = 8'hfb; ram[49] = 8'hc9; ram[50] = 8'h00; ram[51] = 8'h00;
ram[52] = 8'h00; ram[53] = 8'h00; ram[54] = 8'h00; ram[55] = 8'h00;
ram[56] = 8'hf5; ram[57] = 8'hc5; ram[58] = 8'hd5; ram[59] = 8'he5;
ram[60] = 8'he1; ram[61] = 8'hd1; ram[62] = 8'hc1; ram[63] = 8'hf1;
ram[64] = 8'hfb; ram[65] = 8'hc9; ram[66] = 8'h7e; ram[67] = 8'h6f;
ram[68] = 8'h07; ram[69] = 8'h9f; ram[70] = 8'h67; ram[71] = 8'hc9;
ram[72] = 8'h7e; ram[73] = 8'h23; ram[74] = 8'h66; ram[75] = 8'h6f;
ram[76] = 8'hc9; ram[77] = 8'h7d; ram[78] = 8'h12; ram[79] = 8'hc9;
ram[80] = 8'h7d; ram[81] = 8'h12; ram[82] = 8'h13; ram[83] = 8'h7c;
ram[84] = 8'h12; ram[85] = 8'hc9; ram[86] = 8'h7d; ram[87] = 8'hb3;
ram[88] = 8'h6f; ram[89] = 8'h7c; ram[90] = 8'hb2; ram[91] = 8'h67;
ram[92] = 8'hc9; ram[93] = 8'h7d; ram[94] = 8'hab; ram[95] = 8'h6f;
ram[96] = 8'h7c; ram[97] = 8'haa; ram[98] = 8'h67; ram[99] = 8'hc9;
ram[100] = 8'h7d; ram[101] = 8'ha3; ram[102] = 8'h6f; ram[103] = 8'h7c;
ram[104] = 8'ha2; ram[105] = 8'h67; ram[106] = 8'hc9; ram[107] = 8'hcd;
ram[108] = 8'h91; ram[109] = 8'h00; ram[110] = 8'hc8; ram[111] = 8'h2b;
ram[112] = 8'hc9; ram[113] = 8'hcd; ram[114] = 8'h91; ram[115] = 8'h00;
ram[116] = 8'hc0; ram[117] = 8'h2b; ram[118] = 8'hc9; ram[119] = 8'heb;
ram[120] = 8'hcd; ram[121] = 8'h91; ram[122] = 8'h00; ram[123] = 8'hd8;
ram[124] = 8'h2b; ram[125] = 8'hc9; ram[126] = 8'hcd; ram[127] = 8'h91;
ram[128] = 8'h00; ram[129] = 8'hc8; ram[130] = 8'hd8; ram[131] = 8'h2b;
ram[132] = 8'hc9; ram[133] = 8'hcd; ram[134] = 8'h91; ram[135] = 8'h00;
ram[136] = 8'hd0; ram[137] = 8'h2b; ram[138] = 8'hc9; ram[139] = 8'hcd;
ram[140] = 8'h91; ram[141] = 8'h00; ram[142] = 8'hd8; ram[143] = 8'h2b;
ram[144] = 8'hc9; ram[145] = 8'h7b; ram[146] = 8'h95; ram[147] = 8'h5f;
ram[148] = 8'h7a; ram[149] = 8'h9c; ram[150] = 8'h21; ram[151] = 8'h01;
ram[152] = 8'h00; ram[153] = 8'hfa; ram[154] = 8'h9e; ram[155] = 8'h00;
ram[156] = 8'hb3; ram[157] = 8'hc9; ram[158] = 8'hb3; ram[159] = 8'h37;
ram[160] = 8'hc9; ram[161] = 8'hcd; ram[162] = 8'hbb; ram[163] = 8'h00;
ram[164] = 8'hd0; ram[165] = 8'h2b; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hbb; ram[169] = 8'h00; ram[170] = 8'hd8; ram[171] = 8'h2b;
ram[172] = 8'hc9; ram[173] = 8'heb; ram[174] = 8'hcd; ram[175] = 8'hbb;
ram[176] = 8'h00; ram[177] = 8'hd8; ram[178] = 8'h2b; ram[179] = 8'hc9;
ram[180] = 8'hcd; ram[181] = 8'hbb; ram[182] = 8'h00; ram[183] = 8'hc8;
ram[184] = 8'hd8; ram[185] = 8'h2b; ram[186] = 8'hc9; ram[187] = 8'h7a;
ram[188] = 8'hbc; ram[189] = 8'hc2; ram[190] = 8'hc2; ram[191] = 8'h00;
ram[192] = 8'h7b; ram[193] = 8'hbd; ram[194] = 8'h21; ram[195] = 8'h01;
ram[196] = 8'h00; ram[197] = 8'hc9; ram[198] = 8'heb; ram[199] = 8'h7c;
ram[200] = 8'h17; ram[201] = 8'h7c; ram[202] = 8'h1f; ram[203] = 8'h67;
ram[204] = 8'h7d; ram[205] = 8'h1f; ram[206] = 8'h6f; ram[207] = 8'h1d;
ram[208] = 8'hc2; ram[209] = 8'hc7; ram[210] = 8'h00; ram[211] = 8'hc9;
ram[212] = 8'heb; ram[213] = 8'h29; ram[214] = 8'h1d; ram[215] = 8'hc2;
ram[216] = 8'hd5; ram[217] = 8'h00; ram[218] = 8'hc9; ram[219] = 8'h7b;
ram[220] = 8'h95; ram[221] = 8'h6f; ram[222] = 8'h7a; ram[223] = 8'h9c;
ram[224] = 8'h67; ram[225] = 8'hc9; ram[226] = 8'hcd; ram[227] = 8'he7;
ram[228] = 8'h00; ram[229] = 8'h23; ram[230] = 8'hc9; ram[231] = 8'h7c;
ram[232] = 8'h2f; ram[233] = 8'h67; ram[234] = 8'h7d; ram[235] = 8'h2f;
ram[236] = 8'h6f; ram[237] = 8'hc9; ram[238] = 8'h44; ram[239] = 8'h4d;
ram[240] = 8'h21; ram[241] = 8'h00; ram[242] = 8'h00; ram[243] = 8'h79;
ram[244] = 8'h0f; ram[245] = 8'hd2; ram[246] = 8'hf9; ram[247] = 8'h00;
ram[248] = 8'h19; ram[249] = 8'haf; ram[250] = 8'h78; ram[251] = 8'h1f;
ram[252] = 8'h47; ram[253] = 8'h79; ram[254] = 8'h1f; ram[255] = 8'h4f;
ram[256] = 8'hb0; ram[257] = 8'hc8; ram[258] = 8'haf; ram[259] = 8'h7b;
ram[260] = 8'h17; ram[261] = 8'h5f; ram[262] = 8'h7a; ram[263] = 8'h17;
ram[264] = 8'h57; ram[265] = 8'hb3; ram[266] = 8'hc8; ram[267] = 8'hc3;
ram[268] = 8'hf3; ram[269] = 8'h00; ram[270] = 8'h44; ram[271] = 8'h4d;
ram[272] = 8'h7a; ram[273] = 8'ha8; ram[274] = 8'hf5; ram[275] = 8'h7a;
ram[276] = 8'hb7; ram[277] = 8'hfc; ram[278] = 8'h4f; ram[279] = 8'h01;
ram[280] = 8'h78; ram[281] = 8'hb7; ram[282] = 8'hfc; ram[283] = 8'h57;
ram[284] = 8'h01; ram[285] = 8'h3e; ram[286] = 8'h10; ram[287] = 8'hf5;
ram[288] = 8'heb; ram[289] = 8'h11; ram[290] = 8'h00; ram[291] = 8'h00;
ram[292] = 8'h29; ram[293] = 8'hcd; ram[294] = 8'h5f; ram[295] = 8'h01;
ram[296] = 8'hca; ram[297] = 8'h3b; ram[298] = 8'h01; ram[299] = 8'hcd;
ram[300] = 8'h67; ram[301] = 8'h01; ram[302] = 8'hfa; ram[303] = 8'h3b;
ram[304] = 8'h01; ram[305] = 8'h7d; ram[306] = 8'hf6; ram[307] = 8'h01;
ram[308] = 8'h6f; ram[309] = 8'h7b; ram[310] = 8'h91; ram[311] = 8'h5f;
ram[312] = 8'h7a; ram[313] = 8'h98; ram[314] = 8'h57; ram[315] = 8'hf1;
ram[316] = 8'h3d; ram[317] = 8'hca; ram[318] = 8'h44; ram[319] = 8'h01;
ram[320] = 8'hf5; ram[321] = 8'hc3; ram[322] = 8'h24; ram[323] = 8'h01;
ram[324] = 8'hf1; ram[325] = 8'hf0; ram[326] = 8'hcd; ram[327] = 8'h4f;
ram[328] = 8'h01; ram[329] = 8'heb; ram[330] = 8'hcd; ram[331] = 8'h4f;
ram[332] = 8'h01; ram[333] = 8'heb; ram[334] = 8'hc9; ram[335] = 8'h7a;
ram[336] = 8'h2f; ram[337] = 8'h57; ram[338] = 8'h7b; ram[339] = 8'h2f;
ram[340] = 8'h5f; ram[341] = 8'h13; ram[342] = 8'hc9; ram[343] = 8'h78;
ram[344] = 8'h2f; ram[345] = 8'h47; ram[346] = 8'h79; ram[347] = 8'h2f;
ram[348] = 8'h4f; ram[349] = 8'h03; ram[350] = 8'hc9; ram[351] = 8'h7b;
ram[352] = 8'h17; ram[353] = 8'h5f; ram[354] = 8'h7a; ram[355] = 8'h17;
ram[356] = 8'h57; ram[357] = 8'hb3; ram[358] = 8'hc9; ram[359] = 8'h7b;
ram[360] = 8'h91; ram[361] = 8'h7a; ram[362] = 8'h98; ram[363] = 8'hc9;
ram[364] = 8'hdb; ram[365] = 8'h83; ram[366] = 8'hcd; ram[367] = 8'h43;
ram[368] = 8'h00; ram[369] = 8'he5; ram[370] = 8'h21; ram[371] = 8'h01;
ram[372] = 8'h00; ram[373] = 8'hd1; ram[374] = 8'hcd; ram[375] = 8'h64;
ram[376] = 8'h00; ram[377] = 8'h7c; ram[378] = 8'hb5; ram[379] = 8'hca;
ram[380] = 8'h81; ram[381] = 8'h01; ram[382] = 8'hc3; ram[383] = 8'h6c;
ram[384] = 8'h01; ram[385] = 8'h21; ram[386] = 8'h02; ram[387] = 8'h00;
ram[388] = 8'h39; ram[389] = 8'hcd; ram[390] = 8'h42; ram[391] = 8'h00;
ram[392] = 8'h7d; ram[393] = 8'hd3; ram[394] = 8'h80; ram[395] = 8'hc9;
ram[396] = 8'hdb; ram[397] = 8'h83; ram[398] = 8'hcd; ram[399] = 8'h43;
ram[400] = 8'h00; ram[401] = 8'he5; ram[402] = 8'h21; ram[403] = 8'h10;
ram[404] = 8'h00; ram[405] = 8'hd1; ram[406] = 8'hcd; ram[407] = 8'h64;
ram[408] = 8'h00; ram[409] = 8'h7c; ram[410] = 8'hb5; ram[411] = 8'hca;
ram[412] = 8'hae; ram[413] = 8'h01; ram[414] = 8'hdb; ram[415] = 8'h80;
ram[416] = 8'hcd; ram[417] = 8'h43; ram[418] = 8'h00; ram[419] = 8'h7d;
ram[420] = 8'h32; ram[421] = 8'h2c; ram[422] = 8'h04; ram[423] = 8'h21;
ram[424] = 8'h01; ram[425] = 8'h00; ram[426] = 8'hc9; ram[427] = 8'hc3;
ram[428] = 8'hb2; ram[429] = 8'h01; ram[430] = 8'h21; ram[431] = 8'h00;
ram[432] = 8'h00; ram[433] = 8'hc9; ram[434] = 8'hc9; ram[435] = 8'h21;
ram[436] = 8'h0d; ram[437] = 8'h00; ram[438] = 8'he5; ram[439] = 8'hcd;
ram[440] = 8'h6c; ram[441] = 8'h01; ram[442] = 8'hc1; ram[443] = 8'h21;
ram[444] = 8'h0a; ram[445] = 8'h00; ram[446] = 8'he5; ram[447] = 8'hcd;
ram[448] = 8'h6c; ram[449] = 8'h01; ram[450] = 8'hc1; ram[451] = 8'hc9;
ram[452] = 8'h21; ram[453] = 8'h02; ram[454] = 8'h00; ram[455] = 8'h39;
ram[456] = 8'hcd; ram[457] = 8'h48; ram[458] = 8'h00; ram[459] = 8'hcd;
ram[460] = 8'h42; ram[461] = 8'h00; ram[462] = 8'he5; ram[463] = 8'h21;
ram[464] = 8'h00; ram[465] = 8'h00; ram[466] = 8'hd1; ram[467] = 8'hcd;
ram[468] = 8'h71; ram[469] = 8'h00; ram[470] = 8'h7c; ram[471] = 8'hb5;
ram[472] = 8'hca; ram[473] = 8'hf4; ram[474] = 8'h01; ram[475] = 8'h21;
ram[476] = 8'h02; ram[477] = 8'h00; ram[478] = 8'h39; ram[479] = 8'he5;
ram[480] = 8'hcd; ram[481] = 8'h48; ram[482] = 8'h00; ram[483] = 8'h23;
ram[484] = 8'hd1; ram[485] = 8'hcd; ram[486] = 8'h50; ram[487] = 8'h00;
ram[488] = 8'h2b; ram[489] = 8'hcd; ram[490] = 8'h42; ram[491] = 8'h00;
ram[492] = 8'he5; ram[493] = 8'hcd; ram[494] = 8'h6c; ram[495] = 8'h01;
ram[496] = 8'hc1; ram[497] = 8'hc3; ram[498] = 8'hc4; ram[499] = 8'h01;
ram[500] = 8'hc9; ram[501] = 8'h21; ram[502] = 8'h02; ram[503] = 8'h00;
ram[504] = 8'h39; ram[505] = 8'hcd; ram[506] = 8'h48; ram[507] = 8'h00;
ram[508] = 8'he5; ram[509] = 8'h21; ram[510] = 8'h00; ram[511] = 8'h00;
ram[512] = 8'hd1; ram[513] = 8'hcd; ram[514] = 8'h8b; ram[515] = 8'h00;
ram[516] = 8'h7c; ram[517] = 8'hb5; ram[518] = 8'hca; ram[519] = 8'h24;
ram[520] = 8'h02; ram[521] = 8'h21; ram[522] = 8'h2d; ram[523] = 8'h00;
ram[524] = 8'he5; ram[525] = 8'hcd; ram[526] = 8'h6c; ram[527] = 8'h01;
ram[528] = 8'hc1; ram[529] = 8'h21; ram[530] = 8'h02; ram[531] = 8'h00;
ram[532] = 8'h39; ram[533] = 8'he5; ram[534] = 8'h21; ram[535] = 8'h04;
ram[536] = 8'h00; ram[537] = 8'h39; ram[538] = 8'hcd; ram[539] = 8'h48;
ram[540] = 8'h00; ram[541] = 8'hcd; ram[542] = 8'he2; ram[543] = 8'h00;
ram[544] = 8'hd1; ram[545] = 8'hcd; ram[546] = 8'h50; ram[547] = 8'h00;
ram[548] = 8'h21; ram[549] = 8'h02; ram[550] = 8'h00; ram[551] = 8'h39;
ram[552] = 8'hcd; ram[553] = 8'h48; ram[554] = 8'h00; ram[555] = 8'he5;
ram[556] = 8'hcd; ram[557] = 8'h31; ram[558] = 8'h02; ram[559] = 8'hc1;
ram[560] = 8'hc9; ram[561] = 8'hc5; ram[562] = 8'h21; ram[563] = 8'h00;
ram[564] = 8'h00; ram[565] = 8'h39; ram[566] = 8'he5; ram[567] = 8'h21;
ram[568] = 8'h06; ram[569] = 8'h00; ram[570] = 8'h39; ram[571] = 8'hcd;
ram[572] = 8'h48; ram[573] = 8'h00; ram[574] = 8'he5; ram[575] = 8'h21;
ram[576] = 8'h0a; ram[577] = 8'h00; ram[578] = 8'hd1; ram[579] = 8'hcd;
ram[580] = 8'h0e; ram[581] = 8'h01; ram[582] = 8'hd1; ram[583] = 8'hcd;
ram[584] = 8'h50; ram[585] = 8'h00; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'hcd; ram[591] = 8'h48;
ram[592] = 8'h00; ram[593] = 8'h7c; ram[594] = 8'hb5; ram[595] = 8'hca;
ram[596] = 8'h62; ram[597] = 8'h02; ram[598] = 8'h21; ram[599] = 8'h00;
ram[600] = 8'h00; ram[601] = 8'h39; ram[602] = 8'hcd; ram[603] = 8'h48;
ram[604] = 8'h00; ram[605] = 8'he5; ram[606] = 8'hcd; ram[607] = 8'h31;
ram[608] = 8'h02; ram[609] = 8'hc1; ram[610] = 8'h21; ram[611] = 8'h30;
ram[612] = 8'h00; ram[613] = 8'he5; ram[614] = 8'h21; ram[615] = 8'h06;
ram[616] = 8'h00; ram[617] = 8'h39; ram[618] = 8'hcd; ram[619] = 8'h48;
ram[620] = 8'h00; ram[621] = 8'he5; ram[622] = 8'h21; ram[623] = 8'h04;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h48;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'h21; ram[631] = 8'h0a;
ram[632] = 8'h00; ram[633] = 8'hd1; ram[634] = 8'hcd; ram[635] = 8'hee;
ram[636] = 8'h00; ram[637] = 8'hd1; ram[638] = 8'hcd; ram[639] = 8'hdb;
ram[640] = 8'h00; ram[641] = 8'hd1; ram[642] = 8'h19; ram[643] = 8'he5;
ram[644] = 8'hcd; ram[645] = 8'h6c; ram[646] = 8'h01; ram[647] = 8'hc1;
ram[648] = 8'hc1; ram[649] = 8'hc9; ram[650] = 8'hc5; ram[651] = 8'h21;
ram[652] = 8'h00; ram[653] = 8'h00; ram[654] = 8'h39; ram[655] = 8'he5;
ram[656] = 8'h21; ram[657] = 8'h06; ram[658] = 8'h00; ram[659] = 8'h39;
ram[660] = 8'hcd; ram[661] = 8'h48; ram[662] = 8'h00; ram[663] = 8'he5;
ram[664] = 8'h21; ram[665] = 8'h10; ram[666] = 8'h00; ram[667] = 8'hd1;
ram[668] = 8'hcd; ram[669] = 8'h0e; ram[670] = 8'h01; ram[671] = 8'hd1;
ram[672] = 8'hcd; ram[673] = 8'h50; ram[674] = 8'h00; ram[675] = 8'h21;
ram[676] = 8'h00; ram[677] = 8'h00; ram[678] = 8'h39; ram[679] = 8'hcd;
ram[680] = 8'h48; ram[681] = 8'h00; ram[682] = 8'h7c; ram[683] = 8'hb5;
ram[684] = 8'hca; ram[685] = 8'hbb; ram[686] = 8'h02; ram[687] = 8'h21;
ram[688] = 8'h00; ram[689] = 8'h00; ram[690] = 8'h39; ram[691] = 8'hcd;
ram[692] = 8'h48; ram[693] = 8'h00; ram[694] = 8'he5; ram[695] = 8'hcd;
ram[696] = 8'h8a; ram[697] = 8'h02; ram[698] = 8'hc1; ram[699] = 8'h21;
ram[700] = 8'h00; ram[701] = 8'h00; ram[702] = 8'h39; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h06; ram[706] = 8'h00; ram[707] = 8'h39;
ram[708] = 8'hcd; ram[709] = 8'h48; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'h21; ram[713] = 8'h04; ram[714] = 8'h00; ram[715] = 8'h39;
ram[716] = 8'hcd; ram[717] = 8'h48; ram[718] = 8'h00; ram[719] = 8'he5;
ram[720] = 8'h21; ram[721] = 8'h10; ram[722] = 8'h00; ram[723] = 8'hd1;
ram[724] = 8'hcd; ram[725] = 8'hee; ram[726] = 8'h00; ram[727] = 8'hd1;
ram[728] = 8'hcd; ram[729] = 8'hdb; ram[730] = 8'h00; ram[731] = 8'hd1;
ram[732] = 8'hcd; ram[733] = 8'h50; ram[734] = 8'h00; ram[735] = 8'h21;
ram[736] = 8'h00; ram[737] = 8'h00; ram[738] = 8'h39; ram[739] = 8'hcd;
ram[740] = 8'h48; ram[741] = 8'h00; ram[742] = 8'he5; ram[743] = 8'h21;
ram[744] = 8'h09; ram[745] = 8'h00; ram[746] = 8'hd1; ram[747] = 8'hcd;
ram[748] = 8'h77; ram[749] = 8'h00; ram[750] = 8'h7c; ram[751] = 8'hb5;
ram[752] = 8'hca; ram[753] = 8'h10; ram[754] = 8'h03; ram[755] = 8'h21;
ram[756] = 8'h41; ram[757] = 8'h00; ram[758] = 8'he5; ram[759] = 8'h21;
ram[760] = 8'h02; ram[761] = 8'h00; ram[762] = 8'h39; ram[763] = 8'hcd;
ram[764] = 8'h48; ram[765] = 8'h00; ram[766] = 8'hd1; ram[767] = 8'h19;
ram[768] = 8'he5; ram[769] = 8'h21; ram[770] = 8'h0a; ram[771] = 8'h00;
ram[772] = 8'hd1; ram[773] = 8'hcd; ram[774] = 8'hdb; ram[775] = 8'h00;
ram[776] = 8'he5; ram[777] = 8'hcd; ram[778] = 8'h6c; ram[779] = 8'h01;
ram[780] = 8'hc1; ram[781] = 8'hc3; ram[782] = 8'h22; ram[783] = 8'h03;
ram[784] = 8'h21; ram[785] = 8'h30; ram[786] = 8'h00; ram[787] = 8'he5;
ram[788] = 8'h21; ram[789] = 8'h02; ram[790] = 8'h00; ram[791] = 8'h39;
ram[792] = 8'hcd; ram[793] = 8'h48; ram[794] = 8'h00; ram[795] = 8'hd1;
ram[796] = 8'h19; ram[797] = 8'he5; ram[798] = 8'hcd; ram[799] = 8'h6c;
ram[800] = 8'h01; ram[801] = 8'hc1; ram[802] = 8'hc1; ram[803] = 8'hc9;
ram[804] = 8'h21; ram[805] = 8'hd0; ram[806] = 8'h03; ram[807] = 8'he5;
ram[808] = 8'hcd; ram[809] = 8'hc4; ram[810] = 8'h01; ram[811] = 8'hc1;
ram[812] = 8'hcd; ram[813] = 8'hb3; ram[814] = 8'h01; ram[815] = 8'hc9;
ram[816] = 8'h21; ram[817] = 8'ha3; ram[818] = 8'h00; ram[819] = 8'h7d;
ram[820] = 8'hd3; ram[821] = 8'h81; ram[822] = 8'h21; ram[823] = 8'h00;
ram[824] = 8'h00; ram[825] = 8'h7d; ram[826] = 8'hd3; ram[827] = 8'h82;
ram[828] = 8'h21; ram[829] = 8'h00; ram[830] = 8'h00; ram[831] = 8'h7d;
ram[832] = 8'hd3; ram[833] = 8'h84; ram[834] = 8'h21; ram[835] = 8'hff;
ram[836] = 8'h00; ram[837] = 8'h7d; ram[838] = 8'hd3; ram[839] = 8'h85;
ram[840] = 8'h21; ram[841] = 8'h00; ram[842] = 8'h00; ram[843] = 8'h7d;
ram[844] = 8'hd3; ram[845] = 8'h86; ram[846] = 8'h21; ram[847] = 8'hff;
ram[848] = 8'h00; ram[849] = 8'h7d; ram[850] = 8'hd3; ram[851] = 8'h87;
ram[852] = 8'h21; ram[853] = 8'h01; ram[854] = 8'h00; ram[855] = 8'h7d;
ram[856] = 8'hd3; ram[857] = 8'h88; ram[858] = 8'hfb; ram[859] = 8'h21;
ram[860] = 8'hea; ram[861] = 8'h03; ram[862] = 8'he5; ram[863] = 8'hcd;
ram[864] = 8'hc4; ram[865] = 8'h01; ram[866] = 8'hc1; ram[867] = 8'hcd;
ram[868] = 8'hb3; ram[869] = 8'h01; ram[870] = 8'h21; ram[871] = 8'hf9;
ram[872] = 8'h03; ram[873] = 8'he5; ram[874] = 8'hcd; ram[875] = 8'hc4;
ram[876] = 8'h01; ram[877] = 8'hc1; ram[878] = 8'h21; ram[879] = 8'h2d;
ram[880] = 8'h04; ram[881] = 8'he5; ram[882] = 8'h21; ram[883] = 8'h01;
ram[884] = 8'h00; ram[885] = 8'h29; ram[886] = 8'hd1; ram[887] = 8'h19;
ram[888] = 8'hcd; ram[889] = 8'h48; ram[890] = 8'h00; ram[891] = 8'he5;
ram[892] = 8'hcd; ram[893] = 8'hf5; ram[894] = 8'h01; ram[895] = 8'hc1;
ram[896] = 8'hcd; ram[897] = 8'hb3; ram[898] = 8'h01; ram[899] = 8'h21;
ram[900] = 8'h05; ram[901] = 8'h04; ram[902] = 8'he5; ram[903] = 8'hcd;
ram[904] = 8'hc4; ram[905] = 8'h01; ram[906] = 8'hc1; ram[907] = 8'h21;
ram[908] = 8'h2d; ram[909] = 8'h04; ram[910] = 8'he5; ram[911] = 8'h21;
ram[912] = 8'h00; ram[913] = 8'h00; ram[914] = 8'h29; ram[915] = 8'hd1;
ram[916] = 8'h19; ram[917] = 8'hcd; ram[918] = 8'h48; ram[919] = 8'h00;
ram[920] = 8'he5; ram[921] = 8'hcd; ram[922] = 8'h8a; ram[923] = 8'h02;
ram[924] = 8'hc1; ram[925] = 8'hcd; ram[926] = 8'hb3; ram[927] = 8'h01;
ram[928] = 8'h21; ram[929] = 8'h01; ram[930] = 8'h00; ram[931] = 8'h7d;
ram[932] = 8'hd3; ram[933] = 8'h84; ram[934] = 8'h21; ram[935] = 8'h13;
ram[936] = 8'h04; ram[937] = 8'he5; ram[938] = 8'hcd; ram[939] = 8'hc4;
ram[940] = 8'h01; ram[941] = 8'hc1; ram[942] = 8'hcd; ram[943] = 8'hb3;
ram[944] = 8'h01; ram[945] = 8'h21; ram[946] = 8'h01; ram[947] = 8'h00;
ram[948] = 8'h7c; ram[949] = 8'hb5; ram[950] = 8'hca; ram[951] = 8'hcf;
ram[952] = 8'h03; ram[953] = 8'hcd; ram[954] = 8'h8c; ram[955] = 8'h01;
ram[956] = 8'h7c; ram[957] = 8'hb5; ram[958] = 8'hca; ram[959] = 8'hcc;
ram[960] = 8'h03; ram[961] = 8'h3a; ram[962] = 8'h2c; ram[963] = 8'h04;
ram[964] = 8'hcd; ram[965] = 8'h43; ram[966] = 8'h00; ram[967] = 8'he5;
ram[968] = 8'hcd; ram[969] = 8'h6c; ram[970] = 8'h01; ram[971] = 8'hc1;
ram[972] = 8'hc3; ram[973] = 8'hb1; ram[974] = 8'h03; ram[975] = 8'hc9;
ram[976] = 8'h49; ram[977] = 8'h6e; ram[978] = 8'h74; ram[979] = 8'h65;
ram[980] = 8'h72; ram[981] = 8'h72; ram[982] = 8'h75; ram[983] = 8'h70;
ram[984] = 8'h74; ram[985] = 8'h20; ram[986] = 8'h30; ram[987] = 8'h20;
ram[988] = 8'h77; ram[989] = 8'h61; ram[990] = 8'h73; ram[991] = 8'h20;
ram[992] = 8'h61; ram[993] = 8'h73; ram[994] = 8'h73; ram[995] = 8'h65;
ram[996] = 8'h72; ram[997] = 8'h74; ram[998] = 8'h65; ram[999] = 8'h64;
ram[1000] = 8'h2e; ram[1001] = 8'h00; ram[1002] = 8'h48; ram[1003] = 8'h65;
ram[1004] = 8'h6c; ram[1005] = 8'h6c; ram[1006] = 8'h6f; ram[1007] = 8'h20;
ram[1008] = 8'h57; ram[1009] = 8'h6f; ram[1010] = 8'h72; ram[1011] = 8'h6c;
ram[1012] = 8'h64; ram[1013] = 8'h21; ram[1014] = 8'h21; ram[1015] = 8'h21;
ram[1016] = 8'h00; ram[1017] = 8'h44; ram[1018] = 8'h65; ram[1019] = 8'h63;
ram[1020] = 8'h20; ram[1021] = 8'h76; ram[1022] = 8'h61; ram[1023] = 8'h6c;
ram[1024] = 8'h75; ram[1025] = 8'h65; ram[1026] = 8'h3a; ram[1027] = 8'h20;
ram[1028] = 8'h00; ram[1029] = 8'h48; ram[1030] = 8'h65; ram[1031] = 8'h78;
ram[1032] = 8'h20; ram[1033] = 8'h76; ram[1034] = 8'h61; ram[1035] = 8'h6c;
ram[1036] = 8'h75; ram[1037] = 8'h65; ram[1038] = 8'h3a; ram[1039] = 8'h20;
ram[1040] = 8'h30; ram[1041] = 8'h78; ram[1042] = 8'h00; ram[1043] = 8'h45;
ram[1044] = 8'h63; ram[1045] = 8'h68; ram[1046] = 8'h6f; ram[1047] = 8'h69;
ram[1048] = 8'h6e; ram[1049] = 8'h67; ram[1050] = 8'h20; ram[1051] = 8'h72;
ram[1052] = 8'h65; ram[1053] = 8'h63; ram[1054] = 8'h65; ram[1055] = 8'h69;
ram[1056] = 8'h76; ram[1057] = 8'h65; ram[1058] = 8'h64; ram[1059] = 8'h20;
ram[1060] = 8'h62; ram[1061] = 8'h79; ram[1062] = 8'h74; ram[1063] = 8'h65;
ram[1064] = 8'h73; ram[1065] = 8'h3a; ram[1066] = 8'h20; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'hd2; ram[1070] = 8'h04; ram[1071] = 8'h2e;
ram[1072] = 8'h16; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[1076] = 8'h00; ram[1077] = 8'h00; ram[1078] = 8'h00; ram[1079] = 8'h00;
ram[1080] = 8'h00; ram[1081] = 8'h00; ram[1082] = 8'h00; ram[1083] = 8'h00;
ram[1084] = 8'h00; ram[1085] = 8'h00; ram[1086] = 8'h00; ram[1087] = 8'h00;
ram[1088] = 8'h00; ram[1089] = 8'h00; ram[1090] = 8'h00; ram[1091] = 8'h00;
ram[1092] = 8'h00; ram[1093] = 8'h00; ram[1094] = 8'h00; ram[1095] = 8'h00;
ram[1096] = 8'h00; ram[1097] = 8'h00; ram[1098] = 8'h00; ram[1099] = 8'h00;
end
always @(posedge clk)
begin
if (we)
begin
ram[addr] <= din;
dout <= din;
end
else
dout <= ram[addr];
end
endmodule | module ram_image
(
clk, addr,
we, din, dout
); |
input clk;
input [11:0] addr;
input we;
input [7:0] din;
output [7:0] dout;
reg [7:0] dout;
reg [7:0] ram [4095:0];
initial
begin
ram[0] = 8'h21; ram[1] = 8'h00; ram[2] = 8'h0c; ram[3] = 8'hf9;
ram[4] = 8'hcd; ram[5] = 8'h30; ram[6] = 8'h03; ram[7] = 8'h00;
ram[8] = 8'hf5; ram[9] = 8'hc5; ram[10] = 8'hd5; ram[11] = 8'he5;
ram[12] = 8'hcd; ram[13] = 8'h24; ram[14] = 8'h03; ram[15] = 8'he1;
ram[16] = 8'hd1; ram[17] = 8'hc1; ram[18] = 8'hf1; ram[19] = 8'hfb;
ram[20] = 8'hc9; ram[21] = 8'h00; ram[22] = 8'h00; ram[23] = 8'h00;
ram[24] = 8'hf5; ram[25] = 8'hc5; ram[26] = 8'hd5; ram[27] = 8'he5;
ram[28] = 8'he1; ram[29] = 8'hd1; ram[30] = 8'hc1; ram[31] = 8'hf1;
ram[32] = 8'hfb; ram[33] = 8'hc9; ram[34] = 8'h00; ram[35] = 8'h00;
ram[36] = 8'h00; ram[37] = 8'h00; ram[38] = 8'h00; ram[39] = 8'h00;
ram[40] = 8'hf5; ram[41] = 8'hc5; ram[42] = 8'hd5; ram[43] = 8'he5;
ram[44] = 8'he1; ram[45] = 8'hd1; ram[46] = 8'hc1; ram[47] = 8'hf1;
ram[48] = 8'hfb; ram[49] = 8'hc9; ram[50] = 8'h00; ram[51] = 8'h00;
ram[52] = 8'h00; ram[53] = 8'h00; ram[54] = 8'h00; ram[55] = 8'h00;
ram[56] = 8'hf5; ram[57] = 8'hc5; ram[58] = 8'hd5; ram[59] = 8'he5;
ram[60] = 8'he1; ram[61] = 8'hd1; ram[62] = 8'hc1; ram[63] = 8'hf1;
ram[64] = 8'hfb; ram[65] = 8'hc9; ram[66] = 8'h7e; ram[67] = 8'h6f;
ram[68] = 8'h07; ram[69] = 8'h9f; ram[70] = 8'h67; ram[71] = 8'hc9;
ram[72] = 8'h7e; ram[73] = 8'h23; ram[74] = 8'h66; ram[75] = 8'h6f;
ram[76] = 8'hc9; ram[77] = 8'h7d; ram[78] = 8'h12; ram[79] = 8'hc9;
ram[80] = 8'h7d; ram[81] = 8'h12; ram[82] = 8'h13; ram[83] = 8'h7c;
ram[84] = 8'h12; ram[85] = 8'hc9; ram[86] = 8'h7d; ram[87] = 8'hb3;
ram[88] = 8'h6f; ram[89] = 8'h7c; ram[90] = 8'hb2; ram[91] = 8'h67;
ram[92] = 8'hc9; ram[93] = 8'h7d; ram[94] = 8'hab; ram[95] = 8'h6f;
ram[96] = 8'h7c; ram[97] = 8'haa; ram[98] = 8'h67; ram[99] = 8'hc9;
ram[100] = 8'h7d; ram[101] = 8'ha3; ram[102] = 8'h6f; ram[103] = 8'h7c;
ram[104] = 8'ha2; ram[105] = 8'h67; ram[106] = 8'hc9; ram[107] = 8'hcd;
ram[108] = 8'h91; ram[109] = 8'h00; ram[110] = 8'hc8; ram[111] = 8'h2b;
ram[112] = 8'hc9; ram[113] = 8'hcd; ram[114] = 8'h91; ram[115] = 8'h00;
ram[116] = 8'hc0; ram[117] = 8'h2b; ram[118] = 8'hc9; ram[119] = 8'heb;
ram[120] = 8'hcd; ram[121] = 8'h91; ram[122] = 8'h00; ram[123] = 8'hd8;
ram[124] = 8'h2b; ram[125] = 8'hc9; ram[126] = 8'hcd; ram[127] = 8'h91;
ram[128] = 8'h00; ram[129] = 8'hc8; ram[130] = 8'hd8; ram[131] = 8'h2b;
ram[132] = 8'hc9; ram[133] = 8'hcd; ram[134] = 8'h91; ram[135] = 8'h00;
ram[136] = 8'hd0; ram[137] = 8'h2b; ram[138] = 8'hc9; ram[139] = 8'hcd;
ram[140] = 8'h91; ram[141] = 8'h00; ram[142] = 8'hd8; ram[143] = 8'h2b;
ram[144] = 8'hc9; ram[145] = 8'h7b; ram[146] = 8'h95; ram[147] = 8'h5f;
ram[148] = 8'h7a; ram[149] = 8'h9c; ram[150] = 8'h21; ram[151] = 8'h01;
ram[152] = 8'h00; ram[153] = 8'hfa; ram[154] = 8'h9e; ram[155] = 8'h00;
ram[156] = 8'hb3; ram[157] = 8'hc9; ram[158] = 8'hb3; ram[159] = 8'h37;
ram[160] = 8'hc9; ram[161] = 8'hcd; ram[162] = 8'hbb; ram[163] = 8'h00;
ram[164] = 8'hd0; ram[165] = 8'h2b; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hbb; ram[169] = 8'h00; ram[170] = 8'hd8; ram[171] = 8'h2b;
ram[172] = 8'hc9; ram[173] = 8'heb; ram[174] = 8'hcd; ram[175] = 8'hbb;
ram[176] = 8'h00; ram[177] = 8'hd8; ram[178] = 8'h2b; ram[179] = 8'hc9;
ram[180] = 8'hcd; ram[181] = 8'hbb; ram[182] = 8'h00; ram[183] = 8'hc8;
ram[184] = 8'hd8; ram[185] = 8'h2b; ram[186] = 8'hc9; ram[187] = 8'h7a;
ram[188] = 8'hbc; ram[189] = 8'hc2; ram[190] = 8'hc2; ram[191] = 8'h00;
ram[192] = 8'h7b; ram[193] = 8'hbd; ram[194] = 8'h21; ram[195] = 8'h01;
ram[196] = 8'h00; ram[197] = 8'hc9; ram[198] = 8'heb; ram[199] = 8'h7c;
ram[200] = 8'h17; ram[201] = 8'h7c; ram[202] = 8'h1f; ram[203] = 8'h67;
ram[204] = 8'h7d; ram[205] = 8'h1f; ram[206] = 8'h6f; ram[207] = 8'h1d;
ram[208] = 8'hc2; ram[209] = 8'hc7; ram[210] = 8'h00; ram[211] = 8'hc9;
ram[212] = 8'heb; ram[213] = 8'h29; ram[214] = 8'h1d; ram[215] = 8'hc2;
ram[216] = 8'hd5; ram[217] = 8'h00; ram[218] = 8'hc9; ram[219] = 8'h7b;
ram[220] = 8'h95; ram[221] = 8'h6f; ram[222] = 8'h7a; ram[223] = 8'h9c;
ram[224] = 8'h67; ram[225] = 8'hc9; ram[226] = 8'hcd; ram[227] = 8'he7;
ram[228] = 8'h00; ram[229] = 8'h23; ram[230] = 8'hc9; ram[231] = 8'h7c;
ram[232] = 8'h2f; ram[233] = 8'h67; ram[234] = 8'h7d; ram[235] = 8'h2f;
ram[236] = 8'h6f; ram[237] = 8'hc9; ram[238] = 8'h44; ram[239] = 8'h4d;
ram[240] = 8'h21; ram[241] = 8'h00; ram[242] = 8'h00; ram[243] = 8'h79;
ram[244] = 8'h0f; ram[245] = 8'hd2; ram[246] = 8'hf9; ram[247] = 8'h00;
ram[248] = 8'h19; ram[249] = 8'haf; ram[250] = 8'h78; ram[251] = 8'h1f;
ram[252] = 8'h47; ram[253] = 8'h79; ram[254] = 8'h1f; ram[255] = 8'h4f;
ram[256] = 8'hb0; ram[257] = 8'hc8; ram[258] = 8'haf; ram[259] = 8'h7b;
ram[260] = 8'h17; ram[261] = 8'h5f; ram[262] = 8'h7a; ram[263] = 8'h17;
ram[264] = 8'h57; ram[265] = 8'hb3; ram[266] = 8'hc8; ram[267] = 8'hc3;
ram[268] = 8'hf3; ram[269] = 8'h00; ram[270] = 8'h44; ram[271] = 8'h4d;
ram[272] = 8'h7a; ram[273] = 8'ha8; ram[274] = 8'hf5; ram[275] = 8'h7a;
ram[276] = 8'hb7; ram[277] = 8'hfc; ram[278] = 8'h4f; ram[279] = 8'h01;
ram[280] = 8'h78; ram[281] = 8'hb7; ram[282] = 8'hfc; ram[283] = 8'h57;
ram[284] = 8'h01; ram[285] = 8'h3e; ram[286] = 8'h10; ram[287] = 8'hf5;
ram[288] = 8'heb; ram[289] = 8'h11; ram[290] = 8'h00; ram[291] = 8'h00;
ram[292] = 8'h29; ram[293] = 8'hcd; ram[294] = 8'h5f; ram[295] = 8'h01;
ram[296] = 8'hca; ram[297] = 8'h3b; ram[298] = 8'h01; ram[299] = 8'hcd;
ram[300] = 8'h67; ram[301] = 8'h01; ram[302] = 8'hfa; ram[303] = 8'h3b;
ram[304] = 8'h01; ram[305] = 8'h7d; ram[306] = 8'hf6; ram[307] = 8'h01;
ram[308] = 8'h6f; ram[309] = 8'h7b; ram[310] = 8'h91; ram[311] = 8'h5f;
ram[312] = 8'h7a; ram[313] = 8'h98; ram[314] = 8'h57; ram[315] = 8'hf1;
ram[316] = 8'h3d; ram[317] = 8'hca; ram[318] = 8'h44; ram[319] = 8'h01;
ram[320] = 8'hf5; ram[321] = 8'hc3; ram[322] = 8'h24; ram[323] = 8'h01;
ram[324] = 8'hf1; ram[325] = 8'hf0; ram[326] = 8'hcd; ram[327] = 8'h4f;
ram[328] = 8'h01; ram[329] = 8'heb; ram[330] = 8'hcd; ram[331] = 8'h4f;
ram[332] = 8'h01; ram[333] = 8'heb; ram[334] = 8'hc9; ram[335] = 8'h7a;
ram[336] = 8'h2f; ram[337] = 8'h57; ram[338] = 8'h7b; ram[339] = 8'h2f;
ram[340] = 8'h5f; ram[341] = 8'h13; ram[342] = 8'hc9; ram[343] = 8'h78;
ram[344] = 8'h2f; ram[345] = 8'h47; ram[346] = 8'h79; ram[347] = 8'h2f;
ram[348] = 8'h4f; ram[349] = 8'h03; ram[350] = 8'hc9; ram[351] = 8'h7b;
ram[352] = 8'h17; ram[353] = 8'h5f; ram[354] = 8'h7a; ram[355] = 8'h17;
ram[356] = 8'h57; ram[357] = 8'hb3; ram[358] = 8'hc9; ram[359] = 8'h7b;
ram[360] = 8'h91; ram[361] = 8'h7a; ram[362] = 8'h98; ram[363] = 8'hc9;
ram[364] = 8'hdb; ram[365] = 8'h83; ram[366] = 8'hcd; ram[367] = 8'h43;
ram[368] = 8'h00; ram[369] = 8'he5; ram[370] = 8'h21; ram[371] = 8'h01;
ram[372] = 8'h00; ram[373] = 8'hd1; ram[374] = 8'hcd; ram[375] = 8'h64;
ram[376] = 8'h00; ram[377] = 8'h7c; ram[378] = 8'hb5; ram[379] = 8'hca;
ram[380] = 8'h81; ram[381] = 8'h01; ram[382] = 8'hc3; ram[383] = 8'h6c;
ram[384] = 8'h01; ram[385] = 8'h21; ram[386] = 8'h02; ram[387] = 8'h00;
ram[388] = 8'h39; ram[389] = 8'hcd; ram[390] = 8'h42; ram[391] = 8'h00;
ram[392] = 8'h7d; ram[393] = 8'hd3; ram[394] = 8'h80; ram[395] = 8'hc9;
ram[396] = 8'hdb; ram[397] = 8'h83; ram[398] = 8'hcd; ram[399] = 8'h43;
ram[400] = 8'h00; ram[401] = 8'he5; ram[402] = 8'h21; ram[403] = 8'h10;
ram[404] = 8'h00; ram[405] = 8'hd1; ram[406] = 8'hcd; ram[407] = 8'h64;
ram[408] = 8'h00; ram[409] = 8'h7c; ram[410] = 8'hb5; ram[411] = 8'hca;
ram[412] = 8'hae; ram[413] = 8'h01; ram[414] = 8'hdb; ram[415] = 8'h80;
ram[416] = 8'hcd; ram[417] = 8'h43; ram[418] = 8'h00; ram[419] = 8'h7d;
ram[420] = 8'h32; ram[421] = 8'h2c; ram[422] = 8'h04; ram[423] = 8'h21;
ram[424] = 8'h01; ram[425] = 8'h00; ram[426] = 8'hc9; ram[427] = 8'hc3;
ram[428] = 8'hb2; ram[429] = 8'h01; ram[430] = 8'h21; ram[431] = 8'h00;
ram[432] = 8'h00; ram[433] = 8'hc9; ram[434] = 8'hc9; ram[435] = 8'h21;
ram[436] = 8'h0d; ram[437] = 8'h00; ram[438] = 8'he5; ram[439] = 8'hcd;
ram[440] = 8'h6c; ram[441] = 8'h01; ram[442] = 8'hc1; ram[443] = 8'h21;
ram[444] = 8'h0a; ram[445] = 8'h00; ram[446] = 8'he5; ram[447] = 8'hcd;
ram[448] = 8'h6c; ram[449] = 8'h01; ram[450] = 8'hc1; ram[451] = 8'hc9;
ram[452] = 8'h21; ram[453] = 8'h02; ram[454] = 8'h00; ram[455] = 8'h39;
ram[456] = 8'hcd; ram[457] = 8'h48; ram[458] = 8'h00; ram[459] = 8'hcd;
ram[460] = 8'h42; ram[461] = 8'h00; ram[462] = 8'he5; ram[463] = 8'h21;
ram[464] = 8'h00; ram[465] = 8'h00; ram[466] = 8'hd1; ram[467] = 8'hcd;
ram[468] = 8'h71; ram[469] = 8'h00; ram[470] = 8'h7c; ram[471] = 8'hb5;
ram[472] = 8'hca; ram[473] = 8'hf4; ram[474] = 8'h01; ram[475] = 8'h21;
ram[476] = 8'h02; ram[477] = 8'h00; ram[478] = 8'h39; ram[479] = 8'he5;
ram[480] = 8'hcd; ram[481] = 8'h48; ram[482] = 8'h00; ram[483] = 8'h23;
ram[484] = 8'hd1; ram[485] = 8'hcd; ram[486] = 8'h50; ram[487] = 8'h00;
ram[488] = 8'h2b; ram[489] = 8'hcd; ram[490] = 8'h42; ram[491] = 8'h00;
ram[492] = 8'he5; ram[493] = 8'hcd; ram[494] = 8'h6c; ram[495] = 8'h01;
ram[496] = 8'hc1; ram[497] = 8'hc3; ram[498] = 8'hc4; ram[499] = 8'h01;
ram[500] = 8'hc9; ram[501] = 8'h21; ram[502] = 8'h02; ram[503] = 8'h00;
ram[504] = 8'h39; ram[505] = 8'hcd; ram[506] = 8'h48; ram[507] = 8'h00;
ram[508] = 8'he5; ram[509] = 8'h21; ram[510] = 8'h00; ram[511] = 8'h00;
ram[512] = 8'hd1; ram[513] = 8'hcd; ram[514] = 8'h8b; ram[515] = 8'h00;
ram[516] = 8'h7c; ram[517] = 8'hb5; ram[518] = 8'hca; ram[519] = 8'h24;
ram[520] = 8'h02; ram[521] = 8'h21; ram[522] = 8'h2d; ram[523] = 8'h00;
ram[524] = 8'he5; ram[525] = 8'hcd; ram[526] = 8'h6c; ram[527] = 8'h01;
ram[528] = 8'hc1; ram[529] = 8'h21; ram[530] = 8'h02; ram[531] = 8'h00;
ram[532] = 8'h39; ram[533] = 8'he5; ram[534] = 8'h21; ram[535] = 8'h04;
ram[536] = 8'h00; ram[537] = 8'h39; ram[538] = 8'hcd; ram[539] = 8'h48;
ram[540] = 8'h00; ram[541] = 8'hcd; ram[542] = 8'he2; ram[543] = 8'h00;
ram[544] = 8'hd1; ram[545] = 8'hcd; ram[546] = 8'h50; ram[547] = 8'h00;
ram[548] = 8'h21; ram[549] = 8'h02; ram[550] = 8'h00; ram[551] = 8'h39;
ram[552] = 8'hcd; ram[553] = 8'h48; ram[554] = 8'h00; ram[555] = 8'he5;
ram[556] = 8'hcd; ram[557] = 8'h31; ram[558] = 8'h02; ram[559] = 8'hc1;
ram[560] = 8'hc9; ram[561] = 8'hc5; ram[562] = 8'h21; ram[563] = 8'h00;
ram[564] = 8'h00; ram[565] = 8'h39; ram[566] = 8'he5; ram[567] = 8'h21;
ram[568] = 8'h06; ram[569] = 8'h00; ram[570] = 8'h39; ram[571] = 8'hcd;
ram[572] = 8'h48; ram[573] = 8'h00; ram[574] = 8'he5; ram[575] = 8'h21;
ram[576] = 8'h0a; ram[577] = 8'h00; ram[578] = 8'hd1; ram[579] = 8'hcd;
ram[580] = 8'h0e; ram[581] = 8'h01; ram[582] = 8'hd1; ram[583] = 8'hcd;
ram[584] = 8'h50; ram[585] = 8'h00; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'hcd; ram[591] = 8'h48;
ram[592] = 8'h00; ram[593] = 8'h7c; ram[594] = 8'hb5; ram[595] = 8'hca;
ram[596] = 8'h62; ram[597] = 8'h02; ram[598] = 8'h21; ram[599] = 8'h00;
ram[600] = 8'h00; ram[601] = 8'h39; ram[602] = 8'hcd; ram[603] = 8'h48;
ram[604] = 8'h00; ram[605] = 8'he5; ram[606] = 8'hcd; ram[607] = 8'h31;
ram[608] = 8'h02; ram[609] = 8'hc1; ram[610] = 8'h21; ram[611] = 8'h30;
ram[612] = 8'h00; ram[613] = 8'he5; ram[614] = 8'h21; ram[615] = 8'h06;
ram[616] = 8'h00; ram[617] = 8'h39; ram[618] = 8'hcd; ram[619] = 8'h48;
ram[620] = 8'h00; ram[621] = 8'he5; ram[622] = 8'h21; ram[623] = 8'h04;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h48;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'h21; ram[631] = 8'h0a;
ram[632] = 8'h00; ram[633] = 8'hd1; ram[634] = 8'hcd; ram[635] = 8'hee;
ram[636] = 8'h00; ram[637] = 8'hd1; ram[638] = 8'hcd; ram[639] = 8'hdb;
ram[640] = 8'h00; ram[641] = 8'hd1; ram[642] = 8'h19; ram[643] = 8'he5;
ram[644] = 8'hcd; ram[645] = 8'h6c; ram[646] = 8'h01; ram[647] = 8'hc1;
ram[648] = 8'hc1; ram[649] = 8'hc9; ram[650] = 8'hc5; ram[651] = 8'h21;
ram[652] = 8'h00; ram[653] = 8'h00; ram[654] = 8'h39; ram[655] = 8'he5;
ram[656] = 8'h21; ram[657] = 8'h06; ram[658] = 8'h00; ram[659] = 8'h39;
ram[660] = 8'hcd; ram[661] = 8'h48; ram[662] = 8'h00; ram[663] = 8'he5;
ram[664] = 8'h21; ram[665] = 8'h10; ram[666] = 8'h00; ram[667] = 8'hd1;
ram[668] = 8'hcd; ram[669] = 8'h0e; ram[670] = 8'h01; ram[671] = 8'hd1;
ram[672] = 8'hcd; ram[673] = 8'h50; ram[674] = 8'h00; ram[675] = 8'h21;
ram[676] = 8'h00; ram[677] = 8'h00; ram[678] = 8'h39; ram[679] = 8'hcd;
ram[680] = 8'h48; ram[681] = 8'h00; ram[682] = 8'h7c; ram[683] = 8'hb5;
ram[684] = 8'hca; ram[685] = 8'hbb; ram[686] = 8'h02; ram[687] = 8'h21;
ram[688] = 8'h00; ram[689] = 8'h00; ram[690] = 8'h39; ram[691] = 8'hcd;
ram[692] = 8'h48; ram[693] = 8'h00; ram[694] = 8'he5; ram[695] = 8'hcd;
ram[696] = 8'h8a; ram[697] = 8'h02; ram[698] = 8'hc1; ram[699] = 8'h21;
ram[700] = 8'h00; ram[701] = 8'h00; ram[702] = 8'h39; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h06; ram[706] = 8'h00; ram[707] = 8'h39;
ram[708] = 8'hcd; ram[709] = 8'h48; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'h21; ram[713] = 8'h04; ram[714] = 8'h00; ram[715] = 8'h39;
ram[716] = 8'hcd; ram[717] = 8'h48; ram[718] = 8'h00; ram[719] = 8'he5;
ram[720] = 8'h21; ram[721] = 8'h10; ram[722] = 8'h00; ram[723] = 8'hd1;
ram[724] = 8'hcd; ram[725] = 8'hee; ram[726] = 8'h00; ram[727] = 8'hd1;
ram[728] = 8'hcd; ram[729] = 8'hdb; ram[730] = 8'h00; ram[731] = 8'hd1;
ram[732] = 8'hcd; ram[733] = 8'h50; ram[734] = 8'h00; ram[735] = 8'h21;
ram[736] = 8'h00; ram[737] = 8'h00; ram[738] = 8'h39; ram[739] = 8'hcd;
ram[740] = 8'h48; ram[741] = 8'h00; ram[742] = 8'he5; ram[743] = 8'h21;
ram[744] = 8'h09; ram[745] = 8'h00; ram[746] = 8'hd1; ram[747] = 8'hcd;
ram[748] = 8'h77; ram[749] = 8'h00; ram[750] = 8'h7c; ram[751] = 8'hb5;
ram[752] = 8'hca; ram[753] = 8'h10; ram[754] = 8'h03; ram[755] = 8'h21;
ram[756] = 8'h41; ram[757] = 8'h00; ram[758] = 8'he5; ram[759] = 8'h21;
ram[760] = 8'h02; ram[761] = 8'h00; ram[762] = 8'h39; ram[763] = 8'hcd;
ram[764] = 8'h48; ram[765] = 8'h00; ram[766] = 8'hd1; ram[767] = 8'h19;
ram[768] = 8'he5; ram[769] = 8'h21; ram[770] = 8'h0a; ram[771] = 8'h00;
ram[772] = 8'hd1; ram[773] = 8'hcd; ram[774] = 8'hdb; ram[775] = 8'h00;
ram[776] = 8'he5; ram[777] = 8'hcd; ram[778] = 8'h6c; ram[779] = 8'h01;
ram[780] = 8'hc1; ram[781] = 8'hc3; ram[782] = 8'h22; ram[783] = 8'h03;
ram[784] = 8'h21; ram[785] = 8'h30; ram[786] = 8'h00; ram[787] = 8'he5;
ram[788] = 8'h21; ram[789] = 8'h02; ram[790] = 8'h00; ram[791] = 8'h39;
ram[792] = 8'hcd; ram[793] = 8'h48; ram[794] = 8'h00; ram[795] = 8'hd1;
ram[796] = 8'h19; ram[797] = 8'he5; ram[798] = 8'hcd; ram[799] = 8'h6c;
ram[800] = 8'h01; ram[801] = 8'hc1; ram[802] = 8'hc1; ram[803] = 8'hc9;
ram[804] = 8'h21; ram[805] = 8'hd0; ram[806] = 8'h03; ram[807] = 8'he5;
ram[808] = 8'hcd; ram[809] = 8'hc4; ram[810] = 8'h01; ram[811] = 8'hc1;
ram[812] = 8'hcd; ram[813] = 8'hb3; ram[814] = 8'h01; ram[815] = 8'hc9;
ram[816] = 8'h21; ram[817] = 8'ha3; ram[818] = 8'h00; ram[819] = 8'h7d;
ram[820] = 8'hd3; ram[821] = 8'h81; ram[822] = 8'h21; ram[823] = 8'h00;
ram[824] = 8'h00; ram[825] = 8'h7d; ram[826] = 8'hd3; ram[827] = 8'h82;
ram[828] = 8'h21; ram[829] = 8'h00; ram[830] = 8'h00; ram[831] = 8'h7d;
ram[832] = 8'hd3; ram[833] = 8'h84; ram[834] = 8'h21; ram[835] = 8'hff;
ram[836] = 8'h00; ram[837] = 8'h7d; ram[838] = 8'hd3; ram[839] = 8'h85;
ram[840] = 8'h21; ram[841] = 8'h00; ram[842] = 8'h00; ram[843] = 8'h7d;
ram[844] = 8'hd3; ram[845] = 8'h86; ram[846] = 8'h21; ram[847] = 8'hff;
ram[848] = 8'h00; ram[849] = 8'h7d; ram[850] = 8'hd3; ram[851] = 8'h87;
ram[852] = 8'h21; ram[853] = 8'h01; ram[854] = 8'h00; ram[855] = 8'h7d;
ram[856] = 8'hd3; ram[857] = 8'h88; ram[858] = 8'hfb; ram[859] = 8'h21;
ram[860] = 8'hea; ram[861] = 8'h03; ram[862] = 8'he5; ram[863] = 8'hcd;
ram[864] = 8'hc4; ram[865] = 8'h01; ram[866] = 8'hc1; ram[867] = 8'hcd;
ram[868] = 8'hb3; ram[869] = 8'h01; ram[870] = 8'h21; ram[871] = 8'hf9;
ram[872] = 8'h03; ram[873] = 8'he5; ram[874] = 8'hcd; ram[875] = 8'hc4;
ram[876] = 8'h01; ram[877] = 8'hc1; ram[878] = 8'h21; ram[879] = 8'h2d;
ram[880] = 8'h04; ram[881] = 8'he5; ram[882] = 8'h21; ram[883] = 8'h01;
ram[884] = 8'h00; ram[885] = 8'h29; ram[886] = 8'hd1; ram[887] = 8'h19;
ram[888] = 8'hcd; ram[889] = 8'h48; ram[890] = 8'h00; ram[891] = 8'he5;
ram[892] = 8'hcd; ram[893] = 8'hf5; ram[894] = 8'h01; ram[895] = 8'hc1;
ram[896] = 8'hcd; ram[897] = 8'hb3; ram[898] = 8'h01; ram[899] = 8'h21;
ram[900] = 8'h05; ram[901] = 8'h04; ram[902] = 8'he5; ram[903] = 8'hcd;
ram[904] = 8'hc4; ram[905] = 8'h01; ram[906] = 8'hc1; ram[907] = 8'h21;
ram[908] = 8'h2d; ram[909] = 8'h04; ram[910] = 8'he5; ram[911] = 8'h21;
ram[912] = 8'h00; ram[913] = 8'h00; ram[914] = 8'h29; ram[915] = 8'hd1;
ram[916] = 8'h19; ram[917] = 8'hcd; ram[918] = 8'h48; ram[919] = 8'h00;
ram[920] = 8'he5; ram[921] = 8'hcd; ram[922] = 8'h8a; ram[923] = 8'h02;
ram[924] = 8'hc1; ram[925] = 8'hcd; ram[926] = 8'hb3; ram[927] = 8'h01;
ram[928] = 8'h21; ram[929] = 8'h01; ram[930] = 8'h00; ram[931] = 8'h7d;
ram[932] = 8'hd3; ram[933] = 8'h84; ram[934] = 8'h21; ram[935] = 8'h13;
ram[936] = 8'h04; ram[937] = 8'he5; ram[938] = 8'hcd; ram[939] = 8'hc4;
ram[940] = 8'h01; ram[941] = 8'hc1; ram[942] = 8'hcd; ram[943] = 8'hb3;
ram[944] = 8'h01; ram[945] = 8'h21; ram[946] = 8'h01; ram[947] = 8'h00;
ram[948] = 8'h7c; ram[949] = 8'hb5; ram[950] = 8'hca; ram[951] = 8'hcf;
ram[952] = 8'h03; ram[953] = 8'hcd; ram[954] = 8'h8c; ram[955] = 8'h01;
ram[956] = 8'h7c; ram[957] = 8'hb5; ram[958] = 8'hca; ram[959] = 8'hcc;
ram[960] = 8'h03; ram[961] = 8'h3a; ram[962] = 8'h2c; ram[963] = 8'h04;
ram[964] = 8'hcd; ram[965] = 8'h43; ram[966] = 8'h00; ram[967] = 8'he5;
ram[968] = 8'hcd; ram[969] = 8'h6c; ram[970] = 8'h01; ram[971] = 8'hc1;
ram[972] = 8'hc3; ram[973] = 8'hb1; ram[974] = 8'h03; ram[975] = 8'hc9;
ram[976] = 8'h49; ram[977] = 8'h6e; ram[978] = 8'h74; ram[979] = 8'h65;
ram[980] = 8'h72; ram[981] = 8'h72; ram[982] = 8'h75; ram[983] = 8'h70;
ram[984] = 8'h74; ram[985] = 8'h20; ram[986] = 8'h30; ram[987] = 8'h20;
ram[988] = 8'h77; ram[989] = 8'h61; ram[990] = 8'h73; ram[991] = 8'h20;
ram[992] = 8'h61; ram[993] = 8'h73; ram[994] = 8'h73; ram[995] = 8'h65;
ram[996] = 8'h72; ram[997] = 8'h74; ram[998] = 8'h65; ram[999] = 8'h64;
ram[1000] = 8'h2e; ram[1001] = 8'h00; ram[1002] = 8'h48; ram[1003] = 8'h65;
ram[1004] = 8'h6c; ram[1005] = 8'h6c; ram[1006] = 8'h6f; ram[1007] = 8'h20;
ram[1008] = 8'h57; ram[1009] = 8'h6f; ram[1010] = 8'h72; ram[1011] = 8'h6c;
ram[1012] = 8'h64; ram[1013] = 8'h21; ram[1014] = 8'h21; ram[1015] = 8'h21;
ram[1016] = 8'h00; ram[1017] = 8'h44; ram[1018] = 8'h65; ram[1019] = 8'h63;
ram[1020] = 8'h20; ram[1021] = 8'h76; ram[1022] = 8'h61; ram[1023] = 8'h6c;
ram[1024] = 8'h75; ram[1025] = 8'h65; ram[1026] = 8'h3a; ram[1027] = 8'h20;
ram[1028] = 8'h00; ram[1029] = 8'h48; ram[1030] = 8'h65; ram[1031] = 8'h78;
ram[1032] = 8'h20; ram[1033] = 8'h76; ram[1034] = 8'h61; ram[1035] = 8'h6c;
ram[1036] = 8'h75; ram[1037] = 8'h65; ram[1038] = 8'h3a; ram[1039] = 8'h20;
ram[1040] = 8'h30; ram[1041] = 8'h78; ram[1042] = 8'h00; ram[1043] = 8'h45;
ram[1044] = 8'h63; ram[1045] = 8'h68; ram[1046] = 8'h6f; ram[1047] = 8'h69;
ram[1048] = 8'h6e; ram[1049] = 8'h67; ram[1050] = 8'h20; ram[1051] = 8'h72;
ram[1052] = 8'h65; ram[1053] = 8'h63; ram[1054] = 8'h65; ram[1055] = 8'h69;
ram[1056] = 8'h76; ram[1057] = 8'h65; ram[1058] = 8'h64; ram[1059] = 8'h20;
ram[1060] = 8'h62; ram[1061] = 8'h79; ram[1062] = 8'h74; ram[1063] = 8'h65;
ram[1064] = 8'h73; ram[1065] = 8'h3a; ram[1066] = 8'h20; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'hd2; ram[1070] = 8'h04; ram[1071] = 8'h2e;
ram[1072] = 8'h16; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[1076] = 8'h00; ram[1077] = 8'h00; ram[1078] = 8'h00; ram[1079] = 8'h00;
ram[1080] = 8'h00; ram[1081] = 8'h00; ram[1082] = 8'h00; ram[1083] = 8'h00;
ram[1084] = 8'h00; ram[1085] = 8'h00; ram[1086] = 8'h00; ram[1087] = 8'h00;
ram[1088] = 8'h00; ram[1089] = 8'h00; ram[1090] = 8'h00; ram[1091] = 8'h00;
ram[1092] = 8'h00; ram[1093] = 8'h00; ram[1094] = 8'h00; ram[1095] = 8'h00;
ram[1096] = 8'h00; ram[1097] = 8'h00; ram[1098] = 8'h00; ram[1099] = 8'h00;
end
always @(posedge clk)
begin
if (we)
begin
ram[addr] <= din;
dout <= din;
end
else
dout <= ram[addr];
end
endmodule | 0 |
141,893 | data/full_repos/permissive/96181301/quartus/lite8080/top.v | 96,181,301 | top.v | v | 213 | 90 | [] | [] | [] | [(20, 212)] | null | null | 1: b"%Error: data/full_repos/permissive/96181301/quartus/lite8080/top.v:69: Cannot find file containing module: 'light8080'\nlight8080 cpu \n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/lite8080,data/full_repos/permissive/96181301/light8080\n data/full_repos/permissive/96181301/quartus/lite8080,data/full_repos/permissive/96181301/light8080.v\n data/full_repos/permissive/96181301/quartus/lite8080,data/full_repos/permissive/96181301/light8080.sv\n light8080\n light8080.v\n light8080.sv\n obj_dir/light8080\n obj_dir/light8080.v\n obj_dir/light8080.sv\n%Error: data/full_repos/permissive/96181301/quartus/lite8080/top.v:90: Cannot find file containing module: 'ram_image'\nram_image ram \n^~~~~~~~~\n%Error: data/full_repos/permissive/96181301/quartus/lite8080/top.v:161: Cannot find file containing module: 'intr_ctrl'\nintr_ctrl intrc \n^~~~~~~~~\n%Error: data/full_repos/permissive/96181301/quartus/lite8080/top.v:177: Cannot find file containing module: 'uart'\nuart uart \n^~~~\n%Error: Exiting due to 4 error(s)\n" | 312,629 | module | module top (
clock, reset,
txd, rxd,
p1dio, p2dio,
extint
);
input clock;
input reset;
output txd;
input rxd;
inout [7:0] p1dio;
inout [7:0] p2dio;
input [3:0] extint;
`define UDATA_REG 8'h80
`define UBAUDL_REG 8'h81
`define UBAUDH_REG 8'h82
`define USTAT_REG 8'h83
`define P1_DATA_REG 8'h84
`define P1_DIR_REG 8'h85
`define P2_DATA_REG 8'h86
`define P2_DIR_REG 8'h87
`define INTR_EN_REG 8'h88
wire [15:0] cpu_addr;
wire [7:0] cpu_din, cpu_dout, ram_dout, intr_dout;
wire cpu_io, cpu_rd, cpu_wr, cpu_inta, cpu_inte, cpu_intr;
wire [7:0] txData, rxData;
wire txValid, txBusy, rxValid;
reg [15:0] uartbaud;
reg rxfull, scpu_io;
reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
reg [3:0] intr_ena;
light8080 cpu
(
.clk(clock),
.reset(reset),
.addr_out(cpu_addr),
.vma(),
.io(cpu_io),
.rd(cpu_rd),
.wr(cpu_wr),
.fetch(),
.data_in(cpu_din),
.data_out(cpu_dout),
.inta(cpu_inta),
.inte(cpu_inte),
.halt(),
.intr(cpu_intr)
);
assign cpu_din = (cpu_inta) ? intr_dout : (scpu_io) ? io_dout : ram_dout;
ram_image ram
(
.clk(clock),
.addr(cpu_addr[11:0]),
.we(cpu_wr & ~cpu_io),
.din(cpu_dout),
.dout(ram_dout)
);
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
uartbaud <= 16'b0;
rxfull <= 1'b0;
p1reg <= 8'b0;
p1dir <= 8'b0;
p2reg <= 8'b0;
p2dir <= 8'b0;
intr_ena <= 4'b0;
end
else
begin
if (cpu_wr && cpu_io)
begin
if (cpu_addr[7:0] == `UBAUDL_REG) uartbaud[7:0] <= cpu_dout;
if (cpu_addr[7:0] == `UBAUDH_REG) uartbaud[15:8] <= cpu_dout;
if (cpu_addr[7:0] == `P1_DATA_REG) p1reg <= cpu_dout;
if (cpu_addr[7:0] == `P1_DIR_REG) p1dir <= cpu_dout;
if (cpu_addr[7:0] == `P2_DATA_REG) p2reg <= cpu_dout;
if (cpu_addr[7:0] == `P2_DIR_REG) p2dir <= cpu_dout;
if (cpu_addr[7:0] == `INTR_EN_REG) intr_ena <= cpu_dout[3:0];
end
if (rxValid && !rxfull)
rxfull <= 1'b1;
else if (cpu_rd && cpu_io && (cpu_addr[7:0] == `UDATA_REG) && rxfull)
rxfull <= 1'b0;
end
end
assign txValid = cpu_wr & cpu_io & (cpu_addr[7:0] == `UDATA_REG);
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
io_dout <= 8'b0;
end
else
begin
if (cpu_io && (cpu_addr[7:0] == `UDATA_REG))
io_dout <= rxData;
else if (cpu_io && (cpu_addr[7:0] == `USTAT_REG))
io_dout <= {3'b0, rxfull, 3'b0, txBusy};
else if (cpu_io && (cpu_addr[7:0] == `P1_DATA_REG))
io_dout <= p1dio;
else if (cpu_io && (cpu_addr[7:0] == `P2_DATA_REG))
io_dout <= p2dio;
scpu_io <= cpu_io;
end
end
intr_ctrl intrc
(
.clock(clock),
.reset(reset),
.ext_intr(0),
.cpu_intr(cpu_intr),
.cpu_inte(cpu_inte),
.cpu_inta(cpu_inta),
.cpu_rd(cpu_rd),
.cpu_inst(intr_dout),
.intr_ena(intr_ena)
);
uart uart
(
.clock(clock),
.reset(reset),
.serIn(rxd),
.serOut(txd),
.txData(cpu_dout),
.txValid(txValid),
.txBusy(txBusy),
.txDone(),
.rxData(rxData),
.rxValid(rxValid),
.baudDiv(uartbaud)
);
assign p1dio[0] = p1dir[0] ? p1reg[0] : 1'bz;
assign p1dio[1] = p1dir[1] ? p1reg[1] : 1'bz;
assign p1dio[2] = p1dir[2] ? p1reg[2] : 1'bz;
assign p1dio[3] = p1dir[3] ? p1reg[3] : 1'bz;
assign p1dio[4] = p1dir[4] ? p1reg[4] : 1'bz;
assign p1dio[5] = p1dir[5] ? p1reg[5] : 1'bz;
assign p1dio[6] = p1dir[6] ? p1reg[6] : 1'bz;
assign p1dio[7] = p1dir[7] ? p1reg[7] : 1'bz;
assign p2dio[0] = p2dir[0] ? p2reg[0] : 1'bz;
assign p2dio[1] = p2dir[1] ? p2reg[1] : 1'bz;
assign p2dio[2] = p2dir[2] ? p2reg[2] : 1'bz;
assign p2dio[3] = p2dir[3] ? p2reg[3] : 1'bz;
assign p2dio[4] = p2dir[4] ? p2reg[4] : 1'bz;
assign p2dio[5] = p2dir[5] ? p2reg[5] : 1'bz;
assign p2dio[6] = p2dir[6] ? p2reg[6] : 1'bz;
assign p2dio[7] = p2dir[7] ? p2reg[7] : 1'bz;
endmodule | module top (
clock, reset,
txd, rxd,
p1dio, p2dio,
extint
); |
input clock;
input reset;
output txd;
input rxd;
inout [7:0] p1dio;
inout [7:0] p2dio;
input [3:0] extint;
`define UDATA_REG 8'h80
`define UBAUDL_REG 8'h81
`define UBAUDH_REG 8'h82
`define USTAT_REG 8'h83
`define P1_DATA_REG 8'h84
`define P1_DIR_REG 8'h85
`define P2_DATA_REG 8'h86
`define P2_DIR_REG 8'h87
`define INTR_EN_REG 8'h88
wire [15:0] cpu_addr;
wire [7:0] cpu_din, cpu_dout, ram_dout, intr_dout;
wire cpu_io, cpu_rd, cpu_wr, cpu_inta, cpu_inte, cpu_intr;
wire [7:0] txData, rxData;
wire txValid, txBusy, rxValid;
reg [15:0] uartbaud;
reg rxfull, scpu_io;
reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
reg [3:0] intr_ena;
light8080 cpu
(
.clk(clock),
.reset(reset),
.addr_out(cpu_addr),
.vma(),
.io(cpu_io),
.rd(cpu_rd),
.wr(cpu_wr),
.fetch(),
.data_in(cpu_din),
.data_out(cpu_dout),
.inta(cpu_inta),
.inte(cpu_inte),
.halt(),
.intr(cpu_intr)
);
assign cpu_din = (cpu_inta) ? intr_dout : (scpu_io) ? io_dout : ram_dout;
ram_image ram
(
.clk(clock),
.addr(cpu_addr[11:0]),
.we(cpu_wr & ~cpu_io),
.din(cpu_dout),
.dout(ram_dout)
);
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
uartbaud <= 16'b0;
rxfull <= 1'b0;
p1reg <= 8'b0;
p1dir <= 8'b0;
p2reg <= 8'b0;
p2dir <= 8'b0;
intr_ena <= 4'b0;
end
else
begin
if (cpu_wr && cpu_io)
begin
if (cpu_addr[7:0] == `UBAUDL_REG) uartbaud[7:0] <= cpu_dout;
if (cpu_addr[7:0] == `UBAUDH_REG) uartbaud[15:8] <= cpu_dout;
if (cpu_addr[7:0] == `P1_DATA_REG) p1reg <= cpu_dout;
if (cpu_addr[7:0] == `P1_DIR_REG) p1dir <= cpu_dout;
if (cpu_addr[7:0] == `P2_DATA_REG) p2reg <= cpu_dout;
if (cpu_addr[7:0] == `P2_DIR_REG) p2dir <= cpu_dout;
if (cpu_addr[7:0] == `INTR_EN_REG) intr_ena <= cpu_dout[3:0];
end
if (rxValid && !rxfull)
rxfull <= 1'b1;
else if (cpu_rd && cpu_io && (cpu_addr[7:0] == `UDATA_REG) && rxfull)
rxfull <= 1'b0;
end
end
assign txValid = cpu_wr & cpu_io & (cpu_addr[7:0] == `UDATA_REG);
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
io_dout <= 8'b0;
end
else
begin
if (cpu_io && (cpu_addr[7:0] == `UDATA_REG))
io_dout <= rxData;
else if (cpu_io && (cpu_addr[7:0] == `USTAT_REG))
io_dout <= {3'b0, rxfull, 3'b0, txBusy};
else if (cpu_io && (cpu_addr[7:0] == `P1_DATA_REG))
io_dout <= p1dio;
else if (cpu_io && (cpu_addr[7:0] == `P2_DATA_REG))
io_dout <= p2dio;
scpu_io <= cpu_io;
end
end
intr_ctrl intrc
(
.clock(clock),
.reset(reset),
.ext_intr(0),
.cpu_intr(cpu_intr),
.cpu_inte(cpu_inte),
.cpu_inta(cpu_inta),
.cpu_rd(cpu_rd),
.cpu_inst(intr_dout),
.intr_ena(intr_ena)
);
uart uart
(
.clock(clock),
.reset(reset),
.serIn(rxd),
.serOut(txd),
.txData(cpu_dout),
.txValid(txValid),
.txBusy(txBusy),
.txDone(),
.rxData(rxData),
.rxValid(rxValid),
.baudDiv(uartbaud)
);
assign p1dio[0] = p1dir[0] ? p1reg[0] : 1'bz;
assign p1dio[1] = p1dir[1] ? p1reg[1] : 1'bz;
assign p1dio[2] = p1dir[2] ? p1reg[2] : 1'bz;
assign p1dio[3] = p1dir[3] ? p1reg[3] : 1'bz;
assign p1dio[4] = p1dir[4] ? p1reg[4] : 1'bz;
assign p1dio[5] = p1dir[5] ? p1reg[5] : 1'bz;
assign p1dio[6] = p1dir[6] ? p1reg[6] : 1'bz;
assign p1dio[7] = p1dir[7] ? p1reg[7] : 1'bz;
assign p2dio[0] = p2dir[0] ? p2reg[0] : 1'bz;
assign p2dio[1] = p2dir[1] ? p2reg[1] : 1'bz;
assign p2dio[2] = p2dir[2] ? p2reg[2] : 1'bz;
assign p2dio[3] = p2dir[3] ? p2reg[3] : 1'bz;
assign p2dio[4] = p2dir[4] ? p2reg[4] : 1'bz;
assign p2dio[5] = p2dir[5] ? p2reg[5] : 1'bz;
assign p2dio[6] = p2dir[6] ? p2reg[6] : 1'bz;
assign p2dio[7] = p2dir[7] ? p2reg[7] : 1'bz;
endmodule | 0 |
141,894 | data/full_repos/permissive/96181301/quartus/lite8080/uart.v | 96,181,301 | uart.v | v | 195 | 100 | [] | [] | [] | [(6, 191)] | null | data/verilator_xmls/b8316f26-9c5e-4f40-a8cb-4a991521295f.xml | null | 312,630 | module | module uart
(
clock, reset,
serIn, serOut,
txData, txValid,
txBusy, txDone,
rxData, rxValid,
baudDiv
);
input clock;
input reset;
input serIn;
output serOut;
input [7:0] txData;
input txValid;
output txBusy;
output txDone;
output [7:0] rxData;
output rxValid;
input [15:0] baudDiv;
reg serOut, txBusy, txDone, rxValid;
reg [7:0] rxData;
reg [8:0] txShiftReg;
reg [7:0] rxShiftReg;
reg [3:0] txBaudCnt, txBitCnt, rxBaudCnt, rxBitCnt;
reg [15:0] baudCount;
reg baudCE16, sserIn, rxBusy;
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
txBusy <= 1'b0;
txDone <= 1'b0;
txShiftReg <= 9'b0;
serOut <= 1'b1;
txBaudCnt <= 4'b0;
txBitCnt <= 4'b0;
end
else if (!txBusy)
begin
if (txValid)
begin
txShiftReg <= {txData, 1'b0};
txBusy <= 1'b1;
end
serOut <= 1'b1;
txDone <= 1'b0;
txBaudCnt <= 4'b0;
txBitCnt <= 4'b0;
end
else if (baudCE16)
begin
if (txBaudCnt == 4'b0)
begin
if (txBitCnt == 4'd10)
begin
txBusy <= 1'b0;
txDone <= 1'b1;
end
txBitCnt <= txBitCnt + 4'd1;
serOut <= txShiftReg[0];
txShiftReg <= {1'b1, txShiftReg[8:1]};
end
txBaudCnt <= txBaudCnt + 4'd1;
end
end
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
rxBusy <= 1'b0;
rxShiftReg <= 8'b0;
rxBaudCnt <= 4'b0;
rxBitCnt <= 4'b0;
rxData <= 8'b0;
rxValid <= 1'b0;
end
else if (!rxBusy)
begin
if (!sserIn && baudCE16)
begin
if (rxBaudCnt == 4'd7)
begin
rxBusy <= 1'b1;
rxBaudCnt <= 4'b0;
end
else
rxBaudCnt <= rxBaudCnt + 4'd1;
end
rxBitCnt <= 4'b0;
rxValid <= 1'b0;
end
else if (baudCE16)
begin
if (rxBaudCnt == 4'd15)
begin
rxShiftReg <= {sserIn, rxShiftReg[7:1]};
rxBitCnt <= rxBitCnt + 4'd1;
if (rxBitCnt == 4'd8)
begin
rxData <= rxShiftReg;
rxValid <= 1'b1;
rxBusy <= 1'b0;
end
end
rxBaudCnt <= rxBaudCnt + 4'd1;
end
end
always @ (posedge reset or posedge clock)
begin
if (reset)
sserIn <= 1'b0;
else
sserIn <= serIn;
end
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
baudCount <= 16'b0;
baudCE16 <= 1'b0;
end
else if (baudCount == baudDiv)
begin
baudCount <= 16'b0;
baudCE16 <= 1'b1;
end
else
begin
baudCount <= baudCount + 16'd1;
baudCE16 <= 1'b0;
end
end
endmodule | module uart
(
clock, reset,
serIn, serOut,
txData, txValid,
txBusy, txDone,
rxData, rxValid,
baudDiv
); |
input clock;
input reset;
input serIn;
output serOut;
input [7:0] txData;
input txValid;
output txBusy;
output txDone;
output [7:0] rxData;
output rxValid;
input [15:0] baudDiv;
reg serOut, txBusy, txDone, rxValid;
reg [7:0] rxData;
reg [8:0] txShiftReg;
reg [7:0] rxShiftReg;
reg [3:0] txBaudCnt, txBitCnt, rxBaudCnt, rxBitCnt;
reg [15:0] baudCount;
reg baudCE16, sserIn, rxBusy;
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
txBusy <= 1'b0;
txDone <= 1'b0;
txShiftReg <= 9'b0;
serOut <= 1'b1;
txBaudCnt <= 4'b0;
txBitCnt <= 4'b0;
end
else if (!txBusy)
begin
if (txValid)
begin
txShiftReg <= {txData, 1'b0};
txBusy <= 1'b1;
end
serOut <= 1'b1;
txDone <= 1'b0;
txBaudCnt <= 4'b0;
txBitCnt <= 4'b0;
end
else if (baudCE16)
begin
if (txBaudCnt == 4'b0)
begin
if (txBitCnt == 4'd10)
begin
txBusy <= 1'b0;
txDone <= 1'b1;
end
txBitCnt <= txBitCnt + 4'd1;
serOut <= txShiftReg[0];
txShiftReg <= {1'b1, txShiftReg[8:1]};
end
txBaudCnt <= txBaudCnt + 4'd1;
end
end
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
rxBusy <= 1'b0;
rxShiftReg <= 8'b0;
rxBaudCnt <= 4'b0;
rxBitCnt <= 4'b0;
rxData <= 8'b0;
rxValid <= 1'b0;
end
else if (!rxBusy)
begin
if (!sserIn && baudCE16)
begin
if (rxBaudCnt == 4'd7)
begin
rxBusy <= 1'b1;
rxBaudCnt <= 4'b0;
end
else
rxBaudCnt <= rxBaudCnt + 4'd1;
end
rxBitCnt <= 4'b0;
rxValid <= 1'b0;
end
else if (baudCE16)
begin
if (rxBaudCnt == 4'd15)
begin
rxShiftReg <= {sserIn, rxShiftReg[7:1]};
rxBitCnt <= rxBitCnt + 4'd1;
if (rxBitCnt == 4'd8)
begin
rxData <= rxShiftReg;
rxValid <= 1'b1;
rxBusy <= 1'b0;
end
end
rxBaudCnt <= rxBaudCnt + 4'd1;
end
end
always @ (posedge reset or posedge clock)
begin
if (reset)
sserIn <= 1'b0;
else
sserIn <= serIn;
end
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
baudCount <= 16'b0;
baudCE16 <= 1'b0;
end
else if (baudCount == baudDiv)
begin
baudCount <= 16'b0;
baudCE16 <= 1'b1;
end
else
begin
baudCount <= baudCount + 16'd1;
baudCE16 <= 1'b0;
end
end
endmodule | 0 |
141,895 | data/full_repos/permissive/96181301/quartus/mini-sramtest/bram.v | 96,181,301 | bram.v | v | 54 | 59 | [] | [] | [] | null | line:37: before: "]" | data/verilator_xmls/d2468e19-9bba-43b7-8460-98ec90c3fb30.xml | null | 312,631 | module | module BramCtrl (
clk,
reset_l,
sram_req,
sram_addr,
sram_rh_wl,
sram_data_w,
sram_data_r,
sram_data_r_en,
zs_oe_n,
zs_cs_n,
zs_we_n,
zs_addr,
zs_dq
);
parameter ADDR_WIDTH = 19;
parameter DATA_WIDTH = 8;
input clk, reset_l, sram_req;
input sram_rh_wl;
input [ADDR_WIDTH-1:0] sram_addr;
input [DATA_WIDTH-1:0] sram_data_w;
output sram_data_r_en;
output [DATA_WIDTH-1:0] sram_data_r;
output zs_oe_n, zs_cs_n, zs_we_n;
output [ADDR_WIDTH-1:0] zs_addr;
inout [DATA_WIDTH-1:0] zs_dq;
reg [7:0] data_r, mem [16384];
always @(posedge clk) begin
if (sram_req && sram_rh_wl == 0)
mem[sram_addr[13:0]] <= sram_data_w;
data_r <= mem[sram_addr[13:0]];
end
assign sram_data_r = data_r;
reg valid;
always @(posedge clk)
valid <= sram_req;
assign sram_data_r_en = valid;
assign zs_oe_n = 1, zs_cs_n = 1, zs_we_n = 1, zs_addr = 0;
endmodule | module BramCtrl (
clk,
reset_l,
sram_req,
sram_addr,
sram_rh_wl,
sram_data_w,
sram_data_r,
sram_data_r_en,
zs_oe_n,
zs_cs_n,
zs_we_n,
zs_addr,
zs_dq
); |
parameter ADDR_WIDTH = 19;
parameter DATA_WIDTH = 8;
input clk, reset_l, sram_req;
input sram_rh_wl;
input [ADDR_WIDTH-1:0] sram_addr;
input [DATA_WIDTH-1:0] sram_data_w;
output sram_data_r_en;
output [DATA_WIDTH-1:0] sram_data_r;
output zs_oe_n, zs_cs_n, zs_we_n;
output [ADDR_WIDTH-1:0] zs_addr;
inout [DATA_WIDTH-1:0] zs_dq;
reg [7:0] data_r, mem [16384];
always @(posedge clk) begin
if (sram_req && sram_rh_wl == 0)
mem[sram_addr[13:0]] <= sram_data_w;
data_r <= mem[sram_addr[13:0]];
end
assign sram_data_r = data_r;
reg valid;
always @(posedge clk)
valid <= sram_req;
assign sram_data_r_en = valid;
assign zs_oe_n = 1, zs_cs_n = 1, zs_we_n = 1, zs_addr = 0;
endmodule | 0 |
141,896 | data/full_repos/permissive/96181301/quartus/mini-sramtest/spipeek.v | 96,181,301 | spipeek.v | v | 44 | 80 | [] | [] | [] | [(3, 43)] | null | data/verilator_xmls/75aa24df-e136-44fa-bbed-8b6ba4cef46b.xml | null | 312,632 | module | module SpiPeek (
input clk,
input ucSCLK,
input ucMOSI,
output ucMISO,
input ucSEL_,
input [WIDTH-1:0] data_in,
output reg [WIDTH-1:0] data_out
);
parameter WIDTH = 64;
reg [2:0] SCLKr; always @(posedge clk) SCLKr <= {SCLKr[1:0],ucSCLK&~ucSEL_};
wire SCLK_rising = SCLKr[2:1] == 2'b01;
reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0],ucSEL_};
wire SSEL_start = SSELr[2:1] == 2'b10;
wire SSEL_end = SSELr[2:1] == 2'b01;
reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0],ucMOSI};
wire MOSI_data = MOSIr[1];
reg [WIDTH-1:0] shifter;
always @(posedge clk) begin
if (SSEL_start)
shifter <= data_in;
if (SCLK_rising)
shifter <= {shifter[WIDTH-2:0],MOSI_data};
if (SSEL_end)
data_out <= shifter;
end
assign ucMISO = shifter[WIDTH-1];
endmodule | module SpiPeek (
input clk,
input ucSCLK,
input ucMOSI,
output ucMISO,
input ucSEL_,
input [WIDTH-1:0] data_in,
output reg [WIDTH-1:0] data_out
); |
parameter WIDTH = 64;
reg [2:0] SCLKr; always @(posedge clk) SCLKr <= {SCLKr[1:0],ucSCLK&~ucSEL_};
wire SCLK_rising = SCLKr[2:1] == 2'b01;
reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0],ucSEL_};
wire SSEL_start = SSELr[2:1] == 2'b10;
wire SSEL_end = SSELr[2:1] == 2'b01;
reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0],ucMOSI};
wire MOSI_data = MOSIr[1];
reg [WIDTH-1:0] shifter;
always @(posedge clk) begin
if (SSEL_start)
shifter <= data_in;
if (SCLK_rising)
shifter <= {shifter[WIDTH-2:0],MOSI_data};
if (SSEL_end)
data_out <= shifter;
end
assign ucMISO = shifter[WIDTH-1];
endmodule | 0 |
141,897 | data/full_repos/permissive/96181301/quartus/mini-sramtest/sram.v | 96,181,301 | sram.v | v | 122 | 75 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/mini-sramtest/sram.v:119: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'data_w_reg\' generates 8 bits.\n : ... In instance SramCtrl\nassign zs_dq = (~tri_reg) ? data_w_reg : 16\'bz;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/mini-sramtest/sram.v:119: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 16 bits.\n : ... In instance SramCtrl\nassign zs_dq = (~tri_reg) ? data_w_reg : 16\'bz;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,633 | module | module SramCtrl (
input wire clk, reset,
input wire sram_req, sram_rh_wl,
input wire [ADDR_WIDTH-1:0] sram_addr,
input wire [DATA_WIDTH-1:0] sram_data_w,
output reg sram_data_r_en,
output wire [DATA_WIDTH-1:0] sram_data_r, sram_data_ur,
output wire [ADDR_WIDTH-1:0] zs_addr,
output wire zs_cs_n, zs_we_n, zs_oe_n,
inout wire [DATA_WIDTH-1:0] zs_dq
);
parameter ADDR_WIDTH = 19;
parameter DATA_WIDTH = 8;
localparam [2:0] idle = 3'b000,
rd1 = 3'b001,
rd2 = 3'b010,
wr1 = 3'b011,
wr2 = 3'b100;
reg [2:0] state_reg, state_next;
reg [DATA_WIDTH-1:0] data_w_reg, data_w_next, data_r_reg, data_r_next;
reg [ADDR_WIDTH-1:0] addr_reg, addr_next;
reg we_buf, oe_buf, tri_buf;
reg we_reg, oe_reg, tri_reg;
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
addr_reg <= 0;
data_w_reg <= 0;
data_r_reg <= 0;
tri_reg <= 1'b1;
we_reg <= 1'b1;
oe_reg <= 1'b1;
end else begin
state_reg <= state_next;
addr_reg <= addr_next;
data_w_reg <= data_w_next;
data_r_reg <= data_r_next;
tri_reg <= tri_buf;
we_reg <= we_buf;
oe_reg <= oe_buf;
end
always @* begin
addr_next = addr_reg;
data_w_next = data_w_reg;
data_r_next = data_r_reg;
sram_data_r_en = 1'b0;
case (state_reg)
idle: begin
if (sram_req)
state_next = idle;
else begin
addr_next = sram_addr;
if (~sram_rh_wl) begin
state_next = wr1;
data_w_next = sram_data_w;
end else
state_next = rd1;
end
sram_data_r_en = 1'b1;
end
wr1:
state_next = wr2;
wr2:
state_next = idle;
rd1:
state_next = rd2;
rd2: begin
data_r_next = zs_dq;
state_next = idle;
end
default:
state_next = idle;
endcase
end
always @* begin
tri_buf = 1'b1;
we_buf = 1'b1;
oe_buf = 1'b1;
case (state_next)
idle:
oe_buf = 1'b1;
wr1: begin
tri_buf = 1'b0;
we_buf = 1'b0;
end
wr2:
tri_buf = 1'b0;
rd1:
oe_buf = 1'b0;
rd2:
oe_buf = 1'b0;
endcase
end
assign sram_data_r = data_r_reg;
assign sram_data_ur = zs_dq;
assign zs_we_n = we_reg;
assign zs_oe_n = oe_reg;
assign zs_addr = addr_reg;
assign zs_cs_n = 1'b0;
assign zs_dq = (~tri_reg) ? data_w_reg : 16'bz;
endmodule | module SramCtrl (
input wire clk, reset,
input wire sram_req, sram_rh_wl,
input wire [ADDR_WIDTH-1:0] sram_addr,
input wire [DATA_WIDTH-1:0] sram_data_w,
output reg sram_data_r_en,
output wire [DATA_WIDTH-1:0] sram_data_r, sram_data_ur,
output wire [ADDR_WIDTH-1:0] zs_addr,
output wire zs_cs_n, zs_we_n, zs_oe_n,
inout wire [DATA_WIDTH-1:0] zs_dq
); |
parameter ADDR_WIDTH = 19;
parameter DATA_WIDTH = 8;
localparam [2:0] idle = 3'b000,
rd1 = 3'b001,
rd2 = 3'b010,
wr1 = 3'b011,
wr2 = 3'b100;
reg [2:0] state_reg, state_next;
reg [DATA_WIDTH-1:0] data_w_reg, data_w_next, data_r_reg, data_r_next;
reg [ADDR_WIDTH-1:0] addr_reg, addr_next;
reg we_buf, oe_buf, tri_buf;
reg we_reg, oe_reg, tri_reg;
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
addr_reg <= 0;
data_w_reg <= 0;
data_r_reg <= 0;
tri_reg <= 1'b1;
we_reg <= 1'b1;
oe_reg <= 1'b1;
end else begin
state_reg <= state_next;
addr_reg <= addr_next;
data_w_reg <= data_w_next;
data_r_reg <= data_r_next;
tri_reg <= tri_buf;
we_reg <= we_buf;
oe_reg <= oe_buf;
end
always @* begin
addr_next = addr_reg;
data_w_next = data_w_reg;
data_r_next = data_r_reg;
sram_data_r_en = 1'b0;
case (state_reg)
idle: begin
if (sram_req)
state_next = idle;
else begin
addr_next = sram_addr;
if (~sram_rh_wl) begin
state_next = wr1;
data_w_next = sram_data_w;
end else
state_next = rd1;
end
sram_data_r_en = 1'b1;
end
wr1:
state_next = wr2;
wr2:
state_next = idle;
rd1:
state_next = rd2;
rd2: begin
data_r_next = zs_dq;
state_next = idle;
end
default:
state_next = idle;
endcase
end
always @* begin
tri_buf = 1'b1;
we_buf = 1'b1;
oe_buf = 1'b1;
case (state_next)
idle:
oe_buf = 1'b1;
wr1: begin
tri_buf = 1'b0;
we_buf = 1'b0;
end
wr2:
tri_buf = 1'b0;
rd1:
oe_buf = 1'b0;
rd2:
oe_buf = 1'b0;
endcase
end
assign sram_data_r = data_r_reg;
assign sram_data_ur = zs_dq;
assign zs_we_n = we_reg;
assign zs_oe_n = oe_reg;
assign zs_addr = addr_reg;
assign zs_cs_n = 1'b0;
assign zs_dq = (~tri_reg) ? data_w_reg : 16'bz;
endmodule | 0 |
141,898 | data/full_repos/permissive/96181301/quartus/mini-sramtest/top.v | 96,181,301 | top.v | v | 77 | 42 | [] | [] | [] | null | line:56: before: "." | null | 1: b"%Error: data/full_repos/permissive/96181301/quartus/mini-sramtest/top.v:41: Cannot find file containing module: 'pll'\npll U1 (\n^~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/mini-sramtest,data/full_repos/permissive/96181301/pll\n data/full_repos/permissive/96181301/quartus/mini-sramtest,data/full_repos/permissive/96181301/pll.v\n data/full_repos/permissive/96181301/quartus/mini-sramtest,data/full_repos/permissive/96181301/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/96181301/quartus/mini-sramtest/top.v:47: Cannot find file containing module: 'SpiPeek'\nSpiPeek U2 (\n^~~~~~~\n%Error: data/full_repos/permissive/96181301/quartus/mini-sramtest/top.v:58: Cannot find file containing module: 'SramCtrl'\nSramCtrl U3 (\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 312,634 | module | module top (
input clk,
output zs_oe_n,
output zs_cs_n,
output zs_we_n,
output [18:0] zs_addr,
inout [7:0] zs_dq,
input ucSEL_,
input ucSCLK,
input ucMOSI,
output ucMISO,
output [7:0] led
);
wire sram_req;
wire [18:0] sram_addr;
wire sram_rh_wl;
wire [7:0] sram_data_w;
wire [7:0] sram_data_r_lock;
wire [7:0] sram_data_r;
wire sram_data_r_en;
wire [31:0] ins = {
1'b0,
sram_data_r_en,
sram_data_r,
22'b1
};
wire [31:0] outs;
assign sram_req = outs[31];
assign sram_rh_wl = outs[30];
assign sram_data_w = outs[29:22];
assign led = outs[21:14];
assign sram_addr = outs[18:0];
wire c0, reset_l;
pll U1 (
.inclk0(clk),
.c0(c0),
.locked(reset_l)
);
SpiPeek U2 (
.clk(c0),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(ins),
.data_out(outs)
);
defparam U2.WIDTH = 32;
SramCtrl U3 (
.clk (c0),
.reset (~reset_l),
.sram_req (sram_req),
.sram_addr (sram_addr),
.sram_rh_wl (sram_rh_wl),
.sram_data_w (sram_data_w),
.sram_data_r (sram_data_r),
.sram_data_r_en (sram_data_r_en),
.zs_oe_n (zs_oe_n),
.zs_cs_n (zs_cs_n),
.zs_we_n (zs_we_n),
.zs_addr (zs_addr),
.zs_dq (zs_dq)
);
endmodule | module top (
input clk,
output zs_oe_n,
output zs_cs_n,
output zs_we_n,
output [18:0] zs_addr,
inout [7:0] zs_dq,
input ucSEL_,
input ucSCLK,
input ucMOSI,
output ucMISO,
output [7:0] led
); |
wire sram_req;
wire [18:0] sram_addr;
wire sram_rh_wl;
wire [7:0] sram_data_w;
wire [7:0] sram_data_r_lock;
wire [7:0] sram_data_r;
wire sram_data_r_en;
wire [31:0] ins = {
1'b0,
sram_data_r_en,
sram_data_r,
22'b1
};
wire [31:0] outs;
assign sram_req = outs[31];
assign sram_rh_wl = outs[30];
assign sram_data_w = outs[29:22];
assign led = outs[21:14];
assign sram_addr = outs[18:0];
wire c0, reset_l;
pll U1 (
.inclk0(clk),
.c0(c0),
.locked(reset_l)
);
SpiPeek U2 (
.clk(c0),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(ins),
.data_out(outs)
);
defparam U2.WIDTH = 32;
SramCtrl U3 (
.clk (c0),
.reset (~reset_l),
.sram_req (sram_req),
.sram_addr (sram_addr),
.sram_rh_wl (sram_rh_wl),
.sram_data_w (sram_data_w),
.sram_data_r (sram_data_r),
.sram_data_r_en (sram_data_r_en),
.zs_oe_n (zs_oe_n),
.zs_cs_n (zs_cs_n),
.zs_we_n (zs_we_n),
.zs_addr (zs_addr),
.zs_dq (zs_dq)
);
endmodule | 0 |
141,899 | data/full_repos/permissive/96181301/quartus/ringOsc/top.v | 96,181,301 | top.v | v | 13 | 53 | [] | [] | [] | null | line:8: before: "." | null | 1: b"%Error: data/full_repos/permissive/96181301/quartus/ringOsc/top.v:7: Cannot find file containing module: 'ring_counter'\nring_counter U1 (.clk(clk), .rst(0), .out(counter));\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/ringOsc,data/full_repos/permissive/96181301/ring_counter\n data/full_repos/permissive/96181301/quartus/ringOsc,data/full_repos/permissive/96181301/ring_counter.v\n data/full_repos/permissive/96181301/quartus/ringOsc,data/full_repos/permissive/96181301/ring_counter.sv\n ring_counter\n ring_counter.v\n ring_counter.sv\n obj_dir/ring_counter\n obj_dir/ring_counter.v\n obj_dir/ring_counter.sv\n%Error: Exiting due to 1 error(s)\n" | 312,637 | module | module top (
input clk,
output out
);
wire [15:0] counter;
ring_counter U1 (.clk(clk), .rst(0), .out(counter));
defparam U1.DELAY = 100;
assign out = counter[0];
endmodule | module top (
input clk,
output out
); |
wire [15:0] counter;
ring_counter U1 (.clk(clk), .rst(0), .out(counter));
defparam U1.DELAY = 100;
assign out = counter[0];
endmodule | 0 |
141,900 | data/full_repos/permissive/96181301/quartus/spiSim/top.v | 96,181,301 | top.v | v | 54 | 75 | [] | [] | [] | [(1, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/96181301/quartus/spiSim/top.v:15: Duplicate declaration of signal: 'sclk'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire sclk = !count[0];\n ^~~~\n data/full_repos/permissive/96181301/quartus/spiSim/top.v:7: ... Location of original declaration\n output sclk, mosi,\n ^~~~\n%Error: data/full_repos/permissive/96181301/quartus/spiSim/top.v:17: Duplicate declaration of signal: 'done'\nwire done = !active;\n ^~~~\n data/full_repos/permissive/96181301/quartus/spiSim/top.v:5: ... Location of original declaration\n output done,\n ^~~~\n%Error: data/full_repos/permissive/96181301/quartus/spiSim/top.v:18: Duplicate declaration of signal: 'data_out'\nwire data_out = shifter;\n ^~~~~~~~\n data/full_repos/permissive/96181301/quartus/spiSim/top.v:6: ... Location of original declaration\n output [7:0] data_out,\n ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 312,639 | module | module newspi (
input clk,
input wr,
input [7:0] data_in,
output done,
output [7:0] data_out,
output sclk, mosi,
input miso
);
reg [4:0] count;
reg [7:0] shifter;
reg active;
wire sclk = !count[0];
wire busy = count[4];
wire done = !active;
wire data_out = shifter;
wire active_n, mosi_n;
wire [7:0] shifter_n;
wire [4:0] count_n;
always @(*) begin
{ active_n,shifter_n,count_n,mosi_n } = { active,shifter,count,mosi };
case (active)
1'b0:
if (wr) begin
active_n = 1;
shifter_n = data_in;
count_n = 5'b10000;
end
1'b1: begin
if (busy)
count_n = count + 1;
else
active_n = 0;
if (sclk)
mosi_n = shifter[7];
else
shifter_n = { shifter[6:0], miso };
end
endcase
end
always @(posedge clk) begin
active <= active_n;
mosi <= mosi_n;
shifter <= shifter_n;
count <= count_n;
end
endmodule | module newspi (
input clk,
input wr,
input [7:0] data_in,
output done,
output [7:0] data_out,
output sclk, mosi,
input miso
); |
reg [4:0] count;
reg [7:0] shifter;
reg active;
wire sclk = !count[0];
wire busy = count[4];
wire done = !active;
wire data_out = shifter;
wire active_n, mosi_n;
wire [7:0] shifter_n;
wire [4:0] count_n;
always @(*) begin
{ active_n,shifter_n,count_n,mosi_n } = { active,shifter,count,mosi };
case (active)
1'b0:
if (wr) begin
active_n = 1;
shifter_n = data_in;
count_n = 5'b10000;
end
1'b1: begin
if (busy)
count_n = count + 1;
else
active_n = 0;
if (sclk)
mosi_n = shifter[7];
else
shifter_n = { shifter[6:0], miso };
end
endcase
end
always @(posedge clk) begin
active <= active_n;
mosi <= mosi_n;
shifter <= shifter_n;
count <= count_n;
end
endmodule | 0 |
141,901 | data/full_repos/permissive/96181301/quartus/starter-sdramtest/sdram.v | 96,181,301 | sdram.v | v | 318 | 78 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/starter-sdramtest/sdram.v:277: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n : ... In instance SdramCtrl\n zs_addr <= {1\'b0,1\'b0,2\'b00,CAS_LATENCY,4\'h0};\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/starter-sdramtest/sdram.v:293: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n : ... In instance SdramCtrl\n zs_addr <= sdram_addr[COL_WIDTH-1:0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/starter-sdramtest/sdram.v:303: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n : ... In instance SdramCtrl\n zs_addr <= sdram_addr[COL_WIDTH-1:0];\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,640 | module | module SdramCtrl (
clk,
reset_l,
sdram_req,
sdram_ack,
sdram_addr,
sdram_rh_wl,
sdram_data_w,
sdram_data_r,
sdram_data_r_en,
zs_ck,
zs_cke,
zs_cs_n,
zs_ras_n,
zs_cas_n,
zs_we_n,
zs_ba,
zs_addr,
zs_dqm,
zs_dq
);
parameter ADDR_WIDTH = 13;
parameter BANK_WIDTH = 2;
parameter ROW_WIDTH = 13;
parameter COL_WIDTH = 9;
parameter DATA_WIDTH = 16;
parameter CAS_LATENCY = 3'b011;
localparam ROWCOL_WIDTH = ROW_WIDTH + COL_WIDTH;
parameter AUTO_REFRESH_CYCLE = 390;
parameter POWERON_WAIT_CYCLE = 10000;
input clk, reset_l, sdram_req;
input sdram_rh_wl;
input [ROWCOL_WIDTH+BANK_WIDTH-1:0] sdram_addr;
input [DATA_WIDTH-1:0] sdram_data_w;
output sdram_ack;
output sdram_data_r_en;
output [DATA_WIDTH-1:0] sdram_data_r;
output zs_ck, zs_cke, zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n;
output [BANK_WIDTH-1:0] zs_ba;
output [ADDR_WIDTH-1:0] zs_addr;
output [1:0] zs_dqm;
inout [DATA_WIDTH-1:0] zs_dq;
wire zs_ck = clk, zs_cke = 1'b1, zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n;
reg [3:0] sdram_cmd;
reg [BANK_WIDTH-1:0] zs_ba;
reg [ADDR_WIDTH-1:0] zs_addr;
reg [1:0] zs_dqm;
reg zs_dq_o_en;
reg [DATA_WIDTH-1:0] zs_dq_o;
wire [DATA_WIDTH-1:0] zs_dq_i;
assign zs_dq = zs_dq_o_en == 1'b1 ? zs_dq_o : {DATA_WIDTH{1'bz}};
assign zs_dq_i = zs_dq;
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = sdram_cmd;
reg [DATA_WIDTH-1:0] sdram_data_r;
reg sdram_data_r_en;
reg sdram_ack;
localparam stat_poweron_wait = 8'b00000001;
localparam stat_precharge = 8'b00000010;
localparam stat_refresh = 8'b00000100;
localparam stat_mrs = 8'b00001000;
localparam stat_idle = 8'b00010000;
localparam stat_active_row = 8'b00100000;
localparam stat_read = 8'b01000000;
localparam stat_write = 8'b10000000;
reg [7:0] CUR_STATE;
reg [7:0] NEXT_STATE;
reg auto_refresh;
reg [15:0] auto_refresh_cnt;
reg poweron_wait_ok;
reg init_ok;
reg precharge_done;
reg refresh_done;
reg mrs_done;
reg active_row_done;
reg read_done;
reg write_done;
reg [15:0] poweron_wait_cnt;
reg [3:0] status_running_cnt;
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0)
CUR_STATE <= stat_poweron_wait;
else
CUR_STATE <= NEXT_STATE;
always @(*)
case (CUR_STATE)
stat_poweron_wait:
if (poweron_wait_ok == 1'b1)
NEXT_STATE <= stat_precharge;
else
NEXT_STATE <= stat_poweron_wait;
stat_precharge:
if (precharge_done == 1'b1)
if (init_ok == 1'b1)
NEXT_STATE <= stat_idle;
else
NEXT_STATE <= stat_refresh;
else
NEXT_STATE <= stat_precharge;
stat_refresh:
if (refresh_done == 1'b1)
if (init_ok == 1'b1)
NEXT_STATE <= stat_idle;
else
NEXT_STATE <= stat_mrs;
else
NEXT_STATE <= stat_refresh;
stat_mrs:
if (mrs_done == 1'b1)
NEXT_STATE <= stat_idle;
else
NEXT_STATE <= stat_mrs;
stat_idle: begin
if (auto_refresh == 1'b1)
NEXT_STATE <= stat_refresh;
else if (sdram_req == 1'b1)
NEXT_STATE <= stat_active_row;
else
NEXT_STATE <= stat_idle;
end
stat_active_row:
if (active_row_done == 1'b1)
if (sdram_rh_wl == 1'b1)
NEXT_STATE <= stat_read;
else
NEXT_STATE <= stat_write;
else
NEXT_STATE <= stat_active_row;
stat_read:
if (read_done == 1'b1)
NEXT_STATE <= stat_precharge;
else
NEXT_STATE <= stat_read;
stat_write:
if (write_done == 1'b1)
NEXT_STATE <= stat_precharge;
else
NEXT_STATE <= stat_write;
default:
NEXT_STATE <= stat_idle;
endcase
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0)
sdram_ack <= 1'b0;
else if (CUR_STATE == stat_active_row)
sdram_ack <= 1'b1;
else if (sdram_req == 1'b1)
sdram_ack <= 1'b0;
else
sdram_ack <= 1'b0;
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0) begin
poweron_wait_cnt <= 16'b0;
poweron_wait_ok <= 1'b0;
end else begin
poweron_wait_ok <= 1'b0;
if (CUR_STATE == stat_poweron_wait)
if (poweron_wait_cnt >= POWERON_WAIT_CYCLE)
poweron_wait_ok <= 1'b1;
else
poweron_wait_cnt <= poweron_wait_cnt + 16'b1;
else
poweron_wait_cnt <= 16'b0;
end
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0) begin
auto_refresh_cnt <= 16'b0;
auto_refresh <= 1'b0;
end else begin
if (auto_refresh == 1'b0)
auto_refresh_cnt <= auto_refresh_cnt + 16'b1;
else
auto_refresh_cnt <= 16'b0;
if (auto_refresh_cnt >= AUTO_REFRESH_CYCLE)
auto_refresh <= 1'b1;
else if (CUR_STATE == stat_refresh)
auto_refresh <= 1'b0;
end
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0)
status_running_cnt <= 4'b0;
else if (precharge_done || refresh_done || mrs_done ||
active_row_done || read_done || write_done)
status_running_cnt <= 4'b0;
else if (CUR_STATE == stat_precharge || CUR_STATE == stat_refresh ||
CUR_STATE == stat_mrs || CUR_STATE == stat_active_row ||
CUR_STATE == stat_read || CUR_STATE == stat_write)
status_running_cnt <= status_running_cnt + 4'b1;
else
status_running_cnt <= 4'b0;
always @(posedge clk or negedge reset_l) begin
if (reset_l == 1'b0) begin
sdram_cmd <= {4{1'b1}};
zs_ba <= {BANK_WIDTH{1'b0}};
zs_addr <= {ADDR_WIDTH{1'b0}};
zs_dqm <= 2'b0;
zs_dq_o_en <= 1'b0;
zs_dq_o <= {DATA_WIDTH{1'b0}};
init_ok <= 1'b0;
precharge_done <= 1'b0;
refresh_done <= 1'b0;
mrs_done <= 1'b0;
active_row_done <= 1'b0;
read_done <= 1'b0;
write_done <= 1'b0;
sdram_data_r_en <= 1'b0;
sdram_data_r <= {DATA_WIDTH{1'b0}};
end else begin
precharge_done <= 1'b0;
refresh_done <= 1'b0;
mrs_done <= 1'b0;
active_row_done <= 1'b0;
read_done <= 1'b0;
write_done <= 1'b0;
zs_ba <= sdram_addr[ROWCOL_WIDTH+BANK_WIDTH-1:ROWCOL_WIDTH];
zs_dq_o_en <= 1'b0;
sdram_data_r_en <= 1'b0;
case (CUR_STATE)
stat_precharge: begin
sdram_cmd <= 4'b0010;
zs_addr[10] <= 1'b1;
precharge_done <= 1'b1;
end
stat_refresh:
if (status_running_cnt == 4'b0)
sdram_cmd <= 4'b0001;
else begin
sdram_cmd <= 4'b0111;
if (status_running_cnt >= 4'd8)
refresh_done <= 1'b1;
end
stat_mrs:
if (status_running_cnt == 4'b0) begin
sdram_cmd <= 4'b0000;
zs_addr <= {1'b0,1'b0,2'b00,CAS_LATENCY,4'h0};
end else begin
sdram_cmd <= 4'b0111;
if (status_running_cnt >= 4'd3) begin
mrs_done <= 1'b1;
init_ok <= 1'b1;
end
end
stat_active_row: begin
sdram_cmd <= 4'b0011;
zs_addr <= sdram_addr[ROWCOL_WIDTH-1:COL_WIDTH];
active_row_done <= 1'b1;
end
stat_read:
if (status_running_cnt == 4'd0) begin
sdram_cmd <= 4'b0101;
zs_addr <= sdram_addr[COL_WIDTH-1:0];
end else if (status_running_cnt >= 4'd3) begin
read_done <= 1'b1;
sdram_data_r_en <= 1'b1;
sdram_data_r <= zs_dq_i;
end
stat_write: begin
zs_dq_o_en <= 1'b1;
if (status_running_cnt == 4'd0) begin
sdram_cmd <= 4'b0100;
zs_addr <= sdram_addr[COL_WIDTH-1:0];
zs_dq_o <= sdram_data_w;
end else if (status_running_cnt >= 4'd1)
write_done <= 1'b1;
end
stat_idle: begin
sdram_cmd <= 4'b1111;
zs_addr <= {ADDR_WIDTH{1'b0}};
end
default: ;
endcase
end
end
endmodule | module SdramCtrl (
clk,
reset_l,
sdram_req,
sdram_ack,
sdram_addr,
sdram_rh_wl,
sdram_data_w,
sdram_data_r,
sdram_data_r_en,
zs_ck,
zs_cke,
zs_cs_n,
zs_ras_n,
zs_cas_n,
zs_we_n,
zs_ba,
zs_addr,
zs_dqm,
zs_dq
); |
parameter ADDR_WIDTH = 13;
parameter BANK_WIDTH = 2;
parameter ROW_WIDTH = 13;
parameter COL_WIDTH = 9;
parameter DATA_WIDTH = 16;
parameter CAS_LATENCY = 3'b011;
localparam ROWCOL_WIDTH = ROW_WIDTH + COL_WIDTH;
parameter AUTO_REFRESH_CYCLE = 390;
parameter POWERON_WAIT_CYCLE = 10000;
input clk, reset_l, sdram_req;
input sdram_rh_wl;
input [ROWCOL_WIDTH+BANK_WIDTH-1:0] sdram_addr;
input [DATA_WIDTH-1:0] sdram_data_w;
output sdram_ack;
output sdram_data_r_en;
output [DATA_WIDTH-1:0] sdram_data_r;
output zs_ck, zs_cke, zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n;
output [BANK_WIDTH-1:0] zs_ba;
output [ADDR_WIDTH-1:0] zs_addr;
output [1:0] zs_dqm;
inout [DATA_WIDTH-1:0] zs_dq;
wire zs_ck = clk, zs_cke = 1'b1, zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n;
reg [3:0] sdram_cmd;
reg [BANK_WIDTH-1:0] zs_ba;
reg [ADDR_WIDTH-1:0] zs_addr;
reg [1:0] zs_dqm;
reg zs_dq_o_en;
reg [DATA_WIDTH-1:0] zs_dq_o;
wire [DATA_WIDTH-1:0] zs_dq_i;
assign zs_dq = zs_dq_o_en == 1'b1 ? zs_dq_o : {DATA_WIDTH{1'bz}};
assign zs_dq_i = zs_dq;
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = sdram_cmd;
reg [DATA_WIDTH-1:0] sdram_data_r;
reg sdram_data_r_en;
reg sdram_ack;
localparam stat_poweron_wait = 8'b00000001;
localparam stat_precharge = 8'b00000010;
localparam stat_refresh = 8'b00000100;
localparam stat_mrs = 8'b00001000;
localparam stat_idle = 8'b00010000;
localparam stat_active_row = 8'b00100000;
localparam stat_read = 8'b01000000;
localparam stat_write = 8'b10000000;
reg [7:0] CUR_STATE;
reg [7:0] NEXT_STATE;
reg auto_refresh;
reg [15:0] auto_refresh_cnt;
reg poweron_wait_ok;
reg init_ok;
reg precharge_done;
reg refresh_done;
reg mrs_done;
reg active_row_done;
reg read_done;
reg write_done;
reg [15:0] poweron_wait_cnt;
reg [3:0] status_running_cnt;
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0)
CUR_STATE <= stat_poweron_wait;
else
CUR_STATE <= NEXT_STATE;
always @(*)
case (CUR_STATE)
stat_poweron_wait:
if (poweron_wait_ok == 1'b1)
NEXT_STATE <= stat_precharge;
else
NEXT_STATE <= stat_poweron_wait;
stat_precharge:
if (precharge_done == 1'b1)
if (init_ok == 1'b1)
NEXT_STATE <= stat_idle;
else
NEXT_STATE <= stat_refresh;
else
NEXT_STATE <= stat_precharge;
stat_refresh:
if (refresh_done == 1'b1)
if (init_ok == 1'b1)
NEXT_STATE <= stat_idle;
else
NEXT_STATE <= stat_mrs;
else
NEXT_STATE <= stat_refresh;
stat_mrs:
if (mrs_done == 1'b1)
NEXT_STATE <= stat_idle;
else
NEXT_STATE <= stat_mrs;
stat_idle: begin
if (auto_refresh == 1'b1)
NEXT_STATE <= stat_refresh;
else if (sdram_req == 1'b1)
NEXT_STATE <= stat_active_row;
else
NEXT_STATE <= stat_idle;
end
stat_active_row:
if (active_row_done == 1'b1)
if (sdram_rh_wl == 1'b1)
NEXT_STATE <= stat_read;
else
NEXT_STATE <= stat_write;
else
NEXT_STATE <= stat_active_row;
stat_read:
if (read_done == 1'b1)
NEXT_STATE <= stat_precharge;
else
NEXT_STATE <= stat_read;
stat_write:
if (write_done == 1'b1)
NEXT_STATE <= stat_precharge;
else
NEXT_STATE <= stat_write;
default:
NEXT_STATE <= stat_idle;
endcase
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0)
sdram_ack <= 1'b0;
else if (CUR_STATE == stat_active_row)
sdram_ack <= 1'b1;
else if (sdram_req == 1'b1)
sdram_ack <= 1'b0;
else
sdram_ack <= 1'b0;
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0) begin
poweron_wait_cnt <= 16'b0;
poweron_wait_ok <= 1'b0;
end else begin
poweron_wait_ok <= 1'b0;
if (CUR_STATE == stat_poweron_wait)
if (poweron_wait_cnt >= POWERON_WAIT_CYCLE)
poweron_wait_ok <= 1'b1;
else
poweron_wait_cnt <= poweron_wait_cnt + 16'b1;
else
poweron_wait_cnt <= 16'b0;
end
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0) begin
auto_refresh_cnt <= 16'b0;
auto_refresh <= 1'b0;
end else begin
if (auto_refresh == 1'b0)
auto_refresh_cnt <= auto_refresh_cnt + 16'b1;
else
auto_refresh_cnt <= 16'b0;
if (auto_refresh_cnt >= AUTO_REFRESH_CYCLE)
auto_refresh <= 1'b1;
else if (CUR_STATE == stat_refresh)
auto_refresh <= 1'b0;
end
always @(posedge clk or negedge reset_l)
if (reset_l == 1'b0)
status_running_cnt <= 4'b0;
else if (precharge_done || refresh_done || mrs_done ||
active_row_done || read_done || write_done)
status_running_cnt <= 4'b0;
else if (CUR_STATE == stat_precharge || CUR_STATE == stat_refresh ||
CUR_STATE == stat_mrs || CUR_STATE == stat_active_row ||
CUR_STATE == stat_read || CUR_STATE == stat_write)
status_running_cnt <= status_running_cnt + 4'b1;
else
status_running_cnt <= 4'b0;
always @(posedge clk or negedge reset_l) begin
if (reset_l == 1'b0) begin
sdram_cmd <= {4{1'b1}};
zs_ba <= {BANK_WIDTH{1'b0}};
zs_addr <= {ADDR_WIDTH{1'b0}};
zs_dqm <= 2'b0;
zs_dq_o_en <= 1'b0;
zs_dq_o <= {DATA_WIDTH{1'b0}};
init_ok <= 1'b0;
precharge_done <= 1'b0;
refresh_done <= 1'b0;
mrs_done <= 1'b0;
active_row_done <= 1'b0;
read_done <= 1'b0;
write_done <= 1'b0;
sdram_data_r_en <= 1'b0;
sdram_data_r <= {DATA_WIDTH{1'b0}};
end else begin
precharge_done <= 1'b0;
refresh_done <= 1'b0;
mrs_done <= 1'b0;
active_row_done <= 1'b0;
read_done <= 1'b0;
write_done <= 1'b0;
zs_ba <= sdram_addr[ROWCOL_WIDTH+BANK_WIDTH-1:ROWCOL_WIDTH];
zs_dq_o_en <= 1'b0;
sdram_data_r_en <= 1'b0;
case (CUR_STATE)
stat_precharge: begin
sdram_cmd <= 4'b0010;
zs_addr[10] <= 1'b1;
precharge_done <= 1'b1;
end
stat_refresh:
if (status_running_cnt == 4'b0)
sdram_cmd <= 4'b0001;
else begin
sdram_cmd <= 4'b0111;
if (status_running_cnt >= 4'd8)
refresh_done <= 1'b1;
end
stat_mrs:
if (status_running_cnt == 4'b0) begin
sdram_cmd <= 4'b0000;
zs_addr <= {1'b0,1'b0,2'b00,CAS_LATENCY,4'h0};
end else begin
sdram_cmd <= 4'b0111;
if (status_running_cnt >= 4'd3) begin
mrs_done <= 1'b1;
init_ok <= 1'b1;
end
end
stat_active_row: begin
sdram_cmd <= 4'b0011;
zs_addr <= sdram_addr[ROWCOL_WIDTH-1:COL_WIDTH];
active_row_done <= 1'b1;
end
stat_read:
if (status_running_cnt == 4'd0) begin
sdram_cmd <= 4'b0101;
zs_addr <= sdram_addr[COL_WIDTH-1:0];
end else if (status_running_cnt >= 4'd3) begin
read_done <= 1'b1;
sdram_data_r_en <= 1'b1;
sdram_data_r <= zs_dq_i;
end
stat_write: begin
zs_dq_o_en <= 1'b1;
if (status_running_cnt == 4'd0) begin
sdram_cmd <= 4'b0100;
zs_addr <= sdram_addr[COL_WIDTH-1:0];
zs_dq_o <= sdram_data_w;
end else if (status_running_cnt >= 4'd1)
write_done <= 1'b1;
end
stat_idle: begin
sdram_cmd <= 4'b1111;
zs_addr <= {ADDR_WIDTH{1'b0}};
end
default: ;
endcase
end
end
endmodule | 0 |
141,902 | data/full_repos/permissive/96181301/quartus/starter-sdramtest/top.v | 96,181,301 | top.v | v | 89 | 42 | [] | [] | [] | [(1, 88)] | null | null | 1: b"%Error: data/full_repos/permissive/96181301/quartus/starter-sdramtest/top.v:49: Cannot find file containing module: 'pll'\npll U1 (\n^~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/starter-sdramtest,data/full_repos/permissive/96181301/pll\n data/full_repos/permissive/96181301/quartus/starter-sdramtest,data/full_repos/permissive/96181301/pll.v\n data/full_repos/permissive/96181301/quartus/starter-sdramtest,data/full_repos/permissive/96181301/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/96181301/quartus/starter-sdramtest/top.v:54: Cannot find file containing module: 'SpiPeek'\nSpiPeek U2 (\n^~~~~~~\n%Error: data/full_repos/permissive/96181301/quartus/starter-sdramtest/top.v:64: Cannot find file containing module: 'SdramCtrl'\nSdramCtrl U3 (\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 312,642 | module | module top (
input clk,
input reset,
output zs_ck,
output zs_cke,
output zs_cs_n,
output zs_ras_n,
output zs_cas_n,
output zs_we_n,
output [1:0] zs_ba,
output [12:0] zs_addr,
output [1:0] zs_dqm,
inout [ 15:0] zs_dq,
input ucSEL_,
input ucSCLK,
input ucMOSI,
output ucMISO,
output [7:0] led
);
wire sdram_req;
wire [23:0] sdram_addr;
wire sdram_rh_wl;
wire [15:0] sdram_data_w;
wire [15:0] sdram_data_r_lock;
wire [15:0] sdram_data_r;
wire sdram_data_r_en;
wire sdram_ack;
wire [63:0] ins = {
sdram_ack,
sdram_data_r_en,
14'b0,
sdram_data_r,
32'b1
};
wire [63:0] outs;
assign sdram_req = outs[63];
assign sdram_rh_wl = outs[62];
assign sdram_data_w = outs[47:32];
assign led = outs[31:24];
assign sdram_addr = outs[23:0];
wire clk100;
pll U1 (
.inclk0(clk),
.c0(clk100)
);
SpiPeek U2 (
.clk(clk100),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(ins),
.data_out(outs)
);
SdramCtrl U3 (
.clk (clk100),
.reset_l (~reset),
.sdram_req (sdram_req),
.sdram_ack (sdram_ack),
.sdram_addr (sdram_addr),
.sdram_rh_wl (sdram_rh_wl),
.sdram_data_w (sdram_data_w),
.sdram_data_r (sdram_data_r),
.sdram_data_r_en (sdram_data_r_en),
.zs_ck (zs_ck),
.zs_cke (zs_cke),
.zs_cs_n (zs_cs_n),
.zs_ras_n (zs_ras_n),
.zs_cas_n (zs_cas_n),
.zs_we_n (zs_we_n),
.zs_ba (zs_ba),
.zs_addr (zs_addr),
.zs_dqm (zs_dqm),
.zs_dq (zs_dq)
);
endmodule | module top (
input clk,
input reset,
output zs_ck,
output zs_cke,
output zs_cs_n,
output zs_ras_n,
output zs_cas_n,
output zs_we_n,
output [1:0] zs_ba,
output [12:0] zs_addr,
output [1:0] zs_dqm,
inout [ 15:0] zs_dq,
input ucSEL_,
input ucSCLK,
input ucMOSI,
output ucMISO,
output [7:0] led
); |
wire sdram_req;
wire [23:0] sdram_addr;
wire sdram_rh_wl;
wire [15:0] sdram_data_w;
wire [15:0] sdram_data_r_lock;
wire [15:0] sdram_data_r;
wire sdram_data_r_en;
wire sdram_ack;
wire [63:0] ins = {
sdram_ack,
sdram_data_r_en,
14'b0,
sdram_data_r,
32'b1
};
wire [63:0] outs;
assign sdram_req = outs[63];
assign sdram_rh_wl = outs[62];
assign sdram_data_w = outs[47:32];
assign led = outs[31:24];
assign sdram_addr = outs[23:0];
wire clk100;
pll U1 (
.inclk0(clk),
.c0(clk100)
);
SpiPeek U2 (
.clk(clk100),
.ucSCLK(ucSCLK),
.ucMOSI(ucMOSI),
.ucMISO(ucMISO),
.ucSEL_(ucSEL_),
.data_in(ins),
.data_out(outs)
);
SdramCtrl U3 (
.clk (clk100),
.reset_l (~reset),
.sdram_req (sdram_req),
.sdram_ack (sdram_ack),
.sdram_addr (sdram_addr),
.sdram_rh_wl (sdram_rh_wl),
.sdram_data_w (sdram_data_w),
.sdram_data_r (sdram_data_r),
.sdram_data_r_en (sdram_data_r_en),
.zs_ck (zs_ck),
.zs_cke (zs_cke),
.zs_cs_n (zs_cs_n),
.zs_ras_n (zs_ras_n),
.zs_cas_n (zs_cas_n),
.zs_we_n (zs_we_n),
.zs_ba (zs_ba),
.zs_addr (zs_addr),
.zs_dqm (zs_dqm),
.zs_dq (zs_dq)
);
endmodule | 0 |
141,903 | data/full_repos/permissive/96181301/quartus/stiv-fsmc/top.v | 96,181,301 | top.v | v | 67 | 71 | [] | [] | [] | null | line:36: before: "]" | null | 1: b"%Error: data/full_repos/permissive/96181301/quartus/stiv-fsmc/top.v:16: Cannot find file containing module: 'pll'\npll U1 (\n^~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/stiv-fsmc,data/full_repos/permissive/96181301/pll\n data/full_repos/permissive/96181301/quartus/stiv-fsmc,data/full_repos/permissive/96181301/pll.v\n data/full_repos/permissive/96181301/quartus/stiv-fsmc,data/full_repos/permissive/96181301/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/96181301/quartus/stiv-fsmc/top.v:55: Cannot find file containing module: 'vga'\nvga U2 (\n^~~\n%Error: Exiting due to 2 error(s)\n" | 312,645 | module | module top (
input clk,
input noe, nwe, nce2, nce3, ale, cle,
output [3:0] leds,
inout [15:0] data,
output red, green, blue, hsync, vsync,
output wbCSn
);
wire select = nce2 == 0;
wire c0, reset_l;
pll U1 (
.inclk0(clk),
.c0(c0),
.locked(reset_l)
);
reg [2:0] noe_r;
always @(posedge c0)
noe_r <= {noe_r[1:0],noe};
wire read = noe_r[2:1] == 2'b10 && select;
reg [2:0] nwe_r;
always @(posedge c0)
nwe_r <= {nwe_r[1:0],nwe};
wire write = nwe_r[2:1] == 2'b01 && select;
assign leds = index[3:0];
assign wbCSn = 1'b1;
reg [9:0] index;
reg [15:0] latch, tlatch, mem [1024];
always @(posedge c0) begin
if (write) begin
if (ale == 1'b1)
index <= data[9:0];
else if (cle == 1'b0) begin
mem[index] <= data;
index <= index + 10'd1;
end
end else if (read) begin
latch <= mem[index];
index <= index + 10'd1;
end
tlatch <= mem[taddr];
end
assign data = noe == 0 && select ? latch : 16'hzzzz;
wire [9:0] taddr;
vga U2 (
.clk(clk),
.red(red),
.green(green),
.blue(blue),
.hsync(hsync),
.vsync(vsync),
.taddr(taddr),
.tvalue(~tlatch[11:3])
);
endmodule | module top (
input clk,
input noe, nwe, nce2, nce3, ale, cle,
output [3:0] leds,
inout [15:0] data,
output red, green, blue, hsync, vsync,
output wbCSn
); |
wire select = nce2 == 0;
wire c0, reset_l;
pll U1 (
.inclk0(clk),
.c0(c0),
.locked(reset_l)
);
reg [2:0] noe_r;
always @(posedge c0)
noe_r <= {noe_r[1:0],noe};
wire read = noe_r[2:1] == 2'b10 && select;
reg [2:0] nwe_r;
always @(posedge c0)
nwe_r <= {nwe_r[1:0],nwe};
wire write = nwe_r[2:1] == 2'b01 && select;
assign leds = index[3:0];
assign wbCSn = 1'b1;
reg [9:0] index;
reg [15:0] latch, tlatch, mem [1024];
always @(posedge c0) begin
if (write) begin
if (ale == 1'b1)
index <= data[9:0];
else if (cle == 1'b0) begin
mem[index] <= data;
index <= index + 10'd1;
end
end else if (read) begin
latch <= mem[index];
index <= index + 10'd1;
end
tlatch <= mem[taddr];
end
assign data = noe == 0 && select ? latch : 16'hzzzz;
wire [9:0] taddr;
vga U2 (
.clk(clk),
.red(red),
.green(green),
.blue(blue),
.hsync(hsync),
.vsync(vsync),
.taddr(taddr),
.tvalue(~tlatch[11:3])
);
endmodule | 0 |
141,904 | data/full_repos/permissive/96181301/quartus/stiv-fsmc/vga.v | 96,181,301 | vga.v | v | 79 | 66 | [] | [] | [] | [(1, 78)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/stiv-fsmc/vga.v:23: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'yPos\' generates 9 bits.\n : ... In instance vga\n if (yPos == 524)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/96181301/quartus/stiv-fsmc/vga.v:46: Comparison is constant due to unsigned arithmetic\n : ... In instance vga\nwire vBorder = vBars && YMIN <= yPos && yPos <= YMAX;\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/96181301/quartus/stiv-fsmc/vga.v:47: Comparison is constant due to unsigned arithmetic\n : ... In instance vga\nwire hBorder = hBars && XMIN <= xPos && xPos <= XMAX;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,646 | module | module vga (
input clk,
output red, green, blue, hsync, vsync,
output [9:0] taddr,
input [8:0] tvalue
);
reg pixClk;
always @(posedge clk)
pixClk <= ~pixClk;
reg [2:0] pixDiv;
always @(posedge clk)
pixDiv <= pixDiv + 3'd1;
reg [9:0] xPos;
reg [8:0] yPos;
always @(posedge clk)
if (pixClk)
if (xPos == 799) begin
xPos <= 0;
if (yPos == 524)
yPos <= 0;
else
yPos <= yPos + 9'd1;
end else
xPos <= xPos + 10'd1;
reg active, vSync;
always @(*)
if (xPos < 640 && yPos < 480)
{active,vSync} = 2'b10;
else if (yPos < 484)
{active,vSync} = 2'b00;
else if (yPos < 486)
{active,vSync} = 2'b01;
else
{active,vSync} = 2'b00;
wire hSync = 658 <= xPos && xPos < 754;
localparam XMIN=0, XMAX=639, YMIN=0, YMAX=479;
wire vBars = xPos==XMIN || xPos==XMAX;
wire hBars = yPos==YMIN || yPos==YMAX;
wire vBorder = vBars && YMIN <= yPos && yPos <= YMAX;
wire hBorder = hBars && XMIN <= xPos && xPos <= XMAX;
assign taddr = xPos;
reg hSync_d, vSync_d;
reg [2:0] rgb_d;
reg [8:0] tvalue_d;
always @(posedge clk) begin
if (pixClk) begin
hSync_d <= hSync;
vSync_d <= vSync;
tvalue_d <= tvalue;
if (active)
if (vBorder || hBorder)
rgb_d <= 3'b001;
else if ((tvalue <= yPos && yPos <= tvalue_d) ||
(tvalue_d <= yPos && yPos <= tvalue))
rgb_d <= 3'b110;
else
rgb_d <= 3'b000;
else
rgb_d <= 3'b000;
end
end
assign {red,green,blue} = rgb_d;
assign hsync = hSync_d;
assign vsync = vSync_d;
endmodule | module vga (
input clk,
output red, green, blue, hsync, vsync,
output [9:0] taddr,
input [8:0] tvalue
); |
reg pixClk;
always @(posedge clk)
pixClk <= ~pixClk;
reg [2:0] pixDiv;
always @(posedge clk)
pixDiv <= pixDiv + 3'd1;
reg [9:0] xPos;
reg [8:0] yPos;
always @(posedge clk)
if (pixClk)
if (xPos == 799) begin
xPos <= 0;
if (yPos == 524)
yPos <= 0;
else
yPos <= yPos + 9'd1;
end else
xPos <= xPos + 10'd1;
reg active, vSync;
always @(*)
if (xPos < 640 && yPos < 480)
{active,vSync} = 2'b10;
else if (yPos < 484)
{active,vSync} = 2'b00;
else if (yPos < 486)
{active,vSync} = 2'b01;
else
{active,vSync} = 2'b00;
wire hSync = 658 <= xPos && xPos < 754;
localparam XMIN=0, XMAX=639, YMIN=0, YMAX=479;
wire vBars = xPos==XMIN || xPos==XMAX;
wire hBars = yPos==YMIN || yPos==YMAX;
wire vBorder = vBars && YMIN <= yPos && yPos <= YMAX;
wire hBorder = hBars && XMIN <= xPos && xPos <= XMAX;
assign taddr = xPos;
reg hSync_d, vSync_d;
reg [2:0] rgb_d;
reg [8:0] tvalue_d;
always @(posedge clk) begin
if (pixClk) begin
hSync_d <= hSync;
vSync_d <= vSync;
tvalue_d <= tvalue;
if (active)
if (vBorder || hBorder)
rgb_d <= 3'b001;
else if ((tvalue <= yPos && yPos <= tvalue_d) ||
(tvalue_d <= yPos && yPos <= tvalue))
rgb_d <= 3'b110;
else
rgb_d <= 3'b000;
else
rgb_d <= 3'b000;
end
end
assign {red,green,blue} = rgb_d;
assign hsync = hSync_d;
assign vsync = vSync_d;
endmodule | 0 |
141,905 | data/full_repos/permissive/96181301/quartus/stiv-sdramtest/sdram_test.v | 96,181,301 | sdram_test.v | v | 154 | 78 | [] | [] | [] | [(1, 153)] | null | null | 1: b"%Error: data/full_repos/permissive/96181301/quartus/stiv-sdramtest/sdram_test.v:129: Cannot find file containing module: 'SdramCtrl'\nSdramCtrl u_sdram_ctrl (\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96181301/quartus/stiv-sdramtest,data/full_repos/permissive/96181301/SdramCtrl\n data/full_repos/permissive/96181301/quartus/stiv-sdramtest,data/full_repos/permissive/96181301/SdramCtrl.v\n data/full_repos/permissive/96181301/quartus/stiv-sdramtest,data/full_repos/permissive/96181301/SdramCtrl.sv\n SdramCtrl\n SdramCtrl.v\n SdramCtrl.sv\n obj_dir/SdramCtrl\n obj_dir/SdramCtrl.v\n obj_dir/SdramCtrl.sv\n%Error: Exiting due to 1 error(s)\n" | 312,650 | module | module top (
clk,
reset_l,
zs_ck,
zs_cke,
zs_cs_n,
zs_ras_n,
zs_cas_n,
zs_we_n,
zs_ba,
zs_addr,
zs_dqm,
zs_dq,
led
);
input clk;
input reset_l;
output zs_ck;
output zs_cke;
output zs_cs_n;
output zs_ras_n;
output zs_cas_n;
output zs_we_n;
output [1:0] zs_ba;
output [11:0] zs_addr;
output [1:0] zs_dqm;
inout [15:0] zs_dq;
output reg [7:0] led;
parameter IDLE = 3'b001;
parameter WRITE = 3'b010;
parameter READ = 3'b100;
parameter div_400us = 15'd25000;
parameter sdram_addr_num = 22'b0;
parameter sdram_data_w_num = 16'b1111000001010101;
reg sdram_req;
reg [21:0] sdram_addr;
reg sdram_rh_wl;
reg [15:0] sdram_data_w;
reg [2:0] current_state;
reg [2:0] current_state_dly1;
reg [2:0] next_state;
reg [14:0] init_wait_cnt;
reg [7:0] wr_cnt;
reg [15:0] sdram_data_r_lock;
wire [15:0] sdram_data_r;
wire sdram_data_r_en;
wire sdram_ack;
wire rd_en;
wire wr_en;
always @(posedge clk or negedge reset_l)
if (!reset_l)
current_state<=IDLE;
else
current_state <= next_state;
always @(posedge clk or negedge reset_l)
if (!reset_l)
init_wait_cnt<=15'b0;
else if (init_wait_cnt<= (div_400us-1))
init_wait_cnt<=init_wait_cnt+15'b1;
always @(posedge clk or negedge reset_l)
if (!reset_l)
wr_cnt <= 8'b0;
else if (current_state == WRITE && wr_cnt < 8'd250)
wr_cnt <= wr_cnt + 8'b1;
always @(*)
case(current_state)
IDLE:
if (init_wait_cnt>= (div_400us-1))
next_state=WRITE;
else
next_state=IDLE;
WRITE:
if (wr_cnt == 8'd250)
next_state=READ;
else
next_state=WRITE;
READ:
next_state=READ;
endcase
always @(posedge clk or negedge reset_l)
if (!reset_l)
current_state_dly1 <=3'b0;
else
current_state_dly1<=current_state;
assign wr_en = (current_state == WRITE) & (current_state_dly1 != WRITE);
assign rd_en = (current_state == READ) & (current_state_dly1 != READ);
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
sdram_rh_wl<=1'b1;
sdram_req<=1'b0;
sdram_addr<=0;
sdram_data_w<=0;
end else if (current_state == WRITE) begin
sdram_addr <= sdram_addr_num;
sdram_data_w <= sdram_data_w_num;
sdram_req <= wr_en;
sdram_rh_wl <= 1'b0;
end else if (current_state == READ) begin
sdram_rh_wl <= 1'b1;
sdram_req <= rd_en;
end
always @(posedge clk or negedge reset_l)
if (!reset_l)
sdram_data_r_lock <=16'b0;
else if (sdram_ack == 1'b1 && sdram_rh_wl == 1'b1)
sdram_data_r_lock <= sdram_data_r;
always @(posedge clk or negedge reset_l)
if (!reset_l)
led <=8'b0;
else if (sdram_data_r_lock == sdram_data_w)
led <=8'h55;
SdramCtrl u_sdram_ctrl (
.clk (clk),
.reset_l (reset_l),
.sdram_req (sdram_req),
.sdram_ack (sdram_ack),
.sdram_addr (sdram_addr),
.sdram_rh_wl (sdram_rh_wl),
.sdram_data_w (sdram_data_w),
.sdram_data_r (sdram_data_r),
.sdram_data_r_en (sdram_data_r_en),
.zs_ck (zs_ck),
.zs_cke (zs_cke),
.zs_cs_n (zs_cs_n),
.zs_ras_n (zs_ras_n),
.zs_cas_n (zs_cas_n),
.zs_we_n (zs_we_n),
.zs_ba (zs_ba),
.zs_addr (zs_addr),
.zs_dqm (zs_dqm),
.zs_dq (zs_dq)
);
endmodule | module top (
clk,
reset_l,
zs_ck,
zs_cke,
zs_cs_n,
zs_ras_n,
zs_cas_n,
zs_we_n,
zs_ba,
zs_addr,
zs_dqm,
zs_dq,
led
); |
input clk;
input reset_l;
output zs_ck;
output zs_cke;
output zs_cs_n;
output zs_ras_n;
output zs_cas_n;
output zs_we_n;
output [1:0] zs_ba;
output [11:0] zs_addr;
output [1:0] zs_dqm;
inout [15:0] zs_dq;
output reg [7:0] led;
parameter IDLE = 3'b001;
parameter WRITE = 3'b010;
parameter READ = 3'b100;
parameter div_400us = 15'd25000;
parameter sdram_addr_num = 22'b0;
parameter sdram_data_w_num = 16'b1111000001010101;
reg sdram_req;
reg [21:0] sdram_addr;
reg sdram_rh_wl;
reg [15:0] sdram_data_w;
reg [2:0] current_state;
reg [2:0] current_state_dly1;
reg [2:0] next_state;
reg [14:0] init_wait_cnt;
reg [7:0] wr_cnt;
reg [15:0] sdram_data_r_lock;
wire [15:0] sdram_data_r;
wire sdram_data_r_en;
wire sdram_ack;
wire rd_en;
wire wr_en;
always @(posedge clk or negedge reset_l)
if (!reset_l)
current_state<=IDLE;
else
current_state <= next_state;
always @(posedge clk or negedge reset_l)
if (!reset_l)
init_wait_cnt<=15'b0;
else if (init_wait_cnt<= (div_400us-1))
init_wait_cnt<=init_wait_cnt+15'b1;
always @(posedge clk or negedge reset_l)
if (!reset_l)
wr_cnt <= 8'b0;
else if (current_state == WRITE && wr_cnt < 8'd250)
wr_cnt <= wr_cnt + 8'b1;
always @(*)
case(current_state)
IDLE:
if (init_wait_cnt>= (div_400us-1))
next_state=WRITE;
else
next_state=IDLE;
WRITE:
if (wr_cnt == 8'd250)
next_state=READ;
else
next_state=WRITE;
READ:
next_state=READ;
endcase
always @(posedge clk or negedge reset_l)
if (!reset_l)
current_state_dly1 <=3'b0;
else
current_state_dly1<=current_state;
assign wr_en = (current_state == WRITE) & (current_state_dly1 != WRITE);
assign rd_en = (current_state == READ) & (current_state_dly1 != READ);
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
sdram_rh_wl<=1'b1;
sdram_req<=1'b0;
sdram_addr<=0;
sdram_data_w<=0;
end else if (current_state == WRITE) begin
sdram_addr <= sdram_addr_num;
sdram_data_w <= sdram_data_w_num;
sdram_req <= wr_en;
sdram_rh_wl <= 1'b0;
end else if (current_state == READ) begin
sdram_rh_wl <= 1'b1;
sdram_req <= rd_en;
end
always @(posedge clk or negedge reset_l)
if (!reset_l)
sdram_data_r_lock <=16'b0;
else if (sdram_ack == 1'b1 && sdram_rh_wl == 1'b1)
sdram_data_r_lock <= sdram_data_r;
always @(posedge clk or negedge reset_l)
if (!reset_l)
led <=8'b0;
else if (sdram_data_r_lock == sdram_data_w)
led <=8'h55;
SdramCtrl u_sdram_ctrl (
.clk (clk),
.reset_l (reset_l),
.sdram_req (sdram_req),
.sdram_ack (sdram_ack),
.sdram_addr (sdram_addr),
.sdram_rh_wl (sdram_rh_wl),
.sdram_data_w (sdram_data_w),
.sdram_data_r (sdram_data_r),
.sdram_data_r_en (sdram_data_r_en),
.zs_ck (zs_ck),
.zs_cke (zs_cke),
.zs_cs_n (zs_cs_n),
.zs_ras_n (zs_ras_n),
.zs_cas_n (zs_cas_n),
.zs_we_n (zs_we_n),
.zs_ba (zs_ba),
.zs_addr (zs_addr),
.zs_dqm (zs_dqm),
.zs_dq (zs_dq)
);
endmodule | 0 |
141,906 | data/full_repos/permissive/96181301/quartus/tinyUart/top.v | 96,181,301 | top.v | v | 71 | 72 | [] | [] | [] | null | line:58: before: "=" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:12: Cell has missing pin: \'tx_busy\'\nUartTx U3(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:66: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'tx_shifter\' generates 10 bits.\n : ... In instance top.U3\n { tx_shifter, txd } <= tx_shifter;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:45: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n : ... In instance top.U2\n tx_sample_cntr <= 50000000/115200-1;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,652 | module | module top (
input clk,
output txd
);
wire tick, baud;
Tick1hz U1(.clk(clk), .tick(tick));
BaudGen U2(.clk(clk), .baud(baud));
UartTx U3(
.clk(clk),
.tx_clock(baud),
.tx_data(8'h45),
.tx_start(tick),
.txd(txd)
);
endmodule | module top (
input clk,
output txd
); |
wire tick, baud;
Tick1hz U1(.clk(clk), .tick(tick));
BaudGen U2(.clk(clk), .baud(baud));
UartTx U3(
.clk(clk),
.tx_clock(baud),
.tx_data(8'h45),
.tx_start(tick),
.txd(txd)
);
endmodule | 0 |
141,907 | data/full_repos/permissive/96181301/quartus/tinyUart/top.v | 96,181,301 | top.v | v | 71 | 72 | [] | [] | [] | null | line:58: before: "=" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:12: Cell has missing pin: \'tx_busy\'\nUartTx U3(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:66: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'tx_shifter\' generates 10 bits.\n : ... In instance top.U3\n { tx_shifter, txd } <= tx_shifter;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:45: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n : ... In instance top.U2\n tx_sample_cntr <= 50000000/115200-1;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,652 | module | module Tick1hz (
input clk,
output tick
);
reg [31:0] counter = 0;
always @(posedge clk)
if (counter == 50000000-1)
counter <= 0;
else
counter <= counter + 1;
assign tick = counter == 0;
endmodule | module Tick1hz (
input clk,
output tick
); |
reg [31:0] counter = 0;
always @(posedge clk)
if (counter == 50000000-1)
counter <= 0;
else
counter <= counter + 1;
assign tick = counter == 0;
endmodule | 0 |
141,908 | data/full_repos/permissive/96181301/quartus/tinyUart/top.v | 96,181,301 | top.v | v | 71 | 72 | [] | [] | [] | null | line:58: before: "=" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:12: Cell has missing pin: \'tx_busy\'\nUartTx U3(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:66: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'tx_shifter\' generates 10 bits.\n : ... In instance top.U3\n { tx_shifter, txd } <= tx_shifter;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:45: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n : ... In instance top.U2\n tx_sample_cntr <= 50000000/115200-1;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,652 | module | module BaudGen (
input clk,
output baud
);
reg [8:0] tx_sample_cntr = 0;
always @(posedge clk)
if (tx_sample_cntr == 0)
tx_sample_cntr <= 50000000/115200-1;
else
tx_sample_cntr <= tx_sample_cntr - 1;
assign baud = tx_sample_cntr == 0;
endmodule | module BaudGen (
input clk,
output baud
); |
reg [8:0] tx_sample_cntr = 0;
always @(posedge clk)
if (tx_sample_cntr == 0)
tx_sample_cntr <= 50000000/115200-1;
else
tx_sample_cntr <= tx_sample_cntr - 1;
assign baud = tx_sample_cntr == 0;
endmodule | 0 |
141,909 | data/full_repos/permissive/96181301/quartus/tinyUart/top.v | 96,181,301 | top.v | v | 71 | 72 | [] | [] | [] | null | line:58: before: "=" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:12: Cell has missing pin: \'tx_busy\'\nUartTx U3(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:66: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'tx_shifter\' generates 10 bits.\n : ... In instance top.U3\n { tx_shifter, txd } <= tx_shifter;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/tinyUart/top.v:45: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n : ... In instance top.U2\n tx_sample_cntr <= 50000000/115200-1;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,652 | module | module UartTx (
input clk,
input tx_clock,
input [7:0] tx_data,
input tx_start,
output tx_busy,
output reg txd = 1
);
reg [9:0] tx_shifter = 0;
always @(posedge clk) begin
if (tx_start && ~tx_busy)
tx_shifter <= { 1'b1, tx_data, 1'b0 };
if (tx_clock && tx_busy)
{ tx_shifter, txd } <= tx_shifter;
end
assign tx_busy = tx_shifter != 0;
endmodule | module UartTx (
input clk,
input tx_clock,
input [7:0] tx_data,
input tx_start,
output tx_busy,
output reg txd = 1
); |
reg [9:0] tx_shifter = 0;
always @(posedge clk) begin
if (tx_start && ~tx_busy)
tx_shifter <= { 1'b1, tx_data, 1'b0 };
if (tx_clock && tx_busy)
{ tx_shifter, txd } <= tx_shifter;
end
assign tx_busy = tx_shifter != 0;
endmodule | 0 |
141,910 | data/full_repos/permissive/96181301/quartus/tvout/top.v | 96,181,301 | top.v | v | 72 | 73 | [] | [] | [] | [(1, 71)] | null | data/verilator_xmls/604024ab-d402-4d95-9156-2fcb01ab141d.xml | null | 312,653 | module | module top (
input clk,
output vout, sync_
);
reg [2:0] clkDiv;
always @(posedge clk) begin
if (clkDiv == 4)
clkDiv <= 0;
else
clkDiv <= clkDiv + 3'd1;
end
wire pixClk = clkDiv == 0;
reg [2:0] pixDiv;
always @(posedge clk)
pixDiv <= pixDiv + 3'd1;
wire fetchClk = pixDiv == 0;
reg [9:0] xPos;
reg [8:0] yPos;
always @(posedge clk)
if (pixClk)
if (xPos == 639) begin
xPos <= 0;
if (yPos == 308)
yPos <= 0;
else
yPos <= yPos + 9'd1;
end else
xPos <= xPos + 10'd1;
reg active, vSync;
always @(*)
if (xPos < 512 && yPos < 287)
{active,vSync} = 2'b10;
else if (yPos < 288)
{active,vSync} = 2'b00;
else if (yPos < 290)
{active,vSync} = 2'b01;
else if (yPos == 290)
{active,vSync} = xPos < 532-320 ? 2'b01 : 2'b00;
else
{active,vSync} = 2'b00;
wire hSync = 532 <= xPos && xPos < 579;
localparam XMIN=8, XMAX=495, YMIN=18, YMAX=283;
wire vBars = xPos==XMIN || xPos==XMIN+10 || xPos==XMAX-10 || xPos==XMAX;
wire hBars = yPos==YMIN || yPos==YMIN+10 || yPos==YMAX-10 || yPos==YMAX;
wire vTest = vBars && YMIN <= yPos && yPos <= YMAX;
wire hTest = hBars && XMIN <= xPos && xPos <= XMAX;
reg active_d, vout_d, sync_d;
always @(posedge clk) begin
if (fetchClk) begin
active_d = active;
vout_d <= vTest || hTest;
sync_d <= vSync || hSync;
end
end
assign vout = active_d && vout_d;
assign sync_ = !sync_d;
endmodule | module top (
input clk,
output vout, sync_
); |
reg [2:0] clkDiv;
always @(posedge clk) begin
if (clkDiv == 4)
clkDiv <= 0;
else
clkDiv <= clkDiv + 3'd1;
end
wire pixClk = clkDiv == 0;
reg [2:0] pixDiv;
always @(posedge clk)
pixDiv <= pixDiv + 3'd1;
wire fetchClk = pixDiv == 0;
reg [9:0] xPos;
reg [8:0] yPos;
always @(posedge clk)
if (pixClk)
if (xPos == 639) begin
xPos <= 0;
if (yPos == 308)
yPos <= 0;
else
yPos <= yPos + 9'd1;
end else
xPos <= xPos + 10'd1;
reg active, vSync;
always @(*)
if (xPos < 512 && yPos < 287)
{active,vSync} = 2'b10;
else if (yPos < 288)
{active,vSync} = 2'b00;
else if (yPos < 290)
{active,vSync} = 2'b01;
else if (yPos == 290)
{active,vSync} = xPos < 532-320 ? 2'b01 : 2'b00;
else
{active,vSync} = 2'b00;
wire hSync = 532 <= xPos && xPos < 579;
localparam XMIN=8, XMAX=495, YMIN=18, YMAX=283;
wire vBars = xPos==XMIN || xPos==XMIN+10 || xPos==XMAX-10 || xPos==XMAX;
wire hBars = yPos==YMIN || yPos==YMIN+10 || yPos==YMAX-10 || yPos==YMAX;
wire vTest = vBars && YMIN <= yPos && yPos <= YMAX;
wire hTest = hBars && XMIN <= xPos && xPos <= XMAX;
reg active_d, vout_d, sync_d;
always @(posedge clk) begin
if (fetchClk) begin
active_d = active;
vout_d <= vTest || hTest;
sync_d <= vSync || hSync;
end
end
assign vout = active_d && vout_d;
assign sync_ = !sync_d;
endmodule | 0 |
141,911 | data/full_repos/permissive/96181301/quartus/vga1024/top.v | 96,181,301 | top.v | v | 58 | 67 | [] | [] | [] | [(3, 57)] | null | data/verilator_xmls/d99ce6dd-9efc-442e-9b1a-8f843b3cbf00.xml | null | 312,654 | module | module top (
input clk,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync, vsync
);
reg [11:0] hcount;
reg [10:0] vcount;
reg [7:0] data;
wire hcount_ov, vcount_ov, video_active;
parameter
hsync_end = 12'd119,
hdat_begin = 12'd242,
hdat_end = 12'd1266,
hpixel_end = 12'd1345,
vsync_end = 11'd5,
vdat_begin = 11'd32,
vdat_end = 11'd632,
vline_end = 11'd665;
always @(posedge clk)
if (hcount_ov)
hcount <= 12'd0;
else
hcount <= hcount + 12'd1;
assign hcount_ov = hcount == hpixel_end;
always @(posedge clk)
if (hcount_ov)
if (vcount_ov)
vcount <= 11'd0;
else
vcount <= vcount + 11'd1;
assign vcount_ov = vcount == vline_end;
assign video_active = hdat_begin <= hcount && hcount < hdat_end &&
vdat_begin <= vcount && vcount < vdat_end;
assign hsync = hcount > hsync_end;
assign vsync = vcount > vsync_end;
assign red = video_active ? data[2:0] : 3'b0;
assign green = video_active ? data[5:3] : 3'b0;
assign blue = video_active ? data[7:6] : 2'b0;
always @(posedge clk)
data <= vcount[7:0] ^ hcount[7:0];
endmodule | module top (
input clk,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync, vsync
); |
reg [11:0] hcount;
reg [10:0] vcount;
reg [7:0] data;
wire hcount_ov, vcount_ov, video_active;
parameter
hsync_end = 12'd119,
hdat_begin = 12'd242,
hdat_end = 12'd1266,
hpixel_end = 12'd1345,
vsync_end = 11'd5,
vdat_begin = 11'd32,
vdat_end = 11'd632,
vline_end = 11'd665;
always @(posedge clk)
if (hcount_ov)
hcount <= 12'd0;
else
hcount <= hcount + 12'd1;
assign hcount_ov = hcount == hpixel_end;
always @(posedge clk)
if (hcount_ov)
if (vcount_ov)
vcount <= 11'd0;
else
vcount <= vcount + 11'd1;
assign vcount_ov = vcount == vline_end;
assign video_active = hdat_begin <= hcount && hcount < hdat_end &&
vdat_begin <= vcount && vcount < vdat_end;
assign hsync = hcount > hsync_end;
assign vsync = vcount > vsync_end;
assign red = video_active ? data[2:0] : 3'b0;
assign green = video_active ? data[5:3] : 3'b0;
assign blue = video_active ? data[7:6] : 2'b0;
always @(posedge clk)
data <= vcount[7:0] ^ hcount[7:0];
endmodule | 0 |
141,912 | data/full_repos/permissive/96181301/quartus/vgaout/top.v | 96,181,301 | top.v | v | 70 | 73 | [] | [] | [] | [(1, 69)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/96181301/quartus/vgaout/top.v:24: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'yPos\' generates 9 bits.\n : ... In instance top\n if (yPos == 524)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/96181301/quartus/vgaout/top.v:47: Comparison is constant due to unsigned arithmetic\n : ... In instance top\nwire vTest = vBars && YMIN <= yPos && yPos <= YMAX;\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/96181301/quartus/vgaout/top.v:48: Comparison is constant due to unsigned arithmetic\n : ... In instance top\nwire hTest = hBars && XMIN <= xPos && xPos <= XMAX;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 312,655 | module | module top (
input clk,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync, vsync
);
reg pixClk;
always @(posedge clk)
pixClk <= ~pixClk;
reg [2:0] pixDiv;
always @(posedge clk)
pixDiv <= pixDiv + 3'd1;
wire fetchClk = pixDiv == 0;
reg [9:0] xPos;
reg [8:0] yPos;
always @(posedge clk)
if (pixClk)
if (xPos == 799) begin
xPos <= 0;
if (yPos == 524)
yPos <= 0;
else
yPos <= yPos + 9'd1;
end else
xPos <= xPos + 10'd1;
reg active, vSync;
always @(*)
if (xPos < 640 && yPos < 480)
{active,vSync} = 2'b10;
else if (yPos < 481)
{active,vSync} = 2'b00;
else if (yPos < 483)
{active,vSync} = 2'b01;
else
{active,vSync} = 2'b00;
wire hSync = 658 <= xPos && xPos < 754;
localparam XMIN=0, XMAX=639, YMIN=0, YMAX=479;
wire vBars = xPos==XMIN || xPos==XMIN+10 || xPos==XMAX-10 || xPos==XMAX;
wire hBars = yPos==YMIN || yPos==YMIN+10 || yPos==YMAX-10 || yPos==YMAX;
wire vTest = vBars && YMIN <= yPos && yPos <= YMAX;
wire hTest = hBars && XMIN <= xPos && xPos <= XMAX;
reg active_d, vout_d, hSync_d, vSync_d;
always @(posedge clk) begin
if (pixClk) begin
active_d = active;
vout_d <= vTest || hTest;
hSync_d <= hSync;
vSync_d <= vSync;
end
end
assign {red,green,blue} = {8{active_d && vout_d}};
assign hsync = hSync_d;
assign vsync = vSync_d;
endmodule | module top (
input clk,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync, vsync
); |
reg pixClk;
always @(posedge clk)
pixClk <= ~pixClk;
reg [2:0] pixDiv;
always @(posedge clk)
pixDiv <= pixDiv + 3'd1;
wire fetchClk = pixDiv == 0;
reg [9:0] xPos;
reg [8:0] yPos;
always @(posedge clk)
if (pixClk)
if (xPos == 799) begin
xPos <= 0;
if (yPos == 524)
yPos <= 0;
else
yPos <= yPos + 9'd1;
end else
xPos <= xPos + 10'd1;
reg active, vSync;
always @(*)
if (xPos < 640 && yPos < 480)
{active,vSync} = 2'b10;
else if (yPos < 481)
{active,vSync} = 2'b00;
else if (yPos < 483)
{active,vSync} = 2'b01;
else
{active,vSync} = 2'b00;
wire hSync = 658 <= xPos && xPos < 754;
localparam XMIN=0, XMAX=639, YMIN=0, YMAX=479;
wire vBars = xPos==XMIN || xPos==XMIN+10 || xPos==XMAX-10 || xPos==XMAX;
wire hBars = yPos==YMIN || yPos==YMIN+10 || yPos==YMAX-10 || yPos==YMAX;
wire vTest = vBars && YMIN <= yPos && yPos <= YMAX;
wire hTest = hBars && XMIN <= xPos && xPos <= XMAX;
reg active_d, vout_d, hSync_d, vSync_d;
always @(posedge clk) begin
if (pixClk) begin
active_d = active;
vout_d <= vTest || hTest;
hSync_d <= hSync;
vSync_d <= vSync;
end
end
assign {red,green,blue} = {8{active_d && vout_d}};
assign hsync = hSync_d;
assign vsync = vSync_d;
endmodule | 0 |
141,913 | data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v | 96,222,896 | DarkRoom.v | v | 298 | 72 | [] | [] | [] | [(9, 296)] | null | null | 1: b"%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:101: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse00 (\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl,data/full_repos/permissive/96222896/lighthouse_sensor\n data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl,data/full_repos/permissive/96222896/lighthouse_sensor.v\n data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl,data/full_repos/permissive/96222896/lighthouse_sensor.sv\n lighthouse_sensor\n lighthouse_sensor.v\n lighthouse_sensor.sv\n obj_dir/lighthouse_sensor\n obj_dir/lighthouse_sensor.v\n obj_dir/lighthouse_sensor.sv\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:107: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse01 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:113: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse02 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:120: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse03 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:126: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse04 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:132: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse05 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:138: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse06 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:144: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse07 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:150: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse08 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:156: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse09 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:162: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse10 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:168: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse11 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:174: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse12 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:180: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse13 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:186: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse14 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:192: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse15 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:198: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse16 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:204: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse17 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:210: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse18 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:216: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse19 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:222: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse20 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:228: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse21 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:234: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse22 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:240: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse23 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:246: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse24 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:252: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse25 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:258: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse26 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:264: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse27 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:270: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse28 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:276: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse29 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:282: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse30 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/DarkRoom/src/DarkRoom_fpga/fpga-rtl/DarkRoom.v:288: Cannot find file containing module: 'lighthouse_sensor'\nlighthouse_sensor awesome_lighthouse31 (\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n" | 312,656 | module | module DarkRoom (
input clock,
input reset_n,
input [5:0] address,
input write,
input signed [31:0] writedata,
input read,
output signed [31:0] readdata,
output waitrequest,
input [31:0] sensor_signal_i,
output [6:0] LED
);
wire [31:0] sensor_combined_data_00;
wire [31:0] sensor_combined_data_01;
wire [31:0] sensor_combined_data_02;
wire [31:0] sensor_combined_data_03;
wire [31:0] sensor_combined_data_04;
wire [31:0] sensor_combined_data_05;
wire [31:0] sensor_combined_data_06;
wire [31:0] sensor_combined_data_07;
wire [31:0] sensor_combined_data_08;
wire [31:0] sensor_combined_data_09;
wire [31:0] sensor_combined_data_10;
wire [31:0] sensor_combined_data_11;
wire [31:0] sensor_combined_data_12;
wire [31:0] sensor_combined_data_13;
wire [31:0] sensor_combined_data_14;
wire [31:0] sensor_combined_data_15;
wire [31:0] sensor_combined_data_16;
wire [31:0] sensor_combined_data_17;
wire [31:0] sensor_combined_data_18;
wire [31:0] sensor_combined_data_19;
wire [31:0] sensor_combined_data_20;
wire [31:0] sensor_combined_data_21;
wire [31:0] sensor_combined_data_22;
wire [31:0] sensor_combined_data_23;
wire [31:0] sensor_combined_data_24;
wire [31:0] sensor_combined_data_25;
wire [31:0] sensor_combined_data_26;
wire [31:0] sensor_combined_data_27;
wire [31:0] sensor_combined_data_28;
wire [31:0] sensor_combined_data_29;
wire [31:0] sensor_combined_data_30;
wire [31:0] sensor_combined_data_31;
assign readdata =
(address == 0) ? sensor_combined_data_00 :
(address == 1) ? sensor_combined_data_01 :
(address == 2) ? sensor_combined_data_02 :
(address == 3) ? sensor_combined_data_03 :
(address == 4) ? sensor_combined_data_04 :
(address == 5) ? sensor_combined_data_05 :
(address == 6) ? sensor_combined_data_06 :
(address == 7) ? sensor_combined_data_07 :
(address == 8) ? sensor_combined_data_08 :
(address == 9) ? sensor_combined_data_09 :
(address == 10) ? sensor_combined_data_10 :
(address == 11) ? sensor_combined_data_11 :
(address == 12) ? sensor_combined_data_12 :
(address == 13) ? sensor_combined_data_13 :
(address == 14) ? sensor_combined_data_14 :
(address == 15) ? sensor_combined_data_15 :
(address == 16) ? sensor_combined_data_16 :
(address == 17) ? sensor_combined_data_17 :
(address == 18) ? sensor_combined_data_18 :
(address == 19) ? sensor_combined_data_19 :
(address == 20) ? sensor_combined_data_20 :
(address == 21) ? sensor_combined_data_21 :
(address == 22) ? sensor_combined_data_22 :
(address == 23) ? sensor_combined_data_23 :
(address == 24) ? sensor_combined_data_24 :
(address == 25) ? sensor_combined_data_25 :
(address == 26) ? sensor_combined_data_26 :
(address == 27) ? sensor_combined_data_27 :
(address == 28) ? sensor_combined_data_28 :
(address == 29) ? sensor_combined_data_29 :
(address == 30) ? sensor_combined_data_30 :
(address == 31) ? sensor_combined_data_31 :
32'hDEAD_BEEF;
assign waitrequest = 0;
lighthouse_sensor awesome_lighthouse00 (
.clk(clock),
.sensor(sensor_signal_i[0]),
.combined_data(sensor_combined_data_00)
);
lighthouse_sensor awesome_lighthouse01 (
.clk(clock),
.sensor(sensor_signal_i[1]),
.combined_data(sensor_combined_data_01)
);
lighthouse_sensor awesome_lighthouse02 (
.clk(clock),
.sensor(sensor_signal_i[2]),
.combined_data(sensor_combined_data_02)
);
lighthouse_sensor awesome_lighthouse03 (
.clk(clock),
.sensor(sensor_signal_i[3]),
.combined_data(sensor_combined_data_03)
);
lighthouse_sensor awesome_lighthouse04 (
.clk(clock),
.sensor(sensor_signal_i[4]),
.combined_data(sensor_combined_data_04)
);
lighthouse_sensor awesome_lighthouse05 (
.clk(clock),
.sensor(sensor_signal_i[5]),
.combined_data(sensor_combined_data_05)
);
lighthouse_sensor awesome_lighthouse06 (
.clk(clock),
.sensor(sensor_signal_i[6]),
.combined_data(sensor_combined_data_06)
);
lighthouse_sensor awesome_lighthouse07 (
.clk(clock),
.sensor(sensor_signal_i[7]),
.combined_data(sensor_combined_data_07)
);
lighthouse_sensor awesome_lighthouse08 (
.clk(clock),
.sensor(sensor_signal_i[8]),
.combined_data(sensor_combined_data_08)
);
lighthouse_sensor awesome_lighthouse09 (
.clk(clock),
.sensor(sensor_signal_i[9]),
.combined_data(sensor_combined_data_09)
);
lighthouse_sensor awesome_lighthouse10 (
.clk(clock),
.sensor(sensor_signal_i[10]),
.combined_data(sensor_combined_data_10)
);
lighthouse_sensor awesome_lighthouse11 (
.clk(clock),
.sensor(sensor_signal_i[11]),
.combined_data(sensor_combined_data_11)
);
lighthouse_sensor awesome_lighthouse12 (
.clk(clock),
.sensor(sensor_signal_i[12]),
.combined_data(sensor_combined_data_12)
);
lighthouse_sensor awesome_lighthouse13 (
.clk(clock),
.sensor(sensor_signal_i[13]),
.combined_data(sensor_combined_data_13)
);
lighthouse_sensor awesome_lighthouse14 (
.clk(clock),
.sensor(sensor_signal_i[14]),
.combined_data(sensor_combined_data_14)
);
lighthouse_sensor awesome_lighthouse15 (
.clk(clock),
.sensor(sensor_signal_i[15]),
.combined_data(sensor_combined_data_15)
);
lighthouse_sensor awesome_lighthouse16 (
.clk(clock),
.sensor(sensor_signal_i[16]),
.combined_data(sensor_combined_data_16)
);
lighthouse_sensor awesome_lighthouse17 (
.clk(clock),
.sensor(sensor_signal_i[17]),
.combined_data(sensor_combined_data_17)
);
lighthouse_sensor awesome_lighthouse18 (
.clk(clock),
.sensor(sensor_signal_i[18]),
.combined_data(sensor_combined_data_18)
);
lighthouse_sensor awesome_lighthouse19 (
.clk(clock),
.sensor(sensor_signal_i[19]),
.combined_data(sensor_combined_data_19)
);
lighthouse_sensor awesome_lighthouse20 (
.clk(clock),
.sensor(sensor_signal_i[20]),
.combined_data(sensor_combined_data_20)
);
lighthouse_sensor awesome_lighthouse21 (
.clk(clock),
.sensor(sensor_signal_i[21]),
.combined_data(sensor_combined_data_21)
);
lighthouse_sensor awesome_lighthouse22 (
.clk(clock),
.sensor(sensor_signal_i[22]),
.combined_data(sensor_combined_data_22)
);
lighthouse_sensor awesome_lighthouse23 (
.clk(clock),
.sensor(sensor_signal_i[23]),
.combined_data(sensor_combined_data_23)
);
lighthouse_sensor awesome_lighthouse24 (
.clk(clock),
.sensor(sensor_signal_i[24]),
.combined_data(sensor_combined_data_24)
);
lighthouse_sensor awesome_lighthouse25 (
.clk(clock),
.sensor(sensor_signal_i[25]),
.combined_data(sensor_combined_data_25)
);
lighthouse_sensor awesome_lighthouse26 (
.clk(clock),
.sensor(sensor_signal_i[26]),
.combined_data(sensor_combined_data_26)
);
lighthouse_sensor awesome_lighthouse27 (
.clk(clock),
.sensor(sensor_signal_i[27]),
.combined_data(sensor_combined_data_27)
);
lighthouse_sensor awesome_lighthouse28 (
.clk(clock),
.sensor(sensor_signal_i[28]),
.combined_data(sensor_combined_data_28)
);
lighthouse_sensor awesome_lighthouse29 (
.clk(clock),
.sensor(sensor_signal_i[29]),
.combined_data(sensor_combined_data_29)
);
lighthouse_sensor awesome_lighthouse30 (
.clk(clock),
.sensor(sensor_signal_i[30]),
.combined_data(sensor_combined_data_30)
);
lighthouse_sensor awesome_lighthouse31 (
.clk(clock),
.sensor(sensor_signal_i[31]),
.combined_data(sensor_combined_data_31)
);
endmodule | module DarkRoom (
input clock,
input reset_n,
input [5:0] address,
input write,
input signed [31:0] writedata,
input read,
output signed [31:0] readdata,
output waitrequest,
input [31:0] sensor_signal_i,
output [6:0] LED
); |
wire [31:0] sensor_combined_data_00;
wire [31:0] sensor_combined_data_01;
wire [31:0] sensor_combined_data_02;
wire [31:0] sensor_combined_data_03;
wire [31:0] sensor_combined_data_04;
wire [31:0] sensor_combined_data_05;
wire [31:0] sensor_combined_data_06;
wire [31:0] sensor_combined_data_07;
wire [31:0] sensor_combined_data_08;
wire [31:0] sensor_combined_data_09;
wire [31:0] sensor_combined_data_10;
wire [31:0] sensor_combined_data_11;
wire [31:0] sensor_combined_data_12;
wire [31:0] sensor_combined_data_13;
wire [31:0] sensor_combined_data_14;
wire [31:0] sensor_combined_data_15;
wire [31:0] sensor_combined_data_16;
wire [31:0] sensor_combined_data_17;
wire [31:0] sensor_combined_data_18;
wire [31:0] sensor_combined_data_19;
wire [31:0] sensor_combined_data_20;
wire [31:0] sensor_combined_data_21;
wire [31:0] sensor_combined_data_22;
wire [31:0] sensor_combined_data_23;
wire [31:0] sensor_combined_data_24;
wire [31:0] sensor_combined_data_25;
wire [31:0] sensor_combined_data_26;
wire [31:0] sensor_combined_data_27;
wire [31:0] sensor_combined_data_28;
wire [31:0] sensor_combined_data_29;
wire [31:0] sensor_combined_data_30;
wire [31:0] sensor_combined_data_31;
assign readdata =
(address == 0) ? sensor_combined_data_00 :
(address == 1) ? sensor_combined_data_01 :
(address == 2) ? sensor_combined_data_02 :
(address == 3) ? sensor_combined_data_03 :
(address == 4) ? sensor_combined_data_04 :
(address == 5) ? sensor_combined_data_05 :
(address == 6) ? sensor_combined_data_06 :
(address == 7) ? sensor_combined_data_07 :
(address == 8) ? sensor_combined_data_08 :
(address == 9) ? sensor_combined_data_09 :
(address == 10) ? sensor_combined_data_10 :
(address == 11) ? sensor_combined_data_11 :
(address == 12) ? sensor_combined_data_12 :
(address == 13) ? sensor_combined_data_13 :
(address == 14) ? sensor_combined_data_14 :
(address == 15) ? sensor_combined_data_15 :
(address == 16) ? sensor_combined_data_16 :
(address == 17) ? sensor_combined_data_17 :
(address == 18) ? sensor_combined_data_18 :
(address == 19) ? sensor_combined_data_19 :
(address == 20) ? sensor_combined_data_20 :
(address == 21) ? sensor_combined_data_21 :
(address == 22) ? sensor_combined_data_22 :
(address == 23) ? sensor_combined_data_23 :
(address == 24) ? sensor_combined_data_24 :
(address == 25) ? sensor_combined_data_25 :
(address == 26) ? sensor_combined_data_26 :
(address == 27) ? sensor_combined_data_27 :
(address == 28) ? sensor_combined_data_28 :
(address == 29) ? sensor_combined_data_29 :
(address == 30) ? sensor_combined_data_30 :
(address == 31) ? sensor_combined_data_31 :
32'hDEAD_BEEF;
assign waitrequest = 0;
lighthouse_sensor awesome_lighthouse00 (
.clk(clock),
.sensor(sensor_signal_i[0]),
.combined_data(sensor_combined_data_00)
);
lighthouse_sensor awesome_lighthouse01 (
.clk(clock),
.sensor(sensor_signal_i[1]),
.combined_data(sensor_combined_data_01)
);
lighthouse_sensor awesome_lighthouse02 (
.clk(clock),
.sensor(sensor_signal_i[2]),
.combined_data(sensor_combined_data_02)
);
lighthouse_sensor awesome_lighthouse03 (
.clk(clock),
.sensor(sensor_signal_i[3]),
.combined_data(sensor_combined_data_03)
);
lighthouse_sensor awesome_lighthouse04 (
.clk(clock),
.sensor(sensor_signal_i[4]),
.combined_data(sensor_combined_data_04)
);
lighthouse_sensor awesome_lighthouse05 (
.clk(clock),
.sensor(sensor_signal_i[5]),
.combined_data(sensor_combined_data_05)
);
lighthouse_sensor awesome_lighthouse06 (
.clk(clock),
.sensor(sensor_signal_i[6]),
.combined_data(sensor_combined_data_06)
);
lighthouse_sensor awesome_lighthouse07 (
.clk(clock),
.sensor(sensor_signal_i[7]),
.combined_data(sensor_combined_data_07)
);
lighthouse_sensor awesome_lighthouse08 (
.clk(clock),
.sensor(sensor_signal_i[8]),
.combined_data(sensor_combined_data_08)
);
lighthouse_sensor awesome_lighthouse09 (
.clk(clock),
.sensor(sensor_signal_i[9]),
.combined_data(sensor_combined_data_09)
);
lighthouse_sensor awesome_lighthouse10 (
.clk(clock),
.sensor(sensor_signal_i[10]),
.combined_data(sensor_combined_data_10)
);
lighthouse_sensor awesome_lighthouse11 (
.clk(clock),
.sensor(sensor_signal_i[11]),
.combined_data(sensor_combined_data_11)
);
lighthouse_sensor awesome_lighthouse12 (
.clk(clock),
.sensor(sensor_signal_i[12]),
.combined_data(sensor_combined_data_12)
);
lighthouse_sensor awesome_lighthouse13 (
.clk(clock),
.sensor(sensor_signal_i[13]),
.combined_data(sensor_combined_data_13)
);
lighthouse_sensor awesome_lighthouse14 (
.clk(clock),
.sensor(sensor_signal_i[14]),
.combined_data(sensor_combined_data_14)
);
lighthouse_sensor awesome_lighthouse15 (
.clk(clock),
.sensor(sensor_signal_i[15]),
.combined_data(sensor_combined_data_15)
);
lighthouse_sensor awesome_lighthouse16 (
.clk(clock),
.sensor(sensor_signal_i[16]),
.combined_data(sensor_combined_data_16)
);
lighthouse_sensor awesome_lighthouse17 (
.clk(clock),
.sensor(sensor_signal_i[17]),
.combined_data(sensor_combined_data_17)
);
lighthouse_sensor awesome_lighthouse18 (
.clk(clock),
.sensor(sensor_signal_i[18]),
.combined_data(sensor_combined_data_18)
);
lighthouse_sensor awesome_lighthouse19 (
.clk(clock),
.sensor(sensor_signal_i[19]),
.combined_data(sensor_combined_data_19)
);
lighthouse_sensor awesome_lighthouse20 (
.clk(clock),
.sensor(sensor_signal_i[20]),
.combined_data(sensor_combined_data_20)
);
lighthouse_sensor awesome_lighthouse21 (
.clk(clock),
.sensor(sensor_signal_i[21]),
.combined_data(sensor_combined_data_21)
);
lighthouse_sensor awesome_lighthouse22 (
.clk(clock),
.sensor(sensor_signal_i[22]),
.combined_data(sensor_combined_data_22)
);
lighthouse_sensor awesome_lighthouse23 (
.clk(clock),
.sensor(sensor_signal_i[23]),
.combined_data(sensor_combined_data_23)
);
lighthouse_sensor awesome_lighthouse24 (
.clk(clock),
.sensor(sensor_signal_i[24]),
.combined_data(sensor_combined_data_24)
);
lighthouse_sensor awesome_lighthouse25 (
.clk(clock),
.sensor(sensor_signal_i[25]),
.combined_data(sensor_combined_data_25)
);
lighthouse_sensor awesome_lighthouse26 (
.clk(clock),
.sensor(sensor_signal_i[26]),
.combined_data(sensor_combined_data_26)
);
lighthouse_sensor awesome_lighthouse27 (
.clk(clock),
.sensor(sensor_signal_i[27]),
.combined_data(sensor_combined_data_27)
);
lighthouse_sensor awesome_lighthouse28 (
.clk(clock),
.sensor(sensor_signal_i[28]),
.combined_data(sensor_combined_data_28)
);
lighthouse_sensor awesome_lighthouse29 (
.clk(clock),
.sensor(sensor_signal_i[29]),
.combined_data(sensor_combined_data_29)
);
lighthouse_sensor awesome_lighthouse30 (
.clk(clock),
.sensor(sensor_signal_i[30]),
.combined_data(sensor_combined_data_30)
);
lighthouse_sensor awesome_lighthouse31 (
.clk(clock),
.sensor(sensor_signal_i[31]),
.combined_data(sensor_combined_data_31)
);
endmodule | 1 |
141,915 | data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v | 96,222,896 | MYOControl.v | v | 667 | 105 | [] | [] | [] | null | line:108: before: "controller0" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:241: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef0;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:242: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef1;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:243: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef2;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:244: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef3;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:245: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef4;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:246: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef5;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:247: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:125: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reset_myo_control\' generates 1 bits.\n : ... In instance MYOControl\n ((address == 0))? reset_myo_control :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:126: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'spi_activated\' generates 1 bits.\n : ... In instance MYOControl\n ((address == 1))? spi_activated :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:134: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'velocity0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 10))? velocity0 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:135: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'velocity1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 11))? velocity1 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:136: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'velocity2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 12))? velocity2 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:137: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'velocity3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 13))? velocity3 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:138: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'velocity4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 14))? velocity4 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:139: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'velocity5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 15))? velocity5 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:140: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'velocity6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 16))? velocity6 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:141: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'current0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 18))? current0 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:142: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'current1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 19))? current1 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:143: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'current2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 20))? current2 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:144: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'current3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 21))? current3 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:145: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'current4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 22))? current4 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:146: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'current5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 23))? current5 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:147: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'current6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 24))? current6 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:148: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'displacement0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 26))? displacement0 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:149: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'displacement1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 27))? displacement1 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:150: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'displacement2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 28))? displacement2 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:151: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'displacement3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 29))? displacement3 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:152: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'displacement4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 30))? displacement4 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:153: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'displacement5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 31))? displacement5 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:154: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'displacement6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 32))? displacement6 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:155: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kp0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 34))? Kp0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:156: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kp1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 35))? Kp1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:157: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kp2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 36))? Kp2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:158: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kp3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 37))? Kp3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:159: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kp4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 38))? Kp4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:160: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kp5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 39))? Kp5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:161: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kp6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 40))? Kp6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:162: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kd0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 42))? Kd0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:163: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kd1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 43))? Kd1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:164: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kd2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 44))? Kd2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:165: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kd3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 45))? Kd3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:166: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kd4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 46))? Kd4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:167: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kd5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 47))? Kd5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:168: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Kd6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 48))? Kd6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:169: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Ki0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 50))? Ki0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:170: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Ki1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 51))? Ki1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:171: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Ki2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 52))? Ki2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:172: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Ki3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 53))? Ki3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Ki4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 54))? Ki4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:174: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Ki5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 55))? Ki5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:175: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Ki6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 56))? Ki6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:183: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'forwardGain0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 66))? forwardGain0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:184: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'forwardGain1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 67))? forwardGain1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:185: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'forwardGain2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 68))? forwardGain2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:186: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'forwardGain3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 69))? forwardGain3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:187: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'forwardGain4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 70))? forwardGain4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:188: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'forwardGain5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 71))? forwardGain5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:189: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'forwardGain6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 72))? forwardGain6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:190: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputPosMax0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 74))? outputPosMax0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:191: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputPosMax1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 75))? outputPosMax1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:192: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputPosMax2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 76))? outputPosMax2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:193: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputPosMax3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 77))? outputPosMax3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:194: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputPosMax4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 78))? outputPosMax4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:195: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputPosMax5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 79))? outputPosMax5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:196: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputPosMax6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 80))? outputPosMax6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:197: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputNegMax0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 82))? outputNegMax0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:198: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputNegMax1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 83))? outputNegMax1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:199: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputNegMax2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 84))? outputNegMax2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:200: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputNegMax3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 85))? outputNegMax3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:201: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputNegMax4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 86))? outputNegMax4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:202: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputNegMax5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 87))? outputNegMax5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:203: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'outputNegMax6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 88))? outputNegMax6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:204: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralNegMax0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 90))? IntegralNegMax0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:205: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralNegMax1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 91))? IntegralNegMax1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:206: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralNegMax2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 92))? IntegralNegMax2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:207: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralNegMax3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 93))? IntegralNegMax3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:208: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralNegMax4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 94))? IntegralNegMax4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:209: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralNegMax5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 95))? IntegralNegMax5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:210: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralNegMax6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 96))? IntegralNegMax6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:211: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralPosMax0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 98))? IntegralPosMax0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:212: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralPosMax1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 99))? IntegralPosMax1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:213: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralPosMax2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 100))? IntegralPosMax2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:214: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralPosMax3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 101))? IntegralPosMax3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:215: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralPosMax4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 102))? IntegralPosMax4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:216: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralPosMax5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 103))? IntegralPosMax5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:217: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'IntegralPosMax6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 104))? IntegralPosMax6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:218: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'deadBand0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 106))? deadBand0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:219: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'deadBand1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 107))? deadBand1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:220: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'deadBand2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 108))? deadBand2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:221: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'deadBand3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 109))? deadBand3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:222: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'deadBand4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 110))? deadBand4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:223: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'deadBand5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 111))? deadBand5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:224: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'deadBand6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 112))? deadBand6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:225: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'controller0\' generates 2 bits.\n : ... In instance MYOControl\n ((address == 114))? controller0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:226: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'controller1\' generates 2 bits.\n : ... In instance MYOControl\n ((address == 115))? controller1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:227: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'controller2\' generates 2 bits.\n : ... In instance MYOControl\n ((address == 116))? controller2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:228: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'controller3\' generates 2 bits.\n : ... In instance MYOControl\n ((address == 117))? controller3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:229: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'controller4\' generates 2 bits.\n : ... In instance MYOControl\n ((address == 118))? controller4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:230: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'controller5\' generates 2 bits.\n : ... In instance MYOControl\n ((address == 119))? controller5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:231: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'controller6\' generates 2 bits.\n : ... In instance MYOControl\n ((address == 120))? controller6:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:232: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pwmRef0\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 122))? pwmRef0:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:233: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pwmRef1\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 123))? pwmRef1:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:234: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pwmRef2\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 124))? pwmRef2:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:235: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pwmRef3\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 125))? pwmRef3:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:236: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pwmRef4\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 126))? pwmRef4:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:237: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pwmRef5\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 127))? pwmRef5:\n ^\n%Warning-WIDTH: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:238: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pwmRef6\' generates 16 bits.\n : ... In instance MYOControl\n ((address == 128))? pwmRef6:\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:454: Little bit endian vector: MSB < LSB of bit range: 0:31\nwire signed [0:31] position; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:455: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] velocity;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:456: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] current;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:457: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire [0:15] displacement;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:451: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire [0:15] Word;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:453: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] pwmRef;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:458: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] sensor1;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:459: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire signed [0:15] sensor2;\n ^\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:480: Cannot find file containing module: \'SpiControl\'\nSpiControl spi_control(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules,data/full_repos/permissive/96222896/SpiControl\n data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules,data/full_repos/permissive/96222896/SpiControl.v\n data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules,data/full_repos/permissive/96222896/SpiControl.sv\n SpiControl\n SpiControl.v\n SpiControl.sv\n obj_dir/SpiControl\n obj_dir/SpiControl.v\n obj_dir/SpiControl.sv\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:502: Cannot find file containing module: \'spi_master\'\nspi_master #(16, 1\'b0, 1\'b1, 2, 5) spi(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:518: Cannot find file containing module: \'PIDController\'\nPIDController pid_controller0(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:539: Cannot find file containing module: \'PIDController\'\nPIDController pid_controller1(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:560: Cannot find file containing module: \'PIDController\'\nPIDController pid_controller2(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:581: Cannot find file containing module: \'PIDController\'\nPIDController pid_controller3(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:602: Cannot find file containing module: \'PIDController\'\nPIDController pid_controller4(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:623: Cannot find file containing module: \'PIDController\'\nPIDController pid_controller5(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/96222896/de10-nano-soc/myoFPGA/de10-nano-soc/soc_system/synthesis/submodules/MYOControl.v:644: Cannot find file containing module: \'PIDController\'\nPIDController pid_controller6(\n^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 115 warning(s)\n' | 312,720 | module | module MYOControl (
input clock,
input reset,
input [7:0] address,
input write,
input signed [31:0] writedata,
input read,
output signed [31:0] readdata,
output waitrequest,
output [6:0] ss_n_o,
input miso,
output mosi,
output sck
);
reg signed [15:0] Kp0;
reg signed [15:0] Kp1;
reg signed [15:0] Kp2;
reg signed [15:0] Kp3;
reg signed [15:0] Kp4;
reg signed [15:0] Kp5;
reg signed [15:0] Kp6;
reg signed [15:0] Kd0;
reg signed [15:0] Kd1;
reg signed [15:0] Kd2;
reg signed [15:0] Kd3;
reg signed [15:0] Kd4;
reg signed [15:0] Kd5;
reg signed [15:0] Kd6;
reg signed [15:0] Ki0;
reg signed [15:0] Ki1;
reg signed [15:0] Ki2;
reg signed [15:0] Ki3;
reg signed [15:0] Ki4;
reg signed [15:0] Ki5;
reg signed [15:0] Ki6;
reg signed [31:0] sp0;
reg signed [31:0] sp1;
reg signed [31:0] sp2;
reg signed [31:0] sp3;
reg signed [31:0] sp4;
reg signed [31:0] sp5;
reg signed [31:0] sp6;
reg signed [15:0] forwardGain0;
reg signed [15:0] forwardGain1;
reg signed [15:0] forwardGain2;
reg signed [15:0] forwardGain3;
reg signed [15:0] forwardGain4;
reg signed [15:0] forwardGain5;
reg signed [15:0] forwardGain6;
reg signed [15:0] outputPosMax0;
reg signed [15:0] outputPosMax1;
reg signed [15:0] outputPosMax2;
reg signed [15:0] outputPosMax3;
reg signed [15:0] outputPosMax4;
reg signed [15:0] outputPosMax5;
reg signed [15:0] outputPosMax6;
reg signed [15:0] outputNegMax0;
reg signed [15:0] outputNegMax1;
reg signed [15:0] outputNegMax2;
reg signed [15:0] outputNegMax3;
reg signed [15:0] outputNegMax4;
reg signed [15:0] outputNegMax5;
reg signed [15:0] outputNegMax6;
reg signed [15:0] IntegralNegMax0;
reg signed [15:0] IntegralNegMax1;
reg signed [15:0] IntegralNegMax2;
reg signed [15:0] IntegralNegMax3;
reg signed [15:0] IntegralNegMax4;
reg signed [15:0] IntegralNegMax5;
reg signed [15:0] IntegralNegMax6;
reg signed [15:0] IntegralPosMax0;
reg signed [15:0] IntegralPosMax1;
reg signed [15:0] IntegralPosMax2;
reg signed [15:0] IntegralPosMax3;
reg signed [15:0] IntegralPosMax4;
reg signed [15:0] IntegralPosMax5;
reg signed [15:0] IntegralPosMax6;
reg signed [15:0] deadBand0;
reg signed [15:0] deadBand1;
reg signed [15:0] deadBand2;
reg signed [15:0] deadBand3;
reg signed [15:0] deadBand4;
reg signed [15:0] deadBand5;
reg signed [15:0] deadBand6;
reg unsigned [1:0] controller0;
reg unsigned [1:0] controller1;
reg unsigned [1:0] controller2;
reg unsigned [1:0] controller3;
reg unsigned [1:0] controller4;
reg unsigned [1:0] controller5;
reg unsigned [1:0] controller6;
reg reset_controller0;
reg reset_controller1;
reg reset_controller2;
reg reset_controller3;
reg reset_controller4;
reg reset_controller5;
reg reset_controller6;
assign readdata =
((address == 0))? reset_myo_control :
((address == 1))? spi_activated :
((address == 2))? position0 :
((address == 3))? position1 :
((address == 4))? position2 :
((address == 5))? position3 :
((address == 6))? position4 :
((address == 7))? position5 :
((address == 8))? position6 :
((address == 10))? velocity0 :
((address == 11))? velocity1 :
((address == 12))? velocity2 :
((address == 13))? velocity3 :
((address == 14))? velocity4 :
((address == 15))? velocity5 :
((address == 16))? velocity6 :
((address == 18))? current0 :
((address == 19))? current1 :
((address == 20))? current2 :
((address == 21))? current3 :
((address == 22))? current4 :
((address == 23))? current5 :
((address == 24))? current6 :
((address == 26))? displacement0 :
((address == 27))? displacement1 :
((address == 28))? displacement2 :
((address == 29))? displacement3 :
((address == 30))? displacement4 :
((address == 31))? displacement5 :
((address == 32))? displacement6 :
((address == 34))? Kp0:
((address == 35))? Kp1:
((address == 36))? Kp2:
((address == 37))? Kp3:
((address == 38))? Kp4:
((address == 39))? Kp5:
((address == 40))? Kp6:
((address == 42))? Kd0:
((address == 43))? Kd1:
((address == 44))? Kd2:
((address == 45))? Kd3:
((address == 46))? Kd4:
((address == 47))? Kd5:
((address == 48))? Kd6:
((address == 50))? Ki0:
((address == 51))? Ki1:
((address == 52))? Ki2:
((address == 53))? Ki3:
((address == 54))? Ki4:
((address == 55))? Ki5:
((address == 56))? Ki6:
((address == 58))? sp0:
((address == 59))? sp1:
((address == 60))? sp2:
((address == 61))? sp3:
((address == 62))? sp4:
((address == 63))? sp5:
((address == 64))? sp6:
((address == 66))? forwardGain0:
((address == 67))? forwardGain1:
((address == 68))? forwardGain2:
((address == 69))? forwardGain3:
((address == 70))? forwardGain4:
((address == 71))? forwardGain5:
((address == 72))? forwardGain6:
((address == 74))? outputPosMax0:
((address == 75))? outputPosMax1:
((address == 76))? outputPosMax2:
((address == 77))? outputPosMax3:
((address == 78))? outputPosMax4:
((address == 79))? outputPosMax5:
((address == 80))? outputPosMax6:
((address == 82))? outputNegMax0:
((address == 83))? outputNegMax1:
((address == 84))? outputNegMax2:
((address == 85))? outputNegMax3:
((address == 86))? outputNegMax4:
((address == 87))? outputNegMax5:
((address == 88))? outputNegMax6:
((address == 90))? IntegralNegMax0:
((address == 91))? IntegralNegMax1:
((address == 92))? IntegralNegMax2:
((address == 93))? IntegralNegMax3:
((address == 94))? IntegralNegMax4:
((address == 95))? IntegralNegMax5:
((address == 96))? IntegralNegMax6:
((address == 98))? IntegralPosMax0:
((address == 99))? IntegralPosMax1:
((address == 100))? IntegralPosMax2:
((address == 101))? IntegralPosMax3:
((address == 102))? IntegralPosMax4:
((address == 103))? IntegralPosMax5:
((address == 104))? IntegralPosMax6:
((address == 106))? deadBand0:
((address == 107))? deadBand1:
((address == 108))? deadBand2:
((address == 109))? deadBand3:
((address == 110))? deadBand4:
((address == 111))? deadBand5:
((address == 112))? deadBand6:
((address == 114))? controller0:
((address == 115))? controller1:
((address == 116))? controller2:
((address == 117))? controller3:
((address == 118))? controller4:
((address == 119))? controller5:
((address == 120))? controller6:
((address == 122))? pwmRef0:
((address == 123))? pwmRef1:
((address == 124))? pwmRef2:
((address == 125))? pwmRef3:
((address == 126))? pwmRef4:
((address == 127))? pwmRef5:
((address == 128))? pwmRef6:
32'hDEAD_BEEF;
wire signed [0:15] pwmRef0;
wire signed [0:15] pwmRef1;
wire signed [0:15] pwmRef2;
wire signed [0:15] pwmRef3;
wire signed [0:15] pwmRef4;
wire signed [0:15] pwmRef5;
wire signed [0:15] pwmRef6;
reg signed [31:0] position0;
reg signed [31:0] position1;
reg signed [31:0] position2;
reg signed [31:0] position3;
reg signed [31:0] position4;
reg signed [31:0] position5;
reg signed [31:0] position6;
reg signed [15:0] velocity0;
reg signed [15:0] velocity1;
reg signed [15:0] velocity2;
reg signed [15:0] velocity3;
reg signed [15:0] velocity4;
reg signed [15:0] velocity5;
reg signed [15:0] velocity6;
reg signed [15:0] current0;
reg signed [15:0] current1;
reg signed [15:0] current2;
reg signed [15:0] current3;
reg signed [15:0] current4;
reg signed [15:0] current5;
reg signed [15:0] current6;
reg [15:0] displacement0;
reg [15:0] displacement1;
reg [15:0] displacement2;
reg [15:0] displacement3;
reg [15:0] displacement4;
reg [15:0] displacement5;
reg [15:0] displacement6;
reg reset_myo_control;
reg spi_activated;
reg update_controller;
assign waitrequest = update_controller;
reg [2:0] motor;
reg [2:0] pid_update;
always @(posedge clock, posedge reset) begin: MYO_CONTROL_LOGIC
reg spi_done_prev;
if (reset == 1) begin
reset_myo_control <= 0;
spi_activated <= 0;
motor <= 0;
spi_done_prev <= 0;
end else begin
update_controller <= 0;
spi_done_prev <= spi_done;
if(spi_done_prev==0 && spi_done) begin
case(motor)
0: position0[31:0] <= position[0:31];
1: position1[31:0] <= position[0:31];
2: position2[31:0] <= position[0:31];
3: position3[31:0] <= position[0:31];
4: position4[31:0] <= position[0:31];
5: position5[31:0] <= position[0:31];
6: position6[31:0] <= position[0:31];
endcase
case(motor)
0: velocity0[15:0] <= velocity[0:15];
1: velocity1[15:0] <= velocity[0:15];
2: velocity2[15:0] <= velocity[0:15];
3: velocity3[15:0] <= velocity[0:15];
4: velocity4[15:0] <= velocity[0:15];
5: velocity5[15:0] <= velocity[0:15];
6: velocity6[15:0] <= velocity[0:15];
endcase
case(motor)
0: current0[15:0] <= current[0:15];
1: current1[15:0] <= current[0:15];
2: current2[15:0] <= current[0:15];
3: current3[15:0] <= current[0:15];
4: current4[15:0] <= current[0:15];
5: current5[15:0] <= current[0:15];
6: current6[15:0] <= current[0:15];
endcase
case(motor)
0: displacement0[15:0] <= displacement[0:15];
1: displacement1[15:0] <= displacement[0:15];
2: displacement2[15:0] <= displacement[0:15];
3: displacement3[15:0] <= displacement[0:15];
4: displacement4[15:0] <= displacement[0:15];
5: displacement5[15:0] <= displacement[0:15];
6: displacement6[15:0] <= displacement[0:15];
endcase
update_controller <= 1;
pid_update <= motor;
if(motor==6)
motor <= 0;
else
motor <= motor + 1;
end
reset_myo_control <= 0;
reset_controller0 <= 0;
reset_controller1 <= 0;
reset_controller2 <= 0;
reset_controller3 <= 0;
reset_controller4 <= 0;
reset_controller5 <= 0;
reset_controller6 <= 0;
if(write && ~waitrequest) begin
case(address)
0: reset_myo_control <= 1;
1: spi_activated <= (writedata[31:0]!=0);
34: Kp0 <= writedata[15:0];
35: Kp1 <= writedata[15:0];
36: Kp2 <= writedata[15:0];
37: Kp3 <= writedata[15:0];
38: Kp4 <= writedata[15:0];
39: Kp5 <= writedata[15:0];
40: Kp6 <= writedata[15:0];
42: Kd0 <= writedata[15:0];
43: Kd1 <= writedata[15:0];
44: Kd2 <= writedata[15:0];
45: Kd3 <= writedata[15:0];
46: Kd4 <= writedata[15:0];
47: Kd5 <= writedata[15:0];
48: Kd6 <= writedata[15:0];
50: Ki0 <= writedata[15:0];
51: Ki1 <= writedata[15:0];
52: Ki2 <= writedata[15:0];
53: Ki3 <= writedata[15:0];
54: Ki4 <= writedata[15:0];
55: Ki5 <= writedata[15:0];
56: Ki6 <= writedata[15:0];
58: sp0 <= writedata[31:0];
59: sp1 <= writedata[31:0];
60: sp2 <= writedata[31:0];
61: sp3 <= writedata[31:0];
62: sp4 <= writedata[31:0];
63: sp5 <= writedata[31:0];
64: sp6 <= writedata[31:0];
66: forwardGain0 <= writedata[15:0];
67: forwardGain1 <= writedata[15:0];
68: forwardGain2 <= writedata[15:0];
69: forwardGain3 <= writedata[15:0];
70: forwardGain4 <= writedata[15:0];
71: forwardGain5 <= writedata[15:0];
72: forwardGain6 <= writedata[15:0];
74: outputPosMax0 <= writedata[15:0];
75: outputPosMax1 <= writedata[15:0];
76: outputPosMax2 <= writedata[15:0];
77: outputPosMax3 <= writedata[15:0];
78: outputPosMax4 <= writedata[15:0];
79: outputPosMax5 <= writedata[15:0];
80: outputPosMax6 <= writedata[15:0];
82: outputNegMax0 <= writedata[15:0];
83: outputNegMax1 <= writedata[15:0];
84: outputNegMax2 <= writedata[15:0];
85: outputNegMax3 <= writedata[15:0];
86: outputNegMax4 <= writedata[15:0];
87: outputNegMax5 <= writedata[15:0];
88: outputNegMax6 <= writedata[15:0];
90: IntegralNegMax0 <= writedata[15:0];
91: IntegralNegMax1 <= writedata[15:0];
92: IntegralNegMax2 <= writedata[15:0];
93: IntegralNegMax3 <= writedata[15:0];
94: IntegralNegMax4 <= writedata[15:0];
95: IntegralNegMax5 <= writedata[15:0];
96: IntegralNegMax6 <= writedata[15:0];
98: IntegralPosMax0 <= writedata[15:0];
99: IntegralPosMax1 <= writedata[15:0];
100: IntegralPosMax2 <= writedata[15:0];
101: IntegralPosMax3 <= writedata[15:0];
102: IntegralPosMax4 <= writedata[15:0];
103: IntegralPosMax5 <= writedata[15:0];
104: IntegralPosMax6 <= writedata[15:0];
106: deadBand0 <= writedata[15:0];
107: deadBand1 <= writedata[15:0];
108: deadBand2 <= writedata[15:0];
109: deadBand3 <= writedata[15:0];
110: deadBand4 <= writedata[15:0];
111: deadBand5 <= writedata[15:0];
112: deadBand6 <= writedata[15:0];
114: controller0 <= writedata[1:0];
115: controller1 <= writedata[1:0];
116: controller2 <= writedata[1:0];
117: controller3 <= writedata[1:0];
118: controller4 <= writedata[1:0];
119: controller5 <= writedata[1:0];
120: controller6 <= writedata[1:0];
130: reset_controller0 <= 1;
131: reset_controller1 <= 1;
132: reset_controller2 <= 1;
133: reset_controller3 <= 1;
134: reset_controller4 <= 1;
135: reset_controller5 <= 1;
136: reset_controller6 <= 1;
endcase
end
end
end
wire di_req, wr_ack, do_valid, wren, spi_done, ss_n;
wire [0:15] Word;
wire [15:0] data_out;
wire signed [0:15] pwmRef;
wire signed [0:31] position;
wire signed [0:15] velocity;
wire signed [0:15] current;
wire [0:15] displacement;
wire signed [0:15] sensor1;
wire signed [0:15] sensor2;
assign pwmRef =
(motor==0)?pwmRef0:
(motor==1)?pwmRef1:
(motor==2)?pwmRef2:
(motor==3)?pwmRef3:
(motor==4)?pwmRef4:
(motor==5)?pwmRef5:
(motor==6)?pwmRef6:
0;
assign ss_n_o[0] = (motor==0?ss_n:1);
assign ss_n_o[1] = (motor==1?ss_n:1);
assign ss_n_o[2] = (motor==2?ss_n:1);
assign ss_n_o[3] = (motor==3?ss_n:1);
assign ss_n_o[4] = (motor==4?ss_n:1);
assign ss_n_o[5] = (motor==5?ss_n:1);
assign ss_n_o[6] = (motor==6?ss_n:1);
SpiControl spi_control(
.clock(clock),
.reset(reset_myo_control),
.di_req(di_req),
.write_ack(wr_ack),
.data_read_valid(do_valid),
.data_read(data_out[15:0]),
.start(spi_activated && update_controller),
.Word(Word[0:15]),
.wren(wren),
.spi_done(spi_done),
.pwmRef(pwmRef),
.position(position),
.velocity(velocity),
.current(current),
.displacement(displacement),
.sensor1(sensor1),
.sensor2(sensor2),
.ss_n(ss_n)
);
spi_master #(16, 1'b0, 1'b1, 2, 5) spi(
.sclk_i(clock),
.pclk_i(clock),
.rst_i(reset_myo_control),
.spi_miso_i(miso),
.di_i(Word[0:15]),
.wren_i(wren),
.spi_ssel_o(ss_n),
.spi_sck_o(sck),
.spi_mosi_o(mosi),
.di_req_o(di_req),
.wr_ack_o(wr_ack),
.do_valid_o(do_valid),
.do_o(data_out[15:0])
);
PIDController pid_controller0(
.clock(clock),
.reset(reset_myo_control||reset_controller0),
.Kp(Kp0),
.Kd(Kd0),
.Ki(Ki0),
.sp(sp0),
.forwardGain(forwardGain0),
.outputPosMax(outputPosMax0),
.outputNegMax(outputNegMax0),
.IntegralNegMax(IntegralNegMax0),
.IntegralPosMax(IntegralPosMax0),
.deadBand(deadBand0),
.controller(controller0),
.position(position0),
.velocity(velocity0),
.displacement(displacement0),
.update_controller(pid_update==0 && update_controller),
.pwmRef(pwmRef0)
);
PIDController pid_controller1(
.clock(clock),
.reset(reset_myo_control||reset_controller1),
.Kp(Kp1),
.Kd(Kd1),
.Ki(Ki1),
.sp(sp1),
.forwardGain(forwardGain1),
.outputPosMax(outputPosMax1),
.outputNegMax(outputNegMax1),
.IntegralNegMax(IntegralNegMax1),
.IntegralPosMax(IntegralPosMax1),
.deadBand(deadBand1),
.controller(controller1),
.position(position1),
.velocity(velocity1),
.displacement(displacement1),
.update_controller(pid_update==1 && update_controller),
.pwmRef(pwmRef1)
);
PIDController pid_controller2(
.clock(clock),
.reset(reset_myo_control||reset_controller2),
.Kp(Kp2),
.Kd(Kd2),
.Ki(Ki2),
.sp(sp2),
.forwardGain(forwardGain2),
.outputPosMax(outputPosMax2),
.outputNegMax(outputNegMax2),
.IntegralNegMax(IntegralNegMax2),
.IntegralPosMax(IntegralPosMax2),
.deadBand(deadBand2),
.controller(controller2),
.position(position2),
.velocity(velocity2),
.displacement(displacement2),
.update_controller(pid_update==2 && update_controller),
.pwmRef(pwmRef2)
);
PIDController pid_controller3(
.clock(clock),
.reset(reset_myo_control||reset_controller3),
.Kp(Kp3),
.Kd(Kd3),
.Ki(Ki3),
.sp(sp3),
.forwardGain(forwardGain3),
.outputPosMax(outputPosMax3),
.outputNegMax(outputNegMax3),
.IntegralNegMax(IntegralNegMax3),
.IntegralPosMax(IntegralPosMax3),
.deadBand(deadBand3),
.controller(controller3),
.position(position3),
.velocity(velocity3),
.displacement(displacement3),
.update_controller(pid_update==3 && update_controller),
.pwmRef(pwmRef3)
);
PIDController pid_controller4(
.clock(clock),
.reset(reset_myo_control||reset_controller4),
.Kp(Kp4),
.Kd(Kd4),
.Ki(Ki4),
.sp(sp4),
.forwardGain(forwardGain4),
.outputPosMax(outputPosMax4),
.outputNegMax(outputNegMax4),
.IntegralNegMax(IntegralNegMax4),
.IntegralPosMax(IntegralPosMax4),
.deadBand(deadBand4),
.controller(controller4),
.position(position4),
.velocity(velocity4),
.displacement(displacement4),
.update_controller(pid_update==4 && update_controller),
.pwmRef(pwmRef4)
);
PIDController pid_controller5(
.clock(clock),
.reset(reset_myo_control||reset_controller5),
.Kp(Kp5),
.Kd(Kd5),
.Ki(Ki5),
.sp(sp5),
.forwardGain(forwardGain5),
.outputPosMax(outputPosMax5),
.outputNegMax(outputNegMax5),
.IntegralNegMax(IntegralNegMax5),
.IntegralPosMax(IntegralPosMax5),
.deadBand(deadBand5),
.controller(controller5),
.position(position5),
.velocity(velocity5),
.displacement(displacement5),
.update_controller(pid_update==5 && update_controller),
.pwmRef(pwmRef5)
);
PIDController pid_controller6(
.clock(clock),
.reset(reset_myo_control||reset_controller6),
.Kp(Kp6),
.Kd(Kd6),
.Ki(Ki6),
.sp(sp6),
.forwardGain(forwardGain6),
.outputPosMax(outputPosMax6),
.outputNegMax(outputNegMax6),
.IntegralNegMax(IntegralNegMax6),
.IntegralPosMax(IntegralPosMax6),
.deadBand(deadBand6),
.controller(controller6),
.position(position6),
.velocity(velocity6),
.displacement(displacement6),
.update_controller(pid_update==6 && update_controller),
.pwmRef(pwmRef6)
);
endmodule | module MYOControl (
input clock,
input reset,
input [7:0] address,
input write,
input signed [31:0] writedata,
input read,
output signed [31:0] readdata,
output waitrequest,
output [6:0] ss_n_o,
input miso,
output mosi,
output sck
); |
reg signed [15:0] Kp0;
reg signed [15:0] Kp1;
reg signed [15:0] Kp2;
reg signed [15:0] Kp3;
reg signed [15:0] Kp4;
reg signed [15:0] Kp5;
reg signed [15:0] Kp6;
reg signed [15:0] Kd0;
reg signed [15:0] Kd1;
reg signed [15:0] Kd2;
reg signed [15:0] Kd3;
reg signed [15:0] Kd4;
reg signed [15:0] Kd5;
reg signed [15:0] Kd6;
reg signed [15:0] Ki0;
reg signed [15:0] Ki1;
reg signed [15:0] Ki2;
reg signed [15:0] Ki3;
reg signed [15:0] Ki4;
reg signed [15:0] Ki5;
reg signed [15:0] Ki6;
reg signed [31:0] sp0;
reg signed [31:0] sp1;
reg signed [31:0] sp2;
reg signed [31:0] sp3;
reg signed [31:0] sp4;
reg signed [31:0] sp5;
reg signed [31:0] sp6;
reg signed [15:0] forwardGain0;
reg signed [15:0] forwardGain1;
reg signed [15:0] forwardGain2;
reg signed [15:0] forwardGain3;
reg signed [15:0] forwardGain4;
reg signed [15:0] forwardGain5;
reg signed [15:0] forwardGain6;
reg signed [15:0] outputPosMax0;
reg signed [15:0] outputPosMax1;
reg signed [15:0] outputPosMax2;
reg signed [15:0] outputPosMax3;
reg signed [15:0] outputPosMax4;
reg signed [15:0] outputPosMax5;
reg signed [15:0] outputPosMax6;
reg signed [15:0] outputNegMax0;
reg signed [15:0] outputNegMax1;
reg signed [15:0] outputNegMax2;
reg signed [15:0] outputNegMax3;
reg signed [15:0] outputNegMax4;
reg signed [15:0] outputNegMax5;
reg signed [15:0] outputNegMax6;
reg signed [15:0] IntegralNegMax0;
reg signed [15:0] IntegralNegMax1;
reg signed [15:0] IntegralNegMax2;
reg signed [15:0] IntegralNegMax3;
reg signed [15:0] IntegralNegMax4;
reg signed [15:0] IntegralNegMax5;
reg signed [15:0] IntegralNegMax6;
reg signed [15:0] IntegralPosMax0;
reg signed [15:0] IntegralPosMax1;
reg signed [15:0] IntegralPosMax2;
reg signed [15:0] IntegralPosMax3;
reg signed [15:0] IntegralPosMax4;
reg signed [15:0] IntegralPosMax5;
reg signed [15:0] IntegralPosMax6;
reg signed [15:0] deadBand0;
reg signed [15:0] deadBand1;
reg signed [15:0] deadBand2;
reg signed [15:0] deadBand3;
reg signed [15:0] deadBand4;
reg signed [15:0] deadBand5;
reg signed [15:0] deadBand6;
reg unsigned [1:0] controller0;
reg unsigned [1:0] controller1;
reg unsigned [1:0] controller2;
reg unsigned [1:0] controller3;
reg unsigned [1:0] controller4;
reg unsigned [1:0] controller5;
reg unsigned [1:0] controller6;
reg reset_controller0;
reg reset_controller1;
reg reset_controller2;
reg reset_controller3;
reg reset_controller4;
reg reset_controller5;
reg reset_controller6;
assign readdata =
((address == 0))? reset_myo_control :
((address == 1))? spi_activated :
((address == 2))? position0 :
((address == 3))? position1 :
((address == 4))? position2 :
((address == 5))? position3 :
((address == 6))? position4 :
((address == 7))? position5 :
((address == 8))? position6 :
((address == 10))? velocity0 :
((address == 11))? velocity1 :
((address == 12))? velocity2 :
((address == 13))? velocity3 :
((address == 14))? velocity4 :
((address == 15))? velocity5 :
((address == 16))? velocity6 :
((address == 18))? current0 :
((address == 19))? current1 :
((address == 20))? current2 :
((address == 21))? current3 :
((address == 22))? current4 :
((address == 23))? current5 :
((address == 24))? current6 :
((address == 26))? displacement0 :
((address == 27))? displacement1 :
((address == 28))? displacement2 :
((address == 29))? displacement3 :
((address == 30))? displacement4 :
((address == 31))? displacement5 :
((address == 32))? displacement6 :
((address == 34))? Kp0:
((address == 35))? Kp1:
((address == 36))? Kp2:
((address == 37))? Kp3:
((address == 38))? Kp4:
((address == 39))? Kp5:
((address == 40))? Kp6:
((address == 42))? Kd0:
((address == 43))? Kd1:
((address == 44))? Kd2:
((address == 45))? Kd3:
((address == 46))? Kd4:
((address == 47))? Kd5:
((address == 48))? Kd6:
((address == 50))? Ki0:
((address == 51))? Ki1:
((address == 52))? Ki2:
((address == 53))? Ki3:
((address == 54))? Ki4:
((address == 55))? Ki5:
((address == 56))? Ki6:
((address == 58))? sp0:
((address == 59))? sp1:
((address == 60))? sp2:
((address == 61))? sp3:
((address == 62))? sp4:
((address == 63))? sp5:
((address == 64))? sp6:
((address == 66))? forwardGain0:
((address == 67))? forwardGain1:
((address == 68))? forwardGain2:
((address == 69))? forwardGain3:
((address == 70))? forwardGain4:
((address == 71))? forwardGain5:
((address == 72))? forwardGain6:
((address == 74))? outputPosMax0:
((address == 75))? outputPosMax1:
((address == 76))? outputPosMax2:
((address == 77))? outputPosMax3:
((address == 78))? outputPosMax4:
((address == 79))? outputPosMax5:
((address == 80))? outputPosMax6:
((address == 82))? outputNegMax0:
((address == 83))? outputNegMax1:
((address == 84))? outputNegMax2:
((address == 85))? outputNegMax3:
((address == 86))? outputNegMax4:
((address == 87))? outputNegMax5:
((address == 88))? outputNegMax6:
((address == 90))? IntegralNegMax0:
((address == 91))? IntegralNegMax1:
((address == 92))? IntegralNegMax2:
((address == 93))? IntegralNegMax3:
((address == 94))? IntegralNegMax4:
((address == 95))? IntegralNegMax5:
((address == 96))? IntegralNegMax6:
((address == 98))? IntegralPosMax0:
((address == 99))? IntegralPosMax1:
((address == 100))? IntegralPosMax2:
((address == 101))? IntegralPosMax3:
((address == 102))? IntegralPosMax4:
((address == 103))? IntegralPosMax5:
((address == 104))? IntegralPosMax6:
((address == 106))? deadBand0:
((address == 107))? deadBand1:
((address == 108))? deadBand2:
((address == 109))? deadBand3:
((address == 110))? deadBand4:
((address == 111))? deadBand5:
((address == 112))? deadBand6:
((address == 114))? controller0:
((address == 115))? controller1:
((address == 116))? controller2:
((address == 117))? controller3:
((address == 118))? controller4:
((address == 119))? controller5:
((address == 120))? controller6:
((address == 122))? pwmRef0:
((address == 123))? pwmRef1:
((address == 124))? pwmRef2:
((address == 125))? pwmRef3:
((address == 126))? pwmRef4:
((address == 127))? pwmRef5:
((address == 128))? pwmRef6:
32'hDEAD_BEEF;
wire signed [0:15] pwmRef0;
wire signed [0:15] pwmRef1;
wire signed [0:15] pwmRef2;
wire signed [0:15] pwmRef3;
wire signed [0:15] pwmRef4;
wire signed [0:15] pwmRef5;
wire signed [0:15] pwmRef6;
reg signed [31:0] position0;
reg signed [31:0] position1;
reg signed [31:0] position2;
reg signed [31:0] position3;
reg signed [31:0] position4;
reg signed [31:0] position5;
reg signed [31:0] position6;
reg signed [15:0] velocity0;
reg signed [15:0] velocity1;
reg signed [15:0] velocity2;
reg signed [15:0] velocity3;
reg signed [15:0] velocity4;
reg signed [15:0] velocity5;
reg signed [15:0] velocity6;
reg signed [15:0] current0;
reg signed [15:0] current1;
reg signed [15:0] current2;
reg signed [15:0] current3;
reg signed [15:0] current4;
reg signed [15:0] current5;
reg signed [15:0] current6;
reg [15:0] displacement0;
reg [15:0] displacement1;
reg [15:0] displacement2;
reg [15:0] displacement3;
reg [15:0] displacement4;
reg [15:0] displacement5;
reg [15:0] displacement6;
reg reset_myo_control;
reg spi_activated;
reg update_controller;
assign waitrequest = update_controller;
reg [2:0] motor;
reg [2:0] pid_update;
always @(posedge clock, posedge reset) begin: MYO_CONTROL_LOGIC
reg spi_done_prev;
if (reset == 1) begin
reset_myo_control <= 0;
spi_activated <= 0;
motor <= 0;
spi_done_prev <= 0;
end else begin
update_controller <= 0;
spi_done_prev <= spi_done;
if(spi_done_prev==0 && spi_done) begin
case(motor)
0: position0[31:0] <= position[0:31];
1: position1[31:0] <= position[0:31];
2: position2[31:0] <= position[0:31];
3: position3[31:0] <= position[0:31];
4: position4[31:0] <= position[0:31];
5: position5[31:0] <= position[0:31];
6: position6[31:0] <= position[0:31];
endcase
case(motor)
0: velocity0[15:0] <= velocity[0:15];
1: velocity1[15:0] <= velocity[0:15];
2: velocity2[15:0] <= velocity[0:15];
3: velocity3[15:0] <= velocity[0:15];
4: velocity4[15:0] <= velocity[0:15];
5: velocity5[15:0] <= velocity[0:15];
6: velocity6[15:0] <= velocity[0:15];
endcase
case(motor)
0: current0[15:0] <= current[0:15];
1: current1[15:0] <= current[0:15];
2: current2[15:0] <= current[0:15];
3: current3[15:0] <= current[0:15];
4: current4[15:0] <= current[0:15];
5: current5[15:0] <= current[0:15];
6: current6[15:0] <= current[0:15];
endcase
case(motor)
0: displacement0[15:0] <= displacement[0:15];
1: displacement1[15:0] <= displacement[0:15];
2: displacement2[15:0] <= displacement[0:15];
3: displacement3[15:0] <= displacement[0:15];
4: displacement4[15:0] <= displacement[0:15];
5: displacement5[15:0] <= displacement[0:15];
6: displacement6[15:0] <= displacement[0:15];
endcase
update_controller <= 1;
pid_update <= motor;
if(motor==6)
motor <= 0;
else
motor <= motor + 1;
end
reset_myo_control <= 0;
reset_controller0 <= 0;
reset_controller1 <= 0;
reset_controller2 <= 0;
reset_controller3 <= 0;
reset_controller4 <= 0;
reset_controller5 <= 0;
reset_controller6 <= 0;
if(write && ~waitrequest) begin
case(address)
0: reset_myo_control <= 1;
1: spi_activated <= (writedata[31:0]!=0);
34: Kp0 <= writedata[15:0];
35: Kp1 <= writedata[15:0];
36: Kp2 <= writedata[15:0];
37: Kp3 <= writedata[15:0];
38: Kp4 <= writedata[15:0];
39: Kp5 <= writedata[15:0];
40: Kp6 <= writedata[15:0];
42: Kd0 <= writedata[15:0];
43: Kd1 <= writedata[15:0];
44: Kd2 <= writedata[15:0];
45: Kd3 <= writedata[15:0];
46: Kd4 <= writedata[15:0];
47: Kd5 <= writedata[15:0];
48: Kd6 <= writedata[15:0];
50: Ki0 <= writedata[15:0];
51: Ki1 <= writedata[15:0];
52: Ki2 <= writedata[15:0];
53: Ki3 <= writedata[15:0];
54: Ki4 <= writedata[15:0];
55: Ki5 <= writedata[15:0];
56: Ki6 <= writedata[15:0];
58: sp0 <= writedata[31:0];
59: sp1 <= writedata[31:0];
60: sp2 <= writedata[31:0];
61: sp3 <= writedata[31:0];
62: sp4 <= writedata[31:0];
63: sp5 <= writedata[31:0];
64: sp6 <= writedata[31:0];
66: forwardGain0 <= writedata[15:0];
67: forwardGain1 <= writedata[15:0];
68: forwardGain2 <= writedata[15:0];
69: forwardGain3 <= writedata[15:0];
70: forwardGain4 <= writedata[15:0];
71: forwardGain5 <= writedata[15:0];
72: forwardGain6 <= writedata[15:0];
74: outputPosMax0 <= writedata[15:0];
75: outputPosMax1 <= writedata[15:0];
76: outputPosMax2 <= writedata[15:0];
77: outputPosMax3 <= writedata[15:0];
78: outputPosMax4 <= writedata[15:0];
79: outputPosMax5 <= writedata[15:0];
80: outputPosMax6 <= writedata[15:0];
82: outputNegMax0 <= writedata[15:0];
83: outputNegMax1 <= writedata[15:0];
84: outputNegMax2 <= writedata[15:0];
85: outputNegMax3 <= writedata[15:0];
86: outputNegMax4 <= writedata[15:0];
87: outputNegMax5 <= writedata[15:0];
88: outputNegMax6 <= writedata[15:0];
90: IntegralNegMax0 <= writedata[15:0];
91: IntegralNegMax1 <= writedata[15:0];
92: IntegralNegMax2 <= writedata[15:0];
93: IntegralNegMax3 <= writedata[15:0];
94: IntegralNegMax4 <= writedata[15:0];
95: IntegralNegMax5 <= writedata[15:0];
96: IntegralNegMax6 <= writedata[15:0];
98: IntegralPosMax0 <= writedata[15:0];
99: IntegralPosMax1 <= writedata[15:0];
100: IntegralPosMax2 <= writedata[15:0];
101: IntegralPosMax3 <= writedata[15:0];
102: IntegralPosMax4 <= writedata[15:0];
103: IntegralPosMax5 <= writedata[15:0];
104: IntegralPosMax6 <= writedata[15:0];
106: deadBand0 <= writedata[15:0];
107: deadBand1 <= writedata[15:0];
108: deadBand2 <= writedata[15:0];
109: deadBand3 <= writedata[15:0];
110: deadBand4 <= writedata[15:0];
111: deadBand5 <= writedata[15:0];
112: deadBand6 <= writedata[15:0];
114: controller0 <= writedata[1:0];
115: controller1 <= writedata[1:0];
116: controller2 <= writedata[1:0];
117: controller3 <= writedata[1:0];
118: controller4 <= writedata[1:0];
119: controller5 <= writedata[1:0];
120: controller6 <= writedata[1:0];
130: reset_controller0 <= 1;
131: reset_controller1 <= 1;
132: reset_controller2 <= 1;
133: reset_controller3 <= 1;
134: reset_controller4 <= 1;
135: reset_controller5 <= 1;
136: reset_controller6 <= 1;
endcase
end
end
end
wire di_req, wr_ack, do_valid, wren, spi_done, ss_n;
wire [0:15] Word;
wire [15:0] data_out;
wire signed [0:15] pwmRef;
wire signed [0:31] position;
wire signed [0:15] velocity;
wire signed [0:15] current;
wire [0:15] displacement;
wire signed [0:15] sensor1;
wire signed [0:15] sensor2;
assign pwmRef =
(motor==0)?pwmRef0:
(motor==1)?pwmRef1:
(motor==2)?pwmRef2:
(motor==3)?pwmRef3:
(motor==4)?pwmRef4:
(motor==5)?pwmRef5:
(motor==6)?pwmRef6:
0;
assign ss_n_o[0] = (motor==0?ss_n:1);
assign ss_n_o[1] = (motor==1?ss_n:1);
assign ss_n_o[2] = (motor==2?ss_n:1);
assign ss_n_o[3] = (motor==3?ss_n:1);
assign ss_n_o[4] = (motor==4?ss_n:1);
assign ss_n_o[5] = (motor==5?ss_n:1);
assign ss_n_o[6] = (motor==6?ss_n:1);
SpiControl spi_control(
.clock(clock),
.reset(reset_myo_control),
.di_req(di_req),
.write_ack(wr_ack),
.data_read_valid(do_valid),
.data_read(data_out[15:0]),
.start(spi_activated && update_controller),
.Word(Word[0:15]),
.wren(wren),
.spi_done(spi_done),
.pwmRef(pwmRef),
.position(position),
.velocity(velocity),
.current(current),
.displacement(displacement),
.sensor1(sensor1),
.sensor2(sensor2),
.ss_n(ss_n)
);
spi_master #(16, 1'b0, 1'b1, 2, 5) spi(
.sclk_i(clock),
.pclk_i(clock),
.rst_i(reset_myo_control),
.spi_miso_i(miso),
.di_i(Word[0:15]),
.wren_i(wren),
.spi_ssel_o(ss_n),
.spi_sck_o(sck),
.spi_mosi_o(mosi),
.di_req_o(di_req),
.wr_ack_o(wr_ack),
.do_valid_o(do_valid),
.do_o(data_out[15:0])
);
PIDController pid_controller0(
.clock(clock),
.reset(reset_myo_control||reset_controller0),
.Kp(Kp0),
.Kd(Kd0),
.Ki(Ki0),
.sp(sp0),
.forwardGain(forwardGain0),
.outputPosMax(outputPosMax0),
.outputNegMax(outputNegMax0),
.IntegralNegMax(IntegralNegMax0),
.IntegralPosMax(IntegralPosMax0),
.deadBand(deadBand0),
.controller(controller0),
.position(position0),
.velocity(velocity0),
.displacement(displacement0),
.update_controller(pid_update==0 && update_controller),
.pwmRef(pwmRef0)
);
PIDController pid_controller1(
.clock(clock),
.reset(reset_myo_control||reset_controller1),
.Kp(Kp1),
.Kd(Kd1),
.Ki(Ki1),
.sp(sp1),
.forwardGain(forwardGain1),
.outputPosMax(outputPosMax1),
.outputNegMax(outputNegMax1),
.IntegralNegMax(IntegralNegMax1),
.IntegralPosMax(IntegralPosMax1),
.deadBand(deadBand1),
.controller(controller1),
.position(position1),
.velocity(velocity1),
.displacement(displacement1),
.update_controller(pid_update==1 && update_controller),
.pwmRef(pwmRef1)
);
PIDController pid_controller2(
.clock(clock),
.reset(reset_myo_control||reset_controller2),
.Kp(Kp2),
.Kd(Kd2),
.Ki(Ki2),
.sp(sp2),
.forwardGain(forwardGain2),
.outputPosMax(outputPosMax2),
.outputNegMax(outputNegMax2),
.IntegralNegMax(IntegralNegMax2),
.IntegralPosMax(IntegralPosMax2),
.deadBand(deadBand2),
.controller(controller2),
.position(position2),
.velocity(velocity2),
.displacement(displacement2),
.update_controller(pid_update==2 && update_controller),
.pwmRef(pwmRef2)
);
PIDController pid_controller3(
.clock(clock),
.reset(reset_myo_control||reset_controller3),
.Kp(Kp3),
.Kd(Kd3),
.Ki(Ki3),
.sp(sp3),
.forwardGain(forwardGain3),
.outputPosMax(outputPosMax3),
.outputNegMax(outputNegMax3),
.IntegralNegMax(IntegralNegMax3),
.IntegralPosMax(IntegralPosMax3),
.deadBand(deadBand3),
.controller(controller3),
.position(position3),
.velocity(velocity3),
.displacement(displacement3),
.update_controller(pid_update==3 && update_controller),
.pwmRef(pwmRef3)
);
PIDController pid_controller4(
.clock(clock),
.reset(reset_myo_control||reset_controller4),
.Kp(Kp4),
.Kd(Kd4),
.Ki(Ki4),
.sp(sp4),
.forwardGain(forwardGain4),
.outputPosMax(outputPosMax4),
.outputNegMax(outputNegMax4),
.IntegralNegMax(IntegralNegMax4),
.IntegralPosMax(IntegralPosMax4),
.deadBand(deadBand4),
.controller(controller4),
.position(position4),
.velocity(velocity4),
.displacement(displacement4),
.update_controller(pid_update==4 && update_controller),
.pwmRef(pwmRef4)
);
PIDController pid_controller5(
.clock(clock),
.reset(reset_myo_control||reset_controller5),
.Kp(Kp5),
.Kd(Kd5),
.Ki(Ki5),
.sp(sp5),
.forwardGain(forwardGain5),
.outputPosMax(outputPosMax5),
.outputNegMax(outputNegMax5),
.IntegralNegMax(IntegralNegMax5),
.IntegralPosMax(IntegralPosMax5),
.deadBand(deadBand5),
.controller(controller5),
.position(position5),
.velocity(velocity5),
.displacement(displacement5),
.update_controller(pid_update==5 && update_controller),
.pwmRef(pwmRef5)
);
PIDController pid_controller6(
.clock(clock),
.reset(reset_myo_control||reset_controller6),
.Kp(Kp6),
.Kd(Kd6),
.Ki(Ki6),
.sp(sp6),
.forwardGain(forwardGain6),
.outputPosMax(outputPosMax6),
.outputNegMax(outputNegMax6),
.IntegralNegMax(IntegralNegMax6),
.IntegralPosMax(IntegralPosMax6),
.deadBand(deadBand6),
.controller(controller6),
.position(position6),
.velocity(velocity6),
.displacement(displacement6),
.update_controller(pid_update==6 && update_controller),
.pwmRef(pwmRef6)
);
endmodule | 1 |
141,917 | data/full_repos/permissive/96222896/rtl/SpiControl.v | 96,222,896 | SpiControl.v | v | 118 | 124 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:9: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] data_read,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:11: Little bit endian vector: MSB < LSB of bit range: 0:15\n input signed [0:15] pwmRef,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:13: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg [0:15] Word,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:16: Little bit endian vector: MSB < LSB of bit range: 0:31\n output reg signed[0:31] position,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:17: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg signed[0:15] velocity,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:18: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg signed[0:15] current,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:19: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg signed[0:15] displacement,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:20: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg signed[0:15] sensor1,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/96222896/rtl/SpiControl.v:21: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg signed[0:15] sensor2\n ^\n%Error: Exiting due to 9 warning(s)\n' | 312,769 | module | module SpiControl (
input clock,
input reset,
input di_req,
input write_ack,
input data_read_valid,
input [0:15] data_read,
input start,
input signed [0:15] pwmRef,
input ss_n,
output reg [0:15] Word,
output reg wren,
output reg spi_done,
output reg signed[0:31] position,
output reg signed[0:15] velocity,
output reg signed[0:15] current,
output reg signed[0:15] displacement,
output reg signed[0:15] sensor1,
output reg signed[0:15] sensor2
);
reg [7:0] numberOfWordsTransmitted;
reg [7:0] numberOfWordsReceived;
reg write_ack_prev;
reg next_value;
reg start_frame;
reg data_read_valid_prev;
reg [5:0] delay_counter;
`define ENABLE_DELAY
always @(posedge clock, posedge reset) begin: SPICONTROL_SPILOGIC
if (reset == 1) begin
numberOfWordsTransmitted <= 12;
wren <= 0;
write_ack_prev <= 0;
start_frame <= 0;
spi_done <= 0;
end else begin
write_ack_prev <= write_ack;
if( write_ack_prev==0 && write_ack == 1) begin
wren <= 0;
numberOfWordsTransmitted <= numberOfWordsTransmitted + 1;
next_value <= 1;
end
if( (di_req || start_frame) && numberOfWordsTransmitted<12 && next_value==1) begin
case(numberOfWordsTransmitted)
0: Word <= 16'h8000;
1: Word <= pwmRef & 16'h7fff;
2: Word <= 0;
3: Word <= 0;
4: Word <= 0;
default: Word <= 0;
endcase
next_value <= 0;
`ifdef ENABLE_DELAY
delay_counter <= 1;
`else
wren <= 1;
`endif
if(start_frame)
start_frame <= 0;
end
`ifdef ENABLE_DELAY
if(wren==0 && next_value==0) begin
if(delay_counter==0)
wren <= 1;
else if (delay_counter>0)
delay_counter <= delay_counter + 1;
end
`endif
data_read_valid_prev <= data_read_valid;
if( data_read_valid_prev==1 && data_read_valid==0 ) begin
case(numberOfWordsReceived)
5: position[0:15] <= data_read;
6: position[16:31] <= data_read;
7: velocity <= data_read;
8: current <= data_read;
9: displacement <= data_read;
10: sensor1 <= data_read;
11: sensor2 <= data_read;
endcase
numberOfWordsReceived <= numberOfWordsReceived + 1;
end
if ( numberOfWordsTransmitted>=12 && ss_n==1 ) begin
spi_done <= 1;
if ( start ) begin
numberOfWordsTransmitted<= 0;
numberOfWordsReceived <= 0;
start_frame <= 1;
next_value <= 1;
spi_done <= 0;
end
end
end
end
endmodule | module SpiControl (
input clock,
input reset,
input di_req,
input write_ack,
input data_read_valid,
input [0:15] data_read,
input start,
input signed [0:15] pwmRef,
input ss_n,
output reg [0:15] Word,
output reg wren,
output reg spi_done,
output reg signed[0:31] position,
output reg signed[0:15] velocity,
output reg signed[0:15] current,
output reg signed[0:15] displacement,
output reg signed[0:15] sensor1,
output reg signed[0:15] sensor2
); |
reg [7:0] numberOfWordsTransmitted;
reg [7:0] numberOfWordsReceived;
reg write_ack_prev;
reg next_value;
reg start_frame;
reg data_read_valid_prev;
reg [5:0] delay_counter;
`define ENABLE_DELAY
always @(posedge clock, posedge reset) begin: SPICONTROL_SPILOGIC
if (reset == 1) begin
numberOfWordsTransmitted <= 12;
wren <= 0;
write_ack_prev <= 0;
start_frame <= 0;
spi_done <= 0;
end else begin
write_ack_prev <= write_ack;
if( write_ack_prev==0 && write_ack == 1) begin
wren <= 0;
numberOfWordsTransmitted <= numberOfWordsTransmitted + 1;
next_value <= 1;
end
if( (di_req || start_frame) && numberOfWordsTransmitted<12 && next_value==1) begin
case(numberOfWordsTransmitted)
0: Word <= 16'h8000;
1: Word <= pwmRef & 16'h7fff;
2: Word <= 0;
3: Word <= 0;
4: Word <= 0;
default: Word <= 0;
endcase
next_value <= 0;
`ifdef ENABLE_DELAY
delay_counter <= 1;
`else
wren <= 1;
`endif
if(start_frame)
start_frame <= 0;
end
`ifdef ENABLE_DELAY
if(wren==0 && next_value==0) begin
if(delay_counter==0)
wren <= 1;
else if (delay_counter>0)
delay_counter <= delay_counter + 1;
end
`endif
data_read_valid_prev <= data_read_valid;
if( data_read_valid_prev==1 && data_read_valid==0 ) begin
case(numberOfWordsReceived)
5: position[0:15] <= data_read;
6: position[16:31] <= data_read;
7: velocity <= data_read;
8: current <= data_read;
9: displacement <= data_read;
10: sensor1 <= data_read;
11: sensor2 <= data_read;
endcase
numberOfWordsReceived <= numberOfWordsReceived + 1;
end
if ( numberOfWordsTransmitted>=12 && ss_n==1 ) begin
spi_done <= 1;
if ( start ) begin
numberOfWordsTransmitted<= 0;
numberOfWordsReceived <= 0;
start_frame <= 1;
next_value <= 1;
spi_done <= 0;
end
end
end
end
endmodule | 1 |
Subsets and Splits