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141,649 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v | 95,918,395 | t_regfile.v | v | 92 | 83 | [] | [] | [] | [(23, 91)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10 wd3 = 32\'h00000001; a3 = 5\'b00001; we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:70: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:71: Unsupported: Ignoring delay on this delayed statement.\n #40 a1 = 5\'b00001; a2 = 5\'b00001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:73: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 1; a3 = 5\'b00010; wd3 = 32\'h00000002;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:74: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:75: Unsupported: Ignoring delay on this delayed statement.\n #40 a1 = 5\'b00001; a2 = 5\'b00010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:77: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 1; a3 = 5\'b00011; wd3 = 32\'h00000003;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:78: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:79: Unsupported: Ignoring delay on this delayed statement.\n #40 a1 = 5\'b00010; a2 = 5\'b00011;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:82: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 1; a3 = 5\'b00000; wd3 = 32\'h00000004;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:83: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:84: Unsupported: Ignoring delay on this delayed statement.\n #40 a1 = 5\'b00000; a2 = 5\'b00011;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:86: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 1; a3 = 5\'b00100; wd3 = 32\'h00000004;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:87: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:88: Unsupported: Ignoring delay on this delayed statement.\n #40 a1 = 5\'b00100; a2 = 5\'b00011;\n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_regfile.v:37: Cannot find file containing module: \'regfile\'\n regfile uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/regfile\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/regfile.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/regfile.sv\n regfile\n regfile.v\n regfile.sv\n obj_dir/regfile\n obj_dir/regfile.v\n obj_dir/regfile.sv\n%Error: Exiting due to 1 error(s), 18 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,266 | module | module t_regfile;
reg clk, we;
reg [4:0] a1;
reg [4:0] a2;
reg [4:0] a3;
reg [31:0] wd3;
wire [31:0] rd1;
wire [31:0] rd2;
regfile uut (
.clk( clk ),
.WE3( we ),
.A1( a1 ),
.A2( a2 ),
.A3( a3 ),
.WD3( wd3 ),
.RD1( rd1 ),
.RD2( rd2 )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
we = 0;
a1 = 0;
a2 = 0;
a3 = 0;
wd3 = 0;
#100;
#10 wd3 = 32'h00000001; a3 = 5'b00001; we = 1;
#20 we = 0;
#40 a1 = 5'b00001; a2 = 5'b00001;
#40 we = 1; a3 = 5'b00010; wd3 = 32'h00000002;
#20 we = 0;
#40 a1 = 5'b00001; a2 = 5'b00010;
#40 we = 1; a3 = 5'b00011; wd3 = 32'h00000003;
#20 we = 0;
#40 a1 = 5'b00010; a2 = 5'b00011;
#40 we = 1; a3 = 5'b00000; wd3 = 32'h00000004;
#20 we = 0;
#40 a1 = 5'b00000; a2 = 5'b00011;
#40 we = 1; a3 = 5'b00100; wd3 = 32'h00000004;
#20 we = 0;
#40 a1 = 5'b00100; a2 = 5'b00011;
end
endmodule | module t_regfile; |
reg clk, we;
reg [4:0] a1;
reg [4:0] a2;
reg [4:0] a3;
reg [31:0] wd3;
wire [31:0] rd1;
wire [31:0] rd2;
regfile uut (
.clk( clk ),
.WE3( we ),
.A1( a1 ),
.A2( a2 ),
.A3( a3 ),
.WD3( wd3 ),
.RD1( rd1 ),
.RD2( rd2 )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
we = 0;
a1 = 0;
a2 = 0;
a3 = 0;
wd3 = 0;
#100;
#10 wd3 = 32'h00000001; a3 = 5'b00001; we = 1;
#20 we = 0;
#40 a1 = 5'b00001; a2 = 5'b00001;
#40 we = 1; a3 = 5'b00010; wd3 = 32'h00000002;
#20 we = 0;
#40 a1 = 5'b00001; a2 = 5'b00010;
#40 we = 1; a3 = 5'b00011; wd3 = 32'h00000003;
#20 we = 0;
#40 a1 = 5'b00010; a2 = 5'b00011;
#40 we = 1; a3 = 5'b00000; wd3 = 32'h00000004;
#20 we = 0;
#40 a1 = 5'b00000; a2 = 5'b00011;
#40 we = 1; a3 = 5'b00100; wd3 = 32'h00000004;
#20 we = 0;
#40 a1 = 5'b00100; a2 = 5'b00011;
end
endmodule | 0 |
141,650 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v | 95,918,395 | t_scp.v | v | 60 | 83 | [] | [] | [] | [(23, 59)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:46: Can\'t find definition of \'ID\' in dotted scope/variable: \'t_scp.uut.ID\'\n $display(t_scp.uut.ID.jumpaddr);\n ^~\n ... Known scopes under \'t_scp.uut\': <no cells found>\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:47: Can\'t find definition of \'ID\' in dotted scope/variable: \'t_scp.uut.ID\'\n $display(t_scp.uut.ID.WAinstrD);\n ^~\n ... Known scopes under \'t_scp.uut\': <no cells found>\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:48: Can\'t find definition of \'IF\' in dotted scope/variable: \'t_scp.uut.IF\'\n $display(t_scp.uut.IF.WAinstrF);\n ^~\n ... Known scopes under \'t_scp.uut\': <no cells found>\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:49: Can\'t find definition of \'IF\' in dotted scope/variable: \'t_scp.uut.IF\'\n $display(t_scp.uut.IF.PCPrime);\n ^~\n ... Known scopes under \'t_scp.uut\': <no cells found>\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:50: Can\'t find definition of \'IF\' in dotted scope/variable: \'t_scp.uut.IF\'\n $display(t_scp.uut.IF.PC);\n ^~\n ... Known scopes under \'t_scp.uut\': <no cells found>\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_scp.v:51: Can\'t find definition of \'IF\' in dotted scope/variable: \'t_scp.uut.IF\'\n $display(t_scp.uut.IF.PCJump);\n ^~\n ... Known scopes under \'t_scp.uut\': <no cells found>\n%Error: Exiting due to 6 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,267 | module | module t_scp;
reg clk, reset;
singlecycleprocessor uut (
.clk( clk ),
.reset( reset)
);
initial begin
clk = 0;
#20;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
$display(t_scp.uut.ID.jumpaddr);
$display(t_scp.uut.ID.WAinstrD);
$display(t_scp.uut.IF.WAinstrF);
$display(t_scp.uut.IF.PCPrime);
$display(t_scp.uut.IF.PC);
$display(t_scp.uut.IF.PCJump);
reset = 0;
end
endmodule | module t_scp; |
reg clk, reset;
singlecycleprocessor uut (
.clk( clk ),
.reset( reset)
);
initial begin
clk = 0;
#20;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
$display(t_scp.uut.ID.jumpaddr);
$display(t_scp.uut.ID.WAinstrD);
$display(t_scp.uut.IF.WAinstrF);
$display(t_scp.uut.IF.PCPrime);
$display(t_scp.uut.IF.PC);
$display(t_scp.uut.IF.PCJump);
reset = 0;
end
endmodule | 0 |
141,651 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_WB.v | 95,918,395 | t_WB.v | v | 65 | 138 | [] | [] | [] | [(23, 64)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_WB.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_WB.v:56: Unsupported: Ignoring delay on this delayed statement.\n #20 writereg1 = 5\'b01001; memtoreg = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_WB.v:57: Unsupported: Ignoring delay on this delayed statement.\n #20 aluresult = 32\'h00000000; readdata = 32\'h00000000; writereg1 = 5\'b00000; memtoreg = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_WB.v:60: Unsupported: Ignoring delay on this delayed statement.\n #20 regwrite1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_WB.v:61: Unsupported: Ignoring delay on this delayed statement.\n #20 regwrite1 = 0; \n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_WB.v:36: Cannot find file containing module: \'writeback\'\n writeback uut(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/writeback\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/writeback.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/writeback.sv\n writeback\n writeback.v\n writeback.sv\n obj_dir/writeback\n obj_dir/writeback.v\n obj_dir/writeback.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,268 | module | module t_WB;
reg [31:0] readdata, aluresult;
reg [4:0] writereg1;
reg memtoreg, regwrite1;
wire [31:0] result;
wire [4:0] writereg2;
wire regwrite2;
writeback uut(
.ResultW( result ),
.WriteRegW2( writereg2 ),
.RegWriteW2( regwrite2 ),
.ReadDataW( readdata ),
.ALUResultW( aluresult ),
.WriteRegW1( writereg1 ),
.MemToRegW( memtoreg ),
.RegWriteW1( regwrite1 )
);
initial begin
readdata = 0; aluresult = 0; writereg1 = 0; memtoreg = 0; regwrite1 = 0;
#100;
aluresult = 32'hAAAAAAAA; readdata = 32'hFFFFFFFF; writereg1 = 5'b01000; memtoreg = 0;
#20 writereg1 = 5'b01001; memtoreg = 1;
#20 aluresult = 32'h00000000; readdata = 32'h00000000; writereg1 = 5'b00000; memtoreg = 0;
#20 regwrite1 = 1;
#20 regwrite1 = 0;
end
endmodule | module t_WB; |
reg [31:0] readdata, aluresult;
reg [4:0] writereg1;
reg memtoreg, regwrite1;
wire [31:0] result;
wire [4:0] writereg2;
wire regwrite2;
writeback uut(
.ResultW( result ),
.WriteRegW2( writereg2 ),
.RegWriteW2( regwrite2 ),
.ReadDataW( readdata ),
.ALUResultW( aluresult ),
.WriteRegW1( writereg1 ),
.MemToRegW( memtoreg ),
.RegWriteW1( regwrite1 )
);
initial begin
readdata = 0; aluresult = 0; writereg1 = 0; memtoreg = 0; regwrite1 = 0;
#100;
aluresult = 32'hAAAAAAAA; readdata = 32'hFFFFFFFF; writereg1 = 5'b01000; memtoreg = 0;
#20 writereg1 = 5'b01001; memtoreg = 1;
#20 aluresult = 32'h00000000; readdata = 32'h00000000; writereg1 = 5'b00000; memtoreg = 0;
#20 regwrite1 = 1;
#20 regwrite1 = 0;
end
endmodule | 0 |
141,652 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/alu.v | 95,918,395 | alu.v | v | 63 | 163 | [] | [] | [] | [(23, 62)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/alu.v:41: Operator ADD expects 33 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance alu\n assign {Cout, S} = muxBout + A + control[2]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,269 | module | module alu(
output reg [31:0] ALUResult,
output reg Zero,
input [31:0] A,
input [31:0] B,
input [2:0] control
);
wire [31:0] notB, muxBout, S, andResult, orResult, SLT;
wire Cout;
assign notB = ~B;
assign muxBout = (control[2]) ? notB : B;
assign {Cout, S} = muxBout + A + control[2];
assign andResult = A & muxBout;
assign orResult = A | muxBout;
assign SLT = {{31{1'b0}}, {S[31]}};
always @ (control[1:0] or andResult or orResult or S or SLT or ALUResult) begin
case(control[1:0])
2'b00: ALUResult = andResult;
2'b01: ALUResult = orResult;
2'b10: ALUResult = S;
2'b11: ALUResult = SLT;
endcase
if (ALUResult == 32'h00000000) begin
Zero <= 1;
end else begin
Zero <= 0;
end
end
endmodule | module alu(
output reg [31:0] ALUResult,
output reg Zero,
input [31:0] A,
input [31:0] B,
input [2:0] control
); |
wire [31:0] notB, muxBout, S, andResult, orResult, SLT;
wire Cout;
assign notB = ~B;
assign muxBout = (control[2]) ? notB : B;
assign {Cout, S} = muxBout + A + control[2];
assign andResult = A & muxBout;
assign orResult = A | muxBout;
assign SLT = {{31{1'b0}}, {S[31]}};
always @ (control[1:0] or andResult or orResult or S or SLT or ALUResult) begin
case(control[1:0])
2'b00: ALUResult = andResult;
2'b01: ALUResult = orResult;
2'b10: ALUResult = S;
2'b11: ALUResult = SLT;
endcase
if (ALUResult == 32'h00000000) begin
Zero <= 1;
end else begin
Zero <= 0;
end
end
endmodule | 0 |
141,653 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/ctrlunit.v | 95,918,395 | ctrlunit.v | v | 102 | 91 | [] | [] | [] | [(23, 53), (55, 78), (80, 101)] | null | data/verilator_xmls/f6513ac6-2453-4031-8777-18c301e5735b.xml | null | 312,270 | module | module ctrlunit(
input [5:0] OPCode, Funct,
output MemToReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite, Jump,
output [2:0] ALUControl
);
wire [1:0] ALUOp;
maindecoder md_inst(
.op( OPCode ),
.memtoreg( MemToReg ),
.memwrite( MemWrite ),
.branch( Branch ),
.alusrc( ALUSrc ),
.regdst( RegDst ),
.regwrite( RegWrite ),
.jump( Jump ),
.aluop( ALUOp )
);
aludecoder ad_inst(
.funct( Funct ),
.aluop( ALUOp ),
.alucontrol( ALUControl )
);
endmodule | module ctrlunit(
input [5:0] OPCode, Funct,
output MemToReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite, Jump,
output [2:0] ALUControl
); |
wire [1:0] ALUOp;
maindecoder md_inst(
.op( OPCode ),
.memtoreg( MemToReg ),
.memwrite( MemWrite ),
.branch( Branch ),
.alusrc( ALUSrc ),
.regdst( RegDst ),
.regwrite( RegWrite ),
.jump( Jump ),
.aluop( ALUOp )
);
aludecoder ad_inst(
.funct( Funct ),
.aluop( ALUOp ),
.alucontrol( ALUControl )
);
endmodule | 0 |
141,654 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/ctrlunit.v | 95,918,395 | ctrlunit.v | v | 102 | 91 | [] | [] | [] | [(23, 53), (55, 78), (80, 101)] | null | data/verilator_xmls/f6513ac6-2453-4031-8777-18c301e5735b.xml | null | 312,270 | module | module maindecoder(
input [5:0] op,
output memtoreg, memwrite,
output branch, alusrc,
output regdst, regwrite,
output jump,
output [1:0] aluop);
reg [8:0] controls;
assign {memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop} = controls;
always @ (op) begin
case(op)
6'b000000: controls <= 9'b000011011;
6'b100011: controls <= 9'b100101000;
6'b101011: controls <= 9'b010100000;
6'b000100: controls <= 9'b001000001;
6'b001000: controls <= 9'b000101000;
6'b000010: controls <= 9'b000000100;
default: controls <= 9'bxxxxxxxxx;
endcase
end
endmodule | module maindecoder(
input [5:0] op,
output memtoreg, memwrite,
output branch, alusrc,
output regdst, regwrite,
output jump,
output [1:0] aluop); |
reg [8:0] controls;
assign {memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop} = controls;
always @ (op) begin
case(op)
6'b000000: controls <= 9'b000011011;
6'b100011: controls <= 9'b100101000;
6'b101011: controls <= 9'b010100000;
6'b000100: controls <= 9'b001000001;
6'b001000: controls <= 9'b000101000;
6'b000010: controls <= 9'b000000100;
default: controls <= 9'bxxxxxxxxx;
endcase
end
endmodule | 0 |
141,655 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/ctrlunit.v | 95,918,395 | ctrlunit.v | v | 102 | 91 | [] | [] | [] | [(23, 53), (55, 78), (80, 101)] | null | data/verilator_xmls/f6513ac6-2453-4031-8777-18c301e5735b.xml | null | 312,270 | module | module aludecoder(
output reg [2:0] alucontrol,
input [5:0] funct,
input [1:0] aluop
);
always @ (aluop or funct) begin
case(aluop)
2'b00: alucontrol <= 3'b010;
2'b01: alucontrol <= 3'b110;
default: case(funct)
6'b100000: alucontrol <= 3'b010;
6'b100010: alucontrol <= 3'b110;
6'b100100: alucontrol <= 3'b000;
6'b100101: alucontrol <= 3'b001;
6'b101010: alucontrol <= 3'b111;
default: alucontrol <= 3'bxxx;
endcase
endcase
end
endmodule | module aludecoder(
output reg [2:0] alucontrol,
input [5:0] funct,
input [1:0] aluop
); |
always @ (aluop or funct) begin
case(aluop)
2'b00: alucontrol <= 3'b010;
2'b01: alucontrol <= 3'b110;
default: case(funct)
6'b100000: alucontrol <= 3'b010;
6'b100010: alucontrol <= 3'b110;
6'b100100: alucontrol <= 3'b000;
6'b100101: alucontrol <= 3'b001;
6'b101010: alucontrol <= 3'b111;
default: alucontrol <= 3'bxxx;
endcase
endcase
end
endmodule | 0 |
141,656 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/dmem.v | 95,918,395 | dmem.v | v | 43 | 89 | [] | [] | [] | [(23, 42)] | null | data/verilator_xmls/22610034-68e6-4f34-ac39-78d98e6e8d85.xml | null | 312,271 | module | module dmem(
output [31:0] RD,
input [31:0] A, WD,
input WE, clk
);
reg [31:0] RAM [0:255];
assign RD = (A != 0) ? RAM[A[7:0]] : 0;
always @ (posedge clk)
if (WE)
RAM[A[7:0]] <= WD;
endmodule | module dmem(
output [31:0] RD,
input [31:0] A, WD,
input WE, clk
); |
reg [31:0] RAM [0:255];
assign RD = (A != 0) ? RAM[A[7:0]] : 0;
always @ (posedge clk)
if (WE)
RAM[A[7:0]] <= WD;
endmodule | 0 |
141,657 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/execute.v | 95,918,395 | execute.v | v | 63 | 83 | [] | [] | [] | [(26, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/execute.v:38: Cannot find file containing module: 'alu'\n alu alu_ex(\n ^~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/alu\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/alu.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: Exiting due to 1 error(s)\n" | 312,272 | module | module execute(
output [31:0] ALUResult, PCBranchE, WriteDataE,
output [4:0] WriteRegE,
output RegWriteE2, MemToRegE2, MemWriteE2, BranchE2, ZerowireE,
input [31:0] PCPlus4E, srcA, RegRead2, SignImmE,
input [4:0] rt, rd,
input [2:0] ALUControlE,
input ALUSrcE, RegDstE, RegWriteE1, MemToRegE1, MemWriteE1, BranchE1
);
wire [31:0] srcB, WASignImmE;
alu alu_ex(
.ALUResult( ALUResult ),
.Zero( ZerowireE ),
.A( srcA ),
.B( srcB ),
.control( ALUControlE )
);
assign WriteRegE = RegDstE ? rd: rt;
assign srcB = ALUSrcE ? SignImmE : RegRead2;
assign WASignImmE = SignImmE << 2;
assign PCBranchE = PCPlus4E + WASignImmE;
assign WriteDataE = RegRead2;
assign RegWriteE2 = RegWriteE1;
assign MemToRegE2 = MemToRegE1;
assign MemWriteE2 = MemWriteE1;
assign BranchE2 = BranchE1;
endmodule | module execute(
output [31:0] ALUResult, PCBranchE, WriteDataE,
output [4:0] WriteRegE,
output RegWriteE2, MemToRegE2, MemWriteE2, BranchE2, ZerowireE,
input [31:0] PCPlus4E, srcA, RegRead2, SignImmE,
input [4:0] rt, rd,
input [2:0] ALUControlE,
input ALUSrcE, RegDstE, RegWriteE1, MemToRegE1, MemWriteE1, BranchE1
); |
wire [31:0] srcB, WASignImmE;
alu alu_ex(
.ALUResult( ALUResult ),
.Zero( ZerowireE ),
.A( srcA ),
.B( srcB ),
.control( ALUControlE )
);
assign WriteRegE = RegDstE ? rd: rt;
assign srcB = ALUSrcE ? SignImmE : RegRead2;
assign WASignImmE = SignImmE << 2;
assign PCBranchE = PCPlus4E + WASignImmE;
assign WriteDataE = RegRead2;
assign RegWriteE2 = RegWriteE1;
assign MemToRegE2 = MemToRegE1;
assign MemWriteE2 = MemWriteE1;
assign BranchE2 = BranchE1;
endmodule | 0 |
141,658 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/instrmem.v | 95,918,395 | instrmem.v | v | 36 | 83 | [] | [] | [] | [(21, 35)] | null | data/verilator_xmls/ce74eaf9-d99c-400d-8083-742faa35bf2b.xml | null | 312,273 | module | module instrmem(
output [31:0] RD,
input [31:0] A
);
reg [7:0] mem [0:127];
initial begin
$readmemh("testinstructions.dat", mem);
end
assign RD = {mem[A], mem[A+1], mem[A+2], mem[A+3]};
endmodule | module instrmem(
output [31:0] RD,
input [31:0] A
); |
reg [7:0] mem [0:127];
initial begin
$readmemh("testinstructions.dat", mem);
end
assign RD = {mem[A], mem[A+1], mem[A+2], mem[A+3]};
endmodule | 0 |
141,659 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/instructiondecode.v | 95,918,395 | instructiondecode.v | v | 85 | 121 | [] | [] | [] | [(26, 84)] | null | null | 1: b"%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/instructiondecode.v:51: Cannot find file containing module: 'ctrlunit'\n ctrlunit ctrlunit_id(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/ctrlunit\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/ctrlunit.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/ctrlunit.sv\n ctrlunit\n ctrlunit.v\n ctrlunit.sv\n obj_dir/ctrlunit\n obj_dir/ctrlunit.v\n obj_dir/ctrlunit.sv\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/instructiondecode.v:64: Cannot find file containing module: 'regfile'\n regfile regfile_id(\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,274 | module | module instructiondecode(
output [31:0] read1, read2, immediateSE, PCPlus4D2,
output [27:0] WAinstrD,
output [4:0] rt, rd,
output [2:0] ALUControlD,
output RegWriteD, MemToRegD, MemWriteD, BranchD, ALUSrcD, RegDstD, JumpD,
input [31:0] PCPlus4D1, instruction, ResultW,
input [4:0] WriteRegW,
input RegWriteW, clk
);
wire [25:0] jumpaddr;
wire [15:0] imm;
wire [5:0] opcode, funct;
wire [4:0] rs;
assign opcode = instruction[31:26];
assign rs = instruction[25:21];
assign jumpaddr = instruction[25:0];
assign rt = instruction[20:16];
assign rd = instruction[15:11];
assign imm = instruction[15:0];
assign funct = instruction[5:0];
ctrlunit ctrlunit_id(
.OPCode( opcode ),
.Funct( funct ),
.MemToReg( MemToRegD ),
.MemWrite( MemWriteD ),
.Branch( BranchD ),
.ALUSrc( ALUSrcD ),
.RegDst( RegDstD ),
.RegWrite( RegWriteD ),
.Jump( JumpD ),
.ALUControl( ALUControlD )
);
regfile regfile_id(
.RD1( read1 ),
.RD2( read2 ),
.A1( rd ),
.A2( rt ),
.A3( WriteRegW ),
.WD3( ResultW ),
.WE3( RegWriteW ),
.clk( clk )
);
assign WAinstrD = {jumpaddr, {2'b00}};
assign PCPlus4D2 = PCPlus4D1;
assign immediateSE = {{16{imm[15]}}, {imm[15:0]}};
endmodule | module instructiondecode(
output [31:0] read1, read2, immediateSE, PCPlus4D2,
output [27:0] WAinstrD,
output [4:0] rt, rd,
output [2:0] ALUControlD,
output RegWriteD, MemToRegD, MemWriteD, BranchD, ALUSrcD, RegDstD, JumpD,
input [31:0] PCPlus4D1, instruction, ResultW,
input [4:0] WriteRegW,
input RegWriteW, clk
); |
wire [25:0] jumpaddr;
wire [15:0] imm;
wire [5:0] opcode, funct;
wire [4:0] rs;
assign opcode = instruction[31:26];
assign rs = instruction[25:21];
assign jumpaddr = instruction[25:0];
assign rt = instruction[20:16];
assign rd = instruction[15:11];
assign imm = instruction[15:0];
assign funct = instruction[5:0];
ctrlunit ctrlunit_id(
.OPCode( opcode ),
.Funct( funct ),
.MemToReg( MemToRegD ),
.MemWrite( MemWriteD ),
.Branch( BranchD ),
.ALUSrc( ALUSrcD ),
.RegDst( RegDstD ),
.RegWrite( RegWriteD ),
.Jump( JumpD ),
.ALUControl( ALUControlD )
);
regfile regfile_id(
.RD1( read1 ),
.RD2( read2 ),
.A1( rd ),
.A2( rt ),
.A3( WriteRegW ),
.WD3( ResultW ),
.WE3( RegWriteW ),
.clk( clk )
);
assign WAinstrD = {jumpaddr, {2'b00}};
assign PCPlus4D2 = PCPlus4D1;
assign immediateSE = {{16{imm[15]}}, {imm[15:0]}};
endmodule | 0 |
141,660 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/instructionfetch.v | 95,918,395 | instructionfetch.v | v | 93 | 186 | [] | [] | [] | null | line:59: before: "posedge" | null | 1: b"%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/instructionfetch.v:52: Cannot find file containing module: 'instrmem'\n instrmem instrmem_if(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/instrmem\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/instrmem.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/instrmem.sv\n instrmem\n instrmem.v\n instrmem.sv\n obj_dir/instrmem\n obj_dir/instrmem.v\n obj_dir/instrmem.sv\n%Error: Exiting due to 1 error(s)\n" | 312,275 | module | module instructionfetch(
output [31:0] PCPlus4F,
output [31:0] instruction,
input [31:0] PCBranchF,
input [27:0] WAinstrF,
input clk, reset, JumpF, PCSrcF
);
wire [31:0] PCJump;
wire [1:0] controlSignals;
reg [31:0] PC, PCPrime;
instrmem instrmem_if(
.A( PC ),
.RD( instruction )
);
assign controlSignals = {JumpF, PCSrcF};
always @ (controlSignals or posedge reset or posedge clk) begin
if(reset) begin
PCPrime <= 0;
end else begin
case (controlSignals)
2'b00: PCPrime <= PCPlus4F;
2'b01: PCPrime <= PCBranchF;
2'b10: PCPrime <= PCJump;
default: PCPrime <= 0;
endcase
end
end
always @ (posedge clk or posedge reset) begin
if(reset) begin
PC <= 0;
end else begin
PC <= PCPrime;
end
end
assign PCJump = {PCPlus4F[31:28], WAinstrF};
assign PCPlus4F = PCPrime + 32'h4;
initial begin
PC = 32'h00000000;
PCPrime = 32'h00000000;
$display(PC);
$display(PCPrime);
end
endmodule | module instructionfetch(
output [31:0] PCPlus4F,
output [31:0] instruction,
input [31:0] PCBranchF,
input [27:0] WAinstrF,
input clk, reset, JumpF, PCSrcF
); |
wire [31:0] PCJump;
wire [1:0] controlSignals;
reg [31:0] PC, PCPrime;
instrmem instrmem_if(
.A( PC ),
.RD( instruction )
);
assign controlSignals = {JumpF, PCSrcF};
always @ (controlSignals or posedge reset or posedge clk) begin
if(reset) begin
PCPrime <= 0;
end else begin
case (controlSignals)
2'b00: PCPrime <= PCPlus4F;
2'b01: PCPrime <= PCBranchF;
2'b10: PCPrime <= PCJump;
default: PCPrime <= 0;
endcase
end
end
always @ (posedge clk or posedge reset) begin
if(reset) begin
PC <= 0;
end else begin
PC <= PCPrime;
end
end
assign PCJump = {PCPlus4F[31:28], WAinstrF};
assign PCPlus4F = PCPrime + 32'h4;
initial begin
PC = 32'h00000000;
PCPrime = 32'h00000000;
$display(PC);
$display(PCPrime);
end
endmodule | 0 |
141,661 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/memoryaccess.v | 95,918,395 | memoryaccess.v | v | 57 | 83 | [] | [] | [] | [(30, 56)] | null | null | 1: b"%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/memoryaccess.v:39: Cannot find file containing module: 'dmem'\n dmem dmem_mem(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/dmem\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/dmem.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new,data/full_repos/permissive/95918395/dmem.sv\n dmem\n dmem.v\n dmem.sv\n obj_dir/dmem\n obj_dir/dmem.v\n obj_dir/dmem.sv\n%Error: Exiting due to 1 error(s)\n" | 312,276 | module | module memoryaccess(
output [31:0] ReadDataM, ALUResultOut, PCBranchM2,
output [4:0] WriteRegM2,
output RegWriteM2, MemToRegM2, PCSrcM,
input [31:0] WriteDataM, ALUResultIn, PCBranchM1,
input [4:0] WriteRegM1,
input BranchM, MemWriteM, MemToRegM1, RegWriteM1, ZerowireM, clk
);
dmem dmem_mem(
.RD( ReadDataM ),
.A( ALUResultIn ),
.WD( WriteDataM ),
.WE( MemWriteM ),
.clk( clk )
);
assign PCSrcM = BranchM & ZerowireM;
assign ALUResultOut = ALUResultIn;
assign WriteRegM2 = WriteRegM1;
assign PCBranchM2 = PCBranchM1;
assign MemToRegM2 = MemToRegM1;
assign RegWriteM2 = RegWriteM1;
endmodule | module memoryaccess(
output [31:0] ReadDataM, ALUResultOut, PCBranchM2,
output [4:0] WriteRegM2,
output RegWriteM2, MemToRegM2, PCSrcM,
input [31:0] WriteDataM, ALUResultIn, PCBranchM1,
input [4:0] WriteRegM1,
input BranchM, MemWriteM, MemToRegM1, RegWriteM1, ZerowireM, clk
); |
dmem dmem_mem(
.RD( ReadDataM ),
.A( ALUResultIn ),
.WD( WriteDataM ),
.WE( MemWriteM ),
.clk( clk )
);
assign PCSrcM = BranchM & ZerowireM;
assign ALUResultOut = ALUResultIn;
assign WriteRegM2 = WriteRegM1;
assign PCBranchM2 = PCBranchM1;
assign MemToRegM2 = MemToRegM1;
assign RegWriteM2 = RegWriteM1;
endmodule | 0 |
141,662 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/regfile.v | 95,918,395 | regfile.v | v | 67 | 83 | [] | [] | [] | [(42, 66)] | null | data/verilator_xmls/7d485e1e-fb21-49af-9b9c-5dcbbfd8a079.xml | null | 312,277 | module | module regfile(
output [31:0] RD1, RD2,
input [4:0] A1, A2, A3,
input [31:0] WD3,
input WE3, clk
);
reg [31:0] rf [0:31];
initial rf[0] = 32'h00000000;
always @ *
if (WE3 & (A3 != 5'b00000)) begin
rf[A3] <= WD3;
end
assign RD1 = (A1 != 0) ? rf[A1] : 0;
assign RD2 = (A2 != 0) ? rf[A2] : 0;
endmodule | module regfile(
output [31:0] RD1, RD2,
input [4:0] A1, A2, A3,
input [31:0] WD3,
input WE3, clk
); |
reg [31:0] rf [0:31];
initial rf[0] = 32'h00000000;
always @ *
if (WE3 & (A3 != 5'b00000)) begin
rf[A3] <= WD3;
end
assign RD1 = (A1 != 0) ? rf[A1] : 0;
assign RD2 = (A2 != 0) ? rf[A2] : 0;
endmodule | 0 |
141,663 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/singlecycleprocessor.v | 95,918,395 | singlecycleprocessor.v | v | 137 | 116 | [] | [] | [] | [(23, 136)] | null | null | 1: b"%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/singlecycleprocessor.v:133: Can't find definition of 'PC' in dotted variable: 'singlecycleprocessor.IF.PC'\n $display(singlecycleprocessor.IF.PC);\n ^~\n%Error: Exiting due to 1 error(s)\n" | 312,278 | module | module singlecycleprocessor(
input clk, reset
);
wire [31:0] PCPlus4F2D, PCPlus4D2E;
wire [31:0] PCBranchM2F, PCBranchE2M;
wire [31:0] instruction;
wire [31:0] RFRead1D2E, RFRead2D2E;
wire [31:0] ImmSeD2E;
wire [31:0] ResultW2D;
wire [27:0] WAInstrD2F;
wire [4:0] rtD2E, rdD2E, WriteRegW2D;
wire [2:0] ALUControlD2E;
wire PCSrcM2F, JumpD2F, RegWriteD2E, MemToRegD2E, MemWriteD2E, BranchD2E, ALUSrcD2E, RegDstD2E;
wire RegWriteW2D;
wire [31:0] ReadDataM2W, ALUResultOutM2W;
wire [4:0] WriteRegM2W;
wire RegWriteM2W, MemToRegM2W;
wire [31:0] ALUResultE2M, WriteDataE2M;
wire [4:0] WriteRegE2M;
wire RegWriteE2M, MemToRegE2M, BranchE2M, ZerowireE2M, MemWriteE2M;
instructionfetch IF(
.PCPlus4F( PCPlus4F2D ),
.instruction( instruction ),
.PCBranchF( PCBranchM2F ),
.WAinstrF( WAInstrD2F ),
.clk( clk ),
.reset( reset ),
.JumpF( JumpD2F ),
.PCSrcF( PCSrcM2F )
);
instructiondecode ID(
.read1( RFRead1D2E ),
.read2( RFRead2D2E ),
.immediateSE( ImmSeD2E ),
.PCPlus4D2( PCPlus4D2E ),
.WAinstrD( WAInstrD2F ),
.rt( rtD2E ),
.rd( rdD2E ),
.ALUControlD( ALUControlD2E ),
.RegWriteD( RegWriteD2E ),
.MemToRegD( MemToRegD2E ),
.MemWriteD( MemWriteD2E ),
.BranchD( BranchD2E ),
.ALUSrcD( ALUSrcD2E ),
.RegDstD( RegDstD2E ),
.JumpD( JumpD2F ),
.PCPlus4D1( PCPlus4F2D ),
.instruction( instruction ),
.ResultW( ResultW2D ),
.WriteRegW( WriteRegW2D ),
.RegWriteW( RegWriteW2D ),
.clk( clk )
);
execute EX(
.ALUResult( ALUResultE2M ),
.PCBranchE( PCBranchE2M ),
.WriteDataE( WriteDataE2M ),
.WriteRegE( WriteRegE2M ),
.RegWriteE2( RegWriteE2M ), .MemToRegE2( MemToRegE2M ), .MemWriteE2( MemWriteE2M ), .BranchE2( BranchE2M ),
.ZerowireE( ZerowireE2M ),
.PCPlus4E( PCPlus4D2E ),
.srcA( RFRead1D2E ), .RegRead2( RFRead2D2E ), .SignImmE( ImmSeD2E ),
.rt( rtD2E ), .rd( rdD2E ),
.ALUControlE( ALUControlD2E ),
.ALUSrcE( ALUSrcD2E ), .RegDstE( RegDstD2E ),
.RegWriteE1( RegWriteD2E ), .MemToRegE1( MemToRegD2E ), .MemWriteE1( MemWriteD2E ), .BranchE1( BranchD2E )
);
memoryaccess MEM(
.ReadDataM( ReadDataM2W ),
.ALUResultOut( ALUResultOutM2W ),
.PCBranchM2( PCBranchM2F ),
.WriteRegM2( WriteRegM2W ),
.RegWriteM2( RegWriteM2W ),
.MemToRegM2( MemToRegM2W ),
.PCSrcM( PCSrcM2F ),
.WriteDataM( WriteDataE2M ),
.ALUResultIn( ALUResultE2M ),
.PCBranchM1( PCBranchE2M ),
.WriteRegM1( WriteRegE2M ),
.BranchM( BranchE2M ),
.MemWriteM( MemWriteE2M ),
.MemToRegM1( MemToRegE2M ),
.RegWriteM1( RegWriteE2M ),
.ZerowireM( ZerowireE2M ),
.clk( clk )
);
writeback WB(
.ResultW( ResultW2D ),
.WriteRegW2( WriteRegW2D ),
.RegWriteW2( RegWriteW2D ),
.ReadDataW( ReadDataM2W ),
.ALUResultW( ALUResultOutM2W ),
.WriteRegW1( WriteRegM2W ),
.MemToRegW( MemToRegM2W ),
.RegWriteW1( RegWriteM2W )
);
assign PCSrcM2F = BranchE2M & ZerowireE2M;
initial begin
$display(singlecycleprocessor.IF.PC);
end
endmodule | module singlecycleprocessor(
input clk, reset
); |
wire [31:0] PCPlus4F2D, PCPlus4D2E;
wire [31:0] PCBranchM2F, PCBranchE2M;
wire [31:0] instruction;
wire [31:0] RFRead1D2E, RFRead2D2E;
wire [31:0] ImmSeD2E;
wire [31:0] ResultW2D;
wire [27:0] WAInstrD2F;
wire [4:0] rtD2E, rdD2E, WriteRegW2D;
wire [2:0] ALUControlD2E;
wire PCSrcM2F, JumpD2F, RegWriteD2E, MemToRegD2E, MemWriteD2E, BranchD2E, ALUSrcD2E, RegDstD2E;
wire RegWriteW2D;
wire [31:0] ReadDataM2W, ALUResultOutM2W;
wire [4:0] WriteRegM2W;
wire RegWriteM2W, MemToRegM2W;
wire [31:0] ALUResultE2M, WriteDataE2M;
wire [4:0] WriteRegE2M;
wire RegWriteE2M, MemToRegE2M, BranchE2M, ZerowireE2M, MemWriteE2M;
instructionfetch IF(
.PCPlus4F( PCPlus4F2D ),
.instruction( instruction ),
.PCBranchF( PCBranchM2F ),
.WAinstrF( WAInstrD2F ),
.clk( clk ),
.reset( reset ),
.JumpF( JumpD2F ),
.PCSrcF( PCSrcM2F )
);
instructiondecode ID(
.read1( RFRead1D2E ),
.read2( RFRead2D2E ),
.immediateSE( ImmSeD2E ),
.PCPlus4D2( PCPlus4D2E ),
.WAinstrD( WAInstrD2F ),
.rt( rtD2E ),
.rd( rdD2E ),
.ALUControlD( ALUControlD2E ),
.RegWriteD( RegWriteD2E ),
.MemToRegD( MemToRegD2E ),
.MemWriteD( MemWriteD2E ),
.BranchD( BranchD2E ),
.ALUSrcD( ALUSrcD2E ),
.RegDstD( RegDstD2E ),
.JumpD( JumpD2F ),
.PCPlus4D1( PCPlus4F2D ),
.instruction( instruction ),
.ResultW( ResultW2D ),
.WriteRegW( WriteRegW2D ),
.RegWriteW( RegWriteW2D ),
.clk( clk )
);
execute EX(
.ALUResult( ALUResultE2M ),
.PCBranchE( PCBranchE2M ),
.WriteDataE( WriteDataE2M ),
.WriteRegE( WriteRegE2M ),
.RegWriteE2( RegWriteE2M ), .MemToRegE2( MemToRegE2M ), .MemWriteE2( MemWriteE2M ), .BranchE2( BranchE2M ),
.ZerowireE( ZerowireE2M ),
.PCPlus4E( PCPlus4D2E ),
.srcA( RFRead1D2E ), .RegRead2( RFRead2D2E ), .SignImmE( ImmSeD2E ),
.rt( rtD2E ), .rd( rdD2E ),
.ALUControlE( ALUControlD2E ),
.ALUSrcE( ALUSrcD2E ), .RegDstE( RegDstD2E ),
.RegWriteE1( RegWriteD2E ), .MemToRegE1( MemToRegD2E ), .MemWriteE1( MemWriteD2E ), .BranchE1( BranchD2E )
);
memoryaccess MEM(
.ReadDataM( ReadDataM2W ),
.ALUResultOut( ALUResultOutM2W ),
.PCBranchM2( PCBranchM2F ),
.WriteRegM2( WriteRegM2W ),
.RegWriteM2( RegWriteM2W ),
.MemToRegM2( MemToRegM2W ),
.PCSrcM( PCSrcM2F ),
.WriteDataM( WriteDataE2M ),
.ALUResultIn( ALUResultE2M ),
.PCBranchM1( PCBranchE2M ),
.WriteRegM1( WriteRegE2M ),
.BranchM( BranchE2M ),
.MemWriteM( MemWriteE2M ),
.MemToRegM1( MemToRegE2M ),
.RegWriteM1( RegWriteE2M ),
.ZerowireM( ZerowireE2M ),
.clk( clk )
);
writeback WB(
.ResultW( ResultW2D ),
.WriteRegW2( WriteRegW2D ),
.RegWriteW2( RegWriteW2D ),
.ReadDataW( ReadDataM2W ),
.ALUResultW( ALUResultOutM2W ),
.WriteRegW1( WriteRegM2W ),
.MemToRegW( MemToRegM2W ),
.RegWriteW1( RegWriteM2W )
);
assign PCSrcM2F = BranchE2M & ZerowireE2M;
initial begin
$display(singlecycleprocessor.IF.PC);
end
endmodule | 0 |
141,664 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sources_1/new/writeback.v | 95,918,395 | writeback.v | v | 39 | 83 | [] | [] | [] | [(23, 38)] | null | data/verilator_xmls/0dabc6f5-f0de-445e-8849-a52dee641067.xml | null | 312,279 | module | module writeback(
output [31:0] ResultW,
output [4:0] WriteRegW2,
output RegWriteW2,
input [31:0] ReadDataW, ALUResultW,
input [4:0] WriteRegW1,
input MemToRegW, RegWriteW1
);
assign ResultW = MemToRegW ? ReadDataW : ALUResultW;
assign WriteRegW2 = WriteRegW1;
assign RegWriteW2 = RegWriteW1;
endmodule | module writeback(
output [31:0] ResultW,
output [4:0] WriteRegW2,
output RegWriteW2,
input [31:0] ReadDataW, ALUResultW,
input [4:0] WriteRegW1,
input MemToRegW, RegWriteW1
); |
assign ResultW = MemToRegW ? ReadDataW : ALUResultW;
assign WriteRegW2 = WriteRegW1;
assign RegWriteW2 = RegWriteW1;
endmodule | 0 |
141,665 | data/full_repos/permissive/95929275/best_score_handler.v | 95,929,275 | best_score_handler.v | v | 14 | 93 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/2a4db255-6d50-4341-a975-497d9ab503de.xml | null | 312,280 | module | module best_score_handler(clk, current_highscore, alltime_highscore, startGameEn);
input clk;
input startGameEn;
input [7:0] current_highscore;
output reg [7:0] alltime_highscore;
always@(posedge clk) begin
if(current_highscore > alltime_highscore) begin
alltime_highscore <= current_highscore;
end
end
endmodule | module best_score_handler(clk, current_highscore, alltime_highscore, startGameEn); |
input clk;
input startGameEn;
input [7:0] current_highscore;
output reg [7:0] alltime_highscore;
always@(posedge clk) begin
if(current_highscore > alltime_highscore) begin
alltime_highscore <= current_highscore;
end
end
endmodule | 1 |
141,666 | data/full_repos/permissive/95929275/collision_handler.v | 95,929,275 | collision_handler.v | v | 35 | 114 | [] | [] | [] | [(1, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/collision_handler.v:13: Cannot find file containing module: 'rate_divider'\n rate_divider rd_2hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: Exiting due to 1 error(s)\n" | 312,281 | module | module collision_handler(enem_grid, clock, startGameEn, current_health_update, user_x, user_y, enemy_x, enemy_y);
input [160*120-1:0]enem_grid;
input clock;
input startGameEn;
input [7:0] user_x;
input [6:0] user_y;
input [7:0] enemy_x;
input [6:0] enemy_y;
output reg current_health_update;
wire [27:0]rd_2hz_out;
rate_divider rd_2hz(
.enable(1'b1),
.countdown_start(28'd3_125_000),
.clock(clock),
.reset(startGameEn),
.q(rd_2hz_out)
);
wire collision_handler_clock = (rd_2hz_out == 28'b0) ? 1:0;
always@(posedge collision_handler_clock)
begin
if(enem_grid[120*user_x+user_y] == 1'b1)begin
current_health_update <= 1'b1;
end
else begin
current_health_update <= 1'b0;
end
end
endmodule | module collision_handler(enem_grid, clock, startGameEn, current_health_update, user_x, user_y, enemy_x, enemy_y); |
input [160*120-1:0]enem_grid;
input clock;
input startGameEn;
input [7:0] user_x;
input [6:0] user_y;
input [7:0] enemy_x;
input [6:0] enemy_y;
output reg current_health_update;
wire [27:0]rd_2hz_out;
rate_divider rd_2hz(
.enable(1'b1),
.countdown_start(28'd3_125_000),
.clock(clock),
.reset(startGameEn),
.q(rd_2hz_out)
);
wire collision_handler_clock = (rd_2hz_out == 28'b0) ? 1:0;
always@(posedge collision_handler_clock)
begin
if(enem_grid[120*user_x+user_y] == 1'b1)begin
current_health_update <= 1'b1;
end
else begin
current_health_update <= 1'b0;
end
end
endmodule | 1 |
141,668 | data/full_repos/permissive/95929275/current_score_handler.v | 95,929,275 | current_score_handler.v | v | 17 | 96 | [] | [] | [] | [(1, 16)] | null | data/verilator_xmls/b8cfaf6a-dac2-462a-93cc-06b71f890d4a.xml | null | 312,283 | module | module current_score_handler(current_highscore, clk, current_score_update, startGameEn);
input startGameEn;
input clk;
input current_score_update;
output reg [7:0] current_highscore;
always@(posedge clk) begin
if(startGameEn)begin
current_highscore <= 8'b0;
end
if(current_score_update) begin
current_highscore <= (current_highscore < 8'hFF) ? current_highscore + 1'b1 : 8'hFF;
end
end
endmodule | module current_score_handler(current_highscore, clk, current_score_update, startGameEn); |
input startGameEn;
input clk;
input current_score_update;
output reg [7:0] current_highscore;
always@(posedge clk) begin
if(startGameEn)begin
current_highscore <= 8'b0;
end
if(current_score_update) begin
current_highscore <= (current_highscore < 8'hFF) ? current_highscore + 1'b1 : 8'hFF;
end
end
endmodule | 1 |
141,670 | data/full_repos/permissive/95929275/enemy_gun_handler.v | 95,929,275 | enemy_gun_handler.v | v | 32 | 112 | [] | [] | [] | [(1, 31)] | null | data/verilator_xmls/650add90-8792-4777-9161-a1e44c5bf2ed.xml | null | 312,285 | module | module enemy_gun_handler(clock,gun_cooldown, startGameEn, enemy_shoot);
input clock;
input [3:0] gun_cooldown;
input startGameEn;
output reg enemy_shoot;
reg clear;
always@(posedge clock)
begin
if(startGameEn) begin
enemy_shoot = 1'b0;
clear <= 1'b0;
end
if(clear && gun_cooldown != 4'b0000) begin
enemy_shoot = 1'b0;
end
else if (clear && gun_cooldown == 4'b0000) begin
clear <= 1'b0;
end
else if(~clear && gun_cooldown < 4'b1111) begin
enemy_shoot = 1'b1;
end
else if(~clear && gun_cooldown == 4'b1111) begin
clear <= 1'b1;
enemy_shoot = 1'b0;
end
end
endmodule | module enemy_gun_handler(clock,gun_cooldown, startGameEn, enemy_shoot); |
input clock;
input [3:0] gun_cooldown;
input startGameEn;
output reg enemy_shoot;
reg clear;
always@(posedge clock)
begin
if(startGameEn) begin
enemy_shoot = 1'b0;
clear <= 1'b0;
end
if(clear && gun_cooldown != 4'b0000) begin
enemy_shoot = 1'b0;
end
else if (clear && gun_cooldown == 4'b0000) begin
clear <= 1'b0;
end
else if(~clear && gun_cooldown < 4'b1111) begin
enemy_shoot = 1'b1;
end
else if(~clear && gun_cooldown == 4'b1111) begin
clear <= 1'b1;
enemy_shoot = 1'b0;
end
end
endmodule | 1 |
141,671 | data/full_repos/permissive/95929275/enemy_movement_handler.v | 95,929,275 | enemy_movement_handler.v | v | 43 | 101 | [] | [] | [] | [(1, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/enemy_movement_handler.v:8: Cannot find file containing module: 'rate_divider'\n rate_divider rd_2hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: Exiting due to 1 error(s)\n" | 312,286 | module | module enemy_movement_handler(clock, x_val, startGameEn);
input clock;
input startGameEn;
output reg [7:0] x_val;
wire [27:0]rd_2hz_out;
rate_divider rd_2hz(
.enable(1'b1),
.countdown_start(28'd24_99_999),
.clock(clock),
.reset(startGameEn),
.q(rd_2hz_out)
);
wire movement_handler_clock = (rd_2hz_out == 28'b0) ? 1:0;
reg left;
always@(posedge movement_handler_clock)
begin
if(startGameEn)begin
x_val <= 8'b0;
left <= 1'b0;
end
else if(!left) begin
x_val <= x_val + 1'b1;
if(x_val == 8'd160)begin
left = 1'b1;
end
end
else if(left)begin
x_val <= x_val - 1'b1;
if(x_val == 8'b0)begin
left = 1'b0;
end
end
end
endmodule | module enemy_movement_handler(clock, x_val, startGameEn); |
input clock;
input startGameEn;
output reg [7:0] x_val;
wire [27:0]rd_2hz_out;
rate_divider rd_2hz(
.enable(1'b1),
.countdown_start(28'd24_99_999),
.clock(clock),
.reset(startGameEn),
.q(rd_2hz_out)
);
wire movement_handler_clock = (rd_2hz_out == 28'b0) ? 1:0;
reg left;
always@(posedge movement_handler_clock)
begin
if(startGameEn)begin
x_val <= 8'b0;
left <= 1'b0;
end
else if(!left) begin
x_val <= x_val + 1'b1;
if(x_val == 8'd160)begin
left = 1'b1;
end
end
else if(left)begin
x_val <= x_val - 1'b1;
if(x_val == 8'b0)begin
left = 1'b0;
end
end
end
endmodule | 1 |
141,674 | data/full_repos/permissive/95929275/gun_cooldown_handler.v | 95,929,275 | gun_cooldown_handler.v | v | 44 | 99 | [] | [] | [] | [(1, 43)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/gun_cooldown_handler.v:11: Cannot find file containing module: 'rate_divider'\n rate_divider rd_1hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: data/full_repos/permissive/95929275/gun_cooldown_handler.v:22: Cannot find file containing module: 'rate_divider'\n rate_divider rd_050hz(\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,289 | module | module gun_cooldown_handler(clock, shoot, gun_cooldown_counter, startGameEn);
input clock;
input shoot;
input startGameEn;
output reg [3:0] gun_cooldown_counter;
wire [27:0]rd_1hz_out, rd_050hz_out;
rate_divider rd_1hz(
.enable(1'b1),
.countdown_start(28'd49_999_999),
.clock(clock),
.reset(startGameEn),
.q(rd_1hz_out)
);
rate_divider rd_050hz(
.enable(1'b1),
.countdown_start(28'd99_999_999),
.clock(clock),
.reset(startGameEn),
.q(rd_050hz_out)
);
wire gun_firing_enable = (rd_1hz_out == 28'b0) ? 1'b1 : 1'b0;
wire gun_cooldown_enable = (rd_050hz_out == 28'b0) ? 1'b1 : 1'b0;
always@(posedge clock)
begin
if(startGameEn)
gun_cooldown_counter = 4'b0000;
if(gun_firing_enable & shoot)
gun_cooldown_counter = (gun_cooldown_counter < 4'b1111) ? gun_cooldown_counter + 1'b1 : 4'b1111;
if(gun_cooldown_enable & !shoot)
gun_cooldown_counter = (gun_cooldown_counter > 4'b0000) ? gun_cooldown_counter - 1'b1 : 4'b0000;
end
endmodule | module gun_cooldown_handler(clock, shoot, gun_cooldown_counter, startGameEn); |
input clock;
input shoot;
input startGameEn;
output reg [3:0] gun_cooldown_counter;
wire [27:0]rd_1hz_out, rd_050hz_out;
rate_divider rd_1hz(
.enable(1'b1),
.countdown_start(28'd49_999_999),
.clock(clock),
.reset(startGameEn),
.q(rd_1hz_out)
);
rate_divider rd_050hz(
.enable(1'b1),
.countdown_start(28'd99_999_999),
.clock(clock),
.reset(startGameEn),
.q(rd_050hz_out)
);
wire gun_firing_enable = (rd_1hz_out == 28'b0) ? 1'b1 : 1'b0;
wire gun_cooldown_enable = (rd_050hz_out == 28'b0) ? 1'b1 : 1'b0;
always@(posedge clock)
begin
if(startGameEn)
gun_cooldown_counter = 4'b0000;
if(gun_firing_enable & shoot)
gun_cooldown_counter = (gun_cooldown_counter < 4'b1111) ? gun_cooldown_counter + 1'b1 : 4'b1111;
if(gun_cooldown_enable & !shoot)
gun_cooldown_counter = (gun_cooldown_counter > 4'b0000) ? gun_cooldown_counter - 1'b1 : 4'b0000;
end
endmodule | 1 |
141,676 | data/full_repos/permissive/95929275/logic_handler.v | 95,929,275 | logic_handler.v | v | 123 | 205 | [] | [] | [] | [(1, 122)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/logic_handler.v:29: Cannot find file containing module: 'enemy_gun_handler'\n enemy_gun_handler gun(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/enemy_gun_handler\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/enemy_gun_handler.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/enemy_gun_handler.sv\n enemy_gun_handler\n enemy_gun_handler.v\n enemy_gun_handler.sv\n obj_dir/enemy_gun_handler\n obj_dir/enemy_gun_handler.v\n obj_dir/enemy_gun_handler.sv\n%Error: data/full_repos/permissive/95929275/logic_handler.v:37: Cannot find file containing module: 'gun_cooldown_handler'\n gun_cooldown_handler gc(\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:45: Cannot find file containing module: 'user_movement_handler'\n user_movement_handler user_mv(\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:54: Cannot find file containing module: 'enemy_movement_handler'\n enemy_movement_handler enemy_mv(\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:62: Cannot find file containing module: 'shifter_grid'\n shifter_grid sh_enem(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:76: Cannot find file containing module: 'rate_divider'\n rate_divider rd_2hz(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:87: Cannot find file containing module: 'collision_handler'\n collision_handler ch(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:99: Cannot find file containing module: 'current_score_handler'\n current_score_handler csh(\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:107: Cannot find file containing module: 'best_score_handler'\n best_score_handler bsh(\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95929275/logic_handler.v:115: Cannot find file containing module: 'health_handler'\n health_handler h(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n" | 312,292 | module | module logic_handler(clk, reset, right, left, shoot, startGameEn, shipUpdateEn, gridUpdateEn, user_x, user_y, enemy_x, enemy_y, gun_cooldown, enem_grid, ship_health, current_highscore, alltime_highscore);
input clk;
input reset;
input right;
input left;
input shoot;
input startGameEn;
input shipUpdateEn;
input gridUpdateEn;
output [3:0] ship_health;
output [7:0] current_highscore;
output [7:0] alltime_highscore;
output reg [7:0] user_x;
input [6:0] user_y;
output reg [7:0] enemy_x;
input [6:0] enemy_y;
output reg [3:0] gun_cooldown;
output reg [160*120-1:0] enem_grid;
wire enemy_shoot;
enemy_gun_handler gun(
.clock(clk),
.gun_cooldown(gun_cooldown),
.startGameEn(startGameEn),
.enemy_shoot(enemy_shoot)
);
gun_cooldown_handler gc(
.clock(clk),
.shoot(enemy_shoot),
.gun_cooldown_counter(gun_cooldown),
.startGameEn(startGameEn)
);
user_movement_handler user_mv(
.clock(clk),
.right(right),
.left(left),
.x_val(user_x),
.startGameEn(startGameEn)
);
enemy_movement_handler enemy_mv(
.clock(clk),
.x_val(enemy_x),
.startGameEn(startGameEn)
);
shifter_grid sh_enem(
.shoot(enemy_shoot),
.clock(clk),
.user_x(enemy_x),
.grid(enem_grid),
.gridUpdateEn(gridUpdateEn),
.startGameEn(startGameEn)
);
wire current_score_update;
wire current_health_update;
wire [27:0]rd_2hz_out;
rate_divider rd_2hz(
.enable(1'b1),
.countdown_start(28'd24_999_999),
.clock(clk),
.reset(startGameEn),
.q(rd_2hz_out)
);
assign current_score_update = (rd_2hz_out == 28'b0) ? 1'b1 : 1'b0;
collision_handler ch(
.clock(clk),
.current_health_update(current_health_update),
.user_x(user_x),
.user_y(user_y),
.enemy_x(enemy_x),
.enemy_y(enemy_y),
.enem_grid(enem_grid)
);
current_score_handler csh(
.current_highscore(current_highscore),
.current_score_update(current_score_update),
.clk(clk),
.startGameEn(startGameEn)
);
best_score_handler bsh(
.current_highscore(current_highscore),
.alltime_highscore(alltime_highscore),
.clk(clk),
.startGameEn(startGameEn)
);
health_handler h(
.ship_health(ship_health),
.health_update(current_health_update),
.clk(clk),
.startGameEn(startGameEn)
);
endmodule | module logic_handler(clk, reset, right, left, shoot, startGameEn, shipUpdateEn, gridUpdateEn, user_x, user_y, enemy_x, enemy_y, gun_cooldown, enem_grid, ship_health, current_highscore, alltime_highscore); |
input clk;
input reset;
input right;
input left;
input shoot;
input startGameEn;
input shipUpdateEn;
input gridUpdateEn;
output [3:0] ship_health;
output [7:0] current_highscore;
output [7:0] alltime_highscore;
output reg [7:0] user_x;
input [6:0] user_y;
output reg [7:0] enemy_x;
input [6:0] enemy_y;
output reg [3:0] gun_cooldown;
output reg [160*120-1:0] enem_grid;
wire enemy_shoot;
enemy_gun_handler gun(
.clock(clk),
.gun_cooldown(gun_cooldown),
.startGameEn(startGameEn),
.enemy_shoot(enemy_shoot)
);
gun_cooldown_handler gc(
.clock(clk),
.shoot(enemy_shoot),
.gun_cooldown_counter(gun_cooldown),
.startGameEn(startGameEn)
);
user_movement_handler user_mv(
.clock(clk),
.right(right),
.left(left),
.x_val(user_x),
.startGameEn(startGameEn)
);
enemy_movement_handler enemy_mv(
.clock(clk),
.x_val(enemy_x),
.startGameEn(startGameEn)
);
shifter_grid sh_enem(
.shoot(enemy_shoot),
.clock(clk),
.user_x(enemy_x),
.grid(enem_grid),
.gridUpdateEn(gridUpdateEn),
.startGameEn(startGameEn)
);
wire current_score_update;
wire current_health_update;
wire [27:0]rd_2hz_out;
rate_divider rd_2hz(
.enable(1'b1),
.countdown_start(28'd24_999_999),
.clock(clk),
.reset(startGameEn),
.q(rd_2hz_out)
);
assign current_score_update = (rd_2hz_out == 28'b0) ? 1'b1 : 1'b0;
collision_handler ch(
.clock(clk),
.current_health_update(current_health_update),
.user_x(user_x),
.user_y(user_y),
.enemy_x(enemy_x),
.enemy_y(enemy_y),
.enem_grid(enem_grid)
);
current_score_handler csh(
.current_highscore(current_highscore),
.current_score_update(current_score_update),
.clk(clk),
.startGameEn(startGameEn)
);
best_score_handler bsh(
.current_highscore(current_highscore),
.alltime_highscore(alltime_highscore),
.clk(clk),
.startGameEn(startGameEn)
);
health_handler h(
.ship_health(ship_health),
.health_update(current_health_update),
.clk(clk),
.startGameEn(startGameEn)
);
endmodule | 1 |
141,677 | data/full_repos/permissive/95929275/rate_divider.v | 95,929,275 | rate_divider.v | v | 19 | 93 | [] | [] | [] | [(1, 17)] | null | data/verilator_xmls/201cc261-6185-4b26-873a-71c6c22c3f9a.xml | null | 312,293 | module | module rate_divider(enable, countdown_start, clock, reset, q);
input enable;
input reset;
input clock;
input [27:0]countdown_start;
output reg [27:0]q;
always @(posedge clock)
begin
if(reset == 1'b1)
q <= countdown_start;
else if(enable == 1'b1)
q <= (q == 0) ? countdown_start : q - 1'b1;
end
endmodule | module rate_divider(enable, countdown_start, clock, reset, q); |
input enable;
input reset;
input clock;
input [27:0]countdown_start;
output reg [27:0]q;
always @(posedge clock)
begin
if(reset == 1'b1)
q <= countdown_start;
else if(enable == 1'b1)
q <= (q == 0) ? countdown_start : q - 1'b1;
end
endmodule | 1 |
141,678 | data/full_repos/permissive/95929275/shifter_grid.v | 95,929,275 | shifter_grid.v | v | 148 | 151 | [] | [] | [] | [(1, 45), (47, 57), (59, 74), (76, 113), (115, 147)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/shifter_grid.v:12: Cannot find file containing module: 'rate_divider'\n rate_divider rd_1hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: Exiting due to 1 error(s)\n" | 312,294 | module | module shifter_grid(startGameEn, shoot, clock, gridUpdateEn, user_x, grid);
input startGameEn;
input shoot;
input clock;
input gridUpdateEn;
input [7:0]user_x;
output [160*120-1:0]grid;
wire [27:0]rd_1hz_out;
rate_divider rd_1hz(
.enable(1'b1),
.countdown_start(28'd3_125_000),
.clock(clock),
.reset(startGameEn),
.q(rd_1hz_out)
);
wire shift_right_enable = rd_1hz_out == 28'b0 ? 1'b1 : 1'b0;
genvar i;
generate
for(i = 0;i < 160;i = i+1) begin: shifter_grids
shifter shift_i(
.load_val(user_x == i & shoot),
.load_n(shoot),
.shift_right(shift_right_enable),
.ASR(1'b0),
.clk(clock),
.reset_n(startGameEn),
.Q(grid[120*(i+1)-1: 120*i])
);
end
endgenerate
endmodule | module shifter_grid(startGameEn, shoot, clock, gridUpdateEn, user_x, grid); |
input startGameEn;
input shoot;
input clock;
input gridUpdateEn;
input [7:0]user_x;
output [160*120-1:0]grid;
wire [27:0]rd_1hz_out;
rate_divider rd_1hz(
.enable(1'b1),
.countdown_start(28'd3_125_000),
.clock(clock),
.reset(startGameEn),
.q(rd_1hz_out)
);
wire shift_right_enable = rd_1hz_out == 28'b0 ? 1'b1 : 1'b0;
genvar i;
generate
for(i = 0;i < 160;i = i+1) begin: shifter_grids
shifter shift_i(
.load_val(user_x == i & shoot),
.load_n(shoot),
.shift_right(shift_right_enable),
.ASR(1'b0),
.clk(clock),
.reset_n(startGameEn),
.Q(grid[120*(i+1)-1: 120*i])
);
end
endgenerate
endmodule | 1 |
141,679 | data/full_repos/permissive/95929275/shifter_grid.v | 95,929,275 | shifter_grid.v | v | 148 | 151 | [] | [] | [] | [(1, 45), (47, 57), (59, 74), (76, 113), (115, 147)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/shifter_grid.v:12: Cannot find file containing module: 'rate_divider'\n rate_divider rd_1hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: Exiting due to 1 error(s)\n" | 312,294 | module | module mux2to1(x, y, s, m);
input x;
input y;
input s;
output m;
assign m = s & y | ~s & x;
endmodule | module mux2to1(x, y, s, m); |
input x;
input y;
input s;
output m;
assign m = s & y | ~s & x;
endmodule | 1 |
141,680 | data/full_repos/permissive/95929275/shifter_grid.v | 95,929,275 | shifter_grid.v | v | 148 | 151 | [] | [] | [] | [(1, 45), (47, 57), (59, 74), (76, 113), (115, 147)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/shifter_grid.v:12: Cannot find file containing module: 'rate_divider'\n rate_divider rd_1hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: Exiting due to 1 error(s)\n" | 312,294 | module | module flipflop(d, q, clock, reset_n);
input d;
input clock;
input reset_n;
output reg q;
always @(posedge clock)
begin
if(reset_n == 1'b1)
q <= 0;
else
q <= d;
end
endmodule | module flipflop(d, q, clock, reset_n); |
input d;
input clock;
input reset_n;
output reg q;
always @(posedge clock)
begin
if(reset_n == 1'b1)
q <= 0;
else
q <= d;
end
endmodule | 1 |
141,681 | data/full_repos/permissive/95929275/shifter_grid.v | 95,929,275 | shifter_grid.v | v | 148 | 151 | [] | [] | [] | [(1, 45), (47, 57), (59, 74), (76, 113), (115, 147)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/shifter_grid.v:12: Cannot find file containing module: 'rate_divider'\n rate_divider rd_1hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: Exiting due to 1 error(s)\n" | 312,294 | module | module shifter_bit(in, load_val, shift, load_n, ignore_load_n, clk, reset_n, out);
input in;
input load_val;
input shift;
input load_n;
input ignore_load_n;
input clk;
input reset_n;
output out;
wire mux_one_out, mux_two_out;
wire load_val_decider = (load_n) & (~ignore_load_n);
mux2to1 mux_one(
.x(out),
.y(in),
.s(shift),
.m(mux_one_out)
);
mux2to1 mux_two(
.x(mux_one_out),
.y(load_val),
.s(load_val_decider),
.m(mux_two_out)
);
flipflop flip_flop(
.d(mux_two_out),
.q(out),
.clock(clk),
.reset_n(reset_n)
);
endmodule | module shifter_bit(in, load_val, shift, load_n, ignore_load_n, clk, reset_n, out); |
input in;
input load_val;
input shift;
input load_n;
input ignore_load_n;
input clk;
input reset_n;
output out;
wire mux_one_out, mux_two_out;
wire load_val_decider = (load_n) & (~ignore_load_n);
mux2to1 mux_one(
.x(out),
.y(in),
.s(shift),
.m(mux_one_out)
);
mux2to1 mux_two(
.x(mux_one_out),
.y(load_val),
.s(load_val_decider),
.m(mux_two_out)
);
flipflop flip_flop(
.d(mux_two_out),
.q(out),
.clock(clk),
.reset_n(reset_n)
);
endmodule | 1 |
141,682 | data/full_repos/permissive/95929275/shifter_grid.v | 95,929,275 | shifter_grid.v | v | 148 | 151 | [] | [] | [] | [(1, 45), (47, 57), (59, 74), (76, 113), (115, 147)] | null | null | 1: b"%Error: data/full_repos/permissive/95929275/shifter_grid.v:12: Cannot find file containing module: 'rate_divider'\n rate_divider rd_1hz(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.v\n data/full_repos/permissive/95929275,data/full_repos/permissive/95929275/rate_divider.sv\n rate_divider\n rate_divider.v\n rate_divider.sv\n obj_dir/rate_divider\n obj_dir/rate_divider.v\n obj_dir/rate_divider.sv\n%Error: Exiting due to 1 error(s)\n" | 312,294 | module | module shifter(load_val, load_n, shift_right, ASR, clk, reset_n, Q);
input load_val;
input load_n;
input shift_right;
input ASR;
input clk;
input reset_n;
output [119:0]Q;
wire [119:0]sb_out;
genvar i;
generate
for(i = 0;i < 120;i = i+1) begin: shifter_bit_init
shifter_bit sb_i(
.in( (i == 0 ? ASR & load_val : sb_out[i-1]) ),
.load_val(load_val),
.shift(shift_right),
.load_n(load_n),
.ignore_load_n(~(i == 0)),
.clk(clk),
.reset_n(reset_n),
.out(sb_out[i])
);
end
endgenerate
assign Q = sb_out[119:0];
endmodule | module shifter(load_val, load_n, shift_right, ASR, clk, reset_n, Q); |
input load_val;
input load_n;
input shift_right;
input ASR;
input clk;
input reset_n;
output [119:0]Q;
wire [119:0]sb_out;
genvar i;
generate
for(i = 0;i < 120;i = i+1) begin: shifter_bit_init
shifter_bit sb_i(
.in( (i == 0 ? ASR & load_val : sb_out[i-1]) ),
.load_val(load_val),
.shift(shift_right),
.load_n(load_n),
.ignore_load_n(~(i == 0)),
.clk(clk),
.reset_n(reset_n),
.out(sb_out[i])
);
end
endgenerate
assign Q = sb_out[119:0];
endmodule | 1 |
141,685 | data/full_repos/permissive/95938920/src/main/modules/arduino_driver/arduino_driver.v | 95,938,920 | arduino_driver.v | v | 24 | 48 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/bf43df40-bed2-4d7a-a67e-dbd91827a730.xml | null | 312,301 | module | module arduino_driver(
input clk50,
input clk,
input we,
input [7:0] system_input,
input [31:0] module_input,
output reg [7:0] system_output,
output [31:0] module_output);
reg [31:0] system_input_buffer;
always @ (posedge clk50) begin
system_input_buffer <= {24'b0, system_input};
end
always @ (posedge clk) begin
if (we) begin
system_output <= module_input[7:0];
end
end
assign module_output = system_input_buffer;
endmodule | module arduino_driver(
input clk50,
input clk,
input we,
input [7:0] system_input,
input [31:0] module_input,
output reg [7:0] system_output,
output [31:0] module_output); |
reg [31:0] system_input_buffer;
always @ (posedge clk50) begin
system_input_buffer <= {24'b0, system_input};
end
always @ (posedge clk) begin
if (we) begin
system_output <= module_input[7:0];
end
end
assign module_output = system_input_buffer;
endmodule | 0 |
141,686 | data/full_repos/permissive/95938920/src/main/modules/banco_de_registradores/banco_de_registradores.v | 95,938,920 | banco_de_registradores.v | v | 26 | 59 | [] | [] | [] | [(1, 25)] | null | data/verilator_xmls/9e2ff316-948d-4ce9-beb2-b513f8d5f899.xml | null | 312,302 | module | module banco_de_registradores(clock, regWrite, RS, RT,
RD, dadosEscrita, leituraRS, leituraRT);
input [4:0] RS;
input [4:0] RT;
input [4:0] RD;
input [31:0] dadosEscrita;
output [31:0] leituraRS;
output [31:0] leituraRT;
input clock;
input regWrite;
reg [31:0] regs[31:0];
always @ (posedge clock) begin
regs[RD] <= regWrite ? dadosEscrita : regs[RD];
end
assign leituraRS = regs[RS];
assign leituraRT = regs[RT];
endmodule | module banco_de_registradores(clock, regWrite, RS, RT,
RD, dadosEscrita, leituraRS, leituraRT); |
input [4:0] RS;
input [4:0] RT;
input [4:0] RD;
input [31:0] dadosEscrita;
output [31:0] leituraRS;
output [31:0] leituraRT;
input clock;
input regWrite;
reg [31:0] regs[31:0];
always @ (posedge clock) begin
regs[RD] <= regWrite ? dadosEscrita : regs[RD];
end
assign leituraRS = regs[RS];
assign leituraRT = regs[RT];
endmodule | 0 |
141,687 | data/full_repos/permissive/95938920/src/main/modules/BCD_dois_digitos/BCD_dois_digitos.v | 95,938,920 | BCD_dois_digitos.v | v | 43 | 76 | [] | [] | [] | [(1, 42)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/BCD_dois_digitos/BCD_dois_digitos.v:30: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance BCD_dois_digitos\n aux = ~(numero) + 8\'b00000001;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,303 | module | module BCD_dois_digitos(numero, sinal, dezena, unidade);
input [31:0] numero;
output reg sinal;
output reg [3:0] dezena;
output reg [3:0] unidade;
reg [31:0] aux;
integer i;
always @ (numero) begin
aux = 32'b0;
dezena = 4'b0000;
unidade = 4'b0000;
if(numero[15] == 0) begin
sinal = 1'b0;
for(i = 15; i >=0; i = i-1) begin
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = numero[i];
end
end
else begin
aux = ~(numero) + 8'b00000001;
sinal = 1'b1;
for(i = 15; i >=0; i = i-1) begin
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = aux[i];
end
end
end
endmodule | module BCD_dois_digitos(numero, sinal, dezena, unidade); |
input [31:0] numero;
output reg sinal;
output reg [3:0] dezena;
output reg [3:0] unidade;
reg [31:0] aux;
integer i;
always @ (numero) begin
aux = 32'b0;
dezena = 4'b0000;
unidade = 4'b0000;
if(numero[15] == 0) begin
sinal = 1'b0;
for(i = 15; i >=0; i = i-1) begin
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = numero[i];
end
end
else begin
aux = ~(numero) + 8'b00000001;
sinal = 1'b1;
for(i = 15; i >=0; i = i-1) begin
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = aux[i];
end
end
end
endmodule | 0 |
141,688 | data/full_repos/permissive/95938920/src/main/modules/BCD_quatro_digitos/BCD_quatro_digitos.v | 95,938,920 | BCD_quatro_digitos.v | v | 59 | 76 | [] | [] | [] | [(1, 58)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/BCD_quatro_digitos/BCD_quatro_digitos.v:40: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n : ... In instance BCD_quatro_digitos\n aux = ~(numero) + 16\'b0000000000000001;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,304 | module | module BCD_quatro_digitos(numero, sinal, milhar, centena, dezena, unidade);
input [31:0] numero;
output reg sinal;
output reg [3:0] milhar;
output reg [3:0] centena;
output reg [3:0] dezena;
output reg [3:0] unidade;
reg [31:0] aux;
integer i;
always @ (numero) begin
aux = 32'b0;
milhar = 4'b0000;
centena = 4'b0000;
dezena = 4'b0000;
unidade = 4'b0000;
if(numero[31] == 0) begin
sinal = 1'b0;
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = numero[i];
end
end
else begin
aux = ~(numero) + 16'b0000000000000001;
sinal = 1'b1;
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = aux[i];
end
end
end
endmodule | module BCD_quatro_digitos(numero, sinal, milhar, centena, dezena, unidade); |
input [31:0] numero;
output reg sinal;
output reg [3:0] milhar;
output reg [3:0] centena;
output reg [3:0] dezena;
output reg [3:0] unidade;
reg [31:0] aux;
integer i;
always @ (numero) begin
aux = 32'b0;
milhar = 4'b0000;
centena = 4'b0000;
dezena = 4'b0000;
unidade = 4'b0000;
if(numero[31] == 0) begin
sinal = 1'b0;
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = numero[i];
end
end
else begin
aux = ~(numero) + 16'b0000000000000001;
sinal = 1'b1;
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = aux[i];
end
end
end
endmodule | 0 |
141,689 | data/full_repos/permissive/95938920/src/main/modules/bios/bios.v | 95,938,920 | bios.v | v | 70 | 74 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/bios/bios.v:68: Bit extraction of array[58:0] requires 6 bit index, not 26 bits.\n : ... In instance bios\n assign instrucao = bios[pc];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,305 | module | module bios(
input [25:0] pc,
output [31:0] instrucao);
localparam BIOS_SIZE = 59;
wire [31:0] bios [BIOS_SIZE-1:0];
assign bios[0] = 32'b111100_00000000000000000000101111;
assign bios[1] = 32'b000001_11110_11110_0000000000000010;
assign bios[2] = 32'b010000_00000_00001_0000000000010100;
assign bios[3] = 32'b011110_00000_00001_0000000000000000;
assign bios[4] = 32'b010011_00000_01111_0000000000000000;
assign bios[5] = 32'b010000_00000_00001_0000000000010101;
assign bios[6] = 32'b011110_00000_00001_0000000000000000;
assign bios[7] = 32'b010011_00000_10000_0000000000000000;
assign bios[8] = 32'b010000_00000_00001_0000000000010110;
assign bios[9] = 32'b011110_00000_00001_0000000000000000;
assign bios[10] = 32'b010011_00000_10001_0000000000000000;
assign bios[11] = 32'b010000_00000_00001_0000000000010111;
assign bios[12] = 32'b011110_00000_00001_0000000000000000;
assign bios[13] = 32'b010011_00000_10010_0000000000000000;
assign bios[14] = 32'b000000_11111_00000_00000_00000_010010;
assign bios[15] = 32'b000001_11110_11110_0000000000000101;
assign bios[16] = 32'b010000_00000_01111_0000000000111111;
assign bios[17] = 32'b010010_11110_01111_0000000000000000;
assign bios[18] = 32'b010000_00000_10000_0000000000000000;
assign bios[19] = 32'b010010_11110_10000_1111111111111111;
assign bios[20] = 32'b001111_11110_00101_1111111111111111;
assign bios[21] = 32'b001110_00101_00001_0000000000000000;
assign bios[22] = 32'b010110_00001_10001_0000000000000000;
assign bios[23] = 32'b010010_11110_10001_1111111111111110;
assign bios[24] = 32'b001111_11110_00101_1111111111111110;
assign bios[25] = 32'b001101_00101_10010_0000000000011010;
assign bios[26] = 32'b001111_11110_00110_0000000000000000;
assign bios[27] = 32'b000000_10010_00110_10011_00000_001101;
assign bios[28] = 32'b010101_10011_00000_0000000000101001;
assign bios[29] = 32'b001110_00101_00001_0000000000000000;
assign bios[30] = 32'b001111_11110_00111_1111111111111111;
assign bios[31] = 32'b001110_00111_00010_0000000000000000;
assign bios[32] = 32'b011010_00010_00001_0000000000000000;
assign bios[33] = 32'b000001_00111_10100_0000000000000001;
assign bios[34] = 32'b010010_11110_10100_1111111111111111;
assign bios[35] = 32'b001111_11110_00111_1111111111111111;
assign bios[36] = 32'b001110_00111_00001_0000000000000000;
assign bios[37] = 32'b010110_00001_10101_0000000000000000;
assign bios[38] = 32'b010010_11110_10101_1111111111111110;
assign bios[39] = 32'b001111_11110_00101_1111111111111110;
assign bios[40] = 32'b111100_00000000000000000000011000;
assign bios[41] = 32'b001111_11110_00101_1111111111111110;
assign bios[42] = 32'b001110_00101_00001_0000000000000000;
assign bios[43] = 32'b001111_11110_00110_1111111111111111;
assign bios[44] = 32'b001110_00110_00010_0000000000000000;
assign bios[45] = 32'b011010_00010_00001_0000000000000000;
assign bios[46] = 32'b000000_11111_00000_00000_00000_010010;
assign bios[47] = 32'b000001_11110_11110_0000000000000001;
assign bios[48] = 32'b010010_11110_11111_0000000000000000;
assign bios[49] = 32'b111110_00000000000000000000000001;
assign bios[50] = 32'b000010_11110_11110_0000000000000010;
assign bios[51] = 32'b001111_11110_11111_0000000000000000;
assign bios[52] = 32'b001110_11000_00101_0000000000000000;
assign bios[53] = 32'b010010_11110_11111_0000000000000000;
assign bios[54] = 32'b111110_00000000000000000000001111;
assign bios[55] = 32'b000010_11110_11110_0000000000000101;
assign bios[56] = 32'b001111_11110_11111_0000000000000000;
assign bios[57] = 32'b001110_11000_00101_0000000000000000;
assign bios[58] = 32'b111111_00000000000000000000000000;
assign instrucao = bios[pc];
endmodule | module bios(
input [25:0] pc,
output [31:0] instrucao); |
localparam BIOS_SIZE = 59;
wire [31:0] bios [BIOS_SIZE-1:0];
assign bios[0] = 32'b111100_00000000000000000000101111;
assign bios[1] = 32'b000001_11110_11110_0000000000000010;
assign bios[2] = 32'b010000_00000_00001_0000000000010100;
assign bios[3] = 32'b011110_00000_00001_0000000000000000;
assign bios[4] = 32'b010011_00000_01111_0000000000000000;
assign bios[5] = 32'b010000_00000_00001_0000000000010101;
assign bios[6] = 32'b011110_00000_00001_0000000000000000;
assign bios[7] = 32'b010011_00000_10000_0000000000000000;
assign bios[8] = 32'b010000_00000_00001_0000000000010110;
assign bios[9] = 32'b011110_00000_00001_0000000000000000;
assign bios[10] = 32'b010011_00000_10001_0000000000000000;
assign bios[11] = 32'b010000_00000_00001_0000000000010111;
assign bios[12] = 32'b011110_00000_00001_0000000000000000;
assign bios[13] = 32'b010011_00000_10010_0000000000000000;
assign bios[14] = 32'b000000_11111_00000_00000_00000_010010;
assign bios[15] = 32'b000001_11110_11110_0000000000000101;
assign bios[16] = 32'b010000_00000_01111_0000000000111111;
assign bios[17] = 32'b010010_11110_01111_0000000000000000;
assign bios[18] = 32'b010000_00000_10000_0000000000000000;
assign bios[19] = 32'b010010_11110_10000_1111111111111111;
assign bios[20] = 32'b001111_11110_00101_1111111111111111;
assign bios[21] = 32'b001110_00101_00001_0000000000000000;
assign bios[22] = 32'b010110_00001_10001_0000000000000000;
assign bios[23] = 32'b010010_11110_10001_1111111111111110;
assign bios[24] = 32'b001111_11110_00101_1111111111111110;
assign bios[25] = 32'b001101_00101_10010_0000000000011010;
assign bios[26] = 32'b001111_11110_00110_0000000000000000;
assign bios[27] = 32'b000000_10010_00110_10011_00000_001101;
assign bios[28] = 32'b010101_10011_00000_0000000000101001;
assign bios[29] = 32'b001110_00101_00001_0000000000000000;
assign bios[30] = 32'b001111_11110_00111_1111111111111111;
assign bios[31] = 32'b001110_00111_00010_0000000000000000;
assign bios[32] = 32'b011010_00010_00001_0000000000000000;
assign bios[33] = 32'b000001_00111_10100_0000000000000001;
assign bios[34] = 32'b010010_11110_10100_1111111111111111;
assign bios[35] = 32'b001111_11110_00111_1111111111111111;
assign bios[36] = 32'b001110_00111_00001_0000000000000000;
assign bios[37] = 32'b010110_00001_10101_0000000000000000;
assign bios[38] = 32'b010010_11110_10101_1111111111111110;
assign bios[39] = 32'b001111_11110_00101_1111111111111110;
assign bios[40] = 32'b111100_00000000000000000000011000;
assign bios[41] = 32'b001111_11110_00101_1111111111111110;
assign bios[42] = 32'b001110_00101_00001_0000000000000000;
assign bios[43] = 32'b001111_11110_00110_1111111111111111;
assign bios[44] = 32'b001110_00110_00010_0000000000000000;
assign bios[45] = 32'b011010_00010_00001_0000000000000000;
assign bios[46] = 32'b000000_11111_00000_00000_00000_010010;
assign bios[47] = 32'b000001_11110_11110_0000000000000001;
assign bios[48] = 32'b010010_11110_11111_0000000000000000;
assign bios[49] = 32'b111110_00000000000000000000000001;
assign bios[50] = 32'b000010_11110_11110_0000000000000010;
assign bios[51] = 32'b001111_11110_11111_0000000000000000;
assign bios[52] = 32'b001110_11000_00101_0000000000000000;
assign bios[53] = 32'b010010_11110_11111_0000000000000000;
assign bios[54] = 32'b111110_00000000000000000000001111;
assign bios[55] = 32'b000010_11110_11110_0000000000000101;
assign bios[56] = 32'b001111_11110_11111_0000000000000000;
assign bios[57] = 32'b001110_11000_00101_0000000000000000;
assign bios[58] = 32'b111111_00000000000000000000000000;
assign instrucao = bios[pc];
endmodule | 0 |
141,690 | data/full_repos/permissive/95938920/src/main/modules/contador_de_programa/contador_de_programa.v | 95,938,920 | contador_de_programa.v | v | 17 | 46 | [] | [] | [] | [(1, 16)] | null | data/verilator_xmls/4e9db89f-e875-4260-8939-014e490a0046.xml | null | 312,306 | module | module contador_de_programa(
input clk,
input reset,
input inta,
input [25:0] addrin,
output reg [25:0] addrout,
output reg [25:0] addrBckp);
always @ (negedge clk) begin
addrBckp <= inta ? addrBckp : addrin;
end
always @ (posedge clk) begin
addrout <= reset | inta ? 26'b0 : addrin;
end
endmodule | module contador_de_programa(
input clk,
input reset,
input inta,
input [25:0] addrin,
output reg [25:0] addrout,
output reg [25:0] addrBckp); |
always @ (negedge clk) begin
addrBckp <= inta ? addrBckp : addrin;
end
always @ (posedge clk) begin
addrout <= reset | inta ? 26'b0 : addrin;
end
endmodule | 0 |
141,691 | data/full_repos/permissive/95938920/src/main/modules/controlador_bios/controlador_bios.v | 95,938,920 | controlador_bios.v | v | 37 | 61 | [] | [] | [] | null | line:37: before: "data" | data/verilator_xmls/36899c95-45ac-40b6-acdd-2ff9f42b221a.xml | null | 312,307 | module | module controlador_bios(clk, bios, mem, out, reset);
input clk;
input [31:0] bios;
input [31:0] mem;
output [31:0] out;
output reg reset;
reg state;
localparam BIOS = 1'b0, MEMORY = 1'b1;
localparam HALT = 6'b111111;
initial begin
state <= BIOS;
end
always @ (posedge clk) begin
if (state == BIOS) begin
case(bios[31:26])
HALT: begin
state <= MEMORY;
reset <= 1'b1;
end
default: begin
reset <= 1'b0;
end
endcase
end else begin
reset <= 1'b0;
end
end
assign out = state == BIOS ? bios : mem;
endmodule | module controlador_bios(clk, bios, mem, out, reset); |
input clk;
input [31:0] bios;
input [31:0] mem;
output [31:0] out;
output reg reset;
reg state;
localparam BIOS = 1'b0, MEMORY = 1'b1;
localparam HALT = 6'b111111;
initial begin
state <= BIOS;
end
always @ (posedge clk) begin
if (state == BIOS) begin
case(bios[31:26])
HALT: begin
state <= MEMORY;
reset <= 1'b1;
end
default: begin
reset <= 1'b0;
end
endcase
end else begin
reset <= 1'b0;
end
end
assign out = state == BIOS ? bios : mem;
endmodule | 0 |
141,692 | data/full_repos/permissive/95938920/src/main/modules/controlador_interrupcao/controlador_interrupcao.v | 95,938,920 | controlador_interrupcao.v | v | 35 | 93 | [] | [] | [] | [(1, 34)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/controlador_interrupcao/controlador_interrupcao.v:21: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'pc\' generates 26 bits.\n : ... In instance controlador_interrupcao\n pcBckp <= ack ? salto ? pc : pc + 1 : pcBckp;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/controlador_interrupcao/controlador_interrupcao.v:21: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'pc\' generates 26 bits.\n : ... In instance controlador_interrupcao\n pcBckp <= ack ? salto ? pc : pc + 1 : pcBckp;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,308 | module | module controlador_interrupcao(
input clk,
input irq1,
input ack,
input clr,
input [5:0] opcode,
input [25:0] pc,
output intr,
output reg [31:0] cause,
output reg [31:0] pcBckp);
localparam JR = 6'b010010, JF = 6'b010101, J = 6'b111100, JTM = 6'b111101, JAL = 6'b111110;
wire salto = opcode == JR | opcode == JF | opcode == J | opcode == JTM | opcode == JAL;
initial begin
cause <= 32'b0;
end
always @ (posedge clk) begin
pcBckp <= ack ? salto ? pc : pc + 1 : pcBckp;
end
always @ (posedge clk) begin
if (clr)
cause <= 0;
else if (ack) begin
cause <= irq1 ? 2 : 1;
end else
cause <= cause;
end
assign intr = irq1;
endmodule | module controlador_interrupcao(
input clk,
input irq1,
input ack,
input clr,
input [5:0] opcode,
input [25:0] pc,
output intr,
output reg [31:0] cause,
output reg [31:0] pcBckp); |
localparam JR = 6'b010010, JF = 6'b010101, J = 6'b111100, JTM = 6'b111101, JAL = 6'b111110;
wire salto = opcode == JR | opcode == JF | opcode == J | opcode == JTM | opcode == JAL;
initial begin
cause <= 32'b0;
end
always @ (posedge clk) begin
pcBckp <= ack ? salto ? pc : pc + 1 : pcBckp;
end
always @ (posedge clk) begin
if (clr)
cause <= 0;
else if (ack) begin
cause <= irq1 ? 2 : 1;
end else
cause <= cause;
end
assign intr = irq1;
endmodule | 0 |
141,693 | data/full_repos/permissive/95938920/src/main/modules/delay_button/delay_button.v | 95,938,920 | delay_button.v | v | 44 | 44 | [] | [] | [] | [(1, 43)] | null | data/verilator_xmls/0e1255c3-4fb6-457c-8b85-0f7958fc18c2.xml | null | 312,310 | module | module delay_button(clk, in, out);
input clk;
input in;
output reg out;
reg [24:0] contador;
reg estado;
localparam ENABLED = 1'b0, WAITING = 1'b1;
initial begin
estado <= ENABLED;
contador <= {25 {1'b0}};
out <= 1'b1;
end
always @ (posedge clk) begin
if (estado == ENABLED) begin
if (!in)
out <= 1'b0;
end else begin
if (contador[4] == 1'b1)
out <= 1'b1;
end
end
always @ (posedge clk) begin
if (estado == ENABLED) begin
if (!in)
estado <= WAITING;
end else begin
if (contador[24] == 1'b1)
estado <= ENABLED;
end
end
always @ (posedge clk) begin
if (estado == WAITING)
contador <= contador + 1'b1;
else
contador <= {25 {1'b0}};
end
endmodule | module delay_button(clk, in, out); |
input clk;
input in;
output reg out;
reg [24:0] contador;
reg estado;
localparam ENABLED = 1'b0, WAITING = 1'b1;
initial begin
estado <= ENABLED;
contador <= {25 {1'b0}};
out <= 1'b1;
end
always @ (posedge clk) begin
if (estado == ENABLED) begin
if (!in)
out <= 1'b0;
end else begin
if (contador[4] == 1'b1)
out <= 1'b1;
end
end
always @ (posedge clk) begin
if (estado == ENABLED) begin
if (!in)
estado <= WAITING;
end else begin
if (contador[24] == 1'b1)
estado <= ENABLED;
end
end
always @ (posedge clk) begin
if (estado == WAITING)
contador <= contador + 1'b1;
else
contador <= {25 {1'b0}};
end
endmodule | 0 |
141,694 | data/full_repos/permissive/95938920/src/main/modules/display_quadruplo/display_quadruplo.v | 95,938,920 | display_quadruplo.v | v | 36 | 138 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/a2e02ab6-8810-4b1f-8e7a-b854998bf806.xml | null | 312,313 | module | module display_quadruplo(sinal, milhar, centena, dezena, unidade, saida_sinal, saida_milhar, saida_centena, saida_dezena, saida_unidade);
input sinal;
input [3:0] milhar, centena, dezena, unidade;
output reg saida_sinal;
output reg [6:0] saida_milhar, saida_centena, saida_dezena, saida_unidade;
function [6:0] display;
input [3:0] in;
case (in)
4'b0000: display = 7'b0000001;
4'b0001: display = 7'b1001111;
4'b0010: display = 7'b0010010;
4'b0011: display = 7'b0000110;
4'b0100: display = 7'b1001100;
4'b0101: display = 7'b0100100;
4'b0110: display = 7'b0100000;
4'b0111: display = 7'b0001111;
4'b1000: display = 7'b0000000;
4'b1001: display = 7'b0000100;
4'b1111: display = 7'b1111110;
default: display = 7'b1111111;
endcase
endfunction
always @ (*) begin
saida_sinal = sinal;
saida_milhar = display(milhar);
saida_centena = display(centena);
saida_dezena = display(dezena);
saida_unidade = display(unidade);
end
endmodule | module display_quadruplo(sinal, milhar, centena, dezena, unidade, saida_sinal, saida_milhar, saida_centena, saida_dezena, saida_unidade); |
input sinal;
input [3:0] milhar, centena, dezena, unidade;
output reg saida_sinal;
output reg [6:0] saida_milhar, saida_centena, saida_dezena, saida_unidade;
function [6:0] display;
input [3:0] in;
case (in)
4'b0000: display = 7'b0000001;
4'b0001: display = 7'b1001111;
4'b0010: display = 7'b0010010;
4'b0011: display = 7'b0000110;
4'b0100: display = 7'b1001100;
4'b0101: display = 7'b0100100;
4'b0110: display = 7'b0100000;
4'b0111: display = 7'b0001111;
4'b1000: display = 7'b0000000;
4'b1001: display = 7'b0000100;
4'b1111: display = 7'b1111110;
default: display = 7'b1111111;
endcase
endfunction
always @ (*) begin
saida_sinal = sinal;
saida_milhar = display(milhar);
saida_centena = display(centena);
saida_dezena = display(dezena);
saida_unidade = display(unidade);
end
endmodule | 0 |
141,695 | data/full_repos/permissive/95938920/src/main/modules/display_quadruplo/display_quadruplo.v | 95,938,920 | display_quadruplo.v | v | 36 | 138 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/a2e02ab6-8810-4b1f-8e7a-b854998bf806.xml | null | 312,313 | function | function [6:0] display;
input [3:0] in;
case (in)
4'b0000: display = 7'b0000001;
4'b0001: display = 7'b1001111;
4'b0010: display = 7'b0010010;
4'b0011: display = 7'b0000110;
4'b0100: display = 7'b1001100;
4'b0101: display = 7'b0100100;
4'b0110: display = 7'b0100000;
4'b0111: display = 7'b0001111;
4'b1000: display = 7'b0000000;
4'b1001: display = 7'b0000100;
4'b1111: display = 7'b1111110;
default: display = 7'b1111111;
endcase
endfunction | function [6:0] display; |
input [3:0] in;
case (in)
4'b0000: display = 7'b0000001;
4'b0001: display = 7'b1001111;
4'b0010: display = 7'b0010010;
4'b0011: display = 7'b0000110;
4'b0100: display = 7'b1001100;
4'b0101: display = 7'b0100100;
4'b0110: display = 7'b0100000;
4'b0111: display = 7'b0001111;
4'b1000: display = 7'b0000000;
4'b1001: display = 7'b0000100;
4'b1111: display = 7'b1111110;
default: display = 7'b1111111;
endcase
endfunction | 0 |
141,696 | data/full_repos/permissive/95938920/src/main/modules/extensor_de_bit/extensor_de_bit.v | 95,938,920 | extensor_de_bit.v | v | 14 | 68 | [] | [] | [] | [(1, 14)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/extensor_de_bit/extensor_de_bit.v:10: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'entrada\' generates 16 bits.\n : ... In instance extensor_de_bit\n dadoExtendido = entrada + 32\'b11111111111111110000000000000000;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/extensor_de_bit/extensor_de_bit.v:12: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'entrada\' generates 16 bits.\n : ... In instance extensor_de_bit\n dadoExtendido = entrada + 32\'b0;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,314 | module | module extensor_de_bit(entrada, dadoExtendido);
input [15:0] entrada;
output reg [31:0] dadoExtendido;
always @ (entrada) begin
if(entrada[15] == 1'b1)
dadoExtendido = entrada + 32'b11111111111111110000000000000000;
else
dadoExtendido = entrada + 32'b0;
end
endmodule | module extensor_de_bit(entrada, dadoExtendido); |
input [15:0] entrada;
output reg [31:0] dadoExtendido;
always @ (entrada) begin
if(entrada[15] == 1'b1)
dadoExtendido = entrada + 32'b11111111111111110000000000000000;
else
dadoExtendido = entrada + 32'b0;
end
endmodule | 0 |
141,697 | data/full_repos/permissive/95938920/src/main/modules/lcdlab3/lcdlab3.v | 95,938,920 | lcdlab3.v | v | 38 | 97 | [] | [] | [] | [(1, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/95938920/src/main/modules/lcdlab3/lcdlab3.v:18: Cannot find file containing module: 'Reset_Delay'\nReset_Delay r0(.iCLK(CLOCK_50), .oRESET(DLY_RST));\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95938920/src/main/modules/lcdlab3,data/full_repos/permissive/95938920/Reset_Delay\n data/full_repos/permissive/95938920/src/main/modules/lcdlab3,data/full_repos/permissive/95938920/Reset_Delay.v\n data/full_repos/permissive/95938920/src/main/modules/lcdlab3,data/full_repos/permissive/95938920/Reset_Delay.sv\n Reset_Delay\n Reset_Delay.v\n Reset_Delay.sv\n obj_dir/Reset_Delay\n obj_dir/Reset_Delay.v\n obj_dir/Reset_Delay.sv\n%Error: data/full_repos/permissive/95938920/src/main/modules/lcdlab3/lcdlab3.v:23: Cannot find file containing module: 'LCD_Display'\nLCD_Display u1(\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,315 | module | module lcdlab3(CLOCK_50, clk, wlcd, PC, OPCODE, DATA, LCD_ON, LCD_RW, LCD_EN, LCD_RS, LCD_DATA);
input CLOCK_50;
input clk;
input wlcd;
input [31:0] DATA;
input [25:0] PC;
input [5:0] OPCODE;
output LCD_ON;
output LCD_RW;
output LCD_EN;
output LCD_RS;
output [7:0] LCD_DATA;
wire DLY_RST;
Reset_Delay r0(.iCLK(CLOCK_50), .oRESET(DLY_RST));
assign LCD_ON = 1'b1;
LCD_Display u1(
.iCLK_50MHZ(CLOCK_50),
.clk(clk),
.wlcd(wlcd),
.iRST_N(DLY_RST),
.PC(PC),
.OPCODE(OPCODE),
.DATA(DATA),
.LCD_RS(LCD_RS),
.LCD_E(LCD_EN),
.LCD_RW(LCD_RW),
.DATA_BUS(LCD_DATA));
endmodule | module lcdlab3(CLOCK_50, clk, wlcd, PC, OPCODE, DATA, LCD_ON, LCD_RW, LCD_EN, LCD_RS, LCD_DATA); |
input CLOCK_50;
input clk;
input wlcd;
input [31:0] DATA;
input [25:0] PC;
input [5:0] OPCODE;
output LCD_ON;
output LCD_RW;
output LCD_EN;
output LCD_RS;
output [7:0] LCD_DATA;
wire DLY_RST;
Reset_Delay r0(.iCLK(CLOCK_50), .oRESET(DLY_RST));
assign LCD_ON = 1'b1;
LCD_Display u1(
.iCLK_50MHZ(CLOCK_50),
.clk(clk),
.wlcd(wlcd),
.iRST_N(DLY_RST),
.PC(PC),
.OPCODE(OPCODE),
.DATA(DATA),
.LCD_RS(LCD_RS),
.LCD_E(LCD_EN),
.LCD_RW(LCD_RW),
.DATA_BUS(LCD_DATA));
endmodule | 0 |
141,698 | data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v | 95,938,920 | LCD_Display.v | v | 1,500 | 107 | [] | [] | [] | [(40, 264), (266, 1499)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:423: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LCD_Display.u1\n aux = ~(STATE_LCD_CURRENT) + 8\'b00000001;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:461: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'PC\' generates 26 bits.\n : ... In instance LCD_Display.u1\n aux = ~(PC) + 16\'b0000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n : ... In instance LCD_Display.u1\n aux = ~(PC) + 16\'b0000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1392: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance LCD_Display.u1\n STATE_LCD_CHANGE <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1399: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SEL generates 8 bits.\n : ... In instance LCD_Display.u1\n STATE_LCD_CHANGE <= OPCODE == OPCODE_LCD ? DATA[7:0] : STATE_LCD_CHANGE;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MAIN_MENU\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_DEL\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_REN\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_REN_NOME\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_NOME\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_QUIT\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_FIRST_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_SECOND_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_THIRD_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_FOURTH_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM_LOAD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM_DEL\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE_N_PREEMPTIVO\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE_BLOCKED\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_HD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_IMEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_DMEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_START_OS\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'PROG_INSERT\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Error: Exiting due to 27 warning(s)\n' | 312,316 | module | module LCD_Display(iCLK_50MHZ, clk, wlcd, iRST_N, PC, OPCODE, DATA, LCD_RS, LCD_E, LCD_RW, DATA_BUS);
input iCLK_50MHZ, iRST_N;
input clk;
input wlcd;
output LCD_RS, LCD_E, LCD_RW;
inout [7:0] DATA_BUS;
input [25:0] PC;
input [5:0] OPCODE;
input [31:0] DATA;
parameter
HOLD = 4'h0,
FUNC_SET = 4'h1,
DISPLAY_ON = 4'h2,
MODE_SET = 4'h3,
Print_String = 4'h4,
LINE2 = 4'h5,
RETURN_HOME = 4'h6,
DROP_LCD_E = 4'h7,
RESET1 = 4'h8,
RESET2 = 4'h9,
RESET3 = 4'ha,
DISPLAY_OFF = 4'hb,
DISPLAY_CLEAR = 4'hc;
reg [3:0] state, next_command;
reg [7:0] DATA_BUS_VALUE;
wire [7:0] Next_Char;
reg [19:0] CLK_COUNT_400HZ;
reg [4:0] CHAR_COUNT;
reg CLK_400HZ, LCD_RW_INT, LCD_E, LCD_RS;
assign DATA_BUS = (LCD_RW_INT? 8'bZZZZZZZZ: DATA_BUS_VALUE);
LCD_display_string u1(
.clk(clk),
.wlcd(wlcd),
.index(CHAR_COUNT),
.PC(PC),
.OPCODE(OPCODE),
.DATA(DATA),
.out(Next_Char));
assign LCD_RW = LCD_RW_INT;
always @(posedge iCLK_50MHZ or negedge iRST_N)
if (!iRST_N)
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= 1'b0;
end
else if (CLK_COUNT_400HZ < 20'h0F424)
begin
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1'b1;
end
else
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= ~CLK_400HZ;
end
always @(posedge CLK_400HZ or negedge iRST_N)
if (!iRST_N)
begin
state <= RESET1;
end
else
case (state)
RESET1:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET2;
CHAR_COUNT <= 5'b00000;
end
RESET2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET3;
end
RESET3:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= FUNC_SET;
end
FUNC_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= DISPLAY_OFF;
end
DISPLAY_OFF:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h08;
state <= DROP_LCD_E;
next_command <= DISPLAY_CLEAR;
end
DISPLAY_CLEAR:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h01;
state <= DROP_LCD_E;
next_command <= DISPLAY_ON;
end
DISPLAY_ON:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h0C;
state <= DROP_LCD_E;
next_command <= MODE_SET;
end
MODE_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h06;
state <= DROP_LCD_E;
next_command <= Print_String;
end
Print_String:
begin
state <= DROP_LCD_E;
LCD_E <= 1'b1;
LCD_RS <= 1'b1;
LCD_RW_INT <= 1'b0;
if (Next_Char[7:4] != 4'h0)
DATA_BUS_VALUE <= Next_Char;
else if (Next_Char[3:0] >9)
DATA_BUS_VALUE <= {4'h4,Next_Char[3:0]-4'h9};
else
DATA_BUS_VALUE <= {4'h3,Next_Char[3:0]};
if ((CHAR_COUNT < 31) && (Next_Char != 8'hFE))
CHAR_COUNT <= CHAR_COUNT + 1'b1;
else
CHAR_COUNT <= 5'b00000;
if (CHAR_COUNT == 15)
next_command <= LINE2;
else if ((CHAR_COUNT == 31) || (Next_Char == 8'hFE))
next_command <= RETURN_HOME;
else
next_command <= Print_String;
end
LINE2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'hC0;
state <= DROP_LCD_E;
next_command <= Print_String;
end
RETURN_HOME:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h80;
state <= DROP_LCD_E;
next_command <= Print_String;
end
DROP_LCD_E:
begin
LCD_E <= 1'b0;
state <= HOLD;
end
HOLD:
begin
state <= next_command;
end
endcase
endmodule | module LCD_Display(iCLK_50MHZ, clk, wlcd, iRST_N, PC, OPCODE, DATA, LCD_RS, LCD_E, LCD_RW, DATA_BUS); |
input iCLK_50MHZ, iRST_N;
input clk;
input wlcd;
output LCD_RS, LCD_E, LCD_RW;
inout [7:0] DATA_BUS;
input [25:0] PC;
input [5:0] OPCODE;
input [31:0] DATA;
parameter
HOLD = 4'h0,
FUNC_SET = 4'h1,
DISPLAY_ON = 4'h2,
MODE_SET = 4'h3,
Print_String = 4'h4,
LINE2 = 4'h5,
RETURN_HOME = 4'h6,
DROP_LCD_E = 4'h7,
RESET1 = 4'h8,
RESET2 = 4'h9,
RESET3 = 4'ha,
DISPLAY_OFF = 4'hb,
DISPLAY_CLEAR = 4'hc;
reg [3:0] state, next_command;
reg [7:0] DATA_BUS_VALUE;
wire [7:0] Next_Char;
reg [19:0] CLK_COUNT_400HZ;
reg [4:0] CHAR_COUNT;
reg CLK_400HZ, LCD_RW_INT, LCD_E, LCD_RS;
assign DATA_BUS = (LCD_RW_INT? 8'bZZZZZZZZ: DATA_BUS_VALUE);
LCD_display_string u1(
.clk(clk),
.wlcd(wlcd),
.index(CHAR_COUNT),
.PC(PC),
.OPCODE(OPCODE),
.DATA(DATA),
.out(Next_Char));
assign LCD_RW = LCD_RW_INT;
always @(posedge iCLK_50MHZ or negedge iRST_N)
if (!iRST_N)
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= 1'b0;
end
else if (CLK_COUNT_400HZ < 20'h0F424)
begin
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1'b1;
end
else
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= ~CLK_400HZ;
end
always @(posedge CLK_400HZ or negedge iRST_N)
if (!iRST_N)
begin
state <= RESET1;
end
else
case (state)
RESET1:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET2;
CHAR_COUNT <= 5'b00000;
end
RESET2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET3;
end
RESET3:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= FUNC_SET;
end
FUNC_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= DISPLAY_OFF;
end
DISPLAY_OFF:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h08;
state <= DROP_LCD_E;
next_command <= DISPLAY_CLEAR;
end
DISPLAY_CLEAR:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h01;
state <= DROP_LCD_E;
next_command <= DISPLAY_ON;
end
DISPLAY_ON:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h0C;
state <= DROP_LCD_E;
next_command <= MODE_SET;
end
MODE_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h06;
state <= DROP_LCD_E;
next_command <= Print_String;
end
Print_String:
begin
state <= DROP_LCD_E;
LCD_E <= 1'b1;
LCD_RS <= 1'b1;
LCD_RW_INT <= 1'b0;
if (Next_Char[7:4] != 4'h0)
DATA_BUS_VALUE <= Next_Char;
else if (Next_Char[3:0] >9)
DATA_BUS_VALUE <= {4'h4,Next_Char[3:0]-4'h9};
else
DATA_BUS_VALUE <= {4'h3,Next_Char[3:0]};
if ((CHAR_COUNT < 31) && (Next_Char != 8'hFE))
CHAR_COUNT <= CHAR_COUNT + 1'b1;
else
CHAR_COUNT <= 5'b00000;
if (CHAR_COUNT == 15)
next_command <= LINE2;
else if ((CHAR_COUNT == 31) || (Next_Char == 8'hFE))
next_command <= RETURN_HOME;
else
next_command <= Print_String;
end
LINE2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'hC0;
state <= DROP_LCD_E;
next_command <= Print_String;
end
RETURN_HOME:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h80;
state <= DROP_LCD_E;
next_command <= Print_String;
end
DROP_LCD_E:
begin
LCD_E <= 1'b0;
state <= HOLD;
end
HOLD:
begin
state <= next_command;
end
endcase
endmodule | 0 |
141,699 | data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v | 95,938,920 | LCD_Display.v | v | 1,500 | 107 | [] | [] | [] | [(40, 264), (266, 1499)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:423: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LCD_Display.u1\n aux = ~(STATE_LCD_CURRENT) + 8\'b00000001;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:461: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'PC\' generates 26 bits.\n : ... In instance LCD_Display.u1\n aux = ~(PC) + 16\'b0000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n : ... In instance LCD_Display.u1\n aux = ~(PC) + 16\'b0000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1392: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance LCD_Display.u1\n STATE_LCD_CHANGE <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1399: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SEL generates 8 bits.\n : ... In instance LCD_Display.u1\n STATE_LCD_CHANGE <= OPCODE == OPCODE_LCD ? DATA[7:0] : STATE_LCD_CHANGE;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MAIN_MENU\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_DEL\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_REN\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_REN_NOME\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_NOME\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_QUIT\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_FIRST_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_SECOND_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_THIRD_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_FOURTH_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM_LOAD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM_DEL\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE_N_PREEMPTIVO\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE_BLOCKED\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_HD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_IMEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_DMEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_START_OS\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'PROG_INSERT\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Error: Exiting due to 27 warning(s)\n' | 312,316 | module | module LCD_display_string(clk, wlcd, index, PC, OPCODE, DATA, out);
input clk, wlcd;
input [4:0] index;
input [25:0] PC;
input [5:0] OPCODE;
input [31:0] DATA;
output reg [7:0] out;
localparam DATA_WIDTH = 32;
localparam CHAR_WIDTH = 8;
localparam LCD_WIDTH = 32;
localparam [CHAR_WIDTH-1:0] KERNEL_MAIN_MENU = 8'd0;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD = 8'd1;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_DEL = 8'd2;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN = 8'd3;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN_NOME = 8'd4;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_NOME = 8'd5;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_QUIT = 8'd6;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FIRST_PART = 8'd7;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_SECOND_PART = 8'd8;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_THIRD_PART = 8'd9;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FOURTH_PART = 8'd10;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_MEM = 8'd11;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_LOAD = 8'd12;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_DEL = 8'd13;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_EXE = 8'd14;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_N_PREEMPTIVO = 8'd15;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_BLOCKED = 8'd16;
localparam [CHAR_WIDTH-1:0] BIOS_CHECK_HD = 8'd20;
localparam [CHAR_WIDTH-1:0] BIOS_CHECK_IMEM = 8'd21;
localparam [CHAR_WIDTH-1:0] BIOS_CHECK_DMEM = 8'd22;
localparam [CHAR_WIDTH-1:0] BIOS_START_OS = 8'd23;
localparam [CHAR_WIDTH-1:0] PROG_INSERT = 8'd30;
localparam CHAR_a = 8'h61, CHAR_b = 8'h62, CHAR_c = 8'h63, CHAR_d = 8'h64;
localparam CHAR_e = 8'h65, CHAR_f = 8'h66, CHAR_g = 8'h67, CHAR_h = 8'h68;
localparam CHAR_i = 8'h69, CHAR_j = 8'h6A, CHAR_k = 8'h6B, CHAR_l = 8'h6C;
localparam CHAR_m = 8'h6D, CHAR_n = 8'h6E, CHAR_o = 8'h6F, CHAR_p = 8'h70;
localparam CHAR_q = 8'h71, CHAR_r = 8'h72, CHAR_s = 8'h73, CHAR_t = 8'h74;
localparam CHAR_u = 8'h75, CHAR_v = 8'h76, CHAR_w = 8'h77, CHAR_x = 8'h78;
localparam CHAR_y = 8'h79, CHAR_z = 8'h7A;
localparam CHAR_A = 8'h41, CHAR_B = 8'h42, CHAR_C = 8'h43, CHAR_D = 8'h44;
localparam CHAR_E = 8'h45, CHAR_F = 8'h46, CHAR_G = 8'h47, CHAR_H = 8'h48;
localparam CHAR_I = 8'h49, CHAR_J = 8'h4A, CHAR_K = 8'h4B, CHAR_L = 8'h4C;
localparam CHAR_M = 8'h4D, CHAR_N = 8'h4E, CHAR_O = 8'h4F, CHAR_P = 8'h50;
localparam CHAR_Q = 8'h51, CHAR_R = 8'h52, CHAR_S = 8'h53, CHAR_T = 8'h54;
localparam CHAR_U = 8'h55, CHAR_V = 8'h56, CHAR_W = 8'h57, CHAR_X = 8'h58;
localparam CHAR_Y = 8'h59, CHAR_Z = 8'h5A;
localparam CHAR_0 = 8'h30, CHAR_1 = 8'h31, CHAR_2 = 8'h32, CHAR_3 = 8'h33;
localparam CHAR_4 = 8'h34, CHAR_5 = 8'h35, CHAR_6 = 8'h36, CHAR_7 = 8'h37;
localparam CHAR_8 = 8'h38, CHAR_9 = 8'h39;
localparam CHAR_SPACE = 8'h20, CHAR_LEFT_BRACKET = 8'h5B, CHAR_RIGHT_BRACKET = 8'h5D;
localparam CHAR_HYPHEN = 8'h2D, CHAR_HASHTAG = 8'h23, CHAR_AT = 8'h40, CHAR_PLUS = 8'h2B;
localparam CHAR_COLLON = 8'h3A, CHAR_DOT = 8'h2E;
localparam OPCODE_LCD = 6'b011110;
localparam OPCODE_LCD_PGMS = 6'b011111;
localparam OPCODE_LCD_CURR = 6'b100000;
wire [CHAR_WIDTH-1:0] KERNEL_MAIN_MENU_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_DEL_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN_NOME_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_NOME_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_QUIT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FIRST_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_SECOND_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_THIRD_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FOURTH_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_LOAD_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_DEL_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_N_PREEMPTIVO_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_BLOCKED_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_CHECK_HD_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_CHECK_IMEM_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_CHECK_DMEM_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_START_OS_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_DOT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_DOT_DOT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_DOT_DOT_DOT_STRING [0:LCD_WIDTH-1];
reg [CHAR_WIDTH:0] STATE_LCD_CHANGE;
reg [31:0] STATE_LCD_PROGRAMAS;
reg [31:0] STATE_LCD_CURRENT;
reg [7:0] PC_MILHAR;
reg [7:0] PC_CENTENA;
reg [7:0] PC_DEZENA;
reg [7:0] PC_UNIDADE;
reg [7:0] CURRENT_DEZENA;
reg [7:0] CURRENT_UNIDADE;
reg [3:0] milhar;
reg [3:0] centena;
reg [3:0] dezena;
reg [3:0] unidade;
reg [3:0] dezena_c;
reg [3:0] unidade_c;
reg [31:0] aux;
integer i;
function [7:0] display;
input [3:0] in;
case (in)
4'b0000: display = CHAR_0;
4'b0001: display = CHAR_1;
4'b0010: display = CHAR_2;
4'b0011: display = CHAR_3;
4'b0100: display = CHAR_4;
4'b0101: display = CHAR_5;
4'b0110: display = CHAR_6;
4'b0111: display = CHAR_7;
4'b1000: display = CHAR_8;
4'b1001: display = CHAR_9;
default: display = CHAR_HYPHEN;
endcase
endfunction
always @ (PC or STATE_LCD_CURRENT) begin
aux = 32'b0;
dezena_c = 4'b0000;
unidade_c = 4'b0000;
if(STATE_LCD_CURRENT[15] == 0) begin
for(i = 15; i >=0; i = i-1) begin
if(dezena_c >= 5) dezena_c = dezena_c + 4'd3;
if(unidade_c >= 5) unidade_c = unidade_c + 4'd3;
dezena_c = dezena_c << 1;
dezena_c[0] = unidade_c[3];
unidade_c = unidade_c << 1;
unidade_c[0] = STATE_LCD_CURRENT[i];
end
end
else begin
aux = ~(STATE_LCD_CURRENT) + 8'b00000001;
for(i = 15; i >=0; i = i-1) begin
if(dezena_c >= 5) dezena_c = dezena_c + 4'd3;
if(unidade_c >= 5) unidade_c = unidade_c + 4'd3;
dezena_c = dezena_c << 1;
dezena_c[0] = unidade_c[3];
unidade_c = unidade_c << 1;
unidade_c[0] = aux[i];
end
end
CURRENT_DEZENA <= display(dezena_c);
CURRENT_UNIDADE <= display(unidade_c);
end
always @ (PC) begin
aux = 32'b0;
milhar = 4'b0000;
centena = 4'b0000;
dezena = 4'b0000;
unidade = 4'b0000;
if(PC[25] == 0) begin
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = PC[i];
end
end
else begin
aux = ~(PC) + 16'b0000000000000001;
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = aux[i];
end
end
PC_MILHAR <= display(milhar);
PC_CENTENA <= display(centena);
PC_DEZENA <= display(dezena);
PC_UNIDADE <= display(unidade);
end
assign KERNEL_MAIN_MENU_STRING[5'd0] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd1] = CHAR_A;
assign KERNEL_MAIN_MENU_STRING[5'd2] = CHAR_I;
assign KERNEL_MAIN_MENU_STRING[5'd3] = CHAR_N;
assign KERNEL_MAIN_MENU_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd6] = CHAR_1;
assign KERNEL_MAIN_MENU_STRING[5'd7] = CHAR_H;
assign KERNEL_MAIN_MENU_STRING[5'd8] = CHAR_D;
assign KERNEL_MAIN_MENU_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd10] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd12] = CHAR_3;
assign KERNEL_MAIN_MENU_STRING[5'd13] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd14] = CHAR_X;
assign KERNEL_MAIN_MENU_STRING[5'd15] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd16] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd17] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd18] = CHAR_N;
assign KERNEL_MAIN_MENU_STRING[5'd19] = CHAR_U;
assign KERNEL_MAIN_MENU_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd22] = CHAR_2;
assign KERNEL_MAIN_MENU_STRING[5'd23] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd24] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd25] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd28] = CHAR_4;
assign KERNEL_MAIN_MENU_STRING[5'd29] = CHAR_C;
assign KERNEL_MAIN_MENU_STRING[5'd30] = CHAR_L;
assign KERNEL_MAIN_MENU_STRING[5'd31] = CHAR_R;
assign KERNEL_MENU_HD_STRING[5'd0] = CHAR_M;
assign KERNEL_MENU_HD_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_HD_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_HD_STRING[5'd3] = CHAR_U;
assign KERNEL_MENU_HD_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd6] = CHAR_1;
assign KERNEL_MENU_HD_STRING[5'd7] = CHAR_A;
assign KERNEL_MENU_HD_STRING[5'd8] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd9] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd10] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd12] = CHAR_3;
assign KERNEL_MENU_HD_STRING[5'd13] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd14] = CHAR_E;
assign KERNEL_MENU_HD_STRING[5'd15] = CHAR_L;
assign KERNEL_MENU_HD_STRING[5'd16] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd17] = CHAR_H;
assign KERNEL_MENU_HD_STRING[5'd18] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd19] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd22] = CHAR_2;
assign KERNEL_MENU_HD_STRING[5'd23] = CHAR_R;
assign KERNEL_MENU_HD_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_HD_STRING[5'd25] = CHAR_N;
assign KERNEL_MENU_HD_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd28] = CHAR_4;
assign KERNEL_MENU_HD_STRING[5'd29] = CHAR_B;
assign KERNEL_MENU_HD_STRING[5'd30] = CHAR_C;
assign KERNEL_MENU_HD_STRING[5'd31] = CHAR_K;
assign KERNEL_MENU_HD_DEL_STRING[5'd0] = CHAR_P;
assign KERNEL_MENU_HD_DEL_STRING[5'd1] = CHAR_U;
assign KERNEL_MENU_HD_DEL_STRING[5'd2] = CHAR_R;
assign KERNEL_MENU_HD_DEL_STRING[5'd3] = CHAR_G;
assign KERNEL_MENU_HD_DEL_STRING[5'd4] = CHAR_E;
assign KERNEL_MENU_HD_DEL_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_DEL_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_DEL_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_HD_DEL_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_HD_DEL_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd0] = CHAR_R;
assign KERNEL_MENU_HD_REN_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_HD_REN_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_HD_REN_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_REN_STRING[5'd4] = CHAR_M;
assign KERNEL_MENU_HD_REN_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_REN_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_REN_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_HD_REN_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_HD_REN_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd0] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd4] = CHAR_M;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd16] = CHAR_I;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd17] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd18] = CHAR_S;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd19] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd20] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd21] = CHAR_T;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd22] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd23] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd25] = CHAR_W;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd27] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd28] = CHAR_A;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd29] = CHAR_M;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd30] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd21] = CHAR_N;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd22] = CHAR_A;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd23] = CHAR_M;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd25] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd26] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd28] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd19] = CHAR_S;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd20] = CHAR_S;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd22] = CHAR_0;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd24] = CHAR_T;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd25] = CHAR_O;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd27] = CHAR_Q;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd28] = CHAR_U;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd29] = CHAR_I;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd30] = CHAR_T;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd16] = CHAR_F;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd17] = CHAR_I;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd18] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd19] = CHAR_S;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd20] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd22] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd23] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd24] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd25] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd26] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd16] = CHAR_S;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd17] = CHAR_E;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd18] = CHAR_C;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd19] = CHAR_O;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd20] = CHAR_N;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd21] = CHAR_D;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd22] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd23] = CHAR_P;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd24] = CHAR_A;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd25] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd26] = CHAR_T;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd29] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd16] = CHAR_T;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd17] = CHAR_H;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd18] = CHAR_I;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd19] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd20] = CHAR_D;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd22] = CHAR_P;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd23] = CHAR_A;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd24] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd25] = CHAR_T;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd26] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd16] = CHAR_F;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd17] = CHAR_O;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd18] = CHAR_U;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd19] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd20] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd21] = CHAR_H;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd22] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd23] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd24] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd25] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd26] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd29] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd0] = CHAR_M;
assign KERNEL_MENU_MEM_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_MEM_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_MEM_STRING[5'd3] = CHAR_U;
assign KERNEL_MENU_MEM_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd6] = CHAR_1;
assign KERNEL_MENU_MEM_STRING[5'd7] = CHAR_L;
assign KERNEL_MENU_MEM_STRING[5'd8] = CHAR_O;
assign KERNEL_MENU_MEM_STRING[5'd9] = CHAR_A;
assign KERNEL_MENU_MEM_STRING[5'd10] = CHAR_D;
assign KERNEL_MENU_MEM_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd12] = CHAR_3;
assign KERNEL_MENU_MEM_STRING[5'd13] = CHAR_B;
assign KERNEL_MENU_MEM_STRING[5'd14] = CHAR_C;
assign KERNEL_MENU_MEM_STRING[5'd15] = CHAR_K;
assign KERNEL_MENU_MEM_STRING[5'd16] = CHAR_M;
assign KERNEL_MENU_MEM_STRING[5'd17] = CHAR_E;
assign KERNEL_MENU_MEM_STRING[5'd18] = CHAR_M;
assign KERNEL_MENU_MEM_STRING[5'd19] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd22] = CHAR_2;
assign KERNEL_MENU_MEM_STRING[5'd23] = CHAR_D;
assign KERNEL_MENU_MEM_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_MEM_STRING[5'd25] = CHAR_L;
assign KERNEL_MENU_MEM_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd28] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd0] = CHAR_L;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd1] = CHAR_O;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd2] = CHAR_A;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd3] = CHAR_D;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd0] = CHAR_D;
assign KERNEL_MENU_MEM_DEL_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_MEM_DEL_STRING[5'd2] = CHAR_L;
assign KERNEL_MENU_MEM_DEL_STRING[5'd3] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_MEM_DEL_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_MEM_DEL_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_MEM_DEL_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_MEM_DEL_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd0] = CHAR_M;
assign KERNEL_MENU_EXE_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_EXE_STRING[5'd3] = CHAR_U;
assign KERNEL_MENU_EXE_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd6] = CHAR_1;
assign KERNEL_MENU_EXE_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_EXE_STRING[5'd9] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd10] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd12] = CHAR_3;
assign KERNEL_MENU_EXE_STRING[5'd13] = CHAR_B;
assign KERNEL_MENU_EXE_STRING[5'd14] = CHAR_L;
assign KERNEL_MENU_EXE_STRING[5'd15] = CHAR_K;
assign KERNEL_MENU_EXE_STRING[5'd16] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd17] = CHAR_X;
assign KERNEL_MENU_EXE_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd19] = CHAR_C;
assign KERNEL_MENU_EXE_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd22] = CHAR_2;
assign KERNEL_MENU_EXE_STRING[5'd23] = CHAR_N;
assign KERNEL_MENU_EXE_STRING[5'd24] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd25] = CHAR_R;
assign KERNEL_MENU_EXE_STRING[5'd26] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd28] = CHAR_4;
assign KERNEL_MENU_EXE_STRING[5'd29] = CHAR_B;
assign KERNEL_MENU_EXE_STRING[5'd30] = CHAR_C;
assign KERNEL_MENU_EXE_STRING[5'd31] = CHAR_K;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd0] = CHAR_P;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd2] = CHAR_O;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd3] = CHAR_G;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd16] = CHAR_E;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd17] = CHAR_X;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd19] = CHAR_C;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd0] = CHAR_B;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd1] = CHAR_L;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd2] = CHAR_C;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd3] = CHAR_K;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd16] = CHAR_E;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd17] = CHAR_X;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd19] = CHAR_C;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd0] = CHAR_B;
assign BIOS_CHECK_HD_STRING[5'd1] = CHAR_I;
assign BIOS_CHECK_HD_STRING[5'd2] = CHAR_O;
assign BIOS_CHECK_HD_STRING[5'd3] = CHAR_S;
assign BIOS_CHECK_HD_STRING[5'd4] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd5] = CHAR_C;
assign BIOS_CHECK_HD_STRING[5'd6] = CHAR_H;
assign BIOS_CHECK_HD_STRING[5'd7] = CHAR_E;
assign BIOS_CHECK_HD_STRING[5'd8] = CHAR_C;
assign BIOS_CHECK_HD_STRING[5'd9] = CHAR_K;
assign BIOS_CHECK_HD_STRING[5'd10] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd11] = CHAR_H;
assign BIOS_CHECK_HD_STRING[5'd12] = CHAR_D;
assign BIOS_CHECK_HD_STRING[5'd13] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd14] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd15] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd16] = CHAR_S;
assign BIOS_CHECK_HD_STRING[5'd17] = CHAR_I;
assign BIOS_CHECK_HD_STRING[5'd18] = CHAR_Z;
assign BIOS_CHECK_HD_STRING[5'd19] = CHAR_E;
assign BIOS_CHECK_HD_STRING[5'd20] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd21] = CHAR_H;
assign BIOS_CHECK_HD_STRING[5'd22] = CHAR_D;
assign BIOS_CHECK_HD_STRING[5'd23] = CHAR_COLLON;
assign BIOS_CHECK_HD_STRING[5'd24] = CHAR_4;
assign BIOS_CHECK_HD_STRING[5'd25] = CHAR_0;
assign BIOS_CHECK_HD_STRING[5'd26] = CHAR_9;
assign BIOS_CHECK_HD_STRING[5'd27] = CHAR_6;
assign BIOS_CHECK_HD_STRING[5'd28] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd29] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd30] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd31] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd0] = CHAR_B;
assign BIOS_CHECK_IMEM_STRING[5'd1] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd2] = CHAR_O;
assign BIOS_CHECK_IMEM_STRING[5'd3] = CHAR_S;
assign BIOS_CHECK_IMEM_STRING[5'd4] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd5] = CHAR_C;
assign BIOS_CHECK_IMEM_STRING[5'd6] = CHAR_H;
assign BIOS_CHECK_IMEM_STRING[5'd7] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd8] = CHAR_C;
assign BIOS_CHECK_IMEM_STRING[5'd9] = CHAR_K;
assign BIOS_CHECK_IMEM_STRING[5'd10] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd11] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd12] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd13] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd14] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd15] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd16] = CHAR_S;
assign BIOS_CHECK_IMEM_STRING[5'd17] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd18] = CHAR_Z;
assign BIOS_CHECK_IMEM_STRING[5'd19] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd20] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd21] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd22] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd23] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd24] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd25] = CHAR_COLLON;
assign BIOS_CHECK_IMEM_STRING[5'd26] = CHAR_4;
assign BIOS_CHECK_IMEM_STRING[5'd27] = CHAR_0;
assign BIOS_CHECK_IMEM_STRING[5'd28] = CHAR_9;
assign BIOS_CHECK_IMEM_STRING[5'd29] = CHAR_6;
assign BIOS_CHECK_IMEM_STRING[5'd30] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd31] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd0] = CHAR_B;
assign BIOS_CHECK_DMEM_STRING[5'd1] = CHAR_I;
assign BIOS_CHECK_DMEM_STRING[5'd2] = CHAR_O;
assign BIOS_CHECK_DMEM_STRING[5'd3] = CHAR_S;
assign BIOS_CHECK_DMEM_STRING[5'd4] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd5] = CHAR_C;
assign BIOS_CHECK_DMEM_STRING[5'd6] = CHAR_H;
assign BIOS_CHECK_DMEM_STRING[5'd7] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd8] = CHAR_C;
assign BIOS_CHECK_DMEM_STRING[5'd9] = CHAR_K;
assign BIOS_CHECK_DMEM_STRING[5'd10] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd11] = CHAR_D;
assign BIOS_CHECK_DMEM_STRING[5'd12] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd13] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd14] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd15] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd16] = CHAR_S;
assign BIOS_CHECK_DMEM_STRING[5'd17] = CHAR_I;
assign BIOS_CHECK_DMEM_STRING[5'd18] = CHAR_Z;
assign BIOS_CHECK_DMEM_STRING[5'd19] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd20] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd21] = CHAR_D;
assign BIOS_CHECK_DMEM_STRING[5'd22] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd23] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd24] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd25] = CHAR_COLLON;
assign BIOS_CHECK_DMEM_STRING[5'd26] = CHAR_2;
assign BIOS_CHECK_DMEM_STRING[5'd27] = CHAR_0;
assign BIOS_CHECK_DMEM_STRING[5'd28] = CHAR_4;
assign BIOS_CHECK_DMEM_STRING[5'd29] = CHAR_8;
assign BIOS_CHECK_DMEM_STRING[5'd30] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd31] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd0] = CHAR_P;
assign BIOS_START_OS_STRING[5'd1] = CHAR_R;
assign BIOS_START_OS_STRING[5'd2] = CHAR_E;
assign BIOS_START_OS_STRING[5'd3] = CHAR_S;
assign BIOS_START_OS_STRING[5'd4] = CHAR_S;
assign BIOS_START_OS_STRING[5'd5] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd6] = CHAR_I;
assign BIOS_START_OS_STRING[5'd7] = CHAR_N;
assign BIOS_START_OS_STRING[5'd8] = CHAR_S;
assign BIOS_START_OS_STRING[5'd9] = CHAR_E;
assign BIOS_START_OS_STRING[5'd10] = CHAR_R;
assign BIOS_START_OS_STRING[5'd11] = CHAR_T;
assign BIOS_START_OS_STRING[5'd12] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd13] = CHAR_T;
assign BIOS_START_OS_STRING[5'd14] = CHAR_O;
assign BIOS_START_OS_STRING[5'd15] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd16] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd17] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd18] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd19] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd20] = CHAR_S;
assign BIOS_START_OS_STRING[5'd21] = CHAR_T;
assign BIOS_START_OS_STRING[5'd22] = CHAR_A;
assign BIOS_START_OS_STRING[5'd23] = CHAR_R;
assign BIOS_START_OS_STRING[5'd24] = CHAR_T;
assign BIOS_START_OS_STRING[5'd25] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd26] = CHAR_O;
assign BIOS_START_OS_STRING[5'd27] = CHAR_S;
assign BIOS_START_OS_STRING[5'd28] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd29] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd30] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_STRING[5'd27] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd28] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd29] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_DOT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_DOT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_DOT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_DOT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_DOT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_DOT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_DOT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_DOT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_DOT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_DOT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_DOT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_DOT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_DOT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_DOT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_DOT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_DOT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_DOT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_DOT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_DOT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_DOT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_DOT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_DOT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_DOT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_DOT_STRING[5'd27] = CHAR_DOT;
assign PROG_INSERT_DOT_STRING[5'd28] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd29] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_DOT_DOT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_DOT_DOT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_DOT_DOT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_DOT_DOT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_DOT_DOT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_DOT_DOT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_DOT_DOT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_DOT_DOT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_DOT_DOT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_DOT_DOT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_DOT_DOT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_DOT_DOT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_DOT_DOT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_DOT_DOT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_DOT_DOT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_DOT_DOT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_DOT_DOT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_DOT_DOT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_DOT_DOT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_DOT_DOT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_DOT_DOT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_DOT_DOT_STRING[5'd27] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_STRING[5'd28] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_STRING[5'd29] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd27] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd28] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd29] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd31] = CHAR_SPACE;
initial begin
STATE_LCD_CHANGE <= 8'd0;
STATE_LCD_PROGRAMAS <= 32'd0;
STATE_LCD_CURRENT <= 32'd0;
end
always @ (posedge clk) begin
if (wlcd) begin
STATE_LCD_CHANGE <= OPCODE == OPCODE_LCD ? DATA[7:0] : STATE_LCD_CHANGE;
STATE_LCD_PROGRAMAS <= OPCODE == OPCODE_LCD_PGMS ? DATA : STATE_LCD_PROGRAMAS;
STATE_LCD_CURRENT <= OPCODE == OPCODE_LCD_CURR ? DATA : STATE_LCD_CURRENT;
end
end
reg [14:0] contador;
reg [1:0] i_state;
always @ (posedge contador[14]) begin
i_state <= i_state + 1'b1;
end
always @ (posedge clk) begin
contador <= contador + 1'b1;
case (STATE_LCD_CHANGE)
KERNEL_MAIN_MENU: begin
out <= KERNEL_MAIN_MENU_STRING[index];
end
KERNEL_MENU_HD: begin
out <= KERNEL_MENU_HD_STRING[index];
end
KERNEL_MENU_HD_DEL: begin
out <= KERNEL_MENU_HD_DEL_STRING[index];
end
KERNEL_MENU_HD_REN: begin
out <= KERNEL_MENU_HD_REN_STRING[index];
end
KERNEL_MENU_HD_REN_NOME: begin
out <= KERNEL_MENU_HD_REN_NOME_STRING[index];
end
KERNEL_MENU_HD_ADD_NOME: begin
out <= KERNEL_MENU_HD_ADD_NOME_STRING[index];
end
KERNEL_MENU_HD_ADD_QUIT: begin
out <= KERNEL_MENU_HD_ADD_QUIT_STRING[index];
end
KERNEL_MENU_HD_ADD_FIRST_PART: begin
out <= KERNEL_MENU_HD_ADD_FIRST_PART_STRING[index];
end
KERNEL_MENU_HD_ADD_SECOND_PART: begin
out <= KERNEL_MENU_HD_ADD_SECOND_PART_STRING[index];
end
KERNEL_MENU_HD_ADD_THIRD_PART: begin
out <= KERNEL_MENU_HD_ADD_THIRD_PART_STRING[index];
end
KERNEL_MENU_HD_ADD_FOURTH_PART: begin
out <= KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[index];
end
KERNEL_MENU_MEM: begin
out <= KERNEL_MENU_MEM_STRING[index];
end
KERNEL_MENU_MEM_LOAD: begin
out <= KERNEL_MENU_MEM_LOAD_STRING[index];
end
KERNEL_MENU_MEM_DEL: begin
out <= KERNEL_MENU_MEM_DEL_STRING[index];
end
KERNEL_MENU_EXE: begin
out <= KERNEL_MENU_EXE_STRING[index];
end
KERNEL_MENU_EXE_N_PREEMPTIVO: begin
out <= KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[index];
end
KERNEL_MENU_EXE_BLOCKED: begin
out <= KERNEL_MENU_EXE_BLOCKED_STRING[index];
end
BIOS_CHECK_HD: begin
out <= BIOS_CHECK_HD_STRING[index];
end
BIOS_CHECK_IMEM: begin
out <= BIOS_CHECK_IMEM_STRING[index];
end
BIOS_CHECK_DMEM: begin
out <= BIOS_CHECK_DMEM_STRING[index];
end
BIOS_START_OS: begin
out <= BIOS_START_OS_STRING[index];
end
PROG_INSERT: begin
case (i_state)
2'b00: begin
out <= PROG_INSERT_STRING[index];
end
2'b01: begin
out <= PROG_INSERT_DOT_STRING[index];
end
2'b10: begin
out <= PROG_INSERT_DOT_DOT_STRING[index];
end
2'b11: begin
out <= PROG_INSERT_DOT_DOT_DOT_STRING[index];
end
endcase
end
default: begin
out <= CHAR_HYPHEN;
end
endcase
end
endmodule | module LCD_display_string(clk, wlcd, index, PC, OPCODE, DATA, out); |
input clk, wlcd;
input [4:0] index;
input [25:0] PC;
input [5:0] OPCODE;
input [31:0] DATA;
output reg [7:0] out;
localparam DATA_WIDTH = 32;
localparam CHAR_WIDTH = 8;
localparam LCD_WIDTH = 32;
localparam [CHAR_WIDTH-1:0] KERNEL_MAIN_MENU = 8'd0;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD = 8'd1;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_DEL = 8'd2;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN = 8'd3;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN_NOME = 8'd4;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_NOME = 8'd5;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_QUIT = 8'd6;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FIRST_PART = 8'd7;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_SECOND_PART = 8'd8;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_THIRD_PART = 8'd9;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FOURTH_PART = 8'd10;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_MEM = 8'd11;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_LOAD = 8'd12;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_DEL = 8'd13;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_EXE = 8'd14;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_N_PREEMPTIVO = 8'd15;
localparam [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_BLOCKED = 8'd16;
localparam [CHAR_WIDTH-1:0] BIOS_CHECK_HD = 8'd20;
localparam [CHAR_WIDTH-1:0] BIOS_CHECK_IMEM = 8'd21;
localparam [CHAR_WIDTH-1:0] BIOS_CHECK_DMEM = 8'd22;
localparam [CHAR_WIDTH-1:0] BIOS_START_OS = 8'd23;
localparam [CHAR_WIDTH-1:0] PROG_INSERT = 8'd30;
localparam CHAR_a = 8'h61, CHAR_b = 8'h62, CHAR_c = 8'h63, CHAR_d = 8'h64;
localparam CHAR_e = 8'h65, CHAR_f = 8'h66, CHAR_g = 8'h67, CHAR_h = 8'h68;
localparam CHAR_i = 8'h69, CHAR_j = 8'h6A, CHAR_k = 8'h6B, CHAR_l = 8'h6C;
localparam CHAR_m = 8'h6D, CHAR_n = 8'h6E, CHAR_o = 8'h6F, CHAR_p = 8'h70;
localparam CHAR_q = 8'h71, CHAR_r = 8'h72, CHAR_s = 8'h73, CHAR_t = 8'h74;
localparam CHAR_u = 8'h75, CHAR_v = 8'h76, CHAR_w = 8'h77, CHAR_x = 8'h78;
localparam CHAR_y = 8'h79, CHAR_z = 8'h7A;
localparam CHAR_A = 8'h41, CHAR_B = 8'h42, CHAR_C = 8'h43, CHAR_D = 8'h44;
localparam CHAR_E = 8'h45, CHAR_F = 8'h46, CHAR_G = 8'h47, CHAR_H = 8'h48;
localparam CHAR_I = 8'h49, CHAR_J = 8'h4A, CHAR_K = 8'h4B, CHAR_L = 8'h4C;
localparam CHAR_M = 8'h4D, CHAR_N = 8'h4E, CHAR_O = 8'h4F, CHAR_P = 8'h50;
localparam CHAR_Q = 8'h51, CHAR_R = 8'h52, CHAR_S = 8'h53, CHAR_T = 8'h54;
localparam CHAR_U = 8'h55, CHAR_V = 8'h56, CHAR_W = 8'h57, CHAR_X = 8'h58;
localparam CHAR_Y = 8'h59, CHAR_Z = 8'h5A;
localparam CHAR_0 = 8'h30, CHAR_1 = 8'h31, CHAR_2 = 8'h32, CHAR_3 = 8'h33;
localparam CHAR_4 = 8'h34, CHAR_5 = 8'h35, CHAR_6 = 8'h36, CHAR_7 = 8'h37;
localparam CHAR_8 = 8'h38, CHAR_9 = 8'h39;
localparam CHAR_SPACE = 8'h20, CHAR_LEFT_BRACKET = 8'h5B, CHAR_RIGHT_BRACKET = 8'h5D;
localparam CHAR_HYPHEN = 8'h2D, CHAR_HASHTAG = 8'h23, CHAR_AT = 8'h40, CHAR_PLUS = 8'h2B;
localparam CHAR_COLLON = 8'h3A, CHAR_DOT = 8'h2E;
localparam OPCODE_LCD = 6'b011110;
localparam OPCODE_LCD_PGMS = 6'b011111;
localparam OPCODE_LCD_CURR = 6'b100000;
wire [CHAR_WIDTH-1:0] KERNEL_MAIN_MENU_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_DEL_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_REN_NOME_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_NOME_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_QUIT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FIRST_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_SECOND_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_THIRD_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_HD_ADD_FOURTH_PART_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_LOAD_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_MEM_DEL_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_N_PREEMPTIVO_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] KERNEL_MENU_EXE_BLOCKED_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_CHECK_HD_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_CHECK_IMEM_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_CHECK_DMEM_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] BIOS_START_OS_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_DOT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_DOT_DOT_STRING [0:LCD_WIDTH-1];
wire [CHAR_WIDTH-1:0] PROG_INSERT_DOT_DOT_DOT_STRING [0:LCD_WIDTH-1];
reg [CHAR_WIDTH:0] STATE_LCD_CHANGE;
reg [31:0] STATE_LCD_PROGRAMAS;
reg [31:0] STATE_LCD_CURRENT;
reg [7:0] PC_MILHAR;
reg [7:0] PC_CENTENA;
reg [7:0] PC_DEZENA;
reg [7:0] PC_UNIDADE;
reg [7:0] CURRENT_DEZENA;
reg [7:0] CURRENT_UNIDADE;
reg [3:0] milhar;
reg [3:0] centena;
reg [3:0] dezena;
reg [3:0] unidade;
reg [3:0] dezena_c;
reg [3:0] unidade_c;
reg [31:0] aux;
integer i;
function [7:0] display;
input [3:0] in;
case (in)
4'b0000: display = CHAR_0;
4'b0001: display = CHAR_1;
4'b0010: display = CHAR_2;
4'b0011: display = CHAR_3;
4'b0100: display = CHAR_4;
4'b0101: display = CHAR_5;
4'b0110: display = CHAR_6;
4'b0111: display = CHAR_7;
4'b1000: display = CHAR_8;
4'b1001: display = CHAR_9;
default: display = CHAR_HYPHEN;
endcase
endfunction
always @ (PC or STATE_LCD_CURRENT) begin
aux = 32'b0;
dezena_c = 4'b0000;
unidade_c = 4'b0000;
if(STATE_LCD_CURRENT[15] == 0) begin
for(i = 15; i >=0; i = i-1) begin
if(dezena_c >= 5) dezena_c = dezena_c + 4'd3;
if(unidade_c >= 5) unidade_c = unidade_c + 4'd3;
dezena_c = dezena_c << 1;
dezena_c[0] = unidade_c[3];
unidade_c = unidade_c << 1;
unidade_c[0] = STATE_LCD_CURRENT[i];
end
end
else begin
aux = ~(STATE_LCD_CURRENT) + 8'b00000001;
for(i = 15; i >=0; i = i-1) begin
if(dezena_c >= 5) dezena_c = dezena_c + 4'd3;
if(unidade_c >= 5) unidade_c = unidade_c + 4'd3;
dezena_c = dezena_c << 1;
dezena_c[0] = unidade_c[3];
unidade_c = unidade_c << 1;
unidade_c[0] = aux[i];
end
end
CURRENT_DEZENA <= display(dezena_c);
CURRENT_UNIDADE <= display(unidade_c);
end
always @ (PC) begin
aux = 32'b0;
milhar = 4'b0000;
centena = 4'b0000;
dezena = 4'b0000;
unidade = 4'b0000;
if(PC[25] == 0) begin
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = PC[i];
end
end
else begin
aux = ~(PC) + 16'b0000000000000001;
for(i = 15; i >= 0; i = i-1) begin
if(milhar >= 5) milhar = milhar + 4'd3;
if(centena >= 5) centena = centena + 4'd3;
if(dezena >= 5) dezena = dezena + 4'd3;
if(unidade >= 5) unidade = unidade + 4'd3;
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = aux[i];
end
end
PC_MILHAR <= display(milhar);
PC_CENTENA <= display(centena);
PC_DEZENA <= display(dezena);
PC_UNIDADE <= display(unidade);
end
assign KERNEL_MAIN_MENU_STRING[5'd0] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd1] = CHAR_A;
assign KERNEL_MAIN_MENU_STRING[5'd2] = CHAR_I;
assign KERNEL_MAIN_MENU_STRING[5'd3] = CHAR_N;
assign KERNEL_MAIN_MENU_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd6] = CHAR_1;
assign KERNEL_MAIN_MENU_STRING[5'd7] = CHAR_H;
assign KERNEL_MAIN_MENU_STRING[5'd8] = CHAR_D;
assign KERNEL_MAIN_MENU_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd10] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd12] = CHAR_3;
assign KERNEL_MAIN_MENU_STRING[5'd13] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd14] = CHAR_X;
assign KERNEL_MAIN_MENU_STRING[5'd15] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd16] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd17] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd18] = CHAR_N;
assign KERNEL_MAIN_MENU_STRING[5'd19] = CHAR_U;
assign KERNEL_MAIN_MENU_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd22] = CHAR_2;
assign KERNEL_MAIN_MENU_STRING[5'd23] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd24] = CHAR_E;
assign KERNEL_MAIN_MENU_STRING[5'd25] = CHAR_M;
assign KERNEL_MAIN_MENU_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MAIN_MENU_STRING[5'd28] = CHAR_4;
assign KERNEL_MAIN_MENU_STRING[5'd29] = CHAR_C;
assign KERNEL_MAIN_MENU_STRING[5'd30] = CHAR_L;
assign KERNEL_MAIN_MENU_STRING[5'd31] = CHAR_R;
assign KERNEL_MENU_HD_STRING[5'd0] = CHAR_M;
assign KERNEL_MENU_HD_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_HD_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_HD_STRING[5'd3] = CHAR_U;
assign KERNEL_MENU_HD_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd6] = CHAR_1;
assign KERNEL_MENU_HD_STRING[5'd7] = CHAR_A;
assign KERNEL_MENU_HD_STRING[5'd8] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd9] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd10] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd12] = CHAR_3;
assign KERNEL_MENU_HD_STRING[5'd13] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd14] = CHAR_E;
assign KERNEL_MENU_HD_STRING[5'd15] = CHAR_L;
assign KERNEL_MENU_HD_STRING[5'd16] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd17] = CHAR_H;
assign KERNEL_MENU_HD_STRING[5'd18] = CHAR_D;
assign KERNEL_MENU_HD_STRING[5'd19] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd22] = CHAR_2;
assign KERNEL_MENU_HD_STRING[5'd23] = CHAR_R;
assign KERNEL_MENU_HD_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_HD_STRING[5'd25] = CHAR_N;
assign KERNEL_MENU_HD_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_HD_STRING[5'd28] = CHAR_4;
assign KERNEL_MENU_HD_STRING[5'd29] = CHAR_B;
assign KERNEL_MENU_HD_STRING[5'd30] = CHAR_C;
assign KERNEL_MENU_HD_STRING[5'd31] = CHAR_K;
assign KERNEL_MENU_HD_DEL_STRING[5'd0] = CHAR_P;
assign KERNEL_MENU_HD_DEL_STRING[5'd1] = CHAR_U;
assign KERNEL_MENU_HD_DEL_STRING[5'd2] = CHAR_R;
assign KERNEL_MENU_HD_DEL_STRING[5'd3] = CHAR_G;
assign KERNEL_MENU_HD_DEL_STRING[5'd4] = CHAR_E;
assign KERNEL_MENU_HD_DEL_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_DEL_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_DEL_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_HD_DEL_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_HD_DEL_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_DEL_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd0] = CHAR_R;
assign KERNEL_MENU_HD_REN_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_HD_REN_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_HD_REN_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_REN_STRING[5'd4] = CHAR_M;
assign KERNEL_MENU_HD_REN_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_REN_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_REN_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_HD_REN_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_HD_REN_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd0] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd4] = CHAR_M;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd16] = CHAR_I;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd17] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd18] = CHAR_S;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd19] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd20] = CHAR_R;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd21] = CHAR_T;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd22] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd23] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd25] = CHAR_W;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd27] = CHAR_N;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd28] = CHAR_A;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd29] = CHAR_M;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd30] = CHAR_E;
assign KERNEL_MENU_HD_REN_NOME_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd21] = CHAR_N;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd22] = CHAR_A;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd23] = CHAR_M;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd25] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd26] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd28] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_NOME_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd19] = CHAR_S;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd20] = CHAR_S;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd22] = CHAR_0;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd24] = CHAR_T;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd25] = CHAR_O;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd27] = CHAR_Q;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd28] = CHAR_U;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd29] = CHAR_I;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd30] = CHAR_T;
assign KERNEL_MENU_HD_ADD_QUIT_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd16] = CHAR_F;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd17] = CHAR_I;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd18] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd19] = CHAR_S;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd20] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd22] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd23] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd24] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd25] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd26] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FIRST_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd16] = CHAR_S;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd17] = CHAR_E;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd18] = CHAR_C;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd19] = CHAR_O;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd20] = CHAR_N;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd21] = CHAR_D;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd22] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd23] = CHAR_P;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd24] = CHAR_A;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd25] = CHAR_R;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd26] = CHAR_T;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd29] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_SECOND_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd16] = CHAR_T;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd17] = CHAR_H;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd18] = CHAR_I;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd19] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd20] = CHAR_D;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd22] = CHAR_P;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd23] = CHAR_A;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd24] = CHAR_R;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd25] = CHAR_T;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd26] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_THIRD_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd0] = CHAR_C;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd2] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd3] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd4] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd5] = CHAR_E;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd6] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd9] = CHAR_O;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd10] = CHAR_G;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd11] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd12] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd13] = CHAR_M;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd14] = CHAR_COLLON;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd16] = CHAR_F;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd17] = CHAR_O;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd18] = CHAR_U;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd19] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd20] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd21] = CHAR_H;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd22] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd23] = CHAR_P;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd24] = CHAR_A;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd25] = CHAR_R;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd26] = CHAR_T;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd27] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd28] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd29] = CHAR_DOT;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd0] = CHAR_M;
assign KERNEL_MENU_MEM_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_MEM_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_MEM_STRING[5'd3] = CHAR_U;
assign KERNEL_MENU_MEM_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd6] = CHAR_1;
assign KERNEL_MENU_MEM_STRING[5'd7] = CHAR_L;
assign KERNEL_MENU_MEM_STRING[5'd8] = CHAR_O;
assign KERNEL_MENU_MEM_STRING[5'd9] = CHAR_A;
assign KERNEL_MENU_MEM_STRING[5'd10] = CHAR_D;
assign KERNEL_MENU_MEM_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd12] = CHAR_3;
assign KERNEL_MENU_MEM_STRING[5'd13] = CHAR_B;
assign KERNEL_MENU_MEM_STRING[5'd14] = CHAR_C;
assign KERNEL_MENU_MEM_STRING[5'd15] = CHAR_K;
assign KERNEL_MENU_MEM_STRING[5'd16] = CHAR_M;
assign KERNEL_MENU_MEM_STRING[5'd17] = CHAR_E;
assign KERNEL_MENU_MEM_STRING[5'd18] = CHAR_M;
assign KERNEL_MENU_MEM_STRING[5'd19] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd22] = CHAR_2;
assign KERNEL_MENU_MEM_STRING[5'd23] = CHAR_D;
assign KERNEL_MENU_MEM_STRING[5'd24] = CHAR_E;
assign KERNEL_MENU_MEM_STRING[5'd25] = CHAR_L;
assign KERNEL_MENU_MEM_STRING[5'd26] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd28] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd30] = CHAR_SPACE;
assign KERNEL_MENU_MEM_STRING[5'd31] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd0] = CHAR_L;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd1] = CHAR_O;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd2] = CHAR_A;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd3] = CHAR_D;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_LOAD_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd0] = CHAR_D;
assign KERNEL_MENU_MEM_DEL_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_MEM_DEL_STRING[5'd2] = CHAR_L;
assign KERNEL_MENU_MEM_DEL_STRING[5'd3] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd16] = CHAR_P;
assign KERNEL_MENU_MEM_DEL_STRING[5'd17] = CHAR_R;
assign KERNEL_MENU_MEM_DEL_STRING[5'd18] = CHAR_O;
assign KERNEL_MENU_MEM_DEL_STRING[5'd19] = CHAR_G;
assign KERNEL_MENU_MEM_DEL_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_MEM_DEL_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd0] = CHAR_M;
assign KERNEL_MENU_EXE_STRING[5'd1] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd2] = CHAR_N;
assign KERNEL_MENU_EXE_STRING[5'd3] = CHAR_U;
assign KERNEL_MENU_EXE_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd6] = CHAR_1;
assign KERNEL_MENU_EXE_STRING[5'd7] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd8] = CHAR_R;
assign KERNEL_MENU_EXE_STRING[5'd9] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd10] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd12] = CHAR_3;
assign KERNEL_MENU_EXE_STRING[5'd13] = CHAR_B;
assign KERNEL_MENU_EXE_STRING[5'd14] = CHAR_L;
assign KERNEL_MENU_EXE_STRING[5'd15] = CHAR_K;
assign KERNEL_MENU_EXE_STRING[5'd16] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd17] = CHAR_X;
assign KERNEL_MENU_EXE_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_EXE_STRING[5'd19] = CHAR_C;
assign KERNEL_MENU_EXE_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd22] = CHAR_2;
assign KERNEL_MENU_EXE_STRING[5'd23] = CHAR_N;
assign KERNEL_MENU_EXE_STRING[5'd24] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd25] = CHAR_R;
assign KERNEL_MENU_EXE_STRING[5'd26] = CHAR_P;
assign KERNEL_MENU_EXE_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_EXE_STRING[5'd28] = CHAR_4;
assign KERNEL_MENU_EXE_STRING[5'd29] = CHAR_B;
assign KERNEL_MENU_EXE_STRING[5'd30] = CHAR_C;
assign KERNEL_MENU_EXE_STRING[5'd31] = CHAR_K;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd0] = CHAR_P;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd1] = CHAR_R;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd2] = CHAR_O;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd3] = CHAR_G;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd16] = CHAR_E;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd17] = CHAR_X;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd19] = CHAR_C;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd0] = CHAR_B;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd1] = CHAR_L;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd2] = CHAR_C;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd3] = CHAR_K;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd4] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd5] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd6] = STATE_LCD_PROGRAMAS[0] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd7] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd8] = STATE_LCD_PROGRAMAS[1] == 1'b1 ? CHAR_2 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd9] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd10] = STATE_LCD_PROGRAMAS[2] == 1'b1 ? CHAR_3 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd11] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd12] = STATE_LCD_PROGRAMAS[3] == 1'b1 ? CHAR_4 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd13] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd14] = STATE_LCD_PROGRAMAS[4] == 1'b1 ? CHAR_5 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd15] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd16] = CHAR_E;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd17] = CHAR_X;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd18] = CHAR_E;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd19] = CHAR_C;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd20] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd21] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd22] = STATE_LCD_PROGRAMAS[5] == 1'b1 ? CHAR_6 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd23] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd24] = STATE_LCD_PROGRAMAS[6] == 1'b1 ? CHAR_7 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd25] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd26] = STATE_LCD_PROGRAMAS[7] == 1'b1 ? CHAR_8 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd27] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd28] = STATE_LCD_PROGRAMAS[8] == 1'b1 ? CHAR_9 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd29] = CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd30] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_1 : CHAR_SPACE;
assign KERNEL_MENU_EXE_BLOCKED_STRING[5'd31] = STATE_LCD_PROGRAMAS[9] == 1'b1 ? CHAR_0 : CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd0] = CHAR_B;
assign BIOS_CHECK_HD_STRING[5'd1] = CHAR_I;
assign BIOS_CHECK_HD_STRING[5'd2] = CHAR_O;
assign BIOS_CHECK_HD_STRING[5'd3] = CHAR_S;
assign BIOS_CHECK_HD_STRING[5'd4] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd5] = CHAR_C;
assign BIOS_CHECK_HD_STRING[5'd6] = CHAR_H;
assign BIOS_CHECK_HD_STRING[5'd7] = CHAR_E;
assign BIOS_CHECK_HD_STRING[5'd8] = CHAR_C;
assign BIOS_CHECK_HD_STRING[5'd9] = CHAR_K;
assign BIOS_CHECK_HD_STRING[5'd10] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd11] = CHAR_H;
assign BIOS_CHECK_HD_STRING[5'd12] = CHAR_D;
assign BIOS_CHECK_HD_STRING[5'd13] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd14] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd15] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd16] = CHAR_S;
assign BIOS_CHECK_HD_STRING[5'd17] = CHAR_I;
assign BIOS_CHECK_HD_STRING[5'd18] = CHAR_Z;
assign BIOS_CHECK_HD_STRING[5'd19] = CHAR_E;
assign BIOS_CHECK_HD_STRING[5'd20] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd21] = CHAR_H;
assign BIOS_CHECK_HD_STRING[5'd22] = CHAR_D;
assign BIOS_CHECK_HD_STRING[5'd23] = CHAR_COLLON;
assign BIOS_CHECK_HD_STRING[5'd24] = CHAR_4;
assign BIOS_CHECK_HD_STRING[5'd25] = CHAR_0;
assign BIOS_CHECK_HD_STRING[5'd26] = CHAR_9;
assign BIOS_CHECK_HD_STRING[5'd27] = CHAR_6;
assign BIOS_CHECK_HD_STRING[5'd28] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd29] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd30] = CHAR_SPACE;
assign BIOS_CHECK_HD_STRING[5'd31] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd0] = CHAR_B;
assign BIOS_CHECK_IMEM_STRING[5'd1] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd2] = CHAR_O;
assign BIOS_CHECK_IMEM_STRING[5'd3] = CHAR_S;
assign BIOS_CHECK_IMEM_STRING[5'd4] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd5] = CHAR_C;
assign BIOS_CHECK_IMEM_STRING[5'd6] = CHAR_H;
assign BIOS_CHECK_IMEM_STRING[5'd7] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd8] = CHAR_C;
assign BIOS_CHECK_IMEM_STRING[5'd9] = CHAR_K;
assign BIOS_CHECK_IMEM_STRING[5'd10] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd11] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd12] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd13] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd14] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd15] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd16] = CHAR_S;
assign BIOS_CHECK_IMEM_STRING[5'd17] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd18] = CHAR_Z;
assign BIOS_CHECK_IMEM_STRING[5'd19] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd20] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd21] = CHAR_I;
assign BIOS_CHECK_IMEM_STRING[5'd22] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd23] = CHAR_E;
assign BIOS_CHECK_IMEM_STRING[5'd24] = CHAR_M;
assign BIOS_CHECK_IMEM_STRING[5'd25] = CHAR_COLLON;
assign BIOS_CHECK_IMEM_STRING[5'd26] = CHAR_4;
assign BIOS_CHECK_IMEM_STRING[5'd27] = CHAR_0;
assign BIOS_CHECK_IMEM_STRING[5'd28] = CHAR_9;
assign BIOS_CHECK_IMEM_STRING[5'd29] = CHAR_6;
assign BIOS_CHECK_IMEM_STRING[5'd30] = CHAR_SPACE;
assign BIOS_CHECK_IMEM_STRING[5'd31] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd0] = CHAR_B;
assign BIOS_CHECK_DMEM_STRING[5'd1] = CHAR_I;
assign BIOS_CHECK_DMEM_STRING[5'd2] = CHAR_O;
assign BIOS_CHECK_DMEM_STRING[5'd3] = CHAR_S;
assign BIOS_CHECK_DMEM_STRING[5'd4] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd5] = CHAR_C;
assign BIOS_CHECK_DMEM_STRING[5'd6] = CHAR_H;
assign BIOS_CHECK_DMEM_STRING[5'd7] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd8] = CHAR_C;
assign BIOS_CHECK_DMEM_STRING[5'd9] = CHAR_K;
assign BIOS_CHECK_DMEM_STRING[5'd10] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd11] = CHAR_D;
assign BIOS_CHECK_DMEM_STRING[5'd12] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd13] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd14] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd15] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd16] = CHAR_S;
assign BIOS_CHECK_DMEM_STRING[5'd17] = CHAR_I;
assign BIOS_CHECK_DMEM_STRING[5'd18] = CHAR_Z;
assign BIOS_CHECK_DMEM_STRING[5'd19] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd20] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd21] = CHAR_D;
assign BIOS_CHECK_DMEM_STRING[5'd22] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd23] = CHAR_E;
assign BIOS_CHECK_DMEM_STRING[5'd24] = CHAR_M;
assign BIOS_CHECK_DMEM_STRING[5'd25] = CHAR_COLLON;
assign BIOS_CHECK_DMEM_STRING[5'd26] = CHAR_2;
assign BIOS_CHECK_DMEM_STRING[5'd27] = CHAR_0;
assign BIOS_CHECK_DMEM_STRING[5'd28] = CHAR_4;
assign BIOS_CHECK_DMEM_STRING[5'd29] = CHAR_8;
assign BIOS_CHECK_DMEM_STRING[5'd30] = CHAR_SPACE;
assign BIOS_CHECK_DMEM_STRING[5'd31] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd0] = CHAR_P;
assign BIOS_START_OS_STRING[5'd1] = CHAR_R;
assign BIOS_START_OS_STRING[5'd2] = CHAR_E;
assign BIOS_START_OS_STRING[5'd3] = CHAR_S;
assign BIOS_START_OS_STRING[5'd4] = CHAR_S;
assign BIOS_START_OS_STRING[5'd5] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd6] = CHAR_I;
assign BIOS_START_OS_STRING[5'd7] = CHAR_N;
assign BIOS_START_OS_STRING[5'd8] = CHAR_S;
assign BIOS_START_OS_STRING[5'd9] = CHAR_E;
assign BIOS_START_OS_STRING[5'd10] = CHAR_R;
assign BIOS_START_OS_STRING[5'd11] = CHAR_T;
assign BIOS_START_OS_STRING[5'd12] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd13] = CHAR_T;
assign BIOS_START_OS_STRING[5'd14] = CHAR_O;
assign BIOS_START_OS_STRING[5'd15] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd16] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd17] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd18] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd19] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd20] = CHAR_S;
assign BIOS_START_OS_STRING[5'd21] = CHAR_T;
assign BIOS_START_OS_STRING[5'd22] = CHAR_A;
assign BIOS_START_OS_STRING[5'd23] = CHAR_R;
assign BIOS_START_OS_STRING[5'd24] = CHAR_T;
assign BIOS_START_OS_STRING[5'd25] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd26] = CHAR_O;
assign BIOS_START_OS_STRING[5'd27] = CHAR_S;
assign BIOS_START_OS_STRING[5'd28] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd29] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd30] = CHAR_SPACE;
assign BIOS_START_OS_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_STRING[5'd27] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd28] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd29] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_DOT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_DOT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_DOT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_DOT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_DOT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_DOT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_DOT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_DOT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_DOT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_DOT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_DOT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_DOT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_DOT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_DOT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_DOT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_DOT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_DOT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_DOT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_DOT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_DOT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_DOT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_DOT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_DOT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_DOT_STRING[5'd27] = CHAR_DOT;
assign PROG_INSERT_DOT_STRING[5'd28] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd29] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_DOT_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_DOT_DOT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_DOT_DOT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_DOT_DOT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_DOT_DOT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_DOT_DOT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_DOT_DOT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_DOT_DOT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_DOT_DOT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_DOT_DOT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_DOT_DOT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_DOT_DOT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_DOT_DOT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_DOT_DOT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_DOT_DOT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_DOT_DOT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_DOT_DOT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_DOT_DOT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_DOT_DOT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_DOT_DOT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_DOT_DOT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_DOT_DOT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_DOT_DOT_STRING[5'd27] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_STRING[5'd28] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_STRING[5'd29] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_STRING[5'd31] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd0] = CHAR_P;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd1] = CHAR_R;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd2] = CHAR_O;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd3] = CHAR_G;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd4] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd5] = CURRENT_DEZENA;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd6] = CURRENT_UNIDADE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd7] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd8] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd9] = CHAR_P;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd10] = CHAR_C;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd11] = CHAR_COLLON;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd12] = PC_MILHAR;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd13] = PC_CENTENA;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd14] = PC_DEZENA;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd15] = PC_UNIDADE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd16] = CHAR_I;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd17] = CHAR_N;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd18] = CHAR_S;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd19] = CHAR_E;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd20] = CHAR_R;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd21] = CHAR_T;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd22] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd23] = CHAR_D;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd24] = CHAR_A;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd25] = CHAR_T;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd26] = CHAR_A;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd27] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd28] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd29] = CHAR_DOT;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd30] = CHAR_SPACE;
assign PROG_INSERT_DOT_DOT_DOT_STRING[5'd31] = CHAR_SPACE;
initial begin
STATE_LCD_CHANGE <= 8'd0;
STATE_LCD_PROGRAMAS <= 32'd0;
STATE_LCD_CURRENT <= 32'd0;
end
always @ (posedge clk) begin
if (wlcd) begin
STATE_LCD_CHANGE <= OPCODE == OPCODE_LCD ? DATA[7:0] : STATE_LCD_CHANGE;
STATE_LCD_PROGRAMAS <= OPCODE == OPCODE_LCD_PGMS ? DATA : STATE_LCD_PROGRAMAS;
STATE_LCD_CURRENT <= OPCODE == OPCODE_LCD_CURR ? DATA : STATE_LCD_CURRENT;
end
end
reg [14:0] contador;
reg [1:0] i_state;
always @ (posedge contador[14]) begin
i_state <= i_state + 1'b1;
end
always @ (posedge clk) begin
contador <= contador + 1'b1;
case (STATE_LCD_CHANGE)
KERNEL_MAIN_MENU: begin
out <= KERNEL_MAIN_MENU_STRING[index];
end
KERNEL_MENU_HD: begin
out <= KERNEL_MENU_HD_STRING[index];
end
KERNEL_MENU_HD_DEL: begin
out <= KERNEL_MENU_HD_DEL_STRING[index];
end
KERNEL_MENU_HD_REN: begin
out <= KERNEL_MENU_HD_REN_STRING[index];
end
KERNEL_MENU_HD_REN_NOME: begin
out <= KERNEL_MENU_HD_REN_NOME_STRING[index];
end
KERNEL_MENU_HD_ADD_NOME: begin
out <= KERNEL_MENU_HD_ADD_NOME_STRING[index];
end
KERNEL_MENU_HD_ADD_QUIT: begin
out <= KERNEL_MENU_HD_ADD_QUIT_STRING[index];
end
KERNEL_MENU_HD_ADD_FIRST_PART: begin
out <= KERNEL_MENU_HD_ADD_FIRST_PART_STRING[index];
end
KERNEL_MENU_HD_ADD_SECOND_PART: begin
out <= KERNEL_MENU_HD_ADD_SECOND_PART_STRING[index];
end
KERNEL_MENU_HD_ADD_THIRD_PART: begin
out <= KERNEL_MENU_HD_ADD_THIRD_PART_STRING[index];
end
KERNEL_MENU_HD_ADD_FOURTH_PART: begin
out <= KERNEL_MENU_HD_ADD_FOURTH_PART_STRING[index];
end
KERNEL_MENU_MEM: begin
out <= KERNEL_MENU_MEM_STRING[index];
end
KERNEL_MENU_MEM_LOAD: begin
out <= KERNEL_MENU_MEM_LOAD_STRING[index];
end
KERNEL_MENU_MEM_DEL: begin
out <= KERNEL_MENU_MEM_DEL_STRING[index];
end
KERNEL_MENU_EXE: begin
out <= KERNEL_MENU_EXE_STRING[index];
end
KERNEL_MENU_EXE_N_PREEMPTIVO: begin
out <= KERNEL_MENU_EXE_N_PREEMPTIVO_STRING[index];
end
KERNEL_MENU_EXE_BLOCKED: begin
out <= KERNEL_MENU_EXE_BLOCKED_STRING[index];
end
BIOS_CHECK_HD: begin
out <= BIOS_CHECK_HD_STRING[index];
end
BIOS_CHECK_IMEM: begin
out <= BIOS_CHECK_IMEM_STRING[index];
end
BIOS_CHECK_DMEM: begin
out <= BIOS_CHECK_DMEM_STRING[index];
end
BIOS_START_OS: begin
out <= BIOS_START_OS_STRING[index];
end
PROG_INSERT: begin
case (i_state)
2'b00: begin
out <= PROG_INSERT_STRING[index];
end
2'b01: begin
out <= PROG_INSERT_DOT_STRING[index];
end
2'b10: begin
out <= PROG_INSERT_DOT_DOT_STRING[index];
end
2'b11: begin
out <= PROG_INSERT_DOT_DOT_DOT_STRING[index];
end
endcase
end
default: begin
out <= CHAR_HYPHEN;
end
endcase
end
endmodule | 0 |
141,700 | data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v | 95,938,920 | LCD_Display.v | v | 1,500 | 107 | [] | [] | [] | [(40, 264), (266, 1499)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:423: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance LCD_Display.u1\n aux = ~(STATE_LCD_CURRENT) + 8\'b00000001;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:461: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'PC\' generates 26 bits.\n : ... In instance LCD_Display.u1\n aux = ~(PC) + 16\'b0000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n : ... In instance LCD_Display.u1\n aux = ~(PC) + 16\'b0000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1392: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance LCD_Display.u1\n STATE_LCD_CHANGE <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1399: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s SEL generates 8 bits.\n : ... In instance LCD_Display.u1\n STATE_LCD_CHANGE <= OPCODE == OPCODE_LCD ? DATA[7:0] : STATE_LCD_CHANGE;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MAIN_MENU\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_DEL\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_REN\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_REN_NOME\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_NOME\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_QUIT\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_FIRST_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_SECOND_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_THIRD_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_HD_ADD_FOURTH_PART\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM_LOAD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_MEM_DEL\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE_N_PREEMPTIVO\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'KERNEL_MENU_EXE_BLOCKED\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_HD\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_IMEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_CHECK_DMEM\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'BIOS_START_OS\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/LCD_Display/LCD_Display.v:1414: Operator CASE expects 9 bits on the Case Item, but Case Item\'s VARREF \'PROG_INSERT\' generates 8 bits.\n : ... In instance LCD_Display.u1\n case (STATE_LCD_CHANGE)\n ^~~~\n%Error: Exiting due to 27 warning(s)\n' | 312,316 | function | function [7:0] display;
input [3:0] in;
case (in)
4'b0000: display = CHAR_0;
4'b0001: display = CHAR_1;
4'b0010: display = CHAR_2;
4'b0011: display = CHAR_3;
4'b0100: display = CHAR_4;
4'b0101: display = CHAR_5;
4'b0110: display = CHAR_6;
4'b0111: display = CHAR_7;
4'b1000: display = CHAR_8;
4'b1001: display = CHAR_9;
default: display = CHAR_HYPHEN;
endcase
endfunction | function [7:0] display; |
input [3:0] in;
case (in)
4'b0000: display = CHAR_0;
4'b0001: display = CHAR_1;
4'b0010: display = CHAR_2;
4'b0011: display = CHAR_3;
4'b0100: display = CHAR_4;
4'b0101: display = CHAR_5;
4'b0110: display = CHAR_6;
4'b0111: display = CHAR_7;
4'b1000: display = CHAR_8;
4'b1001: display = CHAR_9;
default: display = CHAR_HYPHEN;
endcase
endfunction | 0 |
141,701 | data/full_repos/permissive/95938920/src/main/modules/memoria_de_dados/memoria_de_dados.v | 95,938,920 | memoria_de_dados.v | v | 21 | 66 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/c3bd6d0c-97df-4298-b654-968cade4966f.xml | null | 312,317 | module | module memoria_de_dados (clk_50, clk, we, addr, datain, dataout);
input clk_50;
input clk;
input we;
input [31:0] addr;
input [31:0] datain;
output reg [31:0] dataout;
localparam RAM_SIZE = 2048;
reg [31:0] ram [RAM_SIZE-1:0];
always @ (posedge clk) begin
if (we) ram[addr] <= datain;
end
always @ (posedge clk_50) begin
dataout <= ram[addr];
end
endmodule | module memoria_de_dados (clk_50, clk, we, addr, datain, dataout); |
input clk_50;
input clk;
input we;
input [31:0] addr;
input [31:0] datain;
output reg [31:0] dataout;
localparam RAM_SIZE = 2048;
reg [31:0] ram [RAM_SIZE-1:0];
always @ (posedge clk) begin
if (we) ram[addr] <= datain;
end
always @ (posedge clk_50) begin
dataout <= ram[addr];
end
endmodule | 0 |
141,702 | data/full_repos/permissive/95938920/src/main/modules/memoria_de_instrucoes/memoria_de_instrucoes.v | 95,938,920 | memoria_de_instrucoes.v | v | 21 | 67 | [] | [] | [] | [(1, 20)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/memoria_de_instrucoes/memoria_de_instrucoes.v:18: Bit extraction of array[4095:0] requires 12 bit index, not 26 bits.\n : ... In instance memoria_de_instrucoes\n dataout <= ram[pc];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,318 | module | module memoria_de_instrucoes (clk, we, pc, addr, datain, dataout);
input clk;
input we;
input [25:0] pc;
input [31:0] addr;
input [31:0] datain;
output reg [31:0] dataout;
localparam RAM_SIZE = 4096;
reg [31:0] ram [RAM_SIZE-1:0];
always @ (posedge clk) begin
if (we) ram[addr] <= datain;
end
always @ (*) begin
dataout <= ram[pc];
end
endmodule | module memoria_de_instrucoes (clk, we, pc, addr, datain, dataout); |
input clk;
input we;
input [25:0] pc;
input [31:0] addr;
input [31:0] datain;
output reg [31:0] dataout;
localparam RAM_SIZE = 4096;
reg [31:0] ram [RAM_SIZE-1:0];
always @ (posedge clk) begin
if (we) ram[addr] <= datain;
end
always @ (*) begin
dataout <= ram[pc];
end
endmodule | 0 |
141,703 | data/full_repos/permissive/95938920/src/main/modules/mmu/mmu.v | 95,938,920 | mmu.v | v | 65 | 147 | [] | [] | [] | [(1, 64)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/mmu/mmu.v:57: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'addrIn\' generates 26 bits.\n : ... In instance mmu\n assign enderecoLogico = EXECUTION_MODE == KERNEL_MODE ? addrIn : addrIn + lowerIM[selector];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/mmu/mmu.v:57: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addrIn\' generates 26 bits.\n : ... In instance mmu\n assign enderecoLogico = EXECUTION_MODE == KERNEL_MODE ? addrIn : addrIn + lowerIM[selector];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,319 | module | module mmu(clk_50, clk, we_addr, we_sel, userMode, kernelMode, sel, offset, addrIn, inta, addrOut, isUser);
input clk_50;
input clk;
input we_addr;
input we_sel;
input userMode;
input kernelMode;
input [31:0] sel;
input [31:0] offset;
input [25:0] addrIn;
input inta;
output reg [25:0] addrOut;
output isUser;
reg [31:0] lowerIM[10:0];
reg [31:0] upperIM[10:0];
reg [31:0] lowerDM[10:0];
reg [31:0] upperDM[10:0];
reg [31:0] selector;
wire [31:0] enderecoLogico;
localparam KERNEL_MODE = 1'b0, USER_MODE = 1'b1;
reg EXECUTION_MODE;
initial begin
EXECUTION_MODE <= KERNEL_MODE;
end
always @ (posedge clk) begin
if (we_addr)
lowerIM[selector] <= offset;
end
always @ (posedge clk) begin
if (we_sel)
selector <= sel;
end
always @ (posedge clk) begin
if (userMode)
EXECUTION_MODE <= USER_MODE;
if (kernelMode | inta)
EXECUTION_MODE <= KERNEL_MODE;
end
assign enderecoLogico = EXECUTION_MODE == KERNEL_MODE ? addrIn : addrIn + lowerIM[selector];
always @ (posedge clk_50) begin
addrOut <= enderecoLogico[25:0];
end
assign isUser = EXECUTION_MODE;
endmodule | module mmu(clk_50, clk, we_addr, we_sel, userMode, kernelMode, sel, offset, addrIn, inta, addrOut, isUser); |
input clk_50;
input clk;
input we_addr;
input we_sel;
input userMode;
input kernelMode;
input [31:0] sel;
input [31:0] offset;
input [25:0] addrIn;
input inta;
output reg [25:0] addrOut;
output isUser;
reg [31:0] lowerIM[10:0];
reg [31:0] upperIM[10:0];
reg [31:0] lowerDM[10:0];
reg [31:0] upperDM[10:0];
reg [31:0] selector;
wire [31:0] enderecoLogico;
localparam KERNEL_MODE = 1'b0, USER_MODE = 1'b1;
reg EXECUTION_MODE;
initial begin
EXECUTION_MODE <= KERNEL_MODE;
end
always @ (posedge clk) begin
if (we_addr)
lowerIM[selector] <= offset;
end
always @ (posedge clk) begin
if (we_sel)
selector <= sel;
end
always @ (posedge clk) begin
if (userMode)
EXECUTION_MODE <= USER_MODE;
if (kernelMode | inta)
EXECUTION_MODE <= KERNEL_MODE;
end
assign enderecoLogico = EXECUTION_MODE == KERNEL_MODE ? addrIn : addrIn + lowerIM[selector];
always @ (posedge clk_50) begin
addrOut <= enderecoLogico[25:0];
end
assign isUser = EXECUTION_MODE;
endmodule | 0 |
141,704 | data/full_repos/permissive/95938920/src/main/modules/modulo_input/modulo_input.v | 95,938,920 | modulo_input.v | v | 12 | 84 | [] | [] | [] | [(1, 11)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/modulo_input/modulo_input.v:9: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance modulo_input\n out <= in[7:0] + 32\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,320 | module | module modulo_input(in, out);
input [17:0] in;
output reg [31:0] out;
always @ (*) begin
out <= in[7:0] + 32'b0;
end
endmodule | module modulo_input(in, out); |
input [17:0] in;
output reg [31:0] out;
always @ (*) begin
out <= in[7:0] + 32'b0;
end
endmodule | 0 |
141,705 | data/full_repos/permissive/95938920/src/main/modules/multiplexador_br/multiplexador_br.v | 95,938,920 | multiplexador_br.v | v | 27 | 82 | [] | [] | [] | [(1, 26)] | null | data/verilator_xmls/97eb5ce8-fd3f-4ded-be8c-b48ba693566e.xml | null | 312,321 | module | module multiplexador_br(RT, RD, ctrl, regEscrito);
input [4:0] RT;
input [4:0] RD;
input [1:0] ctrl;
output [4:0] regEscrito;
localparam REG_ADDRESS = 5'b11111;
localparam REG_KERNEL_ADDR = 5'b11001;
function [4:0] select;
input [4:0] RD, RT, RA, RK;
input [1:0] s;
case (s)
2'b00: select = RD;
2'b01: select = RT;
2'b10: select = RA;
2'b11: select = RK;
endcase
endfunction
assign regEscrito = select(RD, RT, REG_ADDRESS, REG_KERNEL_ADDR, ctrl);
endmodule | module multiplexador_br(RT, RD, ctrl, regEscrito); |
input [4:0] RT;
input [4:0] RD;
input [1:0] ctrl;
output [4:0] regEscrito;
localparam REG_ADDRESS = 5'b11111;
localparam REG_KERNEL_ADDR = 5'b11001;
function [4:0] select;
input [4:0] RD, RT, RA, RK;
input [1:0] s;
case (s)
2'b00: select = RD;
2'b01: select = RT;
2'b10: select = RA;
2'b11: select = RK;
endcase
endfunction
assign regEscrito = select(RD, RT, REG_ADDRESS, REG_KERNEL_ADDR, ctrl);
endmodule | 0 |
141,706 | data/full_repos/permissive/95938920/src/main/modules/multiplexador_br/multiplexador_br.v | 95,938,920 | multiplexador_br.v | v | 27 | 82 | [] | [] | [] | [(1, 26)] | null | data/verilator_xmls/97eb5ce8-fd3f-4ded-be8c-b48ba693566e.xml | null | 312,321 | function | function [4:0] select;
input [4:0] RD, RT, RA, RK;
input [1:0] s;
case (s)
2'b00: select = RD;
2'b01: select = RT;
2'b10: select = RA;
2'b11: select = RK;
endcase
endfunction | function [4:0] select; |
input [4:0] RD, RT, RA, RK;
input [1:0] s;
case (s)
2'b00: select = RD;
2'b01: select = RT;
2'b10: select = RA;
2'b11: select = RK;
endcase
endfunction | 0 |
141,707 | data/full_repos/permissive/95938920/src/main/modules/multiplexador_escrita_br/multiplexador_escrita_br.v | 95,938,920 | multiplexador_escrita_br.v | v | 29 | 128 | [] | [] | [] | [(1, 28)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/multiplexador_escrita_br/multiplexador_escrita_br.v:27: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'PC\' generates 26 bits.\n : ... In instance multiplexador_escrita_br\n assign dadoEscrito = select(ULA, memoria_dados, entrada_dados, PC + 32\'d1, disk, arduino, cause, pcBckp, ctrl_mux_escrita_br);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,322 | module | module multiplexador_escrita_br(
input [31:0] entrada_dados,
input [31:0] memoria_dados,
input [31:0] ULA,
input [25:0] PC,
input [31:0] disk,
input [31:0] arduino,
input [31:0] cause,
input [31:0] pcBckp,
input [2:0] ctrl_mux_escrita_br,
output [31:0] dadoEscrito);
function [31:0] select;
input [31:0] a0, a1, a2, a3, a4, a5, a6, a7;
input [2:0] s;
case(s)
3'b000: select = a0;
3'b001: select = a1;
3'b010: select = a2;
3'b011: select = a3;
3'b100: select = a4;
3'b101: select = a5;
3'b110: select = a6;
3'b111: select = a7;
endcase
endfunction
assign dadoEscrito = select(ULA, memoria_dados, entrada_dados, PC + 32'd1, disk, arduino, cause, pcBckp, ctrl_mux_escrita_br);
endmodule | module multiplexador_escrita_br(
input [31:0] entrada_dados,
input [31:0] memoria_dados,
input [31:0] ULA,
input [25:0] PC,
input [31:0] disk,
input [31:0] arduino,
input [31:0] cause,
input [31:0] pcBckp,
input [2:0] ctrl_mux_escrita_br,
output [31:0] dadoEscrito); |
function [31:0] select;
input [31:0] a0, a1, a2, a3, a4, a5, a6, a7;
input [2:0] s;
case(s)
3'b000: select = a0;
3'b001: select = a1;
3'b010: select = a2;
3'b011: select = a3;
3'b100: select = a4;
3'b101: select = a5;
3'b110: select = a6;
3'b111: select = a7;
endcase
endfunction
assign dadoEscrito = select(ULA, memoria_dados, entrada_dados, PC + 32'd1, disk, arduino, cause, pcBckp, ctrl_mux_escrita_br);
endmodule | 0 |
141,708 | data/full_repos/permissive/95938920/src/main/modules/multiplexador_escrita_br/multiplexador_escrita_br.v | 95,938,920 | multiplexador_escrita_br.v | v | 29 | 128 | [] | [] | [] | [(1, 28)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/multiplexador_escrita_br/multiplexador_escrita_br.v:27: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'PC\' generates 26 bits.\n : ... In instance multiplexador_escrita_br\n assign dadoEscrito = select(ULA, memoria_dados, entrada_dados, PC + 32\'d1, disk, arduino, cause, pcBckp, ctrl_mux_escrita_br);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,322 | function | function [31:0] select;
input [31:0] a0, a1, a2, a3, a4, a5, a6, a7;
input [2:0] s;
case(s)
3'b000: select = a0;
3'b001: select = a1;
3'b010: select = a2;
3'b011: select = a3;
3'b100: select = a4;
3'b101: select = a5;
3'b110: select = a6;
3'b111: select = a7;
endcase
endfunction | function [31:0] select; |
input [31:0] a0, a1, a2, a3, a4, a5, a6, a7;
input [2:0] s;
case(s)
3'b000: select = a0;
3'b001: select = a1;
3'b010: select = a2;
3'b011: select = a3;
3'b100: select = a4;
3'b101: select = a5;
3'b110: select = a6;
3'b111: select = a7;
endcase
endfunction | 0 |
141,709 | data/full_repos/permissive/95938920/src/main/modules/multiplexador_jal/multiplexador_jal.v | 95,938,920 | multiplexador_jal.v | v | 11 | 46 | [] | [] | [] | [(1, 10)] | null | data/verilator_xmls/1c3ddcb6-388b-4f16-b5a7-33110e356ca9.xml | null | 312,323 | module | module multiplexador_jal(in, ctrl, out);
input [4:0] in;
input ctrl;
output [4:0] out;
assign out = ctrl ? 5'b11111 : in;
endmodule | module multiplexador_jal(in, ctrl, out); |
input [4:0] in;
input ctrl;
output [4:0] out;
assign out = ctrl ? 5'b11111 : in;
endmodule | 0 |
141,710 | data/full_repos/permissive/95938920/src/main/modules/multiplexador_ula/multiplexador_ula.v | 95,938,920 | multiplexador_ula.v | v | 15 | 57 | [] | [] | [] | [(1, 14)] | null | data/verilator_xmls/6f0f2c05-ce9f-46da-93e9-1c5fe44db79d.xml | null | 312,324 | module | module multiplexador_ula(A, B, S, Y);
input [31:0] A;
input [31:0] B;
input S;
output [31:0] Y;
assign Y = S ? A : B;
endmodule | module multiplexador_ula(A, B, S, Y); |
input [31:0] A;
input [31:0] B;
input S;
output [31:0] Y;
assign Y = S ? A : B;
endmodule | 0 |
141,711 | data/full_repos/permissive/95938920/src/main/modules/saida_de_dados/saida_de_dados.v | 95,938,920 | saida_de_dados.v | v | 33 | 79 | [] | [] | [] | [(1, 32)] | null | data/verilator_xmls/7bb12712-5f80-4395-8711-50b5a68e826f.xml | null | 312,326 | module | module saida_de_dados(clock, endereco, dado_de_saida, reset, OUT, D1, D2, D3);
input [31:0] endereco;
input [31:0] dado_de_saida;
output [31:0] D1;
output [31:0] D2;
output [31:0] D3;
input clock;
input OUT;
input reset;
reg[31:0] saidas[2:0];
always @ (posedge clock or posedge reset) begin
if(reset) begin
saidas[0] <= {32 {1'b0}};
saidas[1] <= {32 {1'b0}};
saidas[2] <= {32 {1'b0}};
end else begin
if(OUT)
saidas[endereco] <= dado_de_saida;
end
end
assign D1 = saidas[0];
assign D2 = saidas[1];
assign D3 = saidas[2];
endmodule | module saida_de_dados(clock, endereco, dado_de_saida, reset, OUT, D1, D2, D3); |
input [31:0] endereco;
input [31:0] dado_de_saida;
output [31:0] D1;
output [31:0] D2;
output [31:0] D3;
input clock;
input OUT;
input reset;
reg[31:0] saidas[2:0];
always @ (posedge clock or posedge reset) begin
if(reset) begin
saidas[0] <= {32 {1'b0}};
saidas[1] <= {32 {1'b0}};
saidas[2] <= {32 {1'b0}};
end else begin
if(OUT)
saidas[endereco] <= dado_de_saida;
end
end
assign D1 = saidas[0];
assign D2 = saidas[1];
assign D3 = saidas[2];
endmodule | 0 |
141,712 | data/full_repos/permissive/95938920/src/main/modules/somador_interruptor/somador_interruptor.v | 95,938,920 | somador_interruptor.v | v | 12 | 81 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/3f281248-8124-458f-bf28-a7f219017702.xml | null | 312,327 | module | module somador_interruptor(pc, isInsert, isHalt, pcNext);
input [25:0] pc;
input isInsert;
input isHalt;
output [25:0] pcNext;
assign pcNext = isInsert | isHalt ? pc - 1'b1 : pc;
endmodule | module somador_interruptor(pc, isInsert, isHalt, pcNext); |
input [25:0] pc;
input isInsert;
input isHalt;
output [25:0] pcNext;
assign pcNext = isInsert | isHalt ? pc - 1'b1 : pc;
endmodule | 0 |
141,713 | data/full_repos/permissive/95938920/src/main/modules/somador_pc/somador_pc.v | 95,938,920 | somador_pc.v | v | 26 | 116 | [] | [] | [] | [(1, 25)] | null | data/verilator_xmls/921d85fc-a43f-4214-b911-6a0c20e4158d.xml | null | 312,328 | module | module somador_pc(pc, branch, regAddr, jump, addOp, pcAtual);
input [25:0] pc;
input [25:0] branch;
input [25:0] regAddr;
input [25:0] jump;
input [1:0] addOp;
output [25:0] pcAtual;
function [25:0] select;
input [25:0] pc, branch, regAddr, jump;
input [1:0] s;
case (s)
2'b00: select = pc + 26'd1;
2'b01: select = branch;
2'b10: select = regAddr;
2'b11: select = jump;
endcase
endfunction
assign pcAtual = select(pc, branch, regAddr, jump, addOp);
endmodule | module somador_pc(pc, branch, regAddr, jump, addOp, pcAtual); |
input [25:0] pc;
input [25:0] branch;
input [25:0] regAddr;
input [25:0] jump;
input [1:0] addOp;
output [25:0] pcAtual;
function [25:0] select;
input [25:0] pc, branch, regAddr, jump;
input [1:0] s;
case (s)
2'b00: select = pc + 26'd1;
2'b01: select = branch;
2'b10: select = regAddr;
2'b11: select = jump;
endcase
endfunction
assign pcAtual = select(pc, branch, regAddr, jump, addOp);
endmodule | 0 |
141,714 | data/full_repos/permissive/95938920/src/main/modules/somador_pc/somador_pc.v | 95,938,920 | somador_pc.v | v | 26 | 116 | [] | [] | [] | [(1, 25)] | null | data/verilator_xmls/921d85fc-a43f-4214-b911-6a0c20e4158d.xml | null | 312,328 | function | function [25:0] select;
input [25:0] pc, branch, regAddr, jump;
input [1:0] s;
case (s)
2'b00: select = pc + 26'd1;
2'b01: select = branch;
2'b10: select = regAddr;
2'b11: select = jump;
endcase
endfunction | function [25:0] select; |
input [25:0] pc, branch, regAddr, jump;
input [1:0] s;
case (s)
2'b00: select = pc + 26'd1;
2'b01: select = branch;
2'b10: select = regAddr;
2'b11: select = jump;
endcase
endfunction | 0 |
141,715 | data/full_repos/permissive/95938920/src/main/modules/temporizador/temporizador.v | 95,938,920 | temporizador.v | v | 11 | 40 | [] | [] | [] | [(1, 10)] | null | data/verilator_xmls/16d9bdfe-3791-4397-8a35-c4aab47a180c.xml | null | 312,329 | module | module temporizador(clock, reduzclock);
input clock;
output reduzclock;
reg [4:0] contador;
always @ (posedge clock) begin
contador <= contador + 1'b1;
end
assign reduzclock = contador[4];
endmodule | module temporizador(clock, reduzclock); |
input clock;
output reduzclock;
reg [4:0] contador;
always @ (posedge clock) begin
contador <= contador + 1'b1;
end
assign reduzclock = contador[4];
endmodule | 0 |
141,716 | data/full_repos/permissive/95938920/src/main/modules/unidade_de_controle/unidade_de_controle.v | 95,938,920 | unidade_de_controle.v | v | 168 | 146 | [] | [] | [] | [(1, 167)] | null | data/verilator_xmls/748008b5-1383-4e80-8414-3450cfac56b4.xml | null | 312,330 | module | module unidade_de_controle(isFalse, isInput, intr, rst, rstBios, op, func, inta, regWrite, memWrite, imWrite, diskWrite, arduinoWrite, mmuWrite,
mmuSelect, isRegAluOp, outWrite, isHalt, isInsert, wlcd, reset, userMode, kernelMode, clearIntr, regDest, pcSource, regWrtSelect, aluOp);
input isFalse;
input isInput;
input intr;
input rst;
input rstBios;
input [5:0] op;
input [5:0] func;
output inta;
output regWrite;
output memWrite;
output imWrite;
output diskWrite;
output arduinoWrite;
output mmuWrite;
output mmuSelect;
output isRegAluOp;
output outWrite;
output isHalt;
output isInsert;
output wlcd;
output reset;
output userMode;
output kernelMode;
output clearIntr;
output [1:0] regDest;
output [1:0] pcSource;
output [2:0] regWrtSelect;
output [4:0] aluOp;
wire rtype = ~|op;
wire i_add = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & ~func[1] & ~func[0];
wire i_sub = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & ~func[1] & func[0];
wire i_mul = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & ~func[0];
wire i_div = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & func[0];
wire i_mod = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & ~func[1] & ~func[0];
wire i_and = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & ~func[1] & func[0];
wire i_or = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & func[1] & ~func[0];
wire i_xor = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & func[1] & func[0];
wire i_land = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & ~func[1] & ~func[0];
wire i_lor = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & ~func[1] & func[0];
wire i_sll = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & func[1] & ~func[0];
wire i_srl = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & func[1] & func[0];
wire i_eq = rtype & ~func[5] & ~func[4] & func[3] & func[2] & ~func[1] & ~func[0];
wire i_ne = rtype & ~func[5] & ~func[4] & func[3] & func[2] & ~func[1] & func[0];
wire i_lt = rtype & ~func[5] & ~func[4] & func[3] & func[2] & func[1] & ~func[0];
wire i_let = rtype & ~func[5] & ~func[4] & func[3] & func[2] & func[1] & func[0];
wire i_gt = rtype & ~func[5] & func[4] & ~func[3] & ~func[2] & ~func[1] & ~func[0];
wire i_get = rtype & ~func[5] & func[4] & ~func[3] & ~func[2] & ~func[1] & func[0];
wire i_jr = rtype & ~func[5] & func[4] & ~func[3] & ~func[2] & func[1] & ~func[0];
wire i_addi = ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire i_subi = ~op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire i_muli = ~op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & op[0];
wire i_divi = ~op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire i_modi = ~op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & op[0];
wire i_andi = ~op[5] & ~op[4] & ~op[3] & op[2] & op[1] & ~op[0];
wire i_ori = ~op[5] & ~op[4] & ~op[3] & op[2] & op[1] & op[0];
wire i_xori = ~op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_not = ~op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire i_landi = ~op[5] & ~op[4] & op[3] & ~op[2] & op[1] & ~op[0];
wire i_lori = ~op[5] & ~op[4] & op[3] & ~op[2] & op[1] & op[0];
wire i_slli = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire i_srli = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & op[0];
wire i_mov = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & ~op[0];
wire i_lw = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & op[0];
wire i_li = ~op[5] & op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_la = ~op[5] & op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire i_sw = ~op[5] & op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire i_in = ~op[5] & op[4] & ~op[3] & ~op[2] & op[1] & op[0];
wire i_out = ~op[5] & op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire i_jf = ~op[5] & op[4] & ~op[3] & op[2] & ~op[1] & op[0];
wire i_ldk = ~op[5] & op[4] & ~op[3] & op[2] & op[1] & ~op[0];
wire i_sdk = ~op[5] & op[4] & ~op[3] & op[2] & op[1] & op[0];
wire i_lam = ~op[5] & op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_sam = ~op[5] & op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire i_sim = ~op[5] & op[4] & op[3] & ~op[2] & op[1] & ~op[0];
wire i_mmu_lower_im = ~op[5] & op[4] & op[3] & ~op[2] & op[1] & op[0];
wire i_mmu_upper_im = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire i_mmu_select = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
wire i_lcd = ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire i_lcd_pgms = ~op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
wire i_lcd_curr = op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_gic = op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire i_cic = op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire i_gip = op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & op[0];
wire i_pre_io = op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire i_syscall = op[5] & op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire i_exec = op[5] & op[4] & op[3] & ~op[2] & op[1] & ~op[0];
wire i_exec_again = op[5] & op[4] & op[3] & ~op[2] & op[1] & op[0];
wire i_j = op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire i_jtm = op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
wire i_jal = op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire i_halt = op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
assign inta = i_pre_io | intr;
assign regWrite = i_add | i_sub | i_mul | i_div | i_mod |
i_addi | i_subi | i_muli | i_divi | i_modi |
i_and | i_or | i_xor | i_not |
i_andi | i_ori | i_xori |
i_sll | i_srl |
i_slli | i_srli |
i_mov | i_lw | i_li | i_la | i_in |
i_jal | i_exec | i_exec_again |
i_eq | i_ne | i_lt | i_let | i_gt | i_get |
i_ldk | i_lam | i_gic | i_gip;
assign memWrite = i_sw;
assign imWrite = i_sim;
assign diskWrite = i_sdk;
assign arduinoWrite = i_sam;
assign mmuWrite = i_mmu_lower_im | i_mmu_upper_im;
assign mmuSelect = i_mmu_select;
assign isRegAluOp = i_add | i_sub | i_mul | i_div | i_mod |
i_and | i_or | i_xor |
i_sll | i_srl |
i_mov |
i_eq | i_ne | i_lt | i_let | i_gt | i_get;
assign outWrite = i_out;
assign isHalt = i_halt;
assign isInsert = i_in & isInput;
assign wlcd = i_lcd | i_lcd_pgms | i_lcd_curr;
assign reset = ~rst | rstBios;
assign userMode = i_exec | i_exec_again;
assign kernelMode = i_syscall;
assign clearIntr = i_cic;
assign regDest[0] = i_addi | i_subi | i_muli | i_divi | i_modi |
i_andi | i_ori | i_xori | i_not |
i_slli | i_srli |
i_mov | i_lw | i_li | i_la | i_in |
i_ldk | i_lam | i_gic | i_gip | i_exec | i_exec_again;
assign regDest[1] = i_jal | i_exec | i_exec_again;
assign pcSource[0] = i_j | i_jtm | i_jal | i_exec | i_jf & isFalse;
assign pcSource[1] = i_j | i_jtm | i_jr | i_jal | i_exec | i_syscall | i_exec_again;
assign regWrtSelect[0] = i_lw | i_jal | i_exec | i_exec_again | i_lam | i_gip;
assign regWrtSelect[1] = i_in | i_jal | i_exec | i_exec_again | i_gic | i_gip;
assign regWrtSelect[2] = i_ldk | i_lam | i_gic | i_gip;
assign aluOp[0] = i_sub | i_div | i_sll | i_or | i_lor | i_not |
i_subi | i_divi | i_slli | i_ori | i_lori |
i_li | i_out |
i_ne | i_let | i_get | i_jf;
assign aluOp[1] = i_mul | i_div | i_xor | i_srl | i_lt | i_not |
i_muli | i_divi | i_xori | i_srli | i_let |
i_mov | i_li | i_jr | i_out | i_jf |
i_ldk | i_sim | i_sdk | i_mmu_select | i_syscall | i_exec_again;
assign aluOp[2] = i_mod | i_sll | i_srl | i_land | i_lor | i_gt |
i_modi | i_slli | i_srli | i_landi| i_lori | i_get |
i_mov | i_li | i_jr | i_out | i_jf |
i_ldk | i_sim | i_sdk | i_mmu_select | i_syscall | i_exec_again;
assign aluOp[3] = i_and | i_or | i_xor | i_land | i_lor | i_not |
i_andi | i_ori | i_xori | i_landi| i_lori |
i_mov | i_li | i_jr | i_out | i_jf |
i_ldk | i_sim | i_sdk | i_mmu_select | i_syscall | i_exec_again;
assign aluOp[4] = i_eq | i_ne | i_lt | i_let | i_gt | i_get;
endmodule | module unidade_de_controle(isFalse, isInput, intr, rst, rstBios, op, func, inta, regWrite, memWrite, imWrite, diskWrite, arduinoWrite, mmuWrite,
mmuSelect, isRegAluOp, outWrite, isHalt, isInsert, wlcd, reset, userMode, kernelMode, clearIntr, regDest, pcSource, regWrtSelect, aluOp); |
input isFalse;
input isInput;
input intr;
input rst;
input rstBios;
input [5:0] op;
input [5:0] func;
output inta;
output regWrite;
output memWrite;
output imWrite;
output diskWrite;
output arduinoWrite;
output mmuWrite;
output mmuSelect;
output isRegAluOp;
output outWrite;
output isHalt;
output isInsert;
output wlcd;
output reset;
output userMode;
output kernelMode;
output clearIntr;
output [1:0] regDest;
output [1:0] pcSource;
output [2:0] regWrtSelect;
output [4:0] aluOp;
wire rtype = ~|op;
wire i_add = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & ~func[1] & ~func[0];
wire i_sub = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & ~func[1] & func[0];
wire i_mul = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & ~func[0];
wire i_div = rtype & ~func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & func[0];
wire i_mod = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & ~func[1] & ~func[0];
wire i_and = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & ~func[1] & func[0];
wire i_or = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & func[1] & ~func[0];
wire i_xor = rtype & ~func[5] & ~func[4] & ~func[3] & func[2] & func[1] & func[0];
wire i_land = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & ~func[1] & ~func[0];
wire i_lor = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & ~func[1] & func[0];
wire i_sll = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & func[1] & ~func[0];
wire i_srl = rtype & ~func[5] & ~func[4] & func[3] & ~func[2] & func[1] & func[0];
wire i_eq = rtype & ~func[5] & ~func[4] & func[3] & func[2] & ~func[1] & ~func[0];
wire i_ne = rtype & ~func[5] & ~func[4] & func[3] & func[2] & ~func[1] & func[0];
wire i_lt = rtype & ~func[5] & ~func[4] & func[3] & func[2] & func[1] & ~func[0];
wire i_let = rtype & ~func[5] & ~func[4] & func[3] & func[2] & func[1] & func[0];
wire i_gt = rtype & ~func[5] & func[4] & ~func[3] & ~func[2] & ~func[1] & ~func[0];
wire i_get = rtype & ~func[5] & func[4] & ~func[3] & ~func[2] & ~func[1] & func[0];
wire i_jr = rtype & ~func[5] & func[4] & ~func[3] & ~func[2] & func[1] & ~func[0];
wire i_addi = ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire i_subi = ~op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire i_muli = ~op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & op[0];
wire i_divi = ~op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire i_modi = ~op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & op[0];
wire i_andi = ~op[5] & ~op[4] & ~op[3] & op[2] & op[1] & ~op[0];
wire i_ori = ~op[5] & ~op[4] & ~op[3] & op[2] & op[1] & op[0];
wire i_xori = ~op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_not = ~op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire i_landi = ~op[5] & ~op[4] & op[3] & ~op[2] & op[1] & ~op[0];
wire i_lori = ~op[5] & ~op[4] & op[3] & ~op[2] & op[1] & op[0];
wire i_slli = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire i_srli = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & op[0];
wire i_mov = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & ~op[0];
wire i_lw = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & op[0];
wire i_li = ~op[5] & op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_la = ~op[5] & op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire i_sw = ~op[5] & op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire i_in = ~op[5] & op[4] & ~op[3] & ~op[2] & op[1] & op[0];
wire i_out = ~op[5] & op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire i_jf = ~op[5] & op[4] & ~op[3] & op[2] & ~op[1] & op[0];
wire i_ldk = ~op[5] & op[4] & ~op[3] & op[2] & op[1] & ~op[0];
wire i_sdk = ~op[5] & op[4] & ~op[3] & op[2] & op[1] & op[0];
wire i_lam = ~op[5] & op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_sam = ~op[5] & op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire i_sim = ~op[5] & op[4] & op[3] & ~op[2] & op[1] & ~op[0];
wire i_mmu_lower_im = ~op[5] & op[4] & op[3] & ~op[2] & op[1] & op[0];
wire i_mmu_upper_im = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire i_mmu_select = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
wire i_lcd = ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire i_lcd_pgms = ~op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
wire i_lcd_curr = op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
wire i_gic = op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire i_cic = op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire i_gip = op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & op[0];
wire i_pre_io = op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire i_syscall = op[5] & op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire i_exec = op[5] & op[4] & op[3] & ~op[2] & op[1] & ~op[0];
wire i_exec_again = op[5] & op[4] & op[3] & ~op[2] & op[1] & op[0];
wire i_j = op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire i_jtm = op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
wire i_jal = op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire i_halt = op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
assign inta = i_pre_io | intr;
assign regWrite = i_add | i_sub | i_mul | i_div | i_mod |
i_addi | i_subi | i_muli | i_divi | i_modi |
i_and | i_or | i_xor | i_not |
i_andi | i_ori | i_xori |
i_sll | i_srl |
i_slli | i_srli |
i_mov | i_lw | i_li | i_la | i_in |
i_jal | i_exec | i_exec_again |
i_eq | i_ne | i_lt | i_let | i_gt | i_get |
i_ldk | i_lam | i_gic | i_gip;
assign memWrite = i_sw;
assign imWrite = i_sim;
assign diskWrite = i_sdk;
assign arduinoWrite = i_sam;
assign mmuWrite = i_mmu_lower_im | i_mmu_upper_im;
assign mmuSelect = i_mmu_select;
assign isRegAluOp = i_add | i_sub | i_mul | i_div | i_mod |
i_and | i_or | i_xor |
i_sll | i_srl |
i_mov |
i_eq | i_ne | i_lt | i_let | i_gt | i_get;
assign outWrite = i_out;
assign isHalt = i_halt;
assign isInsert = i_in & isInput;
assign wlcd = i_lcd | i_lcd_pgms | i_lcd_curr;
assign reset = ~rst | rstBios;
assign userMode = i_exec | i_exec_again;
assign kernelMode = i_syscall;
assign clearIntr = i_cic;
assign regDest[0] = i_addi | i_subi | i_muli | i_divi | i_modi |
i_andi | i_ori | i_xori | i_not |
i_slli | i_srli |
i_mov | i_lw | i_li | i_la | i_in |
i_ldk | i_lam | i_gic | i_gip | i_exec | i_exec_again;
assign regDest[1] = i_jal | i_exec | i_exec_again;
assign pcSource[0] = i_j | i_jtm | i_jal | i_exec | i_jf & isFalse;
assign pcSource[1] = i_j | i_jtm | i_jr | i_jal | i_exec | i_syscall | i_exec_again;
assign regWrtSelect[0] = i_lw | i_jal | i_exec | i_exec_again | i_lam | i_gip;
assign regWrtSelect[1] = i_in | i_jal | i_exec | i_exec_again | i_gic | i_gip;
assign regWrtSelect[2] = i_ldk | i_lam | i_gic | i_gip;
assign aluOp[0] = i_sub | i_div | i_sll | i_or | i_lor | i_not |
i_subi | i_divi | i_slli | i_ori | i_lori |
i_li | i_out |
i_ne | i_let | i_get | i_jf;
assign aluOp[1] = i_mul | i_div | i_xor | i_srl | i_lt | i_not |
i_muli | i_divi | i_xori | i_srli | i_let |
i_mov | i_li | i_jr | i_out | i_jf |
i_ldk | i_sim | i_sdk | i_mmu_select | i_syscall | i_exec_again;
assign aluOp[2] = i_mod | i_sll | i_srl | i_land | i_lor | i_gt |
i_modi | i_slli | i_srli | i_landi| i_lori | i_get |
i_mov | i_li | i_jr | i_out | i_jf |
i_ldk | i_sim | i_sdk | i_mmu_select | i_syscall | i_exec_again;
assign aluOp[3] = i_and | i_or | i_xor | i_land | i_lor | i_not |
i_andi | i_ori | i_xori | i_landi| i_lori |
i_mov | i_li | i_jr | i_out | i_jf |
i_ldk | i_sim | i_sdk | i_mmu_select | i_syscall | i_exec_again;
assign aluOp[4] = i_eq | i_ne | i_lt | i_let | i_gt | i_get;
endmodule | 0 |
141,717 | data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v | 95,938,920 | unidade_logica_aritmetica.v | v | 52 | 67 | [] | [] | [] | [(1, 51)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:32: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01100: select = A && B; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:32: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01100: select = A && B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:32: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01100: select = A && B; \n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:33: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01101: select = A || B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:33: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01101: select = A || B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:33: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01101: select = A || B; \n ^\n%Error: Exiting due to 6 warning(s)\n' | 312,331 | module | module unidade_logica_aritmetica(aluOp, A, B, resultado, isFalse);
input [4:0] aluOp;
input [31:0] A;
input [31:0] B;
output [31:0] resultado;
output isFalse;
function [31:0] select;
input[31:0] A, B;
input[4:0] aluOp;
case(aluOp)
5'b00000: select = A + B;
5'b00001: select = A - B;
5'b00010: select = A * B;
5'b00011: select = A / B;
5'b00100: select = A % B;
5'b00101: select = A << B;
5'b00110: select = A >> B;
5'b01000: select = A & B;
5'b01001: select = A | B;
5'b01010: select = A ^ B;
5'b01011: select = ~A;
5'b01100: select = A && B;
5'b01101: select = A || B;
5'b01110: select = A;
5'b01111: select = B;
5'b10000: select = A == B ? 32'd1 : 32'd0;
5'b10001: select = A != B ? 32'd1 : 32'd0;
5'b10010: select = A < B ? 32'd1 : 32'd0;
5'b10011: select = A <= B ? 32'd1 : 32'd0;
5'b10100: select = A > B ? 32'd1 : 32'd0;
5'b10101: select = A >= B ? 32'd1 : 32'd0;
default: select = 32'd0;
endcase
endfunction
assign isFalse = A == 32'd0 ? 1'b1 : 1'b0;
assign resultado = select(A, B, aluOp);
endmodule | module unidade_logica_aritmetica(aluOp, A, B, resultado, isFalse); |
input [4:0] aluOp;
input [31:0] A;
input [31:0] B;
output [31:0] resultado;
output isFalse;
function [31:0] select;
input[31:0] A, B;
input[4:0] aluOp;
case(aluOp)
5'b00000: select = A + B;
5'b00001: select = A - B;
5'b00010: select = A * B;
5'b00011: select = A / B;
5'b00100: select = A % B;
5'b00101: select = A << B;
5'b00110: select = A >> B;
5'b01000: select = A & B;
5'b01001: select = A | B;
5'b01010: select = A ^ B;
5'b01011: select = ~A;
5'b01100: select = A && B;
5'b01101: select = A || B;
5'b01110: select = A;
5'b01111: select = B;
5'b10000: select = A == B ? 32'd1 : 32'd0;
5'b10001: select = A != B ? 32'd1 : 32'd0;
5'b10010: select = A < B ? 32'd1 : 32'd0;
5'b10011: select = A <= B ? 32'd1 : 32'd0;
5'b10100: select = A > B ? 32'd1 : 32'd0;
5'b10101: select = A >= B ? 32'd1 : 32'd0;
default: select = 32'd0;
endcase
endfunction
assign isFalse = A == 32'd0 ? 1'b1 : 1'b0;
assign resultado = select(A, B, aluOp);
endmodule | 0 |
141,718 | data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v | 95,938,920 | unidade_logica_aritmetica.v | v | 52 | 67 | [] | [] | [] | [(1, 51)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:32: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01100: select = A && B; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:32: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01100: select = A && B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:32: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01100: select = A && B; \n ^\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:33: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01101: select = A || B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:33: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01101: select = A || B; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/95938920/src/main/modules/unidade_logica_aritmetica/unidade_logica_aritmetica.v:33: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n : ... In instance unidade_logica_aritmetica\n 5\'b01101: select = A || B; \n ^\n%Error: Exiting due to 6 warning(s)\n' | 312,331 | function | function [31:0] select;
input[31:0] A, B;
input[4:0] aluOp;
case(aluOp)
5'b00000: select = A + B;
5'b00001: select = A - B;
5'b00010: select = A * B;
5'b00011: select = A / B;
5'b00100: select = A % B;
5'b00101: select = A << B;
5'b00110: select = A >> B;
5'b01000: select = A & B;
5'b01001: select = A | B;
5'b01010: select = A ^ B;
5'b01011: select = ~A;
5'b01100: select = A && B;
5'b01101: select = A || B;
5'b01110: select = A;
5'b01111: select = B;
5'b10000: select = A == B ? 32'd1 : 32'd0;
5'b10001: select = A != B ? 32'd1 : 32'd0;
5'b10010: select = A < B ? 32'd1 : 32'd0;
5'b10011: select = A <= B ? 32'd1 : 32'd0;
5'b10100: select = A > B ? 32'd1 : 32'd0;
5'b10101: select = A >= B ? 32'd1 : 32'd0;
default: select = 32'd0;
endcase
endfunction | function [31:0] select; |
input[31:0] A, B;
input[4:0] aluOp;
case(aluOp)
5'b00000: select = A + B;
5'b00001: select = A - B;
5'b00010: select = A * B;
5'b00011: select = A / B;
5'b00100: select = A % B;
5'b00101: select = A << B;
5'b00110: select = A >> B;
5'b01000: select = A & B;
5'b01001: select = A | B;
5'b01010: select = A ^ B;
5'b01011: select = ~A;
5'b01100: select = A && B;
5'b01101: select = A || B;
5'b01110: select = A;
5'b01111: select = B;
5'b10000: select = A == B ? 32'd1 : 32'd0;
5'b10001: select = A != B ? 32'd1 : 32'd0;
5'b10010: select = A < B ? 32'd1 : 32'd0;
5'b10011: select = A <= B ? 32'd1 : 32'd0;
5'b10100: select = A > B ? 32'd1 : 32'd0;
5'b10101: select = A >= B ? 32'd1 : 32'd0;
default: select = 32'd0;
endcase
endfunction | 0 |
141,719 | data/full_repos/permissive/95938920/src/main/modules/watchdog/watchdog.v | 95,938,920 | watchdog.v | v | 17 | 118 | [] | [] | [] | [(1, 16)] | null | data/verilator_xmls/eb186287-f3a7-4718-9c25-456a754f7bb0.xml | null | 312,332 | module | module watchdog(
input clk,
input reset,
input isUser,
input isInsert,
output irq);
localparam COUNTER_WIDTH = 4;
reg [COUNTER_WIDTH-1:0] contador = 0;
always @ (posedge clk) begin
contador <= reset ? {COUNTER_WIDTH{1'b0}} : isUser ? isInsert ? contador : contador + 1'b1 : {COUNTER_WIDTH{1'b0}};
end
assign irq = contador[COUNTER_WIDTH-1];
endmodule | module watchdog(
input clk,
input reset,
input isUser,
input isInsert,
output irq); |
localparam COUNTER_WIDTH = 4;
reg [COUNTER_WIDTH-1:0] contador = 0;
always @ (posedge clk) begin
contador <= reset ? {COUNTER_WIDTH{1'b0}} : isUser ? isInsert ? contador : contador + 1'b1 : {COUNTER_WIDTH{1'b0}};
end
assign irq = contador[COUNTER_WIDTH-1];
endmodule | 0 |
141,720 | data/full_repos/permissive/95960868/LimeSDR-Mini_factory/factory/factory_bb.v | 95,960,868 | factory_bb.v | v | 43 | 35 | [] | [] | [] | [(2, 42)] | null | data/verilator_xmls/0e21101f-db27-4887-87f4-d224fd0d0f8a.xml | null | 312,333 | module | module factory (
bridge_0_address,
bridge_0_byte_enable,
bridge_0_read,
bridge_0_write,
bridge_0_write_data,
bridge_0_acknowledge,
bridge_0_read_data,
clk_clk,
extfifo_of_d,
extfifo_of_wr,
extfifo_of_wrfull,
extfifo_if_d,
extfifo_if_rd,
extfifo_if_rdempty,
extfifo_fifo_rst,
pio_0_export,
reset_reset_n,
scl_export,
sda_export);
input [20:0] bridge_0_address;
input [3:0] bridge_0_byte_enable;
input bridge_0_read;
input bridge_0_write;
input [31:0] bridge_0_write_data;
output bridge_0_acknowledge;
output [31:0] bridge_0_read_data;
input clk_clk;
output [31:0] extfifo_of_d;
output extfifo_of_wr;
input extfifo_of_wrfull;
input [31:0] extfifo_if_d;
output extfifo_if_rd;
input extfifo_if_rdempty;
output extfifo_fifo_rst;
output [7:0] pio_0_export;
input reset_reset_n;
inout scl_export;
inout sda_export;
endmodule | module factory (
bridge_0_address,
bridge_0_byte_enable,
bridge_0_read,
bridge_0_write,
bridge_0_write_data,
bridge_0_acknowledge,
bridge_0_read_data,
clk_clk,
extfifo_of_d,
extfifo_of_wr,
extfifo_of_wrfull,
extfifo_if_d,
extfifo_if_rd,
extfifo_if_rdempty,
extfifo_fifo_rst,
pio_0_export,
reset_reset_n,
scl_export,
sda_export); |
input [20:0] bridge_0_address;
input [3:0] bridge_0_byte_enable;
input bridge_0_read;
input bridge_0_write;
input [31:0] bridge_0_write_data;
output bridge_0_acknowledge;
output [31:0] bridge_0_read_data;
input clk_clk;
output [31:0] extfifo_of_d;
output extfifo_of_wr;
input extfifo_of_wrfull;
input [31:0] extfifo_if_d;
output extfifo_if_rd;
input extfifo_if_rdempty;
output extfifo_fifo_rst;
output [7:0] pio_0_export;
input reset_reset_n;
inout scl_export;
inout sda_export;
endmodule | 48 |
141,722 | data/full_repos/permissive/95960868/LimeSDR-Mini_lms7_trx/lms_ctr/lms_ctr_bb.v | 95,960,868 | lms_ctr_bb.v | v | 59 | 55 | [] | [] | [] | [(2, 58)] | null | data/verilator_xmls/71e104a2-f186-4e67-af17-c73b11c123bc.xml | null | 312,387 | module | module lms_ctr (
clk_clk,
dac_spi_ext_MISO,
dac_spi_ext_MOSI,
dac_spi_ext_SCLK,
dac_spi_ext_SS_n,
exfifo_if_d_export,
exfifo_if_rd_export,
exfifo_if_rdempty_export,
exfifo_of_d_export,
exfifo_of_wr_export,
exfifo_of_wrfull_export,
exfifo_rst_export,
flash_spi_MISO,
flash_spi_MOSI,
flash_spi_SCLK,
flash_spi_SS_n,
fpga_spi_ext_MISO,
fpga_spi_ext_MOSI,
fpga_spi_ext_SCLK,
fpga_spi_ext_SS_n,
i2c_scl_export,
i2c_sda_export,
leds_external_connection_export,
lms_ctr_gpio_external_connection_export,
switch_external_connection_export,
uart_external_connection_rxd,
uart_external_connection_txd);
input clk_clk;
input dac_spi_ext_MISO;
output dac_spi_ext_MOSI;
output dac_spi_ext_SCLK;
output dac_spi_ext_SS_n;
input [31:0] exfifo_if_d_export;
output exfifo_if_rd_export;
input exfifo_if_rdempty_export;
output [31:0] exfifo_of_d_export;
output exfifo_of_wr_export;
input exfifo_of_wrfull_export;
output exfifo_rst_export;
input flash_spi_MISO;
output flash_spi_MOSI;
output flash_spi_SCLK;
output flash_spi_SS_n;
input fpga_spi_ext_MISO;
output fpga_spi_ext_MOSI;
output fpga_spi_ext_SCLK;
output [1:0] fpga_spi_ext_SS_n;
inout i2c_scl_export;
inout i2c_sda_export;
output [7:0] leds_external_connection_export;
output [3:0] lms_ctr_gpio_external_connection_export;
input [7:0] switch_external_connection_export;
input uart_external_connection_rxd;
output uart_external_connection_txd;
endmodule | module lms_ctr (
clk_clk,
dac_spi_ext_MISO,
dac_spi_ext_MOSI,
dac_spi_ext_SCLK,
dac_spi_ext_SS_n,
exfifo_if_d_export,
exfifo_if_rd_export,
exfifo_if_rdempty_export,
exfifo_of_d_export,
exfifo_of_wr_export,
exfifo_of_wrfull_export,
exfifo_rst_export,
flash_spi_MISO,
flash_spi_MOSI,
flash_spi_SCLK,
flash_spi_SS_n,
fpga_spi_ext_MISO,
fpga_spi_ext_MOSI,
fpga_spi_ext_SCLK,
fpga_spi_ext_SS_n,
i2c_scl_export,
i2c_sda_export,
leds_external_connection_export,
lms_ctr_gpio_external_connection_export,
switch_external_connection_export,
uart_external_connection_rxd,
uart_external_connection_txd); |
input clk_clk;
input dac_spi_ext_MISO;
output dac_spi_ext_MOSI;
output dac_spi_ext_SCLK;
output dac_spi_ext_SS_n;
input [31:0] exfifo_if_d_export;
output exfifo_if_rd_export;
input exfifo_if_rdempty_export;
output [31:0] exfifo_of_d_export;
output exfifo_of_wr_export;
input exfifo_of_wrfull_export;
output exfifo_rst_export;
input flash_spi_MISO;
output flash_spi_MOSI;
output flash_spi_SCLK;
output flash_spi_SS_n;
input fpga_spi_ext_MISO;
output fpga_spi_ext_MOSI;
output fpga_spi_ext_SCLK;
output [1:0] fpga_spi_ext_SS_n;
inout i2c_scl_export;
inout i2c_sda_export;
output [7:0] leds_external_connection_export;
output [3:0] lms_ctr_gpio_external_connection_export;
input [7:0] switch_external_connection_export;
input uart_external_connection_rxd;
output uart_external_connection_txd;
endmodule | 48 |
141,730 | data/full_repos/permissive/95978520/sources/modules/BasicTestMemory.v | 95,978,520 | BasicTestMemory.v | v | 318 | 85 | [] | [] | [] | [(2, 316)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95978520/sources/modules/BasicTestMemory.v:297: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'MemDataContent\' generates 32 bits.\n : ... In instance BasicTestMemory\n dispMem[DataAdd] = MemDataContent;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95978520/sources/modules/BasicTestMemory.v:311: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance BasicTestMemory\n MemDataOut = dispMem[DataAdd]; \n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,449 | module | module BasicTestMemory
#(
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
input wire MEMTYPE,
output reg [31:0] MemDataOut,
output reg [31:0] MemInstOut,
output wire [DisplayBufferSize-1:0] DisplayBuffer
);
reg [31:0] mem [1023:0];
reg [7:0] dispMem [DisplayBufferSize/8:0];
genvar i;
generate
for (i = 0; i < DisplayBufferSize/8; i = i + 1) begin
assign DisplayBuffer[(i+1)*8 - 1 : i*8] = dispMem[DisplayBufferSize/8-i-1][7:0];
end
endgenerate
initial begin
mem[0] = 32'ha01ff800;
mem[1] = 32'h903ff800;
mem[2] = 32'h80410800;
mem[3] = 32'ha4620800;
mem[4] = 32'hb0811000;
mem[5] = 32'hb0000800;
mem[6] = 32'ha8000800;
mem[7] = 32'hb0000800;
mem[8] = 32'ha8001000;
mem[9] = 32'hb0000800;
mem[10] = 32'ha8001800;
mem[11] = 32'hb0000800;
mem[12] = 32'ha8002000;
mem[13] = 32'h641f03fc;
mem[14] = 32'ha8a40800;
mem[15] = 32'hb0c30800;
mem[16] = 32'ha4e22800;
mem[17] = 32'hb1011800;
mem[18] = 32'h81252800;
mem[19] = 32'h85290800;
mem[20] = 32'h81433800;
mem[21] = 32'ha5681800;
mem[22] = 32'hb1865000;
mem[23] = 32'hb58c4800;
mem[24] = 32'hb0000800;
mem[25] = 32'ha8002800;
mem[26] = 32'hb0000800;
mem[27] = 32'ha8003000;
mem[28] = 32'hb0000800;
mem[29] = 32'ha8003800;
mem[30] = 32'hb0000800;
mem[31] = 32'ha8004000;
mem[32] = 32'hb0000800;
mem[33] = 32'ha8004800;
mem[34] = 32'hb0000800;
mem[35] = 32'ha8005000;
mem[36] = 32'hb0000800;
mem[37] = 32'ha8005800;
mem[38] = 32'hb0000800;
mem[39] = 32'ha8006000;
mem[40] = 32'h641f03fc;
mem[41] = 32'h81a73000;
mem[42] = 32'h81c92800;
mem[43] = 32'ha9ea2800;
mem[44] = 32'haa0f3800;
mem[45] = 32'h82108000;
mem[46] = 32'h82246800;
mem[47] = 32'h824f7800;
mem[48] = 32'h86526000;
mem[49] = 32'ha6720800;
mem[50] = 32'h96919000;
mem[51] = 32'h8293a000;
mem[52] = 32'hb0000800;
mem[53] = 32'ha8006800;
mem[54] = 32'hb0000800;
mem[55] = 32'ha8007000;
mem[56] = 32'hb0000800;
mem[57] = 32'ha8007800;
mem[58] = 32'hb0000800;
mem[59] = 32'ha8008000;
mem[60] = 32'hb0000800;
mem[61] = 32'ha8008800;
mem[62] = 32'hb0000800;
mem[63] = 32'ha8009000;
mem[64] = 32'hb0000800;
mem[65] = 32'ha8009800;
mem[66] = 32'hb0000800;
mem[67] = 32'ha800a000;
mem[68] = 32'h641f03fc;
mem[69] = 32'hb2b0a000;
mem[70] = 32'hb2b53800;
mem[71] = 32'hbab5a000;
mem[72] = 32'hbab54800;
mem[73] = 32'h86b1a800;
mem[74] = 32'h9ad3a000;
mem[75] = 32'h82d6a800;
mem[76] = 32'ha6f41800;
mem[77] = 32'hb3061000;
mem[78] = 32'hb3251800;
mem[79] = 32'h87397800;
mem[80] = 32'h8744c000;
mem[81] = 32'h8746d000;
mem[82] = 32'h836e6800;
mem[83] = 32'hb39bd800;
mem[84] = 32'hb79cd800;
mem[85] = 32'h8381e000;
mem[86] = 32'hb3afb800;
mem[87] = 32'hbbbdb800;
mem[88] = 32'h83bd7000;
mem[89] = 32'ha3dde000;
mem[90] = 32'habde1000;
mem[91] = 32'hb0000800;
mem[92] = 32'ha800a800;
mem[93] = 32'hb0000800;
mem[94] = 32'ha800b000;
mem[95] = 32'hb0000800;
mem[96] = 32'ha800b800;
mem[97] = 32'hb0000800;
mem[98] = 32'ha800c000;
mem[99] = 32'hb0000800;
mem[100] = 32'ha800c800;
mem[101] = 32'hb0000800;
mem[102] = 32'ha800d000;
mem[103] = 32'hb0000800;
mem[104] = 32'ha800d800;
mem[105] = 32'hb0000800;
mem[106] = 32'ha800e000;
mem[107] = 32'hb0000800;
mem[108] = 32'ha800e800;
mem[109] = 32'hb0000800;
mem[110] = 32'ha800f000;
mem[111] = 32'h641f03fc;
mem[112] = 32'he43f0003;
mem[113] = 32'he8410004;
mem[114] = 32'he462ffff;
mem[115] = 32'he063000f;
mem[116] = 32'hc0830010;
mem[117] = 32'hb0000800;
mem[118] = 32'ha8000800;
mem[119] = 32'hb0000800;
mem[120] = 32'ha8001000;
mem[121] = 32'hb0000800;
mem[122] = 32'ha8001800;
mem[123] = 32'hb0000800;
mem[124] = 32'ha8002000;
mem[125] = 32'h641f03fc;
mem[126] = 32'hc4a4ffe0;
mem[127] = 32'hd0c5003f;
mem[128] = 32'hc0c6007e;
mem[129] = 32'hd4e60080;
mem[130] = 32'hc4e7ff02;
mem[131] = 32'hd91f0007;
mem[132] = 32'he50801fe;
mem[133] = 32'hd12801fe;
mem[134] = 32'hc12903ff;
mem[135] = 32'hd54903fe;
mem[136] = 32'he94a07ff;
mem[137] = 32'hd96a07fe;
mem[138] = 32'he96b0fff;
mem[139] = 32'hf18b0001;
mem[140] = 32'he98c0001;
mem[141] = 32'hb0000800;
mem[142] = 32'ha8002800;
mem[143] = 32'hb0000800;
mem[144] = 32'ha8003000;
mem[145] = 32'hb0000800;
mem[146] = 32'ha8003800;
mem[147] = 32'hb0000800;
mem[148] = 32'ha8004000;
mem[149] = 32'hb0000800;
mem[150] = 32'ha8004800;
mem[151] = 32'hb0000800;
mem[152] = 32'ha8005000;
mem[153] = 32'hb0000800;
mem[154] = 32'ha8005800;
mem[155] = 32'hb0000800;
mem[156] = 32'ha8006000;
mem[157] = 32'h641f03fc;
mem[158] = 32'hc1bfffff;
mem[159] = 32'hf5ad0012;
mem[160] = 32'hc1cd4000;
mem[161] = 32'hc1ee0001;
mem[162] = 32'hc1ef7fff;
mem[163] = 32'hc21fffff;
mem[164] = 32'hf610000f;
mem[165] = 32'hc63f4000;
mem[166] = 32'hf631000e;
mem[167] = 32'hf2510001;
mem[168] = 32'hc2520001;
mem[169] = 32'hf2720001;
mem[170] = 32'hc2730001;
mem[171] = 32'hb0000800;
mem[172] = 32'ha8006800;
mem[173] = 32'hb0000800;
mem[174] = 32'ha8007000;
mem[175] = 32'hb0000800;
mem[176] = 32'ha8007800;
mem[177] = 32'hb0000800;
mem[178] = 32'ha8008000;
mem[179] = 32'hb0000800;
mem[180] = 32'ha8008800;
mem[181] = 32'hb0000800;
mem[182] = 32'ha8009000;
mem[183] = 32'hb0000800;
mem[184] = 32'ha8009800;
mem[185] = 32'hb0000800;
mem[186] = 32'ha800a000;
mem[187] = 32'h641f03fc;
mem[188] = 32'hc69f0001;
mem[189] = 32'hfa94001f;
mem[190] = 32'hf694000b;
mem[191] = 32'hfab4000c;
mem[192] = 32'hf2b5000d;
mem[193] = 32'hc2b51fff;
mem[194] = 32'he2d5ffff;
mem[195] = 32'hf2d60001;
mem[196] = 32'hc2d60001;
mem[197] = 32'hf2f60001;
mem[198] = 32'hc6f7ffff;
mem[199] = 32'he71f03ff;
mem[200] = 32'hf318000f;
mem[201] = 32'heb187fff;
mem[202] = 32'hc73f0001;
mem[203] = 32'hf7390006;
mem[204] = 32'hc75f0001;
mem[205] = 32'hf75a0005;
mem[206] = 32'hc77f0001;
mem[207] = 32'hf77b0004;
mem[208] = 32'hc79f0001;
mem[209] = 32'hf79c0003;
mem[210] = 32'hc7bf0001;
mem[211] = 32'hf7bd0002;
mem[212] = 32'hc7df0001;
mem[213] = 32'hf7de0001;
mem[214] = 32'hb0000800;
mem[215] = 32'ha800a800;
mem[216] = 32'hb0000800;
mem[217] = 32'ha800b000;
mem[218] = 32'hb0000800;
mem[219] = 32'ha800b800;
mem[220] = 32'hb0000800;
mem[221] = 32'ha800c000;
mem[222] = 32'hb0000800;
mem[223] = 32'ha800c800;
mem[224] = 32'hb0000800;
mem[225] = 32'ha800d000;
mem[226] = 32'hb0000800;
mem[227] = 32'ha800d800;
mem[228] = 32'hb0000800;
mem[229] = 32'ha800e000;
mem[230] = 32'hb0000800;
mem[231] = 32'ha800e800;
mem[232] = 32'hb0000800;
mem[233] = 32'ha800f000;
mem[234] = 32'h641f03fc;
mem[235] = 32'h605f0000;
mem[236] = 32'hb0000800;
mem[237] = 32'ha8001000;
mem[238] = 32'h60610005;
mem[239] = 32'hb0000800;
mem[240] = 32'ha8001800;
mem[241] = 32'h641f03fc;
mem[242] = 32'h83fff800;
mem[243] = 32'h83fff800;
mem[244] = 32'h83fff800;
mem[245] = 32'h83fff800;
mem[246] = 32'h83fff800;
mem[247] = 32'h83fff800;
mem[248] = 32'h83fff800;
mem[249] = 32'h83fff800;
mem[250] = 32'h83fff800;
mem[251] = 32'h83fff800;
mem[252] = 32'hffffffff;
mem[253] = 32'hffffffff;
mem[254] = 32'hffffffff;
mem[255] = 32'hffffffff;
end
always @(posedge clk) begin
if (DataWriteEn) begin
if (MEMTYPE) begin
dispMem[DataAdd] = MemDataContent;
end else begin
mem[DataAdd/4] = MemDataContent;
end
end
end
always @(mem, DataAdd, InstAdd, MEMTYPE) begin
MemInstOut = mem[InstAdd/4];
if (MEMTYPE) begin
MemDataOut = dispMem[DataAdd];
end else begin
MemDataOut = mem[DataAdd/4];
end
end
endmodule | module BasicTestMemory
#(
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
input wire MEMTYPE,
output reg [31:0] MemDataOut,
output reg [31:0] MemInstOut,
output wire [DisplayBufferSize-1:0] DisplayBuffer
); |
reg [31:0] mem [1023:0];
reg [7:0] dispMem [DisplayBufferSize/8:0];
genvar i;
generate
for (i = 0; i < DisplayBufferSize/8; i = i + 1) begin
assign DisplayBuffer[(i+1)*8 - 1 : i*8] = dispMem[DisplayBufferSize/8-i-1][7:0];
end
endgenerate
initial begin
mem[0] = 32'ha01ff800;
mem[1] = 32'h903ff800;
mem[2] = 32'h80410800;
mem[3] = 32'ha4620800;
mem[4] = 32'hb0811000;
mem[5] = 32'hb0000800;
mem[6] = 32'ha8000800;
mem[7] = 32'hb0000800;
mem[8] = 32'ha8001000;
mem[9] = 32'hb0000800;
mem[10] = 32'ha8001800;
mem[11] = 32'hb0000800;
mem[12] = 32'ha8002000;
mem[13] = 32'h641f03fc;
mem[14] = 32'ha8a40800;
mem[15] = 32'hb0c30800;
mem[16] = 32'ha4e22800;
mem[17] = 32'hb1011800;
mem[18] = 32'h81252800;
mem[19] = 32'h85290800;
mem[20] = 32'h81433800;
mem[21] = 32'ha5681800;
mem[22] = 32'hb1865000;
mem[23] = 32'hb58c4800;
mem[24] = 32'hb0000800;
mem[25] = 32'ha8002800;
mem[26] = 32'hb0000800;
mem[27] = 32'ha8003000;
mem[28] = 32'hb0000800;
mem[29] = 32'ha8003800;
mem[30] = 32'hb0000800;
mem[31] = 32'ha8004000;
mem[32] = 32'hb0000800;
mem[33] = 32'ha8004800;
mem[34] = 32'hb0000800;
mem[35] = 32'ha8005000;
mem[36] = 32'hb0000800;
mem[37] = 32'ha8005800;
mem[38] = 32'hb0000800;
mem[39] = 32'ha8006000;
mem[40] = 32'h641f03fc;
mem[41] = 32'h81a73000;
mem[42] = 32'h81c92800;
mem[43] = 32'ha9ea2800;
mem[44] = 32'haa0f3800;
mem[45] = 32'h82108000;
mem[46] = 32'h82246800;
mem[47] = 32'h824f7800;
mem[48] = 32'h86526000;
mem[49] = 32'ha6720800;
mem[50] = 32'h96919000;
mem[51] = 32'h8293a000;
mem[52] = 32'hb0000800;
mem[53] = 32'ha8006800;
mem[54] = 32'hb0000800;
mem[55] = 32'ha8007000;
mem[56] = 32'hb0000800;
mem[57] = 32'ha8007800;
mem[58] = 32'hb0000800;
mem[59] = 32'ha8008000;
mem[60] = 32'hb0000800;
mem[61] = 32'ha8008800;
mem[62] = 32'hb0000800;
mem[63] = 32'ha8009000;
mem[64] = 32'hb0000800;
mem[65] = 32'ha8009800;
mem[66] = 32'hb0000800;
mem[67] = 32'ha800a000;
mem[68] = 32'h641f03fc;
mem[69] = 32'hb2b0a000;
mem[70] = 32'hb2b53800;
mem[71] = 32'hbab5a000;
mem[72] = 32'hbab54800;
mem[73] = 32'h86b1a800;
mem[74] = 32'h9ad3a000;
mem[75] = 32'h82d6a800;
mem[76] = 32'ha6f41800;
mem[77] = 32'hb3061000;
mem[78] = 32'hb3251800;
mem[79] = 32'h87397800;
mem[80] = 32'h8744c000;
mem[81] = 32'h8746d000;
mem[82] = 32'h836e6800;
mem[83] = 32'hb39bd800;
mem[84] = 32'hb79cd800;
mem[85] = 32'h8381e000;
mem[86] = 32'hb3afb800;
mem[87] = 32'hbbbdb800;
mem[88] = 32'h83bd7000;
mem[89] = 32'ha3dde000;
mem[90] = 32'habde1000;
mem[91] = 32'hb0000800;
mem[92] = 32'ha800a800;
mem[93] = 32'hb0000800;
mem[94] = 32'ha800b000;
mem[95] = 32'hb0000800;
mem[96] = 32'ha800b800;
mem[97] = 32'hb0000800;
mem[98] = 32'ha800c000;
mem[99] = 32'hb0000800;
mem[100] = 32'ha800c800;
mem[101] = 32'hb0000800;
mem[102] = 32'ha800d000;
mem[103] = 32'hb0000800;
mem[104] = 32'ha800d800;
mem[105] = 32'hb0000800;
mem[106] = 32'ha800e000;
mem[107] = 32'hb0000800;
mem[108] = 32'ha800e800;
mem[109] = 32'hb0000800;
mem[110] = 32'ha800f000;
mem[111] = 32'h641f03fc;
mem[112] = 32'he43f0003;
mem[113] = 32'he8410004;
mem[114] = 32'he462ffff;
mem[115] = 32'he063000f;
mem[116] = 32'hc0830010;
mem[117] = 32'hb0000800;
mem[118] = 32'ha8000800;
mem[119] = 32'hb0000800;
mem[120] = 32'ha8001000;
mem[121] = 32'hb0000800;
mem[122] = 32'ha8001800;
mem[123] = 32'hb0000800;
mem[124] = 32'ha8002000;
mem[125] = 32'h641f03fc;
mem[126] = 32'hc4a4ffe0;
mem[127] = 32'hd0c5003f;
mem[128] = 32'hc0c6007e;
mem[129] = 32'hd4e60080;
mem[130] = 32'hc4e7ff02;
mem[131] = 32'hd91f0007;
mem[132] = 32'he50801fe;
mem[133] = 32'hd12801fe;
mem[134] = 32'hc12903ff;
mem[135] = 32'hd54903fe;
mem[136] = 32'he94a07ff;
mem[137] = 32'hd96a07fe;
mem[138] = 32'he96b0fff;
mem[139] = 32'hf18b0001;
mem[140] = 32'he98c0001;
mem[141] = 32'hb0000800;
mem[142] = 32'ha8002800;
mem[143] = 32'hb0000800;
mem[144] = 32'ha8003000;
mem[145] = 32'hb0000800;
mem[146] = 32'ha8003800;
mem[147] = 32'hb0000800;
mem[148] = 32'ha8004000;
mem[149] = 32'hb0000800;
mem[150] = 32'ha8004800;
mem[151] = 32'hb0000800;
mem[152] = 32'ha8005000;
mem[153] = 32'hb0000800;
mem[154] = 32'ha8005800;
mem[155] = 32'hb0000800;
mem[156] = 32'ha8006000;
mem[157] = 32'h641f03fc;
mem[158] = 32'hc1bfffff;
mem[159] = 32'hf5ad0012;
mem[160] = 32'hc1cd4000;
mem[161] = 32'hc1ee0001;
mem[162] = 32'hc1ef7fff;
mem[163] = 32'hc21fffff;
mem[164] = 32'hf610000f;
mem[165] = 32'hc63f4000;
mem[166] = 32'hf631000e;
mem[167] = 32'hf2510001;
mem[168] = 32'hc2520001;
mem[169] = 32'hf2720001;
mem[170] = 32'hc2730001;
mem[171] = 32'hb0000800;
mem[172] = 32'ha8006800;
mem[173] = 32'hb0000800;
mem[174] = 32'ha8007000;
mem[175] = 32'hb0000800;
mem[176] = 32'ha8007800;
mem[177] = 32'hb0000800;
mem[178] = 32'ha8008000;
mem[179] = 32'hb0000800;
mem[180] = 32'ha8008800;
mem[181] = 32'hb0000800;
mem[182] = 32'ha8009000;
mem[183] = 32'hb0000800;
mem[184] = 32'ha8009800;
mem[185] = 32'hb0000800;
mem[186] = 32'ha800a000;
mem[187] = 32'h641f03fc;
mem[188] = 32'hc69f0001;
mem[189] = 32'hfa94001f;
mem[190] = 32'hf694000b;
mem[191] = 32'hfab4000c;
mem[192] = 32'hf2b5000d;
mem[193] = 32'hc2b51fff;
mem[194] = 32'he2d5ffff;
mem[195] = 32'hf2d60001;
mem[196] = 32'hc2d60001;
mem[197] = 32'hf2f60001;
mem[198] = 32'hc6f7ffff;
mem[199] = 32'he71f03ff;
mem[200] = 32'hf318000f;
mem[201] = 32'heb187fff;
mem[202] = 32'hc73f0001;
mem[203] = 32'hf7390006;
mem[204] = 32'hc75f0001;
mem[205] = 32'hf75a0005;
mem[206] = 32'hc77f0001;
mem[207] = 32'hf77b0004;
mem[208] = 32'hc79f0001;
mem[209] = 32'hf79c0003;
mem[210] = 32'hc7bf0001;
mem[211] = 32'hf7bd0002;
mem[212] = 32'hc7df0001;
mem[213] = 32'hf7de0001;
mem[214] = 32'hb0000800;
mem[215] = 32'ha800a800;
mem[216] = 32'hb0000800;
mem[217] = 32'ha800b000;
mem[218] = 32'hb0000800;
mem[219] = 32'ha800b800;
mem[220] = 32'hb0000800;
mem[221] = 32'ha800c000;
mem[222] = 32'hb0000800;
mem[223] = 32'ha800c800;
mem[224] = 32'hb0000800;
mem[225] = 32'ha800d000;
mem[226] = 32'hb0000800;
mem[227] = 32'ha800d800;
mem[228] = 32'hb0000800;
mem[229] = 32'ha800e000;
mem[230] = 32'hb0000800;
mem[231] = 32'ha800e800;
mem[232] = 32'hb0000800;
mem[233] = 32'ha800f000;
mem[234] = 32'h641f03fc;
mem[235] = 32'h605f0000;
mem[236] = 32'hb0000800;
mem[237] = 32'ha8001000;
mem[238] = 32'h60610005;
mem[239] = 32'hb0000800;
mem[240] = 32'ha8001800;
mem[241] = 32'h641f03fc;
mem[242] = 32'h83fff800;
mem[243] = 32'h83fff800;
mem[244] = 32'h83fff800;
mem[245] = 32'h83fff800;
mem[246] = 32'h83fff800;
mem[247] = 32'h83fff800;
mem[248] = 32'h83fff800;
mem[249] = 32'h83fff800;
mem[250] = 32'h83fff800;
mem[251] = 32'h83fff800;
mem[252] = 32'hffffffff;
mem[253] = 32'hffffffff;
mem[254] = 32'hffffffff;
mem[255] = 32'hffffffff;
end
always @(posedge clk) begin
if (DataWriteEn) begin
if (MEMTYPE) begin
dispMem[DataAdd] = MemDataContent;
end else begin
mem[DataAdd/4] = MemDataContent;
end
end
end
always @(mem, DataAdd, InstAdd, MEMTYPE) begin
MemInstOut = mem[InstAdd/4];
if (MEMTYPE) begin
MemDataOut = dispMem[DataAdd];
end else begin
MemDataOut = mem[DataAdd/4];
end
end
endmodule | 41 |
141,733 | data/full_repos/permissive/95978520/sources/modules/draw.sv | 95,978,520 | draw.sv | sv | 44 | 175 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/95978520/sources/modules/draw.sv:2: Cannot find include file: dispConsts.svh\n`include "dispConsts.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.v\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.sv\n dispConsts.svh\n dispConsts.svh.v\n dispConsts.svh.sv\n obj_dir/dispConsts.svh\n obj_dir/dispConsts.svh.v\n obj_dir/dispConsts.svh.sv\n%Error: Exiting due to 1 error(s)\n' | 312,452 | module | module draw(clk_25M, charBuffer, hSync, vSync, red, green, blue);
input clk_25M;
input [ASCII_SIZE-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
output wire hSync, vSync;
output reg [3-1:0] red, green, blue;
reg [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
wire draw;
wire [32-1:0] hPos, vPos;
hvSyncGen hvInst(clk_25M, hSync, vSync, draw, hPos, vPos);
initial begin
{{red}, {green}, {blue}} = 12'h000;
$readmemb("/home/suyash/vgaCharRom.bin", fontRom);
end
function getXYPixel;
input [32-1:0] hPos, vPos;
input [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
input [8-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
getXYPixel = fontRom[(charBuffer[vPos>>4][hPos>>3])<<4 + (vPos&4'b111)][hPos&3'b111];
endfunction
always @(hPos, vPos) begin
{{red}, {green}, {blue}} = {12{fontRom[(charBuffer[vPos/16][hPos/8])*16 + (vPos&4'b1111)][hPos&3'b111]}};
end
endmodule | module draw(clk_25M, charBuffer, hSync, vSync, red, green, blue); |
input clk_25M;
input [ASCII_SIZE-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
output wire hSync, vSync;
output reg [3-1:0] red, green, blue;
reg [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
wire draw;
wire [32-1:0] hPos, vPos;
hvSyncGen hvInst(clk_25M, hSync, vSync, draw, hPos, vPos);
initial begin
{{red}, {green}, {blue}} = 12'h000;
$readmemb("/home/suyash/vgaCharRom.bin", fontRom);
end
function getXYPixel;
input [32-1:0] hPos, vPos;
input [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
input [8-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
getXYPixel = fontRom[(charBuffer[vPos>>4][hPos>>3])<<4 + (vPos&4'b111)][hPos&3'b111];
endfunction
always @(hPos, vPos) begin
{{red}, {green}, {blue}} = {12{fontRom[(charBuffer[vPos/16][hPos/8])*16 + (vPos&4'b1111)][hPos&3'b111]}};
end
endmodule | 41 |
141,734 | data/full_repos/permissive/95978520/sources/modules/draw.sv | 95,978,520 | draw.sv | sv | 44 | 175 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/95978520/sources/modules/draw.sv:2: Cannot find include file: dispConsts.svh\n`include "dispConsts.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.v\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.sv\n dispConsts.svh\n dispConsts.svh.v\n dispConsts.svh.sv\n obj_dir/dispConsts.svh\n obj_dir/dispConsts.svh.v\n obj_dir/dispConsts.svh.sv\n%Error: Exiting due to 1 error(s)\n' | 312,452 | function | function getXYPixel;
input [32-1:0] hPos, vPos;
input [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
input [8-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
getXYPixel = fontRom[(charBuffer[vPos>>4][hPos>>3])<<4 + (vPos&4'b111)][hPos&3'b111];
endfunction | function getXYPixel; |
input [32-1:0] hPos, vPos;
input [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
input [8-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
getXYPixel = fontRom[(charBuffer[vPos>>4][hPos>>3])<<4 + (vPos&4'b111)][hPos&3'b111];
endfunction | 41 |
141,735 | data/full_repos/permissive/95978520/sources/modules/FAdder.v | 95,978,520 | FAdder.v | v | 64 | 63 | [] | [] | [] | [(6, 17), (19, 31), (33, 45), (47, 55), (57, 63)] | null | data/verilator_xmls/685afab2-7e0c-4598-bb90-2a3cbee07549.xml | null | 312,453 | module | module Rip32(sum_o, cout, a_i, b_i, cin);
input [31:0]a_i;
input [31:0]b_i;
input cin;
output cout;
output [31:0]sum_o;
wire c16, cout;
Rip16 m1(sum_o[15:0], c16, a_i[15:0], b_i[15:0], cin);
Rip16 m2(sum_o[31:16], cout, a_i[31:16], b_i[31:16], c16);
endmodule | module Rip32(sum_o, cout, a_i, b_i, cin); |
input [31:0]a_i;
input [31:0]b_i;
input cin;
output cout;
output [31:0]sum_o;
wire c16, cout;
Rip16 m1(sum_o[15:0], c16, a_i[15:0], b_i[15:0], cin);
Rip16 m2(sum_o[31:16], cout, a_i[31:16], b_i[31:16], c16);
endmodule | 41 |
141,736 | data/full_repos/permissive/95978520/sources/modules/FAdder.v | 95,978,520 | FAdder.v | v | 64 | 63 | [] | [] | [] | [(6, 17), (19, 31), (33, 45), (47, 55), (57, 63)] | null | data/verilator_xmls/685afab2-7e0c-4598-bb90-2a3cbee07549.xml | null | 312,453 | module | module Rip16(sum_o, cout, a_i, b_i, cin);
input [15:0]a_i;
input [15:0]b_i;
input cin;
output cout;
output [15:0]sum_o;
wire c4, c8, c12, cout;
Rip4 m1(sum_o[3:0], c4, a_i[3:0], b_i[3:0], cin);
Rip4 m2(sum_o[7:4], c8, a_i[7:4], b_i[7:4], c4);
Rip4 m3(sum_o[11:8], c12, a_i[11:8], b_i[11:8], c8);
Rip4 m4(sum_o[15:12], cout, a_i[15:12], b_i[15:12], c12);
endmodule | module Rip16(sum_o, cout, a_i, b_i, cin); |
input [15:0]a_i;
input [15:0]b_i;
input cin;
output cout;
output [15:0]sum_o;
wire c4, c8, c12, cout;
Rip4 m1(sum_o[3:0], c4, a_i[3:0], b_i[3:0], cin);
Rip4 m2(sum_o[7:4], c8, a_i[7:4], b_i[7:4], c4);
Rip4 m3(sum_o[11:8], c12, a_i[11:8], b_i[11:8], c8);
Rip4 m4(sum_o[15:12], cout, a_i[15:12], b_i[15:12], c12);
endmodule | 41 |
141,737 | data/full_repos/permissive/95978520/sources/modules/FAdder.v | 95,978,520 | FAdder.v | v | 64 | 63 | [] | [] | [] | [(6, 17), (19, 31), (33, 45), (47, 55), (57, 63)] | null | data/verilator_xmls/685afab2-7e0c-4598-bb90-2a3cbee07549.xml | null | 312,453 | module | module Rip4(sum_o, cout, a_i, b_i, cin);
input [3:0]a_i;
input [3:0]b_i;
input cin;
output cout;
output [3:0]sum_o;
wire c2, c3, c4, cout;
Fa m1(sum_o[0], c2, a_i[0], b_i[0], cin);
Fa m2(sum_o[1], c3, a_i[1], b_i[1], c2);
Fa m3(sum_o[2], c4, a_i[2], b_i[2], c3);
Fa m4(sum_o[3], cout, a_i[3], b_i[3], c4);
endmodule | module Rip4(sum_o, cout, a_i, b_i, cin); |
input [3:0]a_i;
input [3:0]b_i;
input cin;
output cout;
output [3:0]sum_o;
wire c2, c3, c4, cout;
Fa m1(sum_o[0], c2, a_i[0], b_i[0], cin);
Fa m2(sum_o[1], c3, a_i[1], b_i[1], c2);
Fa m3(sum_o[2], c4, a_i[2], b_i[2], c3);
Fa m4(sum_o[3], cout, a_i[3], b_i[3], c4);
endmodule | 41 |
141,738 | data/full_repos/permissive/95978520/sources/modules/FAdder.v | 95,978,520 | FAdder.v | v | 64 | 63 | [] | [] | [] | [(6, 17), (19, 31), (33, 45), (47, 55), (57, 63)] | null | data/verilator_xmls/685afab2-7e0c-4598-bb90-2a3cbee07549.xml | null | 312,453 | module | module Fa(sum_o, cout, a_i, b_i, cin);
input a_i, b_i, cin;
output sum_o, cout;
wire w1, w2, w3;
Ha m1(w1, w2, a_i, b_i);
Ha m2(sum_o, w3, w1, cin);
or m3(cout, w2, w3);
endmodule | module Fa(sum_o, cout, a_i, b_i, cin); |
input a_i, b_i, cin;
output sum_o, cout;
wire w1, w2, w3;
Ha m1(w1, w2, a_i, b_i);
Ha m2(sum_o, w3, w1, cin);
or m3(cout, w2, w3);
endmodule | 41 |
141,739 | data/full_repos/permissive/95978520/sources/modules/FAdder.v | 95,978,520 | FAdder.v | v | 64 | 63 | [] | [] | [] | [(6, 17), (19, 31), (33, 45), (47, 55), (57, 63)] | null | data/verilator_xmls/685afab2-7e0c-4598-bb90-2a3cbee07549.xml | null | 312,453 | module | module Ha(sum_o,cout,a_i,b_i);
input a_i,b_i;
output sum_o,cout;
xor m1(sum_o,a_i,b_i);
and m2(cout,a_i,b_i);
endmodule | module Ha(sum_o,cout,a_i,b_i); |
input a_i,b_i;
output sum_o,cout;
xor m1(sum_o,a_i,b_i);
and m2(cout,a_i,b_i);
endmodule | 41 |
141,740 | data/full_repos/permissive/95978520/sources/modules/hvSyncGen.sv | 95,978,520 | hvSyncGen.sv | sv | 58 | 103 | [] | [] | [] | null | line:19: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/95978520/sources/modules/hvSyncGen.sv:50: syntax error, unexpected ==, expecting ')'\n always @(posedge (hCounter == 0)) begin\n ^~\n%Error: Cannot continue\n" | 312,454 | module | module hvSyncGen(clk_25M, hSync, vSync, draw, hPos, vPos);
input clk_25M;
output hSync, vSync, draw;
output [32-1:0] hPos, vPos;
`ifdef DEBUG
parameter FP_H = 48, H = 640, BP_H = 48, RT_H = 96;
parameter FP_V = 33, V = 480, BP_V = 33, RT_V = 2;
`else
parameter FP_H = 16, H = 640, BP_H = 48, RT_H = 96;
parameter FP_V = 10, V = 480, BP_V = 33, RT_V = 2;
`endif
integer hCounter, vCounter;
function genXSync;
input integer counter, fp, disp, bp, rt;
begin : genXSync_block
genXSync = (counter > disp + fp) && (counter < disp + fp + rt)
? 1'b1 : 1'b0;
end
endfunction
function genDrawPulse;
input integer hCounter, vCounter;
input integer fp_h, h;
input integer fp_v, v;
if ((hCounter - fp_h < h && hCounter > fp_h) && (vCounter - fp_v < v && vCounter > fp_v)) begin
genDrawPulse = 1'b1;
end else begin
genDrawPulse = 1'b0;
end
endfunction
assign hPos = (hCounter < H) ? hCounter : 0;
assign vPos = (vCounter < V) ? vCounter : 0;
assign hSync = genXSync(hCounter, FP_H, H, BP_H, RT_H);
assign vSync = genXSync(vCounter, FP_V, V, BP_V, RT_V);
assign draw = genDrawPulse(hCounter, vCounter, FP_H, H, FP_V, V);
initial begin
hCounter = 0;
vCounter = 0;
end
always @(posedge (hCounter == 0)) begin
vCounter = (vCounter == FP_V + V + BP_V + RT_V) ? 1'b0 : vCounter + 1;
end
always @(posedge clk_25M) begin
hCounter = (hCounter == FP_H + H + BP_H + RT_H) ? 1'b0 : hCounter + 1;
end
endmodule | module hvSyncGen(clk_25M, hSync, vSync, draw, hPos, vPos); |
input clk_25M;
output hSync, vSync, draw;
output [32-1:0] hPos, vPos;
`ifdef DEBUG
parameter FP_H = 48, H = 640, BP_H = 48, RT_H = 96;
parameter FP_V = 33, V = 480, BP_V = 33, RT_V = 2;
`else
parameter FP_H = 16, H = 640, BP_H = 48, RT_H = 96;
parameter FP_V = 10, V = 480, BP_V = 33, RT_V = 2;
`endif
integer hCounter, vCounter;
function genXSync;
input integer counter, fp, disp, bp, rt;
begin : genXSync_block
genXSync = (counter > disp + fp) && (counter < disp + fp + rt)
? 1'b1 : 1'b0;
end
endfunction
function genDrawPulse;
input integer hCounter, vCounter;
input integer fp_h, h;
input integer fp_v, v;
if ((hCounter - fp_h < h && hCounter > fp_h) && (vCounter - fp_v < v && vCounter > fp_v)) begin
genDrawPulse = 1'b1;
end else begin
genDrawPulse = 1'b0;
end
endfunction
assign hPos = (hCounter < H) ? hCounter : 0;
assign vPos = (vCounter < V) ? vCounter : 0;
assign hSync = genXSync(hCounter, FP_H, H, BP_H, RT_H);
assign vSync = genXSync(vCounter, FP_V, V, BP_V, RT_V);
assign draw = genDrawPulse(hCounter, vCounter, FP_H, H, FP_V, V);
initial begin
hCounter = 0;
vCounter = 0;
end
always @(posedge (hCounter == 0)) begin
vCounter = (vCounter == FP_V + V + BP_V + RT_V) ? 1'b0 : vCounter + 1;
end
always @(posedge clk_25M) begin
hCounter = (hCounter == FP_H + H + BP_H + RT_H) ? 1'b0 : hCounter + 1;
end
endmodule | 41 |
141,741 | data/full_repos/permissive/95978520/sources/modules/hvSyncGen.sv | 95,978,520 | hvSyncGen.sv | sv | 58 | 103 | [] | [] | [] | null | line:19: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/95978520/sources/modules/hvSyncGen.sv:50: syntax error, unexpected ==, expecting ')'\n always @(posedge (hCounter == 0)) begin\n ^~\n%Error: Cannot continue\n" | 312,454 | function | function genXSync;
input integer counter, fp, disp, bp, rt;
begin : genXSync_block
genXSync = (counter > disp + fp) && (counter < disp + fp + rt)
? 1'b1 : 1'b0;
end
endfunction | function genXSync; |
input integer counter, fp, disp, bp, rt;
begin : genXSync_block
genXSync = (counter > disp + fp) && (counter < disp + fp + rt)
? 1'b1 : 1'b0;
end
endfunction | 41 |
141,742 | data/full_repos/permissive/95978520/sources/modules/hvSyncGen.sv | 95,978,520 | hvSyncGen.sv | sv | 58 | 103 | [] | [] | [] | null | line:19: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/95978520/sources/modules/hvSyncGen.sv:50: syntax error, unexpected ==, expecting ')'\n always @(posedge (hCounter == 0)) begin\n ^~\n%Error: Cannot continue\n" | 312,454 | function | function genDrawPulse;
input integer hCounter, vCounter;
input integer fp_h, h;
input integer fp_v, v;
if ((hCounter - fp_h < h && hCounter > fp_h) && (vCounter - fp_v < v && vCounter > fp_v)) begin
genDrawPulse = 1'b1;
end else begin
genDrawPulse = 1'b0;
end
endfunction | function genDrawPulse; |
input integer hCounter, vCounter;
input integer fp_h, h;
input integer fp_v, v;
if ((hCounter - fp_h < h && hCounter > fp_h) && (vCounter - fp_v < v && vCounter > fp_v)) begin
genDrawPulse = 1'b1;
end else begin
genDrawPulse = 1'b0;
end
endfunction | 41 |
141,743 | data/full_repos/permissive/95978520/sources/modules/MemoryModule.v | 95,978,520 | MemoryModule.v | v | 33 | 85 | [] | [] | [] | [(3, 32)] | null | data/verilator_xmls/ba2a4cfd-38fb-4673-b475-19ff2b1cc922.xml | null | 312,455 | module | module MemoryModule (
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
output wire [31:0] MemDataOut,
output wire [31:0] MemInstOut
);
reg [31:0] mem [8192:0];
initial begin
end
always @(posedge clk) begin
if (DataWriteEn & !DataReadEn) begin
mem[DataAdd] = MemDataContent;
end
end
assign MemInstOut = mem[InstAdd];
assign MemDataOut = mem[DataAdd];
endmodule | module MemoryModule (
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
output wire [31:0] MemDataOut,
output wire [31:0] MemInstOut
); |
reg [31:0] mem [8192:0];
initial begin
end
always @(posedge clk) begin
if (DataWriteEn & !DataReadEn) begin
mem[DataAdd] = MemDataContent;
end
end
assign MemInstOut = mem[InstAdd];
assign MemDataOut = mem[DataAdd];
endmodule | 41 |
141,745 | data/full_repos/permissive/95978520/sources/modules/PowerOfTwoMemory.v | 95,978,520 | PowerOfTwoMemory.v | v | 76 | 85 | [] | [] | [] | [(2, 74)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95978520/sources/modules/PowerOfTwoMemory.v:55: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'MemDataContent\' generates 32 bits.\n : ... In instance PowerOfTwoMemory\n dispMem[DataAdd] = MemDataContent;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95978520/sources/modules/PowerOfTwoMemory.v:69: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance PowerOfTwoMemory\n MemDataOut = dispMem[DataAdd]; \n ^\n%Error: Exiting due to 2 warning(s)\n' | 312,457 | module | module PowerOfTwoMemory
#(
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
input wire MEMTYPE,
output reg [31:0] MemDataOut,
output reg [31:0] MemInstOut,
output wire [DisplayBufferSize-1:0] DisplayBuffer
);
reg [31:0] mem [1023:0];
reg [7:0] dispMem [DisplayBufferSize/8:0];
genvar i;
generate
for (i = 0; i < DisplayBufferSize/8; i = i + 1) begin
assign DisplayBuffer[(i+1)*8 - 1 : i*8] = dispMem[DisplayBufferSize/8-i-1][7:0];
end
endgenerate
initial begin
mem[0] = 32'h77FF0008;
mem[1] = 32'h77FF0001;
mem[2] = 32'h77FF0001;
mem[3] = 32'h77FF0005;
mem[4] = 32'hD33A0001;
mem[5] = 32'h7BF90001;
mem[6] = 32'h77FF0002;
mem[7] = 32'h031F0000;
mem[8] = 32'h6FFE0000;
mem[9] = 32'hc31f0001;
mem[10] = 32'hC35F0001;
mem[11] = 32'h8318C000;
mem[12] = 32'h77DFFFF7;
mem[13] = 32'h7BF8FFFD;
mem[14] = 32'hC31F0001;
mem[15] = 32'h00000000;
end
always @(posedge clk) begin
if (DataWriteEn) begin
if (MEMTYPE) begin
dispMem[DataAdd] = MemDataContent;
end else begin
mem[DataAdd/4] = MemDataContent;
end
end
end
always @(mem, DataAdd, InstAdd, MEMTYPE) begin
MemInstOut = mem[InstAdd/4];
if (MEMTYPE) begin
MemDataOut = dispMem[DataAdd];
end else begin
MemDataOut = mem[DataAdd/4];
end
end
endmodule | module PowerOfTwoMemory
#(
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
input wire MEMTYPE,
output reg [31:0] MemDataOut,
output reg [31:0] MemInstOut,
output wire [DisplayBufferSize-1:0] DisplayBuffer
); |
reg [31:0] mem [1023:0];
reg [7:0] dispMem [DisplayBufferSize/8:0];
genvar i;
generate
for (i = 0; i < DisplayBufferSize/8; i = i + 1) begin
assign DisplayBuffer[(i+1)*8 - 1 : i*8] = dispMem[DisplayBufferSize/8-i-1][7:0];
end
endgenerate
initial begin
mem[0] = 32'h77FF0008;
mem[1] = 32'h77FF0001;
mem[2] = 32'h77FF0001;
mem[3] = 32'h77FF0005;
mem[4] = 32'hD33A0001;
mem[5] = 32'h7BF90001;
mem[6] = 32'h77FF0002;
mem[7] = 32'h031F0000;
mem[8] = 32'h6FFE0000;
mem[9] = 32'hc31f0001;
mem[10] = 32'hC35F0001;
mem[11] = 32'h8318C000;
mem[12] = 32'h77DFFFF7;
mem[13] = 32'h7BF8FFFD;
mem[14] = 32'hC31F0001;
mem[15] = 32'h00000000;
end
always @(posedge clk) begin
if (DataWriteEn) begin
if (MEMTYPE) begin
dispMem[DataAdd] = MemDataContent;
end else begin
mem[DataAdd/4] = MemDataContent;
end
end
end
always @(mem, DataAdd, InstAdd, MEMTYPE) begin
MemInstOut = mem[InstAdd/4];
if (MEMTYPE) begin
MemDataOut = dispMem[DataAdd];
end else begin
MemDataOut = mem[DataAdd/4];
end
end
endmodule | 41 |
141,746 | data/full_repos/permissive/95978520/sources/modules/Processor.sv | 95,978,520 | Processor.sv | sv | 147 | 112 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/95978520/sources/modules/Processor.sv:2: Cannot find include file: dispConsts.svh\n`include "dispConsts.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.v\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.sv\n dispConsts.svh\n dispConsts.svh.v\n dispConsts.svh.sv\n obj_dir/dispConsts.svh\n obj_dir/dispConsts.svh.v\n obj_dir/dispConsts.svh.sv\n%Error: Exiting due to 1 error(s)\n' | 312,458 | module | module Processor
#(
parameter RstAddr = 32'h80000000,
parameter XAddr = 32'h80000008,
parameter IllOpAddr = 32'h80000004,
parameter XPReg = 5'b11110,
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire RESET,
input wire IRQ,
input wire [ASCII_SIZE-1:0] DisplayBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0]
);
wire [31:0] InstAdd;
wire [31:0] InstData;
wire [31:0] SextC;
wire WERF;
reg [31:0] WD;
wire [31:0] RD1;
wire [31:0] RD2;
wire [2:0] PCSEL;
wire RA2SEL;
wire ASEL;
wire BSEL;
wire [1:0] WDSEL;
wire [5:0] ALUFN;
wire [31:0] aluRes;
wire WR;
wire WASEL;
wire [31:0] MemDataOut;
wire [31:0] a;
wire [31:0] b;
wire [31:0] Rc;
wire [31:0] JT;
wire [31:0] ShftSextC;
wire [31:0] PcIncr;
wire [31:0] branchOffset;
wire MEMTYPE;
wire Z;
assign Rc = InstData[25:21];
assign SextC = {{16{InstData[15]}}, InstData[15:0]};
assign ShftSextC = SextC << 2;
assign JT = {{RD1[31:2]}, {2'b00}};
assign Z = RD1 == 32'h00000000;
ProgramCounter #(32) pc_inst
(
.RESET(RESET),
.clk(clk),
.PCSEL(PCSEL),
.XAddr(XAddr),
.RstAddr(RstAddr),
.IllOpAddr(IllOpAddr),
.IRQ(IRQ),
.JT(JT&32'hfffffffc),
.ShftSextC(ShftSextC),
.pc_o(InstAdd),
.PcIncr(PcIncr),
.branchOffset(branchOffset)
);
assign a = ASEL ? {{1'b0}, {branchOffset[30:0]}} : RD1;
assign b = BSEL ? SextC : RD2;
Alu alu_inst
(
.alufn(ALUFN),
.a(a),
.b(b),
.alu(aluRes),
.z(),
.v(),
.n()
);
always @(aluRes, InstAdd, PcIncr, MemDataOut, WDSEL) begin
case (WDSEL)
2'b00:
WD = {{InstAdd[31]}, {PcIncr[30:0]}};
2'b01:
WD = aluRes;
2'b10:
WD = MemDataOut;
default:
WD = {32{1'b0}};
endcase
end
RegfileModule regFile_inst
(
.clk(clk),
.XPReg(XPReg),
.WASEL(WASEL),
.Ra(InstData[20:16]),
.Rb(InstData[15:11]),
.Rc(InstData[25:21]),
.WERF(WERF),
.RA2SEL(RA2SEL),
.WD(WD),
.RD1(RD1),
.RD2(RD2)
);
SimpleDisplayMemory
#(
256
) mem_inst (
.clk(clk),
.InstAdd({{1'b0}, {InstAdd[30:0]}}),
.DataAdd(aluRes),
.MemDataContent(RD2),
.DataReadEn(~WR),
.DataWriteEn(WR),
.MemDataOut(MemDataOut),
.MemInstOut(InstData),
.DisplayBuffer(DisplayBuffer),
.MEMTYPE(MEMTYPE)
);
CtrlLogicModule ctrl_inst
(
.OPCODE(InstData[31:26]),
.RESET(RESET),
.IRQ(IRQ),
.PCSEL(PCSEL),
.RA2SEL(RA2SEL),
.ASEL(ASEL),
.BSEL(BSEL),
.WDSEL(WDSEL),
.ALUFN(ALUFN),
.MEMTYPE(MEMTYPE),
.pc_31(InstAdd[31]),
.WR(WR),
.WERF(WERF),
.WASEL(WASEL),
.Z(Z)
);
endmodule | module Processor
#(
parameter RstAddr = 32'h80000000,
parameter XAddr = 32'h80000008,
parameter IllOpAddr = 32'h80000004,
parameter XPReg = 5'b11110,
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire RESET,
input wire IRQ,
input wire [ASCII_SIZE-1:0] DisplayBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0]
); |
wire [31:0] InstAdd;
wire [31:0] InstData;
wire [31:0] SextC;
wire WERF;
reg [31:0] WD;
wire [31:0] RD1;
wire [31:0] RD2;
wire [2:0] PCSEL;
wire RA2SEL;
wire ASEL;
wire BSEL;
wire [1:0] WDSEL;
wire [5:0] ALUFN;
wire [31:0] aluRes;
wire WR;
wire WASEL;
wire [31:0] MemDataOut;
wire [31:0] a;
wire [31:0] b;
wire [31:0] Rc;
wire [31:0] JT;
wire [31:0] ShftSextC;
wire [31:0] PcIncr;
wire [31:0] branchOffset;
wire MEMTYPE;
wire Z;
assign Rc = InstData[25:21];
assign SextC = {{16{InstData[15]}}, InstData[15:0]};
assign ShftSextC = SextC << 2;
assign JT = {{RD1[31:2]}, {2'b00}};
assign Z = RD1 == 32'h00000000;
ProgramCounter #(32) pc_inst
(
.RESET(RESET),
.clk(clk),
.PCSEL(PCSEL),
.XAddr(XAddr),
.RstAddr(RstAddr),
.IllOpAddr(IllOpAddr),
.IRQ(IRQ),
.JT(JT&32'hfffffffc),
.ShftSextC(ShftSextC),
.pc_o(InstAdd),
.PcIncr(PcIncr),
.branchOffset(branchOffset)
);
assign a = ASEL ? {{1'b0}, {branchOffset[30:0]}} : RD1;
assign b = BSEL ? SextC : RD2;
Alu alu_inst
(
.alufn(ALUFN),
.a(a),
.b(b),
.alu(aluRes),
.z(),
.v(),
.n()
);
always @(aluRes, InstAdd, PcIncr, MemDataOut, WDSEL) begin
case (WDSEL)
2'b00:
WD = {{InstAdd[31]}, {PcIncr[30:0]}};
2'b01:
WD = aluRes;
2'b10:
WD = MemDataOut;
default:
WD = {32{1'b0}};
endcase
end
RegfileModule regFile_inst
(
.clk(clk),
.XPReg(XPReg),
.WASEL(WASEL),
.Ra(InstData[20:16]),
.Rb(InstData[15:11]),
.Rc(InstData[25:21]),
.WERF(WERF),
.RA2SEL(RA2SEL),
.WD(WD),
.RD1(RD1),
.RD2(RD2)
);
SimpleDisplayMemory
#(
256
) mem_inst (
.clk(clk),
.InstAdd({{1'b0}, {InstAdd[30:0]}}),
.DataAdd(aluRes),
.MemDataContent(RD2),
.DataReadEn(~WR),
.DataWriteEn(WR),
.MemDataOut(MemDataOut),
.MemInstOut(InstData),
.DisplayBuffer(DisplayBuffer),
.MEMTYPE(MEMTYPE)
);
CtrlLogicModule ctrl_inst
(
.OPCODE(InstData[31:26]),
.RESET(RESET),
.IRQ(IRQ),
.PCSEL(PCSEL),
.RA2SEL(RA2SEL),
.ASEL(ASEL),
.BSEL(BSEL),
.WDSEL(WDSEL),
.ALUFN(ALUFN),
.MEMTYPE(MEMTYPE),
.pc_31(InstAdd[31]),
.WR(WR),
.WERF(WERF),
.WASEL(WASEL),
.Z(Z)
);
endmodule | 41 |
141,747 | data/full_repos/permissive/95978520/sources/modules/ProgramCounter.v | 95,978,520 | ProgramCounter.v | v | 54 | 68 | [] | [] | [] | [(3, 52)] | null | data/verilator_xmls/7776923e-9122-4a74-a509-04b2b0feeb15.xml | null | 312,459 | module | module ProgramCounter #(
parameter ARCHITECTURE = 32
)(
input wire RESET,
input wire clk,
input wire [2:0] PCSEL,
input wire [31:0] XAddr,
input wire [31:0] RstAddr,
input wire [31:0] IllOpAddr,
input wire IRQ,
input wire [31:0] JT,
input wire [31:0] ShftSextC,
output wire [ARCHITECTURE-1:0] pc_o,
output wire [31:0] PcIncr,
output wire [31:0] branchOffset
);
reg [31:0] pc;
wire MsbJt;
assign pc_o = RESET ? RstAddr : pc;
assign PcIncr = pc + 32'h00000004;
assign MsbJt = pc[31] ? JT[31] : pc[31];
assign branchOffset = PcIncr + ShftSextC;
always @(posedge clk) begin
if (RESET) begin
pc = RstAddr;
end else if (IRQ & ~pc_o[31]) begin
pc = XAddr;
end else begin
case (PCSEL)
3'b000:
pc = {{pc[31]}, {PcIncr[30:0]}};
3'b001:
pc = {{pc[31]}, {branchOffset[30:0]}};
3'b010:
pc = {{MsbJt}, {JT[30:0]}};
3'b011:
pc = IllOpAddr;
3'b100:
pc = XAddr;
default:
pc = RstAddr;
endcase
end
end
endmodule | module ProgramCounter #(
parameter ARCHITECTURE = 32
)(
input wire RESET,
input wire clk,
input wire [2:0] PCSEL,
input wire [31:0] XAddr,
input wire [31:0] RstAddr,
input wire [31:0] IllOpAddr,
input wire IRQ,
input wire [31:0] JT,
input wire [31:0] ShftSextC,
output wire [ARCHITECTURE-1:0] pc_o,
output wire [31:0] PcIncr,
output wire [31:0] branchOffset
); |
reg [31:0] pc;
wire MsbJt;
assign pc_o = RESET ? RstAddr : pc;
assign PcIncr = pc + 32'h00000004;
assign MsbJt = pc[31] ? JT[31] : pc[31];
assign branchOffset = PcIncr + ShftSextC;
always @(posedge clk) begin
if (RESET) begin
pc = RstAddr;
end else if (IRQ & ~pc_o[31]) begin
pc = XAddr;
end else begin
case (PCSEL)
3'b000:
pc = {{pc[31]}, {PcIncr[30:0]}};
3'b001:
pc = {{pc[31]}, {branchOffset[30:0]}};
3'b010:
pc = {{MsbJt}, {JT[30:0]}};
3'b011:
pc = IllOpAddr;
3'b100:
pc = XAddr;
default:
pc = RstAddr;
endcase
end
end
endmodule | 41 |
141,750 | data/full_repos/permissive/95978520/sources/modules/SimpleDisplayMemory.sv | 95,978,520 | SimpleDisplayMemory.sv | sv | 131 | 85 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/95978520/sources/modules/SimpleDisplayMemory.sv:2: Cannot find include file: dispConsts.svh\n`include "dispConsts.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.v\n data/full_repos/permissive/95978520/sources/modules,data/full_repos/permissive/95978520/dispConsts.svh.sv\n dispConsts.svh\n dispConsts.svh.v\n dispConsts.svh.sv\n obj_dir/dispConsts.svh\n obj_dir/dispConsts.svh.v\n obj_dir/dispConsts.svh.sv\n%Error: Exiting due to 1 error(s)\n' | 312,462 | module | module SimpleDisplayMemory
#(
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
input wire MEMTYPE,
output reg [31:0] MemDataOut,
output reg [31:0] MemInstOut,
output wire [ASCII_SIZE-1:0] DisplayBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0]
);
reg [31:0] mem [1023:0];
reg [ASCII_SIZE-1:0] dispMem [CHARS_VERT*CHARS_HORZ-1:0];
genvar x, y, z;
generate
for (x = 0; x < CHARS_VERT; x++) begin
for (y = 0; y < CHARS_HORZ; y++) begin
assign DisplayBuffer[x][y] = dispMem[x*y];
end
end
endgenerate
integer k = 0;
initial begin
mem [0] = 32'h77ff0030;
mem [1] = 32'h77ff0001;
mem [2] = 32'h77ff0001;
mem [3] = 32'h77ff002d;
mem [4] = 32'h77ff002c;
mem [5] = 32'h00000030;
mem [6] = 32'h00000031;
mem [7] = 32'h00000032;
mem [8] = 32'h00000033;
mem [9] = 32'h00000034;
mem [10] = 32'h00000035;
mem [11] = 32'h00000036;
mem [12] = 32'h00000037;
mem [13] = 32'h00000038;
mem [14] = 32'h00000039;
mem [15] = 32'h00000061;
mem [16] = 32'h00000062;
mem [17] = 32'h00000063;
mem [18] = 32'h00000064;
mem [19] = 32'h00000065;
mem [20] = 32'h00000066;
mem [21] = 32'hc3bd0004;
mem [22] = 32'h673dfffc;
mem [23] = 32'he339000f;
mem [24] = 32'hf3390002;
mem [25] = 32'h63390014;
mem [26] = 32'h03380000;
mem [27] = 32'h633dfffc;
mem [28] = 32'hc3bdfffc;
mem [29] = 32'h6ffc0000;
mem [30] = 32'hc3bd0004;
mem [31] = 32'h66fdfffc;
mem [32] = 32'hc3bd0004;
mem [33] = 32'h671dfffc;
mem [34] = 32'hc3bd0004;
mem [35] = 32'h679dfffc;
mem [36] = 32'hc31f001c;
mem [37] = 32'h779fffef;
mem [38] = 32'hf7390004;
mem [39] = 32'hc318fffc;
mem [40] = 32'hd6f80000;
mem [41] = 32'h77f7fffb;
mem [42] = 32'h639dfffc;
mem [43] = 32'hc3bdfffc;
mem [44] = 32'h631dfffc;
mem [45] = 32'hc3bdfffc;
mem [46] = 32'h62fdfffc;
mem [47] = 32'hc3bdfffc;
mem [48] = 32'h6ffc0000;
mem [49] = 32'hc3bf0c00;
mem [50] = 32'hc37f0c00;
mem [51] = 32'hc33f01ea;
mem [52] = 32'h779fffe9;
mem [53] = 32'hc3ff0000;
mem [54] = 32'h77fffffe;
for (k = 0; k < DisplayBufferSize; k = k + 1) begin
dispMem[k] = 8'h00;
end
end
always @(posedge clk) begin
if (DataWriteEn) begin
if (MEMTYPE) begin
dispMem[DataAdd/4] = MemDataContent;
end else begin
mem[DataAdd/4] = MemDataContent;
end
end
end
always @(mem, DataAdd, InstAdd, MEMTYPE) begin
MemInstOut = mem[InstAdd/4];
if (MEMTYPE) begin
MemDataOut = dispMem[DataAdd/4];
end else begin
MemDataOut = mem[DataAdd/4];
end
end
endmodule | module SimpleDisplayMemory
#(
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire [31:0] InstAdd,
input wire [31:0] DataAdd,
input wire [31:0] MemDataContent,
input wire DataReadEn,
input wire DataWriteEn,
input wire MEMTYPE,
output reg [31:0] MemDataOut,
output reg [31:0] MemInstOut,
output wire [ASCII_SIZE-1:0] DisplayBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0]
); |
reg [31:0] mem [1023:0];
reg [ASCII_SIZE-1:0] dispMem [CHARS_VERT*CHARS_HORZ-1:0];
genvar x, y, z;
generate
for (x = 0; x < CHARS_VERT; x++) begin
for (y = 0; y < CHARS_HORZ; y++) begin
assign DisplayBuffer[x][y] = dispMem[x*y];
end
end
endgenerate
integer k = 0;
initial begin
mem [0] = 32'h77ff0030;
mem [1] = 32'h77ff0001;
mem [2] = 32'h77ff0001;
mem [3] = 32'h77ff002d;
mem [4] = 32'h77ff002c;
mem [5] = 32'h00000030;
mem [6] = 32'h00000031;
mem [7] = 32'h00000032;
mem [8] = 32'h00000033;
mem [9] = 32'h00000034;
mem [10] = 32'h00000035;
mem [11] = 32'h00000036;
mem [12] = 32'h00000037;
mem [13] = 32'h00000038;
mem [14] = 32'h00000039;
mem [15] = 32'h00000061;
mem [16] = 32'h00000062;
mem [17] = 32'h00000063;
mem [18] = 32'h00000064;
mem [19] = 32'h00000065;
mem [20] = 32'h00000066;
mem [21] = 32'hc3bd0004;
mem [22] = 32'h673dfffc;
mem [23] = 32'he339000f;
mem [24] = 32'hf3390002;
mem [25] = 32'h63390014;
mem [26] = 32'h03380000;
mem [27] = 32'h633dfffc;
mem [28] = 32'hc3bdfffc;
mem [29] = 32'h6ffc0000;
mem [30] = 32'hc3bd0004;
mem [31] = 32'h66fdfffc;
mem [32] = 32'hc3bd0004;
mem [33] = 32'h671dfffc;
mem [34] = 32'hc3bd0004;
mem [35] = 32'h679dfffc;
mem [36] = 32'hc31f001c;
mem [37] = 32'h779fffef;
mem [38] = 32'hf7390004;
mem [39] = 32'hc318fffc;
mem [40] = 32'hd6f80000;
mem [41] = 32'h77f7fffb;
mem [42] = 32'h639dfffc;
mem [43] = 32'hc3bdfffc;
mem [44] = 32'h631dfffc;
mem [45] = 32'hc3bdfffc;
mem [46] = 32'h62fdfffc;
mem [47] = 32'hc3bdfffc;
mem [48] = 32'h6ffc0000;
mem [49] = 32'hc3bf0c00;
mem [50] = 32'hc37f0c00;
mem [51] = 32'hc33f01ea;
mem [52] = 32'h779fffe9;
mem [53] = 32'hc3ff0000;
mem [54] = 32'h77fffffe;
for (k = 0; k < DisplayBufferSize; k = k + 1) begin
dispMem[k] = 8'h00;
end
end
always @(posedge clk) begin
if (DataWriteEn) begin
if (MEMTYPE) begin
dispMem[DataAdd/4] = MemDataContent;
end else begin
mem[DataAdd/4] = MemDataContent;
end
end
end
always @(mem, DataAdd, InstAdd, MEMTYPE) begin
MemInstOut = mem[InstAdd/4];
if (MEMTYPE) begin
MemDataOut = dispMem[DataAdd/4];
end else begin
MemDataOut = mem[DataAdd/4];
end
end
endmodule | 41 |
141,754 | data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v | 95,978,520 | pc_testbench.v | v | 42 | 57 | [] | [] | [] | [(3, 41)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i = ~clk_i;\n ^\n%Error: data/full_repos/permissive/95978520/sources/testbench/pc_testbench.v:9: Cannot find file containing module: \'ProgramCounter\'\n ProgramCounter #(32) program_counter_test_instance (\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95978520/sources/testbench,data/full_repos/permissive/95978520/ProgramCounter\n data/full_repos/permissive/95978520/sources/testbench,data/full_repos/permissive/95978520/ProgramCounter.v\n data/full_repos/permissive/95978520/sources/testbench,data/full_repos/permissive/95978520/ProgramCounter.sv\n ProgramCounter\n ProgramCounter.v\n ProgramCounter.sv\n obj_dir/ProgramCounter\n obj_dir/ProgramCounter.v\n obj_dir/ProgramCounter.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,466 | module | module pc_testbench;
parameter ARCHITECTURE = 32;
reg rst_i;
reg clk_i;
wire [ARCHITECTURE-1:0] pc_o;
ProgramCounter #(32) program_counter_test_instance (
.rst_i(rst_i),
.clk_i(clk_i),
.pc_o(pc_o)
);
initial begin
clk_i = 0;
rst_i = 0;
#10
rst_i = 1'b1;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10
rst_i = 1'b0;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
end
endmodule | module pc_testbench; |
parameter ARCHITECTURE = 32;
reg rst_i;
reg clk_i;
wire [ARCHITECTURE-1:0] pc_o;
ProgramCounter #(32) program_counter_test_instance (
.rst_i(rst_i),
.clk_i(clk_i),
.pc_o(pc_o)
);
initial begin
clk_i = 0;
rst_i = 0;
#10
rst_i = 1'b1;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10
rst_i = 1'b0;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
#10 clk_i = ~clk_i;
end
endmodule | 41 |
141,757 | data/full_repos/permissive/95978520/sources/testbench/Shifter_Testbench.v | 95,978,520 | Shifter_Testbench.v | v | 142 | 57 | [] | [] | [] | [(3, 141)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95978520/sources/testbench/Shifter_Testbench.v:133: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/95978520/sources/testbench/Shifter_Testbench.v:24: Cannot find file containing module: \'ShifterModule\'\nShifterModule shft_inst_0 (\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95978520/sources/testbench,data/full_repos/permissive/95978520/ShifterModule\n data/full_repos/permissive/95978520/sources/testbench,data/full_repos/permissive/95978520/ShifterModule.v\n data/full_repos/permissive/95978520/sources/testbench,data/full_repos/permissive/95978520/ShifterModule.sv\n ShifterModule\n ShifterModule.v\n ShifterModule.sv\n obj_dir/ShifterModule\n obj_dir/ShifterModule.v\n obj_dir/ShifterModule.sv\n%Warning-WIDTH: data/full_repos/permissive/95978520/sources/testbench/Shifter_Testbench.v:135: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance Shifter_Testbench\n alufn = {{3\'b0}, {val[i][1:0]}};\n ^\n%Warning-WIDTH: data/full_repos/permissive/95978520/sources/testbench/Shifter_Testbench.v:139: Operator NOT expects 32 bits on the LHS, but LHS\'s EQ generates 1 bits.\n : ... In instance Shifter_Testbench\n isCorrect = ~(shtRes == val[i][99:68]);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,469 | module | module Shifter_Testbench;
reg [5:0] alufn;
reg [31:0] a;
reg [31:0] b;
wire [31:0] s;
wire z;
wire v;
wire n;
wire [31:0] shtRes;
reg [31:0] isCorrect;
reg [31:0] expRes;
reg [99:0] val [95:0];
integer i = 0;
ShifterModule shft_inst_0 (
.alufn(alufn),
.a(a),
.b(b),
.res(shtRes)
);
initial begin
val[0] = 100'h87654321_87654321_00000000_0;
val[1] = 100'h0ECA8642_87654321_00000001_0;
val[2] = 100'h1D950C84_87654321_00000002_0;
val[3] = 100'h3B2A1908_87654321_00000003_0;
val[4] = 100'h76543210_87654321_00000004_0;
val[5] = 100'hECA86420_87654321_00000005_0;
val[6] = 100'hD950C840_87654321_00000006_0;
val[7] = 100'hB2A19080_87654321_00000007_0;
val[8] = 100'h65432100_87654321_00000008_0;
val[9] = 100'hCA864200_87654321_00000009_0;
val[10] = 100'h950C8400_87654321_0000000A_0;
val[11] = 100'h2A190800_87654321_0000000B_0;
val[12] = 100'h54321000_87654321_0000000C_0;
val[13] = 100'hA8642000_87654321_0000000D_0;
val[14] = 100'h50C84000_87654321_0000000E_0;
val[15] = 100'hA1908000_87654321_0000000F_0;
val[16] = 100'h43210000_87654321_00000010_0;
val[17] = 100'h86420000_87654321_00000011_0;
val[18] = 100'h0C840000_87654321_00000012_0;
val[19] = 100'h19080000_87654321_00000013_0;
val[20] = 100'h32100000_87654321_00000014_0;
val[21] = 100'h64200000_87654321_00000015_0;
val[22] = 100'hC8400000_87654321_00000016_0;
val[23] = 100'h90800000_87654321_00000017_0;
val[24] = 100'h21000000_87654321_00000018_0;
val[25] = 100'h42000000_87654321_00000019_0;
val[26] = 100'h84000000_87654321_0000001A_0;
val[27] = 100'h08000000_87654321_0000001B_0;
val[28] = 100'h10000000_87654321_0000001C_0;
val[29] = 100'h20000000_87654321_0000001D_0;
val[30] = 100'h40000000_87654321_0000001E_0;
val[31] = 100'h80000000_87654321_0000001F_0;
val[32] = 100'hFEDCBA98_FEDCBA98_00000000_1;
val[33] = 100'h3F6E5D4C_7EDCBA98_00000001_1;
val[34] = 100'h3FB72EA6_FEDCBA98_00000002_1;
val[35] = 100'h0FDB9753_7EDCBA98_00000003_1;
val[36] = 100'h0FEDCBA9_FEDCBA98_00000004_1;
val[37] = 100'h03F6E5D4_7EDCBA98_00000005_1;
val[38] = 100'h03FB72EA_FEDCBA98_00000006_1;
val[39] = 100'h00FDB975_7EDCBA98_00000007_1;
val[40] = 100'h007EDCBA_7EDCBA98_00000008_1;
val[41] = 100'h007F6E5D_FEDCBA98_00000009_1;
val[42] = 100'h001FB72E_7EDCBA98_0000000A_1;
val[43] = 100'h001FDB97_FEDCBA98_0000000B_1;
val[44] = 100'h0007EDCB_7EDCBA98_0000000C_1;
val[45] = 100'h0007F6E5_FEDCBA98_0000000D_1;
val[46] = 100'h0001FB72_7EDCBA98_0000000E_1;
val[47] = 100'h0001FDB9_FEDCBA98_0000000F_1;
val[48] = 100'h0000FEDC_FEDCBA98_00000010_1;
val[49] = 100'h00003F6E_7EDCBA98_00000011_1;
val[50] = 100'h00003FB7_FEDCBA98_00000012_1;
val[51] = 100'h00000FDB_7EDCBA98_00000013_1;
val[52] = 100'h00000FED_FEDCBA98_00000014_1;
val[53] = 100'h000003F6_7EDCBA98_00000015_1;
val[54] = 100'h000003FB_FEDCBA98_00000016_1;
val[55] = 100'h000000FD_7EDCBA98_00000017_1;
val[56] = 100'h0000007E_7EDCBA98_00000018_1;
val[57] = 100'h0000007F_FEDCBA98_00000019_1;
val[58] = 100'h0000001F_7EDCBA98_0000001A_1;
val[59] = 100'h0000001F_FEDCBA98_0000001B_1;
val[60] = 100'h00000007_7EDCBA98_0000001C_1;
val[61] = 100'h00000007_FEDCBA98_0000001D_1;
val[62] = 100'h00000001_7EDCBA98_0000001E_1;
val[63] = 100'h00000001_FEDCBA98_0000001F_1;
val[64] = 100'h87654321_87654321_00000000_3;
val[65] = 100'h3B2A1908_76543210_00000001_3;
val[66] = 100'hE1D950C8_87654321_00000002_3;
val[67] = 100'h0ECA8642_76543210_00000003_3;
val[68] = 100'hF8765432_87654321_00000004_3;
val[69] = 100'h03B2A190_76543210_00000005_3;
val[70] = 100'hFE1D950C_87654321_00000006_3;
val[71] = 100'h00ECA864_76543210_00000007_3;
val[72] = 100'h00765432_76543210_00000008_3;
val[73] = 100'hFFC3B2A1_87654321_00000009_3;
val[74] = 100'h001D950C_76543210_0000000A_3;
val[75] = 100'hFFF0ECA8_87654321_0000000B_3;
val[76] = 100'h00076543_76543210_0000000C_3;
val[77] = 100'hFFFC3B2A_87654321_0000000D_3;
val[78] = 100'h0001D950_76543210_0000000E_3;
val[79] = 100'hFFFF0ECA_87654321_0000000F_3;
val[80] = 100'hFFFF8765_87654321_00000010_3;
val[81] = 100'h00003B2A_76543210_00000011_3;
val[82] = 100'hFFFFE1D9_87654321_00000012_3;
val[83] = 100'h00000ECA_76543210_00000013_3;
val[84] = 100'hFFFFF876_87654321_00000014_3;
val[85] = 100'h000003B2_76543210_00000015_3;
val[86] = 100'hFFFFFE1D_87654321_00000016_3;
val[87] = 100'h000000EC_76543210_00000017_3;
val[88] = 100'h00000076_76543210_00000018_3;
val[89] = 100'hFFFFFFC3_87654321_00000019_3;
val[90] = 100'h0000001D_76543210_0000001A_3;
val[91] = 100'hFFFFFFF0_87654321_0000001B_3;
val[92] = 100'h00000007_76543210_0000001C_3;
val[93] = 100'hFFFFFFFC_87654321_0000001D_3;
val[94] = 100'h00000001_76543210_0000001E_3;
val[95] = 100'hFFFFFFFF_87654321_0000001F_3;
end
always begin
#10
i = i + 1;
alufn = {{3'b0}, {val[i][1:0]}};
a = val[i][67:36];
b = val[i][35:4];
expRes = val[i][99:68];
isCorrect = ~(shtRes == val[i][99:68]);
end
endmodule | module Shifter_Testbench; |
reg [5:0] alufn;
reg [31:0] a;
reg [31:0] b;
wire [31:0] s;
wire z;
wire v;
wire n;
wire [31:0] shtRes;
reg [31:0] isCorrect;
reg [31:0] expRes;
reg [99:0] val [95:0];
integer i = 0;
ShifterModule shft_inst_0 (
.alufn(alufn),
.a(a),
.b(b),
.res(shtRes)
);
initial begin
val[0] = 100'h87654321_87654321_00000000_0;
val[1] = 100'h0ECA8642_87654321_00000001_0;
val[2] = 100'h1D950C84_87654321_00000002_0;
val[3] = 100'h3B2A1908_87654321_00000003_0;
val[4] = 100'h76543210_87654321_00000004_0;
val[5] = 100'hECA86420_87654321_00000005_0;
val[6] = 100'hD950C840_87654321_00000006_0;
val[7] = 100'hB2A19080_87654321_00000007_0;
val[8] = 100'h65432100_87654321_00000008_0;
val[9] = 100'hCA864200_87654321_00000009_0;
val[10] = 100'h950C8400_87654321_0000000A_0;
val[11] = 100'h2A190800_87654321_0000000B_0;
val[12] = 100'h54321000_87654321_0000000C_0;
val[13] = 100'hA8642000_87654321_0000000D_0;
val[14] = 100'h50C84000_87654321_0000000E_0;
val[15] = 100'hA1908000_87654321_0000000F_0;
val[16] = 100'h43210000_87654321_00000010_0;
val[17] = 100'h86420000_87654321_00000011_0;
val[18] = 100'h0C840000_87654321_00000012_0;
val[19] = 100'h19080000_87654321_00000013_0;
val[20] = 100'h32100000_87654321_00000014_0;
val[21] = 100'h64200000_87654321_00000015_0;
val[22] = 100'hC8400000_87654321_00000016_0;
val[23] = 100'h90800000_87654321_00000017_0;
val[24] = 100'h21000000_87654321_00000018_0;
val[25] = 100'h42000000_87654321_00000019_0;
val[26] = 100'h84000000_87654321_0000001A_0;
val[27] = 100'h08000000_87654321_0000001B_0;
val[28] = 100'h10000000_87654321_0000001C_0;
val[29] = 100'h20000000_87654321_0000001D_0;
val[30] = 100'h40000000_87654321_0000001E_0;
val[31] = 100'h80000000_87654321_0000001F_0;
val[32] = 100'hFEDCBA98_FEDCBA98_00000000_1;
val[33] = 100'h3F6E5D4C_7EDCBA98_00000001_1;
val[34] = 100'h3FB72EA6_FEDCBA98_00000002_1;
val[35] = 100'h0FDB9753_7EDCBA98_00000003_1;
val[36] = 100'h0FEDCBA9_FEDCBA98_00000004_1;
val[37] = 100'h03F6E5D4_7EDCBA98_00000005_1;
val[38] = 100'h03FB72EA_FEDCBA98_00000006_1;
val[39] = 100'h00FDB975_7EDCBA98_00000007_1;
val[40] = 100'h007EDCBA_7EDCBA98_00000008_1;
val[41] = 100'h007F6E5D_FEDCBA98_00000009_1;
val[42] = 100'h001FB72E_7EDCBA98_0000000A_1;
val[43] = 100'h001FDB97_FEDCBA98_0000000B_1;
val[44] = 100'h0007EDCB_7EDCBA98_0000000C_1;
val[45] = 100'h0007F6E5_FEDCBA98_0000000D_1;
val[46] = 100'h0001FB72_7EDCBA98_0000000E_1;
val[47] = 100'h0001FDB9_FEDCBA98_0000000F_1;
val[48] = 100'h0000FEDC_FEDCBA98_00000010_1;
val[49] = 100'h00003F6E_7EDCBA98_00000011_1;
val[50] = 100'h00003FB7_FEDCBA98_00000012_1;
val[51] = 100'h00000FDB_7EDCBA98_00000013_1;
val[52] = 100'h00000FED_FEDCBA98_00000014_1;
val[53] = 100'h000003F6_7EDCBA98_00000015_1;
val[54] = 100'h000003FB_FEDCBA98_00000016_1;
val[55] = 100'h000000FD_7EDCBA98_00000017_1;
val[56] = 100'h0000007E_7EDCBA98_00000018_1;
val[57] = 100'h0000007F_FEDCBA98_00000019_1;
val[58] = 100'h0000001F_7EDCBA98_0000001A_1;
val[59] = 100'h0000001F_FEDCBA98_0000001B_1;
val[60] = 100'h00000007_7EDCBA98_0000001C_1;
val[61] = 100'h00000007_FEDCBA98_0000001D_1;
val[62] = 100'h00000001_7EDCBA98_0000001E_1;
val[63] = 100'h00000001_FEDCBA98_0000001F_1;
val[64] = 100'h87654321_87654321_00000000_3;
val[65] = 100'h3B2A1908_76543210_00000001_3;
val[66] = 100'hE1D950C8_87654321_00000002_3;
val[67] = 100'h0ECA8642_76543210_00000003_3;
val[68] = 100'hF8765432_87654321_00000004_3;
val[69] = 100'h03B2A190_76543210_00000005_3;
val[70] = 100'hFE1D950C_87654321_00000006_3;
val[71] = 100'h00ECA864_76543210_00000007_3;
val[72] = 100'h00765432_76543210_00000008_3;
val[73] = 100'hFFC3B2A1_87654321_00000009_3;
val[74] = 100'h001D950C_76543210_0000000A_3;
val[75] = 100'hFFF0ECA8_87654321_0000000B_3;
val[76] = 100'h00076543_76543210_0000000C_3;
val[77] = 100'hFFFC3B2A_87654321_0000000D_3;
val[78] = 100'h0001D950_76543210_0000000E_3;
val[79] = 100'hFFFF0ECA_87654321_0000000F_3;
val[80] = 100'hFFFF8765_87654321_00000010_3;
val[81] = 100'h00003B2A_76543210_00000011_3;
val[82] = 100'hFFFFE1D9_87654321_00000012_3;
val[83] = 100'h00000ECA_76543210_00000013_3;
val[84] = 100'hFFFFF876_87654321_00000014_3;
val[85] = 100'h000003B2_76543210_00000015_3;
val[86] = 100'hFFFFFE1D_87654321_00000016_3;
val[87] = 100'h000000EC_76543210_00000017_3;
val[88] = 100'h00000076_76543210_00000018_3;
val[89] = 100'hFFFFFFC3_87654321_00000019_3;
val[90] = 100'h0000001D_76543210_0000001A_3;
val[91] = 100'hFFFFFFF0_87654321_0000001B_3;
val[92] = 100'h00000007_76543210_0000001C_3;
val[93] = 100'hFFFFFFFC_87654321_0000001D_3;
val[94] = 100'h00000001_76543210_0000001E_3;
val[95] = 100'hFFFFFFFF_87654321_0000001F_3;
end
always begin
#10
i = i + 1;
alufn = {{3'b0}, {val[i][1:0]}};
a = val[i][67:36];
b = val[i][35:4];
expRes = val[i][99:68];
isCorrect = ~(shtRes == val[i][99:68]);
end
endmodule | 41 |
141,758 | data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v | 95,987,710 | a1csa.v | v | 59 | 78 | [] | ['apache license'] | [] | [(36, 58)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:47: Cannot find file containing module: 'half_adder'\n half_adder f0 (.a(a[0]),.b(b[0]),.s(s0[0]),.cout(carry[0]));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/half_adder\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/half_adder.v\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/half_adder.sv\n half_adder\n half_adder.v\n half_adder.sv\n obj_dir/half_adder\n obj_dir/half_adder.v\n obj_dir/half_adder.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:48: Cannot find file containing module: 'full_adder'\n full_adder f1 (.cin(carry[0]),.a(a[1]),.b(b[1]),.s(s0[1]),.cout(carry[1]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:49: Cannot find file containing module: 'full_adder'\n full_adder f2 (.cin(carry[1]),.a(a[2]),.b(b[2]),.s(s0[2]),.cout(carry[2])); \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:50: Cannot find file containing module: 'full_adder'\n full_adder f3 (.cin(carry[2]),.a(a[3]),.b(b[3]),.s(s0[3]),.cout(gen));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:52: Cannot find file containing module: 'rb0'\n rb0 r0 (.sel(sel),.s(s0[0]),.rs(s[0]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:53: Cannot find file containing module: 'rb1'\n rb1 r1 (.sel(sel),.s(s0[1:0]),.rs(s[1]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:54: Cannot find file containing module: 'rb2'\n rb2 r2 (.sel(sel),.s(s0[2:0]),.rs(s[2]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa.v:55: Cannot find file containing module: 'rb3'\n rb3 r3 (.sel(sel),.s(s0[3:0]),.rs(s[3]));\n ^~~\n%Error: Exiting due to 8 error(s)\n" | 312,470 | module | module a1csa (sel,a,b,s,gen,prop);
parameter n = 4;
input sel;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-1:0] s0,rs,carry;
half_adder f0 (.a(a[0]),.b(b[0]),.s(s0[0]),.cout(carry[0]));
full_adder f1 (.cin(carry[0]),.a(a[1]),.b(b[1]),.s(s0[1]),.cout(carry[1]));
full_adder f2 (.cin(carry[1]),.a(a[2]),.b(b[2]),.s(s0[2]),.cout(carry[2]));
full_adder f3 (.cin(carry[2]),.a(a[3]),.b(b[3]),.s(s0[3]),.cout(gen));
rb0 r0 (.sel(sel),.s(s0[0]),.rs(s[0]));
rb1 r1 (.sel(sel),.s(s0[1:0]),.rs(s[1]));
rb2 r2 (.sel(sel),.s(s0[2:0]),.rs(s[2]));
rb3 r3 (.sel(sel),.s(s0[3:0]),.rs(s[3]));
assign prop = s0[0] & s0[1] & s0[2] & s0[3];
endmodule | module a1csa (sel,a,b,s,gen,prop); |
parameter n = 4;
input sel;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-1:0] s0,rs,carry;
half_adder f0 (.a(a[0]),.b(b[0]),.s(s0[0]),.cout(carry[0]));
full_adder f1 (.cin(carry[0]),.a(a[1]),.b(b[1]),.s(s0[1]),.cout(carry[1]));
full_adder f2 (.cin(carry[1]),.a(a[2]),.b(b[2]),.s(s0[2]),.cout(carry[2]));
full_adder f3 (.cin(carry[2]),.a(a[3]),.b(b[3]),.s(s0[3]),.cout(gen));
rb0 r0 (.sel(sel),.s(s0[0]),.rs(s[0]));
rb1 r1 (.sel(sel),.s(s0[1:0]),.rs(s[1]));
rb2 r2 (.sel(sel),.s(s0[2:0]),.rs(s[2]));
rb3 r3 (.sel(sel),.s(s0[3:0]),.rs(s[3]));
assign prop = s0[0] & s0[1] & s0[2] & s0[3];
endmodule | 0 |
141,759 | data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v | 95,987,710 | a1csa128bits.v | v | 129 | 78 | [] | ['apache license'] | [] | [(21, 128)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:34: Cannot find file containing module: 'a1csa'\n a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:36: Cannot find file containing module: 'a1csa'\n a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:38: Cannot find file containing module: 'a1csa'\n a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:40: Cannot find file containing module: 'a1csa'\n a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:42: Cannot find file containing module: 'a1csa'\n a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:44: Cannot find file containing module: 'a1csa'\n a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:46: Cannot find file containing module: 'a1csa'\n a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:48: Cannot find file containing module: 'a1csa'\n a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:50: Cannot find file containing module: 'a1csa'\n a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:52: Cannot find file containing module: 'a1csa'\n a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:54: Cannot find file containing module: 'a1csa'\n a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:56: Cannot find file containing module: 'a1csa'\n a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:58: Cannot find file containing module: 'a1csa'\n a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:60: Cannot find file containing module: 'a1csa'\n a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:62: Cannot find file containing module: 'a1csa'\n a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:64: Cannot find file containing module: 'a1csa'\n a1csa a1csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:66: Cannot find file containing module: 'a1csa'\n a1csa a1csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:68: Cannot find file containing module: 'a1csa'\n a1csa a1csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:70: Cannot find file containing module: 'a1csa'\n a1csa a1csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:72: Cannot find file containing module: 'a1csa'\n a1csa a1csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:74: Cannot find file containing module: 'a1csa'\n a1csa a1csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:76: Cannot find file containing module: 'a1csa'\n a1csa a1csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:78: Cannot find file containing module: 'a1csa'\n a1csa a1csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:80: Cannot find file containing module: 'a1csa'\n a1csa a1csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:82: Cannot find file containing module: 'a1csa'\n a1csa a1csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:84: Cannot find file containing module: 'a1csa'\n a1csa a1csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:86: Cannot find file containing module: 'a1csa'\n a1csa a1csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:88: Cannot find file containing module: 'a1csa'\n a1csa a1csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:90: Cannot find file containing module: 'a1csa'\n a1csa a1csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:92: Cannot find file containing module: 'a1csa'\n a1csa a1csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa128bits.v:94: Cannot find file containing module: 'a1csa'\n a1csa a1csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124])\n ^~~~~\n%Error: Exiting due to 32 error(s)\n" | 312,471 | module | module a1csa128bits (cin,a,b,s,cout);
parameter n = 128;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])
,.gen(carry[7]),.prop(prop[7]));
a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])
,.gen(carry[8]),.prop(prop[8]));
a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])
,.gen(carry[9]),.prop(prop[9]));
a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])
,.gen(carry[10]),.prop(prop[10]));
a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])
,.gen(carry[11]),.prop(prop[11]));
a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])
,.gen(carry[12]),.prop(prop[12]));
a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])
,.gen(carry[13]),.prop(prop[13]));
a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])
,.gen(carry[14]),.prop(prop[14]));
a1csa a1csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64])
,.gen(carry[15]),.prop(prop[15]));
a1csa a1csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68])
,.gen(carry[16]),.prop(prop[16]));
a1csa a1csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72])
,.gen(carry[17]),.prop(prop[17]));
a1csa a1csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76])
,.gen(carry[18]),.prop(prop[18]));
a1csa a1csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80])
,.gen(carry[19]),.prop(prop[19]));
a1csa a1csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84])
,.gen(carry[20]),.prop(prop[20]));
a1csa a1csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88])
,.gen(carry[21]),.prop(prop[21]));
a1csa a1csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92])
,.gen(carry[22]),.prop(prop[22]));
a1csa a1csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96])
,.gen(carry[23]),.prop(prop[23]));
a1csa a1csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100])
,.gen(carry[24]),.prop(prop[24]));
a1csa a1csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104])
,.gen(carry[25]),.prop(prop[25]));
a1csa a1csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108])
,.gen(carry[26]),.prop(prop[26]));
a1csa a1csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112])
,.gen(carry[27]),.prop(prop[27]));
a1csa a1csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116])
,.gen(carry[28]),.prop(prop[28]));
a1csa a1csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120])
,.gen(carry[29]),.prop(prop[29]));
a1csa a1csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124])
,.gen(carry[30]),.prop(prop[30]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign sel[7] = carry[6] | (prop[6] & sel[6]);
assign sel[8] = carry[7] | (prop[7] & sel[7]);
assign sel[9] = carry[8] | (prop[8] & sel[8]);
assign sel[10] = carry[9] | (prop[9] & sel[9]);
assign sel[11] = carry[10] | (prop[10] & sel[10]);
assign sel[12] = carry[11] | (prop[11] & sel[11]);
assign sel[13] = carry[12] | (prop[12] & sel[12]);
assign sel[14] = carry[13] | (prop[13] & sel[13]);
assign sel[15] = carry[14] | (prop[14] & sel[14]);
assign sel[16] = carry[15] | (prop[15] & sel[15]);
assign sel[17] = carry[16] | (prop[16] & sel[16]);
assign sel[18] = carry[17] | (prop[17] & sel[17]);
assign sel[19] = carry[18] | (prop[18] & sel[18]);
assign sel[20] = carry[19] | (prop[19] & sel[19]);
assign sel[21] = carry[20] | (prop[20] & sel[20]);
assign sel[22] = carry[21] | (prop[21] & sel[21]);
assign sel[23] = carry[22] | (prop[22] & sel[22]);
assign sel[24] = carry[23] | (prop[23] & sel[23]);
assign sel[25] = carry[24] | (prop[24] & sel[24]);
assign sel[26] = carry[25] | (prop[25] & sel[25]);
assign sel[27] = carry[26] | (prop[26] & sel[26]);
assign sel[28] = carry[27] | (prop[27] & sel[27]);
assign sel[29] = carry[28] | (prop[28] & sel[28]);
assign sel[30] = carry[29] | (prop[29] & sel[29]);
assign cout = carry[30] | (prop[30] & sel[30]);
endmodule | module a1csa128bits (cin,a,b,s,cout); |
parameter n = 128;
parameter m = 32;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])
,.gen(carry[7]),.prop(prop[7]));
a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])
,.gen(carry[8]),.prop(prop[8]));
a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])
,.gen(carry[9]),.prop(prop[9]));
a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])
,.gen(carry[10]),.prop(prop[10]));
a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])
,.gen(carry[11]),.prop(prop[11]));
a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])
,.gen(carry[12]),.prop(prop[12]));
a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])
,.gen(carry[13]),.prop(prop[13]));
a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])
,.gen(carry[14]),.prop(prop[14]));
a1csa a1csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64])
,.gen(carry[15]),.prop(prop[15]));
a1csa a1csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68])
,.gen(carry[16]),.prop(prop[16]));
a1csa a1csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72])
,.gen(carry[17]),.prop(prop[17]));
a1csa a1csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76])
,.gen(carry[18]),.prop(prop[18]));
a1csa a1csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80])
,.gen(carry[19]),.prop(prop[19]));
a1csa a1csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84])
,.gen(carry[20]),.prop(prop[20]));
a1csa a1csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88])
,.gen(carry[21]),.prop(prop[21]));
a1csa a1csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92])
,.gen(carry[22]),.prop(prop[22]));
a1csa a1csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96])
,.gen(carry[23]),.prop(prop[23]));
a1csa a1csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100])
,.gen(carry[24]),.prop(prop[24]));
a1csa a1csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104])
,.gen(carry[25]),.prop(prop[25]));
a1csa a1csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108])
,.gen(carry[26]),.prop(prop[26]));
a1csa a1csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112])
,.gen(carry[27]),.prop(prop[27]));
a1csa a1csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116])
,.gen(carry[28]),.prop(prop[28]));
a1csa a1csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120])
,.gen(carry[29]),.prop(prop[29]));
a1csa a1csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124])
,.gen(carry[30]),.prop(prop[30]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign sel[7] = carry[6] | (prop[6] & sel[6]);
assign sel[8] = carry[7] | (prop[7] & sel[7]);
assign sel[9] = carry[8] | (prop[8] & sel[8]);
assign sel[10] = carry[9] | (prop[9] & sel[9]);
assign sel[11] = carry[10] | (prop[10] & sel[10]);
assign sel[12] = carry[11] | (prop[11] & sel[11]);
assign sel[13] = carry[12] | (prop[12] & sel[12]);
assign sel[14] = carry[13] | (prop[13] & sel[13]);
assign sel[15] = carry[14] | (prop[14] & sel[14]);
assign sel[16] = carry[15] | (prop[15] & sel[15]);
assign sel[17] = carry[16] | (prop[16] & sel[16]);
assign sel[18] = carry[17] | (prop[17] & sel[17]);
assign sel[19] = carry[18] | (prop[18] & sel[18]);
assign sel[20] = carry[19] | (prop[19] & sel[19]);
assign sel[21] = carry[20] | (prop[20] & sel[20]);
assign sel[22] = carry[21] | (prop[21] & sel[21]);
assign sel[23] = carry[22] | (prop[22] & sel[22]);
assign sel[24] = carry[23] | (prop[23] & sel[23]);
assign sel[25] = carry[24] | (prop[24] & sel[24]);
assign sel[26] = carry[25] | (prop[25] & sel[25]);
assign sel[27] = carry[26] | (prop[26] & sel[26]);
assign sel[28] = carry[27] | (prop[27] & sel[27]);
assign sel[29] = carry[28] | (prop[28] & sel[28]);
assign sel[30] = carry[29] | (prop[29] & sel[29]);
assign cout = carry[30] | (prop[30] & sel[30]);
endmodule | 0 |
141,760 | data/full_repos/permissive/95987710/rtl/a1csa/a1csa16bits.v | 95,987,710 | a1csa16bits.v | v | 45 | 78 | [] | ['apache license'] | [] | [(21, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa16bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa16bits.v:34: Cannot find file containing module: 'a1csa'\n a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa16bits.v:36: Cannot find file containing module: 'a1csa'\n a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa16bits.v:38: Cannot find file containing module: 'a1csa'\n a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])\n ^~~~~\n%Error: Exiting due to 4 error(s)\n" | 312,472 | module | module a1csa16bits (cin,a,b,s,cout);
parameter n = 16;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign cout = carry[2] | (prop[2] & sel[2]);
endmodule | module a1csa16bits (cin,a,b,s,cout); |
parameter n = 16;
parameter m = 4;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign cout = carry[2] | (prop[2] & sel[2]);
endmodule | 0 |
141,761 | data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v | 95,987,710 | a1csa256bits.v | v | 225 | 78 | [] | ['apache license'] | [] | [(21, 224)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:34: Cannot find file containing module: 'a1csa'\n a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:36: Cannot find file containing module: 'a1csa'\n a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:38: Cannot find file containing module: 'a1csa'\n a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:40: Cannot find file containing module: 'a1csa'\n a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:42: Cannot find file containing module: 'a1csa'\n a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:44: Cannot find file containing module: 'a1csa'\n a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:46: Cannot find file containing module: 'a1csa'\n a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:48: Cannot find file containing module: 'a1csa'\n a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:50: Cannot find file containing module: 'a1csa'\n a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:52: Cannot find file containing module: 'a1csa'\n a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:54: Cannot find file containing module: 'a1csa'\n a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:56: Cannot find file containing module: 'a1csa'\n a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:58: Cannot find file containing module: 'a1csa'\n a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:60: Cannot find file containing module: 'a1csa'\n a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:62: Cannot find file containing module: 'a1csa'\n a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:64: Cannot find file containing module: 'a1csa'\n a1csa a1csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:66: Cannot find file containing module: 'a1csa'\n a1csa a1csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:68: Cannot find file containing module: 'a1csa'\n a1csa a1csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:70: Cannot find file containing module: 'a1csa'\n a1csa a1csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:72: Cannot find file containing module: 'a1csa'\n a1csa a1csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:74: Cannot find file containing module: 'a1csa'\n a1csa a1csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:76: Cannot find file containing module: 'a1csa'\n a1csa a1csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:78: Cannot find file containing module: 'a1csa'\n a1csa a1csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:80: Cannot find file containing module: 'a1csa'\n a1csa a1csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:82: Cannot find file containing module: 'a1csa'\n a1csa a1csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:84: Cannot find file containing module: 'a1csa'\n a1csa a1csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:86: Cannot find file containing module: 'a1csa'\n a1csa a1csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:88: Cannot find file containing module: 'a1csa'\n a1csa a1csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:90: Cannot find file containing module: 'a1csa'\n a1csa a1csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:92: Cannot find file containing module: 'a1csa'\n a1csa a1csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:94: Cannot find file containing module: 'a1csa'\n a1csa a1csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:96: Cannot find file containing module: 'a1csa'\n a1csa a1csa_32 (.sel(sel[31]),.a(a[131:128]),.b(b[131:128]),.s(s[131:128])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:98: Cannot find file containing module: 'a1csa'\n a1csa a1csa_33 (.sel(sel[32]),.a(a[135:132]),.b(b[135:132]),.s(s[135:132])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:100: Cannot find file containing module: 'a1csa'\n a1csa a1csa_34 (.sel(sel[33]),.a(a[139:136]),.b(b[139:136]),.s(s[139:136])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:102: Cannot find file containing module: 'a1csa'\n a1csa a1csa_35 (.sel(sel[34]),.a(a[143:140]),.b(b[143:140]),.s(s[143:140])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:104: Cannot find file containing module: 'a1csa'\n a1csa a1csa_36 (.sel(sel[35]),.a(a[147:144]),.b(b[147:144]),.s(s[147:144])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:106: Cannot find file containing module: 'a1csa'\n a1csa a1csa_37 (.sel(sel[36]),.a(a[151:148]),.b(b[151:148]),.s(s[151:148])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:108: Cannot find file containing module: 'a1csa'\n a1csa a1csa_38 (.sel(sel[37]),.a(a[155:152]),.b(b[155:152]),.s(s[155:152])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:110: Cannot find file containing module: 'a1csa'\n a1csa a1csa_39 (.sel(sel[38]),.a(a[159:156]),.b(b[159:156]),.s(s[159:156])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:112: Cannot find file containing module: 'a1csa'\n a1csa a1csa_40 (.sel(sel[39]),.a(a[163:160]),.b(b[163:160]),.s(s[163:160])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:114: Cannot find file containing module: 'a1csa'\n a1csa a1csa_41 (.sel(sel[40]),.a(a[167:164]),.b(b[167:164]),.s(s[167:164])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:116: Cannot find file containing module: 'a1csa'\n a1csa a1csa_42 (.sel(sel[41]),.a(a[171:168]),.b(b[171:168]),.s(s[171:168])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:118: Cannot find file containing module: 'a1csa'\n a1csa a1csa_43 (.sel(sel[42]),.a(a[175:172]),.b(b[175:172]),.s(s[175:172])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:120: Cannot find file containing module: 'a1csa'\n a1csa a1csa_44 (.sel(sel[43]),.a(a[179:176]),.b(b[179:176]),.s(s[179:176])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:122: Cannot find file containing module: 'a1csa'\n a1csa a1csa_45 (.sel(sel[44]),.a(a[183:180]),.b(b[183:180]),.s(s[183:180])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:124: Cannot find file containing module: 'a1csa'\n a1csa a1csa_46 (.sel(sel[45]),.a(a[187:184]),.b(b[187:184]),.s(s[187:184])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:126: Cannot find file containing module: 'a1csa'\n a1csa a1csa_47 (.sel(sel[46]),.a(a[191:188]),.b(b[191:188]),.s(s[191:188])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:128: Cannot find file containing module: 'a1csa'\n a1csa a1csa_48 (.sel(sel[47]),.a(a[195:192]),.b(b[195:192]),.s(s[195:192])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa256bits.v:130: Cannot find file containing module: 'a1csa'\n a1csa a1csa_49 (.sel(sel[48]),.a(a[199:196]),.b(b[199:196]),.s(s[199:196])\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 312,473 | module | module a1csa256bits (cin,a,b,s,cout);
parameter n = 256;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])
,.gen(carry[7]),.prop(prop[7]));
a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])
,.gen(carry[8]),.prop(prop[8]));
a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])
,.gen(carry[9]),.prop(prop[9]));
a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])
,.gen(carry[10]),.prop(prop[10]));
a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])
,.gen(carry[11]),.prop(prop[11]));
a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])
,.gen(carry[12]),.prop(prop[12]));
a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])
,.gen(carry[13]),.prop(prop[13]));
a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])
,.gen(carry[14]),.prop(prop[14]));
a1csa a1csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64])
,.gen(carry[15]),.prop(prop[15]));
a1csa a1csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68])
,.gen(carry[16]),.prop(prop[16]));
a1csa a1csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72])
,.gen(carry[17]),.prop(prop[17]));
a1csa a1csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76])
,.gen(carry[18]),.prop(prop[18]));
a1csa a1csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80])
,.gen(carry[19]),.prop(prop[19]));
a1csa a1csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84])
,.gen(carry[20]),.prop(prop[20]));
a1csa a1csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88])
,.gen(carry[21]),.prop(prop[21]));
a1csa a1csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92])
,.gen(carry[22]),.prop(prop[22]));
a1csa a1csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96])
,.gen(carry[23]),.prop(prop[23]));
a1csa a1csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100])
,.gen(carry[24]),.prop(prop[24]));
a1csa a1csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104])
,.gen(carry[25]),.prop(prop[25]));
a1csa a1csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108])
,.gen(carry[26]),.prop(prop[26]));
a1csa a1csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112])
,.gen(carry[27]),.prop(prop[27]));
a1csa a1csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116])
,.gen(carry[28]),.prop(prop[28]));
a1csa a1csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120])
,.gen(carry[29]),.prop(prop[29]));
a1csa a1csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124])
,.gen(carry[30]),.prop(prop[30]));
a1csa a1csa_32 (.sel(sel[31]),.a(a[131:128]),.b(b[131:128]),.s(s[131:128])
,.gen(carry[31]),.prop(prop[31]));
a1csa a1csa_33 (.sel(sel[32]),.a(a[135:132]),.b(b[135:132]),.s(s[135:132])
,.gen(carry[32]),.prop(prop[32]));
a1csa a1csa_34 (.sel(sel[33]),.a(a[139:136]),.b(b[139:136]),.s(s[139:136])
,.gen(carry[33]),.prop(prop[33]));
a1csa a1csa_35 (.sel(sel[34]),.a(a[143:140]),.b(b[143:140]),.s(s[143:140])
,.gen(carry[34]),.prop(prop[34]));
a1csa a1csa_36 (.sel(sel[35]),.a(a[147:144]),.b(b[147:144]),.s(s[147:144])
,.gen(carry[35]),.prop(prop[35]));
a1csa a1csa_37 (.sel(sel[36]),.a(a[151:148]),.b(b[151:148]),.s(s[151:148])
,.gen(carry[36]),.prop(prop[36]));
a1csa a1csa_38 (.sel(sel[37]),.a(a[155:152]),.b(b[155:152]),.s(s[155:152])
,.gen(carry[37]),.prop(prop[37]));
a1csa a1csa_39 (.sel(sel[38]),.a(a[159:156]),.b(b[159:156]),.s(s[159:156])
,.gen(carry[38]),.prop(prop[38]));
a1csa a1csa_40 (.sel(sel[39]),.a(a[163:160]),.b(b[163:160]),.s(s[163:160])
,.gen(carry[39]),.prop(prop[39]));
a1csa a1csa_41 (.sel(sel[40]),.a(a[167:164]),.b(b[167:164]),.s(s[167:164])
,.gen(carry[40]),.prop(prop[40]));
a1csa a1csa_42 (.sel(sel[41]),.a(a[171:168]),.b(b[171:168]),.s(s[171:168])
,.gen(carry[41]),.prop(prop[41]));
a1csa a1csa_43 (.sel(sel[42]),.a(a[175:172]),.b(b[175:172]),.s(s[175:172])
,.gen(carry[42]),.prop(prop[42]));
a1csa a1csa_44 (.sel(sel[43]),.a(a[179:176]),.b(b[179:176]),.s(s[179:176])
,.gen(carry[43]),.prop(prop[43]));
a1csa a1csa_45 (.sel(sel[44]),.a(a[183:180]),.b(b[183:180]),.s(s[183:180])
,.gen(carry[44]),.prop(prop[44]));
a1csa a1csa_46 (.sel(sel[45]),.a(a[187:184]),.b(b[187:184]),.s(s[187:184])
,.gen(carry[45]),.prop(prop[45]));
a1csa a1csa_47 (.sel(sel[46]),.a(a[191:188]),.b(b[191:188]),.s(s[191:188])
,.gen(carry[46]),.prop(prop[46]));
a1csa a1csa_48 (.sel(sel[47]),.a(a[195:192]),.b(b[195:192]),.s(s[195:192])
,.gen(carry[47]),.prop(prop[47]));
a1csa a1csa_49 (.sel(sel[48]),.a(a[199:196]),.b(b[199:196]),.s(s[199:196])
,.gen(carry[48]),.prop(prop[48]));
a1csa a1csa_50 (.sel(sel[49]),.a(a[203:200]),.b(b[203:200]),.s(s[203:200])
,.gen(carry[49]),.prop(prop[49]));
a1csa a1csa_51 (.sel(sel[50]),.a(a[207:204]),.b(b[207:204]),.s(s[207:204])
,.gen(carry[50]),.prop(prop[50]));
a1csa a1csa_52 (.sel(sel[51]),.a(a[211:208]),.b(b[211:208]),.s(s[211:208])
,.gen(carry[51]),.prop(prop[51]));
a1csa a1csa_53 (.sel(sel[52]),.a(a[215:212]),.b(b[215:212]),.s(s[215:212])
,.gen(carry[52]),.prop(prop[52]));
a1csa a1csa_54 (.sel(sel[53]),.a(a[219:216]),.b(b[219:216]),.s(s[219:216])
,.gen(carry[53]),.prop(prop[53]));
a1csa a1csa_55 (.sel(sel[54]),.a(a[223:220]),.b(b[223:220]),.s(s[223:220])
,.gen(carry[54]),.prop(prop[54]));
a1csa a1csa_56 (.sel(sel[55]),.a(a[227:224]),.b(b[227:224]),.s(s[227:224])
,.gen(carry[55]),.prop(prop[55]));
a1csa a1csa_57 (.sel(sel[56]),.a(a[231:228]),.b(b[231:228]),.s(s[231:228])
,.gen(carry[56]),.prop(prop[56]));
a1csa a1csa_58 (.sel(sel[57]),.a(a[235:232]),.b(b[235:232]),.s(s[235:232])
,.gen(carry[57]),.prop(prop[57]));
a1csa a1csa_59 (.sel(sel[58]),.a(a[239:236]),.b(b[239:236]),.s(s[239:236])
,.gen(carry[58]),.prop(prop[58]));
a1csa a1csa_60 (.sel(sel[59]),.a(a[243:240]),.b(b[243:240]),.s(s[243:240])
,.gen(carry[59]),.prop(prop[59]));
a1csa a1csa_61 (.sel(sel[60]),.a(a[247:244]),.b(b[247:244]),.s(s[247:244])
,.gen(carry[60]),.prop(prop[60]));
a1csa a1csa_62 (.sel(sel[61]),.a(a[251:248]),.b(b[251:248]),.s(s[251:248])
,.gen(carry[61]),.prop(prop[61]));
a1csa a1csa_63 (.sel(sel[62]),.a(a[255:252]),.b(b[255:252]),.s(s[255:252])
,.gen(carry[62]),.prop(prop[62]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign sel[7] = carry[6] | (prop[6] & sel[6]);
assign sel[8] = carry[7] | (prop[7] & sel[7]);
assign sel[9] = carry[8] | (prop[8] & sel[8]);
assign sel[10] = carry[9] | (prop[9] & sel[9]);
assign sel[11] = carry[10] | (prop[10] & sel[10]);
assign sel[12] = carry[11] | (prop[11] & sel[11]);
assign sel[13] = carry[12] | (prop[12] & sel[12]);
assign sel[14] = carry[13] | (prop[13] & sel[13]);
assign sel[15] = carry[14] | (prop[14] & sel[14]);
assign sel[16] = carry[15] | (prop[15] & sel[15]);
assign sel[17] = carry[16] | (prop[16] & sel[16]);
assign sel[18] = carry[17] | (prop[17] & sel[17]);
assign sel[19] = carry[18] | (prop[18] & sel[18]);
assign sel[20] = carry[19] | (prop[19] & sel[19]);
assign sel[21] = carry[20] | (prop[20] & sel[20]);
assign sel[22] = carry[21] | (prop[21] & sel[21]);
assign sel[23] = carry[22] | (prop[22] & sel[22]);
assign sel[24] = carry[23] | (prop[23] & sel[23]);
assign sel[25] = carry[24] | (prop[24] & sel[24]);
assign sel[26] = carry[25] | (prop[25] & sel[25]);
assign sel[27] = carry[26] | (prop[26] & sel[26]);
assign sel[28] = carry[27] | (prop[27] & sel[27]);
assign sel[29] = carry[28] | (prop[28] & sel[28]);
assign sel[30] = carry[29] | (prop[29] & sel[29]);
assign sel[31] = carry[30] | (prop[30] & sel[30]);
assign sel[32] = carry[31] | (prop[31] & sel[31]);
assign sel[33] = carry[32] | (prop[32] & sel[32]);
assign sel[34] = carry[33] | (prop[33] & sel[33]);
assign sel[35] = carry[34] | (prop[34] & sel[34]);
assign sel[36] = carry[35] | (prop[35] & sel[35]);
assign sel[37] = carry[36] | (prop[36] & sel[36]);
assign sel[38] = carry[37] | (prop[37] & sel[37]);
assign sel[39] = carry[38] | (prop[38] & sel[38]);
assign sel[40] = carry[39] | (prop[39] & sel[39]);
assign sel[41] = carry[40] | (prop[40] & sel[40]);
assign sel[42] = carry[41] | (prop[41] & sel[41]);
assign sel[43] = carry[42] | (prop[42] & sel[42]);
assign sel[44] = carry[43] | (prop[43] & sel[43]);
assign sel[45] = carry[44] | (prop[44] & sel[44]);
assign sel[46] = carry[45] | (prop[45] & sel[45]);
assign sel[47] = carry[46] | (prop[46] & sel[46]);
assign sel[48] = carry[47] | (prop[47] & sel[47]);
assign sel[49] = carry[48] | (prop[48] & sel[48]);
assign sel[50] = carry[49] | (prop[49] & sel[49]);
assign sel[51] = carry[50] | (prop[50] & sel[50]);
assign sel[52] = carry[51] | (prop[51] & sel[51]);
assign sel[53] = carry[52] | (prop[52] & sel[52]);
assign sel[54] = carry[53] | (prop[53] & sel[53]);
assign sel[55] = carry[54] | (prop[54] & sel[54]);
assign sel[56] = carry[55] | (prop[55] & sel[55]);
assign sel[57] = carry[56] | (prop[56] & sel[56]);
assign sel[58] = carry[57] | (prop[57] & sel[57]);
assign sel[59] = carry[58] | (prop[58] & sel[58]);
assign sel[60] = carry[59] | (prop[59] & sel[59]);
assign sel[61] = carry[60] | (prop[60] & sel[60]);
assign sel[62] = carry[61] | (prop[61] & sel[61]);
assign cout = carry[62] | (prop[62] & sel[62]);
endmodule | module a1csa256bits (cin,a,b,s,cout); |
parameter n = 256;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])
,.gen(carry[7]),.prop(prop[7]));
a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])
,.gen(carry[8]),.prop(prop[8]));
a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])
,.gen(carry[9]),.prop(prop[9]));
a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])
,.gen(carry[10]),.prop(prop[10]));
a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])
,.gen(carry[11]),.prop(prop[11]));
a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])
,.gen(carry[12]),.prop(prop[12]));
a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])
,.gen(carry[13]),.prop(prop[13]));
a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])
,.gen(carry[14]),.prop(prop[14]));
a1csa a1csa_16 (.sel(sel[15]),.a(a[67:64]),.b(b[67:64]),.s(s[67:64])
,.gen(carry[15]),.prop(prop[15]));
a1csa a1csa_17 (.sel(sel[16]),.a(a[71:68]),.b(b[71:68]),.s(s[71:68])
,.gen(carry[16]),.prop(prop[16]));
a1csa a1csa_18 (.sel(sel[17]),.a(a[75:72]),.b(b[75:72]),.s(s[75:72])
,.gen(carry[17]),.prop(prop[17]));
a1csa a1csa_19 (.sel(sel[18]),.a(a[79:76]),.b(b[79:76]),.s(s[79:76])
,.gen(carry[18]),.prop(prop[18]));
a1csa a1csa_20 (.sel(sel[19]),.a(a[83:80]),.b(b[83:80]),.s(s[83:80])
,.gen(carry[19]),.prop(prop[19]));
a1csa a1csa_21 (.sel(sel[20]),.a(a[87:84]),.b(b[87:84]),.s(s[87:84])
,.gen(carry[20]),.prop(prop[20]));
a1csa a1csa_22 (.sel(sel[21]),.a(a[91:88]),.b(b[91:88]),.s(s[91:88])
,.gen(carry[21]),.prop(prop[21]));
a1csa a1csa_23 (.sel(sel[22]),.a(a[95:92]),.b(b[95:92]),.s(s[95:92])
,.gen(carry[22]),.prop(prop[22]));
a1csa a1csa_24 (.sel(sel[23]),.a(a[99:96]),.b(b[99:96]),.s(s[99:96])
,.gen(carry[23]),.prop(prop[23]));
a1csa a1csa_25 (.sel(sel[24]),.a(a[103:100]),.b(b[103:100]),.s(s[103:100])
,.gen(carry[24]),.prop(prop[24]));
a1csa a1csa_26 (.sel(sel[25]),.a(a[107:104]),.b(b[107:104]),.s(s[107:104])
,.gen(carry[25]),.prop(prop[25]));
a1csa a1csa_27 (.sel(sel[26]),.a(a[111:108]),.b(b[111:108]),.s(s[111:108])
,.gen(carry[26]),.prop(prop[26]));
a1csa a1csa_28 (.sel(sel[27]),.a(a[115:112]),.b(b[115:112]),.s(s[115:112])
,.gen(carry[27]),.prop(prop[27]));
a1csa a1csa_29 (.sel(sel[28]),.a(a[119:116]),.b(b[119:116]),.s(s[119:116])
,.gen(carry[28]),.prop(prop[28]));
a1csa a1csa_30 (.sel(sel[29]),.a(a[123:120]),.b(b[123:120]),.s(s[123:120])
,.gen(carry[29]),.prop(prop[29]));
a1csa a1csa_31 (.sel(sel[30]),.a(a[127:124]),.b(b[127:124]),.s(s[127:124])
,.gen(carry[30]),.prop(prop[30]));
a1csa a1csa_32 (.sel(sel[31]),.a(a[131:128]),.b(b[131:128]),.s(s[131:128])
,.gen(carry[31]),.prop(prop[31]));
a1csa a1csa_33 (.sel(sel[32]),.a(a[135:132]),.b(b[135:132]),.s(s[135:132])
,.gen(carry[32]),.prop(prop[32]));
a1csa a1csa_34 (.sel(sel[33]),.a(a[139:136]),.b(b[139:136]),.s(s[139:136])
,.gen(carry[33]),.prop(prop[33]));
a1csa a1csa_35 (.sel(sel[34]),.a(a[143:140]),.b(b[143:140]),.s(s[143:140])
,.gen(carry[34]),.prop(prop[34]));
a1csa a1csa_36 (.sel(sel[35]),.a(a[147:144]),.b(b[147:144]),.s(s[147:144])
,.gen(carry[35]),.prop(prop[35]));
a1csa a1csa_37 (.sel(sel[36]),.a(a[151:148]),.b(b[151:148]),.s(s[151:148])
,.gen(carry[36]),.prop(prop[36]));
a1csa a1csa_38 (.sel(sel[37]),.a(a[155:152]),.b(b[155:152]),.s(s[155:152])
,.gen(carry[37]),.prop(prop[37]));
a1csa a1csa_39 (.sel(sel[38]),.a(a[159:156]),.b(b[159:156]),.s(s[159:156])
,.gen(carry[38]),.prop(prop[38]));
a1csa a1csa_40 (.sel(sel[39]),.a(a[163:160]),.b(b[163:160]),.s(s[163:160])
,.gen(carry[39]),.prop(prop[39]));
a1csa a1csa_41 (.sel(sel[40]),.a(a[167:164]),.b(b[167:164]),.s(s[167:164])
,.gen(carry[40]),.prop(prop[40]));
a1csa a1csa_42 (.sel(sel[41]),.a(a[171:168]),.b(b[171:168]),.s(s[171:168])
,.gen(carry[41]),.prop(prop[41]));
a1csa a1csa_43 (.sel(sel[42]),.a(a[175:172]),.b(b[175:172]),.s(s[175:172])
,.gen(carry[42]),.prop(prop[42]));
a1csa a1csa_44 (.sel(sel[43]),.a(a[179:176]),.b(b[179:176]),.s(s[179:176])
,.gen(carry[43]),.prop(prop[43]));
a1csa a1csa_45 (.sel(sel[44]),.a(a[183:180]),.b(b[183:180]),.s(s[183:180])
,.gen(carry[44]),.prop(prop[44]));
a1csa a1csa_46 (.sel(sel[45]),.a(a[187:184]),.b(b[187:184]),.s(s[187:184])
,.gen(carry[45]),.prop(prop[45]));
a1csa a1csa_47 (.sel(sel[46]),.a(a[191:188]),.b(b[191:188]),.s(s[191:188])
,.gen(carry[46]),.prop(prop[46]));
a1csa a1csa_48 (.sel(sel[47]),.a(a[195:192]),.b(b[195:192]),.s(s[195:192])
,.gen(carry[47]),.prop(prop[47]));
a1csa a1csa_49 (.sel(sel[48]),.a(a[199:196]),.b(b[199:196]),.s(s[199:196])
,.gen(carry[48]),.prop(prop[48]));
a1csa a1csa_50 (.sel(sel[49]),.a(a[203:200]),.b(b[203:200]),.s(s[203:200])
,.gen(carry[49]),.prop(prop[49]));
a1csa a1csa_51 (.sel(sel[50]),.a(a[207:204]),.b(b[207:204]),.s(s[207:204])
,.gen(carry[50]),.prop(prop[50]));
a1csa a1csa_52 (.sel(sel[51]),.a(a[211:208]),.b(b[211:208]),.s(s[211:208])
,.gen(carry[51]),.prop(prop[51]));
a1csa a1csa_53 (.sel(sel[52]),.a(a[215:212]),.b(b[215:212]),.s(s[215:212])
,.gen(carry[52]),.prop(prop[52]));
a1csa a1csa_54 (.sel(sel[53]),.a(a[219:216]),.b(b[219:216]),.s(s[219:216])
,.gen(carry[53]),.prop(prop[53]));
a1csa a1csa_55 (.sel(sel[54]),.a(a[223:220]),.b(b[223:220]),.s(s[223:220])
,.gen(carry[54]),.prop(prop[54]));
a1csa a1csa_56 (.sel(sel[55]),.a(a[227:224]),.b(b[227:224]),.s(s[227:224])
,.gen(carry[55]),.prop(prop[55]));
a1csa a1csa_57 (.sel(sel[56]),.a(a[231:228]),.b(b[231:228]),.s(s[231:228])
,.gen(carry[56]),.prop(prop[56]));
a1csa a1csa_58 (.sel(sel[57]),.a(a[235:232]),.b(b[235:232]),.s(s[235:232])
,.gen(carry[57]),.prop(prop[57]));
a1csa a1csa_59 (.sel(sel[58]),.a(a[239:236]),.b(b[239:236]),.s(s[239:236])
,.gen(carry[58]),.prop(prop[58]));
a1csa a1csa_60 (.sel(sel[59]),.a(a[243:240]),.b(b[243:240]),.s(s[243:240])
,.gen(carry[59]),.prop(prop[59]));
a1csa a1csa_61 (.sel(sel[60]),.a(a[247:244]),.b(b[247:244]),.s(s[247:244])
,.gen(carry[60]),.prop(prop[60]));
a1csa a1csa_62 (.sel(sel[61]),.a(a[251:248]),.b(b[251:248]),.s(s[251:248])
,.gen(carry[61]),.prop(prop[61]));
a1csa a1csa_63 (.sel(sel[62]),.a(a[255:252]),.b(b[255:252]),.s(s[255:252])
,.gen(carry[62]),.prop(prop[62]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign sel[7] = carry[6] | (prop[6] & sel[6]);
assign sel[8] = carry[7] | (prop[7] & sel[7]);
assign sel[9] = carry[8] | (prop[8] & sel[8]);
assign sel[10] = carry[9] | (prop[9] & sel[9]);
assign sel[11] = carry[10] | (prop[10] & sel[10]);
assign sel[12] = carry[11] | (prop[11] & sel[11]);
assign sel[13] = carry[12] | (prop[12] & sel[12]);
assign sel[14] = carry[13] | (prop[13] & sel[13]);
assign sel[15] = carry[14] | (prop[14] & sel[14]);
assign sel[16] = carry[15] | (prop[15] & sel[15]);
assign sel[17] = carry[16] | (prop[16] & sel[16]);
assign sel[18] = carry[17] | (prop[17] & sel[17]);
assign sel[19] = carry[18] | (prop[18] & sel[18]);
assign sel[20] = carry[19] | (prop[19] & sel[19]);
assign sel[21] = carry[20] | (prop[20] & sel[20]);
assign sel[22] = carry[21] | (prop[21] & sel[21]);
assign sel[23] = carry[22] | (prop[22] & sel[22]);
assign sel[24] = carry[23] | (prop[23] & sel[23]);
assign sel[25] = carry[24] | (prop[24] & sel[24]);
assign sel[26] = carry[25] | (prop[25] & sel[25]);
assign sel[27] = carry[26] | (prop[26] & sel[26]);
assign sel[28] = carry[27] | (prop[27] & sel[27]);
assign sel[29] = carry[28] | (prop[28] & sel[28]);
assign sel[30] = carry[29] | (prop[29] & sel[29]);
assign sel[31] = carry[30] | (prop[30] & sel[30]);
assign sel[32] = carry[31] | (prop[31] & sel[31]);
assign sel[33] = carry[32] | (prop[32] & sel[32]);
assign sel[34] = carry[33] | (prop[33] & sel[33]);
assign sel[35] = carry[34] | (prop[34] & sel[34]);
assign sel[36] = carry[35] | (prop[35] & sel[35]);
assign sel[37] = carry[36] | (prop[36] & sel[36]);
assign sel[38] = carry[37] | (prop[37] & sel[37]);
assign sel[39] = carry[38] | (prop[38] & sel[38]);
assign sel[40] = carry[39] | (prop[39] & sel[39]);
assign sel[41] = carry[40] | (prop[40] & sel[40]);
assign sel[42] = carry[41] | (prop[41] & sel[41]);
assign sel[43] = carry[42] | (prop[42] & sel[42]);
assign sel[44] = carry[43] | (prop[43] & sel[43]);
assign sel[45] = carry[44] | (prop[44] & sel[44]);
assign sel[46] = carry[45] | (prop[45] & sel[45]);
assign sel[47] = carry[46] | (prop[46] & sel[46]);
assign sel[48] = carry[47] | (prop[47] & sel[47]);
assign sel[49] = carry[48] | (prop[48] & sel[48]);
assign sel[50] = carry[49] | (prop[49] & sel[49]);
assign sel[51] = carry[50] | (prop[50] & sel[50]);
assign sel[52] = carry[51] | (prop[51] & sel[51]);
assign sel[53] = carry[52] | (prop[52] & sel[52]);
assign sel[54] = carry[53] | (prop[53] & sel[53]);
assign sel[55] = carry[54] | (prop[54] & sel[54]);
assign sel[56] = carry[55] | (prop[55] & sel[55]);
assign sel[57] = carry[56] | (prop[56] & sel[56]);
assign sel[58] = carry[57] | (prop[57] & sel[57]);
assign sel[59] = carry[58] | (prop[58] & sel[58]);
assign sel[60] = carry[59] | (prop[59] & sel[59]);
assign sel[61] = carry[60] | (prop[60] & sel[60]);
assign sel[62] = carry[61] | (prop[61] & sel[61]);
assign cout = carry[62] | (prop[62] & sel[62]);
endmodule | 0 |
141,762 | data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v | 95,987,710 | a1csa32bits.v | v | 57 | 78 | [] | ['apache license'] | [] | [(21, 56)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:34: Cannot find file containing module: 'a1csa'\n a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:36: Cannot find file containing module: 'a1csa'\n a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:38: Cannot find file containing module: 'a1csa'\n a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:40: Cannot find file containing module: 'a1csa'\n a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:42: Cannot find file containing module: 'a1csa'\n a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:44: Cannot find file containing module: 'a1csa'\n a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa32bits.v:46: Cannot find file containing module: 'a1csa'\n a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])\n ^~~~~\n%Error: Exiting due to 8 error(s)\n" | 312,474 | module | module a1csa32bits (cin,a,b,s,cout);
parameter n = 32;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign cout = carry[6] | (prop[6] & sel[6]);
endmodule | module a1csa32bits (cin,a,b,s,cout); |
parameter n = 32;
parameter m = 8;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign cout = carry[6] | (prop[6] & sel[6]);
endmodule | 0 |
141,763 | data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v | 95,987,710 | a1csa64bits.v | v | 81 | 78 | [] | ['apache license'] | [] | [(21, 80)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:34: Cannot find file containing module: 'a1csa'\n a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:36: Cannot find file containing module: 'a1csa'\n a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:38: Cannot find file containing module: 'a1csa'\n a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:40: Cannot find file containing module: 'a1csa'\n a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:42: Cannot find file containing module: 'a1csa'\n a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:44: Cannot find file containing module: 'a1csa'\n a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:46: Cannot find file containing module: 'a1csa'\n a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:48: Cannot find file containing module: 'a1csa'\n a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:50: Cannot find file containing module: 'a1csa'\n a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:52: Cannot find file containing module: 'a1csa'\n a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:54: Cannot find file containing module: 'a1csa'\n a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:56: Cannot find file containing module: 'a1csa'\n a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:58: Cannot find file containing module: 'a1csa'\n a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:60: Cannot find file containing module: 'a1csa'\n a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])\n ^~~~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa64bits.v:62: Cannot find file containing module: 'a1csa'\n a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])\n ^~~~~\n%Error: Exiting due to 16 error(s)\n" | 312,475 | module | module a1csa64bits (cin,a,b,s,cout);
parameter n = 64;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])
,.gen(carry[7]),.prop(prop[7]));
a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])
,.gen(carry[8]),.prop(prop[8]));
a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])
,.gen(carry[9]),.prop(prop[9]));
a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])
,.gen(carry[10]),.prop(prop[10]));
a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])
,.gen(carry[11]),.prop(prop[11]));
a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])
,.gen(carry[12]),.prop(prop[12]));
a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])
,.gen(carry[13]),.prop(prop[13]));
a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])
,.gen(carry[14]),.prop(prop[14]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign sel[7] = carry[6] | (prop[6] & sel[6]);
assign sel[8] = carry[7] | (prop[7] & sel[7]);
assign sel[9] = carry[8] | (prop[8] & sel[8]);
assign sel[10] = carry[9] | (prop[9] & sel[9]);
assign sel[11] = carry[10] | (prop[10] & sel[10]);
assign sel[12] = carry[11] | (prop[11] & sel[11]);
assign sel[13] = carry[12] | (prop[12] & sel[12]);
assign sel[14] = carry[13] | (prop[13] & sel[13]);
assign cout = carry[14] | (prop[14] & sel[14]);
endmodule | module a1csa64bits (cin,a,b,s,cout); |
parameter n = 64;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4])
,.gen(carry[0]),.prop(prop[0]));
a1csa a1csa_2 (.sel(sel[1]),.a(a[11:8]),.b(b[11:8]),.s(s[11:8])
,.gen(carry[1]),.prop(prop[1]));
a1csa a1csa_3 (.sel(sel[2]),.a(a[15:12]),.b(b[15:12]),.s(s[15:12])
,.gen(carry[2]),.prop(prop[2]));
a1csa a1csa_4 (.sel(sel[3]),.a(a[19:16]),.b(b[19:16]),.s(s[19:16])
,.gen(carry[3]),.prop(prop[3]));
a1csa a1csa_5 (.sel(sel[4]),.a(a[23:20]),.b(b[23:20]),.s(s[23:20])
,.gen(carry[4]),.prop(prop[4]));
a1csa a1csa_6 (.sel(sel[5]),.a(a[27:24]),.b(b[27:24]),.s(s[27:24])
,.gen(carry[5]),.prop(prop[5]));
a1csa a1csa_7 (.sel(sel[6]),.a(a[31:28]),.b(b[31:28]),.s(s[31:28])
,.gen(carry[6]),.prop(prop[6]));
a1csa a1csa_8 (.sel(sel[7]),.a(a[35:32]),.b(b[35:32]),.s(s[35:32])
,.gen(carry[7]),.prop(prop[7]));
a1csa a1csa_9 (.sel(sel[8]),.a(a[39:36]),.b(b[39:36]),.s(s[39:36])
,.gen(carry[8]),.prop(prop[8]));
a1csa a1csa_10 (.sel(sel[9]),.a(a[43:40]),.b(b[43:40]),.s(s[43:40])
,.gen(carry[9]),.prop(prop[9]));
a1csa a1csa_11 (.sel(sel[10]),.a(a[47:44]),.b(b[47:44]),.s(s[47:44])
,.gen(carry[10]),.prop(prop[10]));
a1csa a1csa_12 (.sel(sel[11]),.a(a[51:48]),.b(b[51:48]),.s(s[51:48])
,.gen(carry[11]),.prop(prop[11]));
a1csa a1csa_13 (.sel(sel[12]),.a(a[55:52]),.b(b[55:52]),.s(s[55:52])
,.gen(carry[12]),.prop(prop[12]));
a1csa a1csa_14 (.sel(sel[13]),.a(a[59:56]),.b(b[59:56]),.s(s[59:56])
,.gen(carry[13]),.prop(prop[13]));
a1csa a1csa_15 (.sel(sel[14]),.a(a[63:60]),.b(b[63:60]),.s(s[63:60])
,.gen(carry[14]),.prop(prop[14]));
assign sel[1] = carry[0] | (prop[0] & sel[0]);
assign sel[2] = carry[1] | (prop[1] & sel[1]);
assign sel[3] = carry[2] | (prop[2] & sel[2]);
assign sel[4] = carry[3] | (prop[3] & sel[3]);
assign sel[5] = carry[4] | (prop[4] & sel[4]);
assign sel[6] = carry[5] | (prop[5] & sel[5]);
assign sel[7] = carry[6] | (prop[6] & sel[6]);
assign sel[8] = carry[7] | (prop[7] & sel[7]);
assign sel[9] = carry[8] | (prop[8] & sel[8]);
assign sel[10] = carry[9] | (prop[9] & sel[9]);
assign sel[11] = carry[10] | (prop[10] & sel[10]);
assign sel[12] = carry[11] | (prop[11] & sel[11]);
assign sel[13] = carry[12] | (prop[12] & sel[12]);
assign sel[14] = carry[13] | (prop[13] & sel[13]);
assign cout = carry[14] | (prop[14] & sel[14]);
endmodule | 0 |
141,764 | data/full_repos/permissive/95987710/rtl/a1csa/a1csa8bits.v | 95,987,710 | a1csa8bits.v | v | 39 | 78 | [] | ['apache license'] | [] | [(21, 38)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa8bits.v:33: Cannot find file containing module: 'cra4bits'\n cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.v\n data/full_repos/permissive/95987710/rtl/a1csa,data/full_repos/permissive/95987710/cra4bits.sv\n cra4bits\n cra4bits.v\n cra4bits.sv\n obj_dir/cra4bits\n obj_dir/cra4bits.v\n obj_dir/cra4bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csa/a1csa8bits.v:34: Cannot find file containing module: 'a1csa'\n a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.gen(carry[0])\n ^~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,476 | module | module a1csa8bits (cin,a,b,s,cout);
parameter n = 8;
parameter m = 2;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.gen(carry[0])
,.prop(prop[0]));
assign cout = carry[0] | (prop[0] & sel[0]);
endmodule | module a1csa8bits (cin,a,b,s,cout); |
parameter n = 8;
parameter m = 2;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output cout;
wire [m-2:0] carry,prop,sel;
cra4bits a1csa_0 (.cin(cin),.a(a[3:0]),.b(b[3:0]),.s(s[3:0]),.cout(sel[0]));
a1csa a1csa_1 (.sel(sel[0]),.a(a[7:4]),.b(b[7:4]),.s(s[7:4]),.gen(carry[0])
,.prop(prop[0]));
assign cout = carry[0] | (prop[0] & sel[0]);
endmodule | 0 |
141,765 | data/full_repos/permissive/95987710/rtl/a1csa/mux2to1.v | 95,987,710 | mux2to1.v | v | 26 | 76 | [] | ['apache license'] | [] | [(21, 25)] | null | data/verilator_xmls/12d0be8d-4482-4692-bf2b-a610eb73a385.xml | null | 312,477 | module | module mux2to1(a, b,sel,out);
input a, b, sel ;
output out;
assign out = (sel) ? a : b;
endmodule | module mux2to1(a, b,sel,out); |
input a, b, sel ;
output out;
assign out = (sel) ? a : b;
endmodule | 0 |
141,766 | data/full_repos/permissive/95987710/rtl/a1csa/rb0.v | 95,987,710 | rb0.v | v | 28 | 76 | [] | ['apache license'] | [] | [(21, 27)] | null | data/verilator_xmls/53731640-88c0-4ccd-830c-be0d6d484ee1.xml | null | 312,478 | module | module rb0 (sel,s, rs);
parameter n = 1;
input [n-1:0]s ;
input sel;
output rs;
assign rs = sel ^ s[0];
endmodule | module rb0 (sel,s, rs); |
parameter n = 1;
input [n-1:0]s ;
input sel;
output rs;
assign rs = sel ^ s[0];
endmodule | 0 |
141,767 | data/full_repos/permissive/95987710/rtl/a1csa/rb0_mux.v | 95,987,710 | rb0_mux.v | v | 29 | 76 | [] | ['apache license'] | [] | [(21, 27)] | null | data/verilator_xmls/cc089980-b0c0-4adc-b270-7688f6cf1687.xml | null | 312,479 | module | module rb0_mux (s, rs);
parameter n = 1;
input [n-1:0]s ;
output rs;
assign rs = ~s[0];
endmodule | module rb0_mux (s, rs); |
parameter n = 1;
input [n-1:0]s ;
output rs;
assign rs = ~s[0];
endmodule | 0 |
141,768 | data/full_repos/permissive/95987710/rtl/a1csa/rb2.v | 95,987,710 | rb2.v | v | 28 | 76 | [] | ['apache license'] | [] | [(21, 27)] | null | data/verilator_xmls/f923682c-0c07-4c00-9dbb-0273a8ce3e6c.xml | null | 312,482 | module | module rb2 (sel, s, rs);
parameter n = 3;
input [n-1:0]s;
input sel;
output rs;
assign rs= (sel & s[0] & s[1]) ^ s[2];
endmodule | module rb2 (sel, s, rs); |
parameter n = 3;
input [n-1:0]s;
input sel;
output rs;
assign rs= (sel & s[0] & s[1]) ^ s[2];
endmodule | 0 |
141,769 | data/full_repos/permissive/95987710/rtl/a1csa/rb2_mux.v | 95,987,710 | rb2_mux.v | v | 29 | 76 | [] | ['apache license'] | [] | [(21, 27)] | null | data/verilator_xmls/3d61e84e-f21f-41e9-b444-b0fa32378d84.xml | null | 312,483 | module | module rb2_mux (s, rs);
parameter n = 3;
input [n-1:0]s;
output rs;
assign rs= (s[0] & s[1]) ^ s[2];
endmodule | module rb2_mux (s, rs); |
parameter n = 3;
input [n-1:0]s;
output rs;
assign rs= (s[0] & s[1]) ^ s[2];
endmodule | 0 |
141,770 | data/full_repos/permissive/95987710/rtl/a1csa/rb3_mux.v | 95,987,710 | rb3_mux.v | v | 29 | 76 | [] | ['apache license'] | [] | [(21, 27)] | null | data/verilator_xmls/fe36ae2e-ff1d-4e98-841d-4ffdb310dbae.xml | null | 312,485 | module | module rb3_mux (s, rs);
parameter n = 4;
input [n-1:0]s;
output rs;
assign rs= (s[0] & s[1] & s[2]) ^ s[3];
endmodule | module rb3_mux (s, rs); |
parameter n = 4;
input [n-1:0]s;
output rs;
assign rs= (s[0] & s[1] & s[2]) ^ s[3];
endmodule | 0 |
141,771 | data/full_repos/permissive/95987710/rtl/a1csah/a1csah.v | 95,987,710 | a1csah.v | v | 40 | 83 | [] | ['apache license'] | [] | [(22, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah.v:33: Cannot find file containing module: 'clacin0'\n clacin0 cla_base (.a(a[n-1:0]),.b(b[n-1:0]),.s(s0[n-1:0]),.gen(gen),.prop(prop));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/clacin0\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/clacin0.v\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/clacin0.sv\n clacin0\n clacin0.v\n clacin0.sv\n obj_dir/clacin0\n obj_dir/clacin0.v\n obj_dir/clacin0.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah.v:35: Cannot find file containing module: 'rb0'\n rb0 r0 (.sel(sel),.s(s0[0]),.rs(s[0]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah.v:36: Cannot find file containing module: 'rb1'\n rb1 r1 (.sel(sel),.s(s0[1:0]),.rs(s[1]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah.v:37: Cannot find file containing module: 'rb2'\n rb2 r2 (.sel(sel),.s(s0[2:0]),.rs(s[2]));\n ^~~\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah.v:38: Cannot find file containing module: 'rb3'\n rb3 r3 (.sel(sel),.s(s0[3:0]),.rs(s[3]));\n ^~~\n%Error: Exiting due to 5 error(s)\n" | 312,486 | module | module a1csah (sel,a,b,s,gen,prop);
parameter n = 4;
input sel;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-1:0] s0,rs,carry;
clacin0 cla_base (.a(a[n-1:0]),.b(b[n-1:0]),.s(s0[n-1:0]),.gen(gen),.prop(prop));
rb0 r0 (.sel(sel),.s(s0[0]),.rs(s[0]));
rb1 r1 (.sel(sel),.s(s0[1:0]),.rs(s[1]));
rb2 r2 (.sel(sel),.s(s0[2:0]),.rs(s[2]));
rb3 r3 (.sel(sel),.s(s0[3:0]),.rs(s[3]));
endmodule | module a1csah (sel,a,b,s,gen,prop); |
parameter n = 4;
input sel;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire [n-1:0] s0,rs,carry;
clacin0 cla_base (.a(a[n-1:0]),.b(b[n-1:0]),.s(s0[n-1:0]),.gen(gen),.prop(prop));
rb0 r0 (.sel(sel),.s(s0[0]),.rs(s[0]));
rb1 r1 (.sel(sel),.s(s0[1:0]),.rs(s[1]));
rb2 r2 (.sel(sel),.s(s0[2:0]),.rs(s[2]));
rb3 r3 (.sel(sel),.s(s0[3:0]),.rs(s[3]));
endmodule | 0 |
141,772 | data/full_repos/permissive/95987710/rtl/a1csah/a1csah128.v | 95,987,710 | a1csah128.v | v | 44 | 95 | [] | ['apache license'] | [] | [(22, 42)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah128.v:35: Cannot find file containing module: 'a1csah64'\n a1csah64 a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.gen(gen0),.prop(prop0));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah64\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah64.v\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah64.sv\n a1csah64\n a1csah64.v\n a1csah64.sv\n obj_dir/a1csah64\n obj_dir/a1csah64.v\n obj_dir/a1csah64.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah128.v:36: Cannot find file containing module: 'a1csah64'\n a1csah64 a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.gen(gen1),.prop(prop1));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,487 | module | module a1csah128 (cin,a,b,s,gen,prop);
parameter n = 128;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire prop0,gen0,prop1,gen1,sel;
a1csah64 a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.gen(gen0),.prop(prop0));
a1csah64 a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.gen(gen1),.prop(prop1));
assign sel = gen0 | (prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | module a1csah128 (cin,a,b,s,gen,prop); |
parameter n = 128;
parameter m = 64;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
wire prop0,gen0,prop1,gen1,sel;
a1csah64 a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0]),.gen(gen0),.prop(prop0));
a1csah64 a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m]),.gen(gen1),.prop(prop1));
assign sel = gen0 | (prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | 0 |
141,773 | data/full_repos/permissive/95987710/rtl/a1csah/a1csah32bits.v | 95,987,710 | a1csah32bits.v | v | 45 | 76 | [] | ['apache license'] | [] | [(22, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah32bits.v:35: Cannot find file containing module: 'a1csah16bits'\n a1csah16bits a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah16bits\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah16bits.v\n data/full_repos/permissive/95987710/rtl/a1csah,data/full_repos/permissive/95987710/a1csah16bits.sv\n a1csah16bits\n a1csah16bits.v\n a1csah16bits.sv\n obj_dir/a1csah16bits\n obj_dir/a1csah16bits.v\n obj_dir/a1csah16bits.sv\n%Error: data/full_repos/permissive/95987710/rtl/a1csah/a1csah32bits.v:37: Cannot find file containing module: 'a1csah16bits'\n a1csah16bits a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,493 | module | module a1csah32bits (cin,a,b,s,gen,prop,cout);
parameter n = 32;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire prop0,gen0,prop1,gen1,cout0,cout1,sel;
a1csah16bits a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
a1csah16bits a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign sel = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | module a1csah32bits (cin,a,b,s,gen,prop,cout); |
parameter n = 32;
parameter m = 16;
input cin;
input [n-1:0] a;
input [n-1:0] b;
output [n-1:0] s;
output gen;
output prop;
output cout;
wire prop0,gen0,prop1,gen1,cout0,cout1,sel;
a1csah16bits a1csah_0 (.cin(cin),.a(a[m-1:0]),.b(b[m-1:0]),.s(s[m-1:0])
,.gen(gen0),.prop(prop0),.cout(cout0));
a1csah16bits a1csah_1 (.cin(sel),.a(a[n-1:m]),.b(b[n-1:m]),.s(s[n-1:m])
,.gen(gen1),.prop(prop1),.cout(cout1));
assign sel = gen0 | (prop0 & cin);
assign cout = gen1 | (prop1 & gen0) | (prop1 & prop0 & cin);
assign gen = gen1 | (prop1 & gen0);
assign prop = prop1 & prop0;
endmodule | 0 |
Subsets and Splits