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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
141,509 | data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v | 95,577,250 | tb_openMSP430_fpga.v | v | 405 | 88 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:38: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog,data/full_repos/permissive/95577250/timescale.v\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog,data/full_repos/permissive/95577250/timescale.v.v\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog,data/full_repos/permissive/95577250/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:41: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:117: Cannot find include file: registers.v\n`include "registers.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:120: Cannot find include file: stimulus.v\n`include "stimulus.v" \n ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:129: Unsupported: Ignoring delay on this delayed statement.\n #10 $readmemh("./pmem.mem", pmem);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:145: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLK_50MHz <= ~CLK_50MHz; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:151: Unsupported: Ignoring delay on this delayed statement.\n #100 RESET = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:152: Unsupported: Ignoring delay on this delayed statement.\n #600 RESET = 1\'b0;\n ^\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:337: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_openMSP430_fpga.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:338: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb_openMSP430_fpga);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:357: Unsupported: Ignoring delay on this delayed statement.\n #500000;\n ^\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/bench/verilog/tb_openMSP430_fpga.v:370: syntax error, unexpected \'@\'\n @(inst_pc===16\'hffff)\n ^\n%Error: Exiting due to 7 error(s), 5 warning(s)\n' | 312,006 | module | module tb_openMSP430_fpga;
reg CLK_50MHz;
reg RESET;
reg SW7;
reg SW6;
reg SW5;
reg SW4;
reg SW3;
reg SW2;
reg SW1;
reg SW0;
reg BTN2;
reg BTN1;
reg BTN0;
wire LED7;
wire LED6;
wire LED5;
wire LED4;
wire LED3;
wire LED2;
wire LED1;
wire LED0;
wire SEG_A;
wire SEG_B;
wire SEG_C;
wire SEG_D;
wire SEG_E;
wire SEG_F;
wire SEG_G;
wire SEG_DP;
wire SEG_AN0;
wire SEG_AN1;
wire SEG_AN2;
wire SEG_AN3;
reg UART_RXD;
wire UART_TXD;
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
integer i;
integer error;
reg stimulus_done;
`include "registers.v"
`include "stimulus.v"
initial
begin
#10 $readmemh("./pmem.mem", pmem);
for (i=0; i<2048; i=i+1)
begin
dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
end
end
initial
begin
CLK_50MHz = 1'b0;
forever #10 CLK_50MHz <= ~CLK_50MHz;
end
initial
begin
RESET = 1'b0;
#100 RESET = 1'b1;
#600 RESET = 1'b0;
end
initial
begin
error = 0;
stimulus_done = 1;
SW7 = 1'b0;
SW6 = 1'b0;
SW5 = 1'b0;
SW4 = 1'b0;
SW3 = 1'b0;
SW2 = 1'b0;
SW1 = 1'b0;
SW0 = 1'b0;
BTN2 = 1'b0;
BTN1 = 1'b0;
BTN0 = 1'b0;
UART_RXD = 1'b0;
end
openMSP430_fpga dut (
.CLK_50MHz (CLK_50MHz),
.CLK_SOCKET (1'b0),
.SW7 (SW7),
.SW6 (SW6),
.SW5 (SW5),
.SW4 (SW4),
.SW3 (SW3),
.SW2 (SW2),
.SW1 (SW1),
.SW0 (SW0),
.BTN3 (RESET),
.BTN2 (BTN2),
.BTN1 (BTN1),
.BTN0 (BTN0),
.LED7 (LED7),
.LED6 (LED6),
.LED5 (LED5),
.LED4 (LED4),
.LED3 (LED3),
.LED2 (LED2),
.LED1 (LED1),
.LED0 (LED0),
.SEG_A (SEG_A),
.SEG_B (SEG_B),
.SEG_C (SEG_C),
.SEG_D (SEG_D),
.SEG_E (SEG_E),
.SEG_F (SEG_F),
.SEG_G (SEG_G),
.SEG_DP (SEG_DP),
.SEG_AN0 (SEG_AN0),
.SEG_AN1 (SEG_AN1),
.SEG_AN2 (SEG_AN2),
.SEG_AN3 (SEG_AN3),
.UART_RXD (UART_RXD),
.UART_TXD (UART_TXD),
.UART_RXD_A (1'b0),
.UART_TXD_A (UART_TXD_A),
.PS2_D (PS2_D),
.PS2_C (PS2_C),
.SRAM_A17 (SRAM_A17),
.SRAM_A16 (SRAM_A16),
.SRAM_A15 (SRAM_A15),
.SRAM_A14 (SRAM_A14),
.SRAM_A13 (SRAM_A13),
.SRAM_A12 (SRAM_A12),
.SRAM_A11 (SRAM_A11),
.SRAM_A10 (SRAM_A10),
.SRAM_A9 (SRAM_A9),
.SRAM_A8 (SRAM_A8),
.SRAM_A7 (SRAM_A7),
.SRAM_A6 (SRAM_A6),
.SRAM_A5 (SRAM_A5),
.SRAM_A4 (SRAM_A4),
.SRAM_A3 (SRAM_A3),
.SRAM_A2 (SRAM_A2),
.SRAM_A1 (SRAM_A1),
.SRAM_A0 (SRAM_A0),
.SRAM_OE (SRAM_OE),
.SRAM_WE (SRAM_WE),
.SRAM0_IO15 (SRAM0_IO15),
.SRAM0_IO14 (SRAM0_IO14),
.SRAM0_IO13 (SRAM0_IO13),
.SRAM0_IO12 (SRAM0_IO12),
.SRAM0_IO11 (SRAM0_IO11),
.SRAM0_IO10 (SRAM0_IO10),
.SRAM0_IO9 (SRAM0_IO9),
.SRAM0_IO8 (SRAM0_IO8),
.SRAM0_IO7 (SRAM0_IO7),
.SRAM0_IO6 (SRAM0_IO6),
.SRAM0_IO5 (SRAM0_IO5),
.SRAM0_IO4 (SRAM0_IO4),
.SRAM0_IO3 (SRAM0_IO3),
.SRAM0_IO2 (SRAM0_IO2),
.SRAM0_IO1 (SRAM0_IO1),
.SRAM0_IO0 (SRAM0_IO0),
.SRAM0_CE1 (SRAM0_CE1),
.SRAM0_UB1 (SRAM0_UB1),
.SRAM0_LB1 (SRAM0_LB1),
.SRAM1_IO15 (SRAM1_IO15),
.SRAM1_IO14 (SRAM1_IO14),
.SRAM1_IO13 (SRAM1_IO13),
.SRAM1_IO12 (SRAM1_IO12),
.SRAM1_IO11 (SRAM1_IO11),
.SRAM1_IO10 (SRAM1_IO10),
.SRAM1_IO9 (SRAM1_IO9),
.SRAM1_IO8 (SRAM1_IO8),
.SRAM1_IO7 (SRAM1_IO7),
.SRAM1_IO6 (SRAM1_IO6),
.SRAM1_IO5 (SRAM1_IO5),
.SRAM1_IO4 (SRAM1_IO4),
.SRAM1_IO3 (SRAM1_IO3),
.SRAM1_IO2 (SRAM1_IO2),
.SRAM1_IO1 (SRAM1_IO1),
.SRAM1_IO0 (SRAM1_IO0),
.SRAM1_CE2 (SRAM1_CE2),
.SRAM1_UB2 (SRAM1_UB2),
.SRAM1_LB2 (SRAM1_LB2),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS)
);
msp_debug msp_debug_0 (
.e_state (e_state),
.i_state (i_state),
.inst_cycle (inst_cycle),
.inst_full (inst_full),
.inst_number (inst_number),
.inst_pc (inst_pc),
.inst_short (inst_short),
.mclk (mclk),
.puc_rst (puc_rst)
);
initial
begin
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430_fpga.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430_fpga.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430_fpga.vcd");
$dumpvars(0, tb_openMSP430_fpga);
`endif
`endif
end
initial
begin
`ifdef NO_TIMEOUT
`else
`ifdef VERY_LONG_TIMEOUT
#500000000;
`else
`ifdef LONG_TIMEOUT
#5000000;
`else
#500000;
`endif
`endif
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$finish;
`endif
end
initial
begin
@(inst_pc===16'hffff)
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
end
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
endmodule | module tb_openMSP430_fpga; |
reg CLK_50MHz;
reg RESET;
reg SW7;
reg SW6;
reg SW5;
reg SW4;
reg SW3;
reg SW2;
reg SW1;
reg SW0;
reg BTN2;
reg BTN1;
reg BTN0;
wire LED7;
wire LED6;
wire LED5;
wire LED4;
wire LED3;
wire LED2;
wire LED1;
wire LED0;
wire SEG_A;
wire SEG_B;
wire SEG_C;
wire SEG_D;
wire SEG_E;
wire SEG_F;
wire SEG_G;
wire SEG_DP;
wire SEG_AN0;
wire SEG_AN1;
wire SEG_AN2;
wire SEG_AN3;
reg UART_RXD;
wire UART_TXD;
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
integer i;
integer error;
reg stimulus_done;
`include "registers.v"
`include "stimulus.v"
initial
begin
#10 $readmemh("./pmem.mem", pmem);
for (i=0; i<2048; i=i+1)
begin
dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
end
end
initial
begin
CLK_50MHz = 1'b0;
forever #10 CLK_50MHz <= ~CLK_50MHz;
end
initial
begin
RESET = 1'b0;
#100 RESET = 1'b1;
#600 RESET = 1'b0;
end
initial
begin
error = 0;
stimulus_done = 1;
SW7 = 1'b0;
SW6 = 1'b0;
SW5 = 1'b0;
SW4 = 1'b0;
SW3 = 1'b0;
SW2 = 1'b0;
SW1 = 1'b0;
SW0 = 1'b0;
BTN2 = 1'b0;
BTN1 = 1'b0;
BTN0 = 1'b0;
UART_RXD = 1'b0;
end
openMSP430_fpga dut (
.CLK_50MHz (CLK_50MHz),
.CLK_SOCKET (1'b0),
.SW7 (SW7),
.SW6 (SW6),
.SW5 (SW5),
.SW4 (SW4),
.SW3 (SW3),
.SW2 (SW2),
.SW1 (SW1),
.SW0 (SW0),
.BTN3 (RESET),
.BTN2 (BTN2),
.BTN1 (BTN1),
.BTN0 (BTN0),
.LED7 (LED7),
.LED6 (LED6),
.LED5 (LED5),
.LED4 (LED4),
.LED3 (LED3),
.LED2 (LED2),
.LED1 (LED1),
.LED0 (LED0),
.SEG_A (SEG_A),
.SEG_B (SEG_B),
.SEG_C (SEG_C),
.SEG_D (SEG_D),
.SEG_E (SEG_E),
.SEG_F (SEG_F),
.SEG_G (SEG_G),
.SEG_DP (SEG_DP),
.SEG_AN0 (SEG_AN0),
.SEG_AN1 (SEG_AN1),
.SEG_AN2 (SEG_AN2),
.SEG_AN3 (SEG_AN3),
.UART_RXD (UART_RXD),
.UART_TXD (UART_TXD),
.UART_RXD_A (1'b0),
.UART_TXD_A (UART_TXD_A),
.PS2_D (PS2_D),
.PS2_C (PS2_C),
.SRAM_A17 (SRAM_A17),
.SRAM_A16 (SRAM_A16),
.SRAM_A15 (SRAM_A15),
.SRAM_A14 (SRAM_A14),
.SRAM_A13 (SRAM_A13),
.SRAM_A12 (SRAM_A12),
.SRAM_A11 (SRAM_A11),
.SRAM_A10 (SRAM_A10),
.SRAM_A9 (SRAM_A9),
.SRAM_A8 (SRAM_A8),
.SRAM_A7 (SRAM_A7),
.SRAM_A6 (SRAM_A6),
.SRAM_A5 (SRAM_A5),
.SRAM_A4 (SRAM_A4),
.SRAM_A3 (SRAM_A3),
.SRAM_A2 (SRAM_A2),
.SRAM_A1 (SRAM_A1),
.SRAM_A0 (SRAM_A0),
.SRAM_OE (SRAM_OE),
.SRAM_WE (SRAM_WE),
.SRAM0_IO15 (SRAM0_IO15),
.SRAM0_IO14 (SRAM0_IO14),
.SRAM0_IO13 (SRAM0_IO13),
.SRAM0_IO12 (SRAM0_IO12),
.SRAM0_IO11 (SRAM0_IO11),
.SRAM0_IO10 (SRAM0_IO10),
.SRAM0_IO9 (SRAM0_IO9),
.SRAM0_IO8 (SRAM0_IO8),
.SRAM0_IO7 (SRAM0_IO7),
.SRAM0_IO6 (SRAM0_IO6),
.SRAM0_IO5 (SRAM0_IO5),
.SRAM0_IO4 (SRAM0_IO4),
.SRAM0_IO3 (SRAM0_IO3),
.SRAM0_IO2 (SRAM0_IO2),
.SRAM0_IO1 (SRAM0_IO1),
.SRAM0_IO0 (SRAM0_IO0),
.SRAM0_CE1 (SRAM0_CE1),
.SRAM0_UB1 (SRAM0_UB1),
.SRAM0_LB1 (SRAM0_LB1),
.SRAM1_IO15 (SRAM1_IO15),
.SRAM1_IO14 (SRAM1_IO14),
.SRAM1_IO13 (SRAM1_IO13),
.SRAM1_IO12 (SRAM1_IO12),
.SRAM1_IO11 (SRAM1_IO11),
.SRAM1_IO10 (SRAM1_IO10),
.SRAM1_IO9 (SRAM1_IO9),
.SRAM1_IO8 (SRAM1_IO8),
.SRAM1_IO7 (SRAM1_IO7),
.SRAM1_IO6 (SRAM1_IO6),
.SRAM1_IO5 (SRAM1_IO5),
.SRAM1_IO4 (SRAM1_IO4),
.SRAM1_IO3 (SRAM1_IO3),
.SRAM1_IO2 (SRAM1_IO2),
.SRAM1_IO1 (SRAM1_IO1),
.SRAM1_IO0 (SRAM1_IO0),
.SRAM1_CE2 (SRAM1_CE2),
.SRAM1_UB2 (SRAM1_UB2),
.SRAM1_LB2 (SRAM1_LB2),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS)
);
msp_debug msp_debug_0 (
.e_state (e_state),
.i_state (i_state),
.inst_cycle (inst_cycle),
.inst_full (inst_full),
.inst_number (inst_number),
.inst_pc (inst_pc),
.inst_short (inst_short),
.mclk (mclk),
.puc_rst (puc_rst)
);
initial
begin
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430_fpga.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430_fpga.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430_fpga.vcd");
$dumpvars(0, tb_openMSP430_fpga);
`endif
`endif
end
initial
begin
`ifdef NO_TIMEOUT
`else
`ifdef VERY_LONG_TIMEOUT
#500000000;
`else
`ifdef LONG_TIMEOUT
#5000000;
`else
#500000;
`endif
`endif
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$finish;
`endif
end
initial
begin
@(inst_pc===16'hffff)
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
end
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
endmodule | 18 |
141,510 | data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/openMSP430_fpga.v | 95,577,250 | openMSP430_fpga.v | v | 1,025 | 96 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/openMSP430_fpga.v:39: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog,data/full_repos/permissive/95577250/openMSP430_defines.v\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog,data/full_repos/permissive/95577250/openMSP430_defines.v.v\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog,data/full_repos/permissive/95577250/openMSP430_defines.v.sv\n openMSP430_defines.v\n openMSP430_defines.v.v\n openMSP430_defines.v.sv\n obj_dir/openMSP430_defines.v\n obj_dir/openMSP430_defines.v.v\n obj_dir/openMSP430_defines.v.sv\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/openMSP430_fpga.v:295: Define or directive not defined: \'`DMEM_MSB\'\nwire [`DMEM_MSB:0] dmem_addr;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/openMSP430_fpga.v:295: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`DMEM_MSB:0] dmem_addr;\n ^\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/openMSP430_fpga.v:298: Define or directive not defined: \'`PMEM_MSB\'\nwire [`PMEM_MSB:0] pmem_addr;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/openMSP430_fpga.v:298: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`PMEM_MSB:0] pmem_addr;\n ^\n%Error: Exiting due to 5 error(s)\n' | 312,011 | module | module openMSP430_fpga (
CLK_50MHz,
CLK_SOCKET,
SW7,
SW6,
SW5,
SW4,
SW3,
SW2,
SW1,
SW0,
BTN3,
BTN2,
BTN1,
BTN0,
LED7,
LED6,
LED5,
LED4,
LED3,
LED2,
LED1,
LED0,
SEG_A,
SEG_B,
SEG_C,
SEG_D,
SEG_E,
SEG_F,
SEG_G,
SEG_DP,
SEG_AN0,
SEG_AN1,
SEG_AN2,
SEG_AN3,
UART_RXD,
UART_TXD,
UART_RXD_A,
UART_TXD_A,
PS2_D,
PS2_C,
SRAM_A17,
SRAM_A16,
SRAM_A15,
SRAM_A14,
SRAM_A13,
SRAM_A12,
SRAM_A11,
SRAM_A10,
SRAM_A9,
SRAM_A8,
SRAM_A7,
SRAM_A6,
SRAM_A5,
SRAM_A4,
SRAM_A3,
SRAM_A2,
SRAM_A1,
SRAM_A0,
SRAM_OE,
SRAM_WE,
SRAM0_IO15,
SRAM0_IO14,
SRAM0_IO13,
SRAM0_IO12,
SRAM0_IO11,
SRAM0_IO10,
SRAM0_IO9,
SRAM0_IO8,
SRAM0_IO7,
SRAM0_IO6,
SRAM0_IO5,
SRAM0_IO4,
SRAM0_IO3,
SRAM0_IO2,
SRAM0_IO1,
SRAM0_IO0,
SRAM0_CE1,
SRAM0_UB1,
SRAM0_LB1,
SRAM1_IO15,
SRAM1_IO14,
SRAM1_IO13,
SRAM1_IO12,
SRAM1_IO11,
SRAM1_IO10,
SRAM1_IO9,
SRAM1_IO8,
SRAM1_IO7,
SRAM1_IO6,
SRAM1_IO5,
SRAM1_IO4,
SRAM1_IO3,
SRAM1_IO2,
SRAM1_IO1,
SRAM1_IO0,
SRAM1_CE2,
SRAM1_UB2,
SRAM1_LB2,
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS
);
input CLK_50MHz;
input CLK_SOCKET;
input SW7;
input SW6;
input SW5;
input SW4;
input SW3;
input SW2;
input SW1;
input SW0;
input BTN3;
input BTN2;
input BTN1;
input BTN0;
output LED7;
output LED6;
output LED5;
output LED4;
output LED3;
output LED2;
output LED1;
output LED0;
output SEG_A;
output SEG_B;
output SEG_C;
output SEG_D;
output SEG_E;
output SEG_F;
output SEG_G;
output SEG_DP;
output SEG_AN0;
output SEG_AN1;
output SEG_AN2;
output SEG_AN3;
input UART_RXD;
output UART_TXD;
input UART_RXD_A;
output UART_TXD_A;
inout PS2_D;
output PS2_C;
output SRAM_A17;
output SRAM_A16;
output SRAM_A15;
output SRAM_A14;
output SRAM_A13;
output SRAM_A12;
output SRAM_A11;
output SRAM_A10;
output SRAM_A9;
output SRAM_A8;
output SRAM_A7;
output SRAM_A6;
output SRAM_A5;
output SRAM_A4;
output SRAM_A3;
output SRAM_A2;
output SRAM_A1;
output SRAM_A0;
output SRAM_OE;
output SRAM_WE;
inout SRAM0_IO15;
inout SRAM0_IO14;
inout SRAM0_IO13;
inout SRAM0_IO12;
inout SRAM0_IO11;
inout SRAM0_IO10;
inout SRAM0_IO9;
inout SRAM0_IO8;
inout SRAM0_IO7;
inout SRAM0_IO6;
inout SRAM0_IO5;
inout SRAM0_IO4;
inout SRAM0_IO3;
inout SRAM0_IO2;
inout SRAM0_IO1;
inout SRAM0_IO0;
output SRAM0_CE1;
output SRAM0_UB1;
output SRAM0_LB1;
inout SRAM1_IO15;
inout SRAM1_IO14;
inout SRAM1_IO13;
inout SRAM1_IO12;
inout SRAM1_IO11;
inout SRAM1_IO10;
inout SRAM1_IO9;
inout SRAM1_IO8;
inout SRAM1_IO7;
inout SRAM1_IO6;
inout SRAM1_IO5;
inout SRAM1_IO4;
inout SRAM1_IO3;
inout SRAM1_IO2;
inout SRAM1_IO1;
inout SRAM1_IO0;
output SRAM1_CE2;
output SRAM1_UB2;
output SRAM1_LB2;
output VGA_R;
output VGA_G;
output VGA_B;
output VGA_HS;
output VGA_VS;
wire [13:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_we;
wire [`DMEM_MSB:0] dmem_addr;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [`PMEM_MSB:0] pmem_addr;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [13:0] irq_acc;
wire [13:0] irq_bus;
wire [15:0] per_dout;
wire [15:0] dmem_dout;
wire [15:0] pmem_dout;
wire [7:0] p1_din;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_din;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_din;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [15:0] per_dout_dio;
wire [15:0] per_dout_tA;
wire [15:0] per_dout_7seg;
wire irq_uart_rx;
wire irq_uart_tx;
wire [15:0] per_dout_uart;
wire hw_uart_txd;
wire hw_uart_rxd;
wire reset_pin;
IBUFG ibuf_clk_main (.O(clk_50M_in), .I(CLK_50MHz));
IBUFG ibuf_clk_socket (.O(clk_socket_in), .I(CLK_SOCKET));
`ifdef DCM_FX_MODE
DCM dcm_adv_clk_main (
.CLK0 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKDV (),
.CLKFX (dcm_clk),
.CLKFX180 (),
.PSDONE (),
.STATUS (),
.LOCKED (dcm_locked),
.CLKIN (clk_50M_in),
.CLKFB (1'b0),
.PSINCDEC (1'b0),
.PSEN (1'b0),
.DSSEN (1'b0),
.RST (reset_pin),
.PSCLK (1'b0)
);
defparam dcm_adv_clk_main.CLK_FEEDBACK = "NONE";
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.0;
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_adv_clk_main.FACTORY_JF = 16'hC080;
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 5;
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 2;
`else
DCM dcm_adv_clk_main (
.CLKDV (dcm_clk),
.CLKFX (),
.CLKFX180 (),
.CLK0 (CLK0_BUF),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.LOCKED (dcm_locked),
.PSDONE (),
.STATUS (),
.CLKFB (CLKFB_IN),
.CLKIN (clk_50M_in),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.DSSEN (1'b0),
.PSCLK (1'b0),
.RST (reset_pin)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
defparam dcm_adv_clk_main.CLK_FEEDBACK = "1X";
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 1;
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 4;
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.000;
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_adv_clk_main.FACTORY_JF = 16'h8080;
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
`endif
BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk));
IBUF ibuf_reset_n (.O(reset_pin), .I(BTN3));
wire reset_pin_n = ~reset_pin;
assign reset_n = reset_pin_n & dcm_locked;
wire gsr_tb;
wire gts_tb;
STARTUP_SPARTAN3 xstartup (.CLK(clk_sys), .GSR(gsr_tb), .GTS(gts_tb));
openMSP430 openMSP430_0 (
.aclk (),
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.dbg_uart_txd (dbg_uart_txd),
.dco_enable (),
.dco_wkup (),
.dmem_addr (dmem_addr),
.dmem_cen (dmem_cen),
.dmem_din (dmem_din),
.dmem_wen (dmem_wen),
.irq_acc (irq_acc),
.lfxt_enable (),
.lfxt_wkup (),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_we (per_we),
.per_en (per_en),
.pmem_addr (pmem_addr),
.pmem_cen (pmem_cen),
.pmem_din (pmem_din),
.pmem_wen (pmem_wen),
.puc_rst (puc_rst),
.smclk (),
.smclk_en (smclk_en),
.cpu_en (1'b1),
.dbg_en (1'b1),
.dbg_uart_rxd (dbg_uart_rxd),
.dco_clk (clk_sys),
.dmem_dout (dmem_dout),
.irq (irq_bus),
.lfxt_clk (1'b0),
.nmi (nmi),
.per_dout (per_dout),
.pmem_dout (pmem_dout),
.reset_n (reset_n),
.scan_enable (1'b0),
.scan_mode (1'b0),
.wkup (1'b0)
);
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(1),
.P4_EN(0),
.P5_EN(0),
.P6_EN(0)) gpio_0 (
.irq_port1 (irq_port1),
.irq_port2 (irq_port2),
.p1_dout (p1_dout),
.p1_dout_en (p1_dout_en),
.p1_sel (p1_sel),
.p2_dout (p2_dout),
.p2_dout_en (p2_dout_en),
.p2_sel (p2_sel),
.p3_dout (p3_dout),
.p3_dout_en (p3_dout_en),
.p3_sel (p3_sel),
.p4_dout (),
.p4_dout_en (),
.p4_sel (),
.p5_dout (),
.p5_dout_en (),
.p5_sel (),
.p6_dout (),
.p6_dout_en (),
.p6_sel (),
.per_dout (per_dout_dio),
.mclk (mclk),
.p1_din (p1_din),
.p2_din (p2_din),
.p3_din (p3_din),
.p4_din (8'h00),
.p5_din (8'h00),
.p6_din (8'h00),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_timerA timerA_0 (
.irq_ta0 (irq_ta0),
.irq_ta1 (irq_ta1),
.per_dout (per_dout_tA),
.ta_out0 (ta_out0),
.ta_out0_en (ta_out0_en),
.ta_out1 (ta_out1),
.ta_out1_en (ta_out1_en),
.ta_out2 (ta_out2),
.ta_out2_en (ta_out2_en),
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.inclk (inclk),
.irq_ta0_acc (irq_acc[9]),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.ta_cci0a (ta_cci0a),
.ta_cci0b (ta_cci0b),
.ta_cci1a (ta_cci1a),
.ta_cci1b (1'b0),
.ta_cci2a (ta_cci2a),
.ta_cci2b (1'b0),
.taclk (taclk)
);
driver_7segment driver_7segment_0 (
.per_dout (per_dout_7seg),
.seg_a (seg_a_),
.seg_b (seg_b_),
.seg_c (seg_c_),
.seg_d (seg_d_),
.seg_e (seg_e_),
.seg_f (seg_f_),
.seg_g (seg_g_),
.seg_dp (seg_dp_),
.seg_an0 (seg_an0_),
.seg_an1 (seg_an1_),
.seg_an2 (seg_an2_),
.seg_an3 (seg_an3_),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
.irq_uart_rx (irq_uart_rx),
.irq_uart_tx (irq_uart_tx),
.per_dout (per_dout_uart),
.uart_txd (hw_uart_txd),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.uart_rxd (hw_uart_rxd)
);
assign per_dout = per_dout_dio |
per_dout_tA |
per_dout_7seg |
per_dout_uart;
assign nmi = 1'b0;
assign irq_bus = {1'b0,
1'b0,
1'b0,
1'b0,
irq_ta0,
irq_ta1,
irq_uart_rx,
irq_uart_tx,
1'b0,
1'b0,
irq_port2,
irq_port1,
1'b0,
1'b0};
wire [7:0] p1_io_mux_b_unconnected;
wire [7:0] p1_io_dout;
wire [7:0] p1_io_dout_en;
wire [7:0] p1_io_din;
io_mux #8 io_mux_p1 (
.a_din (p1_din),
.a_dout (p1_dout),
.a_dout_en (p1_dout_en),
.b_din ({p1_io_mux_b_unconnected[7],
p1_io_mux_b_unconnected[6],
p1_io_mux_b_unconnected[5],
p1_io_mux_b_unconnected[4],
ta_cci2a,
ta_cci1a,
ta_cci0a,
taclk
}),
.b_dout ({ta_out2,
ta_out1,
ta_out0,
(smclk_en & mclk),
ta_out2,
ta_out1,
ta_out0,
1'b0
}),
.b_dout_en ({ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b1,
ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b0
}),
.io_din (p1_io_din),
.io_dout (p1_io_dout),
.io_dout_en (p1_io_dout_en),
.sel (p1_sel)
);
wire [7:0] p2_io_mux_b_unconnected;
wire [7:0] p2_io_dout;
wire [7:0] p2_io_dout_en;
wire [7:0] p2_io_din;
io_mux #8 io_mux_p2 (
.a_din (p2_din),
.a_dout (p2_dout),
.a_dout_en (p2_dout_en),
.b_din ({p2_io_mux_b_unconnected[7],
p2_io_mux_b_unconnected[6],
p2_io_mux_b_unconnected[5],
p2_io_mux_b_unconnected[4],
p2_io_mux_b_unconnected[3],
ta_cci0b,
inclk,
p2_io_mux_b_unconnected[0]
}),
.b_dout ({1'b0,
1'b0,
1'b0,
ta_out2,
ta_out1,
1'b0,
1'b0,
(aclk_en & mclk)
}),
.b_dout_en ({1'b0,
1'b0,
1'b0,
ta_out2_en,
ta_out1_en,
1'b0,
1'b0,
1'b1
}),
.io_din (p2_io_din),
.io_dout (p2_io_dout),
.io_dout_en (p2_io_dout_en),
.sel (p2_sel)
);
ram_8x512_hi ram_8x512_hi_0 (
.addr (dmem_addr),
.clk (clk_sys),
.din (dmem_din[15:8]),
.dout (dmem_dout[15:8]),
.en (dmem_cen),
.we (dmem_wen[1])
);
ram_8x512_lo ram_8x512_lo_0 (
.addr (dmem_addr),
.clk (clk_sys),
.din (dmem_din[7:0]),
.dout (dmem_dout[7:0]),
.en (dmem_cen),
.we (dmem_wen[0])
);
rom_8x2k_hi rom_8x2k_hi_0 (
.addr (pmem_addr),
.clk (clk_sys),
.din (pmem_din[15:8]),
.dout (pmem_dout[15:8]),
.en (pmem_cen),
.we (pmem_wen[1])
);
rom_8x2k_lo rom_8x2k_lo_0 (
.addr (pmem_addr),
.clk (clk_sys),
.din (pmem_din[7:0]),
.dout (pmem_dout[7:0]),
.en (pmem_cen),
.we (pmem_wen[0])
);
IBUF SW7_PIN (.O(p3_din[7]), .I(SW7));
IBUF SW6_PIN (.O(p3_din[6]), .I(SW6));
IBUF SW5_PIN (.O(p3_din[5]), .I(SW5));
IBUF SW4_PIN (.O(p3_din[4]), .I(SW4));
IBUF SW3_PIN (.O(p3_din[3]), .I(SW3));
IBUF SW2_PIN (.O(p3_din[2]), .I(SW2));
IBUF SW1_PIN (.O(p3_din[1]), .I(SW1));
IBUF SW0_PIN (.O(p3_din[0]), .I(SW0));
OBUF LED7_PIN (.I(p3_dout[7] & p3_dout_en[7]), .O(LED7));
OBUF LED6_PIN (.I(p3_dout[6] & p3_dout_en[6]), .O(LED6));
OBUF LED5_PIN (.I(p3_dout[5] & p3_dout_en[5]), .O(LED5));
OBUF LED4_PIN (.I(p3_dout[4] & p3_dout_en[4]), .O(LED4));
OBUF LED3_PIN (.I(p3_dout[3] & p3_dout_en[3]), .O(LED3));
OBUF LED2_PIN (.I(p3_dout[2] & p3_dout_en[2]), .O(LED2));
OBUF LED1_PIN (.I(p3_dout[1] & p3_dout_en[1]), .O(LED1));
OBUF LED0_PIN (.I(p3_dout[0] & p3_dout_en[0]), .O(LED0));
IBUF BTN2_PIN (.O(), .I(BTN2));
IBUF BTN1_PIN (.O(), .I(BTN1));
IBUF BTN0_PIN (.O(), .I(BTN0));
OBUF SEG_A_PIN (.I(seg_a_), .O(SEG_A));
OBUF SEG_B_PIN (.I(seg_b_), .O(SEG_B));
OBUF SEG_C_PIN (.I(seg_c_), .O(SEG_C));
OBUF SEG_D_PIN (.I(seg_d_), .O(SEG_D));
OBUF SEG_E_PIN (.I(seg_e_), .O(SEG_E));
OBUF SEG_F_PIN (.I(seg_f_), .O(SEG_F));
OBUF SEG_G_PIN (.I(seg_g_), .O(SEG_G));
OBUF SEG_DP_PIN (.I(seg_dp_), .O(SEG_DP));
OBUF SEG_AN0_PIN (.I(seg_an0_), .O(SEG_AN0));
OBUF SEG_AN1_PIN (.I(seg_an1_), .O(SEG_AN1));
OBUF SEG_AN2_PIN (.I(seg_an2_), .O(SEG_AN2));
OBUF SEG_AN3_PIN (.I(seg_an3_), .O(SEG_AN3));
assign p1_io_din = 8'h00;
assign p2_io_din[7:3] = 5'h00;
assign p2_io_din[1:0] = 2'h0;
wire sdi_select = ({p3_din[1], p3_din[0]}==2'b00) |
({p3_din[1], p3_din[0]}==2'b11);
wire gpio_select = ({p3_din[1], p3_din[0]}==2'b01);
wire uart_select = ({p3_din[1], p3_din[0]}==2'b10);
wire uart_txd_out = gpio_select ? p1_io_dout[1] :
uart_select ? hw_uart_txd : dbg_uart_txd;
wire uart_rxd_in;
assign p2_io_din[2] = gpio_select ? uart_rxd_in : 1'b1;
assign hw_uart_rxd = uart_select ? uart_rxd_in : 1'b1;
assign dbg_uart_rxd = sdi_select ? uart_rxd_in : 1'b1;
IBUF UART_RXD_PIN (.O(uart_rxd_in), .I(UART_RXD));
OBUF UART_TXD_PIN (.I(uart_txd_out), .O(UART_TXD));
IBUF UART_RXD_A_PIN (.O(), .I(UART_RXD_A));
OBUF UART_TXD_A_PIN (.I(1'b0), .O(UART_TXD_A));
IOBUF PS2_D_PIN (.O(), .I(1'b0), .T(1'b1), .IO(PS2_D));
OBUF PS2_C_PIN (.I(1'b0), .O(PS2_C));
OBUF SRAM_A17_PIN (.I(1'b0), .O(SRAM_A17));
OBUF SRAM_A16_PIN (.I(1'b0), .O(SRAM_A16));
OBUF SRAM_A15_PIN (.I(1'b0), .O(SRAM_A15));
OBUF SRAM_A14_PIN (.I(1'b0), .O(SRAM_A14));
OBUF SRAM_A13_PIN (.I(1'b0), .O(SRAM_A13));
OBUF SRAM_A12_PIN (.I(1'b0), .O(SRAM_A12));
OBUF SRAM_A11_PIN (.I(1'b0), .O(SRAM_A11));
OBUF SRAM_A10_PIN (.I(1'b0), .O(SRAM_A10));
OBUF SRAM_A9_PIN (.I(1'b0), .O(SRAM_A9));
OBUF SRAM_A8_PIN (.I(1'b0), .O(SRAM_A8));
OBUF SRAM_A7_PIN (.I(1'b0), .O(SRAM_A7));
OBUF SRAM_A6_PIN (.I(1'b0), .O(SRAM_A6));
OBUF SRAM_A5_PIN (.I(1'b0), .O(SRAM_A5));
OBUF SRAM_A4_PIN (.I(1'b0), .O(SRAM_A4));
OBUF SRAM_A3_PIN (.I(1'b0), .O(SRAM_A3));
OBUF SRAM_A2_PIN (.I(1'b0), .O(SRAM_A2));
OBUF SRAM_A1_PIN (.I(1'b0), .O(SRAM_A1));
OBUF SRAM_A0_PIN (.I(1'b0), .O(SRAM_A0));
OBUF SRAM_OE_PIN (.I(1'b1), .O(SRAM_OE));
OBUF SRAM_WE_PIN (.I(1'b1), .O(SRAM_WE));
IOBUF SRAM0_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO15));
IOBUF SRAM0_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO14));
IOBUF SRAM0_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO13));
IOBUF SRAM0_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO12));
IOBUF SRAM0_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO11));
IOBUF SRAM0_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO10));
IOBUF SRAM0_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO9));
IOBUF SRAM0_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO8));
IOBUF SRAM0_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO7));
IOBUF SRAM0_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO6));
IOBUF SRAM0_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO5));
IOBUF SRAM0_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO4));
IOBUF SRAM0_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO3));
IOBUF SRAM0_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO2));
IOBUF SRAM0_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO1));
IOBUF SRAM0_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO0));
OBUF SRAM0_CE1_PIN (.I(1'b1), .O(SRAM0_CE1));
OBUF SRAM0_UB1_PIN (.I(1'b1), .O(SRAM0_UB1));
OBUF SRAM0_LB1_PIN (.I(1'b1), .O(SRAM0_LB1));
IOBUF SRAM1_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO15));
IOBUF SRAM1_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO14));
IOBUF SRAM1_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO13));
IOBUF SRAM1_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO12));
IOBUF SRAM1_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO11));
IOBUF SRAM1_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO10));
IOBUF SRAM1_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO9));
IOBUF SRAM1_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO8));
IOBUF SRAM1_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO7));
IOBUF SRAM1_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO6));
IOBUF SRAM1_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO5));
IOBUF SRAM1_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO4));
IOBUF SRAM1_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO3));
IOBUF SRAM1_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO2));
IOBUF SRAM1_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO1));
IOBUF SRAM1_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO0));
OBUF SRAM1_CE2_PIN (.I(1'b1), .O(SRAM1_CE2));
OBUF SRAM1_UB2_PIN (.I(1'b1), .O(SRAM1_UB2));
OBUF SRAM1_LB2_PIN (.I(1'b1), .O(SRAM1_LB2));
OBUF VGA_R_PIN (.I(1'b0), .O(VGA_R));
OBUF VGA_G_PIN (.I(1'b0), .O(VGA_G));
OBUF VGA_B_PIN (.I(1'b0), .O(VGA_B));
OBUF VGA_HS_PIN (.I(1'b0), .O(VGA_HS));
OBUF VGA_VS_PIN (.I(1'b0), .O(VGA_VS));
endmodule | module openMSP430_fpga (
CLK_50MHz,
CLK_SOCKET,
SW7,
SW6,
SW5,
SW4,
SW3,
SW2,
SW1,
SW0,
BTN3,
BTN2,
BTN1,
BTN0,
LED7,
LED6,
LED5,
LED4,
LED3,
LED2,
LED1,
LED0,
SEG_A,
SEG_B,
SEG_C,
SEG_D,
SEG_E,
SEG_F,
SEG_G,
SEG_DP,
SEG_AN0,
SEG_AN1,
SEG_AN2,
SEG_AN3,
UART_RXD,
UART_TXD,
UART_RXD_A,
UART_TXD_A,
PS2_D,
PS2_C,
SRAM_A17,
SRAM_A16,
SRAM_A15,
SRAM_A14,
SRAM_A13,
SRAM_A12,
SRAM_A11,
SRAM_A10,
SRAM_A9,
SRAM_A8,
SRAM_A7,
SRAM_A6,
SRAM_A5,
SRAM_A4,
SRAM_A3,
SRAM_A2,
SRAM_A1,
SRAM_A0,
SRAM_OE,
SRAM_WE,
SRAM0_IO15,
SRAM0_IO14,
SRAM0_IO13,
SRAM0_IO12,
SRAM0_IO11,
SRAM0_IO10,
SRAM0_IO9,
SRAM0_IO8,
SRAM0_IO7,
SRAM0_IO6,
SRAM0_IO5,
SRAM0_IO4,
SRAM0_IO3,
SRAM0_IO2,
SRAM0_IO1,
SRAM0_IO0,
SRAM0_CE1,
SRAM0_UB1,
SRAM0_LB1,
SRAM1_IO15,
SRAM1_IO14,
SRAM1_IO13,
SRAM1_IO12,
SRAM1_IO11,
SRAM1_IO10,
SRAM1_IO9,
SRAM1_IO8,
SRAM1_IO7,
SRAM1_IO6,
SRAM1_IO5,
SRAM1_IO4,
SRAM1_IO3,
SRAM1_IO2,
SRAM1_IO1,
SRAM1_IO0,
SRAM1_CE2,
SRAM1_UB2,
SRAM1_LB2,
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS
); |
input CLK_50MHz;
input CLK_SOCKET;
input SW7;
input SW6;
input SW5;
input SW4;
input SW3;
input SW2;
input SW1;
input SW0;
input BTN3;
input BTN2;
input BTN1;
input BTN0;
output LED7;
output LED6;
output LED5;
output LED4;
output LED3;
output LED2;
output LED1;
output LED0;
output SEG_A;
output SEG_B;
output SEG_C;
output SEG_D;
output SEG_E;
output SEG_F;
output SEG_G;
output SEG_DP;
output SEG_AN0;
output SEG_AN1;
output SEG_AN2;
output SEG_AN3;
input UART_RXD;
output UART_TXD;
input UART_RXD_A;
output UART_TXD_A;
inout PS2_D;
output PS2_C;
output SRAM_A17;
output SRAM_A16;
output SRAM_A15;
output SRAM_A14;
output SRAM_A13;
output SRAM_A12;
output SRAM_A11;
output SRAM_A10;
output SRAM_A9;
output SRAM_A8;
output SRAM_A7;
output SRAM_A6;
output SRAM_A5;
output SRAM_A4;
output SRAM_A3;
output SRAM_A2;
output SRAM_A1;
output SRAM_A0;
output SRAM_OE;
output SRAM_WE;
inout SRAM0_IO15;
inout SRAM0_IO14;
inout SRAM0_IO13;
inout SRAM0_IO12;
inout SRAM0_IO11;
inout SRAM0_IO10;
inout SRAM0_IO9;
inout SRAM0_IO8;
inout SRAM0_IO7;
inout SRAM0_IO6;
inout SRAM0_IO5;
inout SRAM0_IO4;
inout SRAM0_IO3;
inout SRAM0_IO2;
inout SRAM0_IO1;
inout SRAM0_IO0;
output SRAM0_CE1;
output SRAM0_UB1;
output SRAM0_LB1;
inout SRAM1_IO15;
inout SRAM1_IO14;
inout SRAM1_IO13;
inout SRAM1_IO12;
inout SRAM1_IO11;
inout SRAM1_IO10;
inout SRAM1_IO9;
inout SRAM1_IO8;
inout SRAM1_IO7;
inout SRAM1_IO6;
inout SRAM1_IO5;
inout SRAM1_IO4;
inout SRAM1_IO3;
inout SRAM1_IO2;
inout SRAM1_IO1;
inout SRAM1_IO0;
output SRAM1_CE2;
output SRAM1_UB2;
output SRAM1_LB2;
output VGA_R;
output VGA_G;
output VGA_B;
output VGA_HS;
output VGA_VS;
wire [13:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_we;
wire [`DMEM_MSB:0] dmem_addr;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [`PMEM_MSB:0] pmem_addr;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [13:0] irq_acc;
wire [13:0] irq_bus;
wire [15:0] per_dout;
wire [15:0] dmem_dout;
wire [15:0] pmem_dout;
wire [7:0] p1_din;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_din;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_din;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [15:0] per_dout_dio;
wire [15:0] per_dout_tA;
wire [15:0] per_dout_7seg;
wire irq_uart_rx;
wire irq_uart_tx;
wire [15:0] per_dout_uart;
wire hw_uart_txd;
wire hw_uart_rxd;
wire reset_pin;
IBUFG ibuf_clk_main (.O(clk_50M_in), .I(CLK_50MHz));
IBUFG ibuf_clk_socket (.O(clk_socket_in), .I(CLK_SOCKET));
`ifdef DCM_FX_MODE
DCM dcm_adv_clk_main (
.CLK0 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKDV (),
.CLKFX (dcm_clk),
.CLKFX180 (),
.PSDONE (),
.STATUS (),
.LOCKED (dcm_locked),
.CLKIN (clk_50M_in),
.CLKFB (1'b0),
.PSINCDEC (1'b0),
.PSEN (1'b0),
.DSSEN (1'b0),
.RST (reset_pin),
.PSCLK (1'b0)
);
defparam dcm_adv_clk_main.CLK_FEEDBACK = "NONE";
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.0;
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_adv_clk_main.FACTORY_JF = 16'hC080;
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 5;
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 2;
`else
DCM dcm_adv_clk_main (
.CLKDV (dcm_clk),
.CLKFX (),
.CLKFX180 (),
.CLK0 (CLK0_BUF),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.LOCKED (dcm_locked),
.PSDONE (),
.STATUS (),
.CLKFB (CLKFB_IN),
.CLKIN (clk_50M_in),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.DSSEN (1'b0),
.PSCLK (1'b0),
.RST (reset_pin)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
defparam dcm_adv_clk_main.CLK_FEEDBACK = "1X";
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 1;
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 4;
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.000;
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_adv_clk_main.FACTORY_JF = 16'h8080;
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
`endif
BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk));
IBUF ibuf_reset_n (.O(reset_pin), .I(BTN3));
wire reset_pin_n = ~reset_pin;
assign reset_n = reset_pin_n & dcm_locked;
wire gsr_tb;
wire gts_tb;
STARTUP_SPARTAN3 xstartup (.CLK(clk_sys), .GSR(gsr_tb), .GTS(gts_tb));
openMSP430 openMSP430_0 (
.aclk (),
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.dbg_uart_txd (dbg_uart_txd),
.dco_enable (),
.dco_wkup (),
.dmem_addr (dmem_addr),
.dmem_cen (dmem_cen),
.dmem_din (dmem_din),
.dmem_wen (dmem_wen),
.irq_acc (irq_acc),
.lfxt_enable (),
.lfxt_wkup (),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_we (per_we),
.per_en (per_en),
.pmem_addr (pmem_addr),
.pmem_cen (pmem_cen),
.pmem_din (pmem_din),
.pmem_wen (pmem_wen),
.puc_rst (puc_rst),
.smclk (),
.smclk_en (smclk_en),
.cpu_en (1'b1),
.dbg_en (1'b1),
.dbg_uart_rxd (dbg_uart_rxd),
.dco_clk (clk_sys),
.dmem_dout (dmem_dout),
.irq (irq_bus),
.lfxt_clk (1'b0),
.nmi (nmi),
.per_dout (per_dout),
.pmem_dout (pmem_dout),
.reset_n (reset_n),
.scan_enable (1'b0),
.scan_mode (1'b0),
.wkup (1'b0)
);
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(1),
.P4_EN(0),
.P5_EN(0),
.P6_EN(0)) gpio_0 (
.irq_port1 (irq_port1),
.irq_port2 (irq_port2),
.p1_dout (p1_dout),
.p1_dout_en (p1_dout_en),
.p1_sel (p1_sel),
.p2_dout (p2_dout),
.p2_dout_en (p2_dout_en),
.p2_sel (p2_sel),
.p3_dout (p3_dout),
.p3_dout_en (p3_dout_en),
.p3_sel (p3_sel),
.p4_dout (),
.p4_dout_en (),
.p4_sel (),
.p5_dout (),
.p5_dout_en (),
.p5_sel (),
.p6_dout (),
.p6_dout_en (),
.p6_sel (),
.per_dout (per_dout_dio),
.mclk (mclk),
.p1_din (p1_din),
.p2_din (p2_din),
.p3_din (p3_din),
.p4_din (8'h00),
.p5_din (8'h00),
.p6_din (8'h00),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_timerA timerA_0 (
.irq_ta0 (irq_ta0),
.irq_ta1 (irq_ta1),
.per_dout (per_dout_tA),
.ta_out0 (ta_out0),
.ta_out0_en (ta_out0_en),
.ta_out1 (ta_out1),
.ta_out1_en (ta_out1_en),
.ta_out2 (ta_out2),
.ta_out2_en (ta_out2_en),
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.inclk (inclk),
.irq_ta0_acc (irq_acc[9]),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.ta_cci0a (ta_cci0a),
.ta_cci0b (ta_cci0b),
.ta_cci1a (ta_cci1a),
.ta_cci1b (1'b0),
.ta_cci2a (ta_cci2a),
.ta_cci2b (1'b0),
.taclk (taclk)
);
driver_7segment driver_7segment_0 (
.per_dout (per_dout_7seg),
.seg_a (seg_a_),
.seg_b (seg_b_),
.seg_c (seg_c_),
.seg_d (seg_d_),
.seg_e (seg_e_),
.seg_f (seg_f_),
.seg_g (seg_g_),
.seg_dp (seg_dp_),
.seg_an0 (seg_an0_),
.seg_an1 (seg_an1_),
.seg_an2 (seg_an2_),
.seg_an3 (seg_an3_),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
.irq_uart_rx (irq_uart_rx),
.irq_uart_tx (irq_uart_tx),
.per_dout (per_dout_uart),
.uart_txd (hw_uart_txd),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.uart_rxd (hw_uart_rxd)
);
assign per_dout = per_dout_dio |
per_dout_tA |
per_dout_7seg |
per_dout_uart;
assign nmi = 1'b0;
assign irq_bus = {1'b0,
1'b0,
1'b0,
1'b0,
irq_ta0,
irq_ta1,
irq_uart_rx,
irq_uart_tx,
1'b0,
1'b0,
irq_port2,
irq_port1,
1'b0,
1'b0};
wire [7:0] p1_io_mux_b_unconnected;
wire [7:0] p1_io_dout;
wire [7:0] p1_io_dout_en;
wire [7:0] p1_io_din;
io_mux #8 io_mux_p1 (
.a_din (p1_din),
.a_dout (p1_dout),
.a_dout_en (p1_dout_en),
.b_din ({p1_io_mux_b_unconnected[7],
p1_io_mux_b_unconnected[6],
p1_io_mux_b_unconnected[5],
p1_io_mux_b_unconnected[4],
ta_cci2a,
ta_cci1a,
ta_cci0a,
taclk
}),
.b_dout ({ta_out2,
ta_out1,
ta_out0,
(smclk_en & mclk),
ta_out2,
ta_out1,
ta_out0,
1'b0
}),
.b_dout_en ({ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b1,
ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b0
}),
.io_din (p1_io_din),
.io_dout (p1_io_dout),
.io_dout_en (p1_io_dout_en),
.sel (p1_sel)
);
wire [7:0] p2_io_mux_b_unconnected;
wire [7:0] p2_io_dout;
wire [7:0] p2_io_dout_en;
wire [7:0] p2_io_din;
io_mux #8 io_mux_p2 (
.a_din (p2_din),
.a_dout (p2_dout),
.a_dout_en (p2_dout_en),
.b_din ({p2_io_mux_b_unconnected[7],
p2_io_mux_b_unconnected[6],
p2_io_mux_b_unconnected[5],
p2_io_mux_b_unconnected[4],
p2_io_mux_b_unconnected[3],
ta_cci0b,
inclk,
p2_io_mux_b_unconnected[0]
}),
.b_dout ({1'b0,
1'b0,
1'b0,
ta_out2,
ta_out1,
1'b0,
1'b0,
(aclk_en & mclk)
}),
.b_dout_en ({1'b0,
1'b0,
1'b0,
ta_out2_en,
ta_out1_en,
1'b0,
1'b0,
1'b1
}),
.io_din (p2_io_din),
.io_dout (p2_io_dout),
.io_dout_en (p2_io_dout_en),
.sel (p2_sel)
);
ram_8x512_hi ram_8x512_hi_0 (
.addr (dmem_addr),
.clk (clk_sys),
.din (dmem_din[15:8]),
.dout (dmem_dout[15:8]),
.en (dmem_cen),
.we (dmem_wen[1])
);
ram_8x512_lo ram_8x512_lo_0 (
.addr (dmem_addr),
.clk (clk_sys),
.din (dmem_din[7:0]),
.dout (dmem_dout[7:0]),
.en (dmem_cen),
.we (dmem_wen[0])
);
rom_8x2k_hi rom_8x2k_hi_0 (
.addr (pmem_addr),
.clk (clk_sys),
.din (pmem_din[15:8]),
.dout (pmem_dout[15:8]),
.en (pmem_cen),
.we (pmem_wen[1])
);
rom_8x2k_lo rom_8x2k_lo_0 (
.addr (pmem_addr),
.clk (clk_sys),
.din (pmem_din[7:0]),
.dout (pmem_dout[7:0]),
.en (pmem_cen),
.we (pmem_wen[0])
);
IBUF SW7_PIN (.O(p3_din[7]), .I(SW7));
IBUF SW6_PIN (.O(p3_din[6]), .I(SW6));
IBUF SW5_PIN (.O(p3_din[5]), .I(SW5));
IBUF SW4_PIN (.O(p3_din[4]), .I(SW4));
IBUF SW3_PIN (.O(p3_din[3]), .I(SW3));
IBUF SW2_PIN (.O(p3_din[2]), .I(SW2));
IBUF SW1_PIN (.O(p3_din[1]), .I(SW1));
IBUF SW0_PIN (.O(p3_din[0]), .I(SW0));
OBUF LED7_PIN (.I(p3_dout[7] & p3_dout_en[7]), .O(LED7));
OBUF LED6_PIN (.I(p3_dout[6] & p3_dout_en[6]), .O(LED6));
OBUF LED5_PIN (.I(p3_dout[5] & p3_dout_en[5]), .O(LED5));
OBUF LED4_PIN (.I(p3_dout[4] & p3_dout_en[4]), .O(LED4));
OBUF LED3_PIN (.I(p3_dout[3] & p3_dout_en[3]), .O(LED3));
OBUF LED2_PIN (.I(p3_dout[2] & p3_dout_en[2]), .O(LED2));
OBUF LED1_PIN (.I(p3_dout[1] & p3_dout_en[1]), .O(LED1));
OBUF LED0_PIN (.I(p3_dout[0] & p3_dout_en[0]), .O(LED0));
IBUF BTN2_PIN (.O(), .I(BTN2));
IBUF BTN1_PIN (.O(), .I(BTN1));
IBUF BTN0_PIN (.O(), .I(BTN0));
OBUF SEG_A_PIN (.I(seg_a_), .O(SEG_A));
OBUF SEG_B_PIN (.I(seg_b_), .O(SEG_B));
OBUF SEG_C_PIN (.I(seg_c_), .O(SEG_C));
OBUF SEG_D_PIN (.I(seg_d_), .O(SEG_D));
OBUF SEG_E_PIN (.I(seg_e_), .O(SEG_E));
OBUF SEG_F_PIN (.I(seg_f_), .O(SEG_F));
OBUF SEG_G_PIN (.I(seg_g_), .O(SEG_G));
OBUF SEG_DP_PIN (.I(seg_dp_), .O(SEG_DP));
OBUF SEG_AN0_PIN (.I(seg_an0_), .O(SEG_AN0));
OBUF SEG_AN1_PIN (.I(seg_an1_), .O(SEG_AN1));
OBUF SEG_AN2_PIN (.I(seg_an2_), .O(SEG_AN2));
OBUF SEG_AN3_PIN (.I(seg_an3_), .O(SEG_AN3));
assign p1_io_din = 8'h00;
assign p2_io_din[7:3] = 5'h00;
assign p2_io_din[1:0] = 2'h0;
wire sdi_select = ({p3_din[1], p3_din[0]}==2'b00) |
({p3_din[1], p3_din[0]}==2'b11);
wire gpio_select = ({p3_din[1], p3_din[0]}==2'b01);
wire uart_select = ({p3_din[1], p3_din[0]}==2'b10);
wire uart_txd_out = gpio_select ? p1_io_dout[1] :
uart_select ? hw_uart_txd : dbg_uart_txd;
wire uart_rxd_in;
assign p2_io_din[2] = gpio_select ? uart_rxd_in : 1'b1;
assign hw_uart_rxd = uart_select ? uart_rxd_in : 1'b1;
assign dbg_uart_rxd = sdi_select ? uart_rxd_in : 1'b1;
IBUF UART_RXD_PIN (.O(uart_rxd_in), .I(UART_RXD));
OBUF UART_TXD_PIN (.I(uart_txd_out), .O(UART_TXD));
IBUF UART_RXD_A_PIN (.O(), .I(UART_RXD_A));
OBUF UART_TXD_A_PIN (.I(1'b0), .O(UART_TXD_A));
IOBUF PS2_D_PIN (.O(), .I(1'b0), .T(1'b1), .IO(PS2_D));
OBUF PS2_C_PIN (.I(1'b0), .O(PS2_C));
OBUF SRAM_A17_PIN (.I(1'b0), .O(SRAM_A17));
OBUF SRAM_A16_PIN (.I(1'b0), .O(SRAM_A16));
OBUF SRAM_A15_PIN (.I(1'b0), .O(SRAM_A15));
OBUF SRAM_A14_PIN (.I(1'b0), .O(SRAM_A14));
OBUF SRAM_A13_PIN (.I(1'b0), .O(SRAM_A13));
OBUF SRAM_A12_PIN (.I(1'b0), .O(SRAM_A12));
OBUF SRAM_A11_PIN (.I(1'b0), .O(SRAM_A11));
OBUF SRAM_A10_PIN (.I(1'b0), .O(SRAM_A10));
OBUF SRAM_A9_PIN (.I(1'b0), .O(SRAM_A9));
OBUF SRAM_A8_PIN (.I(1'b0), .O(SRAM_A8));
OBUF SRAM_A7_PIN (.I(1'b0), .O(SRAM_A7));
OBUF SRAM_A6_PIN (.I(1'b0), .O(SRAM_A6));
OBUF SRAM_A5_PIN (.I(1'b0), .O(SRAM_A5));
OBUF SRAM_A4_PIN (.I(1'b0), .O(SRAM_A4));
OBUF SRAM_A3_PIN (.I(1'b0), .O(SRAM_A3));
OBUF SRAM_A2_PIN (.I(1'b0), .O(SRAM_A2));
OBUF SRAM_A1_PIN (.I(1'b0), .O(SRAM_A1));
OBUF SRAM_A0_PIN (.I(1'b0), .O(SRAM_A0));
OBUF SRAM_OE_PIN (.I(1'b1), .O(SRAM_OE));
OBUF SRAM_WE_PIN (.I(1'b1), .O(SRAM_WE));
IOBUF SRAM0_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO15));
IOBUF SRAM0_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO14));
IOBUF SRAM0_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO13));
IOBUF SRAM0_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO12));
IOBUF SRAM0_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO11));
IOBUF SRAM0_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO10));
IOBUF SRAM0_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO9));
IOBUF SRAM0_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO8));
IOBUF SRAM0_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO7));
IOBUF SRAM0_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO6));
IOBUF SRAM0_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO5));
IOBUF SRAM0_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO4));
IOBUF SRAM0_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO3));
IOBUF SRAM0_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO2));
IOBUF SRAM0_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO1));
IOBUF SRAM0_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO0));
OBUF SRAM0_CE1_PIN (.I(1'b1), .O(SRAM0_CE1));
OBUF SRAM0_UB1_PIN (.I(1'b1), .O(SRAM0_UB1));
OBUF SRAM0_LB1_PIN (.I(1'b1), .O(SRAM0_LB1));
IOBUF SRAM1_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO15));
IOBUF SRAM1_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO14));
IOBUF SRAM1_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO13));
IOBUF SRAM1_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO12));
IOBUF SRAM1_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO11));
IOBUF SRAM1_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO10));
IOBUF SRAM1_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO9));
IOBUF SRAM1_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO8));
IOBUF SRAM1_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO7));
IOBUF SRAM1_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO6));
IOBUF SRAM1_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO5));
IOBUF SRAM1_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO4));
IOBUF SRAM1_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO3));
IOBUF SRAM1_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO2));
IOBUF SRAM1_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO1));
IOBUF SRAM1_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO0));
OBUF SRAM1_CE2_PIN (.I(1'b1), .O(SRAM1_CE2));
OBUF SRAM1_UB2_PIN (.I(1'b1), .O(SRAM1_UB2));
OBUF SRAM1_LB2_PIN (.I(1'b1), .O(SRAM1_LB2));
OBUF VGA_R_PIN (.I(1'b0), .O(VGA_R));
OBUF VGA_G_PIN (.I(1'b0), .O(VGA_G));
OBUF VGA_B_PIN (.I(1'b0), .O(VGA_B));
OBUF VGA_HS_PIN (.I(1'b0), .O(VGA_HS));
OBUF VGA_VS_PIN (.I(1'b0), .O(VGA_VS));
endmodule | 18 |
141,511 | data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v | 95,577,250 | rom_8x2k_lo.v | v | 111 | 81 | [] | [] | [] | [(40, 109)] | null | null | 1: b"%Error: data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v:58: Cannot find file containing module: 'BLKMEMSP_V6_2'\n BLKMEMSP_V6_2 #(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/coregen,data/full_repos/permissive/95577250/BLKMEMSP_V6_2\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/coregen,data/full_repos/permissive/95577250/BLKMEMSP_V6_2.v\n data/full_repos/permissive/95577250/fpga/xilinx_digilent_s3board/rtl/verilog/coregen,data/full_repos/permissive/95577250/BLKMEMSP_V6_2.sv\n BLKMEMSP_V6_2\n BLKMEMSP_V6_2.v\n BLKMEMSP_V6_2.sv\n obj_dir/BLKMEMSP_V6_2\n obj_dir/BLKMEMSP_V6_2.v\n obj_dir/BLKMEMSP_V6_2.sv\n%Error: Exiting due to 1 error(s)\n" | 312,015 | module | module rom_8x2k_lo(
addr,
clk,
din,
dout,
en,
we);
input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
BLKMEMSP_V6_2 #(
.c_addr_width(11),
.c_default_data("0"),
.c_depth(2048),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(0),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(0),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
endmodule | module rom_8x2k_lo(
addr,
clk,
din,
dout,
en,
we); |
input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
BLKMEMSP_V6_2 #(
.c_addr_width(11),
.c_default_data("0"),
.c_depth(2048),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(0),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(0),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
endmodule | 18 |
141,512 | data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog/openMSP430_fpga.v | 95,577,250 | openMSP430_fpga.v | v | 837 | 102 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog/openMSP430_fpga.v:35: Cannot find include file: openmsp430/openMSP430_defines.v\n`include "openmsp430/openMSP430_defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog,data/full_repos/permissive/95577250/openmsp430/openMSP430_defines.v\n data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog,data/full_repos/permissive/95577250/openmsp430/openMSP430_defines.v.v\n data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog,data/full_repos/permissive/95577250/openmsp430/openMSP430_defines.v.sv\n openmsp430/openMSP430_defines.v\n openmsp430/openMSP430_defines.v.v\n openmsp430/openMSP430_defines.v.sv\n obj_dir/openmsp430/openMSP430_defines.v\n obj_dir/openmsp430/openMSP430_defines.v.v\n obj_dir/openmsp430/openMSP430_defines.v.sv\n%Error: data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog/openMSP430_fpga.v:105: Define or directive not defined: \'`DMEM_MSB\'\nwire [`DMEM_MSB:0] dmem_addr;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog/openMSP430_fpga.v:105: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`DMEM_MSB:0] dmem_addr;\n ^\n%Error: data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog/openMSP430_fpga.v:109: Define or directive not defined: \'`PMEM_MSB\'\nwire [`PMEM_MSB:0] pmem_addr;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95577250/fpga/xula2-stickit/ise/rtl/verilog/openMSP430_fpga.v:109: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`PMEM_MSB:0] pmem_addr;\n ^\n%Error: Exiting due to 5 error(s)\n' | 312,057 | module | module openMSP430_fpga (
input wire fpgaClk_i,
output wire sdCke_o,
output wire sdClk_o,
input wire sdClkFb_i,
output wire sdCe_bo,
output wire sdRas_bo,
output wire sdCas_bo,
output wire sdWe_bo,
output wire sdDqml_o,
output wire sdDqmh_o,
output wire [1:0] sdBs_o,
output wire [12:0] sdAddr_o,
inout wire [15:0] sdData_io,
output wire usdflashCs_bo,
output wire flashCs_bo,
output wire sclk_o,
output wire mosi_o,
input wire miso_i,
inout wire chanClk_io,
inout wire [31:0] chan_io
);
parameter integer foo = $clog2(16);
assign sdCke_o = 1'b0;
assign sdClk_o = 1'b0;
assign sdCe_bo = 1'b0;
assign sdRas_bo = 1'b0;
assign sdCas_bo = 1'b0;
assign sdWe_bo = 1'b0;
assign sdDqml_o = 1'b0;
assign sdDqmh_o = 1'b0;
assign sdBs_o = 2'b0;
assign sdAddr_o = 13'b0;
assign usdflashCs_bo = 1'b0;
assign flashCs_bo = 1'b0;
assign sclk_o = 1'b0;
assign mosi_o = 1'b0;
wire [15:0] dma_dout;
wire dma_ready;
wire dma_resp;
reg [15:0] dma_din;
reg dma_priority;
reg dma_wkup;
wire [15:1] dma_addr;
wire [1:0] dma_we;
wire dma_en;
wire [15:0] per_dout_dma;
reg dma_tfx_cancel;
wire [13:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_we;
wire [`DMEM_MSB:0] dmem_addr;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [1:0] dmem_wen_n;
wire [`PMEM_MSB:0] pmem_addr;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [1:0] pmem_wen_n;
wire [13:0] irq_acc;
wire [13:0] irq_bus;
wire [15:0] per_dout;
wire [15:0] dmem_dout;
wire [15:0] pmem_dout;
wire [7:0] p1_din;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_din;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p4_din;
wire [15:0] per_dout_dio;
wire [15:0] per_dout_tA;
wire irq_uart_rx;
wire irq_uart_tx;
wire [15:0] per_dout_uart;
wire hw_uart_txd;
wire hw_uart_rxd;
wire hw_uart_txd2;
wire [15:0] per_dout_uart2;
wire [15:0] per_dout_tsc;
wire [15:0] per_dout_led;
wire [7:0] led_so;
wire [15:0] per_dout_spi;
wire spi_mosi;
wire spi_miso;
wire spi_sck;
wire [2:0] spi_ss;
wire reset_pin;
wire dbg_sw = 1'b1;
assign chan_io[25] = dbg_uart_txd & hw_uart2_txd;
assign dbg_uart_rxd = chan_io[26];
assign chan_io[4] = hw_uart_txd;
assign hw_uart_rxd = chan_io[21];
`ifdef FPGA_CHARLIE
assign chan_io[3] = led_so[6];
assign chan_io[18] = led_so[4];
assign chan_io[1] = led_so[2];
assign chan_io[17] = led_so[0];
assign chan_io[0] = led_so[7];
assign chan_io[16] = led_so[5];
assign chanClk_io = led_so[3];
assign chan_io[15] = led_so[1];
`else
assign chan_io[3] = spi_sck;
assign spi_miso = chan_io[18] | chan_io[16];
assign chan_io[1] = spi_mosi;
assign chan_io[17] = spi_ss[0];
assign chan_io[0] = spi_sck;
assign chanClk_io = spi_mosi;
assign chan_io[15] = spi_ss[1];
`endif
IBUFG ibuf_clk_main (.O(clk_12M_in), .I(fpgaClk_i));
DCM_SP #(
.CLKFX_MULTIPLY(5),
.CLKFX_DIVIDE(3),
.CLKIN_PERIOD(83.333)
)dcm_inst(
.CLKFX (dcm_clk),
.CLK0 (CLK0_BUF),
.LOCKED (dcm_locked),
.CLKFB (CLKFB_IN),
.CLKIN (clk_12M_in),
.PSEN (1'b0),
.RST (reset_pin)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
defparam dcm_inst.CLKFX_MULTIPLY = 5;
defparam dcm_inst.CLKFX_DIVIDE = 3;
defparam dcm_int.CLKIN_PERIOD = 83.333;
BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk));
wire reset_pin_n = 1'b1;
assign reset_n = reset_pin_n & dcm_locked;
initial
begin
dma_din = 16'h0000;
dma_priority = 1'b0;
dma_wkup = 1'b0;
dma_tfx_cancel = 1'b0;
end
wire spm_violation;
openMSP430 openMSP430_0 (
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.dbg_uart_txd (dbg_uart_txd),
.dmem_addr (dmem_addr),
.dmem_cen (dmem_cen),
.dmem_din (dmem_din),
.dmem_wen (dmem_wen),
.irq_acc (irq_acc),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_we (per_we),
.per_en (per_en),
.pmem_addr (pmem_addr),
.pmem_cen (pmem_cen),
.pmem_din (pmem_din),
.pmem_wen (pmem_wen),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.dma_dout (dma_dout),
.dma_ready (dma_ready),
.dma_resp (dma_resp),
.cpu_en (1'b1),
.dbg_en (dbg_sw),
.dbg_uart_rxd (dbg_uart_rxd),
.dco_clk (clk_sys),
.dmem_dout (dmem_dout),
.irq (irq_bus),
.lfxt_clk (1'b0),
.dma_addr (dma_addr),
.dma_din (dma_din),
.dma_en (dma_en),
.dma_priority (dma_priority),
.dma_we (dma_we),
.dma_wkup (dma_wkup),
.nmi (nmi),
.per_dout (per_dout),
.pmem_dout (pmem_dout),
.reset_n (reset_n)
);
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(1),
.P4_EN(1),
.P5_EN(0),
.P6_EN(0)) gpio_0 (
.irq_port1 (irq_port1),
.irq_port2 (irq_port2),
.p1_dout (p1_dout),
.p1_dout_en (p1_dout_en),
.p1_sel (p1_sel),
.p2_dout (p2_dout),
.p2_dout_en (p2_dout_en),
.p2_sel (p2_sel),
.p3_dout (p3_dout),
.p3_dout_en (p3_dout_en),
.p3_sel (),
.p4_dout (),
.p4_dout_en (),
.p4_sel (),
.p5_dout (),
.p5_dout_en (),
.p5_sel (),
.p6_dout (),
.p6_dout_en (),
.p6_sel (),
.per_dout (per_dout_dio),
.mclk (mclk),
.p1_din (p1_din),
.p2_din (p2_din),
.p3_din (8'h00),
.p4_din (p4_din),
.p5_din (8'h00),
.p6_din (8'h00),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_timerA timerA_0 (
.irq_ta0 (irq_ta0),
.irq_ta1 (irq_ta1),
.per_dout (per_dout_tA),
.ta_out0 (ta_out0),
.ta_out0_en (ta_out0_en),
.ta_out1 (ta_out1),
.ta_out1_en (ta_out1_en),
.ta_out2 (ta_out2),
.ta_out2_en (ta_out2_en),
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.inclk (inclk),
.irq_ta0_acc (irq_acc[9]),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.ta_cci0a (ta_cci0a),
.ta_cci0b (ta_cci0b),
.ta_cci1a (ta_cci1a),
.ta_cci1b (1'b0),
.ta_cci2a (ta_cci2a),
.ta_cci2b (1'b0),
.taclk (taclk)
);
omsp_uart #(.BASE_ADDR(15'h0080)) hw_uart (
.irq_uart_rx (irq_uart_rx),
.irq_uart_tx (irq_uart_tx),
.per_dout (per_dout_uart),
.uart_txd (hw_uart_txd),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.uart_rxd (hw_uart_rxd)
);
omsp_uart #(.BASE_ADDR(15'h0088)) hw_uart2 (
.irq_uart_rx (),
.irq_uart_tx (),
.per_dout (per_dout_uart2),
.uart_txd (hw_uart2_txd),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.uart_rxd (1'b0)
);
omsp_tsc tsc(
.per_dout (per_dout_tsc),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_spi_master spi_master(
.per_dout (per_dout_spi),
.sck (spi_sck),
.ss (spi_ss),
.mosi (spi_mosi),
.mclk (mclk),
.miso (spi_miso),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
dma_attacker dma_periph(
.per_dout (per_dout_dma),
.dma_addr (dma_addr),
.dma_en (dma_en),
.dma_we (dma_we),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.dma_ready(dma_ready)
);
omsp_led_digits led_digits(
.per_dout (per_dout_led),
.so (led_so),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
assign per_dout = per_dout_dio |
per_dout_tA |
per_dout_uart |
per_dout_uart2 |
per_dout_tsc |
per_dout_dma |
per_dout_led |
per_dout_spi;
assign nmi = 1'b0;
assign irq_bus = {1'b0,
1'b0,
1'b0,
1'b0,
irq_ta0,
irq_ta1,
irq_uart_rx,
irq_uart_tx,
1'b0,
1'b0,
irq_port2,
irq_port1,
1'b0,
1'b0};
wire [7:0] p1_io_mux_b_unconnected;
wire [7:0] p1_io_dout;
wire [7:0] p1_io_dout_en;
wire [7:0] p1_io_din;
io_mux #8 io_mux_p1 (
.a_din (p1_din),
.a_dout (p1_dout),
.a_dout_en (p1_dout_en),
.b_din ({p1_io_mux_b_unconnected[7],
p1_io_mux_b_unconnected[6],
p1_io_mux_b_unconnected[5],
p1_io_mux_b_unconnected[4],
ta_cci2a,
ta_cci1a,
ta_cci0a,
taclk
}),
.b_dout ({ta_out2,
ta_out1,
ta_out0,
(smclk_en & mclk),
ta_out2,
ta_out1,
ta_out0,
1'b0
}),
.b_dout_en ({ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b1,
ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b0
}),
.io_din (p1_io_din),
.io_dout (p1_io_dout),
.io_dout_en (p1_io_dout_en),
.sel (p1_sel)
);
wire [7:0] p2_io_mux_b_unconnected;
wire [7:0] p2_io_dout;
wire [7:0] p2_io_dout_en;
wire [7:0] p2_io_din;
io_mux #8 io_mux_p2 (
.a_din (p2_din),
.a_dout (p2_dout),
.a_dout_en (p2_dout_en),
.b_din ({p2_io_mux_b_unconnected[7],
p2_io_mux_b_unconnected[6],
p2_io_mux_b_unconnected[5],
p2_io_mux_b_unconnected[4],
p2_io_mux_b_unconnected[3],
ta_cci0b,
inclk,
p2_io_mux_b_unconnected[0]
}),
.b_dout ({1'b0,
1'b0,
1'b0,
ta_out2,
ta_out1,
1'b0,
1'b0,
(aclk_en & mclk)
}),
.b_dout_en ({1'b0,
1'b0,
1'b0,
ta_out2_en,
ta_out1_en,
1'b0,
1'b0,
1'b1
}),
.io_din (p2_io_din),
.io_dout (p2_io_dout),
.io_dout_en (p2_io_dout_en),
.sel (p2_sel)
);
assign p1_io_din[0] = chan_io[23];
assign p1_io_din[1] = chan_io[7];
assign p1_io_din[2] = chan_io[8];
assign p1_io_din[3] = chan_io[10];
assign p1_io_din[4] = chan_io[11];
assign p1_io_din[5] = chan_io[28];
assign p1_io_din[6] = chan_io[13];
assign p1_io_din[7] = chan_io[14];
assign chan_io[23] = p1_io_dout_en[0] ? p1_io_dout[0] : 1'bz;
assign chan_io[7] = p1_io_dout_en[1] ? p1_io_dout[1] : 1'bz;
assign chan_io[8] = p1_io_dout_en[2] ? p1_io_dout[2] : 1'bz;
assign chan_io[10] = p1_io_dout_en[3] ? p1_io_dout[3] : 1'bz;
assign chan_io[11] = p1_io_dout_en[4] ? p1_io_dout[4] : 1'bz;
assign chan_io[28] = p1_io_dout_en[5] ? p1_io_dout[5] : 1'bz;
assign chan_io[13] = p1_io_dout_en[6] ? p1_io_dout[6] : 1'bz;
assign chan_io[14] = p1_io_dout_en[7] ? p1_io_dout[7] : 1'bz;
assign dmem_cen_n = ~ dmem_cen;
assign pmem_cen_n = ~ pmem_cen;
assign dmem_wen_n = ~ dmem_wen;
assign pmem_wen_n = ~ pmem_wen;
ram_8x8k ram_hi (
.addra (dmem_addr),
.clka (clk_sys),
.dina (dmem_din[15:8]),
.douta (dmem_dout[15:8]),
.ena (dmem_cen_n),
.wea (dmem_wen_n[1])
);
ram_8x8k ram_lo (
.addra (dmem_addr),
.clka (clk_sys),
.dina (dmem_din[7:0]),
.douta (dmem_dout[7:0]),
.ena (dmem_cen_n),
.wea (dmem_wen_n[0])
);
rom_8x20_5k rom_hi (
.addra (pmem_addr),
.clka (clk_sys),
.dina (pmem_din[15:8]),
.douta (pmem_dout[15:8]),
.ena (pmem_cen_n),
.wea (pmem_wen_n[1])
);
rom_8x20_5k rom_lo (
.addra (pmem_addr),
.clka (clk_sys),
.dina (pmem_din[7:0]),
.douta (pmem_dout[7:0]),
.ena (pmem_cen_n),
.wea (pmem_wen_n[0])
);
assign p2_io_din[1:0] = 2'h00;
assign p2_io_din[7:3] = 5'h00;
endmodule | module openMSP430_fpga (
input wire fpgaClk_i,
output wire sdCke_o,
output wire sdClk_o,
input wire sdClkFb_i,
output wire sdCe_bo,
output wire sdRas_bo,
output wire sdCas_bo,
output wire sdWe_bo,
output wire sdDqml_o,
output wire sdDqmh_o,
output wire [1:0] sdBs_o,
output wire [12:0] sdAddr_o,
inout wire [15:0] sdData_io,
output wire usdflashCs_bo,
output wire flashCs_bo,
output wire sclk_o,
output wire mosi_o,
input wire miso_i,
inout wire chanClk_io,
inout wire [31:0] chan_io
); |
parameter integer foo = $clog2(16);
assign sdCke_o = 1'b0;
assign sdClk_o = 1'b0;
assign sdCe_bo = 1'b0;
assign sdRas_bo = 1'b0;
assign sdCas_bo = 1'b0;
assign sdWe_bo = 1'b0;
assign sdDqml_o = 1'b0;
assign sdDqmh_o = 1'b0;
assign sdBs_o = 2'b0;
assign sdAddr_o = 13'b0;
assign usdflashCs_bo = 1'b0;
assign flashCs_bo = 1'b0;
assign sclk_o = 1'b0;
assign mosi_o = 1'b0;
wire [15:0] dma_dout;
wire dma_ready;
wire dma_resp;
reg [15:0] dma_din;
reg dma_priority;
reg dma_wkup;
wire [15:1] dma_addr;
wire [1:0] dma_we;
wire dma_en;
wire [15:0] per_dout_dma;
reg dma_tfx_cancel;
wire [13:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_we;
wire [`DMEM_MSB:0] dmem_addr;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [1:0] dmem_wen_n;
wire [`PMEM_MSB:0] pmem_addr;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [1:0] pmem_wen_n;
wire [13:0] irq_acc;
wire [13:0] irq_bus;
wire [15:0] per_dout;
wire [15:0] dmem_dout;
wire [15:0] pmem_dout;
wire [7:0] p1_din;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_din;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p4_din;
wire [15:0] per_dout_dio;
wire [15:0] per_dout_tA;
wire irq_uart_rx;
wire irq_uart_tx;
wire [15:0] per_dout_uart;
wire hw_uart_txd;
wire hw_uart_rxd;
wire hw_uart_txd2;
wire [15:0] per_dout_uart2;
wire [15:0] per_dout_tsc;
wire [15:0] per_dout_led;
wire [7:0] led_so;
wire [15:0] per_dout_spi;
wire spi_mosi;
wire spi_miso;
wire spi_sck;
wire [2:0] spi_ss;
wire reset_pin;
wire dbg_sw = 1'b1;
assign chan_io[25] = dbg_uart_txd & hw_uart2_txd;
assign dbg_uart_rxd = chan_io[26];
assign chan_io[4] = hw_uart_txd;
assign hw_uart_rxd = chan_io[21];
`ifdef FPGA_CHARLIE
assign chan_io[3] = led_so[6];
assign chan_io[18] = led_so[4];
assign chan_io[1] = led_so[2];
assign chan_io[17] = led_so[0];
assign chan_io[0] = led_so[7];
assign chan_io[16] = led_so[5];
assign chanClk_io = led_so[3];
assign chan_io[15] = led_so[1];
`else
assign chan_io[3] = spi_sck;
assign spi_miso = chan_io[18] | chan_io[16];
assign chan_io[1] = spi_mosi;
assign chan_io[17] = spi_ss[0];
assign chan_io[0] = spi_sck;
assign chanClk_io = spi_mosi;
assign chan_io[15] = spi_ss[1];
`endif
IBUFG ibuf_clk_main (.O(clk_12M_in), .I(fpgaClk_i));
DCM_SP #(
.CLKFX_MULTIPLY(5),
.CLKFX_DIVIDE(3),
.CLKIN_PERIOD(83.333)
)dcm_inst(
.CLKFX (dcm_clk),
.CLK0 (CLK0_BUF),
.LOCKED (dcm_locked),
.CLKFB (CLKFB_IN),
.CLKIN (clk_12M_in),
.PSEN (1'b0),
.RST (reset_pin)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
defparam dcm_inst.CLKFX_MULTIPLY = 5;
defparam dcm_inst.CLKFX_DIVIDE = 3;
defparam dcm_int.CLKIN_PERIOD = 83.333;
BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk));
wire reset_pin_n = 1'b1;
assign reset_n = reset_pin_n & dcm_locked;
initial
begin
dma_din = 16'h0000;
dma_priority = 1'b0;
dma_wkup = 1'b0;
dma_tfx_cancel = 1'b0;
end
wire spm_violation;
openMSP430 openMSP430_0 (
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.dbg_uart_txd (dbg_uart_txd),
.dmem_addr (dmem_addr),
.dmem_cen (dmem_cen),
.dmem_din (dmem_din),
.dmem_wen (dmem_wen),
.irq_acc (irq_acc),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_we (per_we),
.per_en (per_en),
.pmem_addr (pmem_addr),
.pmem_cen (pmem_cen),
.pmem_din (pmem_din),
.pmem_wen (pmem_wen),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.dma_dout (dma_dout),
.dma_ready (dma_ready),
.dma_resp (dma_resp),
.cpu_en (1'b1),
.dbg_en (dbg_sw),
.dbg_uart_rxd (dbg_uart_rxd),
.dco_clk (clk_sys),
.dmem_dout (dmem_dout),
.irq (irq_bus),
.lfxt_clk (1'b0),
.dma_addr (dma_addr),
.dma_din (dma_din),
.dma_en (dma_en),
.dma_priority (dma_priority),
.dma_we (dma_we),
.dma_wkup (dma_wkup),
.nmi (nmi),
.per_dout (per_dout),
.pmem_dout (pmem_dout),
.reset_n (reset_n)
);
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(1),
.P4_EN(1),
.P5_EN(0),
.P6_EN(0)) gpio_0 (
.irq_port1 (irq_port1),
.irq_port2 (irq_port2),
.p1_dout (p1_dout),
.p1_dout_en (p1_dout_en),
.p1_sel (p1_sel),
.p2_dout (p2_dout),
.p2_dout_en (p2_dout_en),
.p2_sel (p2_sel),
.p3_dout (p3_dout),
.p3_dout_en (p3_dout_en),
.p3_sel (),
.p4_dout (),
.p4_dout_en (),
.p4_sel (),
.p5_dout (),
.p5_dout_en (),
.p5_sel (),
.p6_dout (),
.p6_dout_en (),
.p6_sel (),
.per_dout (per_dout_dio),
.mclk (mclk),
.p1_din (p1_din),
.p2_din (p2_din),
.p3_din (8'h00),
.p4_din (p4_din),
.p5_din (8'h00),
.p6_din (8'h00),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_timerA timerA_0 (
.irq_ta0 (irq_ta0),
.irq_ta1 (irq_ta1),
.per_dout (per_dout_tA),
.ta_out0 (ta_out0),
.ta_out0_en (ta_out0_en),
.ta_out1 (ta_out1),
.ta_out1_en (ta_out1_en),
.ta_out2 (ta_out2),
.ta_out2_en (ta_out2_en),
.aclk_en (aclk_en),
.dbg_freeze (dbg_freeze),
.inclk (inclk),
.irq_ta0_acc (irq_acc[9]),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.ta_cci0a (ta_cci0a),
.ta_cci0b (ta_cci0b),
.ta_cci1a (ta_cci1a),
.ta_cci1b (1'b0),
.ta_cci2a (ta_cci2a),
.ta_cci2b (1'b0),
.taclk (taclk)
);
omsp_uart #(.BASE_ADDR(15'h0080)) hw_uart (
.irq_uart_rx (irq_uart_rx),
.irq_uart_tx (irq_uart_tx),
.per_dout (per_dout_uart),
.uart_txd (hw_uart_txd),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.uart_rxd (hw_uart_rxd)
);
omsp_uart #(.BASE_ADDR(15'h0088)) hw_uart2 (
.irq_uart_rx (),
.irq_uart_tx (),
.per_dout (per_dout_uart2),
.uart_txd (hw_uart2_txd),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.smclk_en (smclk_en),
.uart_rxd (1'b0)
);
omsp_tsc tsc(
.per_dout (per_dout_tsc),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
omsp_spi_master spi_master(
.per_dout (per_dout_spi),
.sck (spi_sck),
.ss (spi_ss),
.mosi (spi_mosi),
.mclk (mclk),
.miso (spi_miso),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
dma_attacker dma_periph(
.per_dout (per_dout_dma),
.dma_addr (dma_addr),
.dma_en (dma_en),
.dma_we (dma_we),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst),
.dma_ready(dma_ready)
);
omsp_led_digits led_digits(
.per_dout (per_dout_led),
.so (led_so),
.mclk (mclk),
.per_addr (per_addr),
.per_din (per_din),
.per_en (per_en),
.per_we (per_we),
.puc_rst (puc_rst)
);
assign per_dout = per_dout_dio |
per_dout_tA |
per_dout_uart |
per_dout_uart2 |
per_dout_tsc |
per_dout_dma |
per_dout_led |
per_dout_spi;
assign nmi = 1'b0;
assign irq_bus = {1'b0,
1'b0,
1'b0,
1'b0,
irq_ta0,
irq_ta1,
irq_uart_rx,
irq_uart_tx,
1'b0,
1'b0,
irq_port2,
irq_port1,
1'b0,
1'b0};
wire [7:0] p1_io_mux_b_unconnected;
wire [7:0] p1_io_dout;
wire [7:0] p1_io_dout_en;
wire [7:0] p1_io_din;
io_mux #8 io_mux_p1 (
.a_din (p1_din),
.a_dout (p1_dout),
.a_dout_en (p1_dout_en),
.b_din ({p1_io_mux_b_unconnected[7],
p1_io_mux_b_unconnected[6],
p1_io_mux_b_unconnected[5],
p1_io_mux_b_unconnected[4],
ta_cci2a,
ta_cci1a,
ta_cci0a,
taclk
}),
.b_dout ({ta_out2,
ta_out1,
ta_out0,
(smclk_en & mclk),
ta_out2,
ta_out1,
ta_out0,
1'b0
}),
.b_dout_en ({ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b1,
ta_out2_en,
ta_out1_en,
ta_out0_en,
1'b0
}),
.io_din (p1_io_din),
.io_dout (p1_io_dout),
.io_dout_en (p1_io_dout_en),
.sel (p1_sel)
);
wire [7:0] p2_io_mux_b_unconnected;
wire [7:0] p2_io_dout;
wire [7:0] p2_io_dout_en;
wire [7:0] p2_io_din;
io_mux #8 io_mux_p2 (
.a_din (p2_din),
.a_dout (p2_dout),
.a_dout_en (p2_dout_en),
.b_din ({p2_io_mux_b_unconnected[7],
p2_io_mux_b_unconnected[6],
p2_io_mux_b_unconnected[5],
p2_io_mux_b_unconnected[4],
p2_io_mux_b_unconnected[3],
ta_cci0b,
inclk,
p2_io_mux_b_unconnected[0]
}),
.b_dout ({1'b0,
1'b0,
1'b0,
ta_out2,
ta_out1,
1'b0,
1'b0,
(aclk_en & mclk)
}),
.b_dout_en ({1'b0,
1'b0,
1'b0,
ta_out2_en,
ta_out1_en,
1'b0,
1'b0,
1'b1
}),
.io_din (p2_io_din),
.io_dout (p2_io_dout),
.io_dout_en (p2_io_dout_en),
.sel (p2_sel)
);
assign p1_io_din[0] = chan_io[23];
assign p1_io_din[1] = chan_io[7];
assign p1_io_din[2] = chan_io[8];
assign p1_io_din[3] = chan_io[10];
assign p1_io_din[4] = chan_io[11];
assign p1_io_din[5] = chan_io[28];
assign p1_io_din[6] = chan_io[13];
assign p1_io_din[7] = chan_io[14];
assign chan_io[23] = p1_io_dout_en[0] ? p1_io_dout[0] : 1'bz;
assign chan_io[7] = p1_io_dout_en[1] ? p1_io_dout[1] : 1'bz;
assign chan_io[8] = p1_io_dout_en[2] ? p1_io_dout[2] : 1'bz;
assign chan_io[10] = p1_io_dout_en[3] ? p1_io_dout[3] : 1'bz;
assign chan_io[11] = p1_io_dout_en[4] ? p1_io_dout[4] : 1'bz;
assign chan_io[28] = p1_io_dout_en[5] ? p1_io_dout[5] : 1'bz;
assign chan_io[13] = p1_io_dout_en[6] ? p1_io_dout[6] : 1'bz;
assign chan_io[14] = p1_io_dout_en[7] ? p1_io_dout[7] : 1'bz;
assign dmem_cen_n = ~ dmem_cen;
assign pmem_cen_n = ~ pmem_cen;
assign dmem_wen_n = ~ dmem_wen;
assign pmem_wen_n = ~ pmem_wen;
ram_8x8k ram_hi (
.addra (dmem_addr),
.clka (clk_sys),
.dina (dmem_din[15:8]),
.douta (dmem_dout[15:8]),
.ena (dmem_cen_n),
.wea (dmem_wen_n[1])
);
ram_8x8k ram_lo (
.addra (dmem_addr),
.clka (clk_sys),
.dina (dmem_din[7:0]),
.douta (dmem_dout[7:0]),
.ena (dmem_cen_n),
.wea (dmem_wen_n[0])
);
rom_8x20_5k rom_hi (
.addra (pmem_addr),
.clka (clk_sys),
.dina (pmem_din[15:8]),
.douta (pmem_dout[15:8]),
.ena (pmem_cen_n),
.wea (pmem_wen_n[1])
);
rom_8x20_5k rom_lo (
.addra (pmem_addr),
.clka (clk_sys),
.dina (pmem_din[7:0]),
.douta (pmem_dout[7:0]),
.ena (pmem_cen_n),
.wea (pmem_wen_n[0])
);
assign p2_io_din[1:0] = 2'h00;
assign p2_io_din[7:3] = 5'h00;
endmodule | 18 |
141,513 | data/full_repos/permissive/9579723/CPU.sv | 9,579,723 | CPU.sv | sv | 517 | 128 | [] | [] | [] | null | line:41: before: "{" | null | 1: b'%Error: data/full_repos/permissive/9579723/CPU.sv:75: Cannot find file containing module: \'ALU\'\n ALU alu(.op(IB[4:0]),\n ^~~\n ... Looked in:\n data/full_repos/permissive/9579723,data/full_repos/permissive/9579723/ALU\n data/full_repos/permissive/9579723,data/full_repos/permissive/9579723/ALU.v\n data/full_repos/permissive/9579723,data/full_repos/permissive/9579723/ALU.sv\n ALU\n ALU.v\n ALU.sv\n obj_dir/ALU\n obj_dir/ALU.v\n obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/9579723/CPU.sv:394: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'extraWord_a\' generates 1 bits.\n : ... In instance CPU\n PC <= PC + extraWord_a + extraWord_b;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9579723/CPU.sv:394: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'extraWord_b\' generates 1 bits.\n : ... In instance CPU\n PC <= PC + extraWord_a + extraWord_b;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 312,087 | module | module CPU (
input CORE_CLK,
input RESET,
output DBG_halt,
output DBG_flag,
output [15:0] DBG_PC,
output [15:0] RAM_addr,
output [15:0] RAM_data,
output RAM_wr,
input [15:0] RAM_q
);
typedef enum {
S_halt,
S_fetch,
S_fetch_a,
S_nextword_a,
S_fetch_b,
S_nextword_b,
S_set_write,
S_arith_write,
S_inc_ij,
S_dec_ij,
S_if,
S_skip,
S_jump_subroutine
} State;
State S;
State nextState;
assign DBG_halt = S == S_halt;
reg DEBUG_flag;
assign DBG_flag = DEBUG_flag;
assign DBG_PC = PC;
reg [15:0] GP [7:0], PC = 16'h0000, SP = 16'h0000, EX, IA = 16'h0000;
reg [15:0] IB;
reg [15:0] NW;
reg skip;
reg [3:0] wait_tick = 4'h0;
reg [15:0] b, a;
wire [15:0] ALU_q, ALU_EX;
wire ALU_cl, ALU_eq, ALU_lt, ALU_un;
ALU alu(.op(IB[4:0]),
.b(b),
.a(a),
.EXin(EX),
.q(ALU_q),
.EXout(ALU_EX),
.cl(ALU_cl),
.eq(ALU_eq),
.lt(ALU_lt),
.un(ALU_un)
);
wire spop = ~|IB[4:0];
wire extraWord_a, extraWord_b;
always_comb
begin
case (IB[15:10])
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E,6'h1F:
extraWord_a <= 1'b1;
default:
extraWord_a <= 1'b0;
endcase
case (IB[9:5])
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E,5'h1F:
extraWord_b <= 1'b1;
default:
extraWord_b <= 1'b0;
endcase
end
always_comb
begin
RAM_addr = 16'h0000;
RAM_data = 16'h0000;
RAM_wr = 1'b0;
case (S)
S_fetch:
RAM_addr = PC;
S_fetch_a: begin
case (IB[15:10])
6'h08,6'h09,6'h0A,6'h0B,6'h0C,6'h0D,6'h0E,6'h0F:
RAM_addr = GP[IB[12:10]];
6'h18,6'h19:
RAM_addr = SP;
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E,6'h1F:
RAM_addr = PC;
endcase
end
S_nextword_a: begin
case (IB[15:10])
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17:
RAM_addr = GP[IB[12:10]] + NW;
6'h1A:
RAM_addr = SP + NW;
6'h1E:
RAM_addr = NW;
endcase
end
S_fetch_b: begin
case (IB[9:5])
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F:
RAM_addr = GP[IB[7:5]];
5'h18:
RAM_addr = SP - 16'h0001;
5'h19:
RAM_addr = SP;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E,5'h1F:
RAM_addr = PC;
endcase
end
S_nextword_b: begin
case (IB[9:5])
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17:
RAM_addr = GP[IB[7:5]] + NW;
5'h1A:
RAM_addr = SP + NW;
5'h1E:
RAM_addr = NW;
endcase
end
S_set_write: begin
case (IB[9:5])
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F: begin
RAM_addr = GP[IB[7:5]];
RAM_wr = 1'b1;
end
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17: begin
RAM_addr = GP[IB[7:5]] + NW;
RAM_wr = 1'b1;
end
5'h18,5'h19: begin
RAM_addr = SP;
RAM_wr = 1'b1;
end
5'h1A: begin
RAM_addr = SP + NW;
RAM_wr = 1'b1;
end
5'h1E: begin
RAM_addr = NW;
RAM_wr = 1'b1;
end
endcase
RAM_data = a;
end
S_arith_write: begin
case (IB[9:5])
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F: begin
RAM_addr = GP[IB[7:5]];
RAM_wr = 1'b1;
end
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17: begin
RAM_addr = GP[IB[7:5]] + NW;
RAM_wr = 1'b1;
end
5'h18,5'h19: begin
RAM_addr = SP;
RAM_wr = 1'b1;
end
5'h1A: begin
RAM_addr = SP + NW;
RAM_wr = 1'b1;
end
5'h1E: begin
RAM_addr = NW;
RAM_wr = 1'b1;
end
endcase
RAM_data = ALU_q;
end
S_jump_subroutine: begin
RAM_addr = SP - 16'h0001;
RAM_data = PC;
RAM_wr = 1'b1;
end
endcase
end
always_ff @(negedge CORE_CLK or posedge RESET)
begin
if (RESET) begin
PC <= 16'h0000;
SP <= 16'h0000;
IA <= 16'h0000;
S <= S_fetch;
skip <= 1'b0;
DEBUG_flag <= '0;
end
else if (|wait_tick)
wait_tick <= wait_tick - 4'h1;
else begin
case (S)
S_fetch: begin
IB <= RAM_q;
PC <= PC + 16'h0001;
end
S_fetch_a:
case (IB[15:10])
6'h00,6'h01,6'h02,6'h03,6'h04,6'h05,6'h06,6'h07:
a <= GP[IB[12:10]];
6'h08,6'h09,6'h0A,6'h0B,6'h0C,6'h0D,6'h0E,6'h0F,6'h19:
a <= RAM_q;
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E: begin
NW <= RAM_q;
PC <= PC + 16'h0001;
end
6'h18: begin
a <= RAM_q;
SP <= SP + 16'h0001;
end
6'h1B:
a <= SP;
6'h1C:
a <= PC;
6'h1D:
a <= EX;
6'h1F: begin
a <= RAM_q;
PC <= PC + 16'h0001;
wait_tick <= 4'h4;
end
default:
a <= {{11{1'b0}},IB[14:10]} - 16'h0001;
endcase
S_nextword_a: begin
a <= RAM_q;
wait_tick <= 4'h3;
end
S_fetch_b:
case (IB[9:5])
5'h00,5'h01,5'h02,5'h03,5'h04,5'h05,5'h06,5'h07:
b <= GP[IB[7:5]];
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F,5'h19:
b <= RAM_q;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E: begin
NW <= RAM_q;
PC <= PC + 16'h0001;
end
5'h18: begin
b <= RAM_q;
SP <= SP - 16'h0001;
end
5'h1B:
b <= SP;
5'h1C:
b <= PC;
5'h1D:
b <= EX;
5'h1F: begin
b <= RAM_q;
PC <= PC + 16'h0001;
wait_tick <= 4'h4;
end
endcase
S_nextword_b: begin
b <= RAM_q;
wait_tick <= 4'h3;
end
S_set_write:
case (IB[9:5])
5'h00,5'h01,5'h02,5'h03,5'h04,5'h05,5'h06,5'h07:
GP[IB[7:5]] <= a;
5'h1b:
SP <= a;
5'h1c:
PC <= a;
5'h1d:
EX <= a;
endcase
S_arith_write: begin
case (IB[9:5])
5'h00,5'h01,5'h02,5'h03,5'h04,5'h05,5'h06,5'h07:
GP[IB[7:5]] <= ALU_q;
5'h1b:
SP <= ALU_q;
5'h1c:
PC <= ALU_q;
5'h1d:
EX <= ALU_q;
endcase
case (IB[4:0])
5'h02,5'h03,5'h04,5'h05:
wait_tick <= 4'h4;
5'h06,5'h07,5'h08,5'h09:
wait_tick <= 4'h8;
endcase
case (IB[4:0])
5'h02,5'h03,5'h04,5'h05,5'h06,5'h07,5'h0D,5'h0E,5'h0F,5'h1A,5'h1B:
EX <= ALU_EX;
endcase
end
S_inc_ij: begin
GP[6] <= GP[6] + 16'h0001;
GP[7] <= GP[7] + 16'h0001;
wait_tick <= 4'h3;
end
S_dec_ij: begin
GP[6] <= GP[6] - 16'h0001;
GP[7] <= GP[7] - 16'h0001;
wait_tick <= 4'h3;
end
S_if: begin
case (IB[4:0])
5'b10000:
if (ALU_cl)
skip <= 1'b1;
5'b10001:
if (!ALU_cl)
skip <= 1'b1;
5'b10010:
if (!ALU_eq)
skip <= 1'b1;
5'b10011:
if (ALU_eq)
skip <= 1'b1;
5'b10100:
if (ALU_lt || ALU_eq)
skip <= 1'b1;
5'b10101:
if (ALU_un || ALU_eq)
skip <= 1'b1;
5'b10110:
if (!ALU_lt)
skip <= 1'b1;
5'b10111:
if (!ALU_un)
skip <= 1'b1;
endcase
wait_tick <= 4'h4;
end
S_skip: begin
PC <= PC + extraWord_a + extraWord_b;
if (IB[4:3] != 2'b10)
skip <= 1'b0;
wait_tick <= 4'h2;
end
S_jump_subroutine: begin
SP <= SP - 16'h0001;
PC <= a;
wait_tick <= 4'h9;
end
endcase
S <= nextState;
end
end
always_comb
case (S)
S_fetch:
if (skip)
nextState = S_skip;
else
nextState = S_fetch_a;
S_fetch_a:
case (IB[15:10])
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E:
nextState = S_nextword_a;
default:
if (spop)
case (IB[9:5])
5'h01:
nextState = S_jump_subroutine;
default:
nextState = S_halt;
endcase
else
nextState = S_fetch_b;
endcase
S_nextword_a: begin
if (spop)
case (IB[9:5])
5'h01:
nextState = S_jump_subroutine;
default:
nextState = S_halt;
endcase
else
nextState = S_fetch_b;
end
S_fetch_b:
case (IB[9:5])
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E:
nextState = S_nextword_b;
default:
case (IB[4:0])
5'h01,5'h1E,5'h1F:
nextState = S_set_write;
5'h02,5'h03,5'h04,5'h05,5'h06,5'h07,5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F,5'h1A,5'h1B:
nextState = S_arith_write;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17:
nextState = S_if;
default:
nextState = S_halt;
endcase
endcase
S_nextword_b:
case (IB[4:0])
5'h01,5'h1E,5'h1F:
nextState = S_set_write;
5'h02,5'h03,5'h04,5'h05,5'h06,5'h07,5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F,5'h1A,5'h1B:
nextState = S_arith_write;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17:
nextState = S_if;
default:
nextState = S_halt;
endcase
S_set_write:
case (IB[4:0])
5'h01:
nextState = S_fetch;
5'h1e:
nextState = S_inc_ij;
5'h1f:
nextState = S_dec_ij;
default:
nextState = S_halt;
endcase
S_arith_write:
nextState = S_fetch;
S_inc_ij:
nextState = S_fetch;
S_dec_ij:
nextState = S_fetch;
S_if:
nextState = S_fetch;
S_skip:
nextState = S_fetch;
S_jump_subroutine:
nextState = S_fetch;
default:
nextState = S_halt;
endcase
endmodule | module CPU (
input CORE_CLK,
input RESET,
output DBG_halt,
output DBG_flag,
output [15:0] DBG_PC,
output [15:0] RAM_addr,
output [15:0] RAM_data,
output RAM_wr,
input [15:0] RAM_q
); |
typedef enum {
S_halt,
S_fetch,
S_fetch_a,
S_nextword_a,
S_fetch_b,
S_nextword_b,
S_set_write,
S_arith_write,
S_inc_ij,
S_dec_ij,
S_if,
S_skip,
S_jump_subroutine
} State;
State S;
State nextState;
assign DBG_halt = S == S_halt;
reg DEBUG_flag;
assign DBG_flag = DEBUG_flag;
assign DBG_PC = PC;
reg [15:0] GP [7:0], PC = 16'h0000, SP = 16'h0000, EX, IA = 16'h0000;
reg [15:0] IB;
reg [15:0] NW;
reg skip;
reg [3:0] wait_tick = 4'h0;
reg [15:0] b, a;
wire [15:0] ALU_q, ALU_EX;
wire ALU_cl, ALU_eq, ALU_lt, ALU_un;
ALU alu(.op(IB[4:0]),
.b(b),
.a(a),
.EXin(EX),
.q(ALU_q),
.EXout(ALU_EX),
.cl(ALU_cl),
.eq(ALU_eq),
.lt(ALU_lt),
.un(ALU_un)
);
wire spop = ~|IB[4:0];
wire extraWord_a, extraWord_b;
always_comb
begin
case (IB[15:10])
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E,6'h1F:
extraWord_a <= 1'b1;
default:
extraWord_a <= 1'b0;
endcase
case (IB[9:5])
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E,5'h1F:
extraWord_b <= 1'b1;
default:
extraWord_b <= 1'b0;
endcase
end
always_comb
begin
RAM_addr = 16'h0000;
RAM_data = 16'h0000;
RAM_wr = 1'b0;
case (S)
S_fetch:
RAM_addr = PC;
S_fetch_a: begin
case (IB[15:10])
6'h08,6'h09,6'h0A,6'h0B,6'h0C,6'h0D,6'h0E,6'h0F:
RAM_addr = GP[IB[12:10]];
6'h18,6'h19:
RAM_addr = SP;
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E,6'h1F:
RAM_addr = PC;
endcase
end
S_nextword_a: begin
case (IB[15:10])
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17:
RAM_addr = GP[IB[12:10]] + NW;
6'h1A:
RAM_addr = SP + NW;
6'h1E:
RAM_addr = NW;
endcase
end
S_fetch_b: begin
case (IB[9:5])
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F:
RAM_addr = GP[IB[7:5]];
5'h18:
RAM_addr = SP - 16'h0001;
5'h19:
RAM_addr = SP;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E,5'h1F:
RAM_addr = PC;
endcase
end
S_nextword_b: begin
case (IB[9:5])
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17:
RAM_addr = GP[IB[7:5]] + NW;
5'h1A:
RAM_addr = SP + NW;
5'h1E:
RAM_addr = NW;
endcase
end
S_set_write: begin
case (IB[9:5])
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F: begin
RAM_addr = GP[IB[7:5]];
RAM_wr = 1'b1;
end
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17: begin
RAM_addr = GP[IB[7:5]] + NW;
RAM_wr = 1'b1;
end
5'h18,5'h19: begin
RAM_addr = SP;
RAM_wr = 1'b1;
end
5'h1A: begin
RAM_addr = SP + NW;
RAM_wr = 1'b1;
end
5'h1E: begin
RAM_addr = NW;
RAM_wr = 1'b1;
end
endcase
RAM_data = a;
end
S_arith_write: begin
case (IB[9:5])
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F: begin
RAM_addr = GP[IB[7:5]];
RAM_wr = 1'b1;
end
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17: begin
RAM_addr = GP[IB[7:5]] + NW;
RAM_wr = 1'b1;
end
5'h18,5'h19: begin
RAM_addr = SP;
RAM_wr = 1'b1;
end
5'h1A: begin
RAM_addr = SP + NW;
RAM_wr = 1'b1;
end
5'h1E: begin
RAM_addr = NW;
RAM_wr = 1'b1;
end
endcase
RAM_data = ALU_q;
end
S_jump_subroutine: begin
RAM_addr = SP - 16'h0001;
RAM_data = PC;
RAM_wr = 1'b1;
end
endcase
end
always_ff @(negedge CORE_CLK or posedge RESET)
begin
if (RESET) begin
PC <= 16'h0000;
SP <= 16'h0000;
IA <= 16'h0000;
S <= S_fetch;
skip <= 1'b0;
DEBUG_flag <= '0;
end
else if (|wait_tick)
wait_tick <= wait_tick - 4'h1;
else begin
case (S)
S_fetch: begin
IB <= RAM_q;
PC <= PC + 16'h0001;
end
S_fetch_a:
case (IB[15:10])
6'h00,6'h01,6'h02,6'h03,6'h04,6'h05,6'h06,6'h07:
a <= GP[IB[12:10]];
6'h08,6'h09,6'h0A,6'h0B,6'h0C,6'h0D,6'h0E,6'h0F,6'h19:
a <= RAM_q;
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E: begin
NW <= RAM_q;
PC <= PC + 16'h0001;
end
6'h18: begin
a <= RAM_q;
SP <= SP + 16'h0001;
end
6'h1B:
a <= SP;
6'h1C:
a <= PC;
6'h1D:
a <= EX;
6'h1F: begin
a <= RAM_q;
PC <= PC + 16'h0001;
wait_tick <= 4'h4;
end
default:
a <= {{11{1'b0}},IB[14:10]} - 16'h0001;
endcase
S_nextword_a: begin
a <= RAM_q;
wait_tick <= 4'h3;
end
S_fetch_b:
case (IB[9:5])
5'h00,5'h01,5'h02,5'h03,5'h04,5'h05,5'h06,5'h07:
b <= GP[IB[7:5]];
5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F,5'h19:
b <= RAM_q;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E: begin
NW <= RAM_q;
PC <= PC + 16'h0001;
end
5'h18: begin
b <= RAM_q;
SP <= SP - 16'h0001;
end
5'h1B:
b <= SP;
5'h1C:
b <= PC;
5'h1D:
b <= EX;
5'h1F: begin
b <= RAM_q;
PC <= PC + 16'h0001;
wait_tick <= 4'h4;
end
endcase
S_nextword_b: begin
b <= RAM_q;
wait_tick <= 4'h3;
end
S_set_write:
case (IB[9:5])
5'h00,5'h01,5'h02,5'h03,5'h04,5'h05,5'h06,5'h07:
GP[IB[7:5]] <= a;
5'h1b:
SP <= a;
5'h1c:
PC <= a;
5'h1d:
EX <= a;
endcase
S_arith_write: begin
case (IB[9:5])
5'h00,5'h01,5'h02,5'h03,5'h04,5'h05,5'h06,5'h07:
GP[IB[7:5]] <= ALU_q;
5'h1b:
SP <= ALU_q;
5'h1c:
PC <= ALU_q;
5'h1d:
EX <= ALU_q;
endcase
case (IB[4:0])
5'h02,5'h03,5'h04,5'h05:
wait_tick <= 4'h4;
5'h06,5'h07,5'h08,5'h09:
wait_tick <= 4'h8;
endcase
case (IB[4:0])
5'h02,5'h03,5'h04,5'h05,5'h06,5'h07,5'h0D,5'h0E,5'h0F,5'h1A,5'h1B:
EX <= ALU_EX;
endcase
end
S_inc_ij: begin
GP[6] <= GP[6] + 16'h0001;
GP[7] <= GP[7] + 16'h0001;
wait_tick <= 4'h3;
end
S_dec_ij: begin
GP[6] <= GP[6] - 16'h0001;
GP[7] <= GP[7] - 16'h0001;
wait_tick <= 4'h3;
end
S_if: begin
case (IB[4:0])
5'b10000:
if (ALU_cl)
skip <= 1'b1;
5'b10001:
if (!ALU_cl)
skip <= 1'b1;
5'b10010:
if (!ALU_eq)
skip <= 1'b1;
5'b10011:
if (ALU_eq)
skip <= 1'b1;
5'b10100:
if (ALU_lt || ALU_eq)
skip <= 1'b1;
5'b10101:
if (ALU_un || ALU_eq)
skip <= 1'b1;
5'b10110:
if (!ALU_lt)
skip <= 1'b1;
5'b10111:
if (!ALU_un)
skip <= 1'b1;
endcase
wait_tick <= 4'h4;
end
S_skip: begin
PC <= PC + extraWord_a + extraWord_b;
if (IB[4:3] != 2'b10)
skip <= 1'b0;
wait_tick <= 4'h2;
end
S_jump_subroutine: begin
SP <= SP - 16'h0001;
PC <= a;
wait_tick <= 4'h9;
end
endcase
S <= nextState;
end
end
always_comb
case (S)
S_fetch:
if (skip)
nextState = S_skip;
else
nextState = S_fetch_a;
S_fetch_a:
case (IB[15:10])
6'h10,6'h11,6'h12,6'h13,6'h14,6'h15,6'h16,6'h17,6'h1A,6'h1E:
nextState = S_nextword_a;
default:
if (spop)
case (IB[9:5])
5'h01:
nextState = S_jump_subroutine;
default:
nextState = S_halt;
endcase
else
nextState = S_fetch_b;
endcase
S_nextword_a: begin
if (spop)
case (IB[9:5])
5'h01:
nextState = S_jump_subroutine;
default:
nextState = S_halt;
endcase
else
nextState = S_fetch_b;
end
S_fetch_b:
case (IB[9:5])
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17,5'h1A,5'h1E:
nextState = S_nextword_b;
default:
case (IB[4:0])
5'h01,5'h1E,5'h1F:
nextState = S_set_write;
5'h02,5'h03,5'h04,5'h05,5'h06,5'h07,5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F,5'h1A,5'h1B:
nextState = S_arith_write;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17:
nextState = S_if;
default:
nextState = S_halt;
endcase
endcase
S_nextword_b:
case (IB[4:0])
5'h01,5'h1E,5'h1F:
nextState = S_set_write;
5'h02,5'h03,5'h04,5'h05,5'h06,5'h07,5'h08,5'h09,5'h0A,5'h0B,5'h0C,5'h0D,5'h0E,5'h0F,5'h1A,5'h1B:
nextState = S_arith_write;
5'h10,5'h11,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17:
nextState = S_if;
default:
nextState = S_halt;
endcase
S_set_write:
case (IB[4:0])
5'h01:
nextState = S_fetch;
5'h1e:
nextState = S_inc_ij;
5'h1f:
nextState = S_dec_ij;
default:
nextState = S_halt;
endcase
S_arith_write:
nextState = S_fetch;
S_inc_ij:
nextState = S_fetch;
S_dec_ij:
nextState = S_fetch;
S_if:
nextState = S_fetch;
S_skip:
nextState = S_fetch;
S_jump_subroutine:
nextState = S_fetch;
default:
nextState = S_halt;
endcase
endmodule | 1 |
141,517 | data/full_repos/permissive/9579723/ALU/ALU.sv | 9,579,723 | ALU.sv | sv | 238 | 89 | [] | [] | [] | [(21, 237)] | null | null | 1: b'%Error: data/full_repos/permissive/9579723/ALU/ALU.sv:185: Cannot find file containing module: \'add_sub_X\'\n add_sub_X addsub(b, a, EXin, add_sub, add_EX, addsub_q, addsub_EX, eq, lt, un);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/add_sub_X\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/add_sub_X.v\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/add_sub_X.sv\n add_sub_X\n add_sub_X.v\n add_sub_X.sv\n obj_dir/add_sub_X\n obj_dir/add_sub_X.v\n obj_dir/add_sub_X.sv\n%Error: data/full_repos/permissive/9579723/ALU/ALU.sv:188: Cannot find file containing module: \'mul_div_mod\'\n mul_div_mod mdm(b, a, mul_div_sgn, mul_q, mul_EX, div_q, div_EX, mod_q);\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9579723/ALU/ALU.sv:201: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s CONST \'15\'h0\' generates 15 bits.\n : ... In instance ALU\n assign sh_b[15:0] = shift_dir ? 15\'d0 : b;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/9579723/ALU/ALU.sv:202: Cannot find file containing module: \'shift16\'\n shift16 shifter(sh_b, shift_dir, a[3:0], sh_out);\n ^~~~~~~\n%Error: data/full_repos/permissive/9579723/ALU/ALU.sv:207: Cannot find file containing module: \'ashift16\'\n ashift16 ashifter({b, 16\'d0}, a[3:0], {ash_q, ash_EX});\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 312,092 | module | module ALU (
input [4:0] op,
input [15:0] b,
input [15:0] a,
input [15:0] EXin,
output [15:0] q,
output [15:0] EXout,
output cl,
output eq,
output lt,
output un
);
wire and_or, add_EX, add_sub, shift_dir, mul_div_sgn;
wire [2:0] out_mux;
always_comb
begin
case(op)
5'h02: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h03,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b1;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h1A: begin
and_or <= 1'b0;
add_EX <= 1'b1;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h1B: begin
and_or <= 1'b0;
add_EX <= 1'b1;
add_sub <= 1'b1;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h04: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b001;
end
5'h05: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b1;
out_mux <= 3'b001;
end
5'h06: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b010;
end
5'h07: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b1;
out_mux <= 3'b010;
end
5'h08: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b011;
end
5'h09: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b1;
out_mux <= 3'b011;
end
5'h0A,5'h10,5'h11: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b100;
end
5'h0B: begin
and_or <= 1'b1;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b100;
end
5'h0C: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b101;
end
5'h0D: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b1;
mul_div_sgn <= 1'b0;
out_mux <= 3'b110;
end
5'h0E: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b111;
end
5'h0F: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b110;
end
default: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
endcase
end
wire [15:0] addsub_q, and_out, and_q, xor_q, sh_q, ash_q, mul_q, div_q, mod_q;
wire [31:0] sh_out;
wire [15:0] addsub_EX, sh_EX, ash_EX, mul_EX, div_EX;
add_sub_X addsub(b, a, EXin, add_sub, add_EX, addsub_q, addsub_EX, eq, lt, un);
mul_div_mod mdm(b, a, mul_div_sgn, mul_q, mul_EX, div_q, div_EX, mod_q);
assign and_out = (b^{16{and_or}}) & (a^{16{and_or}});
assign and_q = and_out ^ {16{and_or}};
assign cl = ~|and_q;
assign xor_q = b ^ a;
wire [31:0] sh_b;
assign sh_b[31:16] = shift_dir ? b : 16'd0;
assign sh_b[15:0] = shift_dir ? 15'd0 : b;
shift16 shifter(sh_b, shift_dir, a[3:0], sh_out);
assign sh_q = shift_dir ? sh_out[31:16] : sh_out[15:0];
assign sh_EX = shift_dir ? sh_out[15:0] : sh_out[31:16];
ashift16 ashifter({b, 16'd0}, a[3:0], {ash_q, ash_EX});
always_comb
begin
q <= 16'h0000;
case(out_mux)
3'b000: q <= addsub_q;
3'b001: q <= mul_q;
3'b010: q <= div_q;
3'b011: q <= mod_q;
3'b100: q <= and_q;
3'b101: q <= xor_q;
3'b110: q <= sh_q;
3'b111: q <= ash_q;
endcase
end
always_comb
begin
EXout <= 16'h0000;
case(out_mux)
3'b000: EXout <= addsub_EX;
3'b001: EXout <= mul_EX;
3'b010: EXout <= div_EX;
3'b110: EXout <= sh_EX;
3'b111: EXout <= ash_EX;
default: EXout <= 16'h0000;
endcase
end
endmodule | module ALU (
input [4:0] op,
input [15:0] b,
input [15:0] a,
input [15:0] EXin,
output [15:0] q,
output [15:0] EXout,
output cl,
output eq,
output lt,
output un
); |
wire and_or, add_EX, add_sub, shift_dir, mul_div_sgn;
wire [2:0] out_mux;
always_comb
begin
case(op)
5'h02: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h03,5'h12,5'h13,5'h14,5'h15,5'h16,5'h17: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b1;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h1A: begin
and_or <= 1'b0;
add_EX <= 1'b1;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h1B: begin
and_or <= 1'b0;
add_EX <= 1'b1;
add_sub <= 1'b1;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
5'h04: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b001;
end
5'h05: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b1;
out_mux <= 3'b001;
end
5'h06: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b010;
end
5'h07: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b1;
out_mux <= 3'b010;
end
5'h08: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b011;
end
5'h09: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b1;
out_mux <= 3'b011;
end
5'h0A,5'h10,5'h11: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b100;
end
5'h0B: begin
and_or <= 1'b1;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b100;
end
5'h0C: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b101;
end
5'h0D: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b1;
mul_div_sgn <= 1'b0;
out_mux <= 3'b110;
end
5'h0E: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b111;
end
5'h0F: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b110;
end
default: begin
and_or <= 1'b0;
add_EX <= 1'b0;
add_sub <= 1'b0;
shift_dir <= 1'b0;
mul_div_sgn <= 1'b0;
out_mux <= 3'b000;
end
endcase
end
wire [15:0] addsub_q, and_out, and_q, xor_q, sh_q, ash_q, mul_q, div_q, mod_q;
wire [31:0] sh_out;
wire [15:0] addsub_EX, sh_EX, ash_EX, mul_EX, div_EX;
add_sub_X addsub(b, a, EXin, add_sub, add_EX, addsub_q, addsub_EX, eq, lt, un);
mul_div_mod mdm(b, a, mul_div_sgn, mul_q, mul_EX, div_q, div_EX, mod_q);
assign and_out = (b^{16{and_or}}) & (a^{16{and_or}});
assign and_q = and_out ^ {16{and_or}};
assign cl = ~|and_q;
assign xor_q = b ^ a;
wire [31:0] sh_b;
assign sh_b[31:16] = shift_dir ? b : 16'd0;
assign sh_b[15:0] = shift_dir ? 15'd0 : b;
shift16 shifter(sh_b, shift_dir, a[3:0], sh_out);
assign sh_q = shift_dir ? sh_out[31:16] : sh_out[15:0];
assign sh_EX = shift_dir ? sh_out[15:0] : sh_out[31:16];
ashift16 ashifter({b, 16'd0}, a[3:0], {ash_q, ash_EX});
always_comb
begin
q <= 16'h0000;
case(out_mux)
3'b000: q <= addsub_q;
3'b001: q <= mul_q;
3'b010: q <= div_q;
3'b011: q <= mod_q;
3'b100: q <= and_q;
3'b101: q <= xor_q;
3'b110: q <= sh_q;
3'b111: q <= ash_q;
endcase
end
always_comb
begin
EXout <= 16'h0000;
case(out_mux)
3'b000: EXout <= addsub_EX;
3'b001: EXout <= mul_EX;
3'b010: EXout <= div_EX;
3'b110: EXout <= sh_EX;
3'b111: EXout <= ash_EX;
default: EXout <= 16'h0000;
endcase
end
endmodule | 1 |
141,518 | data/full_repos/permissive/9579723/ALU/ALUtester.sv | 9,579,723 | ALUtester.sv | sv | 64 | 99 | [] | [] | [] | null | line:23: before: "[" | null | 1: b'%Error: data/full_repos/permissive/9579723/ALU/ALUtester.sv:40: Cannot find file containing module: \'SEG_HEX\'\n SEG_HEX h7(r, HEX7);\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/SEG_HEX\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/SEG_HEX.v\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/SEG_HEX.sv\n SEG_HEX\n SEG_HEX.v\n SEG_HEX.sv\n obj_dir/SEG_HEX\n obj_dir/SEG_HEX.v\n obj_dir/SEG_HEX.sv\n%Error: data/full_repos/permissive/9579723/ALU/ALUtester.sv:46: Cannot find file containing module: \'SEG_HEX\'\n SEG_HEX h3(out1[15:12], HEX3),\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9579723/ALU/ALUtester.sv:58: Bit extraction of array[3:0] requires 2 bit index, not 4 bits.\n : ... In instance ALUtester\n regs[r] <= SW;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/9579723/ALU/ALUtester.sv:61: Cannot find file containing module: \'ALU\'\n ALU alu(regs[0][4:0], regs[1], regs[2], regs[3], out1, out2, LEDG[0], LEDG[1], LEDG[2], LEDG[3]);\n ^~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 312,093 | module | module ALUtester(
input KEY[2:1],
input [15:0] SW,
output [3:0] LEDG,
output [15:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX7
);
reg [15:0] regs [3:0];
reg [3:0] r = 0;
SEG_HEX h7(r, HEX7);
wire [15:0] out2;
assign LEDR[15:0] = out2[15:0];
wire [15:0] out1;
SEG_HEX h3(out1[15:12], HEX3),
h2(out1[11:8], HEX2),
h1(out1[7:4], HEX1),
h0(out1[3:0], HEX0);
always_ff @(negedge KEY[1])
begin
r[1:0] <= r[1:0] + 2'h1;
end
always_ff @(negedge KEY[2])
begin
regs[r] <= SW;
end
ALU alu(regs[0][4:0], regs[1], regs[2], regs[3], out1, out2, LEDG[0], LEDG[1], LEDG[2], LEDG[3]);
endmodule | module ALUtester(
input KEY[2:1],
input [15:0] SW,
output [3:0] LEDG,
output [15:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX7
); |
reg [15:0] regs [3:0];
reg [3:0] r = 0;
SEG_HEX h7(r, HEX7);
wire [15:0] out2;
assign LEDR[15:0] = out2[15:0];
wire [15:0] out1;
SEG_HEX h3(out1[15:12], HEX3),
h2(out1[11:8], HEX2),
h1(out1[7:4], HEX1),
h0(out1[3:0], HEX0);
always_ff @(negedge KEY[1])
begin
r[1:0] <= r[1:0] + 2'h1;
end
always_ff @(negedge KEY[2])
begin
regs[r] <= SW;
end
ALU alu(regs[0][4:0], regs[1], regs[2], regs[3], out1, out2, LEDG[0], LEDG[1], LEDG[2], LEDG[3]);
endmodule | 1 |
141,521 | data/full_repos/permissive/9579723/ALU/mul_div_mod.sv | 9,579,723 | mul_div_mod.sv | sv | 52 | 104 | [] | [] | [] | [(21, 51)] | null | null | 1: b"%Error: data/full_repos/permissive/9579723/ALU/mul_div_mod.sv:41: Cannot find file containing module: 'mult16'\n mult16 mul(unsigned_b, unsigned_a, mul_out);\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/mult16\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/mult16.v\n data/full_repos/permissive/9579723/ALU,data/full_repos/permissive/9579723/mult16.sv\n mult16\n mult16.v\n mult16.sv\n obj_dir/mult16\n obj_dir/mult16.v\n obj_dir/mult16.sv\n%Error: data/full_repos/permissive/9579723/ALU/mul_div_mod.sv:45: Cannot find file containing module: 'div16'\n div16 div(b, a, div_out, mod_out, div_out_ex, divz);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n" | 312,098 | module | module mul_div_mod (
input [15:0] b,
input [15:0] a,
input sgn,
output [15:0] mul_q,
output [15:0] mul_EX,
output [15:0] div_q,
output [15:0] div_EX,
output [15:0] mod_q
);
wire sgn_b = b[15] && sgn;
wire sgn_a = a[15] && sgn;
wire [15:0] unsigned_b = sgn_b ? -b : b;
wire [15:0] unsigned_a = sgn_a ? -a : a;
wire [31:0] mul_out;
wire [15:0] div_out, div_out_ex, mod_out;
wire divz;
mult16 mul(unsigned_b, unsigned_a, mul_out);
assign {mul_EX,mul_q} = sgn_b ^ sgn_a ? -mul_out : mul_out;
div16 div(b, a, div_out, mod_out, div_out_ex, divz);
assign {div_q,div_EX} = divz ? 32'd0 : (sgn_b ^ sgn_a ? -{div_out,div_out_ex} : {div_out,div_out_ex});
assign mod_q = divz ? 16'd0 : (sgn_b ? -mod_out : mod_out);
endmodule | module mul_div_mod (
input [15:0] b,
input [15:0] a,
input sgn,
output [15:0] mul_q,
output [15:0] mul_EX,
output [15:0] div_q,
output [15:0] div_EX,
output [15:0] mod_q
); |
wire sgn_b = b[15] && sgn;
wire sgn_a = a[15] && sgn;
wire [15:0] unsigned_b = sgn_b ? -b : b;
wire [15:0] unsigned_a = sgn_a ? -a : a;
wire [31:0] mul_out;
wire [15:0] div_out, div_out_ex, mod_out;
wire divz;
mult16 mul(unsigned_b, unsigned_a, mul_out);
assign {mul_EX,mul_q} = sgn_b ^ sgn_a ? -mul_out : mul_out;
div16 div(b, a, div_out, mod_out, div_out_ex, divz);
assign {div_q,div_EX} = divz ? 32'd0 : (sgn_b ^ sgn_a ? -{div_out,div_out_ex} : {div_out,div_out_ex});
assign mod_q = divz ? 16'd0 : (sgn_b ? -mod_out : mod_out);
endmodule | 1 |
141,522 | data/full_repos/permissive/9579723/ALU/SEG_HEX.sv | 9,579,723 | SEG_HEX.sv | sv | 45 | 76 | [] | [] | [] | [(21, 44)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h0: HEX <= 7'b1000000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h1: HEX <= 7'b1111001;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h2: HEX <= 7'b0100100;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h3: HEX <= 7'b0110000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:29: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h4: HEX <= 7'b0011001;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:30: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h5: HEX <= 7'b0010010;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:31: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h6: HEX <= 7'b0000010;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:32: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h7: HEX <= 7'b1111000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:33: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h8: HEX <= 7'b0000000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'h9: HEX <= 7'b0010000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:35: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'hA: HEX <= 7'b0001000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:36: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'hB: HEX <= 7'b0000011;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:37: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'hC: HEX <= 7'b1000110;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'hD: HEX <= 7'b0100001;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:39: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'hE: HEX <= 7'b0000110;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:40: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n 4'hF: HEX <= 7'b0001110;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/9579723/ALU/SEG_HEX.sv:41: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'HEX'\n : ... In instance SEG_HEX\n default: HEX <= 7'b1111111;\n ^~~\n%Error: Exiting due to 17 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 312,099 | module | module SEG_HEX(input [3:0] num, output [6:0] HEX);
always_comb
case(num)
4'h0: HEX <= 7'b1000000;
4'h1: HEX <= 7'b1111001;
4'h2: HEX <= 7'b0100100;
4'h3: HEX <= 7'b0110000;
4'h4: HEX <= 7'b0011001;
4'h5: HEX <= 7'b0010010;
4'h6: HEX <= 7'b0000010;
4'h7: HEX <= 7'b1111000;
4'h8: HEX <= 7'b0000000;
4'h9: HEX <= 7'b0010000;
4'hA: HEX <= 7'b0001000;
4'hB: HEX <= 7'b0000011;
4'hC: HEX <= 7'b1000110;
4'hD: HEX <= 7'b0100001;
4'hE: HEX <= 7'b0000110;
4'hF: HEX <= 7'b0001110;
default: HEX <= 7'b1111111;
endcase
endmodule | module SEG_HEX(input [3:0] num, output [6:0] HEX); |
always_comb
case(num)
4'h0: HEX <= 7'b1000000;
4'h1: HEX <= 7'b1111001;
4'h2: HEX <= 7'b0100100;
4'h3: HEX <= 7'b0110000;
4'h4: HEX <= 7'b0011001;
4'h5: HEX <= 7'b0010010;
4'h6: HEX <= 7'b0000010;
4'h7: HEX <= 7'b1111000;
4'h8: HEX <= 7'b0000000;
4'h9: HEX <= 7'b0010000;
4'hA: HEX <= 7'b0001000;
4'hB: HEX <= 7'b0000011;
4'hC: HEX <= 7'b1000110;
4'hD: HEX <= 7'b0100001;
4'hE: HEX <= 7'b0000110;
4'hF: HEX <= 7'b0001110;
default: HEX <= 7'b1111111;
endcase
endmodule | 1 |
141,523 | data/full_repos/permissive/9579723/Devices/DEV_TEMPLATE.sv | 9,579,723 | DEV_TEMPLATE.sv | sv | 43 | 76 | [] | [] | [] | [(21, 42)] | null | data/verilator_xmls/7d3a3c22-e899-4dc7-97e9-48da091d3d1d.xml | null | 312,101 | module | module DEV_TEMPLATE (
input DMA_CLOCK,
input DMA_access,
output DMA_want,
output [15:0] DMA_addr,
output [15:0] DMA_out,
output DMA_wren,
input DMA_data
);
endmodule | module DEV_TEMPLATE (
input DMA_CLOCK,
input DMA_access,
output DMA_want,
output [15:0] DMA_addr,
output [15:0] DMA_out,
output DMA_wren,
input DMA_data
); |
endmodule | 1 |
141,524 | data/full_repos/permissive/9579723/Devices/Test_Monitor/blink_timer.sv | 9,579,723 | blink_timer.sv | sv | 44 | 76 | [] | [] | [] | [(21, 43)] | null | data/verilator_xmls/f7d0d5fe-a0ad-4a18-89ca-070559bfdc5f.xml | null | 312,105 | module | module blink_timer (
input CLOCK_25M,
input RST,
output reg blinker
);
reg [23:0] C;
always_ff @(posedge CLOCK_25M or posedge RST)
begin
if (RST) begin
C <= 0;
blinker <= 1'b0;
end
else begin
C <= C + 24'd1;
if (C == 24'd1)
blinker <= ~blinker;
end
end
endmodule | module blink_timer (
input CLOCK_25M,
input RST,
output reg blinker
); |
reg [23:0] C;
always_ff @(posedge CLOCK_25M or posedge RST)
begin
if (RST) begin
C <= 0;
blinker <= 1'b0;
end
else begin
C <= C + 24'd1;
if (C == 24'd1)
blinker <= ~blinker;
end
end
endmodule | 1 |
141,528 | data/full_repos/permissive/9579723/Devices/Test_Monitor/resetDelay.sv | 9,579,723 | resetDelay.sv | sv | 39 | 76 | [] | [] | [] | [(21, 38)] | null | data/verilator_xmls/4878d2b2-c252-46c1-88af-f1ba0a4cd41c.xml | null | 312,111 | module | module resetDelay(
input CLK,
output reg RST
);
reg [15:0] C = 0;
always_ff @(posedge CLK)
begin
if (C == 16'hFFFF)
RST <= 1'b0;
else begin
C <= C + 16'h0001;
RST <= 1'b1;
end
end
endmodule | module resetDelay(
input CLK,
output reg RST
); |
reg [15:0] C = 0;
always_ff @(posedge CLK)
begin
if (C == 16'hFFFF)
RST <= 1'b0;
else begin
C <= C + 16'h0001;
RST <= 1'b1;
end
end
endmodule | 1 |
141,538 | data/full_repos/permissive/95831745/components/draw.v | 95,831,745 | draw.v | v | 224 | 77 | [] | [] | [] | [(6, 38), (43, 67), (80, 223)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/95831745/components/draw.v:20: Cell has missing pin: \'draw\'\n datapath draw_square(.input_colour(input_colour),\n ^~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/95831745/components/draw.v:31: Cell has missing pin: \'plot\'\n control offset_calc(.clk(clk),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:117: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P1: next_state = P2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:118: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P2: next_state = P3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:119: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P3: next_state = P4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:120: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P4: next_state = P5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:121: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P5: next_state = P6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:122: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P6: next_state = P7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:123: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P7: next_state = P8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:124: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P8: next_state = P9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:125: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P9: next_state = P10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:126: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P10: next_state = P11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:127: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P11: next_state = P12;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:128: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P12: next_state = P13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:129: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P13: next_state = P14;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:130: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P14: next_state = P15;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:131: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P15: next_state = P16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:132: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P16: next_state = RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:133: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n RESTING: next_state = go ? P1 : RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:133: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n RESTING: next_state = go ? P1 : RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:134: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n default: next_state = RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:139: Operator NEQ expects 6 bits on the RHS, but RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n assign plot = (current_state != RESTING);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:219: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n current_state <= RESTING;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:59: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'xOffset\' generates 2 bits.\n : ... In instance square4x4.draw_square\n x <= {x_coords + xOffset};\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:60: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'yOffset\' generates 2 bits.\n : ... In instance square4x4.draw_square\n y <= {y_coords + yOffset};\n ^\n%Error: Exiting due to 58 warning(s)\n' | 312,118 | module | module square4x4(
input clk,
input [7:0] x_coords,
input [6:0] y_coords,
input [2:0] input_colour,
output [7:0] finalX,
output [6:0] finalY,
output [2:0] output_colour
);
wire [1:0] xoff;
wire [1:0] yoff;
datapath draw_square(.input_colour(input_colour),
.x_coords(x_coords),
.y_coords(y_coords),
.xOffset(xoff),
.yOffset(yoff),
.finalX(finalX),
.finalY(finalY),
.output_colour(output_colour)
);
control offset_calc(.clk(clk),
.resetn(1'b1),
.go(1'b1),
.xOffset(xoff),
.yOffset(yoff)
);
endmodule | module square4x4(
input clk,
input [7:0] x_coords,
input [6:0] y_coords,
input [2:0] input_colour,
output [7:0] finalX,
output [6:0] finalY,
output [2:0] output_colour
); |
wire [1:0] xoff;
wire [1:0] yoff;
datapath draw_square(.input_colour(input_colour),
.x_coords(x_coords),
.y_coords(y_coords),
.xOffset(xoff),
.yOffset(yoff),
.finalX(finalX),
.finalY(finalY),
.output_colour(output_colour)
);
control offset_calc(.clk(clk),
.resetn(1'b1),
.go(1'b1),
.xOffset(xoff),
.yOffset(yoff)
);
endmodule | 5 |
141,539 | data/full_repos/permissive/95831745/components/draw.v | 95,831,745 | draw.v | v | 224 | 77 | [] | [] | [] | [(6, 38), (43, 67), (80, 223)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/95831745/components/draw.v:20: Cell has missing pin: \'draw\'\n datapath draw_square(.input_colour(input_colour),\n ^~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/95831745/components/draw.v:31: Cell has missing pin: \'plot\'\n control offset_calc(.clk(clk),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:117: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P1: next_state = P2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:118: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P2: next_state = P3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:119: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P3: next_state = P4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:120: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P4: next_state = P5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:121: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P5: next_state = P6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:122: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P6: next_state = P7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:123: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P7: next_state = P8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:124: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P8: next_state = P9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:125: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P9: next_state = P10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:126: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P10: next_state = P11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:127: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P11: next_state = P12;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:128: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P12: next_state = P13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:129: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P13: next_state = P14;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:130: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P14: next_state = P15;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:131: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P15: next_state = P16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:132: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P16: next_state = RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:133: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n RESTING: next_state = go ? P1 : RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:133: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n RESTING: next_state = go ? P1 : RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:134: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n default: next_state = RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:139: Operator NEQ expects 6 bits on the RHS, but RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n assign plot = (current_state != RESTING);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:219: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n current_state <= RESTING;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:59: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'xOffset\' generates 2 bits.\n : ... In instance square4x4.draw_square\n x <= {x_coords + xOffset};\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:60: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'yOffset\' generates 2 bits.\n : ... In instance square4x4.draw_square\n y <= {y_coords + yOffset};\n ^\n%Error: Exiting due to 58 warning(s)\n' | 312,118 | module | module datapath(
input [2:0] input_colour,
input [7:0] x_coords,
input [6:0] y_coords,
input [1:0] xOffset,
input [1:0] yOffset,
input draw,
output [7:0] finalX,
output [6:0] finalY,
output[2:0] output_colour
);
reg [6:0] y;
reg [7:0] x;
always @(*) begin
x <= {x_coords + xOffset};
y <= {y_coords + yOffset};
end
assign finalY = y;
assign finalX = x;
assign output_colour = input_colour[2:0];
endmodule | module datapath(
input [2:0] input_colour,
input [7:0] x_coords,
input [6:0] y_coords,
input [1:0] xOffset,
input [1:0] yOffset,
input draw,
output [7:0] finalX,
output [6:0] finalY,
output[2:0] output_colour
); |
reg [6:0] y;
reg [7:0] x;
always @(*) begin
x <= {x_coords + xOffset};
y <= {y_coords + yOffset};
end
assign finalY = y;
assign finalX = x;
assign output_colour = input_colour[2:0];
endmodule | 5 |
141,540 | data/full_repos/permissive/95831745/components/draw.v | 95,831,745 | draw.v | v | 224 | 77 | [] | [] | [] | [(6, 38), (43, 67), (80, 223)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/95831745/components/draw.v:20: Cell has missing pin: \'draw\'\n datapath draw_square(.input_colour(input_colour),\n ^~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/95831745/components/draw.v:31: Cell has missing pin: \'plot\'\n control offset_calc(.clk(clk),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:117: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P1: next_state = P2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:118: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P2: next_state = P3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:119: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P3: next_state = P4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:120: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P4: next_state = P5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:121: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P5: next_state = P6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:122: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P6: next_state = P7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:123: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P7: next_state = P8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:124: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P8: next_state = P9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:125: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P9: next_state = P10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:126: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P10: next_state = P11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:127: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P11: next_state = P12;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:128: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P12: next_state = P13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:129: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P13: next_state = P14;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:130: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P14: next_state = P15;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:131: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P15: next_state = P16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:132: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n P16: next_state = RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:133: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n RESTING: next_state = go ? P1 : RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:133: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n RESTING: next_state = go ? P1 : RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:134: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n default: next_state = RESTING;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:116: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:139: Operator NEQ expects 6 bits on the RHS, but RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n assign plot = (current_state != RESTING);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P1\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P2\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P3\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P4\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P5\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P6\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P7\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P8\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P9\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P10\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P11\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P12\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P13\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P14\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P15\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:144: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'P16\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:219: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESTING\' generates 5 bits.\n : ... In instance square4x4.offset_calc\n current_state <= RESTING;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:59: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'xOffset\' generates 2 bits.\n : ... In instance square4x4.draw_square\n x <= {x_coords + xOffset};\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/draw.v:60: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'yOffset\' generates 2 bits.\n : ... In instance square4x4.draw_square\n y <= {y_coords + yOffset};\n ^\n%Error: Exiting due to 58 warning(s)\n' | 312,118 | module | module control(
input clk,
input resetn,
input go,
output [1:0] xOffset,
output [1:0] yOffset,
output plot);
reg [5:0] current_state, next_state;
reg [1:0] xoff;
reg [1:0] yoff;
assign xOffset = xoff;
assign yOffset = yoff;
localparam P1 = 5'd0,
P2 = 5'd1,
P3 = 5'd2,
P4 = 5'd3,
P5 = 5'd4,
P6 = 5'd5,
P7 = 5'd6,
P8 = 5'd7,
P9 = 5'd8,
P10 = 5'd9,
P11 = 5'd10,
P12 = 5'd11,
P13 = 5'd12,
P14 = 5'd13,
P15 = 5'd14,
P16 = 5'd15,
RESTING = 5'd16;
always@(posedge clk)
begin: state_table
case (current_state)
P1: next_state = P2;
P2: next_state = P3;
P3: next_state = P4;
P4: next_state = P5;
P5: next_state = P6;
P6: next_state = P7;
P7: next_state = P8;
P8: next_state = P9;
P9: next_state = P10;
P10: next_state = P11;
P11: next_state = P12;
P12: next_state = P13;
P13: next_state = P14;
P14: next_state = P15;
P15: next_state = P16;
P16: next_state = RESTING;
RESTING: next_state = go ? P1 : RESTING;
default: next_state = RESTING;
endcase
end
assign plot = (current_state != RESTING);
always@(*)
begin: make_output
case(current_state)
P1: begin
xoff <= 2'b00;
yoff <= 2'b00;
end
P2: begin
xoff <= 2'b01;
yoff <= 2'b00;
end
P3: begin
xoff <= 2'b10;
yoff <= 2'b00;
end
P4: begin
xoff <= 2'b11;
yoff <= 2'b00;
end
P5: begin
xoff <= 2'b00;
yoff <= 2'b01;
end
P6: begin
xoff <= 2'b01;
yoff <= 2'b01;
end
P7: begin
xoff <= 2'b10;
yoff <= 2'b01;
end
P8: begin
xoff <= 2'b11;
yoff <= 2'b01;
end
P9: begin
xoff <= 2'b00;
yoff <= 2'b10;
end
P10: begin
xoff <= 2'b01;
yoff <= 2'b10;
end
P11: begin
xoff <= 2'b10;
yoff <= 2'b10;
end
P12: begin
xoff <= 2'b11;
yoff <= 2'b10;
end
P13: begin
xoff <= 2'b00;
yoff <= 2'b11;
end
P14: begin
xoff <= 2'b01;
yoff <= 2'b11;
end
P15: begin
xoff <= 2'b10;
yoff <= 2'b11;
end
P16: begin
xoff <= 2'b11;
yoff <= 2'b11;
end
default: begin
xoff <= 2'b00;
yoff <= 2'b00;
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!resetn)
current_state <= RESTING;
else
current_state <= next_state;
end
endmodule | module control(
input clk,
input resetn,
input go,
output [1:0] xOffset,
output [1:0] yOffset,
output plot); |
reg [5:0] current_state, next_state;
reg [1:0] xoff;
reg [1:0] yoff;
assign xOffset = xoff;
assign yOffset = yoff;
localparam P1 = 5'd0,
P2 = 5'd1,
P3 = 5'd2,
P4 = 5'd3,
P5 = 5'd4,
P6 = 5'd5,
P7 = 5'd6,
P8 = 5'd7,
P9 = 5'd8,
P10 = 5'd9,
P11 = 5'd10,
P12 = 5'd11,
P13 = 5'd12,
P14 = 5'd13,
P15 = 5'd14,
P16 = 5'd15,
RESTING = 5'd16;
always@(posedge clk)
begin: state_table
case (current_state)
P1: next_state = P2;
P2: next_state = P3;
P3: next_state = P4;
P4: next_state = P5;
P5: next_state = P6;
P6: next_state = P7;
P7: next_state = P8;
P8: next_state = P9;
P9: next_state = P10;
P10: next_state = P11;
P11: next_state = P12;
P12: next_state = P13;
P13: next_state = P14;
P14: next_state = P15;
P15: next_state = P16;
P16: next_state = RESTING;
RESTING: next_state = go ? P1 : RESTING;
default: next_state = RESTING;
endcase
end
assign plot = (current_state != RESTING);
always@(*)
begin: make_output
case(current_state)
P1: begin
xoff <= 2'b00;
yoff <= 2'b00;
end
P2: begin
xoff <= 2'b01;
yoff <= 2'b00;
end
P3: begin
xoff <= 2'b10;
yoff <= 2'b00;
end
P4: begin
xoff <= 2'b11;
yoff <= 2'b00;
end
P5: begin
xoff <= 2'b00;
yoff <= 2'b01;
end
P6: begin
xoff <= 2'b01;
yoff <= 2'b01;
end
P7: begin
xoff <= 2'b10;
yoff <= 2'b01;
end
P8: begin
xoff <= 2'b11;
yoff <= 2'b01;
end
P9: begin
xoff <= 2'b00;
yoff <= 2'b10;
end
P10: begin
xoff <= 2'b01;
yoff <= 2'b10;
end
P11: begin
xoff <= 2'b10;
yoff <= 2'b10;
end
P12: begin
xoff <= 2'b11;
yoff <= 2'b10;
end
P13: begin
xoff <= 2'b00;
yoff <= 2'b11;
end
P14: begin
xoff <= 2'b01;
yoff <= 2'b11;
end
P15: begin
xoff <= 2'b10;
yoff <= 2'b11;
end
P16: begin
xoff <= 2'b11;
yoff <= 2'b11;
end
default: begin
xoff <= 2'b00;
yoff <= 2'b00;
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!resetn)
current_state <= RESTING;
else
current_state <= next_state;
end
endmodule | 5 |
141,542 | data/full_repos/permissive/95831745/components/player_control.v | 95,831,745 | player_control.v | v | 15 | 113 | [] | [] | [] | [(7, 14)] | null | data/verilator_xmls/7c972815-2a92-41eb-b37f-a144ab7d3532.xml | null | 312,120 | module | module player_control(
input [2:0] notes,
input [2:0] player_input,
output increase_score,
output decrease_score);
assign increase_score = (notes == player_input) && (notes != 3'b000);
assign decrease_score = (notes != player_input);
endmodule | module player_control(
input [2:0] notes,
input [2:0] player_input,
output increase_score,
output decrease_score); |
assign increase_score = (notes == player_input) && (notes != 3'b000);
assign decrease_score = (notes != player_input);
endmodule | 5 |
141,545 | data/full_repos/permissive/95831745/components/score_counter.v | 95,831,745 | score_counter.v | v | 45 | 53 | [] | [] | [] | [(9, 25), (30, 44)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95831745/components/score_counter.v:30: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'score_counter\'\nmodule score_counter(\n ^~~~~~~~~~~~~\n : ... Top module \'combo_counter\'\nmodule combo_counter(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,122 | module | module score_counter(
input increase_score,
input decrease_score,
input reset,
input clk,
output [7:0] score);
reg [7:0] storage;
assign score = storage;
always @(posedge clk) begin
if (reset)
storage <= 0;
else if (increase_score)
storage <= storage + 1;
else if (decrease_score && storage != 8'b0)
storage <= storage - 1;
end
endmodule | module score_counter(
input increase_score,
input decrease_score,
input reset,
input clk,
output [7:0] score); |
reg [7:0] storage;
assign score = storage;
always @(posedge clk) begin
if (reset)
storage <= 0;
else if (increase_score)
storage <= storage + 1;
else if (decrease_score && storage != 8'b0)
storage <= storage - 1;
end
endmodule | 5 |
141,546 | data/full_repos/permissive/95831745/components/score_counter.v | 95,831,745 | score_counter.v | v | 45 | 53 | [] | [] | [] | [(9, 25), (30, 44)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95831745/components/score_counter.v:30: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'score_counter\'\nmodule score_counter(\n ^~~~~~~~~~~~~\n : ... Top module \'combo_counter\'\nmodule combo_counter(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,122 | module | module combo_counter(
input increase_score,
input decrease_score,
input clk,
output [7:0] combo
);
reg [7:0] storage;
assign combo = storage;
always @(posedge clk) begin
if (increase_score)
storage <= storage + 1;
else if (decrease_score)
storage <= 0;
end
endmodule | module combo_counter(
input increase_score,
input decrease_score,
input clk,
output [7:0] combo
); |
reg [7:0] storage;
assign combo = storage;
always @(posedge clk) begin
if (increase_score)
storage <= storage + 1;
else if (decrease_score)
storage <= 0;
end
endmodule | 5 |
141,547 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module seven_segment_display(c, hex);
input [3:0] c;
output [6:0] hex;
hex_0_control zero(c[0], c[1], c[2], c[3], hex[0]);
hex_1_control one(c[0], c[1], c[2], c[3], hex[1]);
hex_2_control two(c[0], c[1], c[2], c[3], hex[2]);
hex_3_control three(c[0], c[1], c[2], c[3], hex[3]);
hex_4_control four(c[0], c[1], c[2], c[3], hex[4]);
hex_5_control five(c[0], c[1], c[2], c[3], hex[5]);
hex_6_control six(c[0], c[1], c[2], c[3], hex[6]);
endmodule | module seven_segment_display(c, hex); |
input [3:0] c;
output [6:0] hex;
hex_0_control zero(c[0], c[1], c[2], c[3], hex[0]);
hex_1_control one(c[0], c[1], c[2], c[3], hex[1]);
hex_2_control two(c[0], c[1], c[2], c[3], hex[2]);
hex_3_control three(c[0], c[1], c[2], c[3], hex[3]);
hex_4_control four(c[0], c[1], c[2], c[3], hex[4]);
hex_5_control five(c[0], c[1], c[2], c[3], hex[5]);
hex_6_control six(c[0], c[1], c[2], c[3], hex[6]);
endmodule | 5 |
141,548 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module hex_0_control(c0, c1, c2, c3, hex0);
input c0, c1, c2, c3;
output hex0;
assign hex0 = (c3 & ~c2 & c1 & c0) | (c3 & c2 & ~c1 & c0) | (~c3 & ~c2 & ~c1 & c0) | (~c3 & c2 & ~c1 & ~c0);
endmodule | module hex_0_control(c0, c1, c2, c3, hex0); |
input c0, c1, c2, c3;
output hex0;
assign hex0 = (c3 & ~c2 & c1 & c0) | (c3 & c2 & ~c1 & c0) | (~c3 & ~c2 & ~c1 & c0) | (~c3 & c2 & ~c1 & ~c0);
endmodule | 5 |
141,549 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module hex_1_control(c0, c1, c2, c3, hex1);
input c0, c1, c2, c3;
output hex1;
assign hex1 = (c3 & c1 & c0) | (c2 & c1 & ~c0) | (c3 & c2 & ~c0) | (~c3 & c2 & ~c1 & c0);
endmodule | module hex_1_control(c0, c1, c2, c3, hex1); |
input c0, c1, c2, c3;
output hex1;
assign hex1 = (c3 & c1 & c0) | (c2 & c1 & ~c0) | (c3 & c2 & ~c0) | (~c3 & c2 & ~c1 & c0);
endmodule | 5 |
141,550 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module hex_2_control(c0, c1, c2, c3, hex2);
input c0, c1, c2, c3;
output hex2;
assign hex2 = (c3 & c2 & c1) | (c3 & c2 & ~c0) | (~c3 & ~c2 & c1 & ~c0);
endmodule | module hex_2_control(c0, c1, c2, c3, hex2); |
input c0, c1, c2, c3;
output hex2;
assign hex2 = (c3 & c2 & c1) | (c3 & c2 & ~c0) | (~c3 & ~c2 & c1 & ~c0);
endmodule | 5 |
141,551 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module hex_3_control(c0, c1, c2, c3, hex3);
input c0, c1, c2, c3;
output hex3;
assign hex3 = (c2 & c1 & c0) | (c3 & ~c2 & c1 & ~c0) | (c0 ^ c2) & (~c3 & ~c1);
endmodule | module hex_3_control(c0, c1, c2, c3, hex3); |
input c0, c1, c2, c3;
output hex3;
assign hex3 = (c2 & c1 & c0) | (c3 & ~c2 & c1 & ~c0) | (c0 ^ c2) & (~c3 & ~c1);
endmodule | 5 |
141,552 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module hex_4_control(c0, c1, c2, c3, hex4);
input c0, c1, c2, c3;
output hex4;
assign hex4 = (~c3 & c0) | (~c3 & c2 & ~c1) | (~c2 & ~c1 & c0);
endmodule | module hex_4_control(c0, c1, c2, c3, hex4); |
input c0, c1, c2, c3;
output hex4;
assign hex4 = (~c3 & c0) | (~c3 & c2 & ~c1) | (~c2 & ~c1 & c0);
endmodule | 5 |
141,553 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module hex_5_control(c0, c1, c2, c3, hex5);
input c0, c1, c2, c3;
output hex5;
assign hex5 = (c0 & ~c1 & c2 & c3) | (c0 & ~c2 & ~c3) | (c1 & ~c2 & ~c3) | (~c3 & c0 & c1);
endmodule | module hex_5_control(c0, c1, c2, c3, hex5); |
input c0, c1, c2, c3;
output hex5;
assign hex5 = (c0 & ~c1 & c2 & c3) | (c0 & ~c2 & ~c3) | (c1 & ~c2 & ~c3) | (~c3 & c0 & c1);
endmodule | 5 |
141,554 | data/full_repos/permissive/95831745/components/seven_segment_display.v | 95,831,745 | seven_segment_display.v | v | 58 | 113 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f0d82c95-66ec-423a-a33a-fa1d7f5b5983.xml | null | 312,123 | module | module hex_6_control(c0, c1, c2, c3, hex6);
input c0, c1, c2, c3;
output hex6;
assign hex6 = (~c3 & ~c2 & ~c1) | (~c3 & c2 & c1 & c0) | (c3 & c2 & ~c1 & ~c0);
endmodule | module hex_6_control(c0, c1, c2, c3, hex6); |
input c0, c1, c2, c3;
output hex6;
assign hex6 = (~c3 & ~c2 & ~c1) | (~c3 & c2 & c1 & c0) | (c3 & c2 & ~c1 & ~c0);
endmodule | 5 |
141,555 | data/full_repos/permissive/95831745/components/song_loader.v | 95,831,745 | song_loader.v | v | 66 | 127 | [] | [] | [] | null | line:56: before: "default" | null | 1: b'%Error: data/full_repos/permissive/95831745/components/song_loader.v:56: syntax error, unexpected default\n default:\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n' | 312,124 | module | module song_loader(song_select, output_red, output_blue, output_yellow, output_total_notes);
input [4:0] song_select;
output [99:0] output_red, output_blue, output_yellow;
output [7:0] output_total_notes;
reg [7:0] total_notes;
assign output_total_notes = total_notes;
localparam Take_on_Me = 5'b00011,
Through_The_Fire_and_Flames = 5'b11111,
Vlad_Bit = 5'b01010,
Brian_This_Project_Is_Worth_Full_Marks = 5'b10111;
reg [99:0] red, blue, yellow;
assign output_red = red;
assign output_blue = blue;
assign output_yellow = yellow;
always @(*)
begin
case (song_select[4:0])
Through_The_Fire_and_Flames:
begin
red <= 100'b0000000000101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010;
yellow <= 100'b0000000000010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001;
blue <= 100'b0000000000000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100;
total_notes <= 8'd90;
end
Take_on_Me:
begin
red <= 100'b0000000000000000000001010101010101010000000000000000010101010000000000000000010101010000000000000000;
yellow <= 100'b0000000000111111111100000000000000000101010001010101000000000101000001010101000000000000000000000000;
blue <= 100'b0000000000011111111100000000000000000000000100000000000000000000010100000000000000000000000000000000;
total_notes <= 8'd42;
end
Vlad_Bit:
begin
red <= 100'b0010001001001101110101000101001000000001000001011011010100101000010010100101010010010001001000101111;
yellow <= 100'b0111000001000100101001101101101010100011001001001011101110100100000100011011011011010110110111010011;
blue <= 100'b1001001011110110111111111111111111111111111111111000001111111111111111101001001001110111100010101100;
total_notes <= 8'd94;
end
Brian_This_Project_Is_Worth_Full_Marks:
begin
red <= 100'b1010101010101010101010101110101010101000101010010101011000100101010101010100001101001011010011110001;
yellow <= 100'b0000101010101011111010101010101000010101010101111111000001111010001100100100101010100010100101010100;
blue <= 100'b0110101010110010001010101100001010010100001010101010111111010010010000101001101000100101010101010001;
total_notes <= 8'd82;
default:
begin
red <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
yellow <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
blue <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
total_notes <= 0;
end
endcase
end
endmodule | module song_loader(song_select, output_red, output_blue, output_yellow, output_total_notes); |
input [4:0] song_select;
output [99:0] output_red, output_blue, output_yellow;
output [7:0] output_total_notes;
reg [7:0] total_notes;
assign output_total_notes = total_notes;
localparam Take_on_Me = 5'b00011,
Through_The_Fire_and_Flames = 5'b11111,
Vlad_Bit = 5'b01010,
Brian_This_Project_Is_Worth_Full_Marks = 5'b10111;
reg [99:0] red, blue, yellow;
assign output_red = red;
assign output_blue = blue;
assign output_yellow = yellow;
always @(*)
begin
case (song_select[4:0])
Through_The_Fire_and_Flames:
begin
red <= 100'b0000000000101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010;
yellow <= 100'b0000000000010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001;
blue <= 100'b0000000000000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100;
total_notes <= 8'd90;
end
Take_on_Me:
begin
red <= 100'b0000000000000000000001010101010101010000000000000000010101010000000000000000010101010000000000000000;
yellow <= 100'b0000000000111111111100000000000000000101010001010101000000000101000001010101000000000000000000000000;
blue <= 100'b0000000000011111111100000000000000000000000100000000000000000000010100000000000000000000000000000000;
total_notes <= 8'd42;
end
Vlad_Bit:
begin
red <= 100'b0010001001001101110101000101001000000001000001011011010100101000010010100101010010010001001000101111;
yellow <= 100'b0111000001000100101001101101101010100011001001001011101110100100000100011011011011010110110111010011;
blue <= 100'b1001001011110110111111111111111111111111111111111000001111111111111111101001001001110111100010101100;
total_notes <= 8'd94;
end
Brian_This_Project_Is_Worth_Full_Marks:
begin
red <= 100'b1010101010101010101010101110101010101000101010010101011000100101010101010100001101001011010011110001;
yellow <= 100'b0000101010101011111010101010101000010101010101111111000001111010001100100100101010100010100101010100;
blue <= 100'b0110101010110010001010101100001010010100001010101010111111010010010000101001101000100101010101010001;
total_notes <= 8'd82;
default:
begin
red <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
yellow <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
blue <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
total_notes <= 0;
end
endcase
end
endmodule | 5 |
141,556 | data/full_repos/permissive/95831745/components/square_info.v | 95,831,745 | square_info.v | v | 131 | 111 | [] | [] | [] | [(4, 130)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/95831745/components/square_info.v:62: Signal definition not found, creating implicitly: \'swap_now\'\n assign swap_now = (curr_square_state == Row_Swap);\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:62: Operator EQ expects 7 bits on the RHS, but RHS\'s VARREF \'Row_Swap\' generates 6 bits.\n : ... In instance square_info\n assign swap_now = (curr_square_state == Row_Swap);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:70: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s VARREF \'row2\' generates 2 bits.\n : ... In instance square_info\n row1: curr_row_state = swap_now ? row2 : row1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:70: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s VARREF \'row1\' generates 2 bits.\n : ... In instance square_info\n row1: curr_row_state = swap_now ? row2 : row1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:71: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s VARREF \'row3\' generates 2 bits.\n : ... In instance square_info\n row2: curr_row_state = swap_now ? row3 : row2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:71: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s VARREF \'row2\' generates 2 bits.\n : ... In instance square_info\n row2: curr_row_state = swap_now ? row3 : row2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:72: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s VARREF \'row1\' generates 2 bits.\n : ... In instance square_info\n row3: curr_row_state = swap_now ? row1 : row3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:72: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s VARREF \'row3\' generates 2 bits.\n : ... In instance square_info\n row3: curr_row_state = swap_now ? row1 : row3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:73: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'row1\' generates 2 bits.\n : ... In instance square_info\n default: curr_row_state = row1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:69: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'row1\' generates 2 bits.\n : ... In instance square_info\n case(curr_row_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:69: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'row2\' generates 2 bits.\n : ... In instance square_info\n case(curr_row_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:69: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'row3\' generates 2 bits.\n : ... In instance square_info\n case(curr_row_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:77: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square2\' generates 6 bits.\n : ... In instance square_info\n Square1: curr_square_state = Square2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:78: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square3\' generates 6 bits.\n : ... In instance square_info\n Square2: curr_square_state = Square3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:79: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square4\' generates 6 bits.\n : ... In instance square_info\n Square3: curr_square_state = Square4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:80: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square5\' generates 6 bits.\n : ... In instance square_info\n Square4: curr_square_state = Square5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:81: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square6\' generates 6 bits.\n : ... In instance square_info\n Square5: curr_square_state = Square6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:82: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square7\' generates 6 bits.\n : ... In instance square_info\n Square6: curr_square_state = Square7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:83: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square8\' generates 6 bits.\n : ... In instance square_info\n Square7: curr_square_state = Square8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:84: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square9\' generates 6 bits.\n : ... In instance square_info\n Square8: curr_square_state = Square9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:85: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square10\' generates 6 bits.\n : ... In instance square_info\n Square9: curr_square_state = Square10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:86: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square11\' generates 6 bits.\n : ... In instance square_info\n Square10: curr_square_state = Square11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:87: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square12\' generates 6 bits.\n : ... In instance square_info\n Square11: curr_square_state = Square12;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:88: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square13\' generates 6 bits.\n : ... In instance square_info\n Square12: curr_square_state = Square13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:89: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square14\' generates 6 bits.\n : ... In instance square_info\n Square13: curr_square_state = Square14;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:90: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square15\' generates 6 bits.\n : ... In instance square_info\n Square14: curr_square_state = Square15;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:91: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square16\' generates 6 bits.\n : ... In instance square_info\n Square15: curr_square_state = Square16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:92: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square17\' generates 6 bits.\n : ... In instance square_info\n Square16: curr_square_state = Square17;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:93: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square18\' generates 6 bits.\n : ... In instance square_info\n Square17: curr_square_state = Square18;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:94: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square19\' generates 6 bits.\n : ... In instance square_info\n Square18: curr_square_state = Square19;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:95: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square20\' generates 6 bits.\n : ... In instance square_info\n Square19: curr_square_state = Square20;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:96: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square21\' generates 6 bits.\n : ... In instance square_info\n Square20: curr_square_state = Square21;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:97: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square22\' generates 6 bits.\n : ... In instance square_info\n Square21: curr_square_state = Square22;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:98: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square23\' generates 6 bits.\n : ... In instance square_info\n Square22: curr_square_state = Square23;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:99: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square24\' generates 6 bits.\n : ... In instance square_info\n Square23: curr_square_state = Square24;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:100: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square25\' generates 6 bits.\n : ... In instance square_info\n Square24: curr_square_state = Square25;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:101: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square26\' generates 6 bits.\n : ... In instance square_info\n Square25: curr_square_state = Square26;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:102: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Row_Swap\' generates 6 bits.\n : ... In instance square_info\n Square26: curr_square_state = Row_Swap;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:103: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square1\' generates 6 bits.\n : ... In instance square_info\n Row_Swap: curr_square_state = Square1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:104: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Square1\' generates 6 bits.\n : ... In instance square_info\n default: curr_square_state = Square1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square1\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square2\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square3\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square4\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square5\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square6\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square7\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square8\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square9\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square10\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square11\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square12\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square13\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square14\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square15\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square16\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square17\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square18\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square19\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square20\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square21\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square22\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square23\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square24\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square25\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Square26\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:76: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'Row_Swap\' generates 6 bits.\n : ... In instance square_info\n case(curr_square_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:114: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n : ... In instance square_info\n curr_x = {start_x + {x_offset * curr_square_state}};\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:117: Bit extraction of var[25:0] requires 5 bit index, not 7 bits.\n : ... In instance square_info\n row1: curr_colour = red_sequence[curr_square_state] ? RED : BLACK;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:118: Bit extraction of var[25:0] requires 5 bit index, not 7 bits.\n : ... In instance square_info\n row2: curr_colour = yellow_sequence[curr_square_state] ? YELLOW : BLACK;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:119: Bit extraction of var[25:0] requires 5 bit index, not 7 bits.\n : ... In instance square_info\n row3: curr_colour = blue_sequence[curr_square_state] ? BLUE : BLACK;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:116: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'row1\' generates 2 bits.\n : ... In instance square_info\n case(curr_row_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:116: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'row2\' generates 2 bits.\n : ... In instance square_info\n case(curr_row_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:116: Operator CASE expects 7 bits on the Case Item, but Case Item\'s VARREF \'row3\' generates 2 bits.\n : ... In instance square_info\n case(curr_row_state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/95831745/components/square_info.v:111: Operator NEQ expects 7 bits on the RHS, but RHS\'s VARREF \'Row_Swap\' generates 6 bits.\n : ... In instance square_info\n if (curr_square_state != Row_Swap)\n ^~\n%Error: Exiting due to 75 warning(s)\n' | 312,125 | module | module square_info(
input [25:0] red_sequence,
input [25:0] yellow_sequence,
input [25:0] blue_sequence,
input clk,
output [7:0] output_x,
output [6:0] output_y,
output [2:0] colour
);
reg [6:0] curr_square_state, next_square_state,
curr_row_state;
reg [2:0] curr_colour;
localparam BLACK = 3'b000,
WHITE = 3'b111,
RED = 3'b100,
YELLOW = 3'b110,
GREEN = 3'b010,
CYAN = 3'b011,
BLUE = 3'b001,
MAGENTA = 3'b101;
assign colour = curr_colour;
localparam start_x = 7'b0000001,
start_y = 7'b0110101;
localparam x_offset = 7'b0000101,
y_offset = 7'b0001011;
reg [7:0] curr_x;
reg [6:0] curr_y;
assign output_x = curr_x;
assign output_y = curr_y;
localparam Square1 = 6'd0, Square2 = 6'd1, Square3 = 6'd2,
Square4 = 6'd3, Square5 = 6'd4, Square6 = 6'd5,
Square7 = 6'd6, Square8 = 6'd7, Square9 = 6'd8,
Square10 = 6'd9, Square11 = 6'd10, Square12 = 6'd11,
Square13 = 6'd12, Square14 = 6'd13, Square15 = 6'd14,
Square16 = 6'd15, Square17 = 6'd16, Square18 = 6'd17,
Square19 = 6'd18, Square20 = 6'd19, Square21 = 6'd20,
Square22 = 6'd21, Square23 = 6'd22, Square24 = 6'd23,
Square25 = 6'd24, Square26 = 6'd25, Square27 = 6'd26,
Square28 = 6'd27, Square29 = 6'd28, Square30 = 6'd29,
Row_Swap = 6'd30;
assign swap_now = (curr_square_state == Row_Swap);
localparam row1 = 2'd0, row2 = 2'd1, row3 = 2'd2;
always @(posedge clk)
begin: row_state_table
case(curr_row_state)
row1: curr_row_state = swap_now ? row2 : row1;
row2: curr_row_state = swap_now ? row3 : row2;
row3: curr_row_state = swap_now ? row1 : row3;
default: curr_row_state = row1;
endcase
case(curr_square_state)
Square1: curr_square_state = Square2;
Square2: curr_square_state = Square3;
Square3: curr_square_state = Square4;
Square4: curr_square_state = Square5;
Square5: curr_square_state = Square6;
Square6: curr_square_state = Square7;
Square7: curr_square_state = Square8;
Square8: curr_square_state = Square9;
Square9: curr_square_state = Square10;
Square10: curr_square_state = Square11;
Square11: curr_square_state = Square12;
Square12: curr_square_state = Square13;
Square13: curr_square_state = Square14;
Square14: curr_square_state = Square15;
Square15: curr_square_state = Square16;
Square16: curr_square_state = Square17;
Square17: curr_square_state = Square18;
Square18: curr_square_state = Square19;
Square19: curr_square_state = Square20;
Square20: curr_square_state = Square21;
Square21: curr_square_state = Square22;
Square22: curr_square_state = Square23;
Square23: curr_square_state = Square24;
Square24: curr_square_state = Square25;
Square25: curr_square_state = Square26;
Square26: curr_square_state = Row_Swap;
Row_Swap: curr_square_state = Square1;
default: curr_square_state = Square1;
endcase
end
always@(*)
begin: make_coordinates
if (curr_square_state != Row_Swap)
begin
curr_x = {start_x + {x_offset * curr_square_state}};
curr_y = {start_y + {y_offset * curr_row_state}};
case(curr_row_state)
row1: curr_colour = red_sequence[curr_square_state] ? RED : BLACK;
row2: curr_colour = yellow_sequence[curr_square_state] ? YELLOW : BLACK;
row3: curr_colour = blue_sequence[curr_square_state] ? BLUE : BLACK;
default: curr_colour = WHITE;
endcase
end
else
begin
curr_x = 0;
curr_y = 0;
curr_colour = BLACK;
end
end
endmodule | module square_info(
input [25:0] red_sequence,
input [25:0] yellow_sequence,
input [25:0] blue_sequence,
input clk,
output [7:0] output_x,
output [6:0] output_y,
output [2:0] colour
); |
reg [6:0] curr_square_state, next_square_state,
curr_row_state;
reg [2:0] curr_colour;
localparam BLACK = 3'b000,
WHITE = 3'b111,
RED = 3'b100,
YELLOW = 3'b110,
GREEN = 3'b010,
CYAN = 3'b011,
BLUE = 3'b001,
MAGENTA = 3'b101;
assign colour = curr_colour;
localparam start_x = 7'b0000001,
start_y = 7'b0110101;
localparam x_offset = 7'b0000101,
y_offset = 7'b0001011;
reg [7:0] curr_x;
reg [6:0] curr_y;
assign output_x = curr_x;
assign output_y = curr_y;
localparam Square1 = 6'd0, Square2 = 6'd1, Square3 = 6'd2,
Square4 = 6'd3, Square5 = 6'd4, Square6 = 6'd5,
Square7 = 6'd6, Square8 = 6'd7, Square9 = 6'd8,
Square10 = 6'd9, Square11 = 6'd10, Square12 = 6'd11,
Square13 = 6'd12, Square14 = 6'd13, Square15 = 6'd14,
Square16 = 6'd15, Square17 = 6'd16, Square18 = 6'd17,
Square19 = 6'd18, Square20 = 6'd19, Square21 = 6'd20,
Square22 = 6'd21, Square23 = 6'd22, Square24 = 6'd23,
Square25 = 6'd24, Square26 = 6'd25, Square27 = 6'd26,
Square28 = 6'd27, Square29 = 6'd28, Square30 = 6'd29,
Row_Swap = 6'd30;
assign swap_now = (curr_square_state == Row_Swap);
localparam row1 = 2'd0, row2 = 2'd1, row3 = 2'd2;
always @(posedge clk)
begin: row_state_table
case(curr_row_state)
row1: curr_row_state = swap_now ? row2 : row1;
row2: curr_row_state = swap_now ? row3 : row2;
row3: curr_row_state = swap_now ? row1 : row3;
default: curr_row_state = row1;
endcase
case(curr_square_state)
Square1: curr_square_state = Square2;
Square2: curr_square_state = Square3;
Square3: curr_square_state = Square4;
Square4: curr_square_state = Square5;
Square5: curr_square_state = Square6;
Square6: curr_square_state = Square7;
Square7: curr_square_state = Square8;
Square8: curr_square_state = Square9;
Square9: curr_square_state = Square10;
Square10: curr_square_state = Square11;
Square11: curr_square_state = Square12;
Square12: curr_square_state = Square13;
Square13: curr_square_state = Square14;
Square14: curr_square_state = Square15;
Square15: curr_square_state = Square16;
Square16: curr_square_state = Square17;
Square17: curr_square_state = Square18;
Square18: curr_square_state = Square19;
Square19: curr_square_state = Square20;
Square20: curr_square_state = Square21;
Square21: curr_square_state = Square22;
Square22: curr_square_state = Square23;
Square23: curr_square_state = Square24;
Square24: curr_square_state = Square25;
Square25: curr_square_state = Square26;
Square26: curr_square_state = Row_Swap;
Row_Swap: curr_square_state = Square1;
default: curr_square_state = Square1;
endcase
end
always@(*)
begin: make_coordinates
if (curr_square_state != Row_Swap)
begin
curr_x = {start_x + {x_offset * curr_square_state}};
curr_y = {start_y + {y_offset * curr_row_state}};
case(curr_row_state)
row1: curr_colour = red_sequence[curr_square_state] ? RED : BLACK;
row2: curr_colour = yellow_sequence[curr_square_state] ? YELLOW : BLACK;
row3: curr_colour = blue_sequence[curr_square_state] ? BLUE : BLACK;
default: curr_colour = WHITE;
endcase
end
else
begin
curr_x = 0;
curr_y = 0;
curr_colour = BLACK;
end
end
endmodule | 5 |
141,557 | data/full_repos/permissive/95841292/rtl/pipe_mult.v | 95,841,292 | pipe_mult.v | v | 86 | 81 | [] | [] | [] | [(23, 54), (56, 85)] | null | data/verilator_xmls/e499e7af-feba-493b-8369-33dd8fe822c7.xml | null | 312,130 | module | module pipe_mult
#(
parameter DATA_WIDTH = 32,
parameter STAGES = 8
)
(
input wire clk,
input wire rst,
input wire en,
input wire [DATA_WIDTH-1:0] multiplier_i,
input wire [DATA_WIDTH-1:0] multicand_i,
output wire [DATA_WIDTH-1:0] product_o,
output wire done_o
);
wire [STAGES-2:0] inner_dones;
wire [DATA_WIDTH*(STAGES-1)-1:0] inner_mpliers, inner_mcands, inner_prods;
wire [DATA_WIDTH-1:0] final_mcand, final_mplier;
stage_mult #(DATA_WIDTH, DATA_WIDTH / STAGES) stages [STAGES-1:0]
(
.clk(clk), .rst(rst),
.en({inner_dones, en}),
.mcand_i({inner_mcands, multicand_i}),
.mplier_i({inner_mpliers, multiplier_i}),
.prod_i({inner_prods, {DATA_WIDTH{1'b0}}}),
.done_o({done_o, inner_dones}),
.mcand_o({final_mcand, inner_mcands}),
.mplier_o({final_mplier, inner_mpliers}),
.prod_o({product_o, inner_prods})
);
endmodule | module pipe_mult
#(
parameter DATA_WIDTH = 32,
parameter STAGES = 8
)
(
input wire clk,
input wire rst,
input wire en,
input wire [DATA_WIDTH-1:0] multiplier_i,
input wire [DATA_WIDTH-1:0] multicand_i,
output wire [DATA_WIDTH-1:0] product_o,
output wire done_o
); |
wire [STAGES-2:0] inner_dones;
wire [DATA_WIDTH*(STAGES-1)-1:0] inner_mpliers, inner_mcands, inner_prods;
wire [DATA_WIDTH-1:0] final_mcand, final_mplier;
stage_mult #(DATA_WIDTH, DATA_WIDTH / STAGES) stages [STAGES-1:0]
(
.clk(clk), .rst(rst),
.en({inner_dones, en}),
.mcand_i({inner_mcands, multicand_i}),
.mplier_i({inner_mpliers, multiplier_i}),
.prod_i({inner_prods, {DATA_WIDTH{1'b0}}}),
.done_o({done_o, inner_dones}),
.mcand_o({final_mcand, inner_mcands}),
.mplier_o({final_mplier, inner_mpliers}),
.prod_o({product_o, inner_prods})
);
endmodule | 0 |
141,558 | data/full_repos/permissive/95841292/rtl/pipe_mult.v | 95,841,292 | pipe_mult.v | v | 86 | 81 | [] | [] | [] | [(23, 54), (56, 85)] | null | data/verilator_xmls/e499e7af-feba-493b-8369-33dd8fe822c7.xml | null | 312,130 | module | module stage_mult
#(
parameter DATA_WIDTH = 32,
parameter SEL_WIDTH = 8
)
(
input wire clk,
input wire rst,
input wire en,
input wire [DATA_WIDTH-1:0] mcand_i, mplier_i, prod_i,
output wire done_o,
output wire [DATA_WIDTH-1:0] mcand_o, mplier_o, prod_o
);
wire [DATA_WIDTH-1:0] partial_prod;
reg [DATA_WIDTH-1:0] mcand, mplier, prod;
reg done;
assign partial_prod = mplier_i[SEL_WIDTH-1:0] * mcand_i;
assign mcand_o = mcand;
assign mplier_o = mplier;
assign prod_o = prod;
assign done_o = done;
always @(posedge clk) begin
done <= rst ? 0 : en;
mcand <= mcand_i << SEL_WIDTH;
mplier <= mplier_i >> SEL_WIDTH;
prod <= prod_i + partial_prod;
end
endmodule | module stage_mult
#(
parameter DATA_WIDTH = 32,
parameter SEL_WIDTH = 8
)
(
input wire clk,
input wire rst,
input wire en,
input wire [DATA_WIDTH-1:0] mcand_i, mplier_i, prod_i,
output wire done_o,
output wire [DATA_WIDTH-1:0] mcand_o, mplier_o, prod_o
); |
wire [DATA_WIDTH-1:0] partial_prod;
reg [DATA_WIDTH-1:0] mcand, mplier, prod;
reg done;
assign partial_prod = mplier_i[SEL_WIDTH-1:0] * mcand_i;
assign mcand_o = mcand;
assign mplier_o = mplier;
assign prod_o = prod;
assign done_o = done;
always @(posedge clk) begin
done <= rst ? 0 : en;
mcand <= mcand_i << SEL_WIDTH;
mplier <= mplier_i >> SEL_WIDTH;
prod <= prod_i + partial_prod;
end
endmodule | 0 |
141,559 | data/full_repos/permissive/95841292/rtl/sync_dp_ram.v | 95,841,292 | sync_dp_ram.v | v | 26 | 45 | [] | [] | [] | null | line:9: before: "+:" | null | 1: b"%Error: data/full_repos/permissive/95841292/rtl/sync_dp_ram.v:9: syntax error, unexpected +:, expecting ':'\n input wire [0 +: ADDR_WIDTH] wr_addr,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_dp_ram.v:10: syntax error, unexpected +:, expecting ':'\n input wire [0 +: DATA_WIDTH] wr_data,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_dp_ram.v:12: syntax error, unexpected +:, expecting ':'\n input wire [0 +: ADDR_WIDTH] rd_addr,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_dp_ram.v:13: syntax error, unexpected +:, expecting ':'\n output wire [0 +: DATA_WIDTH] rd_data,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_dp_ram.v:16: syntax error, unexpected +:, expecting ':'\n reg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];\n ^~\n%Error: Exiting due to 5 error(s)\n" | 312,131 | module | module sync_dp_ram
#(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 3
)
(
input wire clk,
input wire wr_en,
input wire [0 +: ADDR_WIDTH] wr_addr,
input wire [0 +: DATA_WIDTH] wr_data,
input wire [0 +: ADDR_WIDTH] rd_addr,
output wire [0 +: DATA_WIDTH] rd_data,
);
reg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];
assign rd_data = mem[rd_addr];
always @(posedge clk) begin
if (wr_en)
mem[wr_addr] <= wr_data;
end
endmodule | module sync_dp_ram
#(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 3
)
(
input wire clk,
input wire wr_en,
input wire [0 +: ADDR_WIDTH] wr_addr,
input wire [0 +: DATA_WIDTH] wr_data,
input wire [0 +: ADDR_WIDTH] rd_addr,
output wire [0 +: DATA_WIDTH] rd_data,
); |
reg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];
assign rd_data = mem[rd_addr];
always @(posedge clk) begin
if (wr_en)
mem[wr_addr] <= wr_data;
end
endmodule | 0 |
141,560 | data/full_repos/permissive/95841292/rtl/sync_fifo.v | 95,841,292 | sync_fifo.v | v | 47 | 48 | [] | [] | [] | null | line:11: before: "+:" | null | 1: b"%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:11: syntax error, unexpected +:, expecting ':'\n input wire [0 +: DATA_WIDTH] wr_data,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:12: syntax error, unexpected +:, expecting ':'\n output wire [0 +: DATA_WIDTH] rd_data,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire empty,\n ^~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:15: syntax error, unexpected ')', expecting IDENTIFIER or do or final\n)\n^\n%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:16: syntax error, unexpected +:, expecting ':'\n reg [0 +: RAM_DEPTH] head;\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:17: syntax error, unexpected +:, expecting ':'\n reg [0 +: RAM_DEPTH] tail;\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:18: syntax error, unexpected +:, expecting ':'\n reg [0 +: RAM_DEPTH] cnt;\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/sync_fifo.v:25: syntax error, unexpected always\n always @(posedge clk) begin\n ^~~~~~\n%Error: Exiting due to 8 error(s)\n" | 312,132 | module | module sync_fifo
#(
parameter DATA_WIDTH = 8,
parameter RAM_DEPTH = 3
)
(
input wire clk,
input wire rst,
input wire rd_en,
input wire wr_en,
input wire [0 +: DATA_WIDTH] wr_data,
output wire [0 +: DATA_WIDTH] rd_data,
output wire full,
output wire empty,
)
reg [0 +: RAM_DEPTH] head;
reg [0 +: RAM_DEPTH] tail;
reg [0 +: RAM_DEPTH] cnt;
assign empty = cnt == 0;
assign full = cnt == (1<<RAM_DEPTH);
wire queue = wr_en && !full;
wire dequeue = rd_en && !empty;
always @(posedge clk) begin
if (rst) begin
head <= 0;
tail <= 0;
cnt <= 0;
end
else
head <= head + queue;
tail <= tail + dequeue;
cnt <= cnt + (queue - dequeue);
end
end
sync_dp_ram #(DATA_WIDTH, RAM_DEPTH) fifo_ram
(.clk(clk),
.wr_en(wr_en && !full),
.wr_addr(head),
.wr_data(wr_data),
.rd_en(rd_en && !empty),
.rd_addr(tail),
.rd_data(rd_data));
endmodule | module sync_fifo
#(
parameter DATA_WIDTH = 8,
parameter RAM_DEPTH = 3
)
(
input wire clk,
input wire rst,
input wire rd_en,
input wire wr_en,
input wire [0 +: DATA_WIDTH] wr_data,
output wire [0 +: DATA_WIDTH] rd_data,
output wire full,
output wire empty,
)
reg [0 +: RAM_DEPTH] head; |
reg [0 +: RAM_DEPTH] tail;
reg [0 +: RAM_DEPTH] cnt;
assign empty = cnt == 0;
assign full = cnt == (1<<RAM_DEPTH);
wire queue = wr_en && !full;
wire dequeue = rd_en && !empty;
always @(posedge clk) begin
if (rst) begin
head <= 0;
tail <= 0;
cnt <= 0;
end
else
head <= head + queue;
tail <= tail + dequeue;
cnt <= cnt + (queue - dequeue);
end
end
sync_dp_ram #(DATA_WIDTH, RAM_DEPTH) fifo_ram
(.clk(clk),
.wr_en(wr_en && !full),
.wr_addr(head),
.wr_data(wr_data),
.rd_en(rd_en && !empty),
.rd_addr(tail),
.rd_data(rd_data));
endmodule | 0 |
141,561 | data/full_repos/permissive/95841292/rtl/trv_alu.v | 95,841,292 | trv_alu.v | v | 74 | 54 | [] | [] | [] | null | line:9: before: "=" | null | 1: b"%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:9: syntax error, unexpected '=', expecting IDENTIFIER\n s_rs1 = rs1;\n ^\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:15: Define or directive not defined: '`TRV_OPCODE_BR_EQ'\n `TRV_OPCODE_BR_EQ:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:15: syntax error, unexpected ':', expecting endcase\n `TRV_OPCODE_BR_EQ:\n ^\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:17: Define or directive not defined: '`TRV_OPCODE_BR_NE'\n `TRV_OPCODE_BR_NE:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:19: Define or directive not defined: '`TRV_OPCODE_BR_LT'\n `TRV_OPCODE_BR_LT:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:21: Define or directive not defined: '`TRV_OPCODE_BR_GE'\n `TRV_OPCODE_BR_GE:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:23: Define or directive not defined: '`TRV_OPCODE_BR_LTU'\n `TRV_OPCODE_BR_LTU:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:25: Define or directive not defined: '`TRV_OPCODE_BR_GEU'\n `TRV_OPCODE_BR_GEU:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:44: syntax error, unexpected always\n always @* begin\n ^~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:47: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC'\n `TRV_OPCODE_ALU_OP_ACC: begin\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:47: syntax error, unexpected ':', expecting endcase\n `TRV_OPCODE_ALU_OP_ACC: begin\n ^\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:49: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_ADD'\n `TRV_OPCODE_ALU_OP_ACC_ADD:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:51: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_SUB'\n `TRV_OPCODE_ALU_OP_ACC_SUB:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:53: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_MUL'\n `TRV_OPCODE_ALU_OP_ACC_MUL:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:57: Define or directive not defined: '`TRV_OPCODE_ALU_OP_AND'\n `TRV_OPCODE_ALU_OP_AND:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:59: Define or directive not defined: '`TRV_OPCODE_ALU_OP_OR'\n `TRV_OPCODE_ALU_OP_OR:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:61: Define or directive not defined: '`TRV_OPCODE_ALU_OP_XOR'\n `TRV_OPCODE_ALU_OP_XOR:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:63: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SLT'\n `TRV_OPCODE_ALU_OP_SLT:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:65: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SLTU'\n `TRV_OPCODE_ALU_OP_SLTU:\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:67: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SR'\n `TRV_OPCODE_ALU_OP_SR:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:69: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SL'\n `TRV_OPCODE_ALU_OP_SL:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n" | 312,133 | module | module trv_br_cond
(
input wire [2:0] op,
input wire [31:0] rs1,
input wire [31:0] rs2,
output wire take_branch
);
wire signed s_rs1, s_rs2;
s_rs1 = rs1;
s_rs2 = rs2;
always @* begin
take_branch = 0;
case (op)
`TRV_OPCODE_BR_EQ:
take_branch = rs1 == rs2;
`TRV_OPCODE_BR_NE:
take_branch = rs1 != rs2;
`TRV_OPCODE_BR_LT:
take_branch = s_rs1 < s_rs2;
`TRV_OPCODE_BR_GE:
take_branch = !(s_rs1 < s_rs2);
`TRV_OPCODE_BR_LTU:
take_branch = rs1 < rs2;
`TRV_OPCODE_BR_GEU:
take_branch = !(rs1 < rs2);
endcase
end
endmodule | module trv_br_cond
(
input wire [2:0] op,
input wire [31:0] rs1,
input wire [31:0] rs2,
output wire take_branch
); |
wire signed s_rs1, s_rs2;
s_rs1 = rs1;
s_rs2 = rs2;
always @* begin
take_branch = 0;
case (op)
`TRV_OPCODE_BR_EQ:
take_branch = rs1 == rs2;
`TRV_OPCODE_BR_NE:
take_branch = rs1 != rs2;
`TRV_OPCODE_BR_LT:
take_branch = s_rs1 < s_rs2;
`TRV_OPCODE_BR_GE:
take_branch = !(s_rs1 < s_rs2);
`TRV_OPCODE_BR_LTU:
take_branch = rs1 < rs2;
`TRV_OPCODE_BR_GEU:
take_branch = !(rs1 < rs2);
endcase
end
endmodule | 0 |
141,562 | data/full_repos/permissive/95841292/rtl/trv_alu.v | 95,841,292 | trv_alu.v | v | 74 | 54 | [] | [] | [] | null | line:9: before: "=" | null | 1: b"%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:9: syntax error, unexpected '=', expecting IDENTIFIER\n s_rs1 = rs1;\n ^\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:15: Define or directive not defined: '`TRV_OPCODE_BR_EQ'\n `TRV_OPCODE_BR_EQ:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:15: syntax error, unexpected ':', expecting endcase\n `TRV_OPCODE_BR_EQ:\n ^\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:17: Define or directive not defined: '`TRV_OPCODE_BR_NE'\n `TRV_OPCODE_BR_NE:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:19: Define or directive not defined: '`TRV_OPCODE_BR_LT'\n `TRV_OPCODE_BR_LT:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:21: Define or directive not defined: '`TRV_OPCODE_BR_GE'\n `TRV_OPCODE_BR_GE:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:23: Define or directive not defined: '`TRV_OPCODE_BR_LTU'\n `TRV_OPCODE_BR_LTU:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:25: Define or directive not defined: '`TRV_OPCODE_BR_GEU'\n `TRV_OPCODE_BR_GEU:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:44: syntax error, unexpected always\n always @* begin\n ^~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:47: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC'\n `TRV_OPCODE_ALU_OP_ACC: begin\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:47: syntax error, unexpected ':', expecting endcase\n `TRV_OPCODE_ALU_OP_ACC: begin\n ^\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:49: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_ADD'\n `TRV_OPCODE_ALU_OP_ACC_ADD:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:51: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_SUB'\n `TRV_OPCODE_ALU_OP_ACC_SUB:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:53: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_MUL'\n `TRV_OPCODE_ALU_OP_ACC_MUL:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:57: Define or directive not defined: '`TRV_OPCODE_ALU_OP_AND'\n `TRV_OPCODE_ALU_OP_AND:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:59: Define or directive not defined: '`TRV_OPCODE_ALU_OP_OR'\n `TRV_OPCODE_ALU_OP_OR:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:61: Define or directive not defined: '`TRV_OPCODE_ALU_OP_XOR'\n `TRV_OPCODE_ALU_OP_XOR:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:63: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SLT'\n `TRV_OPCODE_ALU_OP_SLT:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:65: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SLTU'\n `TRV_OPCODE_ALU_OP_SLTU:\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:67: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SR'\n `TRV_OPCODE_ALU_OP_SR:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_alu.v:69: Define or directive not defined: '`TRV_OPCODE_ALU_OP_SL'\n `TRV_OPCODE_ALU_OP_SL:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n" | 312,133 | module | module trv_alu
(
input wire [2:0] op,
input wire [5:0] arg,
input wire [31:0] rs1,
input wire [31:0] rs2,
output wire [31:0] rd,
);
wire signed s_rs1, s_rs2;
assign s_rs1 = rs1;
assign s_rs2 = rs2;
always @* begin
rd = 0;
case(op)
`TRV_OPCODE_ALU_OP_ACC: begin
case (arg)
`TRV_OPCODE_ALU_OP_ACC_ADD:
rd = rs1 + rs2;
`TRV_OPCODE_ALU_OP_ACC_SUB:
rd = rs1 - rs2;
`TRV_OPCODE_ALU_OP_ACC_MUL:
rd = rs1 * rs2;
endcase
end
`TRV_OPCODE_ALU_OP_AND:
rd = rs1 & rs2;
`TRV_OPCODE_ALU_OP_OR:
rd = rs1 | rs2;
`TRV_OPCODE_ALU_OP_XOR:
rd = rs1 ^ rs2;
`TRV_OPCODE_ALU_OP_SLT:
rd = {30'b0, s_rs1 < s_rs2};
`TRV_OPCODE_ALU_OP_SLTU:
rd = {30'b0, rs1 < rs2};
`TRV_OPCODE_ALU_OP_SR:
rd = (arg[1] ? rs1 >> rs2 : s_rs1 >>> s_rs2);
`TRV_OPCODE_ALU_OP_SL:
rd = (arg[1] ? rs1 << rs2 : s_rs1 <<< s_rs2);
endcase
end
endmodule | module trv_alu
(
input wire [2:0] op,
input wire [5:0] arg,
input wire [31:0] rs1,
input wire [31:0] rs2,
output wire [31:0] rd,
); |
wire signed s_rs1, s_rs2;
assign s_rs1 = rs1;
assign s_rs2 = rs2;
always @* begin
rd = 0;
case(op)
`TRV_OPCODE_ALU_OP_ACC: begin
case (arg)
`TRV_OPCODE_ALU_OP_ACC_ADD:
rd = rs1 + rs2;
`TRV_OPCODE_ALU_OP_ACC_SUB:
rd = rs1 - rs2;
`TRV_OPCODE_ALU_OP_ACC_MUL:
rd = rs1 * rs2;
endcase
end
`TRV_OPCODE_ALU_OP_AND:
rd = rs1 & rs2;
`TRV_OPCODE_ALU_OP_OR:
rd = rs1 | rs2;
`TRV_OPCODE_ALU_OP_XOR:
rd = rs1 ^ rs2;
`TRV_OPCODE_ALU_OP_SLT:
rd = {30'b0, s_rs1 < s_rs2};
`TRV_OPCODE_ALU_OP_SLTU:
rd = {30'b0, rs1 < rs2};
`TRV_OPCODE_ALU_OP_SR:
rd = (arg[1] ? rs1 >> rs2 : s_rs1 >>> s_rs2);
`TRV_OPCODE_ALU_OP_SL:
rd = (arg[1] ? rs1 << rs2 : s_rs1 <<< s_rs2);
endcase
end
endmodule | 0 |
141,563 | data/full_repos/permissive/95841292/rtl/trv_decoder.v | 95,841,292 | trv_decoder.v | v | 117 | 82 | [] | [] | [] | null | line:17: before: ")" | null | 1: b"%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:17: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:24: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC'\n alu_op = `TRV_OPCODE_ALU_OP_ACC;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:25: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_ADD'\n alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:27: Define or directive not defined: '`TRV_ALU_ARG_REG'\n sel_rs1 = `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:28: Define or directive not defined: '`TRV_ALU_ARG_REG'\n sel_rs2 = `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:29: Define or directive not defined: '`TRV_ALU_ARG_REG'\n sel_rd = `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:30: Define or directive not defined: '`TRV_ZERO_REG'\n rs1 = `TRV_ZERO_REG;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:31: Define or directive not defined: '`TRV_ZERO_REG'\n rs2 = `TRV_ZERO_REG;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:32: Define or directive not defined: '`TRV_ZERO_REG'\n rd = `TRV_ZERO_REG;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:33: Define or directive not defined: '`TRV_OPCODE'\n case (`TRV_OPCODE(inst))\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:34: Define or directive not defined: '`TRV_OPCODE_CSR'\n `TRV_OPCODE_CSR: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:35: Define or directive not defined: '`TRV_ALU_ARG_REG'\n sel_rd = `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:36: Define or directive not defined: '`TRV_OPCODE_RS1'\n rs1 = `TRV_OPCODE_RS1(inst);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:37: Define or directive not defined: '`TRV_OPCODE_RD'\n rd = `TRV_OPCODE_RD(inst);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:38: Define or directive not defined: '`TRV_OPCODE_I_IMM'\n imm = `TRV_OPCODE_I_IMM(inst);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:39: Define or directive not defined: '`TRV_OPCODE_ALU_OP'\n alu_op = `TRV_OPCODE_ALU_OP(inst);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:41: Define or directive not defined: '`TRV_OPCODE_RR'\n `TRV_OPCODE_RR: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:42: Define or directive not defined: '`TRV_OPCODE_RS1'\n rs1 = `TRV_OPCODE_RS1(inst);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:43: Define or directive not defined: '`TRV_OPCODE_RS2'\n rs2 = `TRV_OPCODE_RS2(inst);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:44: Define or directive not defined: '`TRV_OPCODE_RD'\n rd = `TRV_OPCODE_RD(inst);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:45: Define or directive not defined: '`TRV_OPCODE_ALU_ARG'\n alu_arg = `TRV_OPCODE_ALU_ARG(inst);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:46: Define or directive not defined: '`TRV_OPCODE_ALU_OP'\n alu_op = `TRV_OPCODE_ALU_OP(inst);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:48: Define or directive not defined: '`TRV_OPCODE_RI_GRP1'\n `TRV_OPCODE_RI_GRP1: begin\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:49: Define or directive not defined: '`TRV_ALU_ARG_IMM'\n sel_rs2 = `TRV_ALU_ARG_IMM;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:50: Define or directive not defined: '`TRV_OPCODE_RS1'\n rs1 = `TRV_OPCODE_RS1(inst);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:51: Define or directive not defined: '`TRV_OPCODE_RD'\n rd = `TRV_OPCODE_RD(inst);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:52: Define or directive not defined: '`TRV_OPCODE_ALU_OP'\n alu_op = `TRV_OPCODE_ALU_OP(inst);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:54: Define or directive not defined: '`TRV_OPCODE_RS2'\n imm = `TRV_OPCODE_RS2(inst);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:55: Define or directive not defined: '`TRV_OPCODE_ALU_ARG'\n alu_arg = `TRV_OPCODE_ALU_ARG(inst);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:58: Define or directive not defined: '`TRV_OPCODE_I_IMM'\n imm = `TRV_OPCODE_I_IMM(inst);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:60: Define or directive not defined: '`TRV_OPCODE_LUI'\n `TRV_OPCODE_LUI, `TRV_OPCODE_AUIPC: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:60: Define or directive not defined: '`TRV_OPCODE_AUIPC'\n `TRV_OPCODE_LUI, `TRV_OPCODE_AUIPC: begin\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:61: Define or directive not defined: '`TRV_OPCODE_AUIPC'\n sel_rs1 = opcode == `TRV_OPCODE_AUIPC ? `TRV_ALU_ARG_PC : `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:61: Define or directive not defined: '`TRV_ALU_ARG_PC'\n sel_rs1 = opcode == `TRV_OPCODE_AUIPC ? `TRV_ALU_ARG_PC : `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:61: Define or directive not defined: '`TRV_ALU_ARG_REG'\n sel_rs1 = opcode == `TRV_OPCODE_AUIPC ? `TRV_ALU_ARG_PC : `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:62: Define or directive not defined: '`TRV_ALU_ARG_IMM'\n sel_rs2 = `TRV_ALU_ARG_IMM;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:63: Define or directive not defined: '`TRV_ALU_ARG_REG'\n sel_rd = `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:64: Define or directive not defined: '`TRV_OPCODE_ALU_OP'\n alu_op = `TRV_OPCODE_ALU_OP(inst);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:65: Define or directive not defined: '`TRV_OPCODE_RD'\n rd = `TRV_OPCODE_RD(inst);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:66: Define or directive not defined: '`TRV_OPCODE_U_IMM'\n imm = `TRV_OPCODE_U_IMM(inst) << 12;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:68: Define or directive not defined: '`TRV_OPCODE_STORE'\n `TRV_OPCODE_STORE: begin\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:70: Define or directive not defined: '`TRV_ALU_ARG_MEM'\n sel_rs1 = `TRV_ALU_ARG_MEM;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:71: Define or directive not defined: '`TRV_OPCODE_RS1'\n rs1 = `TRV_OPCODE_RS1(inst);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:72: Define or directive not defined: '`TRV_OPCODE_RS2'\n rs2 = `TRV_OPCODE_RS2(inst);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:73: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC'\n alu_op = `TRV_OPCODE_ALU_OP_ACC;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:74: Define or directive not defined: '`TRV_OPCODE_ALU_OP_ACC_ADD'\n alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:75: Define or directive not defined: '`TRV_OPCODE_S_IMM'\n imm = `TRV_OPCODE_S_IMM(inst);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:77: Define or directive not defined: '`TRV_OPCODE_LOAD'\n `TRV_OPCODE_LOAD: begin\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:79: Define or directive not defined: '`TRV_ALU_ARG_IMM'\n sel_rs2 = `TRV_ALU_ARG_IMM;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/trv_decoder.v:80: Define or directive not defined: '`TRV_ALU_ARG_REG'\n sel_rd = `TRV_ALU_ARG_REG;\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 312,134 | module | module trv_decoder
(
input wire [31:0] inst,
output wire [2:0] alu_op,
output wire [5:0] alu_arg,
output wire sel_rs1,
output wire sel_rs2,
output wire sel_rd,
output wire [4:0] rd,
output wire [4:0] rs1,
output wire [4:0] rs2,
output wire [31:0] imm,
output wire is_rd_mem,
output wire is_wr_mem,
output wire is_cond_br,
output wire is_uncond_br,
);
always @* begin
is_rd_mem = 0;
is_wr_mem = 0;
is_cond_br = 0;
is_uncond_br = 0;
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = 31{1'bx};
sel_rs1 = `TRV_ALU_ARG_REG;
sel_rs2 = `TRV_ALU_ARG_REG;
sel_rd = `TRV_ALU_ARG_REG;
rs1 = `TRV_ZERO_REG;
rs2 = `TRV_ZERO_REG;
rd = `TRV_ZERO_REG;
case (`TRV_OPCODE(inst))
`TRV_OPCODE_CSR: begin
sel_rd = `TRV_ALU_ARG_REG;
rs1 = `TRV_OPCODE_RS1(inst);
rd = `TRV_OPCODE_RD(inst);
imm = `TRV_OPCODE_I_IMM(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
end
`TRV_OPCODE_RR: begin
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
rd = `TRV_OPCODE_RD(inst);
alu_arg = `TRV_OPCODE_ALU_ARG(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
end
`TRV_OPCODE_RI_GRP1: begin
sel_rs2 = `TRV_ALU_ARG_IMM;
rs1 = `TRV_OPCODE_RS1(inst);
rd = `TRV_OPCODE_RD(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
if (alu_op == 3'b101 || alu_op == 3'b001) begin
imm = `TRV_OPCODE_RS2(inst);
alu_arg = `TRV_OPCODE_ALU_ARG(inst);
end
else
imm = `TRV_OPCODE_I_IMM(inst);
end
`TRV_OPCODE_LUI, `TRV_OPCODE_AUIPC: begin
sel_rs1 = opcode == `TRV_OPCODE_AUIPC ? `TRV_ALU_ARG_PC : `TRV_ALU_ARG_REG;
sel_rs2 = `TRV_ALU_ARG_IMM;
sel_rd = `TRV_ALU_ARG_REG;
alu_op = `TRV_OPCODE_ALU_OP(inst);
rd = `TRV_OPCODE_RD(inst);
imm = `TRV_OPCODE_U_IMM(inst) << 12;
end
`TRV_OPCODE_STORE: begin
is_wr_mem = 1;
sel_rs1 = `TRV_ALU_ARG_MEM;
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_S_IMM(inst);
end
`TRV_OPCODE_LOAD: begin
is_rd_mem = 1;
sel_rs2 = `TRV_ALU_ARG_IMM;
sel_rd = `TRV_ALU_ARG_REG;
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
rd = `TRV_OPCODE_RD(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_I_IMM(inst);
end
`TRV_OPCODE_JAL: begin
is_uncond_br = 1;
sel_rs1 = `TRV_ALU_ARG_PC;
sel_rd = `TRV_ALU_ARG_REG;
rd = `TRV_OPCODE_RD(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_J_IMM(inst);
end
`TRV_OPCODE_UNCOND_BR: begin
is_uncond_br = 1;
sel_rd = `TRV_ALU_ARG_REG;
sel_rs2 = `TRV_ALU_ARG_IMM;
rd = `TRV_OPCODE_RD(inst);
rs1 = `TRV_OPCODE_RS1(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_J_IMM(inst);
end
`TRV_OPCODE_COND_BR: begin
is_cond_br = 1;
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
imm = `TRV_OPCODE_B_IMM(inst);
end
endcase
end
endmodule | module trv_decoder
(
input wire [31:0] inst,
output wire [2:0] alu_op,
output wire [5:0] alu_arg,
output wire sel_rs1,
output wire sel_rs2,
output wire sel_rd,
output wire [4:0] rd,
output wire [4:0] rs1,
output wire [4:0] rs2,
output wire [31:0] imm,
output wire is_rd_mem,
output wire is_wr_mem,
output wire is_cond_br,
output wire is_uncond_br,
); |
always @* begin
is_rd_mem = 0;
is_wr_mem = 0;
is_cond_br = 0;
is_uncond_br = 0;
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = 31{1'bx};
sel_rs1 = `TRV_ALU_ARG_REG;
sel_rs2 = `TRV_ALU_ARG_REG;
sel_rd = `TRV_ALU_ARG_REG;
rs1 = `TRV_ZERO_REG;
rs2 = `TRV_ZERO_REG;
rd = `TRV_ZERO_REG;
case (`TRV_OPCODE(inst))
`TRV_OPCODE_CSR: begin
sel_rd = `TRV_ALU_ARG_REG;
rs1 = `TRV_OPCODE_RS1(inst);
rd = `TRV_OPCODE_RD(inst);
imm = `TRV_OPCODE_I_IMM(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
end
`TRV_OPCODE_RR: begin
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
rd = `TRV_OPCODE_RD(inst);
alu_arg = `TRV_OPCODE_ALU_ARG(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
end
`TRV_OPCODE_RI_GRP1: begin
sel_rs2 = `TRV_ALU_ARG_IMM;
rs1 = `TRV_OPCODE_RS1(inst);
rd = `TRV_OPCODE_RD(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
if (alu_op == 3'b101 || alu_op == 3'b001) begin
imm = `TRV_OPCODE_RS2(inst);
alu_arg = `TRV_OPCODE_ALU_ARG(inst);
end
else
imm = `TRV_OPCODE_I_IMM(inst);
end
`TRV_OPCODE_LUI, `TRV_OPCODE_AUIPC: begin
sel_rs1 = opcode == `TRV_OPCODE_AUIPC ? `TRV_ALU_ARG_PC : `TRV_ALU_ARG_REG;
sel_rs2 = `TRV_ALU_ARG_IMM;
sel_rd = `TRV_ALU_ARG_REG;
alu_op = `TRV_OPCODE_ALU_OP(inst);
rd = `TRV_OPCODE_RD(inst);
imm = `TRV_OPCODE_U_IMM(inst) << 12;
end
`TRV_OPCODE_STORE: begin
is_wr_mem = 1;
sel_rs1 = `TRV_ALU_ARG_MEM;
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_S_IMM(inst);
end
`TRV_OPCODE_LOAD: begin
is_rd_mem = 1;
sel_rs2 = `TRV_ALU_ARG_IMM;
sel_rd = `TRV_ALU_ARG_REG;
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
rd = `TRV_OPCODE_RD(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_I_IMM(inst);
end
`TRV_OPCODE_JAL: begin
is_uncond_br = 1;
sel_rs1 = `TRV_ALU_ARG_PC;
sel_rd = `TRV_ALU_ARG_REG;
rd = `TRV_OPCODE_RD(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_J_IMM(inst);
end
`TRV_OPCODE_UNCOND_BR: begin
is_uncond_br = 1;
sel_rd = `TRV_ALU_ARG_REG;
sel_rs2 = `TRV_ALU_ARG_IMM;
rd = `TRV_OPCODE_RD(inst);
rs1 = `TRV_OPCODE_RS1(inst);
alu_op = `TRV_OPCODE_ALU_OP_ACC;
alu_arg = `TRV_OPCODE_ALU_OP_ACC_ADD;
imm = `TRV_OPCODE_J_IMM(inst);
end
`TRV_OPCODE_COND_BR: begin
is_cond_br = 1;
rs1 = `TRV_OPCODE_RS1(inst);
rs2 = `TRV_OPCODE_RS2(inst);
alu_op = `TRV_OPCODE_ALU_OP(inst);
imm = `TRV_OPCODE_B_IMM(inst);
end
endcase
end
endmodule | 0 |
141,564 | data/full_repos/permissive/95841292/rtl/wb_shift_ram.v | 95,841,292 | wb_shift_ram.v | v | 95 | 148 | [] | [] | [] | null | line:8: before: ":" | null | 1: b"%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:12: syntax error, unexpected ')', expecting '['\n)\n^\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire rst_i,\n ^~~~~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [0 +: ADDR_WIDTH] adr_i,\n ^~~~~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:16: syntax error, unexpected +:, expecting ':'\n input wire [0 +: ADDR_WIDTH] adr_i,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:17: syntax error, unexpected +:, expecting ':'\n input wire [0 +: DATA_WIDTH] dat_i,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:18: syntax error, unexpected +:, expecting ':'\n output wire [0 +: DATA_WIDTH] dat_o,\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:19: syntax error, unexpected +:, expecting ':'\n output wire [0 +: ADDR_WIDTH] tag_o, \n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire we_i,\n ^~~~~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire stb_i,\n ^~~~~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire cyc_i,\n ^~~~~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire ack_o,\n ^~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire stall_o\n ^~~~~~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:29: syntax error, unexpected +:, expecting ':'\nreg [0 +: ADDR_WIDTH] lat_pipe_addr [LATENCY_CYCLES];\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:30: syntax error, unexpected +:, expecting ':'\nreg [0 +: DATA_WIDTH] lat_pipe_data [LATENCY_CYCLES];\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:31: syntax error, unexpected +:, expecting ':'\nreg [0 +: DATA_WIDTH / WORD_WIDTH] lat_pipe_sel [LATENCY_CYCLES];\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:36: syntax error, unexpected +:, expecting ':'\nreg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:39: syntax error, unexpected +:, expecting ':'\nreg [0 +: ADDR_WIDTH] current_addr;\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:40: syntax error, unexpected +:, expecting ':'\nreg [0 +: DATA_WIDTH] current_data;\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:41: syntax error, unexpected +:, expecting ':'\nreg [0 +: DATA_WIDTH / WORD_WIDTH] current_sel;\n ^~\n%Error: data/full_repos/permissive/95841292/rtl/wb_shift_ram.v:48: syntax error, unexpected assign\nassign stall_o = 1'b0; \n^~~~~~\n%Error: Exiting due to 20 error(s)\n" | 312,137 | module | module wb_shift_ram
#(
parameter DATA_WIDTH = 32,
parameter WORD_WIDTH = 8,
parameter ADDR_WIDTH = 3,
parameter LATENCY_CYCLES = 3,
)
(
input wire clk_i,
input wire rst_i,
input wire [0 +: ADDR_WIDTH] adr_i,
input wire [0 +: DATA_WIDTH] dat_i,
output wire [0 +: DATA_WIDTH] dat_o,
output wire [0 +: ADDR_WIDTH] tag_o,
input wire sel_i,
input wire we_i,
input wire stb_i,
input wire cyc_i,
output wire ack_o,
output wire stall_o
);
reg [0 +: ADDR_WIDTH] lat_pipe_addr [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH] lat_pipe_data [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH / WORD_WIDTH] lat_pipe_sel [LATENCY_CYCLES];
reg lat_pipe_we [LATENCY_CYCLES];
reg lat_pipe_stb [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];
reg [0 +: ADDR_WIDTH] current_addr;
reg [0 +: DATA_WIDTH] current_data;
reg [0 +: DATA_WIDTH / WORD_WIDTH] current_sel;
reg current_we;
reg current_stb;
integer lat_idx;
assign stall_o = 1'b0;
assign ack_o = current_stb;
assign tag_o = current_addr;
assign dat_o = current_data;
genvar sel_idx;
generate
for (sel_idx = 0 ; sel_idx < (DATA_WIDTH / WORD_WIDTH); sel_idx++) begin : gen_sel_cases
always @(posedge clk_i) begin
if(!rst_i && current_stb && current_we && current_sel[sel_idx]) begin
mem[current_addr][sel_idx*WORD_WIDTH : (sel_idx+1)*WORD_WIDTH - 1] <= current_data[sel_idx*WORD_WIDTH: (sel_idx+1)*WORD_WIDTH - 1];
end
end
endgenerate
always @(posedge clk_i) begin
if (rst_i) begin
for (lat_idx = 0; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_stb[lat_idx] <= 0;
end
end
else begin
lat_pipe_stb [0] <= stb_i;
lat_pipe_sel [0] <= sel_i;
lat_pipe_we [0] <= we_i;
lat_pipe_addr[0] <= adr_i;
lat_pipe_data[0] <= dat_i;
current_addr <= lat_pipe_addr[LATENCY_CYCLES - 1];
current_data <= mem[lat_pipe_addr[LATENCY_CYCLES - 1]];;
current_sel <= lat_pipe_sel [LATENCY_CYCLES - 1];
current_we <= lat_pipe_we [LATENCY_CYCLES - 1];
current_stb <= lat_pipe_stb [LATENCY_CYCLES - 1];
for (lat_idx = 1; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_addr[lat_idx] <= lat_pipe_addr[lat_idx-1];
lat_pipe_data[lat_idx] <= lat_pipe_data[lat_idx-1];
lat_pipe_sel [lat_idx] <= lat_pipe_sel [lat_idx-1];
lat_pipe_we [lat_idx] <= lat_pipe_we [lat_idx-1];
lat_pipe_stb [lat_idx] <= lat_pipe_stb [lat_idx-1];
end
end
end
endmodule | module wb_shift_ram
#(
parameter DATA_WIDTH = 32,
parameter WORD_WIDTH = 8,
parameter ADDR_WIDTH = 3,
parameter LATENCY_CYCLES = 3,
)
(
input wire clk_i,
input wire rst_i,
input wire [0 +: ADDR_WIDTH] adr_i,
input wire [0 +: DATA_WIDTH] dat_i,
output wire [0 +: DATA_WIDTH] dat_o,
output wire [0 +: ADDR_WIDTH] tag_o,
input wire sel_i,
input wire we_i,
input wire stb_i,
input wire cyc_i,
output wire ack_o,
output wire stall_o
); |
reg [0 +: ADDR_WIDTH] lat_pipe_addr [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH] lat_pipe_data [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH / WORD_WIDTH] lat_pipe_sel [LATENCY_CYCLES];
reg lat_pipe_we [LATENCY_CYCLES];
reg lat_pipe_stb [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];
reg [0 +: ADDR_WIDTH] current_addr;
reg [0 +: DATA_WIDTH] current_data;
reg [0 +: DATA_WIDTH / WORD_WIDTH] current_sel;
reg current_we;
reg current_stb;
integer lat_idx;
assign stall_o = 1'b0;
assign ack_o = current_stb;
assign tag_o = current_addr;
assign dat_o = current_data;
genvar sel_idx;
generate
for (sel_idx = 0 ; sel_idx < (DATA_WIDTH / WORD_WIDTH); sel_idx++) begin : gen_sel_cases
always @(posedge clk_i) begin
if(!rst_i && current_stb && current_we && current_sel[sel_idx]) begin
mem[current_addr][sel_idx*WORD_WIDTH : (sel_idx+1)*WORD_WIDTH - 1] <= current_data[sel_idx*WORD_WIDTH: (sel_idx+1)*WORD_WIDTH - 1];
end
end
endgenerate
always @(posedge clk_i) begin
if (rst_i) begin
for (lat_idx = 0; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_stb[lat_idx] <= 0;
end
end
else begin
lat_pipe_stb [0] <= stb_i;
lat_pipe_sel [0] <= sel_i;
lat_pipe_we [0] <= we_i;
lat_pipe_addr[0] <= adr_i;
lat_pipe_data[0] <= dat_i;
current_addr <= lat_pipe_addr[LATENCY_CYCLES - 1];
current_data <= mem[lat_pipe_addr[LATENCY_CYCLES - 1]];;
current_sel <= lat_pipe_sel [LATENCY_CYCLES - 1];
current_we <= lat_pipe_we [LATENCY_CYCLES - 1];
current_stb <= lat_pipe_stb [LATENCY_CYCLES - 1];
for (lat_idx = 1; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_addr[lat_idx] <= lat_pipe_addr[lat_idx-1];
lat_pipe_data[lat_idx] <= lat_pipe_data[lat_idx-1];
lat_pipe_sel [lat_idx] <= lat_pipe_sel [lat_idx-1];
lat_pipe_we [lat_idx] <= lat_pipe_we [lat_idx-1];
lat_pipe_stb [lat_idx] <= lat_pipe_stb [lat_idx-1];
end
end
end
endmodule | 0 |
141,565 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module AND2X1(A, B, Y);
input A, B;
output Y;
and(Y, A, B);
endmodule | module AND2X1(A, B, Y); |
input A, B;
output Y;
and(Y, A, B);
endmodule | 0 |
141,566 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module AND2X2(A, B, Y);
input A, B;
output Y;
and(Y, A, B);
endmodule | module AND2X2(A, B, Y); |
input A, B;
output Y;
and(Y, A, B);
endmodule | 0 |
141,567 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module AOI21X1(A, B, C, Y);
input A, B, C;
output Y;
wire tmp;
and(tmp, A, B);
nor(Y, tmp, C);
endmodule | module AOI21X1(A, B, C, Y); |
input A, B, C;
output Y;
wire tmp;
and(tmp, A, B);
nor(Y, tmp, C);
endmodule | 0 |
141,568 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module AOI22X1(A, B, C, D, Y);
input A, B, C, D;
output Y;
wire tmp0, tmp1;
and(tmp0, A, B);
and(tmp1, C, D);
nor(Y, tmp0, tmp1);
endmodule | module AOI22X1(A, B, C, D, Y); |
input A, B, C, D;
output Y;
wire tmp0, tmp1;
and(tmp0, A, B);
and(tmp1, C, D);
nor(Y, tmp0, tmp1);
endmodule | 0 |
141,569 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module BUFX2(A, Y);
input A;
output Y;
buf(Y, A);
endmodule | module BUFX2(A, Y); |
input A;
output Y;
buf(Y, A);
endmodule | 0 |
141,570 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module BUFX4(A, Y);
input A;
output Y;
buf(Y, A);
endmodule | module BUFX4(A, Y); |
input A;
output Y;
buf(Y, A);
endmodule | 0 |
141,571 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module DFFPOSX1(CLK, D, Q);
input CLK, D;
output reg Q;
always @(posedge CLK)
Q <= D;
endmodule | module DFFPOSX1(CLK, D, Q); |
input CLK, D;
output reg Q;
always @(posedge CLK)
Q <= D;
endmodule | 0 |
141,572 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module INVX1(A, Y);
input A;
output Y;
not(Y, A);
endmodule | module INVX1(A, Y); |
input A;
output Y;
not(Y, A);
endmodule | 0 |
141,573 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module INVX2(A, Y);
input A;
output Y;
not(Y, A);
endmodule | module INVX2(A, Y); |
input A;
output Y;
not(Y, A);
endmodule | 0 |
141,574 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module INVX4(A, Y);
input A;
output Y;
not(Y, A);
endmodule | module INVX4(A, Y); |
input A;
output Y;
not(Y, A);
endmodule | 0 |
141,575 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module INVX8(A, Y);
input A;
output Y;
not(Y, A);
endmodule | module INVX8(A, Y); |
input A;
output Y;
not(Y, A);
endmodule | 0 |
141,576 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module NAND2X1(A, B, Y);
input A, B;
output Y;
nand(Y, A, B);
endmodule | module NAND2X1(A, B, Y); |
input A, B;
output Y;
nand(Y, A, B);
endmodule | 0 |
141,577 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module NAND3X1(A, B, C, Y);
input A, B, C;
output Y;
nand(Y, A, B, C);
endmodule | module NAND3X1(A, B, C, Y); |
input A, B, C;
output Y;
nand(Y, A, B, C);
endmodule | 0 |
141,578 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module NOR2X1(A, B, Y);
input A, B;
output Y;
nor(Y, A, B);
endmodule | module NOR2X1(A, B, Y); |
input A, B;
output Y;
nor(Y, A, B);
endmodule | 0 |
141,579 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module NOR3X1(A, B, C, Y);
input A, B, C;
output Y;
nor(Y, A, B, C);
endmodule | module NOR3X1(A, B, C, Y); |
input A, B, C;
output Y;
nor(Y, A, B, C);
endmodule | 0 |
141,580 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module OAI21X1(A, B, C, Y);
input A, B, C;
output Y;
wire tmp;
or(tmp, A, B);
nand(Y, tmp, C);
endmodule | module OAI21X1(A, B, C, Y); |
input A, B, C;
output Y;
wire tmp;
or(tmp, A, B);
nand(Y, tmp, C);
endmodule | 0 |
141,581 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module OAI22X1(A, B, C, D, Y);
input A, B, C, D;
output Y;
wire tmp0, tmp1;
or(tmp0, A, B);
or(tmp1, C, D);
nand(Y, tmp0, tmp1);
endmodule | module OAI22X1(A, B, C, D, Y); |
input A, B, C, D;
output Y;
wire tmp0, tmp1;
or(tmp0, A, B);
or(tmp1, C, D);
nand(Y, tmp0, tmp1);
endmodule | 0 |
141,582 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module OR2X1(A, B, Y);
input A, B;
output Y;
or(Y, A, B);
endmodule | module OR2X1(A, B, Y); |
input A, B;
output Y;
or(Y, A, B);
endmodule | 0 |
141,583 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module OR2X2(A, B, Y);
input A, B;
output Y;
or(Y, A, B);
endmodule | module OR2X2(A, B, Y); |
input A, B;
output Y;
or(Y, A, B);
endmodule | 0 |
141,584 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module XNOR2X1(A, B, Y);
input A, B;
output Y;
xnor(Y, A, B);
endmodule | module XNOR2X1(A, B, Y); |
input A, B;
output Y;
xnor(Y, A, B);
endmodule | 0 |
141,585 | data/full_repos/permissive/95841292/synth/stdcells.v | 95,841,292 | stdcells.v | v | 137 | 31 | [] | [] | [] | [(1, 5), (7, 11), (13, 19), (21, 28), (30, 34), (36, 40), (42, 47), (49, 53), (55, 59), (61, 65), (67, 71), (73, 77), (79, 83), (85, 89), (91, 95), (97, 103), (105, 112), (114, 118), (120, 124), (126, 130), (132, 136)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/95841292/synth/stdcells.v:7: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'AND2X1\'\nmodule AND2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'AND2X2\'\nmodule AND2X2(A, B, Y);\n ^~~~~~\n : ... Top module \'AOI21X1\'\nmodule AOI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'AOI22X1\'\nmodule AOI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'BUFX2\'\nmodule BUFX2(A, Y);\n ^~~~~\n : ... Top module \'BUFX4\'\nmodule BUFX4(A, Y);\n ^~~~~\n : ... Top module \'DFFPOSX1\'\nmodule DFFPOSX1(CLK, D, Q);\n ^~~~~~~~\n : ... Top module \'INVX1\'\nmodule INVX1(A, Y);\n ^~~~~\n : ... Top module \'INVX2\'\nmodule INVX2(A, Y);\n ^~~~~\n : ... Top module \'INVX4\'\nmodule INVX4(A, Y);\n ^~~~~\n : ... Top module \'INVX8\'\nmodule INVX8(A, Y);\n ^~~~~\n : ... Top module \'NAND2X1\'\nmodule NAND2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'NAND3X1\'\nmodule NAND3X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'NOR2X1\'\nmodule NOR2X1(A, B, Y);\n ^~~~~~\n : ... Top module \'NOR3X1\'\nmodule NOR3X1(A, B, C, Y);\n ^~~~~~\n : ... Top module \'OAI21X1\'\nmodule OAI21X1(A, B, C, Y);\n ^~~~~~~\n : ... Top module \'OAI22X1\'\nmodule OAI22X1(A, B, C, D, Y);\n ^~~~~~~\n : ... Top module \'OR2X1\'\nmodule OR2X1(A, B, Y);\n ^~~~~\n : ... Top module \'OR2X2\'\nmodule OR2X2(A, B, Y);\n ^~~~~\n : ... Top module \'XNOR2X1\'\nmodule XNOR2X1(A, B, Y);\n ^~~~~~~\n : ... Top module \'XOR2X1\'\nmodule XOR2X1(A, B, Y);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 312,138 | module | module XOR2X1(A, B, Y);
input A, B;
output Y;
xor(Y, A, B);
endmodule | module XOR2X1(A, B, Y); |
input A, B;
output Y;
xor(Y, A, B);
endmodule | 0 |
141,586 | data/full_repos/permissive/95841292/tb/pipe_mult_tb.v | 95,841,292 | pipe_mult_tb.v | v | 130 | 122 | [] | [] | [] | [(26, 129)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #2 if(!correct) begin \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:71: Unsupported or unknown PLI call: $dumpfile\n $dumpfile(vcdfn);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:72: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, pipe_mult_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:75: Unsupported or unknown PLI call: $monitor\n $monitor("Time:%4.0f done:%b a:%h b:%h product:%h result:%h",$time,done,stage_a[8],stage_b[8],cres,result);\n ^~~~~~~~\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:84: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:86: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:88: syntax error, unexpected \'@\'\n @(posedge done);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:92: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:94: syntax error, unexpected \'@\'\n @(posedge done);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:100: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:102: syntax error, unexpected \'@\'\n @(posedge done);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:111: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:113: syntax error, unexpected \'@\'\n @(posedge done);\n ^\n%Error: data/full_repos/permissive/95841292/tb/pipe_mult_tb.v:122: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: Exiting due to 13 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,139 | module | module pipe_mult_tb();
reg [1024*8-1:0] vcdfn;
reg [`BIT_WIDTH-1:0] stage_a[`STAGES:0];
reg [`BIT_WIDTH-1:0] stage_b[`STAGES:0];
reg clock, en, reset;
wire [`BIT_WIDTH-1:0] result;
wire done;
wire [`BIT_WIDTH-1:0] cres = stage_a[`STAGES]*stage_b[`STAGES];
wire correct = (cres==result)|~done;
integer i, j;
pipe_mult #(`BIT_WIDTH, `STAGES) m0
(.clk(clock), .rst(reset),
.multiplier_i(stage_a[0]), .multicand_i(stage_b[0]),
.en(en), .product_o(result), .done_o(done));
always @(posedge clock)
for(j=0;j<`STAGES;j=j+1) begin
stage_a[j+1] <= stage_a[j];
stage_b[j+1] <= stage_b[j];
end
always @(posedge clock)
#2 if(!correct) begin
$display("Incorrect at time %4.0f",$time);
$display("cres = %h result = %h",cres,result);
$display ("*** FAILED ***");
$finish;
end
always
begin
#5;
clock=~clock;
end
initial begin
if ($value$plusargs("WAVES=%s",vcdfn)) begin
$dumpfile(vcdfn);
$dumpvars(0, pipe_mult_tb);
end
$monitor("Time:%4.0f done:%b a:%h b:%h product:%h result:%h",$time,done,stage_a[`STAGES],stage_b[`STAGES],cres,result);
$display ("Basic testing");
stage_a[0]=2;
stage_b[0]=3;
reset=1;
clock=0;
en=1;
@(negedge clock);
reset=0;
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
en=1;
stage_a[0]=-1;
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
@(negedge clock);
en=1;
stage_a[0]=-20;
stage_b[0]=5;
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
$display ("Interface test");
for(i=0;i<100;i=i+1)
begin
en=1;
stage_a[0]={$random,$random};
stage_b[0]={$random,$random};
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
end
$display ("Pipelined test");
for(i=0;i<100;i=i+1)
begin
en=1;
stage_a[0]={$random,$random};
stage_b[0]={$random,$random};
@(negedge clock);
end
$display ("*** PASSED ***");
$finish;
end
endmodule | module pipe_mult_tb(); |
reg [1024*8-1:0] vcdfn;
reg [`BIT_WIDTH-1:0] stage_a[`STAGES:0];
reg [`BIT_WIDTH-1:0] stage_b[`STAGES:0];
reg clock, en, reset;
wire [`BIT_WIDTH-1:0] result;
wire done;
wire [`BIT_WIDTH-1:0] cres = stage_a[`STAGES]*stage_b[`STAGES];
wire correct = (cres==result)|~done;
integer i, j;
pipe_mult #(`BIT_WIDTH, `STAGES) m0
(.clk(clock), .rst(reset),
.multiplier_i(stage_a[0]), .multicand_i(stage_b[0]),
.en(en), .product_o(result), .done_o(done));
always @(posedge clock)
for(j=0;j<`STAGES;j=j+1) begin
stage_a[j+1] <= stage_a[j];
stage_b[j+1] <= stage_b[j];
end
always @(posedge clock)
#2 if(!correct) begin
$display("Incorrect at time %4.0f",$time);
$display("cres = %h result = %h",cres,result);
$display ("*** FAILED ***");
$finish;
end
always
begin
#5;
clock=~clock;
end
initial begin
if ($value$plusargs("WAVES=%s",vcdfn)) begin
$dumpfile(vcdfn);
$dumpvars(0, pipe_mult_tb);
end
$monitor("Time:%4.0f done:%b a:%h b:%h product:%h result:%h",$time,done,stage_a[`STAGES],stage_b[`STAGES],cres,result);
$display ("Basic testing");
stage_a[0]=2;
stage_b[0]=3;
reset=1;
clock=0;
en=1;
@(negedge clock);
reset=0;
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
en=1;
stage_a[0]=-1;
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
@(negedge clock);
en=1;
stage_a[0]=-20;
stage_b[0]=5;
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
$display ("Interface test");
for(i=0;i<100;i=i+1)
begin
en=1;
stage_a[0]={$random,$random};
stage_b[0]={$random,$random};
@(negedge clock);
en=0;
@(posedge done);
@(negedge clock);
end
$display ("Pipelined test");
for(i=0;i<100;i=i+1)
begin
en=1;
stage_a[0]={$random,$random};
stage_b[0]={$random,$random};
@(negedge clock);
end
$display ("*** PASSED ***");
$finish;
end
endmodule | 0 |
141,587 | data/full_repos/permissive/95875066/pipeline_processor/ALU.v | 95,875,066 | ALU.v | v | 30 | 53 | [] | [] | [] | null | line:30: before: "/" | null | 1: b"%Error: data/full_repos/permissive/95875066/pipeline_processor/ALU.v:15: Cannot find file containing module: 'ALU_adder'\nALU_adder Add(A, B, ALUFun[0], Sign, Z, V, N, S1);\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/ALU_adder\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/ALU_adder.v\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/ALU_adder.sv\n ALU_adder\n ALU_adder.v\n ALU_adder.sv\n obj_dir/ALU_adder\n obj_dir/ALU_adder.v\n obj_dir/ALU_adder.sv\n%Error: data/full_repos/permissive/95875066/pipeline_processor/ALU.v:16: Cannot find file containing module: 'ALU_Boolean'\nALU_Boolean Logic(A, B, ALUFun[3:1], S2);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/ALU.v:17: Cannot find file containing module: 'ALU_shifter'\nALU_shifter Shift(A[4:0], B[31:0], ALUFun[1:0], S3);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/ALU.v:18: Cannot find file containing module: 'ALU_cmp'\nALU_cmp Cmp(Z, V, N, ALUFun[3:1], S4);\n^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 312,140 | module | module ALU (
input [5:0] ALUFun,
input [31:0] A,
input [31:0] B,
input Sign,
output reg [31:0] S
);
wire Z, V, N;
wire [31:0] S1;
wire [31:0] S2;
wire [31:0] S3;
wire S4;
ALU_adder Add(A, B, ALUFun[0], Sign, Z, V, N, S1);
ALU_Boolean Logic(A, B, ALUFun[3:1], S2);
ALU_shifter Shift(A[4:0], B[31:0], ALUFun[1:0], S3);
ALU_cmp Cmp(Z, V, N, ALUFun[3:1], S4);
always @(*) begin : proc_alu
case (ALUFun[5:4])
2'b00: S = S1;
2'b01: S = S2;
2'b10: S = S3;
2'b11: S = {31'b0, S4};
endcase
end
endmodule | module ALU (
input [5:0] ALUFun,
input [31:0] A,
input [31:0] B,
input Sign,
output reg [31:0] S
); |
wire Z, V, N;
wire [31:0] S1;
wire [31:0] S2;
wire [31:0] S3;
wire S4;
ALU_adder Add(A, B, ALUFun[0], Sign, Z, V, N, S1);
ALU_Boolean Logic(A, B, ALUFun[3:1], S2);
ALU_shifter Shift(A[4:0], B[31:0], ALUFun[1:0], S3);
ALU_cmp Cmp(Z, V, N, ALUFun[3:1], S4);
always @(*) begin : proc_alu
case (ALUFun[5:4])
2'b00: S = S1;
2'b01: S = S2;
2'b10: S = S3;
2'b11: S = {31'b0, S4};
endcase
end
endmodule | 0 |
141,588 | data/full_repos/permissive/95875066/pipeline_processor/ALU_adder.v | 95,875,066 | ALU_adder.v | v | 51 | 75 | [] | [] | [] | [(1, 47)] | null | null | 1: b"%Error: data/full_repos/permissive/95875066/pipeline_processor/ALU_adder.v:24: Cannot find file containing module: 'good_adder'\ngood_adder GA(A, XB, ALUFun0, S);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/good_adder\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/good_adder.v\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/good_adder.sv\n good_adder\n good_adder.v\n good_adder.sv\n obj_dir/good_adder\n obj_dir/good_adder.v\n obj_dir/good_adder.sv\n%Error: Exiting due to 1 error(s)\n" | 312,141 | module | module ALU_adder (
input [31:0] A,
input [31:0] B,
input ALUFun_0,
input Sign,
output Z,
output V,
output N,
output [31:0] S
);
wire [31:0] XB;
wire ALUFun0;
buf BUF(ALUFun0, ALUFun_0);
wire na, nb, ns, ya, yb, ys;
assign XB = B ^ {32{ALUFun0}};
assign Z = ~| (A[31:0] ^ B[31:0]);
good_adder GA(A, XB, ALUFun0, S);
wire V1, V2, V_sign;
nand (V1, A[31], XB[31], ~S[31]);
nand (V2, ~A[31], ~XB[31], S[31]);
nand (V_sign, V1, V2);
assign V = Sign ? V_sign : 0;
wire N1, N2, N3, N_notsign;
nand (N1, ~A[31], B[31]);
nand (N2, B[31], S[31]);
nand (N3, ~A[31], S[31]);
nand (N_notsign, N1, N2, N3);
assign N = Sign ? S[31] : N_notsign;
endmodule | module ALU_adder (
input [31:0] A,
input [31:0] B,
input ALUFun_0,
input Sign,
output Z,
output V,
output N,
output [31:0] S
); |
wire [31:0] XB;
wire ALUFun0;
buf BUF(ALUFun0, ALUFun_0);
wire na, nb, ns, ya, yb, ys;
assign XB = B ^ {32{ALUFun0}};
assign Z = ~| (A[31:0] ^ B[31:0]);
good_adder GA(A, XB, ALUFun0, S);
wire V1, V2, V_sign;
nand (V1, A[31], XB[31], ~S[31]);
nand (V2, ~A[31], ~XB[31], S[31]);
nand (V_sign, V1, V2);
assign V = Sign ? V_sign : 0;
wire N1, N2, N3, N_notsign;
nand (N1, ~A[31], B[31]);
nand (N2, B[31], S[31]);
nand (N3, ~A[31], S[31]);
nand (N_notsign, N1, N2, N3);
assign N = Sign ? S[31] : N_notsign;
endmodule | 0 |
141,589 | data/full_repos/permissive/95875066/pipeline_processor/ALU_Boolean.v | 95,875,066 | ALU_Boolean.v | v | 21 | 31 | [] | [] | [] | [(1, 21)] | null | data/verilator_xmls/ac3935db-a744-4e82-b6fc-567883fa9155.xml | null | 312,142 | module | module ALU_Boolean (
input [31:0] A,
input [31:0] B,
input [2:0] ALUFun,
output reg [31:0] S
);
always @(*) begin : proc_logic
case (ALUFun[2:0])
3'b000: S = ~(A | B);
3'b001: S = 0;
3'b010: S = 0;
3'b011: S = A ^ B;
3'b100: S = A & B;
3'b101: S = A;
3'b110: S = 0;
3'b111: S = A | B;
endcase
end
endmodule | module ALU_Boolean (
input [31:0] A,
input [31:0] B,
input [2:0] ALUFun,
output reg [31:0] S
); |
always @(*) begin : proc_logic
case (ALUFun[2:0])
3'b000: S = ~(A | B);
3'b001: S = 0;
3'b010: S = 0;
3'b011: S = A ^ B;
3'b100: S = A & B;
3'b101: S = A;
3'b110: S = 0;
3'b111: S = A | B;
endcase
end
endmodule | 0 |
141,590 | data/full_repos/permissive/95875066/pipeline_processor/ALU_cmp.v | 95,875,066 | ALU_cmp.v | v | 56 | 44 | [] | [] | [] | [(1, 56)] | null | data/verilator_xmls/3a7012da-021e-46d6-bc6e-9fd3b2d7efd4.xml | null | 312,143 | module | module ALU_cmp (
input Z,
input V,
input N,
input [2:0] ALUFun,
output reg S
);
wire S1;
wire S2;
wire S3;
wire S4_1, S4;
wire S5;
wire S6;
assign S1 = Z;
assign S2 = ~Z;
assign S3 = N^V;
assign S4 = N | Z;
assign S5 = N;
assign S6 = ~(N | Z);
always @(*) begin : proc_compare
case (ALUFun)
3'b000: S = S2;
3'b001: S = S1;
3'b010: S = S3;
3'b011: S = 0;
3'b100: S = 0;
3'b101: S = S5;
3'b110: S = S4;
3'b111: S = S6;
endcase
end
endmodule | module ALU_cmp (
input Z,
input V,
input N,
input [2:0] ALUFun,
output reg S
); |
wire S1;
wire S2;
wire S3;
wire S4_1, S4;
wire S5;
wire S6;
assign S1 = Z;
assign S2 = ~Z;
assign S3 = N^V;
assign S4 = N | Z;
assign S5 = N;
assign S6 = ~(N | Z);
always @(*) begin : proc_compare
case (ALUFun)
3'b000: S = S2;
3'b001: S = S1;
3'b010: S = S3;
3'b011: S = 0;
3'b100: S = 0;
3'b101: S = S5;
3'b110: S = S4;
3'b111: S = S6;
endcase
end
endmodule | 0 |
141,591 | data/full_repos/permissive/95875066/pipeline_processor/ALU_shifter.v | 95,875,066 | ALU_shifter.v | v | 62 | 42 | [] | [] | [] | [(1, 62)] | null | data/verilator_xmls/8e0361e1-4562-4873-94d7-72be2ca818be.xml | null | 312,144 | module | module ALU_shifter (
input [4:0] A,
input [31:0] B,
input [1:0] ALUFun,
output reg [31:0] S
);
wire [31:0] W1;
wire [31:0] X1;
wire [31:0] Y1;
wire [31:0] Z1;
wire [31:0] S1;
wire [31:0] W2;
wire [31:0] X2;
wire [31:0] Y2;
wire [31:0] Z2;
wire [31:0] S2;
wire [31:0] W3;
wire [31:0] X3;
wire [31:0] Y3;
wire [31:0] Z3;
wire [31:0] S3;
assign W1 = A[4]?({B[15:0], 16'b0}):B;
assign X1 = A[3]?({W1[23:0], 8'b0}):W1;
assign Y1 = A[2]?({X1[27:0], 4'b0}):X1;
assign Z1 = A[1]?({Y1[29:0], 2'b0}):Y1;
assign S1 = A[0]?({Z1[30:0], 1'b0}):Z1;
wire B31;
buf BUFA(B31, B[31]);
assign W2 = A[4]?{{16{B31}}, B[31:16]}:B;
assign X2 = A[3]?{{8{B31}}, W2[31:8]}:W2;
assign Y2 = A[2]?{{4{B31}}, X2[31:4]}:X2;
assign Z2 = A[1]?{{2{B31}}, Y2[31:2]}:Y2;
assign S2 = A[0]?{{1{B31}}, Z2[31:1]}:Z2;
assign W3 = A[4]?{16'b0, B[31:16]}:B;
assign X3 = A[3]?{8'b0, W3[31:8]}:W3;
assign Y3 = A[2]?{4'b0, X3[31:4]}:X3;
assign Z3 = A[1]?{2'b0, Y3[31:2]}:Y3;
assign S3 = A[0]?{1'b0, Z3[31:1]}:Z3;
always @(*) begin : proc_sel
case (ALUFun[1:0])
2'b00: S = S1;
2'b01: S = S3;
2'b10: S = 0;
2'b11: S = S2;
endcase
end
endmodule | module ALU_shifter (
input [4:0] A,
input [31:0] B,
input [1:0] ALUFun,
output reg [31:0] S
); |
wire [31:0] W1;
wire [31:0] X1;
wire [31:0] Y1;
wire [31:0] Z1;
wire [31:0] S1;
wire [31:0] W2;
wire [31:0] X2;
wire [31:0] Y2;
wire [31:0] Z2;
wire [31:0] S2;
wire [31:0] W3;
wire [31:0] X3;
wire [31:0] Y3;
wire [31:0] Z3;
wire [31:0] S3;
assign W1 = A[4]?({B[15:0], 16'b0}):B;
assign X1 = A[3]?({W1[23:0], 8'b0}):W1;
assign Y1 = A[2]?({X1[27:0], 4'b0}):X1;
assign Z1 = A[1]?({Y1[29:0], 2'b0}):Y1;
assign S1 = A[0]?({Z1[30:0], 1'b0}):Z1;
wire B31;
buf BUFA(B31, B[31]);
assign W2 = A[4]?{{16{B31}}, B[31:16]}:B;
assign X2 = A[3]?{{8{B31}}, W2[31:8]}:W2;
assign Y2 = A[2]?{{4{B31}}, X2[31:4]}:X2;
assign Z2 = A[1]?{{2{B31}}, Y2[31:2]}:Y2;
assign S2 = A[0]?{{1{B31}}, Z2[31:1]}:Z2;
assign W3 = A[4]?{16'b0, B[31:16]}:B;
assign X3 = A[3]?{8'b0, W3[31:8]}:W3;
assign Y3 = A[2]?{4'b0, X3[31:4]}:X3;
assign Z3 = A[1]?{2'b0, Y3[31:2]}:Y3;
assign S3 = A[0]?{1'b0, Z3[31:1]}:Z3;
always @(*) begin : proc_sel
case (ALUFun[1:0])
2'b00: S = S1;
2'b01: S = S3;
2'b10: S = 0;
2'b11: S = S2;
endcase
end
endmodule | 0 |
141,592 | data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v | 95,875,066 | CPU_pipeline.v | v | 466 | 109 | [] | [] | [] | [(3, 466)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:167: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'ALUOut_EX\' generates 32 bits.\n : ... In instance CPU_pipeline\n (isBranch_ID_EX && ALUOut_EX)?ConBA_ID_EX:PC_in_J;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:170: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'ALUOut_EX\' generates 32 bits.\n : ... In instance CPU_pipeline\n assign IF_ID_Flush = (IRQ || (isJ_ID != 2\'b0 )|| (isBranch_ID_EX && ALUOut_EX))?1:0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:171: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'ALUOut_EX\' generates 32 bits.\n : ... In instance CPU_pipeline\n assign ID_EX_Flush = (!IRQ && (ID_EX_Flush_Hazard || (isBranch_ID_EX && ALUOut_EX)))?1:0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:185: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Shamt_ID_EX\' generates 5 bits.\n : ... In instance CPU_pipeline\n assign ALU_in1_EX = ALUSrc1_ID_EX?Shamt_ID_EX:ALU_reg_in1_EX;\n ^\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:209: Cannot find file containing module: \'PC\'\n PC i_PC (\n ^~\n ... Looked in:\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/PC\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/PC.v\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:217: Cannot find file containing module: \'Inst_Mem\'\n Inst_Mem IM (\n ^~~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:222: Cannot find file containing module: \'IFtoID\'\n IFtoID i_IFtoID (\n ^~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:242: Cannot find file containing module: \'Control\'\n Control i_CTL (\n ^~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:262: Cannot find file containing module: \'RegFile\'\n RegFile RF (\n ^~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:275: Cannot find file containing module: \'IDtoEX\'\n IDtoEX i_IDtoEX (\n ^~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:322: Cannot find file containing module: \'forward\'\n forward i_forward (\n ^~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:342: Cannot find file containing module: \'ALU\'\n ALU ALU_ (\n ^~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:351: Cannot find file containing module: \'EXtoMEM\'\n EXtoMEM i_EXtoMEM (\n ^~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:379: Cannot find file containing module: \'Data_Mem\'\n Data_Mem DM (\n ^~~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:391: Cannot find file containing module: \'Peripheral\'\n Peripheral PE (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:412: Cannot find file containing module: \'MEMtoWB\'\n MEMtoWB i_MEMtoWB (\n ^~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:434: Cannot find file containing module: \'hazard\'\n hazard i_hazard (\n ^~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:448: Cannot find file containing module: \'uart_rx\'\n uart_rx i_uart_rx (\n ^~~~~~~\n%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline.v:457: Cannot find file containing module: \'uart_tx\'\n uart_tx i_uart_tx (\n ^~~~~~~\n%Error: Exiting due to 15 error(s), 4 warning(s)\n' | 312,146 | module | module CPU_pipeline (
input reset ,
input clk ,
input [ 7:0] switch ,
input UART_RX,
output [ 7:0] led ,
output [11:0] digi ,
output UART_TX
);
wire TX_EN ;
wire [7:0] RX_DATA ;
wire [7:0] TX_DATA ;
wire TX_STATUS;
wire RX_STATUS;
wire IRQ ;
wire [31:0] PC_in ;
wire IF_ID_Wr ;
wire ID_EX_Flush ;
wire IF_ID_Flush ;
wire PCWr ;
wire [31:0] PC_in_J ;
wire ID_EX_Flush_Hazard;
wire [31:0] Instruction_IF;
wire [31:0] PC_IF ;
wire [31:0] PC_plus4_IF;
wire [1:0] RegDst_ID ;
wire RegWr_ID ;
wire ALUSrc1_ID ;
wire ALUSrc2_ID ;
wire [5:0] ALUFun_ID ;
wire Sign_ID ;
wire MemWr_ID ;
wire MemRd_ID ;
wire [1:0] MemToReg_ID;
wire EXTOp_ID ;
wire LUOp_ID ;
wire [1:0] isJ_ID ;
wire isBranch_ID;
wire [31:0] Instruction_IF_ID;
wire [31:0] PC_plus4_IF_ID ;
wire [31:0] PC_IF_ID ;
wire [15:0] Imm16_IF_ID ;
wire [ 4:0] Shamt_IF_ID ;
wire [ 4:0] RegisterRd_IF_ID ;
wire [ 4:0] RegisterRt_IF_ID ;
wire [ 4:0] RegisterRs_IF_ID ;
wire [25:0] JT_IF_ID ;
wire [31:0] EXTOut_ID ;
wire [31:0] LUOut_ID ;
wire [31:0] ConBA_ID ;
wire [31:0] JTplusPC_ID;
wire [31:0] PC_plus4_IF_ID_IRQ;
wire RegWr_ID_IRQ ;
wire [ 1:0] RegDst_ID_IRQ ;
wire [ 1:0] MemToReg_ID_IRQ ;
wire [31:0] DataBus_A_ID;
wire [31:0] DataBus_B_ID;
wire [31:0] PC_plus4_ID_EX ;
wire [ 4:0] RegisterRs_ID_EX;
wire [ 4:0] RegisterRt_ID_EX;
wire [ 5:0] ALUFun_ID_EX ;
wire ALUSrc1_ID_EX ;
wire ALUSrc2_ID_EX ;
wire [31:0] DataBus_A_ID_EX ;
wire [31:0] DataBus_B_ID_EX ;
wire Sign_ID_EX ;
wire [31:0] LUOut_ID_EX ;
wire [ 4:0] Shamt_ID_EX ;
wire MemRd_ID_EX ;
wire MemWr_ID_EX ;
wire RegWr_ID_EX ;
wire [ 1:0] MemToReg_ID_EX ;
wire [ 4:0] RegisterRd_ID_EX;
wire [ 1:0] RegDst_ID_EX ;
wire isBranch_ID_EX ;
wire [31:0] ConBA_ID_EX ;
wire [ 1:0] isJ_ID_EX ;
wire [ 1:0] ForwardA ;
wire [ 1:0] ForwardB ;
wire ForwardMEM ;
wire [31:0] ALUOut_EX ;
wire [31:0] ALU_in1_EX ;
wire [31:0] ALU_in2_EX ;
wire [31:0] ALU_reg_in1_EX;
wire [31:0] ALU_reg_in2_EX;
wire [31:0] PC_plus4_EX_MEM ;
wire [ 4:0] RegisterRt_EX_MEM;
wire MemWr_EX_MEM ;
wire MemRd_EX_MEM ;
wire [31:0] DataBus_B_EX_MEM ;
wire [31:0] ALUOut_EX_MEM ;
wire [ 1:0] RegDst_EX_MEM ;
wire RegWr_EX_MEM ;
wire [ 1:0] MemToReg_EX_MEM ;
wire [ 4:0] RegisterRd_EX_MEM;
wire [31:0] Data_Mem_Out_MEM;
wire [31:0] Data_PE_Out_MEM ;
wire [31:0] Data_Out_MEM;
wire [ 4:0] RegisterRd_MEM_WB;
wire [ 4:0] RegisterRt_MEM_WB;
wire [31:0] PC_plus4_MEM_WB ;
wire [31:0] ALUOut_MEM_WB ;
wire [ 1:0] MemtoReg_MEM_WB ;
wire [ 1:0] RegDst_MEM_WB ;
wire RegWr_MEM_WB ;
wire [31:0] Data_Out_MEM_WB ;
wire isBranch_EX_MEM ;
wire [ 4:0] Address_dest_WB;
wire [31:0] DataBus_C_WB ;
assign PC_in_J = (isJ_ID == 2'b01)?JTplusPC_ID:
(isJ_ID == 2'b10)?DataBus_A_ID:
PC_plus4_IF;
assign PC_in = IRQ? 32'h80000004:
(isBranch_ID_EX && ALUOut_EX)?ConBA_ID_EX:PC_in_J;
assign IF_ID_Flush = (IRQ || (isJ_ID != 2'b0 )|| (isBranch_ID_EX && ALUOut_EX))?1:0;
assign ID_EX_Flush = (!IRQ && (ID_EX_Flush_Hazard || (isBranch_ID_EX && ALUOut_EX)))?1:0;
assign PC_plus4_IF = {PC_IF[31], PC_IF[30:0]+31'h00000004};
assign LUOut_ID = LUOp_ID? {Imm16_IF_ID, 16'b0}: EXTOut_ID;
assign EXTOut_ID = EXTOp_ID? {{16{Imm16_IF_ID[15]}}, Imm16_IF_ID}:
{16'b0, Imm16_IF_ID};
assign ConBA_ID = PC_plus4_IF_ID + {EXTOut_ID[29:0], 2'b00};
assign JTplusPC_ID = {PC_IF_ID[31:28], JT_IF_ID, 2'b0};
assign ALU_reg_in1_EX = (ForwardA==2'b01)?((MemtoReg_MEM_WB==2'b01)?Data_Out_MEM_WB:ALUOut_MEM_WB):
(ForwardA==2'b10)?ALUOut_EX_MEM:DataBus_A_ID_EX;
assign ALU_reg_in2_EX = (ForwardB==2'b01)?((MemtoReg_MEM_WB==2'b01)?Data_Out_MEM_WB:ALUOut_MEM_WB):
(ForwardB==2'b10)?ALUOut_EX_MEM:DataBus_B_ID_EX;
assign ALU_in1_EX = ALUSrc1_ID_EX?Shamt_ID_EX:ALU_reg_in1_EX;
assign ALU_in2_EX = ALUSrc2_ID_EX?LUOut_ID_EX:ALU_reg_in2_EX;
assign Data_Out_MEM = ALUOut_EX_MEM[30]?Data_PE_Out_MEM:Data_Mem_Out_MEM;
assign Address_dest_WB = (RegDst_MEM_WB == 2'b00)?RegisterRd_MEM_WB:
(RegDst_MEM_WB == 2'b01)?RegisterRt_MEM_WB:
(RegDst_MEM_WB == 2'b10)?5'b11111:5'b11010;
assign DataBus_C_WB = (MemtoReg_MEM_WB == 2'b00)?ALUOut_MEM_WB:
(MemtoReg_MEM_WB == 2'b01)?Data_Out_MEM_WB:
(MemtoReg_MEM_WB == 2'b10)?PC_plus4_MEM_WB:0;
assign PC_plus4_IF_ID_IRQ = (IRQ && isBranch_EX_MEM)?PC_plus4_EX_MEM:
(IRQ && (isBranch_ID_EX || isJ_ID_EX == 2'b01 || isJ_ID_EX == 2'b10))?PC_plus4_ID_EX:
PC_plus4_IF_ID;
assign RegDst_ID_IRQ = IRQ?2'b11:RegDst_ID;
assign RegWr_ID_IRQ = IRQ?1'b1:RegWr_ID;
assign MemToReg_ID_IRQ = IRQ?2'b10:MemToReg_ID;
PC i_PC (
.PCWr (PCWr ),
.reset(reset),
.clk (clk ),
.PC_in(PC_in),
.PC (PC_IF)
);
Inst_Mem IM (
.addr(PC_IF ),
.data(Instruction_IF)
);
IFtoID i_IFtoID (
.clk (clk ),
.reset (reset ),
.IF_ID_Wr (IF_ID_Wr ),
.IF_ID_Flush (IF_ID_Flush ),
.Instruction (Instruction_IF ),
.PC_plus4 (PC_plus4_IF ),
.Instruction_out (Instruction_IF_ID),
.PC_plus4_out (PC_plus4_IF_ID ),
.PC_in (PC_IF ),
.PC_out (PC_IF_ID ),
.Imm16_IF_ID (Imm16_IF_ID ),
.Shamt_IF_ID (Shamt_IF_ID ),
.RegisterRd_IF_ID(RegisterRd_IF_ID ),
.RegisterRt_IF_ID(RegisterRt_IF_ID ),
.RegisterRs_IF_ID(RegisterRs_IF_ID ),
.JT_IF_ID (JT_IF_ID )
);
Control i_CTL (
.IRQ (IRQ ),
.Instruction(Instruction_IF_ID),
.RegDst (RegDst_ID ),
.RegWr (RegWr_ID ),
.ALUSrc1 (ALUSrc1_ID ),
.ALUSrc2 (ALUSrc2_ID ),
.ALUFun (ALUFun_ID ),
.Sign (Sign_ID ),
.MemWr (MemWr_ID ),
.MemRd (MemRd_ID ),
.MemToReg (MemToReg_ID ),
.EXTOp (EXTOp_ID ),
.LUOp (LUOp_ID ),
.isJ (isJ_ID ),
.isBranch (isBranch_ID )
);
RegFile RF (
.reset(reset ),
.clk (clk ),
.wr (RegWr_MEM_WB ),
.addr1(RegisterRs_IF_ID),
.addr2(RegisterRt_IF_ID),
.addr3(Address_dest_WB ),
.data3(DataBus_C_WB ),
.data1(DataBus_A_ID ),
.data2(DataBus_B_ID )
);
IDtoEX i_IDtoEX (
.clk (clk ),
.reset (reset ),
.ID_EX_Flush (ID_EX_Flush ),
.PC_plus4 (PC_plus4_IF_ID_IRQ),
.PC_plus4_out (PC_plus4_ID_EX ),
.RegisterRs (RegisterRs_IF_ID ),
.RegisterRt (RegisterRt_IF_ID ),
.ALUFun (ALUFun_ID ),
.ALUSrc1 (ALUSrc1_ID ),
.ALUSrc2 (ALUSrc2_ID ),
.DataBus_A (DataBus_A_ID ),
.DataBus_B (DataBus_B_ID ),
.Sign (Sign_ID ),
.Immediate (LUOut_ID ),
.Shamt (Shamt_IF_ID ),
.RegisterRs_out(RegisterRs_ID_EX ),
.RegisterRt_out(RegisterRt_ID_EX ),
.ALUFun_out (ALUFun_ID_EX ),
.ALUSrc1_out (ALUSrc1_ID_EX ),
.ALUSrc2_out (ALUSrc2_ID_EX ),
.DataBus_A_out (DataBus_A_ID_EX ),
.DataBus_B_out (DataBus_B_ID_EX ),
.Sign_out (Sign_ID_EX ),
.Immediate_out (LUOut_ID_EX ),
.Shamt_out (Shamt_ID_EX ),
.MemWr (MemWr_ID ),
.MemRd (MemRd_ID ),
.MemRd_out (MemRd_ID_EX ),
.MemWr_out (MemWr_ID_EX ),
.RegWr (RegWr_ID_IRQ ),
.RegisterRd (RegisterRd_IF_ID ),
.RegDst (RegDst_ID_IRQ ),
.MemToReg (MemToReg_ID_IRQ ),
.RegWr_out (RegWr_ID_EX ),
.MemToReg_out (MemToReg_ID_EX ),
.RegisterRd_out(RegisterRd_ID_EX ),
.RegDst_out (RegDst_ID_EX ),
.isBranch (isBranch_ID ),
.isBranch_out (isBranch_ID_EX ),
.ConBA (ConBA_ID ),
.ConBA_ID_EX (ConBA_ID_EX ),
.isJ (isJ_ID ),
.isJ_out (isJ_ID_EX )
);
forward i_forward (
.RegWr_EX_MEM (RegWr_EX_MEM ),
.RegisterRd_EX_MEM(RegisterRd_EX_MEM),
.RegisterRt_ID_EX (RegisterRt_ID_EX ),
.RegisterRs_ID_EX (RegisterRs_ID_EX ),
.RegWr_MEM_WB (RegWr_MEM_WB ),
.RegisterRd_MEM_WB(RegisterRd_MEM_WB),
.MemtoReg_MEM_WB (MemtoReg_MEM_WB ),
.MemWr_EX_MEM (MemWr_EX_MEM ),
.RegisterRt_EX_MEM(RegisterRt_EX_MEM),
.RegDst_MEM_WB (RegDst_MEM_WB ),
.RegDst_EX_MEM (RegDst_EX_MEM ),
.RegisterRt_MEM_WB(RegisterRt_MEM_WB),
.ForwardA (ForwardA ),
.ForwardB (ForwardB ),
.ForwardMEM (ForwardMEM )
);
ALU ALU_ (
.ALUFun(ALUFun_ID_EX),
.A (ALU_in1_EX ),
.B (ALU_in2_EX ),
.Sign (Sign_ID_EX ),
.S (ALUOut_EX )
);
EXtoMEM i_EXtoMEM (
.clk (clk ),
.reset (reset ),
.PC_plus4 (PC_plus4_ID_EX ),
.PC_plus4_out (PC_plus4_EX_MEM ),
.RegisterRt (RegisterRt_ID_EX ),
.RegisterRt_out(RegisterRt_EX_MEM),
.MemWr (MemWr_ID_EX ),
.MemRd (MemRd_ID_EX ),
.DataBus_B (ALU_reg_in2_EX ),
.ALUOut (ALUOut_EX ),
.MemWr_out (MemWr_EX_MEM ),
.MemRd_out (MemRd_EX_MEM ),
.DataBus_B_out (DataBus_B_EX_MEM ),
.ALUOut_out (ALUOut_EX_MEM ),
.RegDst (RegDst_ID_EX ),
.RegWr (RegWr_ID_EX ),
.MemToReg (MemToReg_ID_EX ),
.RegisterRd (RegisterRd_ID_EX ),
.RegDst_out (RegDst_EX_MEM ),
.RegWr_out (RegWr_EX_MEM ),
.MemToReg_out (MemToReg_EX_MEM ),
.RegisterRd_out(RegisterRd_EX_MEM),
.isBranch (isBranch_ID_EX ),
.isBranch_out (isBranch_EX_MEM )
);
Data_Mem DM (
.reset(reset ),
.clk (clk ),
.rd (MemRd_EX_MEM ),
.wr (MemWr_EX_MEM ),
.addr (ALUOut_EX_MEM ),
.rdata(Data_Mem_Out_MEM),
.wdata(DataBus_B_EX_MEM)
);
Peripheral PE (
.reset (reset ),
.clk (clk ),
.rd (MemRd_EX_MEM ),
.wr (MemWr_EX_MEM ),
.addr (ALUOut_EX_MEM ),
.wdata (DataBus_B_EX_MEM),
.RX_STATUS(RX_STATUS ),
.TX_STATUS(TX_STATUS ),
.RX_DATA (RX_DATA ),
.rdata (Data_PE_Out_MEM ),
.led (led ),
.digi (digi ),
.irqout (IRQ ),
.TX_EN (TX_EN ),
.TX_DATA (TX_DATA )
);
MEMtoWB i_MEMtoWB (
.clk (clk ),
.reset (reset ),
.PC_plus4 (PC_plus4_EX_MEM ),
.Data_Mem_Out (Data_Out_MEM ),
.ALUOut (ALUOut_EX_MEM ),
.RegDst (RegDst_EX_MEM ),
.RegWr (RegWr_EX_MEM ),
.MemToReg (MemToReg_EX_MEM ),
.RegisterRd (RegisterRd_EX_MEM),
.RegisterRt (RegisterRt_EX_MEM),
.PC_plus4_out (PC_plus4_MEM_WB ),
.Data_Mem_Out_out(Data_Out_MEM_WB ),
.ALUOut_out (ALUOut_MEM_WB ),
.RegDst_out (RegDst_MEM_WB ),
.RegWr_out (RegWr_MEM_WB ),
.RegisterRd_out (RegisterRd_MEM_WB),
.RegisterRt_out (RegisterRt_MEM_WB),
.MemToReg_out (MemtoReg_MEM_WB )
);
hazard i_hazard (
.MemRd_ID_EX (MemRd_ID_EX ),
.RegisterRt_ID_EX(RegisterRt_ID_EX ),
.RegisterRs_IF_ID(RegisterRs_IF_ID ),
.RegisterRt_IF_ID(RegisterRt_IF_ID ),
.PCWr (PCWr ),
.IF_ID_Wr (IF_ID_Wr ),
.ID_EX_Flush (ID_EX_Flush_Hazard)
);
uart_rx i_uart_rx (
.i_Clock (clk ),
.i_Rx_Serial(UART_RX ),
.o_Rx_DV (RX_STATUS),
.o_Rx_Byte (RX_DATA )
);
uart_tx i_uart_tx (
.i_Clock (clk ),
.i_Tx_DV (TX_EN ),
.i_Tx_Byte (TX_DATA ),
.o_Tx_Active(TX_STATUS),
.o_Tx_Serial(UART_TX ),
.o_Tx_Done ( )
);
endmodule | module CPU_pipeline (
input reset ,
input clk ,
input [ 7:0] switch ,
input UART_RX,
output [ 7:0] led ,
output [11:0] digi ,
output UART_TX
); |
wire TX_EN ;
wire [7:0] RX_DATA ;
wire [7:0] TX_DATA ;
wire TX_STATUS;
wire RX_STATUS;
wire IRQ ;
wire [31:0] PC_in ;
wire IF_ID_Wr ;
wire ID_EX_Flush ;
wire IF_ID_Flush ;
wire PCWr ;
wire [31:0] PC_in_J ;
wire ID_EX_Flush_Hazard;
wire [31:0] Instruction_IF;
wire [31:0] PC_IF ;
wire [31:0] PC_plus4_IF;
wire [1:0] RegDst_ID ;
wire RegWr_ID ;
wire ALUSrc1_ID ;
wire ALUSrc2_ID ;
wire [5:0] ALUFun_ID ;
wire Sign_ID ;
wire MemWr_ID ;
wire MemRd_ID ;
wire [1:0] MemToReg_ID;
wire EXTOp_ID ;
wire LUOp_ID ;
wire [1:0] isJ_ID ;
wire isBranch_ID;
wire [31:0] Instruction_IF_ID;
wire [31:0] PC_plus4_IF_ID ;
wire [31:0] PC_IF_ID ;
wire [15:0] Imm16_IF_ID ;
wire [ 4:0] Shamt_IF_ID ;
wire [ 4:0] RegisterRd_IF_ID ;
wire [ 4:0] RegisterRt_IF_ID ;
wire [ 4:0] RegisterRs_IF_ID ;
wire [25:0] JT_IF_ID ;
wire [31:0] EXTOut_ID ;
wire [31:0] LUOut_ID ;
wire [31:0] ConBA_ID ;
wire [31:0] JTplusPC_ID;
wire [31:0] PC_plus4_IF_ID_IRQ;
wire RegWr_ID_IRQ ;
wire [ 1:0] RegDst_ID_IRQ ;
wire [ 1:0] MemToReg_ID_IRQ ;
wire [31:0] DataBus_A_ID;
wire [31:0] DataBus_B_ID;
wire [31:0] PC_plus4_ID_EX ;
wire [ 4:0] RegisterRs_ID_EX;
wire [ 4:0] RegisterRt_ID_EX;
wire [ 5:0] ALUFun_ID_EX ;
wire ALUSrc1_ID_EX ;
wire ALUSrc2_ID_EX ;
wire [31:0] DataBus_A_ID_EX ;
wire [31:0] DataBus_B_ID_EX ;
wire Sign_ID_EX ;
wire [31:0] LUOut_ID_EX ;
wire [ 4:0] Shamt_ID_EX ;
wire MemRd_ID_EX ;
wire MemWr_ID_EX ;
wire RegWr_ID_EX ;
wire [ 1:0] MemToReg_ID_EX ;
wire [ 4:0] RegisterRd_ID_EX;
wire [ 1:0] RegDst_ID_EX ;
wire isBranch_ID_EX ;
wire [31:0] ConBA_ID_EX ;
wire [ 1:0] isJ_ID_EX ;
wire [ 1:0] ForwardA ;
wire [ 1:0] ForwardB ;
wire ForwardMEM ;
wire [31:0] ALUOut_EX ;
wire [31:0] ALU_in1_EX ;
wire [31:0] ALU_in2_EX ;
wire [31:0] ALU_reg_in1_EX;
wire [31:0] ALU_reg_in2_EX;
wire [31:0] PC_plus4_EX_MEM ;
wire [ 4:0] RegisterRt_EX_MEM;
wire MemWr_EX_MEM ;
wire MemRd_EX_MEM ;
wire [31:0] DataBus_B_EX_MEM ;
wire [31:0] ALUOut_EX_MEM ;
wire [ 1:0] RegDst_EX_MEM ;
wire RegWr_EX_MEM ;
wire [ 1:0] MemToReg_EX_MEM ;
wire [ 4:0] RegisterRd_EX_MEM;
wire [31:0] Data_Mem_Out_MEM;
wire [31:0] Data_PE_Out_MEM ;
wire [31:0] Data_Out_MEM;
wire [ 4:0] RegisterRd_MEM_WB;
wire [ 4:0] RegisterRt_MEM_WB;
wire [31:0] PC_plus4_MEM_WB ;
wire [31:0] ALUOut_MEM_WB ;
wire [ 1:0] MemtoReg_MEM_WB ;
wire [ 1:0] RegDst_MEM_WB ;
wire RegWr_MEM_WB ;
wire [31:0] Data_Out_MEM_WB ;
wire isBranch_EX_MEM ;
wire [ 4:0] Address_dest_WB;
wire [31:0] DataBus_C_WB ;
assign PC_in_J = (isJ_ID == 2'b01)?JTplusPC_ID:
(isJ_ID == 2'b10)?DataBus_A_ID:
PC_plus4_IF;
assign PC_in = IRQ? 32'h80000004:
(isBranch_ID_EX && ALUOut_EX)?ConBA_ID_EX:PC_in_J;
assign IF_ID_Flush = (IRQ || (isJ_ID != 2'b0 )|| (isBranch_ID_EX && ALUOut_EX))?1:0;
assign ID_EX_Flush = (!IRQ && (ID_EX_Flush_Hazard || (isBranch_ID_EX && ALUOut_EX)))?1:0;
assign PC_plus4_IF = {PC_IF[31], PC_IF[30:0]+31'h00000004};
assign LUOut_ID = LUOp_ID? {Imm16_IF_ID, 16'b0}: EXTOut_ID;
assign EXTOut_ID = EXTOp_ID? {{16{Imm16_IF_ID[15]}}, Imm16_IF_ID}:
{16'b0, Imm16_IF_ID};
assign ConBA_ID = PC_plus4_IF_ID + {EXTOut_ID[29:0], 2'b00};
assign JTplusPC_ID = {PC_IF_ID[31:28], JT_IF_ID, 2'b0};
assign ALU_reg_in1_EX = (ForwardA==2'b01)?((MemtoReg_MEM_WB==2'b01)?Data_Out_MEM_WB:ALUOut_MEM_WB):
(ForwardA==2'b10)?ALUOut_EX_MEM:DataBus_A_ID_EX;
assign ALU_reg_in2_EX = (ForwardB==2'b01)?((MemtoReg_MEM_WB==2'b01)?Data_Out_MEM_WB:ALUOut_MEM_WB):
(ForwardB==2'b10)?ALUOut_EX_MEM:DataBus_B_ID_EX;
assign ALU_in1_EX = ALUSrc1_ID_EX?Shamt_ID_EX:ALU_reg_in1_EX;
assign ALU_in2_EX = ALUSrc2_ID_EX?LUOut_ID_EX:ALU_reg_in2_EX;
assign Data_Out_MEM = ALUOut_EX_MEM[30]?Data_PE_Out_MEM:Data_Mem_Out_MEM;
assign Address_dest_WB = (RegDst_MEM_WB == 2'b00)?RegisterRd_MEM_WB:
(RegDst_MEM_WB == 2'b01)?RegisterRt_MEM_WB:
(RegDst_MEM_WB == 2'b10)?5'b11111:5'b11010;
assign DataBus_C_WB = (MemtoReg_MEM_WB == 2'b00)?ALUOut_MEM_WB:
(MemtoReg_MEM_WB == 2'b01)?Data_Out_MEM_WB:
(MemtoReg_MEM_WB == 2'b10)?PC_plus4_MEM_WB:0;
assign PC_plus4_IF_ID_IRQ = (IRQ && isBranch_EX_MEM)?PC_plus4_EX_MEM:
(IRQ && (isBranch_ID_EX || isJ_ID_EX == 2'b01 || isJ_ID_EX == 2'b10))?PC_plus4_ID_EX:
PC_plus4_IF_ID;
assign RegDst_ID_IRQ = IRQ?2'b11:RegDst_ID;
assign RegWr_ID_IRQ = IRQ?1'b1:RegWr_ID;
assign MemToReg_ID_IRQ = IRQ?2'b10:MemToReg_ID;
PC i_PC (
.PCWr (PCWr ),
.reset(reset),
.clk (clk ),
.PC_in(PC_in),
.PC (PC_IF)
);
Inst_Mem IM (
.addr(PC_IF ),
.data(Instruction_IF)
);
IFtoID i_IFtoID (
.clk (clk ),
.reset (reset ),
.IF_ID_Wr (IF_ID_Wr ),
.IF_ID_Flush (IF_ID_Flush ),
.Instruction (Instruction_IF ),
.PC_plus4 (PC_plus4_IF ),
.Instruction_out (Instruction_IF_ID),
.PC_plus4_out (PC_plus4_IF_ID ),
.PC_in (PC_IF ),
.PC_out (PC_IF_ID ),
.Imm16_IF_ID (Imm16_IF_ID ),
.Shamt_IF_ID (Shamt_IF_ID ),
.RegisterRd_IF_ID(RegisterRd_IF_ID ),
.RegisterRt_IF_ID(RegisterRt_IF_ID ),
.RegisterRs_IF_ID(RegisterRs_IF_ID ),
.JT_IF_ID (JT_IF_ID )
);
Control i_CTL (
.IRQ (IRQ ),
.Instruction(Instruction_IF_ID),
.RegDst (RegDst_ID ),
.RegWr (RegWr_ID ),
.ALUSrc1 (ALUSrc1_ID ),
.ALUSrc2 (ALUSrc2_ID ),
.ALUFun (ALUFun_ID ),
.Sign (Sign_ID ),
.MemWr (MemWr_ID ),
.MemRd (MemRd_ID ),
.MemToReg (MemToReg_ID ),
.EXTOp (EXTOp_ID ),
.LUOp (LUOp_ID ),
.isJ (isJ_ID ),
.isBranch (isBranch_ID )
);
RegFile RF (
.reset(reset ),
.clk (clk ),
.wr (RegWr_MEM_WB ),
.addr1(RegisterRs_IF_ID),
.addr2(RegisterRt_IF_ID),
.addr3(Address_dest_WB ),
.data3(DataBus_C_WB ),
.data1(DataBus_A_ID ),
.data2(DataBus_B_ID )
);
IDtoEX i_IDtoEX (
.clk (clk ),
.reset (reset ),
.ID_EX_Flush (ID_EX_Flush ),
.PC_plus4 (PC_plus4_IF_ID_IRQ),
.PC_plus4_out (PC_plus4_ID_EX ),
.RegisterRs (RegisterRs_IF_ID ),
.RegisterRt (RegisterRt_IF_ID ),
.ALUFun (ALUFun_ID ),
.ALUSrc1 (ALUSrc1_ID ),
.ALUSrc2 (ALUSrc2_ID ),
.DataBus_A (DataBus_A_ID ),
.DataBus_B (DataBus_B_ID ),
.Sign (Sign_ID ),
.Immediate (LUOut_ID ),
.Shamt (Shamt_IF_ID ),
.RegisterRs_out(RegisterRs_ID_EX ),
.RegisterRt_out(RegisterRt_ID_EX ),
.ALUFun_out (ALUFun_ID_EX ),
.ALUSrc1_out (ALUSrc1_ID_EX ),
.ALUSrc2_out (ALUSrc2_ID_EX ),
.DataBus_A_out (DataBus_A_ID_EX ),
.DataBus_B_out (DataBus_B_ID_EX ),
.Sign_out (Sign_ID_EX ),
.Immediate_out (LUOut_ID_EX ),
.Shamt_out (Shamt_ID_EX ),
.MemWr (MemWr_ID ),
.MemRd (MemRd_ID ),
.MemRd_out (MemRd_ID_EX ),
.MemWr_out (MemWr_ID_EX ),
.RegWr (RegWr_ID_IRQ ),
.RegisterRd (RegisterRd_IF_ID ),
.RegDst (RegDst_ID_IRQ ),
.MemToReg (MemToReg_ID_IRQ ),
.RegWr_out (RegWr_ID_EX ),
.MemToReg_out (MemToReg_ID_EX ),
.RegisterRd_out(RegisterRd_ID_EX ),
.RegDst_out (RegDst_ID_EX ),
.isBranch (isBranch_ID ),
.isBranch_out (isBranch_ID_EX ),
.ConBA (ConBA_ID ),
.ConBA_ID_EX (ConBA_ID_EX ),
.isJ (isJ_ID ),
.isJ_out (isJ_ID_EX )
);
forward i_forward (
.RegWr_EX_MEM (RegWr_EX_MEM ),
.RegisterRd_EX_MEM(RegisterRd_EX_MEM),
.RegisterRt_ID_EX (RegisterRt_ID_EX ),
.RegisterRs_ID_EX (RegisterRs_ID_EX ),
.RegWr_MEM_WB (RegWr_MEM_WB ),
.RegisterRd_MEM_WB(RegisterRd_MEM_WB),
.MemtoReg_MEM_WB (MemtoReg_MEM_WB ),
.MemWr_EX_MEM (MemWr_EX_MEM ),
.RegisterRt_EX_MEM(RegisterRt_EX_MEM),
.RegDst_MEM_WB (RegDst_MEM_WB ),
.RegDst_EX_MEM (RegDst_EX_MEM ),
.RegisterRt_MEM_WB(RegisterRt_MEM_WB),
.ForwardA (ForwardA ),
.ForwardB (ForwardB ),
.ForwardMEM (ForwardMEM )
);
ALU ALU_ (
.ALUFun(ALUFun_ID_EX),
.A (ALU_in1_EX ),
.B (ALU_in2_EX ),
.Sign (Sign_ID_EX ),
.S (ALUOut_EX )
);
EXtoMEM i_EXtoMEM (
.clk (clk ),
.reset (reset ),
.PC_plus4 (PC_plus4_ID_EX ),
.PC_plus4_out (PC_plus4_EX_MEM ),
.RegisterRt (RegisterRt_ID_EX ),
.RegisterRt_out(RegisterRt_EX_MEM),
.MemWr (MemWr_ID_EX ),
.MemRd (MemRd_ID_EX ),
.DataBus_B (ALU_reg_in2_EX ),
.ALUOut (ALUOut_EX ),
.MemWr_out (MemWr_EX_MEM ),
.MemRd_out (MemRd_EX_MEM ),
.DataBus_B_out (DataBus_B_EX_MEM ),
.ALUOut_out (ALUOut_EX_MEM ),
.RegDst (RegDst_ID_EX ),
.RegWr (RegWr_ID_EX ),
.MemToReg (MemToReg_ID_EX ),
.RegisterRd (RegisterRd_ID_EX ),
.RegDst_out (RegDst_EX_MEM ),
.RegWr_out (RegWr_EX_MEM ),
.MemToReg_out (MemToReg_EX_MEM ),
.RegisterRd_out(RegisterRd_EX_MEM),
.isBranch (isBranch_ID_EX ),
.isBranch_out (isBranch_EX_MEM )
);
Data_Mem DM (
.reset(reset ),
.clk (clk ),
.rd (MemRd_EX_MEM ),
.wr (MemWr_EX_MEM ),
.addr (ALUOut_EX_MEM ),
.rdata(Data_Mem_Out_MEM),
.wdata(DataBus_B_EX_MEM)
);
Peripheral PE (
.reset (reset ),
.clk (clk ),
.rd (MemRd_EX_MEM ),
.wr (MemWr_EX_MEM ),
.addr (ALUOut_EX_MEM ),
.wdata (DataBus_B_EX_MEM),
.RX_STATUS(RX_STATUS ),
.TX_STATUS(TX_STATUS ),
.RX_DATA (RX_DATA ),
.rdata (Data_PE_Out_MEM ),
.led (led ),
.digi (digi ),
.irqout (IRQ ),
.TX_EN (TX_EN ),
.TX_DATA (TX_DATA )
);
MEMtoWB i_MEMtoWB (
.clk (clk ),
.reset (reset ),
.PC_plus4 (PC_plus4_EX_MEM ),
.Data_Mem_Out (Data_Out_MEM ),
.ALUOut (ALUOut_EX_MEM ),
.RegDst (RegDst_EX_MEM ),
.RegWr (RegWr_EX_MEM ),
.MemToReg (MemToReg_EX_MEM ),
.RegisterRd (RegisterRd_EX_MEM),
.RegisterRt (RegisterRt_EX_MEM),
.PC_plus4_out (PC_plus4_MEM_WB ),
.Data_Mem_Out_out(Data_Out_MEM_WB ),
.ALUOut_out (ALUOut_MEM_WB ),
.RegDst_out (RegDst_MEM_WB ),
.RegWr_out (RegWr_MEM_WB ),
.RegisterRd_out (RegisterRd_MEM_WB),
.RegisterRt_out (RegisterRt_MEM_WB),
.MemToReg_out (MemtoReg_MEM_WB )
);
hazard i_hazard (
.MemRd_ID_EX (MemRd_ID_EX ),
.RegisterRt_ID_EX(RegisterRt_ID_EX ),
.RegisterRs_IF_ID(RegisterRs_IF_ID ),
.RegisterRt_IF_ID(RegisterRt_IF_ID ),
.PCWr (PCWr ),
.IF_ID_Wr (IF_ID_Wr ),
.ID_EX_Flush (ID_EX_Flush_Hazard)
);
uart_rx i_uart_rx (
.i_Clock (clk ),
.i_Rx_Serial(UART_RX ),
.o_Rx_DV (RX_STATUS),
.o_Rx_Byte (RX_DATA )
);
uart_tx i_uart_tx (
.i_Clock (clk ),
.i_Tx_DV (TX_EN ),
.i_Tx_Byte (TX_DATA ),
.o_Tx_Active(TX_STATUS),
.o_Tx_Serial(UART_TX ),
.o_Tx_Done ( )
);
endmodule | 0 |
141,593 | data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline_top.v | 95,875,066 | CPU_pipeline_top.v | v | 40 | 30 | [] | [] | [] | [(1, 40)] | null | null | 1: b"%Error: data/full_repos/permissive/95875066/pipeline_processor/CPU_pipeline_top.v:29: Cannot find file containing module: 'CPU_single'\nCPU_single processor(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/CPU_single\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/CPU_single.v\n data/full_repos/permissive/95875066/pipeline_processor,data/full_repos/permissive/95875066/CPU_single.sv\n CPU_single\n CPU_single.v\n CPU_single.sv\n obj_dir/CPU_single\n obj_dir/CPU_single.v\n obj_dir/CPU_single.sv\n%Error: Exiting due to 1 error(s)\n" | 312,147 | module | module CPU_single_cycle_top (
input clk,
input switch,
input UART_RX,
output [7:0] led,
output [11:0] digi,
output UART_TX
);
wire reset = switch;
reg [1:0] counter;
reg div_clk;
initial begin
div_clk = 0;
counter = 0;
end
always @(posedge clk) begin
if(counter == 3) begin
counter <= 0;
div_clk <= ~div_clk;
end
else
counter <= counter + 1;
end
CPU_single processor(
.reset (reset),
.switch(),
.led (led),
.digi (digi),
.clk (div_clk),
.UART_RX(UART_RX),
.UART_TX(UART_TX)
);
endmodule | module CPU_single_cycle_top (
input clk,
input switch,
input UART_RX,
output [7:0] led,
output [11:0] digi,
output UART_TX
); |
wire reset = switch;
reg [1:0] counter;
reg div_clk;
initial begin
div_clk = 0;
counter = 0;
end
always @(posedge clk) begin
if(counter == 3) begin
counter <= 0;
div_clk <= ~div_clk;
end
else
counter <= counter + 1;
end
CPU_single processor(
.reset (reset),
.switch(),
.led (led),
.digi (digi),
.clk (div_clk),
.UART_RX(UART_RX),
.UART_TX(UART_TX)
);
endmodule | 0 |
141,594 | data/full_repos/permissive/95875066/pipeline_processor/Data_Mem.v | 95,875,066 | Data_Mem.v | v | 31 | 74 | [] | [] | [] | [(3, 30)] | null | data/verilator_xmls/f21eca2a-fa52-41e2-a2b0-89e7f48d3de8.xml | null | 312,148 | module | module Data_Mem (
input reset,
input clk,
input rd,
input wr,
input [31:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
parameter RAM_SIZE = 256;
parameter RAM_SIZE_mul_4 = 1024;
(* ram_style = "distributed" *) reg [31:0] RAMDATA [RAM_SIZE-1:0];
assign rdata = (rd && (addr < RAM_SIZE_mul_4))? RAMDATA[addr[9:2]]:32'b0;
integer i;
always@(posedge clk) begin
if(~reset) begin
for (i = 0; i < RAM_SIZE; i=i+1) begin
RAMDATA[i] <= 32'b0;
end
end
if(wr && (addr < RAM_SIZE_mul_4)) RAMDATA[addr[9:2]]<=wdata;
end
endmodule | module Data_Mem (
input reset,
input clk,
input rd,
input wr,
input [31:0] addr,
input [31:0] wdata,
output [31:0] rdata
); |
parameter RAM_SIZE = 256;
parameter RAM_SIZE_mul_4 = 1024;
(* ram_style = "distributed" *) reg [31:0] RAMDATA [RAM_SIZE-1:0];
assign rdata = (rd && (addr < RAM_SIZE_mul_4))? RAMDATA[addr[9:2]]:32'b0;
integer i;
always@(posedge clk) begin
if(~reset) begin
for (i = 0; i < RAM_SIZE; i=i+1) begin
RAMDATA[i] <= 32'b0;
end
end
if(wr && (addr < RAM_SIZE_mul_4)) RAMDATA[addr[9:2]]<=wdata;
end
endmodule | 0 |
141,595 | data/full_repos/permissive/95875066/pipeline_processor/EXtoMEM.v | 95,875,066 | EXtoMEM.v | v | 81 | 37 | [] | [] | [] | [(2, 81)] | null | data/verilator_xmls/9bec72ee-271b-4fa1-8c8d-c3852f40bfc6.xml | null | 312,149 | module | module EXtoMEM(
input clk,
input reset,
input [31:0] PC_plus4,
output reg [31:0]PC_plus4_out,
input isBranch,
output reg isBranch_out,
input [4:0] RegisterRt,
output reg [4:0] RegisterRt_out,
input MemWr,
input MemRd,
input [31:0] DataBus_B,
input [31:0] ALUOut,
output reg MemWr_out,
output reg MemRd_out,
output reg [31:0] DataBus_B_out,
output reg [31:0] ALUOut_out,
input [1:0] RegDst,
input RegWr,
input [1:0] MemToReg,
input [4:0] RegisterRd,
output reg [1:0] RegDst_out,
output reg RegWr_out,
output reg [1:0] MemToReg_out,
output reg [4:0] RegisterRd_out
);
initial begin
PC_plus4_out <= 0;
RegisterRt_out <= 0;
MemWr_out <= 0;
MemRd_out <= 0;
DataBus_B_out <= 0;
ALUOut_out <= 0;
RegDst_out <= 0;
RegWr_out <= 0;
MemToReg_out <= 0;
RegisterRd_out <= 0;
isBranch_out <= 0;
end
always@(posedge clk) begin
if(~reset) begin
MemWr_out <= 0;
RegWr_out <= 0;
MemRd_out <= 0;
end
else begin
PC_plus4_out<=PC_plus4;
RegisterRt_out<=RegisterRt;
isBranch_out <= isBranch;
ALUOut_out<=ALUOut;
MemWr_out<=MemWr;
MemRd_out<=MemRd;
DataBus_B_out<=DataBus_B;
RegDst_out<=RegDst;
RegWr_out<=RegWr;
MemToReg_out<=MemToReg;
RegisterRd_out<=RegisterRd;
end
end
endmodule | module EXtoMEM(
input clk,
input reset,
input [31:0] PC_plus4,
output reg [31:0]PC_plus4_out,
input isBranch,
output reg isBranch_out,
input [4:0] RegisterRt,
output reg [4:0] RegisterRt_out,
input MemWr,
input MemRd,
input [31:0] DataBus_B,
input [31:0] ALUOut,
output reg MemWr_out,
output reg MemRd_out,
output reg [31:0] DataBus_B_out,
output reg [31:0] ALUOut_out,
input [1:0] RegDst,
input RegWr,
input [1:0] MemToReg,
input [4:0] RegisterRd,
output reg [1:0] RegDst_out,
output reg RegWr_out,
output reg [1:0] MemToReg_out,
output reg [4:0] RegisterRd_out
); |
initial begin
PC_plus4_out <= 0;
RegisterRt_out <= 0;
MemWr_out <= 0;
MemRd_out <= 0;
DataBus_B_out <= 0;
ALUOut_out <= 0;
RegDst_out <= 0;
RegWr_out <= 0;
MemToReg_out <= 0;
RegisterRd_out <= 0;
isBranch_out <= 0;
end
always@(posedge clk) begin
if(~reset) begin
MemWr_out <= 0;
RegWr_out <= 0;
MemRd_out <= 0;
end
else begin
PC_plus4_out<=PC_plus4;
RegisterRt_out<=RegisterRt;
isBranch_out <= isBranch;
ALUOut_out<=ALUOut;
MemWr_out<=MemWr;
MemRd_out<=MemRd;
DataBus_B_out<=DataBus_B;
RegDst_out<=RegDst;
RegWr_out<=RegWr;
MemToReg_out<=MemToReg;
RegisterRd_out<=RegisterRd;
end
end
endmodule | 0 |
141,596 | data/full_repos/permissive/95875066/pipeline_processor/forward.v | 95,875,066 | forward.v | v | 57 | 116 | [] | [] | [] | [(1, 57)] | null | data/verilator_xmls/1f202e47-1164-444c-88fd-d01addda7a3f.xml | null | 312,150 | module | module forward (
input RegWr_EX_MEM ,
input [4:0] RegisterRd_EX_MEM,
input [4:0] RegisterRt_ID_EX ,
input [4:0] RegisterRs_ID_EX ,
input RegWr_MEM_WB ,
input [4:0] RegisterRd_MEM_WB,
input [1:0] RegDst_MEM_WB,
input [1:0] RegDst_EX_MEM,
input [1:0] MemtoReg_MEM_WB ,
input MemWr_EX_MEM ,
input [4:0] RegisterRt_EX_MEM,
input [4:0] RegisterRt_MEM_WB,
output [1:0] ForwardA ,
output [1:0] ForwardB ,
output ForwardMEM
);
assign ForwardA = (RegWr_EX_MEM &&
(((RegDst_EX_MEM == 2'b0) && (RegisterRd_EX_MEM != 5'b0) && (RegisterRd_EX_MEM == RegisterRs_ID_EX))
|| ((RegDst_EX_MEM == 2'b01) && (RegisterRt_EX_MEM != 5'b0) && (RegisterRt_EX_MEM == RegisterRs_ID_EX))))? 2'b10:
(RegWr_MEM_WB &&
(((RegDst_MEM_WB == 2'b0) && (RegisterRd_MEM_WB != 5'b0) && (RegisterRd_MEM_WB == RegisterRs_ID_EX))
|| ((RegDst_MEM_WB == 2'b01) && (RegisterRt_MEM_WB != 5'b0) && (RegisterRt_MEM_WB == RegisterRs_ID_EX))))? 2'b01:
2'b00;
assign ForwardB = (RegWr_EX_MEM &&
(((RegDst_EX_MEM == 2'b0) && (RegisterRd_EX_MEM != 5'b0) && (RegisterRd_EX_MEM == RegisterRt_ID_EX))
|| ((RegDst_EX_MEM == 2'b01) && (RegisterRt_EX_MEM != 5'b0) && (RegisterRt_EX_MEM == RegisterRt_ID_EX))))? 2'b10:
(RegWr_MEM_WB &&
(((RegDst_MEM_WB == 2'b0) && (RegisterRd_MEM_WB != 5'b0) && (RegisterRd_MEM_WB == RegisterRt_ID_EX))
|| ((RegDst_MEM_WB == 2'b01) && (RegisterRt_MEM_WB != 5'b0) && (RegisterRt_MEM_WB == RegisterRt_ID_EX))))? 2'b01:
2'b00;
assign ForwardMEM = ((MemtoReg_MEM_WB == 2'b01) && MemWr_EX_MEM && (RegisterRt_MEM_WB == RegisterRt_EX_MEM))?1:0;
endmodule | module forward (
input RegWr_EX_MEM ,
input [4:0] RegisterRd_EX_MEM,
input [4:0] RegisterRt_ID_EX ,
input [4:0] RegisterRs_ID_EX ,
input RegWr_MEM_WB ,
input [4:0] RegisterRd_MEM_WB,
input [1:0] RegDst_MEM_WB,
input [1:0] RegDst_EX_MEM,
input [1:0] MemtoReg_MEM_WB ,
input MemWr_EX_MEM ,
input [4:0] RegisterRt_EX_MEM,
input [4:0] RegisterRt_MEM_WB,
output [1:0] ForwardA ,
output [1:0] ForwardB ,
output ForwardMEM
); |
assign ForwardA = (RegWr_EX_MEM &&
(((RegDst_EX_MEM == 2'b0) && (RegisterRd_EX_MEM != 5'b0) && (RegisterRd_EX_MEM == RegisterRs_ID_EX))
|| ((RegDst_EX_MEM == 2'b01) && (RegisterRt_EX_MEM != 5'b0) && (RegisterRt_EX_MEM == RegisterRs_ID_EX))))? 2'b10:
(RegWr_MEM_WB &&
(((RegDst_MEM_WB == 2'b0) && (RegisterRd_MEM_WB != 5'b0) && (RegisterRd_MEM_WB == RegisterRs_ID_EX))
|| ((RegDst_MEM_WB == 2'b01) && (RegisterRt_MEM_WB != 5'b0) && (RegisterRt_MEM_WB == RegisterRs_ID_EX))))? 2'b01:
2'b00;
assign ForwardB = (RegWr_EX_MEM &&
(((RegDst_EX_MEM == 2'b0) && (RegisterRd_EX_MEM != 5'b0) && (RegisterRd_EX_MEM == RegisterRt_ID_EX))
|| ((RegDst_EX_MEM == 2'b01) && (RegisterRt_EX_MEM != 5'b0) && (RegisterRt_EX_MEM == RegisterRt_ID_EX))))? 2'b10:
(RegWr_MEM_WB &&
(((RegDst_MEM_WB == 2'b0) && (RegisterRd_MEM_WB != 5'b0) && (RegisterRd_MEM_WB == RegisterRt_ID_EX))
|| ((RegDst_MEM_WB == 2'b01) && (RegisterRt_MEM_WB != 5'b0) && (RegisterRt_MEM_WB == RegisterRt_ID_EX))))? 2'b01:
2'b00;
assign ForwardMEM = ((MemtoReg_MEM_WB == 2'b01) && MemWr_EX_MEM && (RegisterRt_MEM_WB == RegisterRt_EX_MEM))?1:0;
endmodule | 0 |
141,597 | data/full_repos/permissive/95875066/pipeline_processor/good_adder.v | 95,875,066 | good_adder.v | v | 180 | 174 | [] | [] | [] | [(2, 9), (11, 18), (21, 44), (50, 63), (67, 78), (82, 180)] | null | data/verilator_xmls/38465416-1d78-4be2-ae3c-58fdb1cf0e10.xml | null | 312,151 | module | module oai21 (
input a1,
input a2,
input b,
output c
);
assign c = ~ ((a1 | a2) & b);
endmodule | module oai21 (
input a1,
input a2,
input b,
output c
); |
assign c = ~ ((a1 | a2) & b);
endmodule | 0 |
141,598 | data/full_repos/permissive/95875066/pipeline_processor/good_adder.v | 95,875,066 | good_adder.v | v | 180 | 174 | [] | [] | [] | [(2, 9), (11, 18), (21, 44), (50, 63), (67, 78), (82, 180)] | null | data/verilator_xmls/38465416-1d78-4be2-ae3c-58fdb1cf0e10.xml | null | 312,151 | module | module aoi21 (
input a1,
input a2,
input b,
output c
);
assign c = ~((a1 & a2) | b );
endmodule | module aoi21 (
input a1,
input a2,
input b,
output c
); |
assign c = ~((a1 & a2) | b );
endmodule | 0 |
141,599 | data/full_repos/permissive/95875066/pipeline_processor/good_adder.v | 95,875,066 | good_adder.v | v | 180 | 174 | [] | [] | [] | [(2, 9), (11, 18), (21, 44), (50, 63), (67, 78), (82, 180)] | null | data/verilator_xmls/38465416-1d78-4be2-ae3c-58fdb1cf0e10.xml | null | 312,151 | module | module adder_module_A (
input i_bit1,
input i_bit2,
input i_carry,
output o_sum,
output o_ng,
output o_np
);
wire nbit1, nbit2, nc, a, b1, b2;
not (nbit1, i_bit1);
not (nbit2, i_bit2);
not (nc, i_carry);
nor (o_np, i_bit1, i_bit2);
nand (o_ng, i_bit1, i_bit2);
wire x1, x2, x3, x4;
nand (x1, i_bit1, nbit2, nc);
nand (x2, nbit1, i_bit2, nc);
nand (x3, nbit1, nbit2, i_carry);
nand (x4, i_bit1, i_bit2, i_carry);
nand (o_sum, x1, x2, x3, x4);
endmodule | module adder_module_A (
input i_bit1,
input i_bit2,
input i_carry,
output o_sum,
output o_ng,
output o_np
); |
wire nbit1, nbit2, nc, a, b1, b2;
not (nbit1, i_bit1);
not (nbit2, i_bit2);
not (nc, i_carry);
nor (o_np, i_bit1, i_bit2);
nand (o_ng, i_bit1, i_bit2);
wire x1, x2, x3, x4;
nand (x1, i_bit1, nbit2, nc);
nand (x2, nbit1, i_bit2, nc);
nand (x3, nbit1, nbit2, i_carry);
nand (x4, i_bit1, i_bit2, i_carry);
nand (o_sum, x1, x2, x3, x4);
endmodule | 0 |
141,600 | data/full_repos/permissive/95875066/pipeline_processor/good_adder.v | 95,875,066 | good_adder.v | v | 180 | 174 | [] | [] | [] | [(2, 9), (11, 18), (21, 44), (50, 63), (67, 78), (82, 180)] | null | data/verilator_xmls/38465416-1d78-4be2-ae3c-58fdb1cf0e10.xml | null | 312,151 | module | module adder_module_B_type_1 (
input i_ng1, i_ng2,
input i_np1, i_np2,
input i_ncarry,
output o_carry1, o_carry2,
output o_g3, o_p3
);
nor (o_p3, i_np1, i_np2);
oai21 G1(i_np1, i_ng2, i_ng1, o_g3);
not (o_carry2, i_ncarry);
oai21 G2(i_np2, i_ncarry, i_ng2, o_carry1);
endmodule | module adder_module_B_type_1 (
input i_ng1, i_ng2,
input i_np1, i_np2,
input i_ncarry,
output o_carry1, o_carry2,
output o_g3, o_p3
); |
nor (o_p3, i_np1, i_np2);
oai21 G1(i_np1, i_ng2, i_ng1, o_g3);
not (o_carry2, i_ncarry);
oai21 G2(i_np2, i_ncarry, i_ng2, o_carry1);
endmodule | 0 |
141,601 | data/full_repos/permissive/95875066/pipeline_processor/good_adder.v | 95,875,066 | good_adder.v | v | 180 | 174 | [] | [] | [] | [(2, 9), (11, 18), (21, 44), (50, 63), (67, 78), (82, 180)] | null | data/verilator_xmls/38465416-1d78-4be2-ae3c-58fdb1cf0e10.xml | null | 312,151 | module | module adder_module_B_type_2 (
input i_g1, i_g2,
input i_p1, i_p2,
input i_carry,
output o_ncarry1, o_ncarry2,
output o_ng3, o_np3
);
nand (o_np3, i_p1, i_p2);
aoi21 G12(i_p1, i_g2, i_g1, o_ng3);
not (o_ncarry2, i_carry);
aoi21 G2(i_p2, i_carry, i_g2, o_ncarry1);
endmodule | module adder_module_B_type_2 (
input i_g1, i_g2,
input i_p1, i_p2,
input i_carry,
output o_ncarry1, o_ncarry2,
output o_ng3, o_np3
); |
nand (o_np3, i_p1, i_p2);
aoi21 G12(i_p1, i_g2, i_g1, o_ng3);
not (o_ncarry2, i_carry);
aoi21 G2(i_p2, i_carry, i_g2, o_ncarry1);
endmodule | 0 |
141,602 | data/full_repos/permissive/95875066/pipeline_processor/good_adder.v | 95,875,066 | good_adder.v | v | 180 | 174 | [] | [] | [] | [(2, 9), (11, 18), (21, 44), (50, 63), (67, 78), (82, 180)] | null | data/verilator_xmls/38465416-1d78-4be2-ae3c-58fdb1cf0e10.xml | null | 312,151 | module | module good_adder (
input [31:0] A,
input [31:0] B,
input carry,
output [31:0] S
);
wire [31:0] C;
wire [31:0] G1;
wire [31:0] P1;
adder_module_A A1(.i_bit1(A[0]),.i_bit2(B[0]),.i_carry(C[0]),.o_sum(S[0]),.o_ng(G1[0]),.o_np(P1[0]));
adder_module_A A2(.i_bit1(A[1]),.i_bit2(B[1]),.i_carry(C[1]),.o_sum(S[1]),.o_ng(G1[1]),.o_np(P1[1]));
adder_module_A A3(.i_bit1(A[2]),.i_bit2(B[2]),.i_carry(C[2]),.o_sum(S[2]),.o_ng(G1[2]),.o_np(P1[2]));
adder_module_A A4(.i_bit1(A[3]),.i_bit2(B[3]),.i_carry(C[3]),.o_sum(S[3]),.o_ng(G1[3]),.o_np(P1[3]));
adder_module_A A5(.i_bit1(A[4]),.i_bit2(B[4]),.i_carry(C[4]),.o_sum(S[4]),.o_ng(G1[4]),.o_np(P1[4]));
adder_module_A A6(.i_bit1(A[5]),.i_bit2(B[5]),.i_carry(C[5]),.o_sum(S[5]),.o_ng(G1[5]),.o_np(P1[5]));
adder_module_A A7(.i_bit1(A[6]),.i_bit2(B[6]),.i_carry(C[6]),.o_sum(S[6]),.o_ng(G1[6]),.o_np(P1[6]));
adder_module_A A8(.i_bit1(A[7]),.i_bit2(B[7]),.i_carry(C[7]),.o_sum(S[7]),.o_ng(G1[7]),.o_np(P1[7]));
adder_module_A A9(.i_bit1(A[8]),.i_bit2(B[8]),.i_carry(C[8]),.o_sum(S[8]),.o_ng(G1[8]),.o_np(P1[8]));
adder_module_A A10(.i_bit1(A[9]),.i_bit2(B[9]),.i_carry(C[9]),.o_sum(S[9]),.o_ng(G1[9]),.o_np(P1[9]));
adder_module_A A11(.i_bit1(A[10]),.i_bit2(B[10]),.i_carry(C[10]),.o_sum(S[10]),.o_ng(G1[10]),.o_np(P1[10]));
adder_module_A A12(.i_bit1(A[11]),.i_bit2(B[11]),.i_carry(C[11]),.o_sum(S[11]),.o_ng(G1[11]),.o_np(P1[11]));
adder_module_A A13(.i_bit1(A[12]),.i_bit2(B[12]),.i_carry(C[12]),.o_sum(S[12]),.o_ng(G1[12]),.o_np(P1[12]));
adder_module_A A14(.i_bit1(A[13]),.i_bit2(B[13]),.i_carry(C[13]),.o_sum(S[13]),.o_ng(G1[13]),.o_np(P1[13]));
adder_module_A A15(.i_bit1(A[14]),.i_bit2(B[14]),.i_carry(C[14]),.o_sum(S[14]),.o_ng(G1[14]),.o_np(P1[14]));
adder_module_A A16(.i_bit1(A[15]),.i_bit2(B[15]),.i_carry(C[15]),.o_sum(S[15]),.o_ng(G1[15]),.o_np(P1[15]));
adder_module_A A17(.i_bit1(A[16]),.i_bit2(B[16]),.i_carry(C[16]),.o_sum(S[16]),.o_ng(G1[16]),.o_np(P1[16]));
adder_module_A A18(.i_bit1(A[17]),.i_bit2(B[17]),.i_carry(C[17]),.o_sum(S[17]),.o_ng(G1[17]),.o_np(P1[17]));
adder_module_A A19(.i_bit1(A[18]),.i_bit2(B[18]),.i_carry(C[18]),.o_sum(S[18]),.o_ng(G1[18]),.o_np(P1[18]));
adder_module_A A20(.i_bit1(A[19]),.i_bit2(B[19]),.i_carry(C[19]),.o_sum(S[19]),.o_ng(G1[19]),.o_np(P1[19]));
adder_module_A A21(.i_bit1(A[20]),.i_bit2(B[20]),.i_carry(C[20]),.o_sum(S[20]),.o_ng(G1[20]),.o_np(P1[20]));
adder_module_A A22(.i_bit1(A[21]),.i_bit2(B[21]),.i_carry(C[21]),.o_sum(S[21]),.o_ng(G1[21]),.o_np(P1[21]));
adder_module_A A23(.i_bit1(A[22]),.i_bit2(B[22]),.i_carry(C[22]),.o_sum(S[22]),.o_ng(G1[22]),.o_np(P1[22]));
adder_module_A A24(.i_bit1(A[23]),.i_bit2(B[23]),.i_carry(C[23]),.o_sum(S[23]),.o_ng(G1[23]),.o_np(P1[23]));
adder_module_A A25(.i_bit1(A[24]),.i_bit2(B[24]),.i_carry(C[24]),.o_sum(S[24]),.o_ng(G1[24]),.o_np(P1[24]));
adder_module_A A26(.i_bit1(A[25]),.i_bit2(B[25]),.i_carry(C[25]),.o_sum(S[25]),.o_ng(G1[25]),.o_np(P1[25]));
adder_module_A A27(.i_bit1(A[26]),.i_bit2(B[26]),.i_carry(C[26]),.o_sum(S[26]),.o_ng(G1[26]),.o_np(P1[26]));
adder_module_A A28(.i_bit1(A[27]),.i_bit2(B[27]),.i_carry(C[27]),.o_sum(S[27]),.o_ng(G1[27]),.o_np(P1[27]));
adder_module_A A29(.i_bit1(A[28]),.i_bit2(B[28]),.i_carry(C[28]),.o_sum(S[28]),.o_ng(G1[28]),.o_np(P1[28]));
adder_module_A A30(.i_bit1(A[29]),.i_bit2(B[29]),.i_carry(C[29]),.o_sum(S[29]),.o_ng(G1[29]),.o_np(P1[29]));
adder_module_A A31(.i_bit1(A[30]),.i_bit2(B[30]),.i_carry(C[30]),.o_sum(S[30]),.o_ng(G1[30]),.o_np(P1[30]));
adder_module_A A32(.i_bit1(A[31]),.i_bit2(B[31]),.i_carry(C[31]),.o_sum(S[31]),.o_ng(G1[31]),.o_np(P1[31]));
wire [15:0] G2;
wire [15:0] P2;
wire [15:0] C2;
adder_module_B_type_1 B1_1(.i_ng1(G1[1]), .i_ng2(G1[0]),.i_np1(P1[1]), .i_np2(P1[0]),.i_ncarry(C2[0]),.o_carry1(C[1]), .o_carry2(C[0]),.o_g3(G2[0]), .o_p3(P2[0]));
adder_module_B_type_1 B1_2(.i_ng1(G1[3]), .i_ng2(G1[2]),.i_np1(P1[3]), .i_np2(P1[2]),.i_ncarry(C2[1]),.o_carry1(C[3]), .o_carry2(C[2]),.o_g3(G2[1]), .o_p3(P2[1]));
adder_module_B_type_1 B1_3(.i_ng1(G1[5]), .i_ng2(G1[4]),.i_np1(P1[5]), .i_np2(P1[4]),.i_ncarry(C2[2]),.o_carry1(C[5]), .o_carry2(C[4]),.o_g3(G2[2]), .o_p3(P2[2]));
adder_module_B_type_1 B1_4(.i_ng1(G1[7]), .i_ng2(G1[6]),.i_np1(P1[7]), .i_np2(P1[6]),.i_ncarry(C2[3]),.o_carry1(C[7]), .o_carry2(C[6]),.o_g3(G2[3]), .o_p3(P2[3]));
adder_module_B_type_1 B1_5(.i_ng1(G1[9]), .i_ng2(G1[8]),.i_np1(P1[9]), .i_np2(P1[8]),.i_ncarry(C2[4]),.o_carry1(C[9]), .o_carry2(C[8]),.o_g3(G2[4]), .o_p3(P2[4]));
adder_module_B_type_1 B1_6(.i_ng1(G1[11]), .i_ng2(G1[10]),.i_np1(P1[11]), .i_np2(P1[10]),.i_ncarry(C2[5]),.o_carry1(C[11]), .o_carry2(C[10]),.o_g3(G2[5]), .o_p3(P2[5]));
adder_module_B_type_1 B1_7(.i_ng1(G1[13]), .i_ng2(G1[12]),.i_np1(P1[13]), .i_np2(P1[12]),.i_ncarry(C2[6]),.o_carry1(C[13]), .o_carry2(C[12]),.o_g3(G2[6]), .o_p3(P2[6]));
adder_module_B_type_1 B1_8(.i_ng1(G1[15]), .i_ng2(G1[14]),.i_np1(P1[15]), .i_np2(P1[14]),.i_ncarry(C2[7]),.o_carry1(C[15]), .o_carry2(C[14]),.o_g3(G2[7]), .o_p3(P2[7]));
adder_module_B_type_1 B1_9(.i_ng1(G1[17]), .i_ng2(G1[16]),.i_np1(P1[17]), .i_np2(P1[16]),.i_ncarry(C2[8]),.o_carry1(C[17]), .o_carry2(C[16]),.o_g3(G2[8]), .o_p3(P2[8]));
adder_module_B_type_1 B1_10(.i_ng1(G1[19]), .i_ng2(G1[18]),.i_np1(P1[19]), .i_np2(P1[18]),.i_ncarry(C2[9]),.o_carry1(C[19]), .o_carry2(C[18]),.o_g3(G2[9]), .o_p3(P2[9]));
adder_module_B_type_1 B1_11(.i_ng1(G1[21]), .i_ng2(G1[20]),.i_np1(P1[21]), .i_np2(P1[20]),.i_ncarry(C2[10]),.o_carry1(C[21]), .o_carry2(C[20]),.o_g3(G2[10]), .o_p3(P2[10]));
adder_module_B_type_1 B1_12(.i_ng1(G1[23]), .i_ng2(G1[22]),.i_np1(P1[23]), .i_np2(P1[22]),.i_ncarry(C2[11]),.o_carry1(C[23]), .o_carry2(C[22]),.o_g3(G2[11]), .o_p3(P2[11]));
adder_module_B_type_1 B1_13(.i_ng1(G1[25]), .i_ng2(G1[24]),.i_np1(P1[25]), .i_np2(P1[24]),.i_ncarry(C2[12]),.o_carry1(C[25]), .o_carry2(C[24]),.o_g3(G2[12]), .o_p3(P2[12]));
adder_module_B_type_1 B1_14(.i_ng1(G1[27]), .i_ng2(G1[26]),.i_np1(P1[27]), .i_np2(P1[26]),.i_ncarry(C2[13]),.o_carry1(C[27]), .o_carry2(C[26]),.o_g3(G2[13]), .o_p3(P2[13]));
adder_module_B_type_1 B1_15(.i_ng1(G1[29]), .i_ng2(G1[28]),.i_np1(P1[29]), .i_np2(P1[28]),.i_ncarry(C2[14]),.o_carry1(C[29]), .o_carry2(C[28]),.o_g3(G2[14]), .o_p3(P2[14]));
adder_module_B_type_1 B1_16(.i_ng1(G1[31]), .i_ng2(G1[30]),.i_np1(P1[31]), .i_np2(P1[30]),.i_ncarry(C2[15]),.o_carry1(C[31]), .o_carry2(C[30]),.o_g3(G2[15]), .o_p3(P2[15]));
wire [7:0] G3;
wire [7:0] P3;
wire [7:0] C3;
adder_module_B_type_2 B2_1(.i_g1(G2[1]), .i_g2(G2[0]),.i_p1(P2[1]), .i_p2(P2[0]),.i_carry(C3[0]),.o_ncarry1(C2[1]), .o_ncarry2(C2[0]),.o_ng3(G3[0]), .o_np3(P3[0]));
adder_module_B_type_2 B2_2(.i_g1(G2[3]), .i_g2(G2[2]),.i_p1(P2[3]), .i_p2(P2[2]),.i_carry(C3[1]),.o_ncarry1(C2[3]), .o_ncarry2(C2[2]),.o_ng3(G3[1]), .o_np3(P3[1]));
adder_module_B_type_2 B2_3(.i_g1(G2[5]), .i_g2(G2[4]),.i_p1(P2[5]), .i_p2(P2[4]),.i_carry(C3[2]),.o_ncarry1(C2[5]), .o_ncarry2(C2[4]),.o_ng3(G3[2]), .o_np3(P3[2]));
adder_module_B_type_2 B2_4(.i_g1(G2[7]), .i_g2(G2[6]),.i_p1(P2[7]), .i_p2(P2[6]),.i_carry(C3[3]),.o_ncarry1(C2[7]), .o_ncarry2(C2[6]),.o_ng3(G3[3]), .o_np3(P3[3]));
adder_module_B_type_2 B2_5(.i_g1(G2[9]), .i_g2(G2[8]),.i_p1(P2[9]), .i_p2(P2[8]),.i_carry(C3[4]),.o_ncarry1(C2[9]), .o_ncarry2(C2[8]),.o_ng3(G3[4]), .o_np3(P3[4]));
adder_module_B_type_2 B2_6(.i_g1(G2[11]), .i_g2(G2[10]),.i_p1(P2[11]), .i_p2(P2[10]),.i_carry(C3[5]),.o_ncarry1(C2[11]), .o_ncarry2(C2[10]),.o_ng3(G3[5]), .o_np3(P3[5]));
adder_module_B_type_2 B2_7(.i_g1(G2[13]), .i_g2(G2[12]),.i_p1(P2[13]), .i_p2(P2[12]),.i_carry(C3[6]),.o_ncarry1(C2[13]), .o_ncarry2(C2[12]),.o_ng3(G3[6]), .o_np3(P3[6]));
adder_module_B_type_2 B2_8(.i_g1(G2[15]), .i_g2(G2[14]),.i_p1(P2[15]), .i_p2(P2[14]),.i_carry(C3[7]),.o_ncarry1(C2[15]), .o_ncarry2(C2[14]),.o_ng3(G3[7]), .o_np3(P3[7]));
wire [3:0] G4;
wire [3:0] P4;
wire [3:0] C4;
adder_module_B_type_1 B3_1(.i_ng1(G3[1]), .i_ng2(G3[0]),.i_np1(P3[1]), .i_np2(P3[0]),.i_ncarry(C4[0]),.o_carry1(C3[1]), .o_carry2(C3[0]),.o_g3(G4[0]), .o_p3(P4[0]));
adder_module_B_type_1 B3_2(.i_ng1(G3[3]), .i_ng2(G3[2]),.i_np1(P3[3]), .i_np2(P3[2]),.i_ncarry(C4[1]),.o_carry1(C3[3]), .o_carry2(C3[2]),.o_g3(G4[1]), .o_p3(P4[1]));
adder_module_B_type_1 B3_3(.i_ng1(G3[5]), .i_ng2(G3[4]),.i_np1(P3[5]), .i_np2(P3[4]),.i_ncarry(C4[2]),.o_carry1(C3[5]), .o_carry2(C3[4]),.o_g3(G4[2]), .o_p3(P4[2]));
adder_module_B_type_1 B3_4(.i_ng1(G3[7]), .i_ng2(G3[6]),.i_np1(P3[7]), .i_np2(P3[6]),.i_ncarry(C4[3]),.o_carry1(C3[7]), .o_carry2(C3[6]),.o_g3(G4[3]), .o_p3(P4[3]));
wire [1:0] G5;
wire [1:0] P5;
wire [1:0] C5;
adder_module_B_type_2 B4_1(.i_g1(G4[1]), .i_g2(G4[0]),.i_p1(P4[1]), .i_p2(P4[0]),.i_carry(C5[0]),.o_ncarry1(C4[1]), .o_ncarry2(C4[0]),.o_ng3(G5[0]), .o_np3(P5[0]));
adder_module_B_type_2 B4_2(.i_g1(G4[3]), .i_g2(G4[2]),.i_p1(P4[3]), .i_p2(P4[2]),.i_carry(C5[1]),.o_ncarry1(C4[3]), .o_ncarry2(C4[2]),.o_ng3(G5[1]), .o_np3(P5[1]));
wire ncarry;
not (ncarry, carry);
adder_module_B_type_1 B5_1(.i_ng1(G5[1]), .i_ng2(G5[0]),.i_np1(P5[1]), .i_np2(P5[0]),.i_ncarry(ncarry),.o_carry1(C5[1]), .o_carry2(C5[0]),.o_g3(), .o_p3());
endmodule | module good_adder (
input [31:0] A,
input [31:0] B,
input carry,
output [31:0] S
); |
wire [31:0] C;
wire [31:0] G1;
wire [31:0] P1;
adder_module_A A1(.i_bit1(A[0]),.i_bit2(B[0]),.i_carry(C[0]),.o_sum(S[0]),.o_ng(G1[0]),.o_np(P1[0]));
adder_module_A A2(.i_bit1(A[1]),.i_bit2(B[1]),.i_carry(C[1]),.o_sum(S[1]),.o_ng(G1[1]),.o_np(P1[1]));
adder_module_A A3(.i_bit1(A[2]),.i_bit2(B[2]),.i_carry(C[2]),.o_sum(S[2]),.o_ng(G1[2]),.o_np(P1[2]));
adder_module_A A4(.i_bit1(A[3]),.i_bit2(B[3]),.i_carry(C[3]),.o_sum(S[3]),.o_ng(G1[3]),.o_np(P1[3]));
adder_module_A A5(.i_bit1(A[4]),.i_bit2(B[4]),.i_carry(C[4]),.o_sum(S[4]),.o_ng(G1[4]),.o_np(P1[4]));
adder_module_A A6(.i_bit1(A[5]),.i_bit2(B[5]),.i_carry(C[5]),.o_sum(S[5]),.o_ng(G1[5]),.o_np(P1[5]));
adder_module_A A7(.i_bit1(A[6]),.i_bit2(B[6]),.i_carry(C[6]),.o_sum(S[6]),.o_ng(G1[6]),.o_np(P1[6]));
adder_module_A A8(.i_bit1(A[7]),.i_bit2(B[7]),.i_carry(C[7]),.o_sum(S[7]),.o_ng(G1[7]),.o_np(P1[7]));
adder_module_A A9(.i_bit1(A[8]),.i_bit2(B[8]),.i_carry(C[8]),.o_sum(S[8]),.o_ng(G1[8]),.o_np(P1[8]));
adder_module_A A10(.i_bit1(A[9]),.i_bit2(B[9]),.i_carry(C[9]),.o_sum(S[9]),.o_ng(G1[9]),.o_np(P1[9]));
adder_module_A A11(.i_bit1(A[10]),.i_bit2(B[10]),.i_carry(C[10]),.o_sum(S[10]),.o_ng(G1[10]),.o_np(P1[10]));
adder_module_A A12(.i_bit1(A[11]),.i_bit2(B[11]),.i_carry(C[11]),.o_sum(S[11]),.o_ng(G1[11]),.o_np(P1[11]));
adder_module_A A13(.i_bit1(A[12]),.i_bit2(B[12]),.i_carry(C[12]),.o_sum(S[12]),.o_ng(G1[12]),.o_np(P1[12]));
adder_module_A A14(.i_bit1(A[13]),.i_bit2(B[13]),.i_carry(C[13]),.o_sum(S[13]),.o_ng(G1[13]),.o_np(P1[13]));
adder_module_A A15(.i_bit1(A[14]),.i_bit2(B[14]),.i_carry(C[14]),.o_sum(S[14]),.o_ng(G1[14]),.o_np(P1[14]));
adder_module_A A16(.i_bit1(A[15]),.i_bit2(B[15]),.i_carry(C[15]),.o_sum(S[15]),.o_ng(G1[15]),.o_np(P1[15]));
adder_module_A A17(.i_bit1(A[16]),.i_bit2(B[16]),.i_carry(C[16]),.o_sum(S[16]),.o_ng(G1[16]),.o_np(P1[16]));
adder_module_A A18(.i_bit1(A[17]),.i_bit2(B[17]),.i_carry(C[17]),.o_sum(S[17]),.o_ng(G1[17]),.o_np(P1[17]));
adder_module_A A19(.i_bit1(A[18]),.i_bit2(B[18]),.i_carry(C[18]),.o_sum(S[18]),.o_ng(G1[18]),.o_np(P1[18]));
adder_module_A A20(.i_bit1(A[19]),.i_bit2(B[19]),.i_carry(C[19]),.o_sum(S[19]),.o_ng(G1[19]),.o_np(P1[19]));
adder_module_A A21(.i_bit1(A[20]),.i_bit2(B[20]),.i_carry(C[20]),.o_sum(S[20]),.o_ng(G1[20]),.o_np(P1[20]));
adder_module_A A22(.i_bit1(A[21]),.i_bit2(B[21]),.i_carry(C[21]),.o_sum(S[21]),.o_ng(G1[21]),.o_np(P1[21]));
adder_module_A A23(.i_bit1(A[22]),.i_bit2(B[22]),.i_carry(C[22]),.o_sum(S[22]),.o_ng(G1[22]),.o_np(P1[22]));
adder_module_A A24(.i_bit1(A[23]),.i_bit2(B[23]),.i_carry(C[23]),.o_sum(S[23]),.o_ng(G1[23]),.o_np(P1[23]));
adder_module_A A25(.i_bit1(A[24]),.i_bit2(B[24]),.i_carry(C[24]),.o_sum(S[24]),.o_ng(G1[24]),.o_np(P1[24]));
adder_module_A A26(.i_bit1(A[25]),.i_bit2(B[25]),.i_carry(C[25]),.o_sum(S[25]),.o_ng(G1[25]),.o_np(P1[25]));
adder_module_A A27(.i_bit1(A[26]),.i_bit2(B[26]),.i_carry(C[26]),.o_sum(S[26]),.o_ng(G1[26]),.o_np(P1[26]));
adder_module_A A28(.i_bit1(A[27]),.i_bit2(B[27]),.i_carry(C[27]),.o_sum(S[27]),.o_ng(G1[27]),.o_np(P1[27]));
adder_module_A A29(.i_bit1(A[28]),.i_bit2(B[28]),.i_carry(C[28]),.o_sum(S[28]),.o_ng(G1[28]),.o_np(P1[28]));
adder_module_A A30(.i_bit1(A[29]),.i_bit2(B[29]),.i_carry(C[29]),.o_sum(S[29]),.o_ng(G1[29]),.o_np(P1[29]));
adder_module_A A31(.i_bit1(A[30]),.i_bit2(B[30]),.i_carry(C[30]),.o_sum(S[30]),.o_ng(G1[30]),.o_np(P1[30]));
adder_module_A A32(.i_bit1(A[31]),.i_bit2(B[31]),.i_carry(C[31]),.o_sum(S[31]),.o_ng(G1[31]),.o_np(P1[31]));
wire [15:0] G2;
wire [15:0] P2;
wire [15:0] C2;
adder_module_B_type_1 B1_1(.i_ng1(G1[1]), .i_ng2(G1[0]),.i_np1(P1[1]), .i_np2(P1[0]),.i_ncarry(C2[0]),.o_carry1(C[1]), .o_carry2(C[0]),.o_g3(G2[0]), .o_p3(P2[0]));
adder_module_B_type_1 B1_2(.i_ng1(G1[3]), .i_ng2(G1[2]),.i_np1(P1[3]), .i_np2(P1[2]),.i_ncarry(C2[1]),.o_carry1(C[3]), .o_carry2(C[2]),.o_g3(G2[1]), .o_p3(P2[1]));
adder_module_B_type_1 B1_3(.i_ng1(G1[5]), .i_ng2(G1[4]),.i_np1(P1[5]), .i_np2(P1[4]),.i_ncarry(C2[2]),.o_carry1(C[5]), .o_carry2(C[4]),.o_g3(G2[2]), .o_p3(P2[2]));
adder_module_B_type_1 B1_4(.i_ng1(G1[7]), .i_ng2(G1[6]),.i_np1(P1[7]), .i_np2(P1[6]),.i_ncarry(C2[3]),.o_carry1(C[7]), .o_carry2(C[6]),.o_g3(G2[3]), .o_p3(P2[3]));
adder_module_B_type_1 B1_5(.i_ng1(G1[9]), .i_ng2(G1[8]),.i_np1(P1[9]), .i_np2(P1[8]),.i_ncarry(C2[4]),.o_carry1(C[9]), .o_carry2(C[8]),.o_g3(G2[4]), .o_p3(P2[4]));
adder_module_B_type_1 B1_6(.i_ng1(G1[11]), .i_ng2(G1[10]),.i_np1(P1[11]), .i_np2(P1[10]),.i_ncarry(C2[5]),.o_carry1(C[11]), .o_carry2(C[10]),.o_g3(G2[5]), .o_p3(P2[5]));
adder_module_B_type_1 B1_7(.i_ng1(G1[13]), .i_ng2(G1[12]),.i_np1(P1[13]), .i_np2(P1[12]),.i_ncarry(C2[6]),.o_carry1(C[13]), .o_carry2(C[12]),.o_g3(G2[6]), .o_p3(P2[6]));
adder_module_B_type_1 B1_8(.i_ng1(G1[15]), .i_ng2(G1[14]),.i_np1(P1[15]), .i_np2(P1[14]),.i_ncarry(C2[7]),.o_carry1(C[15]), .o_carry2(C[14]),.o_g3(G2[7]), .o_p3(P2[7]));
adder_module_B_type_1 B1_9(.i_ng1(G1[17]), .i_ng2(G1[16]),.i_np1(P1[17]), .i_np2(P1[16]),.i_ncarry(C2[8]),.o_carry1(C[17]), .o_carry2(C[16]),.o_g3(G2[8]), .o_p3(P2[8]));
adder_module_B_type_1 B1_10(.i_ng1(G1[19]), .i_ng2(G1[18]),.i_np1(P1[19]), .i_np2(P1[18]),.i_ncarry(C2[9]),.o_carry1(C[19]), .o_carry2(C[18]),.o_g3(G2[9]), .o_p3(P2[9]));
adder_module_B_type_1 B1_11(.i_ng1(G1[21]), .i_ng2(G1[20]),.i_np1(P1[21]), .i_np2(P1[20]),.i_ncarry(C2[10]),.o_carry1(C[21]), .o_carry2(C[20]),.o_g3(G2[10]), .o_p3(P2[10]));
adder_module_B_type_1 B1_12(.i_ng1(G1[23]), .i_ng2(G1[22]),.i_np1(P1[23]), .i_np2(P1[22]),.i_ncarry(C2[11]),.o_carry1(C[23]), .o_carry2(C[22]),.o_g3(G2[11]), .o_p3(P2[11]));
adder_module_B_type_1 B1_13(.i_ng1(G1[25]), .i_ng2(G1[24]),.i_np1(P1[25]), .i_np2(P1[24]),.i_ncarry(C2[12]),.o_carry1(C[25]), .o_carry2(C[24]),.o_g3(G2[12]), .o_p3(P2[12]));
adder_module_B_type_1 B1_14(.i_ng1(G1[27]), .i_ng2(G1[26]),.i_np1(P1[27]), .i_np2(P1[26]),.i_ncarry(C2[13]),.o_carry1(C[27]), .o_carry2(C[26]),.o_g3(G2[13]), .o_p3(P2[13]));
adder_module_B_type_1 B1_15(.i_ng1(G1[29]), .i_ng2(G1[28]),.i_np1(P1[29]), .i_np2(P1[28]),.i_ncarry(C2[14]),.o_carry1(C[29]), .o_carry2(C[28]),.o_g3(G2[14]), .o_p3(P2[14]));
adder_module_B_type_1 B1_16(.i_ng1(G1[31]), .i_ng2(G1[30]),.i_np1(P1[31]), .i_np2(P1[30]),.i_ncarry(C2[15]),.o_carry1(C[31]), .o_carry2(C[30]),.o_g3(G2[15]), .o_p3(P2[15]));
wire [7:0] G3;
wire [7:0] P3;
wire [7:0] C3;
adder_module_B_type_2 B2_1(.i_g1(G2[1]), .i_g2(G2[0]),.i_p1(P2[1]), .i_p2(P2[0]),.i_carry(C3[0]),.o_ncarry1(C2[1]), .o_ncarry2(C2[0]),.o_ng3(G3[0]), .o_np3(P3[0]));
adder_module_B_type_2 B2_2(.i_g1(G2[3]), .i_g2(G2[2]),.i_p1(P2[3]), .i_p2(P2[2]),.i_carry(C3[1]),.o_ncarry1(C2[3]), .o_ncarry2(C2[2]),.o_ng3(G3[1]), .o_np3(P3[1]));
adder_module_B_type_2 B2_3(.i_g1(G2[5]), .i_g2(G2[4]),.i_p1(P2[5]), .i_p2(P2[4]),.i_carry(C3[2]),.o_ncarry1(C2[5]), .o_ncarry2(C2[4]),.o_ng3(G3[2]), .o_np3(P3[2]));
adder_module_B_type_2 B2_4(.i_g1(G2[7]), .i_g2(G2[6]),.i_p1(P2[7]), .i_p2(P2[6]),.i_carry(C3[3]),.o_ncarry1(C2[7]), .o_ncarry2(C2[6]),.o_ng3(G3[3]), .o_np3(P3[3]));
adder_module_B_type_2 B2_5(.i_g1(G2[9]), .i_g2(G2[8]),.i_p1(P2[9]), .i_p2(P2[8]),.i_carry(C3[4]),.o_ncarry1(C2[9]), .o_ncarry2(C2[8]),.o_ng3(G3[4]), .o_np3(P3[4]));
adder_module_B_type_2 B2_6(.i_g1(G2[11]), .i_g2(G2[10]),.i_p1(P2[11]), .i_p2(P2[10]),.i_carry(C3[5]),.o_ncarry1(C2[11]), .o_ncarry2(C2[10]),.o_ng3(G3[5]), .o_np3(P3[5]));
adder_module_B_type_2 B2_7(.i_g1(G2[13]), .i_g2(G2[12]),.i_p1(P2[13]), .i_p2(P2[12]),.i_carry(C3[6]),.o_ncarry1(C2[13]), .o_ncarry2(C2[12]),.o_ng3(G3[6]), .o_np3(P3[6]));
adder_module_B_type_2 B2_8(.i_g1(G2[15]), .i_g2(G2[14]),.i_p1(P2[15]), .i_p2(P2[14]),.i_carry(C3[7]),.o_ncarry1(C2[15]), .o_ncarry2(C2[14]),.o_ng3(G3[7]), .o_np3(P3[7]));
wire [3:0] G4;
wire [3:0] P4;
wire [3:0] C4;
adder_module_B_type_1 B3_1(.i_ng1(G3[1]), .i_ng2(G3[0]),.i_np1(P3[1]), .i_np2(P3[0]),.i_ncarry(C4[0]),.o_carry1(C3[1]), .o_carry2(C3[0]),.o_g3(G4[0]), .o_p3(P4[0]));
adder_module_B_type_1 B3_2(.i_ng1(G3[3]), .i_ng2(G3[2]),.i_np1(P3[3]), .i_np2(P3[2]),.i_ncarry(C4[1]),.o_carry1(C3[3]), .o_carry2(C3[2]),.o_g3(G4[1]), .o_p3(P4[1]));
adder_module_B_type_1 B3_3(.i_ng1(G3[5]), .i_ng2(G3[4]),.i_np1(P3[5]), .i_np2(P3[4]),.i_ncarry(C4[2]),.o_carry1(C3[5]), .o_carry2(C3[4]),.o_g3(G4[2]), .o_p3(P4[2]));
adder_module_B_type_1 B3_4(.i_ng1(G3[7]), .i_ng2(G3[6]),.i_np1(P3[7]), .i_np2(P3[6]),.i_ncarry(C4[3]),.o_carry1(C3[7]), .o_carry2(C3[6]),.o_g3(G4[3]), .o_p3(P4[3]));
wire [1:0] G5;
wire [1:0] P5;
wire [1:0] C5;
adder_module_B_type_2 B4_1(.i_g1(G4[1]), .i_g2(G4[0]),.i_p1(P4[1]), .i_p2(P4[0]),.i_carry(C5[0]),.o_ncarry1(C4[1]), .o_ncarry2(C4[0]),.o_ng3(G5[0]), .o_np3(P5[0]));
adder_module_B_type_2 B4_2(.i_g1(G4[3]), .i_g2(G4[2]),.i_p1(P4[3]), .i_p2(P4[2]),.i_carry(C5[1]),.o_ncarry1(C4[3]), .o_ncarry2(C4[2]),.o_ng3(G5[1]), .o_np3(P5[1]));
wire ncarry;
not (ncarry, carry);
adder_module_B_type_1 B5_1(.i_ng1(G5[1]), .i_ng2(G5[0]),.i_np1(P5[1]), .i_np2(P5[0]),.i_ncarry(ncarry),.o_carry1(C5[1]), .o_carry2(C5[0]),.o_g3(), .o_p3());
endmodule | 0 |
141,603 | data/full_repos/permissive/95875066/pipeline_processor/hazard.v | 95,875,066 | hazard.v | v | 28 | 88 | [] | [] | [] | [(1, 28)] | null | data/verilator_xmls/997d3cf8-3a91-40ad-ae22-318f41c1b957.xml | null | 312,152 | module | module hazard (
input MemRd_ID_EX,
input [4:0] RegisterRt_ID_EX,
input [4:0] RegisterRs_IF_ID,
input [4:0] RegisterRt_IF_ID,
output reg PCWr,
output reg IF_ID_Wr,
output reg ID_EX_Flush
);
always @(*) begin : proc_lw_use
if(MemRd_ID_EX &&
(RegisterRt_ID_EX == RegisterRt_IF_ID || RegisterRt_ID_EX == RegisterRs_IF_ID)) begin
PCWr = 0;
IF_ID_Wr = 0;
ID_EX_Flush = 1;
end
else begin
PCWr = 1;
IF_ID_Wr = 1;
ID_EX_Flush = 0;
end
end
endmodule | module hazard (
input MemRd_ID_EX,
input [4:0] RegisterRt_ID_EX,
input [4:0] RegisterRs_IF_ID,
input [4:0] RegisterRt_IF_ID,
output reg PCWr,
output reg IF_ID_Wr,
output reg ID_EX_Flush
); |
always @(*) begin : proc_lw_use
if(MemRd_ID_EX &&
(RegisterRt_ID_EX == RegisterRt_IF_ID || RegisterRt_ID_EX == RegisterRs_IF_ID)) begin
PCWr = 0;
IF_ID_Wr = 0;
ID_EX_Flush = 1;
end
else begin
PCWr = 1;
IF_ID_Wr = 1;
ID_EX_Flush = 0;
end
end
endmodule | 0 |
141,604 | data/full_repos/permissive/95875066/pipeline_processor/IDtoEX.v | 95,875,066 | IDtoEX.v | v | 118 | 36 | [] | [] | [] | [(2, 118)] | null | data/verilator_xmls/512b17ff-33e9-4f42-9104-284eb82c10ec.xml | null | 312,153 | module | module IDtoEX (
input clk ,
input reset ,
input ID_EX_Flush ,
input [31:0] PC_plus4 ,
output reg [31:0] PC_plus4_out ,
input [ 4:0] RegisterRs ,
input [ 4:0] RegisterRt ,
input [ 5:0] ALUFun ,
input ALUSrc1 ,
input ALUSrc2 ,
input [31:0] DataBus_A ,
input [31:0] DataBus_B ,
input Sign ,
input [31:0] Immediate ,
input [ 4:0] Shamt ,
input isBranch ,
input [31:0] ConBA ,
input [1:0] isJ,
output reg [1:0] isJ_out,
output reg isBranch_out ,
output reg [31:0] ConBA_ID_EX ,
output reg [ 4:0] RegisterRs_out,
output reg [ 4:0] RegisterRt_out,
output reg [ 5:0] ALUFun_out ,
output reg ALUSrc1_out ,
output reg ALUSrc2_out ,
output reg [31:0] DataBus_A_out ,
output reg [31:0] DataBus_B_out ,
output reg Sign_out ,
output reg [31:0] Immediate_out ,
output reg [4:0] Shamt_out ,
input MemWr ,
input MemRd ,
output reg MemRd_out ,
output reg MemWr_out ,
input RegWr ,
input [ 4:0] RegisterRd ,
input [ 1:0] RegDst ,
input [ 1:0] MemToReg ,
output reg RegWr_out ,
output reg [ 1:0] MemToReg_out ,
output reg [ 1:0] RegDst_out ,
output reg [ 4:0] RegisterRd_out
);
initial begin
isBranch_out <= 0;
RegisterRs_out <= 0;
RegisterRt_out <= 0;
ALUFun_out <= 0;
ALUSrc1_out <= 0;
ALUSrc2_out <= 0;
DataBus_A_out <= 0;
DataBus_B_out <= 0;
Sign_out <= 0;
Immediate_out <= 0;
Shamt_out <= 0;
RegWr_out <= 0;
MemToReg_out <= 0;
RegDst_out <= 0;
RegisterRd_out <= 0;
MemRd_out <= 0;
MemWr_out <= 0;
PC_plus4_out <= 0;
ConBA_ID_EX <= 0;
isJ_out <= 0;
end
always@(posedge clk) begin
if(~reset || ID_EX_Flush) begin
MemWr_out <= 0;
RegWr_out <= 0;
MemRd_out <= 0;
isBranch_out <= 0;
end
else begin
PC_plus4_out <= PC_plus4;
isBranch_out <= isBranch;
ALUFun_out <= ALUFun;
ALUSrc1_out <= ALUSrc1;
ALUSrc2_out <= ALUSrc2;
DataBus_A_out <= DataBus_A;
DataBus_B_out <= DataBus_B;
Sign_out <= Sign;
RegisterRs_out <= RegisterRs;
RegisterRt_out <= RegisterRt;
Immediate_out <= Immediate;
Shamt_out <= Shamt;
MemWr_out <= MemWr;
MemRd_out <= MemRd;
RegDst_out <= RegDst;
RegWr_out <= RegWr;
MemToReg_out <= MemToReg;
RegisterRd_out <= RegisterRd;
ConBA_ID_EX <= ConBA;
isJ_out <= isJ;
end
end
endmodule | module IDtoEX (
input clk ,
input reset ,
input ID_EX_Flush ,
input [31:0] PC_plus4 ,
output reg [31:0] PC_plus4_out ,
input [ 4:0] RegisterRs ,
input [ 4:0] RegisterRt ,
input [ 5:0] ALUFun ,
input ALUSrc1 ,
input ALUSrc2 ,
input [31:0] DataBus_A ,
input [31:0] DataBus_B ,
input Sign ,
input [31:0] Immediate ,
input [ 4:0] Shamt ,
input isBranch ,
input [31:0] ConBA ,
input [1:0] isJ,
output reg [1:0] isJ_out,
output reg isBranch_out ,
output reg [31:0] ConBA_ID_EX ,
output reg [ 4:0] RegisterRs_out,
output reg [ 4:0] RegisterRt_out,
output reg [ 5:0] ALUFun_out ,
output reg ALUSrc1_out ,
output reg ALUSrc2_out ,
output reg [31:0] DataBus_A_out ,
output reg [31:0] DataBus_B_out ,
output reg Sign_out ,
output reg [31:0] Immediate_out ,
output reg [4:0] Shamt_out ,
input MemWr ,
input MemRd ,
output reg MemRd_out ,
output reg MemWr_out ,
input RegWr ,
input [ 4:0] RegisterRd ,
input [ 1:0] RegDst ,
input [ 1:0] MemToReg ,
output reg RegWr_out ,
output reg [ 1:0] MemToReg_out ,
output reg [ 1:0] RegDst_out ,
output reg [ 4:0] RegisterRd_out
); |
initial begin
isBranch_out <= 0;
RegisterRs_out <= 0;
RegisterRt_out <= 0;
ALUFun_out <= 0;
ALUSrc1_out <= 0;
ALUSrc2_out <= 0;
DataBus_A_out <= 0;
DataBus_B_out <= 0;
Sign_out <= 0;
Immediate_out <= 0;
Shamt_out <= 0;
RegWr_out <= 0;
MemToReg_out <= 0;
RegDst_out <= 0;
RegisterRd_out <= 0;
MemRd_out <= 0;
MemWr_out <= 0;
PC_plus4_out <= 0;
ConBA_ID_EX <= 0;
isJ_out <= 0;
end
always@(posedge clk) begin
if(~reset || ID_EX_Flush) begin
MemWr_out <= 0;
RegWr_out <= 0;
MemRd_out <= 0;
isBranch_out <= 0;
end
else begin
PC_plus4_out <= PC_plus4;
isBranch_out <= isBranch;
ALUFun_out <= ALUFun;
ALUSrc1_out <= ALUSrc1;
ALUSrc2_out <= ALUSrc2;
DataBus_A_out <= DataBus_A;
DataBus_B_out <= DataBus_B;
Sign_out <= Sign;
RegisterRs_out <= RegisterRs;
RegisterRt_out <= RegisterRt;
Immediate_out <= Immediate;
Shamt_out <= Shamt;
MemWr_out <= MemWr;
MemRd_out <= MemRd;
RegDst_out <= RegDst;
RegWr_out <= RegWr;
MemToReg_out <= MemToReg;
RegisterRd_out <= RegisterRd;
ConBA_ID_EX <= ConBA;
isJ_out <= isJ;
end
end
endmodule | 0 |
141,605 | data/full_repos/permissive/95875066/pipeline_processor/IFtoID.v | 95,875,066 | IFtoID.v | v | 57 | 46 | [] | [] | [] | [(2, 57)] | null | data/verilator_xmls/f2acc048-ef99-48a9-9017-3761567256d5.xml | null | 312,154 | module | module IFtoID (
input clk ,
input reset ,
input IF_ID_Wr ,
input IF_ID_Flush ,
input [31:0] PC_in ,
input [31:0] Instruction ,
input [31:0] PC_plus4 ,
output reg [31:0] Instruction_out ,
output reg [31:0] PC_plus4_out ,
output reg [31:0] PC_out ,
output reg [15:0] Imm16_IF_ID ,
output reg [ 4:0] Shamt_IF_ID ,
output reg [ 4:0] RegisterRd_IF_ID,
output reg [ 4:0] RegisterRt_IF_ID,
output reg [ 4:0] RegisterRs_IF_ID,
output reg [25:0] JT_IF_ID
);
initial begin
Instruction_out <= 0;
PC_plus4_out <= 0;
PC_out <= 0;
Imm16_IF_ID <= 0;
Shamt_IF_ID <= 0;
RegisterRd_IF_ID <= 0;
RegisterRt_IF_ID <= 0;
RegisterRs_IF_ID <= 0;
JT_IF_ID <= 0;
end
always@(posedge clk) begin
if(~reset || IF_ID_Flush) begin
Instruction_out <= 0;
Shamt_IF_ID <= 0;
RegisterRs_IF_ID <= 0;
RegisterRd_IF_ID <= 0;
RegisterRt_IF_ID <= 0;
JT_IF_ID <= 0;
Imm16_IF_ID <= 0;
end
else if(IF_ID_Wr) begin
Instruction_out <= Instruction;
PC_plus4_out <= PC_plus4;
Shamt_IF_ID <= Instruction[10:6];
RegisterRd_IF_ID <= Instruction[15:11];
RegisterRt_IF_ID <= Instruction[20:16];
RegisterRs_IF_ID <= Instruction[25:21];
JT_IF_ID <= Instruction[25:0];
Imm16_IF_ID <= Instruction[15:0];
PC_out <= PC_in;
end
end
endmodule | module IFtoID (
input clk ,
input reset ,
input IF_ID_Wr ,
input IF_ID_Flush ,
input [31:0] PC_in ,
input [31:0] Instruction ,
input [31:0] PC_plus4 ,
output reg [31:0] Instruction_out ,
output reg [31:0] PC_plus4_out ,
output reg [31:0] PC_out ,
output reg [15:0] Imm16_IF_ID ,
output reg [ 4:0] Shamt_IF_ID ,
output reg [ 4:0] RegisterRd_IF_ID,
output reg [ 4:0] RegisterRt_IF_ID,
output reg [ 4:0] RegisterRs_IF_ID,
output reg [25:0] JT_IF_ID
); |
initial begin
Instruction_out <= 0;
PC_plus4_out <= 0;
PC_out <= 0;
Imm16_IF_ID <= 0;
Shamt_IF_ID <= 0;
RegisterRd_IF_ID <= 0;
RegisterRt_IF_ID <= 0;
RegisterRs_IF_ID <= 0;
JT_IF_ID <= 0;
end
always@(posedge clk) begin
if(~reset || IF_ID_Flush) begin
Instruction_out <= 0;
Shamt_IF_ID <= 0;
RegisterRs_IF_ID <= 0;
RegisterRd_IF_ID <= 0;
RegisterRt_IF_ID <= 0;
JT_IF_ID <= 0;
Imm16_IF_ID <= 0;
end
else if(IF_ID_Wr) begin
Instruction_out <= Instruction;
PC_plus4_out <= PC_plus4;
Shamt_IF_ID <= Instruction[10:6];
RegisterRd_IF_ID <= Instruction[15:11];
RegisterRt_IF_ID <= Instruction[20:16];
RegisterRs_IF_ID <= Instruction[25:21];
JT_IF_ID <= Instruction[25:0];
Imm16_IF_ID <= Instruction[15:0];
PC_out <= PC_in;
end
end
endmodule | 0 |
141,606 | data/full_repos/permissive/95875066/pipeline_processor/Inst_Mem.v | 95,875,066 | Inst_Mem.v | v | 186 | 66 | [] | [] | [] | [(3, 185)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95875066/pipeline_processor/Inst_Mem.v:11: Bit extraction of array[255:0] requires 8 bit index, not 29 bits.\n : ... In instance Inst_Mem\nassign data = (addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 312,155 | module | module Inst_Mem (
input [31:0] addr,
output [31:0] data
);
localparam ROM_SIZE = 256;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data = (addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h08000003;
ROMDATA[1] <= 32'h0800002d;
ROMDATA[2] <= 32'h080000a5;
ROMDATA[3] <= 32'h3c084000;
ROMDATA[4] <= 32'h35080008;
ROMDATA[5] <= 32'had000000;
ROMDATA[6] <= 32'h3c0affff;
ROMDATA[7] <= 32'h354affe0;
ROMDATA[8] <= 32'had0afff8;
ROMDATA[9] <= 32'h354affff;
ROMDATA[10] <= 32'had0afffc;
ROMDATA[11] <= 32'h20090000;
ROMDATA[12] <= 32'had090000;
ROMDATA[13] <= 32'h00001020;
ROMDATA[14] <= 32'h8d100018;
ROMDATA[15] <= 32'h32100008;
ROMDATA[16] <= 32'h1e000004;
ROMDATA[17] <= 32'h0800000e;
ROMDATA[18] <= 32'h8d040014;
ROMDATA[19] <= 32'h20420001;
ROMDATA[20] <= 32'h0800000e;
ROMDATA[21] <= 32'had000018;
ROMDATA[22] <= 32'h1040fffb;
ROMDATA[23] <= 32'h8d050014;
ROMDATA[24] <= 32'h00808020;
ROMDATA[25] <= 32'h00a08820;
ROMDATA[26] <= 32'h00105020;
ROMDATA[27] <= 32'h00118020;
ROMDATA[28] <= 32'h000a8820;
ROMDATA[29] <= 32'h0230582a;
ROMDATA[30] <= 32'h11600003;
ROMDATA[31] <= 32'h00105020;
ROMDATA[32] <= 32'h00118020;
ROMDATA[33] <= 32'h000a8820;
ROMDATA[34] <= 32'h02308822;
ROMDATA[35] <= 32'h0211582a;
ROMDATA[36] <= 32'h11600001;
ROMDATA[37] <= 32'h08000022;
ROMDATA[38] <= 32'h12200001;
ROMDATA[39] <= 32'h0800001a;
ROMDATA[40] <= 32'had100010;
ROMDATA[41] <= 32'had100004;
ROMDATA[42] <= 32'h20090003;
ROMDATA[43] <= 32'had090000;
ROMDATA[44] <= 32'h1800ffff;
ROMDATA[45] <= 32'hafa90004;
ROMDATA[46] <= 32'hafa80008;
ROMDATA[47] <= 32'h00004020;
ROMDATA[48] <= 32'h3c084000;
ROMDATA[49] <= 32'h8d090008;
ROMDATA[50] <= 32'h3129fff9;
ROMDATA[51] <= 32'had090008;
ROMDATA[52] <= 32'h23bd0024;
ROMDATA[53] <= 32'hafb00000;
ROMDATA[54] <= 32'hafa4fffc;
ROMDATA[55] <= 32'hafa5fff8;
ROMDATA[56] <= 32'hafaafff4;
ROMDATA[57] <= 32'hafa2fff0;
ROMDATA[58] <= 32'hafa3ffec;
ROMDATA[59] <= 32'hafbfffe8;
ROMDATA[60] <= 32'h8d100014;
ROMDATA[61] <= 32'h00108202;
ROMDATA[62] <= 32'h2003000e;
ROMDATA[63] <= 32'h12030006;
ROMDATA[64] <= 32'h2003000d;
ROMDATA[65] <= 32'h12030007;
ROMDATA[66] <= 32'h2003000b;
ROMDATA[67] <= 32'h12030008;
ROMDATA[68] <= 32'h20030007;
ROMDATA[69] <= 32'h12030009;
ROMDATA[70] <= 32'h20100d00;
ROMDATA[71] <= 32'h3087000f;
ROMDATA[72] <= 32'h08000052;
ROMDATA[73] <= 32'h20100b00;
ROMDATA[74] <= 32'h00053902;
ROMDATA[75] <= 32'h08000052;
ROMDATA[76] <= 32'h20100700;
ROMDATA[77] <= 32'h30a7000f;
ROMDATA[78] <= 32'h08000052;
ROMDATA[79] <= 32'h20100e00;
ROMDATA[80] <= 32'h00043902;
ROMDATA[81] <= 32'h08000052;
ROMDATA[82] <= 32'h0c000056;
ROMDATA[83] <= 32'h020a8025;
ROMDATA[84] <= 32'had100014;
ROMDATA[85] <= 32'h08000097;
ROMDATA[86] <= 32'h00001020;
ROMDATA[87] <= 32'h10e2001f;
ROMDATA[88] <= 32'h20420001;
ROMDATA[89] <= 32'h10e2001f;
ROMDATA[90] <= 32'h20420001;
ROMDATA[91] <= 32'h10e2001f;
ROMDATA[92] <= 32'h20420001;
ROMDATA[93] <= 32'h10e2001f;
ROMDATA[94] <= 32'h20420001;
ROMDATA[95] <= 32'h10e2001f;
ROMDATA[96] <= 32'h20420001;
ROMDATA[97] <= 32'h10e2001f;
ROMDATA[98] <= 32'h20420001;
ROMDATA[99] <= 32'h10e2001f;
ROMDATA[100] <= 32'h20420001;
ROMDATA[101] <= 32'h10e2001f;
ROMDATA[102] <= 32'h20420001;
ROMDATA[103] <= 32'h10e2001f;
ROMDATA[104] <= 32'h20420001;
ROMDATA[105] <= 32'h10e2001f;
ROMDATA[106] <= 32'h20420001;
ROMDATA[107] <= 32'h10e2001f;
ROMDATA[108] <= 32'h20420001;
ROMDATA[109] <= 32'h10e2001f;
ROMDATA[110] <= 32'h20420001;
ROMDATA[111] <= 32'h10e2001f;
ROMDATA[112] <= 32'h20420001;
ROMDATA[113] <= 32'h10e2001f;
ROMDATA[114] <= 32'h20420001;
ROMDATA[115] <= 32'h10e2001f;
ROMDATA[116] <= 32'h20420001;
ROMDATA[117] <= 32'h10e2001f;
ROMDATA[118] <= 32'h03e00008;
ROMDATA[119] <= 32'h200a0001;
ROMDATA[120] <= 32'h03e00008;
ROMDATA[121] <= 32'h200a004f;
ROMDATA[122] <= 32'h03e00008;
ROMDATA[123] <= 32'h200a0012;
ROMDATA[124] <= 32'h03e00008;
ROMDATA[125] <= 32'h200a0006;
ROMDATA[126] <= 32'h03e00008;
ROMDATA[127] <= 32'h200a004c;
ROMDATA[128] <= 32'h03e00008;
ROMDATA[129] <= 32'h200a0024;
ROMDATA[130] <= 32'h03e00008;
ROMDATA[131] <= 32'h200a0020;
ROMDATA[132] <= 32'h03e00008;
ROMDATA[133] <= 32'h200a000f;
ROMDATA[134] <= 32'h03e00008;
ROMDATA[135] <= 32'h200a0000;
ROMDATA[136] <= 32'h03e00008;
ROMDATA[137] <= 32'h200a0004;
ROMDATA[138] <= 32'h03e00008;
ROMDATA[139] <= 32'h200a0008;
ROMDATA[140] <= 32'h03e00008;
ROMDATA[141] <= 32'h200a0060;
ROMDATA[142] <= 32'h03e00008;
ROMDATA[143] <= 32'h200a0031;
ROMDATA[144] <= 32'h03e00008;
ROMDATA[145] <= 32'h200a0042;
ROMDATA[146] <= 32'h03e00008;
ROMDATA[147] <= 32'h200a0030;
ROMDATA[148] <= 32'h03e00008;
ROMDATA[149] <= 32'h200a0038;
ROMDATA[150] <= 32'h03e00008;
ROMDATA[151] <= 32'h23bdffdc;
ROMDATA[152] <= 32'h8fbf000c;
ROMDATA[153] <= 32'h8fa30010;
ROMDATA[154] <= 32'h8fa20014;
ROMDATA[155] <= 32'h8faa0018;
ROMDATA[156] <= 32'h8fa5001c;
ROMDATA[157] <= 32'h8fa40020;
ROMDATA[158] <= 32'h8fb00024;
ROMDATA[159] <= 32'h235afffc;
ROMDATA[160] <= 32'h35290002;
ROMDATA[161] <= 32'had090008;
ROMDATA[162] <= 32'h8fa90004;
ROMDATA[163] <= 32'h8fa80008;
ROMDATA[164] <= 32'h03400008;
ROMDATA[165] <= 32'h03400008;
for (i=166;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | module Inst_Mem (
input [31:0] addr,
output [31:0] data
); |
localparam ROM_SIZE = 256;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data = (addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h08000003;
ROMDATA[1] <= 32'h0800002d;
ROMDATA[2] <= 32'h080000a5;
ROMDATA[3] <= 32'h3c084000;
ROMDATA[4] <= 32'h35080008;
ROMDATA[5] <= 32'had000000;
ROMDATA[6] <= 32'h3c0affff;
ROMDATA[7] <= 32'h354affe0;
ROMDATA[8] <= 32'had0afff8;
ROMDATA[9] <= 32'h354affff;
ROMDATA[10] <= 32'had0afffc;
ROMDATA[11] <= 32'h20090000;
ROMDATA[12] <= 32'had090000;
ROMDATA[13] <= 32'h00001020;
ROMDATA[14] <= 32'h8d100018;
ROMDATA[15] <= 32'h32100008;
ROMDATA[16] <= 32'h1e000004;
ROMDATA[17] <= 32'h0800000e;
ROMDATA[18] <= 32'h8d040014;
ROMDATA[19] <= 32'h20420001;
ROMDATA[20] <= 32'h0800000e;
ROMDATA[21] <= 32'had000018;
ROMDATA[22] <= 32'h1040fffb;
ROMDATA[23] <= 32'h8d050014;
ROMDATA[24] <= 32'h00808020;
ROMDATA[25] <= 32'h00a08820;
ROMDATA[26] <= 32'h00105020;
ROMDATA[27] <= 32'h00118020;
ROMDATA[28] <= 32'h000a8820;
ROMDATA[29] <= 32'h0230582a;
ROMDATA[30] <= 32'h11600003;
ROMDATA[31] <= 32'h00105020;
ROMDATA[32] <= 32'h00118020;
ROMDATA[33] <= 32'h000a8820;
ROMDATA[34] <= 32'h02308822;
ROMDATA[35] <= 32'h0211582a;
ROMDATA[36] <= 32'h11600001;
ROMDATA[37] <= 32'h08000022;
ROMDATA[38] <= 32'h12200001;
ROMDATA[39] <= 32'h0800001a;
ROMDATA[40] <= 32'had100010;
ROMDATA[41] <= 32'had100004;
ROMDATA[42] <= 32'h20090003;
ROMDATA[43] <= 32'had090000;
ROMDATA[44] <= 32'h1800ffff;
ROMDATA[45] <= 32'hafa90004;
ROMDATA[46] <= 32'hafa80008;
ROMDATA[47] <= 32'h00004020;
ROMDATA[48] <= 32'h3c084000;
ROMDATA[49] <= 32'h8d090008;
ROMDATA[50] <= 32'h3129fff9;
ROMDATA[51] <= 32'had090008;
ROMDATA[52] <= 32'h23bd0024;
ROMDATA[53] <= 32'hafb00000;
ROMDATA[54] <= 32'hafa4fffc;
ROMDATA[55] <= 32'hafa5fff8;
ROMDATA[56] <= 32'hafaafff4;
ROMDATA[57] <= 32'hafa2fff0;
ROMDATA[58] <= 32'hafa3ffec;
ROMDATA[59] <= 32'hafbfffe8;
ROMDATA[60] <= 32'h8d100014;
ROMDATA[61] <= 32'h00108202;
ROMDATA[62] <= 32'h2003000e;
ROMDATA[63] <= 32'h12030006;
ROMDATA[64] <= 32'h2003000d;
ROMDATA[65] <= 32'h12030007;
ROMDATA[66] <= 32'h2003000b;
ROMDATA[67] <= 32'h12030008;
ROMDATA[68] <= 32'h20030007;
ROMDATA[69] <= 32'h12030009;
ROMDATA[70] <= 32'h20100d00;
ROMDATA[71] <= 32'h3087000f;
ROMDATA[72] <= 32'h08000052;
ROMDATA[73] <= 32'h20100b00;
ROMDATA[74] <= 32'h00053902;
ROMDATA[75] <= 32'h08000052;
ROMDATA[76] <= 32'h20100700;
ROMDATA[77] <= 32'h30a7000f;
ROMDATA[78] <= 32'h08000052;
ROMDATA[79] <= 32'h20100e00;
ROMDATA[80] <= 32'h00043902;
ROMDATA[81] <= 32'h08000052;
ROMDATA[82] <= 32'h0c000056;
ROMDATA[83] <= 32'h020a8025;
ROMDATA[84] <= 32'had100014;
ROMDATA[85] <= 32'h08000097;
ROMDATA[86] <= 32'h00001020;
ROMDATA[87] <= 32'h10e2001f;
ROMDATA[88] <= 32'h20420001;
ROMDATA[89] <= 32'h10e2001f;
ROMDATA[90] <= 32'h20420001;
ROMDATA[91] <= 32'h10e2001f;
ROMDATA[92] <= 32'h20420001;
ROMDATA[93] <= 32'h10e2001f;
ROMDATA[94] <= 32'h20420001;
ROMDATA[95] <= 32'h10e2001f;
ROMDATA[96] <= 32'h20420001;
ROMDATA[97] <= 32'h10e2001f;
ROMDATA[98] <= 32'h20420001;
ROMDATA[99] <= 32'h10e2001f;
ROMDATA[100] <= 32'h20420001;
ROMDATA[101] <= 32'h10e2001f;
ROMDATA[102] <= 32'h20420001;
ROMDATA[103] <= 32'h10e2001f;
ROMDATA[104] <= 32'h20420001;
ROMDATA[105] <= 32'h10e2001f;
ROMDATA[106] <= 32'h20420001;
ROMDATA[107] <= 32'h10e2001f;
ROMDATA[108] <= 32'h20420001;
ROMDATA[109] <= 32'h10e2001f;
ROMDATA[110] <= 32'h20420001;
ROMDATA[111] <= 32'h10e2001f;
ROMDATA[112] <= 32'h20420001;
ROMDATA[113] <= 32'h10e2001f;
ROMDATA[114] <= 32'h20420001;
ROMDATA[115] <= 32'h10e2001f;
ROMDATA[116] <= 32'h20420001;
ROMDATA[117] <= 32'h10e2001f;
ROMDATA[118] <= 32'h03e00008;
ROMDATA[119] <= 32'h200a0001;
ROMDATA[120] <= 32'h03e00008;
ROMDATA[121] <= 32'h200a004f;
ROMDATA[122] <= 32'h03e00008;
ROMDATA[123] <= 32'h200a0012;
ROMDATA[124] <= 32'h03e00008;
ROMDATA[125] <= 32'h200a0006;
ROMDATA[126] <= 32'h03e00008;
ROMDATA[127] <= 32'h200a004c;
ROMDATA[128] <= 32'h03e00008;
ROMDATA[129] <= 32'h200a0024;
ROMDATA[130] <= 32'h03e00008;
ROMDATA[131] <= 32'h200a0020;
ROMDATA[132] <= 32'h03e00008;
ROMDATA[133] <= 32'h200a000f;
ROMDATA[134] <= 32'h03e00008;
ROMDATA[135] <= 32'h200a0000;
ROMDATA[136] <= 32'h03e00008;
ROMDATA[137] <= 32'h200a0004;
ROMDATA[138] <= 32'h03e00008;
ROMDATA[139] <= 32'h200a0008;
ROMDATA[140] <= 32'h03e00008;
ROMDATA[141] <= 32'h200a0060;
ROMDATA[142] <= 32'h03e00008;
ROMDATA[143] <= 32'h200a0031;
ROMDATA[144] <= 32'h03e00008;
ROMDATA[145] <= 32'h200a0042;
ROMDATA[146] <= 32'h03e00008;
ROMDATA[147] <= 32'h200a0030;
ROMDATA[148] <= 32'h03e00008;
ROMDATA[149] <= 32'h200a0038;
ROMDATA[150] <= 32'h03e00008;
ROMDATA[151] <= 32'h23bdffdc;
ROMDATA[152] <= 32'h8fbf000c;
ROMDATA[153] <= 32'h8fa30010;
ROMDATA[154] <= 32'h8fa20014;
ROMDATA[155] <= 32'h8faa0018;
ROMDATA[156] <= 32'h8fa5001c;
ROMDATA[157] <= 32'h8fa40020;
ROMDATA[158] <= 32'h8fb00024;
ROMDATA[159] <= 32'h235afffc;
ROMDATA[160] <= 32'h35290002;
ROMDATA[161] <= 32'had090008;
ROMDATA[162] <= 32'h8fa90004;
ROMDATA[163] <= 32'h8fa80008;
ROMDATA[164] <= 32'h03400008;
ROMDATA[165] <= 32'h03400008;
for (i=166;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | 0 |
141,607 | data/full_repos/permissive/95875066/pipeline_processor/MEMtoWB.v | 95,875,066 | MEMtoWB.v | v | 48 | 46 | [] | [] | [] | [(2, 48)] | null | data/verilator_xmls/db0d8fdd-80f4-4f0a-ab9d-bd7272b28271.xml | null | 312,156 | module | module MEMtoWB (
input clk ,
input reset ,
input [31:0] PC_plus4 ,
input [31:0] Data_Mem_Out ,
input [31:0] ALUOut ,
input [ 1:0] RegDst ,
input RegWr ,
input [ 1:0] MemToReg ,
input [ 4:0] RegisterRd ,
input [ 4:0] RegisterRt ,
output reg [31:0] PC_plus4_out ,
output reg [31:0] Data_Mem_Out_out,
output reg [31:0] ALUOut_out ,
output reg [ 1:0] RegDst_out ,
output reg RegWr_out ,
output reg [ 1:0] MemToReg_out ,
output reg [ 4:0] RegisterRd_out ,
output reg [ 4:0] RegisterRt_out
);
initial begin
PC_plus4_out <= 0;
Data_Mem_Out_out <= 0;
ALUOut_out <= 0;
RegDst_out <= 0;
RegWr_out <= 0;
MemToReg_out <= 0;
RegisterRd_out <= 0;
RegisterRt_out <= 0;
end
always@(posedge clk) begin
if(~reset) begin
RegWr_out <= 0;
end else begin
PC_plus4_out <= PC_plus4;
Data_Mem_Out_out <= Data_Mem_Out;
ALUOut_out <= ALUOut;
RegDst_out <= RegDst;
RegWr_out <= RegWr;
MemToReg_out <= MemToReg;
RegisterRt_out <= RegisterRt;
RegisterRd_out <= RegisterRd;
end
end
endmodule | module MEMtoWB (
input clk ,
input reset ,
input [31:0] PC_plus4 ,
input [31:0] Data_Mem_Out ,
input [31:0] ALUOut ,
input [ 1:0] RegDst ,
input RegWr ,
input [ 1:0] MemToReg ,
input [ 4:0] RegisterRd ,
input [ 4:0] RegisterRt ,
output reg [31:0] PC_plus4_out ,
output reg [31:0] Data_Mem_Out_out,
output reg [31:0] ALUOut_out ,
output reg [ 1:0] RegDst_out ,
output reg RegWr_out ,
output reg [ 1:0] MemToReg_out ,
output reg [ 4:0] RegisterRd_out ,
output reg [ 4:0] RegisterRt_out
); |
initial begin
PC_plus4_out <= 0;
Data_Mem_Out_out <= 0;
ALUOut_out <= 0;
RegDst_out <= 0;
RegWr_out <= 0;
MemToReg_out <= 0;
RegisterRd_out <= 0;
RegisterRt_out <= 0;
end
always@(posedge clk) begin
if(~reset) begin
RegWr_out <= 0;
end else begin
PC_plus4_out <= PC_plus4;
Data_Mem_Out_out <= Data_Mem_Out;
ALUOut_out <= ALUOut;
RegDst_out <= RegDst;
RegWr_out <= RegWr;
MemToReg_out <= MemToReg;
RegisterRt_out <= RegisterRt;
RegisterRd_out <= RegisterRd;
end
end
endmodule | 0 |
141,608 | data/full_repos/permissive/95875066/pipeline_processor/PC.v | 95,875,066 | PC.v | v | 25 | 54 | [] | [] | [] | [(3, 25)] | null | data/verilator_xmls/495fe38c-31ff-412b-a3a8-cf6b5c213482.xml | null | 312,157 | module | module PC (
input reset,
input clk ,
input PCWr ,
input [31:0] PC_in,
output reg [31:0] PC
);
parameter ILLOP = 32'h80000004;
parameter XADR = 32'h80000008;
parameter RESETPC = 32'h00000000;
always@(posedge clk) begin
if(~reset) begin
PC <= RESETPC;
end
else if(PCWr) begin
PC <= PC_in;
end
end
endmodule | module PC (
input reset,
input clk ,
input PCWr ,
input [31:0] PC_in,
output reg [31:0] PC
); |
parameter ILLOP = 32'h80000004;
parameter XADR = 32'h80000008;
parameter RESETPC = 32'h00000000;
always@(posedge clk) begin
if(~reset) begin
PC <= RESETPC;
end
else if(PCWr) begin
PC <= PC_in;
end
end
endmodule | 0 |
141,609 | data/full_repos/permissive/95875066/pipeline_processor/Peripheral.v | 95,875,066 | Peripheral.v | v | 177 | 66 | [] | [] | [] | [(3, 175)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95875066/pipeline_processor/Peripheral.v:93: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance Peripheral\n UART_RXD <= 32\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95875066/pipeline_processor/Peripheral.v:94: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance Peripheral\n UART_TXD <= 32\'b0;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 312,158 | module | module Peripheral (
input reset,clk,
input rd,wr,
input [31:0] addr,
input [31:0] wdata,
input [7:0] switch,
input RX_STATUS,
input TX_STATUS,
input [7:0] RX_DATA,
output reg [31:0] rdata,
output reg [7:0] led,
output reg [11:0] digi,
output irqout,
output TX_EN,
output [7:0] TX_DATA
);
reg [31:0] TH,TL;
reg [2:0] TCON;
reg [7:0] UART_TXD, UART_RXD;
reg [4:0] UARTCON;
reg [1:0] UART_status_counter;
initial begin
led = 0;
digi = 0;
UART_status_counter = 0;
end
assign irqout = TCON[2];
assign TX_EN = UARTCON[2];
assign TX_DATA = UART_TXD;
always@(*) begin
if(rd) begin
case(addr)
32'h40000000: rdata <= TH;
32'h40000004: rdata <= TL;
32'h40000008: rdata <= {29'b0,TCON};
32'h4000000C: rdata <= {24'b0,led};
32'h40000010: rdata <= {24'b0,switch};
32'h40000014: rdata <= {20'b0,digi};
32'h40000018: rdata <= {24'b0, UART_TXD};
32'h4000001c: rdata <= {24'b0, UART_RXD};
32'h40000020: begin
rdata <= {27'b0,UARTCON};
end
default: rdata <= 32'b0;
endcase
end
else
rdata <= 32'b0;
end
always@(posedge clk) begin
if(~reset) begin
TH <= 32'b0;
TL <= 32'b0;
TCON <= 3'b0;
UARTCON <= 5'b0;
UART_RXD <= 32'b0;
UART_TXD <= 32'b0;
led <= 0;
digi <= 0;
end
else begin
if(TCON[0]) begin
if(TL==32'hffffffff) begin
TL <= TH;
if(TCON[1]) begin
TCON[2] <= 1'b1;
end
end
else begin
TL <= TL + 1;
TCON[2] <= 0;
end
end
if (UART_status_counter == 0) begin
if (RX_STATUS) begin
UART_RXD <= RX_DATA;
UARTCON[3] <= 1'b1;
end
UARTCON[2] <= 0;
end
else if (UART_status_counter == 1) begin
UART_status_counter <= 0;
UARTCON[2] <= 1;
end
else begin
if (~TX_STATUS) begin
UART_status_counter <= 0;
UARTCON[2] <= 1;
end
else begin
UART_status_counter <= 2;
end
end
if(wr) begin
case(addr)
32'h40000000: TH <= wdata;
32'h40000004: TL <= wdata;
32'h40000008: TCON <= wdata[2:0];
32'h4000000C: led <= wdata[7:0];
32'h40000014: digi <= wdata[11:0];
32'h40000018: begin
UART_TXD <= wdata[7:0];
if(TX_STATUS)
UART_status_counter <= 2;
else
UART_status_counter <= 1;
end
32'h40000020: UARTCON <= wdata[4:0];
default: ;
endcase
end
end
end
endmodule | module Peripheral (
input reset,clk,
input rd,wr,
input [31:0] addr,
input [31:0] wdata,
input [7:0] switch,
input RX_STATUS,
input TX_STATUS,
input [7:0] RX_DATA,
output reg [31:0] rdata,
output reg [7:0] led,
output reg [11:0] digi,
output irqout,
output TX_EN,
output [7:0] TX_DATA
); |
reg [31:0] TH,TL;
reg [2:0] TCON;
reg [7:0] UART_TXD, UART_RXD;
reg [4:0] UARTCON;
reg [1:0] UART_status_counter;
initial begin
led = 0;
digi = 0;
UART_status_counter = 0;
end
assign irqout = TCON[2];
assign TX_EN = UARTCON[2];
assign TX_DATA = UART_TXD;
always@(*) begin
if(rd) begin
case(addr)
32'h40000000: rdata <= TH;
32'h40000004: rdata <= TL;
32'h40000008: rdata <= {29'b0,TCON};
32'h4000000C: rdata <= {24'b0,led};
32'h40000010: rdata <= {24'b0,switch};
32'h40000014: rdata <= {20'b0,digi};
32'h40000018: rdata <= {24'b0, UART_TXD};
32'h4000001c: rdata <= {24'b0, UART_RXD};
32'h40000020: begin
rdata <= {27'b0,UARTCON};
end
default: rdata <= 32'b0;
endcase
end
else
rdata <= 32'b0;
end
always@(posedge clk) begin
if(~reset) begin
TH <= 32'b0;
TL <= 32'b0;
TCON <= 3'b0;
UARTCON <= 5'b0;
UART_RXD <= 32'b0;
UART_TXD <= 32'b0;
led <= 0;
digi <= 0;
end
else begin
if(TCON[0]) begin
if(TL==32'hffffffff) begin
TL <= TH;
if(TCON[1]) begin
TCON[2] <= 1'b1;
end
end
else begin
TL <= TL + 1;
TCON[2] <= 0;
end
end
if (UART_status_counter == 0) begin
if (RX_STATUS) begin
UART_RXD <= RX_DATA;
UARTCON[3] <= 1'b1;
end
UARTCON[2] <= 0;
end
else if (UART_status_counter == 1) begin
UART_status_counter <= 0;
UARTCON[2] <= 1;
end
else begin
if (~TX_STATUS) begin
UART_status_counter <= 0;
UARTCON[2] <= 1;
end
else begin
UART_status_counter <= 2;
end
end
if(wr) begin
case(addr)
32'h40000000: TH <= wdata;
32'h40000004: TL <= wdata;
32'h40000008: TCON <= wdata[2:0];
32'h4000000C: led <= wdata[7:0];
32'h40000014: digi <= wdata[11:0];
32'h40000018: begin
UART_TXD <= wdata[7:0];
if(TX_STATUS)
UART_status_counter <= 2;
else
UART_status_counter <= 1;
end
32'h40000020: UARTCON <= wdata[4:0];
default: ;
endcase
end
end
end
endmodule | 0 |
141,610 | data/full_repos/permissive/95875066/single_cycle_processor/Control.v | 95,875,066 | Control.v | v | 90 | 276 | [] | [] | [] | [(1, 90)] | null | data/verilator_xmls/06082f3e-4a72-4c93-9865-9469306dcae2.xml | null | 312,167 | module | module Control (
input IRQ,
input [31:0] Instruction,
output [2:0] PCSrc,
output [1:0] RegDst,
output RegWr,
output ALUSrc1,
output ALUSrc2,
output [5:0] ALUFun,
output Sign,
output MemWr,
output MemRd,
output [1:0] MemToReg,
output EXTOp,
output LUOp
);
wire Except;
assign Except = !((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h20 || Instruction[5:0] == 6'h2a || Instruction[5:0] == 6'h03 || Instruction[5:0] == 6'h02 ||
Instruction[5:0] == 6'h21 || Instruction[5:0] == 6'h22 || Instruction[5:0] == 6'h23 || Instruction[5:0] == 6'h24 || Instruction[5:0] == 6'h25 ||
Instruction[5:0] == 6'h26 || Instruction[5:0] == 6'h27 || Instruction[5:0] == 6'h00 || Instruction[5:0] == 6'h08 || Instruction[5:0] == 6'h09)) ||
Instruction[31:26] == 6'h01 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h0a || Instruction[31:26] == 6'h0b || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h04 ||
Instruction[31:26] == 6'h23 || Instruction[31:26] == 6'h2b || Instruction[31:26] == 6'h0f || Instruction[31:26] == 6'h08 || Instruction[31:26] == 6'h09 || Instruction[31:26] == 6'h0c ||
Instruction[31:26] == 6'h02 || Instruction[31:26] == 6'h03 || Instruction[31:26] == 6'h07 || Instruction[31:26] == 6'h0d);
assign PCSrc = IRQ? 3'b100:
Except? 3'b101:
(Instruction[31:26] == 6'h02 || Instruction[31:26] == 6'h03 )? 3'b010:
(Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h08 || Instruction[5:0] == 6'h09))? 3'b011:
(Instruction[31:26] == 6'h04 || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h07 || Instruction[31:26] == 6'h01)? 3'b001:
3'b000;
assign RegDst = (Except || IRQ)? 3:
(Instruction[31:26] == 6'h03)? 2:
(Instruction[31:26] == 6'h00)? 0: 1;
assign RegWr = (IRQ || Except)?1:(Instruction[31:26] == 6'h2b || Instruction[31:26] == 6'h04 || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h07 ||
Instruction[31:26] == 6'h01 || Instruction[31:26] == 6'h02 || (Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h08))? 0: 1;
assign ALUSrc1 = (Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h00 || Instruction[5:0] == 6'h02 || Instruction[5:0] == 6'h03))? 1: 0;
assign ALUSrc2 = (Instruction[31:26] == 6'h00 || Instruction[31:26] == 6'h04 || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h07 || Instruction[31:26] == 6'h01)? 0: 1;
assign ALUFun = ((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h20 || Instruction[5:0] == 6'h21)) || Instruction[31:26] == 6'h23 || Instruction[31:26] == 6'h2b || Instruction[31:26] == 6'h0f || Instruction[31:26] == 6'h08 || Instruction[31:26] == 6'h09 )? 6'b000000:
(Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h22 || Instruction[5:0] == 6'h23))? 6'b000001:
((Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h24) || Instruction[31:26] == 6'h0c)? 6'b011000:
((Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h25) || Instruction[31:26] == 6'h0d)? 6'b011110:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h26)? 6'b010110:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h27)? 6'b010001:
((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h00 || Instruction[5:0] == 6'h08 || Instruction[5:0] == 6'h09)) || Instruction[31:26] == 6'h02 || Instruction[31:26] == 6'h03)? 6'b100000:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h02)? 6'b100001:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h03)? 6'b100011:
(Instruction[31:26] == 6'h04)? 6'b110011:
(Instruction[31:26] == 6'h05)? 6'b110001:
((Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h2a) || Instruction[31:26] == 6'h0a || Instruction[31:26] == 6'h0b)? 6'b110101:
(Instruction[31:26] == 6'h06)? 6'b111101:
(Instruction[31:26] == 6'h01)? 6'b111011:
6'b111111;
assign Sign = ((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h21 || Instruction[5:0] == 6'h23)) || Instruction[31:26] == 6'h09 || Instruction[31:26] == 6'h0b)? 0 : 1;
assign MemRd = (Instruction[31:26] == 6'h23)? 1:0;
assign MemWr = (Instruction[31:26] == 6'h2b)? 1:0;
assign MemToReg = (Except || IRQ || Instruction[31:26] == 6'h03 || (Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h09))? 2:
(Instruction[31:26] == 6'h23)? 1:0;
assign EXTOp = (Instruction[31:26] == 6'h0c || Instruction[31:26] == 6'h0d)? 0 : 1;
assign LUOp = (Instruction[31:26] == 6'h0f)? 1:0;
endmodule | module Control (
input IRQ,
input [31:0] Instruction,
output [2:0] PCSrc,
output [1:0] RegDst,
output RegWr,
output ALUSrc1,
output ALUSrc2,
output [5:0] ALUFun,
output Sign,
output MemWr,
output MemRd,
output [1:0] MemToReg,
output EXTOp,
output LUOp
); |
wire Except;
assign Except = !((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h20 || Instruction[5:0] == 6'h2a || Instruction[5:0] == 6'h03 || Instruction[5:0] == 6'h02 ||
Instruction[5:0] == 6'h21 || Instruction[5:0] == 6'h22 || Instruction[5:0] == 6'h23 || Instruction[5:0] == 6'h24 || Instruction[5:0] == 6'h25 ||
Instruction[5:0] == 6'h26 || Instruction[5:0] == 6'h27 || Instruction[5:0] == 6'h00 || Instruction[5:0] == 6'h08 || Instruction[5:0] == 6'h09)) ||
Instruction[31:26] == 6'h01 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h0a || Instruction[31:26] == 6'h0b || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h04 ||
Instruction[31:26] == 6'h23 || Instruction[31:26] == 6'h2b || Instruction[31:26] == 6'h0f || Instruction[31:26] == 6'h08 || Instruction[31:26] == 6'h09 || Instruction[31:26] == 6'h0c ||
Instruction[31:26] == 6'h02 || Instruction[31:26] == 6'h03 || Instruction[31:26] == 6'h07 || Instruction[31:26] == 6'h0d);
assign PCSrc = IRQ? 3'b100:
Except? 3'b101:
(Instruction[31:26] == 6'h02 || Instruction[31:26] == 6'h03 )? 3'b010:
(Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h08 || Instruction[5:0] == 6'h09))? 3'b011:
(Instruction[31:26] == 6'h04 || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h07 || Instruction[31:26] == 6'h01)? 3'b001:
3'b000;
assign RegDst = (Except || IRQ)? 3:
(Instruction[31:26] == 6'h03)? 2:
(Instruction[31:26] == 6'h00)? 0: 1;
assign RegWr = (IRQ || Except)?1:(Instruction[31:26] == 6'h2b || Instruction[31:26] == 6'h04 || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h07 ||
Instruction[31:26] == 6'h01 || Instruction[31:26] == 6'h02 || (Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h08))? 0: 1;
assign ALUSrc1 = (Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h00 || Instruction[5:0] == 6'h02 || Instruction[5:0] == 6'h03))? 1: 0;
assign ALUSrc2 = (Instruction[31:26] == 6'h00 || Instruction[31:26] == 6'h04 || Instruction[31:26] == 6'h05 || Instruction[31:26] == 6'h06 || Instruction[31:26] == 6'h07 || Instruction[31:26] == 6'h01)? 0: 1;
assign ALUFun = ((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h20 || Instruction[5:0] == 6'h21)) || Instruction[31:26] == 6'h23 || Instruction[31:26] == 6'h2b || Instruction[31:26] == 6'h0f || Instruction[31:26] == 6'h08 || Instruction[31:26] == 6'h09 )? 6'b000000:
(Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h22 || Instruction[5:0] == 6'h23))? 6'b000001:
((Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h24) || Instruction[31:26] == 6'h0c)? 6'b011000:
((Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h25) || Instruction[31:26] == 6'h0d)? 6'b011110:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h26)? 6'b010110:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h27)? 6'b010001:
((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h00 || Instruction[5:0] == 6'h08 || Instruction[5:0] == 6'h09)) || Instruction[31:26] == 6'h02 || Instruction[31:26] == 6'h03)? 6'b100000:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h02)? 6'b100001:
(Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h03)? 6'b100011:
(Instruction[31:26] == 6'h04)? 6'b110011:
(Instruction[31:26] == 6'h05)? 6'b110001:
((Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h2a) || Instruction[31:26] == 6'h0a || Instruction[31:26] == 6'h0b)? 6'b110101:
(Instruction[31:26] == 6'h06)? 6'b111101:
(Instruction[31:26] == 6'h01)? 6'b111011:
6'b111111;
assign Sign = ((Instruction[31:26] == 6'h00 && (Instruction[5:0] == 6'h21 || Instruction[5:0] == 6'h23)) || Instruction[31:26] == 6'h09 || Instruction[31:26] == 6'h0b)? 0 : 1;
assign MemRd = (Instruction[31:26] == 6'h23)? 1:0;
assign MemWr = (Instruction[31:26] == 6'h2b)? 1:0;
assign MemToReg = (Except || IRQ || Instruction[31:26] == 6'h03 || (Instruction[31:26] == 6'h00 && Instruction[5:0] == 6'h09))? 2:
(Instruction[31:26] == 6'h23)? 1:0;
assign EXTOp = (Instruction[31:26] == 6'h0c || Instruction[31:26] == 6'h0d)? 0 : 1;
assign LUOp = (Instruction[31:26] == 6'h0f)? 1:0;
endmodule | 0 |
141,611 | data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v | 95,875,066 | CPU_single.v | v | 194 | 69 | [] | [] | [] | [(3, 194)] | null | null | 1: b'%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:55: Cannot find file containing module: \'Control\'\nControl CTL(\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/95875066/single_cycle_processor,data/full_repos/permissive/95875066/Control\n data/full_repos/permissive/95875066/single_cycle_processor,data/full_repos/permissive/95875066/Control.v\n data/full_repos/permissive/95875066/single_cycle_processor,data/full_repos/permissive/95875066/Control.sv\n Control\n Control.v\n Control.sv\n obj_dir/Control\n obj_dir/Control.v\n obj_dir/Control.sv\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:75: Cannot find file containing module: \'PC_add\'\nPC_add PCA(\n^~~~~~\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:88: Cannot find file containing module: \'Inst_Mem\'\nInst_Mem IM(\n^~~~~~~~\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:99: Cannot find file containing module: \'RegFile\'\nRegFile RF(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:115: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s SEL generates 5 bits.\n : ... In instance CPU_single\nassign ALU_in1 = ALUSrc1?Instruction[10:6]:DataBus_A;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:118: Cannot find file containing module: \'ALU\'\nALU ALU_(\n^~~\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:135: Cannot find file containing module: \'Data_Mem\'\nData_Mem DM(\n^~~~~~~~\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:154: Cannot find file containing module: \'Peripheral\'\nPeripheral PE(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:176: Cannot find file containing module: \'uart_rx\'\nuart_rx i_uart_rx (\n^~~~~~~\n%Error: data/full_repos/permissive/95875066/single_cycle_processor/CPU_single.v:185: Cannot find file containing module: \'uart_tx\'\nuart_tx i_uart_tx (\n^~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n' | 312,168 | module | module CPU_single (
input reset,
input clk,
input [7:0] switch,
input UART_RX,
output [7:0] led,
output [11:0] digi,
output UART_TX
);
wire [2:0] PCSrc;
wire [1:0] RegDst;
wire RegWr;
wire ALUSrc1;
wire ALUSrc2;
wire Sign;
wire MemWr;
wire MemRd;
wire [1:0] MemToReg;
wire EXTOp;
wire LUOp;
wire IRQ;
wire [31:0] Instruction;
wire [5:0] ALUFun;
wire [31:0] PC_plus4;
wire [31:0] ALUOut;
wire [31:0] EXTOut;
wire [31:0] DataBus_A;
wire [31:0] DataBus_B;
wire [31:0] DataBus_C;
wire [31:0] PC;
wire baudclk;
wire [7:0] TX_DATA;
wire TX_EN;
wire TX_STATUS;
wire [7:0] RX_DATA;
wire RX_STATUS;
Control CTL(
.IRQ (IRQ),
.Instruction(Instruction),
.PCSrc (PCSrc),
.RegDst (RegDst),
.RegWr (RegWr),
.ALUSrc1 (ALUSrc1),
.ALUSrc2 (ALUSrc2),
.ALUFun (ALUFun),
.Sign (Sign),
.MemWr (MemWr),
.MemRd (MemRd),
.MemToReg (MemToReg),
.EXTOp (EXTOp),
.LUOp (LUOp)
);
PC_add PCA(
.reset (reset),
.clk (clk),
.PCSrc (PCSrc),
.ALUOut(ALUOut[0]),
.EXTOut(EXTOut),
.JT (Instruction[25:0]),
.A (DataBus_A),
.PC (PC),
.plus4 (PC_plus4)
);
Inst_Mem IM(
.addr(PC[31:0]),
.data(Instruction)
);
wire [4:0] Addr_destination;
assign Addr_destination = (RegDst[1:0] == 2'b00)?Instruction[15:11]:
(RegDst[1:0] == 2'b01)?Instruction[20:16]:
(RegDst[1:0] == 2'b10)?5'b11111:5'b11010;
RegFile RF(
.reset(reset),
.clk (clk),
.wr (RegWr),
.addr1(Instruction[25:21]),
.addr2(Instruction[20:16]),
.addr3(Addr_destination),
.data3(DataBus_C),
.data1(DataBus_A),
.data2(DataBus_B)
);
wire [31:0] ALU_in1;
wire [31:0] ALU_in2;
wire [31:0] LUOut;
assign ALU_in1 = ALUSrc1?Instruction[10:6]:DataBus_A;
assign ALU_in2 = ALUSrc2?LUOut:DataBus_B;
ALU ALU_(
.ALUFun(ALUFun),
.A (ALU_in1),
.B (ALU_in2),
.Sign (Sign),
.S (ALUOut)
);
assign LUOut = LUOp? {Instruction[15:0], 16'b0}: EXTOut;
assign EXTOut = EXTOp? {{16{Instruction[15]}}, Instruction[15:0]}:
{16'b0, Instruction[15:0]};
wire [31:0] Data_Mem_Out;
wire [31:0] Data_PE_Out;
wire [31:0] Data_Out;
Data_Mem DM(
.reset(reset),
.clk (clk),
.rd (MemRd),
.wr (MemWr),
.addr (ALUOut),
.rdata(Data_Mem_Out),
.wdata(DataBus_B)
);
assign Data_Out = ALUOut[30]?Data_PE_Out:Data_Mem_Out;
assign DataBus_C = (MemToReg == 2'b00)?ALUOut:
(MemToReg == 2'b01)?Data_Out:
(MemToReg == 2'b10)?PC_plus4:0;
Peripheral PE(
.reset (reset),
.clk (clk),
.rd (MemRd),
.wr (MemWr),
.addr (ALUOut),
.wdata (DataBus_B),
.switch (switch),
.RX_STATUS (RX_STATUS),
.TX_STATUS (TX_STATUS),
.RX_DATA (RX_DATA),
.rdata (Data_PE_Out),
.led (led),
.digi (digi),
.irqout (IRQ),
.TX_EN (TX_EN),
.TX_DATA (TX_DATA)
);
uart_rx i_uart_rx (
.i_Clock (clk),
.i_Rx_Serial(UART_RX),
.o_Rx_DV (RX_STATUS),
.o_Rx_Byte (RX_DATA)
);
uart_tx i_uart_tx (
.i_Clock (clk ),
.i_Tx_DV (TX_EN ),
.i_Tx_Byte (TX_DATA ),
.o_Tx_Active(TX_STATUS),
.o_Tx_Serial(UART_TX),
.o_Tx_Done ( )
);
endmodule | module CPU_single (
input reset,
input clk,
input [7:0] switch,
input UART_RX,
output [7:0] led,
output [11:0] digi,
output UART_TX
); |
wire [2:0] PCSrc;
wire [1:0] RegDst;
wire RegWr;
wire ALUSrc1;
wire ALUSrc2;
wire Sign;
wire MemWr;
wire MemRd;
wire [1:0] MemToReg;
wire EXTOp;
wire LUOp;
wire IRQ;
wire [31:0] Instruction;
wire [5:0] ALUFun;
wire [31:0] PC_plus4;
wire [31:0] ALUOut;
wire [31:0] EXTOut;
wire [31:0] DataBus_A;
wire [31:0] DataBus_B;
wire [31:0] DataBus_C;
wire [31:0] PC;
wire baudclk;
wire [7:0] TX_DATA;
wire TX_EN;
wire TX_STATUS;
wire [7:0] RX_DATA;
wire RX_STATUS;
Control CTL(
.IRQ (IRQ),
.Instruction(Instruction),
.PCSrc (PCSrc),
.RegDst (RegDst),
.RegWr (RegWr),
.ALUSrc1 (ALUSrc1),
.ALUSrc2 (ALUSrc2),
.ALUFun (ALUFun),
.Sign (Sign),
.MemWr (MemWr),
.MemRd (MemRd),
.MemToReg (MemToReg),
.EXTOp (EXTOp),
.LUOp (LUOp)
);
PC_add PCA(
.reset (reset),
.clk (clk),
.PCSrc (PCSrc),
.ALUOut(ALUOut[0]),
.EXTOut(EXTOut),
.JT (Instruction[25:0]),
.A (DataBus_A),
.PC (PC),
.plus4 (PC_plus4)
);
Inst_Mem IM(
.addr(PC[31:0]),
.data(Instruction)
);
wire [4:0] Addr_destination;
assign Addr_destination = (RegDst[1:0] == 2'b00)?Instruction[15:11]:
(RegDst[1:0] == 2'b01)?Instruction[20:16]:
(RegDst[1:0] == 2'b10)?5'b11111:5'b11010;
RegFile RF(
.reset(reset),
.clk (clk),
.wr (RegWr),
.addr1(Instruction[25:21]),
.addr2(Instruction[20:16]),
.addr3(Addr_destination),
.data3(DataBus_C),
.data1(DataBus_A),
.data2(DataBus_B)
);
wire [31:0] ALU_in1;
wire [31:0] ALU_in2;
wire [31:0] LUOut;
assign ALU_in1 = ALUSrc1?Instruction[10:6]:DataBus_A;
assign ALU_in2 = ALUSrc2?LUOut:DataBus_B;
ALU ALU_(
.ALUFun(ALUFun),
.A (ALU_in1),
.B (ALU_in2),
.Sign (Sign),
.S (ALUOut)
);
assign LUOut = LUOp? {Instruction[15:0], 16'b0}: EXTOut;
assign EXTOut = EXTOp? {{16{Instruction[15]}}, Instruction[15:0]}:
{16'b0, Instruction[15:0]};
wire [31:0] Data_Mem_Out;
wire [31:0] Data_PE_Out;
wire [31:0] Data_Out;
Data_Mem DM(
.reset(reset),
.clk (clk),
.rd (MemRd),
.wr (MemWr),
.addr (ALUOut),
.rdata(Data_Mem_Out),
.wdata(DataBus_B)
);
assign Data_Out = ALUOut[30]?Data_PE_Out:Data_Mem_Out;
assign DataBus_C = (MemToReg == 2'b00)?ALUOut:
(MemToReg == 2'b01)?Data_Out:
(MemToReg == 2'b10)?PC_plus4:0;
Peripheral PE(
.reset (reset),
.clk (clk),
.rd (MemRd),
.wr (MemWr),
.addr (ALUOut),
.wdata (DataBus_B),
.switch (switch),
.RX_STATUS (RX_STATUS),
.TX_STATUS (TX_STATUS),
.RX_DATA (RX_DATA),
.rdata (Data_PE_Out),
.led (led),
.digi (digi),
.irqout (IRQ),
.TX_EN (TX_EN),
.TX_DATA (TX_DATA)
);
uart_rx i_uart_rx (
.i_Clock (clk),
.i_Rx_Serial(UART_RX),
.o_Rx_DV (RX_STATUS),
.o_Rx_Byte (RX_DATA)
);
uart_tx i_uart_tx (
.i_Clock (clk ),
.i_Tx_DV (TX_EN ),
.i_Tx_Byte (TX_DATA ),
.o_Tx_Active(TX_STATUS),
.o_Tx_Serial(UART_TX),
.o_Tx_Done ( )
);
endmodule | 0 |
141,612 | data/full_repos/permissive/95875066/single_cycle_processor/PC_add.v | 95,875,066 | PC_add.v | v | 47 | 56 | [] | [] | [] | [(3, 47)] | null | data/verilator_xmls/dbf32dba-807a-4e32-9282-d7b2d5ff8e75.xml | null | 312,173 | module | module PC_add (
input reset,
input clk,
input [2:0] PCSrc,
input ALUOut,
input [31:0] EXTOut,
input [25:0] JT,
input [31:0] A,
output reg [31:0] PC,
output [31:0] plus4
);
parameter ILLOP = 32'h80000004;
parameter XADR = 32'h80000008;
parameter RESETPC = 32'h00000000;
wire [31:0] sel1;
wire [31:0] JTplusPC;
wire [31:0] ConBA;
assign ConBA = plus4 + {EXTOut[29:0], 2'b00};
assign sel1 = ALUOut?ConBA:plus4;
assign plus4 = {PC[31], PC[30:0]+31'h00000004};
assign JTplusPC = {PC[31:28], JT, 2'b0};
always@(posedge clk) begin
if(~reset) begin
PC <= RESETPC;
end
else begin
case (PCSrc)
3'b000: PC <= plus4;
3'b001: PC <= sel1;
3'b010: PC <= JTplusPC;
3'b011: PC <= A;
3'b100: PC <= ILLOP;
3'b101: PC <= XADR;
default: PC <= PC;
endcase
end
end
endmodule | module PC_add (
input reset,
input clk,
input [2:0] PCSrc,
input ALUOut,
input [31:0] EXTOut,
input [25:0] JT,
input [31:0] A,
output reg [31:0] PC,
output [31:0] plus4
); |
parameter ILLOP = 32'h80000004;
parameter XADR = 32'h80000008;
parameter RESETPC = 32'h00000000;
wire [31:0] sel1;
wire [31:0] JTplusPC;
wire [31:0] ConBA;
assign ConBA = plus4 + {EXTOut[29:0], 2'b00};
assign sel1 = ALUOut?ConBA:plus4;
assign plus4 = {PC[31], PC[30:0]+31'h00000004};
assign JTplusPC = {PC[31:28], JT, 2'b0};
always@(posedge clk) begin
if(~reset) begin
PC <= RESETPC;
end
else begin
case (PCSrc)
3'b000: PC <= plus4;
3'b001: PC <= sel1;
3'b010: PC <= JTplusPC;
3'b011: PC <= A;
3'b100: PC <= ILLOP;
3'b101: PC <= XADR;
default: PC <= PC;
endcase
end
end
endmodule | 0 |
141,615 | data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/eth_miim.v | 95,888,822 | eth_miim.v | v | 367 | 152 | [] | [] | [] | [(55, 415)] | null | null | 1: b'%Error: data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/eth_miim.v:3: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code,data/full_repos/permissive/95888822/timescale.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code,data/full_repos/permissive/95888822/timescale.v.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code,data/full_repos/permissive/95888822/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n' | 312,181 | module | module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
input Clk;
input Reset;
input [7:0] Divider;
input [15:0] CtrlData;
input [4:0] Rgad;
input [4:0] Fiad;
input NoPre;
input WCtrlData;
input RStat;
input ScanStat;
input Mdi;
output Mdc;
output Mdo;
output MdoEn;
output Busy;
output LinkFail;
output Nvalid;
output [15:0] Prsd;
output WCtrlDataStart;
output RStatStart;
output UpdateMIIRX_DATAReg;
reg Nvalid;
reg EndBusy_d;
reg EndBusy;
reg WCtrlData_q1;
reg WCtrlData_q2;
reg WCtrlData_q3;
reg WCtrlDataStart;
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1;
reg WCtrlDataStart_q2;
reg RStat_q1;
reg RStat_q2;
reg RStat_q3;
reg RStatStart;
reg RStatStart_q1;
reg RStatStart_q2;
reg ScanStat_q1;
reg ScanStat_q2;
reg SyncStatMdcEn;
wire WriteDataOp;
wire ReadStatusOp;
wire ScanStatusOp;
wire StartOp;
wire EndOp;
reg InProgress;
reg InProgress_q1;
reg InProgress_q2;
reg InProgress_q3;
reg WriteOp;
reg [6:0] BitCounter;
wire [3:0] ByteSelect;
wire MdcEn;
wire ShiftedBit;
wire MdcEn_n;
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte;
reg UpdateMIIRX_DATAReg;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= 1'b0;
EndBusy <= 1'b0;
end
else
begin
EndBusy_d <= ~InProgress_q2 & InProgress_q3;
EndBusy <= EndBusy_d;
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= 1;
else
UpdateMIIRX_DATAReg <= 0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= 1'b0;
WCtrlData_q2 <= 1'b0;
WCtrlData_q3 <= 1'b0;
RStat_q1 <= 1'b0;
RStat_q2 <= 1'b0;
RStat_q3 <= 1'b0;
ScanStat_q1 <= 1'b0;
ScanStat_q2 <= 1'b0;
SyncStatMdcEn <= 1'b0;
end
else
begin
WCtrlData_q1 <= WCtrlData;
WCtrlData_q2 <= WCtrlData_q1;
WCtrlData_q3 <= WCtrlData_q2;
RStat_q1 <= RStat;
RStat_q2 <= RStat_q1;
RStat_q3 <= RStat_q2;
ScanStat_q1 <= ScanStat;
ScanStat_q2 <= ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= ScanStat_q2;
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= 1'b0;
WCtrlDataStart_q <= 1'b0;
RStatStart <= 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= 1'b0;
RStatStart <= 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= 1'b1;
WCtrlDataStart_q <= WCtrlDataStart;
end
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= 1'b1;
end
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= 1'b0;
WCtrlDataStart_q2 <= 1'b0;
RStatStart_q1 <= 1'b0;
RStatStart_q2 <= 1'b0;
InProgress_q1 <= 1'b0;
InProgress_q2 <= 1'b0;
InProgress_q3 <= 1'b0;
LatchByte0_d <= 1'b0;
LatchByte1_d <= 1'b0;
LatchByte <= 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= WCtrlDataStart;
WCtrlDataStart_q2 <= WCtrlDataStart_q1;
RStatStart_q1 <= RStatStart;
RStatStart_q2 <= RStatStart_q1;
LatchByte[0] <= LatchByte0_d;
LatchByte[1] <= LatchByte1_d;
LatchByte0_d <= LatchByte0_d2;
LatchByte1_d <= LatchByte1_d2;
InProgress_q1 <= InProgress;
InProgress_q2 <= InProgress_q1;
InProgress_q3 <= InProgress_q2;
end
end
end
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= 1'b0;
WriteOp <= 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= WriteDataOp;
InProgress <= 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= 1'b0;
WriteOp <= 1'b0;
end
end
end
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= 7'h21;
else
BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= 7'h0;
end
end
end
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule | module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
); |
input Clk;
input Reset;
input [7:0] Divider;
input [15:0] CtrlData;
input [4:0] Rgad;
input [4:0] Fiad;
input NoPre;
input WCtrlData;
input RStat;
input ScanStat;
input Mdi;
output Mdc;
output Mdo;
output MdoEn;
output Busy;
output LinkFail;
output Nvalid;
output [15:0] Prsd;
output WCtrlDataStart;
output RStatStart;
output UpdateMIIRX_DATAReg;
reg Nvalid;
reg EndBusy_d;
reg EndBusy;
reg WCtrlData_q1;
reg WCtrlData_q2;
reg WCtrlData_q3;
reg WCtrlDataStart;
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1;
reg WCtrlDataStart_q2;
reg RStat_q1;
reg RStat_q2;
reg RStat_q3;
reg RStatStart;
reg RStatStart_q1;
reg RStatStart_q2;
reg ScanStat_q1;
reg ScanStat_q2;
reg SyncStatMdcEn;
wire WriteDataOp;
wire ReadStatusOp;
wire ScanStatusOp;
wire StartOp;
wire EndOp;
reg InProgress;
reg InProgress_q1;
reg InProgress_q2;
reg InProgress_q3;
reg WriteOp;
reg [6:0] BitCounter;
wire [3:0] ByteSelect;
wire MdcEn;
wire ShiftedBit;
wire MdcEn_n;
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte;
reg UpdateMIIRX_DATAReg;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= 1'b0;
EndBusy <= 1'b0;
end
else
begin
EndBusy_d <= ~InProgress_q2 & InProgress_q3;
EndBusy <= EndBusy_d;
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= 1;
else
UpdateMIIRX_DATAReg <= 0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= 1'b0;
WCtrlData_q2 <= 1'b0;
WCtrlData_q3 <= 1'b0;
RStat_q1 <= 1'b0;
RStat_q2 <= 1'b0;
RStat_q3 <= 1'b0;
ScanStat_q1 <= 1'b0;
ScanStat_q2 <= 1'b0;
SyncStatMdcEn <= 1'b0;
end
else
begin
WCtrlData_q1 <= WCtrlData;
WCtrlData_q2 <= WCtrlData_q1;
WCtrlData_q3 <= WCtrlData_q2;
RStat_q1 <= RStat;
RStat_q2 <= RStat_q1;
RStat_q3 <= RStat_q2;
ScanStat_q1 <= ScanStat;
ScanStat_q2 <= ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= ScanStat_q2;
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= 1'b0;
WCtrlDataStart_q <= 1'b0;
RStatStart <= 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= 1'b0;
RStatStart <= 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= 1'b1;
WCtrlDataStart_q <= WCtrlDataStart;
end
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= 1'b1;
end
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= 1'b0;
WCtrlDataStart_q2 <= 1'b0;
RStatStart_q1 <= 1'b0;
RStatStart_q2 <= 1'b0;
InProgress_q1 <= 1'b0;
InProgress_q2 <= 1'b0;
InProgress_q3 <= 1'b0;
LatchByte0_d <= 1'b0;
LatchByte1_d <= 1'b0;
LatchByte <= 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= WCtrlDataStart;
WCtrlDataStart_q2 <= WCtrlDataStart_q1;
RStatStart_q1 <= RStatStart;
RStatStart_q2 <= RStatStart_q1;
LatchByte[0] <= LatchByte0_d;
LatchByte[1] <= LatchByte1_d;
LatchByte0_d <= LatchByte0_d2;
LatchByte1_d <= LatchByte1_d2;
InProgress_q1 <= InProgress;
InProgress_q2 <= InProgress_q1;
InProgress_q3 <= InProgress_q2;
end
end
end
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= 1'b0;
WriteOp <= 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= WriteDataOp;
InProgress <= 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= 1'b0;
WriteOp <= 1'b0;
end
end
end
end
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= 7'h21;
else
BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= 7'h0;
end
end
end
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule | 1 |
141,620 | data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/tx_dual_port_ram_8bit.v | 95,888,822 | tx_dual_port_ram_8bit.v | v | 50 | 79 | [] | [] | [] | [(4, 49)] | null | data/verilator_xmls/cbc721c4-6f58-4925-8f25-71d0efa13045.xml | null | 312,197 | module | module tx_dual_port_ram_8bit
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
input [(DATA_WIDTH-1):0] data_a, data_b,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [(DATA_WIDTH-1):0] q_a, q_b
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps/tx_data.txt", ram);
end
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule | module tx_dual_port_ram_8bit
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
input [(DATA_WIDTH-1):0] data_a, data_b,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [(DATA_WIDTH-1):0] q_a, q_b
); |
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps/tx_data.txt", ram);
end
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule | 1 |
141,621 | data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_crc.v | 95,888,822 | fb_crc.v | v | 77 | 72 | [] | [] | [] | [(55, 125)] | null | null | 1: b'%Error: data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_crc.v:4: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n' | 312,198 | module | module fb_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [7:0] Crc;
output CrcError;
reg [7:0] Crc;
wire [7:0] Crc1;
wire [7:0] Crc2;
wire [7:0] Crc3;
wire [7:0] Crc4;
assign Crc1[7] = Crc[6] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[6] = Crc[5] ;
assign Crc1[5] = Crc[4] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[4] = Crc[3] ;
assign Crc1[3] = Crc[2] ;
assign Crc1[2] = Crc[1] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[1] = Crc[0] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[0] = ((Data[3] ^ Crc[7]) & Enable);
assign Crc2[7] = Crc1[6] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[6] = Crc1[5] ;
assign Crc2[5] = Crc1[4] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[4] = Crc1[3] ;
assign Crc2[3] = Crc1[2] ;
assign Crc2[2] = Crc1[1] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[1] = Crc1[0] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[0] = ((Data[2] ^ Crc1[7]) & Enable);
assign Crc3[7] = Crc2[6] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[6] = Crc2[5] ;
assign Crc3[5] = Crc2[4] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[4] = Crc2[3] ;
assign Crc3[3] = Crc2[2] ;
assign Crc3[2] = Crc2[1] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[1] = Crc2[0] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[0] = ((Data[1] ^ Crc2[7]) & Enable);
assign Crc4[7] = Crc3[6] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[6] = Crc3[5] ;
assign Crc4[5] = Crc3[4] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[4] = Crc3[3] ;
assign Crc4[3] = Crc3[2] ;
assign Crc4[2] = Crc3[1] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[1] = Crc3[0] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[0] = ((Data[0] ^ Crc3[7]) & Enable);
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= 8'hff;
else
if(Initialize)
Crc <= 8'hff;
else
Crc <= Crc4;
end
assign CrcError = Crc[7:0] != 32'h7b;
endmodule | module fb_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); |
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [7:0] Crc;
output CrcError;
reg [7:0] Crc;
wire [7:0] Crc1;
wire [7:0] Crc2;
wire [7:0] Crc3;
wire [7:0] Crc4;
assign Crc1[7] = Crc[6] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[6] = Crc[5] ;
assign Crc1[5] = Crc[4] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[4] = Crc[3] ;
assign Crc1[3] = Crc[2] ;
assign Crc1[2] = Crc[1] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[1] = Crc[0] ^ ((Data[3] ^ Crc[7]) & Enable);
assign Crc1[0] = ((Data[3] ^ Crc[7]) & Enable);
assign Crc2[7] = Crc1[6] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[6] = Crc1[5] ;
assign Crc2[5] = Crc1[4] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[4] = Crc1[3] ;
assign Crc2[3] = Crc1[2] ;
assign Crc2[2] = Crc1[1] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[1] = Crc1[0] ^ ((Data[2] ^ Crc1[7]) & Enable);
assign Crc2[0] = ((Data[2] ^ Crc1[7]) & Enable);
assign Crc3[7] = Crc2[6] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[6] = Crc2[5] ;
assign Crc3[5] = Crc2[4] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[4] = Crc2[3] ;
assign Crc3[3] = Crc2[2] ;
assign Crc3[2] = Crc2[1] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[1] = Crc2[0] ^ ((Data[1] ^ Crc2[7]) & Enable);
assign Crc3[0] = ((Data[1] ^ Crc2[7]) & Enable);
assign Crc4[7] = Crc3[6] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[6] = Crc3[5] ;
assign Crc4[5] = Crc3[4] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[4] = Crc3[3] ;
assign Crc4[3] = Crc3[2] ;
assign Crc4[2] = Crc3[1] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[1] = Crc3[0] ^ ((Data[0] ^ Crc3[7]) & Enable);
assign Crc4[0] = ((Data[0] ^ Crc3[7]) & Enable);
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= 8'hff;
else
if(Initialize)
Crc <= 8'hff;
else
Crc <= Crc4;
end
assign CrcError = Crc[7:0] != 32'h7b;
endmodule | 1 |
141,623 | data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_rxmac.v | 95,888,822 | fb_rxmac.v | v | 361 | 225 | [] | [] | [] | [(54, 409)] | null | null | 1: b'%Error: data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_rxmac.v:2: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n' | 312,201 | module | module fb_rxmac (MRxClk, MRxDV, MRxD, Reset, inLastSlaveIDPlus1,
RxData, RxValid, RxRamAddr, LastSlaveIDPlus1, DelaySum,
NumbFrameReceived, DistFrameReceived, DelayFrameReceived, DataFrameReceived, DelayDistFrameReceived,
StateIdle, StateFFS, StatePreamble, StateNumb, StateDist, StateDelay, StateData, StateFrmCrc,debug
);
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Reset;
input [7:0] inLastSlaveIDPlus1;
output [7:0] RxData;
output RxValid;
output [7:0] RxRamAddr;
output [7:0] LastSlaveIDPlus1;
output [15:0] DelaySum;
output NumbFrameReceived;
output DistFrameReceived;
output DelayFrameReceived;
output DataFrameReceived;
output DelayDistFrameReceived;
output StateIdle;
output StateFFS;
output StatePreamble;
output [1:0] StateNumb;
output [1:0] StateDist;
output [1:0] StateDelay;
output [1:0] StateData;
output StateFrmCrc;
output debug;
reg debug;
reg [7:0] RxData;
reg RxValid;
reg RegNumbSoC;
reg RegDistSoC;
reg RegDelaySoC;
reg RegDelayDistSoC;
reg RegDataSoC;
reg NumbFrameReceived;
reg DistFrameReceived;
reg DelayFrameReceived;
reg DataFrameReceived;
reg DelayDistFrameReceived;
reg [7:0] LatchedByte;
reg [7:0] LastSlaveIDPlus1;
reg [15:0] DelaySum;
reg [15:0] DelaySumCnt;
reg RegFrmCrcError;
reg [15:0] RegTotalFrmNibbleCnt;
wire [7:0] FrmCrc;
wire TotalRecvNibCntEq0;
wire [15:0] TotalRecvNibCnt;
wire [7: 0] RxRamAddr;
wire DelayFrameEnd;
wire DataFrameEnd;
wire FrmCrcStateEnd;
wire [3:0] FrmCrcNibCnt;
wire [7: 0] SlaveDataNibbleCnt;
wire MRxDEq5;
wire MRxDEqNumbSoC;
wire MRxDEqDataSoC;
wire MRxDEqDistSoC;
wire MRxDEqDelaySoC;
wire MRxDEqDelayDistSoC;
wire GreatEq5thNibble;
wire BeforeFrameCrc;
wire BeforeFrmCrcAtDelayFrm;
wire [7:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
assign SlaveDataNibbleCnt = 8'd4;
assign MRxDEq5 = MRxD == 4'd5;
assign MRxDEqDelayDistSoC = MRxD == 4'd2;
assign MRxDEqDelaySoC = MRxD == 4'd3;
assign MRxDEqDistSoC = MRxD == 4'd4;
assign MRxDEqNumbSoC = MRxD == 4'd6;
assign MRxDEqDataSoC = MRxD == 4'd7;
assign DelayFrameEnd = TotalRecvNibCnt == 15'd4 + 15'd2*inLastSlaveIDPlus1 - 16'd1;
assign DataFrameEnd = TotalRecvNibCnt == RegTotalFrmNibbleCnt - 16'd1;
assign GreatEq5thNibble = TotalRecvNibCnt > 16'd4;
assign BeforeFrameCrc = TotalRecvNibCnt <= RegTotalFrmNibbleCnt;
assign BeforeFrmCrcAtDelayFrm = TotalRecvNibCnt <= 15'd4 + 15'd2*inLastSlaveIDPlus1;
fb_rxcounters fb_rxcounters_ins(
.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.RxValid(RxValid),
.StateIdle(StateIdle),
.StateFFS(StateFFS),
.StatePreamble(StatePreamble),
.StateData(StateData),
.StateFrmCrc(StateFrmCrc),
.MRxDEqDataSoC(MRxDEqDataSoC),
.TotalRecvNibCntEq0(TotalRecvNibCntEq0),
.TotalRecvNibCnt(TotalRecvNibCnt),
.RxRamAddr(RxRamAddr),
.FrmCrcNibCnt(FrmCrcNibCnt),
.FrmCrcStateEnd(FrmCrcStateEnd)
);
fb_rxstatem rxstatem_ins
(.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.MRxDEqDataSoC(MRxDEqDataSoC),
.MRxDEqNumbSoC(MRxDEqNumbSoC),
.MRxDEqDistSoC(MRxDEqDistSoC),
.MRxDEqDelaySoC(MRxDEqDelaySoC),
.MRxDEqDelayDistSoC(MRxDEqDelayDistSoC),
.MRxDEq5(MRxDEq5),
.DelayFrameEnd(DelayFrameEnd),
.DataFrameEnd(DataFrameEnd),
.FrmCrcStateEnd(FrmCrcStateEnd),
.StateIdle(StateIdle),
.StateFFS(StateFFS),
.StatePreamble(StatePreamble),
.StateNumb(StateNumb),
.StateDist(StateDist),
.StateDelay(StateDelay),
.StateData(StateData),
.StateFrmCrc(StateFrmCrc)
);
always @ (LastSlaveIDPlus1 or SlaveDataNibbleCnt or Reset)
begin
if(Reset)
RegTotalFrmNibbleCnt = 0 ;
else
RegTotalFrmNibbleCnt = ((SlaveDataNibbleCnt + 8'd2 ) * 8'd2) + 8'd4;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
NumbFrameReceived <= 1'b0 ;
DistFrameReceived <= 1'b0 ;
DelayFrameReceived <= 1'b0 ;
DataFrameReceived <= 1'b0 ;
DelayDistFrameReceived <= 1'b0 ;
end
else
if (StateFrmCrc & FrmCrcStateEnd)
begin
if (RegNumbSoC)
NumbFrameReceived <= 1'b1;
else
if (RegDistSoC)
DistFrameReceived <= 1'b1;
else
if (RegDelaySoC)
DelayFrameReceived<= 1'b1;
else
if (RegDataSoC)
DataFrameReceived <= 1'b1;
else
if (RegDelayDistSoC)
DelayDistFrameReceived <= 1'b1;
end
else
if (StateIdle)
begin
NumbFrameReceived <= 1'b0;
DistFrameReceived <= 1'b0;
DelayFrameReceived <= 1'b0;
DataFrameReceived <= 1'b0;
DelayDistFrameReceived <= 1'b0 ;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RegDataSoC <= 1'b0;
RegNumbSoC <= 1'b0;
RegDistSoC <= 1'b0;
RegDelaySoC <= 1'b0;
RegDelayDistSoC <= 1'b0;
end
else
if (StatePreamble)
begin
if (MRxDEqDataSoC)
RegDataSoC <= 1'b1;
else
if (MRxDEqNumbSoC)
RegNumbSoC <= 1'b1;
else
if (MRxDEqDistSoC)
RegDistSoC <= 1'b1;
else
if (MRxDEqDelaySoC)
RegDelaySoC<= 1'b1;
else
if (MRxDEqDelayDistSoC)
RegDelayDistSoC <= 1'b1;
end
else
if (StateIdle)
begin
RegDataSoC <= 1'b0;
RegNumbSoC <= 1'b0;
RegDistSoC <= 1'b0;
RegDelaySoC <= 1'b0;
RegDelayDistSoC <= 1'b0;
end
end
assign GenerateRxValid = (RegDataSoC & ~TotalRecvNibCnt[0] & GreatEq5thNibble & BeforeFrameCrc )| ( RegNumbSoC & (TotalRecvNibCnt == 16'd6)) | ( RegDelaySoC & ~TotalRecvNibCnt[0] & GreatEq5thNibble & BeforeFrmCrcAtDelayFrm);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
LatchedByte[7:0] <= 8'h0;
RxData[7:0] <= 8'h0;
LastSlaveIDPlus1 <= 8'h0;
DelaySumCnt <= 16'h0;
end
else
begin
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
if(GenerateRxValid)
begin
if (RegNumbSoC)
begin
LastSlaveIDPlus1 <= LatchedByte[7:0];
end
else
if (RegDelaySoC)
begin
DelaySumCnt <= DelaySumCnt + LatchedByte[7:0];
end
else
RxData[7:0] <= LatchedByte[7:0];
end
else
begin
if (~RegDelaySoC)
DelaySumCnt <= 16'd0;
RxData[7:0] <= 8'h0;
end
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
DelaySum <= 16'b0;
end
else
begin
if ( RegDelaySoC & FrmCrcStateEnd)
DelaySum <= DelaySumCnt ;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
debug <= 1'b0;
end
else
begin
if ( DelaySumCnt != 16'b0)
debug <= 1'b1 ;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid <= 1'b0;
end
else
begin
if ( ~RegNumbSoC & ~RegDistSoC & ~RegDelaySoC)
RxValid <= GenerateRxValid ;
end
end
wire Enable_FrmCrc;
wire [3:0] Data_FrmCrc;
wire Initialize_FrmCrc;
assign Enable_FrmCrc = ~StateFrmCrc;
assign Data_FrmCrc = MRxD;
assign Initialize_FrmCrc = StateIdle & ~MRxDV;
fb_crc framecrc
(
.Clk(MRxClk),
.Reset(Reset),
.Data(Data_FrmCrc),
.Enable(Enable_FrmCrc),
.Initialize(Initialize_FrmCrc),
.Crc(FrmCrc)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RegFrmCrcError <= 1'b0;
else
if (StateFrmCrc)
begin
if ( {~FrmCrc[4], ~FrmCrc[5], ~FrmCrc[6], ~FrmCrc[7]} != MRxD)
RegFrmCrcError <= 1'b1 ;
end
else
if (StateIdle)
RegFrmCrcError <= 1'b0;
end
endmodule | module fb_rxmac (MRxClk, MRxDV, MRxD, Reset, inLastSlaveIDPlus1,
RxData, RxValid, RxRamAddr, LastSlaveIDPlus1, DelaySum,
NumbFrameReceived, DistFrameReceived, DelayFrameReceived, DataFrameReceived, DelayDistFrameReceived,
StateIdle, StateFFS, StatePreamble, StateNumb, StateDist, StateDelay, StateData, StateFrmCrc,debug
); |
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Reset;
input [7:0] inLastSlaveIDPlus1;
output [7:0] RxData;
output RxValid;
output [7:0] RxRamAddr;
output [7:0] LastSlaveIDPlus1;
output [15:0] DelaySum;
output NumbFrameReceived;
output DistFrameReceived;
output DelayFrameReceived;
output DataFrameReceived;
output DelayDistFrameReceived;
output StateIdle;
output StateFFS;
output StatePreamble;
output [1:0] StateNumb;
output [1:0] StateDist;
output [1:0] StateDelay;
output [1:0] StateData;
output StateFrmCrc;
output debug;
reg debug;
reg [7:0] RxData;
reg RxValid;
reg RegNumbSoC;
reg RegDistSoC;
reg RegDelaySoC;
reg RegDelayDistSoC;
reg RegDataSoC;
reg NumbFrameReceived;
reg DistFrameReceived;
reg DelayFrameReceived;
reg DataFrameReceived;
reg DelayDistFrameReceived;
reg [7:0] LatchedByte;
reg [7:0] LastSlaveIDPlus1;
reg [15:0] DelaySum;
reg [15:0] DelaySumCnt;
reg RegFrmCrcError;
reg [15:0] RegTotalFrmNibbleCnt;
wire [7:0] FrmCrc;
wire TotalRecvNibCntEq0;
wire [15:0] TotalRecvNibCnt;
wire [7: 0] RxRamAddr;
wire DelayFrameEnd;
wire DataFrameEnd;
wire FrmCrcStateEnd;
wire [3:0] FrmCrcNibCnt;
wire [7: 0] SlaveDataNibbleCnt;
wire MRxDEq5;
wire MRxDEqNumbSoC;
wire MRxDEqDataSoC;
wire MRxDEqDistSoC;
wire MRxDEqDelaySoC;
wire MRxDEqDelayDistSoC;
wire GreatEq5thNibble;
wire BeforeFrameCrc;
wire BeforeFrmCrcAtDelayFrm;
wire [7:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
assign SlaveDataNibbleCnt = 8'd4;
assign MRxDEq5 = MRxD == 4'd5;
assign MRxDEqDelayDistSoC = MRxD == 4'd2;
assign MRxDEqDelaySoC = MRxD == 4'd3;
assign MRxDEqDistSoC = MRxD == 4'd4;
assign MRxDEqNumbSoC = MRxD == 4'd6;
assign MRxDEqDataSoC = MRxD == 4'd7;
assign DelayFrameEnd = TotalRecvNibCnt == 15'd4 + 15'd2*inLastSlaveIDPlus1 - 16'd1;
assign DataFrameEnd = TotalRecvNibCnt == RegTotalFrmNibbleCnt - 16'd1;
assign GreatEq5thNibble = TotalRecvNibCnt > 16'd4;
assign BeforeFrameCrc = TotalRecvNibCnt <= RegTotalFrmNibbleCnt;
assign BeforeFrmCrcAtDelayFrm = TotalRecvNibCnt <= 15'd4 + 15'd2*inLastSlaveIDPlus1;
fb_rxcounters fb_rxcounters_ins(
.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.RxValid(RxValid),
.StateIdle(StateIdle),
.StateFFS(StateFFS),
.StatePreamble(StatePreamble),
.StateData(StateData),
.StateFrmCrc(StateFrmCrc),
.MRxDEqDataSoC(MRxDEqDataSoC),
.TotalRecvNibCntEq0(TotalRecvNibCntEq0),
.TotalRecvNibCnt(TotalRecvNibCnt),
.RxRamAddr(RxRamAddr),
.FrmCrcNibCnt(FrmCrcNibCnt),
.FrmCrcStateEnd(FrmCrcStateEnd)
);
fb_rxstatem rxstatem_ins
(.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.MRxDEqDataSoC(MRxDEqDataSoC),
.MRxDEqNumbSoC(MRxDEqNumbSoC),
.MRxDEqDistSoC(MRxDEqDistSoC),
.MRxDEqDelaySoC(MRxDEqDelaySoC),
.MRxDEqDelayDistSoC(MRxDEqDelayDistSoC),
.MRxDEq5(MRxDEq5),
.DelayFrameEnd(DelayFrameEnd),
.DataFrameEnd(DataFrameEnd),
.FrmCrcStateEnd(FrmCrcStateEnd),
.StateIdle(StateIdle),
.StateFFS(StateFFS),
.StatePreamble(StatePreamble),
.StateNumb(StateNumb),
.StateDist(StateDist),
.StateDelay(StateDelay),
.StateData(StateData),
.StateFrmCrc(StateFrmCrc)
);
always @ (LastSlaveIDPlus1 or SlaveDataNibbleCnt or Reset)
begin
if(Reset)
RegTotalFrmNibbleCnt = 0 ;
else
RegTotalFrmNibbleCnt = ((SlaveDataNibbleCnt + 8'd2 ) * 8'd2) + 8'd4;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
NumbFrameReceived <= 1'b0 ;
DistFrameReceived <= 1'b0 ;
DelayFrameReceived <= 1'b0 ;
DataFrameReceived <= 1'b0 ;
DelayDistFrameReceived <= 1'b0 ;
end
else
if (StateFrmCrc & FrmCrcStateEnd)
begin
if (RegNumbSoC)
NumbFrameReceived <= 1'b1;
else
if (RegDistSoC)
DistFrameReceived <= 1'b1;
else
if (RegDelaySoC)
DelayFrameReceived<= 1'b1;
else
if (RegDataSoC)
DataFrameReceived <= 1'b1;
else
if (RegDelayDistSoC)
DelayDistFrameReceived <= 1'b1;
end
else
if (StateIdle)
begin
NumbFrameReceived <= 1'b0;
DistFrameReceived <= 1'b0;
DelayFrameReceived <= 1'b0;
DataFrameReceived <= 1'b0;
DelayDistFrameReceived <= 1'b0 ;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RegDataSoC <= 1'b0;
RegNumbSoC <= 1'b0;
RegDistSoC <= 1'b0;
RegDelaySoC <= 1'b0;
RegDelayDistSoC <= 1'b0;
end
else
if (StatePreamble)
begin
if (MRxDEqDataSoC)
RegDataSoC <= 1'b1;
else
if (MRxDEqNumbSoC)
RegNumbSoC <= 1'b1;
else
if (MRxDEqDistSoC)
RegDistSoC <= 1'b1;
else
if (MRxDEqDelaySoC)
RegDelaySoC<= 1'b1;
else
if (MRxDEqDelayDistSoC)
RegDelayDistSoC <= 1'b1;
end
else
if (StateIdle)
begin
RegDataSoC <= 1'b0;
RegNumbSoC <= 1'b0;
RegDistSoC <= 1'b0;
RegDelaySoC <= 1'b0;
RegDelayDistSoC <= 1'b0;
end
end
assign GenerateRxValid = (RegDataSoC & ~TotalRecvNibCnt[0] & GreatEq5thNibble & BeforeFrameCrc )| ( RegNumbSoC & (TotalRecvNibCnt == 16'd6)) | ( RegDelaySoC & ~TotalRecvNibCnt[0] & GreatEq5thNibble & BeforeFrmCrcAtDelayFrm);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
LatchedByte[7:0] <= 8'h0;
RxData[7:0] <= 8'h0;
LastSlaveIDPlus1 <= 8'h0;
DelaySumCnt <= 16'h0;
end
else
begin
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
if(GenerateRxValid)
begin
if (RegNumbSoC)
begin
LastSlaveIDPlus1 <= LatchedByte[7:0];
end
else
if (RegDelaySoC)
begin
DelaySumCnt <= DelaySumCnt + LatchedByte[7:0];
end
else
RxData[7:0] <= LatchedByte[7:0];
end
else
begin
if (~RegDelaySoC)
DelaySumCnt <= 16'd0;
RxData[7:0] <= 8'h0;
end
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
DelaySum <= 16'b0;
end
else
begin
if ( RegDelaySoC & FrmCrcStateEnd)
DelaySum <= DelaySumCnt ;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
debug <= 1'b0;
end
else
begin
if ( DelaySumCnt != 16'b0)
debug <= 1'b1 ;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid <= 1'b0;
end
else
begin
if ( ~RegNumbSoC & ~RegDistSoC & ~RegDelaySoC)
RxValid <= GenerateRxValid ;
end
end
wire Enable_FrmCrc;
wire [3:0] Data_FrmCrc;
wire Initialize_FrmCrc;
assign Enable_FrmCrc = ~StateFrmCrc;
assign Data_FrmCrc = MRxD;
assign Initialize_FrmCrc = StateIdle & ~MRxDV;
fb_crc framecrc
(
.Clk(MRxClk),
.Reset(Reset),
.Data(Data_FrmCrc),
.Enable(Enable_FrmCrc),
.Initialize(Initialize_FrmCrc),
.Crc(FrmCrc)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RegFrmCrcError <= 1'b0;
else
if (StateFrmCrc)
begin
if ( {~FrmCrc[4], ~FrmCrc[5], ~FrmCrc[6], ~FrmCrc[7]} != MRxD)
RegFrmCrcError <= 1'b1 ;
end
else
if (StateIdle)
RegFrmCrcError <= 1'b0;
end
endmodule | 1 |
141,627 | data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_slave_statem.v | 95,888,822 | fb_slave_statem.v | v | 126 | 103 | [] | [] | [] | null | line:55: before: "SlaveDataEnd" | null | 1: b'%Error: data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_slave_statem.v:2: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n' | 312,205 | module | module fb_slave_statem (MRxClk, Reset, MRxDV, MRxDEqDataSoC, MRxDEq5, SlaveDataStart
SlaveDataEnd, SlaveCrcEnd, LastSlave, DataFrameEnd, FrmCrcStateEnd,
StateIdle, StatePreamble, StateFFS, StateData, StateSlaveData,
StateSlaveCrc, StateFrmCrc
);
input MRxClk;
input Reset;
input MRxDV;
input MRxDEq5;
input MRxDEqDataSoC;
input SlaveDataStart;
input SlaveDataEnd;
input SlaveCrcEnd;
input LastSlave;
input DataFrameEnd;
input FrmCrcStateEnd;
output StateIdle;
output StateFFS;
output StatePreamble;
output StateData;
output StateSlaveData;
output StateSlaveCrc;
output StateFrmCrc;
reg StateIdle;
reg StateFFS;
reg StatePreamble;
reg StateData;
reg StateSlaveData;
reg StateSlaveCrc;
reg StateFrmCrc;
wire StartIdle;
wire StartFFS;
wire StartPreamble;
wire StartData;
wire StartSlaveData;
wire StartSlaveCrc;
wire StartFrmCrc;
assign StartIdle = ~MRxDV & ( StatePreamble | StateFFS ) | (StateFrmCrc & FrmCrcStateEnd);
assign StartFFS = MRxDV & ~MRxDEq5 & StateIdle;
assign StartPreamble = MRxDV & MRxDEq5 & (StateIdle | StateFFS);
assign StartData = (MRxDV & StatePreamble & MRxDEqDataSoC)|(StateSlaveCrc & SlaveCrcEnd & ~LastSlave);
assign StartSlaveData[0] = StateData & SlaveDataStart | StateSlaveData[1] & ~SlaveDataEnd;;
assign StartSlaveData[1] = StateSlaveData[0];
assign StartSlaveCrc = StateSlaveData[1] & SlaveDataEnd;
assign StartFrmCrc = StateSlaveCrc & SlaveCrcEnd & LastSlave | StateData & DataFrameEnd;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= 1'b1;
StateFFS <= 1'b0;
StatePreamble <= 1'b0;
StateData <= 1'b0;
StateSlave <= 1'b0;
StateSlaveCrc <= 1'b0;
StateFrmCrc <= 1'b0;
end
else
begin
if(StartPreamble | StartFFS)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartPreamble | StartIdle)
StateFFS <= 1'b0;
else
if(StartFFS)
StateFFS <= 1'b1;
if(StartData)
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartSlaveData | StartFrmCrc)
StateData <= 1'b0;
else
if(StartData)
StateData <= 1'b1;
if(StartSlaveCrc)
StateSlaveData <= 1'b0;
else
if(StartSlaveData)
StateSlaveData <= 1'b1;
if(StartData | StartFrmCrc)
StateSlaveCrc <= 1'b0;
else
if(StartSlaveCrc)
StateSlaveCrc <= 1'b1;
if(StartIdle)
StateFrmCrc <= 1'b0;
else
if(StartFrmCrc)
StateFrmCrc <= 1'b1;
end
end
endmodule | module fb_slave_statem (MRxClk, Reset, MRxDV, MRxDEqDataSoC, MRxDEq5, SlaveDataStart
SlaveDataEnd, SlaveCrcEnd, LastSlave, DataFrameEnd, FrmCrcStateEnd,
StateIdle, StatePreamble, StateFFS, StateData, StateSlaveData,
StateSlaveCrc, StateFrmCrc
); |
input MRxClk;
input Reset;
input MRxDV;
input MRxDEq5;
input MRxDEqDataSoC;
input SlaveDataStart;
input SlaveDataEnd;
input SlaveCrcEnd;
input LastSlave;
input DataFrameEnd;
input FrmCrcStateEnd;
output StateIdle;
output StateFFS;
output StatePreamble;
output StateData;
output StateSlaveData;
output StateSlaveCrc;
output StateFrmCrc;
reg StateIdle;
reg StateFFS;
reg StatePreamble;
reg StateData;
reg StateSlaveData;
reg StateSlaveCrc;
reg StateFrmCrc;
wire StartIdle;
wire StartFFS;
wire StartPreamble;
wire StartData;
wire StartSlaveData;
wire StartSlaveCrc;
wire StartFrmCrc;
assign StartIdle = ~MRxDV & ( StatePreamble | StateFFS ) | (StateFrmCrc & FrmCrcStateEnd);
assign StartFFS = MRxDV & ~MRxDEq5 & StateIdle;
assign StartPreamble = MRxDV & MRxDEq5 & (StateIdle | StateFFS);
assign StartData = (MRxDV & StatePreamble & MRxDEqDataSoC)|(StateSlaveCrc & SlaveCrcEnd & ~LastSlave);
assign StartSlaveData[0] = StateData & SlaveDataStart | StateSlaveData[1] & ~SlaveDataEnd;;
assign StartSlaveData[1] = StateSlaveData[0];
assign StartSlaveCrc = StateSlaveData[1] & SlaveDataEnd;
assign StartFrmCrc = StateSlaveCrc & SlaveCrcEnd & LastSlave | StateData & DataFrameEnd;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= 1'b1;
StateFFS <= 1'b0;
StatePreamble <= 1'b0;
StateData <= 1'b0;
StateSlave <= 1'b0;
StateSlaveCrc <= 1'b0;
StateFrmCrc <= 1'b0;
end
else
begin
if(StartPreamble | StartFFS)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartPreamble | StartIdle)
StateFFS <= 1'b0;
else
if(StartFFS)
StateFFS <= 1'b1;
if(StartData)
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartSlaveData | StartFrmCrc)
StateData <= 1'b0;
else
if(StartData)
StateData <= 1'b1;
if(StartSlaveCrc)
StateSlaveData <= 1'b0;
else
if(StartSlaveData)
StateSlaveData <= 1'b1;
if(StartData | StartFrmCrc)
StateSlaveCrc <= 1'b0;
else
if(StartSlaveCrc)
StateSlaveCrc <= 1'b1;
if(StartIdle)
StateFrmCrc <= 1'b0;
else
if(StartFrmCrc)
StateFrmCrc <= 1'b1;
end
end
endmodule | 1 |
141,629 | data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_txcounters.v | 95,888,822 | fb_txcounters.v | v | 173 | 143 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus/fb_txcounters.v:3: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.v\n data/full_repos/permissive/95888822/DE2_115_MASTER/source_code/freedm_bus,data/full_repos/permissive/95888822/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n' | 312,207 | module | module fb_txcounters (MTxClk, Reset,
StateIdle, StatePreamble, StateSoC, StateNumb, StateDist, StateDelay, StateDelayDist,
StateData, StateCrc, StateFrmCrc,
StartData, CrcNibCnt,
TotalNibCnt, NibCnt, CrcStateEnd, PreambleStateEnd, FrmCrcStateEnd, TxRamAddr
);
input MTxClk;
input Reset;
input StateIdle;
input StatePreamble;
input StateSoC;
input StateNumb;
input [1:0] StateDist;
input StateDelay;
input [1:0] StateDelayDist;
input [1:0] StateData;
input [1:0] StartData;
input StateCrc;
input StateFrmCrc;
output [3: 0] CrcNibCnt;
output [15:0] TotalNibCnt;
output [15:0] NibCnt;
output CrcStateEnd;
output PreambleStateEnd;
output FrmCrcStateEnd;
output [7: 0] TxRamAddr;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetTotalNibCnt;
wire IncrementTotalNibCnt;
reg [15:0] TotalNibCnt;
reg [15:0] NibCnt;
reg [3: 0] CrcNibCnt;
reg [3: 0] PreambleNibCnt;
reg [3: 0] FrmCrcNibCnt;
reg [7: 0] TxRamAddr;
assign IncrementNibCnt = (|StateData) ;
assign ResetNibCnt = StateIdle | StateSoC & StartData[0] | StateCrc & StartData[0]| StateCrc;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 16'd1;
end
end
assign IncrementTotalNibCnt = StatePreamble | StateSoC | StateNumb | (|StateDist) | StateDelay | (|StateDelayDist)| (|StateData) | StateCrc ;
assign ResetTotalNibCnt = StateIdle;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TotalNibCnt <= 16'h0;
else
begin
if(ResetTotalNibCnt)
TotalNibCnt <= 16'h0;
else
if(IncrementTotalNibCnt)
TotalNibCnt <= TotalNibCnt + 16'd1;
end
end
wire IncrementCrcNibCnt;
wire ResetCrcNibCnt;
assign IncrementCrcNibCnt = StateCrc ;
assign ResetCrcNibCnt = (|StateData);
assign CrcStateEnd = CrcNibCnt[0] ;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CrcNibCnt <= 4'b0;
else
begin
if(ResetCrcNibCnt)
CrcNibCnt <= 4'b0;
else
if(IncrementCrcNibCnt)
CrcNibCnt <= CrcNibCnt + 4'b0001;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateCrc ;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
wire IncrementPreambleNibCnt;
wire ResetPreambleNibCnt;
assign IncrementPreambleNibCnt = StatePreamble ;
assign ResetPreambleNibCnt = StateIdle;
assign PreambleStateEnd = (PreambleNibCnt == 4'b0010);
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
PreambleNibCnt <= 4'b0;
else
begin
if(ResetPreambleNibCnt)
PreambleNibCnt <= 4'b0;
else
if(IncrementPreambleNibCnt)
PreambleNibCnt <= PreambleNibCnt + 4'b0001;
end
end
wire IncrementTxRamAddr;
wire ResetTxRamAddr;
assign IncrementTxRamAddr = StateData[0];
assign ResetTxRamAddr = StateIdle | StatePreamble | StateSoC;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRamAddr <= 8'b0;
else
begin
if(ResetTxRamAddr)
TxRamAddr <= 8'b0;
else
if(IncrementTxRamAddr)
TxRamAddr <= TxRamAddr + 8'b0001;
end
end
endmodule | module fb_txcounters (MTxClk, Reset,
StateIdle, StatePreamble, StateSoC, StateNumb, StateDist, StateDelay, StateDelayDist,
StateData, StateCrc, StateFrmCrc,
StartData, CrcNibCnt,
TotalNibCnt, NibCnt, CrcStateEnd, PreambleStateEnd, FrmCrcStateEnd, TxRamAddr
); |
input MTxClk;
input Reset;
input StateIdle;
input StatePreamble;
input StateSoC;
input StateNumb;
input [1:0] StateDist;
input StateDelay;
input [1:0] StateDelayDist;
input [1:0] StateData;
input [1:0] StartData;
input StateCrc;
input StateFrmCrc;
output [3: 0] CrcNibCnt;
output [15:0] TotalNibCnt;
output [15:0] NibCnt;
output CrcStateEnd;
output PreambleStateEnd;
output FrmCrcStateEnd;
output [7: 0] TxRamAddr;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetTotalNibCnt;
wire IncrementTotalNibCnt;
reg [15:0] TotalNibCnt;
reg [15:0] NibCnt;
reg [3: 0] CrcNibCnt;
reg [3: 0] PreambleNibCnt;
reg [3: 0] FrmCrcNibCnt;
reg [7: 0] TxRamAddr;
assign IncrementNibCnt = (|StateData) ;
assign ResetNibCnt = StateIdle | StateSoC & StartData[0] | StateCrc & StartData[0]| StateCrc;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 16'd1;
end
end
assign IncrementTotalNibCnt = StatePreamble | StateSoC | StateNumb | (|StateDist) | StateDelay | (|StateDelayDist)| (|StateData) | StateCrc ;
assign ResetTotalNibCnt = StateIdle;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TotalNibCnt <= 16'h0;
else
begin
if(ResetTotalNibCnt)
TotalNibCnt <= 16'h0;
else
if(IncrementTotalNibCnt)
TotalNibCnt <= TotalNibCnt + 16'd1;
end
end
wire IncrementCrcNibCnt;
wire ResetCrcNibCnt;
assign IncrementCrcNibCnt = StateCrc ;
assign ResetCrcNibCnt = (|StateData);
assign CrcStateEnd = CrcNibCnt[0] ;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CrcNibCnt <= 4'b0;
else
begin
if(ResetCrcNibCnt)
CrcNibCnt <= 4'b0;
else
if(IncrementCrcNibCnt)
CrcNibCnt <= CrcNibCnt + 4'b0001;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateCrc ;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
wire IncrementPreambleNibCnt;
wire ResetPreambleNibCnt;
assign IncrementPreambleNibCnt = StatePreamble ;
assign ResetPreambleNibCnt = StateIdle;
assign PreambleStateEnd = (PreambleNibCnt == 4'b0010);
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
PreambleNibCnt <= 4'b0;
else
begin
if(ResetPreambleNibCnt)
PreambleNibCnt <= 4'b0;
else
if(IncrementPreambleNibCnt)
PreambleNibCnt <= PreambleNibCnt + 4'b0001;
end
end
wire IncrementTxRamAddr;
wire ResetTxRamAddr;
assign IncrementTxRamAddr = StateData[0];
assign ResetTxRamAddr = StateIdle | StatePreamble | StateSoC;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRamAddr <= 8'b0;
else
begin
if(ResetTxRamAddr)
TxRamAddr <= 8'b0;
else
if(IncrementTxRamAddr)
TxRamAddr <= TxRamAddr + 8'b0001;
end
end
endmodule | 1 |
141,635 | data/full_repos/permissive/95888822/DE2_115_SLAVE/source_code/SynchModule.v | 95,888,822 | SynchModule.v | v | 34 | 101 | [] | [] | [] | [(1, 34)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/95888822/DE2_115_SLAVE/source_code/SynchModule.v:18: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'LastSlaveIDPlus1\' generates 8 bits.\n : ... In instance SynchModule\nassign SynchDelay = (LastSlaveIDPlus1 - SlaveID - 8\'d1) * AveSlaveDelay + 32\'d1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95888822/DE2_115_SLAVE/source_code/SynchModule.v:18: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'SlaveID\' generates 8 bits.\n : ... In instance SynchModule\nassign SynchDelay = (LastSlaveIDPlus1 - SlaveID - 8\'d1) * AveSlaveDelay + 32\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95888822/DE2_115_SLAVE/source_code/SynchModule.v:18: Operator SUB expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance SynchModule\nassign SynchDelay = (LastSlaveIDPlus1 - SlaveID - 8\'d1) * AveSlaveDelay + 32\'d1;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 312,227 | module | module SynchModule( Clk_100MHz, Reset, Busy, LastSlaveIDPlus1, SlaveID, AveSlaveDelay, SynchSignal);
input Clk_100MHz;
input Reset;
input Busy;
input [7:0] LastSlaveIDPlus1;
input [7:0] SlaveID;
input [7:0] AveSlaveDelay;
output SynchSignal;
wire [31:0] SynchDelay;
wire SynchSignal;
reg [31:0] SynchDelayCnt;
assign SynchDelay = (LastSlaveIDPlus1 - SlaveID - 8'd1) * AveSlaveDelay + 32'd1;
always @ (posedge Clk_100MHz)
begin
if ( Reset )
SynchDelayCnt <= 32'd0;
else
if (Busy)
SynchDelayCnt <= 32'd0;
else
SynchDelayCnt <= SynchDelayCnt + 32'd1;
end
assign SynchSignal = SynchDelayCnt >= SynchDelay;
endmodule | module SynchModule( Clk_100MHz, Reset, Busy, LastSlaveIDPlus1, SlaveID, AveSlaveDelay, SynchSignal); |
input Clk_100MHz;
input Reset;
input Busy;
input [7:0] LastSlaveIDPlus1;
input [7:0] SlaveID;
input [7:0] AveSlaveDelay;
output SynchSignal;
wire [31:0] SynchDelay;
wire SynchSignal;
reg [31:0] SynchDelayCnt;
assign SynchDelay = (LastSlaveIDPlus1 - SlaveID - 8'd1) * AveSlaveDelay + 32'd1;
always @ (posedge Clk_100MHz)
begin
if ( Reset )
SynchDelayCnt <= 32'd0;
else
if (Busy)
SynchDelayCnt <= 32'd0;
else
SynchDelayCnt <= SynchDelayCnt + 32'd1;
end
assign SynchSignal = SynchDelayCnt >= SynchDelay;
endmodule | 1 |
141,638 | data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v | 95,888,822 | PHYctrl_Slave_MAX10.v | v | 230 | 114 | [] | [] | [] | [(3, 224)] | null | null | 1: b'%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:64: Cannot find file containing module: \'tx_dual_port_ram_8bit\'\n tx_dual_port_ram_8bit tx_dual_port_ram_8bit_ins( \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95888822/MAX10_SLAVE,data/full_repos/permissive/95888822/tx_dual_port_ram_8bit\n data/full_repos/permissive/95888822/MAX10_SLAVE,data/full_repos/permissive/95888822/tx_dual_port_ram_8bit.v\n data/full_repos/permissive/95888822/MAX10_SLAVE,data/full_repos/permissive/95888822/tx_dual_port_ram_8bit.sv\n tx_dual_port_ram_8bit\n tx_dual_port_ram_8bit.v\n tx_dual_port_ram_8bit.sv\n obj_dir/tx_dual_port_ram_8bit\n obj_dir/tx_dual_port_ram_8bit.v\n obj_dir/tx_dual_port_ram_8bit.sv\n%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:84: Cannot find file containing module: \'rx_dual_port_ram_8bit\'\n rx_dual_port_ram_8bit rx_dual_port_ram_8bit_ins(\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:110: Cannot find file containing module: \'rx_data_ram\'\n rx_data_ram rx_data_ram_ins(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:126: Cannot find file containing module: \'pll_25to100MHz\'\n pll_25to100MHz delay_measure_clock\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:139: Cannot find file containing module: \'fb_slave_mac\'\n fb_slave_mac fb_slave_mac_ins\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:178: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s SEL generates 2 bits.\n : ... In instance PHYctrl_Slave_MAX10\n assign readSlaveID = USER_PB[1]?LastSlaveIDPlus1[1:0]:SlaveID[1:0];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:178: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s SEL generates 2 bits.\n : ... In instance PHYctrl_Slave_MAX10\n assign readSlaveID = USER_PB[1]?LastSlaveIDPlus1[1:0]:SlaveID[1:0];\n ^\n%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:187: Cannot find file containing module: \'phyInital\'\n phyInital phyInital_ins0 (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:206: Cannot find file containing module: \'phyIniCommand0\'\n phyIniCommand0 pyhIniCommands (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/95888822/MAX10_SLAVE/PHYctrl_Slave_MAX10.v:211: Cannot find file containing module: \'phyIniCommand0_and\'\n phyIniCommand0_and pyhIniCommands_and (\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n' | 312,241 | module | module PHYctrl_Slave_MAX10 (
input CLOCK_50_MAX10,
input CLOCK_25_MAX10,
input [3: 0] USER_PB,
output [4: 0] USER_LED,
output [1:0] PMODA_IO,
output ENET_MDC,
inout ENET_MDIO,
output ENET0_RESET_N,
output ENET0_GTX_CLK,
input ENET0_TX_CLK,
input ENET0_RX_CLK,
input [3: 0] ENET0_RX_DATA,
input ENET0_RX_DV,
input ENET0_LED_LINK100,
output [3: 0] ENET0_TX_DATA,
output ENET0_TX_EN,
output ENET0_TX_ER,
output ENET1_GTX_CLK,
output ENET1_RESET_N,
input ENET1_TX_CLK,
input ENET1_RX_CLK,
input [3: 0] ENET1_RX_DATA,
input ENET1_RX_DV,
input ENET1_LED_LINK100,
output [3: 0] ENET1_TX_DATA,
output ENET1_TX_EN
);
wire rst;
assign rst = ~USER_PB[3];
assign ENET0_RESET_N = USER_PB[3];
assign ENET1_RESET_N = USER_PB[3];
wire clk_tx0_25;
wire clk_tx1_25;
wire clk_rx0_25;
wire clk_rx1_25;
assign clk_tx0_25 = ENET0_TX_CLK;
assign clk_tx1_25 = ENET1_TX_CLK;
assign clk_rx0_25 = ENET0_RX_CLK;
assign clk_rx1_25 = ENET1_RX_CLK;
wire [7:0] TxRamAddr;
wire [7:0] TxData;
tx_dual_port_ram_8bit tx_dual_port_ram_8bit_ins(
.data_b(TxData),
.addr_b(TxRamAddr),
.we_b(1'b0),
.clk(clk_rx1_25),
.q_b(TxData)
);
wire [7:0]RxRamAddr;
wire [7:0]RxData;
wire RxValid;
wire [7:0]readFromRxRam8bit;
rx_dual_port_ram_8bit rx_dual_port_ram_8bit_ins(
.data_a(RxData),
.addr_a(RxRamAddr),
.we_a(RxValid),
.we_b(1'b0),
.clk(clk_rx1_25),
.q_b(readFromRxRam8bit)
);
reg [5:0]rx_ram_addr1;
always @ (posedge clk_rx1_25 )
begin
if (rst) begin
rx_ram_addr1 <= 6'b0;
end else if (ENET1_RX_DV)begin
if (rx_ram_addr1 < 6'b111110 )
rx_ram_addr1 <= rx_ram_addr1 + 1'b1;
end
end
wire [3:0]readFromRxRam;
rx_data_ram rx_data_ram_ins(
.data_a(ENET1_RX_DATA),
.addr_a(rx_ram_addr1),
.we_a(ENET1_RX_DV),
.we_b(1'b0),
.clk(clk_rx1_25),
.q_b(readFromRxRam)
);
wire Clk_100MHz;
pll_25to100MHz delay_measure_clock
(
.inclk0(CLOCK_25_MAX10),
.areset(rst),
.c0(Clk_100MHz)
);
wire [7:0]LastSlaveIDPlus1;
wire [7:0]SlaveID;
wire [3:0]readSlaveID;
wire [7:0]LogicDelay;
wire [7:0]AveSlaveDelay;
fb_slave_mac fb_slave_mac_ins
(
.MRxClk(clk_rx1_25),
.MTxClk(clk_tx0_25),
.Clk_100MHz(Clk_100MHz),
.MRxDV(ENET1_RX_DV),
.MRxD(ENET1_RX_DATA),
.Reset(rst),
.TxData(TxData),
.inSlaveID(8'd1),
.inLastSlaveIDPlus1(8'd2),
.MTxD_sync2(ENET0_TX_DATA),
.MTxEn_sync2(ENET0_TX_EN),
.RxData(RxData),
.RxValid(RxValid),
.RxRamAddr(RxRamAddr),
.TxRamAddr(TxRamAddr),
.SynchSignal(PMODA_IO[0]),
.SlaveID(SlaveID),
.LastSlaveIDPlus1(LastSlaveIDPlus1),
.LogicDelay(LogicDelay),
.AveSlaveDelay(AveSlaveDelay)
);
assign readSlaveID = USER_PB[1]?LastSlaveIDPlus1[1:0]:SlaveID[1:0];
assign USER_LED[1:0] = readSlaveID[1:0];
wire [31:0] command0;
wire [15:0] command_and0;
wire [3: 0] comm_addr0;
wire [15:0] readData0;
wire [15:0] readDataRam0;
phyInital phyInital_ins0 (
.clk(CLOCK_50_MAX10),
.reset(~USER_PB[0]),
.mdc(ENET_MDC),
.md_inout(ENET_MDIO),
.command(command0),
.command_and(command_and0),
.comm_addr(comm_addr0),
.iniStart(1'b1),
.readDataoutRam(readDataRam0)
);
phyIniCommand0 pyhIniCommands (
.clk(CLOCK_50_MAX10),
.q(command0),
.addr(comm_addr0)
);
phyIniCommand0_and pyhIniCommands_and (
.clk(CLOCK_50_MAX10),
.q(command_and0),
.addr(comm_addr0)
);
assign USER_LED[3] = ENET0_LED_LINK100;
assign USER_LED[4] = ENET1_LED_LINK100;
endmodule | module PHYctrl_Slave_MAX10 (
input CLOCK_50_MAX10,
input CLOCK_25_MAX10,
input [3: 0] USER_PB,
output [4: 0] USER_LED,
output [1:0] PMODA_IO,
output ENET_MDC,
inout ENET_MDIO,
output ENET0_RESET_N,
output ENET0_GTX_CLK,
input ENET0_TX_CLK,
input ENET0_RX_CLK,
input [3: 0] ENET0_RX_DATA,
input ENET0_RX_DV,
input ENET0_LED_LINK100,
output [3: 0] ENET0_TX_DATA,
output ENET0_TX_EN,
output ENET0_TX_ER,
output ENET1_GTX_CLK,
output ENET1_RESET_N,
input ENET1_TX_CLK,
input ENET1_RX_CLK,
input [3: 0] ENET1_RX_DATA,
input ENET1_RX_DV,
input ENET1_LED_LINK100,
output [3: 0] ENET1_TX_DATA,
output ENET1_TX_EN
); |
wire rst;
assign rst = ~USER_PB[3];
assign ENET0_RESET_N = USER_PB[3];
assign ENET1_RESET_N = USER_PB[3];
wire clk_tx0_25;
wire clk_tx1_25;
wire clk_rx0_25;
wire clk_rx1_25;
assign clk_tx0_25 = ENET0_TX_CLK;
assign clk_tx1_25 = ENET1_TX_CLK;
assign clk_rx0_25 = ENET0_RX_CLK;
assign clk_rx1_25 = ENET1_RX_CLK;
wire [7:0] TxRamAddr;
wire [7:0] TxData;
tx_dual_port_ram_8bit tx_dual_port_ram_8bit_ins(
.data_b(TxData),
.addr_b(TxRamAddr),
.we_b(1'b0),
.clk(clk_rx1_25),
.q_b(TxData)
);
wire [7:0]RxRamAddr;
wire [7:0]RxData;
wire RxValid;
wire [7:0]readFromRxRam8bit;
rx_dual_port_ram_8bit rx_dual_port_ram_8bit_ins(
.data_a(RxData),
.addr_a(RxRamAddr),
.we_a(RxValid),
.we_b(1'b0),
.clk(clk_rx1_25),
.q_b(readFromRxRam8bit)
);
reg [5:0]rx_ram_addr1;
always @ (posedge clk_rx1_25 )
begin
if (rst) begin
rx_ram_addr1 <= 6'b0;
end else if (ENET1_RX_DV)begin
if (rx_ram_addr1 < 6'b111110 )
rx_ram_addr1 <= rx_ram_addr1 + 1'b1;
end
end
wire [3:0]readFromRxRam;
rx_data_ram rx_data_ram_ins(
.data_a(ENET1_RX_DATA),
.addr_a(rx_ram_addr1),
.we_a(ENET1_RX_DV),
.we_b(1'b0),
.clk(clk_rx1_25),
.q_b(readFromRxRam)
);
wire Clk_100MHz;
pll_25to100MHz delay_measure_clock
(
.inclk0(CLOCK_25_MAX10),
.areset(rst),
.c0(Clk_100MHz)
);
wire [7:0]LastSlaveIDPlus1;
wire [7:0]SlaveID;
wire [3:0]readSlaveID;
wire [7:0]LogicDelay;
wire [7:0]AveSlaveDelay;
fb_slave_mac fb_slave_mac_ins
(
.MRxClk(clk_rx1_25),
.MTxClk(clk_tx0_25),
.Clk_100MHz(Clk_100MHz),
.MRxDV(ENET1_RX_DV),
.MRxD(ENET1_RX_DATA),
.Reset(rst),
.TxData(TxData),
.inSlaveID(8'd1),
.inLastSlaveIDPlus1(8'd2),
.MTxD_sync2(ENET0_TX_DATA),
.MTxEn_sync2(ENET0_TX_EN),
.RxData(RxData),
.RxValid(RxValid),
.RxRamAddr(RxRamAddr),
.TxRamAddr(TxRamAddr),
.SynchSignal(PMODA_IO[0]),
.SlaveID(SlaveID),
.LastSlaveIDPlus1(LastSlaveIDPlus1),
.LogicDelay(LogicDelay),
.AveSlaveDelay(AveSlaveDelay)
);
assign readSlaveID = USER_PB[1]?LastSlaveIDPlus1[1:0]:SlaveID[1:0];
assign USER_LED[1:0] = readSlaveID[1:0];
wire [31:0] command0;
wire [15:0] command_and0;
wire [3: 0] comm_addr0;
wire [15:0] readData0;
wire [15:0] readDataRam0;
phyInital phyInital_ins0 (
.clk(CLOCK_50_MAX10),
.reset(~USER_PB[0]),
.mdc(ENET_MDC),
.md_inout(ENET_MDIO),
.command(command0),
.command_and(command_and0),
.comm_addr(comm_addr0),
.iniStart(1'b1),
.readDataoutRam(readDataRam0)
);
phyIniCommand0 pyhIniCommands (
.clk(CLOCK_50_MAX10),
.q(command0),
.addr(comm_addr0)
);
phyIniCommand0_and pyhIniCommands_and (
.clk(CLOCK_50_MAX10),
.q(command_and0),
.addr(comm_addr0)
);
assign USER_LED[3] = ENET0_LED_LINK100;
assign USER_LED[4] = ENET1_LED_LINK100;
endmodule | 1 |
141,641 | data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v | 95,918,395 | t_id.v | v | 137 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10 instruction = 32\'b10001100000010000000000000000001; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:97: Unsupported: Ignoring delay on this delayed statement.\n #20 instruction = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:101: Unsupported: Ignoring delay on this delayed statement.\n #20 instruction = 32\'b10001100000010010000000000000001; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:105: Unsupported: Ignoring delay on this delayed statement.\n #20 instruction = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:116: Unsupported: Ignoring delay on this delayed statement.\n #20 instruction = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:119: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:125: Unsupported: Ignoring delay on this delayed statement.\n #20 instruction = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:132: Unsupported: Ignoring delay on this delayed statement.\n #20 instruction = 0;\n ^\n%Error: data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new/t_id.v:49: Cannot find file containing module: \'instructiondecode\'\n instructiondecode uut(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new,data/full_repos/permissive/95918395/instructiondecode\n data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new,data/full_repos/permissive/95918395/instructiondecode.v\n data/full_repos/permissive/95918395/mipsprocessor.srcs/sim_1/new,data/full_repos/permissive/95918395/instructiondecode.sv\n instructiondecode\n instructiondecode.v\n instructiondecode.sv\n obj_dir/instructiondecode\n obj_dir/instructiondecode.v\n obj_dir/instructiondecode.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,258 | module | module t_id;
reg [31:0] pcplus41, instruction, resultw;
reg [4:0] writereg;
reg regwritew, clk;
wire [31:0] read1, read2, immse, pcplus42;
wire [27:0] wainstr;
wire [4:0] rt, rd;
wire [2:0] alucontrol;
wire regwrited, memtoreg, memwrite, branch, alusrc, regdst, jump;
instructiondecode uut(
.clk( clk ),
.read1( read1 ),
.read2( read2 ),
.immediateSE( immse ),
.PCPlus4D2( pcplus42 ),
.WAinstrD( wainstr ),
.rt( rt ),
.rd( rd ),
.ALUControlD( alucontrol ),
.RegWriteD( regwrited ),
.MemToRegD( memtoreg ),
.MemWriteD( memwrite ),
.BranchD( branch ),
.ALUSrcD( alusrc ),
.RegDstD( regdst ),
.JumpD( jump ),
.PCPlus4D1( pcplus41),
.instruction( instruction ),
.ResultW( resultw ),
.WriteRegW( writereg ),
.RegWriteW( regwritew )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
pcplus41 = 0; instruction = 0; resultw = 0;
writereg = 0; regwritew = 0;
#100;
#10 instruction = 32'b10001100000010000000000000000001;
writereg = 5'h08; resultw = 32'h00000001; regwritew = 1;
#20 instruction = 0;
writereg = 5'h00; resultw = 32'h00000000; regwritew = 0;
#20 instruction = 32'b10001100000010010000000000000001;
writereg = 5'h09; resultw = 32'h00000001; regwritew = 1;
#20 instruction = 0;
writereg = 5'b00; resultw = 32'h00000000; regwritew = 0;
#100;
instruction = 32'b00000001000010010101000000100000;
writereg = 5'h0A; resultw = 32'h00000002; regwritew = 1;
#20 instruction = 0;
writereg = 5'h0; resultw = 32'h00000000; regwritew = 0;
#100;
instruction = 32'b00010001001010000000000000000001;
#20 instruction = 0;
#100;
instruction = 32'b00001000000000000000000000000001;
#20 instruction = 0;
end
endmodule | module t_id; |
reg [31:0] pcplus41, instruction, resultw;
reg [4:0] writereg;
reg regwritew, clk;
wire [31:0] read1, read2, immse, pcplus42;
wire [27:0] wainstr;
wire [4:0] rt, rd;
wire [2:0] alucontrol;
wire regwrited, memtoreg, memwrite, branch, alusrc, regdst, jump;
instructiondecode uut(
.clk( clk ),
.read1( read1 ),
.read2( read2 ),
.immediateSE( immse ),
.PCPlus4D2( pcplus42 ),
.WAinstrD( wainstr ),
.rt( rt ),
.rd( rd ),
.ALUControlD( alucontrol ),
.RegWriteD( regwrited ),
.MemToRegD( memtoreg ),
.MemWriteD( memwrite ),
.BranchD( branch ),
.ALUSrcD( alusrc ),
.RegDstD( regdst ),
.JumpD( jump ),
.PCPlus4D1( pcplus41),
.instruction( instruction ),
.ResultW( resultw ),
.WriteRegW( writereg ),
.RegWriteW( regwritew )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
pcplus41 = 0; instruction = 0; resultw = 0;
writereg = 0; regwritew = 0;
#100;
#10 instruction = 32'b10001100000010000000000000000001;
writereg = 5'h08; resultw = 32'h00000001; regwritew = 1;
#20 instruction = 0;
writereg = 5'h00; resultw = 32'h00000000; regwritew = 0;
#20 instruction = 32'b10001100000010010000000000000001;
writereg = 5'h09; resultw = 32'h00000001; regwritew = 1;
#20 instruction = 0;
writereg = 5'b00; resultw = 32'h00000000; regwritew = 0;
#100;
instruction = 32'b00000001000010010101000000100000;
writereg = 5'h0A; resultw = 32'h00000002; regwritew = 1;
#20 instruction = 0;
writereg = 5'h0; resultw = 32'h00000000; regwritew = 0;
#100;
instruction = 32'b00010001001010000000000000000001;
#20 instruction = 0;
#100;
instruction = 32'b00001000000000000000000000000001;
#20 instruction = 0;
end
endmodule | 0 |
141,642 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v | 95,918,395 | t_alu.v | v | 64 | 107 | [] | [] | [] | [(23, 63)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h0000FFFF; b = 32\'h000000FF; alu_sel = 3\'b000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'hFFFF0000; b = 32\'h0000FFFF; alu_sel = 3\'b001; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000001; b = 32\'h00000001; alu_sel = 3\'b010; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'hFFFFFFFF; b = 32\'hFFFFFFFF; alu_sel = 3\'b100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h0000FFFF; b = 32\'h0000FFFF; alu_sel = 3\'b101; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h7FFFFFFF; b = 32\'h0000000F; alu_sel = 3\'b110; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000000; b = 32\'h00000001; alu_sel = 3\'b111; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000001; b = 32\'h00000000; alu_sel = 3\'b111; \n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_alu.v:34: Cannot find file containing module: \'alu\'\n alu uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/alu\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/alu.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,259 | module | module t_alu;
reg [31:0] a;
reg [31:0] b;
reg [2:0] alu_sel;
wire [31:0] z;
alu uut (
.control( alu_sel ),
.ALUResult( z ),
.A( a ),
.B( b )
);
initial begin
alu_sel = 0;
a = 0;
b = 0;
#100;
#100 a = 32'h0000FFFF; b = 32'h000000FF; alu_sel = 3'b000;
#100 a = 32'hFFFF0000; b = 32'h0000FFFF; alu_sel = 3'b001;
#100 a = 32'h00000001; b = 32'h00000001; alu_sel = 3'b010;
#100 a = 32'hFFFFFFFF; b = 32'hFFFFFFFF; alu_sel = 3'b100;
#100 a = 32'h0000FFFF; b = 32'h0000FFFF; alu_sel = 3'b101;
#100 a = 32'h7FFFFFFF; b = 32'h0000000F; alu_sel = 3'b110;
#100 a = 32'h00000000; b = 32'h00000001; alu_sel = 3'b111;
#100 a = 32'h00000001; b = 32'h00000000; alu_sel = 3'b111;
end
endmodule | module t_alu; |
reg [31:0] a;
reg [31:0] b;
reg [2:0] alu_sel;
wire [31:0] z;
alu uut (
.control( alu_sel ),
.ALUResult( z ),
.A( a ),
.B( b )
);
initial begin
alu_sel = 0;
a = 0;
b = 0;
#100;
#100 a = 32'h0000FFFF; b = 32'h000000FF; alu_sel = 3'b000;
#100 a = 32'hFFFF0000; b = 32'h0000FFFF; alu_sel = 3'b001;
#100 a = 32'h00000001; b = 32'h00000001; alu_sel = 3'b010;
#100 a = 32'hFFFFFFFF; b = 32'hFFFFFFFF; alu_sel = 3'b100;
#100 a = 32'h0000FFFF; b = 32'h0000FFFF; alu_sel = 3'b101;
#100 a = 32'h7FFFFFFF; b = 32'h0000000F; alu_sel = 3'b110;
#100 a = 32'h00000000; b = 32'h00000001; alu_sel = 3'b111;
#100 a = 32'h00000001; b = 32'h00000000; alu_sel = 3'b111;
end
endmodule | 0 |
141,643 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v | 95,918,395 | t_ctrlunit.v | v | 87 | 103 | [] | [] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h00; funct = 6\'h20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:56: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:58: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h00; funct = 6\'h22; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:59: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h00; funct = 6\'h24; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:62: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h00; funct = 6\'h25; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:65: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h00; funct = 6\'h2A; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:68: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h23; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:71: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h2B; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:74: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h04; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:77: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:79: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h08; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:80: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:82: Unsupported: Ignoring delay on this delayed statement.\n #10 opcode = 6\'h02; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:83: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ctrlunit.v:33: Cannot find file containing module: \'ctrlunit\'\n ctrlunit uut(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/ctrlunit\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/ctrlunit.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/ctrlunit.sv\n ctrlunit\n ctrlunit.v\n ctrlunit.sv\n obj_dir/ctrlunit\n obj_dir/ctrlunit.v\n obj_dir/ctrlunit.sv\n%Error: Exiting due to 1 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,260 | module | module t_ctrlunit;
reg [5:0] opcode, funct;
wire memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump;
wire [2:0] alucontrol;
ctrlunit uut(
.OPCode( opcode ),
.Funct( funct ),
.MemToReg( memtoreg ),
.MemWrite( memwrite ),
.Branch( branch ),
.ALUSrc( alusrc ),
.RegDst( regdst ),
.RegWrite( regwrite ),
.Jump( jump ),
.ALUControl( alucontrol )
);
initial begin
opcode = 0;
funct = 0;
#100;
#10 opcode = 6'h00; funct = 6'h20;
#40;
#10 opcode = 6'h00; funct = 6'h22;
#40;
#10 opcode = 6'h00; funct = 6'h24;
#40;
#10 opcode = 6'h00; funct = 6'h25;
#40;
#10 opcode = 6'h00; funct = 6'h2A;
#40;
#10 opcode = 6'h23;
#40;
#10 opcode = 6'h2B;
#40;
#10 opcode = 6'h04;
#40;
#10 opcode = 6'h08;
#40;
#10 opcode = 6'h02;
#40;
end
endmodule | module t_ctrlunit; |
reg [5:0] opcode, funct;
wire memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump;
wire [2:0] alucontrol;
ctrlunit uut(
.OPCode( opcode ),
.Funct( funct ),
.MemToReg( memtoreg ),
.MemWrite( memwrite ),
.Branch( branch ),
.ALUSrc( alusrc ),
.RegDst( regdst ),
.RegWrite( regwrite ),
.Jump( jump ),
.ALUControl( alucontrol )
);
initial begin
opcode = 0;
funct = 0;
#100;
#10 opcode = 6'h00; funct = 6'h20;
#40;
#10 opcode = 6'h00; funct = 6'h22;
#40;
#10 opcode = 6'h00; funct = 6'h24;
#40;
#10 opcode = 6'h00; funct = 6'h25;
#40;
#10 opcode = 6'h00; funct = 6'h2A;
#40;
#10 opcode = 6'h23;
#40;
#10 opcode = 6'h2B;
#40;
#10 opcode = 6'h04;
#40;
#10 opcode = 6'h08;
#40;
#10 opcode = 6'h02;
#40;
end
endmodule | 0 |
141,644 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v | 95,918,395 | t_dmem.v | v | 79 | 83 | [] | [] | [] | null | line:79: before: "." | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:61: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:63: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:64: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:66: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h02;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:67: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:69: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h03;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:70: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:73: Unsupported: Ignoring delay on this delayed statement.\n #20 we = 1; wd = 32\'hFFFFFFFF; a = 32\'h00000004;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:74: Unsupported: Ignoring delay on this delayed statement.\n #40 we = 0;\n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:33: Cannot find file containing module: \'dmem\'\n dmem uut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/dmem\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/dmem.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/dmem.sv\n dmem\n dmem.v\n dmem.sv\n obj_dir/dmem\n obj_dir/dmem.v\n obj_dir/dmem.sv\n%Warning-WIDTH: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:60: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance t_dmem\n #10 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h00;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:63: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance t_dmem\n #20 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h01;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:66: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance t_dmem\n #20 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h02;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_dmem.v:69: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n : ... In instance t_dmem\n #20 we = 1; wd = 32\'hFFFFFFFF; a = 8\'h03;\n ^\n%Error: Exiting due to 1 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,261 | module | module t_dmem;
reg [31:0] a, wd;
reg we, clk;
wire [31:0] rd;
dmem uut (
.RD( rd ),
.A( a ),
.WD( wd ),
.WE( we ),
.clk( clk )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
we = 0;
a = 0;
wd = 0;
#100;
#10 we = 1; wd = 32'hFFFFFFFF; a = 8'h00;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 8'h01;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 8'h02;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 8'h03;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 32'h00000004;
#40 we = 0;
end
endmodule | module t_dmem; |
reg [31:0] a, wd;
reg we, clk;
wire [31:0] rd;
dmem uut (
.RD( rd ),
.A( a ),
.WD( wd ),
.WE( we ),
.clk( clk )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
we = 0;
a = 0;
wd = 0;
#100;
#10 we = 1; wd = 32'hFFFFFFFF; a = 8'h00;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 8'h01;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 8'h02;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 8'h03;
#40 we = 0;
#20 we = 1; wd = 32'hFFFFFFFF; a = 32'h00000004;
#40 we = 0;
end
endmodule | 0 |
141,645 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v | 95,918,395 | t_ex.v | v | 104 | 150 | [] | [] | [] | [(26, 103)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:77: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:81: Unsupported: Ignoring delay on this delayed statement.\n #20 regdst = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:82: Unsupported: Ignoring delay on this delayed statement.\n #20 rt = 0; rd = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:84: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:87: Unsupported: Ignoring delay on this delayed statement.\n #20 srca = 32\'h00001111; regread2 = 32\'hFFFF0000; signimm = 32\'hFFFFFFFF; alusrc = 0; alucontrol = 3\'b001; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:89: Unsupported: Ignoring delay on this delayed statement.\n #20 alusrc = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:90: Unsupported: Ignoring delay on this delayed statement.\n #20 srca = 0; regread2 = 0; signimm = 0; alusrc = 0; alucontrol = 3\'b000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:92: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:98: Unsupported: Ignoring delay on this delayed statement.\n #20 regwrite1 = 1; memtoreg1 = 1; memwrite1 = 1; branch1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:100: Unsupported: Ignoring delay on this delayed statement.\n #20 regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;\n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_ex.v:39: Cannot find file containing module: \'execute\'\n execute uut(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/execute\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/execute.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/execute.sv\n execute\n execute.v\n execute.sv\n obj_dir/execute\n obj_dir/execute.v\n obj_dir/execute.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,262 | module | module t_ex;
reg [31:0] pcplus4, srca, regread2, signimm;
reg [4:0] rt, rd;
reg [2:0] alucontrol;
reg alusrc, regdst, regwrite1, memtoreg1, memwrite1, branch1;
wire [31:0] aluresult, pcbranch, writedata;
wire [4:0] writereg;
wire regwrite2, memtoreg2, memwrite2, branch2, zerowire;
execute uut(
.ALUResult( aluresult ),
.PCBranchE( pcbranch ),
.WriteDataE( writedata ),
.WriteRegE( writereg ),
.RegWriteE2( regwrite2 ),
.MemToRegE2( memtoreg2 ),
.MemWriteE2( memwrite2 ),
.BranchE2( branch2 ),
.ZerowireE( zerowire ),
.PCPlus4E( pcplus4 ),
.srcA( srca ),
.RegRead2( regread2 ),
.SignImmE( signimm ),
.rt( rt ),
.rd( rd ),
.ALUControlE( alucontrol ),
.ALUSrcE( alusrc ),
.RegDstE( regdst ),
.RegWriteE1( regwrite1 ),
.MemToRegE1( memtoreg1 ),
.MemWriteE1( memwrite1 ),
.BranchE1( branch1 )
);
initial begin
pcplus4 = 0; srca = 0; regread2 = 0; signimm = 0;
rt = 0; rd = 0;
alucontrol = 0;
alusrc = 0; regdst = 0; regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
$display(srca);
$display(regread2);
#100;
rt = 5'b01000; rd = 5'b01001; regdst = 1;
#20 regdst = 0;
#20 rt = 0; rd = 0;
#100;
#20 srca = 32'h00001111; regread2 = 32'hFFFF0000; signimm = 32'hFFFFFFFF; alusrc = 0; alucontrol = 3'b001;
#20 alusrc = 1;
#20 srca = 0; regread2 = 0; signimm = 0; alusrc = 0; alucontrol = 3'b000;
#100;
pcplus4 = 32'h00000004; signimm = 32'h00000001;
#20 regwrite1 = 1; memtoreg1 = 1; memwrite1 = 1; branch1 = 1;
#20 regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
end
endmodule | module t_ex; |
reg [31:0] pcplus4, srca, regread2, signimm;
reg [4:0] rt, rd;
reg [2:0] alucontrol;
reg alusrc, regdst, regwrite1, memtoreg1, memwrite1, branch1;
wire [31:0] aluresult, pcbranch, writedata;
wire [4:0] writereg;
wire regwrite2, memtoreg2, memwrite2, branch2, zerowire;
execute uut(
.ALUResult( aluresult ),
.PCBranchE( pcbranch ),
.WriteDataE( writedata ),
.WriteRegE( writereg ),
.RegWriteE2( regwrite2 ),
.MemToRegE2( memtoreg2 ),
.MemWriteE2( memwrite2 ),
.BranchE2( branch2 ),
.ZerowireE( zerowire ),
.PCPlus4E( pcplus4 ),
.srcA( srca ),
.RegRead2( regread2 ),
.SignImmE( signimm ),
.rt( rt ),
.rd( rd ),
.ALUControlE( alucontrol ),
.ALUSrcE( alusrc ),
.RegDstE( regdst ),
.RegWriteE1( regwrite1 ),
.MemToRegE1( memtoreg1 ),
.MemWriteE1( memwrite1 ),
.BranchE1( branch1 )
);
initial begin
pcplus4 = 0; srca = 0; regread2 = 0; signimm = 0;
rt = 0; rd = 0;
alucontrol = 0;
alusrc = 0; regdst = 0; regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
$display(srca);
$display(regread2);
#100;
rt = 5'b01000; rd = 5'b01001; regdst = 1;
#20 regdst = 0;
#20 rt = 0; rd = 0;
#100;
#20 srca = 32'h00001111; regread2 = 32'hFFFF0000; signimm = 32'hFFFFFFFF; alusrc = 0; alucontrol = 3'b001;
#20 alusrc = 1;
#20 srca = 0; regread2 = 0; signimm = 0; alusrc = 0; alucontrol = 3'b000;
#100;
pcplus4 = 32'h00000004; signimm = 32'h00000001;
#20 regwrite1 = 1; memtoreg1 = 1; memwrite1 = 1; branch1 = 1;
#20 regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
end
endmodule | 0 |
141,646 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v | 95,918,395 | t_if.v | v | 81 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20 clk = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:63: Unsupported: Ignoring delay on this delayed statement.\n #40 reset = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:65: Unsupported: Ignoring delay on this delayed statement.\n #260 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:69: Unsupported: Ignoring delay on this delayed statement.\n #40 jump = 0; pcSrc = 0; waInstruction = 27\'h000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:72: Unsupported: Ignoring delay on this delayed statement.\n #40 jump = 0; pcSrc = 1; pcBranch = 32\'h0000001C;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:73: Unsupported: Ignoring delay on this delayed statement.\n #40 jump = 0; pcSrc = 0; pcBranch = 32\'h00000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:34: Cannot find file containing module: \'instructionfetch\'\n instructionfetch uut(\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/instructionfetch\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/instructionfetch.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/instructionfetch.sv\n instructionfetch\n instructionfetch.v\n instructionfetch.sv\n obj_dir/instructionfetch\n obj_dir/instructionfetch.v\n obj_dir/instructionfetch.sv\n%Warning-WIDTH: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:68: Operator ASSIGN expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h0\' generates 27 bits.\n : ... In instance t_if\n jump = 1; pcSrc = 0; waInstruction = 27\'h000000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_if.v:69: Operator ASSIGN expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h0\' generates 27 bits.\n : ... In instance t_if\n #40 jump = 0; pcSrc = 0; waInstruction = 27\'h000000;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,263 | module | module t_if;
reg [31:0] pcBranch;
reg [27:0] waInstruction;
reg clk, reset, jump, pcSrc;
wire [31:0] pcPlus4, instruction;
instructionfetch uut(
.PCPlus4F( pcPlus4 ),
.instruction( instruction ),
.PCBranchF( pcBranch ),
.WAinstrF( waInstruction ),
.clk( clk ),
.reset( reset ),
.JumpF( jump ),
.PCSrcF( pcSrc )
);
initial begin
clk = 0;
forever begin
#20 clk = 1;
#20 clk = 0;
end
end
initial begin
pcBranch = 0;
waInstruction = 0;
jump = 0;
pcSrc = 0;
reset = 0;
reset = 1;
#40 reset = 0;
#260
jump = 1; pcSrc = 0; waInstruction = 27'h000000;
#40 jump = 0; pcSrc = 0; waInstruction = 27'h000000;
#40 jump = 0; pcSrc = 1; pcBranch = 32'h0000001C;
#40 jump = 0; pcSrc = 0; pcBranch = 32'h00000000;
#100;
end
endmodule | module t_if; |
reg [31:0] pcBranch;
reg [27:0] waInstruction;
reg clk, reset, jump, pcSrc;
wire [31:0] pcPlus4, instruction;
instructionfetch uut(
.PCPlus4F( pcPlus4 ),
.instruction( instruction ),
.PCBranchF( pcBranch ),
.WAinstrF( waInstruction ),
.clk( clk ),
.reset( reset ),
.JumpF( jump ),
.PCSrcF( pcSrc )
);
initial begin
clk = 0;
forever begin
#20 clk = 1;
#20 clk = 0;
end
end
initial begin
pcBranch = 0;
waInstruction = 0;
jump = 0;
pcSrc = 0;
reset = 0;
reset = 1;
#40 reset = 0;
#260
jump = 1; pcSrc = 0; waInstruction = 27'h000000;
#40 jump = 0; pcSrc = 0; waInstruction = 27'h000000;
#40 jump = 0; pcSrc = 1; pcBranch = 32'h0000001C;
#40 jump = 0; pcSrc = 0; pcBranch = 32'h00000000;
#100;
end
endmodule | 0 |
141,647 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v | 95,918,395 | t_instrmem.v | v | 59 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000004;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000008;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:49: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h0000000C;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000014;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000018;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h0000001C;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100 a = 32\'h00000020;\n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_instrmem.v:32: Cannot find file containing module: \'instrmem\'\n instrmem uut (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/instrmem\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/instrmem.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/instrmem.sv\n instrmem\n instrmem.v\n instrmem.sv\n obj_dir/instrmem\n obj_dir/instrmem.v\n obj_dir/instrmem.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,264 | module | module t_instrmem;
reg [31:0] a;
wire [31:0] rd;
instrmem uut (
.A( a ),
.RD( rd )
);
initial begin
a = 0;
#100;
a = 32'h00000000;
#100 a = 32'h00000004;
#100 a = 32'h00000008;
#100 a = 32'h0000000C;
#100 a = 32'h00000010;
#100 a = 32'h00000014;
#100 a = 32'h00000018;
#100 a = 32'h0000001C;
#100 a = 32'h00000020;
end
endmodule | module t_instrmem; |
reg [31:0] a;
wire [31:0] rd;
instrmem uut (
.A( a ),
.RD( rd )
);
initial begin
a = 0;
#100;
a = 32'h00000000;
#100 a = 32'h00000004;
#100 a = 32'h00000008;
#100 a = 32'h0000000C;
#100 a = 32'h00000010;
#100 a = 32'h00000014;
#100 a = 32'h00000018;
#100 a = 32'h0000001C;
#100 a = 32'h00000020;
end
endmodule | 0 |
141,648 | data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v | 95,918,395 | t_mem.v | v | 86 | 153 | [] | [] | [] | [(23, 85)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:64: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 zerowire = 0; branch = 0; pcbranch1 = 32\'h00000008; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:68: Unsupported: Ignoring delay on this delayed statement.\n #20 zerowire = 0; branch = 1; pcbranch1 = 32\'h00000008; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:69: Unsupported: Ignoring delay on this delayed statement.\n #20 zerowire = 1; branch = 0; pcbranch1 = 32\'h00000008; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:70: Unsupported: Ignoring delay on this delayed statement.\n #20 zerowire = 1; branch = 1; pcbranch1 = 32\'h00000008; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:73: Unsupported: Ignoring delay on this delayed statement.\n #20 aluresultin = 32\'h00000001; memwrite = 1; writedata = 32\'hFFFFFFFF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:75: Unsupported: Ignoring delay on this delayed statement.\n #20 aluresultin = 32\'h00000001; memwrite = 0; writedata = 32\'hAAAAAAAA; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:80: Unsupported: Ignoring delay on this delayed statement.\n #20 writereg1 = 5\'b01000; memtoreg1 = 1; regwrite1 = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:81: Unsupported: Ignoring delay on this delayed statement.\n #20 writereg1 = 5\'b01001; memtoreg1 = 0; regwrite1 = 0; \n ^\n%Error: data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new/t_mem.v:36: Cannot find file containing module: \'memoryaccess\'\n memoryaccess uut (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/memoryaccess\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/memoryaccess.v\n data/full_repos/permissive/95918395/Mips_single_cycle.srcs/sim_1/new,data/full_repos/permissive/95918395/memoryaccess.sv\n memoryaccess\n memoryaccess.v\n memoryaccess.sv\n obj_dir/memoryaccess\n obj_dir/memoryaccess.v\n obj_dir/memoryaccess.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 312,265 | module | module t_mem;
reg [31:0] writedata, aluresultin, pcbranch1;
reg [4:0] writereg1;
reg branch, memwrite, memtoreg1, regwrite1, zerowire, clk;
wire [31:0] readdata, aluresultout, pcbranch2;
wire [4:0] writereg2;
wire regwrite2, memtoreg2, pcsrc;
memoryaccess uut (
.ReadDataM( readdata ), .ALUResultOut( aluresultout ), .PCBranchM2( pcbranch2 ),
.WriteRegM2( writereg2 ),
.RegWriteM2( regwrite2 ), .MemToRegM2( memtoreg2 ), .PCSrcM( pcsrc ),
.WriteDataM( writedata ), .ALUResultIn( aluresultin ), .PCBranchM1( pcbranch1 ),
.WriteRegM1( writereg1 ),
.BranchM( branch ), .MemWriteM( memwrite ), .MemToRegM1( memtoreg1 ),
.RegWriteM1( regwrite1 ),
.ZerowireM( zerowire ), .clk( clk )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
writedata = 0; aluresultin = 0; pcbranch1 = 0;
writereg1 = 0;
branch = 0; memwrite = 0; memtoreg1 = 0; regwrite1 = 0; zerowire = 0; clk = 0;
#100;
#10 zerowire = 0; branch = 0; pcbranch1 = 32'h00000008;
#20 zerowire = 0; branch = 1; pcbranch1 = 32'h00000008;
#20 zerowire = 1; branch = 0; pcbranch1 = 32'h00000008;
#20 zerowire = 1; branch = 1; pcbranch1 = 32'h00000008;
#20 aluresultin = 32'h00000001; memwrite = 1; writedata = 32'hFFFFFFFF;
#20 aluresultin = 32'h00000001; memwrite = 0; writedata = 32'hAAAAAAAA;
#20 writereg1 = 5'b01000; memtoreg1 = 1; regwrite1 = 1;
#20 writereg1 = 5'b01001; memtoreg1 = 0; regwrite1 = 0;
end
endmodule | module t_mem; |
reg [31:0] writedata, aluresultin, pcbranch1;
reg [4:0] writereg1;
reg branch, memwrite, memtoreg1, regwrite1, zerowire, clk;
wire [31:0] readdata, aluresultout, pcbranch2;
wire [4:0] writereg2;
wire regwrite2, memtoreg2, pcsrc;
memoryaccess uut (
.ReadDataM( readdata ), .ALUResultOut( aluresultout ), .PCBranchM2( pcbranch2 ),
.WriteRegM2( writereg2 ),
.RegWriteM2( regwrite2 ), .MemToRegM2( memtoreg2 ), .PCSrcM( pcsrc ),
.WriteDataM( writedata ), .ALUResultIn( aluresultin ), .PCBranchM1( pcbranch1 ),
.WriteRegM1( writereg1 ),
.BranchM( branch ), .MemWriteM( memwrite ), .MemToRegM1( memtoreg1 ),
.RegWriteM1( regwrite1 ),
.ZerowireM( zerowire ), .clk( clk )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
writedata = 0; aluresultin = 0; pcbranch1 = 0;
writereg1 = 0;
branch = 0; memwrite = 0; memtoreg1 = 0; regwrite1 = 0; zerowire = 0; clk = 0;
#100;
#10 zerowire = 0; branch = 0; pcbranch1 = 32'h00000008;
#20 zerowire = 0; branch = 1; pcbranch1 = 32'h00000008;
#20 zerowire = 1; branch = 0; pcbranch1 = 32'h00000008;
#20 zerowire = 1; branch = 1; pcbranch1 = 32'h00000008;
#20 aluresultin = 32'h00000001; memwrite = 1; writedata = 32'hFFFFFFFF;
#20 aluresultin = 32'h00000001; memwrite = 0; writedata = 32'hAAAAAAAA;
#20 writereg1 = 5'b01000; memtoreg1 = 1; regwrite1 = 1;
#20 writereg1 = 5'b01001; memtoreg1 = 0; regwrite1 = 0;
end
endmodule | 0 |
Subsets and Splits