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141,158 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac3 (c, gout, pout, Cin, g, p); |
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,159 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac4 (c, gout, pout, Cin, g, p); |
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,160 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac5 (c, gout, pout, Cin, g, p); |
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,161 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module lac6 (c, gout, pout, Cin, g, p);
output [63:0] c;
output gout, pout;
input Cin;
input [63:0] g, p;
wire [1:0] cint, gint, pint;
lac5 leaf0(
.c(c[31:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[31:0]),
.p(p[31:0])
);
lac5 leaf1(
.c(c[63:32]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[63:32]),
.p(p[63:32])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac6 (c, gout, pout, Cin, g, p); |
output [63:0] c;
output gout, pout;
input Cin;
input [63:0] g, p;
wire [1:0] cint, gint, pint;
lac5 leaf0(
.c(c[31:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[31:0]),
.p(p[31:0])
);
lac5 leaf1(
.c(c[63:32]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[63:32]),
.p(p[63:32])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,162 | data/full_repos/permissive/93755996/Project2_LUT/And_LUT.v | 93,755,996 | And_LUT.v | v | 9 | 44 | [] | [] | [] | [(1, 9)] | null | data/verilator_xmls/c8de369b-02b3-4cb2-b29f-2a5a43e8ff60.xml | null | 310,909 | module | module And_Gate (
input i_Switch_1,
input i_Switch_2,
output o_LED_1
);
assign o_LED_1 = i_Switch_1 & i_Switch_2;
endmodule | module And_Gate (
input i_Switch_1,
input i_Switch_2,
output o_LED_1
); |
assign o_LED_1 = i_Switch_1 & i_Switch_2;
endmodule | 2 |
141,163 | data/full_repos/permissive/93755996/Project3_FlipFlop/flipflop.v | 93,755,996 | flipflop.v | v | 20 | 56 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/01bfe522-06c9-4c47-86d8-08c17b0ecc50.xml | null | 310,910 | module | module flipflop (
input i_Clk,
input i_Switch_1,
output o_LED_1
);
reg r_Switch_1 = 1'b0;
reg r_LED_1 = 1'b0;
always @ (posedge i_Clk) begin
r_Switch_1 <= i_Switch_1;
if (i_Switch_1 == 1'b0 && r_Switch_1 == 1'b1) begin
r_LED_1 <= ~r_LED_1;
end
end
assign o_LED_1 = r_LED_1;
endmodule | module flipflop (
input i_Clk,
input i_Switch_1,
output o_LED_1
); |
reg r_Switch_1 = 1'b0;
reg r_LED_1 = 1'b0;
always @ (posedge i_Clk) begin
r_Switch_1 <= i_Switch_1;
if (i_Switch_1 == 1'b0 && r_Switch_1 == 1'b1) begin
r_LED_1 <= ~r_LED_1;
end
end
assign o_LED_1 = r_LED_1;
endmodule | 2 |
141,164 | data/full_repos/permissive/93755996/Project4_Debounce/Main.v | 93,755,996 | Main.v | v | 29 | 56 | [] | [] | [] | null | line:26: before: "input" | null | 1: b'%Error: data/full_repos/permissive/93755996/Project4_Debounce/Main.v:1: Cannot find include file: Debounce_Switch.v\n`include "Debounce_Switch.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93755996/Project4_Debounce,data/full_repos/permissive/93755996/Debounce_Switch.v\n data/full_repos/permissive/93755996/Project4_Debounce,data/full_repos/permissive/93755996/Debounce_Switch.v.v\n data/full_repos/permissive/93755996/Project4_Debounce,data/full_repos/permissive/93755996/Debounce_Switch.v.sv\n Debounce_Switch.v\n Debounce_Switch.v.v\n Debounce_Switch.v.sv\n obj_dir/Debounce_Switch.v\n obj_dir/Debounce_Switch.v.v\n obj_dir/Debounce_Switch.v.sv\n%Error: Exiting due to 1 error(s)\n' | 310,912 | module | module Main (
input i_Clk,
input i_Switch_1,
output o_LED_1
);
reg r_Switch_1 = 1'b0;
reg r_LED_1 = 1'b0;
wire w_Switch_1;
Debounce_Switch Debounce_Switch_1 (
.i_Clk(i_Clk),
.i_Switch(i_Switch_1),
.o_Switch(w_Switch_1)
);
always @ (posedge i_Clk) begin
r_Switch_1 <= w_Switch_1;
if (w_Switch_1 == 1'b0 && r_Switch_1 == 1'b1) begin
r_LED_1 <= ~r_LED_1;
end
end
assign o_LED_1 = r_LED_1;
endmodule | module Main (
input i_Clk,
input i_Switch_1,
output o_LED_1
); |
reg r_Switch_1 = 1'b0;
reg r_LED_1 = 1'b0;
wire w_Switch_1;
Debounce_Switch Debounce_Switch_1 (
.i_Clk(i_Clk),
.i_Switch(i_Switch_1),
.o_Switch(w_Switch_1)
);
always @ (posedge i_Clk) begin
r_Switch_1 <= w_Switch_1;
if (w_Switch_1 == 1'b0 && r_Switch_1 == 1'b1) begin
r_LED_1 <= ~r_LED_1;
end
end
assign o_LED_1 = r_LED_1;
endmodule | 2 |
141,166 | data/full_repos/permissive/93755996/Project5.1_Score_Counter/Main.v | 93,755,996 | Main.v | v | 79 | 69 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/93755996/Project5.1_Score_Counter/Main.v:1: Cannot find include file: Debounce_Switch.v\n`include "Debounce_Switch.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93755996/Project5.1_Score_Counter,data/full_repos/permissive/93755996/Debounce_Switch.v\n data/full_repos/permissive/93755996/Project5.1_Score_Counter,data/full_repos/permissive/93755996/Debounce_Switch.v.v\n data/full_repos/permissive/93755996/Project5.1_Score_Counter,data/full_repos/permissive/93755996/Debounce_Switch.v.sv\n Debounce_Switch.v\n Debounce_Switch.v.v\n Debounce_Switch.v.sv\n obj_dir/Debounce_Switch.v\n obj_dir/Debounce_Switch.v.v\n obj_dir/Debounce_Switch.v.sv\n%Error: data/full_repos/permissive/93755996/Project5.1_Score_Counter/Main.v:2: Cannot find include file: Seven_Segment_Display.v\n`include "Seven_Segment_Display.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 310,917 | module | module Main (
input i_Clk,
input i_Switch_1,
input i_Switch_2,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
input i_Switch_3,
input i_Switch_4,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G
);
reg r_Any_Switch = 1'b0;
reg [3:0] r_State_1 = 0;
reg [3:0] r_State_2 = 0;
wire w_Any_Switch;
Debounce_Switch Debounce_Switch (
.i_Clk(i_Clk),
.i_Switch(i_Switch_1 || i_Switch_2 || i_Switch_3 || i_Switch_4),
.o_Switch(w_Any_Switch)
);
Seven_Segment_Display Seven_Segment_Display_1 (
.i_Nibble(r_State_1),
.o_Segment_A(o_Segment1_A),
.o_Segment_B(o_Segment1_B),
.o_Segment_C(o_Segment1_C),
.o_Segment_D(o_Segment1_D),
.o_Segment_E(o_Segment1_E),
.o_Segment_F(o_Segment1_F),
.o_Segment_G(o_Segment1_G)
);
Seven_Segment_Display Seven_Segment_Display_2 (
.i_Nibble(r_State_2),
.o_Segment_A(o_Segment2_A),
.o_Segment_B(o_Segment2_B),
.o_Segment_C(o_Segment2_C),
.o_Segment_D(o_Segment2_D),
.o_Segment_E(o_Segment2_E),
.o_Segment_F(o_Segment2_F),
.o_Segment_G(o_Segment2_G)
);
always @ (posedge i_Clk) begin
r_Any_Switch <= w_Any_Switch;
if (w_Any_Switch == 1'b1 && r_Any_Switch == 1'b0) begin
if (i_Switch_1 == 1'b1) begin
if (r_State_1 === 9)
r_State_1 <= 0;
else
r_State_1 <= r_State_1 + 4'b1;
end else if (i_Switch_2 == 1'b1)
r_State_1 <= 0;
else if (i_Switch_3 == 1'b1) begin
if (r_State_2 === 9)
r_State_2 <= 0;
else
r_State_2 <= r_State_2 + 4'b1;
end else if (i_Switch_4 == 1'b1)
r_State_2 <= 0;
end
end
endmodule | module Main (
input i_Clk,
input i_Switch_1,
input i_Switch_2,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
input i_Switch_3,
input i_Switch_4,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G
); |
reg r_Any_Switch = 1'b0;
reg [3:0] r_State_1 = 0;
reg [3:0] r_State_2 = 0;
wire w_Any_Switch;
Debounce_Switch Debounce_Switch (
.i_Clk(i_Clk),
.i_Switch(i_Switch_1 || i_Switch_2 || i_Switch_3 || i_Switch_4),
.o_Switch(w_Any_Switch)
);
Seven_Segment_Display Seven_Segment_Display_1 (
.i_Nibble(r_State_1),
.o_Segment_A(o_Segment1_A),
.o_Segment_B(o_Segment1_B),
.o_Segment_C(o_Segment1_C),
.o_Segment_D(o_Segment1_D),
.o_Segment_E(o_Segment1_E),
.o_Segment_F(o_Segment1_F),
.o_Segment_G(o_Segment1_G)
);
Seven_Segment_Display Seven_Segment_Display_2 (
.i_Nibble(r_State_2),
.o_Segment_A(o_Segment2_A),
.o_Segment_B(o_Segment2_B),
.o_Segment_C(o_Segment2_C),
.o_Segment_D(o_Segment2_D),
.o_Segment_E(o_Segment2_E),
.o_Segment_F(o_Segment2_F),
.o_Segment_G(o_Segment2_G)
);
always @ (posedge i_Clk) begin
r_Any_Switch <= w_Any_Switch;
if (w_Any_Switch == 1'b1 && r_Any_Switch == 1'b0) begin
if (i_Switch_1 == 1'b1) begin
if (r_State_1 === 9)
r_State_1 <= 0;
else
r_State_1 <= r_State_1 + 4'b1;
end else if (i_Switch_2 == 1'b1)
r_State_1 <= 0;
else if (i_Switch_3 == 1'b1) begin
if (r_State_2 === 9)
r_State_2 <= 0;
else
r_State_2 <= r_State_2 + 4'b1;
end else if (i_Switch_4 == 1'b1)
r_State_2 <= 0;
end
end
endmodule | 2 |
141,168 | data/full_repos/permissive/93755996/Project6_LED_Blink/LED_Blink.v | 93,755,996 | LED_Blink.v | v | 65 | 70 | [] | [] | [] | null | line:7: before: "=" | data/verilator_xmls/5251953d-ddcf-4c65-923c-b25ace89109b.xml | null | 310,923 | module | module LED_Blink
#(parameter g_COUNT_10HZ = 1250000,
parameter g_COUNT_5HZ = 2500000,
parameter g_COUNT_2HZ = 6250000,
parameter g_COUNT_1HZ = 12500000)
(input i_Clk,
output reg o_LED_1 = 1'b0,
output reg o_LED_2 = 1'b0,
output reg o_LED_3 = 1'b0,
output reg o_LED_4 = 1'b0);
reg [31:0] r_Count_10Hz = 0;
reg [31:0] r_Count_5Hz = 0;
reg [31:0] r_Count_2Hz = 0;
reg [31:0] r_Count_1Hz = 0;
always @(posedge i_Clk)
begin
if (r_Count_10Hz == g_COUNT_10HZ)
begin
o_LED_1 <= ~o_LED_1;
r_Count_10Hz <= 0;
end
else
r_Count_10Hz <= r_Count_10Hz + 1;
end
always @(posedge i_Clk)
begin
if (r_Count_5Hz == g_COUNT_5HZ)
begin
o_LED_2 <= ~o_LED_2;
r_Count_5Hz <= 0;
end
else
r_Count_5Hz <= r_Count_5Hz + 1;
end
always @(posedge i_Clk)
begin
if (r_Count_2Hz == g_COUNT_2HZ)
begin
o_LED_3 <= ~o_LED_3;
r_Count_2Hz <= 0;
end
else
r_Count_2Hz <= r_Count_2Hz + 1;
end
always @(posedge i_Clk)
begin
if (r_Count_1Hz == g_COUNT_1HZ)
begin
o_LED_4 <= ~o_LED_4;
r_Count_1Hz <= 0;
end
else
r_Count_1Hz <= r_Count_1Hz + 1;
end
endmodule | module LED_Blink
#(parameter g_COUNT_10HZ = 1250000,
parameter g_COUNT_5HZ = 2500000,
parameter g_COUNT_2HZ = 6250000,
parameter g_COUNT_1HZ = 12500000)
(input i_Clk,
output reg o_LED_1 = 1'b0,
output reg o_LED_2 = 1'b0,
output reg o_LED_3 = 1'b0,
output reg o_LED_4 = 1'b0); |
reg [31:0] r_Count_10Hz = 0;
reg [31:0] r_Count_5Hz = 0;
reg [31:0] r_Count_2Hz = 0;
reg [31:0] r_Count_1Hz = 0;
always @(posedge i_Clk)
begin
if (r_Count_10Hz == g_COUNT_10HZ)
begin
o_LED_1 <= ~o_LED_1;
r_Count_10Hz <= 0;
end
else
r_Count_10Hz <= r_Count_10Hz + 1;
end
always @(posedge i_Clk)
begin
if (r_Count_5Hz == g_COUNT_5HZ)
begin
o_LED_2 <= ~o_LED_2;
r_Count_5Hz <= 0;
end
else
r_Count_5Hz <= r_Count_5Hz + 1;
end
always @(posedge i_Clk)
begin
if (r_Count_2Hz == g_COUNT_2HZ)
begin
o_LED_3 <= ~o_LED_3;
r_Count_2Hz <= 0;
end
else
r_Count_2Hz <= r_Count_2Hz + 1;
end
always @(posedge i_Clk)
begin
if (r_Count_1Hz == g_COUNT_1HZ)
begin
o_LED_4 <= ~o_LED_4;
r_Count_1Hz <= 0;
end
else
r_Count_1Hz <= r_Count_1Hz + 1;
end
endmodule | 2 |
141,169 | data/full_repos/permissive/93755996/Project6_LED_Blink/LED_Blink_Top.v | 93,755,996 | LED_Blink_Top.v | v | 14 | 25 | [] | [] | [] | [(1, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/93755996/Project6_LED_Blink/LED_Blink_Top.v:8: Cannot find file containing module: 'LED_Blink'\n LED_Blink Instance\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93755996/Project6_LED_Blink,data/full_repos/permissive/93755996/LED_Blink\n data/full_repos/permissive/93755996/Project6_LED_Blink,data/full_repos/permissive/93755996/LED_Blink.v\n data/full_repos/permissive/93755996/Project6_LED_Blink,data/full_repos/permissive/93755996/LED_Blink.sv\n LED_Blink\n LED_Blink.v\n LED_Blink.sv\n obj_dir/LED_Blink\n obj_dir/LED_Blink.v\n obj_dir/LED_Blink.sv\n%Error: Exiting due to 1 error(s)\n" | 310,924 | module | module LED_Blink_Top
(input i_Clk,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4);
LED_Blink Instance
(.i_Clk(i_Clk),
.o_LED_1(o_LED_1),
.o_LED_2(o_LED_2),
.o_LED_3(o_LED_3),
.o_LED_4(o_LED_4));
endmodule | module LED_Blink_Top
(input i_Clk,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4); |
LED_Blink Instance
(.i_Clk(i_Clk),
.o_LED_1(o_LED_1),
.o_LED_2(o_LED_2),
.o_LED_3(o_LED_3),
.o_LED_4(o_LED_4));
endmodule | 2 |
141,171 | data/full_repos/permissive/93755996/Project7.0_UART/Manual_UART_1Baud.v | 93,755,996 | Manual_UART_1Baud.v | v | 92 | 80 | [] | [] | [] | null | line:92: before: "/" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/93755996/Project7.0_UART/Manual_UART_1Baud.v:25: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg [0:7] r_Byte = 0;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/93755996/Project7.0_UART/Manual_UART_1Baud.v:38: Cannot find file containing module: \'Debounce_Switch\'\n Debounce_Switch Debounce_Switch\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93755996/Project7.0_UART,data/full_repos/permissive/93755996/Debounce_Switch\n data/full_repos/permissive/93755996/Project7.0_UART,data/full_repos/permissive/93755996/Debounce_Switch.v\n data/full_repos/permissive/93755996/Project7.0_UART,data/full_repos/permissive/93755996/Debounce_Switch.sv\n Debounce_Switch\n Debounce_Switch.v\n Debounce_Switch.sv\n obj_dir/Debounce_Switch\n obj_dir/Debounce_Switch.v\n obj_dir/Debounce_Switch.sv\n%Warning-WIDTH: data/full_repos/permissive/93755996/Project7.0_UART/Manual_UART_1Baud.v:59: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'i_Switch_2\' generates 1 bits.\n : ... In instance Manual_UART_1Baud\n r_Byte <= r_Byte * 2 + i_Switch_2;\n ^\n%Error: data/full_repos/permissive/93755996/Project7.0_UART/Manual_UART_1Baud.v:74: Cannot find file containing module: \'Byte_To_Seven_Segment_Display\'\n Byte_To_Seven_Segment_Display Byte_To_Seven_Segment_Display_a\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 310,927 | module | module Manual_UART_1Baud (
input i_Clk,
input i_Switch_2,
input i_Switch_4,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G,
output o_LED_3,
output o_LED_4
);
parameter CLKS_PER_BIT = 25000000;
reg [0:7] r_Byte = 0;
reg [31:0] c_SampleClock = 32'b0;
reg [3:0] r_DigitsToCapture = 4'b0;
reg r_Switch_2 = 1'b0;
reg r_Switch_4 = 1'b0;
reg r_Any_Switch = 1'b0;
reg r_LED_3 = 1'b0;
reg r_LED_4 = 1'b0;
wire w_Any_Switch;
Debounce_Switch Debounce_Switch
(.i_Clk(i_Clk),
.i_Switch(i_Switch_2 || i_Switch_4),
.o_Switch(w_Any_Switch));
always @(posedge i_Clk) begin
r_Switch_2 <= i_Switch_2;
r_Switch_4 <= i_Switch_4;
r_Any_Switch <= w_Any_Switch;
if (r_Any_Switch == 0 && w_Any_Switch == 1) begin
if (i_Switch_4 == 1) begin
r_Byte <= 0;
r_DigitsToCapture <= 8;
end
end
if (r_DigitsToCapture > 0) begin
if (c_SampleClock == CLKS_PER_BIT) begin
r_LED_3 <= ~r_LED_3;
r_Byte <= r_Byte * 2 + i_Switch_2;
c_SampleClock <= 0;
r_DigitsToCapture <= r_DigitsToCapture - 1;
end
else begin
c_SampleClock <= c_SampleClock + 1;
end
end
end
assign o_LED_3 = r_LED_3;
assign o_LED_4 = (r_DigitsToCapture > 0);
Byte_To_Seven_Segment_Display Byte_To_Seven_Segment_Display_a
(.i_Byte(r_Byte),
.o_Segment1_A(o_Segment1_A),
.o_Segment1_B(o_Segment1_B),
.o_Segment1_C(o_Segment1_C),
.o_Segment1_D(o_Segment1_D),
.o_Segment1_E(o_Segment1_E),
.o_Segment1_F(o_Segment1_F),
.o_Segment1_G(o_Segment1_G),
.o_Segment2_A(o_Segment2_A),
.o_Segment2_B(o_Segment2_B),
.o_Segment2_C(o_Segment2_C),
.o_Segment2_D(o_Segment2_D),
.o_Segment2_E(o_Segment2_E),
.o_Segment2_F(o_Segment2_F),
.o_Segment2_G(o_Segment2_G)
);
endmodule | module Manual_UART_1Baud (
input i_Clk,
input i_Switch_2,
input i_Switch_4,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G,
output o_LED_3,
output o_LED_4
); |
parameter CLKS_PER_BIT = 25000000;
reg [0:7] r_Byte = 0;
reg [31:0] c_SampleClock = 32'b0;
reg [3:0] r_DigitsToCapture = 4'b0;
reg r_Switch_2 = 1'b0;
reg r_Switch_4 = 1'b0;
reg r_Any_Switch = 1'b0;
reg r_LED_3 = 1'b0;
reg r_LED_4 = 1'b0;
wire w_Any_Switch;
Debounce_Switch Debounce_Switch
(.i_Clk(i_Clk),
.i_Switch(i_Switch_2 || i_Switch_4),
.o_Switch(w_Any_Switch));
always @(posedge i_Clk) begin
r_Switch_2 <= i_Switch_2;
r_Switch_4 <= i_Switch_4;
r_Any_Switch <= w_Any_Switch;
if (r_Any_Switch == 0 && w_Any_Switch == 1) begin
if (i_Switch_4 == 1) begin
r_Byte <= 0;
r_DigitsToCapture <= 8;
end
end
if (r_DigitsToCapture > 0) begin
if (c_SampleClock == CLKS_PER_BIT) begin
r_LED_3 <= ~r_LED_3;
r_Byte <= r_Byte * 2 + i_Switch_2;
c_SampleClock <= 0;
r_DigitsToCapture <= r_DigitsToCapture - 1;
end
else begin
c_SampleClock <= c_SampleClock + 1;
end
end
end
assign o_LED_3 = r_LED_3;
assign o_LED_4 = (r_DigitsToCapture > 0);
Byte_To_Seven_Segment_Display Byte_To_Seven_Segment_Display_a
(.i_Byte(r_Byte),
.o_Segment1_A(o_Segment1_A),
.o_Segment1_B(o_Segment1_B),
.o_Segment1_C(o_Segment1_C),
.o_Segment1_D(o_Segment1_D),
.o_Segment1_E(o_Segment1_E),
.o_Segment1_F(o_Segment1_F),
.o_Segment1_G(o_Segment1_G),
.o_Segment2_A(o_Segment2_A),
.o_Segment2_B(o_Segment2_B),
.o_Segment2_C(o_Segment2_C),
.o_Segment2_D(o_Segment2_D),
.o_Segment2_E(o_Segment2_E),
.o_Segment2_F(o_Segment2_F),
.o_Segment2_G(o_Segment2_G)
);
endmodule | 2 |
141,173 | data/full_repos/permissive/93755996/Project7.1_Variable_Rate_UART/Next_Baud_Rate.v | 93,755,996 | Next_Baud_Rate.v | v | 66 | 69 | [] | [] | [] | [(2, 65)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93755996/Project7.1_Variable_Rate_UART/Next_Baud_Rate.v:34: Operator VAR \'TICKS_PER_300_HZ\' expects 20 bits on the Initial value, but Initial value\'s DIVS generates 32 or 25 bits.\n : ... In instance Next_Baud_Rate\n parameter [19:0] TICKS_PER_300_HZ = CLOCK_SPEED / 300;\n ^~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93755996/Project7.1_Variable_Rate_UART/Next_Baud_Rate.v:35: Operator VAR \'TICKS_PER_38400_HZ\' expects 20 bits on the Initial value, but Initial value\'s DIVS generates 32 or 25 bits.\n : ... In instance Next_Baud_Rate\n parameter [19:0] TICKS_PER_38400_HZ = CLOCK_SPEED / 38400;\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93755996/Project7.1_Variable_Rate_UART/Next_Baud_Rate.v:36: Operator VAR \'TICKS_PER_57600_HZ\' expects 20 bits on the Initial value, but Initial value\'s DIVS generates 32 or 25 bits.\n : ... In instance Next_Baud_Rate\n parameter [19:0] TICKS_PER_57600_HZ = CLOCK_SPEED / 57600;\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93755996/Project7.1_Variable_Rate_UART/Next_Baud_Rate.v:37: Operator VAR \'TICKS_PER_921600_HZ\' expects 20 bits on the Initial value, but Initial value\'s DIVS generates 32 or 25 bits.\n : ... In instance Next_Baud_Rate\n parameter [19:0] TICKS_PER_921600_HZ = CLOCK_SPEED / 921600;\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 warning(s)\n' | 310,933 | module | module Next_Baud_Rate #(
parameter CLOCK_SPEED=25000000
) (
input [19:0] i_CurrentPeriod,
output [19:0] o_NextPeriod,
output [4:0] o_NextIndex
);
parameter [19:0] TICKS_PER_300_HZ = CLOCK_SPEED / 300;
parameter [19:0] TICKS_PER_38400_HZ = CLOCK_SPEED / 38400;
parameter [19:0] TICKS_PER_57600_HZ = CLOCK_SPEED / 57600;
parameter [19:0] TICKS_PER_921600_HZ = CLOCK_SPEED / 921600;
reg [19:0] r_Next;
reg [4:0] r_Index = 5'b0;
always @ ( * ) begin
if (i_CurrentPeriod == 0) begin
r_Next <= TICKS_PER_300_HZ;
r_Index <= 0;
end
else if (i_CurrentPeriod == TICKS_PER_38400_HZ) begin
r_Next <= TICKS_PER_57600_HZ;
r_Index <= r_Index + 1;
end
else if (i_CurrentPeriod === TICKS_PER_921600_HZ) begin
r_Next <= TICKS_PER_300_HZ;
r_Index <= 0;
end
else begin
r_Next <= i_CurrentPeriod >> 1;
r_Index <= r_Index + 1;
end
end
assign o_NextPeriod = r_Next;
assign o_NextIndex = r_Index;
endmodule | module Next_Baud_Rate #(
parameter CLOCK_SPEED=25000000
) (
input [19:0] i_CurrentPeriod,
output [19:0] o_NextPeriod,
output [4:0] o_NextIndex
); |
parameter [19:0] TICKS_PER_300_HZ = CLOCK_SPEED / 300;
parameter [19:0] TICKS_PER_38400_HZ = CLOCK_SPEED / 38400;
parameter [19:0] TICKS_PER_57600_HZ = CLOCK_SPEED / 57600;
parameter [19:0] TICKS_PER_921600_HZ = CLOCK_SPEED / 921600;
reg [19:0] r_Next;
reg [4:0] r_Index = 5'b0;
always @ ( * ) begin
if (i_CurrentPeriod == 0) begin
r_Next <= TICKS_PER_300_HZ;
r_Index <= 0;
end
else if (i_CurrentPeriod == TICKS_PER_38400_HZ) begin
r_Next <= TICKS_PER_57600_HZ;
r_Index <= r_Index + 1;
end
else if (i_CurrentPeriod === TICKS_PER_921600_HZ) begin
r_Next <= TICKS_PER_300_HZ;
r_Index <= 0;
end
else begin
r_Next <= i_CurrentPeriod >> 1;
r_Index <= r_Index + 1;
end
end
assign o_NextPeriod = r_Next;
assign o_NextIndex = r_Index;
endmodule | 2 |
141,183 | data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer/Byte_To_Seven_Segment_Display.v | 93,755,996 | Byte_To_Seven_Segment_Display.v | v | 40 | 50 | [] | [] | [] | [(1, 40)] | null | null | 1: b"%Error: data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer/Byte_To_Seven_Segment_Display.v:19: Cannot find file containing module: 'Seven_Segment_Display'\n Seven_Segment_Display Seven_Segment_Display_1 (\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer,data/full_repos/permissive/93755996/Seven_Segment_Display\n data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer,data/full_repos/permissive/93755996/Seven_Segment_Display.v\n data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer,data/full_repos/permissive/93755996/Seven_Segment_Display.sv\n Seven_Segment_Display\n Seven_Segment_Display.v\n Seven_Segment_Display.sv\n obj_dir/Seven_Segment_Display\n obj_dir/Seven_Segment_Display.v\n obj_dir/Seven_Segment_Display.sv\n%Error: data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer/Byte_To_Seven_Segment_Display.v:29: Cannot find file containing module: 'Seven_Segment_Display'\n Seven_Segment_Display Seven_Segment_Display_2 (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 310,950 | module | module Byte_To_Seven_Segment_Display (
input [7:0] i_Byte,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G
);
Seven_Segment_Display Seven_Segment_Display_1 (
.i_Nibble(i_Byte[7:4]),
.o_Segment_A(o_Segment1_A),
.o_Segment_B(o_Segment1_B),
.o_Segment_C(o_Segment1_C),
.o_Segment_D(o_Segment1_D),
.o_Segment_E(o_Segment1_E),
.o_Segment_F(o_Segment1_F),
.o_Segment_G(o_Segment1_G)
);
Seven_Segment_Display Seven_Segment_Display_2 (
.i_Nibble(i_Byte[3:0]),
.o_Segment_A(o_Segment2_A),
.o_Segment_B(o_Segment2_B),
.o_Segment_C(o_Segment2_C),
.o_Segment_D(o_Segment2_D),
.o_Segment_E(o_Segment2_E),
.o_Segment_F(o_Segment2_F),
.o_Segment_G(o_Segment2_G)
);
endmodule | module Byte_To_Seven_Segment_Display (
input [7:0] i_Byte,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G
); |
Seven_Segment_Display Seven_Segment_Display_1 (
.i_Nibble(i_Byte[7:4]),
.o_Segment_A(o_Segment1_A),
.o_Segment_B(o_Segment1_B),
.o_Segment_C(o_Segment1_C),
.o_Segment_D(o_Segment1_D),
.o_Segment_E(o_Segment1_E),
.o_Segment_F(o_Segment1_F),
.o_Segment_G(o_Segment1_G)
);
Seven_Segment_Display Seven_Segment_Display_2 (
.i_Nibble(i_Byte[3:0]),
.o_Segment_A(o_Segment2_A),
.o_Segment_B(o_Segment2_B),
.o_Segment_C(o_Segment2_C),
.o_Segment_D(o_Segment2_D),
.o_Segment_E(o_Segment2_E),
.o_Segment_F(o_Segment2_F),
.o_Segment_G(o_Segment2_G)
);
endmodule | 2 |
141,185 | data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer/Rising_Edge_Detector.v | 93,755,996 | Rising_Edge_Detector.v | v | 16 | 61 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/69aa779a-b0af-4b56-9b40-886ed6156f83.xml | null | 310,952 | module | module Rising_Edge_Detector (
input i_Clk,
input i_Signal,
output o_Pulse
);
reg r_Signal_1 = 1'b0;
reg r_Output = 1'b0;
always @(posedge i_Clk)
r_Signal_1 <= i_Signal;
assign o_Pulse = (i_Signal == 1'b1 && r_Signal_1 == 1'b0);
endmodule | module Rising_Edge_Detector (
input i_Clk,
input i_Signal,
output o_Pulse
); |
reg r_Signal_1 = 1'b0;
reg r_Output = 1'b0;
always @(posedge i_Clk)
r_Signal_1 <= i_Signal;
assign o_Pulse = (i_Signal == 1'b1 && r_Signal_1 == 1'b0);
endmodule | 2 |
141,186 | data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer/Small_FIFO.v | 93,755,996 | Small_FIFO.v | v | 51 | 58 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93755996/Project8.1_UART_Stream_Buffer/Small_FIFO.v:47: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_Free_Space\' generates 4 bits.\n : ... In instance Small_FIFO\n assign o_Free_Space = r_Free_Space;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 310,955 | module | module Small_FIFO (
input i_Rst,
input i_Clk,
input i_Append_Now,
input i_Shift_Now,
input [7:0] i_Byte,
output [7:0] o_Byte,
output o_Ready_To_Read,
output o_Ready_To_Write,
output [2:0] o_Free_Space
);
parameter BUFFER_SIZE = 8;
reg [7:0] r_Memory [BUFFER_SIZE-1:0];
reg [3:0] r_Free_Space = BUFFER_SIZE;
always @(posedge i_Clk) begin
if (i_Rst == 1'b1) begin
r_Memory[7] = 8'b0;
r_Memory[6] = 8'b0;
r_Memory[5] = 8'b0;
r_Memory[4] = 8'b0;
r_Memory[3] = 8'b0;
r_Memory[2] = 8'b0;
r_Memory[1] = 8'b0;
r_Memory[0] = 8'b0;
r_Free_Space = BUFFER_SIZE;
end else begin
if (i_Append_Now == 1'b1 && r_Free_Space > 0) begin
r_Memory[r_Free_Space-1] = i_Byte;
r_Free_Space = r_Free_Space - 1;
end
if (i_Shift_Now == 1'b1) begin
if (r_Free_Space < BUFFER_SIZE)
r_Free_Space = r_Free_Space + 1;
r_Memory[7] = r_Memory[6];
r_Memory[6] = r_Memory[5];
r_Memory[5] = r_Memory[4];
r_Memory[4] = r_Memory[3];
r_Memory[3] = r_Memory[2];
r_Memory[2] = r_Memory[1];
r_Memory[1] = r_Memory[0];
end
end
end
assign o_Byte = r_Memory[BUFFER_SIZE-1];
assign o_Free_Space = r_Free_Space;
assign o_Ready_To_Read = r_Free_Space < BUFFER_SIZE;
assign o_Ready_To_Write = r_Free_Space > 0;
endmodule | module Small_FIFO (
input i_Rst,
input i_Clk,
input i_Append_Now,
input i_Shift_Now,
input [7:0] i_Byte,
output [7:0] o_Byte,
output o_Ready_To_Read,
output o_Ready_To_Write,
output [2:0] o_Free_Space
); |
parameter BUFFER_SIZE = 8;
reg [7:0] r_Memory [BUFFER_SIZE-1:0];
reg [3:0] r_Free_Space = BUFFER_SIZE;
always @(posedge i_Clk) begin
if (i_Rst == 1'b1) begin
r_Memory[7] = 8'b0;
r_Memory[6] = 8'b0;
r_Memory[5] = 8'b0;
r_Memory[4] = 8'b0;
r_Memory[3] = 8'b0;
r_Memory[2] = 8'b0;
r_Memory[1] = 8'b0;
r_Memory[0] = 8'b0;
r_Free_Space = BUFFER_SIZE;
end else begin
if (i_Append_Now == 1'b1 && r_Free_Space > 0) begin
r_Memory[r_Free_Space-1] = i_Byte;
r_Free_Space = r_Free_Space - 1;
end
if (i_Shift_Now == 1'b1) begin
if (r_Free_Space < BUFFER_SIZE)
r_Free_Space = r_Free_Space + 1;
r_Memory[7] = r_Memory[6];
r_Memory[6] = r_Memory[5];
r_Memory[5] = r_Memory[4];
r_Memory[4] = r_Memory[3];
r_Memory[3] = r_Memory[2];
r_Memory[2] = r_Memory[1];
r_Memory[1] = r_Memory[0];
end
end
end
assign o_Byte = r_Memory[BUFFER_SIZE-1];
assign o_Free_Space = r_Free_Space;
assign o_Ready_To_Read = r_Free_Space < BUFFER_SIZE;
assign o_Ready_To_Write = r_Free_Space > 0;
endmodule | 2 |
141,194 | data/full_repos/permissive/93755996/Project9.2_VGA_Gradient/Main.v | 93,755,996 | Main.v | v | 146 | 162 | [] | [] | [] | null | line:29: before: "input" | null | 1: b'%Error: data/full_repos/permissive/93755996/Project9.2_VGA_Gradient/Main.v:1: Cannot find include file: Debounce_Switch.v\n`include "Debounce_Switch.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93755996/Project9.2_VGA_Gradient,data/full_repos/permissive/93755996/Debounce_Switch.v\n data/full_repos/permissive/93755996/Project9.2_VGA_Gradient,data/full_repos/permissive/93755996/Debounce_Switch.v.v\n data/full_repos/permissive/93755996/Project9.2_VGA_Gradient,data/full_repos/permissive/93755996/Debounce_Switch.v.sv\n Debounce_Switch.v\n Debounce_Switch.v.v\n Debounce_Switch.v.sv\n obj_dir/Debounce_Switch.v\n obj_dir/Debounce_Switch.v.v\n obj_dir/Debounce_Switch.v.sv\n%Error: data/full_repos/permissive/93755996/Project9.2_VGA_Gradient/Main.v:2: Cannot find include file: VGA_Controller.v\n`include "VGA_Controller.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/93755996/Project9.2_VGA_Gradient/Main.v:3: Cannot find include file: Stateless_Seven_Segment_Display.v\n`include "Stateless_Seven_Segment_Display.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/93755996/Project9.2_VGA_Gradient/Main.v:4: Cannot find include file: Byte_To_Seven_Segment_Display.v\n`include "Byte_To_Seven_Segment_Display.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 310,971 | module | module Main (
input i_Clk,
input i_Switch_1, input i_Switch_2, input i_Switch_3, input i_Switch_4,
output o_LED_1, output o_LED_2, output o_LED_3, output o_LED_4,
output io_PMOD_1, output io_PMOD_2, output io_PMOD_3, output io_PMOD_4,
output io_PMOD_7, output io_PMOD_8, output io_PMOD_9, output io_PMOD_10,
output o_Segment1_A, output o_Segment1_B, output o_Segment1_C, output o_Segment1_D, output o_Segment1_E, output o_Segment1_F, output o_Segment1_G,
output o_Segment2_A, output o_Segment2_B, output o_Segment2_C, output o_Segment2_D, output o_Segment2_E, output o_Segment2_F, output o_Segment2_G,
output o_VGA_Red_0, output o_VGA_Red_1, output o_VGA_Red_2,
output o_VGA_Grn_0, output o_VGA_Grn_1, output o_VGA_Grn_2,
output o_VGA_Blu_0, output o_VGA_Blu_1, output o_VGA_Blu_2,
output o_VGA_HSync, output o_VGA_VSync
);
reg r_Any_Switch = 1'b0;
wire w_Any_Switch;
wire w_Reset = i_Switch_1 && w_Any_Switch;
Debounce_Switch Debounce_Switch
(.i_Clk(i_Clk),
.i_Switch(i_Switch_1 || i_Switch_2 || i_Switch_3 || i_Switch_4),
.o_Switch(w_Any_Switch));
reg [7:0] col = 0;
reg [7:0] row = 0;
Byte_To_Seven_Segment_Display Byte_To_Seven_Segment_Display_a
(.i_Byte({row, col}),
.o_Segment1_A(o_Segment1_A),
.o_Segment1_B(o_Segment1_B),
.o_Segment1_C(o_Segment1_C),
.o_Segment1_D(o_Segment1_D),
.o_Segment1_E(o_Segment1_E),
.o_Segment1_F(o_Segment1_F),
.o_Segment1_G(o_Segment1_G),
.o_Segment2_A(o_Segment2_A),
.o_Segment2_B(o_Segment2_B),
.o_Segment2_C(o_Segment2_C),
.o_Segment2_D(o_Segment2_D),
.o_Segment2_E(o_Segment2_E),
.o_Segment2_F(o_Segment2_F),
.o_Segment2_G(o_Segment2_G)
);
wire [11:0] r_X;
wire [11:0] r_Y;
VGA_Controller VGA_Controller_1 (
.i_Clk(i_Clk),
.i_Reset(w_Reset),
.i_VGA_Red(A_Red),
.i_VGA_Grn(A_Grn),
.i_VGA_Blu(A_Blu),
.o_X(r_X),
.o_Y(r_Y),
.o_VGA_HSync(o_VGA_HSync),
.o_VGA_VSync(o_VGA_VSync),
.o_VGA_Red_2(o_VGA_Red_2),
.o_VGA_Red_1(o_VGA_Red_1),
.o_VGA_Red_0(o_VGA_Red_0),
.o_VGA_Grn_2(o_VGA_Grn_2),
.o_VGA_Grn_1(o_VGA_Grn_1),
.o_VGA_Grn_0(o_VGA_Grn_0),
.o_VGA_Blu_2(o_VGA_Blu_2),
.o_VGA_Blu_1(o_VGA_Blu_1),
.o_VGA_Blu_0(o_VGA_Blu_0)
);
always @ (posedge i_Clk) begin
if (w_Reset === 1'b1) begin
col <= 0;
row <= 0;
end else begin
if (r_X < 80) col <= 0;
else if (r_X < 80*2) col <= 1;
else if (r_X < 80*3) col <= 2;
else if (r_X < 80*4) col <= 3;
else if (r_X < 80*5) col <= 4;
else if (r_X < 80*6) col <= 5;
else if (r_X < 80*7) col <= 6;
else if (r_X < 80*8) col <= 7;
else col <= 8;
if (r_Y < 80) row <= 0;
else if (r_Y < 80*2) row <= 1;
else if (r_Y < 80*3) row <= 2;
else if (r_Y < 80*4) row <= 3;
else if (r_Y < 80*5) row <= 4;
else if (r_Y < 80*6) row <= 5;
else row <= 6;
end
end
reg A_Red [2:0] = 3'b0;
reg A_Grn [2:0] = 3'b0;
reg A_Blu [2:0] = 3'b0;
always @ ( * ) begin
if (col === 7) begin
A_Red = 7 - (r_Y / 60);
A_Grn = 7 - (r_Y / 60);
A_Blu = 7 - (r_Y / 60);
end else begin
if (row === 0 || row === 1 || row == 5)
A_Red = col + 1;
else
A_Red = 3'b0;
if (0 < row && row < 4)
A_Grn = col + 1;
else
A_Grn = 3'b0;
if (2 < row && row < 6)
A_Blu = col + 1;
else
A_Blu = 3'b0;
end
end
endmodule | module Main (
input i_Clk,
input i_Switch_1, input i_Switch_2, input i_Switch_3, input i_Switch_4,
output o_LED_1, output o_LED_2, output o_LED_3, output o_LED_4,
output io_PMOD_1, output io_PMOD_2, output io_PMOD_3, output io_PMOD_4,
output io_PMOD_7, output io_PMOD_8, output io_PMOD_9, output io_PMOD_10,
output o_Segment1_A, output o_Segment1_B, output o_Segment1_C, output o_Segment1_D, output o_Segment1_E, output o_Segment1_F, output o_Segment1_G,
output o_Segment2_A, output o_Segment2_B, output o_Segment2_C, output o_Segment2_D, output o_Segment2_E, output o_Segment2_F, output o_Segment2_G,
output o_VGA_Red_0, output o_VGA_Red_1, output o_VGA_Red_2,
output o_VGA_Grn_0, output o_VGA_Grn_1, output o_VGA_Grn_2,
output o_VGA_Blu_0, output o_VGA_Blu_1, output o_VGA_Blu_2,
output o_VGA_HSync, output o_VGA_VSync
); |
reg r_Any_Switch = 1'b0;
wire w_Any_Switch;
wire w_Reset = i_Switch_1 && w_Any_Switch;
Debounce_Switch Debounce_Switch
(.i_Clk(i_Clk),
.i_Switch(i_Switch_1 || i_Switch_2 || i_Switch_3 || i_Switch_4),
.o_Switch(w_Any_Switch));
reg [7:0] col = 0;
reg [7:0] row = 0;
Byte_To_Seven_Segment_Display Byte_To_Seven_Segment_Display_a
(.i_Byte({row, col}),
.o_Segment1_A(o_Segment1_A),
.o_Segment1_B(o_Segment1_B),
.o_Segment1_C(o_Segment1_C),
.o_Segment1_D(o_Segment1_D),
.o_Segment1_E(o_Segment1_E),
.o_Segment1_F(o_Segment1_F),
.o_Segment1_G(o_Segment1_G),
.o_Segment2_A(o_Segment2_A),
.o_Segment2_B(o_Segment2_B),
.o_Segment2_C(o_Segment2_C),
.o_Segment2_D(o_Segment2_D),
.o_Segment2_E(o_Segment2_E),
.o_Segment2_F(o_Segment2_F),
.o_Segment2_G(o_Segment2_G)
);
wire [11:0] r_X;
wire [11:0] r_Y;
VGA_Controller VGA_Controller_1 (
.i_Clk(i_Clk),
.i_Reset(w_Reset),
.i_VGA_Red(A_Red),
.i_VGA_Grn(A_Grn),
.i_VGA_Blu(A_Blu),
.o_X(r_X),
.o_Y(r_Y),
.o_VGA_HSync(o_VGA_HSync),
.o_VGA_VSync(o_VGA_VSync),
.o_VGA_Red_2(o_VGA_Red_2),
.o_VGA_Red_1(o_VGA_Red_1),
.o_VGA_Red_0(o_VGA_Red_0),
.o_VGA_Grn_2(o_VGA_Grn_2),
.o_VGA_Grn_1(o_VGA_Grn_1),
.o_VGA_Grn_0(o_VGA_Grn_0),
.o_VGA_Blu_2(o_VGA_Blu_2),
.o_VGA_Blu_1(o_VGA_Blu_1),
.o_VGA_Blu_0(o_VGA_Blu_0)
);
always @ (posedge i_Clk) begin
if (w_Reset === 1'b1) begin
col <= 0;
row <= 0;
end else begin
if (r_X < 80) col <= 0;
else if (r_X < 80*2) col <= 1;
else if (r_X < 80*3) col <= 2;
else if (r_X < 80*4) col <= 3;
else if (r_X < 80*5) col <= 4;
else if (r_X < 80*6) col <= 5;
else if (r_X < 80*7) col <= 6;
else if (r_X < 80*8) col <= 7;
else col <= 8;
if (r_Y < 80) row <= 0;
else if (r_Y < 80*2) row <= 1;
else if (r_Y < 80*3) row <= 2;
else if (r_Y < 80*4) row <= 3;
else if (r_Y < 80*5) row <= 4;
else if (r_Y < 80*6) row <= 5;
else row <= 6;
end
end
reg A_Red [2:0] = 3'b0;
reg A_Grn [2:0] = 3'b0;
reg A_Blu [2:0] = 3'b0;
always @ ( * ) begin
if (col === 7) begin
A_Red = 7 - (r_Y / 60);
A_Grn = 7 - (r_Y / 60);
A_Blu = 7 - (r_Y / 60);
end else begin
if (row === 0 || row === 1 || row == 5)
A_Red = col + 1;
else
A_Red = 3'b0;
if (0 < row && row < 4)
A_Grn = col + 1;
else
A_Grn = 3'b0;
if (2 < row && row < 6)
A_Blu = col + 1;
else
A_Blu = 3'b0;
end
end
endmodule | 2 |
141,200 | data/full_repos/permissive/93755996/Project9.5_VGA_Fonts/VGA_Controller.v | 93,755,996 | VGA_Controller.v | v | 130 | 67 | [] | [] | [] | [(1, 130)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93755996/Project9.5_VGA_Fonts/VGA_Controller.v:113: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_HCounter\' generates 12 bits.\n : ... In instance VGA_Controller\n assign o_HCounter = r_HCounter;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93755996/Project9.5_VGA_Fonts/VGA_Controller.v:114: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_VCounter\' generates 12 bits.\n : ... In instance VGA_Controller\n assign o_VCounter = r_VCounter;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 310,996 | module | module VGA_Controller (
input i_Clk,
input i_Reset,
input [2:0] i_VGA_Red,
input [2:0] i_VGA_Grn,
input [2:0] i_VGA_Blu,
output [11:0] o_X,
output [11:0] o_Y,
output o_Active,
output o_VGA_HSync,
output o_VGA_VSync,
output o_VGA_Red_2,
output o_VGA_Red_1,
output o_VGA_Red_0,
output o_VGA_Grn_2,
output o_VGA_Grn_1,
output o_VGA_Grn_0,
output o_VGA_Blu_2,
output o_VGA_Blu_1,
output o_VGA_Blu_0,
output o_HCounter,
output o_VCounter
);
parameter LEAD_CYCLES = 12'd0;
parameter H_TOTAL_WIDTH = 12'd800;
parameter H_VISIBLE_WIDTH = 12'd640;
parameter H_FRONT_PORCH = 12'd18;
parameter H_BACK_PORCH = 12'd50;
parameter H_START = H_VISIBLE_WIDTH + H_FRONT_PORCH;
parameter H_FINISH = H_TOTAL_WIDTH - H_BACK_PORCH;
parameter V_TOTAL_HEIGHT = 12'd525;
parameter V_VISIBLE_HEIGHT = 12'd480;
parameter V_FRONT_PORCH = 12'd10;
parameter V_BACK_PORCH = 12'd33;
parameter V_START = V_VISIBLE_HEIGHT + V_FRONT_PORCH;
parameter V_FINISH = V_TOTAL_HEIGHT - V_BACK_PORCH;
reg [2:0] r_VGA_Red;
reg [2:0] r_VGA_Grn;
reg [2:0] r_VGA_Blu;
reg [11:0] r_HCounter = 12'b0;
reg [11:0] r_VCounter = 12'b0;
reg [11:0] r_X = LEAD_CYCLES;
reg [11:0] r_Y = 12'b0;
reg r_HSync = 1'b1;
reg r_VSync = 1'b1;
reg r_Active = 1'b0;
always @ (posedge i_Clk) begin
if (i_Reset === 1'b1) begin
r_HCounter <= 12'b0;
r_VCounter <= 12'b0;
r_HSync <= 1'b0;
r_VSync <= 1'b0;
r_X <= LEAD_CYCLES;
r_Y <= 12'b0;
end else begin
if (r_HCounter === H_TOTAL_WIDTH - 1) begin
r_HCounter <= 12'b0;
if (r_VCounter === V_TOTAL_HEIGHT - 1) begin
r_VCounter <= 12'b0;
r_X <= LEAD_CYCLES;
end else begin
r_VCounter <= r_VCounter + 1;
end
end else begin
r_HCounter <= r_HCounter + 1;
end
if (r_X === H_TOTAL_WIDTH - 1) begin
r_X <= 12'b0;
if (r_Y === V_TOTAL_HEIGHT - 1) begin
r_Y <= 12'b0;
end else begin
r_Y <= r_Y + 1;
end
end else begin
r_X <= r_X + 1;
end
end
if (r_HCounter == H_START)
r_HSync <= 1'b0;
else if (r_HCounter == H_FINISH)
r_HSync <= 1'b1;
if (r_VCounter == V_START)
r_VSync <= 1'b0;
else if (r_VCounter == V_FINISH)
r_VSync <= 1'b1;
r_Active <= (r_HCounter < 12'd640) && (r_VCounter < 12'd480);
r_VGA_Red <= i_VGA_Red;
r_VGA_Grn <= i_VGA_Grn;
r_VGA_Blu <= i_VGA_Blu;
end
assign o_X = r_X;
assign o_Y = r_Y;
assign o_Active = r_Active;
assign o_HCounter = r_HCounter;
assign o_VCounter = r_VCounter;
assign o_VGA_HSync = r_HSync;
assign o_VGA_VSync = r_VSync;
assign o_VGA_Red_2 = r_Active && r_VGA_Red[2];
assign o_VGA_Red_1 = r_Active && r_VGA_Red[1];
assign o_VGA_Red_0 = r_Active && r_VGA_Red[0];
assign o_VGA_Grn_2 = r_Active && r_VGA_Grn[2];
assign o_VGA_Grn_1 = r_Active && r_VGA_Grn[1];
assign o_VGA_Grn_0 = r_Active && r_VGA_Grn[0];
assign o_VGA_Blu_2 = r_Active && r_VGA_Blu[2];
assign o_VGA_Blu_1 = r_Active && r_VGA_Blu[1];
assign o_VGA_Blu_0 = r_Active && r_VGA_Blu[0];
endmodule | module VGA_Controller (
input i_Clk,
input i_Reset,
input [2:0] i_VGA_Red,
input [2:0] i_VGA_Grn,
input [2:0] i_VGA_Blu,
output [11:0] o_X,
output [11:0] o_Y,
output o_Active,
output o_VGA_HSync,
output o_VGA_VSync,
output o_VGA_Red_2,
output o_VGA_Red_1,
output o_VGA_Red_0,
output o_VGA_Grn_2,
output o_VGA_Grn_1,
output o_VGA_Grn_0,
output o_VGA_Blu_2,
output o_VGA_Blu_1,
output o_VGA_Blu_0,
output o_HCounter,
output o_VCounter
); |
parameter LEAD_CYCLES = 12'd0;
parameter H_TOTAL_WIDTH = 12'd800;
parameter H_VISIBLE_WIDTH = 12'd640;
parameter H_FRONT_PORCH = 12'd18;
parameter H_BACK_PORCH = 12'd50;
parameter H_START = H_VISIBLE_WIDTH + H_FRONT_PORCH;
parameter H_FINISH = H_TOTAL_WIDTH - H_BACK_PORCH;
parameter V_TOTAL_HEIGHT = 12'd525;
parameter V_VISIBLE_HEIGHT = 12'd480;
parameter V_FRONT_PORCH = 12'd10;
parameter V_BACK_PORCH = 12'd33;
parameter V_START = V_VISIBLE_HEIGHT + V_FRONT_PORCH;
parameter V_FINISH = V_TOTAL_HEIGHT - V_BACK_PORCH;
reg [2:0] r_VGA_Red;
reg [2:0] r_VGA_Grn;
reg [2:0] r_VGA_Blu;
reg [11:0] r_HCounter = 12'b0;
reg [11:0] r_VCounter = 12'b0;
reg [11:0] r_X = LEAD_CYCLES;
reg [11:0] r_Y = 12'b0;
reg r_HSync = 1'b1;
reg r_VSync = 1'b1;
reg r_Active = 1'b0;
always @ (posedge i_Clk) begin
if (i_Reset === 1'b1) begin
r_HCounter <= 12'b0;
r_VCounter <= 12'b0;
r_HSync <= 1'b0;
r_VSync <= 1'b0;
r_X <= LEAD_CYCLES;
r_Y <= 12'b0;
end else begin
if (r_HCounter === H_TOTAL_WIDTH - 1) begin
r_HCounter <= 12'b0;
if (r_VCounter === V_TOTAL_HEIGHT - 1) begin
r_VCounter <= 12'b0;
r_X <= LEAD_CYCLES;
end else begin
r_VCounter <= r_VCounter + 1;
end
end else begin
r_HCounter <= r_HCounter + 1;
end
if (r_X === H_TOTAL_WIDTH - 1) begin
r_X <= 12'b0;
if (r_Y === V_TOTAL_HEIGHT - 1) begin
r_Y <= 12'b0;
end else begin
r_Y <= r_Y + 1;
end
end else begin
r_X <= r_X + 1;
end
end
if (r_HCounter == H_START)
r_HSync <= 1'b0;
else if (r_HCounter == H_FINISH)
r_HSync <= 1'b1;
if (r_VCounter == V_START)
r_VSync <= 1'b0;
else if (r_VCounter == V_FINISH)
r_VSync <= 1'b1;
r_Active <= (r_HCounter < 12'd640) && (r_VCounter < 12'd480);
r_VGA_Red <= i_VGA_Red;
r_VGA_Grn <= i_VGA_Grn;
r_VGA_Blu <= i_VGA_Blu;
end
assign o_X = r_X;
assign o_Y = r_Y;
assign o_Active = r_Active;
assign o_HCounter = r_HCounter;
assign o_VCounter = r_VCounter;
assign o_VGA_HSync = r_HSync;
assign o_VGA_VSync = r_VSync;
assign o_VGA_Red_2 = r_Active && r_VGA_Red[2];
assign o_VGA_Red_1 = r_Active && r_VGA_Red[1];
assign o_VGA_Red_0 = r_Active && r_VGA_Red[0];
assign o_VGA_Grn_2 = r_Active && r_VGA_Grn[2];
assign o_VGA_Grn_1 = r_Active && r_VGA_Grn[1];
assign o_VGA_Grn_0 = r_Active && r_VGA_Grn[0];
assign o_VGA_Blu_2 = r_Active && r_VGA_Blu[2];
assign o_VGA_Blu_1 = r_Active && r_VGA_Blu[1];
assign o_VGA_Blu_0 = r_Active && r_VGA_Blu[0];
endmodule | 2 |
141,201 | data/full_repos/permissive/93755996/Project9.6_VGA_Remote_Buffer/Virtual_RAM.v | 93,755,996 | Virtual_RAM.v | v | 51 | 69 | [] | [] | [] | null | line:22: before: "module" | null | 1: b'%Error: data/full_repos/permissive/93755996/Project9.6_VGA_Remote_Buffer/Virtual_RAM.v:51: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n' | 311,007 | module | module Virtual_RAM (
input i_Clk,
input i_Perform_Write,
input [addr_width-1:0] i_Write_Address,
input [data_width-1:0] i_Write_Data,
input i_Perform_Read,
input [addr_width-1:0] i_Read_Address,
output [addr_width-1:0] o_Read_Address,
output reg [data_width-1:0] o_Read_Data,
output reg o_Ready_Write,
output reg o_Ready_Read
);
parameter addr_width = 12;
parameter data_width = 8;
reg [addr_width-1:0] r_Write_Address;
reg [addr_width-1:0] r_Read_Address;
reg [data_width-1:0] r_Write_Data;
reg [data_width-1:0] r_Read_Data;
module Rising_Edge_Detector (
input i_Clk,
input i_Perform_Write,
output w_Perform_Write_Now
);
module Rising_Edge_Detector (
input i_Clk,
input i_Perform_Read,
output w_Perform_Read_Now
);
always @(posedge i_Clk) begin
if (w_Perform_Write_Now == 1'b1) begin
r_Write_Address <= i_Write_Address;
r_Write_Data <= i_Write_Data;
end
if (w_Perform_Read_Now == 1'b1) begin
r_Read_Address <= i_Read_Address;
r_Read_Data <= i_Read_Data;
end
if (i_Write_Enable && i_Write_Address < 2400)
mem[i_Write_Address] <= i_Data_In;
if (i_Read_Address < 2400)
o_Data_Out <= mem[i_Read_Address];
else
o_Data_Out <= 0;
endmodule | module Virtual_RAM (
input i_Clk,
input i_Perform_Write,
input [addr_width-1:0] i_Write_Address,
input [data_width-1:0] i_Write_Data,
input i_Perform_Read,
input [addr_width-1:0] i_Read_Address,
output [addr_width-1:0] o_Read_Address,
output reg [data_width-1:0] o_Read_Data,
output reg o_Ready_Write,
output reg o_Ready_Read
); |
parameter addr_width = 12;
parameter data_width = 8;
reg [addr_width-1:0] r_Write_Address;
reg [addr_width-1:0] r_Read_Address;
reg [data_width-1:0] r_Write_Data;
reg [data_width-1:0] r_Read_Data;
module Rising_Edge_Detector (
input i_Clk,
input i_Perform_Write,
output w_Perform_Write_Now
);
module Rising_Edge_Detector (
input i_Clk,
input i_Perform_Read,
output w_Perform_Read_Now
);
always @(posedge i_Clk) begin
if (w_Perform_Write_Now == 1'b1) begin
r_Write_Address <= i_Write_Address;
r_Write_Data <= i_Write_Data;
end
if (w_Perform_Read_Now == 1'b1) begin
r_Read_Address <= i_Read_Address;
r_Read_Data <= i_Read_Data;
end
if (i_Write_Enable && i_Write_Address < 2400)
mem[i_Write_Address] <= i_Data_In;
if (i_Read_Address < 2400)
o_Data_Out <= mem[i_Read_Address];
else
o_Data_Out <= 0;
endmodule | 2 |
141,203 | data/full_repos/permissive/93808810/button.v | 93,808,810 | button.v | v | 30 | 48 | [] | [] | [] | null | line:2 column:12: Illegal character '©' | null | 1: b'%Error: data/full_repos/permissive/93808810/button.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/button.v:6: Define or directive not defined: \'`c_ms\'\n parameter DEB_CMAX = `c_ms(5);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n' | 311,012 | module | module button(tr_btn, a_btn, lock, clk, rst_n);
parameter DEB_CMAX = `c_ms(5);
output tr_btn;
input a_btn;
input lock, clk, rst_n;
reg r_lock = 'b0;
wire pe_btn, ne_btn;
assign tr_btn = ne_btn && !r_lock && !lock;
always @(posedge clk)
if (!rst_n)
r_lock <= 'b0;
else if (pe_btn)
r_lock <= lock;
debouncer #(
.DEB_CMAX(DEB_CMAX)
) x_deb_btn(
.sig(),
.pe_sig(pe_btn),
.ne_sig(ne_btn),
.a_sig(a_btn),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module button(tr_btn, a_btn, lock, clk, rst_n); |
parameter DEB_CMAX = `c_ms(5);
output tr_btn;
input a_btn;
input lock, clk, rst_n;
reg r_lock = 'b0;
wire pe_btn, ne_btn;
assign tr_btn = ne_btn && !r_lock && !lock;
always @(posedge clk)
if (!rst_n)
r_lock <= 'b0;
else if (pe_btn)
r_lock <= lock;
debouncer #(
.DEB_CMAX(DEB_CMAX)
) x_deb_btn(
.sig(),
.pe_sig(pe_btn),
.ne_sig(ne_btn),
.a_sig(a_btn),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,204 | data/full_repos/permissive/93808810/buzzer.v | 93,808,810 | buzzer.v | v | 88 | 77 | [] | [] | [] | [(10, 34), (36, 63), (65, 92)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/buzzer.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/buzzer.v:6: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/buzzer.v:32: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/buzzer.v:61: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: Exiting due to 4 error(s)\n' | 311,013 | module | module buzzer(buz, tr_a, tr_b, clk, rst_n);
parameter FLA_CMAX = `c_ms(100);
output buz;
input tr_a, tr_b;
input clk, rst_n;
wire buz_a, buz_b;
assign buz = buz_a || buz_b;
_buz_a #(
.FLA_CMAX(FLA_CMAX)
) x_buz_a(
.buz(buz_a),
.tr_sig(tr_a),
.clk(clk),
.rst_n(rst_n)
);
_buz_b #(
.FLA_CMAX(FLA_CMAX)
) x_buz_b(
.buz(buz_b),
.tr_sig(tr_b),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module buzzer(buz, tr_a, tr_b, clk, rst_n); |
parameter FLA_CMAX = `c_ms(100);
output buz;
input tr_a, tr_b;
input clk, rst_n;
wire buz_a, buz_b;
assign buz = buz_a || buz_b;
_buz_a #(
.FLA_CMAX(FLA_CMAX)
) x_buz_a(
.buz(buz_a),
.tr_sig(tr_a),
.clk(clk),
.rst_n(rst_n)
);
_buz_b #(
.FLA_CMAX(FLA_CMAX)
) x_buz_b(
.buz(buz_b),
.tr_sig(tr_b),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,205 | data/full_repos/permissive/93808810/buzzer.v | 93,808,810 | buzzer.v | v | 88 | 77 | [] | [] | [] | [(10, 34), (36, 63), (65, 92)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/buzzer.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/buzzer.v:6: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/buzzer.v:32: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/buzzer.v:61: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: Exiting due to 4 error(s)\n' | 311,013 | module | module _buz_a(buz, tr_sig, clk, rst_n);
parameter FLA_CMAX = `c_ms(100);
output buz;
input tr_sig;
input clk, rst_n;
reg st = 'd0;
wire tm_done;
wire tm_clr = tr_sig;
assign buz = st;
always @(posedge clk, negedge rst_n)
if (!rst_n)
st <= 'd0;
else if (tr_sig)
st <= 'd1;
else if (tm_done && st)
st <= 'd0;
timer #(
.CMAX(FLA_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module _buz_a(buz, tr_sig, clk, rst_n); |
parameter FLA_CMAX = `c_ms(100);
output buz;
input tr_sig;
input clk, rst_n;
reg st = 'd0;
wire tm_done;
wire tm_clr = tr_sig;
assign buz = st;
always @(posedge clk, negedge rst_n)
if (!rst_n)
st <= 'd0;
else if (tr_sig)
st <= 'd1;
else if (tm_done && st)
st <= 'd0;
timer #(
.CMAX(FLA_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,206 | data/full_repos/permissive/93808810/buzzer.v | 93,808,810 | buzzer.v | v | 88 | 77 | [] | [] | [] | [(10, 34), (36, 63), (65, 92)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/buzzer.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/buzzer.v:6: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/buzzer.v:32: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/buzzer.v:61: Define or directive not defined: \'`c_ms\'\n parameter FLA_CMAX = `c_ms(100);\n ^~~~~\n%Error: Exiting due to 4 error(s)\n' | 311,013 | module | module _buz_b(buz, tr_sig, clk, rst_n);
parameter FLA_CMAX = `c_ms(100);
output buz;
input tr_sig;
input clk, rst_n;
reg [4:0] st = 'd0;
wire tm_done;
wire tm_clr = tr_sig;
assign buz = st[0] && st != 7 && st != 15;
always @(posedge clk, negedge rst_n)
if (!rst_n)
st <= 'd0;
else if (tr_sig)
st <= 'd1;
else if (tm_done && st)
st <= st == 'd21 ? 'd0 : st + 'd1;
timer #(
.CMAX(FLA_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module _buz_b(buz, tr_sig, clk, rst_n); |
parameter FLA_CMAX = `c_ms(100);
output buz;
input tr_sig;
input clk, rst_n;
reg [4:0] st = 'd0;
wire tm_done;
wire tm_clr = tr_sig;
assign buz = st[0] && st != 7 && st != 15;
always @(posedge clk, negedge rst_n)
if (!rst_n)
st <= 'd0;
else if (tr_sig)
st <= 'd1;
else if (tm_done && st)
st <= st == 'd21 ? 'd0 : st + 'd1;
timer #(
.CMAX(FLA_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,207 | data/full_repos/permissive/93808810/debouncer.v | 93,808,810 | debouncer.v | v | 37 | 58 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/93808810/debouncer.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/debouncer.v:6: Define or directive not defined: \'`c_ms\'\n parameter DEB_CMAX = `c_ms(5);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n' | 311,014 | module | module debouncer(sig, pe_sig, ne_sig, a_sig, clk, rst_n);
parameter DEB_CMAX = `c_ms(5);
output reg sig = 'b0;
output pe_sig, ne_sig;
input a_sig;
input clk, rst_n;
reg r_a_sig = 'b0;
wire tm_done;
wire tm_clr = sig == r_a_sig;
assign pe_sig = tm_done && !sig;
assign ne_sig = tm_done && sig;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
sig <= 'b0;
r_a_sig <= 'b0;
end
else begin
r_a_sig <= a_sig;
if (tm_done)
sig <= !sig;
end
timer #(
.CMAX(DEB_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module debouncer(sig, pe_sig, ne_sig, a_sig, clk, rst_n); |
parameter DEB_CMAX = `c_ms(5);
output reg sig = 'b0;
output pe_sig, ne_sig;
input a_sig;
input clk, rst_n;
reg r_a_sig = 'b0;
wire tm_done;
wire tm_clr = sig == r_a_sig;
assign pe_sig = tm_done && !sig;
assign ne_sig = tm_done && sig;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
sig <= 'b0;
r_a_sig <= 'b0;
end
else begin
r_a_sig <= a_sig;
if (tm_done)
sig <= !sig;
end
timer #(
.CMAX(DEB_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,208 | data/full_repos/permissive/93808810/display.v | 93,808,810 | display.v | v | 89 | 79 | [] | [] | [] | [(10, 55), (57, 62), (64, 74), (76, 93)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/display.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/display.v:6: Define or directive not defined: \'`c_ms\'\n parameter SCA_CMAX = `c_ms(1);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n' | 311,015 | module | module display(seg_n, an_n, u_tot, u_cur, u_wat, fl_disp, clk_fl, clk, rst_n);
parameter SCA_CMAX = `c_ms(1);
output [7:0] seg_n, an_n;
input [5:0] u_tot, u_cur, u_wat;
input fl_disp;
input clk_fl, clk, rst_n;
wire clk_sca;
wire [3:0] mem[7:0];
assign mem[3] = 'b1111;
assign mem[2] = 'b1111;
wire [2:0] pos;
assign an_n = ~((rst_n && (!fl_disp || clk_fl)) << pos);
_disp_decimal x_dec_tot(
.e1(mem[7]),
.e0(mem[6]),
.val(u_tot)
);
_disp_decimal x_dec_cur(
.e1(mem[5]),
.e0(mem[4]),
.val(u_cur)
);
_disp_decimal x_dec_wat(
.e1(mem[1]),
.e0(mem[0]),
.val(u_wat)
);
divider #(
.CMAX(SCA_CMAX)
) x_divider(
.clk_div(clk_sca),
.clk(clk),
.rst_n(rst_n)
);
_disp_counter8 x_counter(
.cnt(pos),
.clk(clk_sca),
.rst_n(rst_n)
);
_disp_pattern x_pattern(
.seg_n(seg_n),
.val(mem[pos])
);
endmodule | module display(seg_n, an_n, u_tot, u_cur, u_wat, fl_disp, clk_fl, clk, rst_n); |
parameter SCA_CMAX = `c_ms(1);
output [7:0] seg_n, an_n;
input [5:0] u_tot, u_cur, u_wat;
input fl_disp;
input clk_fl, clk, rst_n;
wire clk_sca;
wire [3:0] mem[7:0];
assign mem[3] = 'b1111;
assign mem[2] = 'b1111;
wire [2:0] pos;
assign an_n = ~((rst_n && (!fl_disp || clk_fl)) << pos);
_disp_decimal x_dec_tot(
.e1(mem[7]),
.e0(mem[6]),
.val(u_tot)
);
_disp_decimal x_dec_cur(
.e1(mem[5]),
.e0(mem[4]),
.val(u_cur)
);
_disp_decimal x_dec_wat(
.e1(mem[1]),
.e0(mem[0]),
.val(u_wat)
);
divider #(
.CMAX(SCA_CMAX)
) x_divider(
.clk_div(clk_sca),
.clk(clk),
.rst_n(rst_n)
);
_disp_counter8 x_counter(
.cnt(pos),
.clk(clk_sca),
.rst_n(rst_n)
);
_disp_pattern x_pattern(
.seg_n(seg_n),
.val(mem[pos])
);
endmodule | 0 |
141,209 | data/full_repos/permissive/93808810/display.v | 93,808,810 | display.v | v | 89 | 79 | [] | [] | [] | [(10, 55), (57, 62), (64, 74), (76, 93)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/display.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/display.v:6: Define or directive not defined: \'`c_ms\'\n parameter SCA_CMAX = `c_ms(1);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n' | 311,015 | module | module _disp_decimal(e1, e0, val);
output [3:0] e1, e0;
input [5:0] val;
assign e1 = val / 10;
assign e0 = val % 10;
endmodule | module _disp_decimal(e1, e0, val); |
output [3:0] e1, e0;
input [5:0] val;
assign e1 = val / 10;
assign e0 = val % 10;
endmodule | 0 |
141,210 | data/full_repos/permissive/93808810/display.v | 93,808,810 | display.v | v | 89 | 79 | [] | [] | [] | [(10, 55), (57, 62), (64, 74), (76, 93)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/display.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/display.v:6: Define or directive not defined: \'`c_ms\'\n parameter SCA_CMAX = `c_ms(1);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n' | 311,015 | module | module _disp_counter8(cnt, clk, rst_n);
output reg [2:0] cnt = 'd0;
input clk, rst_n;
always @(posedge clk, negedge rst_n)
if (!rst_n)
cnt <= 'd0;
else
cnt <= cnt + 'd1;
endmodule | module _disp_counter8(cnt, clk, rst_n); |
output reg [2:0] cnt = 'd0;
input clk, rst_n;
always @(posedge clk, negedge rst_n)
if (!rst_n)
cnt <= 'd0;
else
cnt <= cnt + 'd1;
endmodule | 0 |
141,211 | data/full_repos/permissive/93808810/display.v | 93,808,810 | display.v | v | 89 | 79 | [] | [] | [] | [(10, 55), (57, 62), (64, 74), (76, 93)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/display.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/display.v:6: Define or directive not defined: \'`c_ms\'\n parameter SCA_CMAX = `c_ms(1);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n' | 311,015 | module | module _disp_pattern(seg_n, val);
output reg [7:0] seg_n;
input [3:0] val;
always @(*)
case (val)
'd0: seg_n <= 'b11000000;
'd1: seg_n <= 'b11111001;
'd2: seg_n <= 'b10100100;
'd3: seg_n <= 'b10110000;
'd4: seg_n <= 'b10011001;
'd5: seg_n <= 'b10010010;
'd6: seg_n <= 'b10000010;
'd7: seg_n <= 'b11111000;
'd8: seg_n <= 'b10000000;
'd9: seg_n <= 'b10010000;
default: seg_n <= 'b11111111;
endcase
endmodule | module _disp_pattern(seg_n, val); |
output reg [7:0] seg_n;
input [3:0] val;
always @(*)
case (val)
'd0: seg_n <= 'b11000000;
'd1: seg_n <= 'b11111001;
'd2: seg_n <= 'b10100100;
'd3: seg_n <= 'b10110000;
'd4: seg_n <= 'b10011001;
'd5: seg_n <= 'b10010010;
'd6: seg_n <= 'b10000010;
'd7: seg_n <= 'b11111000;
'd8: seg_n <= 'b10000000;
'd9: seg_n <= 'b10010000;
default: seg_n <= 'b11111111;
endcase
endmodule | 0 |
141,212 | data/full_repos/permissive/93808810/divider.v | 93,808,810 | divider.v | v | 26 | 41 | [] | [] | [] | null | line:11: before: "(" | null | 1: b'%Error: data/full_repos/permissive/93808810/divider.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/divider.v:6: Cannot find include file: h_cbit.v\n`include "h_cbit.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93808810/divider.v:7: Define or directive not defined: \'`c_ms\'\n parameter CMAX = `c_ms(500);\n ^~~~~\n%Error: Exiting due to 3 error(s)\n' | 311,016 | module | module divider(clk_div, clk, rst_n);
`include "h_cbit.v"
parameter CMAX = `c_ms(500);
localparam CBIT = cbit(CMAX);
output reg clk_div = 'b1;
input clk, rst_n;
reg [CBIT - 1:0] cnt = 'd0;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
clk_div <= 'b1;
cnt <= 'd0;
end
else if (cnt == CMAX) begin
clk_div <= !clk_div;
cnt <= 'd1;
end
else
cnt <= cnt + 'd1;
endmodule | module divider(clk_div, clk, rst_n); |
`include "h_cbit.v"
parameter CMAX = `c_ms(500);
localparam CBIT = cbit(CMAX);
output reg clk_div = 'b1;
input clk, rst_n;
reg [CBIT - 1:0] cnt = 'd0;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
clk_div <= 'b1;
cnt <= 'd0;
end
else if (cnt == CMAX) begin
clk_div <= !clk_div;
cnt <= 'd1;
end
else
cnt <= cnt + 'd1;
endmodule | 0 |
141,213 | data/full_repos/permissive/93808810/h_cbit.v | 93,808,810 | h_cbit.v | v | 7 | 46 | [] | [] | [] | null | line:1: before: "function" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93808810/h_cbit.v:3: Logical Operator WHILE expects 1 bit on the For Test Condition, but For Test Condition\'s VARREF \'cmax\' generates 64 bits.\n for (cbit = 0; cmax; cbit = cbit + 1)\n ^~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 311,017 | function | function integer cbit(input time cmax);
begin
for (cbit = 0; cmax; cbit = cbit + 1)
cmax = cmax >> 1;
end
endfunction | function integer cbit(input time cmax); |
begin
for (cbit = 0; cmax; cbit = cbit + 1)
cmax = cmax >> 1;
end
endfunction | 0 |
141,214 | data/full_repos/permissive/93808810/leds.v | 93,808,810 | leds.v | v | 74 | 46 | [] | [] | [] | [(10, 70), (72, 78)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/leds.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: Exiting due to 1 error(s)\n' | 311,020 | module | module leds(
led_dry, led_rin, led_was,
led_fil, led_spi, led_dra,
ld_drw, fl_drw, ld_fsd,
clk_fl, rst_n
);
output led_dry, led_rin, led_was;
output led_fil, led_spi, led_dra;
input [2:0] ld_drw, fl_drw, ld_fsd;
input clk_fl, rst_n;
_led x_led_dry(
.led(led_dry),
.ld(ld_drw[2]),
.fl(fl_drw[2]),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_rin(
.led(led_rin),
.ld(ld_drw[1]),
.fl(fl_drw[1]),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_was(
.led(led_was),
.ld(ld_drw[0]),
.fl(fl_drw[0]),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_fil(
.led(led_fil),
.ld(ld_fsd[2]),
.fl('b0),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_spi(
.led(led_spi),
.ld(ld_fsd[1]),
.fl('b0),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_dra(
.led(led_dra),
.ld(ld_fsd[0]),
.fl('b0),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
endmodule | module leds(
led_dry, led_rin, led_was,
led_fil, led_spi, led_dra,
ld_drw, fl_drw, ld_fsd,
clk_fl, rst_n
); |
output led_dry, led_rin, led_was;
output led_fil, led_spi, led_dra;
input [2:0] ld_drw, fl_drw, ld_fsd;
input clk_fl, rst_n;
_led x_led_dry(
.led(led_dry),
.ld(ld_drw[2]),
.fl(fl_drw[2]),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_rin(
.led(led_rin),
.ld(ld_drw[1]),
.fl(fl_drw[1]),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_was(
.led(led_was),
.ld(ld_drw[0]),
.fl(fl_drw[0]),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_fil(
.led(led_fil),
.ld(ld_fsd[2]),
.fl('b0),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_spi(
.led(led_spi),
.ld(ld_fsd[1]),
.fl('b0),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
_led x_led_dra(
.led(led_dra),
.ld(ld_fsd[0]),
.fl('b0),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
endmodule | 0 |
141,215 | data/full_repos/permissive/93808810/leds.v | 93,808,810 | leds.v | v | 74 | 46 | [] | [] | [] | [(10, 70), (72, 78)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/leds.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: Exiting due to 1 error(s)\n' | 311,020 | module | module _led(led, ld, fl, clk_fl, rst_n);
output led;
input ld, fl;
input clk_fl, rst_n;
assign led = rst_n && (fl ? clk_fl : ld);
endmodule | module _led(led, ld, fl, clk_fl, rst_n); |
output led;
input ld, fl;
input clk_fl, rst_n;
assign led = rst_n && (fl ? clk_fl : ld);
endmodule | 0 |
141,216 | data/full_repos/permissive/93808810/main.v | 93,808,810 | main.v | v | 114 | 78 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/93808810/main.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/main.v:13: Define or directive not defined: \'`c_ms\'\n parameter TIM_CMAX = `c_ms(1000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/main.v:14: Define or directive not defined: \'`c_s\'\n parameter END_CMAX = `c_s(10);\n ^~~~\n%Error: Exiting due to 3 error(s)\n' | 311,021 | module | module main(
done, prog_done,
ioh,
ld_drw, fl_drw, ld_fsd,
u_tot, u_cur, u_wat, fl_disp,
tr_pwr, tr_mod, tr_run, tr_wat,
clk, rst_n
);
parameter TIM_CMAX = `c_ms(1000);
parameter END_CMAX = `c_s(10);
output done, prog_done;
output ioh;
output [2:0] ld_drw, fl_drw;
output [2:0] ld_fsd;
output [5:0] u_tot, u_cur, u_wat;
output fl_disp;
input tr_pwr, tr_mod, tr_run, tr_wat;
input clk, rst_n;
wire tr_set = tr_mod || tr_wat;
reg [1:0] st = 'b00;
wire started = st[0];
wire se_done;
wire [2:0] se_ld_drw;
wire [5:0] se_u_tot, se_u_cur, se_u_wat;
wire [2:0] se_mode;
wire se_clr = started;
wire [2:0] ru_ld_drw, ru_fl_drw;
wire [2:0] ru_ld_fsd;
wire [5:0] ru_u_tot, ru_u_cur;
wire ru_done;
wire ru_pau = st == 'b11;
wire ru_clr = !started;
wire tm_done;
wire tm_clr = st != 'b10;
assign done = rst_n && ((st == 'b10 && tm_done) || (!started && tr_pwr));
assign ioh = started;
assign ld_drw = started ? ru_ld_drw : se_ld_drw;
assign fl_drw = started ? ru_fl_drw : 'b000;
assign ld_fsd = started ? ru_ld_fsd : 'b000;
assign u_tot = started ? ru_u_tot : se_u_tot;
assign u_cur = started ? ru_u_cur : se_u_cur;
assign u_wat = se_u_wat;
assign fl_disp = ru_pau;
always @(posedge clk, negedge rst_n)
if (!rst_n)
st <= 'b00;
else case (st)
'b00:
if (se_done)
st <= 'b01;
'b01:
if (ru_done)
st <= 'b10;
else if (tr_run)
st <= 'b11;
'b10:
if (tr_set)
st <= 'b00;
else if (se_done)
st <= 'b01;
'b11:
if (tr_run)
st <= 'b01;
else if (tr_set)
st <= 'b00;
endcase
setting x_setting(
.done(se_done),
.mode(se_mode),
.ld_drw(se_ld_drw),
.u_tot(se_u_tot),
.u_cur(se_u_cur),
.u_wat(se_u_wat),
.tr_mod(tr_mod),
.tr_run(tr_run),
.tr_wat(tr_wat),
.clr(se_clr),
.clk(clk),
.rst_n(rst_n)
);
run_mode #(
.TIM_CMAX(TIM_CMAX)
) x_run_mode(
.done(ru_done),
.prog_done(prog_done),
.ld_drw(ru_ld_drw),
.fl_drw(ru_fl_drw),
.ld_fsd(ru_ld_fsd),
.u_tot(ru_u_tot),
.u_cur(ru_u_cur),
.u_wat(se_u_wat),
.init(se_mode),
.pau(ru_pau),
.clr(ru_clr),
.clk(clk),
.rst_n(rst_n)
);
timer #(
.CMAX(END_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module main(
done, prog_done,
ioh,
ld_drw, fl_drw, ld_fsd,
u_tot, u_cur, u_wat, fl_disp,
tr_pwr, tr_mod, tr_run, tr_wat,
clk, rst_n
); |
parameter TIM_CMAX = `c_ms(1000);
parameter END_CMAX = `c_s(10);
output done, prog_done;
output ioh;
output [2:0] ld_drw, fl_drw;
output [2:0] ld_fsd;
output [5:0] u_tot, u_cur, u_wat;
output fl_disp;
input tr_pwr, tr_mod, tr_run, tr_wat;
input clk, rst_n;
wire tr_set = tr_mod || tr_wat;
reg [1:0] st = 'b00;
wire started = st[0];
wire se_done;
wire [2:0] se_ld_drw;
wire [5:0] se_u_tot, se_u_cur, se_u_wat;
wire [2:0] se_mode;
wire se_clr = started;
wire [2:0] ru_ld_drw, ru_fl_drw;
wire [2:0] ru_ld_fsd;
wire [5:0] ru_u_tot, ru_u_cur;
wire ru_done;
wire ru_pau = st == 'b11;
wire ru_clr = !started;
wire tm_done;
wire tm_clr = st != 'b10;
assign done = rst_n && ((st == 'b10 && tm_done) || (!started && tr_pwr));
assign ioh = started;
assign ld_drw = started ? ru_ld_drw : se_ld_drw;
assign fl_drw = started ? ru_fl_drw : 'b000;
assign ld_fsd = started ? ru_ld_fsd : 'b000;
assign u_tot = started ? ru_u_tot : se_u_tot;
assign u_cur = started ? ru_u_cur : se_u_cur;
assign u_wat = se_u_wat;
assign fl_disp = ru_pau;
always @(posedge clk, negedge rst_n)
if (!rst_n)
st <= 'b00;
else case (st)
'b00:
if (se_done)
st <= 'b01;
'b01:
if (ru_done)
st <= 'b10;
else if (tr_run)
st <= 'b11;
'b10:
if (tr_set)
st <= 'b00;
else if (se_done)
st <= 'b01;
'b11:
if (tr_run)
st <= 'b01;
else if (tr_set)
st <= 'b00;
endcase
setting x_setting(
.done(se_done),
.mode(se_mode),
.ld_drw(se_ld_drw),
.u_tot(se_u_tot),
.u_cur(se_u_cur),
.u_wat(se_u_wat),
.tr_mod(tr_mod),
.tr_run(tr_run),
.tr_wat(tr_wat),
.clr(se_clr),
.clk(clk),
.rst_n(rst_n)
);
run_mode #(
.TIM_CMAX(TIM_CMAX)
) x_run_mode(
.done(ru_done),
.prog_done(prog_done),
.ld_drw(ru_ld_drw),
.fl_drw(ru_fl_drw),
.ld_fsd(ru_ld_fsd),
.u_tot(ru_u_tot),
.u_cur(ru_u_cur),
.u_wat(se_u_wat),
.init(se_mode),
.pau(ru_pau),
.clr(ru_clr),
.clk(clk),
.rst_n(rst_n)
);
timer #(
.CMAX(END_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,217 | data/full_repos/permissive/93808810/power.v | 93,808,810 | power.v | v | 56 | 68 | [] | [] | [] | [(10, 60)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/power.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/power.v:6: Define or directive not defined: \'`c_ms\'\n parameter TIM_CMAX = `c_ms(2000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/power.v:7: Define or directive not defined: \'`c_ms\'\n parameter DEB_CMAX = `c_ms(5);\n ^~~~~\n%Error: Exiting due to 3 error(s)\n' | 311,022 | module | module power(rst_n, tr_pwr, led_pwr, a_pwr, main_done, lock, clk);
parameter TIM_CMAX = `c_ms(2000);
parameter DEB_CMAX = `c_ms(5);
output reg rst_n = 'b0;
output tr_pwr;
output led_pwr;
input a_pwr;
input main_done;
input lock, clk;
reg r_lock = 'b0;
wire tm_done;
wire tm_clr = !pwr;
reg r_rst_n = 'b0;
wire pwr, pe_pwr, ne_pwr;
assign tr_pwr = ne_pwr && !r_lock && !lock && r_rst_n == rst_n;
assign led_pwr = rst_n;
always @(posedge clk)
if (tm_done || main_done)
rst_n <= 'b0;
else if (!rst_n && tr_pwr)
rst_n <= 'b1;
else if (pe_pwr)
r_rst_n <= rst_n;
always @(posedge clk, negedge rst_n)
if (!rst_n)
r_lock <= 'b0;
else if (pe_pwr)
r_lock <= lock;
timer #(
.CMAX(TIM_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
debouncer #(
.DEB_CMAX(DEB_CMAX)
) x_deb_pwr(
.sig(pwr),
.pe_sig(pe_pwr),
.ne_sig(ne_pwr),
.a_sig(a_pwr),
.clk(clk),
.rst_n('b1)
);
endmodule | module power(rst_n, tr_pwr, led_pwr, a_pwr, main_done, lock, clk); |
parameter TIM_CMAX = `c_ms(2000);
parameter DEB_CMAX = `c_ms(5);
output reg rst_n = 'b0;
output tr_pwr;
output led_pwr;
input a_pwr;
input main_done;
input lock, clk;
reg r_lock = 'b0;
wire tm_done;
wire tm_clr = !pwr;
reg r_rst_n = 'b0;
wire pwr, pe_pwr, ne_pwr;
assign tr_pwr = ne_pwr && !r_lock && !lock && r_rst_n == rst_n;
assign led_pwr = rst_n;
always @(posedge clk)
if (tm_done || main_done)
rst_n <= 'b0;
else if (!rst_n && tr_pwr)
rst_n <= 'b1;
else if (pe_pwr)
r_rst_n <= rst_n;
always @(posedge clk, negedge rst_n)
if (!rst_n)
r_lock <= 'b0;
else if (pe_pwr)
r_lock <= lock;
timer #(
.CMAX(TIM_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
debouncer #(
.DEB_CMAX(DEB_CMAX)
) x_deb_pwr(
.sig(pwr),
.pe_sig(pe_pwr),
.ne_sig(ne_pwr),
.a_sig(a_pwr),
.clk(clk),
.rst_n('b1)
);
endmodule | 0 |
141,218 | data/full_repos/permissive/93808810/protector.v | 93,808,810 | protector.v | v | 50 | 60 | [] | [] | [] | [(10, 54)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/protector.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/protector.v:6: Define or directive not defined: \'`c_ms\'\n parameter TIM_CMAX = `c_ms(1000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/protector.v:7: Define or directive not defined: \'`c_ms\'\n parameter DEB_CMAX = `c_ms(5);\n ^~~~~\n%Error: Exiting due to 3 error(s)\n' | 311,023 | module | module protector(lock, tr_lck, led_lck, a_lck, clk, rst_n);
parameter TIM_CMAX = `c_ms(1000);
parameter DEB_CMAX = `c_ms(5);
output reg lock = 'b0;
output tr_lck;
output led_lck;
input a_lck;
input clk, rst_n;
reg r_lock = 'b0;
wire tm_done;
wire lck, pe_lck;
wire tm_clr = !lck || r_lock != lock;
assign tr_lck = tm_done;
assign led_lck = lock;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
lock <= 'b0;
r_lock <= 'b0;
end
else if (tm_done)
lock <= !lock;
else if (pe_lck)
r_lock <= lock;
timer #(
.CMAX(TIM_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
debouncer #(
.DEB_CMAX(DEB_CMAX)
) x_deb_lck(
.sig(lck),
.pe_sig(pe_lck),
.ne_sig(),
.a_sig(a_lck),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module protector(lock, tr_lck, led_lck, a_lck, clk, rst_n); |
parameter TIM_CMAX = `c_ms(1000);
parameter DEB_CMAX = `c_ms(5);
output reg lock = 'b0;
output tr_lck;
output led_lck;
input a_lck;
input clk, rst_n;
reg r_lock = 'b0;
wire tm_done;
wire lck, pe_lck;
wire tm_clr = !lck || r_lock != lock;
assign tr_lck = tm_done;
assign led_lck = lock;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
lock <= 'b0;
r_lock <= 'b0;
end
else if (tm_done)
lock <= !lock;
else if (pe_lck)
r_lock <= lock;
timer #(
.CMAX(TIM_CMAX)
) x_timer(
.done(tm_done),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
debouncer #(
.DEB_CMAX(DEB_CMAX)
) x_deb_lck(
.sig(lck),
.pe_sig(pe_lck),
.ne_sig(),
.a_sig(a_lck),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,219 | data/full_repos/permissive/93808810/run_mode.v | 93,808,810 | run_mode.v | v | 75 | 43 | [] | [] | [] | [(18, 86)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/run_mode.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/run_mode.v:4: Cannot find include file: h_time.v\n`include "h_time.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93808810/run_mode.v:12: Define or directive not defined: \'`c_ms\'\n parameter TIM_CMAX = `c_ms(1000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/run_mode.v:41: Define or directive not defined: \'`TG_WAS\'\n (srem[0] ? `TG_WAS : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_mode.v:41: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n (srem[0] ? `TG_WAS : 0) +\n ^\n%Error: data/full_repos/permissive/93808810/run_mode.v:42: Define or directive not defined: \'`TG_RIN\'\n (srem[1] ? `TG_RIN : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_mode.v:43: Define or directive not defined: \'`TG_DRY\'\n (srem[2] ? `TG_DRY : 0)\n ^~~~~~~\n%Error: Exiting due to 7 error(s)\n' | 311,024 | module | module run_mode(
done, prog_done,
ld_drw, fl_drw, ld_fsd,
u_tot, u_cur,
u_wat, init, pau, clr, clk, rst_n
);
parameter TIM_CMAX = `c_ms(1000);
output done, prog_done;
output [2:0] ld_drw, fl_drw;
output [2:0] ld_fsd;
output [5:0] u_tot, u_cur;
input [5:0] u_wat;
input [2:0] init;
input pau, clr, clk, rst_n;
reg [2:0] st = 'b000;
wire [2:0] lowb = st & -st;
wire [2:0] srem = st ^ lowb;
reg r_prog_done = 'b0;
reg [4:0] prog_init;
always @(*)
case (lowb)
'b001: prog_init <= 'b01100;
'b010: prog_init <= 'b10111;
'b100: prog_init <= 'b00011;
default: prog_init <= 'b00000;
endcase
reg r_clr = 'b0;
wire prog_clr = r_clr || r_prog_done;
assign done = !st && r_prog_done;
assign ld_drw = st;
assign fl_drw = lowb;
assign u_tot = u_cur + u_wat * (
(srem[0] ? `TG_WAS : 0) +
(srem[1] ? `TG_RIN : 0) +
(srem[2] ? `TG_DRY : 0)
);
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
st <= 'b000;
r_prog_done <= 'b0;
r_clr <= 'b0;
end
else if (!pau) begin
r_prog_done <= prog_done;
r_clr <= clr;
if (clr) begin
st <= init;
end
else if (prog_done)
st <= srem;
end
run_prog #(
.TIM_CMAX(TIM_CMAX)
) x_run_prog(
.done(prog_done),
.ld_fsd(ld_fsd),
.u_cur(u_cur),
.u_wat(u_wat),
.init(prog_init),
.pau(pau),
.clr(prog_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module run_mode(
done, prog_done,
ld_drw, fl_drw, ld_fsd,
u_tot, u_cur,
u_wat, init, pau, clr, clk, rst_n
); |
parameter TIM_CMAX = `c_ms(1000);
output done, prog_done;
output [2:0] ld_drw, fl_drw;
output [2:0] ld_fsd;
output [5:0] u_tot, u_cur;
input [5:0] u_wat;
input [2:0] init;
input pau, clr, clk, rst_n;
reg [2:0] st = 'b000;
wire [2:0] lowb = st & -st;
wire [2:0] srem = st ^ lowb;
reg r_prog_done = 'b0;
reg [4:0] prog_init;
always @(*)
case (lowb)
'b001: prog_init <= 'b01100;
'b010: prog_init <= 'b10111;
'b100: prog_init <= 'b00011;
default: prog_init <= 'b00000;
endcase
reg r_clr = 'b0;
wire prog_clr = r_clr || r_prog_done;
assign done = !st && r_prog_done;
assign ld_drw = st;
assign fl_drw = lowb;
assign u_tot = u_cur + u_wat * (
(srem[0] ? `TG_WAS : 0) +
(srem[1] ? `TG_RIN : 0) +
(srem[2] ? `TG_DRY : 0)
);
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
st <= 'b000;
r_prog_done <= 'b0;
r_clr <= 'b0;
end
else if (!pau) begin
r_prog_done <= prog_done;
r_clr <= clr;
if (clr) begin
st <= init;
end
else if (prog_done)
st <= srem;
end
run_prog #(
.TIM_CMAX(TIM_CMAX)
) x_run_prog(
.done(prog_done),
.ld_fsd(ld_fsd),
.u_cur(u_cur),
.u_wat(u_wat),
.init(prog_init),
.pau(pau),
.clr(prog_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,220 | data/full_repos/permissive/93808810/run_prog.v | 93,808,810 | run_prog.v | v | 74 | 46 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/93808810/run_prog.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/run_prog.v:4: Cannot find include file: h_time.v\n`include "h_time.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:11: Define or directive not defined: \'`c_ms\'\n parameter TIM_CMAX = `c_ms(1000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:25: Define or directive not defined: \'`TC_DRA\'\n \'b00001: tm_init_mul <= `TC_DRA;\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n \'b00001: tm_init_mul <= `TC_DRA;\n ^\n%Error: data/full_repos/permissive/93808810/run_prog.v:26: Define or directive not defined: \'`TC_SPI\'\n \'b00010: tm_init_mul <= `TC_SPI;\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n \'b00010: tm_init_mul <= `TC_SPI;\n ^\n%Error: data/full_repos/permissive/93808810/run_prog.v:27: Define or directive not defined: \'`TC_FIL\'\n \'b00100: tm_init_mul <= `TC_FIL;\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n \'b00100: tm_init_mul <= `TC_FIL;\n ^\n%Error: data/full_repos/permissive/93808810/run_prog.v:28: Define or directive not defined: \'`TC_WAS\'\n \'b01000: tm_init_mul <= `TC_WAS;\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n \'b01000: tm_init_mul <= `TC_WAS;\n ^\n%Error: data/full_repos/permissive/93808810/run_prog.v:29: Define or directive not defined: \'`TC_RIN\'\n \'b10000: tm_init_mul <= `TC_RIN;\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:29: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n \'b10000: tm_init_mul <= `TC_RIN;\n ^\n%Error: data/full_repos/permissive/93808810/run_prog.v:41: Define or directive not defined: \'`TC_DRA\'\n (srem[0] ? `TC_DRA : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:41: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n (srem[0] ? `TC_DRA : 0) +\n ^\n%Error: data/full_repos/permissive/93808810/run_prog.v:42: Define or directive not defined: \'`TC_SPI\'\n (srem[1] ? `TC_SPI : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:43: Define or directive not defined: \'`TC_FIL\'\n (srem[2] ? `TC_FIL : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:44: Define or directive not defined: \'`TC_WAS\'\n (srem[3] ? `TC_WAS : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/run_prog.v:45: Define or directive not defined: \'`TC_RIN\'\n (srem[4] ? `TC_RIN : 0)\n ^~~~~~~\n%Error: Exiting due to 19 error(s)\n' | 311,025 | module | module run_prog(
done,
ld_fsd, u_cur,
u_wat, init, pau, clr, clk, rst_n
);
parameter TIM_CMAX = `c_ms(1000);
output done;
output [2:0] ld_fsd;
output [5:0] u_cur;
input [5:0] u_wat;
input [4:0] init;
input pau, clr, clk, rst_n;
reg[4:0] st = 'b00000;
wire [4:0] lowb = st & -st;
wire [4:0] srem = st ^ lowb;
reg [5:0] tm_init_mul;
always @(*)
case (lowb)
'b00001: tm_init_mul <= `TC_DRA;
'b00010: tm_init_mul <= `TC_SPI;
'b00100: tm_init_mul <= `TC_FIL;
'b01000: tm_init_mul <= `TC_WAS;
'b10000: tm_init_mul <= `TC_RIN;
default: tm_init_mul <= 'd0;
endcase
wire tm_done;
reg r_tm_done = 'b0;
wire [5:0] tm_rema;
wire [5:0] tm_init = u_wat * tm_init_mul;
reg r_clr = 'b0;
wire tm_clr = r_clr || r_tm_done;
assign done = !st && r_tm_done;
assign ld_fsd = lowb[2:0];
assign u_cur = tm_rema + u_wat * (
(srem[0] ? `TC_DRA : 0) +
(srem[1] ? `TC_SPI : 0) +
(srem[2] ? `TC_FIL : 0) +
(srem[3] ? `TC_WAS : 0) +
(srem[4] ? `TC_RIN : 0)
);
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
st <= 'b00000;
r_tm_done <= 'b0;
r_clr <= 'b0;
end
else if (!pau) begin
r_tm_done <= tm_done;
r_clr <= clr;
if (clr)
st <= init;
else if (tm_done)
st <= srem;
end
timer_nested #(
.CBIT(6),
.INNER_CMAX(TIM_CMAX)
) x_timer(
.done(tm_done),
.rema(tm_rema),
.init(tm_init),
.pau(pau),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module run_prog(
done,
ld_fsd, u_cur,
u_wat, init, pau, clr, clk, rst_n
); |
parameter TIM_CMAX = `c_ms(1000);
output done;
output [2:0] ld_fsd;
output [5:0] u_cur;
input [5:0] u_wat;
input [4:0] init;
input pau, clr, clk, rst_n;
reg[4:0] st = 'b00000;
wire [4:0] lowb = st & -st;
wire [4:0] srem = st ^ lowb;
reg [5:0] tm_init_mul;
always @(*)
case (lowb)
'b00001: tm_init_mul <= `TC_DRA;
'b00010: tm_init_mul <= `TC_SPI;
'b00100: tm_init_mul <= `TC_FIL;
'b01000: tm_init_mul <= `TC_WAS;
'b10000: tm_init_mul <= `TC_RIN;
default: tm_init_mul <= 'd0;
endcase
wire tm_done;
reg r_tm_done = 'b0;
wire [5:0] tm_rema;
wire [5:0] tm_init = u_wat * tm_init_mul;
reg r_clr = 'b0;
wire tm_clr = r_clr || r_tm_done;
assign done = !st && r_tm_done;
assign ld_fsd = lowb[2:0];
assign u_cur = tm_rema + u_wat * (
(srem[0] ? `TC_DRA : 0) +
(srem[1] ? `TC_SPI : 0) +
(srem[2] ? `TC_FIL : 0) +
(srem[3] ? `TC_WAS : 0) +
(srem[4] ? `TC_RIN : 0)
);
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
st <= 'b00000;
r_tm_done <= 'b0;
r_clr <= 'b0;
end
else if (!pau) begin
r_tm_done <= tm_done;
r_clr <= clr;
if (clr)
st <= init;
else if (tm_done)
st <= srem;
end
timer_nested #(
.CBIT(6),
.INNER_CMAX(TIM_CMAX)
) x_timer(
.done(tm_done),
.rema(tm_rema),
.init(tm_init),
.pau(pau),
.clr(tm_clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,221 | data/full_repos/permissive/93808810/setting.v | 93,808,810 | setting.v | v | 56 | 55 | [] | [] | [] | [(12, 62)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/setting.v:3: Cannot find include file: h_time.v\n`include "h_time.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_time.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_time.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_time.v.sv\n h_time.v\n h_time.v.v\n h_time.v.sv\n obj_dir/h_time.v\n obj_dir/h_time.v.v\n obj_dir/h_time.v.sv\n%Error: data/full_repos/permissive/93808810/setting.v:26: Define or directive not defined: \'`TG_WAS\'\n (mode[0] ? `TG_WAS : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/setting.v:26: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n (mode[0] ? `TG_WAS : 0) +\n ^\n%Error: data/full_repos/permissive/93808810/setting.v:27: Define or directive not defined: \'`TG_RIN\'\n (mode[1] ? `TG_RIN : 0) +\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/setting.v:28: Define or directive not defined: \'`TG_DRY\'\n (mode[2] ? `TG_DRY : 0)\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/setting.v:31: Define or directive not defined: \'`TG_WAS\'\n mode[0] ? `TG_WAS :\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/setting.v:31: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n mode[0] ? `TG_WAS :\n ^\n%Error: data/full_repos/permissive/93808810/setting.v:32: Define or directive not defined: \'`TG_RIN\'\n mode[1] ? `TG_RIN :\n ^~~~~~~\n%Error: data/full_repos/permissive/93808810/setting.v:33: Define or directive not defined: \'`TG_DRY\'\n mode[2] ? `TG_DRY : 0\n ^~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 311,026 | module | module setting(
done, mode,
ld_drw,
u_tot, u_cur, u_wat,
tr_mod, tr_run, tr_wat,
clr, clk, rst_n
);
output done;
output reg [2:0] mode = 'b111;
output [2:0] ld_drw;
output [5:0] u_tot, u_cur;
output reg [5:0] u_wat = 'd3;
input tr_mod, tr_run, tr_wat;
input clr, clk, rst_n;
assign done = tr_run;
assign ld_drw = mode;
assign u_tot = u_wat * (
(mode[0] ? `TG_WAS : 0) +
(mode[1] ? `TG_RIN : 0) +
(mode[2] ? `TG_DRY : 0)
);
assign u_cur = u_wat * (
mode[0] ? `TG_WAS :
mode[1] ? `TG_RIN :
mode[2] ? `TG_DRY : 0
);
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
mode <= 'b111;
u_wat <= 'd3;
end
else if (clr)
mode <= 'b111;
else if (tr_mod)
case (mode)
'b111: mode <= 'b001;
'b001: mode <= 'b011;
'b011: mode <= 'b010;
'b010: mode <= 'b110;
'b110: mode <= 'b100;
'b100: mode <= 'b111;
default: mode <= 'b111;
endcase
else if (tr_wat)
u_wat <= u_wat == 'd5 ? 'd2 : u_wat + 'd1;
endmodule | module setting(
done, mode,
ld_drw,
u_tot, u_cur, u_wat,
tr_mod, tr_run, tr_wat,
clr, clk, rst_n
); |
output done;
output reg [2:0] mode = 'b111;
output [2:0] ld_drw;
output [5:0] u_tot, u_cur;
output reg [5:0] u_wat = 'd3;
input tr_mod, tr_run, tr_wat;
input clr, clk, rst_n;
assign done = tr_run;
assign ld_drw = mode;
assign u_tot = u_wat * (
(mode[0] ? `TG_WAS : 0) +
(mode[1] ? `TG_RIN : 0) +
(mode[2] ? `TG_DRY : 0)
);
assign u_cur = u_wat * (
mode[0] ? `TG_WAS :
mode[1] ? `TG_RIN :
mode[2] ? `TG_DRY : 0
);
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
mode <= 'b111;
u_wat <= 'd3;
end
else if (clr)
mode <= 'b111;
else if (tr_mod)
case (mode)
'b111: mode <= 'b001;
'b001: mode <= 'b011;
'b011: mode <= 'b010;
'b010: mode <= 'b110;
'b110: mode <= 'b100;
'b100: mode <= 'b111;
default: mode <= 'b111;
endcase
else if (tr_wat)
u_wat <= u_wat == 'd5 ? 'd2 : u_wat + 'd1;
endmodule | 0 |
141,222 | data/full_repos/permissive/93808810/timer.v | 93,808,810 | timer.v | v | 22 | 43 | [] | [] | [] | null | line:11: before: "(" | null | 1: b'%Error: data/full_repos/permissive/93808810/timer.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/timer.v:6: Cannot find include file: h_cbit.v\n`include "h_cbit.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93808810/timer.v:7: Define or directive not defined: \'`c_ms\'\n parameter CMAX = `c_ms(1000);\n ^~~~~\n%Error: Exiting due to 3 error(s)\n' | 311,027 | module | module timer(done, clr, clk, rst_n);
`include "h_cbit.v"
parameter CMAX = `c_ms(1000);
localparam CBIT = cbit(CMAX);
output done;
input clr, clk, rst_n;
reg [CBIT - 1:0] cnt = 'd0;
assign done = cnt == CMAX;
always @(posedge clk, negedge rst_n)
if (!rst_n)
cnt <= 'd0;
else if (clr)
cnt <= 'd0;
else
cnt <= done ? 'd1 : cnt + 'd1;
endmodule | module timer(done, clr, clk, rst_n); |
`include "h_cbit.v"
parameter CMAX = `c_ms(1000);
localparam CBIT = cbit(CMAX);
output done;
input clr, clk, rst_n;
reg [CBIT - 1:0] cnt = 'd0;
assign done = cnt == CMAX;
always @(posedge clk, negedge rst_n)
if (!rst_n)
cnt <= 'd0;
else if (clr)
cnt <= 'd0;
else
cnt <= done ? 'd1 : cnt + 'd1;
endmodule | 0 |
141,223 | data/full_repos/permissive/93808810/timer_nested.v | 93,808,810 | timer_nested.v | v | 39 | 61 | [] | [] | [] | [(10, 43)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/timer_nested.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/timer_nested.v:7: Define or directive not defined: \'`c_ms\'\n parameter INNER_CMAX = `c_ms(1000);\n ^~~~~\n%Error: Exiting due to 2 error(s)\n' | 311,028 | module | module timer_nested(done, rema, init, pau, clr, clk, rst_n);
parameter CBIT = 6;
parameter INNER_CMAX = `c_ms(1000);
output done;
output reg [CBIT - 1:0] rema = 'd0;
input [CBIT - 1:0] init;
input pau, clr, clk, rst_n;
wire ok = !rema;
wire tm_done;
reg r_tm_done = 'b0;
assign done = r_tm_done && ok;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
rema <= 'd0;
r_tm_done <= 'b0;
end
else if (!pau) begin
r_tm_done <= tm_done;
if (clr)
rema <= init;
else if (tm_done)
rema <= (ok ? init : rema) - 1;
end
timer #(
.CMAX(INNER_CMAX)
) x_timer(
.done(tm_done),
.clr(clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module timer_nested(done, rema, init, pau, clr, clk, rst_n); |
parameter CBIT = 6;
parameter INNER_CMAX = `c_ms(1000);
output done;
output reg [CBIT - 1:0] rema = 'd0;
input [CBIT - 1:0] init;
input pau, clr, clk, rst_n;
wire ok = !rema;
wire tm_done;
reg r_tm_done = 'b0;
assign done = r_tm_done && ok;
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
rema <= 'd0;
r_tm_done <= 'b0;
end
else if (!pau) begin
r_tm_done <= tm_done;
if (clr)
rema <= init;
else if (tm_done)
rema <= (ok ? init : rema) - 1;
end
timer #(
.CMAX(INNER_CMAX)
) x_timer(
.done(tm_done),
.clr(clr),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,224 | data/full_repos/permissive/93808810/top.v | 93,808,810 | top.v | v | 168 | 58 | [] | [] | [] | [(10, 172)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/top.v:3: Cannot find include file: h_cmax.v\n`include "h_cmax.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.v\n data/full_repos/permissive/93808810,data/full_repos/permissive/93808810/h_cmax.v.sv\n h_cmax.v\n h_cmax.v.v\n h_cmax.v.sv\n obj_dir/h_cmax.v\n obj_dir/h_cmax.v.v\n obj_dir/h_cmax.v.sv\n%Error: data/full_repos/permissive/93808810/top.v:14: Define or directive not defined: \'`c_ms\'\n parameter TIM_UNIT = `c_ms(1000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/top.v:15: Define or directive not defined: \'`c_s\'\n parameter END_WAIT = `c_s(10);\n ^~~~\n%Error: data/full_repos/permissive/93808810/top.v:16: Define or directive not defined: \'`c_ms\'\n parameter DEB_WAIT = `c_ms(5);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/top.v:17: Define or directive not defined: \'`c_ms\'\n parameter LCK_WAIT = `c_ms(1000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/top.v:18: Define or directive not defined: \'`c_ms\'\n parameter FPO_WAIT = `c_ms(2000);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/top.v:19: Define or directive not defined: \'`c_ms\'\n parameter BUZ_INTV = `c_ms(100);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/top.v:20: Define or directive not defined: \'`c_ms\'\n parameter FLA_INTV = `c_ms(500);\n ^~~~~\n%Error: data/full_repos/permissive/93808810/top.v:21: Define or directive not defined: \'`c_ms\'\n parameter DIS_INTV = `c_ms(1);\n ^~~~~\n%Error: Exiting due to 9 error(s)\n' | 311,029 | module | module top(
buz, ioh,
led_pwr, led_lck,
led_dry, led_rin, led_was,
led_fil, led_spi, led_dra,
seg_n, an_n,
a_mod, a_run, a_wat, a_pwr,
clk
);
parameter TIM_UNIT = `c_ms(1000);
parameter END_WAIT = `c_s(10);
parameter DEB_WAIT = `c_ms(5);
parameter LCK_WAIT = `c_ms(1000);
parameter FPO_WAIT = `c_ms(2000);
parameter BUZ_INTV = `c_ms(100);
parameter FLA_INTV = `c_ms(500);
parameter DIS_INTV = `c_ms(1);
output buz, ioh;
output led_pwr, led_lck;
output led_dry, led_rin, led_was;
output led_fil, led_spi, led_dra;
output [7:0] seg_n, an_n;
input a_mod, a_run, a_wat, a_pwr;
input clk;
wire a_lck = a_mod && a_wat;
wire clk_fl;
wire [2:0] ld_drw, fl_drw, ld_fsd;
wire [5:0] u_tot, u_cur, u_wat;
wire fl_disp;
wire main_done, prog_done;
wire rst_n, tr_pwr;
wire lock;
wire tr_lck, tr_mod, tr_run, tr_wat;
wire buz_tr_a = tr_lck || tr_mod || tr_run || tr_wat;
wire buz_tr_b = prog_done;
main #(
.TIM_CMAX(TIM_UNIT),
.END_CMAX(END_WAIT)
) x_main(
.done(main_done),
.prog_done(prog_done),
.ioh(ioh),
.ld_drw(ld_drw),
.fl_drw(fl_drw),
.ld_fsd(ld_fsd),
.u_tot(u_tot),
.u_cur(u_cur),
.u_wat(u_wat),
.fl_disp(fl_disp),
.tr_pwr(tr_pwr),
.tr_mod(tr_mod),
.tr_run(tr_run),
.tr_wat(tr_wat),
.clk(clk),
.rst_n(rst_n)
);
power #(
.TIM_CMAX(FPO_WAIT),
.DEB_CMAX(DEB_WAIT)
) x_power(
.rst_n(rst_n),
.tr_pwr(tr_pwr),
.led_pwr(led_pwr),
.a_pwr(a_pwr),
.main_done(main_done),
.lock(lock),
.clk(clk)
);
protector #(
.TIM_CMAX(LCK_WAIT),
.DEB_CMAX(DEB_WAIT)
) x_protector(
.lock(lock),
.tr_lck(tr_lck),
.led_lck(led_lck),
.a_lck(a_lck),
.clk(clk),
.rst_n(rst_n)
);
button #(
.DEB_CMAX(DEB_WAIT)
) x_deb_mod(
.tr_btn(tr_mod),
.a_btn(a_mod),
.lock(lock),
.clk(clk),
.rst_n(rst_n)
);
button #(
.DEB_CMAX(DEB_WAIT)
) x_deb_run(
.tr_btn(tr_run),
.a_btn(a_run),
.lock(lock),
.clk(clk),
.rst_n(rst_n)
);
button #(
.DEB_CMAX(DEB_WAIT)
) x_deb_wat(
.tr_btn(tr_wat),
.a_btn(a_wat),
.lock(lock),
.clk(clk),
.rst_n(rst_n)
);
buzzer #(
.FLA_CMAX(BUZ_INTV)
) x_buzzer(
.buz(buz),
.tr_a(buz_tr_a),
.tr_b(buz_tr_b),
.clk(clk),
.rst_n(rst_n)
);
divider #(
.CMAX(FLA_INTV)
) x_divider_fl(
.clk_div(clk_fl),
.clk(clk),
.rst_n(rst_n)
);
leds x_leds(
.led_dry(led_dry),
.led_rin(led_rin),
.led_was(led_was),
.led_fil(led_fil),
.led_spi(led_spi),
.led_dra(led_dra),
.ld_drw(ld_drw),
.fl_drw(fl_drw),
.ld_fsd(ld_fsd),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
display #(
.SCA_CMAX(DIS_INTV)
) x_display(
.seg_n(seg_n),
.an_n(an_n),
.u_tot(u_tot),
.u_cur(u_cur),
.u_wat(u_wat),
.fl_disp(fl_disp),
.clk_fl(clk_fl),
.clk(clk),
.rst_n(rst_n)
);
endmodule | module top(
buz, ioh,
led_pwr, led_lck,
led_dry, led_rin, led_was,
led_fil, led_spi, led_dra,
seg_n, an_n,
a_mod, a_run, a_wat, a_pwr,
clk
); |
parameter TIM_UNIT = `c_ms(1000);
parameter END_WAIT = `c_s(10);
parameter DEB_WAIT = `c_ms(5);
parameter LCK_WAIT = `c_ms(1000);
parameter FPO_WAIT = `c_ms(2000);
parameter BUZ_INTV = `c_ms(100);
parameter FLA_INTV = `c_ms(500);
parameter DIS_INTV = `c_ms(1);
output buz, ioh;
output led_pwr, led_lck;
output led_dry, led_rin, led_was;
output led_fil, led_spi, led_dra;
output [7:0] seg_n, an_n;
input a_mod, a_run, a_wat, a_pwr;
input clk;
wire a_lck = a_mod && a_wat;
wire clk_fl;
wire [2:0] ld_drw, fl_drw, ld_fsd;
wire [5:0] u_tot, u_cur, u_wat;
wire fl_disp;
wire main_done, prog_done;
wire rst_n, tr_pwr;
wire lock;
wire tr_lck, tr_mod, tr_run, tr_wat;
wire buz_tr_a = tr_lck || tr_mod || tr_run || tr_wat;
wire buz_tr_b = prog_done;
main #(
.TIM_CMAX(TIM_UNIT),
.END_CMAX(END_WAIT)
) x_main(
.done(main_done),
.prog_done(prog_done),
.ioh(ioh),
.ld_drw(ld_drw),
.fl_drw(fl_drw),
.ld_fsd(ld_fsd),
.u_tot(u_tot),
.u_cur(u_cur),
.u_wat(u_wat),
.fl_disp(fl_disp),
.tr_pwr(tr_pwr),
.tr_mod(tr_mod),
.tr_run(tr_run),
.tr_wat(tr_wat),
.clk(clk),
.rst_n(rst_n)
);
power #(
.TIM_CMAX(FPO_WAIT),
.DEB_CMAX(DEB_WAIT)
) x_power(
.rst_n(rst_n),
.tr_pwr(tr_pwr),
.led_pwr(led_pwr),
.a_pwr(a_pwr),
.main_done(main_done),
.lock(lock),
.clk(clk)
);
protector #(
.TIM_CMAX(LCK_WAIT),
.DEB_CMAX(DEB_WAIT)
) x_protector(
.lock(lock),
.tr_lck(tr_lck),
.led_lck(led_lck),
.a_lck(a_lck),
.clk(clk),
.rst_n(rst_n)
);
button #(
.DEB_CMAX(DEB_WAIT)
) x_deb_mod(
.tr_btn(tr_mod),
.a_btn(a_mod),
.lock(lock),
.clk(clk),
.rst_n(rst_n)
);
button #(
.DEB_CMAX(DEB_WAIT)
) x_deb_run(
.tr_btn(tr_run),
.a_btn(a_run),
.lock(lock),
.clk(clk),
.rst_n(rst_n)
);
button #(
.DEB_CMAX(DEB_WAIT)
) x_deb_wat(
.tr_btn(tr_wat),
.a_btn(a_wat),
.lock(lock),
.clk(clk),
.rst_n(rst_n)
);
buzzer #(
.FLA_CMAX(BUZ_INTV)
) x_buzzer(
.buz(buz),
.tr_a(buz_tr_a),
.tr_b(buz_tr_b),
.clk(clk),
.rst_n(rst_n)
);
divider #(
.CMAX(FLA_INTV)
) x_divider_fl(
.clk_div(clk_fl),
.clk(clk),
.rst_n(rst_n)
);
leds x_leds(
.led_dry(led_dry),
.led_rin(led_rin),
.led_was(led_was),
.led_fil(led_fil),
.led_spi(led_spi),
.led_dra(led_dra),
.ld_drw(ld_drw),
.fl_drw(fl_drw),
.ld_fsd(ld_fsd),
.clk_fl(clk_fl),
.rst_n(rst_n)
);
display #(
.SCA_CMAX(DIS_INTV)
) x_display(
.seg_n(seg_n),
.an_n(an_n),
.u_tot(u_tot),
.u_cur(u_cur),
.u_wat(u_wat),
.fl_disp(fl_disp),
.clk_fl(clk_fl),
.clk(clk),
.rst_n(rst_n)
);
endmodule | 0 |
141,225 | data/full_repos/permissive/93808810/test/tb_buzzer.v | 93,808,810 | tb_buzzer.v | v | 43 | 55 | [] | [] | [] | null | line:23: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:4: Cannot find include file: tb_h_common.v\n`include "tb_h_common.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.sv\n tb_h_common.v\n tb_h_common.v.v\n tb_h_common.v.sv\n obj_dir/tb_h_common.v\n obj_dir/tb_h_common.v.v\n obj_dir/tb_h_common.v.sv\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:9: Define or directive not defined: \'`us\'\n begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:9: syntax error, unexpected IDENTIFIER\n begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:9: Define or directive not defined: \'`us\'\n begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:9: syntax error, unexpected IDENTIFIER\n begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:10: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:10: syntax error, unexpected begin\n `us(10) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:10: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:10: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:10: syntax error, unexpected IDENTIFIER\n `us(10) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:11: Define or directive not defined: \'`us\'\n `us(4.7) begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:11: syntax error, unexpected \'(\'\n `us(4.7) begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:11: Define or directive not defined: \'`us\'\n `us(4.7) begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:11: Define or directive not defined: \'`us\'\n `us(4.7) begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:12: Define or directive not defined: \'`us\'\n `us(120) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:12: Define or directive not defined: \'`us\'\n `us(120) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:12: Define or directive not defined: \'`us\'\n `us(120) begin `us(2) a_b = 1; `us(1) a_b = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:13: Define or directive not defined: \'`us\'\n `us(12) begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:13: Define or directive not defined: \'`us\'\n `us(12) begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:13: Define or directive not defined: \'`us\'\n `us(12) begin `us(2) a_a = 1; `us(1) a_a = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:17: Define or directive not defined: \'`c_us\'\n .FLA_CMAX(`c_us(5))\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:25: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_buzzer.v:34: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: Exiting due to 23 error(s)\n' | 311,030 | module | module tb_buzzer();
`include "tb_h_common.v"
`define press(x) begin `us(2) x = 1; `us(1) x = 0; end
reg a_a = 0;
reg a_b = 0;
initial begin
`press(a_a);
`us(10) `press(a_b);
`us(4.7) `press(a_a);
`us(120) `press(a_b);
`us(12) `press(a_a);
end
wire tr_a, tr_b;
buzzer #(
.FLA_CMAX(`c_us(5))
) x_dut(
.tr_a(tr_a),
.tr_b(tr_b),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_a(
.tr_btn(tr_a),
.a_btn(a_a),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_b(
.tr_btn(tr_b),
.a_btn(a_b),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
endmodule | module tb_buzzer(); |
`include "tb_h_common.v"
`define press(x) begin `us(2) x = 1; `us(1) x = 0; end
reg a_a = 0;
reg a_b = 0;
initial begin
`press(a_a);
`us(10) `press(a_b);
`us(4.7) `press(a_a);
`us(120) `press(a_b);
`us(12) `press(a_a);
end
wire tr_a, tr_b;
buzzer #(
.FLA_CMAX(`c_us(5))
) x_dut(
.tr_a(tr_a),
.tr_b(tr_b),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_a(
.tr_btn(tr_a),
.a_btn(a_a),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_b(
.tr_btn(tr_b),
.a_btn(a_b),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
endmodule | 0 |
141,226 | data/full_repos/permissive/93808810/test/tb_debouncer.v | 93,808,810 | tb_debouncer.v | v | 22 | 29 | [] | [] | [] | [(3, 34)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:4: Cannot find include file: tb_h_common.v\n`include "tb_h_common.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.sv\n tb_h_common.v\n tb_h_common.v.v\n tb_h_common.v.sv\n obj_dir/tb_h_common.v\n obj_dir/tb_h_common.v.v\n obj_dir/tb_h_common.v.sv\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:7: Define or directive not defined: \'`cp\'\n `cp(1.3) a_sig = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:7: syntax error, unexpected IDENTIFIER\n `cp(1.3) a_sig = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:8: Define or directive not defined: \'`cp\'\n `cp(10.1) a_sig = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:8: syntax error, unexpected IDENTIFIER\n `cp(10.1) a_sig = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:9: Define or directive not defined: \'`cp\'\n `cp(9.9) a_sig = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:9: syntax error, unexpected IDENTIFIER\n `cp(9.9) a_sig = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:10: Define or directive not defined: \'`cp\'\n `cp(2.8) a_sig = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:10: syntax error, unexpected IDENTIFIER\n `cp(2.8) a_sig = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:11: Define or directive not defined: \'`cp\'\n `cp(10.1) a_sig = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:11: syntax error, unexpected IDENTIFIER\n `cp(10.1) a_sig = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:12: Define or directive not defined: \'`cp\'\n `cp(9.9) a_sig = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:12: syntax error, unexpected IDENTIFIER\n `cp(9.9) a_sig = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_debouncer.v:15: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: Exiting due to 14 error(s)\n' | 311,031 | module | module tb_debouncer();
`include "tb_h_common.v"
reg a_sig = 'b0;
initial begin
`cp(1.3) a_sig = 1;
`cp(10.1) a_sig = 0;
`cp(9.9) a_sig = 1;
`cp(2.8) a_sig = 0;
`cp(10.1) a_sig = 1;
`cp(9.9) a_sig = 0;
end
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_dut(
.a_sig(a_sig),
.clk(clk),
.rst_n('b1)
);
endmodule | module tb_debouncer(); |
`include "tb_h_common.v"
reg a_sig = 'b0;
initial begin
`cp(1.3) a_sig = 1;
`cp(10.1) a_sig = 0;
`cp(9.9) a_sig = 1;
`cp(2.8) a_sig = 0;
`cp(10.1) a_sig = 1;
`cp(9.9) a_sig = 0;
end
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_dut(
.a_sig(a_sig),
.clk(clk),
.rst_n('b1)
);
endmodule | 0 |
141,227 | data/full_repos/permissive/93808810/test/tb_running.v | 93,808,810 | tb_running.v | v | 45 | 31 | [] | [] | [] | [(3, 57)] | null | null | 1: b'%Error: data/full_repos/permissive/93808810/test/tb_running.v:4: Cannot find include file: tb_h_common.v\n`include "tb_h_common.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.sv\n tb_h_common.v\n tb_h_common.v.v\n tb_h_common.v.sv\n obj_dir/tb_h_common.v\n obj_dir/tb_h_common.v.v\n obj_dir/tb_h_common.v.sv\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:10: Define or directive not defined: \'`us\'\n `us(1) a_clr = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:10: syntax error, unexpected IDENTIFIER\n `us(1) a_clr = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:11: Define or directive not defined: \'`us\'\n `us(800) a_clr = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:11: syntax error, unexpected IDENTIFIER\n `us(800) a_clr = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:12: Define or directive not defined: \'`us\'\n `us(1) init = \'b011;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:12: syntax error, unexpected IDENTIFIER\n `us(1) init = \'b011;\n ^~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:13: Define or directive not defined: \'`us\'\n `us(1) a_clr = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:13: syntax error, unexpected IDENTIFIER\n `us(1) a_clr = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:14: Define or directive not defined: \'`us\'\n `us(82) a_pau = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:14: syntax error, unexpected IDENTIFIER\n `us(82) a_pau = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:15: Define or directive not defined: \'`us\'\n `us(800) a_pau = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:15: syntax error, unexpected IDENTIFIER\n `us(800) a_pau = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:19: Define or directive not defined: \'`c_us\'\n .TIM_CMAX(`c_us(10))\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:29: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_running.v:37: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: Exiting due to 16 error(s)\n' | 311,033 | module | module tb_running();
`include "tb_h_common.v"
reg a_pau = 0;
reg a_clr = 1;
reg [2:0] init = 'b111;
reg [5:0] u_wat = 3;
initial begin
`us(1) a_clr = 0;
`us(800) a_clr = 1;
`us(1) init = 'b011;
`us(1) a_clr = 0;
`us(82) a_pau = 1;
`us(800) a_pau = 0;
end
wire pau, clr;
run_mode #(
.TIM_CMAX(`c_us(10))
) x_dut(
.u_wat(u_wat),
.init(init),
.pau(pau),
.clr(clr),
.clk(clk),
.rst_n('b1)
);
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_deb_pau(
.sig(pau),
.a_sig(a_pau),
.clk(clk),
.rst_n('b1)
);
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_deb_clr(
.sig(clr),
.a_sig(a_clr),
.clk(clk),
.rst_n('b1)
);
endmodule | module tb_running(); |
`include "tb_h_common.v"
reg a_pau = 0;
reg a_clr = 1;
reg [2:0] init = 'b111;
reg [5:0] u_wat = 3;
initial begin
`us(1) a_clr = 0;
`us(800) a_clr = 1;
`us(1) init = 'b011;
`us(1) a_clr = 0;
`us(82) a_pau = 1;
`us(800) a_pau = 0;
end
wire pau, clr;
run_mode #(
.TIM_CMAX(`c_us(10))
) x_dut(
.u_wat(u_wat),
.init(init),
.pau(pau),
.clr(clr),
.clk(clk),
.rst_n('b1)
);
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_deb_pau(
.sig(pau),
.a_sig(a_pau),
.clk(clk),
.rst_n('b1)
);
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_deb_clr(
.sig(clr),
.a_sig(a_clr),
.clk(clk),
.rst_n('b1)
);
endmodule | 0 |
141,228 | data/full_repos/permissive/93808810/test/tb_setting.v | 93,808,810 | tb_setting.v | v | 64 | 55 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/93808810/test/tb_setting.v:4: Cannot find include file: tb_h_common.v\n`include "tb_h_common.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.sv\n tb_h_common.v\n tb_h_common.v.v\n tb_h_common.v.sv\n obj_dir/tb_h_common.v\n obj_dir/tb_h_common.v.v\n obj_dir/tb_h_common.v.sv\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:11: Define or directive not defined: \'`us\'\n begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:11: syntax error, unexpected IDENTIFIER\n begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:11: Define or directive not defined: \'`us\'\n begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:11: syntax error, unexpected IDENTIFIER\n begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:12: Define or directive not defined: \'`us\'\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:12: syntax error, unexpected IDENTIFIER\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:12: Define or directive not defined: \'`us\'\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:12: syntax error, unexpected IDENTIFIER\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:13: Define or directive not defined: \'`us\'\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:13: syntax error, unexpected IDENTIFIER\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:13: Define or directive not defined: \'`us\'\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:13: syntax error, unexpected IDENTIFIER\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:14: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:14: syntax error, unexpected begin\n `us(10) begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:14: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:14: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:14: syntax error, unexpected IDENTIFIER\n `us(10) begin `us(2) a_clr = 1; `us(1) a_clr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:15: syntax error, unexpected begin\n begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:15: Define or directive not defined: \'`us\'\n begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:15: Define or directive not defined: \'`us\'\n begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:16: Define or directive not defined: \'`us\'\n begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:16: Define or directive not defined: \'`us\'\n begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:17: Define or directive not defined: \'`us\'\n `us(10) a_clr = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:29: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:38: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:47: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_setting.v:56: Define or directive not defined: \'`c_cp\'\n .DEB_CMAX(`c_cp(10))\n ^~~~~\n%Error: Exiting due to 28 error(s)\n' | 311,034 | module | module tb_setting();
`include "tb_h_common.v"
`define press(x) begin `us(2) x = 1; `us(1) x = 0; end
reg a_mod = 0;
reg a_run = 0;
reg a_wat = 0;
reg a_clr = 0;
initial begin
`press(a_clr);
repeat (6) `press(a_mod);
repeat (4) `press(a_wat);
`us(10) `press(a_clr);
`press(a_wat);
`press(a_mod);
`us(10) a_clr = 1;
end
wire tr_mod, tr_run, tr_wat, clr;
setting x_dut(
.tr_mod(tr_mod),
.tr_run(tr_run),
.tr_wat(tr_wat),
.clr(clr),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_mod(
.tr_btn(tr_mod),
.a_btn(a_mod),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_run(
.tr_btn(tr_run),
.a_btn(a_run),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_wat(
.tr_btn(tr_wat),
.a_btn(a_wat),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_deb_clr(
.sig(clr),
.a_sig(a_clr),
.clk(clk),
.rst_n('b1)
);
endmodule | module tb_setting(); |
`include "tb_h_common.v"
`define press(x) begin `us(2) x = 1; `us(1) x = 0; end
reg a_mod = 0;
reg a_run = 0;
reg a_wat = 0;
reg a_clr = 0;
initial begin
`press(a_clr);
repeat (6) `press(a_mod);
repeat (4) `press(a_wat);
`us(10) `press(a_clr);
`press(a_wat);
`press(a_mod);
`us(10) a_clr = 1;
end
wire tr_mod, tr_run, tr_wat, clr;
setting x_dut(
.tr_mod(tr_mod),
.tr_run(tr_run),
.tr_wat(tr_wat),
.clr(clr),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_mod(
.tr_btn(tr_mod),
.a_btn(a_mod),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_run(
.tr_btn(tr_run),
.a_btn(a_run),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
button #(
.DEB_CMAX(`c_cp(10))
) x_btn_wat(
.tr_btn(tr_wat),
.a_btn(a_wat),
.lock('b0),
.clk(clk),
.rst_n('b1)
);
debouncer #(
.DEB_CMAX(`c_cp(10))
) x_deb_clr(
.sig(clr),
.a_sig(a_clr),
.clk(clk),
.rst_n('b1)
);
endmodule | 0 |
141,229 | data/full_repos/permissive/93808810/test/tb_top.v | 93,808,810 | tb_top.v | v | 62 | 55 | [] | [] | [] | null | line:26: before: "(" | null | 1: b'%Error: data/full_repos/permissive/93808810/test/tb_top.v:4: Cannot find include file: tb_h_common.v\n`include "tb_h_common.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.v\n data/full_repos/permissive/93808810/test,data/full_repos/permissive/93808810/tb_h_common.v.sv\n tb_h_common.v\n tb_h_common.v.v\n tb_h_common.v.sv\n obj_dir/tb_h_common.v\n obj_dir/tb_h_common.v.v\n obj_dir/tb_h_common.v.sv\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:12: Define or directive not defined: \'`us\'\n begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:12: syntax error, unexpected IDENTIFIER\n begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:12: Define or directive not defined: \'`us\'\n begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:12: syntax error, unexpected IDENTIFIER\n begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:13: Define or directive not defined: \'`us\'\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:13: syntax error, unexpected IDENTIFIER\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:13: Define or directive not defined: \'`us\'\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:13: syntax error, unexpected IDENTIFIER\n repeat (6) begin `us(2) a_mod = 1; `us(1) a_mod = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:14: Define or directive not defined: \'`us\'\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:14: syntax error, unexpected IDENTIFIER\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:14: Define or directive not defined: \'`us\'\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:14: syntax error, unexpected IDENTIFIER\n repeat (4) begin `us(2) a_wat = 1; `us(1) a_wat = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:15: Define or directive not defined: \'`us\'\n begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:15: syntax error, unexpected IDENTIFIER\n begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:15: Define or directive not defined: \'`us\'\n begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:15: syntax error, unexpected IDENTIFIER\n begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:16: Define or directive not defined: \'`us\'\n `us(20) a_mod = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:16: syntax error, unexpected IDENTIFIER\n `us(20) a_mod = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:17: Define or directive not defined: \'`us\'\n `us(4) a_wat = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:17: syntax error, unexpected IDENTIFIER\n `us(4) a_wat = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:18: Define or directive not defined: \'`us\'\n `us(20) a_wat = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:18: syntax error, unexpected IDENTIFIER\n `us(20) a_wat = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:19: Define or directive not defined: \'`us\'\n `us(6) a_mod = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:19: syntax error, unexpected IDENTIFIER\n `us(6) a_mod = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:20: Define or directive not defined: \'`us\'\n `us(20) a_pwr = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:20: syntax error, unexpected IDENTIFIER\n `us(20) a_pwr = 1;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:21: Define or directive not defined: \'`us\'\n `us(30) a_pwr = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:21: syntax error, unexpected IDENTIFIER\n `us(30) a_pwr = 0;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:22: Define or directive not defined: \'`us\'\n `us(50) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:22: syntax error, unexpected begin\n `us(50) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:22: Define or directive not defined: \'`us\'\n `us(50) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:22: Define or directive not defined: \'`us\'\n `us(50) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:22: syntax error, unexpected IDENTIFIER\n `us(50) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:23: syntax error, unexpected begin\n begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:23: Define or directive not defined: \'`us\'\n begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:23: Define or directive not defined: \'`us\'\n begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:24: Define or directive not defined: \'`us\'\n `us(40) begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:24: Define or directive not defined: \'`us\'\n `us(40) begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:24: Define or directive not defined: \'`us\'\n `us(40) begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:25: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:25: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:25: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_pwr = 1; `us(1) a_pwr = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:26: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:26: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:26: Define or directive not defined: \'`us\'\n `us(10) begin `us(2) a_run = 1; `us(1) a_run = 0; end;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:27: Define or directive not defined: \'`us\'\n `us(20) a_mod = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:28: Define or directive not defined: \'`us\'\n `us(4) a_wat = 1;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:29: Define or directive not defined: \'`us\'\n `us(12) a_mod = 0;\n ^~~\n%Error: data/full_repos/permissive/93808810/test/tb_top.v:30: Define or directive not defined: \'`us\'\n `us(2) a_wat = 0;\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 311,035 | module | module tb_top();
`include "tb_h_common.v"
`define press(x) begin `us(2) x = 1; `us(1) x = 0; end
wire pwr;
reg a_mod = 0;
reg a_run = 0;
reg a_wat = 0;
reg a_pwr = 0;
initial begin
`press(a_pwr);
repeat (6) `press(a_mod);
repeat (4) `press(a_wat);
`press(a_run);
`us(20) a_mod = 1;
`us(4) a_wat = 1;
`us(20) a_wat = 0;
`us(6) a_mod = 0;
`us(20) a_pwr = 1;
`us(30) a_pwr = 0;
`us(50) `press(a_pwr);
`press(a_run);
`us(40) `press(a_run);
`us(10) `press(a_pwr);
`us(10) `press(a_run);
`us(20) a_mod = 1;
`us(4) a_wat = 1;
`us(12) a_mod = 0;
`us(2) a_wat = 0;
`press(a_pwr);
`press(a_mod);
`press(a_run);
`press(a_wat);
`us(20) a_mod = 1;
`us(4) a_wat = 1;
`us(12) a_mod = 0;
`us(4) a_wat = 0;
`press(a_run);
`press(a_pwr);
repeat (5) `press(a_mod);
`press(a_run);
end
top #(
.TIM_UNIT(`c_us(10)),
.END_WAIT(`c_us(100)),
.DEB_WAIT(`c_cp(5)),
.LCK_WAIT(`c_us(10)),
.FPO_WAIT(`c_us(20)),
.BUZ_INTV(`c_us(1)),
.FLA_INTV(`c_us(5)),
.DIS_INTV(`c_cp(1))
) x_dut(
.led_pwr(pwr),
.a_mod(a_mod),
.a_run(a_run),
.a_wat(a_wat),
.a_pwr(a_pwr),
.clk(clk)
);
endmodule | module tb_top(); |
`include "tb_h_common.v"
`define press(x) begin `us(2) x = 1; `us(1) x = 0; end
wire pwr;
reg a_mod = 0;
reg a_run = 0;
reg a_wat = 0;
reg a_pwr = 0;
initial begin
`press(a_pwr);
repeat (6) `press(a_mod);
repeat (4) `press(a_wat);
`press(a_run);
`us(20) a_mod = 1;
`us(4) a_wat = 1;
`us(20) a_wat = 0;
`us(6) a_mod = 0;
`us(20) a_pwr = 1;
`us(30) a_pwr = 0;
`us(50) `press(a_pwr);
`press(a_run);
`us(40) `press(a_run);
`us(10) `press(a_pwr);
`us(10) `press(a_run);
`us(20) a_mod = 1;
`us(4) a_wat = 1;
`us(12) a_mod = 0;
`us(2) a_wat = 0;
`press(a_pwr);
`press(a_mod);
`press(a_run);
`press(a_wat);
`us(20) a_mod = 1;
`us(4) a_wat = 1;
`us(12) a_mod = 0;
`us(4) a_wat = 0;
`press(a_run);
`press(a_pwr);
repeat (5) `press(a_mod);
`press(a_run);
end
top #(
.TIM_UNIT(`c_us(10)),
.END_WAIT(`c_us(100)),
.DEB_WAIT(`c_cp(5)),
.LCK_WAIT(`c_us(10)),
.FPO_WAIT(`c_us(20)),
.BUZ_INTV(`c_us(1)),
.FLA_INTV(`c_us(5)),
.DIS_INTV(`c_cp(1))
) x_dut(
.led_pwr(pwr),
.a_mod(a_mod),
.a_run(a_run),
.a_wat(a_wat),
.a_pwr(a_pwr),
.clk(clk)
);
endmodule | 0 |
141,231 | data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v | 9,411,126 | sha-256-functions.v | v | 83 | 72 | [] | [] | [] | [(23, 30), (33, 40), (43, 50), (53, 60), (63, 71), (74, 82)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v:33: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'e0\'\nmodule e0 (x, y);\n ^~\n : ... Top module \'e1\'\nmodule e1 (x, y);\n ^~\n : ... Top module \'ch\'\nmodule ch (x, y, z, o);\n ^~\n : ... Top module \'maj\'\nmodule maj (x, y, z, o);\n ^~~\n : ... Top module \'s0\'\nmodule s0 (x, y);\n ^~\n : ... Top module \'s1\'\nmodule s1 (x, y);\n ^~\n%Error: Exiting due to 1 warning(s)\n' | 311,038 | module | module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule | module e0 (x, y); |
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule | 22 |
141,232 | data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v | 9,411,126 | sha-256-functions.v | v | 83 | 72 | [] | [] | [] | [(23, 30), (33, 40), (43, 50), (53, 60), (63, 71), (74, 82)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v:33: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'e0\'\nmodule e0 (x, y);\n ^~\n : ... Top module \'e1\'\nmodule e1 (x, y);\n ^~\n : ... Top module \'ch\'\nmodule ch (x, y, z, o);\n ^~\n : ... Top module \'maj\'\nmodule maj (x, y, z, o);\n ^~~\n : ... Top module \'s0\'\nmodule s0 (x, y);\n ^~\n : ... Top module \'s1\'\nmodule s1 (x, y);\n ^~\n%Error: Exiting due to 1 warning(s)\n' | 311,038 | module | module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule | module e1 (x, y); |
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule | 22 |
141,233 | data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v | 9,411,126 | sha-256-functions.v | v | 83 | 72 | [] | [] | [] | [(23, 30), (33, 40), (43, 50), (53, 60), (63, 71), (74, 82)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v:33: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'e0\'\nmodule e0 (x, y);\n ^~\n : ... Top module \'e1\'\nmodule e1 (x, y);\n ^~\n : ... Top module \'ch\'\nmodule ch (x, y, z, o);\n ^~\n : ... Top module \'maj\'\nmodule maj (x, y, z, o);\n ^~~\n : ... Top module \'s0\'\nmodule s0 (x, y);\n ^~\n : ... Top module \'s1\'\nmodule s1 (x, y);\n ^~\n%Error: Exiting due to 1 warning(s)\n' | 311,038 | module | module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule | module ch (x, y, z, o); |
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule | 22 |
141,234 | data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v | 9,411,126 | sha-256-functions.v | v | 83 | 72 | [] | [] | [] | [(23, 30), (33, 40), (43, 50), (53, 60), (63, 71), (74, 82)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v:33: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'e0\'\nmodule e0 (x, y);\n ^~\n : ... Top module \'e1\'\nmodule e1 (x, y);\n ^~\n : ... Top module \'ch\'\nmodule ch (x, y, z, o);\n ^~\n : ... Top module \'maj\'\nmodule maj (x, y, z, o);\n ^~~\n : ... Top module \'s0\'\nmodule s0 (x, y);\n ^~\n : ... Top module \'s1\'\nmodule s1 (x, y);\n ^~\n%Error: Exiting due to 1 warning(s)\n' | 311,038 | module | module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule | module maj (x, y, z, o); |
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule | 22 |
141,235 | data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v | 9,411,126 | sha-256-functions.v | v | 83 | 72 | [] | [] | [] | [(23, 30), (33, 40), (43, 50), (53, 60), (63, 71), (74, 82)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v:33: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'e0\'\nmodule e0 (x, y);\n ^~\n : ... Top module \'e1\'\nmodule e1 (x, y);\n ^~\n : ... Top module \'ch\'\nmodule ch (x, y, z, o);\n ^~\n : ... Top module \'maj\'\nmodule maj (x, y, z, o);\n ^~~\n : ... Top module \'s0\'\nmodule s0 (x, y);\n ^~\n : ... Top module \'s1\'\nmodule s1 (x, y);\n ^~\n%Error: Exiting due to 1 warning(s)\n' | 311,038 | module | module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule | module s0 (x, y); |
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule | 22 |
141,236 | data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v | 9,411,126 | sha-256-functions.v | v | 83 | 72 | [] | [] | [] | [(23, 30), (33, 40), (43, 50), (53, 60), (63, 71), (74, 82)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/9411126/cores/sha256/sha-256-functions.v:33: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'e0\'\nmodule e0 (x, y);\n ^~\n : ... Top module \'e1\'\nmodule e1 (x, y);\n ^~\n : ... Top module \'ch\'\nmodule ch (x, y, z, o);\n ^~\n : ... Top module \'maj\'\nmodule maj (x, y, z, o);\n ^~~\n : ... Top module \'s0\'\nmodule s0 (x, y);\n ^~\n : ... Top module \'s1\'\nmodule s1 (x, y);\n ^~\n%Error: Exiting due to 1 warning(s)\n' | 311,038 | module | module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule | module s1 (x, y); |
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule | 22 |
141,237 | data/full_repos/permissive/9411126/cores/sha256/sha256.v | 9,411,126 | sha256.v | v | 191 | 83 | [] | [] | [] | null | line:30: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9411126/cores/sha256/sha256.v:147: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2048 bits.\n : ... In instance sha256.rom_blk\n assign tx_k = Ks >> {rx_address, 5\'d0};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:53: Cannot find file containing module: \'s0\'\n s0 s0_blk (w[(((1)+1)*(32)-1):((1)*(32))], s0_w);\n ^~\n ... Looked in:\n data/full_repos/permissive/9411126/cores/sha256,data/full_repos/permissive/9411126/s0\n data/full_repos/permissive/9411126/cores/sha256,data/full_repos/permissive/9411126/s0.v\n data/full_repos/permissive/9411126/cores/sha256,data/full_repos/permissive/9411126/s0.sv\n s0\n s0.v\n s0.sv\n obj_dir/s0\n obj_dir/s0.v\n obj_dir/s0.sv\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:54: Cannot find file containing module: \'s1\'\n s1 s1_blk (w[(((14)+1)*(32)-1):((14)*(32))], s1_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:55: Cannot find file containing module: \'e0\'\n e0 e0_blk (state[(((0)+1)*(32)-1):((0)*(32))], e0_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:56: Cannot find file containing module: \'e1\'\n e1 e1_blk (state[(((4)+1)*(32)-1):((4)*(32))], e1_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:57: Cannot find file containing module: \'ch\'\n ch ch_blk (state[(((4)+1)*(32)-1):((4)*(32))], state[(((5)+1)*(32)-1):((5)*(32))], state[(((6)+1)*(32)-1):((6)*(32))], ch_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:58: Cannot find file containing module: \'maj\'\n maj maj_blk (state[(((0)+1)*(32)-1):((0)*(32))], state[(((1)+1)*(32)-1):((1)*(32))], state[(((2)+1)*(32)-1):((2)*(32))], maj_w);\n ^~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 311,039 | module | module sha256 (
input clk,
input rx_reset,
input [263:0] rx_public_key,
output reg tx_done = 1'b0,
output reg [255:0] tx_hash = 256'd0
);
wire [247:0] padding = {8'h80, 176'h00, 64'h0000000000000108};
reg [511:0] w;
reg [255:0] state;
reg [6:0] k_addr;
wire [31:0] k_const;
k_const_rom rom_blk (
.clk (clk),
.rx_address (k_addr[5:0]),
.tx_k (k_const)
);
wire [31:0] s0_w, s1_w, e0_w, e1_w, ch_w, maj_w;
s0 s0_blk (w[`IDX(1)], s0_w);
s1 s1_blk (w[`IDX(14)], s1_w);
e0 e0_blk (state[`IDX(0)], e0_w);
e1 e1_blk (state[`IDX(4)], e1_w);
ch ch_blk (state[`IDX(4)], state[`IDX(5)], state[`IDX(6)], ch_w);
maj maj_blk (state[`IDX(0)], state[`IDX(1)], state[`IDX(2)], maj_w);
wire [31:0] t1 = state[`IDX(7)] + e1_w + ch_w + w[31:0] + k_const;
wire [31:0] t2 = e0_w + maj_w;
always @ (posedge clk)
begin
w[`IDX(15)] <= w[`IDX(0)] + w[`IDX(9)] + s0_w + s1_w;
w[479:0] <= w[511:32];
state[`IDX(7)] <= state[`IDX(6)];
state[`IDX(6)] <= state[`IDX(5)];
state[`IDX(5)] <= state[`IDX(4)];
state[`IDX(4)] <= state[`IDX(3)] + t1;
state[`IDX(3)] <= state[`IDX(2)];
state[`IDX(2)] <= state[`IDX(1)];
state[`IDX(1)] <= state[`IDX(0)];
state[`IDX(0)] <= t1 + t2;
if (k_addr < 64)
k_addr <= k_addr + 7'd1;
if (k_addr == 64 && !tx_done)
begin
tx_hash[`IDX(7)] <= 32'h6a09e667 + state[`IDX(0)];
tx_hash[`IDX(6)] <= 32'hbb67ae85 + state[`IDX(1)];
tx_hash[`IDX(5)] <= 32'h3c6ef372 + state[`IDX(2)];
tx_hash[`IDX(4)] <= 32'ha54ff53a + state[`IDX(3)];
tx_hash[`IDX(3)] <= 32'h510e527f + state[`IDX(4)];
tx_hash[`IDX(2)] <= 32'h9b05688c + state[`IDX(5)];
tx_hash[`IDX(1)] <= 32'h1f83d9ab + state[`IDX(6)];
tx_hash[`IDX(0)] <= 32'h5be0cd19 + state[`IDX(7)];
tx_done <= 1'b1;
end
if (rx_reset)
begin
tx_done <= 1'b0;
state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
k_addr <= 0;
w[`IDX(0)] <= rx_public_key[263:232];
w[`IDX(1)] <= rx_public_key[231:200];
w[`IDX(2)] <= rx_public_key[199:168];
w[`IDX(3)] <= rx_public_key[167:136];
w[`IDX(4)] <= rx_public_key[135:104];
w[`IDX(5)] <= rx_public_key[103:72];
w[`IDX(6)] <= rx_public_key[71:40];
w[`IDX(7)] <= rx_public_key[39:8];
w[`IDX(8)] <= {rx_public_key[7:0], padding[247:224]};
w[`IDX(9)] <= padding[223:192];
w[`IDX(10)] <= padding[191:160];
w[`IDX(11)] <= padding[159:128];
w[`IDX(12)] <= padding[127:96];
w[`IDX(13)] <= padding[95:64];
w[`IDX(14)] <= padding[63:32];
w[`IDX(15)] <= padding[31:0];
end
end
endmodule | module sha256 (
input clk,
input rx_reset,
input [263:0] rx_public_key,
output reg tx_done = 1'b0,
output reg [255:0] tx_hash = 256'd0
); |
wire [247:0] padding = {8'h80, 176'h00, 64'h0000000000000108};
reg [511:0] w;
reg [255:0] state;
reg [6:0] k_addr;
wire [31:0] k_const;
k_const_rom rom_blk (
.clk (clk),
.rx_address (k_addr[5:0]),
.tx_k (k_const)
);
wire [31:0] s0_w, s1_w, e0_w, e1_w, ch_w, maj_w;
s0 s0_blk (w[`IDX(1)], s0_w);
s1 s1_blk (w[`IDX(14)], s1_w);
e0 e0_blk (state[`IDX(0)], e0_w);
e1 e1_blk (state[`IDX(4)], e1_w);
ch ch_blk (state[`IDX(4)], state[`IDX(5)], state[`IDX(6)], ch_w);
maj maj_blk (state[`IDX(0)], state[`IDX(1)], state[`IDX(2)], maj_w);
wire [31:0] t1 = state[`IDX(7)] + e1_w + ch_w + w[31:0] + k_const;
wire [31:0] t2 = e0_w + maj_w;
always @ (posedge clk)
begin
w[`IDX(15)] <= w[`IDX(0)] + w[`IDX(9)] + s0_w + s1_w;
w[479:0] <= w[511:32];
state[`IDX(7)] <= state[`IDX(6)];
state[`IDX(6)] <= state[`IDX(5)];
state[`IDX(5)] <= state[`IDX(4)];
state[`IDX(4)] <= state[`IDX(3)] + t1;
state[`IDX(3)] <= state[`IDX(2)];
state[`IDX(2)] <= state[`IDX(1)];
state[`IDX(1)] <= state[`IDX(0)];
state[`IDX(0)] <= t1 + t2;
if (k_addr < 64)
k_addr <= k_addr + 7'd1;
if (k_addr == 64 && !tx_done)
begin
tx_hash[`IDX(7)] <= 32'h6a09e667 + state[`IDX(0)];
tx_hash[`IDX(6)] <= 32'hbb67ae85 + state[`IDX(1)];
tx_hash[`IDX(5)] <= 32'h3c6ef372 + state[`IDX(2)];
tx_hash[`IDX(4)] <= 32'ha54ff53a + state[`IDX(3)];
tx_hash[`IDX(3)] <= 32'h510e527f + state[`IDX(4)];
tx_hash[`IDX(2)] <= 32'h9b05688c + state[`IDX(5)];
tx_hash[`IDX(1)] <= 32'h1f83d9ab + state[`IDX(6)];
tx_hash[`IDX(0)] <= 32'h5be0cd19 + state[`IDX(7)];
tx_done <= 1'b1;
end
if (rx_reset)
begin
tx_done <= 1'b0;
state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
k_addr <= 0;
w[`IDX(0)] <= rx_public_key[263:232];
w[`IDX(1)] <= rx_public_key[231:200];
w[`IDX(2)] <= rx_public_key[199:168];
w[`IDX(3)] <= rx_public_key[167:136];
w[`IDX(4)] <= rx_public_key[135:104];
w[`IDX(5)] <= rx_public_key[103:72];
w[`IDX(6)] <= rx_public_key[71:40];
w[`IDX(7)] <= rx_public_key[39:8];
w[`IDX(8)] <= {rx_public_key[7:0], padding[247:224]};
w[`IDX(9)] <= padding[223:192];
w[`IDX(10)] <= padding[191:160];
w[`IDX(11)] <= padding[159:128];
w[`IDX(12)] <= padding[127:96];
w[`IDX(13)] <= padding[95:64];
w[`IDX(14)] <= padding[63:32];
w[`IDX(15)] <= padding[31:0];
end
end
endmodule | 22 |
141,238 | data/full_repos/permissive/9411126/cores/sha256/sha256.v | 9,411,126 | sha256.v | v | 191 | 83 | [] | [] | [] | null | line:30: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9411126/cores/sha256/sha256.v:147: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2048 bits.\n : ... In instance sha256.rom_blk\n assign tx_k = Ks >> {rx_address, 5\'d0};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:53: Cannot find file containing module: \'s0\'\n s0 s0_blk (w[(((1)+1)*(32)-1):((1)*(32))], s0_w);\n ^~\n ... Looked in:\n data/full_repos/permissive/9411126/cores/sha256,data/full_repos/permissive/9411126/s0\n data/full_repos/permissive/9411126/cores/sha256,data/full_repos/permissive/9411126/s0.v\n data/full_repos/permissive/9411126/cores/sha256,data/full_repos/permissive/9411126/s0.sv\n s0\n s0.v\n s0.sv\n obj_dir/s0\n obj_dir/s0.v\n obj_dir/s0.sv\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:54: Cannot find file containing module: \'s1\'\n s1 s1_blk (w[(((14)+1)*(32)-1):((14)*(32))], s1_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:55: Cannot find file containing module: \'e0\'\n e0 e0_blk (state[(((0)+1)*(32)-1):((0)*(32))], e0_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:56: Cannot find file containing module: \'e1\'\n e1 e1_blk (state[(((4)+1)*(32)-1):((4)*(32))], e1_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:57: Cannot find file containing module: \'ch\'\n ch ch_blk (state[(((4)+1)*(32)-1):((4)*(32))], state[(((5)+1)*(32)-1):((5)*(32))], state[(((6)+1)*(32)-1):((6)*(32))], ch_w);\n ^~\n%Error: data/full_repos/permissive/9411126/cores/sha256/sha256.v:58: Cannot find file containing module: \'maj\'\n maj maj_blk (state[(((0)+1)*(32)-1):((0)*(32))], state[(((1)+1)*(32)-1):((1)*(32))], state[(((2)+1)*(32)-1):((2)*(32))], maj_w);\n ^~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 311,039 | module | module k_const_rom (
input clk,
input [5:0] rx_address,
output [31:0] tx_k
);
localparam Ks = {
32'hC67178F2, 32'hBEF9A3F7, 32'hA4506CEB, 32'h90BEFFFA,
32'h8CC70208, 32'h84C87814, 32'h78A5636F, 32'h748F82EE,
32'h682E6FF3, 32'h5B9CCA4F, 32'h4ED8AA4A, 32'h391C0CB3,
32'h34B0BCB5, 32'h2748774C, 32'h1E376C08, 32'h19A4C116,
32'h106AA070, 32'hF40E3585, 32'hD6990624, 32'hD192E819,
32'hC76C51A3, 32'hC24B8B70, 32'hA81A664B, 32'hA2BFE8A1,
32'h92722C85, 32'h81C2C92E, 32'h766A0ABB, 32'h650A7354,
32'h53380D13, 32'h4D2C6DFC, 32'h2E1B2138, 32'h27B70A85,
32'h14292967, 32'h06CA6351, 32'hD5A79147, 32'hC6E00BF3,
32'hBF597FC7, 32'hB00327C8, 32'hA831C66D, 32'h983E5152,
32'h76F988DA, 32'h5CB0A9DC, 32'h4A7484AA, 32'h2DE92C6F,
32'h240CA1CC, 32'h0FC19DC6, 32'hEFBE4786, 32'hE49B69C1,
32'hC19BF174, 32'h9BDC06A7, 32'h80DEB1FE, 32'h72BE5D74,
32'h550C7DC3, 32'h243185BE, 32'h12835B01, 32'hD807AA98,
32'hAB1C5ED5, 32'h923F82A4, 32'h59F111F1, 32'h3956C25B,
32'hE9B5DBA5, 32'hB5C0FBCF, 32'h71374491, 32'h428A2F98};
assign tx_k = Ks >> {rx_address, 5'd0};
endmodule | module k_const_rom (
input clk,
input [5:0] rx_address,
output [31:0] tx_k
); |
localparam Ks = {
32'hC67178F2, 32'hBEF9A3F7, 32'hA4506CEB, 32'h90BEFFFA,
32'h8CC70208, 32'h84C87814, 32'h78A5636F, 32'h748F82EE,
32'h682E6FF3, 32'h5B9CCA4F, 32'h4ED8AA4A, 32'h391C0CB3,
32'h34B0BCB5, 32'h2748774C, 32'h1E376C08, 32'h19A4C116,
32'h106AA070, 32'hF40E3585, 32'hD6990624, 32'hD192E819,
32'hC76C51A3, 32'hC24B8B70, 32'hA81A664B, 32'hA2BFE8A1,
32'h92722C85, 32'h81C2C92E, 32'h766A0ABB, 32'h650A7354,
32'h53380D13, 32'h4D2C6DFC, 32'h2E1B2138, 32'h27B70A85,
32'h14292967, 32'h06CA6351, 32'hD5A79147, 32'hC6E00BF3,
32'hBF597FC7, 32'hB00327C8, 32'hA831C66D, 32'h983E5152,
32'h76F988DA, 32'h5CB0A9DC, 32'h4A7484AA, 32'h2DE92C6F,
32'h240CA1CC, 32'h0FC19DC6, 32'hEFBE4786, 32'hE49B69C1,
32'hC19BF174, 32'h9BDC06A7, 32'h80DEB1FE, 32'h72BE5D74,
32'h550C7DC3, 32'h243185BE, 32'h12835B01, 32'hD807AA98,
32'hAB1C5ED5, 32'h923F82A4, 32'h59F111F1, 32'h3956C25B,
32'hE9B5DBA5, 32'hB5C0FBCF, 32'h71374491, 32'h428A2F98};
assign tx_k = Ks >> {rx_address, 5'd0};
endmodule | 22 |
141,239 | data/full_repos/permissive/9411126/cores/vanitygen-serial/address_hash.v | 9,411,126 | address_hash.v | v | 63 | 72 | [] | [] | [] | [(25, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/9411126/cores/vanitygen-serial/address_hash.v:38: Cannot find file containing module: 'sha256'\n sha256 sha256_blk (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/9411126/cores/vanitygen-serial,data/full_repos/permissive/9411126/sha256\n data/full_repos/permissive/9411126/cores/vanitygen-serial,data/full_repos/permissive/9411126/sha256.v\n data/full_repos/permissive/9411126/cores/vanitygen-serial,data/full_repos/permissive/9411126/sha256.sv\n sha256\n sha256.v\n sha256.sv\n obj_dir/sha256\n obj_dir/sha256.v\n obj_dir/sha256.sv\n%Error: data/full_repos/permissive/9411126/cores/vanitygen-serial/address_hash.v:46: Cannot find file containing module: 'ripemd160'\n ripemd160 ripemd160_blk (\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 311,040 | module | module address_hash (
input clk,
input rx_reset,
input [255:0] rx_x,
input [255:0] rx_y,
output tx_done,
output [159:0] tx_hash
);
reg ripe_reset = 1'b1;
wire sha_done;
wire [255:0] sha_hash;
sha256 sha256_blk (
.clk (clk),
.rx_reset (rx_reset),
.rx_public_key ({7'h1, rx_y[0], rx_x}),
.tx_done (sha_done),
.tx_hash (sha_hash)
);
ripemd160 ripemd160_blk (
.clk (clk),
.rx_reset (rx_reset | ripe_reset),
.rx_hash (sha_hash),
.tx_done (tx_done),
.tx_hash (tx_hash)
);
always @ (posedge clk)
begin
if (rx_reset)
ripe_reset <= 1'b1;
else if (sha_done)
ripe_reset <= 1'b0;
end
endmodule | module address_hash (
input clk,
input rx_reset,
input [255:0] rx_x,
input [255:0] rx_y,
output tx_done,
output [159:0] tx_hash
); |
reg ripe_reset = 1'b1;
wire sha_done;
wire [255:0] sha_hash;
sha256 sha256_blk (
.clk (clk),
.rx_reset (rx_reset),
.rx_public_key ({7'h1, rx_y[0], rx_x}),
.tx_done (sha_done),
.tx_hash (sha_hash)
);
ripemd160 ripemd160_blk (
.clk (clk),
.rx_reset (rx_reset | ripe_reset),
.rx_hash (sha_hash),
.tx_done (tx_done),
.tx_hash (tx_hash)
);
always @ (posedge clk)
begin
if (rx_reset)
ripe_reset <= 1'b1;
else if (sha_done)
ripe_reset <= 1'b0;
end
endmodule | 22 |
141,240 | data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v | 9,411,126 | bn_mul.v | v | 91 | 72 | [] | [] | [] | [(23, 90)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v:37: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 256 bits.\n : ... In instance bn_mul\n wire [31:0] a = rx_a >> ({i, 5\'d0});\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v:38: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 256 bits.\n : ... In instance bn_mul\n wire [31:0] b = rx_b >> ({j, 5\'d0});\n ^\n%Warning-WIDTH: data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v:40: Operator ADD expects 68 bits on the RHS, but RHS\'s VARREF \'mult_result\' generates 64 bits.\n : ... In instance bn_mul\n wire [67:0] new_accum = accum + mult_result;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v:53: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 4 bits.\n : ... In instance bn_mul\n j <= k + 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v:57: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n : ... In instance bn_mul\n i <= k - 6;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v:64: Operator SHIFTL expects 512 bits on the LHS, but LHS\'s SEL generates 32 bits.\n : ... In instance bn_mul\n tx_r <= tx_r | (new_accum[31:0] << ({k, 5\'d0}));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/9411126/cores/vanitygen-serial/bn_mul.v:47: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'i\' generates 3 bits.\n : ... In instance bn_mul\n if (i == 7 || i == k)\n ^~\n%Error: Exiting due to 7 warning(s)\n' | 311,041 | module | module bn_mul (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
output reg tx_done,
output reg [511:0] tx_r
);
reg [3:0] k;
reg [2:0] i, j;
reg [67:0] accum;
wire [31:0] a = rx_a >> ({i, 5'd0});
wire [31:0] b = rx_b >> ({j, 5'd0});
wire [63:0] mult_result = a * b;
wire [67:0] new_accum = accum + mult_result;
always @ (posedge clk)
begin
accum <= new_accum;
if (i == 7 || i == k)
begin
k <= k + 1;
if (k < 7)
begin
i <= 0;
j <= k + 1;
end
else
begin
i <= k - 6;
j <= 7;
end
accum <= new_accum >> 32;
if (!tx_done)
tx_r <= tx_r | (new_accum[31:0] << ({k, 5'd0}));
if (k == 14 && !tx_done)
begin
tx_done <= 1'b1;
tx_r[511:480] <= new_accum[63:32];
end
end
else
begin
i <= i + 1;
j <= j - 1;
end
if (reset)
begin
k <= 4'd0;
i <= 3'd0;
j <= 3'd0;
accum <= 68'd0;
tx_r <= 512'd0;
tx_done <= 1'b0;
end
end
endmodule | module bn_mul (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
output reg tx_done,
output reg [511:0] tx_r
); |
reg [3:0] k;
reg [2:0] i, j;
reg [67:0] accum;
wire [31:0] a = rx_a >> ({i, 5'd0});
wire [31:0] b = rx_b >> ({j, 5'd0});
wire [63:0] mult_result = a * b;
wire [67:0] new_accum = accum + mult_result;
always @ (posedge clk)
begin
accum <= new_accum;
if (i == 7 || i == k)
begin
k <= k + 1;
if (k < 7)
begin
i <= 0;
j <= k + 1;
end
else
begin
i <= k - 6;
j <= 7;
end
accum <= new_accum >> 32;
if (!tx_done)
tx_r <= tx_r | (new_accum[31:0] << ({k, 5'd0}));
if (k == 14 && !tx_done)
begin
tx_done <= 1'b1;
tx_r[511:480] <= new_accum[63:32];
end
end
else
begin
i <= i + 1;
j <= j - 1;
end
if (reset)
begin
k <= 4'd0;
i <= 3'd0;
j <= 3'd0;
accum <= 68'd0;
tx_r <= 512'd0;
tx_done <= 1'b0;
end
end
endmodule | 22 |
141,242 | data/full_repos/permissive/9411126/cores/vanitygen-serial/ff_mul.v | 9,411,126 | ff_mul.v | v | 64 | 72 | [] | [] | [] | [(22, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/9411126/cores/vanitygen-serial/ff_mul.v:34: Cannot find file containing module: 'bn_mul'\n bn_mul uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/9411126/cores/vanitygen-serial,data/full_repos/permissive/9411126/bn_mul\n data/full_repos/permissive/9411126/cores/vanitygen-serial,data/full_repos/permissive/9411126/bn_mul.v\n data/full_repos/permissive/9411126/cores/vanitygen-serial,data/full_repos/permissive/9411126/bn_mul.sv\n bn_mul\n bn_mul.v\n bn_mul.sv\n obj_dir/bn_mul\n obj_dir/bn_mul.v\n obj_dir/bn_mul.sv\n%Error: data/full_repos/permissive/9411126/cores/vanitygen-serial/ff_mul.v:45: Cannot find file containing module: 'ff_reduce_secp256k1'\n ff_reduce_secp256k1 uut2 (\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 311,043 | module | module ff_mul (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
output tx_done,
output [255:0] tx_c
);
wire mul_done;
wire [511:0] mul_result;
bn_mul uut (
.clk (clk),
.reset (reset),
.rx_a (rx_a),
.rx_b (rx_b),
.tx_done (mul_done),
.tx_r (mul_result)
);
reg reduce_reset = 1'b1;
ff_reduce_secp256k1 uut2 (
.clk (clk),
.reset (reset | reduce_reset),
.rx_a (mul_result),
.tx_done (tx_done),
.tx_a (tx_c)
);
always @ (posedge clk)
begin
if (reset)
reduce_reset <= 1'b1;
else if (mul_done)
reduce_reset <= 1'b0;
end
endmodule | module ff_mul (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
output tx_done,
output [255:0] tx_c
); |
wire mul_done;
wire [511:0] mul_result;
bn_mul uut (
.clk (clk),
.reset (reset),
.rx_a (rx_a),
.rx_b (rx_b),
.tx_done (mul_done),
.tx_r (mul_result)
);
reg reduce_reset = 1'b1;
ff_reduce_secp256k1 uut2 (
.clk (clk),
.reset (reset | reduce_reset),
.rx_a (mul_result),
.tx_done (tx_done),
.tx_a (tx_c)
);
always @ (posedge clk)
begin
if (reset)
reduce_reset <= 1'b1;
else if (mul_done)
reduce_reset <= 1'b0;
end
endmodule | 22 |
141,253 | data/full_repos/permissive/9411126/cores/virtual_wire/virtual_wire.v | 9,411,126 | virtual_wire.v | v | 65 | 72 | [] | [] | [] | null | line:56: before: "." | null | 1: b"%Error: data/full_repos/permissive/9411126/cores/virtual_wire/virtual_wire.v:34: Cannot find file containing module: 'altsource_probe'\n altsource_probe altsource_probe_component (\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9411126/cores/virtual_wire,data/full_repos/permissive/9411126/altsource_probe\n data/full_repos/permissive/9411126/cores/virtual_wire,data/full_repos/permissive/9411126/altsource_probe.v\n data/full_repos/permissive/9411126/cores/virtual_wire,data/full_repos/permissive/9411126/altsource_probe.sv\n altsource_probe\n altsource_probe.v\n altsource_probe.sv\n obj_dir/altsource_probe\n obj_dir/altsource_probe.v\n obj_dir/altsource_probe.sv\n%Error: Exiting due to 1 error(s)\n" | 311,049 | module | module virtual_wire # (
parameter INPUT_WIDTH = 1,
parameter OUTPUT_WIDTH = 1,
parameter INITIAL_VALUE = " 0",
parameter INSTANCE_ID = "NONE"
) (
input clk,
input [INPUT_WIDTH-1:0] rx_input,
output [OUTPUT_WIDTH-1:0] tx_output
);
altsource_probe altsource_probe_component (
.probe (rx_input),
.source (tx_output),
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (clk),
.source_ena (1'b1),
.tdi (),
.tdo (),
.usr1 ()
);
defparam
altsource_probe_component.enable_metastability = "YES",
altsource_probe_component.instance_id = INSTANCE_ID,
altsource_probe_component.probe_width = INPUT_WIDTH,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = INITIAL_VALUE,
altsource_probe_component.source_width = OUTPUT_WIDTH;
endmodule | module virtual_wire # (
parameter INPUT_WIDTH = 1,
parameter OUTPUT_WIDTH = 1,
parameter INITIAL_VALUE = " 0",
parameter INSTANCE_ID = "NONE"
) (
input clk,
input [INPUT_WIDTH-1:0] rx_input,
output [OUTPUT_WIDTH-1:0] tx_output
); |
altsource_probe altsource_probe_component (
.probe (rx_input),
.source (tx_output),
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (clk),
.source_ena (1'b1),
.tdi (),
.tdo (),
.usr1 ()
);
defparam
altsource_probe_component.enable_metastability = "YES",
altsource_probe_component.instance_id = INSTANCE_ID,
altsource_probe_component.probe_width = INPUT_WIDTH,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = INITIAL_VALUE,
altsource_probe_component.source_width = OUTPUT_WIDTH;
endmodule | 22 |
141,255 | data/full_repos/permissive/94358170/Apogee.sv | 94,358,170 | Apogee.sv | sv | 761 | 158 | [] | [] | [] | null | line:121 column:20: Illegal character "'" | null | 1: b'%Error: data/full_repos/permissive/94358170/Apogee.sv:155: Cannot find include file: build_id.v\n`include "build_id.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94358170,data/full_repos/permissive/94358170/build_id.v\n data/full_repos/permissive/94358170,data/full_repos/permissive/94358170/build_id.v.v\n data/full_repos/permissive/94358170,data/full_repos/permissive/94358170/build_id.v.sv\n build_id.v\n build_id.v.v\n build_id.v.sv\n obj_dir/build_id.v\n obj_dir/build_id.v.v\n obj_dir/build_id.v.sv\n%Error: data/full_repos/permissive/94358170/Apogee.sv:169: Define or directive not defined: \'`BUILD_DATE\'\n "V,v",`BUILD_DATE\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94358170/Apogee.sv:170: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n};\n^\n%Error: Exiting due to 3 error(s)\n' | 311,051 | module | module emu
(
input CLK_50M,
input RESET,
inout [45:0] HPS_BUS,
output CLK_VIDEO,
output CE_PIXEL,
output [11:0] VIDEO_ARX,
output [11:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER,
output LED_USER,
output [1:0] LED_POWER,
output [1:0] LED_DISK,
output [1:0] BUTTONS,
input CLK_AUDIO,
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S,
output [1:0] AUDIO_MIX,
inout [3:0] ADC_BUS,
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
);
assign ADC_BUS = 'Z;
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign LED_USER = filling;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign BUTTONS = 0;
assign VGA_SCALER= 0;
wire [1:0] ar = status[7:6];
assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
assign CLK_VIDEO = clk_sys;
wire [31:0] status;
wire [1:0] buttons;
wire forced_scandoubler;
wire [10:0] ps2_key;
wire [21:0] gamma_bus;
wire ioctl_wait;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_data;
wire ioctl_download;
wire [7:0] ioctl_index;
`include "build_id.v"
localparam CONF_STR =
{
"APOGEE;;",
"-;",
"F,RKARKRGAM;",
"O5,Autostart,Yes,No;",
"-;",
"O1,Color,On,Off;",
"O67,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"O23,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
"-;",
"O4,CPU speed,Normal,Double;",
"R0,Reset;",
"V,v",`BUILD_DATE
};
hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str(CONF_STR),
.buttons(buttons),
.forced_scandoubler(forced_scandoubler),
.gamma_bus(gamma_bus),
.status(status),
.ioctl_download(ioctl_download),
.ioctl_index(ioctl_index),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_data),
.ioctl_wait(ioctl_wait),
.ps2_key(ps2_key),
.ps2_kbd_led_use(0),
.ps2_kbd_led_status(0),
.sd_lba(0),
.sd_rd(0),
.sd_wr(0),
.sd_conf(0),
.sd_buff_din(0)
);
wire locked;
wire clk_sys;
reg ce_f1,ce_f2;
reg ce_pix;
reg ce_pit;
reg ce_lpf;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys),
.locked(locked)
);
always @(posedge clk_sys) begin
reg [3:0] clk_viddiv;
reg [6:0] cpu_div = 0;
reg turbo = 0;
clk_viddiv <= clk_viddiv + 1'd1;
if(clk_viddiv == 11) clk_viddiv <=0;
ce_pix <= (clk_viddiv == 0);
cpu_div <= cpu_div + 1'd1;
if(cpu_div == 53) begin
cpu_div <= 0;
turbo <= status[4];
end
ce_f1 <= ((cpu_div == 0) | (turbo & (cpu_div == 27)));
ce_f2 <= ((cpu_div == 13) | (turbo & (cpu_div == 40)));
ce_pit <= (cpu_div == 8);
ce_lpf <= ((cpu_div == 0) | (cpu_div == 27));
startup <= reset|(startup&~addrbus[15]);
end
reg reset;
reg sys_ready = 0;
wire reset_req = ~sys_ready | status[0] | buttons[1] | reset_key[0] | filling;
always @(posedge clk_sys) begin
reg [3:0] reset_cnt;
reg old_rst;
old_rst <= status[0];
if(old_rst & ~status[0]) sys_ready <= 1;
if(reset_req) begin
reset <= 1;
reset_cnt <= 0;
end else if(~&reset_cnt) begin
reset_cnt <= reset_cnt + 1'd1;
end else begin
reset <= 0;
end
end
wire [7:0] ram_dout;
reg [7:0] ram_din;
reg [15:0] ram_addr;
reg ram_we;
always_comb begin
if(filling) begin
ram_din <= fill_data;
ram_addr <= fill_addr[15:0];
ram_we <= fill_wr && !fill_addr[24:16];
end else begin
ram_din <= cpu_o;
ram_addr <= addrbus;
ram_we <= ~cpu_wr_n;
end
end
wire [7:0] rom_o;
bios rom(.address({addrbus[11]|startup,addrbus[10:0]}), .clock(clk_sys), .q(rom_o));
wire [7:0] rom86_o;
bios86 rom86(.address(addrbus[10:0]), .clock(clk_sys), .q(rom86_o));
wire [7:0] vid_dout;
dpram ram
(
.clock(clk_sys),
.address_a(ram_addr),
.data_a(ram_din),
.wren_a(ram_we),
.q_a(ram_dout),
.address_b(vid_addr),
.data_b(0),
.wren_b(0),
.q_b(vid_dout)
);
assign DDRAM_CLK = clk_sys;
wire [7:0] ext_dout;
wire ext_ready;
wire ext_rd = ~ppa2_sel | cpu_wr_n;
ddram ext_rom
(
.*,
.addr((filling && !ioctl_index) ? fill_addr[18:0] : extaddr),
.din(fill_data),
.we(fill_wr && !ioctl_index),
.dout(ext_dout),
.rd(ext_rd),
.ready(ext_ready)
);
assign ioctl_wait = ioctl_download && !ioctl_index && ~ext_ready;
wire [15:0] addrbus;
reg [7:0] cpu_i;
wire [7:0] cpu_o;
wire cpu_sync;
wire cpu_rd;
wire cpu_wr_n;
wire cpu_int = 0;
wire cpu_inta_n;
wire inte;
reg startup;
reg mode86 = 0;
always @(posedge clk_sys) begin
reg old_download;
old_download <= ioctl_download;
if(~old_download & ioctl_download) mode86 <= (ioctl_index>1);
if(reset_key) mode86 <= reset_key[2];
end
reg ppa1_sel, ppa2_sel, pit_sel, crt_sel, dma_sel;
always_comb begin
ppa1_sel =0;
ppa2_sel =0;
pit_sel =0;
crt_sel =0;
dma_sel =0;
casex({startup, mode86, addrbus[15:8]})
10'b0011101100: begin cpu_i = pit_o; pit_sel = 1; end
10'b0011101101: begin cpu_i = ppa1_o; ppa1_sel = 1; end
10'b0011101110: begin cpu_i = ppa2_o; ppa2_sel = 1; end
10'b0011101111: begin cpu_i = crt_o; crt_sel = 1; end
10'b001111XXXX: begin cpu_i = rom_o; dma_sel = !addrbus[11:8]; end
10'b10XXXXXXXX: begin cpu_i = rom_o; end
10'b01100XXXXX: begin cpu_i = ppa1_o; ppa1_sel = 1; end
10'b0110100XXX: begin cpu_i = pit_o; pit_sel = 1; end
10'b0110101XXX: begin cpu_i = 0; end
10'b011011XXXX: begin cpu_i = 0; end
10'b01110XXXXX: begin cpu_i = crt_o; crt_sel = 1; end
10'b01111XXXXX: begin cpu_i = rom86_o; dma_sel = 1; end
10'b11XXXXXXXX: begin cpu_i = rom86_o; end
default: cpu_i <= ram_dout;
endcase
end
k580vm80a cpu
(
.pin_clk(clk_sys),
.pin_f1(ce_f1),
.pin_f2(ce_f2),
.pin_reset(reset),
.pin_a(addrbus),
.pin_dout(cpu_o),
.pin_din(cpu_i),
.pin_hold(hrq),
.pin_hlda(hlda),
.pin_ready(ext_ready),
.pin_wait(),
.pin_int(cpu_int),
.pin_inte(inte),
.pin_sync(cpu_sync),
.pin_dbin(cpu_rd),
.pin_wr_n(cpu_wr_n)
);
wire [7:0] dma_o;
wire hlda;
wire dma_rd_n;
wire hrq;
wire vid_drq;
wire vid_dack;
wire [7:0] crt_o;
wire [15:0] vid_addr;
wire pix;
wire vid_hilight;
wire [1:0] vid_gattr;
wire [3:0] bw_pix = {{1{pix}}, {3{pix & vid_hilight}}};
wire [5:0] R_out, r_out;
wire [5:0] G_out, g_out;
wire [5:0] B_out, b_out;
wire HSync, VSync, HBlank, VBlank, hs_out, vs_out;
k580vt57 dma
(
.clk(clk_sys),
.ce_dma(ce_f2),
.reset(reset),
.iaddr(addrbus[3:0]),
.idata(cpu_o),
.drq ({1'b0,vid_drq, 2'b00}),
.dack({1'bZ,vid_dack,2'bZZ}),
.iwe_n(~dma_sel | cpu_wr_n),
.ird_n(1),
.hlda(hlda),
.hrq(hrq),
.odata(dma_o),
.oaddr(vid_addr),
.oiord_n(dma_rd_n)
);
k580vg75 crt
(
.clk_sys(clk_sys),
.ce_pix(ce_pix),
.iaddr(addrbus[0]),
.idata(hlda ? vid_dout : cpu_o),
.odata(crt_o),
.iwe_n(~crt_sel | cpu_wr_n),
.ird_n(~crt_sel | ~cpu_rd),
.drq(vid_drq),
.dack(vid_dack),
.vrtc(VSync),
.hrtc(HSync),
.vblank(VBlank),
.hblank(HBlank),
.pix(pix),
.hilight(vid_hilight),
.gattr(vid_gattr),
.charset(mode86 ? 1'b0 : inte),
.scr_shift(alt_dir)
);
assign VGA_SL = status[3:2];
assign VGA_F1 = 0;
video_mixer #(.HALF_DEPTH(1), .GAMMA(1)) video_mixer
(
.*,
.clk_vid(clk_sys),
.ce_pix_out(CE_PIXEL),
.scanlines(0),
.hq2x(0),
.scandoubler(VGA_SL || forced_scandoubler),
.mono(0),
.R(status[1] ? bw_pix : {4{pix & ~vid_hilight }}),
.G(status[1] ? bw_pix : {4{pix & ~vid_gattr[1]}}),
.B(status[1] ? bw_pix : {4{pix & ~vid_gattr[0]}})
);
wire [7:0] kbd_o;
wire [2:0] kbd_shift;
wire [2:0] reset_key;
wire [4:0] alt_dir;
keyboard keyboard
(
.clk(clk_sys),
.reset(reset),
.downloading(erasing & ~status[5]),
.ps2_key(ps2_key),
.addr(~ppa1_a),
.odata(kbd_o),
.shift(kbd_shift),
.reset_key(reset_key),
.alt_dir(alt_dir)
);
wire [7:0] ppa1_o;
wire [7:0] ppa1_a;
wire [7:0] ppa1_b;
wire [7:0] ppa1_c;
k580vv55 ppa1
(
.clk_sys(clk_sys),
.reset(reset),
.addr(addrbus[1:0]),
.we_n(~ppa1_sel | cpu_wr_n),
.idata(cpu_o),
.odata(ppa1_o),
.ipa(ppa1_a),
.opa(ppa1_a),
.ipb(~kbd_o),
.opb(ppa1_b),
.ipc({~kbd_shift,tapein,ppa1_c[3:0]}),
.opc(ppa1_c)
);
wire [7:0] ppa2_o;
wire [7:0] ppa2_b;
wire [7:0] ppa2_c;
reg [3:0] tm9;
wire [18:0] extaddr = {tm9, ppa2_c[6:0], ppa2_b};
always @(posedge clk_sys) begin
reg old_c7;
old_c7 <= ppa2_c[7];
if(~old_c7 & ppa2_c[7]) tm9<=ppa2_b[3:0];
end
k580vv55 ppa2
(
.clk_sys(clk_sys),
.reset(reset),
.addr(addrbus[1:0]),
.we_n(~ppa2_sel | cpu_wr_n),
.idata(cpu_o),
.odata(ppa2_o),
.ipa(ext_dout),
.ipb(ppa2_b),
.opb(ppa2_b),
.ipc(ppa2_c),
.opc(ppa2_c)
);
wire tapein = 0;
wire [7:0] pit_o;
wire pit_out0;
wire pit_out1;
wire pit_out2;
k580vi53 pit
(
.reset(reset),
.clk_sys(clk_sys),
.clk_timer({ce_pit,ce_pit,ce_pit}),
.addr(addrbus[1:0]),
.wr(pit_sel & ~cpu_wr_n),
.rd(pit_sel & cpu_rd),
.din(cpu_o),
.dout(pit_o),
.gate(3'b111),
.out({pit_out2, pit_out1, pit_out0})
);
wire [15:0] sample = {2'b00, {13{ppa1_c[0]}}} + {2'b00, {13{(mode86 & inte)}}} + {2'b00, {13{pit_out0}}} + {2'b00, {13{pit_out1}}} + {2'b00, {13{pit_out2}}};
lpf48k #(15) lpf48k
(
.RESET(0),
.CLK(clk_sys),
.CE(ce_lpf),
.ENABLE(1),
.IDATA(sample),
.ODATA(AUDIO_R)
);
assign AUDIO_L = AUDIO_R;
assign AUDIO_S = 0;
assign AUDIO_MIX = 0;
wire filling = (ioctl_download || erasing);
reg erasing = 0;
reg fill_wr;
reg [24:0] fill_addr;
reg [7:0] fill_data;
reg [24:0] erase_mask;
wire [24:0] next_erase = (fill_addr + 1'd1) & erase_mask;
wire addr_off = ((ioctl_index == 'h01) || (ioctl_index == 'h41));
always@(posedge clk_sys) begin
reg [24:0] addr;
reg wr;
reg [5:0] erase_clk_div;
reg [24:0] end_addr;
reg erase_trigger = 0;
reg [15:0] start_addr;
fill_wr <= wr;
wr <= 0;
if(ioctl_download) begin
erasing <= 0;
erase_trigger <= (ioctl_index != 0);
if(ioctl_wr) begin
if(!ioctl_index) begin
fill_addr <= 25'h200000 + ioctl_addr;
fill_data <= ioctl_data;
wr <= 1;
end
else begin
case(ioctl_addr+addr_off)
0: begin
end
1: begin
start_addr[15:8] <= ioctl_data;
fill_data <= 8'hC3;
fill_addr <= 0;
wr <= 1;
end
2: begin
start_addr[7:0] <= ioctl_data;
fill_data <= ioctl_data;
fill_addr <= 1;
wr <= 1;
end
3: begin
fill_data <= start_addr[15:8];
fill_addr <= 2;
wr <= 1;
end
4: begin
addr <= start_addr;
end
default:
begin
fill_addr <= addr;
fill_data <= ioctl_data;
addr <= addr + 1'd1;
wr <= 1;
end
endcase
end
end
end else begin
if(erase_trigger) begin
erase_trigger <= 0;
erase_mask <= 'hFFFF;
end_addr <= start_addr;
erase_clk_div <= 1;
erasing <= 1;
end else if(erasing) begin
erase_clk_div <= erase_clk_div + 1'd1;
if(!erase_clk_div) begin
if(next_erase == end_addr) erasing <= 0;
else begin
fill_addr <= next_erase;
fill_data <= 0;
if(next_erase > 2) wr <= 1;
end
end
end
end
end
endmodule | module emu
(
input CLK_50M,
input RESET,
inout [45:0] HPS_BUS,
output CLK_VIDEO,
output CE_PIXEL,
output [11:0] VIDEO_ARX,
output [11:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER,
output LED_USER,
output [1:0] LED_POWER,
output [1:0] LED_DISK,
output [1:0] BUTTONS,
input CLK_AUDIO,
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S,
output [1:0] AUDIO_MIX,
inout [3:0] ADC_BUS,
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
); |
assign ADC_BUS = 'Z;
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign LED_USER = filling;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign BUTTONS = 0;
assign VGA_SCALER= 0;
wire [1:0] ar = status[7:6];
assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
assign CLK_VIDEO = clk_sys;
wire [31:0] status;
wire [1:0] buttons;
wire forced_scandoubler;
wire [10:0] ps2_key;
wire [21:0] gamma_bus;
wire ioctl_wait;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_data;
wire ioctl_download;
wire [7:0] ioctl_index;
`include "build_id.v"
localparam CONF_STR =
{
"APOGEE;;",
"-;",
"F,RKARKRGAM;",
"O5,Autostart,Yes,No;",
"-;",
"O1,Color,On,Off;",
"O67,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"O23,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
"-;",
"O4,CPU speed,Normal,Double;",
"R0,Reset;",
"V,v",`BUILD_DATE
};
hps_io #(.STRLEN(($size(CONF_STR)>>3))) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str(CONF_STR),
.buttons(buttons),
.forced_scandoubler(forced_scandoubler),
.gamma_bus(gamma_bus),
.status(status),
.ioctl_download(ioctl_download),
.ioctl_index(ioctl_index),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_data),
.ioctl_wait(ioctl_wait),
.ps2_key(ps2_key),
.ps2_kbd_led_use(0),
.ps2_kbd_led_status(0),
.sd_lba(0),
.sd_rd(0),
.sd_wr(0),
.sd_conf(0),
.sd_buff_din(0)
);
wire locked;
wire clk_sys;
reg ce_f1,ce_f2;
reg ce_pix;
reg ce_pit;
reg ce_lpf;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys),
.locked(locked)
);
always @(posedge clk_sys) begin
reg [3:0] clk_viddiv;
reg [6:0] cpu_div = 0;
reg turbo = 0;
clk_viddiv <= clk_viddiv + 1'd1;
if(clk_viddiv == 11) clk_viddiv <=0;
ce_pix <= (clk_viddiv == 0);
cpu_div <= cpu_div + 1'd1;
if(cpu_div == 53) begin
cpu_div <= 0;
turbo <= status[4];
end
ce_f1 <= ((cpu_div == 0) | (turbo & (cpu_div == 27)));
ce_f2 <= ((cpu_div == 13) | (turbo & (cpu_div == 40)));
ce_pit <= (cpu_div == 8);
ce_lpf <= ((cpu_div == 0) | (cpu_div == 27));
startup <= reset|(startup&~addrbus[15]);
end
reg reset;
reg sys_ready = 0;
wire reset_req = ~sys_ready | status[0] | buttons[1] | reset_key[0] | filling;
always @(posedge clk_sys) begin
reg [3:0] reset_cnt;
reg old_rst;
old_rst <= status[0];
if(old_rst & ~status[0]) sys_ready <= 1;
if(reset_req) begin
reset <= 1;
reset_cnt <= 0;
end else if(~&reset_cnt) begin
reset_cnt <= reset_cnt + 1'd1;
end else begin
reset <= 0;
end
end
wire [7:0] ram_dout;
reg [7:0] ram_din;
reg [15:0] ram_addr;
reg ram_we;
always_comb begin
if(filling) begin
ram_din <= fill_data;
ram_addr <= fill_addr[15:0];
ram_we <= fill_wr && !fill_addr[24:16];
end else begin
ram_din <= cpu_o;
ram_addr <= addrbus;
ram_we <= ~cpu_wr_n;
end
end
wire [7:0] rom_o;
bios rom(.address({addrbus[11]|startup,addrbus[10:0]}), .clock(clk_sys), .q(rom_o));
wire [7:0] rom86_o;
bios86 rom86(.address(addrbus[10:0]), .clock(clk_sys), .q(rom86_o));
wire [7:0] vid_dout;
dpram ram
(
.clock(clk_sys),
.address_a(ram_addr),
.data_a(ram_din),
.wren_a(ram_we),
.q_a(ram_dout),
.address_b(vid_addr),
.data_b(0),
.wren_b(0),
.q_b(vid_dout)
);
assign DDRAM_CLK = clk_sys;
wire [7:0] ext_dout;
wire ext_ready;
wire ext_rd = ~ppa2_sel | cpu_wr_n;
ddram ext_rom
(
.*,
.addr((filling && !ioctl_index) ? fill_addr[18:0] : extaddr),
.din(fill_data),
.we(fill_wr && !ioctl_index),
.dout(ext_dout),
.rd(ext_rd),
.ready(ext_ready)
);
assign ioctl_wait = ioctl_download && !ioctl_index && ~ext_ready;
wire [15:0] addrbus;
reg [7:0] cpu_i;
wire [7:0] cpu_o;
wire cpu_sync;
wire cpu_rd;
wire cpu_wr_n;
wire cpu_int = 0;
wire cpu_inta_n;
wire inte;
reg startup;
reg mode86 = 0;
always @(posedge clk_sys) begin
reg old_download;
old_download <= ioctl_download;
if(~old_download & ioctl_download) mode86 <= (ioctl_index>1);
if(reset_key) mode86 <= reset_key[2];
end
reg ppa1_sel, ppa2_sel, pit_sel, crt_sel, dma_sel;
always_comb begin
ppa1_sel =0;
ppa2_sel =0;
pit_sel =0;
crt_sel =0;
dma_sel =0;
casex({startup, mode86, addrbus[15:8]})
10'b0011101100: begin cpu_i = pit_o; pit_sel = 1; end
10'b0011101101: begin cpu_i = ppa1_o; ppa1_sel = 1; end
10'b0011101110: begin cpu_i = ppa2_o; ppa2_sel = 1; end
10'b0011101111: begin cpu_i = crt_o; crt_sel = 1; end
10'b001111XXXX: begin cpu_i = rom_o; dma_sel = !addrbus[11:8]; end
10'b10XXXXXXXX: begin cpu_i = rom_o; end
10'b01100XXXXX: begin cpu_i = ppa1_o; ppa1_sel = 1; end
10'b0110100XXX: begin cpu_i = pit_o; pit_sel = 1; end
10'b0110101XXX: begin cpu_i = 0; end
10'b011011XXXX: begin cpu_i = 0; end
10'b01110XXXXX: begin cpu_i = crt_o; crt_sel = 1; end
10'b01111XXXXX: begin cpu_i = rom86_o; dma_sel = 1; end
10'b11XXXXXXXX: begin cpu_i = rom86_o; end
default: cpu_i <= ram_dout;
endcase
end
k580vm80a cpu
(
.pin_clk(clk_sys),
.pin_f1(ce_f1),
.pin_f2(ce_f2),
.pin_reset(reset),
.pin_a(addrbus),
.pin_dout(cpu_o),
.pin_din(cpu_i),
.pin_hold(hrq),
.pin_hlda(hlda),
.pin_ready(ext_ready),
.pin_wait(),
.pin_int(cpu_int),
.pin_inte(inte),
.pin_sync(cpu_sync),
.pin_dbin(cpu_rd),
.pin_wr_n(cpu_wr_n)
);
wire [7:0] dma_o;
wire hlda;
wire dma_rd_n;
wire hrq;
wire vid_drq;
wire vid_dack;
wire [7:0] crt_o;
wire [15:0] vid_addr;
wire pix;
wire vid_hilight;
wire [1:0] vid_gattr;
wire [3:0] bw_pix = {{1{pix}}, {3{pix & vid_hilight}}};
wire [5:0] R_out, r_out;
wire [5:0] G_out, g_out;
wire [5:0] B_out, b_out;
wire HSync, VSync, HBlank, VBlank, hs_out, vs_out;
k580vt57 dma
(
.clk(clk_sys),
.ce_dma(ce_f2),
.reset(reset),
.iaddr(addrbus[3:0]),
.idata(cpu_o),
.drq ({1'b0,vid_drq, 2'b00}),
.dack({1'bZ,vid_dack,2'bZZ}),
.iwe_n(~dma_sel | cpu_wr_n),
.ird_n(1),
.hlda(hlda),
.hrq(hrq),
.odata(dma_o),
.oaddr(vid_addr),
.oiord_n(dma_rd_n)
);
k580vg75 crt
(
.clk_sys(clk_sys),
.ce_pix(ce_pix),
.iaddr(addrbus[0]),
.idata(hlda ? vid_dout : cpu_o),
.odata(crt_o),
.iwe_n(~crt_sel | cpu_wr_n),
.ird_n(~crt_sel | ~cpu_rd),
.drq(vid_drq),
.dack(vid_dack),
.vrtc(VSync),
.hrtc(HSync),
.vblank(VBlank),
.hblank(HBlank),
.pix(pix),
.hilight(vid_hilight),
.gattr(vid_gattr),
.charset(mode86 ? 1'b0 : inte),
.scr_shift(alt_dir)
);
assign VGA_SL = status[3:2];
assign VGA_F1 = 0;
video_mixer #(.HALF_DEPTH(1), .GAMMA(1)) video_mixer
(
.*,
.clk_vid(clk_sys),
.ce_pix_out(CE_PIXEL),
.scanlines(0),
.hq2x(0),
.scandoubler(VGA_SL || forced_scandoubler),
.mono(0),
.R(status[1] ? bw_pix : {4{pix & ~vid_hilight }}),
.G(status[1] ? bw_pix : {4{pix & ~vid_gattr[1]}}),
.B(status[1] ? bw_pix : {4{pix & ~vid_gattr[0]}})
);
wire [7:0] kbd_o;
wire [2:0] kbd_shift;
wire [2:0] reset_key;
wire [4:0] alt_dir;
keyboard keyboard
(
.clk(clk_sys),
.reset(reset),
.downloading(erasing & ~status[5]),
.ps2_key(ps2_key),
.addr(~ppa1_a),
.odata(kbd_o),
.shift(kbd_shift),
.reset_key(reset_key),
.alt_dir(alt_dir)
);
wire [7:0] ppa1_o;
wire [7:0] ppa1_a;
wire [7:0] ppa1_b;
wire [7:0] ppa1_c;
k580vv55 ppa1
(
.clk_sys(clk_sys),
.reset(reset),
.addr(addrbus[1:0]),
.we_n(~ppa1_sel | cpu_wr_n),
.idata(cpu_o),
.odata(ppa1_o),
.ipa(ppa1_a),
.opa(ppa1_a),
.ipb(~kbd_o),
.opb(ppa1_b),
.ipc({~kbd_shift,tapein,ppa1_c[3:0]}),
.opc(ppa1_c)
);
wire [7:0] ppa2_o;
wire [7:0] ppa2_b;
wire [7:0] ppa2_c;
reg [3:0] tm9;
wire [18:0] extaddr = {tm9, ppa2_c[6:0], ppa2_b};
always @(posedge clk_sys) begin
reg old_c7;
old_c7 <= ppa2_c[7];
if(~old_c7 & ppa2_c[7]) tm9<=ppa2_b[3:0];
end
k580vv55 ppa2
(
.clk_sys(clk_sys),
.reset(reset),
.addr(addrbus[1:0]),
.we_n(~ppa2_sel | cpu_wr_n),
.idata(cpu_o),
.odata(ppa2_o),
.ipa(ext_dout),
.ipb(ppa2_b),
.opb(ppa2_b),
.ipc(ppa2_c),
.opc(ppa2_c)
);
wire tapein = 0;
wire [7:0] pit_o;
wire pit_out0;
wire pit_out1;
wire pit_out2;
k580vi53 pit
(
.reset(reset),
.clk_sys(clk_sys),
.clk_timer({ce_pit,ce_pit,ce_pit}),
.addr(addrbus[1:0]),
.wr(pit_sel & ~cpu_wr_n),
.rd(pit_sel & cpu_rd),
.din(cpu_o),
.dout(pit_o),
.gate(3'b111),
.out({pit_out2, pit_out1, pit_out0})
);
wire [15:0] sample = {2'b00, {13{ppa1_c[0]}}} + {2'b00, {13{(mode86 & inte)}}} + {2'b00, {13{pit_out0}}} + {2'b00, {13{pit_out1}}} + {2'b00, {13{pit_out2}}};
lpf48k #(15) lpf48k
(
.RESET(0),
.CLK(clk_sys),
.CE(ce_lpf),
.ENABLE(1),
.IDATA(sample),
.ODATA(AUDIO_R)
);
assign AUDIO_L = AUDIO_R;
assign AUDIO_S = 0;
assign AUDIO_MIX = 0;
wire filling = (ioctl_download || erasing);
reg erasing = 0;
reg fill_wr;
reg [24:0] fill_addr;
reg [7:0] fill_data;
reg [24:0] erase_mask;
wire [24:0] next_erase = (fill_addr + 1'd1) & erase_mask;
wire addr_off = ((ioctl_index == 'h01) || (ioctl_index == 'h41));
always@(posedge clk_sys) begin
reg [24:0] addr;
reg wr;
reg [5:0] erase_clk_div;
reg [24:0] end_addr;
reg erase_trigger = 0;
reg [15:0] start_addr;
fill_wr <= wr;
wr <= 0;
if(ioctl_download) begin
erasing <= 0;
erase_trigger <= (ioctl_index != 0);
if(ioctl_wr) begin
if(!ioctl_index) begin
fill_addr <= 25'h200000 + ioctl_addr;
fill_data <= ioctl_data;
wr <= 1;
end
else begin
case(ioctl_addr+addr_off)
0: begin
end
1: begin
start_addr[15:8] <= ioctl_data;
fill_data <= 8'hC3;
fill_addr <= 0;
wr <= 1;
end
2: begin
start_addr[7:0] <= ioctl_data;
fill_data <= ioctl_data;
fill_addr <= 1;
wr <= 1;
end
3: begin
fill_data <= start_addr[15:8];
fill_addr <= 2;
wr <= 1;
end
4: begin
addr <= start_addr;
end
default:
begin
fill_addr <= addr;
fill_data <= ioctl_data;
addr <= addr + 1'd1;
wr <= 1;
end
endcase
end
end
end else begin
if(erase_trigger) begin
erase_trigger <= 0;
erase_mask <= 'hFFFF;
end_addr <= start_addr;
erase_clk_div <= 1;
erasing <= 1;
end else if(erasing) begin
erase_clk_div <= erase_clk_div + 1'd1;
if(!erase_clk_div) begin
if(next_erase == end_addr) erasing <= 0;
else begin
fill_addr <= next_erase;
fill_data <= 0;
if(next_erase > 2) wr <= 1;
end
end
end
end
end
endmodule | 2 |
141,256 | data/full_repos/permissive/94358170/Apogee.sv | 94,358,170 | Apogee.sv | sv | 761 | 158 | [] | [] | [] | null | line:121 column:20: Illegal character "'" | null | 1: b'%Error: data/full_repos/permissive/94358170/Apogee.sv:155: Cannot find include file: build_id.v\n`include "build_id.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94358170,data/full_repos/permissive/94358170/build_id.v\n data/full_repos/permissive/94358170,data/full_repos/permissive/94358170/build_id.v.v\n data/full_repos/permissive/94358170,data/full_repos/permissive/94358170/build_id.v.sv\n build_id.v\n build_id.v.v\n build_id.v.sv\n obj_dir/build_id.v\n obj_dir/build_id.v.v\n obj_dir/build_id.v.sv\n%Error: data/full_repos/permissive/94358170/Apogee.sv:169: Define or directive not defined: \'`BUILD_DATE\'\n "V,v",`BUILD_DATE\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94358170/Apogee.sv:170: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n};\n^\n%Error: Exiting due to 3 error(s)\n' | 311,051 | module | module dpram
(
input clock,
input [15:0] address_a,
input [7:0] data_a,
input wren_a,
output [7:0] q_a,
input [15:0] address_b,
input [7:0] data_b,
input wren_b,
output [7:0] q_b
);
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.numwords_b = 65536,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 16,
altsyncram_component.widthad_b = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule | module dpram
(
input clock,
input [15:0] address_a,
input [7:0] data_a,
input wren_a,
output [7:0] q_a,
input [15:0] address_b,
input [7:0] data_b,
input wren_b,
output [7:0] q_b
); |
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.numwords_b = 65536,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 16,
altsyncram_component.widthad_b = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule | 2 |
141,261 | data/full_repos/permissive/94367211/rtl/keyboard.sv | 94,367,211 | keyboard.sv | sv | 171 | 111 | [] | [] | [] | null | line:26: before: "=" | data/verilator_xmls/7f4b11c0-28ec-4c80-98de-e6f10363dcdd.xml | null | 311,102 | module | module keyboard
(
input clk,
input reset,
input [10:0] ps2_key,
input [7:0] addr,
output reg[7:0] odata,
output [2:0] shift,
output reg[2:0] reset_key = 0
);
assign shift = keystate[8][2:0];
reg [2:0] c;
reg [3:0] r;
reg [7:0] keystate[10:0];
wire [7:0] kcode = {ps2_key[7:0]};
wire pressed = ps2_key[9];
always @(addr,keystate) begin
odata =
(keystate[0] & {8{addr[0]}})|
(keystate[1] & {8{addr[1]}})|
(keystate[2] & {8{addr[2]}})|
(keystate[3] & {8{addr[3]}})|
(keystate[4] & {8{addr[4]}})|
(keystate[5] & {8{addr[5]}})|
(keystate[6] & {8{addr[6]}})|
(keystate[7] & {8{addr[7]}});
end
always @(*) begin
case (kcode)
8'h0D: {c,r} = 7'h00;
8'h71: {c,r} = 7'h10;
8'h5A: {c,r} = 7'h20;
8'h66: {c,r} = 7'h30;
8'h6B: {c,r} = 7'h40;
8'h75: {c,r} = 7'h50;
8'h74: {c,r} = 7'h60;
8'h72: {c,r} = 7'h70;
8'h6C: {c,r} = 7'h01;
8'h7D: {c,r} = 7'h11;
8'h76: {c,r} = 7'h21;
8'h05: {c,r} = 7'h31;
8'h06: {c,r} = 7'h41;
8'h04: {c,r} = 7'h51;
8'h0C: {c,r} = 7'h61;
8'h03: {c,r} = 7'h71;
8'h0B: {c,r} = 7'h01;
8'h83: {c,r} = 7'h11;
8'h45: {c,r} = 7'h02;
8'h16: {c,r} = 7'h12;
8'h1E: {c,r} = 7'h22;
8'h26: {c,r} = 7'h32;
8'h25: {c,r} = 7'h42;
8'h2E: {c,r} = 7'h52;
8'h36: {c,r} = 7'h62;
8'h3D: {c,r} = 7'h72;
8'h3E: {c,r} = 7'h03;
8'h46: {c,r} = 7'h13;
8'h55: {c,r} = 7'h23;
8'h0E: {c,r} = 7'h33;
8'h41: {c,r} = 7'h43;
8'h4E: {c,r} = 7'h53;
8'h49: {c,r} = 7'h63;
8'h4A: {c,r} = 7'h73;
8'h4C: {c,r} = 7'h04;
8'h1C: {c,r} = 7'h14;
8'h32: {c,r} = 7'h24;
8'h21: {c,r} = 7'h34;
8'h23: {c,r} = 7'h44;
8'h24: {c,r} = 7'h54;
8'h2B: {c,r} = 7'h64;
8'h34: {c,r} = 7'h74;
8'h33: {c,r} = 7'h05;
8'h43: {c,r} = 7'h15;
8'h3B: {c,r} = 7'h25;
8'h42: {c,r} = 7'h35;
8'h4B: {c,r} = 7'h45;
8'h3A: {c,r} = 7'h55;
8'h31: {c,r} = 7'h65;
8'h44: {c,r} = 7'h75;
8'h4D: {c,r} = 7'h06;
8'h15: {c,r} = 7'h16;
8'h2D: {c,r} = 7'h26;
8'h1B: {c,r} = 7'h36;
8'h2C: {c,r} = 7'h46;
8'h3C: {c,r} = 7'h56;
8'h2A: {c,r} = 7'h66;
8'h1D: {c,r} = 7'h76;
8'h22: {c,r} = 7'h07;
8'h35: {c,r} = 7'h17;
8'h1A: {c,r} = 7'h27;
8'h54: {c,r} = 7'h37;
8'h52: {c,r} = 7'h47;
8'h5B: {c,r} = 7'h57;
8'h5D: {c,r} = 7'h67;
8'h29: {c,r} = 7'h77;
8'h12: {c,r} = 7'h08;
8'h59: {c,r} = 7'h08;
8'h14: {c,r} = 7'h18;
8'h11: {c,r} = 7'h28;
default: {c,r} = 7'h7F;
endcase
end
always @(posedge clk) begin
reg old_reset;
reg old_stb;
reg malt = 0;
reg mctrl = 0;
reg mshift = 0;
old_stb <= ps2_key[10];
old_reset <= reset;
if(!old_reset && reset) begin
keystate[0] <= 0;
keystate[1] <= 0;
keystate[2] <= 0;
keystate[3] <= 0;
keystate[4] <= 0;
keystate[5] <= 0;
keystate[6] <= 0;
keystate[7] <= 0;
keystate[8] <= 0;
keystate[9] <= 0;
keystate[10]<= 0;
end else begin
if (old_stb != ps2_key[10]) begin
if (kcode==8'h11) malt <= pressed;
if (kcode==8'h14) mctrl <= pressed;
if (kcode==8'h12) mshift <= pressed;
if (kcode==8'h59) mshift <= pressed;
if (kcode==8'h78) reset_key <= {(malt & pressed), (mshift & pressed), ((mctrl | mshift | malt) & pressed)};
if(r != 'hF) keystate[r][c] <= pressed;
end
end
end
endmodule | module keyboard
(
input clk,
input reset,
input [10:0] ps2_key,
input [7:0] addr,
output reg[7:0] odata,
output [2:0] shift,
output reg[2:0] reset_key = 0
); |
assign shift = keystate[8][2:0];
reg [2:0] c;
reg [3:0] r;
reg [7:0] keystate[10:0];
wire [7:0] kcode = {ps2_key[7:0]};
wire pressed = ps2_key[9];
always @(addr,keystate) begin
odata =
(keystate[0] & {8{addr[0]}})|
(keystate[1] & {8{addr[1]}})|
(keystate[2] & {8{addr[2]}})|
(keystate[3] & {8{addr[3]}})|
(keystate[4] & {8{addr[4]}})|
(keystate[5] & {8{addr[5]}})|
(keystate[6] & {8{addr[6]}})|
(keystate[7] & {8{addr[7]}});
end
always @(*) begin
case (kcode)
8'h0D: {c,r} = 7'h00;
8'h71: {c,r} = 7'h10;
8'h5A: {c,r} = 7'h20;
8'h66: {c,r} = 7'h30;
8'h6B: {c,r} = 7'h40;
8'h75: {c,r} = 7'h50;
8'h74: {c,r} = 7'h60;
8'h72: {c,r} = 7'h70;
8'h6C: {c,r} = 7'h01;
8'h7D: {c,r} = 7'h11;
8'h76: {c,r} = 7'h21;
8'h05: {c,r} = 7'h31;
8'h06: {c,r} = 7'h41;
8'h04: {c,r} = 7'h51;
8'h0C: {c,r} = 7'h61;
8'h03: {c,r} = 7'h71;
8'h0B: {c,r} = 7'h01;
8'h83: {c,r} = 7'h11;
8'h45: {c,r} = 7'h02;
8'h16: {c,r} = 7'h12;
8'h1E: {c,r} = 7'h22;
8'h26: {c,r} = 7'h32;
8'h25: {c,r} = 7'h42;
8'h2E: {c,r} = 7'h52;
8'h36: {c,r} = 7'h62;
8'h3D: {c,r} = 7'h72;
8'h3E: {c,r} = 7'h03;
8'h46: {c,r} = 7'h13;
8'h55: {c,r} = 7'h23;
8'h0E: {c,r} = 7'h33;
8'h41: {c,r} = 7'h43;
8'h4E: {c,r} = 7'h53;
8'h49: {c,r} = 7'h63;
8'h4A: {c,r} = 7'h73;
8'h4C: {c,r} = 7'h04;
8'h1C: {c,r} = 7'h14;
8'h32: {c,r} = 7'h24;
8'h21: {c,r} = 7'h34;
8'h23: {c,r} = 7'h44;
8'h24: {c,r} = 7'h54;
8'h2B: {c,r} = 7'h64;
8'h34: {c,r} = 7'h74;
8'h33: {c,r} = 7'h05;
8'h43: {c,r} = 7'h15;
8'h3B: {c,r} = 7'h25;
8'h42: {c,r} = 7'h35;
8'h4B: {c,r} = 7'h45;
8'h3A: {c,r} = 7'h55;
8'h31: {c,r} = 7'h65;
8'h44: {c,r} = 7'h75;
8'h4D: {c,r} = 7'h06;
8'h15: {c,r} = 7'h16;
8'h2D: {c,r} = 7'h26;
8'h1B: {c,r} = 7'h36;
8'h2C: {c,r} = 7'h46;
8'h3C: {c,r} = 7'h56;
8'h2A: {c,r} = 7'h66;
8'h1D: {c,r} = 7'h76;
8'h22: {c,r} = 7'h07;
8'h35: {c,r} = 7'h17;
8'h1A: {c,r} = 7'h27;
8'h54: {c,r} = 7'h37;
8'h52: {c,r} = 7'h47;
8'h5B: {c,r} = 7'h57;
8'h5D: {c,r} = 7'h67;
8'h29: {c,r} = 7'h77;
8'h12: {c,r} = 7'h08;
8'h59: {c,r} = 7'h08;
8'h14: {c,r} = 7'h18;
8'h11: {c,r} = 7'h28;
default: {c,r} = 7'h7F;
endcase
end
always @(posedge clk) begin
reg old_reset;
reg old_stb;
reg malt = 0;
reg mctrl = 0;
reg mshift = 0;
old_stb <= ps2_key[10];
old_reset <= reset;
if(!old_reset && reset) begin
keystate[0] <= 0;
keystate[1] <= 0;
keystate[2] <= 0;
keystate[3] <= 0;
keystate[4] <= 0;
keystate[5] <= 0;
keystate[6] <= 0;
keystate[7] <= 0;
keystate[8] <= 0;
keystate[9] <= 0;
keystate[10]<= 0;
end else begin
if (old_stb != ps2_key[10]) begin
if (kcode==8'h11) malt <= pressed;
if (kcode==8'h14) mctrl <= pressed;
if (kcode==8'h12) mshift <= pressed;
if (kcode==8'h59) mshift <= pressed;
if (kcode==8'h78) reset_key <= {(malt & pressed), (mshift & pressed), ((mctrl | mshift | malt) & pressed)};
if(r != 'hF) keystate[r][c] <= pressed;
end
end
end
endmodule | 4 |
141,263 | data/full_repos/permissive/94388515/Gato.v | 94,388,515 | Gato.v | v | 359 | 232 | [] | [] | [] | [(6, 358)] | null | null | 1: b"%Error: data/full_repos/permissive/94388515/Gato.v:45: Cannot find file containing module: 'Teclado'\n Teclado keyboard\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/94388515,data/full_repos/permissive/94388515/Teclado\n data/full_repos/permissive/94388515,data/full_repos/permissive/94388515/Teclado.v\n data/full_repos/permissive/94388515,data/full_repos/permissive/94388515/Teclado.sv\n Teclado\n Teclado.v\n Teclado.sv\n obj_dir/Teclado\n obj_dir/Teclado.v\n obj_dir/Teclado.sv\n%Error: data/full_repos/permissive/94388515/Gato.v:55: Cannot find file containing module: 'top'\n top display\n ^~~\n%Error: Exiting due to 2 error(s)\n" | 311,145 | module | module Gato(
input clk,
input reset,
output [3:0] row,
input [3:0] col,
output [2:0]r,
output [2:0]g,
output [1:0]b,
output vSync,
output hSync,
output listening,
output p1
);
reg [2:0]previousGameState=0;
reg [2:0]gameState=0;
reg [8:0]player1=0;
reg [8:0]player2=0;
reg sleepEnable=0;
wire [2:0] wDisplayState;
wire [8:0] wDisplayP1;
wire [8:0] wDisplayP2;
assign wDisplayState=gameState;
assign wDisplayP1 = player1;
assign wDisplayP2 = player2;
assign p1 = wDisplayP1[0];
wire wKbIsReady;
wire [3:0]wKbKey;
Teclado keyboard
(
.clk(clk),
.col(col),
.isReady(wKbIsReady),
.row(row),
.key(wKbKey)
);
assign listening = ~wKbIsReady;
top display
(
.clk(clk),
.gState(wDisplayState),
.P1(wDisplayP1),
.P2(wDisplayP2),
.r(r),
.g(g),
.b(b),
.vSync(vSync),
.hSync(hSync)
);
reg [26:0] mainDelayCounter = 0;
reg mainDelay;
always @(posedge clk)begin
if (mainDelayCounter == 2500000)
begin
mainDelayCounter <= 0;
mainDelay <= mainDelay +1;
end
else
mainDelayCounter<=mainDelayCounter + 1;
end
reg [50:0] displayCounter = 0;
reg displayDelay;
always @(posedge clk)begin
if(sleepEnable)begin
if (displayCounter == 45000000)
begin
displayCounter <= 0;
displayDelay <= displayDelay +1;
end
else
displayCounter<=displayCounter + 1;
end
else
displayDelay <= 0;
end
always@(posedge mainDelay) begin
if(reset) begin
gameState <= 0;
previousGameState <= 0;
player1 <= 0;
player2 <= 0;
end
case(gameState)
0:begin
if((player1[0]|player2[0])&&(player1[1]|player2[1])&&(player1[2]|player2[2])&&(player1[3]|player2[3])&&(player1[4]|player2[4])&&(player1[5]|player2[5])&&(player1[6]|player2[6])&&(player1[7]|player2[7]&&(player1[8]|player2[8])))
gameState<=5;
else if(~wKbIsReady) begin
gameState<=1;
previousGameState<=0;
case(wKbKey)
1:begin
if(player1[0] != 1 && player2[0] != 1)
begin
player1[0] <= 1;
if((player1[1]&&player1[2]) | (player1[4]&&player1[8]) | (player1[3]&&player1[6]))
gameState<=2;
end
else
gameState<=4;
end
2:begin
if(player1[1] != 1 && player2[1] != 1)
begin
player1[1] <= 1;
if((player1[0]&&player1[2]) | (player1[4]&&player1[7]))
gameState<=2;
end
else
gameState<=4;
end
3:begin
if(player1[2] != 1 && player2[2] != 1)
begin
player1[2] <= 1;
if((player1[0]&&player1[1]) | (player1[6]&&player1[4]) | (player1[5]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
4:begin
if(player1[3] != 1 && player2[3] != 1)
begin
player1[3] <= 1;
if((player1[0]&&player1[6]) | (player1[4]&&player1[5]))
gameState<=2;
end
else
gameState<=4;
end
5:begin
if(player1[4] != 1 && player2[4] != 1)
begin
player1[4] <= 1;
if((player1[0]&&player1[8]) | (player1[1]&&player1[7]) | (player1[6]&&player1[2]) | (player1[3]&&player1[5]))
gameState<=2;
end
else
gameState<=4;
end
6:begin
if(player1[5] != 1 && player2[5] != 1)
begin
player1[5] <= 1;
if((player1[4]&&player1[3]) | (player1[2]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
7:begin
if(player1[6] != 1 && player2[6] != 1)
begin
player1[6] <= 1;
if((player1[0]&&player1[3]) | (player1[2]&&player1[4]) | (player1[7]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
8:begin
if(player1[7] != 1 && player2[7] != 1)
begin
player1[7] <= 1;
if((player1[4]&&player1[1]) | (player1[6]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
9:begin
if(player1[8] != 1 && player2[8] != 1)
begin
player1[8] <= 1;
if((player1[0]&&player1[4]) | (player1[2]&&player1[5]) | (player1[7]&&player1[6]))
gameState<=2;
end
else
gameState<=4;
end
default: gameState<=4;
endcase
end
end
1:begin
if((player1[0]|player2[0])&&(player1[1]|player2[1])&&(player1[2]|player2[2])&&(player1[3]|player2[3])&&(player1[4]|player2[4])&&(player1[5]|player2[5])&&(player1[6]|player2[6])&&(player1[7]|player2[7]&&(player1[8]|player2[8])))
gameState<=5;
else if(~wKbIsReady) begin
gameState<=0;
previousGameState<=1;
case(wKbKey)
1:begin
if(player1[0] != 1 && player2[0] != 1)
begin
player2[0] <= 1;
if((player2[1]&&player2[2]) | (player2[4]&&player2[8]) | (player2[3]&&player2[6]))
gameState<=3;
end
else
gameState<=4;
end
2:begin
if(player1[1] != 1 && player2[1] != 1)
begin
player2[1] <= 1;
if((player2[0]&&player2[2]) | (player2[4]&&player2[7]))
gameState<=3;
end
else
gameState<=4;
end
3:begin
if(player1[2] != 1 && player2[2] != 1)
begin
player2[2] <= 1;
if((player2[0]&&player2[1]) | (player2[6]&&player2[4]) | (player2[5]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
4:begin
if(player1[3] != 1 && player2[3] != 1)
begin
player2[3] <= 1;
if((player2[0]&&player2[6]) | (player2[4]&&player2[5]))
gameState<=3;
end
else
gameState<=4;
end
5:begin
if(player1[4] != 1 && player2[4] != 1)
begin
player2[4] <= 1;
if((player2[0]&&player2[8]) | (player2[1]&&player2[7]) | (player2[6]&&player2[2]) | (player2[3]&&player2[5]))
gameState<=3;
end
else
gameState<=4;
end
6:begin
if(player1[5] != 1 && player2[5] != 1)
begin
player2[5] <= 1;
if((player2[4]&&player2[3]) | (player2[2]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
7:begin
if(player1[6] != 1 && player2[6] != 1)
begin
player2[6] <= 1;
if((player2[0]&&player2[3]) | (player2[2]&&player2[4]) | (player2[7]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
8:begin
if(player1[7] != 1 && player2[7] != 1)
begin
player2[7] <= 1;
if((player2[4]&&player2[1]) | (player2[6]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
9:begin
if(player1[8] != 1 && player2[8] != 1)
begin
player2[8] <= 1;
if((player2[0]&&player2[4]) | (player2[2]&&player2[5]) | (player2[7]&&player2[6]))
gameState<=3;
end
else
gameState<=4;
end
default: gameState<=4;
endcase
end
end
2:begin
player1 <= 0;
player2 <= 0;
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= 0;
end
end
3:begin
player1 <= 0;
player2 <= 0;
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= 0;
end
end
4:begin
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= previousGameState;
end
end
5:begin
player1 <= 0;
player2 <= 0;
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= 0;
end
end
endcase
end
endmodule | module Gato(
input clk,
input reset,
output [3:0] row,
input [3:0] col,
output [2:0]r,
output [2:0]g,
output [1:0]b,
output vSync,
output hSync,
output listening,
output p1
); |
reg [2:0]previousGameState=0;
reg [2:0]gameState=0;
reg [8:0]player1=0;
reg [8:0]player2=0;
reg sleepEnable=0;
wire [2:0] wDisplayState;
wire [8:0] wDisplayP1;
wire [8:0] wDisplayP2;
assign wDisplayState=gameState;
assign wDisplayP1 = player1;
assign wDisplayP2 = player2;
assign p1 = wDisplayP1[0];
wire wKbIsReady;
wire [3:0]wKbKey;
Teclado keyboard
(
.clk(clk),
.col(col),
.isReady(wKbIsReady),
.row(row),
.key(wKbKey)
);
assign listening = ~wKbIsReady;
top display
(
.clk(clk),
.gState(wDisplayState),
.P1(wDisplayP1),
.P2(wDisplayP2),
.r(r),
.g(g),
.b(b),
.vSync(vSync),
.hSync(hSync)
);
reg [26:0] mainDelayCounter = 0;
reg mainDelay;
always @(posedge clk)begin
if (mainDelayCounter == 2500000)
begin
mainDelayCounter <= 0;
mainDelay <= mainDelay +1;
end
else
mainDelayCounter<=mainDelayCounter + 1;
end
reg [50:0] displayCounter = 0;
reg displayDelay;
always @(posedge clk)begin
if(sleepEnable)begin
if (displayCounter == 45000000)
begin
displayCounter <= 0;
displayDelay <= displayDelay +1;
end
else
displayCounter<=displayCounter + 1;
end
else
displayDelay <= 0;
end
always@(posedge mainDelay) begin
if(reset) begin
gameState <= 0;
previousGameState <= 0;
player1 <= 0;
player2 <= 0;
end
case(gameState)
0:begin
if((player1[0]|player2[0])&&(player1[1]|player2[1])&&(player1[2]|player2[2])&&(player1[3]|player2[3])&&(player1[4]|player2[4])&&(player1[5]|player2[5])&&(player1[6]|player2[6])&&(player1[7]|player2[7]&&(player1[8]|player2[8])))
gameState<=5;
else if(~wKbIsReady) begin
gameState<=1;
previousGameState<=0;
case(wKbKey)
1:begin
if(player1[0] != 1 && player2[0] != 1)
begin
player1[0] <= 1;
if((player1[1]&&player1[2]) | (player1[4]&&player1[8]) | (player1[3]&&player1[6]))
gameState<=2;
end
else
gameState<=4;
end
2:begin
if(player1[1] != 1 && player2[1] != 1)
begin
player1[1] <= 1;
if((player1[0]&&player1[2]) | (player1[4]&&player1[7]))
gameState<=2;
end
else
gameState<=4;
end
3:begin
if(player1[2] != 1 && player2[2] != 1)
begin
player1[2] <= 1;
if((player1[0]&&player1[1]) | (player1[6]&&player1[4]) | (player1[5]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
4:begin
if(player1[3] != 1 && player2[3] != 1)
begin
player1[3] <= 1;
if((player1[0]&&player1[6]) | (player1[4]&&player1[5]))
gameState<=2;
end
else
gameState<=4;
end
5:begin
if(player1[4] != 1 && player2[4] != 1)
begin
player1[4] <= 1;
if((player1[0]&&player1[8]) | (player1[1]&&player1[7]) | (player1[6]&&player1[2]) | (player1[3]&&player1[5]))
gameState<=2;
end
else
gameState<=4;
end
6:begin
if(player1[5] != 1 && player2[5] != 1)
begin
player1[5] <= 1;
if((player1[4]&&player1[3]) | (player1[2]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
7:begin
if(player1[6] != 1 && player2[6] != 1)
begin
player1[6] <= 1;
if((player1[0]&&player1[3]) | (player1[2]&&player1[4]) | (player1[7]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
8:begin
if(player1[7] != 1 && player2[7] != 1)
begin
player1[7] <= 1;
if((player1[4]&&player1[1]) | (player1[6]&&player1[8]))
gameState<=2;
end
else
gameState<=4;
end
9:begin
if(player1[8] != 1 && player2[8] != 1)
begin
player1[8] <= 1;
if((player1[0]&&player1[4]) | (player1[2]&&player1[5]) | (player1[7]&&player1[6]))
gameState<=2;
end
else
gameState<=4;
end
default: gameState<=4;
endcase
end
end
1:begin
if((player1[0]|player2[0])&&(player1[1]|player2[1])&&(player1[2]|player2[2])&&(player1[3]|player2[3])&&(player1[4]|player2[4])&&(player1[5]|player2[5])&&(player1[6]|player2[6])&&(player1[7]|player2[7]&&(player1[8]|player2[8])))
gameState<=5;
else if(~wKbIsReady) begin
gameState<=0;
previousGameState<=1;
case(wKbKey)
1:begin
if(player1[0] != 1 && player2[0] != 1)
begin
player2[0] <= 1;
if((player2[1]&&player2[2]) | (player2[4]&&player2[8]) | (player2[3]&&player2[6]))
gameState<=3;
end
else
gameState<=4;
end
2:begin
if(player1[1] != 1 && player2[1] != 1)
begin
player2[1] <= 1;
if((player2[0]&&player2[2]) | (player2[4]&&player2[7]))
gameState<=3;
end
else
gameState<=4;
end
3:begin
if(player1[2] != 1 && player2[2] != 1)
begin
player2[2] <= 1;
if((player2[0]&&player2[1]) | (player2[6]&&player2[4]) | (player2[5]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
4:begin
if(player1[3] != 1 && player2[3] != 1)
begin
player2[3] <= 1;
if((player2[0]&&player2[6]) | (player2[4]&&player2[5]))
gameState<=3;
end
else
gameState<=4;
end
5:begin
if(player1[4] != 1 && player2[4] != 1)
begin
player2[4] <= 1;
if((player2[0]&&player2[8]) | (player2[1]&&player2[7]) | (player2[6]&&player2[2]) | (player2[3]&&player2[5]))
gameState<=3;
end
else
gameState<=4;
end
6:begin
if(player1[5] != 1 && player2[5] != 1)
begin
player2[5] <= 1;
if((player2[4]&&player2[3]) | (player2[2]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
7:begin
if(player1[6] != 1 && player2[6] != 1)
begin
player2[6] <= 1;
if((player2[0]&&player2[3]) | (player2[2]&&player2[4]) | (player2[7]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
8:begin
if(player1[7] != 1 && player2[7] != 1)
begin
player2[7] <= 1;
if((player2[4]&&player2[1]) | (player2[6]&&player2[8]))
gameState<=3;
end
else
gameState<=4;
end
9:begin
if(player1[8] != 1 && player2[8] != 1)
begin
player2[8] <= 1;
if((player2[0]&&player2[4]) | (player2[2]&&player2[5]) | (player2[7]&&player2[6]))
gameState<=3;
end
else
gameState<=4;
end
default: gameState<=4;
endcase
end
end
2:begin
player1 <= 0;
player2 <= 0;
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= 0;
end
end
3:begin
player1 <= 0;
player2 <= 0;
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= 0;
end
end
4:begin
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= previousGameState;
end
end
5:begin
player1 <= 0;
player2 <= 0;
sleepEnable <= 1;
if(displayDelay == 1) begin
sleepEnable <= 0;
gameState <= 0;
end
end
endcase
end
endmodule | 0 |
141,264 | data/full_repos/permissive/94388515/Teclado.v | 94,388,515 | Teclado.v | v | 76 | 83 | [] | [] | [] | [(6, 75)] | null | data/verilator_xmls/fe85db4a-3d07-496b-9e95-d4296f373143.xml | null | 311,146 | module | module Teclado(
input clk,
input [3:0] col,
output reg isReady,
output reg [3:0] row,
output reg [3:0] key
);
reg [1:0] scan;
reg [26:0] counter;
reg delay;
always @(posedge clk)begin
if (counter == 2500000)
begin
counter <= 0;
delay <= delay +1;
end
else
counter<=counter + 1;
end
always @(posedge delay) begin
scan = scan + 1;
isReady = 1;
case(scan)
0:row <= 4'b1000;
1:row <= 4'b0100;
2:row <= 4'b0010;
3:row <= 4'b0001;
default: row <= 0;
endcase
if(col[3] || col[2] || col[1] || col[0])begin
isReady = 0;
if(row == 4'b1000)
case(col)
'b1000: key <= 'd1;
'b0100: key <= 'd2;
'b0010: key <= 'd3;
'b0001: key <= 'd10;
endcase
if(row == 4'b0100)
case(col)
'b1000: key <= 'd4;
'b0100: key <= 'd5;
'b0010: key <= 'd6;
'b0001: key <= 'd11;
endcase
if(row == 4'b0010)
case(col)
'b1000: key <= 'd7;
'b0100: key <= 'd8;
'b0010: key <= 'd9;
'b0001: key <= 'd12;
endcase
if(row == 4'b0001)
case(col)
'b1000: key <= 'd15;
'b0100: key <= 'd0;
'b0010: key <= 'd14;
'b0001: key <= 'd13;
endcase
end
end
endmodule | module Teclado(
input clk,
input [3:0] col,
output reg isReady,
output reg [3:0] row,
output reg [3:0] key
); |
reg [1:0] scan;
reg [26:0] counter;
reg delay;
always @(posedge clk)begin
if (counter == 2500000)
begin
counter <= 0;
delay <= delay +1;
end
else
counter<=counter + 1;
end
always @(posedge delay) begin
scan = scan + 1;
isReady = 1;
case(scan)
0:row <= 4'b1000;
1:row <= 4'b0100;
2:row <= 4'b0010;
3:row <= 4'b0001;
default: row <= 0;
endcase
if(col[3] || col[2] || col[1] || col[0])begin
isReady = 0;
if(row == 4'b1000)
case(col)
'b1000: key <= 'd1;
'b0100: key <= 'd2;
'b0010: key <= 'd3;
'b0001: key <= 'd10;
endcase
if(row == 4'b0100)
case(col)
'b1000: key <= 'd4;
'b0100: key <= 'd5;
'b0010: key <= 'd6;
'b0001: key <= 'd11;
endcase
if(row == 4'b0010)
case(col)
'b1000: key <= 'd7;
'b0100: key <= 'd8;
'b0010: key <= 'd9;
'b0001: key <= 'd12;
endcase
if(row == 4'b0001)
case(col)
'b1000: key <= 'd15;
'b0100: key <= 'd0;
'b0010: key <= 'd14;
'b0001: key <= 'd13;
endcase
end
end
endmodule | 0 |
141,265 | data/full_repos/permissive/94388515/top.v | 94,388,515 | top.v | v | 323 | 242 | [] | [] | [] | [(6, 322)] | null | null | 1: b"%Error: data/full_repos/permissive/94388515/top.v:27: Cannot find file containing module: 'VGA_ctrler'\n VGA_ctrler vga\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94388515,data/full_repos/permissive/94388515/VGA_ctrler\n data/full_repos/permissive/94388515,data/full_repos/permissive/94388515/VGA_ctrler.v\n data/full_repos/permissive/94388515,data/full_repos/permissive/94388515/VGA_ctrler.sv\n VGA_ctrler\n VGA_ctrler.v\n VGA_ctrler.sv\n obj_dir/VGA_ctrler\n obj_dir/VGA_ctrler.v\n obj_dir/VGA_ctrler.sv\n%Error: Exiting due to 1 error(s)\n" | 311,147 | module | module top(
input clk,
input [2:0] gState,
input [8:0] P1,
input [8:0] P2,
output [2:0] r,
output [2:0] g,
output [1:0] b,
output vSync,
output hSync
);
reg [3:0] cubo;
wire [9:0] x;
wire [9:0] y;
reg [2:0] iR = 0;
reg [2:0] iG = 0;
reg [1:0] iB = 0;
VGA_ctrler vga
(
.clk_50(clk),
.red_in(iR),
.green_in(iG),
.blue_in(iB),
.pixel_column(x),
.pixel_row(y),
.red_out(r),
.green_out(g),
.blue_out(b),
.horiz_sync_out(hSync),
.vert_sync_out(vSync)
);
always@(posedge clk) begin
iR <= 'b000;
iG <= 'b111;
iB <= 'b11;
if(x < 'd50) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(x > 'd590) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(y < 'd50) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(y > 'd430) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(x>'d223 && x<'d233 && (y>'d50 && y<'d430))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(x>'d403 && x<'d413 && (y>'d50 && y<'d430))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(y>'d170 && y<'d180 && (x>'d50 && x<'d590))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(y>'d300 && y<'d310 && (x>'d50 && x<'d590))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(x>'d50 && x<'d223 && (y>'d50 && y<'d170))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 0;
end
else if(x>'d233 && x<'d403 && (y>'d50 && y<'d170))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 1;
end
else if(x>'d413 && x<'d586 && (y>'d50 && y<'d170))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 2;
end
else if(x>'d50 && x<'d223 && (y>'d180 && y<'d300))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 3;
end
else if(x>'d233 && x<'d403 && (y>'d180 && y<'d300))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 4;
end
else if(x>'d413 && x<'d586 && (y>'d180 && y<'d300))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 5;
end
else if(x>'d50 && x<'d223 && (y>'d310 && y<'d430))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 6;
end
else if(x>'d233 && x<'d403 && (y>'d310 && y<'d430))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 7;
end
else if(x>'d413 && x<'d586 && (y>'d310 && y<'d430))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 8;
end
else
cubo<= 9;
if(P1[cubo]==1)begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b11;
end
if(P2[cubo]==1)begin
iR <= 'b000;
iG <= 'b111;
iB <= 'b00;
end
if( gState== 'd2 || gState =='d3)begin
if((x>'d5 &&x<'d20 && y>'d5 && y<'d40) || (x>='d20 && x<'d40 && y>'d5 && y<'d25))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d100 && x<'d140 && y>='d30 && y<='d40) || (x>='d100 && x<'d109 && y>='d5 && y<='d40) || (x>='d117 && x<'d125 && y>='d5 && y<='d40) ||(x>='d134 && x<'d142 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if(x>='d150 && x<'d165 && y>='d5 && y<='d40 )begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d170 && x<'d210 && y>='d5 && y<='d15) || (x>='d170 && x<'d180 && y>='d5 && y<='d40) || (x>='d200 && x<'d210 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d220 && x<'d260 && y>='d5 && y<='d10) || (x>='d220 && x<'d260 && y>='d20 && y<='d25) || (x>='d220 && x<'d260 && y>='d35 && y<='d40) || (x>='d220 && x<'d225 && y>='d10 && y<='d20) || (x>='d255 && x<'d260 && y>='d25 && y<='d35))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if(gState == 'd2)begin
if((x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d58 && x<'d73 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
if(gState == 'd3)begin
if((x>='d45 && x<'d85 && y>='d5 && y<='d15) || (x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d45 && x<'d65 && y>='d20 && y<='d40) || (x>='d65 && x<'d85 && y>='d5 && y<='d20))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
end
else if(gState=='d0 ||gState=='d1)begin
if((x>'d5 &&x<'d20 && y>'d5 && y<'d40) || (x>='d20 && x<'d40 && y>'d5 && y<'d25))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d100 && x<'d140 && y>='d5 && y<='d20) || (x>='d100 && x<'d109 && y>='d5 && y<='d40) || (x>='d117 && x<'d125 && y>='d5 && y<='d40) ||(x>='d134 && x<'d142 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d150 && x<'d190 && y>='d35 && y<='d40) ||(x>='d150 && x<'d190 && y>='d5 && y<='d15) ||(x>='d150 && x<'d160 && y>='d5 && y<='d40) ||(x>='d180 && x<'d190 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d200 && x<'d240 && y>='d35 && y<='d40) ||(x>='d200 && x<'d210 && y>='d5 && y<='d40) ||(x>='d230 && x<'d240 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d250 && x<'d290 && y>='d35 && y<='d40) ||(x>='d250 && x<'d290 && y>='d5 && y<='d15)||(x>='d250 && x<'d290 && y>='d20 && y<='d25) ||(x>='d250 && x<'d260 && y>='d5 && y<='d40) )begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d300 && x<'d340 && y>='d5 && y<='d10) || (x>='d300 && x<'d340 && y>='d20 && y<='d25) || (x>='d300 && x<'d340 && y>='d35 && y<='d40) || (x>='d300 && x<'d305 && y>='d10 && y<='d20) || (x>='d335 && x<'d340 && y>='d25 && y<='d35))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if(gState == 'd0)begin
if((x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d58 && x<'d73 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
if(gState == 'd1)begin
if((x>='d45 && x<'d85 && y>='d5 && y<='d15) || (x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d45 && x<'d65 && y>='d20 && y<='d40) || (x>='d65 && x<'d85 && y>='d5 && y<='d20))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
end
else if(gState == 'd4)begin
if ((x>='d60 && x<'d100 && y>='d35 && y<='d40) ||(x>='d60 && x<'d100 && y>='d5 && y<='d15)||(x>='d60 && x<'d100 && y>='d20 && y<='d25) ||(x>='d60 && x<'d70 && y>='d5 && y<='d40) )begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d110 &&x<'d125 && y>'d5 && y<'d40) || (x>='d125 && x<'d150 && y>'d5 && y<'d25)|| (x>='d125 && x<'d138 && y>'d25 && y<'d32) ||(x>='d138 && x<'d150 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d160 &&x<'d175 && y>'d5 && y<'d40) || (x>='d175 && x<'d200 && y>'d5 && y<'d25) || (x>='d175 && x<'d188 && y>'d25 && y<'d32) ||(x>='d188 && x<'d200 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d210 && x<'d250 && y>='d35 && y<='d40) ||(x>='d210 && x<'d250 && y>='d5 && y<='d15) ||(x>='d210 && x<'d220 && y>='d5 && y<='d40) ||(x>='d240 && x<'d250 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d260 &&x<'d275 && y>'d5 && y<'d40) || (x>='d275 && x<'d300 && y>'d5 && y<'d25) || (x>='d275 && x<'d288 && y>'d25 && y<'d32) ||(x>='d288 && x<'d300 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
else if(gState == 'd5)begin
if((x>='d125 &&x<='d140 && y>'d5 && y<'d40) || (x>='d100 && x<='d125 && y>'d15 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d150 &&x<'d165 && y>'d5 && y<'d40) || (x>='d165 && x<'d190 && y>'d5 && y<'d25)|| (x>='d165 && x<'d178 && y>'d25 && y<'d32) ||(x>='d188 && x<'d190 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d200 && x<'d240 && y>='d20 && y<='d30) ||(x>='d200 && x<'d240 && y>='d5 && y<='d15) ||(x>='d200 && x<'d210 && y>='d5 && y<='d40) ||(x>='d230 && x<'d240 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d250 && x<'d290 && y>='d30 && y<='d40) || (x>='d250 && x<'d259 && y>='d5 && y<='d40) || (x>='d267 && x<'d275 && y>='d5 && y<='d40) ||(x>='d284 && x<'d292 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
end
endmodule | module top(
input clk,
input [2:0] gState,
input [8:0] P1,
input [8:0] P2,
output [2:0] r,
output [2:0] g,
output [1:0] b,
output vSync,
output hSync
); |
reg [3:0] cubo;
wire [9:0] x;
wire [9:0] y;
reg [2:0] iR = 0;
reg [2:0] iG = 0;
reg [1:0] iB = 0;
VGA_ctrler vga
(
.clk_50(clk),
.red_in(iR),
.green_in(iG),
.blue_in(iB),
.pixel_column(x),
.pixel_row(y),
.red_out(r),
.green_out(g),
.blue_out(b),
.horiz_sync_out(hSync),
.vert_sync_out(vSync)
);
always@(posedge clk) begin
iR <= 'b000;
iG <= 'b111;
iB <= 'b11;
if(x < 'd50) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(x > 'd590) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(y < 'd50) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(y > 'd430) begin
iR <= 'b111;
iG <= 'b000;
iB <= 'b00;
end
if(x>'d223 && x<'d233 && (y>'d50 && y<'d430))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(x>'d403 && x<'d413 && (y>'d50 && y<'d430))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(y>'d170 && y<'d180 && (x>'d50 && x<'d590))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(y>'d300 && y<'d310 && (x>'d50 && x<'d590))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
cubo <= 9;
end
if(x>'d50 && x<'d223 && (y>'d50 && y<'d170))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 0;
end
else if(x>'d233 && x<'d403 && (y>'d50 && y<'d170))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 1;
end
else if(x>'d413 && x<'d586 && (y>'d50 && y<'d170))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 2;
end
else if(x>'d50 && x<'d223 && (y>'d180 && y<'d300))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 3;
end
else if(x>'d233 && x<'d403 && (y>'d180 && y<'d300))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 4;
end
else if(x>'d413 && x<'d586 && (y>'d180 && y<'d300))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 5;
end
else if(x>'d50 && x<'d223 && (y>'d310 && y<'d430))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 6;
end
else if(x>'d233 && x<'d403 && (y>'d310 && y<'d430))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 7;
end
else if(x>'d413 && x<'d586 && (y>'d310 && y<'d430))begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b00;
cubo <= 8;
end
else
cubo<= 9;
if(P1[cubo]==1)begin
iR <= 'b000;
iG <= 'b000;
iB <= 'b11;
end
if(P2[cubo]==1)begin
iR <= 'b000;
iG <= 'b111;
iB <= 'b00;
end
if( gState== 'd2 || gState =='d3)begin
if((x>'d5 &&x<'d20 && y>'d5 && y<'d40) || (x>='d20 && x<'d40 && y>'d5 && y<'d25))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d100 && x<'d140 && y>='d30 && y<='d40) || (x>='d100 && x<'d109 && y>='d5 && y<='d40) || (x>='d117 && x<'d125 && y>='d5 && y<='d40) ||(x>='d134 && x<'d142 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if(x>='d150 && x<'d165 && y>='d5 && y<='d40 )begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d170 && x<'d210 && y>='d5 && y<='d15) || (x>='d170 && x<'d180 && y>='d5 && y<='d40) || (x>='d200 && x<'d210 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d220 && x<'d260 && y>='d5 && y<='d10) || (x>='d220 && x<'d260 && y>='d20 && y<='d25) || (x>='d220 && x<'d260 && y>='d35 && y<='d40) || (x>='d220 && x<'d225 && y>='d10 && y<='d20) || (x>='d255 && x<'d260 && y>='d25 && y<='d35))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if(gState == 'd2)begin
if((x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d58 && x<'d73 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
if(gState == 'd3)begin
if((x>='d45 && x<'d85 && y>='d5 && y<='d15) || (x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d45 && x<'d65 && y>='d20 && y<='d40) || (x>='d65 && x<'d85 && y>='d5 && y<='d20))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
end
else if(gState=='d0 ||gState=='d1)begin
if((x>'d5 &&x<'d20 && y>'d5 && y<'d40) || (x>='d20 && x<'d40 && y>'d5 && y<'d25))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d100 && x<'d140 && y>='d5 && y<='d20) || (x>='d100 && x<'d109 && y>='d5 && y<='d40) || (x>='d117 && x<'d125 && y>='d5 && y<='d40) ||(x>='d134 && x<'d142 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d150 && x<'d190 && y>='d35 && y<='d40) ||(x>='d150 && x<'d190 && y>='d5 && y<='d15) ||(x>='d150 && x<'d160 && y>='d5 && y<='d40) ||(x>='d180 && x<'d190 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d200 && x<'d240 && y>='d35 && y<='d40) ||(x>='d200 && x<'d210 && y>='d5 && y<='d40) ||(x>='d230 && x<'d240 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d250 && x<'d290 && y>='d35 && y<='d40) ||(x>='d250 && x<'d290 && y>='d5 && y<='d15)||(x>='d250 && x<'d290 && y>='d20 && y<='d25) ||(x>='d250 && x<'d260 && y>='d5 && y<='d40) )begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d300 && x<'d340 && y>='d5 && y<='d10) || (x>='d300 && x<'d340 && y>='d20 && y<='d25) || (x>='d300 && x<'d340 && y>='d35 && y<='d40) || (x>='d300 && x<'d305 && y>='d10 && y<='d20) || (x>='d335 && x<'d340 && y>='d25 && y<='d35))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if(gState == 'd0)begin
if((x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d58 && x<'d73 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
if(gState == 'd1)begin
if((x>='d45 && x<'d85 && y>='d5 && y<='d15) || (x>='d45 && x<'d85 && y>='d30 && y<='d40) || (x>='d45 && x<'d65 && y>='d20 && y<='d40) || (x>='d65 && x<'d85 && y>='d5 && y<='d20))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
end
else if(gState == 'd4)begin
if ((x>='d60 && x<'d100 && y>='d35 && y<='d40) ||(x>='d60 && x<'d100 && y>='d5 && y<='d15)||(x>='d60 && x<'d100 && y>='d20 && y<='d25) ||(x>='d60 && x<'d70 && y>='d5 && y<='d40) )begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d110 &&x<'d125 && y>'d5 && y<'d40) || (x>='d125 && x<'d150 && y>'d5 && y<'d25)|| (x>='d125 && x<'d138 && y>'d25 && y<'d32) ||(x>='d138 && x<'d150 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d160 &&x<'d175 && y>'d5 && y<'d40) || (x>='d175 && x<'d200 && y>'d5 && y<'d25) || (x>='d175 && x<'d188 && y>'d25 && y<'d32) ||(x>='d188 && x<'d200 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d210 && x<'d250 && y>='d35 && y<='d40) ||(x>='d210 && x<'d250 && y>='d5 && y<='d15) ||(x>='d210 && x<'d220 && y>='d5 && y<='d40) ||(x>='d240 && x<'d250 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d260 &&x<'d275 && y>'d5 && y<'d40) || (x>='d275 && x<'d300 && y>'d5 && y<'d25) || (x>='d275 && x<'d288 && y>'d25 && y<'d32) ||(x>='d288 && x<'d300 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
else if(gState == 'd5)begin
if((x>='d125 &&x<='d140 && y>'d5 && y<'d40) || (x>='d100 && x<='d125 && y>'d15 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>'d150 &&x<'d165 && y>'d5 && y<'d40) || (x>='d165 && x<'d190 && y>'d5 && y<'d25)|| (x>='d165 && x<'d178 && y>'d25 && y<'d32) ||(x>='d188 && x<'d190 && y>'d32 && y<'d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d200 && x<'d240 && y>='d20 && y<='d30) ||(x>='d200 && x<'d240 && y>='d5 && y<='d15) ||(x>='d200 && x<'d210 && y>='d5 && y<='d40) ||(x>='d230 && x<'d240 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
if((x>='d250 && x<'d290 && y>='d30 && y<='d40) || (x>='d250 && x<'d259 && y>='d5 && y<='d40) || (x>='d267 && x<'d275 && y>='d5 && y<='d40) ||(x>='d284 && x<'d292 && y>='d5 && y<='d40))begin
iR <= 'b111;
iG <= 'b111;
iB <= 'b11;
end
end
end
endmodule | 0 |
141,266 | data/full_repos/permissive/94422424/source/openmips_benchmark.v | 94,422,424 | openmips_benchmark.v | v | 27 | 50 | [] | [] | [] | null | line:8224: before: "$" | null | 1: b'%Error: data/full_repos/permissive/94422424/source/openmips_benchmark.v:1: Cannot find include file: machine/machine.v\n`include "machine/machine.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source,data/full_repos/permissive/94422424/machine/machine.v\n data/full_repos/permissive/94422424/source,data/full_repos/permissive/94422424/machine/machine.v.v\n data/full_repos/permissive/94422424/source,data/full_repos/permissive/94422424/machine/machine.v.sv\n machine/machine.v\n machine/machine.v.v\n machine/machine.v.sv\n obj_dir/machine/machine.v\n obj_dir/machine/machine.v.v\n obj_dir/machine/machine.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/94422424/source/openmips_benchmark.v:12: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/94422424/source/openmips_benchmark.v:16: Define or directive not defined: \'`ENABLE\'\n reset = `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/openmips_benchmark.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reset = `ENABLE;\n ^\n%Error: data/full_repos/permissive/94422424/source/openmips_benchmark.v:17: Define or directive not defined: \'`DISABLE\'\n #195 reset = `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/openmips_benchmark.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #195 reset = `DISABLE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/94422424/source/openmips_benchmark.v:17: Unsupported: Ignoring delay on this delayed statement.\n #195 reset = `DISABLE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/94422424/source/openmips_benchmark.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10000 $stop;\n ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 311,149 | module | module openmips_benchmark();
reg CLOCK_50;
reg reset;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
reset = `ENABLE;
#195 reset = `DISABLE;
#10000 $stop;
end
machine machine_instance(
.clock(CLOCK_50),
.reset(reset)
);
endmodule | module openmips_benchmark(); |
reg CLOCK_50;
reg reset;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
reset = `ENABLE;
#195 reset = `DISABLE;
#10000 $stop;
end
machine machine_instance(
.clock(CLOCK_50),
.reset(reset)
);
endmodule | 0 |
141,267 | data/full_repos/permissive/94422424/source/machine/machine.v | 94,422,424 | machine.v | v | 66 | 69 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/machine.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:2: Cannot find include file: machine/cpu/mips.v\n`include "machine/cpu/mips.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:3: Cannot find include file: machine/memory/rom.v\n`include "machine/memory/rom.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:4: Cannot find include file: machine/memory/ram.v\n`include "machine/memory/ram.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:11: Define or directive not defined: \'`INST_ADDR_BUS\'\n wire[`INST_ADDR_BUS] rom_addr;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_ADDR_BUS] rom_addr;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:12: Define or directive not defined: \'`INST_DATA_BUS\'\n wire[`INST_DATA_BUS] rom_instruction;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_DATA_BUS] rom_instruction;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:16: Define or directive not defined: \'`INST_ADDR_BUS\'\n wire[`INST_ADDR_BUS] ram_addr;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_ADDR_BUS] ram_addr;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:17: Define or directive not defined: \'`BYTE_SEL_BUS\'\n wire[`BYTE_SEL_BUS] ram_select_signal;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`BYTE_SEL_BUS] ram_select_signal;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:18: Define or directive not defined: \'`INST_DATA_BUS\'\n wire[`INST_DATA_BUS] ram_write_data;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_DATA_BUS] ram_write_data;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:19: Define or directive not defined: \'`INST_DATA_BUS\'\n wire[`INST_DATA_BUS] ram_read_data;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_DATA_BUS] ram_read_data;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:55: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wave.lxt");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:56: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, mips_instance);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:57: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, rom_instance);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:58: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, ram_instance);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/machine.v:60: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, mips_instance.gpr_file_instance.regs[idx]);\n ^~~~~~~~~\n%Error: Exiting due to 21 error(s)\n' | 311,150 | module | module machine(
input wire clock,
input wire reset
);
wire[`INST_ADDR_BUS] rom_addr;
wire[`INST_DATA_BUS] rom_instruction;
wire rom_chip_enable;
wire ram_operation;
wire[`INST_ADDR_BUS] ram_addr;
wire[`BYTE_SEL_BUS] ram_select_signal;
wire[`INST_DATA_BUS] ram_write_data;
wire[`INST_DATA_BUS] ram_read_data;
wire ram_chip_enable;
mips mips_instance(
.clock(clock),
.reset(reset),
.rom_data(rom_instruction),
.ram_read_data(ram_read_data),
.rom_addr(rom_addr),
.rom_chip_enable(rom_chip_enable),
.ram_operation(ram_operation),
.ram_select_signal(ram_select_signal),
.ram_addr(ram_addr),
.ram_write_data(ram_write_data),
.ram_chip_enable(ram_chip_enable)
);
rom rom_instance(
.chip_enable(rom_chip_enable),
.addr(rom_addr),
.instruction(rom_instruction)
);
ram ram_instance(
.clock(clock),
.chip_enable(ram_chip_enable),
.operation(ram_operation),
.addr(ram_addr),
.select_signal(ram_select_signal),
.write_data(ram_write_data),
.read_data(ram_read_data)
);
integer idx;
initial begin
$dumpfile("wave.lxt");
$dumpvars(0, mips_instance);
$dumpvars(0, rom_instance);
$dumpvars(0, ram_instance);
for (idx = 0; idx < 32; idx = idx + 1) begin
$dumpvars(0, mips_instance.gpr_file_instance.regs[idx]);
end
end
endmodule | module machine(
input wire clock,
input wire reset
); |
wire[`INST_ADDR_BUS] rom_addr;
wire[`INST_DATA_BUS] rom_instruction;
wire rom_chip_enable;
wire ram_operation;
wire[`INST_ADDR_BUS] ram_addr;
wire[`BYTE_SEL_BUS] ram_select_signal;
wire[`INST_DATA_BUS] ram_write_data;
wire[`INST_DATA_BUS] ram_read_data;
wire ram_chip_enable;
mips mips_instance(
.clock(clock),
.reset(reset),
.rom_data(rom_instruction),
.ram_read_data(ram_read_data),
.rom_addr(rom_addr),
.rom_chip_enable(rom_chip_enable),
.ram_operation(ram_operation),
.ram_select_signal(ram_select_signal),
.ram_addr(ram_addr),
.ram_write_data(ram_write_data),
.ram_chip_enable(ram_chip_enable)
);
rom rom_instance(
.chip_enable(rom_chip_enable),
.addr(rom_addr),
.instruction(rom_instruction)
);
ram ram_instance(
.clock(clock),
.chip_enable(ram_chip_enable),
.operation(ram_operation),
.addr(ram_addr),
.select_signal(ram_select_signal),
.write_data(ram_write_data),
.read_data(ram_read_data)
);
integer idx;
initial begin
$dumpfile("wave.lxt");
$dumpvars(0, mips_instance);
$dumpvars(0, rom_instance);
$dumpvars(0, ram_instance);
for (idx = 0; idx < 32; idx = idx + 1) begin
$dumpvars(0, mips_instance.gpr_file_instance.regs[idx]);
end
end
endmodule | 0 |
141,268 | data/full_repos/permissive/94422424/source/machine/cpu/control.v | 94,422,424 | control.v | v | 22 | 77 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/control.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/control.v:7: Define or directive not defined: \'`SIGNAL_BUS\'\n output reg[`SIGNAL_BUS] stall\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/control.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output reg[`SIGNAL_BUS] stall\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/control.v:11: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/control.v:13: Define or directive not defined: \'`ENABLE\'\n end else if (stall_from_ex == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/control.v:15: Define or directive not defined: \'`ENABLE\'\n end else if (stall_from_id == `ENABLE) begin\n ^~~~~~~\n%Error: Exiting due to 6 error(s)\n' | 311,151 | module | module control(
input wire reset,
input wire stall_from_id,
input wire stall_from_ex,
output reg[`SIGNAL_BUS] stall
);
always @ (*) begin
if (reset == `ENABLE) begin
stall <= 0;
end else if (stall_from_ex == `ENABLE) begin
stall <= 6'b001111;
end else if (stall_from_id == `ENABLE) begin
stall <= 6'b000111;
end else begin
stall <= 0;
end
end
endmodule | module control(
input wire reset,
input wire stall_from_id,
input wire stall_from_ex,
output reg[`SIGNAL_BUS] stall
); |
always @ (*) begin
if (reset == `ENABLE) begin
stall <= 0;
end else if (stall_from_ex == `ENABLE) begin
stall <= 6'b001111;
end else if (stall_from_id == `ENABLE) begin
stall <= 6'b000111;
end else begin
stall <= 0;
end
end
endmodule | 0 |
141,269 | data/full_repos/permissive/94422424/source/machine/cpu/mips.v | 94,422,424 | mips.v | v | 359 | 77 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:2: Cannot find include file: machine/cpu/control.v\n`include "machine/cpu/control.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:3: Cannot find include file: machine/cpu/stages/pc-reg.v\n`include "machine/cpu/stages/pc-reg.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:4: Cannot find include file: machine/cpu/stages/if-id-buffer.v\n`include "machine/cpu/stages/if-id-buffer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:5: Cannot find include file: machine/cpu/stages/id.v\n`include "machine/cpu/stages/id.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:6: Cannot find include file: machine/cpu/regfile/gpr-file.v\n`include "machine/cpu/regfile/gpr-file.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:7: Cannot find include file: machine/cpu/regfile/hilo-file.v\n`include "machine/cpu/regfile/hilo-file.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:8: Cannot find include file: machine/cpu/stages/id-ex-buffer.v\n`include "machine/cpu/stages/id-ex-buffer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:9: Cannot find include file: machine/cpu/stages/ex.v\n`include "machine/cpu/stages/ex.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:10: Cannot find include file: machine/cpu/stages/ex-div.v\n`include "machine/cpu/stages/ex-div.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:11: Cannot find include file: machine/cpu/stages/ex-mem-buffer.v\n`include "machine/cpu/stages/ex-mem-buffer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:12: Cannot find include file: machine/cpu/stages/mem.v\n`include "machine/cpu/stages/mem.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:13: Cannot find include file: machine/cpu/stages/mem-wb-buffer.v\n`include "machine/cpu/stages/mem-wb-buffer.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:19: Define or directive not defined: \'`INST_DATA_BUS\'\n input wire[`INST_DATA_BUS] rom_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`INST_DATA_BUS] rom_data,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:21: Define or directive not defined: \'`INST_DATA_BUS\'\n input wire[`INST_DATA_BUS] ram_read_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:23: Define or directive not defined: \'`INST_ADDR_BUS\'\n output wire[`INST_ADDR_BUS] rom_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire ram_operation,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`BYTE_SEL_BUS] ram_select_signal,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:27: Define or directive not defined: \'`BYTE_SEL_BUS\'\n output wire[`BYTE_SEL_BUS] ram_select_signal,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:28: Define or directive not defined: \'`INST_ADDR_BUS\'\n output wire[`INST_ADDR_BUS] ram_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:29: Define or directive not defined: \'`INST_DATA_BUS\'\n output wire[`INST_DATA_BUS] ram_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:32: Define or directive not defined: \'`INST_ADDR_BUS\'\n wire[`INST_ADDR_BUS] if_program_counter;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_ADDR_BUS] if_program_counter;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:34: Define or directive not defined: \'`INST_ADDR_BUS\'\n wire[`INST_ADDR_BUS] if_id_program_counter;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_ADDR_BUS] if_id_program_counter;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:35: Define or directive not defined: \'`INST_DATA_BUS\'\n wire[`INST_DATA_BUS] if_id_instruction;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_DATA_BUS] if_id_instruction;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:37: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n wire[`ALU_OPERATOR_BUS] id_alu_operator;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ALU_OPERATOR_BUS] id_alu_operator;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:38: Define or directive not defined: \'`ALU_CATEGORY_BUS\'\n wire[`ALU_CATEGORY_BUS] id_alu_category;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ALU_CATEGORY_BUS] id_alu_category;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:39: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] id_alu_operand1;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] id_alu_operand1;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:40: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] id_alu_operand2;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] id_alu_operand2;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:42: Define or directive not defined: \'`REGS_ADDR_BUS\'\n wire[`REGS_ADDR_BUS] id_write_addr;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_ADDR_BUS] id_write_addr;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:43: Define or directive not defined: \'`INST_DATA_BUS\'\n wire[`INST_DATA_BUS] id_instruction;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`INST_DATA_BUS] id_instruction;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:45: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n wire[`ALU_OPERATOR_BUS] id_ex_buffer_alu_operator;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ALU_OPERATOR_BUS] id_ex_buffer_alu_operator;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:46: Define or directive not defined: \'`ALU_CATEGORY_BUS\'\n wire[`ALU_CATEGORY_BUS] id_ex_buffer_alu_category;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ALU_CATEGORY_BUS] id_ex_buffer_alu_category;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:47: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand1;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand1;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:48: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand2;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand2;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:50: Define or directive not defined: \'`REGS_ADDR_BUS\'\n wire[`REGS_ADDR_BUS] id_ex_buffer_write_addr;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/mips.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_ADDR_BUS] id_ex_buffer_write_addr;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 311,152 | module | module mips(
input wire clock,
input wire reset,
input wire[`INST_DATA_BUS] rom_data,
input wire[`INST_DATA_BUS] ram_read_data,
output wire[`INST_ADDR_BUS] rom_addr,
output wire rom_chip_enable,
output wire ram_operation,
output wire[`BYTE_SEL_BUS] ram_select_signal,
output wire[`INST_ADDR_BUS] ram_addr,
output wire[`INST_DATA_BUS] ram_write_data,
output wire ram_chip_enable
);
wire[`INST_ADDR_BUS] if_program_counter;
wire[`INST_ADDR_BUS] if_id_program_counter;
wire[`INST_DATA_BUS] if_id_instruction;
wire[`ALU_OPERATOR_BUS] id_alu_operator;
wire[`ALU_CATEGORY_BUS] id_alu_category;
wire[`REGS_DATA_BUS] id_alu_operand1;
wire[`REGS_DATA_BUS] id_alu_operand2;
wire id_write_enable;
wire[`REGS_ADDR_BUS] id_write_addr;
wire[`INST_DATA_BUS] id_instruction;
wire[`ALU_OPERATOR_BUS] id_ex_buffer_alu_operator;
wire[`ALU_CATEGORY_BUS] id_ex_buffer_alu_category;
wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand1;
wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand2;
wire id_ex_buffer_write_enable;
wire[`REGS_ADDR_BUS] id_ex_buffer_write_addr;
wire[`INST_DATA_BUS] id_ex_instruction;
wire ex_write_enable;
wire[`REGS_ADDR_BUS] ex_write_addr;
wire[`REGS_DATA_BUS] ex_write_data;
wire ex_write_hilo_enable;
wire[`REGS_DATA_BUS] ex_write_hi_data;
wire[`REGS_DATA_BUS] ex_write_lo_data;
wire[`REGS_DATA_BUS] ex_to_div_operand1;
wire[`REGS_DATA_BUS] ex_to_div_operand2;
wire ex_to_div_is_start;
wire ex_to_div_is_signed;
wire[`ALU_OPERATOR_BUS] ex_alu_operator;
wire[`REGS_DATA_BUS] ex_alu_operand2;
wire[`REGS_DATA_BUS] ex_ram_addr;
wire[`DOUBLE_REGS_DATA_BUS] ex_div_result;
wire ex_div_is_ended;
wire ex_mem_buffer_write_enable;
wire[`REGS_ADDR_BUS] ex_mem_buffer_write_addr;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_data;
wire ex_mem_buffer_write_hilo_enable;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_hi_data;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_lo_data;
wire[`DOUBLE_REGS_DATA_BUS] ex_mem_last_result;
wire[`CYCLE_BUS] ex_mem_last_cycle;
wire[`ALU_OPERATOR_BUS] ex_mem_alu_operator;
wire[`REGS_DATA_BUS] ex_mem_alu_operand2;
wire[`REGS_DATA_BUS] ex_mem_ram_addr;
wire mem_write_enable;
wire[`REGS_ADDR_BUS] mem_write_addr;
wire[`REGS_DATA_BUS] mem_write_data;
wire mem_write_hilo_enable;
wire[`REGS_DATA_BUS] mem_write_hi_data;
wire[`REGS_DATA_BUS] mem_write_lo_data;
wire mem_wb_buffer_write_enable;
wire[`REGS_ADDR_BUS] mem_wb_buffer_write_addr;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_data;
wire mem_wb_buffer_write_hilo_enable;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_hi_data;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_lo_data;
wire gpr_file_read_enable1;
wire gpr_file_read_enable2;
wire[`REGS_ADDR_BUS] gpr_file_read_addr1;
wire[`REGS_ADDR_BUS] gpr_file_read_addr2;
wire[`REGS_DATA_BUS] gpr_file_read_result1;
wire[`REGS_DATA_BUS] gpr_file_read_result2;
wire[`REGS_DATA_BUS] hilo_file_hi_data;
wire[`REGS_DATA_BUS] hilo_file_lo_data;
wire[`SIGNAL_BUS] stall_signal;
wire stall_from_id;
wire stall_from_ex;
wire[`DOUBLE_REGS_DATA_BUS] ex_current_result;
wire[`CYCLE_BUS] ex_current_cycle;
wire curr_next_is_in_delayslot_connector;
wire id_is_curr_in_delayslot;
wire id_is_next_in_delayslot;
wire id_branch_signal;
wire[`REGS_DATA_BUS] id_branch_target;
wire[`REGS_DATA_BUS] id_return_target;
wire id_ex_is_curr_in_delayslot;
wire[`REGS_DATA_BUS] id_ex_return_target;
pc_reg pc_reg_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.program_counter(if_program_counter),
.chip_enable(rom_chip_enable),
.branch_signal(id_branch_signal),
.branch_target(id_branch_target)
);
assign rom_addr = if_program_counter;
control control_instance(
.reset(reset),
.stall_from_id(stall_from_id),
.stall_from_ex(stall_from_ex),
.stall(stall_signal)
);
if_id_buffer if_id_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.if_program_counter(if_program_counter),
.if_instruction(rom_data),
.id_program_counter(if_id_program_counter),
.id_instruction(if_id_instruction)
);
gpr_file gpr_file_instance(
.clock(clock),
.reset(reset),
.write_enable(mem_wb_buffer_write_enable),
.write_addr(mem_wb_buffer_write_addr),
.write_data(mem_wb_buffer_write_data),
.read_enable1(gpr_file_read_enable1),
.read_addr1(gpr_file_read_addr1),
.read_data1(gpr_file_read_result1),
.read_enable2(gpr_file_read_enable2),
.read_addr2(gpr_file_read_addr2),
.read_data2(gpr_file_read_result2)
);
hilo_file hilo_file_instance(
.clock(clock),
.reset(reset),
.write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.write_hi_data(mem_wb_buffer_write_hi_data),
.write_lo_data(mem_wb_buffer_write_lo_data),
.hi_data(hilo_file_hi_data),
.lo_data(hilo_file_lo_data)
);
id id_instance(
.reset(reset),
.program_counter(if_id_program_counter),
.instruction(if_id_instruction),
.ex_write_enable(ex_write_enable),
.ex_write_addr(ex_write_addr),
.ex_write_data(ex_write_data),
.mem_write_enable(mem_write_enable),
.mem_write_addr(mem_write_addr),
.mem_write_data(mem_write_data),
.read_result1(gpr_file_read_result1),
.read_result2(gpr_file_read_result2),
.input_is_curr_in_delayslot(curr_next_is_in_delayslot_connector),
.ex_alu_operator(ex_alu_operator),
.broadcast_instruction(id_instruction),
.is_curr_in_delayslot(id_is_curr_in_delayslot),
.is_next_in_delayslot(id_is_next_in_delayslot),
.branch_signal(id_branch_signal),
.branch_target(id_branch_target),
.return_target(id_return_target),
.read_enable1(gpr_file_read_enable1),
.read_enable2(gpr_file_read_enable2),
.read_addr1(gpr_file_read_addr1),
.read_addr2(gpr_file_read_addr2),
.alu_operator(id_alu_operator),
.alu_category(id_alu_category),
.alu_operand1(id_alu_operand1),
.alu_operand2(id_alu_operand2),
.write_enable(id_write_enable),
.write_addr(id_write_addr),
.stall_signal(stall_from_id)
);
id_ex_buffer id_ex_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.id_operator(id_alu_operator),
.id_category(id_alu_category),
.id_operand1(id_alu_operand1),
.id_operand2(id_alu_operand2),
.id_write_addr(id_write_addr),
.id_write_enable(id_write_enable),
.id_return_target(id_return_target),
.id_is_curr_in_delayslot(id_is_curr_in_delayslot),
.input_is_next_in_delayslot(id_is_next_in_delayslot),
.id_instruction(id_instruction),
.ex_operator(id_ex_buffer_alu_operator),
.ex_category(id_ex_buffer_alu_category),
.ex_operand1(id_ex_buffer_alu_operand1),
.ex_operand2(id_ex_buffer_alu_operand2),
.ex_write_addr(id_ex_buffer_write_addr),
.ex_write_enable(id_ex_buffer_write_enable),
.ex_return_target(id_ex_return_target),
.ex_is_curr_in_delayslot(id_ex_is_curr_in_delayslot),
.is_curr_in_delayslot(curr_next_is_in_delayslot_connector),
.ex_instruction(id_ex_instruction)
);
ex ex_instance(
.reset(reset),
.operand_hi(hilo_file_hi_data),
.operand_lo(hilo_file_lo_data),
.wb_write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.wb_write_hi_data(mem_wb_buffer_write_hi_data),
.wb_write_lo_data(mem_wb_buffer_write_lo_data),
.mem_write_hilo_enable(mem_write_hilo_enable),
.mem_write_hi_data(mem_write_hi_data),
.mem_write_lo_data(mem_write_lo_data),
.ex_div_result(ex_div_result),
.ex_div_is_ended(ex_div_is_ended),
.operator(id_ex_buffer_alu_operator),
.category(id_ex_buffer_alu_category),
.operand1(id_ex_buffer_alu_operand1),
.operand2(id_ex_buffer_alu_operand2),
.input_write_addr(id_ex_buffer_write_addr),
.input_write_enable(id_ex_buffer_write_enable),
.last_result(ex_mem_last_result),
.last_cycle(ex_mem_last_cycle),
.return_target(id_ex_return_target),
.is_curr_in_delayslot(id_ex_is_curr_in_delayslot),
.instruction(id_ex_instruction),
.to_div_operand1(ex_to_div_operand1),
.to_div_operand2(ex_to_div_operand2),
.to_div_is_start(ex_to_div_is_start),
.to_div_is_signed(ex_to_div_is_signed),
.write_hilo_enable(ex_write_hilo_enable),
.write_hi_data(ex_write_hi_data),
.write_lo_data(ex_write_lo_data),
.write_addr(ex_write_addr),
.write_enable(ex_write_enable),
.write_data(ex_write_data),
.current_result(ex_current_result),
.current_cycle(ex_current_cycle),
.stall_signal(stall_from_ex),
.broadcast_alu_operator(ex_alu_operator),
.broadcast_alu_operand2(ex_alu_operand2),
.broadcast_ram_addr(ex_ram_addr)
);
ex_div ex_div_instance(
.clock(clock),
.reset(reset),
.is_signed(ex_to_div_is_signed),
.operand1(ex_to_div_operand1),
.operand2(ex_to_div_operand2),
.is_start(ex_to_div_is_start),
.is_annul(1'b0),
.is_ended(ex_div_is_ended),
.result(ex_div_result)
);
ex_mem_buffer ex_mem_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.ex_write_enable(ex_write_enable),
.ex_write_addr(ex_write_addr),
.ex_write_data(ex_write_data),
.ex_write_hilo_enable(ex_write_hilo_enable),
.ex_write_hi_data(ex_write_hi_data),
.ex_write_lo_data(ex_write_lo_data),
.ex_current_result(ex_current_result),
.ex_current_cycle(ex_current_cycle),
.ex_alu_operator(ex_alu_operator),
.ex_alu_operand2(ex_alu_operand2),
.ex_ram_addr(ex_ram_addr),
.mem_write_enable(ex_mem_buffer_write_enable),
.mem_write_addr(ex_mem_buffer_write_addr),
.mem_write_data(ex_mem_buffer_write_data),
.mem_write_hilo_enable(ex_mem_buffer_write_hilo_enable),
.mem_write_hi_data(ex_mem_buffer_write_hi_data),
.mem_write_lo_data(ex_mem_buffer_write_lo_data),
.mem_last_result(ex_mem_last_result),
.mem_last_cycle(ex_mem_last_cycle),
.mem_alu_operator(ex_mem_alu_operator),
.mem_alu_operand2(ex_mem_alu_operand2),
.mem_ram_addr(ex_mem_ram_addr)
);
mem mem_instance(
.reset(reset),
.input_write_enable(ex_mem_buffer_write_enable),
.input_write_addr(ex_mem_buffer_write_addr),
.input_write_data(ex_mem_buffer_write_data),
.input_write_hilo_enable(ex_mem_buffer_write_hilo_enable),
.input_write_hi_data(ex_mem_buffer_write_hi_data),
.input_write_lo_data(ex_mem_buffer_write_lo_data),
.input_alu_operator(ex_mem_alu_operator),
.input_alu_operand2(ex_mem_alu_operand2),
.input_ram_addr(ex_mem_ram_addr),
.input_ram_read_data(ram_read_data),
.write_enable(mem_write_enable),
.write_addr(mem_write_addr),
.write_data(mem_write_data),
.write_hilo_enable(mem_write_hilo_enable),
.write_hi_data(mem_write_hi_data),
.write_lo_data(mem_write_lo_data),
.ram_addr(ram_addr),
.ram_operation(ram_operation),
.ram_select_signal(ram_select_signal),
.ram_write_data(ram_write_data),
.ram_chip_enable(ram_chip_enable)
);
mem_wb_buffer mem_wb_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.mem_write_enable(mem_write_enable),
.mem_write_addr(mem_write_addr),
.mem_write_data(mem_write_data),
.mem_write_hilo_enable(mem_write_hilo_enable),
.mem_write_hi_data(mem_write_hi_data),
.mem_write_lo_data(mem_write_lo_data),
.wb_write_enable(mem_wb_buffer_write_enable),
.wb_write_addr(mem_wb_buffer_write_addr),
.wb_write_data(mem_wb_buffer_write_data),
.wb_write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.wb_write_hi_data(mem_wb_buffer_write_hi_data),
.wb_write_lo_data(mem_wb_buffer_write_lo_data)
);
endmodule | module mips(
input wire clock,
input wire reset,
input wire[`INST_DATA_BUS] rom_data,
input wire[`INST_DATA_BUS] ram_read_data,
output wire[`INST_ADDR_BUS] rom_addr,
output wire rom_chip_enable,
output wire ram_operation,
output wire[`BYTE_SEL_BUS] ram_select_signal,
output wire[`INST_ADDR_BUS] ram_addr,
output wire[`INST_DATA_BUS] ram_write_data,
output wire ram_chip_enable
); |
wire[`INST_ADDR_BUS] if_program_counter;
wire[`INST_ADDR_BUS] if_id_program_counter;
wire[`INST_DATA_BUS] if_id_instruction;
wire[`ALU_OPERATOR_BUS] id_alu_operator;
wire[`ALU_CATEGORY_BUS] id_alu_category;
wire[`REGS_DATA_BUS] id_alu_operand1;
wire[`REGS_DATA_BUS] id_alu_operand2;
wire id_write_enable;
wire[`REGS_ADDR_BUS] id_write_addr;
wire[`INST_DATA_BUS] id_instruction;
wire[`ALU_OPERATOR_BUS] id_ex_buffer_alu_operator;
wire[`ALU_CATEGORY_BUS] id_ex_buffer_alu_category;
wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand1;
wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand2;
wire id_ex_buffer_write_enable;
wire[`REGS_ADDR_BUS] id_ex_buffer_write_addr;
wire[`INST_DATA_BUS] id_ex_instruction;
wire ex_write_enable;
wire[`REGS_ADDR_BUS] ex_write_addr;
wire[`REGS_DATA_BUS] ex_write_data;
wire ex_write_hilo_enable;
wire[`REGS_DATA_BUS] ex_write_hi_data;
wire[`REGS_DATA_BUS] ex_write_lo_data;
wire[`REGS_DATA_BUS] ex_to_div_operand1;
wire[`REGS_DATA_BUS] ex_to_div_operand2;
wire ex_to_div_is_start;
wire ex_to_div_is_signed;
wire[`ALU_OPERATOR_BUS] ex_alu_operator;
wire[`REGS_DATA_BUS] ex_alu_operand2;
wire[`REGS_DATA_BUS] ex_ram_addr;
wire[`DOUBLE_REGS_DATA_BUS] ex_div_result;
wire ex_div_is_ended;
wire ex_mem_buffer_write_enable;
wire[`REGS_ADDR_BUS] ex_mem_buffer_write_addr;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_data;
wire ex_mem_buffer_write_hilo_enable;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_hi_data;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_lo_data;
wire[`DOUBLE_REGS_DATA_BUS] ex_mem_last_result;
wire[`CYCLE_BUS] ex_mem_last_cycle;
wire[`ALU_OPERATOR_BUS] ex_mem_alu_operator;
wire[`REGS_DATA_BUS] ex_mem_alu_operand2;
wire[`REGS_DATA_BUS] ex_mem_ram_addr;
wire mem_write_enable;
wire[`REGS_ADDR_BUS] mem_write_addr;
wire[`REGS_DATA_BUS] mem_write_data;
wire mem_write_hilo_enable;
wire[`REGS_DATA_BUS] mem_write_hi_data;
wire[`REGS_DATA_BUS] mem_write_lo_data;
wire mem_wb_buffer_write_enable;
wire[`REGS_ADDR_BUS] mem_wb_buffer_write_addr;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_data;
wire mem_wb_buffer_write_hilo_enable;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_hi_data;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_lo_data;
wire gpr_file_read_enable1;
wire gpr_file_read_enable2;
wire[`REGS_ADDR_BUS] gpr_file_read_addr1;
wire[`REGS_ADDR_BUS] gpr_file_read_addr2;
wire[`REGS_DATA_BUS] gpr_file_read_result1;
wire[`REGS_DATA_BUS] gpr_file_read_result2;
wire[`REGS_DATA_BUS] hilo_file_hi_data;
wire[`REGS_DATA_BUS] hilo_file_lo_data;
wire[`SIGNAL_BUS] stall_signal;
wire stall_from_id;
wire stall_from_ex;
wire[`DOUBLE_REGS_DATA_BUS] ex_current_result;
wire[`CYCLE_BUS] ex_current_cycle;
wire curr_next_is_in_delayslot_connector;
wire id_is_curr_in_delayslot;
wire id_is_next_in_delayslot;
wire id_branch_signal;
wire[`REGS_DATA_BUS] id_branch_target;
wire[`REGS_DATA_BUS] id_return_target;
wire id_ex_is_curr_in_delayslot;
wire[`REGS_DATA_BUS] id_ex_return_target;
pc_reg pc_reg_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.program_counter(if_program_counter),
.chip_enable(rom_chip_enable),
.branch_signal(id_branch_signal),
.branch_target(id_branch_target)
);
assign rom_addr = if_program_counter;
control control_instance(
.reset(reset),
.stall_from_id(stall_from_id),
.stall_from_ex(stall_from_ex),
.stall(stall_signal)
);
if_id_buffer if_id_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.if_program_counter(if_program_counter),
.if_instruction(rom_data),
.id_program_counter(if_id_program_counter),
.id_instruction(if_id_instruction)
);
gpr_file gpr_file_instance(
.clock(clock),
.reset(reset),
.write_enable(mem_wb_buffer_write_enable),
.write_addr(mem_wb_buffer_write_addr),
.write_data(mem_wb_buffer_write_data),
.read_enable1(gpr_file_read_enable1),
.read_addr1(gpr_file_read_addr1),
.read_data1(gpr_file_read_result1),
.read_enable2(gpr_file_read_enable2),
.read_addr2(gpr_file_read_addr2),
.read_data2(gpr_file_read_result2)
);
hilo_file hilo_file_instance(
.clock(clock),
.reset(reset),
.write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.write_hi_data(mem_wb_buffer_write_hi_data),
.write_lo_data(mem_wb_buffer_write_lo_data),
.hi_data(hilo_file_hi_data),
.lo_data(hilo_file_lo_data)
);
id id_instance(
.reset(reset),
.program_counter(if_id_program_counter),
.instruction(if_id_instruction),
.ex_write_enable(ex_write_enable),
.ex_write_addr(ex_write_addr),
.ex_write_data(ex_write_data),
.mem_write_enable(mem_write_enable),
.mem_write_addr(mem_write_addr),
.mem_write_data(mem_write_data),
.read_result1(gpr_file_read_result1),
.read_result2(gpr_file_read_result2),
.input_is_curr_in_delayslot(curr_next_is_in_delayslot_connector),
.ex_alu_operator(ex_alu_operator),
.broadcast_instruction(id_instruction),
.is_curr_in_delayslot(id_is_curr_in_delayslot),
.is_next_in_delayslot(id_is_next_in_delayslot),
.branch_signal(id_branch_signal),
.branch_target(id_branch_target),
.return_target(id_return_target),
.read_enable1(gpr_file_read_enable1),
.read_enable2(gpr_file_read_enable2),
.read_addr1(gpr_file_read_addr1),
.read_addr2(gpr_file_read_addr2),
.alu_operator(id_alu_operator),
.alu_category(id_alu_category),
.alu_operand1(id_alu_operand1),
.alu_operand2(id_alu_operand2),
.write_enable(id_write_enable),
.write_addr(id_write_addr),
.stall_signal(stall_from_id)
);
id_ex_buffer id_ex_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.id_operator(id_alu_operator),
.id_category(id_alu_category),
.id_operand1(id_alu_operand1),
.id_operand2(id_alu_operand2),
.id_write_addr(id_write_addr),
.id_write_enable(id_write_enable),
.id_return_target(id_return_target),
.id_is_curr_in_delayslot(id_is_curr_in_delayslot),
.input_is_next_in_delayslot(id_is_next_in_delayslot),
.id_instruction(id_instruction),
.ex_operator(id_ex_buffer_alu_operator),
.ex_category(id_ex_buffer_alu_category),
.ex_operand1(id_ex_buffer_alu_operand1),
.ex_operand2(id_ex_buffer_alu_operand2),
.ex_write_addr(id_ex_buffer_write_addr),
.ex_write_enable(id_ex_buffer_write_enable),
.ex_return_target(id_ex_return_target),
.ex_is_curr_in_delayslot(id_ex_is_curr_in_delayslot),
.is_curr_in_delayslot(curr_next_is_in_delayslot_connector),
.ex_instruction(id_ex_instruction)
);
ex ex_instance(
.reset(reset),
.operand_hi(hilo_file_hi_data),
.operand_lo(hilo_file_lo_data),
.wb_write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.wb_write_hi_data(mem_wb_buffer_write_hi_data),
.wb_write_lo_data(mem_wb_buffer_write_lo_data),
.mem_write_hilo_enable(mem_write_hilo_enable),
.mem_write_hi_data(mem_write_hi_data),
.mem_write_lo_data(mem_write_lo_data),
.ex_div_result(ex_div_result),
.ex_div_is_ended(ex_div_is_ended),
.operator(id_ex_buffer_alu_operator),
.category(id_ex_buffer_alu_category),
.operand1(id_ex_buffer_alu_operand1),
.operand2(id_ex_buffer_alu_operand2),
.input_write_addr(id_ex_buffer_write_addr),
.input_write_enable(id_ex_buffer_write_enable),
.last_result(ex_mem_last_result),
.last_cycle(ex_mem_last_cycle),
.return_target(id_ex_return_target),
.is_curr_in_delayslot(id_ex_is_curr_in_delayslot),
.instruction(id_ex_instruction),
.to_div_operand1(ex_to_div_operand1),
.to_div_operand2(ex_to_div_operand2),
.to_div_is_start(ex_to_div_is_start),
.to_div_is_signed(ex_to_div_is_signed),
.write_hilo_enable(ex_write_hilo_enable),
.write_hi_data(ex_write_hi_data),
.write_lo_data(ex_write_lo_data),
.write_addr(ex_write_addr),
.write_enable(ex_write_enable),
.write_data(ex_write_data),
.current_result(ex_current_result),
.current_cycle(ex_current_cycle),
.stall_signal(stall_from_ex),
.broadcast_alu_operator(ex_alu_operator),
.broadcast_alu_operand2(ex_alu_operand2),
.broadcast_ram_addr(ex_ram_addr)
);
ex_div ex_div_instance(
.clock(clock),
.reset(reset),
.is_signed(ex_to_div_is_signed),
.operand1(ex_to_div_operand1),
.operand2(ex_to_div_operand2),
.is_start(ex_to_div_is_start),
.is_annul(1'b0),
.is_ended(ex_div_is_ended),
.result(ex_div_result)
);
ex_mem_buffer ex_mem_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.ex_write_enable(ex_write_enable),
.ex_write_addr(ex_write_addr),
.ex_write_data(ex_write_data),
.ex_write_hilo_enable(ex_write_hilo_enable),
.ex_write_hi_data(ex_write_hi_data),
.ex_write_lo_data(ex_write_lo_data),
.ex_current_result(ex_current_result),
.ex_current_cycle(ex_current_cycle),
.ex_alu_operator(ex_alu_operator),
.ex_alu_operand2(ex_alu_operand2),
.ex_ram_addr(ex_ram_addr),
.mem_write_enable(ex_mem_buffer_write_enable),
.mem_write_addr(ex_mem_buffer_write_addr),
.mem_write_data(ex_mem_buffer_write_data),
.mem_write_hilo_enable(ex_mem_buffer_write_hilo_enable),
.mem_write_hi_data(ex_mem_buffer_write_hi_data),
.mem_write_lo_data(ex_mem_buffer_write_lo_data),
.mem_last_result(ex_mem_last_result),
.mem_last_cycle(ex_mem_last_cycle),
.mem_alu_operator(ex_mem_alu_operator),
.mem_alu_operand2(ex_mem_alu_operand2),
.mem_ram_addr(ex_mem_ram_addr)
);
mem mem_instance(
.reset(reset),
.input_write_enable(ex_mem_buffer_write_enable),
.input_write_addr(ex_mem_buffer_write_addr),
.input_write_data(ex_mem_buffer_write_data),
.input_write_hilo_enable(ex_mem_buffer_write_hilo_enable),
.input_write_hi_data(ex_mem_buffer_write_hi_data),
.input_write_lo_data(ex_mem_buffer_write_lo_data),
.input_alu_operator(ex_mem_alu_operator),
.input_alu_operand2(ex_mem_alu_operand2),
.input_ram_addr(ex_mem_ram_addr),
.input_ram_read_data(ram_read_data),
.write_enable(mem_write_enable),
.write_addr(mem_write_addr),
.write_data(mem_write_data),
.write_hilo_enable(mem_write_hilo_enable),
.write_hi_data(mem_write_hi_data),
.write_lo_data(mem_write_lo_data),
.ram_addr(ram_addr),
.ram_operation(ram_operation),
.ram_select_signal(ram_select_signal),
.ram_write_data(ram_write_data),
.ram_chip_enable(ram_chip_enable)
);
mem_wb_buffer mem_wb_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.mem_write_enable(mem_write_enable),
.mem_write_addr(mem_write_addr),
.mem_write_data(mem_write_data),
.mem_write_hilo_enable(mem_write_hilo_enable),
.mem_write_hi_data(mem_write_hi_data),
.mem_write_lo_data(mem_write_lo_data),
.wb_write_enable(mem_wb_buffer_write_enable),
.wb_write_addr(mem_wb_buffer_write_addr),
.wb_write_data(mem_wb_buffer_write_data),
.wb_write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.wb_write_hi_data(mem_wb_buffer_write_hi_data),
.wb_write_lo_data(mem_wb_buffer_write_lo_data)
);
endmodule | 0 |
141,270 | data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v | 94,422,424 | gpr-file.v | v | 58 | 107 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/regfile,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/regfile,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/regfile,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:8: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`REGS_ADDR_BUS] write_addr,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:9: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_ADDR_BUS] read_addr1,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:12: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] read_addr1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:13: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] read_data1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_ADDR_BUS] read_addr2,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:16: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] read_addr2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:17: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] read_data2\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:20: Define or directive not defined: \'`REGS_DATA_BUS\'\n reg[`REGS_DATA_BUS] regs[0:`REGS_NUM - 1];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`REGS_DATA_BUS] regs[0:`REGS_NUM - 1];\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:20: Define or directive not defined: \'`REGS_NUM\'\n reg[`REGS_DATA_BUS] regs[0:`REGS_NUM - 1];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:24: Define or directive not defined: \'`DISABLE\'\n if (reset == `DISABLE && write_enable == `ENABLE && write_addr != `REGS_NUM_LOG\'h0) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:24: Define or directive not defined: \'`ENABLE\'\n if (reset == `DISABLE && write_enable == `ENABLE && write_addr != `REGS_NUM_LOG\'h0) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:24: Define or directive not defined: \'`REGS_NUM_LOG\'\n if (reset == `DISABLE && write_enable == `ENABLE && write_addr != `REGS_NUM_LOG\'h0) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:30: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:32: Define or directive not defined: \'`REGS_NUM_LOG\'\n end else if (read_addr1 == `REGS_NUM_LOG\'h0) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:34: Define or directive not defined: \'`ENABLE\'\n end else if (write_enable == `ENABLE && read_enable1 == `ENABLE && read_addr1 == write_addr) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:34: Define or directive not defined: \'`ENABLE\'\n end else if (write_enable == `ENABLE && read_enable1 == `ENABLE && read_addr1 == write_addr) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:36: Define or directive not defined: \'`ENABLE\'\n end else if (read_enable1 == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:44: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:46: Define or directive not defined: \'`REGS_NUM_LOG\'\n end else if (read_addr2 == `REGS_NUM_LOG\'h0) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:48: Define or directive not defined: \'`ENABLE\'\n end else if (write_enable == `ENABLE && read_enable2 == `ENABLE && read_addr2 == write_addr) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:48: Define or directive not defined: \'`ENABLE\'\n end else if (write_enable == `ENABLE && read_enable2 == `ENABLE && read_addr2 == write_addr) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/gpr-file.v:50: Define or directive not defined: \'`ENABLE\'\n end else if (read_enable2 == `ENABLE) begin\n ^~~~~~~\n%Error: Exiting due to 26 error(s)\n' | 311,153 | module | module gpr_file(
input wire clock,
input wire reset,
input wire write_enable,
input wire[`REGS_ADDR_BUS] write_addr,
input wire[`REGS_DATA_BUS] write_data,
input wire read_enable1,
input wire[`REGS_ADDR_BUS] read_addr1,
output reg[`REGS_DATA_BUS] read_data1,
input wire read_enable2,
input wire[`REGS_ADDR_BUS] read_addr2,
output reg[`REGS_DATA_BUS] read_data2
);
reg[`REGS_DATA_BUS] regs[0:`REGS_NUM - 1];
always @ (posedge clock) begin
if (reset == `DISABLE && write_enable == `ENABLE && write_addr != `REGS_NUM_LOG'h0) begin
regs[write_addr] <= write_data;
end
end
always @ (*) begin
if (reset == `ENABLE) begin
read_data1 <= 0;
end else if (read_addr1 == `REGS_NUM_LOG'h0) begin
read_data1 <= 0;
end else if (write_enable == `ENABLE && read_enable1 == `ENABLE && read_addr1 == write_addr) begin
read_data1 <= write_data;
end else if (read_enable1 == `ENABLE) begin
read_data1 <= regs[read_addr1];
end else begin
read_data1 <= 0;
end
end
always @ (*) begin
if (reset == `ENABLE) begin
read_data2 <= 0;
end else if (read_addr2 == `REGS_NUM_LOG'h0) begin
read_data2 <= 0;
end else if (write_enable == `ENABLE && read_enable2 == `ENABLE && read_addr2 == write_addr) begin
read_data2 <= write_data;
end else if (read_enable2 == `ENABLE) begin
read_data2 <= regs[read_addr2];
end else begin
read_data2 <= 0;
end
end
endmodule | module gpr_file(
input wire clock,
input wire reset,
input wire write_enable,
input wire[`REGS_ADDR_BUS] write_addr,
input wire[`REGS_DATA_BUS] write_data,
input wire read_enable1,
input wire[`REGS_ADDR_BUS] read_addr1,
output reg[`REGS_DATA_BUS] read_data1,
input wire read_enable2,
input wire[`REGS_ADDR_BUS] read_addr2,
output reg[`REGS_DATA_BUS] read_data2
); |
reg[`REGS_DATA_BUS] regs[0:`REGS_NUM - 1];
always @ (posedge clock) begin
if (reset == `DISABLE && write_enable == `ENABLE && write_addr != `REGS_NUM_LOG'h0) begin
regs[write_addr] <= write_data;
end
end
always @ (*) begin
if (reset == `ENABLE) begin
read_data1 <= 0;
end else if (read_addr1 == `REGS_NUM_LOG'h0) begin
read_data1 <= 0;
end else if (write_enable == `ENABLE && read_enable1 == `ENABLE && read_addr1 == write_addr) begin
read_data1 <= write_data;
end else if (read_enable1 == `ENABLE) begin
read_data1 <= regs[read_addr1];
end else begin
read_data1 <= 0;
end
end
always @ (*) begin
if (reset == `ENABLE) begin
read_data2 <= 0;
end else if (read_addr2 == `REGS_NUM_LOG'h0) begin
read_data2 <= 0;
end else if (write_enable == `ENABLE && read_enable2 == `ENABLE && read_addr2 == write_addr) begin
read_data2 <= write_data;
end else if (read_enable2 == `ENABLE) begin
read_data2 <= regs[read_addr2];
end else begin
read_data2 <= 0;
end
end
endmodule | 0 |
141,271 | data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v | 94,422,424 | hilo-file.v | v | 25 | 99 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/regfile,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/regfile,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/regfile,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:8: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`REGS_DATA_BUS] write_hi_data,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:9: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:12: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] lo_data\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:16: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/regfile/hilo-file.v:19: Define or directive not defined: \'`ENABLE\'\n end else if (write_hilo_enable == `ENABLE) begin\n ^~~~~~~\n%Error: Exiting due to 8 error(s)\n' | 311,154 | module | module hilo_file(
input wire clock,
input wire reset,
input wire write_hilo_enable,
input wire[`REGS_DATA_BUS] write_hi_data,
input wire[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_DATA_BUS] hi_data,
output reg[`REGS_DATA_BUS] lo_data
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
hi_data <= 0;
lo_data <= 0;
end else if (write_hilo_enable == `ENABLE) begin
hi_data <= write_hi_data;
lo_data <= write_lo_data;
end
end
endmodule | module hilo_file(
input wire clock,
input wire reset,
input wire write_hilo_enable,
input wire[`REGS_DATA_BUS] write_hi_data,
input wire[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_DATA_BUS] hi_data,
output reg[`REGS_DATA_BUS] lo_data
); |
always @ (posedge clock) begin
if (reset == `ENABLE) begin
hi_data <= 0;
lo_data <= 0;
end else if (write_hilo_enable == `ENABLE) begin
hi_data <= write_hi_data;
lo_data <= write_lo_data;
end
end
endmodule | 0 |
141,272 | data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v | 94,422,424 | ex-div.v | v | 95 | 106 | [] | [] | [] | null | line:6: before: "]" | null | 1: b"%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:6: Define or directive not defined: '`REGS_DATA_BUS'\n input wire[`REGS_DATA_BUS] operand1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:6: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n input wire[`REGS_DATA_BUS] operand1,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:7: Define or directive not defined: '`REGS_DATA_BUS'\n input wire[`REGS_DATA_BUS] operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire is_annul,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg is_ended,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:13: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n output reg[`DOUBLE_REGS_DATA_BUS] result\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:13: Define or directive not defined: '`DOUBLE_REGS_DATA_BUS'\n output reg[`DOUBLE_REGS_DATA_BUS] result\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:16: Define or directive not defined: '`EXT_REGS_DATA_BUS'\n wire[`EXT_REGS_DATA_BUS] div_temp;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:16: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n wire[`EXT_REGS_DATA_BUS] div_temp;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:17: Define or directive not defined: '`EXT_DOUBLE_REGS_DATA_BUS'\n reg[`EXT_DOUBLE_REGS_DATA_BUS] dividend;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:17: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n reg[`EXT_DOUBLE_REGS_DATA_BUS] dividend;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:18: Define or directive not defined: '`REGS_DATA_BUS'\n reg[`REGS_DATA_BUS] divisor;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:18: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n reg[`REGS_DATA_BUS] divisor;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:22: syntax error, unexpected assign\n assign div_temp = {1'b0, dividend[63 : 32]} - {1'b0, divisor};\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:25: Define or directive not defined: '`ENABLE'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:26: Define or directive not defined: '`DIV_FREE'\n state <= `DIV_FREE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:27: Define or directive not defined: '`FALSE'\n is_ended <= `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:31: Define or directive not defined: '`DIV_FREE'\n `DIV_FREE: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:32: Define or directive not defined: '`TRUE'\n if (is_start == `TRUE && is_annul == `FALSE) begin\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:32: Define or directive not defined: '`FALSE'\n if (is_start == `TRUE && is_annul == `FALSE) begin\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:34: Define or directive not defined: '`DIV_BY_ZERO'\n state <= `DIV_BY_ZERO;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:36: Define or directive not defined: '`DIV_ON'\n state <= `DIV_ON;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:39: Define or directive not defined: '`TRUE'\n if (is_signed == `TRUE && operand1[31] == 1'b1) begin\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:44: Define or directive not defined: '`TRUE'\n if (is_signed == `TRUE && operand2[31] == 1'b1) begin\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:51: Define or directive not defined: '`FALSE'\n is_ended <= `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:55: Define or directive not defined: '`DIV_BY_ZERO'\n `DIV_BY_ZERO: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:57: Define or directive not defined: '`DIV_END'\n state <= `DIV_END;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:59: Define or directive not defined: '`DIV_ON'\n `DIV_ON: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:60: Define or directive not defined: '`FALSE'\n if (is_annul == `FALSE) begin\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:75: Define or directive not defined: '`DIV_END'\n state <= `DIV_END;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:79: Define or directive not defined: '`DIV_FREE'\n state <= `DIV_FREE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:82: Define or directive not defined: '`DIV_END'\n `DIV_END: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:84: Define or directive not defined: '`TRUE'\n is_ended <= `TRUE;\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:85: Define or directive not defined: '`FALSE'\n if (is_start <= `FALSE) begin\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:86: Define or directive not defined: '`DIV_FREE'\n state <= `DIV_FREE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-div.v:87: Define or directive not defined: '`FALSE'\n is_ended <= `FALSE;\n ^~~~~~\n%Error: Exiting due to 36 error(s)\n" | 311,155 | module | module ex_div(
input wire clock,
input wire reset,
input wire is_signed,
input wire[`REGS_DATA_BUS] operand1,
input wire[`REGS_DATA_BUS] operand2,
input wire is_start,
input wire is_annul,
output reg is_ended,
output reg[`DOUBLE_REGS_DATA_BUS] result
);
wire[`EXT_REGS_DATA_BUS] div_temp;
reg[`EXT_DOUBLE_REGS_DATA_BUS] dividend;
reg[`REGS_DATA_BUS] divisor;
reg[5 : 0] cycle;
reg[1 : 0] state;
assign div_temp = {1'b0, dividend[63 : 32]} - {1'b0, divisor};
always @ (posedge clock) begin
if (reset == `ENABLE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0;
end else begin
case (state)
`DIV_FREE: begin
if (is_start == `TRUE && is_annul == `FALSE) begin
if (operand2 == 0) begin
state <= `DIV_BY_ZERO;
end else begin
state <= `DIV_ON;
cycle <= 6'b000000;
dividend = 0;
if (is_signed == `TRUE && operand1[31] == 1'b1) begin
dividend[32 : 1] <= ~operand1 + 1;
end else begin
dividend[32 : 1] <= operand1;
end
if (is_signed == `TRUE && operand2[31] == 1'b1) begin
divisor <= ~operand2 + 1;
end else begin
divisor <= operand2;
end
end
end else begin
is_ended <= `FALSE;
result <= 0;
end
end
`DIV_BY_ZERO: begin
dividend <= 0;
state <= `DIV_END;
end
`DIV_ON: begin
if (is_annul == `FALSE) begin
if (cycle != 6'b100000) begin
if (div_temp[32] == 1'b1) begin
dividend <= {dividend[63 : 0], 1'b0};
end else begin
dividend <= {div_temp[31 : 0], dividend[31 : 0], 1'b1};
end
cycle <= cycle + 1;
end else begin
if (is_signed && (operand1[31] ^ operand2[31])) begin
dividend[31 : 0] <= ~dividend[31 : 0] + 1;
end
if (is_signed && (operand1[31] ^ dividend[64])) begin
dividend[64 : 33] <= ~dividend[64 : 33] + 1;
end
state <= `DIV_END;
cycle <= 6'b000000;
end
end else begin
state <= `DIV_FREE;
end
end
`DIV_END: begin
result <= {dividend[64 : 33], dividend[31 : 0]};
is_ended <= `TRUE;
if (is_start <= `FALSE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0;
end
end
endcase
end
end
endmodule | module ex_div(
input wire clock,
input wire reset,
input wire is_signed,
input wire[`REGS_DATA_BUS] operand1,
input wire[`REGS_DATA_BUS] operand2,
input wire is_start,
input wire is_annul,
output reg is_ended,
output reg[`DOUBLE_REGS_DATA_BUS] result
); |
wire[`EXT_REGS_DATA_BUS] div_temp;
reg[`EXT_DOUBLE_REGS_DATA_BUS] dividend;
reg[`REGS_DATA_BUS] divisor;
reg[5 : 0] cycle;
reg[1 : 0] state;
assign div_temp = {1'b0, dividend[63 : 32]} - {1'b0, divisor};
always @ (posedge clock) begin
if (reset == `ENABLE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0;
end else begin
case (state)
`DIV_FREE: begin
if (is_start == `TRUE && is_annul == `FALSE) begin
if (operand2 == 0) begin
state <= `DIV_BY_ZERO;
end else begin
state <= `DIV_ON;
cycle <= 6'b000000;
dividend = 0;
if (is_signed == `TRUE && operand1[31] == 1'b1) begin
dividend[32 : 1] <= ~operand1 + 1;
end else begin
dividend[32 : 1] <= operand1;
end
if (is_signed == `TRUE && operand2[31] == 1'b1) begin
divisor <= ~operand2 + 1;
end else begin
divisor <= operand2;
end
end
end else begin
is_ended <= `FALSE;
result <= 0;
end
end
`DIV_BY_ZERO: begin
dividend <= 0;
state <= `DIV_END;
end
`DIV_ON: begin
if (is_annul == `FALSE) begin
if (cycle != 6'b100000) begin
if (div_temp[32] == 1'b1) begin
dividend <= {dividend[63 : 0], 1'b0};
end else begin
dividend <= {div_temp[31 : 0], dividend[31 : 0], 1'b1};
end
cycle <= cycle + 1;
end else begin
if (is_signed && (operand1[31] ^ operand2[31])) begin
dividend[31 : 0] <= ~dividend[31 : 0] + 1;
end
if (is_signed && (operand1[31] ^ dividend[64])) begin
dividend[64 : 33] <= ~dividend[64 : 33] + 1;
end
state <= `DIV_END;
cycle <= 6'b000000;
end
end else begin
state <= `DIV_FREE;
end
end
`DIV_END: begin
result <= {dividend[64 : 33], dividend[31 : 0]};
is_ended <= `TRUE;
if (is_start <= `FALSE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0;
end
end
endcase
end
end
endmodule | 0 |
141,273 | data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v | 94,422,424 | ex-mem-buffer.v | v | 84 | 116 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:7: Define or directive not defined: \'`SIGNAL_BUS\'\n input wire[`SIGNAL_BUS] stall,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`SIGNAL_BUS] stall,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_ADDR_BUS] ex_write_addr,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:10: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] ex_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] ex_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] ex_write_hi_data,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:14: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] ex_write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:15: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] ex_write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:17: Define or directive not defined: \'`DOUBLE_REGS_DATA_BUS\'\n input wire[`DOUBLE_REGS_DATA_BUS] ex_current_result,\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:18: Define or directive not defined: \'`CYCLE_BUS\'\n input wire[`CYCLE_BUS] ex_current_cycle,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:20: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n input wire[`ALU_OPERATOR_BUS] ex_alu_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:21: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] ex_alu_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:22: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] ex_ram_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_ADDR_BUS] mem_write_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:25: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] mem_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:26: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] mem_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] mem_write_hi_data,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:29: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] mem_write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:30: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] mem_write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:32: Define or directive not defined: \'`DOUBLE_REGS_DATA_BUS\'\n output reg[`DOUBLE_REGS_DATA_BUS] mem_last_result,\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:33: Define or directive not defined: \'`CYCLE_BUS\'\n output reg[`CYCLE_BUS] mem_last_cycle,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:35: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n output reg[`ALU_OPERATOR_BUS] mem_alu_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:36: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] mem_alu_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:37: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] mem_ram_addr\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:41: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:42: Define or directive not defined: \'`DISABLE\'\n mem_write_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:45: Define or directive not defined: \'`DISABLE\'\n mem_write_hilo_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:53: Define or directive not defined: \'`ENABLE\'\n end if (stall[3] == `ENABLE && stall[4] == `DISABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:53: Define or directive not defined: \'`DISABLE\'\n end if (stall[3] == `ENABLE && stall[4] == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:54: Define or directive not defined: \'`DISABLE\'\n mem_write_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:57: Define or directive not defined: \'`DISABLE\'\n mem_write_hilo_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex-mem-buffer.v:65: Define or directive not defined: \'`DISABLE\'\n end else if (stall[3] == `DISABLE) begin\n ^~~~~~~~\n%Error: Exiting due to 33 error(s)\n' | 311,156 | module | module ex_mem_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire ex_write_enable,
input wire[`REGS_ADDR_BUS] ex_write_addr,
input wire[`REGS_DATA_BUS] ex_write_data,
input wire ex_write_hilo_enable,
input wire[`REGS_DATA_BUS] ex_write_hi_data,
input wire[`REGS_DATA_BUS] ex_write_lo_data,
input wire[`DOUBLE_REGS_DATA_BUS] ex_current_result,
input wire[`CYCLE_BUS] ex_current_cycle,
input wire[`ALU_OPERATOR_BUS] ex_alu_operator,
input wire[`REGS_DATA_BUS] ex_alu_operand2,
input wire[`REGS_DATA_BUS] ex_ram_addr,
output reg mem_write_enable,
output reg[`REGS_ADDR_BUS] mem_write_addr,
output reg[`REGS_DATA_BUS] mem_write_data,
output reg mem_write_hilo_enable,
output reg[`REGS_DATA_BUS] mem_write_hi_data,
output reg[`REGS_DATA_BUS] mem_write_lo_data,
output reg[`DOUBLE_REGS_DATA_BUS] mem_last_result,
output reg[`CYCLE_BUS] mem_last_cycle,
output reg[`ALU_OPERATOR_BUS] mem_alu_operator,
output reg[`REGS_DATA_BUS] mem_alu_operand2,
output reg[`REGS_DATA_BUS] mem_ram_addr
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0;
mem_write_addr <= 0;
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0;
mem_write_lo_data <= 0;
mem_last_result <= 0;
mem_last_cycle <= 0;
mem_alu_operator <= 0;
mem_alu_operand2 <= 0;
mem_ram_addr <= 0;
end if (stall[3] == `ENABLE && stall[4] == `DISABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0;
mem_write_addr <= 0;
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0;
mem_write_lo_data <= 0;
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
mem_alu_operator <= 0;
mem_alu_operand2 <= 0;
mem_ram_addr <= 0;
end else if (stall[3] == `DISABLE) begin
mem_write_enable <= ex_write_enable;
mem_write_addr <= ex_write_addr;
mem_write_data <= ex_write_data;
mem_write_hilo_enable <= ex_write_hilo_enable;
mem_write_hi_data <= ex_write_hi_data;
mem_write_lo_data <= ex_write_lo_data;
mem_last_result <= 0;
mem_last_cycle <= 0;
mem_alu_operator <= ex_alu_operator;
mem_alu_operand2 <= ex_alu_operand2;
mem_ram_addr <= ex_ram_addr;
end else begin
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
end
end
endmodule | module ex_mem_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire ex_write_enable,
input wire[`REGS_ADDR_BUS] ex_write_addr,
input wire[`REGS_DATA_BUS] ex_write_data,
input wire ex_write_hilo_enable,
input wire[`REGS_DATA_BUS] ex_write_hi_data,
input wire[`REGS_DATA_BUS] ex_write_lo_data,
input wire[`DOUBLE_REGS_DATA_BUS] ex_current_result,
input wire[`CYCLE_BUS] ex_current_cycle,
input wire[`ALU_OPERATOR_BUS] ex_alu_operator,
input wire[`REGS_DATA_BUS] ex_alu_operand2,
input wire[`REGS_DATA_BUS] ex_ram_addr,
output reg mem_write_enable,
output reg[`REGS_ADDR_BUS] mem_write_addr,
output reg[`REGS_DATA_BUS] mem_write_data,
output reg mem_write_hilo_enable,
output reg[`REGS_DATA_BUS] mem_write_hi_data,
output reg[`REGS_DATA_BUS] mem_write_lo_data,
output reg[`DOUBLE_REGS_DATA_BUS] mem_last_result,
output reg[`CYCLE_BUS] mem_last_cycle,
output reg[`ALU_OPERATOR_BUS] mem_alu_operator,
output reg[`REGS_DATA_BUS] mem_alu_operand2,
output reg[`REGS_DATA_BUS] mem_ram_addr
); |
always @ (posedge clock) begin
if (reset == `ENABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0;
mem_write_addr <= 0;
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0;
mem_write_lo_data <= 0;
mem_last_result <= 0;
mem_last_cycle <= 0;
mem_alu_operator <= 0;
mem_alu_operand2 <= 0;
mem_ram_addr <= 0;
end if (stall[3] == `ENABLE && stall[4] == `DISABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0;
mem_write_addr <= 0;
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0;
mem_write_lo_data <= 0;
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
mem_alu_operator <= 0;
mem_alu_operand2 <= 0;
mem_ram_addr <= 0;
end else if (stall[3] == `DISABLE) begin
mem_write_enable <= ex_write_enable;
mem_write_addr <= ex_write_addr;
mem_write_data <= ex_write_data;
mem_write_hilo_enable <= ex_write_hilo_enable;
mem_write_hi_data <= ex_write_hi_data;
mem_write_lo_data <= ex_write_lo_data;
mem_last_result <= 0;
mem_last_cycle <= 0;
mem_alu_operator <= ex_alu_operator;
mem_alu_operand2 <= ex_alu_operand2;
mem_ram_addr <= ex_ram_addr;
end else begin
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
end
end
endmodule | 0 |
141,274 | data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v | 94,422,424 | ex.v | v | 421 | 192 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:6: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] operand_hi,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`REGS_DATA_BUS] operand_hi,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:7: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] operand_lo,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] wb_write_hi_data,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:10: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] wb_write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] wb_write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] mem_write_hi_data,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:14: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] mem_write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:15: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] mem_write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:17: Define or directive not defined: \'`DOUBLE_REGS_DATA_BUS\'\n input wire[`DOUBLE_REGS_DATA_BUS] ex_div_result,\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ALU_OPERATOR_BUS] operator,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:20: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n input wire[`ALU_OPERATOR_BUS] operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:21: Define or directive not defined: \'`ALU_CATEGORY_BUS\'\n input wire[`ALU_CATEGORY_BUS] category,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:22: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] operand1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:23: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:24: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] input_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`DOUBLE_REGS_DATA_BUS] last_result,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:27: Define or directive not defined: \'`DOUBLE_REGS_DATA_BUS\'\n input wire[`DOUBLE_REGS_DATA_BUS] last_result,\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:28: Define or directive not defined: \'`CYCLE_BUS\'\n input wire[`CYCLE_BUS] last_cycle,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:30: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] return_target,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] instruction,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:33: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] instruction,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:35: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] to_div_operand1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:36: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] to_div_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:38: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg to_div_is_signed,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg write_hilo_enable,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] write_hi_data,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:41: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:42: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:44: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:46: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] write_data,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:46: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:48: Define or directive not defined: \'`DOUBLE_REGS_DATA_BUS\'\n output reg[`DOUBLE_REGS_DATA_BUS] current_result,\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:49: Define or directive not defined: \'`CYCLE_BUS\'\n output reg[`CYCLE_BUS] current_cycle,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:53: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire[`ALU_OPERATOR_BUS] broadcast_alu_operator,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:53: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n output wire[`ALU_OPERATOR_BUS] broadcast_alu_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:54: Define or directive not defined: \'`REGS_DATA_BUS\'\n output wire[`REGS_DATA_BUS] broadcast_alu_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:55: Define or directive not defined: \'`REGS_DATA_BUS\'\n output wire[`REGS_DATA_BUS] broadcast_ram_addr\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:62: Define or directive not defined: \'`REGS_DATA_BUS\'\n reg[`REGS_DATA_BUS] logic_result;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`REGS_DATA_BUS] logic_result;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:63: Define or directive not defined: \'`REGS_DATA_BUS\'\n reg[`REGS_DATA_BUS] shift_result;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`REGS_DATA_BUS] shift_result;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:64: Define or directive not defined: \'`REGS_DATA_BUS\'\n reg[`REGS_DATA_BUS] move_result;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`REGS_DATA_BUS] move_result;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:65: Define or directive not defined: \'`REGS_DATA_BUS\'\n reg[`REGS_DATA_BUS] arithmetic_result;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`REGS_DATA_BUS] arithmetic_result;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:66: Define or directive not defined: \'`DOUBLE_REGS_DATA_BUS\'\n reg[`DOUBLE_REGS_DATA_BUS] mult_result;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`DOUBLE_REGS_DATA_BUS] mult_result;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/ex.v:68: Define or directive not defined: \'`REGS_DATA_BUS\'\n reg[`REGS_DATA_BUS] hi_result_0;\n ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 311,157 | module | module ex(
input wire reset,
input wire[`REGS_DATA_BUS] operand_hi,
input wire[`REGS_DATA_BUS] operand_lo,
input wire wb_write_hilo_enable,
input wire[`REGS_DATA_BUS] wb_write_hi_data,
input wire[`REGS_DATA_BUS] wb_write_lo_data,
input wire mem_write_hilo_enable,
input wire[`REGS_DATA_BUS] mem_write_hi_data,
input wire[`REGS_DATA_BUS] mem_write_lo_data,
input wire[`DOUBLE_REGS_DATA_BUS] ex_div_result,
input wire ex_div_is_ended,
input wire[`ALU_OPERATOR_BUS] operator,
input wire[`ALU_CATEGORY_BUS] category,
input wire[`REGS_DATA_BUS] operand1,
input wire[`REGS_DATA_BUS] operand2,
input wire[`REGS_ADDR_BUS] input_write_addr,
input wire input_write_enable,
input wire[`DOUBLE_REGS_DATA_BUS] last_result,
input wire[`CYCLE_BUS] last_cycle,
input wire[`REGS_DATA_BUS] return_target,
input wire is_curr_in_delayslot,
input wire[`REGS_DATA_BUS] instruction,
output reg[`REGS_DATA_BUS] to_div_operand1,
output reg[`REGS_DATA_BUS] to_div_operand2,
output reg to_div_is_start,
output reg to_div_is_signed,
output reg write_hilo_enable,
output reg[`REGS_DATA_BUS] write_hi_data,
output reg[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_ADDR_BUS] write_addr,
output reg write_enable,
output reg[`REGS_DATA_BUS] write_data,
output reg[`DOUBLE_REGS_DATA_BUS] current_result,
output reg[`CYCLE_BUS] current_cycle,
output reg stall_signal,
output wire[`ALU_OPERATOR_BUS] broadcast_alu_operator,
output wire[`REGS_DATA_BUS] broadcast_alu_operand2,
output wire[`REGS_DATA_BUS] broadcast_ram_addr
);
assign broadcast_alu_operator = operator;
assign broadcast_alu_operand2 = operand2;
assign broadcast_ram_addr = operand1 + {{16{instruction[15]}}, instruction[15 : 0]};
reg[`REGS_DATA_BUS] logic_result;
reg[`REGS_DATA_BUS] shift_result;
reg[`REGS_DATA_BUS] move_result;
reg[`REGS_DATA_BUS] arithmetic_result;
reg[`DOUBLE_REGS_DATA_BUS] mult_result;
reg[`REGS_DATA_BUS] hi_result_0;
reg[`REGS_DATA_BUS] lo_result_0;
reg[`REGS_DATA_BUS] hi_result_1;
reg[`REGS_DATA_BUS] lo_result_1;
wire is_overflow;
wire[`REGS_DATA_BUS] operand2_mux;
wire[`REGS_DATA_BUS] addition_sum;
wire[`REGS_DATA_BUS] operand1_not;
wire[`REGS_DATA_BUS] opdata1_mult;
wire[`REGS_DATA_BUS] opdata2_mult;
reg stall_signal_from_div;
reg stall_signal_from_mul;
assign operand2_mux = (operator == `OPERATOR_SUB
|| operator == `OPERATOR_SUBU
|| operator == `OPERATOR_SLT) ?
(~operand2) + 1 : operand2;
assign operand1_not = ~operand1;
assign addition_sum = operand1 + operand2_mux;
assign is_overflow = ((!operand1[31] && !operand2_mux[31]) && addition_sum[31])
|| (operand1[31] && operand2_mux[31]) && (!addition_sum[31]);
assign opdata1_mult = ((operator == `OPERATOR_MUL || operator == `OPERATOR_MULT || operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) && operand1[31]) ? (~operand1 + 1) : operand1;
assign opdata2_mult = ((operator == `OPERATOR_MUL || operator == `OPERATOR_MULT || operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) && operand2[31]) ? (~operand2 + 1) : operand2;
always @ (*) begin
if (reset == `ENABLE) begin
mult_result <= 0;
end else if (operator == `OPERATOR_MUL || operator == `OPERATOR_MULT
|| operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) begin
if (operand1[31] ^ operand2[31] == 1'b1) begin
mult_result <= ~(opdata1_mult * opdata2_mult) + 1;
end else begin
mult_result <= opdata1_mult * opdata2_mult;
end
end else begin
mult_result <= operand1 * operand2;
end
end
always @ (*) begin
stall_signal <= stall_signal_from_div || stall_signal_from_mul;
end
always @ (*) begin
if (reset == `ENABLE) begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
case (operator)
`OPERATOR_DIV: begin
if (ex_div_is_ended == `FALSE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `TRUE;
to_div_is_signed <= `TRUE;
stall_signal_from_div <= `ENABLE;
end else if (ex_div_is_ended == `TRUE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `FALSE;
to_div_is_signed <= `TRUE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end
end
`OPERATOR_DIVU: begin
if (ex_div_is_ended == `FALSE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `TRUE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `ENABLE;
end else if (ex_div_is_ended == `TRUE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
current_result <= 0;
current_cycle <= 0;
stall_signal_from_mul <= `DISABLE;
end else begin
case (operator)
`OPERATOR_MADD, `OPERATOR_MADDU: begin
if (last_cycle == 0) begin
current_result <= mult_result;
current_cycle <= 1;
{hi_result_1, lo_result_1} <= 0;
stall_signal_from_mul <= `ENABLE;
end else if (last_cycle == 1) begin
current_result <= 0;
current_cycle <= 2;
{hi_result_1, lo_result_1} <= last_result + {hi_result_0, lo_result_0};
stall_signal_from_mul <= `DISABLE;
end
end
`OPERATOR_MSUB, `OPERATOR_MSUBU: begin
if (last_cycle == 0) begin
current_result <= ~mult_result + 1;
current_cycle <= 1;
{hi_result_1, lo_result_1} <= 0;
stall_signal_from_mul <= `ENABLE;
end else if (last_cycle == 1) begin
current_result <= 0;
current_cycle <= 2;
{hi_result_1, lo_result_1} <= last_result + {hi_result_0, lo_result_0};
stall_signal_from_mul <= `DISABLE;
end
end
default: begin
current_result <= 0;
current_cycle <= 0;
stall_signal_from_mul <= `DISABLE;
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
arithmetic_result <= 0;
end else begin
case (operator)
`OPERATOR_SLT, `OPERATOR_SLTU: begin
arithmetic_result <=
((operand1[31] && !operand2[31])
|| (!operand1[31] && !operand2[31] && addition_sum[31])
|| (operand1[31] && operand2[31] && addition_sum[31]));
end
`OPERATOR_SLTU: begin
arithmetic_result <= (operand1 < operand2);
end
`OPERATOR_ADD, `OPERATOR_ADDU,
`OPERATOR_SUB, `OPERATOR_SUBU,
`OPERATOR_ADDI, `OPERATOR_ADDIU: begin
arithmetic_result <= addition_sum;
end
`OPERATOR_CLZ: begin
arithmetic_result <=
operand1[31] ? 0 : operand1[30] ? 1 : operand1[29] ? 2 :
operand1[28] ? 3 : operand1[27] ? 4 : operand1[26] ? 5 :
operand1[25] ? 6 : operand1[24] ? 7 : operand1[23] ? 8 :
operand1[22] ? 9 : operand1[21] ? 10 : operand1[20] ? 11 :
operand1[19] ? 12 : operand1[18] ? 13 : operand1[17] ? 14 :
operand1[16] ? 15 : operand1[15] ? 16 : operand1[14] ? 17 :
operand1[13] ? 18 : operand1[12] ? 19 : operand1[11] ? 20 :
operand1[10] ? 21 : operand1[9] ? 22 : operand1[8] ? 23 :
operand1[7] ? 24 : operand1[6] ? 25 : operand1[5] ? 26 :
operand1[4] ? 27 : operand1[3] ? 28 : operand1[2] ? 29 :
operand1[1] ? 30 : operand1[0] ? 31 : 32;
end
`OPERATOR_CLO: begin
arithmetic_result <=
operand1_not[31] ? 0 : operand1_not[30] ? 1 : operand1_not[29] ? 2 :
operand1_not[28] ? 3 : operand1_not[27] ? 4 : operand1_not[26] ? 5 :
operand1_not[25] ? 6 : operand1_not[24] ? 7 : operand1_not[23] ? 8 :
operand1_not[22] ? 9 : operand1_not[21] ? 10 : operand1_not[20] ? 11 :
operand1_not[19] ? 12 : operand1_not[18] ? 13 : operand1_not[17] ? 14 :
operand1_not[16] ? 15 : operand1_not[15] ? 16 : operand1_not[14] ? 17 :
operand1_not[13] ? 18 : operand1_not[12] ? 19 : operand1_not[11] ? 20 :
operand1_not[10] ? 21 : operand1_not[9] ? 22 : operand1_not[8] ? 23 :
operand1_not[7] ? 24 : operand1_not[6] ? 25 : operand1_not[5] ? 26 :
operand1_not[4] ? 27 : operand1_not[3] ? 28 : operand1_not[2] ? 29 :
operand1_not[1] ? 30 : operand1_not[0] ? 31 : 32;
end
default: begin
arithmetic_result <= 0;
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
{hi_result_0, lo_result_0} <= 0;
end else if (mem_write_hilo_enable == `ENABLE) begin
{hi_result_0, lo_result_0} <= {mem_write_hi_data, mem_write_lo_data};
end else if (wb_write_hilo_enable == `ENABLE) begin
{hi_result_0, lo_result_0} <= {wb_write_hi_data, wb_write_lo_data};
end else begin
{hi_result_0, lo_result_0} <= {operand_hi, operand_lo};
end
end
always @ (*) begin
if (reset == `ENABLE) begin
move_result <= 0;
end else begin
move_result <= 0;
case (operator)
`INST_MFHI_OPERATOR: begin
move_result <= hi_result_0;
end
`INST_MFLO_OPERATOR: begin
move_result <= lo_result_0;
end
`INST_MOVZ_OPERATOR: begin
move_result <= operand1;
end
`INST_MOVN_OPERATOR: begin
move_result <= operand1;
end
default: begin
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
logic_result <= 0;
end else begin
case (operator)
`OPERATOR_OR: begin
logic_result <= operand1 | operand2;
end
`OPERATOR_AND: begin
logic_result <= operand1 & operand2;
end
`OPERATOR_NOR: begin
logic_result <= ~(operand1 | operand2);
end
`OPERATOR_XOR: begin
logic_result <= operand1 ^ operand2;
end
default: begin
logic_result <= 0;
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
shift_result <= 0;
end else begin
case (operator)
`OPERATOR_SLL: begin
shift_result <= operand2 << operand1[4 : 0];
end
`OPERATOR_SRL: begin
shift_result <= operand2 >> operand1[4 : 0];
end
`OPERATOR_SRA: begin
shift_result <= ({32{operand2[31]}} << (6'd32 - {1'b0, operand1[4 : 0]}))
| operand2 >> operand1[4 : 0];
end
default: begin
shift_result <= 0;
end
endcase
end
end
always @ (*) begin
write_addr <= input_write_addr;
if ((operator == `OPERATOR_ADD || operator == `OPERATOR_ADDI
|| operator ==`OPERATOR_SUB) && is_overflow == 1'b1) begin
write_enable <= `DISABLE;
end else begin
write_enable <= input_write_enable;
end
case (category)
`CATEGORY_LOGIC: begin
write_data <= logic_result;
end
`CATEGORY_SHIFT: begin
write_data <= shift_result;
end
`CATEGORY_MOVE: begin
write_data <= move_result;
end
`CATEGORY_ARITHMETIC: begin
write_data <= arithmetic_result;
end
`CATEGORY_MULTIPLY: begin
write_data <= mult_result;
end
`CATEGORY_FORK: begin
write_data <= return_target;
end
default: begin
write_data <= 0;
end
endcase
end
always @ (*) begin
if (reset == `ENABLE) begin
write_hilo_enable <= `DISABLE;
write_hi_data <= 0;
write_lo_data <= 0;
end else if (operator == `OPERATOR_DIV || operator == `OPERATOR_DIVU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= ex_div_result[63 : 32];
write_lo_data <= ex_div_result[31 : 0];
end else if (operator == `OPERATOR_MSUB || operator == `OPERATOR_MSUBU
|| operator == `OPERATOR_MADD || operator == `OPERATOR_MADDU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= hi_result_1;
write_lo_data <= lo_result_1;
end else if (operator == `OPERATOR_MULT || operator == `OPERATOR_MULTU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= mult_result[63 : 32];
write_lo_data <= mult_result[31 : 0];
end else if (operator == `OPERATOR_MTHI) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= operand1;
write_lo_data <= lo_result_0;
end else if (operator == `OPERATOR_MTLO) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= hi_result_0;
write_lo_data <= operand1;
end else begin
write_hilo_enable <= `DISABLE;
write_hi_data <= 0;
write_lo_data <= 0;
end
end
endmodule | module ex(
input wire reset,
input wire[`REGS_DATA_BUS] operand_hi,
input wire[`REGS_DATA_BUS] operand_lo,
input wire wb_write_hilo_enable,
input wire[`REGS_DATA_BUS] wb_write_hi_data,
input wire[`REGS_DATA_BUS] wb_write_lo_data,
input wire mem_write_hilo_enable,
input wire[`REGS_DATA_BUS] mem_write_hi_data,
input wire[`REGS_DATA_BUS] mem_write_lo_data,
input wire[`DOUBLE_REGS_DATA_BUS] ex_div_result,
input wire ex_div_is_ended,
input wire[`ALU_OPERATOR_BUS] operator,
input wire[`ALU_CATEGORY_BUS] category,
input wire[`REGS_DATA_BUS] operand1,
input wire[`REGS_DATA_BUS] operand2,
input wire[`REGS_ADDR_BUS] input_write_addr,
input wire input_write_enable,
input wire[`DOUBLE_REGS_DATA_BUS] last_result,
input wire[`CYCLE_BUS] last_cycle,
input wire[`REGS_DATA_BUS] return_target,
input wire is_curr_in_delayslot,
input wire[`REGS_DATA_BUS] instruction,
output reg[`REGS_DATA_BUS] to_div_operand1,
output reg[`REGS_DATA_BUS] to_div_operand2,
output reg to_div_is_start,
output reg to_div_is_signed,
output reg write_hilo_enable,
output reg[`REGS_DATA_BUS] write_hi_data,
output reg[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_ADDR_BUS] write_addr,
output reg write_enable,
output reg[`REGS_DATA_BUS] write_data,
output reg[`DOUBLE_REGS_DATA_BUS] current_result,
output reg[`CYCLE_BUS] current_cycle,
output reg stall_signal,
output wire[`ALU_OPERATOR_BUS] broadcast_alu_operator,
output wire[`REGS_DATA_BUS] broadcast_alu_operand2,
output wire[`REGS_DATA_BUS] broadcast_ram_addr
); |
assign broadcast_alu_operator = operator;
assign broadcast_alu_operand2 = operand2;
assign broadcast_ram_addr = operand1 + {{16{instruction[15]}}, instruction[15 : 0]};
reg[`REGS_DATA_BUS] logic_result;
reg[`REGS_DATA_BUS] shift_result;
reg[`REGS_DATA_BUS] move_result;
reg[`REGS_DATA_BUS] arithmetic_result;
reg[`DOUBLE_REGS_DATA_BUS] mult_result;
reg[`REGS_DATA_BUS] hi_result_0;
reg[`REGS_DATA_BUS] lo_result_0;
reg[`REGS_DATA_BUS] hi_result_1;
reg[`REGS_DATA_BUS] lo_result_1;
wire is_overflow;
wire[`REGS_DATA_BUS] operand2_mux;
wire[`REGS_DATA_BUS] addition_sum;
wire[`REGS_DATA_BUS] operand1_not;
wire[`REGS_DATA_BUS] opdata1_mult;
wire[`REGS_DATA_BUS] opdata2_mult;
reg stall_signal_from_div;
reg stall_signal_from_mul;
assign operand2_mux = (operator == `OPERATOR_SUB
|| operator == `OPERATOR_SUBU
|| operator == `OPERATOR_SLT) ?
(~operand2) + 1 : operand2;
assign operand1_not = ~operand1;
assign addition_sum = operand1 + operand2_mux;
assign is_overflow = ((!operand1[31] && !operand2_mux[31]) && addition_sum[31])
|| (operand1[31] && operand2_mux[31]) && (!addition_sum[31]);
assign opdata1_mult = ((operator == `OPERATOR_MUL || operator == `OPERATOR_MULT || operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) && operand1[31]) ? (~operand1 + 1) : operand1;
assign opdata2_mult = ((operator == `OPERATOR_MUL || operator == `OPERATOR_MULT || operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) && operand2[31]) ? (~operand2 + 1) : operand2;
always @ (*) begin
if (reset == `ENABLE) begin
mult_result <= 0;
end else if (operator == `OPERATOR_MUL || operator == `OPERATOR_MULT
|| operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) begin
if (operand1[31] ^ operand2[31] == 1'b1) begin
mult_result <= ~(opdata1_mult * opdata2_mult) + 1;
end else begin
mult_result <= opdata1_mult * opdata2_mult;
end
end else begin
mult_result <= operand1 * operand2;
end
end
always @ (*) begin
stall_signal <= stall_signal_from_div || stall_signal_from_mul;
end
always @ (*) begin
if (reset == `ENABLE) begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
case (operator)
`OPERATOR_DIV: begin
if (ex_div_is_ended == `FALSE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `TRUE;
to_div_is_signed <= `TRUE;
stall_signal_from_div <= `ENABLE;
end else if (ex_div_is_ended == `TRUE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `FALSE;
to_div_is_signed <= `TRUE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end
end
`OPERATOR_DIVU: begin
if (ex_div_is_ended == `FALSE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `TRUE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `ENABLE;
end else if (ex_div_is_ended == `TRUE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0;
to_div_operand2 <= 0;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
current_result <= 0;
current_cycle <= 0;
stall_signal_from_mul <= `DISABLE;
end else begin
case (operator)
`OPERATOR_MADD, `OPERATOR_MADDU: begin
if (last_cycle == 0) begin
current_result <= mult_result;
current_cycle <= 1;
{hi_result_1, lo_result_1} <= 0;
stall_signal_from_mul <= `ENABLE;
end else if (last_cycle == 1) begin
current_result <= 0;
current_cycle <= 2;
{hi_result_1, lo_result_1} <= last_result + {hi_result_0, lo_result_0};
stall_signal_from_mul <= `DISABLE;
end
end
`OPERATOR_MSUB, `OPERATOR_MSUBU: begin
if (last_cycle == 0) begin
current_result <= ~mult_result + 1;
current_cycle <= 1;
{hi_result_1, lo_result_1} <= 0;
stall_signal_from_mul <= `ENABLE;
end else if (last_cycle == 1) begin
current_result <= 0;
current_cycle <= 2;
{hi_result_1, lo_result_1} <= last_result + {hi_result_0, lo_result_0};
stall_signal_from_mul <= `DISABLE;
end
end
default: begin
current_result <= 0;
current_cycle <= 0;
stall_signal_from_mul <= `DISABLE;
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
arithmetic_result <= 0;
end else begin
case (operator)
`OPERATOR_SLT, `OPERATOR_SLTU: begin
arithmetic_result <=
((operand1[31] && !operand2[31])
|| (!operand1[31] && !operand2[31] && addition_sum[31])
|| (operand1[31] && operand2[31] && addition_sum[31]));
end
`OPERATOR_SLTU: begin
arithmetic_result <= (operand1 < operand2);
end
`OPERATOR_ADD, `OPERATOR_ADDU,
`OPERATOR_SUB, `OPERATOR_SUBU,
`OPERATOR_ADDI, `OPERATOR_ADDIU: begin
arithmetic_result <= addition_sum;
end
`OPERATOR_CLZ: begin
arithmetic_result <=
operand1[31] ? 0 : operand1[30] ? 1 : operand1[29] ? 2 :
operand1[28] ? 3 : operand1[27] ? 4 : operand1[26] ? 5 :
operand1[25] ? 6 : operand1[24] ? 7 : operand1[23] ? 8 :
operand1[22] ? 9 : operand1[21] ? 10 : operand1[20] ? 11 :
operand1[19] ? 12 : operand1[18] ? 13 : operand1[17] ? 14 :
operand1[16] ? 15 : operand1[15] ? 16 : operand1[14] ? 17 :
operand1[13] ? 18 : operand1[12] ? 19 : operand1[11] ? 20 :
operand1[10] ? 21 : operand1[9] ? 22 : operand1[8] ? 23 :
operand1[7] ? 24 : operand1[6] ? 25 : operand1[5] ? 26 :
operand1[4] ? 27 : operand1[3] ? 28 : operand1[2] ? 29 :
operand1[1] ? 30 : operand1[0] ? 31 : 32;
end
`OPERATOR_CLO: begin
arithmetic_result <=
operand1_not[31] ? 0 : operand1_not[30] ? 1 : operand1_not[29] ? 2 :
operand1_not[28] ? 3 : operand1_not[27] ? 4 : operand1_not[26] ? 5 :
operand1_not[25] ? 6 : operand1_not[24] ? 7 : operand1_not[23] ? 8 :
operand1_not[22] ? 9 : operand1_not[21] ? 10 : operand1_not[20] ? 11 :
operand1_not[19] ? 12 : operand1_not[18] ? 13 : operand1_not[17] ? 14 :
operand1_not[16] ? 15 : operand1_not[15] ? 16 : operand1_not[14] ? 17 :
operand1_not[13] ? 18 : operand1_not[12] ? 19 : operand1_not[11] ? 20 :
operand1_not[10] ? 21 : operand1_not[9] ? 22 : operand1_not[8] ? 23 :
operand1_not[7] ? 24 : operand1_not[6] ? 25 : operand1_not[5] ? 26 :
operand1_not[4] ? 27 : operand1_not[3] ? 28 : operand1_not[2] ? 29 :
operand1_not[1] ? 30 : operand1_not[0] ? 31 : 32;
end
default: begin
arithmetic_result <= 0;
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
{hi_result_0, lo_result_0} <= 0;
end else if (mem_write_hilo_enable == `ENABLE) begin
{hi_result_0, lo_result_0} <= {mem_write_hi_data, mem_write_lo_data};
end else if (wb_write_hilo_enable == `ENABLE) begin
{hi_result_0, lo_result_0} <= {wb_write_hi_data, wb_write_lo_data};
end else begin
{hi_result_0, lo_result_0} <= {operand_hi, operand_lo};
end
end
always @ (*) begin
if (reset == `ENABLE) begin
move_result <= 0;
end else begin
move_result <= 0;
case (operator)
`INST_MFHI_OPERATOR: begin
move_result <= hi_result_0;
end
`INST_MFLO_OPERATOR: begin
move_result <= lo_result_0;
end
`INST_MOVZ_OPERATOR: begin
move_result <= operand1;
end
`INST_MOVN_OPERATOR: begin
move_result <= operand1;
end
default: begin
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
logic_result <= 0;
end else begin
case (operator)
`OPERATOR_OR: begin
logic_result <= operand1 | operand2;
end
`OPERATOR_AND: begin
logic_result <= operand1 & operand2;
end
`OPERATOR_NOR: begin
logic_result <= ~(operand1 | operand2);
end
`OPERATOR_XOR: begin
logic_result <= operand1 ^ operand2;
end
default: begin
logic_result <= 0;
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
shift_result <= 0;
end else begin
case (operator)
`OPERATOR_SLL: begin
shift_result <= operand2 << operand1[4 : 0];
end
`OPERATOR_SRL: begin
shift_result <= operand2 >> operand1[4 : 0];
end
`OPERATOR_SRA: begin
shift_result <= ({32{operand2[31]}} << (6'd32 - {1'b0, operand1[4 : 0]}))
| operand2 >> operand1[4 : 0];
end
default: begin
shift_result <= 0;
end
endcase
end
end
always @ (*) begin
write_addr <= input_write_addr;
if ((operator == `OPERATOR_ADD || operator == `OPERATOR_ADDI
|| operator ==`OPERATOR_SUB) && is_overflow == 1'b1) begin
write_enable <= `DISABLE;
end else begin
write_enable <= input_write_enable;
end
case (category)
`CATEGORY_LOGIC: begin
write_data <= logic_result;
end
`CATEGORY_SHIFT: begin
write_data <= shift_result;
end
`CATEGORY_MOVE: begin
write_data <= move_result;
end
`CATEGORY_ARITHMETIC: begin
write_data <= arithmetic_result;
end
`CATEGORY_MULTIPLY: begin
write_data <= mult_result;
end
`CATEGORY_FORK: begin
write_data <= return_target;
end
default: begin
write_data <= 0;
end
endcase
end
always @ (*) begin
if (reset == `ENABLE) begin
write_hilo_enable <= `DISABLE;
write_hi_data <= 0;
write_lo_data <= 0;
end else if (operator == `OPERATOR_DIV || operator == `OPERATOR_DIVU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= ex_div_result[63 : 32];
write_lo_data <= ex_div_result[31 : 0];
end else if (operator == `OPERATOR_MSUB || operator == `OPERATOR_MSUBU
|| operator == `OPERATOR_MADD || operator == `OPERATOR_MADDU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= hi_result_1;
write_lo_data <= lo_result_1;
end else if (operator == `OPERATOR_MULT || operator == `OPERATOR_MULTU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= mult_result[63 : 32];
write_lo_data <= mult_result[31 : 0];
end else if (operator == `OPERATOR_MTHI) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= operand1;
write_lo_data <= lo_result_0;
end else if (operator == `OPERATOR_MTLO) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= hi_result_0;
write_lo_data <= operand1;
end else begin
write_hilo_enable <= `DISABLE;
write_hi_data <= 0;
write_lo_data <= 0;
end
end
endmodule | 0 |
141,275 | data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v | 94,422,424 | id-ex-buffer.v | v | 74 | 99 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:7: Define or directive not defined: \'`SIGNAL_BUS\'\n input wire[`SIGNAL_BUS] stall,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`SIGNAL_BUS] stall,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:9: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n input wire[`ALU_OPERATOR_BUS] id_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:10: Define or directive not defined: \'`ALU_CATEGORY_BUS\'\n input wire[`ALU_CATEGORY_BUS] id_category,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] id_operand1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:12: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] id_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:13: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] id_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] id_return_target,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:16: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] id_return_target,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire input_is_next_in_delayslot,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] id_instruction,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:21: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] id_instruction,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:23: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n output reg[`ALU_OPERATOR_BUS] ex_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:24: Define or directive not defined: \'`ALU_CATEGORY_BUS\'\n output reg[`ALU_CATEGORY_BUS] ex_category,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:25: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] ex_operand1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:26: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] ex_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:27: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] ex_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] ex_return_target,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:30: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] ex_return_target,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:32: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg is_curr_in_delayslot,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] ex_instruction\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:34: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] ex_instruction\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:38: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:44: Define or directive not defined: \'`DISABLE\'\n ex_write_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:46: Define or directive not defined: \'`FALSE\'\n ex_is_curr_in_delayslot <= `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:47: Define or directive not defined: \'`FALSE\'\n is_curr_in_delayslot <= `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:49: Define or directive not defined: \'`ENABLE\'\n end else if (stall[2] == `ENABLE && stall[3] == `DISABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:49: Define or directive not defined: \'`DISABLE\'\n end else if (stall[2] == `ENABLE && stall[3] == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:55: Define or directive not defined: \'`DISABLE\'\n ex_write_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:57: Define or directive not defined: \'`FALSE\'\n ex_is_curr_in_delayslot <= `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id-ex-buffer.v:59: Define or directive not defined: \'`DISABLE\'\n end else if (stall[2] == `DISABLE) begin\n ^~~~~~~~\n%Error: Exiting due to 32 error(s)\n' | 311,158 | module | module id_ex_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`ALU_OPERATOR_BUS] id_operator,
input wire[`ALU_CATEGORY_BUS] id_category,
input wire[`REGS_DATA_BUS] id_operand1,
input wire[`REGS_DATA_BUS] id_operand2,
input wire[`REGS_ADDR_BUS] id_write_addr,
input wire id_write_enable,
input wire[`REGS_DATA_BUS] id_return_target,
input wire id_is_curr_in_delayslot,
input wire input_is_next_in_delayslot,
input wire[`REGS_DATA_BUS] id_instruction,
output reg[`ALU_OPERATOR_BUS] ex_operator,
output reg[`ALU_CATEGORY_BUS] ex_category,
output reg[`REGS_DATA_BUS] ex_operand1,
output reg[`REGS_DATA_BUS] ex_operand2,
output reg[`REGS_ADDR_BUS] ex_write_addr,
output reg ex_write_enable,
output reg[`REGS_DATA_BUS] ex_return_target,
output reg ex_is_curr_in_delayslot,
output reg is_curr_in_delayslot,
output reg[`REGS_DATA_BUS] ex_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
ex_operator <= 0;
ex_category <= 0;
ex_operand1 <= 0;
ex_operand2 <= 0;
ex_write_addr <= 0;
ex_write_enable <= `DISABLE;
ex_return_target <= 0;
ex_is_curr_in_delayslot <= `FALSE;
is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0;
end else if (stall[2] == `ENABLE && stall[3] == `DISABLE) begin
ex_operator <= 0;
ex_category <= 0;
ex_operand1 <= 0;
ex_operand2 <= 0;
ex_write_addr <= 0;
ex_write_enable <= `DISABLE;
ex_return_target <= 0;
ex_is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0;
end else if (stall[2] == `DISABLE) begin
ex_operator <= id_operator;
ex_category <= id_category;
ex_operand1 <= id_operand1;
ex_operand2 <= id_operand2;
ex_write_addr <= id_write_addr;
ex_write_enable <= id_write_enable;
ex_return_target <= id_return_target;
ex_is_curr_in_delayslot <= id_is_curr_in_delayslot;
is_curr_in_delayslot <= input_is_next_in_delayslot;
ex_instruction <= id_instruction;
end
end
endmodule | module id_ex_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`ALU_OPERATOR_BUS] id_operator,
input wire[`ALU_CATEGORY_BUS] id_category,
input wire[`REGS_DATA_BUS] id_operand1,
input wire[`REGS_DATA_BUS] id_operand2,
input wire[`REGS_ADDR_BUS] id_write_addr,
input wire id_write_enable,
input wire[`REGS_DATA_BUS] id_return_target,
input wire id_is_curr_in_delayslot,
input wire input_is_next_in_delayslot,
input wire[`REGS_DATA_BUS] id_instruction,
output reg[`ALU_OPERATOR_BUS] ex_operator,
output reg[`ALU_CATEGORY_BUS] ex_category,
output reg[`REGS_DATA_BUS] ex_operand1,
output reg[`REGS_DATA_BUS] ex_operand2,
output reg[`REGS_ADDR_BUS] ex_write_addr,
output reg ex_write_enable,
output reg[`REGS_DATA_BUS] ex_return_target,
output reg ex_is_curr_in_delayslot,
output reg is_curr_in_delayslot,
output reg[`REGS_DATA_BUS] ex_instruction
); |
always @ (posedge clock) begin
if (reset == `ENABLE) begin
ex_operator <= 0;
ex_category <= 0;
ex_operand1 <= 0;
ex_operand2 <= 0;
ex_write_addr <= 0;
ex_write_enable <= `DISABLE;
ex_return_target <= 0;
ex_is_curr_in_delayslot <= `FALSE;
is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0;
end else if (stall[2] == `ENABLE && stall[3] == `DISABLE) begin
ex_operator <= 0;
ex_category <= 0;
ex_operand1 <= 0;
ex_operand2 <= 0;
ex_write_addr <= 0;
ex_write_enable <= `DISABLE;
ex_return_target <= 0;
ex_is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0;
end else if (stall[2] == `DISABLE) begin
ex_operator <= id_operator;
ex_category <= id_category;
ex_operand1 <= id_operand1;
ex_operand2 <= id_operand2;
ex_write_addr <= id_write_addr;
ex_write_enable <= id_write_enable;
ex_return_target <= id_return_target;
ex_is_curr_in_delayslot <= id_is_curr_in_delayslot;
is_curr_in_delayslot <= input_is_next_in_delayslot;
ex_instruction <= id_instruction;
end
end
endmodule | 0 |
141,276 | data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v | 94,422,424 | id.v | v | 818 | 115 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:6: Define or directive not defined: \'`INST_ADDR_BUS\'\n input wire[`INST_ADDR_BUS] program_counter,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`INST_ADDR_BUS] program_counter,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:7: Define or directive not defined: \'`INST_DATA_BUS\'\n input wire[`INST_DATA_BUS] instruction,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_ADDR_BUS] ex_write_addr,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:10: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] ex_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] ex_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_ADDR_BUS] mem_write_addr,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:14: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] mem_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:15: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] mem_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:17: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] read_result1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:18: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] read_result2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ALU_OPERATOR_BUS] ex_alu_operator,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:22: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n input wire[`ALU_OPERATOR_BUS] ex_alu_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:24: Define or directive not defined: \'`REGS_DATA_BUS\'\n output wire[`REGS_DATA_BUS] broadcast_instruction,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg is_next_in_delayslot,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg branch_signal,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] branch_target,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:29: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] branch_target,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:30: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] return_target,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg read_enable2,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_ADDR_BUS] read_addr1,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:34: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] read_addr1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:35: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] read_addr2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:37: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n output reg[`ALU_OPERATOR_BUS] alu_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:38: Define or directive not defined: \'`ALU_CATEGORY_BUS\'\n output reg[`ALU_CATEGORY_BUS] alu_category,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:39: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] alu_operand1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:40: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] alu_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_ADDR_BUS] write_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:43: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:54: syntax error, unexpected assign\n assign pre_inst_is_load = (ex_alu_operator == `OPERATOR_LB || ex_alu_operator == `OPERATOR_LBU\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:54: Define or directive not defined: \'`OPERATOR_LB\'\n assign pre_inst_is_load = (ex_alu_operator == `OPERATOR_LB || ex_alu_operator == `OPERATOR_LBU\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:54: Define or directive not defined: \'`OPERATOR_LBU\'\n assign pre_inst_is_load = (ex_alu_operator == `OPERATOR_LB || ex_alu_operator == `OPERATOR_LBU\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:55: Define or directive not defined: \'`OPERATOR_LH\'\n || ex_alu_operator == `OPERATOR_LH || ex_alu_operator == `OPERATOR_LHU\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:55: Define or directive not defined: \'`OPERATOR_LHU\'\n || ex_alu_operator == `OPERATOR_LH || ex_alu_operator == `OPERATOR_LHU\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:56: Define or directive not defined: \'`OPERATOR_LW\'\n || ex_alu_operator == `OPERATOR_LW || ex_alu_operator == `OPERATOR_LWR\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:56: Define or directive not defined: \'`OPERATOR_LWR\'\n || ex_alu_operator == `OPERATOR_LW || ex_alu_operator == `OPERATOR_LWR\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:57: Define or directive not defined: \'`OPERATOR_LWL\'\n || ex_alu_operator == `OPERATOR_LWL) ? `TRUE : `FALSE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:57: Define or directive not defined: \'`TRUE\'\n || ex_alu_operator == `OPERATOR_LWL) ? `TRUE : `FALSE;\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:57: Define or directive not defined: \'`FALSE\'\n || ex_alu_operator == `OPERATOR_LWL) ? `TRUE : `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:59: Define or directive not defined: \'`REGS_DATA_BUS\'\n reg[`REGS_DATA_BUS] imm;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`REGS_DATA_BUS] imm;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:62: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] pc_plus_8;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] pc_plus_8;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:63: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] pc_plus_4;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] pc_plus_4;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:65: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] imm_sll2_signed_next;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] imm_sll2_signed_next;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:73: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/id.v:74: Define or directive not defined: \'`INST_NOP_OPERATOR\'\n alu_operator <= `INST_NOP_OPERATOR;\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 311,159 | module | module id(
input wire reset,
input wire[`INST_ADDR_BUS] program_counter,
input wire[`INST_DATA_BUS] instruction,
input wire ex_write_enable,
input wire[`REGS_ADDR_BUS] ex_write_addr,
input wire[`REGS_DATA_BUS] ex_write_data,
input wire mem_write_enable,
input wire[`REGS_ADDR_BUS] mem_write_addr,
input wire[`REGS_DATA_BUS] mem_write_data,
input wire[`REGS_DATA_BUS] read_result1,
input wire[`REGS_DATA_BUS] read_result2,
input wire input_is_curr_in_delayslot,
input wire[`ALU_OPERATOR_BUS] ex_alu_operator,
output wire[`REGS_DATA_BUS] broadcast_instruction,
output reg is_curr_in_delayslot,
output reg is_next_in_delayslot,
output reg branch_signal,
output reg[`REGS_DATA_BUS] branch_target,
output reg[`REGS_DATA_BUS] return_target,
output reg read_enable1,
output reg read_enable2,
output reg[`REGS_ADDR_BUS] read_addr1,
output reg[`REGS_ADDR_BUS] read_addr2,
output reg[`ALU_OPERATOR_BUS] alu_operator,
output reg[`ALU_CATEGORY_BUS] alu_category,
output reg[`REGS_DATA_BUS] alu_operand1,
output reg[`REGS_DATA_BUS] alu_operand2,
output reg write_enable,
output reg[`REGS_ADDR_BUS] write_addr,
output wire stall_signal
);
assign broadcast_instruction = instruction;
reg stall_signal_from_reg1_load_relate;
reg stall_signal_from_reg2_load_relate;
wire pre_inst_is_load;
assign pre_inst_is_load = (ex_alu_operator == `OPERATOR_LB || ex_alu_operator == `OPERATOR_LBU
|| ex_alu_operator == `OPERATOR_LH || ex_alu_operator == `OPERATOR_LHU
|| ex_alu_operator == `OPERATOR_LW || ex_alu_operator == `OPERATOR_LWR
|| ex_alu_operator == `OPERATOR_LWL) ? `TRUE : `FALSE;
reg[`REGS_DATA_BUS] imm;
reg validality;
wire[`REGS_DATA_BUS] pc_plus_8;
wire[`REGS_DATA_BUS] pc_plus_4;
wire[`REGS_DATA_BUS] imm_sll2_signed_next;
assign pc_plus_8 = program_counter + 8;
assign pc_plus_4 = program_counter + 4;
assign imm_sll2_signed_next = {{14{instruction[15]}}, instruction[15 : 0], 2'b00};
always @ (*) begin
if (reset == `ENABLE) begin
alu_operator <= `INST_NOP_OPERATOR;
alu_category <= `INST_NOP_CATEGORY;
write_addr <= 0;
write_enable <= `DISABLE;
validality <= `VALID;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
read_addr1 <= 0;
read_addr2 <= 0;
imm <= 0;
return_target <= 0;
branch_target <= 0;
branch_signal <= `DISABLE;
is_next_in_delayslot <= `FALSE;
end else begin
alu_operator <= `INST_NOP_OPERATOR;
alu_category <= `INST_NOP_CATEGORY;
write_enable <= `DISABLE;
write_addr <= instruction[15 : 11];
validality <= `INVALID;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
read_addr1 <= instruction[25 : 21];
read_addr2 <= instruction[20 : 16];
imm <= 0;
return_target <= 0;
branch_target <= 0;
branch_signal <= `DISABLE;
is_next_in_delayslot <= `FALSE;
case (instruction[31 : 26])
6'b000000: begin
if (instruction[10 : 6] == 5'b00000) begin
case (instruction[5 : 0])
`INST_OR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_OR_OPERATOR;
alu_category <= `INST_OR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_AND_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_AND_OPERATOR;
alu_category <= `INST_AND_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_XOR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_XOR_OPERATOR;
alu_category <= `INST_XOR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_NOR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_NOR_OPERATOR;
alu_category <= `INST_NOR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SLLV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLLV_OPERATOR;
alu_category <= `INST_SLLV_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SRLV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRLV_OPERATOR;
alu_category <= `INST_SRLV_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SRAV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRAV_OPERATOR;
alu_category <= `INST_SRAV_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SYNC_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SYNC_OPERATOR;
alu_category <= `INST_SYNC_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MFHI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MFHI_OPERATOR;
alu_category <= `INST_MFHI_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MFLO_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MFLO_OPERATOR;
alu_category <= `INST_MFLO_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MTHI_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MTHI_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MTLO_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MTLO_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MOVN_ID: begin
if (alu_operand2 != 0) begin
write_enable <= `ENABLE;
end else begin
write_enable <= `DISABLE;
end
alu_operator <= `INST_MOVN_OPERATOR;
alu_category <= `INST_MOVN_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MOVZ_ID: begin
if (alu_operand2 == 0) begin
write_enable <= `ENABLE;
end else begin
write_enable <= `DISABLE;
end
alu_operator <= `INST_MOVZ_OPERATOR;
alu_category <= `INST_MOVZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SLT_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLT_OPERATOR;
alu_category <= `INST_SLT_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SLTU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLTU_OPERATOR;
alu_category <= `INST_SLTU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_ADD_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADD_OPERATOR;
alu_category <= `INST_ADD_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_ADDU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADDU_OPERATOR;
alu_category <= `INST_ADDU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SUB_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SUB_OPERATOR;
alu_category <= `INST_SUB_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SUBU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SUBU_OPERATOR;
alu_category <= `INST_SUBU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MULT_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MULT_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MULTU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MULTU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_DIV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_DIV_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_DIVU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_DIVU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_JR_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_JR_OPERATOR;
alu_category <= `INST_JR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
return_target <= 0;
branch_target <= alu_operand1;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
`INST_JALR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_JALR_OPERATOR;
alu_category <= `INST_JALR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[15 : 11];
return_target <= pc_plus_8;
branch_target <= alu_operand1;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
default: begin
end
endcase
end
end
6'b000001: begin
case (instruction[20 : 16])
`INST_BGEZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BGEZ_OPERATOR;
alu_category <= `INST_BGEZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (!alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BGEZAL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_BGEZAL_OPERATOR;
alu_category <= `INST_BGEZAL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
return_target <= pc_plus_8;
write_addr <= 5'b11111;
validality <= `VALID;
if (!alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BLTZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BLTZ_OPERATOR;
alu_category <= `INST_BLTZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BLTZAL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_BLTZAL_OPERATOR;
alu_category <= `INST_BLTZAL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
return_target <= pc_plus_8;
write_addr <= 5'b11111;
validality <= `VALID;
if (alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
endcase
end
6'b011100: begin
case (instruction[5 : 0])
`INST_CLZ_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_CLZ_OPERATOR;
alu_category <= `INST_CLZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_CLO_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_CLO_OPERATOR;
alu_category <= `INST_CLO_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MUL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MUL_OPERATOR;
alu_category <= `INST_MUL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MADD_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MADD_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MADDU_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MADDU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MSUB_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MSUB_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MSUBU_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MSUBU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
default: begin
end
endcase
end
`INST_LB_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LB_OPERATOR;
alu_category <= `INST_LB_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LBU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LBU_OPERATOR;
alu_category <= `INST_LBU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LH_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LH_OPERATOR;
alu_category <= `INST_LH_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LHU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LHU_OPERATOR;
alu_category <= `INST_LHU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LW_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LW_OPERATOR;
alu_category <= `INST_LW_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LWL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LWL_OPERATOR;
alu_category <= `INST_LWL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LWR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LWR_OPERATOR;
alu_category <= `INST_LWR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_SB_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SB_OPERATOR;
alu_category <= `INST_SB_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SH_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SH_OPERATOR;
alu_category <= `INST_SH_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SW_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SW_OPERATOR;
alu_category <= `INST_SW_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SWL_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SWL_OPERATOR;
alu_category <= `INST_SWL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SWR_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SWR_OPERATOR;
alu_category <= `INST_SWR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_J_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_J_OPERATOR;
alu_category <= `INST_J_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
return_target <= 0;
branch_signal <= `ENABLE;
branch_target <= {pc_plus_4[31 : 28], instruction[25 : 0], 2'b00};
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
`INST_JAL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_JAL_OPERATOR;
alu_category <= `INST_JAL_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
write_addr <= 5'b11111;
return_target <= pc_plus_8;
branch_signal <= `ENABLE;
branch_target <= {pc_plus_4[31 : 28], instruction[25 : 0], 2'b00};
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
`INST_BEQ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BEQ_OPERATOR;
alu_category <= `INST_BEQ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
if (alu_operand1 == alu_operand2) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BGTZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BGTZ_OPERATOR;
alu_category <= `INST_BGTZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (!alu_operand1[31] && alu_operand1 != 0) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BLEZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BLEZ_OPERATOR;
alu_category <= `INST_BLEZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (alu_operand1[31] || alu_operand1 == 0) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BNE_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BNE_OPERATOR;
alu_category <= `INST_BNE_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
if (alu_operand1 != alu_operand2) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_ORI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ORI_OPERATOR;
alu_category <= `INST_ORI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {16'h0, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_ANDI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ANDI_OPERATOR;
alu_category <= `INST_ANDI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {16'h0, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_XORI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_XORI_OPERATOR;
alu_category <= `INST_XORI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {16'h0, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LUI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LUI_OPERATOR;
alu_category <= `INST_LUI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {instruction[15 : 0], 16'h0};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_PREF_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_PREF_OPERATOR;
alu_category <= `INST_PREF_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_SLTI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLTI_OPERATOR;
alu_category <= `INST_SLTI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_SLTIU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLTIU_OPERATOR;
alu_category <= `INST_SLTIU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_ADDI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADDI_OPERATOR;
alu_category <= `INST_ADDI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_ADDIU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADDIU_OPERATOR;
alu_category <= `INST_ADDIU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
default: begin
end
endcase
if (instruction[31 : 21] == 11'b00000000000) begin
case (instruction[5 : 0])
`INST_SLL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLL_OPERATOR;
alu_category <= `INST_SLL_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
imm[4 : 0] <= instruction[10 : 6];
write_addr <= instruction[15 : 11];
validality <= `VALID;
end
`INST_SRL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRL_OPERATOR;
alu_category <= `INST_SRL_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
imm[4 : 0] <= instruction[10 : 6];
write_addr <= instruction[15 : 11];
validality <= `VALID;
end
`INST_SRA_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRA_OPERATOR;
alu_category <= `INST_SRA_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
imm[4 : 0] <= instruction[10 : 6];
write_addr <= instruction[15 : 11];
validality <= `VALID;
end
endcase
end
end
end
always @ (*) begin
if (reset == `ENABLE) begin
is_curr_in_delayslot <= `FALSE;
end else begin
is_curr_in_delayslot <= input_is_curr_in_delayslot;
end
end
always @ (*) begin
stall_signal_from_reg1_load_relate <= `DISABLE;
if (reset == `ENABLE) begin
alu_operand1 <= 0;
end else if (pre_inst_is_load && ex_write_addr == read_addr1 && read_enable1) begin
stall_signal_from_reg1_load_relate <= `ENABLE;
end else if (read_enable1 == `ENABLE && ex_write_enable == `ENABLE && ex_write_addr == read_addr1) begin
alu_operand1 <= ex_write_data;
end else if (read_enable1 == `ENABLE && mem_write_enable == `ENABLE && mem_write_addr == read_addr1) begin
alu_operand1 <= mem_write_data;
end else if (read_enable1 == `ENABLE) begin
alu_operand1 <= read_result1;
end else if (read_enable1 == `DISABLE) begin
alu_operand1 <= imm;
end else begin
alu_operand1 <= 0;
end
end
always @ (*) begin
stall_signal_from_reg2_load_relate <= `DISABLE;
if (reset == `ENABLE) begin
alu_operand2 <= 0;
end else if (pre_inst_is_load && ex_write_addr == read_addr2 && read_enable2) begin
stall_signal_from_reg2_load_relate <= `ENABLE;
end else if (read_enable2 == `ENABLE && ex_write_enable == `ENABLE && ex_write_addr == read_addr2) begin
alu_operand2 <= ex_write_data;
end else if (read_enable2 == `ENABLE && mem_write_enable == `ENABLE && mem_write_addr == read_addr2) begin
alu_operand2 <= mem_write_data;
end else if (read_enable2 == `ENABLE) begin
alu_operand2 <= read_result2;
end else if (read_enable2 == `DISABLE) begin
alu_operand2 <= imm;
end else begin
alu_operand2 <= 0;
end
end
assign stall_signal = stall_signal_from_reg1_load_relate || stall_signal_from_reg2_load_relate;
endmodule | module id(
input wire reset,
input wire[`INST_ADDR_BUS] program_counter,
input wire[`INST_DATA_BUS] instruction,
input wire ex_write_enable,
input wire[`REGS_ADDR_BUS] ex_write_addr,
input wire[`REGS_DATA_BUS] ex_write_data,
input wire mem_write_enable,
input wire[`REGS_ADDR_BUS] mem_write_addr,
input wire[`REGS_DATA_BUS] mem_write_data,
input wire[`REGS_DATA_BUS] read_result1,
input wire[`REGS_DATA_BUS] read_result2,
input wire input_is_curr_in_delayslot,
input wire[`ALU_OPERATOR_BUS] ex_alu_operator,
output wire[`REGS_DATA_BUS] broadcast_instruction,
output reg is_curr_in_delayslot,
output reg is_next_in_delayslot,
output reg branch_signal,
output reg[`REGS_DATA_BUS] branch_target,
output reg[`REGS_DATA_BUS] return_target,
output reg read_enable1,
output reg read_enable2,
output reg[`REGS_ADDR_BUS] read_addr1,
output reg[`REGS_ADDR_BUS] read_addr2,
output reg[`ALU_OPERATOR_BUS] alu_operator,
output reg[`ALU_CATEGORY_BUS] alu_category,
output reg[`REGS_DATA_BUS] alu_operand1,
output reg[`REGS_DATA_BUS] alu_operand2,
output reg write_enable,
output reg[`REGS_ADDR_BUS] write_addr,
output wire stall_signal
); |
assign broadcast_instruction = instruction;
reg stall_signal_from_reg1_load_relate;
reg stall_signal_from_reg2_load_relate;
wire pre_inst_is_load;
assign pre_inst_is_load = (ex_alu_operator == `OPERATOR_LB || ex_alu_operator == `OPERATOR_LBU
|| ex_alu_operator == `OPERATOR_LH || ex_alu_operator == `OPERATOR_LHU
|| ex_alu_operator == `OPERATOR_LW || ex_alu_operator == `OPERATOR_LWR
|| ex_alu_operator == `OPERATOR_LWL) ? `TRUE : `FALSE;
reg[`REGS_DATA_BUS] imm;
reg validality;
wire[`REGS_DATA_BUS] pc_plus_8;
wire[`REGS_DATA_BUS] pc_plus_4;
wire[`REGS_DATA_BUS] imm_sll2_signed_next;
assign pc_plus_8 = program_counter + 8;
assign pc_plus_4 = program_counter + 4;
assign imm_sll2_signed_next = {{14{instruction[15]}}, instruction[15 : 0], 2'b00};
always @ (*) begin
if (reset == `ENABLE) begin
alu_operator <= `INST_NOP_OPERATOR;
alu_category <= `INST_NOP_CATEGORY;
write_addr <= 0;
write_enable <= `DISABLE;
validality <= `VALID;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
read_addr1 <= 0;
read_addr2 <= 0;
imm <= 0;
return_target <= 0;
branch_target <= 0;
branch_signal <= `DISABLE;
is_next_in_delayslot <= `FALSE;
end else begin
alu_operator <= `INST_NOP_OPERATOR;
alu_category <= `INST_NOP_CATEGORY;
write_enable <= `DISABLE;
write_addr <= instruction[15 : 11];
validality <= `INVALID;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
read_addr1 <= instruction[25 : 21];
read_addr2 <= instruction[20 : 16];
imm <= 0;
return_target <= 0;
branch_target <= 0;
branch_signal <= `DISABLE;
is_next_in_delayslot <= `FALSE;
case (instruction[31 : 26])
6'b000000: begin
if (instruction[10 : 6] == 5'b00000) begin
case (instruction[5 : 0])
`INST_OR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_OR_OPERATOR;
alu_category <= `INST_OR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_AND_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_AND_OPERATOR;
alu_category <= `INST_AND_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_XOR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_XOR_OPERATOR;
alu_category <= `INST_XOR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_NOR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_NOR_OPERATOR;
alu_category <= `INST_NOR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SLLV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLLV_OPERATOR;
alu_category <= `INST_SLLV_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SRLV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRLV_OPERATOR;
alu_category <= `INST_SRLV_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SRAV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRAV_OPERATOR;
alu_category <= `INST_SRAV_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SYNC_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SYNC_OPERATOR;
alu_category <= `INST_SYNC_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MFHI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MFHI_OPERATOR;
alu_category <= `INST_MFHI_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MFLO_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MFLO_OPERATOR;
alu_category <= `INST_MFLO_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MTHI_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MTHI_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MTLO_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MTLO_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MOVN_ID: begin
if (alu_operand2 != 0) begin
write_enable <= `ENABLE;
end else begin
write_enable <= `DISABLE;
end
alu_operator <= `INST_MOVN_OPERATOR;
alu_category <= `INST_MOVN_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MOVZ_ID: begin
if (alu_operand2 == 0) begin
write_enable <= `ENABLE;
end else begin
write_enable <= `DISABLE;
end
alu_operator <= `INST_MOVZ_OPERATOR;
alu_category <= `INST_MOVZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SLT_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLT_OPERATOR;
alu_category <= `INST_SLT_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SLTU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLTU_OPERATOR;
alu_category <= `INST_SLTU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_ADD_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADD_OPERATOR;
alu_category <= `INST_ADD_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_ADDU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADDU_OPERATOR;
alu_category <= `INST_ADDU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SUB_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SUB_OPERATOR;
alu_category <= `INST_SUB_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SUBU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SUBU_OPERATOR;
alu_category <= `INST_SUBU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MULT_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MULT_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MULTU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MULTU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_DIV_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_DIV_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_DIVU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_DIVU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_JR_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_JR_OPERATOR;
alu_category <= `INST_JR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
return_target <= 0;
branch_target <= alu_operand1;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
`INST_JALR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_JALR_OPERATOR;
alu_category <= `INST_JALR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[15 : 11];
return_target <= pc_plus_8;
branch_target <= alu_operand1;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
default: begin
end
endcase
end
end
6'b000001: begin
case (instruction[20 : 16])
`INST_BGEZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BGEZ_OPERATOR;
alu_category <= `INST_BGEZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (!alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BGEZAL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_BGEZAL_OPERATOR;
alu_category <= `INST_BGEZAL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
return_target <= pc_plus_8;
write_addr <= 5'b11111;
validality <= `VALID;
if (!alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BLTZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BLTZ_OPERATOR;
alu_category <= `INST_BLTZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BLTZAL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_BLTZAL_OPERATOR;
alu_category <= `INST_BLTZAL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
return_target <= pc_plus_8;
write_addr <= 5'b11111;
validality <= `VALID;
if (alu_operand1[31]) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
endcase
end
6'b011100: begin
case (instruction[5 : 0])
`INST_CLZ_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_CLZ_OPERATOR;
alu_category <= `INST_CLZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_CLO_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_CLO_OPERATOR;
alu_category <= `INST_CLO_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_MUL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_MUL_OPERATOR;
alu_category <= `INST_MUL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MADD_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MADD_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MADDU_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MADDU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MSUB_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MSUB_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_MSUBU_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_MSUBU_OPERATOR;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
default: begin
end
endcase
end
`INST_LB_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LB_OPERATOR;
alu_category <= `INST_LB_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LBU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LBU_OPERATOR;
alu_category <= `INST_LBU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LH_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LH_OPERATOR;
alu_category <= `INST_LH_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LHU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LHU_OPERATOR;
alu_category <= `INST_LHU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LW_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LW_OPERATOR;
alu_category <= `INST_LW_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LWL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LWL_OPERATOR;
alu_category <= `INST_LWL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LWR_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LWR_OPERATOR;
alu_category <= `INST_LWR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_SB_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SB_OPERATOR;
alu_category <= `INST_SB_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SH_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SH_OPERATOR;
alu_category <= `INST_SH_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SW_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SW_OPERATOR;
alu_category <= `INST_SW_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SWL_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SWL_OPERATOR;
alu_category <= `INST_SWL_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_SWR_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_SWR_OPERATOR;
alu_category <= `INST_SWR_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
end
`INST_J_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_J_OPERATOR;
alu_category <= `INST_J_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
return_target <= 0;
branch_signal <= `ENABLE;
branch_target <= {pc_plus_4[31 : 28], instruction[25 : 0], 2'b00};
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
`INST_JAL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_JAL_OPERATOR;
alu_category <= `INST_JAL_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
write_addr <= 5'b11111;
return_target <= pc_plus_8;
branch_signal <= `ENABLE;
branch_target <= {pc_plus_4[31 : 28], instruction[25 : 0], 2'b00};
is_next_in_delayslot <= `TRUE;
validality <= `VALID;
end
`INST_BEQ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BEQ_OPERATOR;
alu_category <= `INST_BEQ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
if (alu_operand1 == alu_operand2) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BGTZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BGTZ_OPERATOR;
alu_category <= `INST_BGTZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (!alu_operand1[31] && alu_operand1 != 0) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BLEZ_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BLEZ_OPERATOR;
alu_category <= `INST_BLEZ_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
if (alu_operand1[31] || alu_operand1 == 0) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_BNE_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_BNE_OPERATOR;
alu_category <= `INST_BNE_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `ENABLE;
validality <= `VALID;
if (alu_operand1 != alu_operand2) begin
branch_target <= pc_plus_4 + imm_sll2_signed_next;
branch_signal <= `ENABLE;
is_next_in_delayslot <= `TRUE;
end
end
`INST_ORI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ORI_OPERATOR;
alu_category <= `INST_ORI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {16'h0, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_ANDI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ANDI_OPERATOR;
alu_category <= `INST_ANDI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {16'h0, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_XORI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_XORI_OPERATOR;
alu_category <= `INST_XORI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {16'h0, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_LUI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_LUI_OPERATOR;
alu_category <= `INST_LUI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {instruction[15 : 0], 16'h0};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_PREF_ID: begin
write_enable <= `DISABLE;
alu_operator <= `INST_PREF_OPERATOR;
alu_category <= `INST_PREF_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `DISABLE;
validality <= `VALID;
end
`INST_SLTI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLTI_OPERATOR;
alu_category <= `INST_SLTI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_SLTIU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLTIU_OPERATOR;
alu_category <= `INST_SLTIU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_ADDI_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADDI_OPERATOR;
alu_category <= `INST_ADDI_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
`INST_ADDIU_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_ADDIU_OPERATOR;
alu_category <= `INST_ADDIU_CATEGORY;
read_enable1 <= `ENABLE;
read_enable2 <= `DISABLE;
imm <= {{16{instruction[15]}}, instruction[15 : 0]};
write_addr <= instruction[20 : 16];
validality <= `VALID;
end
default: begin
end
endcase
if (instruction[31 : 21] == 11'b00000000000) begin
case (instruction[5 : 0])
`INST_SLL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SLL_OPERATOR;
alu_category <= `INST_SLL_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
imm[4 : 0] <= instruction[10 : 6];
write_addr <= instruction[15 : 11];
validality <= `VALID;
end
`INST_SRL_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRL_OPERATOR;
alu_category <= `INST_SRL_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
imm[4 : 0] <= instruction[10 : 6];
write_addr <= instruction[15 : 11];
validality <= `VALID;
end
`INST_SRA_ID: begin
write_enable <= `ENABLE;
alu_operator <= `INST_SRA_OPERATOR;
alu_category <= `INST_SRA_CATEGORY;
read_enable1 <= `DISABLE;
read_enable2 <= `ENABLE;
imm[4 : 0] <= instruction[10 : 6];
write_addr <= instruction[15 : 11];
validality <= `VALID;
end
endcase
end
end
end
always @ (*) begin
if (reset == `ENABLE) begin
is_curr_in_delayslot <= `FALSE;
end else begin
is_curr_in_delayslot <= input_is_curr_in_delayslot;
end
end
always @ (*) begin
stall_signal_from_reg1_load_relate <= `DISABLE;
if (reset == `ENABLE) begin
alu_operand1 <= 0;
end else if (pre_inst_is_load && ex_write_addr == read_addr1 && read_enable1) begin
stall_signal_from_reg1_load_relate <= `ENABLE;
end else if (read_enable1 == `ENABLE && ex_write_enable == `ENABLE && ex_write_addr == read_addr1) begin
alu_operand1 <= ex_write_data;
end else if (read_enable1 == `ENABLE && mem_write_enable == `ENABLE && mem_write_addr == read_addr1) begin
alu_operand1 <= mem_write_data;
end else if (read_enable1 == `ENABLE) begin
alu_operand1 <= read_result1;
end else if (read_enable1 == `DISABLE) begin
alu_operand1 <= imm;
end else begin
alu_operand1 <= 0;
end
end
always @ (*) begin
stall_signal_from_reg2_load_relate <= `DISABLE;
if (reset == `ENABLE) begin
alu_operand2 <= 0;
end else if (pre_inst_is_load && ex_write_addr == read_addr2 && read_enable2) begin
stall_signal_from_reg2_load_relate <= `ENABLE;
end else if (read_enable2 == `ENABLE && ex_write_enable == `ENABLE && ex_write_addr == read_addr2) begin
alu_operand2 <= ex_write_data;
end else if (read_enable2 == `ENABLE && mem_write_enable == `ENABLE && mem_write_addr == read_addr2) begin
alu_operand2 <= mem_write_data;
end else if (read_enable2 == `ENABLE) begin
alu_operand2 <= read_result2;
end else if (read_enable2 == `DISABLE) begin
alu_operand2 <= imm;
end else begin
alu_operand2 <= 0;
end
end
assign stall_signal = stall_signal_from_reg1_load_relate || stall_signal_from_reg2_load_relate;
endmodule | 0 |
141,277 | data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v | 94,422,424 | if-id-buffer.v | v | 30 | 109 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:7: Define or directive not defined: \'`SIGNAL_BUS\'\n input wire[`SIGNAL_BUS] stall,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`SIGNAL_BUS] stall,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:9: Define or directive not defined: \'`INST_ADDR_BUS\'\n input wire[`INST_ADDR_BUS] if_program_counter,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:10: Define or directive not defined: \'`INST_DATA_BUS\'\n input wire[`INST_DATA_BUS] if_instruction,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:12: Define or directive not defined: \'`INST_ADDR_BUS\'\n output reg[`INST_ADDR_BUS] id_program_counter,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:13: Define or directive not defined: \'`INST_DATA_BUS\'\n output reg[`INST_DATA_BUS] id_instruction\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:17: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:20: Define or directive not defined: \'`ENABLE\'\n end else if (stall[1] == `ENABLE && stall[2] == `DISABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:20: Define or directive not defined: \'`DISABLE\'\n end else if (stall[1] == `ENABLE && stall[2] == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/if-id-buffer.v:23: Define or directive not defined: \'`DISABLE\'\n end else if (stall[1] == `DISABLE) begin\n ^~~~~~~~\n%Error: Exiting due to 11 error(s)\n' | 311,160 | module | module if_id_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`INST_ADDR_BUS] if_program_counter,
input wire[`INST_DATA_BUS] if_instruction,
output reg[`INST_ADDR_BUS] id_program_counter,
output reg[`INST_DATA_BUS] id_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
id_program_counter <= 0;
id_instruction <= 0;
end else if (stall[1] == `ENABLE && stall[2] == `DISABLE) begin
id_program_counter <= 0;
id_instruction <= 0;
end else if (stall[1] == `DISABLE) begin
id_program_counter <= if_program_counter;
id_instruction <= if_instruction;
end
end
endmodule | module if_id_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`INST_ADDR_BUS] if_program_counter,
input wire[`INST_DATA_BUS] if_instruction,
output reg[`INST_ADDR_BUS] id_program_counter,
output reg[`INST_DATA_BUS] id_instruction
); |
always @ (posedge clock) begin
if (reset == `ENABLE) begin
id_program_counter <= 0;
id_instruction <= 0;
end else if (stall[1] == `ENABLE && stall[2] == `DISABLE) begin
id_program_counter <= 0;
id_instruction <= 0;
end else if (stall[1] == `DISABLE) begin
id_program_counter <= if_program_counter;
id_instruction <= if_instruction;
end
end
endmodule | 0 |
141,278 | data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v | 94,422,424 | mem-wb-buffer.v | v | 52 | 89 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:7: Define or directive not defined: \'`SIGNAL_BUS\'\n input wire[`SIGNAL_BUS] stall,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`SIGNAL_BUS] stall,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_ADDR_BUS] mem_write_addr,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:10: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] mem_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] mem_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] mem_write_hi_data,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:14: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] mem_write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:15: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] mem_write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:18: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_ADDR_BUS] wb_write_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:18: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] wb_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:19: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] wb_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] wb_write_hi_data,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:22: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] wb_write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:23: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] wb_write_lo_data\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:27: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:28: Define or directive not defined: \'`DISABLE\'\n wb_write_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:31: Define or directive not defined: \'`DISABLE\'\n wb_write_hilo_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:34: Define or directive not defined: \'`ENABLE\'\n end else if (stall[4] == `ENABLE && stall[5] == `DISABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:34: Define or directive not defined: \'`DISABLE\'\n end else if (stall[4] == `ENABLE && stall[5] == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:35: Define or directive not defined: \'`DISABLE\'\n wb_write_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:38: Define or directive not defined: \'`DISABLE\'\n wb_write_hilo_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem-wb-buffer.v:41: Define or directive not defined: \'`DISABLE\'\n end else if (stall[4] == `DISABLE) begin\n ^~~~~~~~\n%Error: Exiting due to 23 error(s)\n' | 311,161 | module | module mem_wb_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire mem_write_enable,
input wire[`REGS_ADDR_BUS] mem_write_addr,
input wire[`REGS_DATA_BUS] mem_write_data,
input wire mem_write_hilo_enable,
input wire[`REGS_DATA_BUS] mem_write_hi_data,
input wire[`REGS_DATA_BUS] mem_write_lo_data,
output reg wb_write_enable,
output reg[`REGS_ADDR_BUS] wb_write_addr,
output reg[`REGS_DATA_BUS] wb_write_data,
output reg wb_write_hilo_enable,
output reg[`REGS_DATA_BUS] wb_write_hi_data,
output reg[`REGS_DATA_BUS] wb_write_lo_data
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
wb_write_enable <= `DISABLE;
wb_write_addr <= 0;
wb_write_data <= 0;
wb_write_hilo_enable <= `DISABLE;
wb_write_hi_data <= 0;
wb_write_lo_data <= 0;
end else if (stall[4] == `ENABLE && stall[5] == `DISABLE) begin
wb_write_enable <= `DISABLE;
wb_write_addr <= 0;
wb_write_data <= 0;
wb_write_hilo_enable <= `DISABLE;
wb_write_hi_data <= 0;
wb_write_lo_data <= 0;
end else if (stall[4] == `DISABLE) begin
wb_write_enable <= mem_write_enable;
wb_write_addr <= mem_write_addr;
wb_write_data <= mem_write_data;
wb_write_hilo_enable <= mem_write_hilo_enable;
wb_write_hi_data <= mem_write_hi_data;
wb_write_lo_data <= mem_write_lo_data;
end
end
endmodule | module mem_wb_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire mem_write_enable,
input wire[`REGS_ADDR_BUS] mem_write_addr,
input wire[`REGS_DATA_BUS] mem_write_data,
input wire mem_write_hilo_enable,
input wire[`REGS_DATA_BUS] mem_write_hi_data,
input wire[`REGS_DATA_BUS] mem_write_lo_data,
output reg wb_write_enable,
output reg[`REGS_ADDR_BUS] wb_write_addr,
output reg[`REGS_DATA_BUS] wb_write_data,
output reg wb_write_hilo_enable,
output reg[`REGS_DATA_BUS] wb_write_hi_data,
output reg[`REGS_DATA_BUS] wb_write_lo_data
); |
always @ (posedge clock) begin
if (reset == `ENABLE) begin
wb_write_enable <= `DISABLE;
wb_write_addr <= 0;
wb_write_data <= 0;
wb_write_hilo_enable <= `DISABLE;
wb_write_hi_data <= 0;
wb_write_lo_data <= 0;
end else if (stall[4] == `ENABLE && stall[5] == `DISABLE) begin
wb_write_enable <= `DISABLE;
wb_write_addr <= 0;
wb_write_data <= 0;
wb_write_hilo_enable <= `DISABLE;
wb_write_hi_data <= 0;
wb_write_lo_data <= 0;
end else if (stall[4] == `DISABLE) begin
wb_write_enable <= mem_write_enable;
wb_write_addr <= mem_write_addr;
wb_write_data <= mem_write_data;
wb_write_hilo_enable <= mem_write_hilo_enable;
wb_write_hi_data <= mem_write_hi_data;
wb_write_lo_data <= mem_write_lo_data;
end
end
endmodule | 0 |
141,279 | data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v | 94,422,424 | mem.v | v | 312 | 105 | [] | [] | [] | [(1, 5)] | null | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:7: Define or directive not defined: \'`REGS_ADDR_BUS\'\n input wire[`REGS_ADDR_BUS] input_write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`REGS_ADDR_BUS] input_write_addr,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:8: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] input_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] input_write_hi_data,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] input_write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:12: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] input_write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:14: Define or directive not defined: \'`ALU_OPERATOR_BUS\'\n input wire[`ALU_OPERATOR_BUS] input_alu_operator,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:15: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] input_alu_operand2,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:16: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] input_ram_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:18: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] input_ram_read_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_ADDR_BUS] write_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:21: Define or directive not defined: \'`REGS_ADDR_BUS\'\n output reg[`REGS_ADDR_BUS] write_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:22: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`REGS_DATA_BUS] write_hi_data,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:25: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] write_hi_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:26: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] write_lo_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:28: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] ram_addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`BYTE_SEL_BUS] ram_select_signal,\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:30: Define or directive not defined: \'`BYTE_SEL_BUS\'\n output reg[`BYTE_SEL_BUS] ram_select_signal,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:31: Define or directive not defined: \'`REGS_DATA_BUS\'\n output reg[`REGS_DATA_BUS] ram_write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:35: Define or directive not defined: \'`REGS_DATA_BUS\'\n wire[`REGS_DATA_BUS] zero32;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`REGS_DATA_BUS] zero32;\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:38: syntax error, unexpected assign\n assign ram_operation = ram_operation_register;\n ^~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:42: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:43: Define or directive not defined: \'`DISABLE\'\n write_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:46: Define or directive not defined: \'`DISABLE\'\n write_hilo_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:50: Define or directive not defined: \'`DISABLE\'\n ram_operation_register <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:53: Define or directive not defined: \'`DISABLE\'\n ram_chip_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:61: Define or directive not defined: \'`DISABLE\'\n ram_operation_register <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:64: Define or directive not defined: \'`DISABLE\'\n ram_chip_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:66: Define or directive not defined: \'`OPERATOR_LB\'\n `OPERATOR_LB: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:68: Define or directive not defined: \'`RAM_READ\'\n ram_operation_register <= `RAM_READ;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:69: Define or directive not defined: \'`ENABLE\'\n ram_chip_enable <= `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:92: Define or directive not defined: \'`OPERATOR_LBU\'\n `OPERATOR_LBU: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:94: Define or directive not defined: \'`RAM_READ\'\n ram_operation_register <= `RAM_READ;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:95: Define or directive not defined: \'`ENABLE\'\n ram_chip_enable <= `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:118: Define or directive not defined: \'`OPERATOR_LH\'\n `OPERATOR_LH: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:120: Define or directive not defined: \'`RAM_READ\'\n ram_operation_register <= `RAM_READ;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:121: Define or directive not defined: \'`ENABLE\'\n ram_chip_enable <= `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:136: Define or directive not defined: \'`OPERATOR_LHU\'\n `OPERATOR_LHU: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:138: Define or directive not defined: \'`RAM_READ\'\n ram_operation_register <= `RAM_READ;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:139: Define or directive not defined: \'`ENABLE\'\n ram_chip_enable <= `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:154: Define or directive not defined: \'`OPERATOR_LW\'\n `OPERATOR_LW: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:156: Define or directive not defined: \'`RAM_READ\'\n ram_operation_register <= `RAM_READ;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:158: Define or directive not defined: \'`ENABLE\'\n ram_chip_enable <= `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:161: Define or directive not defined: \'`OPERATOR_LWL\'\n `OPERATOR_LWL: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:163: Define or directive not defined: \'`RAM_READ\'\n ram_operation_register <= `RAM_READ;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:165: Define or directive not defined: \'`ENABLE\'\n ram_chip_enable <= `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/mem.v:184: Define or directive not defined: \'`OPERATOR_LWR\'\n `OPERATOR_LWR: begin\n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 311,162 | module | module mem(
input wire reset,
input wire input_write_enable,
input wire[`REGS_ADDR_BUS] input_write_addr,
input wire[`REGS_DATA_BUS] input_write_data,
input wire input_write_hilo_enable,
input wire[`REGS_DATA_BUS] input_write_hi_data,
input wire[`REGS_DATA_BUS] input_write_lo_data,
input wire[`ALU_OPERATOR_BUS] input_alu_operator,
input wire[`REGS_DATA_BUS] input_alu_operand2,
input wire[`REGS_DATA_BUS] input_ram_addr,
input wire[`REGS_DATA_BUS] input_ram_read_data,
output reg write_enable,
output reg[`REGS_ADDR_BUS] write_addr,
output reg[`REGS_DATA_BUS] write_data,
output reg write_hilo_enable,
output reg[`REGS_DATA_BUS] write_hi_data,
output reg[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_DATA_BUS] ram_addr,
output wire ram_operation,
output reg[`BYTE_SEL_BUS] ram_select_signal,
output reg[`REGS_DATA_BUS] ram_write_data,
output reg ram_chip_enable
);
wire[`REGS_DATA_BUS] zero32;
reg ram_operation_register;
assign ram_operation = ram_operation_register;
assign zero32 = 0;
always @ (*) begin
if (reset == `ENABLE) begin
write_enable <= `DISABLE;
write_addr <= 0;
write_data <= 0;
write_hilo_enable <= `DISABLE;
write_hi_data <= 0;
write_lo_data <= 0;
ram_addr <= 0;
ram_operation_register <= `DISABLE;
ram_select_signal <= 0;
ram_write_data <= 0;
ram_chip_enable <= `DISABLE;
end else begin
write_enable <= input_write_enable;
write_addr <= input_write_addr;
write_data <= input_write_data;
write_hilo_enable <= input_write_hilo_enable;
write_hi_data <= input_write_hi_data;
write_lo_data <= input_write_lo_data;
ram_operation_register <= `DISABLE;
ram_addr <= 0;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `DISABLE;
case (input_alu_operator)
`OPERATOR_LB: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{24{input_ram_read_data[31]}}, input_ram_read_data[31 : 24]};
ram_select_signal <= 4'b1000;
end
2'b01: begin
write_data <= {{24{input_ram_read_data[23]}}, input_ram_read_data[23 : 16]};
ram_select_signal <= 4'b0100;
end
2'b10: begin
write_data <= {{24{input_ram_read_data[15]}}, input_ram_read_data[15 : 8]};
ram_select_signal <= 4'b0010;
end
2'b11: begin
write_data <= {{24{input_ram_read_data[7]}}, input_ram_read_data[7 : 0]};
ram_select_signal <= 4'b0001;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LBU: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{24{1'b0}}, input_ram_read_data[31 : 24]};
ram_select_signal <= 4'b1000;
end
2'b01: begin
write_data <= {{24{1'b0}}, input_ram_read_data[23 : 16]};
ram_select_signal <= 4'b0100;
end
2'b10: begin
write_data <= {{24{1'b0}}, input_ram_read_data[15 : 8]};
ram_select_signal <= 4'b0010;
end
2'b11: begin
write_data <= {{24{1'b0}}, input_ram_read_data[7 : 0]};
ram_select_signal <= 4'b0001;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LH: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{16{input_ram_read_data[31]}}, input_ram_read_data[31 : 16]};
ram_select_signal <= 4'b1100;
end
2'b10: begin
write_data <= {{16{input_ram_read_data[15]}}, input_ram_read_data[15 : 0]};
ram_select_signal <= 4'b0011;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LHU: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{16{1'b0}}, input_ram_read_data[31 : 16]};
ram_select_signal <= 4'b1100;
end
2'b10: begin
write_data <= {{16{1'b0}}, input_ram_read_data[15 : 0]};
ram_select_signal <= 4'b0011;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LW: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
write_data <= input_ram_read_data;
end
`OPERATOR_LWL: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= input_ram_read_data[31 : 0];
end
2'b01: begin
write_data <= {input_ram_read_data[23 : 0], input_alu_operand2[7 : 0]};
end
2'b10: begin
write_data <= {input_ram_read_data[15 : 0], input_alu_operand2[15 : 0]};
end
2'b11: begin
write_data <= {input_ram_read_data[7 : 0], input_alu_operand2[23 : 0]};
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LWR: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {input_alu_operand2[31 : 8], input_ram_read_data[31 : 24]};
end
2'b01: begin
write_data <= {input_alu_operand2[31 : 16], input_ram_read_data[31 : 16]};
end
2'b10: begin
write_data <= {input_alu_operand2[31 : 24], input_ram_read_data[31 : 8]};
end
2'b11: begin
write_data <= input_ram_read_data;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_SB: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= {input_alu_operand2[7 : 0], input_alu_operand2[7 : 0],
input_alu_operand2[7 : 0], input_alu_operand2[7 : 0]};
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1000;
end
2'b01: begin
ram_select_signal <= 4'b0100;
end
2'b10: begin
ram_select_signal <= 4'b0010;
end
2'b11: begin
ram_select_signal <= 4'b0001;
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SH: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= {input_alu_operand2[15 : 0], input_alu_operand2[15 : 0]};
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1100;
end
2'b10: begin
ram_select_signal <= 4'b0011;
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SW: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= input_alu_operand2;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
end
`OPERATOR_SWL: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_WRITE;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1111;
ram_write_data <= input_alu_operand2;
end
2'b01: begin
ram_select_signal <= 4'b0111;
ram_write_data <= {zero32[7 : 0], input_alu_operand2[31 : 8]};
end
2'b10: begin
ram_select_signal <= 4'b0011;
ram_write_data <= {zero32[15 : 0], input_alu_operand2[31 : 16]};
end
2'b11: begin
ram_select_signal <= 4'b0001;
ram_write_data <= {zero32[23 : 0], input_alu_operand2[31 : 24]};
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SWR: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_WRITE;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1000;
ram_write_data <= {input_alu_operand2[7 : 0], zero32[23 : 0]};
end
2'b01: begin
ram_select_signal <= 4'b1100;
ram_write_data <= {input_alu_operand2[15 : 0], zero32[15 : 0]};
end
2'b10: begin
ram_select_signal <= 4'b1110;
ram_write_data <= {input_alu_operand2[23 : 0], zero32[7 : 0]};
end
2'b11: begin
ram_select_signal <= 4'b1111;
ram_write_data <= input_alu_operand2[31 : 0];
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
endcase
end
end
endmodule | module mem(
input wire reset,
input wire input_write_enable,
input wire[`REGS_ADDR_BUS] input_write_addr,
input wire[`REGS_DATA_BUS] input_write_data,
input wire input_write_hilo_enable,
input wire[`REGS_DATA_BUS] input_write_hi_data,
input wire[`REGS_DATA_BUS] input_write_lo_data,
input wire[`ALU_OPERATOR_BUS] input_alu_operator,
input wire[`REGS_DATA_BUS] input_alu_operand2,
input wire[`REGS_DATA_BUS] input_ram_addr,
input wire[`REGS_DATA_BUS] input_ram_read_data,
output reg write_enable,
output reg[`REGS_ADDR_BUS] write_addr,
output reg[`REGS_DATA_BUS] write_data,
output reg write_hilo_enable,
output reg[`REGS_DATA_BUS] write_hi_data,
output reg[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_DATA_BUS] ram_addr,
output wire ram_operation,
output reg[`BYTE_SEL_BUS] ram_select_signal,
output reg[`REGS_DATA_BUS] ram_write_data,
output reg ram_chip_enable
); |
wire[`REGS_DATA_BUS] zero32;
reg ram_operation_register;
assign ram_operation = ram_operation_register;
assign zero32 = 0;
always @ (*) begin
if (reset == `ENABLE) begin
write_enable <= `DISABLE;
write_addr <= 0;
write_data <= 0;
write_hilo_enable <= `DISABLE;
write_hi_data <= 0;
write_lo_data <= 0;
ram_addr <= 0;
ram_operation_register <= `DISABLE;
ram_select_signal <= 0;
ram_write_data <= 0;
ram_chip_enable <= `DISABLE;
end else begin
write_enable <= input_write_enable;
write_addr <= input_write_addr;
write_data <= input_write_data;
write_hilo_enable <= input_write_hilo_enable;
write_hi_data <= input_write_hi_data;
write_lo_data <= input_write_lo_data;
ram_operation_register <= `DISABLE;
ram_addr <= 0;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `DISABLE;
case (input_alu_operator)
`OPERATOR_LB: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{24{input_ram_read_data[31]}}, input_ram_read_data[31 : 24]};
ram_select_signal <= 4'b1000;
end
2'b01: begin
write_data <= {{24{input_ram_read_data[23]}}, input_ram_read_data[23 : 16]};
ram_select_signal <= 4'b0100;
end
2'b10: begin
write_data <= {{24{input_ram_read_data[15]}}, input_ram_read_data[15 : 8]};
ram_select_signal <= 4'b0010;
end
2'b11: begin
write_data <= {{24{input_ram_read_data[7]}}, input_ram_read_data[7 : 0]};
ram_select_signal <= 4'b0001;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LBU: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{24{1'b0}}, input_ram_read_data[31 : 24]};
ram_select_signal <= 4'b1000;
end
2'b01: begin
write_data <= {{24{1'b0}}, input_ram_read_data[23 : 16]};
ram_select_signal <= 4'b0100;
end
2'b10: begin
write_data <= {{24{1'b0}}, input_ram_read_data[15 : 8]};
ram_select_signal <= 4'b0010;
end
2'b11: begin
write_data <= {{24{1'b0}}, input_ram_read_data[7 : 0]};
ram_select_signal <= 4'b0001;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LH: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{16{input_ram_read_data[31]}}, input_ram_read_data[31 : 16]};
ram_select_signal <= 4'b1100;
end
2'b10: begin
write_data <= {{16{input_ram_read_data[15]}}, input_ram_read_data[15 : 0]};
ram_select_signal <= 4'b0011;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LHU: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{16{1'b0}}, input_ram_read_data[31 : 16]};
ram_select_signal <= 4'b1100;
end
2'b10: begin
write_data <= {{16{1'b0}}, input_ram_read_data[15 : 0]};
ram_select_signal <= 4'b0011;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LW: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
write_data <= input_ram_read_data;
end
`OPERATOR_LWL: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= input_ram_read_data[31 : 0];
end
2'b01: begin
write_data <= {input_ram_read_data[23 : 0], input_alu_operand2[7 : 0]};
end
2'b10: begin
write_data <= {input_ram_read_data[15 : 0], input_alu_operand2[15 : 0]};
end
2'b11: begin
write_data <= {input_ram_read_data[7 : 0], input_alu_operand2[23 : 0]};
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_LWR: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {input_alu_operand2[31 : 8], input_ram_read_data[31 : 24]};
end
2'b01: begin
write_data <= {input_alu_operand2[31 : 16], input_ram_read_data[31 : 16]};
end
2'b10: begin
write_data <= {input_alu_operand2[31 : 24], input_ram_read_data[31 : 8]};
end
2'b11: begin
write_data <= input_ram_read_data;
end
default: begin
write_data <= 0;
end
endcase
end
`OPERATOR_SB: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= {input_alu_operand2[7 : 0], input_alu_operand2[7 : 0],
input_alu_operand2[7 : 0], input_alu_operand2[7 : 0]};
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1000;
end
2'b01: begin
ram_select_signal <= 4'b0100;
end
2'b10: begin
ram_select_signal <= 4'b0010;
end
2'b11: begin
ram_select_signal <= 4'b0001;
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SH: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= {input_alu_operand2[15 : 0], input_alu_operand2[15 : 0]};
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1100;
end
2'b10: begin
ram_select_signal <= 4'b0011;
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SW: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= input_alu_operand2;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
end
`OPERATOR_SWL: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_WRITE;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1111;
ram_write_data <= input_alu_operand2;
end
2'b01: begin
ram_select_signal <= 4'b0111;
ram_write_data <= {zero32[7 : 0], input_alu_operand2[31 : 8]};
end
2'b10: begin
ram_select_signal <= 4'b0011;
ram_write_data <= {zero32[15 : 0], input_alu_operand2[31 : 16]};
end
2'b11: begin
ram_select_signal <= 4'b0001;
ram_write_data <= {zero32[23 : 0], input_alu_operand2[31 : 24]};
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SWR: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_WRITE;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1000;
ram_write_data <= {input_alu_operand2[7 : 0], zero32[23 : 0]};
end
2'b01: begin
ram_select_signal <= 4'b1100;
ram_write_data <= {input_alu_operand2[15 : 0], zero32[15 : 0]};
end
2'b10: begin
ram_select_signal <= 4'b1110;
ram_write_data <= {input_alu_operand2[23 : 0], zero32[7 : 0]};
end
2'b11: begin
ram_select_signal <= 4'b1111;
ram_write_data <= input_alu_operand2[31 : 0];
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
endcase
end
end
endmodule | 0 |
141,280 | data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v | 94,422,424 | pc-reg.v | v | 35 | 106 | [] | [] | [] | [(1, 5)] | null | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/cpu/stages,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:6: Define or directive not defined: \'`SIGNAL_BUS\'\n input wire[`SIGNAL_BUS] stall,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`SIGNAL_BUS] stall,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:7: Define or directive not defined: \'`INST_ADDR_BUS\'\n output reg[`INST_ADDR_BUS] program_counter,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:10: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input wire branch_signal,\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`REGS_DATA_BUS] branch_target\n ^~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:11: Define or directive not defined: \'`REGS_DATA_BUS\'\n input wire[`REGS_DATA_BUS] branch_target\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:15: Define or directive not defined: \'`ENABLE\'\n if (reset == `ENABLE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:16: Define or directive not defined: \'`DISABLE\'\n chip_enable <= `DISABLE;\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:18: Define or directive not defined: \'`ENABLE\'\n chip_enable <= `ENABLE;\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:23: Define or directive not defined: \'`DISABLE\'\n if (chip_enable == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:25: Define or directive not defined: \'`DISABLE\'\n end else if (stall[0] == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/cpu/stages/pc-reg.v:26: Define or directive not defined: \'`ENABLE\'\n if (branch_signal == `ENABLE) begin\n ^~~~~~~\n%Error: Exiting due to 13 error(s)\n' | 311,163 | module | module pc_reg(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
output reg[`INST_ADDR_BUS] program_counter,
output reg chip_enable,
input wire branch_signal,
input wire[`REGS_DATA_BUS] branch_target
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
chip_enable <= `DISABLE;
end else begin
chip_enable <= `ENABLE;
end
end
always @ (posedge clock) begin
if (chip_enable == `DISABLE) begin
program_counter <= 0;
end else if (stall[0] == `DISABLE) begin
if (branch_signal == `ENABLE) begin
program_counter <= branch_target;
end else begin
program_counter <= program_counter + 4'h4;
end
end
end
endmodule | module pc_reg(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
output reg[`INST_ADDR_BUS] program_counter,
output reg chip_enable,
input wire branch_signal,
input wire[`REGS_DATA_BUS] branch_target
); |
always @ (posedge clock) begin
if (reset == `ENABLE) begin
chip_enable <= `DISABLE;
end else begin
chip_enable <= `ENABLE;
end
end
always @ (posedge clock) begin
if (chip_enable == `DISABLE) begin
program_counter <= 0;
end else if (stall[0] == `DISABLE) begin
if (branch_signal == `ENABLE) begin
program_counter <= branch_target;
end else begin
program_counter <= program_counter + 4'h4;
end
end
end
endmodule | 0 |
141,281 | data/full_repos/permissive/94422424/source/machine/memory/ram.v | 94,422,424 | ram.v | v | 50 | 78 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/memory,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/memory,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/memory,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:7: Define or directive not defined: \'`INST_ADDR_BUS\'\n input wire[`INST_ADDR_BUS] addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`INST_ADDR_BUS] addr,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:8: Define or directive not defined: \'`BYTE_SEL_BUS\'\n input wire[`BYTE_SEL_BUS] select_signal,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:9: Define or directive not defined: \'`INST_DATA_BUS\'\n input wire[`INST_DATA_BUS] write_data,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:10: Define or directive not defined: \'`INST_DATA_BUS\'\n output reg[`INST_DATA_BUS] read_data\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:13: Define or directive not defined: \'`BYTE_WIDTH\'\n reg[`BYTE_WIDTH] data_mem0[0 : `RAM_NUM - 1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`BYTE_WIDTH] data_mem0[0 : `RAM_NUM - 1];\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:13: Define or directive not defined: \'`RAM_NUM\'\n reg[`BYTE_WIDTH] data_mem0[0 : `RAM_NUM - 1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:14: Define or directive not defined: \'`BYTE_WIDTH\'\n reg[`BYTE_WIDTH] data_mem1[0 : `RAM_NUM - 1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`BYTE_WIDTH] data_mem1[0 : `RAM_NUM - 1];\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:14: Define or directive not defined: \'`RAM_NUM\'\n reg[`BYTE_WIDTH] data_mem1[0 : `RAM_NUM - 1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:15: Define or directive not defined: \'`BYTE_WIDTH\'\n reg[`BYTE_WIDTH] data_mem2[0 : `RAM_NUM - 1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`BYTE_WIDTH] data_mem2[0 : `RAM_NUM - 1];\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:15: Define or directive not defined: \'`RAM_NUM\'\n reg[`BYTE_WIDTH] data_mem2[0 : `RAM_NUM - 1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:16: Define or directive not defined: \'`BYTE_WIDTH\'\n reg[`BYTE_WIDTH] data_mem3[0 : `RAM_NUM - 1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`BYTE_WIDTH] data_mem3[0 : `RAM_NUM - 1];\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:16: Define or directive not defined: \'`RAM_NUM\'\n reg[`BYTE_WIDTH] data_mem3[0 : `RAM_NUM - 1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:19: Define or directive not defined: \'`ENABLE\'\n if (chip_enable == `ENABLE && operation == `RAM_WRITE) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:19: Define or directive not defined: \'`RAM_WRITE\'\n if (chip_enable == `ENABLE && operation == `RAM_WRITE) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:21: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem3[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[31 : 24];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:24: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem2[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[23 : 16];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:27: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem1[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[15 : 8];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:30: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem0[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[7 : 0];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:36: Define or directive not defined: \'`DISABLE\'\n if (chip_enable == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:38: Define or directive not defined: \'`RAM_READ\'\n end else if (operation == `RAM_READ) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:40: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem3[addr[`RAM_NUM_LOG + 1 : 2]],\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:41: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem2[addr[`RAM_NUM_LOG + 1 : 2]],\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:42: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem1[addr[`RAM_NUM_LOG + 1 : 2]],\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/ram.v:43: Define or directive not defined: \'`RAM_NUM_LOG\'\n data_mem0[addr[`RAM_NUM_LOG + 1 : 2]]\n ^~~~~~~~~~~~\n%Error: Exiting due to 30 error(s)\n' | 311,164 | module | module ram(
input wire clock,
input wire chip_enable,
input wire operation,
input wire[`INST_ADDR_BUS] addr,
input wire[`BYTE_SEL_BUS] select_signal,
input wire[`INST_DATA_BUS] write_data,
output reg[`INST_DATA_BUS] read_data
);
reg[`BYTE_WIDTH] data_mem0[0 : `RAM_NUM - 1];
reg[`BYTE_WIDTH] data_mem1[0 : `RAM_NUM - 1];
reg[`BYTE_WIDTH] data_mem2[0 : `RAM_NUM - 1];
reg[`BYTE_WIDTH] data_mem3[0 : `RAM_NUM - 1];
always @ (posedge clock) begin
if (chip_enable == `ENABLE && operation == `RAM_WRITE) begin
if (select_signal[3]) begin
data_mem3[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[31 : 24];
end
if (select_signal[2]) begin
data_mem2[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[23 : 16];
end
if (select_signal[1]) begin
data_mem1[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[15 : 8];
end
if (select_signal[0]) begin
data_mem0[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[7 : 0];
end
end
end
always @ (*) begin
if (chip_enable == `DISABLE) begin
read_data <= 0;
end else if (operation == `RAM_READ) begin
read_data = {
data_mem3[addr[`RAM_NUM_LOG + 1 : 2]],
data_mem2[addr[`RAM_NUM_LOG + 1 : 2]],
data_mem1[addr[`RAM_NUM_LOG + 1 : 2]],
data_mem0[addr[`RAM_NUM_LOG + 1 : 2]]
};
end else begin
read_data <= 0;
end
end
endmodule | module ram(
input wire clock,
input wire chip_enable,
input wire operation,
input wire[`INST_ADDR_BUS] addr,
input wire[`BYTE_SEL_BUS] select_signal,
input wire[`INST_DATA_BUS] write_data,
output reg[`INST_DATA_BUS] read_data
); |
reg[`BYTE_WIDTH] data_mem0[0 : `RAM_NUM - 1];
reg[`BYTE_WIDTH] data_mem1[0 : `RAM_NUM - 1];
reg[`BYTE_WIDTH] data_mem2[0 : `RAM_NUM - 1];
reg[`BYTE_WIDTH] data_mem3[0 : `RAM_NUM - 1];
always @ (posedge clock) begin
if (chip_enable == `ENABLE && operation == `RAM_WRITE) begin
if (select_signal[3]) begin
data_mem3[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[31 : 24];
end
if (select_signal[2]) begin
data_mem2[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[23 : 16];
end
if (select_signal[1]) begin
data_mem1[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[15 : 8];
end
if (select_signal[0]) begin
data_mem0[addr[`RAM_NUM_LOG + 1 : 2]] <= write_data[7 : 0];
end
end
end
always @ (*) begin
if (chip_enable == `DISABLE) begin
read_data <= 0;
end else if (operation == `RAM_READ) begin
read_data = {
data_mem3[addr[`RAM_NUM_LOG + 1 : 2]],
data_mem2[addr[`RAM_NUM_LOG + 1 : 2]],
data_mem1[addr[`RAM_NUM_LOG + 1 : 2]],
data_mem0[addr[`RAM_NUM_LOG + 1 : 2]]
};
end else begin
read_data <= 0;
end
end
endmodule | 0 |
141,282 | data/full_repos/permissive/94422424/source/machine/memory/rom.v | 94,422,424 | rom.v | v | 22 | 80 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:1: Cannot find include file: macro.v\n`include "macro.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94422424/source/machine/memory,data/full_repos/permissive/94422424/macro.v\n data/full_repos/permissive/94422424/source/machine/memory,data/full_repos/permissive/94422424/macro.v.v\n data/full_repos/permissive/94422424/source/machine/memory,data/full_repos/permissive/94422424/macro.v.sv\n macro.v\n macro.v.v\n macro.v.sv\n obj_dir/macro.v\n obj_dir/macro.v.v\n obj_dir/macro.v.sv\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:5: Define or directive not defined: \'`INST_ADDR_BUS\'\n input wire[`INST_ADDR_BUS] addr,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`INST_ADDR_BUS] addr,\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:6: Define or directive not defined: \'`INST_ADDR_BUS\'\n output reg[`INST_ADDR_BUS] instruction\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:9: Define or directive not defined: \'`INST_DATA_BUS\'\n reg[`INST_DATA_BUS] memory[0:`MEMO_NUM - 1];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`INST_DATA_BUS] memory[0:`MEMO_NUM - 1];\n ^\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:9: Define or directive not defined: \'`MEMO_NUM\'\n reg[`INST_DATA_BUS] memory[0:`MEMO_NUM - 1];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:14: Define or directive not defined: \'`DISABLE\'\n if (chip_enable == `DISABLE) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/94422424/source/machine/memory/rom.v:17: Define or directive not defined: \'`MEMO_NUM_LOG\'\n instruction <= memory[addr[`MEMO_NUM_LOG + 1 : 2]];\n ^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 311,165 | module | module rom(
input wire chip_enable,
input wire[`INST_ADDR_BUS] addr,
output reg[`INST_ADDR_BUS] instruction
);
reg[`INST_DATA_BUS] memory[0:`MEMO_NUM - 1];
initial $readmemh("program.rom", memory);
always @ (*) begin
if (chip_enable == `DISABLE) begin
instruction <= 0;
end else begin
instruction <= memory[addr[`MEMO_NUM_LOG + 1 : 2]];
end
end
endmodule | module rom(
input wire chip_enable,
input wire[`INST_ADDR_BUS] addr,
output reg[`INST_ADDR_BUS] instruction
); |
reg[`INST_DATA_BUS] memory[0:`MEMO_NUM - 1];
initial $readmemh("program.rom", memory);
always @ (*) begin
if (chip_enable == `DISABLE) begin
instruction <= 0;
end else begin
instruction <= memory[addr[`MEMO_NUM_LOG + 1 : 2]];
end
end
endmodule | 0 |
141,283 | data/full_repos/permissive/94493208/sim/contact_tb.sv | 94,493,208 | contact_tb.sv | sv | 54 | 84 | [] | [] | [] | [(3, 52)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/94493208/sim/contact_tb.sv:15: Unsupported: Ignoring delay on this delayed statement.\n #(N/2);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/94493208/sim/contact_tb.sv:22: Unsupported: Ignoring delay on this delayed statement.\n #(10*N);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/94493208/sim/contact_tb.sv:24: Unsupported: Ignoring delay on this delayed statement.\n #(10*N);\n ^\n%Error: data/full_repos/permissive/94493208/sim/contact_tb.sv:30: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("contact_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94493208/sim/contact_tb.sv:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, contact_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/94493208/sim/contact_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n #(1000*N);\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 311,166 | module | module contact_tb ();
localparam N = 125;
logic clk;
logic rst;
logic prime_seq;
logic [31:0] prime_seq_cnt;
initial begin
clk = 1'b0;
forever begin
#(N/2);
clk = ~clk;
end
end
initial begin
rst = 1'b0;
#(10*N);
rst = 1'b1;
#(10*N);
rst = 1'b0;
end
initial begin
$dumpfile("contact_tb.vcd");
$dumpvars(0, contact_tb);
#(1000*N);
$finish();
$stop();
end
contact #(
.PULSE_LEN_COUNT (32'd8),
.INTER_PRIME_GAP (32'd32),
.INTER_SEQUENCE_GAP (32'd128),
.ILA_CONTACT_DEBUG (32'd0)
)
contact_i0 (
.clk (clk),
.rst (rst),
.prime_seq (prime_seq),
.prime_seq_cnt (prime_seq_cnt)
);
endmodule | module contact_tb (); |
localparam N = 125;
logic clk;
logic rst;
logic prime_seq;
logic [31:0] prime_seq_cnt;
initial begin
clk = 1'b0;
forever begin
#(N/2);
clk = ~clk;
end
end
initial begin
rst = 1'b0;
#(10*N);
rst = 1'b1;
#(10*N);
rst = 1'b0;
end
initial begin
$dumpfile("contact_tb.vcd");
$dumpvars(0, contact_tb);
#(1000*N);
$finish();
$stop();
end
contact #(
.PULSE_LEN_COUNT (32'd8),
.INTER_PRIME_GAP (32'd32),
.INTER_SEQUENCE_GAP (32'd128),
.ILA_CONTACT_DEBUG (32'd0)
)
contact_i0 (
.clk (clk),
.rst (rst),
.prime_seq (prime_seq),
.prime_seq_cnt (prime_seq_cnt)
);
endmodule | 0 |
141,284 | data/full_repos/permissive/94493208/src/rtl/contact.v | 94,493,208 | contact.v | v | 191 | 117 | [] | [] | [] | null | line:63: before: "[" | data/verilator_xmls/0a1ea27c-b179-4ba4-b28e-120f2c22a572.xml | null | 311,167 | module | module contact #(
parameter integer PULSE_LEN_COUNT = 32'h007A_1200,
parameter integer INTER_PRIME_GAP = 32'h00F4_2400,
parameter integer INTER_SEQUENCE_GAP = 32'h01E8_4800,
parameter RESET_POLARITY = 1'b1,
parameter ILA_CONTACT_DEBUG = 1'b0
)
(
input wire clk,
input wire rst,
output reg prime_seq,
output reg [31:0] prime_seq_cnt
);
localparam [31:0] NUM_PRIMES = 32'd5;
localparam [31:0] PRIMES [0:(NUM_PRIMES-1)] = '{ 32'd2, 32'd3, 32'd5, 32'd7, 32'd11 };
localparam S0 = 32'd0;
localparam S1 = 32'd1;
localparam S2 = 32'd2;
localparam S3 = 32'd3;
reg [15:0] prime_state_ascii;
always @(*) begin
case (prime_state)
S0: begin prime_state_ascii = "S0"; end
S1: begin prime_state_ascii = "S1"; end
S2: begin prime_state_ascii = "S2"; end
S3: begin prime_state_ascii = "S3"; end
default: begin end
endcase
end
reg [31:0] pulse_cnt;
reg [31:0] prime_cnt;
reg [31:0] prime_idx;
reg [31:0] prime_state;
always @(posedge clk) begin
if ( rst == RESET_POLARITY ) begin
prime_seq <= 1'b0;
prime_seq_cnt <= 32'd0;
pulse_cnt <= 32'd0;
prime_cnt <= 32'd0;
prime_idx <= 32'd0;
prime_state <= S0;
end else begin
case (prime_state)
S0: begin
prime_seq <= 1'b1;
if ( pulse_cnt != ( PULSE_LEN_COUNT - 32'd1 ) ) begin
prime_state <= S0;
pulse_cnt <= pulse_cnt + 32'd1;
prime_cnt <= prime_cnt;
end else begin
if ( prime_cnt != ( PRIMES[prime_idx] - 32'd1 ) ) begin
prime_state <= S1;
prime_cnt <= prime_cnt + 32'd1;
end else begin
if ( prime_idx == ( NUM_PRIMES - 32'd1 ) ) begin
prime_state <= S3;
end else begin
prime_state <= S2;
end
prime_cnt <= 32'd0;
end
pulse_cnt <= 32'd0;
end
end
S1: begin
prime_seq <= 1'b0;
prime_idx <= prime_idx;
if ( pulse_cnt != ( PULSE_LEN_COUNT - 32'd1 ) ) begin
prime_state <= S1;
pulse_cnt <= pulse_cnt + 32'd1;
end else begin
prime_state <= S0;
pulse_cnt <= 32'd0;
end
end
S2: begin
prime_seq <= 1'b0;
prime_cnt <= 32'd0;
if ( pulse_cnt != ( INTER_PRIME_GAP - 32'd1 ) ) begin
prime_state <= S2;
pulse_cnt <= pulse_cnt + 32'd1;
prime_idx <= prime_idx;
end else begin
prime_state <= S0;
pulse_cnt <= 32'd0;
prime_idx <= prime_idx + 32'd1;
end
end
S3: begin
prime_seq <= 1'b0;
prime_idx <= 32'd0;
prime_cnt <= 32'd0;
if ( pulse_cnt != ( INTER_SEQUENCE_GAP - 32'd1 ) ) begin
prime_state <= S3;
pulse_cnt <= pulse_cnt + 32'd1;
prime_seq_cnt <= prime_seq_cnt;
end else begin
prime_state <= S0;
pulse_cnt <= 32'd0;
prime_seq_cnt <= prime_seq_cnt + 32'd1;
end
end
default: begin end
endcase
end
end
generate
if ( ILA_CONTACT_DEBUG == 1'b1 ) begin
ila_contact
ila_contact_i0 (
.clk (clk),
.probe0 (rst),
.probe1 (prime_seq),
.probe2 (prime_seq_cnt),
.probe3 (pulse_cnt),
.probe4 (prime_cnt),
.probe5 (prime_idx),
.probe6 (prime_state)
);
end
endgenerate
endmodule | module contact #(
parameter integer PULSE_LEN_COUNT = 32'h007A_1200,
parameter integer INTER_PRIME_GAP = 32'h00F4_2400,
parameter integer INTER_SEQUENCE_GAP = 32'h01E8_4800,
parameter RESET_POLARITY = 1'b1,
parameter ILA_CONTACT_DEBUG = 1'b0
)
(
input wire clk,
input wire rst,
output reg prime_seq,
output reg [31:0] prime_seq_cnt
); |
localparam [31:0] NUM_PRIMES = 32'd5;
localparam [31:0] PRIMES [0:(NUM_PRIMES-1)] = '{ 32'd2, 32'd3, 32'd5, 32'd7, 32'd11 };
localparam S0 = 32'd0;
localparam S1 = 32'd1;
localparam S2 = 32'd2;
localparam S3 = 32'd3;
reg [15:0] prime_state_ascii;
always @(*) begin
case (prime_state)
S0: begin prime_state_ascii = "S0"; end
S1: begin prime_state_ascii = "S1"; end
S2: begin prime_state_ascii = "S2"; end
S3: begin prime_state_ascii = "S3"; end
default: begin end
endcase
end
reg [31:0] pulse_cnt;
reg [31:0] prime_cnt;
reg [31:0] prime_idx;
reg [31:0] prime_state;
always @(posedge clk) begin
if ( rst == RESET_POLARITY ) begin
prime_seq <= 1'b0;
prime_seq_cnt <= 32'd0;
pulse_cnt <= 32'd0;
prime_cnt <= 32'd0;
prime_idx <= 32'd0;
prime_state <= S0;
end else begin
case (prime_state)
S0: begin
prime_seq <= 1'b1;
if ( pulse_cnt != ( PULSE_LEN_COUNT - 32'd1 ) ) begin
prime_state <= S0;
pulse_cnt <= pulse_cnt + 32'd1;
prime_cnt <= prime_cnt;
end else begin
if ( prime_cnt != ( PRIMES[prime_idx] - 32'd1 ) ) begin
prime_state <= S1;
prime_cnt <= prime_cnt + 32'd1;
end else begin
if ( prime_idx == ( NUM_PRIMES - 32'd1 ) ) begin
prime_state <= S3;
end else begin
prime_state <= S2;
end
prime_cnt <= 32'd0;
end
pulse_cnt <= 32'd0;
end
end
S1: begin
prime_seq <= 1'b0;
prime_idx <= prime_idx;
if ( pulse_cnt != ( PULSE_LEN_COUNT - 32'd1 ) ) begin
prime_state <= S1;
pulse_cnt <= pulse_cnt + 32'd1;
end else begin
prime_state <= S0;
pulse_cnt <= 32'd0;
end
end
S2: begin
prime_seq <= 1'b0;
prime_cnt <= 32'd0;
if ( pulse_cnt != ( INTER_PRIME_GAP - 32'd1 ) ) begin
prime_state <= S2;
pulse_cnt <= pulse_cnt + 32'd1;
prime_idx <= prime_idx;
end else begin
prime_state <= S0;
pulse_cnt <= 32'd0;
prime_idx <= prime_idx + 32'd1;
end
end
S3: begin
prime_seq <= 1'b0;
prime_idx <= 32'd0;
prime_cnt <= 32'd0;
if ( pulse_cnt != ( INTER_SEQUENCE_GAP - 32'd1 ) ) begin
prime_state <= S3;
pulse_cnt <= pulse_cnt + 32'd1;
prime_seq_cnt <= prime_seq_cnt;
end else begin
prime_state <= S0;
pulse_cnt <= 32'd0;
prime_seq_cnt <= prime_seq_cnt + 32'd1;
end
end
default: begin end
endcase
end
end
generate
if ( ILA_CONTACT_DEBUG == 1'b1 ) begin
ila_contact
ila_contact_i0 (
.clk (clk),
.probe0 (rst),
.probe1 (prime_seq),
.probe2 (prime_seq_cnt),
.probe3 (pulse_cnt),
.probe4 (prime_cnt),
.probe5 (prime_idx),
.probe6 (prime_state)
);
end
endgenerate
endmodule | 0 |
141,285 | data/full_repos/permissive/94493208/src/rtl/contact_wrapper.v | 94,493,208 | contact_wrapper.v | v | 30 | 67 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/94493208/src/rtl/contact_wrapper.v:15: Cannot find file containing module: 'contact'\n contact #(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/94493208/src/rtl,data/full_repos/permissive/94493208/contact\n data/full_repos/permissive/94493208/src/rtl,data/full_repos/permissive/94493208/contact.v\n data/full_repos/permissive/94493208/src/rtl,data/full_repos/permissive/94493208/contact.sv\n contact\n contact.v\n contact.sv\n obj_dir/contact\n obj_dir/contact.v\n obj_dir/contact.sv\n%Error: Exiting due to 1 error(s)\n" | 311,168 | module | module contact_wrapper #(
parameter integer PULSE_LEN_COUNT = 32'h007A_1200,
parameter integer INTER_PRIME_GAP = 32'h00F4_2400,
parameter integer INTER_SEQUENCE_GAP = 32'h01E8_4800,
parameter RESET_POLARITY = 1'b1,
parameter ILA_CONTACT_DEBUG = 1'b0
)
(
input wire clk,
input wire rst,
output wire prime_seq,
output wire [31:0] prime_seq_cnt
);
contact #(
.PULSE_LEN_COUNT (PULSE_LEN_COUNT),
.INTER_PRIME_GAP (INTER_PRIME_GAP),
.INTER_SEQUENCE_GAP (INTER_SEQUENCE_GAP),
.RESET_POLARITY (RESET_POLARITY),
.ILA_CONTACT_DEBUG (ILA_CONTACT_DEBUG)
)
contact_i0 (
.clk (clk),
.rst (rst),
.prime_seq (prime_seq),
.prime_seq_cnt (prime_seq_cnt)
);
endmodule | module contact_wrapper #(
parameter integer PULSE_LEN_COUNT = 32'h007A_1200,
parameter integer INTER_PRIME_GAP = 32'h00F4_2400,
parameter integer INTER_SEQUENCE_GAP = 32'h01E8_4800,
parameter RESET_POLARITY = 1'b1,
parameter ILA_CONTACT_DEBUG = 1'b0
)
(
input wire clk,
input wire rst,
output wire prime_seq,
output wire [31:0] prime_seq_cnt
); |
contact #(
.PULSE_LEN_COUNT (PULSE_LEN_COUNT),
.INTER_PRIME_GAP (INTER_PRIME_GAP),
.INTER_SEQUENCE_GAP (INTER_SEQUENCE_GAP),
.RESET_POLARITY (RESET_POLARITY),
.ILA_CONTACT_DEBUG (ILA_CONTACT_DEBUG)
)
contact_i0 (
.clk (clk),
.rst (rst),
.prime_seq (prime_seq),
.prime_seq_cnt (prime_seq_cnt)
);
endmodule | 0 |
141,286 | data/full_repos/permissive/94493208/src/rtl/porfgen.v | 94,493,208 | porfgen.v | v | 83 | 82 | [] | [] | [] | null | line:42: before: "case" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/94493208/src/rtl/porfgen.v:42: Operator GENCASE expects 120 bits on the Case expression, but Case expression\'s VARREF \'DEVICE\' generates 56 bits.\n : ... In instance porfgen\n case (DEVICE)\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/94493208/src/rtl/porfgen.v:46: Cannot find file containing module: \'FDPE\'\n FDPE #(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/94493208/src/rtl,data/full_repos/permissive/94493208/FDPE\n data/full_repos/permissive/94493208/src/rtl,data/full_repos/permissive/94493208/FDPE.v\n data/full_repos/permissive/94493208/src/rtl,data/full_repos/permissive/94493208/FDPE.sv\n FDPE\n FDPE.v\n FDPE.sv\n obj_dir/FDPE\n obj_dir/FDPE.v\n obj_dir/FDPE.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 311,169 | module | module porfgen #(
parameter integer PORF_LEN = 10,
parameter DEVICE = "7SERIES"
)
(
input wire clk,
input wire async_rst,
output wire sync_rst
);
localparam GND = 1'b0;
wire [PORF_LEN:0] data;
assign data[0] = GND;
assign sync_rst = data[PORF_LEN];
genvar i;
generate
case (DEVICE)
"7SERIES": begin
for (i = 0; i < PORF_LEN; i = i + 1) begin
FDPE #(
.INIT (1'b1)
)
fdpe_inst (
.PRE (async_rst),
.D (data[i]),
.C (clk),
.CE (1'b1),
.Q (data[i+1])
);
end
end
"ULTRASCALE",
"ULTRASCALE_PLUS": begin
for (i = 0; i < PORF_LEN; i = i + 1) begin
FDPE #(
.INIT (1'b1),
.IS_C_INVERTED (1'b0),
.IS_D_INVERTED (1'b0),
.IS_PRE_INVERTED (1'b0)
)
fdpe_inst (
.PRE (async_rst),
.D (data[i]),
.C (clk),
.CE (1'b1),
.Q (data[i+1])
);
end
end
default: begin end
endcase
endgenerate
endmodule | module porfgen #(
parameter integer PORF_LEN = 10,
parameter DEVICE = "7SERIES"
)
(
input wire clk,
input wire async_rst,
output wire sync_rst
); |
localparam GND = 1'b0;
wire [PORF_LEN:0] data;
assign data[0] = GND;
assign sync_rst = data[PORF_LEN];
genvar i;
generate
case (DEVICE)
"7SERIES": begin
for (i = 0; i < PORF_LEN; i = i + 1) begin
FDPE #(
.INIT (1'b1)
)
fdpe_inst (
.PRE (async_rst),
.D (data[i]),
.C (clk),
.CE (1'b1),
.Q (data[i+1])
);
end
end
"ULTRASCALE",
"ULTRASCALE_PLUS": begin
for (i = 0; i < PORF_LEN; i = i + 1) begin
FDPE #(
.INIT (1'b1),
.IS_C_INVERTED (1'b0),
.IS_D_INVERTED (1'b0),
.IS_PRE_INVERTED (1'b0)
)
fdpe_inst (
.PRE (async_rst),
.D (data[i]),
.C (clk),
.CE (1'b1),
.Q (data[i+1])
);
end
end
default: begin end
endcase
endgenerate
endmodule | 0 |
141,289 | data/full_repos/permissive/94604266/bubble_sort.v | 94,604,266 | bubble_sort.v | v | 95 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xcf in position 483: invalid continuation byte | null | 1: b"%Error: data/full_repos/permissive/94604266/bubble_sort.v:41: Cannot find file containing module: 'sort3'\n sort3 s3_1(\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort3\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort3.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort3.sv\n sort3\n sort3.v\n sort3.sv\n obj_dir/sort3\n obj_dir/sort3.v\n obj_dir/sort3.sv\n%Error: Exiting due to 1 error(s)\n" | 311,172 | module | module bubble_sort(CLK,nRST,weight_A,weight_B,weight_C,weight_D,SORT_RESULT);
input CLK;
input nRST;
input [7:0] weight_A;
input [7:0] weight_B;
input [7:0] weight_C;
input [7:0] weight_D;
output [31:0] SORT_RESULT;
reg [7:0] temp;
wire [7:0] temp1;
wire [7:0] temp2;
wire [7:0] temp3;
reg [7:0] new1;
reg [7:0] new2;
reg [7:0] new3;
reg [7:0] new4;
sort3 s3_1(
.CLK(CLK),
.nRST(nRST),
.node1(weight_A),
.node2(weight_B),
.node3(weight_C),
.new1(temp1),
.new2(temp2),
.new3(temp3)
);
always @(posedge CLK or negedge nRST)
begin
if(!nRST)
begin
new1 <= 8'b0;
new2 <= 8'b0;
new3 <= 8'b0;
end
else
begin
temp <= weight_D;
if(temp[7:4] <= temp1[7:4])
begin
new1 <= temp;
new2 <= temp1;
new3 <= temp2;
new4 <= temp3;
end
else if(temp[7:4] > temp1[7:4] && temp[7:4] <= temp2[7:4])
begin
new1 <= temp1;
new2 <= temp;
new3 <= temp2;
new4 <= temp3;
end
else if(temp[7:4] > temp2[7:4] && temp[7:4] <= temp3[7:4])
begin
new1 <= temp1;
new2 <= temp2;
new3 <= temp;
new4 <= temp3;
end
else
begin
new1 <= temp1;
new2 <= temp2;
new3 <= temp3;
new4 <= temp;
end
end
end
assign SORT_RESULT = {new4,new3,new2,new1};
endmodule | module bubble_sort(CLK,nRST,weight_A,weight_B,weight_C,weight_D,SORT_RESULT); |
input CLK;
input nRST;
input [7:0] weight_A;
input [7:0] weight_B;
input [7:0] weight_C;
input [7:0] weight_D;
output [31:0] SORT_RESULT;
reg [7:0] temp;
wire [7:0] temp1;
wire [7:0] temp2;
wire [7:0] temp3;
reg [7:0] new1;
reg [7:0] new2;
reg [7:0] new3;
reg [7:0] new4;
sort3 s3_1(
.CLK(CLK),
.nRST(nRST),
.node1(weight_A),
.node2(weight_B),
.node3(weight_C),
.new1(temp1),
.new2(temp2),
.new3(temp3)
);
always @(posedge CLK or negedge nRST)
begin
if(!nRST)
begin
new1 <= 8'b0;
new2 <= 8'b0;
new3 <= 8'b0;
end
else
begin
temp <= weight_D;
if(temp[7:4] <= temp1[7:4])
begin
new1 <= temp;
new2 <= temp1;
new3 <= temp2;
new4 <= temp3;
end
else if(temp[7:4] > temp1[7:4] && temp[7:4] <= temp2[7:4])
begin
new1 <= temp1;
new2 <= temp;
new3 <= temp2;
new4 <= temp3;
end
else if(temp[7:4] > temp2[7:4] && temp[7:4] <= temp3[7:4])
begin
new1 <= temp1;
new2 <= temp2;
new3 <= temp;
new4 <= temp3;
end
else
begin
new1 <= temp1;
new2 <= temp2;
new3 <= temp3;
new4 <= temp;
end
end
end
assign SORT_RESULT = {new4,new3,new2,new1};
endmodule | 3 |
141,291 | data/full_repos/permissive/94604266/CLK_DIV.v | 94,604,266 | CLK_DIV.v | v | 52 | 83 | [] | [] | [] | [(21, 51)] | null | data/verilator_xmls/87cb1c23-3864-4721-a9c8-2e9755f22643.xml | null | 311,174 | module | module CLK_DIV(CLK_IN, nRST, CLK_OUT);
input CLK_IN;
input nRST;
output CLK_OUT;
reg CLK_OUT = 1'b1;
reg [9:0] DIV_counter = 10'h000;
parameter DIV_FACTOR = 1;
always@(posedge CLK_IN)
begin
if(!nRST)
begin
CLK_OUT <= 1'b1;
DIV_counter <= 10'h000;
end
else
begin
if(DIV_counter != DIV_FACTOR >> 1)
begin
DIV_counter <= DIV_counter + 1;
end
else
begin
DIV_counter <= 10'h000;
CLK_OUT <= !CLK_OUT;
end
end
end
endmodule | module CLK_DIV(CLK_IN, nRST, CLK_OUT); |
input CLK_IN;
input nRST;
output CLK_OUT;
reg CLK_OUT = 1'b1;
reg [9:0] DIV_counter = 10'h000;
parameter DIV_FACTOR = 1;
always@(posedge CLK_IN)
begin
if(!nRST)
begin
CLK_OUT <= 1'b1;
DIV_counter <= 10'h000;
end
else
begin
if(DIV_counter != DIV_FACTOR >> 1)
begin
DIV_counter <= DIV_counter + 1;
end
else
begin
DIV_counter <= 10'h000;
CLK_OUT <= !CLK_OUT;
end
end
end
endmodule | 3 |
141,292 | data/full_repos/permissive/94604266/coding.v | 94,604,266 | coding.v | v | 97 | 92 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa3 in position 986: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/94604266/coding.v:51: Cannot find file containing module: 'count_frequent'\n count_frequent count(\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/count_frequent\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/count_frequent.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/count_frequent.sv\n count_frequent\n count_frequent.v\n count_frequent.sv\n obj_dir/count_frequent\n obj_dir/count_frequent.v\n obj_dir/count_frequent.sv\n%Error: data/full_repos/permissive/94604266/coding.v:59: Cannot find file containing module: 'sort_frequent'\n sort_frequent sort( \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94604266/coding.v:65: Cannot find file containing module: 'generate_tree'\n generate_tree tree(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94604266/coding.v:77: Cannot find file containing module: 'generate_code'\n generate_code code(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94604266/coding.v:89: Cannot find file containing module: 'light_led'\n light_led light(\n ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 311,175 | module | module coding(CLK,nRST,DATA_OUT);
input CLK;
input nRST;
output [3:0] DATA_OUT;
wire [27:0] character;
wire [15:0] frequent;
wire [31:0] frequent_after;
wire [12:0] info_node_1;
wire [12:0] info_node_2;
wire [12:0] info_node_3;
wire [12:0] info_node_4;
wire [12:0] info_node_5;
wire [12:0] info_node_6;
wire [12:0] info_node_7;
wire [7:0] node_new1;
wire [7:0] node_new2;
wire [7:0] node_new3;
wire [15:0] CODE_TABLE;
assign character=28'b1011_1010_1100_1101_1101_1011_1101;
count_frequent count(
.CLK(CLK),
.nRST(nRST),
.CHARACTER_IN(character[27:0]),
.FREQUENT_OUT(frequent[15:0])
);
sort_frequent sort(
.CLK(CLK),
.nRST(nRST),
.FREQUENT_IN(frequent[15:0]),
.FREQUENT_OUT(frequent_after[31:0])
);
generate_tree tree(
.CLK(CLK),
.nRST(nRST),
.weight_Gather(frequent_after),
.info_node_1(info_node_1[12:0]),
.info_node_2(info_node_2[12:0]),
.info_node_3(info_node_3[12:0]),
.info_node_4(info_node_4[12:0]),
.info_node_5(info_node_5[12:0]),
.info_node_6(info_node_6[12:0]),
.info_node_7(info_node_7[12:0])
);
generate_code code(
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1[12:0]),
.info_node_2(info_node_2[12:0]),
.info_node_3(info_node_3[12:0]),
.info_node_4(info_node_4[12:0]),
.info_node_5(info_node_5[12:0]),
.info_node_6(info_node_6[12:0]),
.info_node_7(info_node_7[12:0]),
.CODE_TABLE(CODE_TABLE[15:0])
);
light_led light(
.CLK(CLK),
.nRST(nRST),
.CODE_TABLE(CODE_TABLE[15:0]),
.LED_DATA(DATA_OUT[3:0])
);
endmodule | module coding(CLK,nRST,DATA_OUT); |
input CLK;
input nRST;
output [3:0] DATA_OUT;
wire [27:0] character;
wire [15:0] frequent;
wire [31:0] frequent_after;
wire [12:0] info_node_1;
wire [12:0] info_node_2;
wire [12:0] info_node_3;
wire [12:0] info_node_4;
wire [12:0] info_node_5;
wire [12:0] info_node_6;
wire [12:0] info_node_7;
wire [7:0] node_new1;
wire [7:0] node_new2;
wire [7:0] node_new3;
wire [15:0] CODE_TABLE;
assign character=28'b1011_1010_1100_1101_1101_1011_1101;
count_frequent count(
.CLK(CLK),
.nRST(nRST),
.CHARACTER_IN(character[27:0]),
.FREQUENT_OUT(frequent[15:0])
);
sort_frequent sort(
.CLK(CLK),
.nRST(nRST),
.FREQUENT_IN(frequent[15:0]),
.FREQUENT_OUT(frequent_after[31:0])
);
generate_tree tree(
.CLK(CLK),
.nRST(nRST),
.weight_Gather(frequent_after),
.info_node_1(info_node_1[12:0]),
.info_node_2(info_node_2[12:0]),
.info_node_3(info_node_3[12:0]),
.info_node_4(info_node_4[12:0]),
.info_node_5(info_node_5[12:0]),
.info_node_6(info_node_6[12:0]),
.info_node_7(info_node_7[12:0])
);
generate_code code(
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1[12:0]),
.info_node_2(info_node_2[12:0]),
.info_node_3(info_node_3[12:0]),
.info_node_4(info_node_4[12:0]),
.info_node_5(info_node_5[12:0]),
.info_node_6(info_node_6[12:0]),
.info_node_7(info_node_7[12:0]),
.CODE_TABLE(CODE_TABLE[15:0])
);
light_led light(
.CLK(CLK),
.nRST(nRST),
.CODE_TABLE(CODE_TABLE[15:0]),
.LED_DATA(DATA_OUT[3:0])
);
endmodule | 3 |
141,293 | data/full_repos/permissive/94604266/coding_test.v | 94,604,266 | coding_test.v | v | 58 | 81 | [] | [] | [] | [(25, 56)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/94604266/coding_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/94604266/coding_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n #DELAY CLK = ~ CLK;\n ^\n%Error: data/full_repos/permissive/94604266/coding_test.v:35: Cannot find file containing module: \'coding\'\n coding uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/coding\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/coding.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/coding.sv\n coding\n coding.v\n coding.sv\n obj_dir/coding\n obj_dir/coding.v\n obj_dir/coding.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 311,176 | module | module coding_test;
reg CLK;
reg nRST;
wire [7:0] DATA_OUT;
coding uut (
.CLK(CLK),
.nRST(nRST),
.DATA_OUT(DATA_OUT)
);
initial begin
CLK = 0;
nRST = 0;
#100;
nRST = 1;
end
parameter DELAY = 1;
always
#DELAY CLK = ~ CLK;
endmodule | module coding_test; |
reg CLK;
reg nRST;
wire [7:0] DATA_OUT;
coding uut (
.CLK(CLK),
.nRST(nRST),
.DATA_OUT(DATA_OUT)
);
initial begin
CLK = 0;
nRST = 0;
#100;
nRST = 1;
end
parameter DELAY = 1;
always
#DELAY CLK = ~ CLK;
endmodule | 3 |
141,295 | data/full_repos/permissive/94604266/count_frequent_test.v | 94,604,266 | count_frequent_test.v | v | 62 | 81 | [] | [] | [] | [(25, 60)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/94604266/count_frequent_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/94604266/count_frequent_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n #DELAY CLK =~CLK;\n ^\n%Error: data/full_repos/permissive/94604266/count_frequent_test.v:36: Cannot find file containing module: \'count_frequent\'\n count_frequent uut (\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/count_frequent\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/count_frequent.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/count_frequent.sv\n count_frequent\n count_frequent.v\n count_frequent.sv\n obj_dir/count_frequent\n obj_dir/count_frequent.v\n obj_dir/count_frequent.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 311,178 | module | module count_frequent_test;
reg CLK;
reg nRST;
reg [27:0] CHARACTER_IN;
wire [15:0] FREQUENT_OUT;
count_frequent uut (
.CLK(CLK),
.nRST(nRST),
.CHARACTER_IN(CHARACTER_IN),
.FREQUENT_OUT(FREQUENT_OUT)
);
initial begin
CLK = 0;
nRST = 0;
CHARACTER_IN = 28'b1010_1010_1100_1101_1101_1011_1011;
#100;
nRST = 1;
end
parameter DELAY = 1;
always
#DELAY CLK =~CLK;
endmodule | module count_frequent_test; |
reg CLK;
reg nRST;
reg [27:0] CHARACTER_IN;
wire [15:0] FREQUENT_OUT;
count_frequent uut (
.CLK(CLK),
.nRST(nRST),
.CHARACTER_IN(CHARACTER_IN),
.FREQUENT_OUT(FREQUENT_OUT)
);
initial begin
CLK = 0;
nRST = 0;
CHARACTER_IN = 28'b1010_1010_1100_1101_1101_1011_1011;
#100;
nRST = 1;
end
parameter DELAY = 1;
always
#DELAY CLK =~CLK;
endmodule | 3 |
141,298 | data/full_repos/permissive/94604266/decoding.v | 94,604,266 | decoding.v | v | 25 | 83 | [] | [] | [] | [(21, 24)] | null | null | 1: b"%Error: data/full_repos/permissive/94604266/decoding.v:21: Input/output/inout declaration not found for port: 'CLK'\nmodule decoding(CLK,nRST,EN,CODING_IN,DECODING_OUT);\n ^~~\n%Error: data/full_repos/permissive/94604266/decoding.v:21: Input/output/inout declaration not found for port: 'nRST'\nmodule decoding(CLK,nRST,EN,CODING_IN,DECODING_OUT);\n ^~~~\n%Error: data/full_repos/permissive/94604266/decoding.v:21: Input/output/inout declaration not found for port: 'EN'\nmodule decoding(CLK,nRST,EN,CODING_IN,DECODING_OUT);\n ^~\n%Error: data/full_repos/permissive/94604266/decoding.v:21: Input/output/inout declaration not found for port: 'CODING_IN'\nmodule decoding(CLK,nRST,EN,CODING_IN,DECODING_OUT);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/94604266/decoding.v:21: Input/output/inout declaration not found for port: 'DECODING_OUT'\nmodule decoding(CLK,nRST,EN,CODING_IN,DECODING_OUT);\n ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 311,183 | module | module decoding(CLK,nRST,EN,CODING_IN,DECODING_OUT);
endmodule | module decoding(CLK,nRST,EN,CODING_IN,DECODING_OUT); |
endmodule | 3 |
141,300 | data/full_repos/permissive/94604266/example_test.v | 94,604,266 | example_test.v | v | 94 | 81 | [] | [] | [] | [(25, 92)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/94604266/example_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/94604266/example_test.v:90: Unsupported: Ignoring delay on this delayed statement.\n #DELAY CLK = ~CLK; \n ^\n%Error: data/full_repos/permissive/94604266/example_test.v:49: Cannot find file containing module: \'example\'\n example uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/example\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/example.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/example.sv\n example\n example.v\n example.sv\n obj_dir/example\n obj_dir/example.v\n obj_dir/example.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 311,185 | module | module example_test;
reg CLK;
reg nRST;
reg [1:0] state;
reg [12:0] info_node_1;
reg [12:0] info_node_2;
reg [12:0] info_node_3;
reg [12:0] info_node_4;
reg [12:0] info_node_5;
reg [12:0] info_node_6;
reg [12:0] info_node_7;
wire [7:0] state1;
wire [7:0] state2;
wire [7:0] state3;
wire [7:0] state4;
wire [7:0] state5;
wire [7:0] state6;
wire [7:0] state7;
example uut (
.CLK(CLK),
.nRST(nRST),
.state(state),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.state1(state1),
.state2(state2),
.state3(state3),
.state4(state4),
.state5(state5),
.state6(state6),
.state7(state7)
);
initial begin
CLK = 0;
nRST = 0;
state = 2'b10;
info_node_1 = 13'b0000_0_0001_1010;
info_node_2 = 13'b0000_1_0001_1100;
info_node_3 = 13'b0001_0_0010_0010;
info_node_4 = 13'b0001_1_0010_1011;
info_node_5 = 13'b0010_0_0011_1101;
info_node_6 = 13'b0010_1_0100_0100;
info_node_7 = 13'b1111_1_0111_0111;
#100;
nRST = 1;
end
parameter DELAY = 2;
always
#DELAY CLK = ~CLK;
endmodule | module example_test; |
reg CLK;
reg nRST;
reg [1:0] state;
reg [12:0] info_node_1;
reg [12:0] info_node_2;
reg [12:0] info_node_3;
reg [12:0] info_node_4;
reg [12:0] info_node_5;
reg [12:0] info_node_6;
reg [12:0] info_node_7;
wire [7:0] state1;
wire [7:0] state2;
wire [7:0] state3;
wire [7:0] state4;
wire [7:0] state5;
wire [7:0] state6;
wire [7:0] state7;
example uut (
.CLK(CLK),
.nRST(nRST),
.state(state),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.state1(state1),
.state2(state2),
.state3(state3),
.state4(state4),
.state5(state5),
.state6(state6),
.state7(state7)
);
initial begin
CLK = 0;
nRST = 0;
state = 2'b10;
info_node_1 = 13'b0000_0_0001_1010;
info_node_2 = 13'b0000_1_0001_1100;
info_node_3 = 13'b0001_0_0010_0010;
info_node_4 = 13'b0001_1_0010_1011;
info_node_5 = 13'b0010_0_0011_1101;
info_node_6 = 13'b0010_1_0100_0100;
info_node_7 = 13'b1111_1_0111_0111;
#100;
nRST = 1;
end
parameter DELAY = 2;
always
#DELAY CLK = ~CLK;
endmodule | 3 |
141,301 | data/full_repos/permissive/94604266/generate_code.v | 94,604,266 | generate_code.v | v | 102 | 103 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd5 in position 483: invalid continuation byte | null | 1: b"%Error: data/full_repos/permissive/94604266/generate_code.v:62: Cannot find file containing module: 'select_not_leaf_state'\n select_not_leaf_state get_state(\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/select_not_leaf_state\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/select_not_leaf_state.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/select_not_leaf_state.sv\n select_not_leaf_state\n select_not_leaf_state.v\n select_not_leaf_state.sv\n obj_dir/select_not_leaf_state\n obj_dir/select_not_leaf_state.v\n obj_dir/select_not_leaf_state.sv\n%Error: data/full_repos/permissive/94604266/generate_code.v:74: Cannot find file containing module: 'select_leaf_node'\n select_leaf_node leaf_node(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/94604266/generate_code.v:90: Cannot find file containing module: 'create_node_code'\n create_node_code create(\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 311,186 | module | module generate_code(CLK,nRST,info_node_1,info_node_2,info_node_3,info_node_4,info_node_5,info_node_6,
info_node_7,CODE_TABLE);
input CLK;
input nRST;
input [12:0] info_node_1;
input [12:0] info_node_2;
input [12:0] info_node_3;
input [12:0] info_node_4;
input [12:0] info_node_5;
input [12:0] info_node_6;
input [12:0] info_node_7;
output [15:0] CODE_TABLE;
wire [1:0] state;
reg [12:0] temp_node;
reg [2:0] counter;
reg [7:0] state1;
reg [7:0] state2;
reg [7:0] state3;
reg [7:0] state4;
reg [7:0] state5;
reg [7:0] state6;
reg [7:0] state7;
wire [3:0] S0;
wire [3:0] S1;
wire [3:0] S2;
wire [12:0] leaf_A;
wire [12:0] leaf_B;
wire [12:0] leaf_C;
wire [12:0] leaf_D;
assign S0 = 4'b0000;
assign S1 = 4'b0001;
assign S2 = 4'b0010;
select_not_leaf_state get_state(
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.state(state)
);
select_leaf_node leaf_node(
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.leaf_A(leaf_A),
.leaf_B(leaf_B),
.leaf_C(leaf_C),
.leaf_D(leaf_D)
);
create_node_code create(
.CLK(CLK),
.nRST(nRST),
.state(state),
.leaf_A(leaf_A),
.leaf_B(leaf_B),
.leaf_C(leaf_C),
.leaf_D(leaf_D),
.CODE_TABLE(CODE_TABLE)
);
endmodule | module generate_code(CLK,nRST,info_node_1,info_node_2,info_node_3,info_node_4,info_node_5,info_node_6,
info_node_7,CODE_TABLE); |
input CLK;
input nRST;
input [12:0] info_node_1;
input [12:0] info_node_2;
input [12:0] info_node_3;
input [12:0] info_node_4;
input [12:0] info_node_5;
input [12:0] info_node_6;
input [12:0] info_node_7;
output [15:0] CODE_TABLE;
wire [1:0] state;
reg [12:0] temp_node;
reg [2:0] counter;
reg [7:0] state1;
reg [7:0] state2;
reg [7:0] state3;
reg [7:0] state4;
reg [7:0] state5;
reg [7:0] state6;
reg [7:0] state7;
wire [3:0] S0;
wire [3:0] S1;
wire [3:0] S2;
wire [12:0] leaf_A;
wire [12:0] leaf_B;
wire [12:0] leaf_C;
wire [12:0] leaf_D;
assign S0 = 4'b0000;
assign S1 = 4'b0001;
assign S2 = 4'b0010;
select_not_leaf_state get_state(
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.state(state)
);
select_leaf_node leaf_node(
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.leaf_A(leaf_A),
.leaf_B(leaf_B),
.leaf_C(leaf_C),
.leaf_D(leaf_D)
);
create_node_code create(
.CLK(CLK),
.nRST(nRST),
.state(state),
.leaf_A(leaf_A),
.leaf_B(leaf_B),
.leaf_C(leaf_C),
.leaf_D(leaf_D),
.CODE_TABLE(CODE_TABLE)
);
endmodule | 3 |
141,306 | data/full_repos/permissive/94604266/main.v | 94,604,266 | main.v | v | 34 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb1 in position 591: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/94604266/main.v:27: Cannot find file containing module: 'coding'\n coding huffman_coding(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/coding\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/coding.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/coding.sv\n coding\n coding.v\n coding.sv\n obj_dir/coding\n obj_dir/coding.v\n obj_dir/coding.sv\n%Error: Exiting due to 1 error(s)\n" | 311,192 | module | module main(CLK, RESET_Z, LED_DATA);
input CLK;
input RESET_Z;
(* KEEP="TRUE"*)output [3:0] LED_DATA;
coding huffman_coding(
.CLK(CLK),
.nRST(RESET_Z),
.DATA_OUT(LED_DATA[3:0])
);
endmodule | module main(CLK, RESET_Z, LED_DATA); |
input CLK;
input RESET_Z;
(* KEEP="TRUE"*)output [3:0] LED_DATA;
coding huffman_coding(
.CLK(CLK),
.nRST(RESET_Z),
.DATA_OUT(LED_DATA[3:0])
);
endmodule | 3 |
141,307 | data/full_repos/permissive/94604266/main_test.v | 94,604,266 | main_test.v | v | 58 | 81 | [] | [] | [] | [(25, 56)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/94604266/main_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/94604266/main_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n #DELAY CLK = ~CLK;\n ^\n%Error: data/full_repos/permissive/94604266/main_test.v:35: Cannot find file containing module: \'main\'\n main uut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/main\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/main.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/main.sv\n main\n main.v\n main.sv\n obj_dir/main\n obj_dir/main.v\n obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 311,193 | module | module main_test;
reg CLK;
reg RESET_Z;
wire [7:0] LED_DATA;
main uut (
.CLK(CLK),
.RESET_Z(RESET_Z),
.LED_DATA(LED_DATA)
);
initial begin
CLK = 0;
RESET_Z = 0;
#100;
RESET_Z = 1;
end
parameter DELAY = 1;
always
#DELAY CLK = ~CLK;
endmodule | module main_test; |
reg CLK;
reg RESET_Z;
wire [7:0] LED_DATA;
main uut (
.CLK(CLK),
.RESET_Z(RESET_Z),
.LED_DATA(LED_DATA)
);
initial begin
CLK = 0;
RESET_Z = 0;
#100;
RESET_Z = 1;
end
parameter DELAY = 1;
always
#DELAY CLK = ~CLK;
endmodule | 3 |
141,312 | data/full_repos/permissive/94604266/select_not_leaf_state.v | 94,604,266 | select_not_leaf_state.v | v | 158 | 111 | [] | [] | [] | [(21, 157)] | null | data/verilator_xmls/7fdded2b-daf0-4fc3-8712-7d8596f52ea6.xml | null | 311,198 | module | module select_not_leaf_state(CLK,nRST,info_node_1,info_node_2,info_node_3,info_node_4,info_node_5,info_node_6,
info_node_7,state);
input CLK;
input nRST;
input [12:0] info_node_1;
input [12:0] info_node_2;
input [12:0] info_node_3;
input [12:0] info_node_4;
input [12:0] info_node_5;
input [12:0] info_node_6;
input [12:0] info_node_7;
output [1:0] state;
reg state_S0;
reg state_S1;
reg state_S2;
reg [12:0] temp_node;
reg [11:0] counter;
wire [3:0] S1;
wire [3:0] S2;
assign S1 = 4'b0001;
assign S2 = 4'b0010;
always @ (posedge CLK or negedge nRST)
begin
if(!nRST)
counter <= 1;
else
begin
if(counter < 12'h00f)
begin
counter <= counter + 1;
case(counter)
12'h001: temp_node <= info_node_1;
12'h002: begin
temp_node <= info_node_1;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h003: temp_node <= info_node_2;
12'h004: begin
temp_node <= info_node_2;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h005: temp_node <= info_node_3;
12'h006: begin
temp_node <= info_node_3;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h007: temp_node <= info_node_4;
12'h008: begin
temp_node <= info_node_4;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h009: temp_node <= info_node_5;
12'h00a: begin
temp_node <= info_node_5;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h00b: temp_node <= info_node_6;
12'h00c: begin
temp_node <= info_node_6;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h00d: temp_node <= info_node_7;
12'h00e: begin
temp_node <= info_node_7;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
default:;
endcase
end
else;
end
end
assign state = {state_S2,state_S1};
endmodule | module select_not_leaf_state(CLK,nRST,info_node_1,info_node_2,info_node_3,info_node_4,info_node_5,info_node_6,
info_node_7,state); |
input CLK;
input nRST;
input [12:0] info_node_1;
input [12:0] info_node_2;
input [12:0] info_node_3;
input [12:0] info_node_4;
input [12:0] info_node_5;
input [12:0] info_node_6;
input [12:0] info_node_7;
output [1:0] state;
reg state_S0;
reg state_S1;
reg state_S2;
reg [12:0] temp_node;
reg [11:0] counter;
wire [3:0] S1;
wire [3:0] S2;
assign S1 = 4'b0001;
assign S2 = 4'b0010;
always @ (posedge CLK or negedge nRST)
begin
if(!nRST)
counter <= 1;
else
begin
if(counter < 12'h00f)
begin
counter <= counter + 1;
case(counter)
12'h001: temp_node <= info_node_1;
12'h002: begin
temp_node <= info_node_1;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h003: temp_node <= info_node_2;
12'h004: begin
temp_node <= info_node_2;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h005: temp_node <= info_node_3;
12'h006: begin
temp_node <= info_node_3;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h007: temp_node <= info_node_4;
12'h008: begin
temp_node <= info_node_4;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h009: temp_node <= info_node_5;
12'h00a: begin
temp_node <= info_node_5;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h00b: temp_node <= info_node_6;
12'h00c: begin
temp_node <= info_node_6;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
12'h00d: temp_node <= info_node_7;
12'h00e: begin
temp_node <= info_node_7;
if(temp_node[3:0] == temp_node[7:4])
begin
case(temp_node[12:9])
S1: state_S1 <= temp_node[8];
S2: state_S2 <= temp_node[8];
default:;
endcase
end
else;
end
default:;
endcase
end
else;
end
end
assign state = {state_S2,state_S1};
endmodule | 3 |
141,313 | data/full_repos/permissive/94604266/select_not_leaf_state_test.v | 94,604,266 | select_not_leaf_state_test.v | v | 79 | 81 | [] | [] | [] | [(25, 77)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/94604266/select_not_leaf_state_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/94604266/select_not_leaf_state_test.v:75: Unsupported: Ignoring delay on this delayed statement.\n #DELAY CLK = ~CLK; \n ^\n%Error: data/full_repos/permissive/94604266/select_not_leaf_state_test.v:42: Cannot find file containing module: \'select_not_leaf_state\'\n select_not_leaf_state uut (\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/select_not_leaf_state\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/select_not_leaf_state.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/select_not_leaf_state.sv\n select_not_leaf_state\n select_not_leaf_state.v\n select_not_leaf_state.sv\n obj_dir/select_not_leaf_state\n obj_dir/select_not_leaf_state.v\n obj_dir/select_not_leaf_state.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 311,199 | module | module select_not_leaf_state_test;
reg CLK;
reg nRST;
reg [12:0] info_node_1;
reg [12:0] info_node_2;
reg [12:0] info_node_3;
reg [12:0] info_node_4;
reg [12:0] info_node_5;
reg [12:0] info_node_6;
reg [12:0] info_node_7;
wire [1:0] state;
select_not_leaf_state uut (
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.state(state)
);
initial begin
CLK = 0;
nRST = 0;
info_node_1 = 13'b0000_0_0001_1010;
info_node_2 = 13'b0000_1_0001_1100;
info_node_3 = 13'b0001_0_0010_0010;
info_node_4 = 13'b0001_1_0010_1011;
info_node_5 = 13'b0010_0_0011_1101;
info_node_6 = 13'b0010_1_0100_0100;
info_node_7 = 13'b1111_1_0111_0111;
#100;
nRST = 1;
end
parameter DELAY = 2;
always
#DELAY CLK = ~CLK;
endmodule | module select_not_leaf_state_test; |
reg CLK;
reg nRST;
reg [12:0] info_node_1;
reg [12:0] info_node_2;
reg [12:0] info_node_3;
reg [12:0] info_node_4;
reg [12:0] info_node_5;
reg [12:0] info_node_6;
reg [12:0] info_node_7;
wire [1:0] state;
select_not_leaf_state uut (
.CLK(CLK),
.nRST(nRST),
.info_node_1(info_node_1),
.info_node_2(info_node_2),
.info_node_3(info_node_3),
.info_node_4(info_node_4),
.info_node_5(info_node_5),
.info_node_6(info_node_6),
.info_node_7(info_node_7),
.state(state)
);
initial begin
CLK = 0;
nRST = 0;
info_node_1 = 13'b0000_0_0001_1010;
info_node_2 = 13'b0000_1_0001_1100;
info_node_3 = 13'b0001_0_0010_0010;
info_node_4 = 13'b0001_1_0010_1011;
info_node_5 = 13'b0010_0_0011_1101;
info_node_6 = 13'b0010_1_0100_0100;
info_node_7 = 13'b1111_1_0111_0111;
#100;
nRST = 1;
end
parameter DELAY = 2;
always
#DELAY CLK = ~CLK;
endmodule | 3 |
141,314 | data/full_repos/permissive/94604266/sort2.v | 94,604,266 | sort2.v | v | 53 | 83 | [] | [] | [] | [(21, 52)] | null | data/verilator_xmls/c9d10618-5296-4a0e-ad9c-fce3b8aba0d2.xml | null | 311,200 | module | module sort2(CLK,nRST,node1,node2,new1,new2);
input CLK;
input nRST;
input [7:0] node1;
input [7:0] node2;
output [7:0] new1;
output [7:0] new2;
reg [7:0] new1;
reg [7:0] new2;
always @ (posedge CLK or negedge nRST)
begin
if(!nRST)
begin
new1 <= 8'b0;
new2 <= 8'b0;
end
else
begin
new1 <= node1;
new2 <= node2;
if(new1[7:4] > new2[7:4])
begin
new1 <= new2;
new2 <= new1;
end
else;
end
end
endmodule | module sort2(CLK,nRST,node1,node2,new1,new2); |
input CLK;
input nRST;
input [7:0] node1;
input [7:0] node2;
output [7:0] new1;
output [7:0] new2;
reg [7:0] new1;
reg [7:0] new2;
always @ (posedge CLK or negedge nRST)
begin
if(!nRST)
begin
new1 <= 8'b0;
new2 <= 8'b0;
end
else
begin
new1 <= node1;
new2 <= node2;
if(new1[7:4] > new2[7:4])
begin
new1 <= new2;
new2 <= new1;
end
else;
end
end
endmodule | 3 |
141,316 | data/full_repos/permissive/94604266/sort3.v | 94,604,266 | sort3.v | v | 82 | 83 | [] | [] | [] | [(21, 81)] | null | null | 1: b"%Error: data/full_repos/permissive/94604266/sort3.v:40: Cannot find file containing module: 'sort2'\n sort2 s2_1(\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort2\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort2.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort2.sv\n sort2\n sort2.v\n sort2.sv\n obj_dir/sort2\n obj_dir/sort2.v\n obj_dir/sort2.sv\n%Error: Exiting due to 1 error(s)\n" | 311,202 | module | module sort3(CLK,nRST,node1,node2,node3,new1,new2,new3);
input CLK;
input nRST;
input [7:0] node1;
input [7:0] node2;
input [7:0] node3;
output [7:0] new1;
output [7:0] new2;
output [7:0] new3;
reg [7:0] new1;
reg [7:0] new2;
reg [7:0] new3;
reg [7:0] temp;
wire [7:0] temp1;
wire [7:0] temp2;
sort2 s2_1(
.CLK(CLK),
.nRST(nRST),
.node1(node1),
.node2(node2),
.new1(temp1),
.new2(temp2)
);
always @(posedge CLK or negedge nRST)
begin
if(!nRST)
begin
new1 <= 8'b0;
new2 <= 8'b0;
new3 <= 8'b0;
end
else
begin
temp <= node3;
if(temp[7:4] <= temp1[7:4])
begin
new1 <= temp;
new2 <= temp1;
new3 <= temp2;
end
else if(temp[7:4] > temp1[7:4] && temp[7:4] <= temp2[7:4])
begin
new1 <= temp1;
new2 <= temp;
new3 <= temp2;
end
else
begin
new1 <= temp1;
new2 <= temp2;
new3 <= temp;
end
end
end
endmodule | module sort3(CLK,nRST,node1,node2,node3,new1,new2,new3); |
input CLK;
input nRST;
input [7:0] node1;
input [7:0] node2;
input [7:0] node3;
output [7:0] new1;
output [7:0] new2;
output [7:0] new3;
reg [7:0] new1;
reg [7:0] new2;
reg [7:0] new3;
reg [7:0] temp;
wire [7:0] temp1;
wire [7:0] temp2;
sort2 s2_1(
.CLK(CLK),
.nRST(nRST),
.node1(node1),
.node2(node2),
.new1(temp1),
.new2(temp2)
);
always @(posedge CLK or negedge nRST)
begin
if(!nRST)
begin
new1 <= 8'b0;
new2 <= 8'b0;
new3 <= 8'b0;
end
else
begin
temp <= node3;
if(temp[7:4] <= temp1[7:4])
begin
new1 <= temp;
new2 <= temp1;
new3 <= temp2;
end
else if(temp[7:4] > temp1[7:4] && temp[7:4] <= temp2[7:4])
begin
new1 <= temp1;
new2 <= temp;
new3 <= temp2;
end
else
begin
new1 <= temp1;
new2 <= temp2;
new3 <= temp;
end
end
end
endmodule | 3 |
141,318 | data/full_repos/permissive/94604266/sort_frequent.v | 94,604,266 | sort_frequent.v | v | 49 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbd in position 483: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/94604266/sort_frequent.v:38: Cannot find file containing module: 'bubble_sort'\n bubble_sort sort(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/bubble_sort\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/bubble_sort.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/bubble_sort.sv\n bubble_sort\n bubble_sort.v\n bubble_sort.sv\n obj_dir/bubble_sort\n obj_dir/bubble_sort.v\n obj_dir/bubble_sort.sv\n%Error: Exiting due to 1 error(s)\n" | 311,204 | module | module sort_frequent(CLK,nRST,FREQUENT_IN,FREQUENT_OUT);
input CLK;
input nRST;
input [15:0] FREQUENT_IN;
output [31:0] FREQUENT_OUT;
wire [7:0] weight_A;
wire [7:0] weight_B;
wire [7:0] weight_C;
wire [7:0] weight_D;
assign weight_A[7:0] = {FREQUENT_IN[3:0],4'b1010};
assign weight_B[7:0] = {FREQUENT_IN[7:4],4'b1011};
assign weight_C[7:0] = {FREQUENT_IN[11:8],4'b1100};
assign weight_D[7:0] = {FREQUENT_IN[15:12],4'b1101};
bubble_sort sort(
.CLK(CLK),
.nRST(nRST),
.weight_A(weight_A),
.weight_B(weight_B),
.weight_C(weight_C),
.weight_D(weight_D),
.SORT_RESULT(FREQUENT_OUT[31:0])
);
endmodule | module sort_frequent(CLK,nRST,FREQUENT_IN,FREQUENT_OUT); |
input CLK;
input nRST;
input [15:0] FREQUENT_IN;
output [31:0] FREQUENT_OUT;
wire [7:0] weight_A;
wire [7:0] weight_B;
wire [7:0] weight_C;
wire [7:0] weight_D;
assign weight_A[7:0] = {FREQUENT_IN[3:0],4'b1010};
assign weight_B[7:0] = {FREQUENT_IN[7:4],4'b1011};
assign weight_C[7:0] = {FREQUENT_IN[11:8],4'b1100};
assign weight_D[7:0] = {FREQUENT_IN[15:12],4'b1101};
bubble_sort sort(
.CLK(CLK),
.nRST(nRST),
.weight_A(weight_A),
.weight_B(weight_B),
.weight_C(weight_C),
.weight_D(weight_D),
.SORT_RESULT(FREQUENT_OUT[31:0])
);
endmodule | 3 |
141,319 | data/full_repos/permissive/94604266/sort_frequent_test.v | 94,604,266 | sort_frequent_test.v | v | 62 | 81 | [] | [] | [] | [(25, 60)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/94604266/sort_frequent_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/94604266/sort_frequent_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n #DELAY CLK = ~CLK;\n ^\n%Error: data/full_repos/permissive/94604266/sort_frequent_test.v:36: Cannot find file containing module: \'sort_frequent\'\n sort_frequent uut (\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort_frequent\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort_frequent.v\n data/full_repos/permissive/94604266,data/full_repos/permissive/94604266/sort_frequent.sv\n sort_frequent\n sort_frequent.v\n sort_frequent.sv\n obj_dir/sort_frequent\n obj_dir/sort_frequent.v\n obj_dir/sort_frequent.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 311,205 | module | module sort_frequent_test;
reg CLK;
reg nRST;
reg [15:0] FREQUENT_IN;
wire [31:0] FREQUENT_OUT;
sort_frequent uut (
.CLK(CLK),
.nRST(nRST),
.FREQUENT_IN(FREQUENT_IN),
.FREQUENT_OUT(FREQUENT_OUT)
);
initial begin
CLK = 0;
nRST = 0;
FREQUENT_IN = 16'b0011_0001_0010_0001;
#100;
nRST = 1;
end
parameter DELAY = 1;
always
#DELAY CLK = ~CLK;
endmodule | module sort_frequent_test; |
reg CLK;
reg nRST;
reg [15:0] FREQUENT_IN;
wire [31:0] FREQUENT_OUT;
sort_frequent uut (
.CLK(CLK),
.nRST(nRST),
.FREQUENT_IN(FREQUENT_IN),
.FREQUENT_OUT(FREQUENT_OUT)
);
initial begin
CLK = 0;
nRST = 0;
FREQUENT_IN = 16'b0011_0001_0010_0001;
#100;
nRST = 1;
end
parameter DELAY = 1;
always
#DELAY CLK = ~CLK;
endmodule | 3 |
Subsets and Splits