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140,915 | data/full_repos/permissive/92697978/dsm_stereo.v | 92,697,978 | dsm_stereo.v | v | 35 | 60 | [] | [] | [] | [(3, 34)] | null | data/verilator_xmls/100ba39a-b157-4e47-96c4-38af0dd1c7d0.xml | null | 309,922 | module | module dsm_stereo
#(parameter DSM_WIDTH = 12)
(
input clk,
input aclr,
input [DSM_WIDTH-1:0] left_pcm,
input [DSM_WIDTH-1:0] right_pcm,
output left_out,
output right_out
);
reg [DSM_WIDTH:0] left_accum = 0;
reg [DSM_WIDTH:0] right_accum = 0;
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
left_accum <= 0;
right_accum <= 0;
end
else
begin
left_accum <= left_accum[DSM_WIDTH-1:0] + left_pcm;
right_accum <= right_accum[DSM_WIDTH-1:0] + right_pcm;
end
end
assign left_out = left_accum[DSM_WIDTH];
assign right_out = right_accum[DSM_WIDTH];
endmodule | module dsm_stereo
#(parameter DSM_WIDTH = 12)
(
input clk,
input aclr,
input [DSM_WIDTH-1:0] left_pcm,
input [DSM_WIDTH-1:0] right_pcm,
output left_out,
output right_out
); |
reg [DSM_WIDTH:0] left_accum = 0;
reg [DSM_WIDTH:0] right_accum = 0;
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
left_accum <= 0;
right_accum <= 0;
end
else
begin
left_accum <= left_accum[DSM_WIDTH-1:0] + left_pcm;
right_accum <= right_accum[DSM_WIDTH-1:0] + right_pcm;
end
end
assign left_out = left_accum[DSM_WIDTH];
assign right_out = right_accum[DSM_WIDTH];
endmodule | 0 |
140,916 | data/full_repos/permissive/92697978/dsm_stereo_tb.v | 92,697,978 | dsm_stereo_tb.v | v | 43 | 42 | [] | [] | [] | null | line:5: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_PERIOD_NS/2) clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 4096)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 4096)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 4096)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/dsm_stereo_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 4096)\n ^\n%Error: data/full_repos/permissive/92697978/dsm_stereo_tb.v:11: Cannot find file containing module: \'dsm_stereo\'\n dsm_stereo #(DSM_WIDTH) MUT\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/dsm_stereo\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/dsm_stereo.v\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/dsm_stereo.sv\n dsm_stereo\n dsm_stereo.v\n dsm_stereo.sv\n obj_dir/dsm_stereo\n obj_dir/dsm_stereo.v\n obj_dir/dsm_stereo.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,923 | module | module dsm_stereo_tb ();
localparam CLOCK_PERIOD_NS = 20;
localparam DSM_WIDTH = 12;
reg clk = 0, aclr = 0;
reg [DSM_WIDTH-1:0] left = 0, right = 0;
wire left_out, right_out;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
dsm_stereo #(DSM_WIDTH) MUT
(
.aclr(aclr),
.clk(clk),
.left_pcm(left),
.right_pcm(right),
.left_out(left_out),
.right_out(right_out)
);
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1;
#CLOCK_PERIOD_NS
aclr <= 0;
#CLOCK_PERIOD_NS
left = 12'd127;
#(CLOCK_PERIOD_NS * 4096)
left = 12'd0;
right = 12'd1024;
#(CLOCK_PERIOD_NS * 4096)
left = 12'd2048;
right = 12'd3750;
#(CLOCK_PERIOD_NS * 4096)
left = 12'd0;
right = 12'd0;
#(CLOCK_PERIOD_NS * 4096)
$finish;
end
endmodule | module dsm_stereo_tb (); |
localparam CLOCK_PERIOD_NS = 20;
localparam DSM_WIDTH = 12;
reg clk = 0, aclr = 0;
reg [DSM_WIDTH-1:0] left = 0, right = 0;
wire left_out, right_out;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
dsm_stereo #(DSM_WIDTH) MUT
(
.aclr(aclr),
.clk(clk),
.left_pcm(left),
.right_pcm(right),
.left_out(left_out),
.right_out(right_out)
);
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1;
#CLOCK_PERIOD_NS
aclr <= 0;
#CLOCK_PERIOD_NS
left = 12'd127;
#(CLOCK_PERIOD_NS * 4096)
left = 12'd0;
right = 12'd1024;
#(CLOCK_PERIOD_NS * 4096)
left = 12'd2048;
right = 12'd3750;
#(CLOCK_PERIOD_NS * 4096)
left = 12'd0;
right = 12'd0;
#(CLOCK_PERIOD_NS * 4096)
$finish;
end
endmodule | 0 |
140,917 | data/full_repos/permissive/92697978/pll_12bit_44_1kHz_sim.v | 92,697,978 | pll_12bit_44_1kHz_sim.v | v | 32 | 50 | [] | [] | [] | null | line:8: before: "=" | data/verilator_xmls/2ef19fe3-e161-4a4d-8d2a-f355f169fcd2.xml | null | 309,930 | module | module pll_12bit_44_1kHz_sim
(
input areset,
input inclk0,
output c0,
output reg locked = 1
);
assign c0 = !inclk0;
endmodule | module pll_12bit_44_1kHz_sim
(
input areset,
input inclk0,
output c0,
output reg locked = 1
); |
assign c0 = !inclk0;
endmodule | 0 |
140,918 | data/full_repos/permissive/92697978/pll_12bit_44_1kHz_sim_tb.v | 92,697,978 | pll_12bit_44_1kHz_sim_tb.v | v | 17 | 35 | [] | [] | [] | [(3, 16)] | null | null | 1: b"%Error: data/full_repos/permissive/92697978/pll_12bit_44_1kHz_sim_tb.v:6: Cannot find file containing module: 'pll_12bit_44_1kHz_sim'\n pll_12bit_44_1kHz_sim MUT\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/pll_12bit_44_1kHz_sim\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/pll_12bit_44_1kHz_sim.v\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/pll_12bit_44_1kHz_sim.sv\n pll_12bit_44_1kHz_sim\n pll_12bit_44_1kHz_sim.v\n pll_12bit_44_1kHz_sim.sv\n obj_dir/pll_12bit_44_1kHz_sim\n obj_dir/pll_12bit_44_1kHz_sim.v\n obj_dir/pll_12bit_44_1kHz_sim.sv\n%Error: Exiting due to 1 error(s)\n" | 309,931 | module | module pll_12bit_44_1kHz_sim_tb();
wire aclr, clk, c0, locked;
pll_12bit_44_1kHz_sim MUT
(
.areset(aclr),
.inclk0(clk),
.c0(c0),
.locked(locked)
);
assign #(10) clk = !clk;
endmodule | module pll_12bit_44_1kHz_sim_tb(); |
wire aclr, clk, c0, locked;
pll_12bit_44_1kHz_sim MUT
(
.areset(aclr),
.inclk0(clk),
.c0(c0),
.locked(locked)
);
assign #(10) clk = !clk;
endmodule | 0 |
140,919 | data/full_repos/permissive/92697978/tone_generator.v | 92,697,978 | tone_generator.v | v | 93 | 52 | [] | ['mit license'] | [] | null | line:15: before: "=" | null | 1: b"%Error: data/full_repos/permissive/92697978/tone_generator.v:24: Cannot find file containing module: 'audio_44_1kHz'\n audio_44_1kHz #(AUDIO_BITS) MUT\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audio_44_1kHz\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audio_44_1kHz.v\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audio_44_1kHz.sv\n audio_44_1kHz\n audio_44_1kHz.v\n audio_44_1kHz.sv\n obj_dir/audio_44_1kHz\n obj_dir/audio_44_1kHz.v\n obj_dir/audio_44_1kHz.sv\n%Error: Exiting due to 1 error(s)\n" | 309,932 | module | module tone_generator
#(parameter AUDIO_BITS = 12)
(
input clk,
input aclr_,
output wire clk_audio,
output wire left_out,
output wire right_out,
output wire pll_locked,
output reg status = 0,
output wire ready
);
reg wreq = 0;
reg [(AUDIO_BITS*2)-1:0] sample = 0;
reg [31:0] count = 0;
reg [AUDIO_BITS-1:0] sout = 12'd4095;
audio_44_1kHz #(AUDIO_BITS) MUT
(
.clk(clk),
.aclr_(aclr_),
.clk_audio(clk_audio),
.wreq(wreq),
.sample(sample),
.left_out(left_out),
.right_out(right_out),
.pll_locked(pll_locked),
.ready(ready)
);
always @(posedge clk_audio or negedge aclr_)
begin
if (!aclr_)
begin
wreq <= 0;
sample <= 0;
end
else
begin
if (ready)
begin
wreq <= 1;
sample[(AUDIO_BITS*2)-1:AUDIO_BITS] <= sout;
sample[AUDIO_BITS-1:0] <= sout;
end
else
begin
wreq <= 0;
sample <= 0;
end
end
end
always @(posedge clk_audio or negedge aclr_)
begin
if (!aclr_)
sout <= 4095;
else
begin
if (count % 180633 == 0)
sout <= sout - 12'd1;
else
sout <= sout;
end
end
always @(posedge clk_audio or negedge aclr_)
begin
if (!aclr_)
count <= 0;
else
begin
if (count == 44100 * 4096)
begin
status <= !status;
count <= 0;
end
else
begin
count <= count + 1;
status <= status;
end
end
end
endmodule | module tone_generator
#(parameter AUDIO_BITS = 12)
(
input clk,
input aclr_,
output wire clk_audio,
output wire left_out,
output wire right_out,
output wire pll_locked,
output reg status = 0,
output wire ready
); |
reg wreq = 0;
reg [(AUDIO_BITS*2)-1:0] sample = 0;
reg [31:0] count = 0;
reg [AUDIO_BITS-1:0] sout = 12'd4095;
audio_44_1kHz #(AUDIO_BITS) MUT
(
.clk(clk),
.aclr_(aclr_),
.clk_audio(clk_audio),
.wreq(wreq),
.sample(sample),
.left_out(left_out),
.right_out(right_out),
.pll_locked(pll_locked),
.ready(ready)
);
always @(posedge clk_audio or negedge aclr_)
begin
if (!aclr_)
begin
wreq <= 0;
sample <= 0;
end
else
begin
if (ready)
begin
wreq <= 1;
sample[(AUDIO_BITS*2)-1:AUDIO_BITS] <= sout;
sample[AUDIO_BITS-1:0] <= sout;
end
else
begin
wreq <= 0;
sample <= 0;
end
end
end
always @(posedge clk_audio or negedge aclr_)
begin
if (!aclr_)
sout <= 4095;
else
begin
if (count % 180633 == 0)
sout <= sout - 12'd1;
else
sout <= sout;
end
end
always @(posedge clk_audio or negedge aclr_)
begin
if (!aclr_)
count <= 0;
else
begin
if (count == 44100 * 4096)
begin
status <= !status;
count <= 0;
end
else
begin
count <= count + 1;
status <= status;
end
end
end
endmodule | 0 |
140,923 | data/full_repos/permissive/92788834/verilog/Butterfly.v | 92,788,834 | Butterfly.v | v | 33 | 73 | [] | [] | [] | [(4, 32)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Butterfly.v:27: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 or 17 bits.\n : ... In instance Butterfly\nassign y0_re = (add_re + RH) >>> 1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Butterfly.v:28: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 or 17 bits.\n : ... In instance Butterfly\nassign y0_im = (add_im + RH) >>> 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Butterfly.v:29: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 or 17 bits.\n : ... In instance Butterfly\nassign y1_re = (sub_re + RH) >>> 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Butterfly.v:30: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 or 17 bits.\n : ... In instance Butterfly\nassign y1_im = (sub_im + RH) >>> 1;\n ^\n%Error: Exiting due to 4 warning(s)\n' | 309,939 | module | module Butterfly #(
parameter WIDTH = 16,
parameter RH = 0
)(
input signed [WIDTH-1:0] x0_re,
input signed [WIDTH-1:0] x0_im,
input signed [WIDTH-1:0] x1_re,
input signed [WIDTH-1:0] x1_im,
output signed [WIDTH-1:0] y0_re,
output signed [WIDTH-1:0] y0_im,
output signed [WIDTH-1:0] y1_re,
output signed [WIDTH-1:0] y1_im
);
wire signed [WIDTH:0] add_re, add_im, sub_re, sub_im;
assign add_re = x0_re + x1_re;
assign add_im = x0_im + x1_im;
assign sub_re = x0_re - x1_re;
assign sub_im = x0_im - x1_im;
assign y0_re = (add_re + RH) >>> 1;
assign y0_im = (add_im + RH) >>> 1;
assign y1_re = (sub_re + RH) >>> 1;
assign y1_im = (sub_im + RH) >>> 1;
endmodule | module Butterfly #(
parameter WIDTH = 16,
parameter RH = 0
)(
input signed [WIDTH-1:0] x0_re,
input signed [WIDTH-1:0] x0_im,
input signed [WIDTH-1:0] x1_re,
input signed [WIDTH-1:0] x1_im,
output signed [WIDTH-1:0] y0_re,
output signed [WIDTH-1:0] y0_im,
output signed [WIDTH-1:0] y1_re,
output signed [WIDTH-1:0] y1_im
); |
wire signed [WIDTH:0] add_re, add_im, sub_re, sub_im;
assign add_re = x0_re + x1_re;
assign add_im = x0_im + x1_im;
assign sub_re = x0_re - x1_re;
assign sub_im = x0_im - x1_im;
assign y0_re = (add_re + RH) >>> 1;
assign y0_im = (add_im + RH) >>> 1;
assign y1_re = (sub_re + RH) >>> 1;
assign y1_im = (sub_im + RH) >>> 1;
endmodule | 11 |
140,924 | data/full_repos/permissive/92788834/verilog/DelayBuffer.v | 92,788,834 | DelayBuffer.v | v | 33 | 73 | [] | [] | [] | [(4, 32)] | null | data/verilator_xmls/7ce37330-0615-4dc6-9417-9c26e9be5331.xml | null | 309,940 | module | module DelayBuffer #(
parameter DEPTH = 32,
parameter WIDTH = 16
)(
input clock,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
);
reg [WIDTH-1:0] buf_re[0:DEPTH-1];
reg [WIDTH-1:0] buf_im[0:DEPTH-1];
integer n;
always @(posedge clock) begin
for (n = DEPTH-1; n > 0; n = n - 1) begin
buf_re[n] <= buf_re[n-1];
buf_im[n] <= buf_im[n-1];
end
buf_re[0] <= di_re;
buf_im[0] <= di_im;
end
assign do_re = buf_re[DEPTH-1];
assign do_im = buf_im[DEPTH-1];
endmodule | module DelayBuffer #(
parameter DEPTH = 32,
parameter WIDTH = 16
)(
input clock,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
); |
reg [WIDTH-1:0] buf_re[0:DEPTH-1];
reg [WIDTH-1:0] buf_im[0:DEPTH-1];
integer n;
always @(posedge clock) begin
for (n = DEPTH-1; n > 0; n = n - 1) begin
buf_re[n] <= buf_re[n-1];
buf_im[n] <= buf_im[n-1];
end
buf_re[0] <= di_re;
buf_im[0] <= di_im;
end
assign do_re = buf_re[DEPTH-1];
assign do_im = buf_im[DEPTH-1];
endmodule | 11 |
140,926 | data/full_repos/permissive/92788834/verilog/FFT128.v | 92,788,834 | FFT128.v | v | 77 | 73 | [] | [] | [] | [(4, 76)] | null | null | 1: b"%Error: data/full_repos/permissive/92788834/verilog/FFT128.v:32: Cannot find file containing module: 'SdfUnit'\nSdfUnit #(.N(128),.M(128),.WIDTH(WIDTH)) SU1 (\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/SdfUnit\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/SdfUnit.v\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/SdfUnit.sv\n SdfUnit\n SdfUnit.v\n SdfUnit.sv\n obj_dir/SdfUnit\n obj_dir/SdfUnit.v\n obj_dir/SdfUnit.sv\n%Error: data/full_repos/permissive/92788834/verilog/FFT128.v:43: Cannot find file containing module: 'SdfUnit'\nSdfUnit #(.N(128),.M(32),.WIDTH(WIDTH)) SU2 (\n^~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/FFT128.v:54: Cannot find file containing module: 'SdfUnit'\nSdfUnit #(.N(128),.M(8),.WIDTH(WIDTH)) SU3 (\n^~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/FFT128.v:65: Cannot find file containing module: 'SdfUnit2'\nSdfUnit2 #(.WIDTH(WIDTH)) SU4 (\n^~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 309,942 | module | module FFT #(
parameter WIDTH = 16
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output do_en,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
);
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
wire su3_do_en;
wire[WIDTH-1:0] su3_do_re;
wire[WIDTH-1:0] su3_do_im;
SdfUnit #(.N(128),.M(128),.WIDTH(WIDTH)) SU1 (
.clock (clock ),
.reset (reset ),
.di_en (di_en ),
.di_re (di_re ),
.di_im (di_im ),
.do_en (su1_do_en ),
.do_re (su1_do_re ),
.do_im (su1_do_im )
);
SdfUnit #(.N(128),.M(32),.WIDTH(WIDTH)) SU2 (
.clock (clock ),
.reset (reset ),
.di_en (su1_do_en ),
.di_re (su1_do_re ),
.di_im (su1_do_im ),
.do_en (su2_do_en ),
.do_re (su2_do_re ),
.do_im (su2_do_im )
);
SdfUnit #(.N(128),.M(8),.WIDTH(WIDTH)) SU3 (
.clock (clock ),
.reset (reset ),
.di_en (su2_do_en ),
.di_re (su2_do_re ),
.di_im (su2_do_im ),
.do_en (su3_do_en ),
.do_re (su3_do_re ),
.do_im (su3_do_im )
);
SdfUnit2 #(.WIDTH(WIDTH)) SU4 (
.clock (clock ),
.reset (reset ),
.di_en (su3_do_en ),
.di_re (su3_do_re ),
.di_im (su3_do_im ),
.do_en (do_en ),
.do_re (do_re ),
.do_im (do_im )
);
endmodule | module FFT #(
parameter WIDTH = 16
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output do_en,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
); |
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
wire su3_do_en;
wire[WIDTH-1:0] su3_do_re;
wire[WIDTH-1:0] su3_do_im;
SdfUnit #(.N(128),.M(128),.WIDTH(WIDTH)) SU1 (
.clock (clock ),
.reset (reset ),
.di_en (di_en ),
.di_re (di_re ),
.di_im (di_im ),
.do_en (su1_do_en ),
.do_re (su1_do_re ),
.do_im (su1_do_im )
);
SdfUnit #(.N(128),.M(32),.WIDTH(WIDTH)) SU2 (
.clock (clock ),
.reset (reset ),
.di_en (su1_do_en ),
.di_re (su1_do_re ),
.di_im (su1_do_im ),
.do_en (su2_do_en ),
.do_re (su2_do_re ),
.do_im (su2_do_im )
);
SdfUnit #(.N(128),.M(8),.WIDTH(WIDTH)) SU3 (
.clock (clock ),
.reset (reset ),
.di_en (su2_do_en ),
.di_re (su2_do_re ),
.di_im (su2_do_im ),
.do_en (su3_do_en ),
.do_re (su3_do_re ),
.do_im (su3_do_im )
);
SdfUnit2 #(.WIDTH(WIDTH)) SU4 (
.clock (clock ),
.reset (reset ),
.di_en (su3_do_en ),
.di_re (su3_do_re ),
.di_im (su3_do_im ),
.do_en (do_en ),
.do_re (do_re ),
.do_im (do_im )
);
endmodule | 11 |
140,927 | data/full_repos/permissive/92788834/verilog/FFT64.v | 92,788,834 | FFT64.v | v | 63 | 73 | [] | [] | [] | [(4, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/92788834/verilog/FFT64.v:29: Cannot find file containing module: 'SdfUnit'\nSdfUnit #(.N(64),.M(64),.WIDTH(WIDTH)) SU1 (\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/SdfUnit\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/SdfUnit.v\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/SdfUnit.sv\n SdfUnit\n SdfUnit.v\n SdfUnit.sv\n obj_dir/SdfUnit\n obj_dir/SdfUnit.v\n obj_dir/SdfUnit.sv\n%Error: data/full_repos/permissive/92788834/verilog/FFT64.v:40: Cannot find file containing module: 'SdfUnit'\nSdfUnit #(.N(64),.M(16),.WIDTH(WIDTH)) SU2 (\n^~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/FFT64.v:51: Cannot find file containing module: 'SdfUnit'\nSdfUnit #(.N(64),.M(4),.WIDTH(WIDTH)) SU3 (\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 309,943 | module | module FFT #(
parameter WIDTH = 16
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output do_en,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
);
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
SdfUnit #(.N(64),.M(64),.WIDTH(WIDTH)) SU1 (
.clock (clock ),
.reset (reset ),
.di_en (di_en ),
.di_re (di_re ),
.di_im (di_im ),
.do_en (su1_do_en ),
.do_re (su1_do_re ),
.do_im (su1_do_im )
);
SdfUnit #(.N(64),.M(16),.WIDTH(WIDTH)) SU2 (
.clock (clock ),
.reset (reset ),
.di_en (su1_do_en ),
.di_re (su1_do_re ),
.di_im (su1_do_im ),
.do_en (su2_do_en ),
.do_re (su2_do_re ),
.do_im (su2_do_im )
);
SdfUnit #(.N(64),.M(4),.WIDTH(WIDTH)) SU3 (
.clock (clock ),
.reset (reset ),
.di_en (su2_do_en ),
.di_re (su2_do_re ),
.di_im (su2_do_im ),
.do_en (do_en ),
.do_re (do_re ),
.do_im (do_im )
);
endmodule | module FFT #(
parameter WIDTH = 16
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output do_en,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
); |
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
SdfUnit #(.N(64),.M(64),.WIDTH(WIDTH)) SU1 (
.clock (clock ),
.reset (reset ),
.di_en (di_en ),
.di_re (di_re ),
.di_im (di_im ),
.do_en (su1_do_en ),
.do_re (su1_do_re ),
.do_im (su1_do_im )
);
SdfUnit #(.N(64),.M(16),.WIDTH(WIDTH)) SU2 (
.clock (clock ),
.reset (reset ),
.di_en (su1_do_en ),
.di_re (su1_do_re ),
.di_im (su1_do_im ),
.do_en (su2_do_en ),
.do_re (su2_do_re ),
.do_im (su2_do_im )
);
SdfUnit #(.N(64),.M(4),.WIDTH(WIDTH)) SU3 (
.clock (clock ),
.reset (reset ),
.di_en (su2_do_en ),
.di_re (su2_do_re ),
.di_im (su2_do_im ),
.do_en (do_en ),
.do_re (do_re ),
.do_im (do_im )
);
endmodule | 11 |
140,928 | data/full_repos/permissive/92788834/verilog/Multiply.v | 92,788,834 | Multiply.v | v | 36 | 73 | [] | [] | [] | [(4, 35)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Multiply.v:25: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 bits.\n : ... In instance Multiply\nassign sc_arbr = arbr >>> (WIDTH-1);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Multiply.v:26: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 bits.\n : ... In instance Multiply\nassign sc_arbi = arbi >>> (WIDTH-1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Multiply.v:27: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 bits.\n : ... In instance Multiply\nassign sc_aibr = aibr >>> (WIDTH-1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/Multiply.v:28: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 bits.\n : ... In instance Multiply\nassign sc_aibi = aibi >>> (WIDTH-1);\n ^\n%Error: Exiting due to 4 warning(s)\n' | 309,944 | module | module Multiply #(
parameter WIDTH = 16
)(
input signed [WIDTH-1:0] a_re,
input signed [WIDTH-1:0] a_im,
input signed [WIDTH-1:0] b_re,
input signed [WIDTH-1:0] b_im,
output signed [WIDTH-1:0] m_re,
output signed [WIDTH-1:0] m_im
);
wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi;
wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi;
assign arbr = a_re * b_re;
assign arbi = a_re * b_im;
assign aibr = a_im * b_re;
assign aibi = a_im * b_im;
assign sc_arbr = arbr >>> (WIDTH-1);
assign sc_arbi = arbi >>> (WIDTH-1);
assign sc_aibr = aibr >>> (WIDTH-1);
assign sc_aibi = aibi >>> (WIDTH-1);
assign m_re = sc_arbr - sc_aibi;
assign m_im = sc_arbi + sc_aibr;
endmodule | module Multiply #(
parameter WIDTH = 16
)(
input signed [WIDTH-1:0] a_re,
input signed [WIDTH-1:0] a_im,
input signed [WIDTH-1:0] b_re,
input signed [WIDTH-1:0] b_im,
output signed [WIDTH-1:0] m_re,
output signed [WIDTH-1:0] m_im
); |
wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi;
wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi;
assign arbr = a_re * b_re;
assign arbi = a_re * b_im;
assign aibr = a_im * b_re;
assign aibi = a_im * b_im;
assign sc_arbr = arbr >>> (WIDTH-1);
assign sc_arbi = arbi >>> (WIDTH-1);
assign sc_aibr = aibr >>> (WIDTH-1);
assign sc_aibi = aibi >>> (WIDTH-1);
assign m_re = sc_arbr - sc_aibi;
assign m_im = sc_arbi + sc_aibr;
endmodule | 11 |
140,929 | data/full_repos/permissive/92788834/verilog/SdfUnit.v | 92,788,834 | SdfUnit.v | v | 278 | 74 | [] | [] | [] | null | line:21: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:118: Cannot find file containing module: \'Butterfly\'\nButterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly.v\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly.sv\n Butterfly\n Butterfly.v\n Butterfly.sv\n obj_dir/Butterfly\n obj_dir/Butterfly.v\n obj_dir/Butterfly.sv\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:129: Cannot find file containing module: \'DelayBuffer\'\nDelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:175: Cannot find file containing module: \'Butterfly\'\nButterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:186: Cannot find file containing module: \'DelayBuffer\'\nDelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/SdfUnit.v:232: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 6 bits.\n : ... In instance SdfUnit\nassign tw_num = bf2_count << (LOG_N-LOG_M);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:235: Cannot find file containing module: \'Twiddle\'\nTwiddle TW (\n^~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:250: Cannot find file containing module: \'Multiply\'\nMultiply #(.WIDTH(WIDTH)) MU (\n^~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 309,945 | module | module SdfUnit #(
parameter N = 64,
parameter M = 64,
parameter WIDTH = 16
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output do_en,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
);
function integer log2;
input integer x;
integer value;
begin
value = x-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
localparam LOG_N = log2(N);
localparam LOG_M = log2(M);
reg [LOG_N-1:0] di_count;
wire bf1_bf;
wire[WIDTH-1:0] bf1_x0_re;
wire[WIDTH-1:0] bf1_x0_im;
wire[WIDTH-1:0] bf1_x1_re;
wire[WIDTH-1:0] bf1_x1_im;
wire[WIDTH-1:0] bf1_y0_re;
wire[WIDTH-1:0] bf1_y0_im;
wire[WIDTH-1:0] bf1_y1_re;
wire[WIDTH-1:0] bf1_y1_im;
wire[WIDTH-1:0] db1_di_re;
wire[WIDTH-1:0] db1_di_im;
wire[WIDTH-1:0] db1_do_re;
wire[WIDTH-1:0] db1_do_im;
wire[WIDTH-1:0] bf1_sp_re;
wire[WIDTH-1:0] bf1_sp_im;
reg bf1_sp_en;
reg [LOG_N-1:0] bf1_count;
wire bf1_start;
wire bf1_end;
wire bf1_mj;
reg [WIDTH-1:0] bf1_do_re;
reg [WIDTH-1:0] bf1_do_im;
reg bf2_bf;
wire[WIDTH-1:0] bf2_x0_re;
wire[WIDTH-1:0] bf2_x0_im;
wire[WIDTH-1:0] bf2_x1_re;
wire[WIDTH-1:0] bf2_x1_im;
wire[WIDTH-1:0] bf2_y0_re;
wire[WIDTH-1:0] bf2_y0_im;
wire[WIDTH-1:0] bf2_y1_re;
wire[WIDTH-1:0] bf2_y1_im;
wire[WIDTH-1:0] db2_di_re;
wire[WIDTH-1:0] db2_di_im;
wire[WIDTH-1:0] db2_do_re;
wire[WIDTH-1:0] db2_do_im;
wire[WIDTH-1:0] bf2_sp_re;
wire[WIDTH-1:0] bf2_sp_im;
reg bf2_sp_en;
reg [LOG_N-1:0] bf2_count;
reg bf2_start;
wire bf2_end;
reg [WIDTH-1:0] bf2_do_re;
reg [WIDTH-1:0] bf2_do_im;
reg bf2_do_en;
wire[1:0] tw_sel;
wire[LOG_N-3:0] tw_num;
wire[LOG_N-1:0] tw_addr;
wire[WIDTH-1:0] tw_re;
wire[WIDTH-1:0] tw_im;
reg mu_en;
wire[WIDTH-1:0] mu_a_re;
wire[WIDTH-1:0] mu_a_im;
wire[WIDTH-1:0] mu_m_re;
wire[WIDTH-1:0] mu_m_im;
reg [WIDTH-1:0] mu_do_re;
reg [WIDTH-1:0] mu_do_im;
reg mu_do_en;
always @(posedge clock or posedge reset) begin
if (reset) begin
di_count <= {LOG_N{1'b0}};
end else begin
di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_bf = di_count[LOG_M-1];
assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
.x0_re (bf1_x0_re ),
.x0_im (bf1_x0_im ),
.x1_re (bf1_x1_re ),
.x1_im (bf1_x1_im ),
.y0_re (bf1_y0_re ),
.y0_im (bf1_y0_im ),
.y1_re (bf1_y1_re ),
.y1_im (bf1_y1_im )
);
DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
.clock (clock ),
.di_re (db1_di_re ),
.di_im (db1_di_im ),
.do_re (db1_do_re ),
.do_im (db1_do_im )
);
assign db1_di_re = bf1_bf ? bf1_y1_re : di_re;
assign db1_di_im = bf1_bf ? bf1_y1_im : di_im;
assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re;
assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf1_sp_en <= 1'b0;
bf1_count <= {LOG_N{1'b0}};
end else begin
bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_start = (di_count == (2**(LOG_M-1)-1));
assign bf1_end = (bf1_count == (2**LOG_N-1));
assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
always @(posedge clock) begin
bf1_do_re <= bf1_sp_re;
bf1_do_im <= bf1_sp_im;
end
always @(posedge clock) begin
bf2_bf <= bf1_count[LOG_M-2];
end
assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
.x0_re (bf2_x0_re ),
.x0_im (bf2_x0_im ),
.x1_re (bf2_x1_re ),
.x1_im (bf2_x1_im ),
.y0_re (bf2_y0_re ),
.y0_im (bf2_y0_im ),
.y1_re (bf2_y1_re ),
.y1_im (bf2_y1_im )
);
DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
.clock (clock ),
.di_re (db2_di_re ),
.di_im (db2_di_im ),
.do_re (db2_do_re ),
.do_im (db2_do_im )
);
assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_sp_en <= 1'b0;
bf2_count <= {LOG_N{1'b0}};
end else begin
bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
end
end
always @(posedge clock) begin
bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
end
assign bf2_end = (bf2_count == (2**LOG_N-1));
always @(posedge clock) begin
bf2_do_re <= bf2_sp_re;
bf2_do_im <= bf2_sp_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_do_en <= 1'b0;
end else begin
bf2_do_en <= bf2_sp_en;
end
end
assign tw_sel[1] = bf2_count[LOG_M-2];
assign tw_sel[0] = bf2_count[LOG_M-1];
assign tw_num = bf2_count << (LOG_N-LOG_M);
assign tw_addr = tw_num * tw_sel;
Twiddle TW (
.clock (clock ),
.addr (tw_addr),
.tw_re (tw_re ),
.tw_im (tw_im )
);
always @(posedge clock) begin
mu_en <= (tw_addr != {LOG_N{1'b0}});
end
assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
Multiply #(.WIDTH(WIDTH)) MU (
.a_re (mu_a_re),
.a_im (mu_a_im),
.b_re (tw_re ),
.b_im (tw_im ),
.m_re (mu_m_re),
.m_im (mu_m_im)
);
always @(posedge clock) begin
mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
mu_do_en <= 1'b0;
end else begin
mu_do_en <= bf2_do_en;
end
end
assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
endmodule | module SdfUnit #(
parameter N = 64,
parameter M = 64,
parameter WIDTH = 16
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output do_en,
output [WIDTH-1:0] do_re,
output [WIDTH-1:0] do_im
); |
function integer log2;
input integer x;
integer value;
begin
value = x-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
localparam LOG_N = log2(N);
localparam LOG_M = log2(M);
reg [LOG_N-1:0] di_count;
wire bf1_bf;
wire[WIDTH-1:0] bf1_x0_re;
wire[WIDTH-1:0] bf1_x0_im;
wire[WIDTH-1:0] bf1_x1_re;
wire[WIDTH-1:0] bf1_x1_im;
wire[WIDTH-1:0] bf1_y0_re;
wire[WIDTH-1:0] bf1_y0_im;
wire[WIDTH-1:0] bf1_y1_re;
wire[WIDTH-1:0] bf1_y1_im;
wire[WIDTH-1:0] db1_di_re;
wire[WIDTH-1:0] db1_di_im;
wire[WIDTH-1:0] db1_do_re;
wire[WIDTH-1:0] db1_do_im;
wire[WIDTH-1:0] bf1_sp_re;
wire[WIDTH-1:0] bf1_sp_im;
reg bf1_sp_en;
reg [LOG_N-1:0] bf1_count;
wire bf1_start;
wire bf1_end;
wire bf1_mj;
reg [WIDTH-1:0] bf1_do_re;
reg [WIDTH-1:0] bf1_do_im;
reg bf2_bf;
wire[WIDTH-1:0] bf2_x0_re;
wire[WIDTH-1:0] bf2_x0_im;
wire[WIDTH-1:0] bf2_x1_re;
wire[WIDTH-1:0] bf2_x1_im;
wire[WIDTH-1:0] bf2_y0_re;
wire[WIDTH-1:0] bf2_y0_im;
wire[WIDTH-1:0] bf2_y1_re;
wire[WIDTH-1:0] bf2_y1_im;
wire[WIDTH-1:0] db2_di_re;
wire[WIDTH-1:0] db2_di_im;
wire[WIDTH-1:0] db2_do_re;
wire[WIDTH-1:0] db2_do_im;
wire[WIDTH-1:0] bf2_sp_re;
wire[WIDTH-1:0] bf2_sp_im;
reg bf2_sp_en;
reg [LOG_N-1:0] bf2_count;
reg bf2_start;
wire bf2_end;
reg [WIDTH-1:0] bf2_do_re;
reg [WIDTH-1:0] bf2_do_im;
reg bf2_do_en;
wire[1:0] tw_sel;
wire[LOG_N-3:0] tw_num;
wire[LOG_N-1:0] tw_addr;
wire[WIDTH-1:0] tw_re;
wire[WIDTH-1:0] tw_im;
reg mu_en;
wire[WIDTH-1:0] mu_a_re;
wire[WIDTH-1:0] mu_a_im;
wire[WIDTH-1:0] mu_m_re;
wire[WIDTH-1:0] mu_m_im;
reg [WIDTH-1:0] mu_do_re;
reg [WIDTH-1:0] mu_do_im;
reg mu_do_en;
always @(posedge clock or posedge reset) begin
if (reset) begin
di_count <= {LOG_N{1'b0}};
end else begin
di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_bf = di_count[LOG_M-1];
assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
.x0_re (bf1_x0_re ),
.x0_im (bf1_x0_im ),
.x1_re (bf1_x1_re ),
.x1_im (bf1_x1_im ),
.y0_re (bf1_y0_re ),
.y0_im (bf1_y0_im ),
.y1_re (bf1_y1_re ),
.y1_im (bf1_y1_im )
);
DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
.clock (clock ),
.di_re (db1_di_re ),
.di_im (db1_di_im ),
.do_re (db1_do_re ),
.do_im (db1_do_im )
);
assign db1_di_re = bf1_bf ? bf1_y1_re : di_re;
assign db1_di_im = bf1_bf ? bf1_y1_im : di_im;
assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re;
assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf1_sp_en <= 1'b0;
bf1_count <= {LOG_N{1'b0}};
end else begin
bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_start = (di_count == (2**(LOG_M-1)-1));
assign bf1_end = (bf1_count == (2**LOG_N-1));
assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
always @(posedge clock) begin
bf1_do_re <= bf1_sp_re;
bf1_do_im <= bf1_sp_im;
end
always @(posedge clock) begin
bf2_bf <= bf1_count[LOG_M-2];
end
assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
.x0_re (bf2_x0_re ),
.x0_im (bf2_x0_im ),
.x1_re (bf2_x1_re ),
.x1_im (bf2_x1_im ),
.y0_re (bf2_y0_re ),
.y0_im (bf2_y0_im ),
.y1_re (bf2_y1_re ),
.y1_im (bf2_y1_im )
);
DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
.clock (clock ),
.di_re (db2_di_re ),
.di_im (db2_di_im ),
.do_re (db2_do_re ),
.do_im (db2_do_im )
);
assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_sp_en <= 1'b0;
bf2_count <= {LOG_N{1'b0}};
end else begin
bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
end
end
always @(posedge clock) begin
bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
end
assign bf2_end = (bf2_count == (2**LOG_N-1));
always @(posedge clock) begin
bf2_do_re <= bf2_sp_re;
bf2_do_im <= bf2_sp_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_do_en <= 1'b0;
end else begin
bf2_do_en <= bf2_sp_en;
end
end
assign tw_sel[1] = bf2_count[LOG_M-2];
assign tw_sel[0] = bf2_count[LOG_M-1];
assign tw_num = bf2_count << (LOG_N-LOG_M);
assign tw_addr = tw_num * tw_sel;
Twiddle TW (
.clock (clock ),
.addr (tw_addr),
.tw_re (tw_re ),
.tw_im (tw_im )
);
always @(posedge clock) begin
mu_en <= (tw_addr != {LOG_N{1'b0}});
end
assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
Multiply #(.WIDTH(WIDTH)) MU (
.a_re (mu_a_re),
.a_im (mu_a_im),
.b_re (tw_re ),
.b_im (tw_im ),
.m_re (mu_m_re),
.m_im (mu_m_im)
);
always @(posedge clock) begin
mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
mu_do_en <= 1'b0;
end else begin
mu_do_en <= bf2_do_en;
end
end
assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
endmodule | 11 |
140,930 | data/full_repos/permissive/92788834/verilog/SdfUnit.v | 92,788,834 | SdfUnit.v | v | 278 | 74 | [] | [] | [] | null | line:21: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:118: Cannot find file containing module: \'Butterfly\'\nButterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly.v\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly.sv\n Butterfly\n Butterfly.v\n Butterfly.sv\n obj_dir/Butterfly\n obj_dir/Butterfly.v\n obj_dir/Butterfly.sv\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:129: Cannot find file containing module: \'DelayBuffer\'\nDelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:175: Cannot find file containing module: \'Butterfly\'\nButterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:186: Cannot find file containing module: \'DelayBuffer\'\nDelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/SdfUnit.v:232: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 6 bits.\n : ... In instance SdfUnit\nassign tw_num = bf2_count << (LOG_N-LOG_M);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:235: Cannot find file containing module: \'Twiddle\'\nTwiddle TW (\n^~~~~~~\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit.v:250: Cannot find file containing module: \'Multiply\'\nMultiply #(.WIDTH(WIDTH)) MU (\n^~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 309,945 | function | function integer log2;
input integer x;
integer value;
begin
value = x-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function integer log2; |
input integer x;
integer value;
begin
value = x-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 11 |
140,931 | data/full_repos/permissive/92788834/verilog/SdfUnit2.v | 92,788,834 | SdfUnit2.v | v | 95 | 73 | [] | [] | [] | [(4, 94)] | null | null | 1: b"%Error: data/full_repos/permissive/92788834/verilog/SdfUnit2.v:55: Cannot find file containing module: 'Butterfly'\nButterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly.v\n data/full_repos/permissive/92788834/verilog,data/full_repos/permissive/92788834/Butterfly.sv\n Butterfly\n Butterfly.v\n Butterfly.sv\n obj_dir/Butterfly\n obj_dir/Butterfly.v\n obj_dir/Butterfly.sv\n%Error: data/full_repos/permissive/92788834/verilog/SdfUnit2.v:66: Cannot find file containing module: 'DelayBuffer'\nDelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,946 | module | module SdfUnit2 #(
parameter WIDTH = 16,
parameter BF_RH = 0
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output reg do_en,
output reg [WIDTH-1:0] do_re,
output reg [WIDTH-1:0] do_im
);
reg bf_en;
wire[WIDTH-1:0] x0_re;
wire[WIDTH-1:0] x0_im;
wire[WIDTH-1:0] x1_re;
wire[WIDTH-1:0] x1_im;
wire[WIDTH-1:0] y0_re;
wire[WIDTH-1:0] y0_im;
wire[WIDTH-1:0] y1_re;
wire[WIDTH-1:0] y1_im;
wire[WIDTH-1:0] db_di_re;
wire[WIDTH-1:0] db_di_im;
wire[WIDTH-1:0] db_do_re;
wire[WIDTH-1:0] db_do_im;
wire[WIDTH-1:0] bf_sp_re;
wire[WIDTH-1:0] bf_sp_im;
reg bf_sp_en;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf_en <= 1'b0;
end else begin
bf_en <= di_en ? ~bf_en : 1'b0;
end
end
assign x0_re = bf_en ? db_do_re : {WIDTH{1'bx}};
assign x0_im = bf_en ? db_do_im : {WIDTH{1'bx}};
assign x1_re = bf_en ? di_re : {WIDTH{1'bx}};
assign x1_im = bf_en ? di_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (
.x0_re (x0_re ),
.x0_im (x0_im ),
.x1_re (x1_re ),
.x1_im (x1_im ),
.y0_re (y0_re ),
.y0_im (y0_im ),
.y1_re (y1_re ),
.y1_im (y1_im )
);
DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (
.clock (clock ),
.di_re (db_di_re ),
.di_im (db_di_im ),
.do_re (db_do_re ),
.do_im (db_do_im )
);
assign db_di_re = bf_en ? y1_re : di_re;
assign db_di_im = bf_en ? y1_im : di_im;
assign bf_sp_re = bf_en ? y0_re : db_do_re;
assign bf_sp_im = bf_en ? y0_im : db_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf_sp_en <= 1'b0;
do_en <= 1'b0;
end else begin
bf_sp_en <= di_en;
do_en <= bf_sp_en;
end
end
always @(posedge clock) begin
do_re <= bf_sp_re;
do_im <= bf_sp_im;
end
endmodule | module SdfUnit2 #(
parameter WIDTH = 16,
parameter BF_RH = 0
)(
input clock,
input reset,
input di_en,
input [WIDTH-1:0] di_re,
input [WIDTH-1:0] di_im,
output reg do_en,
output reg [WIDTH-1:0] do_re,
output reg [WIDTH-1:0] do_im
); |
reg bf_en;
wire[WIDTH-1:0] x0_re;
wire[WIDTH-1:0] x0_im;
wire[WIDTH-1:0] x1_re;
wire[WIDTH-1:0] x1_im;
wire[WIDTH-1:0] y0_re;
wire[WIDTH-1:0] y0_im;
wire[WIDTH-1:0] y1_re;
wire[WIDTH-1:0] y1_im;
wire[WIDTH-1:0] db_di_re;
wire[WIDTH-1:0] db_di_im;
wire[WIDTH-1:0] db_do_re;
wire[WIDTH-1:0] db_do_im;
wire[WIDTH-1:0] bf_sp_re;
wire[WIDTH-1:0] bf_sp_im;
reg bf_sp_en;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf_en <= 1'b0;
end else begin
bf_en <= di_en ? ~bf_en : 1'b0;
end
end
assign x0_re = bf_en ? db_do_re : {WIDTH{1'bx}};
assign x0_im = bf_en ? db_do_im : {WIDTH{1'bx}};
assign x1_re = bf_en ? di_re : {WIDTH{1'bx}};
assign x1_im = bf_en ? di_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (
.x0_re (x0_re ),
.x0_im (x0_im ),
.x1_re (x1_re ),
.x1_im (x1_im ),
.y0_re (y0_re ),
.y0_im (y0_im ),
.y1_re (y1_re ),
.y1_im (y1_im )
);
DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (
.clock (clock ),
.di_re (db_di_re ),
.di_im (db_di_im ),
.do_re (db_do_re ),
.do_im (db_do_im )
);
assign db_di_re = bf_en ? y1_re : di_re;
assign db_di_im = bf_en ? y1_im : di_im;
assign bf_sp_re = bf_en ? y0_re : db_do_re;
assign bf_sp_im = bf_en ? y0_im : db_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf_sp_en <= 1'b0;
do_en <= 1'b0;
end else begin
bf_sp_en <= di_en;
do_en <= bf_sp_en;
end
end
always @(posedge clock) begin
do_re <= bf_sp_re;
do_im <= bf_sp_im;
end
endmodule | 11 |
140,935 | data/full_repos/permissive/92788834/verilog/TwiddleConvert4.v | 92,788,834 | TwiddleConvert4.v | v | 62 | 77 | [] | [] | [] | [(4, 61)] | null | data/verilator_xmls/e8d042eb-485c-438e-bd4f-34bf38184223.xml | null | 309,951 | module | module TwiddleConvert4 #(
parameter LOG_N = 6,
parameter WIDTH = 16,
parameter TW_FF = 1,
parameter TC_FF = 1
)(
input clock,
input [LOG_N-1:0] tw_addr,
input [WIDTH-1:0] tw_re,
input [WIDTH-1:0] tw_im,
output [LOG_N-1:0] tc_addr,
output [WIDTH-1:0] tc_re,
output [WIDTH-1:0] tc_im
);
reg [LOG_N-1:0] ff_addr;
wire[LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
assign tc_addr[LOG_N-1:LOG_N-2] = 2'd0;
assign tc_addr[LOG_N-3:0] = tw_addr[LOG_N-3:0];
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-3:0] == {LOG_N-2{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
2'd1 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {1'b1,{WIDTH-1{1'b0}}}};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0 : {mx_re, mx_im} <= { tw_re, tw_im};
2'd1 : {mx_re, mx_im} <= { tw_im, -tw_re};
2'd2 : {mx_re, mx_im} <= {-tw_re, -tw_im};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule | module TwiddleConvert4 #(
parameter LOG_N = 6,
parameter WIDTH = 16,
parameter TW_FF = 1,
parameter TC_FF = 1
)(
input clock,
input [LOG_N-1:0] tw_addr,
input [WIDTH-1:0] tw_re,
input [WIDTH-1:0] tw_im,
output [LOG_N-1:0] tc_addr,
output [WIDTH-1:0] tc_re,
output [WIDTH-1:0] tc_im
); |
reg [LOG_N-1:0] ff_addr;
wire[LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
assign tc_addr[LOG_N-1:LOG_N-2] = 2'd0;
assign tc_addr[LOG_N-3:0] = tw_addr[LOG_N-3:0];
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-3:0] == {LOG_N-2{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
2'd1 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {1'b1,{WIDTH-1{1'b0}}}};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0 : {mx_re, mx_im} <= { tw_re, tw_im};
2'd1 : {mx_re, mx_im} <= { tw_im, -tw_re};
2'd2 : {mx_re, mx_im} <= {-tw_re, -tw_im};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule | 11 |
140,936 | data/full_repos/permissive/92788834/verilog/TwiddleConvert8.v | 92,788,834 | TwiddleConvert8.v | v | 71 | 90 | [] | [] | [] | [(4, 70)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/TwiddleConvert8.v:20: Operator VAR \'COSMQ\' expects 16 bits on the Initial value, but Initial value\'s SHIFTR generates 32 bits.\n : ... In instance TwiddleConvert8\nlocalparam[WIDTH-1:0] COSMQ = (((32\'h5A82799A<<1) >> (32-WIDTH)) + 1)>>1; \n ^~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/92788834/verilog/TwiddleConvert8.v:21: Operator VAR \'SINMH\' expects 16 bits on the Initial value, but Initial value\'s SHIFTR generates 32 bits.\n : ... In instance TwiddleConvert8\nlocalparam[WIDTH-1:0] SINMH = 32\'h80000000 >> (32-WIDTH); \n ^~~~~\n%Error: Exiting due to 2 warning(s)\n' | 309,952 | module | module TwiddleConvert8 #(
parameter LOG_N = 6,
parameter WIDTH = 16,
parameter TW_FF = 1,
parameter TC_FF = 1
)(
input clock,
input [LOG_N-1:0] tw_addr,
input [WIDTH-1:0] tw_re,
input [WIDTH-1:0] tw_im,
output [LOG_N-1:0] tc_addr,
output [WIDTH-1:0] tc_re,
output [WIDTH-1:0] tc_im
);
localparam[WIDTH-1:0] COSMQ = (((32'h5A82799A<<1) >> (32-WIDTH)) + 1)>>1;
localparam[WIDTH-1:0] SINMH = 32'h80000000 >> (32-WIDTH);
reg [LOG_N-1:0] ff_addr;
wire[LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
assign tc_addr[LOG_N-1:LOG_N-3] = 3'd0;
assign tc_addr[LOG_N-4:0] = tw_addr[LOG_N-3] ? -tw_addr[LOG_N-4:0] : tw_addr[LOG_N-4:0];
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-4:0] == {LOG_N-3{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
3'd1 : {mx_re, mx_im} <= { COSMQ , -COSMQ };
3'd2 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, SINMH };
3'd3 : {mx_re, mx_im} <= {-COSMQ , -COSMQ };
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0 : {mx_re, mx_im} <= { tw_re, tw_im};
3'd1 : {mx_re, mx_im} <= {-tw_im, -tw_re};
3'd2 : {mx_re, mx_im} <= { tw_im, -tw_re};
3'd3 : {mx_re, mx_im} <= {-tw_re, tw_im};
3'd4 : {mx_re, mx_im} <= {-tw_re, -tw_im};
3'd5 : {mx_re, mx_im} <= { tw_im, tw_re};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule | module TwiddleConvert8 #(
parameter LOG_N = 6,
parameter WIDTH = 16,
parameter TW_FF = 1,
parameter TC_FF = 1
)(
input clock,
input [LOG_N-1:0] tw_addr,
input [WIDTH-1:0] tw_re,
input [WIDTH-1:0] tw_im,
output [LOG_N-1:0] tc_addr,
output [WIDTH-1:0] tc_re,
output [WIDTH-1:0] tc_im
); |
localparam[WIDTH-1:0] COSMQ = (((32'h5A82799A<<1) >> (32-WIDTH)) + 1)>>1;
localparam[WIDTH-1:0] SINMH = 32'h80000000 >> (32-WIDTH);
reg [LOG_N-1:0] ff_addr;
wire[LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
assign tc_addr[LOG_N-1:LOG_N-3] = 3'd0;
assign tc_addr[LOG_N-4:0] = tw_addr[LOG_N-3] ? -tw_addr[LOG_N-4:0] : tw_addr[LOG_N-4:0];
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-4:0] == {LOG_N-3{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
3'd1 : {mx_re, mx_im} <= { COSMQ , -COSMQ };
3'd2 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, SINMH };
3'd3 : {mx_re, mx_im} <= {-COSMQ , -COSMQ };
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0 : {mx_re, mx_im} <= { tw_re, tw_im};
3'd1 : {mx_re, mx_im} <= {-tw_im, -tw_re};
3'd2 : {mx_re, mx_im} <= { tw_im, -tw_re};
3'd3 : {mx_re, mx_im} <= {-tw_re, tw_im};
3'd4 : {mx_re, mx_im} <= {-tw_re, -tw_im};
3'd5 : {mx_re, mx_im} <= { tw_im, tw_re};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule | 11 |
140,937 | data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v | 9,286,699 | alink.v | v | 267 | 120 | [] | [] | [] | [(15, 277)] | null | null | 1: b'%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:2: Cannot find include file: alink_define.v\n`include "alink_define.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.sv\n alink_define.v\n alink_define.v.v\n alink_define.v.sv\n obj_dir/alink_define.v\n obj_dir/alink_define.v.v\n obj_dir/alink_define.v.sv\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:25: Define or directive not defined: \'`PHY_NUM\'\n output [`PHY_NUM-1:0] TX_P ,\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:26: Define or directive not defined: \'`PHY_NUM\'\n output [`PHY_NUM-1:0] TX_N ,\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:28: Define or directive not defined: \'`PHY_NUM\'\n input [`PHY_NUM-1:0] RX_P ,\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:29: Define or directive not defined: \'`PHY_NUM\'\n input [`PHY_NUM-1:0] RX_N ,\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:76: Define or directive not defined: \'`PHY_NUM\'\nwire [`PHY_NUM-1:0] tx_phy_sel ;\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:80: Define or directive not defined: \'`PHY_NUM\'\nwire [32*`PHY_NUM-1:0] timer_cnt ; \n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:131: Define or directive not defined: \'`TX_DATA_LEN\'\nassign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ; \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:131: Define or directive not defined: \'`TX_TASKID_LEN\'\nassign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:131: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ; \n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:131: Define or directive not defined: \'`TX_FIFO_DEPTH\'\nassign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:132: Define or directive not defined: \'`TX_DATA_LEN\'\nwire tx_task_vld = tx_data_count >= (`TX_DATA_LEN+`TX_TASKID_LEN) ; \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:132: Define or directive not defined: \'`TX_TASKID_LEN\'\nwire tx_task_vld = tx_data_count >= (`TX_DATA_LEN+`TX_TASKID_LEN) ; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:132: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire tx_task_vld = tx_data_count >= (`TX_DATA_LEN+`TX_TASKID_LEN) ; \n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:148: Define or directive not defined: \'`RX_DATA_LEN\'\nassign rxempty = rx_data_count < `RX_DATA_LEN ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:148: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign rxempty = rx_data_count < `RX_DATA_LEN ;\n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:149: Define or directive not defined: \'`RX_DATA_LEN\'\nwire rx_almost_full = (rx_data_count + `RX_DATA_LEN*2) > `RX_FIFO_DEPTH ; \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:149: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire rx_almost_full = (rx_data_count + `RX_DATA_LEN*2) > `RX_FIFO_DEPTH ; \n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink.v:149: Define or directive not defined: \'`RX_FIFO_DEPTH\'\nwire rx_almost_full = (rx_data_count + `RX_DATA_LEN*2) > `RX_FIFO_DEPTH ; \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n' | 309,955 | module | module alink(
input CLK_I ,
input RST_I ,
input ALINK_CYC_I ,
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,
input [2:0] ALINK_CTI_I ,
input [1:0] ALINK_BTE_I ,
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,
output ALINK_ACK_O ,
output ALINK_ERR_O ,
output ALINK_RTY_O ,
output [31:0] ALINK_DAT_O ,
output [`PHY_NUM-1:0] TX_P ,
output [`PHY_NUM-1:0] TX_N ,
input [`PHY_NUM-1:0] RX_P ,
input [`PHY_NUM-1:0] RX_N ,
output [4:0] ALINK_led
);
assign ALINK_ERR_O = 1'b0 ;
assign ALINK_RTY_O = 1'b0 ;
wire [31:0] reg_tout ;
wire txfifo_push ;
wire [31:0] txfifo_din ;
wire [3:0] rxcnt ;
wire rxempty ;
wire [3:0] txcnt ;
wire reg_flush ;
wire txfull ;
wire [31:0] reg_mask ;
wire reg_scan ;
wire [31:0] busy ;
assign ALINK_led[0] = ~reg_mask[0] ;
assign ALINK_led[1] = ~reg_mask[1] ;
assign ALINK_led[2] = ~reg_mask[2] ;
assign ALINK_led[3] = ~reg_mask[3] ;
assign ALINK_led[4] = ~reg_mask[4] ;
wire rxfifo_pop ;
wire [31:0] rxfifo_dout ;
wire [31 : 0] tx_din ;
wire tx_wr_en ;
wire tx_rd_en ;
wire [31 : 0] tx_dout ;
wire [10 : 0] tx_data_count ;
wire [31 : 0] rx_din ;
wire rx_wr_en ;
wire [9 : 0] rx_data_count ;
wire tx_phy_start ;
wire [`PHY_NUM-1:0] tx_phy_sel ;
wire tx_phy_done ;
wire [1:0] cur_state ;
wire [1:0] nxt_state ;
wire [32*`PHY_NUM-1:0] timer_cnt ;
wire task_id_vld ;
wire [31:0] rx_phy_sel ;
wire [31:0] task_id_h ;
wire [31:0] task_id_l ;
alink_slave alink_slave(
.clk (CLK_I ) ,
.rst (RST_I ) ,
.ALINK_CYC_I (ALINK_CYC_I ) ,
.ALINK_STB_I (ALINK_STB_I ) ,
.ALINK_WE_I (ALINK_WE_I ) ,
.ALINK_LOCK_I(ALINK_LOCK_I ) ,
.ALINK_CTI_I (ALINK_CTI_I ) ,
.ALINK_BTE_I (ALINK_BTE_I ) ,
.ALINK_ADR_I (ALINK_ADR_I ) ,
.ALINK_DAT_I (ALINK_DAT_I ) ,
.ALINK_SEL_I (ALINK_SEL_I ) ,
.ALINK_ACK_O (ALINK_ACK_O ) ,
.ALINK_ERR_O (ALINK_ERR_O ) ,
.ALINK_RTY_O (ALINK_RTY_O ) ,
.ALINK_DAT_O (ALINK_DAT_O ) ,
.txfifo_push (tx_wr_en ) ,
.txfifo_din (tx_din ) ,
.rxcnt (rx_data_count ) ,
.rxempty (rxempty ) ,
.txcnt (tx_data_count ) ,
.reg_flush (reg_flush ) ,
.txfull (txfull ) ,
.reg_mask (reg_mask ) ,
.reg_scan (reg_scan ) ,
.busy (busy ) ,
.rxfifo_pop (rxfifo_pop ) ,
.rxfifo_dout (rxfifo_dout )
);
assign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ;
wire tx_task_vld = tx_data_count >= (`TX_DATA_LEN+`TX_TASKID_LEN) ;
tx_fifo tx_fifo(
.clk (CLK_I ),
.srst (RST_I|reg_flush ),
.din (tx_din ),
.wr_en (tx_wr_en ),
.rd_en (tx_rd_en ),
.dout (tx_dout ),
.full ( ),
.empty ( ),
.data_count(tx_data_count )
) ;
assign rxempty = rx_data_count < `RX_DATA_LEN ;
wire rx_almost_full = (rx_data_count + `RX_DATA_LEN*2) > `RX_FIFO_DEPTH ;
`ifdef SIM
always @ ( posedge rx_almost_full ) begin
#200 ;
$display("[WAR] rx fifo full:%d",rx_data_count);
end
`endif
rx_fifo rx_fifo(
.clk (CLK_I ),
.srst (RST_I|reg_flush ),
.din (rx_din ),
.wr_en (rx_wr_en ),
.rd_en (rxfifo_pop ),
.dout (rxfifo_dout ),
.full (rx_full ),
.empty ( ),
.data_count(rx_data_count )
);
txc txc(
.clk (CLK_I ) ,
.rst (RST_I|reg_flush ) ,
.reg_flush (reg_flush ) ,
.reg_mask (reg_mask ) ,
.task_id_vld (task_id_vld ) ,
.reg_tout (reg_tout ) ,
.tx_task_vld (tx_task_vld ) ,
.tx_phy_start(tx_phy_start ) ,
.tx_phy_sel (tx_phy_sel ) ,
.tx_phy_done (tx_phy_done ) ,
.cur_state (cur_state ) ,
.nxt_state (nxt_state ) ,
.timer_cnt (timer_cnt ) ,
.reg_busy (busy )
);
tx_phy tx_phy(
.clk (CLK_I ) ,
.rst (RST_I|reg_flush ) ,
.reg_flush (reg_flush ) ,
.reg_scan (reg_scan ) ,
.tx_phy_start(tx_phy_start ) ,
.tx_phy_sel (tx_phy_sel ) ,
.tx_phy_done (tx_phy_done ) ,
.tx_dout (tx_dout ) ,
.tx_rd_en (tx_rd_en ) ,
.task_id_vld (task_id_vld ) ,
.rx_phy_sel (rx_phy_sel ) ,
.task_id_h (task_id_h ) ,
.task_id_l (task_id_l ) ,
.reg_tout (reg_tout ) ,
.TX_P (TX_P ) ,
.TX_N (TX_N )
);
rxc rxc(
.clk (CLK_I ) ,
.rst (RST_I|reg_flush ) ,
.reg_flush (reg_flush ) ,
.reg_mask (reg_mask ) ,
.reg_busy (busy ) ,
.rx_almost_full (rx_almost_full ) ,
.tx_phy_start (tx_phy_start ) ,
.tx_phy_sel (tx_phy_sel ) ,
.task_id_vld (task_id_vld ) ,
.rx_phy_sel (rx_phy_sel ) ,
.task_id_h (task_id_h ) ,
.task_id_l (task_id_l ) ,
.timer_cnt (timer_cnt ) ,
.rx_vld (rx_wr_en ) ,
.rx_dat (rx_din ) ,
.RX_P (RX_P ) ,
.RX_N (RX_N )
);
endmodule | module alink(
input CLK_I ,
input RST_I ,
input ALINK_CYC_I ,
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,
input [2:0] ALINK_CTI_I ,
input [1:0] ALINK_BTE_I ,
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,
output ALINK_ACK_O ,
output ALINK_ERR_O ,
output ALINK_RTY_O ,
output [31:0] ALINK_DAT_O ,
output [`PHY_NUM-1:0] TX_P ,
output [`PHY_NUM-1:0] TX_N ,
input [`PHY_NUM-1:0] RX_P ,
input [`PHY_NUM-1:0] RX_N ,
output [4:0] ALINK_led
); |
assign ALINK_ERR_O = 1'b0 ;
assign ALINK_RTY_O = 1'b0 ;
wire [31:0] reg_tout ;
wire txfifo_push ;
wire [31:0] txfifo_din ;
wire [3:0] rxcnt ;
wire rxempty ;
wire [3:0] txcnt ;
wire reg_flush ;
wire txfull ;
wire [31:0] reg_mask ;
wire reg_scan ;
wire [31:0] busy ;
assign ALINK_led[0] = ~reg_mask[0] ;
assign ALINK_led[1] = ~reg_mask[1] ;
assign ALINK_led[2] = ~reg_mask[2] ;
assign ALINK_led[3] = ~reg_mask[3] ;
assign ALINK_led[4] = ~reg_mask[4] ;
wire rxfifo_pop ;
wire [31:0] rxfifo_dout ;
wire [31 : 0] tx_din ;
wire tx_wr_en ;
wire tx_rd_en ;
wire [31 : 0] tx_dout ;
wire [10 : 0] tx_data_count ;
wire [31 : 0] rx_din ;
wire rx_wr_en ;
wire [9 : 0] rx_data_count ;
wire tx_phy_start ;
wire [`PHY_NUM-1:0] tx_phy_sel ;
wire tx_phy_done ;
wire [1:0] cur_state ;
wire [1:0] nxt_state ;
wire [32*`PHY_NUM-1:0] timer_cnt ;
wire task_id_vld ;
wire [31:0] rx_phy_sel ;
wire [31:0] task_id_h ;
wire [31:0] task_id_l ;
alink_slave alink_slave(
.clk (CLK_I ) ,
.rst (RST_I ) ,
.ALINK_CYC_I (ALINK_CYC_I ) ,
.ALINK_STB_I (ALINK_STB_I ) ,
.ALINK_WE_I (ALINK_WE_I ) ,
.ALINK_LOCK_I(ALINK_LOCK_I ) ,
.ALINK_CTI_I (ALINK_CTI_I ) ,
.ALINK_BTE_I (ALINK_BTE_I ) ,
.ALINK_ADR_I (ALINK_ADR_I ) ,
.ALINK_DAT_I (ALINK_DAT_I ) ,
.ALINK_SEL_I (ALINK_SEL_I ) ,
.ALINK_ACK_O (ALINK_ACK_O ) ,
.ALINK_ERR_O (ALINK_ERR_O ) ,
.ALINK_RTY_O (ALINK_RTY_O ) ,
.ALINK_DAT_O (ALINK_DAT_O ) ,
.txfifo_push (tx_wr_en ) ,
.txfifo_din (tx_din ) ,
.rxcnt (rx_data_count ) ,
.rxempty (rxempty ) ,
.txcnt (tx_data_count ) ,
.reg_flush (reg_flush ) ,
.txfull (txfull ) ,
.reg_mask (reg_mask ) ,
.reg_scan (reg_scan ) ,
.busy (busy ) ,
.rxfifo_pop (rxfifo_pop ) ,
.rxfifo_dout (rxfifo_dout )
);
assign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ;
wire tx_task_vld = tx_data_count >= (`TX_DATA_LEN+`TX_TASKID_LEN) ;
tx_fifo tx_fifo(
.clk (CLK_I ),
.srst (RST_I|reg_flush ),
.din (tx_din ),
.wr_en (tx_wr_en ),
.rd_en (tx_rd_en ),
.dout (tx_dout ),
.full ( ),
.empty ( ),
.data_count(tx_data_count )
) ;
assign rxempty = rx_data_count < `RX_DATA_LEN ;
wire rx_almost_full = (rx_data_count + `RX_DATA_LEN*2) > `RX_FIFO_DEPTH ;
`ifdef SIM
always @ ( posedge rx_almost_full ) begin
#200 ;
$display("[WAR] rx fifo full:%d",rx_data_count);
end
`endif
rx_fifo rx_fifo(
.clk (CLK_I ),
.srst (RST_I|reg_flush ),
.din (rx_din ),
.wr_en (rx_wr_en ),
.rd_en (rxfifo_pop ),
.dout (rxfifo_dout ),
.full (rx_full ),
.empty ( ),
.data_count(rx_data_count )
);
txc txc(
.clk (CLK_I ) ,
.rst (RST_I|reg_flush ) ,
.reg_flush (reg_flush ) ,
.reg_mask (reg_mask ) ,
.task_id_vld (task_id_vld ) ,
.reg_tout (reg_tout ) ,
.tx_task_vld (tx_task_vld ) ,
.tx_phy_start(tx_phy_start ) ,
.tx_phy_sel (tx_phy_sel ) ,
.tx_phy_done (tx_phy_done ) ,
.cur_state (cur_state ) ,
.nxt_state (nxt_state ) ,
.timer_cnt (timer_cnt ) ,
.reg_busy (busy )
);
tx_phy tx_phy(
.clk (CLK_I ) ,
.rst (RST_I|reg_flush ) ,
.reg_flush (reg_flush ) ,
.reg_scan (reg_scan ) ,
.tx_phy_start(tx_phy_start ) ,
.tx_phy_sel (tx_phy_sel ) ,
.tx_phy_done (tx_phy_done ) ,
.tx_dout (tx_dout ) ,
.tx_rd_en (tx_rd_en ) ,
.task_id_vld (task_id_vld ) ,
.rx_phy_sel (rx_phy_sel ) ,
.task_id_h (task_id_h ) ,
.task_id_l (task_id_l ) ,
.reg_tout (reg_tout ) ,
.TX_P (TX_P ) ,
.TX_N (TX_N )
);
rxc rxc(
.clk (CLK_I ) ,
.rst (RST_I|reg_flush ) ,
.reg_flush (reg_flush ) ,
.reg_mask (reg_mask ) ,
.reg_busy (busy ) ,
.rx_almost_full (rx_almost_full ) ,
.tx_phy_start (tx_phy_start ) ,
.tx_phy_sel (tx_phy_sel ) ,
.task_id_vld (task_id_vld ) ,
.rx_phy_sel (rx_phy_sel ) ,
.task_id_h (task_id_h ) ,
.task_id_l (task_id_l ) ,
.timer_cnt (timer_cnt ) ,
.rx_vld (rx_wr_en ) ,
.rx_dat (rx_din ) ,
.RX_P (RX_P ) ,
.RX_N (RX_N )
);
endmodule | 26 |
140,938 | data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink_slave.v | 9,286,699 | alink_slave.v | v | 144 | 103 | [] | [] | [] | [(13, 153)] | null | null | 1: b'%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/alink_slave.v:1: Cannot find include file: alink_define.v\n`include "alink_define.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.sv\n alink_define.v\n alink_define.v.v\n alink_define.v.sv\n obj_dir/alink_define.v\n obj_dir/alink_define.v.v\n obj_dir/alink_define.v.sv\n%Error: Exiting due to 1 error(s)\n' | 309,957 | module | module alink_slave(
input clk ,
input rst ,
input ALINK_CYC_I ,
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,
input [2:0] ALINK_CTI_I ,
input [1:0] ALINK_BTE_I ,
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,
output reg ALINK_ACK_O ,
output ALINK_ERR_O ,
output ALINK_RTY_O ,
output reg [31:0] ALINK_DAT_O ,
output reg txfifo_push ,
output reg [31:0] txfifo_din ,
input [9:0] rxcnt ,
input rxempty ,
input [10:0] txcnt ,
output reg_flush ,
input txfull ,
output reg [31:0] reg_mask ,
output reg reg_scan ,
input [31:0] busy ,
output rxfifo_pop ,
input [31:0] rxfifo_dout
);
parameter ALINK_TXFIFO = 6'h00 ;
parameter ALINK_STATE = 6'h04 ;
parameter ALINK_MASK = 6'h08 ;
parameter ALINK_BUSY = 6'h0c ;
parameter ALINK_RXFIFO = 6'h10 ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
ALINK_ACK_O <= 1'b0 ;
else if( ALINK_STB_I && (~ALINK_ACK_O) )
ALINK_ACK_O <= 1'b1 ;
else
ALINK_ACK_O <= 1'b0 ;
end
wire alink_txfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_txfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_state_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_state_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_mask_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_mask_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_busy_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_busy_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_rxfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
wire alink_rxfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
always @ ( posedge clk ) begin
txfifo_push <= alink_txfifo_wr_en ;
txfifo_din <= ALINK_DAT_I ;
end
reg [3:0] reg_flush_r ;
wire [31:0] rd_state = {reg_scan,1'b0,rxcnt[9:0],3'b0,rxempty,
1'b0,txcnt[10:0],2'b0,reg_flush,txfull} ;
always @ ( posedge clk ) begin
if( alink_state_wr_en )
reg_flush_r <= {3'b0,ALINK_DAT_I[1]} ;
else
reg_flush_r <= reg_flush_r << 1 ;
end
always @ ( posedge clk ) begin
if( rst )
reg_scan <= 1'b0 ;
else if( alink_state_wr_en )
reg_scan <= ALINK_DAT_I[31] ;
end
assign reg_flush = |reg_flush_r ;
always @ ( posedge clk ) begin
if( alink_mask_wr_en )
reg_mask <= ALINK_DAT_I ;
end
wire [31:0] rd_busy = busy[31:0] ;
wire [31:0] rd_rxfifo = rxfifo_dout[31:0] ;
assign rxfifo_pop = alink_rxfifo_rd_en ;
always @ ( posedge clk ) begin
case( 1'b1 )
alink_state_rd_en : ALINK_DAT_O <= rd_state ;
alink_busy_rd_en : ALINK_DAT_O <= rd_busy ;
alink_rxfifo_rd_en : ALINK_DAT_O <= rd_rxfifo ;
default: ALINK_DAT_O <= 32'hdeaddead ;
endcase
end
endmodule | module alink_slave(
input clk ,
input rst ,
input ALINK_CYC_I ,
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,
input [2:0] ALINK_CTI_I ,
input [1:0] ALINK_BTE_I ,
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,
output reg ALINK_ACK_O ,
output ALINK_ERR_O ,
output ALINK_RTY_O ,
output reg [31:0] ALINK_DAT_O ,
output reg txfifo_push ,
output reg [31:0] txfifo_din ,
input [9:0] rxcnt ,
input rxempty ,
input [10:0] txcnt ,
output reg_flush ,
input txfull ,
output reg [31:0] reg_mask ,
output reg reg_scan ,
input [31:0] busy ,
output rxfifo_pop ,
input [31:0] rxfifo_dout
); |
parameter ALINK_TXFIFO = 6'h00 ;
parameter ALINK_STATE = 6'h04 ;
parameter ALINK_MASK = 6'h08 ;
parameter ALINK_BUSY = 6'h0c ;
parameter ALINK_RXFIFO = 6'h10 ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
ALINK_ACK_O <= 1'b0 ;
else if( ALINK_STB_I && (~ALINK_ACK_O) )
ALINK_ACK_O <= 1'b1 ;
else
ALINK_ACK_O <= 1'b0 ;
end
wire alink_txfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_txfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_state_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_state_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_mask_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_mask_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_busy_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_busy_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_rxfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
wire alink_rxfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
always @ ( posedge clk ) begin
txfifo_push <= alink_txfifo_wr_en ;
txfifo_din <= ALINK_DAT_I ;
end
reg [3:0] reg_flush_r ;
wire [31:0] rd_state = {reg_scan,1'b0,rxcnt[9:0],3'b0,rxempty,
1'b0,txcnt[10:0],2'b0,reg_flush,txfull} ;
always @ ( posedge clk ) begin
if( alink_state_wr_en )
reg_flush_r <= {3'b0,ALINK_DAT_I[1]} ;
else
reg_flush_r <= reg_flush_r << 1 ;
end
always @ ( posedge clk ) begin
if( rst )
reg_scan <= 1'b0 ;
else if( alink_state_wr_en )
reg_scan <= ALINK_DAT_I[31] ;
end
assign reg_flush = |reg_flush_r ;
always @ ( posedge clk ) begin
if( alink_mask_wr_en )
reg_mask <= ALINK_DAT_I ;
end
wire [31:0] rd_busy = busy[31:0] ;
wire [31:0] rd_rxfifo = rxfifo_dout[31:0] ;
assign rxfifo_pop = alink_rxfifo_rd_en ;
always @ ( posedge clk ) begin
case( 1'b1 )
alink_state_rd_en : ALINK_DAT_O <= rd_state ;
alink_busy_rd_en : ALINK_DAT_O <= rd_busy ;
alink_rxfifo_rd_en : ALINK_DAT_O <= rd_rxfifo ;
default: ALINK_DAT_O <= 32'hdeaddead ;
endcase
end
endmodule | 26 |
140,940 | data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/rx_phy.v | 9,286,699 | rx_phy.v | v | 111 | 114 | [] | [] | [] | [(14, 121)] | null | null | 1: b'%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/rx_phy.v:2: Cannot find include file: alink_define.v\n`include "alink_define.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.sv\n alink_define.v\n alink_define.v.v\n alink_define.v.sv\n obj_dir/alink_define.v\n obj_dir/alink_define.v.v\n obj_dir/alink_define.v.sv\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/rx_phy.v:97: Define or directive not defined: \'`RX_DATA_LEN\'\n else if( |push_cnt && push_cnt < `RX_DATA_LEN )\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/rx_phy.v:97: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n else if( |push_cnt && push_cnt < `RX_DATA_LEN )\n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/rx_phy.v:109: Define or directive not defined: \'`RX_DATA_LEN\'\nassign rx_last = push_cnt == `RX_DATA_LEN ;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/rx_phy.v:109: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign rx_last = push_cnt == `RX_DATA_LEN ;\n ^\n%Error: Exiting due to 5 error(s)\n' | 309,959 | module | module rx_phy(
input clk ,
input rst ,
input reg_flush ,
input reg_busy ,
input task_id_vld ,
input [31:0] task_id_h ,
input [31:0] task_id_l ,
input [31:0] timer_cnt ,
output rx_start ,
output rx_last ,
output rx_vld ,
output [31:0] rx_dat ,
input RX_P ,
input RX_N
);
parameter MY_RXID = 32'd0 ;
reg [3:0] report_p_d ;
reg [3:0] report_n_d ;
always@(posedge clk or posedge rst )begin
if( reg_flush || rst || ~reg_busy) begin
report_p_d <= 4'hf ;
report_n_d <= 4'hf ;
end else begin
report_p_d <= #1 {report_p_d[2:0], RX_P};
report_n_d <= #1 {report_n_d[2:0], RX_N};
end
end
wire rx_0 = ((~report_n_d[3]) && (&report_n_d[2:1])) && ~(|report_p_d[3:1]);
wire rx_1 = ((~report_p_d[3]) && (&report_p_d[2:1])) && ~(|report_n_d[3:1]);
wire rx_stop = (report_p_d[3]^report_n_d[3]) && (report_p_d[2]^report_n_d[2]) && (report_p_d[1]&report_n_d[1]) ;
reg [31:0] nonce_buf;
always@(posedge clk)begin
if(rx_0)
nonce_buf <= #1 {1'b0, nonce_buf[31:1]};
else if(rx_1)
nonce_buf <= #1 {1'b1, nonce_buf[31:1]};
end
reg [31:0] task_id_h_r ;
reg [31:0] task_id_l_r ;
always @ ( posedge clk ) begin
if( ~rx_vld && task_id_vld ) begin
task_id_h_r <= task_id_h ;
task_id_l_r <= task_id_l ;
end
end
reg [2:0] push_cnt ;
always @ ( posedge clk ) begin
if( rst )
push_cnt <= 3'b0 ;
else if( reg_busy && rx_stop && ~rx_vld)
push_cnt <= 3'b1 ;
else if( |push_cnt && push_cnt < `RX_DATA_LEN )
push_cnt <= push_cnt + 3'b1 ;
else
push_cnt <= 3'b0 ;
end
assign rx_vld = |push_cnt ;
assign rx_dat = push_cnt == 1 ? MY_RXID :
push_cnt == 2 ? task_id_h_r :
push_cnt == 3 ? task_id_l_r :
push_cnt == 4 ? timer_cnt : nonce_buf ;
assign rx_start = reg_busy && rx_stop && ~rx_vld ;
assign rx_last = push_cnt == `RX_DATA_LEN ;
endmodule | module rx_phy(
input clk ,
input rst ,
input reg_flush ,
input reg_busy ,
input task_id_vld ,
input [31:0] task_id_h ,
input [31:0] task_id_l ,
input [31:0] timer_cnt ,
output rx_start ,
output rx_last ,
output rx_vld ,
output [31:0] rx_dat ,
input RX_P ,
input RX_N
); |
parameter MY_RXID = 32'd0 ;
reg [3:0] report_p_d ;
reg [3:0] report_n_d ;
always@(posedge clk or posedge rst )begin
if( reg_flush || rst || ~reg_busy) begin
report_p_d <= 4'hf ;
report_n_d <= 4'hf ;
end else begin
report_p_d <= #1 {report_p_d[2:0], RX_P};
report_n_d <= #1 {report_n_d[2:0], RX_N};
end
end
wire rx_0 = ((~report_n_d[3]) && (&report_n_d[2:1])) && ~(|report_p_d[3:1]);
wire rx_1 = ((~report_p_d[3]) && (&report_p_d[2:1])) && ~(|report_n_d[3:1]);
wire rx_stop = (report_p_d[3]^report_n_d[3]) && (report_p_d[2]^report_n_d[2]) && (report_p_d[1]&report_n_d[1]) ;
reg [31:0] nonce_buf;
always@(posedge clk)begin
if(rx_0)
nonce_buf <= #1 {1'b0, nonce_buf[31:1]};
else if(rx_1)
nonce_buf <= #1 {1'b1, nonce_buf[31:1]};
end
reg [31:0] task_id_h_r ;
reg [31:0] task_id_l_r ;
always @ ( posedge clk ) begin
if( ~rx_vld && task_id_vld ) begin
task_id_h_r <= task_id_h ;
task_id_l_r <= task_id_l ;
end
end
reg [2:0] push_cnt ;
always @ ( posedge clk ) begin
if( rst )
push_cnt <= 3'b0 ;
else if( reg_busy && rx_stop && ~rx_vld)
push_cnt <= 3'b1 ;
else if( |push_cnt && push_cnt < `RX_DATA_LEN )
push_cnt <= push_cnt + 3'b1 ;
else
push_cnt <= 3'b0 ;
end
assign rx_vld = |push_cnt ;
assign rx_dat = push_cnt == 1 ? MY_RXID :
push_cnt == 2 ? task_id_h_r :
push_cnt == 3 ? task_id_l_r :
push_cnt == 4 ? timer_cnt : nonce_buf ;
assign rx_start = reg_busy && rx_stop && ~rx_vld ;
assign rx_last = push_cnt == `RX_DATA_LEN ;
endmodule | 26 |
140,941 | data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v | 9,286,699 | txc.v | v | 119 | 72 | [] | [] | [] | [(14, 129)] | null | null | 1: b'%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:2: Cannot find include file: alink_define.v\n`include "alink_define.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.sv\n alink_define.v\n alink_define.v.v\n alink_define.v.sv\n obj_dir/alink_define.v\n obj_dir/alink_define.v.v\n obj_dir/alink_define.v.sv\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:8: Define or directive not defined: \'`PHY_NUM\'\ninput [`PHY_NUM-1:0] reg_mask ,\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:14: Define or directive not defined: \'`PHY_NUM\'\noutput reg [`PHY_NUM-1:0]tx_phy_sel ,\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:19: Define or directive not defined: \'`PHY_NUM\'\noutput [32*`PHY_NUM-1:0] timer_cnt , \n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:20: Define or directive not defined: \'`PHY_NUM\'\noutput [`PHY_NUM-1:0] reg_busy \n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:27: Define or directive not defined: \'`PHY_NUM\'\nwire [`PHY_NUM-1:0] timer_start ;\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:28: Define or directive not defined: \'`PHY_NUM\'\nwire [`PHY_NUM-1:0] timer_busy ;\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:36: Define or directive not defined: \'`PHY_NUM\'\n for( i=0 ; i < `PHY_NUM ; i = i + 1 ) begin : G\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for( i=0 ; i < `PHY_NUM ; i = i + 1 ) begin : G\n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:50: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n IDLE: if( |tx_phy_sel ) nxt_state = REQ ;\n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n REQ : if( tx_task_vld ) nxt_state = SENT ;\n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:69: syntax error, unexpected \'=\', expecting IDENTIFIER\n SENT: if( tx_phy_done ) nxt_state = IDLE ;\n ^\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/txc.v:70: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : nxt_state = IDLE ;\n ^\n%Error: Cannot continue\n' | 309,960 | module | module txc(
input clk ,
input rst ,
input reg_flush ,
input [`PHY_NUM-1:0] reg_mask ,
input task_id_vld ,
input [31:0] reg_tout ,
input tx_task_vld ,
output tx_phy_start,
output reg [`PHY_NUM-1:0]tx_phy_sel ,
input tx_phy_done ,
output reg [1:0] cur_state ,
output reg [1:0] nxt_state ,
output [32*`PHY_NUM-1:0] timer_cnt ,
output [`PHY_NUM-1:0] reg_busy
);
parameter IDLE = 2'b00 ;
parameter REQ = 2'b01 ;
parameter SENT = 2'b10 ;
wire [`PHY_NUM-1:0] timer_start ;
wire [`PHY_NUM-1:0] timer_busy ;
assign tx_phy_start = cur_state == REQ && nxt_state == SENT ;
genvar i ;
generate
for( i=0 ; i < `PHY_NUM ; i = i + 1 ) begin : G
assign timer_start[i] = task_id_vld & tx_phy_sel[i] ;
tx_timer tx_timer(
.clk (clk ) ,
.rst (rst ) ,
.reg_flush (reg_flush ) ,
.reg_tout (reg_tout ) ,
.timer_start (timer_start[i] ) ,
.timer_busy (timer_busy[i] ) ,
.timer_cnt (timer_cnt[i*32+32-1:i*32] )
);
assign reg_busy[i] = timer_start[i] | timer_busy[i] ;
end
endgenerate
always @ ( posedge clk ) begin
if( rst || reg_flush )
cur_state <= IDLE ;
else
cur_state <= nxt_state ;
end
always @ ( * ) begin
nxt_state = cur_state ;
case( cur_state )
IDLE: if( |tx_phy_sel ) nxt_state = REQ ;
REQ : if( tx_task_vld ) nxt_state = SENT ;
SENT: if( tx_phy_done ) nxt_state = IDLE ;
default : nxt_state = IDLE ;
endcase
end
always @ ( posedge clk ) begin
if( rst || reg_flush || (cur_state == SENT && nxt_state == IDLE))
tx_phy_sel <= 32'b0 ;
else if( cur_state == IDLE ) begin
if( ~reg_busy[0 ]&®_mask[0 ] ) tx_phy_sel <= 32'b1<<0 ;
else if( ~reg_busy[1 ]&®_mask[1 ] ) tx_phy_sel <= 32'b1<<1 ;
else if( ~reg_busy[2 ]&®_mask[2 ] ) tx_phy_sel <= 32'b1<<2 ;
else if( ~reg_busy[3 ]&®_mask[3 ] ) tx_phy_sel <= 32'b1<<3 ;
else if( ~reg_busy[4 ]&®_mask[4 ] ) tx_phy_sel <= 32'b1<<4 ;
`ifdef PHY_10
else if( ~reg_busy[5 ]&®_mask[5 ] ) tx_phy_sel <= 32'b1<<5 ;
else if( ~reg_busy[6 ]&®_mask[6 ] ) tx_phy_sel <= 32'b1<<6 ;
else if( ~reg_busy[7 ]&®_mask[7 ] ) tx_phy_sel <= 32'b1<<7 ;
else if( ~reg_busy[8 ]&®_mask[8 ] ) tx_phy_sel <= 32'b1<<8 ;
else if( ~reg_busy[9 ]&®_mask[9 ] ) tx_phy_sel <= 32'b1<<9 ;
else if( ~reg_busy[10]&®_mask[10] ) tx_phy_sel <= 32'b1<<10 ;
else if( ~reg_busy[11]&®_mask[11] ) tx_phy_sel <= 32'b1<<11 ;
else if( ~reg_busy[12]&®_mask[12] ) tx_phy_sel <= 32'b1<<12 ;
else if( ~reg_busy[13]&®_mask[13] ) tx_phy_sel <= 32'b1<<13 ;
else if( ~reg_busy[14]&®_mask[14] ) tx_phy_sel <= 32'b1<<14 ;
else if( ~reg_busy[15]&®_mask[15] ) tx_phy_sel <= 32'b1<<15 ;
else if( ~reg_busy[16]&®_mask[16] ) tx_phy_sel <= 32'b1<<16 ;
else if( ~reg_busy[17]&®_mask[17] ) tx_phy_sel <= 32'b1<<17 ;
else if( ~reg_busy[18]&®_mask[18] ) tx_phy_sel <= 32'b1<<18 ;
else if( ~reg_busy[19]&®_mask[19] ) tx_phy_sel <= 32'b1<<19 ;
else if( ~reg_busy[20]&®_mask[20] ) tx_phy_sel <= 32'b1<<20 ;
else if( ~reg_busy[21]&®_mask[21] ) tx_phy_sel <= 32'b1<<21 ;
else if( ~reg_busy[22]&®_mask[22] ) tx_phy_sel <= 32'b1<<22 ;
else if( ~reg_busy[23]&®_mask[23] ) tx_phy_sel <= 32'b1<<23 ;
else if( ~reg_busy[24]&®_mask[24] ) tx_phy_sel <= 32'b1<<24 ;
else if( ~reg_busy[25]&®_mask[25] ) tx_phy_sel <= 32'b1<<25 ;
else if( ~reg_busy[26]&®_mask[26] ) tx_phy_sel <= 32'b1<<26 ;
else if( ~reg_busy[27]&®_mask[27] ) tx_phy_sel <= 32'b1<<27 ;
else if( ~reg_busy[28]&®_mask[28] ) tx_phy_sel <= 32'b1<<28 ;
else if( ~reg_busy[29]&®_mask[29] ) tx_phy_sel <= 32'b1<<29 ;
else if( ~reg_busy[30]&®_mask[30] ) tx_phy_sel <= 32'b1<<30 ;
else if( ~reg_busy[31]&®_mask[31] ) tx_phy_sel <= 32'b1<<31 ;
`endif
else tx_phy_sel <= 32'b0 ;
end
end
endmodule | module txc(
input clk ,
input rst ,
input reg_flush ,
input [`PHY_NUM-1:0] reg_mask ,
input task_id_vld ,
input [31:0] reg_tout ,
input tx_task_vld ,
output tx_phy_start,
output reg [`PHY_NUM-1:0]tx_phy_sel ,
input tx_phy_done ,
output reg [1:0] cur_state ,
output reg [1:0] nxt_state ,
output [32*`PHY_NUM-1:0] timer_cnt ,
output [`PHY_NUM-1:0] reg_busy
); |
parameter IDLE = 2'b00 ;
parameter REQ = 2'b01 ;
parameter SENT = 2'b10 ;
wire [`PHY_NUM-1:0] timer_start ;
wire [`PHY_NUM-1:0] timer_busy ;
assign tx_phy_start = cur_state == REQ && nxt_state == SENT ;
genvar i ;
generate
for( i=0 ; i < `PHY_NUM ; i = i + 1 ) begin : G
assign timer_start[i] = task_id_vld & tx_phy_sel[i] ;
tx_timer tx_timer(
.clk (clk ) ,
.rst (rst ) ,
.reg_flush (reg_flush ) ,
.reg_tout (reg_tout ) ,
.timer_start (timer_start[i] ) ,
.timer_busy (timer_busy[i] ) ,
.timer_cnt (timer_cnt[i*32+32-1:i*32] )
);
assign reg_busy[i] = timer_start[i] | timer_busy[i] ;
end
endgenerate
always @ ( posedge clk ) begin
if( rst || reg_flush )
cur_state <= IDLE ;
else
cur_state <= nxt_state ;
end
always @ ( * ) begin
nxt_state = cur_state ;
case( cur_state )
IDLE: if( |tx_phy_sel ) nxt_state = REQ ;
REQ : if( tx_task_vld ) nxt_state = SENT ;
SENT: if( tx_phy_done ) nxt_state = IDLE ;
default : nxt_state = IDLE ;
endcase
end
always @ ( posedge clk ) begin
if( rst || reg_flush || (cur_state == SENT && nxt_state == IDLE))
tx_phy_sel <= 32'b0 ;
else if( cur_state == IDLE ) begin
if( ~reg_busy[0 ]&®_mask[0 ] ) tx_phy_sel <= 32'b1<<0 ;
else if( ~reg_busy[1 ]&®_mask[1 ] ) tx_phy_sel <= 32'b1<<1 ;
else if( ~reg_busy[2 ]&®_mask[2 ] ) tx_phy_sel <= 32'b1<<2 ;
else if( ~reg_busy[3 ]&®_mask[3 ] ) tx_phy_sel <= 32'b1<<3 ;
else if( ~reg_busy[4 ]&®_mask[4 ] ) tx_phy_sel <= 32'b1<<4 ;
`ifdef PHY_10
else if( ~reg_busy[5 ]&®_mask[5 ] ) tx_phy_sel <= 32'b1<<5 ;
else if( ~reg_busy[6 ]&®_mask[6 ] ) tx_phy_sel <= 32'b1<<6 ;
else if( ~reg_busy[7 ]&®_mask[7 ] ) tx_phy_sel <= 32'b1<<7 ;
else if( ~reg_busy[8 ]&®_mask[8 ] ) tx_phy_sel <= 32'b1<<8 ;
else if( ~reg_busy[9 ]&®_mask[9 ] ) tx_phy_sel <= 32'b1<<9 ;
else if( ~reg_busy[10]&®_mask[10] ) tx_phy_sel <= 32'b1<<10 ;
else if( ~reg_busy[11]&®_mask[11] ) tx_phy_sel <= 32'b1<<11 ;
else if( ~reg_busy[12]&®_mask[12] ) tx_phy_sel <= 32'b1<<12 ;
else if( ~reg_busy[13]&®_mask[13] ) tx_phy_sel <= 32'b1<<13 ;
else if( ~reg_busy[14]&®_mask[14] ) tx_phy_sel <= 32'b1<<14 ;
else if( ~reg_busy[15]&®_mask[15] ) tx_phy_sel <= 32'b1<<15 ;
else if( ~reg_busy[16]&®_mask[16] ) tx_phy_sel <= 32'b1<<16 ;
else if( ~reg_busy[17]&®_mask[17] ) tx_phy_sel <= 32'b1<<17 ;
else if( ~reg_busy[18]&®_mask[18] ) tx_phy_sel <= 32'b1<<18 ;
else if( ~reg_busy[19]&®_mask[19] ) tx_phy_sel <= 32'b1<<19 ;
else if( ~reg_busy[20]&®_mask[20] ) tx_phy_sel <= 32'b1<<20 ;
else if( ~reg_busy[21]&®_mask[21] ) tx_phy_sel <= 32'b1<<21 ;
else if( ~reg_busy[22]&®_mask[22] ) tx_phy_sel <= 32'b1<<22 ;
else if( ~reg_busy[23]&®_mask[23] ) tx_phy_sel <= 32'b1<<23 ;
else if( ~reg_busy[24]&®_mask[24] ) tx_phy_sel <= 32'b1<<24 ;
else if( ~reg_busy[25]&®_mask[25] ) tx_phy_sel <= 32'b1<<25 ;
else if( ~reg_busy[26]&®_mask[26] ) tx_phy_sel <= 32'b1<<26 ;
else if( ~reg_busy[27]&®_mask[27] ) tx_phy_sel <= 32'b1<<27 ;
else if( ~reg_busy[28]&®_mask[28] ) tx_phy_sel <= 32'b1<<28 ;
else if( ~reg_busy[29]&®_mask[29] ) tx_phy_sel <= 32'b1<<29 ;
else if( ~reg_busy[30]&®_mask[30] ) tx_phy_sel <= 32'b1<<30 ;
else if( ~reg_busy[31]&®_mask[31] ) tx_phy_sel <= 32'b1<<31 ;
`endif
else tx_phy_sel <= 32'b0 ;
end
end
endmodule | 26 |
140,943 | data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/tx_timer.v | 9,286,699 | tx_timer.v | v | 35 | 58 | [] | [] | [] | [(14, 45)] | null | null | 1: b'%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/alink/tx_timer.v:2: Cannot find include file: alink_define.v\n`include "alink_define.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/alink,data/full_repos/permissive/9286699/alink_define.v.sv\n alink_define.v\n alink_define.v.v\n alink_define.v.sv\n obj_dir/alink_define.v\n obj_dir/alink_define.v.v\n obj_dir/alink_define.v.sv\n%Error: Exiting due to 1 error(s)\n' | 309,962 | module | module tx_timer(
input clk ,
input rst ,
input reg_flush ,
input [31:0] reg_tout ,
input timer_start ,
output reg timer_busy ,
output [31:0] timer_cnt
);
reg [25:0] timer ;
assign timer_cnt = {6'b0,timer} ;
always @ ( posedge clk ) begin
if( rst || (timer == reg_tout) || reg_flush )
timer <= 'b0 ;
else if( timer_start )
timer <= 'b1 ;
else if( |timer && (timer < reg_tout))
timer <= 'b1 + timer ;
end
always @ ( posedge clk ) begin
if( rst )
timer_busy <= 1'b0 ;
else if( timer_start )
timer_busy <= 1'b1 ;
else if ( (timer == reg_tout[25:0]) && |reg_tout[25:0] )
timer_busy <= 1'b0 ;
end
endmodule | module tx_timer(
input clk ,
input rst ,
input reg_flush ,
input [31:0] reg_tout ,
input timer_start ,
output reg timer_busy ,
output [31:0] timer_cnt
); |
reg [25:0] timer ;
assign timer_cnt = {6'b0,timer} ;
always @ ( posedge clk ) begin
if( rst || (timer == reg_tout) || reg_flush )
timer <= 'b0 ;
else if( timer_start )
timer <= 'b1 ;
else if( |timer && (timer < reg_tout))
timer <= 'b1 + timer ;
end
always @ ( posedge clk ) begin
if( rst )
timer_busy <= 1'b0 ;
else if( timer_start )
timer_busy <= 1'b1 ;
else if ( (timer == reg_tout[25:0]) && |reg_tout[25:0] )
timer_busy <= 1'b0 ;
end
endmodule | 26 |
140,944 | data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/shift.v | 9,286,699 | shift.v | v | 87 | 55 | [] | [] | [] | [(7, 86)] | null | null | 1: b"%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/shift.v:23: Duplicate declaration of signal: 'sft_mr_n'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg sft_mr_n ;\n ^~~~~~~~\n data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/shift.v:19: ... Location of original declaration\noutput sft_mr_n ,\n ^~~~~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/shift.v:24: Duplicate declaration of signal: 'sft_oe_n'\nreg sft_oe_n ;\n ^~~~~~~~\n data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/shift.v:20: ... Location of original declaration\noutput sft_oe_n \n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,999 | module | module shift(
input clk ,
input rst ,
input vld ,
input [1:0] cmd ,
input cmd_oen ,
input [7:0] din ,
output done ,
output sft_shcp ,
output sft_ds ,
output sft_stcp ,
output sft_mr_n ,
output sft_oe_n
);
reg sft_mr_n ;
reg sft_oe_n ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_mr_n <= 1'b1 ;
else if( vld && cmd == 2'b00 )
sft_mr_n <= 1'b0 ;
else
sft_mr_n <= 1'b1 ;
end
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_oe_n <= 1'b1 ;
else if( vld && cmd == 2'b11 )
sft_oe_n <= cmd_oen ;
end
reg [5:0] shcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
shcp_cnt <= 0 ;
else if( vld && cmd == 2'b01 )
shcp_cnt <= 1 ;
else if( |shcp_cnt )
shcp_cnt <= shcp_cnt + 1 ;
end
assign sft_shcp = shcp_cnt[2] ;
reg [7:0] data ;
always @ ( posedge clk ) begin
if( vld && cmd == 2'b01 )
data <= din ;
else if( &shcp_cnt[2:0] )
data <= data >> 1 ;
end
assign sft_ds = (vld&&cmd==2'b01) ? din[0] : data[0] ;
reg [5:0] stcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
stcp_cnt <= 0 ;
else if( vld && cmd == 2'b10 )
stcp_cnt <= 1 ;
else if( |stcp_cnt )
stcp_cnt <= stcp_cnt + 1 ;
end
assign sft_stcp = stcp_cnt[2] ;
assign done = (stcp_cnt == 63) || (shcp_cnt == 63) ;
endmodule | module shift(
input clk ,
input rst ,
input vld ,
input [1:0] cmd ,
input cmd_oen ,
input [7:0] din ,
output done ,
output sft_shcp ,
output sft_ds ,
output sft_stcp ,
output sft_mr_n ,
output sft_oe_n
); |
reg sft_mr_n ;
reg sft_oe_n ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_mr_n <= 1'b1 ;
else if( vld && cmd == 2'b00 )
sft_mr_n <= 1'b0 ;
else
sft_mr_n <= 1'b1 ;
end
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_oe_n <= 1'b1 ;
else if( vld && cmd == 2'b11 )
sft_oe_n <= cmd_oen ;
end
reg [5:0] shcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
shcp_cnt <= 0 ;
else if( vld && cmd == 2'b01 )
shcp_cnt <= 1 ;
else if( |shcp_cnt )
shcp_cnt <= shcp_cnt + 1 ;
end
assign sft_shcp = shcp_cnt[2] ;
reg [7:0] data ;
always @ ( posedge clk ) begin
if( vld && cmd == 2'b01 )
data <= din ;
else if( &shcp_cnt[2:0] )
data <= data >> 1 ;
end
assign sft_ds = (vld&&cmd==2'b01) ? din[0] : data[0] ;
reg [5:0] stcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
stcp_cnt <= 0 ;
else if( vld && cmd == 2'b10 )
stcp_cnt <= 1 ;
else if( |stcp_cnt )
stcp_cnt <= stcp_cnt + 1 ;
end
assign sft_stcp = stcp_cnt[2] ;
assign done = (stcp_cnt == 63) || (shcp_cnt == 63) ;
endmodule | 26 |
140,946 | data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/twi_core.v | 9,286,699 | twi_core.v | v | 173 | 77 | [] | [] | [] | [(14, 182)] | null | null | 1: b'%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/twi_core.v:2: Cannot find include file: twi_define.v\n`include "twi_define.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9286699/verilog/superkdf9/components/twi,data/full_repos/permissive/9286699/twi_define.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/twi,data/full_repos/permissive/9286699/twi_define.v.v\n data/full_repos/permissive/9286699/verilog/superkdf9/components/twi,data/full_repos/permissive/9286699/twi_define.v.sv\n twi_define.v\n twi_define.v.v\n twi_define.v.sv\n obj_dir/twi_define.v\n obj_dir/twi_define.v.v\n obj_dir/twi_define.v.sv\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/twi_core.v:53: Define or directive not defined: \'`I2CR\'\n else if( wr_addr == `I2CR && wr ) begin\n ^~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/twi_core.v:53: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n else if( wr_addr == `I2CR && wr ) begin\n ^~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/twi_core.v:58: syntax error, unexpected else\n else begin\n ^~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/twi_core.v:67: Define or directive not defined: \'`I2WD\'\n else if( wr_addr == `I2WD && wr )\n ^~~~~\n%Error: data/full_repos/permissive/9286699/verilog/superkdf9/components/twi/twi_core.v:77: Define or directive not defined: \'`I2CR\'\n else if( wr_addr == `I2CR && wr )\n ^~~~~\n%Error: Exiting due to 6 error(s)\n' | 310,001 | module | module twi_core (
input clk ,
input rst ,
input wr ,
input [7:0] data_in,
input [7:0] wr_addr,
output [7:0] i2cr ,
output [7:0] i2rd ,
output twi_scl_o ,
input twi_sda_i ,
output twi_sda_oen
);
parameter TWI_F = 3 ;
parameter START_SDA = 600/TWI_F+1 ;
parameter SDA_SET = 700/TWI_F+1 ;
parameter SDA_WAIT = 600/TWI_F+1 ;
parameter START_SCL = START_SDA+100/TWI_F+1 ;
parameter TWI_DONE = START_SCL+1300/TWI_F+1 ;
parameter STOP_SCL = 100/TWI_F+1 ;
reg [7:0] rd_buf ;
reg [11:0] cnt ;
reg done ;
reg [3:0] byte_cnt ;
reg [7:0] i2wd_r ;
reg [7:0] i2rd_r ;
assign i2wd = i2wd_r ;
assign i2rd = rd_buf ;
reg en_r , init_r ;
reg [2:0] cmd_r ;
wire cmd_start = cmd_r == 3'b000 && en_r ;
wire cmd_wr = cmd_r == 3'b001 && en_r ;
wire cmd_rd = cmd_r == 3'b010 && en_r ;
wire cmd_stop = cmd_r == 3'b011 && en_r ;
wire cmd_rd_no = cmd_r == 3'b100 && en_r ;
assign i2cr = {1'b0,cmd_r,1'b0,done,init_r,en_r};
always @ ( posedge clk ) begin
if( rst ) begin
en_r <= 1'b0 ;
init_r <= 1'b0 ;
cmd_r <= 3'b0 ;
end
else if( wr_addr == `I2CR && wr ) begin
en_r <= data_in[0] ;
init_r <= data_in[1] ;
cmd_r <= data_in[6:4] ;
end
else begin
init_r <= 1'b0 ;
end
end
always @ ( posedge clk ) begin
if( rst )
i2wd_r <= 8'b0 ;
else if( wr_addr == `I2WD && wr )
i2wd_r <= data_in ;
else if( cmd_wr && cnt == (SDA_SET*2+SDA_WAIT) )
i2wd_r <= {i2wd_r[6:0],1'b1};
end
always @ ( posedge clk ) begin
if( rst )
done <= 1'b0 ;
else if( wr_addr == `I2CR && wr )
done <= data_in[2] ;
else if( init_r )
done <= 1'b0 ;
else if( (cmd_start || cmd_stop ) && cnt == TWI_DONE )
done <= 1'b1 ;
else if( (cmd_wr || cmd_rd) && byte_cnt == 9 )
done <= 1'b1 ;
end
always @ ( posedge clk ) begin
if( rst )
byte_cnt <= 4'b0 ;
else if( init_r )
byte_cnt <= 4'b0 ;
else if( (cmd_wr || cmd_rd) && (cnt == (SDA_SET*2+SDA_WAIT)) )
byte_cnt <= byte_cnt + 4'b1 ;
end
always @ ( posedge clk ) begin
if( rst || ~en_r )
cnt <= 12'b0 ;
else if( (cmd_start || cmd_stop ) && init_r )
cnt <= 12'b1 ;
else if( (cmd_start || cmd_stop ) && cnt != 0 )
cnt <= cnt + 12'b1 ;
else if( (cmd_wr || cmd_rd) && init_r )
cnt <= 12'b0 ;
else if( (cmd_wr || cmd_rd) && cnt < (SDA_SET*2+SDA_WAIT) && byte_cnt < 9 )
cnt <= cnt + 12'b1 ;
else if( (cmd_wr || cmd_rd) && cnt == (SDA_SET*2+SDA_WAIT) )
cnt <= 12'b0 ;
end
reg scl_o ;
always @ ( posedge clk ) begin
if( rst || ~en_r ) begin
scl_o <= 1'b1 ;
end
else if( cmd_start ) begin
if( cnt == START_SCL )
scl_o <= 1'b0 ;
end
else if( cmd_wr || cmd_rd ) begin
scl_o <= cnt == 12'b0 ? 1'b0 :
cnt == SDA_SET ? 1'b1 :
cnt == (SDA_SET+SDA_WAIT) ? 1'b0 : scl_o ;
end
else if( cmd_stop && cnt == SDA_SET ) begin
scl_o <= 1'b1 ;
end
end
reg sda_oen ;
always @ ( posedge clk ) begin
if( rst || ~en_r ) begin
sda_oen <= 1'b1 ;
end
else if( cmd_start ) begin
if( cnt == START_SDA )
sda_oen <= 1'b0 ;
end
else if( cmd_wr ) begin
sda_oen <= i2wd_r[7] ;
end
else if( cmd_rd ) begin
if( byte_cnt == 8 || byte_cnt == 9)
sda_oen <= 1'b0 ;
else
sda_oen <= 1'b1 ;
end
else if( cmd_stop ) begin
if( init_r )
sda_oen <= 1'b0 ;
else if( cnt == STOP_SCL+SDA_SET )
sda_oen <= 1'b1 ;
end
else if( cmd_rd_no ) begin
sda_oen <= 1'b1 ;
end
end
always @ ( posedge clk ) begin
if( rst )
rd_buf <= 8'b0 ;
else if( cmd_rd && cnt == (SDA_SET+100) && byte_cnt <=7)
rd_buf <= {rd_buf[6:0],twi_sda_i} ;
end
assign twi_scl_o = scl_o ;
assign twi_sda_oen = sda_oen ;
endmodule | module twi_core (
input clk ,
input rst ,
input wr ,
input [7:0] data_in,
input [7:0] wr_addr,
output [7:0] i2cr ,
output [7:0] i2rd ,
output twi_scl_o ,
input twi_sda_i ,
output twi_sda_oen
); |
parameter TWI_F = 3 ;
parameter START_SDA = 600/TWI_F+1 ;
parameter SDA_SET = 700/TWI_F+1 ;
parameter SDA_WAIT = 600/TWI_F+1 ;
parameter START_SCL = START_SDA+100/TWI_F+1 ;
parameter TWI_DONE = START_SCL+1300/TWI_F+1 ;
parameter STOP_SCL = 100/TWI_F+1 ;
reg [7:0] rd_buf ;
reg [11:0] cnt ;
reg done ;
reg [3:0] byte_cnt ;
reg [7:0] i2wd_r ;
reg [7:0] i2rd_r ;
assign i2wd = i2wd_r ;
assign i2rd = rd_buf ;
reg en_r , init_r ;
reg [2:0] cmd_r ;
wire cmd_start = cmd_r == 3'b000 && en_r ;
wire cmd_wr = cmd_r == 3'b001 && en_r ;
wire cmd_rd = cmd_r == 3'b010 && en_r ;
wire cmd_stop = cmd_r == 3'b011 && en_r ;
wire cmd_rd_no = cmd_r == 3'b100 && en_r ;
assign i2cr = {1'b0,cmd_r,1'b0,done,init_r,en_r};
always @ ( posedge clk ) begin
if( rst ) begin
en_r <= 1'b0 ;
init_r <= 1'b0 ;
cmd_r <= 3'b0 ;
end
else if( wr_addr == `I2CR && wr ) begin
en_r <= data_in[0] ;
init_r <= data_in[1] ;
cmd_r <= data_in[6:4] ;
end
else begin
init_r <= 1'b0 ;
end
end
always @ ( posedge clk ) begin
if( rst )
i2wd_r <= 8'b0 ;
else if( wr_addr == `I2WD && wr )
i2wd_r <= data_in ;
else if( cmd_wr && cnt == (SDA_SET*2+SDA_WAIT) )
i2wd_r <= {i2wd_r[6:0],1'b1};
end
always @ ( posedge clk ) begin
if( rst )
done <= 1'b0 ;
else if( wr_addr == `I2CR && wr )
done <= data_in[2] ;
else if( init_r )
done <= 1'b0 ;
else if( (cmd_start || cmd_stop ) && cnt == TWI_DONE )
done <= 1'b1 ;
else if( (cmd_wr || cmd_rd) && byte_cnt == 9 )
done <= 1'b1 ;
end
always @ ( posedge clk ) begin
if( rst )
byte_cnt <= 4'b0 ;
else if( init_r )
byte_cnt <= 4'b0 ;
else if( (cmd_wr || cmd_rd) && (cnt == (SDA_SET*2+SDA_WAIT)) )
byte_cnt <= byte_cnt + 4'b1 ;
end
always @ ( posedge clk ) begin
if( rst || ~en_r )
cnt <= 12'b0 ;
else if( (cmd_start || cmd_stop ) && init_r )
cnt <= 12'b1 ;
else if( (cmd_start || cmd_stop ) && cnt != 0 )
cnt <= cnt + 12'b1 ;
else if( (cmd_wr || cmd_rd) && init_r )
cnt <= 12'b0 ;
else if( (cmd_wr || cmd_rd) && cnt < (SDA_SET*2+SDA_WAIT) && byte_cnt < 9 )
cnt <= cnt + 12'b1 ;
else if( (cmd_wr || cmd_rd) && cnt == (SDA_SET*2+SDA_WAIT) )
cnt <= 12'b0 ;
end
reg scl_o ;
always @ ( posedge clk ) begin
if( rst || ~en_r ) begin
scl_o <= 1'b1 ;
end
else if( cmd_start ) begin
if( cnt == START_SCL )
scl_o <= 1'b0 ;
end
else if( cmd_wr || cmd_rd ) begin
scl_o <= cnt == 12'b0 ? 1'b0 :
cnt == SDA_SET ? 1'b1 :
cnt == (SDA_SET+SDA_WAIT) ? 1'b0 : scl_o ;
end
else if( cmd_stop && cnt == SDA_SET ) begin
scl_o <= 1'b1 ;
end
end
reg sda_oen ;
always @ ( posedge clk ) begin
if( rst || ~en_r ) begin
sda_oen <= 1'b1 ;
end
else if( cmd_start ) begin
if( cnt == START_SDA )
sda_oen <= 1'b0 ;
end
else if( cmd_wr ) begin
sda_oen <= i2wd_r[7] ;
end
else if( cmd_rd ) begin
if( byte_cnt == 8 || byte_cnt == 9)
sda_oen <= 1'b0 ;
else
sda_oen <= 1'b1 ;
end
else if( cmd_stop ) begin
if( init_r )
sda_oen <= 1'b0 ;
else if( cnt == STOP_SCL+SDA_SET )
sda_oen <= 1'b1 ;
end
else if( cmd_rd_no ) begin
sda_oen <= 1'b1 ;
end
end
always @ ( posedge clk ) begin
if( rst )
rd_buf <= 8'b0 ;
else if( cmd_rd && cnt == (SDA_SET+100) && byte_cnt <=7)
rd_buf <= {rd_buf[6:0],twi_sda_i} ;
end
assign twi_scl_o = scl_o ;
assign twi_sda_oen = sda_oen ;
endmodule | 26 |
140,948 | data/full_repos/permissive/92914346/CPLD Firmware/adc_serial_interface.v | 92,914,346 | adc_serial_interface.v | v | 305 | 121 | [] | [] | [] | [(1, 304)] | null | null | 1: b'%Error: Cannot find file containing module: Firmware,data/full_repos/permissive/92914346\n ... Looked in:\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.v\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.sv\n Firmware,data/full_repos/permissive/92914346\n Firmware,data/full_repos/permissive/92914346.v\n Firmware,data/full_repos/permissive/92914346.sv\n obj_dir/Firmware,data/full_repos/permissive/92914346\n obj_dir/Firmware,data/full_repos/permissive/92914346.v\n obj_dir/Firmware,data/full_repos/permissive/92914346.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/92914346/CPLD\n%Error: Cannot find file containing module: Firmware/adc_serial_interface.v\n%Error: Exiting due to 3 error(s)\n' | 310,019 | module | module adc_serial_interface ( clock, reset, start, sd_write_ready,
adc_data_ready, adc_clock, adc_data_0, adc_data_1,
adc_channel_data_ch1, adc_channel_data_ch2,
adc_channel_data_ch3, adc_channel_data_ch4,
adc_channel_data_ch5, adc_channel_data_ch6,
adc_channel_data_ch7, adc_channel_data_ch8,
adc_event_detected_ch1, adc_event_detected_ch2,
adc_event_detected_ch3, adc_event_detected_ch4,
adc_event_detected_ch5, adc_event_detected_ch6,
adc_event_detected_ch7, adc_event_detected_ch8,
adc_buffer_data, buffer_write_enable, buffer_full);
input clock;
input reset;
input start;
input sd_write_ready;
input adc_data_ready;
input adc_clock;
input adc_data_0;
input adc_data_1;
input buffer_full;
output reg buffer_write_enable;
output reg [31:0] adc_buffer_data;
output reg [31:0] adc_channel_data_ch1;
output reg [31:0] adc_channel_data_ch2;
output reg [31:0] adc_channel_data_ch3;
output reg [31:0] adc_channel_data_ch4;
output reg [31:0] adc_channel_data_ch5;
output reg [31:0] adc_channel_data_ch6;
output reg [31:0] adc_channel_data_ch7;
output reg [31:0] adc_channel_data_ch8;
output adc_event_detected_ch1;
output adc_event_detected_ch2;
output adc_event_detected_ch3;
output adc_event_detected_ch4;
output adc_event_detected_ch5;
output adc_event_detected_ch6;
output adc_event_detected_ch7;
output adc_event_detected_ch8;
reg adc_channel_data_ready_ch1;
reg adc_channel_data_ready_ch2;
reg adc_channel_data_ready_ch3;
reg adc_channel_data_ready_ch4;
reg adc_channel_data_ready_ch5;
reg adc_channel_data_ready_ch6;
reg adc_channel_data_ready_ch7;
reg adc_channel_data_ready_ch8;
reg [31:0] adc_channel_data_0;
reg [31:0] adc_channel_data_1;
reg adc_channel_data_ready;
reg adc_data_ready_reg;
reg adc_clock_reg;
reg adc_clock_reg_1;
reg adc_data_0_reg;
reg adc_data_1_reg;
reg [ 8:0] bit_count;
reg buffer_write_start;
always@(posedge clock or posedge reset)
begin
if(reset)
begin
adc_data_ready_reg <= 1'b0;
adc_clock_reg <= 1'b0;
adc_clock_reg_1 <= 1'b0;
adc_data_0_reg <= 1'b0;
adc_data_1_reg <= 1'b0;
bit_count <= 0;
adc_channel_data_ready <= 1'b0;
adc_buffer_data <= 32'h0;
adc_channel_data_0 <= 32'h0;
adc_channel_data_1 <= 32'h0;
adc_channel_data_ch1 <= 32'h1;
adc_channel_data_ch2 <= 32'h2;
adc_channel_data_ch3 <= 32'h3;
adc_channel_data_ch4 <= 32'h4;
adc_channel_data_ch5 <= 32'h5;
adc_channel_data_ch6 <= 32'h6;
adc_channel_data_ch7 <= 32'h7;
adc_channel_data_ch8 <= 32'h8;
adc_channel_data_ready_ch1 <= 1'b0;
adc_channel_data_ready_ch2 <= 1'b0;
adc_channel_data_ready_ch3 <= 1'b0;
adc_channel_data_ready_ch4 <= 1'b0;
adc_channel_data_ready_ch5 <= 1'b0;
adc_channel_data_ready_ch6 <= 1'b0;
adc_channel_data_ready_ch7 <= 1'b0;
adc_channel_data_ready_ch8 <= 1'b0;
buffer_write_enable <= 1'b0;
buffer_write_start <= 1'b0;
end
else if(start)
begin
adc_data_ready_reg <= adc_data_ready;
adc_clock_reg <= adc_clock;
adc_clock_reg_1 <= adc_clock_reg;
adc_data_0_reg <= adc_data_0;
adc_data_1_reg <= adc_data_1;
if(adc_channel_data_ready)
begin
if(bit_count == 9'h020)
begin
adc_channel_data_ch1 <= adc_channel_data_0;
adc_channel_data_ready_ch1 <= 1'b1;
end
if(bit_count == 9'h040)
begin
adc_channel_data_ch2 <= adc_channel_data_0;
adc_channel_data_ready_ch2 <= 1'b1;
end
if(bit_count == 9'h060)
begin
adc_channel_data_ch3 <= adc_channel_data_0;
adc_channel_data_ready_ch3 <= 1'b1;
end
if(bit_count == 9'h080)
begin
adc_channel_data_ch4 <= adc_channel_data_0;
adc_channel_data_ready_ch4 <= 1'b1;
end
if(bit_count == 9'h0A0)
begin
adc_channel_data_ch5 <= adc_channel_data_0;
adc_channel_data_ready_ch5 <= 1'b1;
end
if(bit_count == 9'h0C0)
begin
adc_channel_data_ch6 <= adc_channel_data_0;
adc_channel_data_ready_ch6 <= 1'b1;
end
if(bit_count == 9'h0E0)
begin
adc_channel_data_ch7 <= adc_channel_data_0;
adc_channel_data_ready_ch7 <= 1'b1;
end
if(bit_count == 9'h100)
begin
adc_channel_data_ch8 <= adc_channel_data_0;
adc_channel_data_ready_ch8 <= 1'b1;
end
end
if(buffer_write_start && !buffer_write_enable && adc_channel_data_ready_ch8)
begin
buffer_write_enable <= 1'b1;
if(adc_channel_data_ready_ch1)
begin
adc_channel_data_ready_ch1 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch1;
end
else if(adc_channel_data_ready_ch2)
begin
adc_channel_data_ready_ch2 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch2;
end
else if(adc_channel_data_ready_ch3)
begin
adc_channel_data_ready_ch3 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch3;
end
else if(adc_channel_data_ready_ch4)
begin
adc_channel_data_ready_ch4 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch4;
end
else if(adc_channel_data_ready_ch5)
begin
adc_channel_data_ready_ch5 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch5;
end
else if(adc_channel_data_ready_ch6)
begin
adc_channel_data_ready_ch6 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch6;
end
else if(adc_channel_data_ready_ch7)
begin
adc_channel_data_ready_ch7 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch7;
end
else
begin
adc_channel_data_ready_ch8 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch8;
end
end
else
begin
buffer_write_enable <= 1'b0;
end
if(adc_data_ready_reg == 1'b1)
begin
bit_count <= 8'h00;
adc_channel_data_ready <= 1'b0;
if(sd_write_ready)
begin
if(!buffer_full)
buffer_write_start <= 1'b1;
else
buffer_write_start <= 1'b0;
end
end
else if((adc_clock_reg_1 == 1'b1) && (adc_clock_reg == 1'b0) && (bit_count < 9'h100))
begin
bit_count <= bit_count + 1;
adc_channel_data_0 <= {adc_channel_data_0[30:0],adc_data_0_reg};
adc_channel_data_1 <= {adc_channel_data_1[30:0],adc_data_1_reg};
if( (bit_count == 9'h01F) || (bit_count == 9'h03F) || (bit_count == 9'h05F) || (bit_count == 9'h07F)
|| (bit_count == 9'h09F) || (bit_count == 9'h0BF) || (bit_count == 9'h0DF) || (bit_count == 9'h0FF)
)
adc_channel_data_ready <= 1'b1;
end
else
adc_channel_data_ready <= 1'b0;
end
end
event_detect event_detect_ch1 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch1),
.adc_count(adc_channel_data_ch1[23:0]),
.event_detected(adc_event_detected_ch1));
event_detect event_detect_ch2 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch2),
.adc_count(adc_channel_data_ch2[23:0]),
.event_detected(adc_event_detected_ch2));
event_detect event_detect_ch3 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch3),
.adc_count(adc_channel_data_ch3[23:0]),
.event_detected(adc_event_detected_ch3));
event_detect event_detect_ch4 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch4),
.adc_count(adc_channel_data_ch4[23:0]),
.event_detected(adc_event_detected_ch4));
event_detect event_detect_ch5 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch5),
.adc_count(adc_channel_data_ch5[23:0]),
.event_detected(adc_event_detected_ch5));
event_detect event_detect_ch6 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch6),
.adc_count(adc_channel_data_ch6[23:0]),
.event_detected(adc_event_detected_ch6));
event_detect event_detect_ch7 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch7),
.adc_count(adc_channel_data_ch7[23:0]),
.event_detected(adc_event_detected_ch7));
event_detect event_detect_ch8 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch8),
.adc_count(adc_channel_data_ch8[23:0]),
.event_detected(adc_event_detected_ch8));
endmodule | module adc_serial_interface ( clock, reset, start, sd_write_ready,
adc_data_ready, adc_clock, adc_data_0, adc_data_1,
adc_channel_data_ch1, adc_channel_data_ch2,
adc_channel_data_ch3, adc_channel_data_ch4,
adc_channel_data_ch5, adc_channel_data_ch6,
adc_channel_data_ch7, adc_channel_data_ch8,
adc_event_detected_ch1, adc_event_detected_ch2,
adc_event_detected_ch3, adc_event_detected_ch4,
adc_event_detected_ch5, adc_event_detected_ch6,
adc_event_detected_ch7, adc_event_detected_ch8,
adc_buffer_data, buffer_write_enable, buffer_full); |
input clock;
input reset;
input start;
input sd_write_ready;
input adc_data_ready;
input adc_clock;
input adc_data_0;
input adc_data_1;
input buffer_full;
output reg buffer_write_enable;
output reg [31:0] adc_buffer_data;
output reg [31:0] adc_channel_data_ch1;
output reg [31:0] adc_channel_data_ch2;
output reg [31:0] adc_channel_data_ch3;
output reg [31:0] adc_channel_data_ch4;
output reg [31:0] adc_channel_data_ch5;
output reg [31:0] adc_channel_data_ch6;
output reg [31:0] adc_channel_data_ch7;
output reg [31:0] adc_channel_data_ch8;
output adc_event_detected_ch1;
output adc_event_detected_ch2;
output adc_event_detected_ch3;
output adc_event_detected_ch4;
output adc_event_detected_ch5;
output adc_event_detected_ch6;
output adc_event_detected_ch7;
output adc_event_detected_ch8;
reg adc_channel_data_ready_ch1;
reg adc_channel_data_ready_ch2;
reg adc_channel_data_ready_ch3;
reg adc_channel_data_ready_ch4;
reg adc_channel_data_ready_ch5;
reg adc_channel_data_ready_ch6;
reg adc_channel_data_ready_ch7;
reg adc_channel_data_ready_ch8;
reg [31:0] adc_channel_data_0;
reg [31:0] adc_channel_data_1;
reg adc_channel_data_ready;
reg adc_data_ready_reg;
reg adc_clock_reg;
reg adc_clock_reg_1;
reg adc_data_0_reg;
reg adc_data_1_reg;
reg [ 8:0] bit_count;
reg buffer_write_start;
always@(posedge clock or posedge reset)
begin
if(reset)
begin
adc_data_ready_reg <= 1'b0;
adc_clock_reg <= 1'b0;
adc_clock_reg_1 <= 1'b0;
adc_data_0_reg <= 1'b0;
adc_data_1_reg <= 1'b0;
bit_count <= 0;
adc_channel_data_ready <= 1'b0;
adc_buffer_data <= 32'h0;
adc_channel_data_0 <= 32'h0;
adc_channel_data_1 <= 32'h0;
adc_channel_data_ch1 <= 32'h1;
adc_channel_data_ch2 <= 32'h2;
adc_channel_data_ch3 <= 32'h3;
adc_channel_data_ch4 <= 32'h4;
adc_channel_data_ch5 <= 32'h5;
adc_channel_data_ch6 <= 32'h6;
adc_channel_data_ch7 <= 32'h7;
adc_channel_data_ch8 <= 32'h8;
adc_channel_data_ready_ch1 <= 1'b0;
adc_channel_data_ready_ch2 <= 1'b0;
adc_channel_data_ready_ch3 <= 1'b0;
adc_channel_data_ready_ch4 <= 1'b0;
adc_channel_data_ready_ch5 <= 1'b0;
adc_channel_data_ready_ch6 <= 1'b0;
adc_channel_data_ready_ch7 <= 1'b0;
adc_channel_data_ready_ch8 <= 1'b0;
buffer_write_enable <= 1'b0;
buffer_write_start <= 1'b0;
end
else if(start)
begin
adc_data_ready_reg <= adc_data_ready;
adc_clock_reg <= adc_clock;
adc_clock_reg_1 <= adc_clock_reg;
adc_data_0_reg <= adc_data_0;
adc_data_1_reg <= adc_data_1;
if(adc_channel_data_ready)
begin
if(bit_count == 9'h020)
begin
adc_channel_data_ch1 <= adc_channel_data_0;
adc_channel_data_ready_ch1 <= 1'b1;
end
if(bit_count == 9'h040)
begin
adc_channel_data_ch2 <= adc_channel_data_0;
adc_channel_data_ready_ch2 <= 1'b1;
end
if(bit_count == 9'h060)
begin
adc_channel_data_ch3 <= adc_channel_data_0;
adc_channel_data_ready_ch3 <= 1'b1;
end
if(bit_count == 9'h080)
begin
adc_channel_data_ch4 <= adc_channel_data_0;
adc_channel_data_ready_ch4 <= 1'b1;
end
if(bit_count == 9'h0A0)
begin
adc_channel_data_ch5 <= adc_channel_data_0;
adc_channel_data_ready_ch5 <= 1'b1;
end
if(bit_count == 9'h0C0)
begin
adc_channel_data_ch6 <= adc_channel_data_0;
adc_channel_data_ready_ch6 <= 1'b1;
end
if(bit_count == 9'h0E0)
begin
adc_channel_data_ch7 <= adc_channel_data_0;
adc_channel_data_ready_ch7 <= 1'b1;
end
if(bit_count == 9'h100)
begin
adc_channel_data_ch8 <= adc_channel_data_0;
adc_channel_data_ready_ch8 <= 1'b1;
end
end
if(buffer_write_start && !buffer_write_enable && adc_channel_data_ready_ch8)
begin
buffer_write_enable <= 1'b1;
if(adc_channel_data_ready_ch1)
begin
adc_channel_data_ready_ch1 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch1;
end
else if(adc_channel_data_ready_ch2)
begin
adc_channel_data_ready_ch2 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch2;
end
else if(adc_channel_data_ready_ch3)
begin
adc_channel_data_ready_ch3 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch3;
end
else if(adc_channel_data_ready_ch4)
begin
adc_channel_data_ready_ch4 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch4;
end
else if(adc_channel_data_ready_ch5)
begin
adc_channel_data_ready_ch5 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch5;
end
else if(adc_channel_data_ready_ch6)
begin
adc_channel_data_ready_ch6 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch6;
end
else if(adc_channel_data_ready_ch7)
begin
adc_channel_data_ready_ch7 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch7;
end
else
begin
adc_channel_data_ready_ch8 <= 1'b0;
adc_buffer_data <= adc_channel_data_ch8;
end
end
else
begin
buffer_write_enable <= 1'b0;
end
if(adc_data_ready_reg == 1'b1)
begin
bit_count <= 8'h00;
adc_channel_data_ready <= 1'b0;
if(sd_write_ready)
begin
if(!buffer_full)
buffer_write_start <= 1'b1;
else
buffer_write_start <= 1'b0;
end
end
else if((adc_clock_reg_1 == 1'b1) && (adc_clock_reg == 1'b0) && (bit_count < 9'h100))
begin
bit_count <= bit_count + 1;
adc_channel_data_0 <= {adc_channel_data_0[30:0],adc_data_0_reg};
adc_channel_data_1 <= {adc_channel_data_1[30:0],adc_data_1_reg};
if( (bit_count == 9'h01F) || (bit_count == 9'h03F) || (bit_count == 9'h05F) || (bit_count == 9'h07F)
|| (bit_count == 9'h09F) || (bit_count == 9'h0BF) || (bit_count == 9'h0DF) || (bit_count == 9'h0FF)
)
adc_channel_data_ready <= 1'b1;
end
else
adc_channel_data_ready <= 1'b0;
end
end
event_detect event_detect_ch1 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch1),
.adc_count(adc_channel_data_ch1[23:0]),
.event_detected(adc_event_detected_ch1));
event_detect event_detect_ch2 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch2),
.adc_count(adc_channel_data_ch2[23:0]),
.event_detected(adc_event_detected_ch2));
event_detect event_detect_ch3 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch3),
.adc_count(adc_channel_data_ch3[23:0]),
.event_detected(adc_event_detected_ch3));
event_detect event_detect_ch4 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch4),
.adc_count(adc_channel_data_ch4[23:0]),
.event_detected(adc_event_detected_ch4));
event_detect event_detect_ch5 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch5),
.adc_count(adc_channel_data_ch5[23:0]),
.event_detected(adc_event_detected_ch5));
event_detect event_detect_ch6 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch6),
.adc_count(adc_channel_data_ch6[23:0]),
.event_detected(adc_event_detected_ch6));
event_detect event_detect_ch7 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch7),
.adc_count(adc_channel_data_ch7[23:0]),
.event_detected(adc_event_detected_ch7));
event_detect event_detect_ch8 (
.clock(clock),
.reset(reset),
.adc_count_valid(adc_channel_data_ready_ch8),
.adc_count(adc_channel_data_ch8[23:0]),
.event_detected(adc_event_detected_ch8));
endmodule | 3 |
140,950 | data/full_repos/permissive/92914346/CPLD Firmware/event_detect.v | 92,914,346 | event_detect.v | v | 50 | 121 | [] | [] | [] | [(1, 49)] | null | null | 1: b'%Error: Cannot find file containing module: Firmware,data/full_repos/permissive/92914346\n ... Looked in:\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.v\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.sv\n Firmware,data/full_repos/permissive/92914346\n Firmware,data/full_repos/permissive/92914346.v\n Firmware,data/full_repos/permissive/92914346.sv\n obj_dir/Firmware,data/full_repos/permissive/92914346\n obj_dir/Firmware,data/full_repos/permissive/92914346.v\n obj_dir/Firmware,data/full_repos/permissive/92914346.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/92914346/CPLD\n%Error: Cannot find file containing module: Firmware/event_detect.v\n%Error: Exiting due to 3 error(s)\n' | 310,022 | module | module event_detect ( clock, reset, adc_count_valid, adc_count, event_detected);
input clock;
input reset;
input adc_count_valid;
input signed [23:0] adc_count;
output reg event_detected;
parameter NOISE_THRESHOLD = 25'sd16106;
reg adc_count_valid_reg;
reg signed [23:0] last_adc_count;
reg first_sample;
reg event_trigger;
always@(posedge clock or posedge reset)
begin
if(reset)
begin
adc_count_valid_reg <= 1'b0;
last_adc_count <= 1'b0;
first_sample <= 1'b1;
event_trigger <= 1'b0;
event_detected <= 1'b0;
end
else
begin
adc_count_valid_reg <= adc_count_valid;
if((adc_count_valid_reg == 1'b0) && (adc_count_valid == 1'b1))
begin
last_adc_count <= adc_count;
first_sample <= 1'b0;
if((first_sample == 1'b0) && (event_trigger == 1'b0) && ((adc_count - last_adc_count) > NOISE_THRESHOLD))
event_trigger <= 1'b1;
else if((event_trigger == 1'b1) && (adc_count < last_adc_count))
begin
event_trigger <= 1'b0;
event_detected <= 1'b1;
end
end
else
event_detected <= 1'b0;
end
end
endmodule | module event_detect ( clock, reset, adc_count_valid, adc_count, event_detected); |
input clock;
input reset;
input adc_count_valid;
input signed [23:0] adc_count;
output reg event_detected;
parameter NOISE_THRESHOLD = 25'sd16106;
reg adc_count_valid_reg;
reg signed [23:0] last_adc_count;
reg first_sample;
reg event_trigger;
always@(posedge clock or posedge reset)
begin
if(reset)
begin
adc_count_valid_reg <= 1'b0;
last_adc_count <= 1'b0;
first_sample <= 1'b1;
event_trigger <= 1'b0;
event_detected <= 1'b0;
end
else
begin
adc_count_valid_reg <= adc_count_valid;
if((adc_count_valid_reg == 1'b0) && (adc_count_valid == 1'b1))
begin
last_adc_count <= adc_count;
first_sample <= 1'b0;
if((first_sample == 1'b0) && (event_trigger == 1'b0) && ((adc_count - last_adc_count) > NOISE_THRESHOLD))
event_trigger <= 1'b1;
else if((event_trigger == 1'b1) && (adc_count < last_adc_count))
begin
event_trigger <= 1'b0;
event_detected <= 1'b1;
end
end
else
event_detected <= 1'b0;
end
end
endmodule | 3 |
140,953 | data/full_repos/permissive/92914346/CPLD Firmware/pseudo_adc.v | 92,914,346 | pseudo_adc.v | v | 63 | 105 | [] | [] | [] | [(1, 62)] | null | null | 1: b'%Error: Cannot find file containing module: Firmware,data/full_repos/permissive/92914346\n ... Looked in:\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.v\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.sv\n Firmware,data/full_repos/permissive/92914346\n Firmware,data/full_repos/permissive/92914346.v\n Firmware,data/full_repos/permissive/92914346.sv\n obj_dir/Firmware,data/full_repos/permissive/92914346\n obj_dir/Firmware,data/full_repos/permissive/92914346.v\n obj_dir/Firmware,data/full_repos/permissive/92914346.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/92914346/CPLD\n%Error: Cannot find file containing module: Firmware/pseudo_adc.v\n%Error: Exiting due to 3 error(s)\n' | 310,026 | module | module pseudo_adc ( clock, reset, source, adc_count);
input clock;
input reset;
inout source;
output [19:0] adc_count;
reg source_reg;
reg [21:0] count_sum;
reg [19:0] count_1;
reg [19:0] count_2;
reg [19:0] count_3;
reg [19:0] count_4;
reg [19:0] counter;
reg switch_direction;
assign source = (switch_direction) ? 1'b0 : 1'bz;
assign adc_count = count_sum[21:2];
always@(posedge clock or posedge reset)
begin
if(reset)
begin
source_reg <= 0;
count_sum <= 0;
count_1 <= 0;
count_2 <= 0;
count_3 <= 0;
count_4 <= 0;
counter <= 0;
switch_direction <= 1;
end
else
begin
source_reg <= source;
if((switch_direction == 1'b0) && (source_reg == 1'b1))
begin
count_sum <= {2'b00,count_1} + {2'b00,count_2} + {2'b00,count_3} + {2'b00,count_4};
count_1 <= counter;
count_2 <= count_1;
count_3 <= count_2;
count_4 <= count_3;
switch_direction <= 1'b1;
counter <= 0;
end
else if((switch_direction == 1'b1) && (counter == 20'h1FFF))
begin
switch_direction <= 1'b0;
counter <= 0;
end
else if((switch_direction == 1'b0) || (source_reg == 1'b0))
begin
if(counter < 20'hFFFFF)
counter <= counter + 1;
end
else
counter <= 0;
end
end
endmodule | module pseudo_adc ( clock, reset, source, adc_count); |
input clock;
input reset;
inout source;
output [19:0] adc_count;
reg source_reg;
reg [21:0] count_sum;
reg [19:0] count_1;
reg [19:0] count_2;
reg [19:0] count_3;
reg [19:0] count_4;
reg [19:0] counter;
reg switch_direction;
assign source = (switch_direction) ? 1'b0 : 1'bz;
assign adc_count = count_sum[21:2];
always@(posedge clock or posedge reset)
begin
if(reset)
begin
source_reg <= 0;
count_sum <= 0;
count_1 <= 0;
count_2 <= 0;
count_3 <= 0;
count_4 <= 0;
counter <= 0;
switch_direction <= 1;
end
else
begin
source_reg <= source;
if((switch_direction == 1'b0) && (source_reg == 1'b1))
begin
count_sum <= {2'b00,count_1} + {2'b00,count_2} + {2'b00,count_3} + {2'b00,count_4};
count_1 <= counter;
count_2 <= count_1;
count_3 <= count_2;
count_4 <= count_3;
switch_direction <= 1'b1;
counter <= 0;
end
else if((switch_direction == 1'b1) && (counter == 20'h1FFF))
begin
switch_direction <= 1'b0;
counter <= 0;
end
else if((switch_direction == 1'b0) || (source_reg == 1'b0))
begin
if(counter < 20'hFFFFF)
counter <= counter + 1;
end
else
counter <= 0;
end
end
endmodule | 3 |
140,955 | data/full_repos/permissive/92914346/CPLD Firmware/rs232_decoder_encoder.v | 92,914,346 | rs232_decoder_encoder.v | v | 134 | 95 | [] | [] | [] | [(1, 133)] | null | null | 1: b'%Error: Cannot find file containing module: Firmware,data/full_repos/permissive/92914346\n ... Looked in:\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.v\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.sv\n Firmware,data/full_repos/permissive/92914346\n Firmware,data/full_repos/permissive/92914346.v\n Firmware,data/full_repos/permissive/92914346.sv\n obj_dir/Firmware,data/full_repos/permissive/92914346\n obj_dir/Firmware,data/full_repos/permissive/92914346.v\n obj_dir/Firmware,data/full_repos/permissive/92914346.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/92914346/CPLD\n%Error: Cannot find file containing module: Firmware/rs232_decoder_encoder.v\n%Error: Exiting due to 3 error(s)\n' | 310,028 | module | module rs232_decoder_encoder ( clock, clock_4x, reset, rx, tx, rx_byte, rx_valid,
tx_buffer_empty, tx_buffer_byte, tx_buffer_read_enable);
input clock;
input clock_4x;
input reset;
input rx;
input tx_buffer_empty;
input [7:0] tx_buffer_byte;
output reg tx_buffer_read_enable;
output reg tx;
output reg [7:0] rx_byte;
output reg rx_valid;
reg [9:0] incoming_data;
reg [3:0] rx_count;
reg [1:0] rx_reg;
reg [2:0] rx_sample_count;
reg [2:0] rx_sample_time;
always@(posedge clock_4x or posedge reset)
begin
if(reset)
begin
rx_reg <= 1'b0;
rx_sample_time <= 3'h4;
rx_sample_count <= 3'h0;
rx_byte <= 8'h00;
rx_valid <= 1'b0;
incoming_data <= 10'h000;
rx_count <= 4'h0;
end
else
begin
rx_reg <= {rx_reg[0],rx};
if((rx_reg[1] != rx_reg[0]) || (rx_sample_count == rx_sample_time))
begin
rx_sample_count <= 3'h0;
if(rx_reg[1] != rx_reg[0])
rx_sample_time <= 3'h4;
else
rx_sample_time <= 3'h3;
incoming_data[9:0] <= {rx_reg[0], incoming_data[9:1]};
if((incoming_data[9] == 1'b0) && (incoming_data[8] == 1'b1) && (rx_count == 0))
begin
rx_count <= 1;
rx_valid <= 0;
end
else if(rx_count == 9)
begin
rx_count <= 0;
rx_byte <= incoming_data[8:1];
rx_valid <= 1;
end
else if(rx_count > 0)
begin
rx_count <= rx_count + 1;
rx_valid <= 0;
end
else
rx_valid <= 0;
end
else
rx_sample_count <= rx_sample_count + 3'h1;
end
end
reg [9:0] outgoing_data;
reg [3:0] tx_count;
reg tx_start;
reg first_read;
always@(posedge clock or posedge reset)
begin
if(reset)
begin
tx <= 1'b1;
outgoing_data <= 10'h3FF;
tx_count <= 0;
tx_start <= 0;
tx_buffer_read_enable <= 0;
first_read <= 1;
end
else
begin
tx <= outgoing_data[0];
if((first_read == 1'b1) && (tx_buffer_empty == 0))
begin
tx_buffer_read_enable <= 1;
first_read <= 0;
end
else if((tx_count == 0) && (tx_start == 0) && (tx_buffer_empty == 0))
begin
tx_start <= 1;
tx_buffer_read_enable <= 1;
end
else
begin
tx_start <= 0;
tx_buffer_read_enable <= 0;
end
if((tx_start == 1'b1) && (tx_count == 0))
begin
outgoing_data <= {1'b1, tx_buffer_byte, 1'b0};
tx_count <= 1;
end
else if(tx_count == 10)
begin
outgoing_data <= 10'h3FF;
tx_count <= 0;
end
else if(tx_count > 0)
begin
outgoing_data <= {1'b1, outgoing_data[9:1]};
tx_count <= tx_count + 1;
end
end
end
endmodule | module rs232_decoder_encoder ( clock, clock_4x, reset, rx, tx, rx_byte, rx_valid,
tx_buffer_empty, tx_buffer_byte, tx_buffer_read_enable); |
input clock;
input clock_4x;
input reset;
input rx;
input tx_buffer_empty;
input [7:0] tx_buffer_byte;
output reg tx_buffer_read_enable;
output reg tx;
output reg [7:0] rx_byte;
output reg rx_valid;
reg [9:0] incoming_data;
reg [3:0] rx_count;
reg [1:0] rx_reg;
reg [2:0] rx_sample_count;
reg [2:0] rx_sample_time;
always@(posedge clock_4x or posedge reset)
begin
if(reset)
begin
rx_reg <= 1'b0;
rx_sample_time <= 3'h4;
rx_sample_count <= 3'h0;
rx_byte <= 8'h00;
rx_valid <= 1'b0;
incoming_data <= 10'h000;
rx_count <= 4'h0;
end
else
begin
rx_reg <= {rx_reg[0],rx};
if((rx_reg[1] != rx_reg[0]) || (rx_sample_count == rx_sample_time))
begin
rx_sample_count <= 3'h0;
if(rx_reg[1] != rx_reg[0])
rx_sample_time <= 3'h4;
else
rx_sample_time <= 3'h3;
incoming_data[9:0] <= {rx_reg[0], incoming_data[9:1]};
if((incoming_data[9] == 1'b0) && (incoming_data[8] == 1'b1) && (rx_count == 0))
begin
rx_count <= 1;
rx_valid <= 0;
end
else if(rx_count == 9)
begin
rx_count <= 0;
rx_byte <= incoming_data[8:1];
rx_valid <= 1;
end
else if(rx_count > 0)
begin
rx_count <= rx_count + 1;
rx_valid <= 0;
end
else
rx_valid <= 0;
end
else
rx_sample_count <= rx_sample_count + 3'h1;
end
end
reg [9:0] outgoing_data;
reg [3:0] tx_count;
reg tx_start;
reg first_read;
always@(posedge clock or posedge reset)
begin
if(reset)
begin
tx <= 1'b1;
outgoing_data <= 10'h3FF;
tx_count <= 0;
tx_start <= 0;
tx_buffer_read_enable <= 0;
first_read <= 1;
end
else
begin
tx <= outgoing_data[0];
if((first_read == 1'b1) && (tx_buffer_empty == 0))
begin
tx_buffer_read_enable <= 1;
first_read <= 0;
end
else if((tx_count == 0) && (tx_start == 0) && (tx_buffer_empty == 0))
begin
tx_start <= 1;
tx_buffer_read_enable <= 1;
end
else
begin
tx_start <= 0;
tx_buffer_read_enable <= 0;
end
if((tx_start == 1'b1) && (tx_count == 0))
begin
outgoing_data <= {1'b1, tx_buffer_byte, 1'b0};
tx_count <= 1;
end
else if(tx_count == 10)
begin
outgoing_data <= 10'h3FF;
tx_count <= 0;
end
else if(tx_count > 0)
begin
outgoing_data <= {1'b1, outgoing_data[9:1]};
tx_count <= tx_count + 1;
end
end
end
endmodule | 3 |
140,958 | data/full_repos/permissive/92914346/CPLD Firmware/top.v | 92,914,346 | top.v | v | 797 | 154 | [] | [] | [] | null | line:80: before: "." | null | 1: b'%Error: Cannot find file containing module: Firmware,data/full_repos/permissive/92914346\n ... Looked in:\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.v\n data/full_repos/permissive/92914346/CPLD/Firmware,data/full_repos/permissive/92914346.sv\n Firmware,data/full_repos/permissive/92914346\n Firmware,data/full_repos/permissive/92914346.v\n Firmware,data/full_repos/permissive/92914346.sv\n obj_dir/Firmware,data/full_repos/permissive/92914346\n obj_dir/Firmware,data/full_repos/permissive/92914346.v\n obj_dir/Firmware,data/full_repos/permissive/92914346.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/92914346/CPLD\n%Error: Cannot find file containing module: Firmware/top.v\n%Error: Exiting due to 3 error(s)\n' | 310,032 | module | module top ( stdby_in, stdby1, switch0,
regulator_12v_en, regulator_3_3v_sd_en, regulator_3_3v_adc_en,
spi_clk, spi_miso, spi_mosi, spi_csn0,
spi_csn1, spi_csn2, spi_csn3, spi_csn4,
adc_drdy, adc_clock, adc_data_0, adc_data_1, adc_data_2, adc_data_3,
rs232_rx, rs232_tx,
temp_rxtx,
therm_en1, therm_en2, therm_en3, therm_en4,
regulator_main_source, regulator_12_source, regulator_5_source, regulator_3_3_main_source, regulator_3_3_adc_source, regulator_3_3_sd_source,
test_a, test_b, test_c, test_d, test_e, test_f);
input stdby_in;
output stdby1;
input switch0;
output regulator_12v_en, regulator_3_3v_sd_en, regulator_3_3v_adc_en;
output spi_clk, spi_mosi;
input spi_miso;
output spi_csn0, spi_csn1, spi_csn2, spi_csn3, spi_csn4;
input adc_drdy, adc_clock, adc_data_0, adc_data_1, adc_data_2, adc_data_3;
input rs232_rx;
output rs232_tx;
inout temp_rxtx;
output reg therm_en1, therm_en2, therm_en3, therm_en4;
inout regulator_main_source, regulator_12_source, regulator_5_source, regulator_3_3_main_source, regulator_3_3_adc_source, regulator_3_3_sd_source;
output test_a, test_b, test_c, test_d, test_e, test_f;
wire clock_126_000;
wire clock_42_0000;
wire clock_00_0192;
reg clock_00_0048;
reg switch0_db;
wire clock_lock;
wire rs232_reset;
wire reset = (~switch0_db) | (~clock_lock) | rs232_reset;
wire stby_flag ;
wire [5:0] spi_csn;
wire sd_cs;
assign spi_csn0 = spi_csn[0];
assign spi_csn1 = spi_csn[1];
assign spi_csn2 = spi_csn[2];
assign spi_csn3 = reset ? 1'b1: spi_csn[3];
assign spi_csn4 = reset ? 1'b1: spi_csn[4];
wire test_signal_120ns;
wire temp_tx_switch;
wire regulator_3_3v_adc_en_command_processor;
wire regulator_3_3v_sd_en_command_processor;
wire regulator_3_3v_adc_en_spi_controller;
wire regulator_3_3v_sd_en_spi_controller;
assign regulator_3_3v_adc_en = regulator_3_3v_adc_en_command_processor | regulator_3_3v_adc_en_spi_controller;
assign regulator_3_3v_sd_en = regulator_3_3v_sd_en_command_processor | regulator_3_3v_sd_en_spi_controller;
defparam OSCH_inst.NOM_FREQ = "7";
OSCH OSCH_inst (
.STDBY(1'b0),
.OSC(osc_clk ),
.SEDSTDBY());
pll pll_inst (
.CLKI(osc_clk ),
.LOCK(clock_lock),
.CLKOP(clock_126_000 ),
.CLKOS(clock_42_0000 ),
.CLKOS2(clock_00_0192 ));
pwr_cntrllr pcm1 (
.USERSTDBY(stdby_in ),
.CLRFLAG(stby_flag ),
.CFGSTDBY(1'b0 ),
.STDBY(stdby1 ),
.SFLAG(stby_flag ));
reg test_signal_120ns_reg;
reg [7:0] test_signal_counter;
assign test_signal_120ns = (test_signal_120ns_reg) ? 1'b1 : 1'bz;
always@(posedge clock_42_0000 or posedge reset)
begin
if(reset)
begin
test_signal_120ns_reg <= 0;
test_signal_counter <= 0;
end
else
begin
test_signal_counter <= test_signal_counter + 1;
if(test_signal_counter <= 10)
test_signal_120ns_reg <= 1'b1;
else
test_signal_120ns_reg <= 1'b0;
end
end
wire buffer_full;
reg buffer_full_latch;
always@(posedge clock_42_0000 or posedge reset)
begin
if(reset)
buffer_full_latch <= 1'b0;
else
if(buffer_full == 1'b1)
buffer_full_latch <= 1'b1;
end
wire adc_init;
wire sd_init_1;
wire sd_init_2;
wire sd_write_error;
reg [1:0] clk_div;
wire reset_c = ~clock_lock;
always@(posedge clock_00_0192 or posedge reset_c)
begin
if(reset_c)
begin
clk_div <= 2'b00;
clock_00_0048 <= 1'b0;
end
else
begin
clk_div <= clk_div + 2'b01;
clock_00_0048 <= clk_div[1];
end
end
reg temp_sample_pulse;
reg [13:0] temp_clock_counter;
always@(posedge clock_00_0048 or posedge reset_c)
begin
if(reset_c)
begin
temp_sample_pulse <= 1'b0;
temp_clock_counter <= 0;
end
else
begin
if(temp_clock_counter == 14'h2580)
begin
temp_sample_pulse <= 1'b1;
temp_clock_counter <= 0;
end
else
begin
temp_sample_pulse <= 1'b0;
temp_clock_counter <= temp_clock_counter + 1;
end
end
end
reg ms_pulse;
reg [16:0] ms_counter;
wire therm_reset_control;
reg therm_reset_control_reg;
reg therm_reset;
always@(posedge clock_42_0000 or posedge reset_c)
begin
if(reset_c)
begin
ms_pulse <= 1'b0;
ms_counter <= 0;
therm_reset_control_reg <= 1'b0;
therm_reset <= 1'b0;
end
else
begin
if(therm_reset_control)
therm_reset_control_reg <= 1'b1;
if(ms_counter == 17'd42000)
begin
ms_pulse <= 1'b1;
ms_counter <= 0;
if(therm_reset_control_reg)
begin
therm_reset_control_reg <= 1'b0;
therm_reset <= 1'b1;
end
else
therm_reset <= 1'b0;
end
else
begin
ms_pulse <= 1'b0;
ms_counter <= ms_counter + 1;
end
end
end
reg [3:0] debounce_counter;
always@(posedge clock_00_0048 or posedge reset_c)
begin
if(reset_c)
begin
switch0_db <= 1'b0;
debounce_counter <= 4'h0;
end
else
begin
if(debounce_counter == 4'hF)
switch0_db <= switch0;
if((switch0_db != switch0) && (debounce_counter != 4'hF))
debounce_counter <= debounce_counter + 1;
else
debounce_counter <= 4'h0;
end
end
wire [19:0] regulator_main_count;
wire [19:0] regulator_12_count;
wire [19:0] regulator_5_count;
wire [19:0] regulator_3_3_main_count;
wire [19:0] regulator_3_3_adc_count;
wire [19:0] regulator_3_3_sd_count;
pseudo_adc pseudo_adc_regulator_main (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_main_source),
.adc_count(regulator_main_count));
pseudo_adc pseudo_adc_regulator_12 (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_12_source),
.adc_count(regulator_12_count));
pseudo_adc pseudo_adc_regulator_5 (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_5_source),
.adc_count(regulator_5_count));
pseudo_adc pseudo_adc_regulator_3_3_main (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_3_3_main_source),
.adc_count(regulator_3_3_main_count));
pseudo_adc pseudo_adc_regulator_3_3_adc (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_3_3_adc_source),
.adc_count(regulator_3_3_adc_count));
pseudo_adc pseudo_adc_regulator_3_3_sd (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_3_3_sd_source),
.adc_count(regulator_3_3_sd_count));
wire wb_cyc;
wire wb_stb;
wire wb_we;
wire [7:0] wb_adr;
wire [7:0] wb_dat_i;
wire [7:0] wb_dat_o;
wire wb_ack;
efb efb_inst (
.wb_clk_i(clock_126_000),
.wb_rst_i(reset),
.wb_cyc_i(wb_cyc),
.wb_stb_i(wb_stb),
.wb_we_i(wb_we),
.wb_adr_i(wb_adr),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_ack_o(wb_ack),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_scsn(1'b1),
.spi_csn(spi_csn)
);
wire adc_sample_start;
wire [31:0] adc_buffer_data;
wire [31:0] adc_data_ch1;
wire [31:0] adc_data_ch2;
wire [31:0] adc_data_ch3;
wire [31:0] adc_data_ch4;
wire [31:0] adc_data_ch5;
wire [31:0] adc_data_ch6;
wire [31:0] adc_data_ch7;
wire [31:0] adc_data_ch8;
wire [31:0] buffer_data;
wire buffer_write_enable;
wire buffer_write_enable_adc;
wire buffer_read_enable;
wire buffer_empty;
wire buffer_almost_empty;
wire buffer_almost_full;
wire system_idle;
wire sd_busy;
wire sd_write_ready;
parameter MAX_BYTES = 78;
wire [MAX_BYTES*8-1:0] record_bytes;
wire [7:0] record_num_bytes;
wire record_valid;
wire adc_disable;
wire sd_disable;
spi_controller #(.MAX_BYTES(MAX_BYTES)) spi_controller_inst (
.clock_126(clock_126_000 ),
.clock(clock_42_0000 ),
.reset(reset ),
.wb_cyc(wb_cyc),
.wb_stb(wb_stb),
.wb_we(wb_we),
.wb_adr(wb_adr),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_ack(wb_ack),
.adc_sample_start(adc_sample_start),
.buffer_read_enable(buffer_read_enable),
.buffer_data(buffer_data),
.buffer_ready(!buffer_almost_empty),
.adc_disable(adc_disable),
.sd_disable(sd_disable),
.adc_init(adc_init),
.sd_init_1(sd_init_1),
.sd_init_2(sd_init_2),
.sd_write_error(sd_write_error),
.sd_write_ready(sd_write_ready),
.sd_busy(sd_busy),
.ms_pulse(ms_pulse),
.regulator_3_3v_adc_en(regulator_3_3v_adc_en_spi_controller),
.regulator_3_3v_sd_en(regulator_3_3v_sd_en_spi_controller),
.record_bytes(record_bytes),
.record_num_bytes(record_num_bytes),
.record_valid(record_valid));
wire adc_event_detected_ch1;
wire adc_event_detected_ch2;
wire adc_event_detected_ch3;
wire adc_event_detected_ch4;
wire adc_event_detected_ch5;
wire adc_event_detected_ch6;
wire adc_event_detected_ch7;
wire adc_event_detected_ch8;
adc_serial_interface adc_serial_interface_inst (
.clock(clock_42_0000 ),
.reset(reset ),
.start(adc_sample_start),
.sd_write_ready(sd_write_ready),
.adc_data_ready(adc_drdy),
.adc_clock(adc_clock),
.adc_data_0(adc_data_0),
.adc_data_1(adc_data_1),
.adc_channel_data_ch1(adc_data_ch1),
.adc_channel_data_ch2(adc_data_ch2),
.adc_channel_data_ch3(adc_data_ch3),
.adc_channel_data_ch4(adc_data_ch4),
.adc_channel_data_ch5(adc_data_ch5),
.adc_channel_data_ch6(adc_data_ch6),
.adc_channel_data_ch7(adc_data_ch7),
.adc_channel_data_ch8(adc_data_ch8),
.adc_event_detected_ch1(adc_event_detected_ch1),
.adc_event_detected_ch2(adc_event_detected_ch2),
.adc_event_detected_ch3(adc_event_detected_ch3),
.adc_event_detected_ch4(adc_event_detected_ch4),
.adc_event_detected_ch5(adc_event_detected_ch5),
.adc_event_detected_ch6(adc_event_detected_ch6),
.adc_event_detected_ch7(adc_event_detected_ch7),
.adc_event_detected_ch8(adc_event_detected_ch8),
.adc_buffer_data(adc_buffer_data),
.buffer_write_enable(buffer_write_enable_adc),
.buffer_full(buffer_almost_full));
assign buffer_write_enable = (system_idle) ? 1'b0 : buffer_write_enable_adc;
fifo_buffer fifo_buffer_inst (
.Data(adc_buffer_data),
.WrClock(clock_42_0000),
.RdClock(clock_42_0000),
.WrEn(buffer_write_enable),
.RdEn(buffer_read_enable),
.Reset(reset),
.RPReset(reset),
.Q(buffer_data),
.Empty(buffer_empty),
.AlmostEmpty(buffer_almost_empty),
.Full(buffer_full),
.AlmostFull(buffer_almost_full)
);
reg [5:0] temp_pwm_count;
wire [5:0] therm_pwm1;
wire [5:0] therm_pwm2;
wire [5:0] therm_pwm3;
wire [5:0] therm_pwm4;
wire [5:0] therm_controller_pwm1;
wire [5:0] therm_controller_pwm2;
wire [5:0] therm_controller_pwm3;
wire [5:0] therm_controller_pwm4;
reg [5:0] therm_override_pwm1;
reg [5:0] therm_override_pwm2;
reg [5:0] therm_override_pwm3;
reg [5:0] therm_override_pwm4;
wire therm_override_1;
wire therm_override_2;
wire therm_override_3;
wire therm_override_4;
wire therm_increment_1;
wire therm_increment_2;
wire therm_increment_3;
wire therm_increment_4;
wire therm_decrement_1;
wire therm_decrement_2;
wire therm_decrement_3;
wire therm_decrement_4;
reg therm_increment_1_reg;
reg therm_increment_2_reg;
reg therm_increment_3_reg;
reg therm_increment_4_reg;
reg therm_decrement_1_reg;
reg therm_decrement_2_reg;
reg therm_decrement_3_reg;
reg therm_decrement_4_reg;
assign therm_pwm1 = (therm_override_1) ? therm_override_pwm1 : therm_controller_pwm1;
assign therm_pwm2 = (therm_override_2) ? therm_override_pwm2 : therm_controller_pwm2;
assign therm_pwm3 = (therm_override_3) ? therm_override_pwm3 : therm_controller_pwm3;
assign therm_pwm4 = (therm_override_4) ? therm_override_pwm4 : therm_controller_pwm4;
always@(posedge clock_00_0048 or posedge reset)
begin
if(reset)
begin
temp_pwm_count <= 6'h00;
therm_en1 <= 1'b0;
therm_en2 <= 1'b0;
therm_en3 <= 1'b0;
therm_en4 <= 1'b0;
therm_override_pwm1 <= 0;
therm_override_pwm2 <= 0;
therm_override_pwm3 <= 0;
therm_override_pwm4 <= 0;
therm_increment_1_reg <= 1'b0;
therm_increment_2_reg <= 1'b0;
therm_increment_3_reg <= 1'b0;
therm_increment_4_reg <= 1'b0;
therm_decrement_1_reg <= 1'b0;
therm_decrement_2_reg <= 1'b0;
therm_decrement_3_reg <= 1'b0;
therm_decrement_4_reg <= 1'b0;
end
else
begin
therm_increment_1_reg <= therm_increment_1;
therm_increment_2_reg <= therm_increment_2;
therm_increment_3_reg <= therm_increment_3;
therm_increment_4_reg <= therm_increment_4;
therm_decrement_1_reg <= therm_decrement_1;
therm_decrement_2_reg <= therm_decrement_2;
therm_decrement_3_reg <= therm_decrement_3;
therm_decrement_4_reg <= therm_decrement_4;
if(~therm_increment_1_reg && therm_increment_1)
begin
if(therm_override_pwm1 <= 6'h39)
therm_override_pwm1 <= therm_override_pwm1 + 6;
else
therm_override_pwm1 <= 6'h3F;
end
else if(~therm_decrement_1_reg && therm_decrement_1)
begin
if(therm_override_pwm1 >= 6'h6)
therm_override_pwm1 <= therm_override_pwm1 - 6;
else
therm_override_pwm1 <= 6'h00;
end
if(~therm_increment_2_reg && therm_increment_2)
begin
if(therm_override_pwm2 <= 6'h39)
therm_override_pwm2 <= therm_override_pwm2 + 6;
else
therm_override_pwm2 <= 6'h3F;
end
else if(~therm_decrement_2_reg && therm_decrement_2)
begin
if(therm_override_pwm2 >= 6'h6)
therm_override_pwm2 <= therm_override_pwm2 - 6;
else
therm_override_pwm2 <= 6'h00;
end
if(~therm_increment_3_reg && therm_increment_3)
begin
if(therm_override_pwm3 <= 6'h39)
therm_override_pwm3 <= therm_override_pwm3 + 6;
else
therm_override_pwm3 <= 6'h3F;
end
else if(~therm_decrement_3_reg && therm_decrement_3)
begin
if(therm_override_pwm3 >= 6'h6)
therm_override_pwm3 <= therm_override_pwm3 - 6;
else
therm_override_pwm3 <= 6'h00;
end
if(~therm_increment_4_reg && therm_increment_4)
begin
if(therm_override_pwm4 <= 6'h39)
therm_override_pwm4 <= therm_override_pwm4 + 6;
else
therm_override_pwm4 <= 6'h3F;
end
else if(~therm_decrement_4_reg && therm_decrement_4)
begin
if(therm_override_pwm4 >= 6'h6)
therm_override_pwm4 <= therm_override_pwm4 - 6;
else
therm_override_pwm4 <= 6'h00;
end
temp_pwm_count <= temp_pwm_count + 1;
if((therm_pwm1 != 6'h00) && (temp_pwm_count <= therm_pwm1))
therm_en1 <= 1'b1;
else
therm_en1 <= 1'b0;
if((therm_pwm2 != 6'h00) && (temp_pwm_count <= therm_pwm2))
therm_en2 <= 1'b1;
else
therm_en2 <= 1'b0;
if((therm_pwm3 != 6'h00) && (temp_pwm_count <= therm_pwm3))
therm_en3 <= 1'b1;
else
therm_en3 <= 1'b0;
if((therm_pwm4 != 6'h00) && (temp_pwm_count <= therm_pwm4))
therm_en4 <= 1'b1;
else
therm_en4 <= 1'b0;
end
end
parameter TEMP_MAX_BYTES = 5;
wire [TEMP_MAX_BYTES*8-1:0] temp_tx_bytes;
wire [3:0] temp_tx_num_bytes;
wire temp_tx_valid;
wire [7:0] temp_rx_byte;
wire temp_rx_valid;
temp_decoder_encoder temp_decoder_encoder_inst(
.clock(clock_00_0048 ),
.clock_4x(clock_00_0192),
.reset(reset | therm_reset),
.rxtx(temp_rxtx ),
.rx_valid(temp_rx_valid),
.rx_byte(temp_rx_byte),
.tx_bytes(temp_tx_bytes),
.tx_num_bytes(temp_tx_num_bytes),
.tx_valid(temp_tx_valid),
.tx_switch(temp_tx_switch));
wire [15:0] temp1_value;
wire [15:0] temp2_value;
wire [15:0] temp3_value;
wire [15:0] temp4_value;
thermal_controller thermal_controller_inst(
.clock(clock_42_0000 ),
.reset(reset | therm_reset),
.temp_sample_pulse(temp_sample_pulse),
.temp_rx_valid(temp_rx_valid),
.temp_rx_byte(temp_rx_byte),
.temp_tx_bytes(temp_tx_bytes),
.temp_tx_num_bytes(temp_tx_num_bytes),
.temp_tx_valid(temp_tx_valid),
.temp1_value(temp1_value),
.temp2_value(temp2_value),
.temp3_value(temp3_value),
.temp4_value(temp4_value),
.therm_pwm1(therm_controller_pwm1),
.therm_pwm2(therm_controller_pwm2),
.therm_pwm3(therm_controller_pwm3),
.therm_pwm4(therm_controller_pwm4)
);
wire [7:0] rs232_rx_byte;
wire rs232_rx_valid;
wire [7:0] rs232_rx_command_valid;
wire rs232_buffer_write_enable;
wire [7:0] rs232_record_byte;
wire rs232_buffer_read_enable;
wire [7:0] rs232_tx_buffer_byte;
wire rs232_buffer_empty;
wire rs232_buffer_full;
rs232_decoder_encoder rs232_decoder_encoder_inst(
.clock(clock_00_0048 ),
.clock_4x(clock_00_0192),
.reset(reset ),
.rx(rs232_rx ),
.tx(rs232_tx ),
.rx_valid(rs232_rx_valid),
.rx_byte(rs232_rx_byte),
.tx_buffer_empty(rs232_buffer_empty),
.tx_buffer_read_enable(rs232_buffer_read_enable),
.tx_buffer_byte(rs232_tx_buffer_byte)
);
fifo_buffer_rs232_tx fifo_buffer_rs232_inst (
.Data(rs232_record_byte),
.WrClock(clock_42_0000),
.RdClock(clock_00_0048),
.WrEn(rs232_buffer_write_enable),
.RdEn(rs232_buffer_read_enable),
.Reset(reset),
.RPReset(reset),
.Q(rs232_tx_buffer_byte),
.Empty(rs232_buffer_empty),
.Full(rs232_buffer_full)
);
command_processor #(.MAX_BYTES(MAX_BYTES)) command_processor_inst(
.clock(clock_42_0000 ),
.reset(reset ),
.regulator_12v_en(regulator_12v_en),
.regulator_3_3v_sd_en(regulator_3_3v_sd_en_command_processor),
.regulator_3_3v_adc_en(regulator_3_3v_adc_en_command_processor),
.regulator_12v_en_sup(regulator_12v_en),
.regulator_3_3v_sd_en_sup(regulator_3_3v_sd_en),
.regulator_3_3v_adc_en_sup(regulator_3_3v_adc_en),
.ms_pulse(ms_pulse),
.rs232_reset(rs232_reset),
.rs232_rx_valid(rs232_rx_valid),
.rs232_rx_byte(rs232_rx_byte),
.command_valid(rs232_rx_command_valid),
.rs232_buffer_full(rs232_buffer_full),
.rs232_buffer_write_enable(rs232_buffer_write_enable),
.rs232_record_byte(rs232_record_byte),
.rs232_tx_bytes(record_bytes),
.rs232_tx_byte_count(record_num_bytes),
.rs232_tx_valid(record_valid),
.temp1_value(temp1_value),
.temp2_value(temp2_value),
.temp3_value(temp3_value),
.temp4_value(temp4_value),
.therm_pwm1(therm_pwm1),
.therm_pwm2(therm_pwm2),
.therm_pwm3(therm_pwm3),
.therm_pwm4(therm_pwm4),
.therm_override_1(therm_override_1),
.therm_override_2(therm_override_2),
.therm_override_3(therm_override_3),
.therm_override_4(therm_override_4),
.therm_increment_1(therm_increment_1),
.therm_increment_2(therm_increment_2),
.therm_increment_3(therm_increment_3),
.therm_increment_4(therm_increment_4),
.therm_decrement_1(therm_decrement_1),
.therm_decrement_2(therm_decrement_2),
.therm_decrement_3(therm_decrement_3),
.therm_decrement_4(therm_decrement_4),
.therm_reset(therm_reset_control),
.system_idle(system_idle),
.adc_disable(adc_disable),
.sd_disable(sd_disable),
.adc_init(adc_init),
.sd_init_1(sd_init_1),
.sd_init_2(sd_init_2),
.sd_write_ready(sd_write_ready),
.buffer_full(buffer_full),
.buffer_full_latch(buffer_full_latch),
.adc_data_ch1(adc_data_ch1),
.adc_data_ch2(adc_data_ch2),
.adc_data_ch3(adc_data_ch3),
.adc_data_ch4(adc_data_ch4),
.adc_data_ch5(adc_data_ch5),
.adc_data_ch6(adc_data_ch6),
.adc_data_ch7(adc_data_ch7),
.adc_data_ch8(adc_data_ch8),
.adc_event_detected_ch1(adc_event_detected_ch1),
.adc_event_detected_ch2(adc_event_detected_ch2),
.adc_event_detected_ch3(adc_event_detected_ch3),
.adc_event_detected_ch4(adc_event_detected_ch4),
.adc_event_detected_ch5(adc_event_detected_ch5),
.adc_event_detected_ch6(adc_event_detected_ch6),
.adc_event_detected_ch7(adc_event_detected_ch7),
.adc_event_detected_ch8(adc_event_detected_ch8),
.regulator_main_count(regulator_main_count),
.regulator_12_count(regulator_12_count),
.regulator_5_count(regulator_5_count),
.regulator_3_3_main_count(regulator_3_3_main_count),
.regulator_3_3_adc_count(regulator_3_3_adc_count),
.regulator_3_3_sd_count(regulator_3_3_sd_count)
);
assign test_a = test_signal_120ns;
assign test_b = clock_00_0048;
assign test_c = therm_en1;
assign test_d = buffer_full;
assign test_e = sd_busy;
assign test_f = ms_pulse;
endmodule | module top ( stdby_in, stdby1, switch0,
regulator_12v_en, regulator_3_3v_sd_en, regulator_3_3v_adc_en,
spi_clk, spi_miso, spi_mosi, spi_csn0,
spi_csn1, spi_csn2, spi_csn3, spi_csn4,
adc_drdy, adc_clock, adc_data_0, adc_data_1, adc_data_2, adc_data_3,
rs232_rx, rs232_tx,
temp_rxtx,
therm_en1, therm_en2, therm_en3, therm_en4,
regulator_main_source, regulator_12_source, regulator_5_source, regulator_3_3_main_source, regulator_3_3_adc_source, regulator_3_3_sd_source,
test_a, test_b, test_c, test_d, test_e, test_f); |
input stdby_in;
output stdby1;
input switch0;
output regulator_12v_en, regulator_3_3v_sd_en, regulator_3_3v_adc_en;
output spi_clk, spi_mosi;
input spi_miso;
output spi_csn0, spi_csn1, spi_csn2, spi_csn3, spi_csn4;
input adc_drdy, adc_clock, adc_data_0, adc_data_1, adc_data_2, adc_data_3;
input rs232_rx;
output rs232_tx;
inout temp_rxtx;
output reg therm_en1, therm_en2, therm_en3, therm_en4;
inout regulator_main_source, regulator_12_source, regulator_5_source, regulator_3_3_main_source, regulator_3_3_adc_source, regulator_3_3_sd_source;
output test_a, test_b, test_c, test_d, test_e, test_f;
wire clock_126_000;
wire clock_42_0000;
wire clock_00_0192;
reg clock_00_0048;
reg switch0_db;
wire clock_lock;
wire rs232_reset;
wire reset = (~switch0_db) | (~clock_lock) | rs232_reset;
wire stby_flag ;
wire [5:0] spi_csn;
wire sd_cs;
assign spi_csn0 = spi_csn[0];
assign spi_csn1 = spi_csn[1];
assign spi_csn2 = spi_csn[2];
assign spi_csn3 = reset ? 1'b1: spi_csn[3];
assign spi_csn4 = reset ? 1'b1: spi_csn[4];
wire test_signal_120ns;
wire temp_tx_switch;
wire regulator_3_3v_adc_en_command_processor;
wire regulator_3_3v_sd_en_command_processor;
wire regulator_3_3v_adc_en_spi_controller;
wire regulator_3_3v_sd_en_spi_controller;
assign regulator_3_3v_adc_en = regulator_3_3v_adc_en_command_processor | regulator_3_3v_adc_en_spi_controller;
assign regulator_3_3v_sd_en = regulator_3_3v_sd_en_command_processor | regulator_3_3v_sd_en_spi_controller;
defparam OSCH_inst.NOM_FREQ = "7";
OSCH OSCH_inst (
.STDBY(1'b0),
.OSC(osc_clk ),
.SEDSTDBY());
pll pll_inst (
.CLKI(osc_clk ),
.LOCK(clock_lock),
.CLKOP(clock_126_000 ),
.CLKOS(clock_42_0000 ),
.CLKOS2(clock_00_0192 ));
pwr_cntrllr pcm1 (
.USERSTDBY(stdby_in ),
.CLRFLAG(stby_flag ),
.CFGSTDBY(1'b0 ),
.STDBY(stdby1 ),
.SFLAG(stby_flag ));
reg test_signal_120ns_reg;
reg [7:0] test_signal_counter;
assign test_signal_120ns = (test_signal_120ns_reg) ? 1'b1 : 1'bz;
always@(posedge clock_42_0000 or posedge reset)
begin
if(reset)
begin
test_signal_120ns_reg <= 0;
test_signal_counter <= 0;
end
else
begin
test_signal_counter <= test_signal_counter + 1;
if(test_signal_counter <= 10)
test_signal_120ns_reg <= 1'b1;
else
test_signal_120ns_reg <= 1'b0;
end
end
wire buffer_full;
reg buffer_full_latch;
always@(posedge clock_42_0000 or posedge reset)
begin
if(reset)
buffer_full_latch <= 1'b0;
else
if(buffer_full == 1'b1)
buffer_full_latch <= 1'b1;
end
wire adc_init;
wire sd_init_1;
wire sd_init_2;
wire sd_write_error;
reg [1:0] clk_div;
wire reset_c = ~clock_lock;
always@(posedge clock_00_0192 or posedge reset_c)
begin
if(reset_c)
begin
clk_div <= 2'b00;
clock_00_0048 <= 1'b0;
end
else
begin
clk_div <= clk_div + 2'b01;
clock_00_0048 <= clk_div[1];
end
end
reg temp_sample_pulse;
reg [13:0] temp_clock_counter;
always@(posedge clock_00_0048 or posedge reset_c)
begin
if(reset_c)
begin
temp_sample_pulse <= 1'b0;
temp_clock_counter <= 0;
end
else
begin
if(temp_clock_counter == 14'h2580)
begin
temp_sample_pulse <= 1'b1;
temp_clock_counter <= 0;
end
else
begin
temp_sample_pulse <= 1'b0;
temp_clock_counter <= temp_clock_counter + 1;
end
end
end
reg ms_pulse;
reg [16:0] ms_counter;
wire therm_reset_control;
reg therm_reset_control_reg;
reg therm_reset;
always@(posedge clock_42_0000 or posedge reset_c)
begin
if(reset_c)
begin
ms_pulse <= 1'b0;
ms_counter <= 0;
therm_reset_control_reg <= 1'b0;
therm_reset <= 1'b0;
end
else
begin
if(therm_reset_control)
therm_reset_control_reg <= 1'b1;
if(ms_counter == 17'd42000)
begin
ms_pulse <= 1'b1;
ms_counter <= 0;
if(therm_reset_control_reg)
begin
therm_reset_control_reg <= 1'b0;
therm_reset <= 1'b1;
end
else
therm_reset <= 1'b0;
end
else
begin
ms_pulse <= 1'b0;
ms_counter <= ms_counter + 1;
end
end
end
reg [3:0] debounce_counter;
always@(posedge clock_00_0048 or posedge reset_c)
begin
if(reset_c)
begin
switch0_db <= 1'b0;
debounce_counter <= 4'h0;
end
else
begin
if(debounce_counter == 4'hF)
switch0_db <= switch0;
if((switch0_db != switch0) && (debounce_counter != 4'hF))
debounce_counter <= debounce_counter + 1;
else
debounce_counter <= 4'h0;
end
end
wire [19:0] regulator_main_count;
wire [19:0] regulator_12_count;
wire [19:0] regulator_5_count;
wire [19:0] regulator_3_3_main_count;
wire [19:0] regulator_3_3_adc_count;
wire [19:0] regulator_3_3_sd_count;
pseudo_adc pseudo_adc_regulator_main (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_main_source),
.adc_count(regulator_main_count));
pseudo_adc pseudo_adc_regulator_12 (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_12_source),
.adc_count(regulator_12_count));
pseudo_adc pseudo_adc_regulator_5 (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_5_source),
.adc_count(regulator_5_count));
pseudo_adc pseudo_adc_regulator_3_3_main (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_3_3_main_source),
.adc_count(regulator_3_3_main_count));
pseudo_adc pseudo_adc_regulator_3_3_adc (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_3_3_adc_source),
.adc_count(regulator_3_3_adc_count));
pseudo_adc pseudo_adc_regulator_3_3_sd (
.clock(clock_42_0000),
.reset(reset),
.source(regulator_3_3_sd_source),
.adc_count(regulator_3_3_sd_count));
wire wb_cyc;
wire wb_stb;
wire wb_we;
wire [7:0] wb_adr;
wire [7:0] wb_dat_i;
wire [7:0] wb_dat_o;
wire wb_ack;
efb efb_inst (
.wb_clk_i(clock_126_000),
.wb_rst_i(reset),
.wb_cyc_i(wb_cyc),
.wb_stb_i(wb_stb),
.wb_we_i(wb_we),
.wb_adr_i(wb_adr),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_ack_o(wb_ack),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_scsn(1'b1),
.spi_csn(spi_csn)
);
wire adc_sample_start;
wire [31:0] adc_buffer_data;
wire [31:0] adc_data_ch1;
wire [31:0] adc_data_ch2;
wire [31:0] adc_data_ch3;
wire [31:0] adc_data_ch4;
wire [31:0] adc_data_ch5;
wire [31:0] adc_data_ch6;
wire [31:0] adc_data_ch7;
wire [31:0] adc_data_ch8;
wire [31:0] buffer_data;
wire buffer_write_enable;
wire buffer_write_enable_adc;
wire buffer_read_enable;
wire buffer_empty;
wire buffer_almost_empty;
wire buffer_almost_full;
wire system_idle;
wire sd_busy;
wire sd_write_ready;
parameter MAX_BYTES = 78;
wire [MAX_BYTES*8-1:0] record_bytes;
wire [7:0] record_num_bytes;
wire record_valid;
wire adc_disable;
wire sd_disable;
spi_controller #(.MAX_BYTES(MAX_BYTES)) spi_controller_inst (
.clock_126(clock_126_000 ),
.clock(clock_42_0000 ),
.reset(reset ),
.wb_cyc(wb_cyc),
.wb_stb(wb_stb),
.wb_we(wb_we),
.wb_adr(wb_adr),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_ack(wb_ack),
.adc_sample_start(adc_sample_start),
.buffer_read_enable(buffer_read_enable),
.buffer_data(buffer_data),
.buffer_ready(!buffer_almost_empty),
.adc_disable(adc_disable),
.sd_disable(sd_disable),
.adc_init(adc_init),
.sd_init_1(sd_init_1),
.sd_init_2(sd_init_2),
.sd_write_error(sd_write_error),
.sd_write_ready(sd_write_ready),
.sd_busy(sd_busy),
.ms_pulse(ms_pulse),
.regulator_3_3v_adc_en(regulator_3_3v_adc_en_spi_controller),
.regulator_3_3v_sd_en(regulator_3_3v_sd_en_spi_controller),
.record_bytes(record_bytes),
.record_num_bytes(record_num_bytes),
.record_valid(record_valid));
wire adc_event_detected_ch1;
wire adc_event_detected_ch2;
wire adc_event_detected_ch3;
wire adc_event_detected_ch4;
wire adc_event_detected_ch5;
wire adc_event_detected_ch6;
wire adc_event_detected_ch7;
wire adc_event_detected_ch8;
adc_serial_interface adc_serial_interface_inst (
.clock(clock_42_0000 ),
.reset(reset ),
.start(adc_sample_start),
.sd_write_ready(sd_write_ready),
.adc_data_ready(adc_drdy),
.adc_clock(adc_clock),
.adc_data_0(adc_data_0),
.adc_data_1(adc_data_1),
.adc_channel_data_ch1(adc_data_ch1),
.adc_channel_data_ch2(adc_data_ch2),
.adc_channel_data_ch3(adc_data_ch3),
.adc_channel_data_ch4(adc_data_ch4),
.adc_channel_data_ch5(adc_data_ch5),
.adc_channel_data_ch6(adc_data_ch6),
.adc_channel_data_ch7(adc_data_ch7),
.adc_channel_data_ch8(adc_data_ch8),
.adc_event_detected_ch1(adc_event_detected_ch1),
.adc_event_detected_ch2(adc_event_detected_ch2),
.adc_event_detected_ch3(adc_event_detected_ch3),
.adc_event_detected_ch4(adc_event_detected_ch4),
.adc_event_detected_ch5(adc_event_detected_ch5),
.adc_event_detected_ch6(adc_event_detected_ch6),
.adc_event_detected_ch7(adc_event_detected_ch7),
.adc_event_detected_ch8(adc_event_detected_ch8),
.adc_buffer_data(adc_buffer_data),
.buffer_write_enable(buffer_write_enable_adc),
.buffer_full(buffer_almost_full));
assign buffer_write_enable = (system_idle) ? 1'b0 : buffer_write_enable_adc;
fifo_buffer fifo_buffer_inst (
.Data(adc_buffer_data),
.WrClock(clock_42_0000),
.RdClock(clock_42_0000),
.WrEn(buffer_write_enable),
.RdEn(buffer_read_enable),
.Reset(reset),
.RPReset(reset),
.Q(buffer_data),
.Empty(buffer_empty),
.AlmostEmpty(buffer_almost_empty),
.Full(buffer_full),
.AlmostFull(buffer_almost_full)
);
reg [5:0] temp_pwm_count;
wire [5:0] therm_pwm1;
wire [5:0] therm_pwm2;
wire [5:0] therm_pwm3;
wire [5:0] therm_pwm4;
wire [5:0] therm_controller_pwm1;
wire [5:0] therm_controller_pwm2;
wire [5:0] therm_controller_pwm3;
wire [5:0] therm_controller_pwm4;
reg [5:0] therm_override_pwm1;
reg [5:0] therm_override_pwm2;
reg [5:0] therm_override_pwm3;
reg [5:0] therm_override_pwm4;
wire therm_override_1;
wire therm_override_2;
wire therm_override_3;
wire therm_override_4;
wire therm_increment_1;
wire therm_increment_2;
wire therm_increment_3;
wire therm_increment_4;
wire therm_decrement_1;
wire therm_decrement_2;
wire therm_decrement_3;
wire therm_decrement_4;
reg therm_increment_1_reg;
reg therm_increment_2_reg;
reg therm_increment_3_reg;
reg therm_increment_4_reg;
reg therm_decrement_1_reg;
reg therm_decrement_2_reg;
reg therm_decrement_3_reg;
reg therm_decrement_4_reg;
assign therm_pwm1 = (therm_override_1) ? therm_override_pwm1 : therm_controller_pwm1;
assign therm_pwm2 = (therm_override_2) ? therm_override_pwm2 : therm_controller_pwm2;
assign therm_pwm3 = (therm_override_3) ? therm_override_pwm3 : therm_controller_pwm3;
assign therm_pwm4 = (therm_override_4) ? therm_override_pwm4 : therm_controller_pwm4;
always@(posedge clock_00_0048 or posedge reset)
begin
if(reset)
begin
temp_pwm_count <= 6'h00;
therm_en1 <= 1'b0;
therm_en2 <= 1'b0;
therm_en3 <= 1'b0;
therm_en4 <= 1'b0;
therm_override_pwm1 <= 0;
therm_override_pwm2 <= 0;
therm_override_pwm3 <= 0;
therm_override_pwm4 <= 0;
therm_increment_1_reg <= 1'b0;
therm_increment_2_reg <= 1'b0;
therm_increment_3_reg <= 1'b0;
therm_increment_4_reg <= 1'b0;
therm_decrement_1_reg <= 1'b0;
therm_decrement_2_reg <= 1'b0;
therm_decrement_3_reg <= 1'b0;
therm_decrement_4_reg <= 1'b0;
end
else
begin
therm_increment_1_reg <= therm_increment_1;
therm_increment_2_reg <= therm_increment_2;
therm_increment_3_reg <= therm_increment_3;
therm_increment_4_reg <= therm_increment_4;
therm_decrement_1_reg <= therm_decrement_1;
therm_decrement_2_reg <= therm_decrement_2;
therm_decrement_3_reg <= therm_decrement_3;
therm_decrement_4_reg <= therm_decrement_4;
if(~therm_increment_1_reg && therm_increment_1)
begin
if(therm_override_pwm1 <= 6'h39)
therm_override_pwm1 <= therm_override_pwm1 + 6;
else
therm_override_pwm1 <= 6'h3F;
end
else if(~therm_decrement_1_reg && therm_decrement_1)
begin
if(therm_override_pwm1 >= 6'h6)
therm_override_pwm1 <= therm_override_pwm1 - 6;
else
therm_override_pwm1 <= 6'h00;
end
if(~therm_increment_2_reg && therm_increment_2)
begin
if(therm_override_pwm2 <= 6'h39)
therm_override_pwm2 <= therm_override_pwm2 + 6;
else
therm_override_pwm2 <= 6'h3F;
end
else if(~therm_decrement_2_reg && therm_decrement_2)
begin
if(therm_override_pwm2 >= 6'h6)
therm_override_pwm2 <= therm_override_pwm2 - 6;
else
therm_override_pwm2 <= 6'h00;
end
if(~therm_increment_3_reg && therm_increment_3)
begin
if(therm_override_pwm3 <= 6'h39)
therm_override_pwm3 <= therm_override_pwm3 + 6;
else
therm_override_pwm3 <= 6'h3F;
end
else if(~therm_decrement_3_reg && therm_decrement_3)
begin
if(therm_override_pwm3 >= 6'h6)
therm_override_pwm3 <= therm_override_pwm3 - 6;
else
therm_override_pwm3 <= 6'h00;
end
if(~therm_increment_4_reg && therm_increment_4)
begin
if(therm_override_pwm4 <= 6'h39)
therm_override_pwm4 <= therm_override_pwm4 + 6;
else
therm_override_pwm4 <= 6'h3F;
end
else if(~therm_decrement_4_reg && therm_decrement_4)
begin
if(therm_override_pwm4 >= 6'h6)
therm_override_pwm4 <= therm_override_pwm4 - 6;
else
therm_override_pwm4 <= 6'h00;
end
temp_pwm_count <= temp_pwm_count + 1;
if((therm_pwm1 != 6'h00) && (temp_pwm_count <= therm_pwm1))
therm_en1 <= 1'b1;
else
therm_en1 <= 1'b0;
if((therm_pwm2 != 6'h00) && (temp_pwm_count <= therm_pwm2))
therm_en2 <= 1'b1;
else
therm_en2 <= 1'b0;
if((therm_pwm3 != 6'h00) && (temp_pwm_count <= therm_pwm3))
therm_en3 <= 1'b1;
else
therm_en3 <= 1'b0;
if((therm_pwm4 != 6'h00) && (temp_pwm_count <= therm_pwm4))
therm_en4 <= 1'b1;
else
therm_en4 <= 1'b0;
end
end
parameter TEMP_MAX_BYTES = 5;
wire [TEMP_MAX_BYTES*8-1:0] temp_tx_bytes;
wire [3:0] temp_tx_num_bytes;
wire temp_tx_valid;
wire [7:0] temp_rx_byte;
wire temp_rx_valid;
temp_decoder_encoder temp_decoder_encoder_inst(
.clock(clock_00_0048 ),
.clock_4x(clock_00_0192),
.reset(reset | therm_reset),
.rxtx(temp_rxtx ),
.rx_valid(temp_rx_valid),
.rx_byte(temp_rx_byte),
.tx_bytes(temp_tx_bytes),
.tx_num_bytes(temp_tx_num_bytes),
.tx_valid(temp_tx_valid),
.tx_switch(temp_tx_switch));
wire [15:0] temp1_value;
wire [15:0] temp2_value;
wire [15:0] temp3_value;
wire [15:0] temp4_value;
thermal_controller thermal_controller_inst(
.clock(clock_42_0000 ),
.reset(reset | therm_reset),
.temp_sample_pulse(temp_sample_pulse),
.temp_rx_valid(temp_rx_valid),
.temp_rx_byte(temp_rx_byte),
.temp_tx_bytes(temp_tx_bytes),
.temp_tx_num_bytes(temp_tx_num_bytes),
.temp_tx_valid(temp_tx_valid),
.temp1_value(temp1_value),
.temp2_value(temp2_value),
.temp3_value(temp3_value),
.temp4_value(temp4_value),
.therm_pwm1(therm_controller_pwm1),
.therm_pwm2(therm_controller_pwm2),
.therm_pwm3(therm_controller_pwm3),
.therm_pwm4(therm_controller_pwm4)
);
wire [7:0] rs232_rx_byte;
wire rs232_rx_valid;
wire [7:0] rs232_rx_command_valid;
wire rs232_buffer_write_enable;
wire [7:0] rs232_record_byte;
wire rs232_buffer_read_enable;
wire [7:0] rs232_tx_buffer_byte;
wire rs232_buffer_empty;
wire rs232_buffer_full;
rs232_decoder_encoder rs232_decoder_encoder_inst(
.clock(clock_00_0048 ),
.clock_4x(clock_00_0192),
.reset(reset ),
.rx(rs232_rx ),
.tx(rs232_tx ),
.rx_valid(rs232_rx_valid),
.rx_byte(rs232_rx_byte),
.tx_buffer_empty(rs232_buffer_empty),
.tx_buffer_read_enable(rs232_buffer_read_enable),
.tx_buffer_byte(rs232_tx_buffer_byte)
);
fifo_buffer_rs232_tx fifo_buffer_rs232_inst (
.Data(rs232_record_byte),
.WrClock(clock_42_0000),
.RdClock(clock_00_0048),
.WrEn(rs232_buffer_write_enable),
.RdEn(rs232_buffer_read_enable),
.Reset(reset),
.RPReset(reset),
.Q(rs232_tx_buffer_byte),
.Empty(rs232_buffer_empty),
.Full(rs232_buffer_full)
);
command_processor #(.MAX_BYTES(MAX_BYTES)) command_processor_inst(
.clock(clock_42_0000 ),
.reset(reset ),
.regulator_12v_en(regulator_12v_en),
.regulator_3_3v_sd_en(regulator_3_3v_sd_en_command_processor),
.regulator_3_3v_adc_en(regulator_3_3v_adc_en_command_processor),
.regulator_12v_en_sup(regulator_12v_en),
.regulator_3_3v_sd_en_sup(regulator_3_3v_sd_en),
.regulator_3_3v_adc_en_sup(regulator_3_3v_adc_en),
.ms_pulse(ms_pulse),
.rs232_reset(rs232_reset),
.rs232_rx_valid(rs232_rx_valid),
.rs232_rx_byte(rs232_rx_byte),
.command_valid(rs232_rx_command_valid),
.rs232_buffer_full(rs232_buffer_full),
.rs232_buffer_write_enable(rs232_buffer_write_enable),
.rs232_record_byte(rs232_record_byte),
.rs232_tx_bytes(record_bytes),
.rs232_tx_byte_count(record_num_bytes),
.rs232_tx_valid(record_valid),
.temp1_value(temp1_value),
.temp2_value(temp2_value),
.temp3_value(temp3_value),
.temp4_value(temp4_value),
.therm_pwm1(therm_pwm1),
.therm_pwm2(therm_pwm2),
.therm_pwm3(therm_pwm3),
.therm_pwm4(therm_pwm4),
.therm_override_1(therm_override_1),
.therm_override_2(therm_override_2),
.therm_override_3(therm_override_3),
.therm_override_4(therm_override_4),
.therm_increment_1(therm_increment_1),
.therm_increment_2(therm_increment_2),
.therm_increment_3(therm_increment_3),
.therm_increment_4(therm_increment_4),
.therm_decrement_1(therm_decrement_1),
.therm_decrement_2(therm_decrement_2),
.therm_decrement_3(therm_decrement_3),
.therm_decrement_4(therm_decrement_4),
.therm_reset(therm_reset_control),
.system_idle(system_idle),
.adc_disable(adc_disable),
.sd_disable(sd_disable),
.adc_init(adc_init),
.sd_init_1(sd_init_1),
.sd_init_2(sd_init_2),
.sd_write_ready(sd_write_ready),
.buffer_full(buffer_full),
.buffer_full_latch(buffer_full_latch),
.adc_data_ch1(adc_data_ch1),
.adc_data_ch2(adc_data_ch2),
.adc_data_ch3(adc_data_ch3),
.adc_data_ch4(adc_data_ch4),
.adc_data_ch5(adc_data_ch5),
.adc_data_ch6(adc_data_ch6),
.adc_data_ch7(adc_data_ch7),
.adc_data_ch8(adc_data_ch8),
.adc_event_detected_ch1(adc_event_detected_ch1),
.adc_event_detected_ch2(adc_event_detected_ch2),
.adc_event_detected_ch3(adc_event_detected_ch3),
.adc_event_detected_ch4(adc_event_detected_ch4),
.adc_event_detected_ch5(adc_event_detected_ch5),
.adc_event_detected_ch6(adc_event_detected_ch6),
.adc_event_detected_ch7(adc_event_detected_ch7),
.adc_event_detected_ch8(adc_event_detected_ch8),
.regulator_main_count(regulator_main_count),
.regulator_12_count(regulator_12_count),
.regulator_5_count(regulator_5_count),
.regulator_3_3_main_count(regulator_3_3_main_count),
.regulator_3_3_adc_count(regulator_3_3_adc_count),
.regulator_3_3_sd_count(regulator_3_3_sd_count)
);
assign test_a = test_signal_120ns;
assign test_b = clock_00_0048;
assign test_c = therm_en1;
assign test_d = buffer_full;
assign test_e = sd_busy;
assign test_f = ms_pulse;
endmodule | 3 |
140,959 | data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v | 92,973,199 | SHA1_core_tb.v | v | 76 | 98 | [] | [] | [] | null | line:70: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5 rst = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10 i_hash_in_start = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10 msgIn =0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #6000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:40: Cannot find file containing module: \'Initial_Hash_In\'\nInitial_Hash_In I1(clk,rst,i_hash_in_start,i_hash_in,i_hash_out_done,i_hash_out);\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new,data/full_repos/permissive/92973199/Initial_Hash_In\n data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new,data/full_repos/permissive/92973199/Initial_Hash_In.v\n data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new,data/full_repos/permissive/92973199/Initial_Hash_In.sv\n Initial_Hash_In\n Initial_Hash_In.v\n Initial_Hash_In.sv\n obj_dir/Initial_Hash_In\n obj_dir/Initial_Hash_In.v\n obj_dir/Initial_Hash_In.sv\n%Error: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:41: Cannot find file containing module: \'Msg_In\'\nMsg_In M1(clk,rst,msg_in_start,msgIn,msgOutDone,msgOut);\n^~~~~~\n%Error: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:42: Cannot find file containing module: \'SHA1_core\'\nSHA1_core S1(clk,rst,i_hash_out_done,i_hash_out,msgOutDone,msgLenBits,msgOut,digest_done,digest);\n^~~~~~~~~\n%Error: data/full_repos/permissive/92973199/SHA1_core.srcs/sim_1/new/SHA1_core_tb.v:43: Cannot find file containing module: \'SHA1_out\'\nSHA1_out O1(clk,rst,digest_done,digest,f_hash_done,f_hash_out);\n^~~~~~~~\n%Error: Exiting due to 4 error(s), 18 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,036 | module | module SHA1_core_tb(
);
reg clk,rst;
reg i_hash_in_start;
reg [31:0]i_hash_in;
reg msg_in_start;
reg [31:0]msgIn;
reg [9:0]msgLenBits;
wire msgOutDone;
wire [511:0]msgOut;
wire [159:0]i_hash_out;
wire i_hash_out_done;
wire digest_done;
wire [159:0]digest;
wire f_hash_done;
wire [31:0]f_hash_out;
Initial_Hash_In I1(clk,rst,i_hash_in_start,i_hash_in,i_hash_out_done,i_hash_out);
Msg_In M1(clk,rst,msg_in_start,msgIn,msgOutDone,msgOut);
SHA1_core S1(clk,rst,i_hash_out_done,i_hash_out,msgOutDone,msgLenBits,msgOut,digest_done,digest);
SHA1_out O1(clk,rst,digest_done,digest,f_hash_done,f_hash_out);
initial begin
clk = 0;
#5 rst = 0;
#10 rst = 1;
#10 i_hash_in_start = 1;
msg_in_start = 1;
msgLenBits = 24;
msgIn = 32'h61626300;
i_hash_in = 32'h67452301;
#10 msgIn = 0;
i_hash_in = 32'hefcdab89;
#10 msgIn = 0;
i_hash_in = 32'h98badcfe;
#10 msgIn = 0;
i_hash_in = 32'h10325476;
#10 msgIn = 0;
i_hash_in = 32'hc3d2e1f0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn =0;
#6000 $finish;
end
always begin
#5 clk = ~clk;
end
endmodule | module SHA1_core_tb(
); |
reg clk,rst;
reg i_hash_in_start;
reg [31:0]i_hash_in;
reg msg_in_start;
reg [31:0]msgIn;
reg [9:0]msgLenBits;
wire msgOutDone;
wire [511:0]msgOut;
wire [159:0]i_hash_out;
wire i_hash_out_done;
wire digest_done;
wire [159:0]digest;
wire f_hash_done;
wire [31:0]f_hash_out;
Initial_Hash_In I1(clk,rst,i_hash_in_start,i_hash_in,i_hash_out_done,i_hash_out);
Msg_In M1(clk,rst,msg_in_start,msgIn,msgOutDone,msgOut);
SHA1_core S1(clk,rst,i_hash_out_done,i_hash_out,msgOutDone,msgLenBits,msgOut,digest_done,digest);
SHA1_out O1(clk,rst,digest_done,digest,f_hash_done,f_hash_out);
initial begin
clk = 0;
#5 rst = 0;
#10 rst = 1;
#10 i_hash_in_start = 1;
msg_in_start = 1;
msgLenBits = 24;
msgIn = 32'h61626300;
i_hash_in = 32'h67452301;
#10 msgIn = 0;
i_hash_in = 32'hefcdab89;
#10 msgIn = 0;
i_hash_in = 32'h98badcfe;
#10 msgIn = 0;
i_hash_in = 32'h10325476;
#10 msgIn = 0;
i_hash_in = 32'hc3d2e1f0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn =0;
#6000 $finish;
end
always begin
#5 clk = ~clk;
end
endmodule | 0 |
140,960 | data/full_repos/permissive/92973199/SHA1_core.srcs/sources_1/new/Initial_hash.v | 92,973,199 | Initial_hash.v | v | 64 | 83 | [] | [] | [] | [(23, 63)] | null | data/verilator_xmls/826e3ed7-a1a5-49f5-a7af-14d586ad7fdc.xml | null | 310,037 | module | module Initial_Hash_In(input clk,
input rst,
input start,
input [31:0]initial_hash_in,
output reg done,
output reg [159:0]initial_hash_out
);
reg [2:0]count;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
done <= 0;
initial_hash_out <= 0;
count <= 0;
end else begin
if(start)
if(count < 6)
count <= count + 1;
end
end
always@(count) begin
if(count == 1) begin
initial_hash_out[159:128] = initial_hash_in;
end
else if(count == 2)
initial_hash_out[127:96] = initial_hash_in;
else if(count == 3)
initial_hash_out[95:64] = initial_hash_in;
else if(count == 4)
initial_hash_out[63:32] = initial_hash_in;
else if(count == 5)
initial_hash_out[31:0] = initial_hash_in;
else if (count == 6) begin
done = 1;
end
else begin end
end
endmodule | module Initial_Hash_In(input clk,
input rst,
input start,
input [31:0]initial_hash_in,
output reg done,
output reg [159:0]initial_hash_out
); |
reg [2:0]count;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
done <= 0;
initial_hash_out <= 0;
count <= 0;
end else begin
if(start)
if(count < 6)
count <= count + 1;
end
end
always@(count) begin
if(count == 1) begin
initial_hash_out[159:128] = initial_hash_in;
end
else if(count == 2)
initial_hash_out[127:96] = initial_hash_in;
else if(count == 3)
initial_hash_out[95:64] = initial_hash_in;
else if(count == 4)
initial_hash_out[63:32] = initial_hash_in;
else if(count == 5)
initial_hash_out[31:0] = initial_hash_in;
else if (count == 6) begin
done = 1;
end
else begin end
end
endmodule | 0 |
140,961 | data/full_repos/permissive/92973199/SHA1_core.srcs/sources_1/new/Msg_In.v | 92,973,199 | Msg_In.v | v | 84 | 83 | [] | [] | [] | [(23, 83)] | null | data/verilator_xmls/95e14890-1e6a-4cbc-bc43-c6ebdd7bd7c1.xml | null | 310,038 | module | module Msg_In(input clk,
input rst,
input start,
input [31:0]msg_in,
output reg done,
output reg [511:0]msg_out
);
reg [9:0]count;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
done <= 0;
msg_out <= 0;
count <= 0;
end else begin
if(start)
if(count < 17)
count <= count + 1;
end
end
always@(count) begin
if(count == 1)
msg_out[511:480] = msg_in;
else if(count == 2)
msg_out[479:448] = msg_in;
else if(count == 3)
msg_out[447:416] = msg_in;
else if(count == 4)
msg_out[415:384] = msg_in;
else if(count == 5)
msg_out[383:352] = msg_in;
else if (count == 6)
msg_out[351:320] = msg_in;
else if (count == 7)
msg_out[319:288] = msg_in;
else if (count == 8)
msg_out[287:256] = msg_in;
else if (count == 9)
msg_out[255:224] = msg_in;
else if (count == 10)
msg_out[223:192] = msg_in;
else if (count == 11)
msg_out[191:160] = msg_in;
else if (count == 12)
msg_out[159:128] = msg_in;
else if (count == 13)
msg_out[127:96] = msg_in;
else if (count == 14)
msg_out[95:64] = msg_in;
else if (count == 15)
msg_out[63:32] = msg_in;
else if (count == 16)
msg_out[31:0] = msg_in;
else if (count == 17)
done = 1;
else begin end
end
endmodule | module Msg_In(input clk,
input rst,
input start,
input [31:0]msg_in,
output reg done,
output reg [511:0]msg_out
); |
reg [9:0]count;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
done <= 0;
msg_out <= 0;
count <= 0;
end else begin
if(start)
if(count < 17)
count <= count + 1;
end
end
always@(count) begin
if(count == 1)
msg_out[511:480] = msg_in;
else if(count == 2)
msg_out[479:448] = msg_in;
else if(count == 3)
msg_out[447:416] = msg_in;
else if(count == 4)
msg_out[415:384] = msg_in;
else if(count == 5)
msg_out[383:352] = msg_in;
else if (count == 6)
msg_out[351:320] = msg_in;
else if (count == 7)
msg_out[319:288] = msg_in;
else if (count == 8)
msg_out[287:256] = msg_in;
else if (count == 9)
msg_out[255:224] = msg_in;
else if (count == 10)
msg_out[223:192] = msg_in;
else if (count == 11)
msg_out[191:160] = msg_in;
else if (count == 12)
msg_out[159:128] = msg_in;
else if (count == 13)
msg_out[127:96] = msg_in;
else if (count == 14)
msg_out[95:64] = msg_in;
else if (count == 15)
msg_out[63:32] = msg_in;
else if (count == 16)
msg_out[31:0] = msg_in;
else if (count == 17)
done = 1;
else begin end
end
endmodule | 0 |
140,962 | data/full_repos/permissive/92973199/SHA1_core.srcs/sources_1/new/SHA1_core.v | 92,973,199 | SHA1_core.v | v | 785 | 117 | [] | [] | [] | [(23, 785)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/92973199/SHA1_core.srcs/sources_1/new/SHA1_core.v:118: Operator OR expects 512 bits on the RHS, but RHS\'s VARREF \'msg_len\' generates 10 bits.\n : ... In instance SHA1_core\n temp1 = msg|(1<<(511-msg_len))|msg_len;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 310,039 | module | module SHA1_core(
input clk,
input rst,
input initial_hash_start,
input [159:0]initial_hash,
input msg_in_start,
input [9:0]msg_len,
input [511:0]msg,
output reg digest_done,
output reg [159:0]digest_out
);
reg [31:0]a[80:0],b[80:0],c[80:0],d[80:0],e[80:0];
reg [31:0]h[4:0];
reg [31:0]hash[4:0];
reg [31:0]k[3:0];
reg [31:0]w[79:0];
reg [31:0]wt[63:0];
reg [31:0]temp[79:0];
reg [511:0]temp1;
reg [3:0] curr_state, next_state;
reg [3:0] flag;
parameter SHA1_RESET = 0;
parameter SHA1_INIT = 1;
parameter SHA1_W_ROUNDS = 2;
parameter SHA1_ABCDE_INIT = 3;
parameter SHA1_F0_ROUNDS = 4;
parameter SHA1_F1_ROUNDS = 5;
parameter SHA1_F2_ROUNDS = 6;
parameter SHA1_F3_ROUNDS = 7;
parameter SHA1_FINAL = 8;
parameter SHA1_DIGEST = 9;
initial
flag = 0;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
curr_state <= SHA1_RESET;
end else begin
curr_state <= next_state;
end
end
always@(*) begin
if(flag == 1)
next_state = SHA1_INIT;
else if(flag == 2)
next_state = SHA1_W_ROUNDS;
else if(flag == 3)
next_state = SHA1_ABCDE_INIT;
else if(flag == 4)
next_state = SHA1_F0_ROUNDS;
else if(flag == 5)
next_state = SHA1_F1_ROUNDS;
else if(flag == 6)
next_state = SHA1_F2_ROUNDS;
else if(flag == 7)
next_state = SHA1_F3_ROUNDS;
else if(flag == 8)
next_state = SHA1_FINAL;
else if(flag == 9)
next_state = SHA1_DIGEST;
else begin end
end
always@(*) begin
if(curr_state == SHA1_RESET) begin
h[0] = 0;
h[1] = 0;
h[2] = 0;
h[3] = 0;
h[4] = 0;
w[0] = 0;w[1] = 0;w[2] = 0;w[3] = 0;w[4] = 0;w[5] = 0;w[6] = 0;w[7] = 0;w[8] = 0;w[9] = 0;
w[10] = 0;w[11] = 0;w[12] = 0;w[13] = 0;w[14] = 0;w[15] = 0;w[16] = 0;w[17] = 0;w[18] = 0;w[19] = 0;
w[20] = 0;w[21] = 0;w[22] = 0;w[23] = 0;w[24] = 0;w[25] = 0;w[26] = 0;w[27] = 0;w[28] = 0;w[29] = 0;
w[30] = 0;w[31] = 0;w[32] = 0;w[33] = 0;w[34] = 0;w[35] = 0;w[36] = 0;w[37] = 0;w[38] = 0;w[39] = 0;
w[40] = 0;w[41] = 0;w[42] = 0;w[43] = 0;w[44] = 0;w[45] = 0;w[46] = 0;w[47] = 0;w[48] = 0;w[49] = 0;
w[50] = 0;w[51] = 0;w[52] = 0;w[53] = 0;w[54] = 0;w[55] = 0;w[56] = 0;w[57] = 0;w[58] = 0;w[59] = 0;
w[60] = 0;w[61] = 0;w[62] = 0;w[63] = 0;w[64] = 0;w[65] = 0;w[66] = 0;w[67] = 0;w[68] = 0;w[69] = 0;
w[70] = 0;w[71] = 0;w[72] = 0;w[73] = 0;w[74] = 0;w[75] = 0;w[76] = 0;w[77] = 0;w[78] = 0;w[79] = 0;
flag = 1;
end else if(curr_state == SHA1_INIT) begin
k[0] = 32'h5a827999;
k[1] = 32'h6ed9eba1;
k[2] = 32'h8f1bbcdc;
k[3] = 32'hca62c1d6;
if(initial_hash_start)begin
h[4] = initial_hash[31:0];
h[3] = initial_hash[63:32];
h[2] = initial_hash[95:64];
h[1] = initial_hash[127:96];
h[0] = initial_hash[159:128];
end
if(msg_in_start)begin
temp1 = msg|(1<<(511-msg_len))|msg_len;
w[0] = temp1[511:480];
w[1] = temp1[479:448];
w[2] = temp1[447:416];
w[3] = temp1[415:384];
w[4] = temp1[383:352];
w[5] = temp1[351:320];
w[6] = temp1[319:288];
w[7] = temp1[287:256];
w[8] = temp1[255:224];
w[9] = temp1[223:192];
w[10] = temp1[191:160];
w[11] = temp1[159:128];
w[12] = temp1[127:96];
w[13] = temp1[95:64];
w[14] = temp1[63:32];
w[15] = temp1[31:0];
flag = 2;
end
end else if(curr_state == SHA1_W_ROUNDS) begin
wt[0] = w[13]^w[8]^w[2]^w[0];
w[16] = {wt[0][30:0],wt[0][31]};
wt[1] = w[14]^w[9]^w[3]^w[1];
w[17] = {wt[1][30:0],wt[1][31]};
wt[2] = w[15]^w[10]^w[4]^w[2];
w[18] = {wt[2][30:0],wt[2][31]};
wt[3] = w[16]^w[11]^w[5]^w[3];
w[19] = {wt[3][30:0],wt[3][31]};
wt[4] = w[17]^w[12]^w[6]^w[4];
w[20] = {wt[4][30:0],wt[4][31]};
wt[5] = w[18]^w[13]^w[7]^w[5];
w[21] = {wt[5][30:0],wt[5][31]};
wt[6] = w[19]^w[14]^w[8]^w[6];
w[22] = {wt[6][30:0],wt[6][31]};
wt[7] = w[20]^w[15]^w[9]^w[7];
w[23] = {wt[7][30:0],wt[7][31]};
wt[8] = w[21]^w[16]^w[10]^w[8];
w[24] = {wt[8][30:0],wt[8][31]};
wt[9] = w[22]^w[17]^w[11]^w[9];
w[25] = {wt[9][30:0],wt[9][31]};
wt[10] = w[23]^w[18]^w[12]^w[10];
w[26] = {wt[10][30:0],wt[10][31]};
wt[11] = w[24]^w[19]^w[13]^w[11];
w[27] = {wt[11][30:0],wt[11][31]};
wt[12] = w[25]^w[20]^w[14]^w[12];
w[28] = {wt[12][30:0],wt[12][31]};
wt[13] = w[26]^w[21]^w[15]^w[13];
w[29] = {wt[13][30:0],wt[13][31]};
wt[14] = w[27]^w[22]^w[16]^w[14];
w[30] = {wt[14][30:0],wt[14][31]};
wt[15] = w[28]^w[23]^w[17]^w[15];
w[31] = {wt[15][30:0],wt[15][31]};
wt[16] = w[29]^w[24]^w[18]^w[16];
w[32] = {wt[16][30:0],wt[16][31]};
wt[17] = w[30]^w[25]^w[19]^w[17];
w[33] = {wt[17][30:0],wt[17][31]};
wt[18] = w[31]^w[26]^w[20]^w[18];
w[34] = {wt[18][30:0],wt[18][31]};
wt[19] = w[32]^w[27]^w[21]^w[19];
w[35] = {wt[19][30:0],wt[19][31]};
wt[20] = w[33]^w[28]^w[22]^w[20];
w[36] = {wt[20][30:0],wt[20][31]};
wt[21] = w[34]^w[29]^w[23]^w[21];
w[37] = {wt[21][30:0],wt[21][31]};
wt[22] = w[35]^w[30]^w[24]^w[22];
w[38] = {wt[22][30:0],wt[22][31]};
wt[23] = w[36]^w[31]^w[25]^w[23];
w[39] = {wt[23][30:0],wt[23][31]};
wt[24] = w[37]^w[32]^w[26]^w[24];
w[40] = {wt[24][30:0],wt[24][31]};
wt[25] = w[38]^w[33]^w[27]^w[25];
w[41] = {wt[25][30:0],wt[25][31]};
wt[26] = w[39]^w[34]^w[28]^w[26];
w[42] = {wt[26][30:0],wt[26][31]};
wt[27] = w[40]^w[35]^w[29]^w[27];
w[43] = {wt[27][30:0],wt[27][31]};
wt[28] = w[41]^w[36]^w[30]^w[28];
w[44] = {wt[28][30:0],wt[28][31]};
wt[29] = w[42]^w[37]^w[31]^w[29];
w[45] = {wt[29][30:0],wt[29][31]};
wt[30] = w[43]^w[38]^w[32]^w[30];
w[46] = {wt[30][30:0],wt[30][31]};
wt[31] = w[44]^w[39]^w[33]^w[31];
w[47] = {wt[31][30:0],wt[31][31]};
wt[32] = w[45]^w[40]^w[34]^w[32];
w[48] = {wt[32][30:0],wt[32][31]};
wt[33] = w[46]^w[41]^w[35]^w[33];
w[49] = {wt[33][30:0],wt[33][31]};
wt[34] = w[47]^w[42]^w[36]^w[34];
w[50] = {wt[34][30:0],wt[34][31]};
wt[35] = w[48]^w[43]^w[37]^w[35];
w[51] = {wt[35][30:0],wt[35][31]};
wt[36] = w[49]^w[44]^w[38]^w[36];
w[52] = {wt[36][30:0],wt[36][31]};
wt[37] = w[50]^w[45]^w[39]^w[37];
w[53] = {wt[37][30:0],wt[37][31]};
wt[38] = w[51]^w[46]^w[40]^w[38];
w[54] = {wt[38][30:0],wt[38][31]};
wt[39] = w[52]^w[47]^w[41]^w[39];
w[55] = {wt[39][30:0],wt[39][31]};
wt[40] = w[53]^w[48]^w[42]^w[40];
w[56] = {wt[40][30:0],wt[40][31]};
wt[41] = w[54]^w[49]^w[43]^w[41];
w[57] = {wt[41][30:0],wt[41][31]};
wt[42] = w[55]^w[50]^w[44]^w[42];
w[58] = {wt[42][30:0],wt[42][31]};
wt[43] = w[56]^w[51]^w[45]^w[43];
w[59] = {wt[43][30:0],wt[43][31]};
wt[44] = w[57]^w[52]^w[46]^w[44];
w[60] = {wt[44][30:0],wt[44][31]};
wt[45] = w[58]^w[53]^w[47]^w[45];
w[61] = {wt[45][30:0],wt[45][31]};
wt[46] = w[59]^w[54]^w[48]^w[46];
w[62] = {wt[46][30:0],wt[46][31]};
wt[47] = w[60]^w[55]^w[49]^w[47];
w[63] = {wt[47][30:0],wt[47][31]};
wt[48] = w[61]^w[56]^w[50]^w[48];
w[64] = {wt[48][30:0],wt[48][31]};
wt[49] = w[62]^w[57]^w[51]^w[49];
w[65] = {wt[49][30:0],wt[49][31]};
wt[50] = w[63]^w[58]^w[52]^w[50];
w[66] = {wt[50][30:0],wt[50][31]};
wt[51] = w[64]^w[59]^w[53]^w[51];
w[67] = {wt[51][30:0],wt[51][31]};
wt[52] = w[65]^w[60]^w[54]^w[52];
w[68] = {wt[52][30:0],wt[52][31]};
wt[53] = w[66]^w[61]^w[55]^w[53];
w[69] = {wt[53][30:0],wt[53][31]};
wt[54] = w[67]^w[62]^w[56]^w[54];
w[70] = {wt[54][30:0],wt[54][31]};
wt[55] = w[68]^w[63]^w[57]^w[55];
w[71] = {wt[55][30:0],wt[55][31]};
wt[56] = w[69]^w[64]^w[58]^w[56];
w[72] = {wt[56][30:0],wt[56][31]};
wt[57] = w[70]^w[65]^w[59]^w[57];
w[73] = {wt[57][30:0],wt[57][31]};
wt[58] = w[71]^w[66]^w[60]^w[58];
w[74] = {wt[58][30:0],wt[58][31]};
wt[59] = w[72]^w[67]^w[61]^w[59];
w[75] = {wt[59][30:0],wt[59][31]};
wt[60] = w[73]^w[68]^w[62]^w[60];
w[76] = {wt[60][30:0],wt[60][31]};
wt[61] = w[74]^w[69]^w[63]^w[61];
w[77] = {wt[61][30:0],wt[61][31]};
wt[62] = w[75]^w[70]^w[64]^w[62];
w[78] = {wt[62][30:0],wt[62][31]};
wt[63] = w[76]^w[71]^w[65]^w[63];
w[79] = {wt[63][30:0],wt[63][31]};
flag = 3;
end else if(curr_state == SHA1_ABCDE_INIT) begin
a[0] = h[0];
b[0] = h[1];
c[0] = h[2];
d[0] = h[3];
e[0] = h[4];
flag = 4;
end else if(curr_state == SHA1_F0_ROUNDS) begin
temp[0] = {a[0][26:0],a[0][31:27]} + ((b[0] & c[0]) | ((~b[0]) & d[0])) + e[0] + w[0] + k[0] ;
e[1] = d[0];
d[1] = c[0];
c[1] = {b[0][1:0],b[0][31:2]};
b[1] = a[0];
a[1] = temp[0];
temp[1] = {a[1][26:0],a[1][31:27]} + ((b[1] & c[1]) | ((~b[1]) & d[1])) + e[1] + w[1] + k[0] ;
e[2] = d[1];
d[2] = c[1];
c[2] = {b[1][1:0],b[1][31:2]};
b[2] = a[1];
a[2] = temp[1];
temp[2] = {a[2][26:0],a[2][31:27]} + ((b[2] & c[2]) | ((~b[2]) & d[2])) + e[2] + w[2] + k[0] ;
e[3] = d[2];
d[3] = c[2];
c[3] = {b[2][1:0],b[2][31:2]};
b[3] = a[2];
a[3] = temp[2];
temp[3] = {a[3][26:0],a[3][31:27]} + ((b[3] & c[3]) | ((~b[3]) & d[3])) + e[3] + w[3] + k[0] ;
e[4] = d[3];
d[4] = c[3];
c[4] = {b[3][1:0],b[3][31:2]};
b[4] = a[3];
a[4] = temp[3];
temp[4] = {a[4][26:0],a[4][31:27]} + ((b[4] & c[4]) | ((~b[4]) & d[4])) + e[4] + w[4] + k[0] ;
e[5] = d[4];
d[5] = c[4];
c[5] = {b[4][1:0],b[4][31:2]};
b[5] = a[4];
a[5] = temp[4];
temp[5] = {a[5][26:0],a[5][31:27]} + ((b[5] & c[5]) | ((~b[5]) & d[5])) + e[5] + w[5] + k[0] ;
e[6] = d[5];
d[6] = c[5];
c[6] = {b[5][1:0],b[5][31:2]};
b[6] = a[5];
a[6] = temp[5];
temp[6] = {a[6][26:0],a[6][31:27]} + ((b[6] & c[6]) | ((~b[6]) & d[6])) + e[6] + w[6] + k[0] ;
e[7] = d[6];
d[7] = c[6];
c[7] = {b[6][1:0],b[6][31:2]};
b[7] = a[6];
a[7] = temp[6];
temp[7] = {a[7][26:0],a[7][31:27]} + ((b[7] & c[7]) | ((~b[7]) & d[7])) + e[7] + w[7] + k[0] ;
e[8] = d[7];
d[8] = c[7];
c[8] = {b[7][1:0],b[7][31:2]};
b[8] = a[7];
a[8] = temp[7];
temp[8] = {a[8][26:0],a[8][31:27]} + ((b[8] & c[8]) | ((~b[8]) & d[8])) + e[8] + w[8] + k[0] ;
e[9] = d[8];
d[9] = c[8];
c[9] = {b[8][1:0],b[8][31:2]};
b[9] = a[8];
a[9] = temp[8];
temp[9] = {a[9][26:0],a[9][31:27]} + ((b[9] & c[9]) | ((~b[9]) & d[9])) + e[9] + w[9] + k[0] ;
e[10] = d[9];
d[10] = c[9];
c[10] = {b[9][1:0],b[9][31:2]};
b[10] = a[9];
a[10] = temp[9];
temp[10] = {a[10][26:0],a[10][31:27]} + ((b[10] & c[10]) | ((~b[10]) & d[10])) + e[10] + w[10] + k[0] ;
e[11] = d[10];
d[11] = c[10];
c[11] = {b[10][1:0],b[10][31:2]};
b[11] = a[10];
a[11] = temp[10];
temp[11] = {a[11][26:0],a[11][31:27]} + ((b[11] & c[11]) | ((~b[11]) & d[11])) + e[11] + w[11] + k[0] ;
e[12] = d[11];
d[12] = c[11];
c[12] = {b[11][1:0],b[11][31:2]};
b[12] = a[11];
a[12] = temp[11];
temp[12] = {a[12][26:0],a[12][31:27]} + ((b[12] & c[12]) | ((~b[12]) & d[12])) + e[12] + w[12] + k[0] ;
e[13] = d[12];
d[13] = c[12];
c[13] = {b[12][1:0],b[12][31:2]};
b[13] = a[12];
a[13] = temp[12];
temp[13] = {a[13][26:0],a[13][31:27]} + ((b[13] & c[13]) | ((~b[13]) & d[13])) + e[13] + w[13] + k[0] ;
e[14] = d[13];
d[14] = c[13];
c[14] = {b[13][1:0],b[13][31:2]};
b[14] = a[13];
a[14] = temp[13];
temp[14] = {a[14][26:0],a[14][31:27]} + ((b[14] & c[14]) | ((~b[14]) & d[14])) + e[14] + w[14] + k[0] ;
e[15] = d[14];
d[15] = c[14];
c[15] = {b[14][1:0],b[14][31:2]};
b[15] = a[14];
a[15] = temp[14];
temp[15] = {a[15][26:0],a[15][31:27]} + ((b[15] & c[15]) | ((~b[15]) & d[15])) + e[15] + w[15] + k[0] ;
e[16] = d[15];
d[16] = c[15];
c[16] = {b[15][1:0],b[15][31:2]};
b[16] = a[15];
a[16] = temp[15];
temp[16] = {a[16][26:0],a[16][31:27]} + ((b[16] & c[16]) | ((~b[16]) & d[16])) + e[16] + w[16] + k[0] ;
e[17] = d[16];
d[17] = c[16];
c[17] = {b[16][1:0],b[16][31:2]};
b[17] = a[16];
a[17] = temp[16];
temp[17] = {a[17][26:0],a[17][31:27]} + ((b[17] & c[17]) | ((~b[17]) & d[17])) + e[17] + w[17] + k[0] ;
e[18] = d[17];
d[18] = c[17];
c[18] = {b[17][1:0],b[17][31:2]};
b[18] = a[17];
a[18] = temp[17];
temp[18] = {a[18][26:0],a[18][31:27]} + ((b[18] & c[18]) | ((~b[18]) & d[18])) + e[18] + w[18] + k[0] ;
e[19] = d[18];
d[19] = c[18];
c[19] = {b[18][1:0],b[18][31:2]};
b[19] = a[18];
a[19] = temp[18];
temp[19] = {a[19][26:0],a[19][31:27]} + ((b[19] & c[19]) | ((~b[19]) & d[19])) + e[19] + w[19] + k[0] ;
e[20] = d[19];
d[20] = c[19];
c[20] = {b[19][1:0],b[19][31:2]};
b[20] = a[19];
a[20] = temp[19];
flag = 5;
end else if(curr_state == SHA1_F1_ROUNDS) begin
temp[20] = {a[20][26:0],a[20][31:27]} + (b[20] ^ c[20] ^ d[20]) + e[20] + w[20] + k[1] ;
e[21] = d[20];
d[21] = c[20];
c[21] = {b[20][1:0],b[20][31:2]};
b[21] = a[20];
a[21] = temp[20];
temp[21] = {a[21][26:0],a[21][31:27]} + (b[21] ^ c[21] ^ d[21]) + e[21] + w[21] + k[1] ;
e[22] = d[21];
d[22] = c[21];
c[22] = {b[21][1:0],b[21][31:2]};
b[22] = a[21];
a[22] = temp[21];
temp[22] = {a[22][26:0],a[22][31:27]} + (b[22] ^ c[22] ^ d[22]) + e[22] + w[22] + k[1] ;
e[23] = d[22];
d[23] = c[22];
c[23] = {b[22][1:0],b[22][31:2]};
b[23] = a[22];
a[23] = temp[22];
temp[23] = {a[23][26:0],a[23][31:27]} + (b[23] ^ c[23] ^ d[23]) + e[23] + w[23] + k[1] ;
e[24] = d[23];
d[24] = c[23];
c[24] = {b[23][1:0],b[23][31:2]};
b[24] = a[23];
a[24] = temp[23];
temp[24] = {a[24][26:0],a[24][31:27]} + (b[24] ^ c[24] ^ d[24]) + e[24] + w[24] + k[1] ;
e[25] = d[24];
d[25] = c[24];
c[25] = {b[24][1:0],b[24][31:2]};
b[25] = a[24];
a[25] = temp[24];
temp[25] = {a[25][26:0],a[25][31:27]} + (b[25] ^ c[25] ^ d[25]) + e[25] + w[25] + k[1] ;
e[26] = d[25];
d[26] = c[25];
c[26] = {b[25][1:0],b[25][31:2]};
b[26] = a[25];
a[26] = temp[25];
temp[26] = {a[26][26:0],a[26][31:27]} + (b[26] ^ c[26] ^ d[26]) + e[26] + w[26] + k[1] ;
e[27] = d[26];
d[27] = c[26];
c[27] = {b[26][1:0],b[26][31:2]};
b[27] = a[26];
a[27] = temp[26];
temp[27] = {a[27][26:0],a[27][31:27]} + (b[27] ^ c[27] ^ d[27]) + e[27] + w[27] + k[1] ;
e[28] = d[27];
d[28] = c[27];
c[28] = {b[27][1:0],b[27][31:2]};
b[28] = a[27];
a[28] = temp[27];
temp[28] = {a[28][26:0],a[28][31:27]} + (b[28] ^ c[28] ^ d[28]) + e[28] + w[28] + k[1] ;
e[29] = d[28];
d[29] = c[28];
c[29] = {b[28][1:0],b[28][31:2]};
b[29] = a[28];
a[29] = temp[28];
temp[29] = {a[29][26:0],a[29][31:27]} + (b[29] ^ c[29] ^ d[29]) + e[29] + w[29] + k[1] ;
e[30] = d[29];
d[30] = c[29];
c[30] = {b[29][1:0],b[29][31:2]};
b[30] = a[29];
a[30] = temp[29];
temp[30] = {a[30][26:0],a[30][31:27]} + (b[30] ^ c[30] ^ d[30]) + e[30] + w[30] + k[1] ;
e[31] = d[30];
d[31] = c[30];
c[31] = {b[30][1:0],b[30][31:2]};
b[31] = a[30];
a[31] = temp[30];
temp[30] = {a[30][26:0],a[30][31:27]} + (b[30] ^ c[30] ^ d[30]) + e[30] + w[30] + k[1] ;
e[31] = d[30];
d[31] = c[30];
c[31] = {b[30][1:0],b[30][31:2]};
b[31] = a[30];
a[31] = temp[30];
temp[31] = {a[31][26:0],a[31][31:27]} + (b[31] ^ c[31] ^ d[31]) + e[31] + w[31] + k[1] ;
e[32] = d[31];
d[32] = c[31];
c[32] = {b[31][1:0],b[31][31:2]};
b[32] = a[31];
a[32] = temp[31];
temp[32] = {a[32][26:0],a[32][31:27]} + (b[32] ^ c[32] ^ d[32]) + e[32] + w[32] + k[1] ;
e[33] = d[32];
d[33] = c[32];
c[33] = {b[32][1:0],b[32][31:2]};
b[33] = a[32];
a[33] = temp[32];
temp[33] = {a[33][26:0],a[33][31:27]} + (b[33] ^ c[33] ^ d[33]) + e[33] + w[33] + k[1] ;
e[34] = d[33];
d[34] = c[33];
c[34] = {b[33][1:0],b[33][31:2]};
b[34] = a[33];
a[34] = temp[33];
temp[34] = {a[34][26:0],a[34][31:27]} + (b[34] ^ c[34] ^ d[34]) + e[34] + w[34] + k[1] ;
e[35] = d[34];
d[35] = c[34];
c[35] = {b[34][1:0],b[34][31:2]};
b[35] = a[34];
a[35] = temp[34];
temp[35] = {a[35][26:0],a[35][31:27]} + (b[35] ^ c[35] ^ d[35]) + e[35] + w[35] + k[1] ;
e[36] = d[35];
d[36] = c[35];
c[36] = {b[35][1:0],b[35][31:2]};
b[36] = a[35];
a[36] = temp[35];
temp[36] = {a[36][26:0],a[36][31:27]} + (b[36] ^ c[36] ^ d[36]) + e[36] + w[36] + k[1] ;
e[37] = d[36];
d[37] = c[36];
c[37] = {b[36][1:0],b[36][31:2]};
b[37] = a[36];
a[37] = temp[36];
temp[37] = {a[37][26:0],a[37][31:27]} + (b[37] ^ c[37] ^ d[37]) + e[37] + w[37] + k[1] ;
e[38] = d[37];
d[38] = c[37];
c[38] = {b[37][1:0],b[37][31:2]};
b[38] = a[37];
a[38] = temp[37];
temp[38] = {a[38][26:0],a[38][31:27]} + (b[38] ^ c[38] ^ d[38]) + e[38] + w[38] + k[1] ;
e[39] = d[38];
d[39] = c[38];
c[39] = {b[38][1:0],b[38][31:2]};
b[39] = a[38];
a[39] = temp[38];
temp[39] = {a[39][26:0],a[39][31:27]} + (b[39] ^ c[39] ^ d[39]) + e[39] + w[39] + k[1] ;
e[40] = d[39];
d[40] = c[39];
c[40] = {b[39][1:0],b[39][31:2]};
b[40] = a[39];
a[40] = temp[39];
flag = 6;
end else if(curr_state == SHA1_F2_ROUNDS) begin
temp[40] = {a[40][26:0],a[40][31:27]} + ((b[40]&c[40])|(b[40]&d[40])|(c[40]&d[40])) + e[40] + w[40] + k[2] ;
e[41] = d[40];
d[41] = c[40];
c[41] = {b[40][1:0],b[40][31:2]};
b[41] = a[40];
a[41] = temp[40];
temp[41] = {a[41][26:0],a[41][31:27]} + ((b[41]&c[41])|(b[41]&d[41])|(c[41]&d[41])) + e[41] + w[41] + k[2] ;
e[42] = d[41];
d[42] = c[41];
c[42] = {b[41][1:0],b[41][31:2]};
b[42] = a[41];
a[42] = temp[41];
temp[42] = {a[42][26:0],a[42][31:27]} + ((b[42]&c[42])|(b[42]&d[42])|(c[42]&d[42])) + e[42] + w[42] + k[2] ;
e[43] = d[42];
d[43] = c[42];
c[43] = {b[42][1:0],b[42][31:2]};
b[43] = a[42];
a[43] = temp[42];
temp[43] = {a[43][26:0],a[43][31:27]} + ((b[43]&c[43])|(b[43]&d[43])|(c[43]&d[43])) + e[43] + w[43] + k[2] ;
e[44] = d[43];
d[44] = c[43];
c[44] = {b[43][1:0],b[43][31:2]};
b[44] = a[43];
a[44] = temp[43];
temp[44] = {a[44][26:0],a[44][31:27]} + ((b[44]&c[44])|(b[44]&d[44])|(c[44]&d[44])) + e[44] + w[44] + k[2] ;
e[45] = d[44];
d[45] = c[44];
c[45] = {b[44][1:0],b[44][31:2]};
b[45] = a[44];
a[45] = temp[44];
temp[45] = {a[45][26:0],a[45][31:27]} + ((b[45]&c[45])|(b[45]&d[45])|(c[45]&d[45])) + e[45] + w[45] + k[2] ;
e[46] = d[45];
d[46] = c[45];
c[46] = {b[45][1:0],b[45][31:2]};
b[46] = a[45];
a[46] = temp[45];
temp[46] = {a[46][26:0],a[46][31:27]} + ((b[46]&c[46])|(b[46]&d[46])|(c[46]&d[46])) + e[46] + w[46] + k[2] ;
e[47] = d[46];
d[47] = c[46];
c[47] = {b[46][1:0],b[46][31:2]};
b[47] = a[46];
a[47] = temp[46];
temp[47] = {a[47][26:0],a[47][31:27]} + ((b[47]&c[47])|(b[47]&d[47])|(c[47]&d[47])) + e[47] + w[47] + k[2] ;
e[48] = d[47];
d[48] = c[47];
c[48] = {b[47][1:0],b[47][31:2]};
b[48] = a[47];
a[48] = temp[47];
temp[48] = {a[48][26:0],a[48][31:27]} + ((b[48]&c[48])|(b[48]&d[48])|(c[48]&d[48])) + e[48] + w[48] + k[2] ;
e[49] = d[48];
d[49] = c[48];
c[49] = {b[48][1:0],b[48][31:2]};
b[49] = a[48];
a[49] = temp[48];
temp[49] = {a[49][26:0],a[49][31:27]} + ((b[49]&c[49])|(b[49]&d[49])|(c[49]&d[49])) + e[49] + w[49] + k[2] ;
e[50] = d[49];
d[50] = c[49];
c[50] = {b[49][1:0],b[49][31:2]};
b[50] = a[49];
a[50] = temp[49];
temp[50] = {a[50][26:0],a[50][31:27]} + ((b[50]&c[50])|(b[50]&d[50])|(c[50]&d[50])) + e[50] + w[50] + k[2] ;
e[51] = d[50];
d[51] = c[50];
c[51] = {b[50][1:0],b[50][31:2]};
b[51] = a[50];
a[51] = temp[50];
temp[51] = {a[51][26:0],a[51][31:27]} + ((b[51]&c[51])|(b[51]&d[51])|(c[51]&d[51])) + e[51] + w[51] + k[2] ;
e[52] = d[51];
d[52] = c[51];
c[52] = {b[51][1:0],b[51][31:2]};
b[52] = a[51];
a[52] = temp[51];
temp[52] = {a[52][26:0],a[52][31:27]} + ((b[52]&c[52])|(b[52]&d[52])|(c[52]&d[52])) + e[52] + w[52] + k[2] ;
e[53] = d[52];
d[53] = c[52];
c[53] = {b[52][1:0],b[52][31:2]};
b[53] = a[52];
a[53] = temp[52];
temp[53] = {a[53][26:0],a[53][31:27]} + ((b[53]&c[53])|(b[53]&d[53])|(c[53]&d[53])) + e[53] + w[53] + k[2] ;
e[54] = d[53];
d[54] = c[53];
c[54] = {b[53][1:0],b[53][31:2]};
b[54] = a[53];
a[54] = temp[53];
temp[54] = {a[54][26:0],a[54][31:27]} + ((b[54]&c[54])|(b[54]&d[54])|(c[54]&d[54])) + e[54] + w[54] + k[2] ;
e[55] = d[54];
d[55] = c[54];
c[55] = {b[54][1:0],b[54][31:2]};
b[55] = a[54];
a[55] = temp[54];
temp[55] = {a[55][26:0],a[55][31:27]} + ((b[55]&c[55])|(b[55]&d[55])|(c[55]&d[55])) + e[55] + w[55] + k[2] ;
e[56] = d[55];
d[56] = c[55];
c[56] = {b[55][1:0],b[55][31:2]};
b[56] = a[55];
a[56] = temp[55];
temp[56] = {a[56][26:0],a[56][31:27]} + ((b[56]&c[56])|(b[56]&d[56])|(c[56]&d[56])) + e[56] + w[56] + k[2] ;
e[57] = d[56];
d[57] = c[56];
c[57] = {b[56][1:0],b[56][31:2]};
b[57] = a[56];
a[57] = temp[56];
temp[57] = {a[57][26:0],a[57][31:27]} + ((b[57]&c[57])|(b[57]&d[57])|(c[57]&d[57])) + e[57] + w[57] + k[2] ;
e[58] = d[57];
d[58] = c[57];
c[58] = {b[57][1:0],b[57][31:2]};
b[58] = a[57];
a[58] = temp[57];
temp[58] = {a[58][26:0],a[58][31:27]} + ((b[58]&c[58])|(b[58]&d[58])|(c[58]&d[58])) + e[58] + w[58] + k[2] ;
e[59] = d[58];
d[59] = c[58];
c[59] = {b[58][1:0],b[58][31:2]};
b[59] = a[58];
a[59] = temp[58];
temp[59] = {a[59][26:0],a[59][31:27]} + ((b[59]&c[59])|(b[59]&d[59])|(c[59]&d[59])) + e[59] + w[59] + k[2] ;
e[60] = d[59];
d[60] = c[59];
c[60] = {b[59][1:0],b[59][31:2]};
b[60] = a[59];
a[60] = temp[59];
flag = 7;
end else if(curr_state == SHA1_F3_ROUNDS) begin
temp[60] = {a[60][26:0],a[60][31:27]} + (b[60]^c[60]^d[60]) + e[60] + w[60] + k[3] ;
e[61] = d[60];
d[61] = c[60];
c[61] = {b[60][1:0],b[60][31:2]};
b[61] = a[60];
a[61] = temp[60];
temp[61] = {a[61][26:0],a[61][31:27]} + (b[61]^c[61]^d[61]) + e[61] + w[61] + k[3] ;
e[62] = d[61];
d[62] = c[61];
c[62] = {b[61][1:0],b[61][31:2]};
b[62] = a[61];
a[62] = temp[61];
temp[62] = {a[62][26:0],a[62][31:27]} + (b[62]^c[62]^d[62]) + e[62] + w[62] + k[3] ;
e[63] = d[62];
d[63] = c[62];
c[63] = {b[62][1:0],b[62][31:2]};
b[63] = a[62];
a[63] = temp[62];
temp[63] = {a[63][26:0],a[63][31:27]} + (b[63]^c[63]^d[63]) + e[63] + w[63] + k[3] ;
e[64] = d[63];
d[64] = c[63];
c[64] = {b[63][1:0],b[63][31:2]};
b[64] = a[63];
a[64] = temp[63];
temp[64] = {a[64][26:0],a[64][31:27]} + (b[64]^c[64]^d[64]) + e[64] + w[64] + k[3] ;
e[65] = d[64];
d[65] = c[64];
c[65] = {b[64][1:0],b[64][31:2]};
b[65] = a[64];
a[65] = temp[64];
temp[65] = {a[65][26:0],a[65][31:27]} + (b[65]^c[65]^d[65]) + e[65] + w[65] + k[3] ;
e[66] = d[65];
d[66] = c[65];
c[66] = {b[65][1:0],b[65][31:2]};
b[66] = a[65];
a[66] = temp[65];
temp[66] = {a[66][26:0],a[66][31:27]} + (b[66]^c[66]^d[66]) + e[66] + w[66] + k[3] ;
e[67] = d[66];
d[67] = c[66];
c[67] = {b[66][1:0],b[66][31:2]};
b[67] = a[66];
a[67] = temp[66];
temp[67] = {a[67][26:0],a[67][31:27]} + (b[67]^c[67]^d[67]) + e[67] + w[67] + k[3] ;
e[68] = d[67];
d[68] = c[67];
c[68] = {b[67][1:0],b[67][31:2]};
b[68] = a[67];
a[68] = temp[67];
temp[68] = {a[68][26:0],a[68][31:27]} + (b[68]^c[68]^d[68]) + e[68] + w[68] + k[3] ;
e[69] = d[68];
d[69] = c[68];
c[69] = {b[68][1:0],b[68][31:2]};
b[69] = a[68];
a[69] = temp[68];
temp[69] = {a[69][26:0],a[69][31:27]} + (b[69]^c[69]^d[69]) + e[69] + w[69] + k[3] ;
e[70] = d[69];
d[70] = c[69];
c[70] = {b[69][1:0],b[69][31:2]};
b[70] = a[69];
a[70] = temp[69];
temp[70] = {a[70][26:0],a[70][31:27]} + (b[70]^c[70]^d[70]) + e[70] + w[70] + k[3] ;
e[71] = d[70];
d[71] = c[70];
c[71] = {b[70][1:0],b[70][31:2]};
b[71] = a[70];
a[71] = temp[70];
temp[71] = {a[71][26:0],a[71][31:27]} + (b[71]^c[71]^d[71]) + e[71] + w[71] + k[3] ;
e[72] = d[71];
d[72] = c[71];
c[72] = {b[71][1:0],b[71][31:2]};
b[72] = a[71];
a[72] = temp[71];
temp[72] = {a[72][26:0],a[72][31:27]} + (b[72]^c[72]^d[72]) + e[72] + w[72] + k[3] ;
e[73] = d[72];
d[73] = c[72];
c[73] = {b[72][1:0],b[72][31:2]};
b[73] = a[72];
a[73] = temp[72];
temp[73] = {a[73][26:0],a[73][31:27]} + (b[73]^c[73]^d[73]) + e[73] + w[73] + k[3] ;
e[74] = d[73];
d[74] = c[73];
c[74] = {b[73][1:0],b[73][31:2]};
b[74] = a[73];
a[74] = temp[73];
temp[74] = {a[74][26:0],a[74][31:27]} + (b[74]^c[74]^d[74]) + e[74] + w[74] + k[3] ;
e[75] = d[74];
d[75] = c[74];
c[75] = {b[74][1:0],b[74][31:2]};
b[75] = a[74];
a[75] = temp[74];
temp[75] = {a[75][26:0],a[75][31:27]} + (b[75]^c[75]^d[75]) + e[75] + w[75] + k[3] ;
e[76] = d[75];
d[76] = c[75];
c[76] = {b[75][1:0],b[75][31:2]};
b[76] = a[75];
a[76] = temp[75];
temp[76] = {a[76][26:0],a[76][31:27]} + (b[76]^c[76]^d[76]) + e[76] + w[76] + k[3] ;
e[77] = d[76];
d[77] = c[76];
c[77] = {b[76][1:0],b[76][31:2]};
b[77] = a[76];
a[77] = temp[76];
temp[77] = {a[77][26:0],a[77][31:27]} + (b[77]^c[77]^d[77]) + e[77] + w[77] + k[3] ;
e[78] = d[77];
d[78] = c[77];
c[78] = {b[77][1:0],b[77][31:2]};
b[78] = a[77];
a[78] = temp[77];
temp[78] = {a[78][26:0],a[78][31:27]} + (b[78]^c[78]^d[78]) + e[78] + w[78] + k[3] ;
e[79] = d[78];
d[79] = c[78];
c[79] = {b[78][1:0],b[78][31:2]};
b[79] = a[78];
a[79] = temp[78];
temp[79] = {a[79][26:0],a[79][31:27]} + (b[79]^c[79]^d[79]) + e[79] + w[79] + k[3] ;
e[80] = d[79];
d[80] = c[79];
c[80] = {b[79][1:0],b[79][31:2]};
b[80] = a[79];
a[80] = temp[79];
flag = 8;
end else if(curr_state == SHA1_FINAL) begin
hash[0] = h[0] + a[80];
hash[1] = h[1] + b[80];
hash[2] = h[2] + c[80];
hash[3] = h[3] + d[80];
hash[4] = h[4] + e[80];
flag = 9;
end else if(curr_state == SHA1_DIGEST) begin
digest_out = {hash[0],hash[1],hash[2],hash[3],hash[4]};
digest_done = 1;
end else begin end
end
endmodule | module SHA1_core(
input clk,
input rst,
input initial_hash_start,
input [159:0]initial_hash,
input msg_in_start,
input [9:0]msg_len,
input [511:0]msg,
output reg digest_done,
output reg [159:0]digest_out
); |
reg [31:0]a[80:0],b[80:0],c[80:0],d[80:0],e[80:0];
reg [31:0]h[4:0];
reg [31:0]hash[4:0];
reg [31:0]k[3:0];
reg [31:0]w[79:0];
reg [31:0]wt[63:0];
reg [31:0]temp[79:0];
reg [511:0]temp1;
reg [3:0] curr_state, next_state;
reg [3:0] flag;
parameter SHA1_RESET = 0;
parameter SHA1_INIT = 1;
parameter SHA1_W_ROUNDS = 2;
parameter SHA1_ABCDE_INIT = 3;
parameter SHA1_F0_ROUNDS = 4;
parameter SHA1_F1_ROUNDS = 5;
parameter SHA1_F2_ROUNDS = 6;
parameter SHA1_F3_ROUNDS = 7;
parameter SHA1_FINAL = 8;
parameter SHA1_DIGEST = 9;
initial
flag = 0;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
curr_state <= SHA1_RESET;
end else begin
curr_state <= next_state;
end
end
always@(*) begin
if(flag == 1)
next_state = SHA1_INIT;
else if(flag == 2)
next_state = SHA1_W_ROUNDS;
else if(flag == 3)
next_state = SHA1_ABCDE_INIT;
else if(flag == 4)
next_state = SHA1_F0_ROUNDS;
else if(flag == 5)
next_state = SHA1_F1_ROUNDS;
else if(flag == 6)
next_state = SHA1_F2_ROUNDS;
else if(flag == 7)
next_state = SHA1_F3_ROUNDS;
else if(flag == 8)
next_state = SHA1_FINAL;
else if(flag == 9)
next_state = SHA1_DIGEST;
else begin end
end
always@(*) begin
if(curr_state == SHA1_RESET) begin
h[0] = 0;
h[1] = 0;
h[2] = 0;
h[3] = 0;
h[4] = 0;
w[0] = 0;w[1] = 0;w[2] = 0;w[3] = 0;w[4] = 0;w[5] = 0;w[6] = 0;w[7] = 0;w[8] = 0;w[9] = 0;
w[10] = 0;w[11] = 0;w[12] = 0;w[13] = 0;w[14] = 0;w[15] = 0;w[16] = 0;w[17] = 0;w[18] = 0;w[19] = 0;
w[20] = 0;w[21] = 0;w[22] = 0;w[23] = 0;w[24] = 0;w[25] = 0;w[26] = 0;w[27] = 0;w[28] = 0;w[29] = 0;
w[30] = 0;w[31] = 0;w[32] = 0;w[33] = 0;w[34] = 0;w[35] = 0;w[36] = 0;w[37] = 0;w[38] = 0;w[39] = 0;
w[40] = 0;w[41] = 0;w[42] = 0;w[43] = 0;w[44] = 0;w[45] = 0;w[46] = 0;w[47] = 0;w[48] = 0;w[49] = 0;
w[50] = 0;w[51] = 0;w[52] = 0;w[53] = 0;w[54] = 0;w[55] = 0;w[56] = 0;w[57] = 0;w[58] = 0;w[59] = 0;
w[60] = 0;w[61] = 0;w[62] = 0;w[63] = 0;w[64] = 0;w[65] = 0;w[66] = 0;w[67] = 0;w[68] = 0;w[69] = 0;
w[70] = 0;w[71] = 0;w[72] = 0;w[73] = 0;w[74] = 0;w[75] = 0;w[76] = 0;w[77] = 0;w[78] = 0;w[79] = 0;
flag = 1;
end else if(curr_state == SHA1_INIT) begin
k[0] = 32'h5a827999;
k[1] = 32'h6ed9eba1;
k[2] = 32'h8f1bbcdc;
k[3] = 32'hca62c1d6;
if(initial_hash_start)begin
h[4] = initial_hash[31:0];
h[3] = initial_hash[63:32];
h[2] = initial_hash[95:64];
h[1] = initial_hash[127:96];
h[0] = initial_hash[159:128];
end
if(msg_in_start)begin
temp1 = msg|(1<<(511-msg_len))|msg_len;
w[0] = temp1[511:480];
w[1] = temp1[479:448];
w[2] = temp1[447:416];
w[3] = temp1[415:384];
w[4] = temp1[383:352];
w[5] = temp1[351:320];
w[6] = temp1[319:288];
w[7] = temp1[287:256];
w[8] = temp1[255:224];
w[9] = temp1[223:192];
w[10] = temp1[191:160];
w[11] = temp1[159:128];
w[12] = temp1[127:96];
w[13] = temp1[95:64];
w[14] = temp1[63:32];
w[15] = temp1[31:0];
flag = 2;
end
end else if(curr_state == SHA1_W_ROUNDS) begin
wt[0] = w[13]^w[8]^w[2]^w[0];
w[16] = {wt[0][30:0],wt[0][31]};
wt[1] = w[14]^w[9]^w[3]^w[1];
w[17] = {wt[1][30:0],wt[1][31]};
wt[2] = w[15]^w[10]^w[4]^w[2];
w[18] = {wt[2][30:0],wt[2][31]};
wt[3] = w[16]^w[11]^w[5]^w[3];
w[19] = {wt[3][30:0],wt[3][31]};
wt[4] = w[17]^w[12]^w[6]^w[4];
w[20] = {wt[4][30:0],wt[4][31]};
wt[5] = w[18]^w[13]^w[7]^w[5];
w[21] = {wt[5][30:0],wt[5][31]};
wt[6] = w[19]^w[14]^w[8]^w[6];
w[22] = {wt[6][30:0],wt[6][31]};
wt[7] = w[20]^w[15]^w[9]^w[7];
w[23] = {wt[7][30:0],wt[7][31]};
wt[8] = w[21]^w[16]^w[10]^w[8];
w[24] = {wt[8][30:0],wt[8][31]};
wt[9] = w[22]^w[17]^w[11]^w[9];
w[25] = {wt[9][30:0],wt[9][31]};
wt[10] = w[23]^w[18]^w[12]^w[10];
w[26] = {wt[10][30:0],wt[10][31]};
wt[11] = w[24]^w[19]^w[13]^w[11];
w[27] = {wt[11][30:0],wt[11][31]};
wt[12] = w[25]^w[20]^w[14]^w[12];
w[28] = {wt[12][30:0],wt[12][31]};
wt[13] = w[26]^w[21]^w[15]^w[13];
w[29] = {wt[13][30:0],wt[13][31]};
wt[14] = w[27]^w[22]^w[16]^w[14];
w[30] = {wt[14][30:0],wt[14][31]};
wt[15] = w[28]^w[23]^w[17]^w[15];
w[31] = {wt[15][30:0],wt[15][31]};
wt[16] = w[29]^w[24]^w[18]^w[16];
w[32] = {wt[16][30:0],wt[16][31]};
wt[17] = w[30]^w[25]^w[19]^w[17];
w[33] = {wt[17][30:0],wt[17][31]};
wt[18] = w[31]^w[26]^w[20]^w[18];
w[34] = {wt[18][30:0],wt[18][31]};
wt[19] = w[32]^w[27]^w[21]^w[19];
w[35] = {wt[19][30:0],wt[19][31]};
wt[20] = w[33]^w[28]^w[22]^w[20];
w[36] = {wt[20][30:0],wt[20][31]};
wt[21] = w[34]^w[29]^w[23]^w[21];
w[37] = {wt[21][30:0],wt[21][31]};
wt[22] = w[35]^w[30]^w[24]^w[22];
w[38] = {wt[22][30:0],wt[22][31]};
wt[23] = w[36]^w[31]^w[25]^w[23];
w[39] = {wt[23][30:0],wt[23][31]};
wt[24] = w[37]^w[32]^w[26]^w[24];
w[40] = {wt[24][30:0],wt[24][31]};
wt[25] = w[38]^w[33]^w[27]^w[25];
w[41] = {wt[25][30:0],wt[25][31]};
wt[26] = w[39]^w[34]^w[28]^w[26];
w[42] = {wt[26][30:0],wt[26][31]};
wt[27] = w[40]^w[35]^w[29]^w[27];
w[43] = {wt[27][30:0],wt[27][31]};
wt[28] = w[41]^w[36]^w[30]^w[28];
w[44] = {wt[28][30:0],wt[28][31]};
wt[29] = w[42]^w[37]^w[31]^w[29];
w[45] = {wt[29][30:0],wt[29][31]};
wt[30] = w[43]^w[38]^w[32]^w[30];
w[46] = {wt[30][30:0],wt[30][31]};
wt[31] = w[44]^w[39]^w[33]^w[31];
w[47] = {wt[31][30:0],wt[31][31]};
wt[32] = w[45]^w[40]^w[34]^w[32];
w[48] = {wt[32][30:0],wt[32][31]};
wt[33] = w[46]^w[41]^w[35]^w[33];
w[49] = {wt[33][30:0],wt[33][31]};
wt[34] = w[47]^w[42]^w[36]^w[34];
w[50] = {wt[34][30:0],wt[34][31]};
wt[35] = w[48]^w[43]^w[37]^w[35];
w[51] = {wt[35][30:0],wt[35][31]};
wt[36] = w[49]^w[44]^w[38]^w[36];
w[52] = {wt[36][30:0],wt[36][31]};
wt[37] = w[50]^w[45]^w[39]^w[37];
w[53] = {wt[37][30:0],wt[37][31]};
wt[38] = w[51]^w[46]^w[40]^w[38];
w[54] = {wt[38][30:0],wt[38][31]};
wt[39] = w[52]^w[47]^w[41]^w[39];
w[55] = {wt[39][30:0],wt[39][31]};
wt[40] = w[53]^w[48]^w[42]^w[40];
w[56] = {wt[40][30:0],wt[40][31]};
wt[41] = w[54]^w[49]^w[43]^w[41];
w[57] = {wt[41][30:0],wt[41][31]};
wt[42] = w[55]^w[50]^w[44]^w[42];
w[58] = {wt[42][30:0],wt[42][31]};
wt[43] = w[56]^w[51]^w[45]^w[43];
w[59] = {wt[43][30:0],wt[43][31]};
wt[44] = w[57]^w[52]^w[46]^w[44];
w[60] = {wt[44][30:0],wt[44][31]};
wt[45] = w[58]^w[53]^w[47]^w[45];
w[61] = {wt[45][30:0],wt[45][31]};
wt[46] = w[59]^w[54]^w[48]^w[46];
w[62] = {wt[46][30:0],wt[46][31]};
wt[47] = w[60]^w[55]^w[49]^w[47];
w[63] = {wt[47][30:0],wt[47][31]};
wt[48] = w[61]^w[56]^w[50]^w[48];
w[64] = {wt[48][30:0],wt[48][31]};
wt[49] = w[62]^w[57]^w[51]^w[49];
w[65] = {wt[49][30:0],wt[49][31]};
wt[50] = w[63]^w[58]^w[52]^w[50];
w[66] = {wt[50][30:0],wt[50][31]};
wt[51] = w[64]^w[59]^w[53]^w[51];
w[67] = {wt[51][30:0],wt[51][31]};
wt[52] = w[65]^w[60]^w[54]^w[52];
w[68] = {wt[52][30:0],wt[52][31]};
wt[53] = w[66]^w[61]^w[55]^w[53];
w[69] = {wt[53][30:0],wt[53][31]};
wt[54] = w[67]^w[62]^w[56]^w[54];
w[70] = {wt[54][30:0],wt[54][31]};
wt[55] = w[68]^w[63]^w[57]^w[55];
w[71] = {wt[55][30:0],wt[55][31]};
wt[56] = w[69]^w[64]^w[58]^w[56];
w[72] = {wt[56][30:0],wt[56][31]};
wt[57] = w[70]^w[65]^w[59]^w[57];
w[73] = {wt[57][30:0],wt[57][31]};
wt[58] = w[71]^w[66]^w[60]^w[58];
w[74] = {wt[58][30:0],wt[58][31]};
wt[59] = w[72]^w[67]^w[61]^w[59];
w[75] = {wt[59][30:0],wt[59][31]};
wt[60] = w[73]^w[68]^w[62]^w[60];
w[76] = {wt[60][30:0],wt[60][31]};
wt[61] = w[74]^w[69]^w[63]^w[61];
w[77] = {wt[61][30:0],wt[61][31]};
wt[62] = w[75]^w[70]^w[64]^w[62];
w[78] = {wt[62][30:0],wt[62][31]};
wt[63] = w[76]^w[71]^w[65]^w[63];
w[79] = {wt[63][30:0],wt[63][31]};
flag = 3;
end else if(curr_state == SHA1_ABCDE_INIT) begin
a[0] = h[0];
b[0] = h[1];
c[0] = h[2];
d[0] = h[3];
e[0] = h[4];
flag = 4;
end else if(curr_state == SHA1_F0_ROUNDS) begin
temp[0] = {a[0][26:0],a[0][31:27]} + ((b[0] & c[0]) | ((~b[0]) & d[0])) + e[0] + w[0] + k[0] ;
e[1] = d[0];
d[1] = c[0];
c[1] = {b[0][1:0],b[0][31:2]};
b[1] = a[0];
a[1] = temp[0];
temp[1] = {a[1][26:0],a[1][31:27]} + ((b[1] & c[1]) | ((~b[1]) & d[1])) + e[1] + w[1] + k[0] ;
e[2] = d[1];
d[2] = c[1];
c[2] = {b[1][1:0],b[1][31:2]};
b[2] = a[1];
a[2] = temp[1];
temp[2] = {a[2][26:0],a[2][31:27]} + ((b[2] & c[2]) | ((~b[2]) & d[2])) + e[2] + w[2] + k[0] ;
e[3] = d[2];
d[3] = c[2];
c[3] = {b[2][1:0],b[2][31:2]};
b[3] = a[2];
a[3] = temp[2];
temp[3] = {a[3][26:0],a[3][31:27]} + ((b[3] & c[3]) | ((~b[3]) & d[3])) + e[3] + w[3] + k[0] ;
e[4] = d[3];
d[4] = c[3];
c[4] = {b[3][1:0],b[3][31:2]};
b[4] = a[3];
a[4] = temp[3];
temp[4] = {a[4][26:0],a[4][31:27]} + ((b[4] & c[4]) | ((~b[4]) & d[4])) + e[4] + w[4] + k[0] ;
e[5] = d[4];
d[5] = c[4];
c[5] = {b[4][1:0],b[4][31:2]};
b[5] = a[4];
a[5] = temp[4];
temp[5] = {a[5][26:0],a[5][31:27]} + ((b[5] & c[5]) | ((~b[5]) & d[5])) + e[5] + w[5] + k[0] ;
e[6] = d[5];
d[6] = c[5];
c[6] = {b[5][1:0],b[5][31:2]};
b[6] = a[5];
a[6] = temp[5];
temp[6] = {a[6][26:0],a[6][31:27]} + ((b[6] & c[6]) | ((~b[6]) & d[6])) + e[6] + w[6] + k[0] ;
e[7] = d[6];
d[7] = c[6];
c[7] = {b[6][1:0],b[6][31:2]};
b[7] = a[6];
a[7] = temp[6];
temp[7] = {a[7][26:0],a[7][31:27]} + ((b[7] & c[7]) | ((~b[7]) & d[7])) + e[7] + w[7] + k[0] ;
e[8] = d[7];
d[8] = c[7];
c[8] = {b[7][1:0],b[7][31:2]};
b[8] = a[7];
a[8] = temp[7];
temp[8] = {a[8][26:0],a[8][31:27]} + ((b[8] & c[8]) | ((~b[8]) & d[8])) + e[8] + w[8] + k[0] ;
e[9] = d[8];
d[9] = c[8];
c[9] = {b[8][1:0],b[8][31:2]};
b[9] = a[8];
a[9] = temp[8];
temp[9] = {a[9][26:0],a[9][31:27]} + ((b[9] & c[9]) | ((~b[9]) & d[9])) + e[9] + w[9] + k[0] ;
e[10] = d[9];
d[10] = c[9];
c[10] = {b[9][1:0],b[9][31:2]};
b[10] = a[9];
a[10] = temp[9];
temp[10] = {a[10][26:0],a[10][31:27]} + ((b[10] & c[10]) | ((~b[10]) & d[10])) + e[10] + w[10] + k[0] ;
e[11] = d[10];
d[11] = c[10];
c[11] = {b[10][1:0],b[10][31:2]};
b[11] = a[10];
a[11] = temp[10];
temp[11] = {a[11][26:0],a[11][31:27]} + ((b[11] & c[11]) | ((~b[11]) & d[11])) + e[11] + w[11] + k[0] ;
e[12] = d[11];
d[12] = c[11];
c[12] = {b[11][1:0],b[11][31:2]};
b[12] = a[11];
a[12] = temp[11];
temp[12] = {a[12][26:0],a[12][31:27]} + ((b[12] & c[12]) | ((~b[12]) & d[12])) + e[12] + w[12] + k[0] ;
e[13] = d[12];
d[13] = c[12];
c[13] = {b[12][1:0],b[12][31:2]};
b[13] = a[12];
a[13] = temp[12];
temp[13] = {a[13][26:0],a[13][31:27]} + ((b[13] & c[13]) | ((~b[13]) & d[13])) + e[13] + w[13] + k[0] ;
e[14] = d[13];
d[14] = c[13];
c[14] = {b[13][1:0],b[13][31:2]};
b[14] = a[13];
a[14] = temp[13];
temp[14] = {a[14][26:0],a[14][31:27]} + ((b[14] & c[14]) | ((~b[14]) & d[14])) + e[14] + w[14] + k[0] ;
e[15] = d[14];
d[15] = c[14];
c[15] = {b[14][1:0],b[14][31:2]};
b[15] = a[14];
a[15] = temp[14];
temp[15] = {a[15][26:0],a[15][31:27]} + ((b[15] & c[15]) | ((~b[15]) & d[15])) + e[15] + w[15] + k[0] ;
e[16] = d[15];
d[16] = c[15];
c[16] = {b[15][1:0],b[15][31:2]};
b[16] = a[15];
a[16] = temp[15];
temp[16] = {a[16][26:0],a[16][31:27]} + ((b[16] & c[16]) | ((~b[16]) & d[16])) + e[16] + w[16] + k[0] ;
e[17] = d[16];
d[17] = c[16];
c[17] = {b[16][1:0],b[16][31:2]};
b[17] = a[16];
a[17] = temp[16];
temp[17] = {a[17][26:0],a[17][31:27]} + ((b[17] & c[17]) | ((~b[17]) & d[17])) + e[17] + w[17] + k[0] ;
e[18] = d[17];
d[18] = c[17];
c[18] = {b[17][1:0],b[17][31:2]};
b[18] = a[17];
a[18] = temp[17];
temp[18] = {a[18][26:0],a[18][31:27]} + ((b[18] & c[18]) | ((~b[18]) & d[18])) + e[18] + w[18] + k[0] ;
e[19] = d[18];
d[19] = c[18];
c[19] = {b[18][1:0],b[18][31:2]};
b[19] = a[18];
a[19] = temp[18];
temp[19] = {a[19][26:0],a[19][31:27]} + ((b[19] & c[19]) | ((~b[19]) & d[19])) + e[19] + w[19] + k[0] ;
e[20] = d[19];
d[20] = c[19];
c[20] = {b[19][1:0],b[19][31:2]};
b[20] = a[19];
a[20] = temp[19];
flag = 5;
end else if(curr_state == SHA1_F1_ROUNDS) begin
temp[20] = {a[20][26:0],a[20][31:27]} + (b[20] ^ c[20] ^ d[20]) + e[20] + w[20] + k[1] ;
e[21] = d[20];
d[21] = c[20];
c[21] = {b[20][1:0],b[20][31:2]};
b[21] = a[20];
a[21] = temp[20];
temp[21] = {a[21][26:0],a[21][31:27]} + (b[21] ^ c[21] ^ d[21]) + e[21] + w[21] + k[1] ;
e[22] = d[21];
d[22] = c[21];
c[22] = {b[21][1:0],b[21][31:2]};
b[22] = a[21];
a[22] = temp[21];
temp[22] = {a[22][26:0],a[22][31:27]} + (b[22] ^ c[22] ^ d[22]) + e[22] + w[22] + k[1] ;
e[23] = d[22];
d[23] = c[22];
c[23] = {b[22][1:0],b[22][31:2]};
b[23] = a[22];
a[23] = temp[22];
temp[23] = {a[23][26:0],a[23][31:27]} + (b[23] ^ c[23] ^ d[23]) + e[23] + w[23] + k[1] ;
e[24] = d[23];
d[24] = c[23];
c[24] = {b[23][1:0],b[23][31:2]};
b[24] = a[23];
a[24] = temp[23];
temp[24] = {a[24][26:0],a[24][31:27]} + (b[24] ^ c[24] ^ d[24]) + e[24] + w[24] + k[1] ;
e[25] = d[24];
d[25] = c[24];
c[25] = {b[24][1:0],b[24][31:2]};
b[25] = a[24];
a[25] = temp[24];
temp[25] = {a[25][26:0],a[25][31:27]} + (b[25] ^ c[25] ^ d[25]) + e[25] + w[25] + k[1] ;
e[26] = d[25];
d[26] = c[25];
c[26] = {b[25][1:0],b[25][31:2]};
b[26] = a[25];
a[26] = temp[25];
temp[26] = {a[26][26:0],a[26][31:27]} + (b[26] ^ c[26] ^ d[26]) + e[26] + w[26] + k[1] ;
e[27] = d[26];
d[27] = c[26];
c[27] = {b[26][1:0],b[26][31:2]};
b[27] = a[26];
a[27] = temp[26];
temp[27] = {a[27][26:0],a[27][31:27]} + (b[27] ^ c[27] ^ d[27]) + e[27] + w[27] + k[1] ;
e[28] = d[27];
d[28] = c[27];
c[28] = {b[27][1:0],b[27][31:2]};
b[28] = a[27];
a[28] = temp[27];
temp[28] = {a[28][26:0],a[28][31:27]} + (b[28] ^ c[28] ^ d[28]) + e[28] + w[28] + k[1] ;
e[29] = d[28];
d[29] = c[28];
c[29] = {b[28][1:0],b[28][31:2]};
b[29] = a[28];
a[29] = temp[28];
temp[29] = {a[29][26:0],a[29][31:27]} + (b[29] ^ c[29] ^ d[29]) + e[29] + w[29] + k[1] ;
e[30] = d[29];
d[30] = c[29];
c[30] = {b[29][1:0],b[29][31:2]};
b[30] = a[29];
a[30] = temp[29];
temp[30] = {a[30][26:0],a[30][31:27]} + (b[30] ^ c[30] ^ d[30]) + e[30] + w[30] + k[1] ;
e[31] = d[30];
d[31] = c[30];
c[31] = {b[30][1:0],b[30][31:2]};
b[31] = a[30];
a[31] = temp[30];
temp[30] = {a[30][26:0],a[30][31:27]} + (b[30] ^ c[30] ^ d[30]) + e[30] + w[30] + k[1] ;
e[31] = d[30];
d[31] = c[30];
c[31] = {b[30][1:0],b[30][31:2]};
b[31] = a[30];
a[31] = temp[30];
temp[31] = {a[31][26:0],a[31][31:27]} + (b[31] ^ c[31] ^ d[31]) + e[31] + w[31] + k[1] ;
e[32] = d[31];
d[32] = c[31];
c[32] = {b[31][1:0],b[31][31:2]};
b[32] = a[31];
a[32] = temp[31];
temp[32] = {a[32][26:0],a[32][31:27]} + (b[32] ^ c[32] ^ d[32]) + e[32] + w[32] + k[1] ;
e[33] = d[32];
d[33] = c[32];
c[33] = {b[32][1:0],b[32][31:2]};
b[33] = a[32];
a[33] = temp[32];
temp[33] = {a[33][26:0],a[33][31:27]} + (b[33] ^ c[33] ^ d[33]) + e[33] + w[33] + k[1] ;
e[34] = d[33];
d[34] = c[33];
c[34] = {b[33][1:0],b[33][31:2]};
b[34] = a[33];
a[34] = temp[33];
temp[34] = {a[34][26:0],a[34][31:27]} + (b[34] ^ c[34] ^ d[34]) + e[34] + w[34] + k[1] ;
e[35] = d[34];
d[35] = c[34];
c[35] = {b[34][1:0],b[34][31:2]};
b[35] = a[34];
a[35] = temp[34];
temp[35] = {a[35][26:0],a[35][31:27]} + (b[35] ^ c[35] ^ d[35]) + e[35] + w[35] + k[1] ;
e[36] = d[35];
d[36] = c[35];
c[36] = {b[35][1:0],b[35][31:2]};
b[36] = a[35];
a[36] = temp[35];
temp[36] = {a[36][26:0],a[36][31:27]} + (b[36] ^ c[36] ^ d[36]) + e[36] + w[36] + k[1] ;
e[37] = d[36];
d[37] = c[36];
c[37] = {b[36][1:0],b[36][31:2]};
b[37] = a[36];
a[37] = temp[36];
temp[37] = {a[37][26:0],a[37][31:27]} + (b[37] ^ c[37] ^ d[37]) + e[37] + w[37] + k[1] ;
e[38] = d[37];
d[38] = c[37];
c[38] = {b[37][1:0],b[37][31:2]};
b[38] = a[37];
a[38] = temp[37];
temp[38] = {a[38][26:0],a[38][31:27]} + (b[38] ^ c[38] ^ d[38]) + e[38] + w[38] + k[1] ;
e[39] = d[38];
d[39] = c[38];
c[39] = {b[38][1:0],b[38][31:2]};
b[39] = a[38];
a[39] = temp[38];
temp[39] = {a[39][26:0],a[39][31:27]} + (b[39] ^ c[39] ^ d[39]) + e[39] + w[39] + k[1] ;
e[40] = d[39];
d[40] = c[39];
c[40] = {b[39][1:0],b[39][31:2]};
b[40] = a[39];
a[40] = temp[39];
flag = 6;
end else if(curr_state == SHA1_F2_ROUNDS) begin
temp[40] = {a[40][26:0],a[40][31:27]} + ((b[40]&c[40])|(b[40]&d[40])|(c[40]&d[40])) + e[40] + w[40] + k[2] ;
e[41] = d[40];
d[41] = c[40];
c[41] = {b[40][1:0],b[40][31:2]};
b[41] = a[40];
a[41] = temp[40];
temp[41] = {a[41][26:0],a[41][31:27]} + ((b[41]&c[41])|(b[41]&d[41])|(c[41]&d[41])) + e[41] + w[41] + k[2] ;
e[42] = d[41];
d[42] = c[41];
c[42] = {b[41][1:0],b[41][31:2]};
b[42] = a[41];
a[42] = temp[41];
temp[42] = {a[42][26:0],a[42][31:27]} + ((b[42]&c[42])|(b[42]&d[42])|(c[42]&d[42])) + e[42] + w[42] + k[2] ;
e[43] = d[42];
d[43] = c[42];
c[43] = {b[42][1:0],b[42][31:2]};
b[43] = a[42];
a[43] = temp[42];
temp[43] = {a[43][26:0],a[43][31:27]} + ((b[43]&c[43])|(b[43]&d[43])|(c[43]&d[43])) + e[43] + w[43] + k[2] ;
e[44] = d[43];
d[44] = c[43];
c[44] = {b[43][1:0],b[43][31:2]};
b[44] = a[43];
a[44] = temp[43];
temp[44] = {a[44][26:0],a[44][31:27]} + ((b[44]&c[44])|(b[44]&d[44])|(c[44]&d[44])) + e[44] + w[44] + k[2] ;
e[45] = d[44];
d[45] = c[44];
c[45] = {b[44][1:0],b[44][31:2]};
b[45] = a[44];
a[45] = temp[44];
temp[45] = {a[45][26:0],a[45][31:27]} + ((b[45]&c[45])|(b[45]&d[45])|(c[45]&d[45])) + e[45] + w[45] + k[2] ;
e[46] = d[45];
d[46] = c[45];
c[46] = {b[45][1:0],b[45][31:2]};
b[46] = a[45];
a[46] = temp[45];
temp[46] = {a[46][26:0],a[46][31:27]} + ((b[46]&c[46])|(b[46]&d[46])|(c[46]&d[46])) + e[46] + w[46] + k[2] ;
e[47] = d[46];
d[47] = c[46];
c[47] = {b[46][1:0],b[46][31:2]};
b[47] = a[46];
a[47] = temp[46];
temp[47] = {a[47][26:0],a[47][31:27]} + ((b[47]&c[47])|(b[47]&d[47])|(c[47]&d[47])) + e[47] + w[47] + k[2] ;
e[48] = d[47];
d[48] = c[47];
c[48] = {b[47][1:0],b[47][31:2]};
b[48] = a[47];
a[48] = temp[47];
temp[48] = {a[48][26:0],a[48][31:27]} + ((b[48]&c[48])|(b[48]&d[48])|(c[48]&d[48])) + e[48] + w[48] + k[2] ;
e[49] = d[48];
d[49] = c[48];
c[49] = {b[48][1:0],b[48][31:2]};
b[49] = a[48];
a[49] = temp[48];
temp[49] = {a[49][26:0],a[49][31:27]} + ((b[49]&c[49])|(b[49]&d[49])|(c[49]&d[49])) + e[49] + w[49] + k[2] ;
e[50] = d[49];
d[50] = c[49];
c[50] = {b[49][1:0],b[49][31:2]};
b[50] = a[49];
a[50] = temp[49];
temp[50] = {a[50][26:0],a[50][31:27]} + ((b[50]&c[50])|(b[50]&d[50])|(c[50]&d[50])) + e[50] + w[50] + k[2] ;
e[51] = d[50];
d[51] = c[50];
c[51] = {b[50][1:0],b[50][31:2]};
b[51] = a[50];
a[51] = temp[50];
temp[51] = {a[51][26:0],a[51][31:27]} + ((b[51]&c[51])|(b[51]&d[51])|(c[51]&d[51])) + e[51] + w[51] + k[2] ;
e[52] = d[51];
d[52] = c[51];
c[52] = {b[51][1:0],b[51][31:2]};
b[52] = a[51];
a[52] = temp[51];
temp[52] = {a[52][26:0],a[52][31:27]} + ((b[52]&c[52])|(b[52]&d[52])|(c[52]&d[52])) + e[52] + w[52] + k[2] ;
e[53] = d[52];
d[53] = c[52];
c[53] = {b[52][1:0],b[52][31:2]};
b[53] = a[52];
a[53] = temp[52];
temp[53] = {a[53][26:0],a[53][31:27]} + ((b[53]&c[53])|(b[53]&d[53])|(c[53]&d[53])) + e[53] + w[53] + k[2] ;
e[54] = d[53];
d[54] = c[53];
c[54] = {b[53][1:0],b[53][31:2]};
b[54] = a[53];
a[54] = temp[53];
temp[54] = {a[54][26:0],a[54][31:27]} + ((b[54]&c[54])|(b[54]&d[54])|(c[54]&d[54])) + e[54] + w[54] + k[2] ;
e[55] = d[54];
d[55] = c[54];
c[55] = {b[54][1:0],b[54][31:2]};
b[55] = a[54];
a[55] = temp[54];
temp[55] = {a[55][26:0],a[55][31:27]} + ((b[55]&c[55])|(b[55]&d[55])|(c[55]&d[55])) + e[55] + w[55] + k[2] ;
e[56] = d[55];
d[56] = c[55];
c[56] = {b[55][1:0],b[55][31:2]};
b[56] = a[55];
a[56] = temp[55];
temp[56] = {a[56][26:0],a[56][31:27]} + ((b[56]&c[56])|(b[56]&d[56])|(c[56]&d[56])) + e[56] + w[56] + k[2] ;
e[57] = d[56];
d[57] = c[56];
c[57] = {b[56][1:0],b[56][31:2]};
b[57] = a[56];
a[57] = temp[56];
temp[57] = {a[57][26:0],a[57][31:27]} + ((b[57]&c[57])|(b[57]&d[57])|(c[57]&d[57])) + e[57] + w[57] + k[2] ;
e[58] = d[57];
d[58] = c[57];
c[58] = {b[57][1:0],b[57][31:2]};
b[58] = a[57];
a[58] = temp[57];
temp[58] = {a[58][26:0],a[58][31:27]} + ((b[58]&c[58])|(b[58]&d[58])|(c[58]&d[58])) + e[58] + w[58] + k[2] ;
e[59] = d[58];
d[59] = c[58];
c[59] = {b[58][1:0],b[58][31:2]};
b[59] = a[58];
a[59] = temp[58];
temp[59] = {a[59][26:0],a[59][31:27]} + ((b[59]&c[59])|(b[59]&d[59])|(c[59]&d[59])) + e[59] + w[59] + k[2] ;
e[60] = d[59];
d[60] = c[59];
c[60] = {b[59][1:0],b[59][31:2]};
b[60] = a[59];
a[60] = temp[59];
flag = 7;
end else if(curr_state == SHA1_F3_ROUNDS) begin
temp[60] = {a[60][26:0],a[60][31:27]} + (b[60]^c[60]^d[60]) + e[60] + w[60] + k[3] ;
e[61] = d[60];
d[61] = c[60];
c[61] = {b[60][1:0],b[60][31:2]};
b[61] = a[60];
a[61] = temp[60];
temp[61] = {a[61][26:0],a[61][31:27]} + (b[61]^c[61]^d[61]) + e[61] + w[61] + k[3] ;
e[62] = d[61];
d[62] = c[61];
c[62] = {b[61][1:0],b[61][31:2]};
b[62] = a[61];
a[62] = temp[61];
temp[62] = {a[62][26:0],a[62][31:27]} + (b[62]^c[62]^d[62]) + e[62] + w[62] + k[3] ;
e[63] = d[62];
d[63] = c[62];
c[63] = {b[62][1:0],b[62][31:2]};
b[63] = a[62];
a[63] = temp[62];
temp[63] = {a[63][26:0],a[63][31:27]} + (b[63]^c[63]^d[63]) + e[63] + w[63] + k[3] ;
e[64] = d[63];
d[64] = c[63];
c[64] = {b[63][1:0],b[63][31:2]};
b[64] = a[63];
a[64] = temp[63];
temp[64] = {a[64][26:0],a[64][31:27]} + (b[64]^c[64]^d[64]) + e[64] + w[64] + k[3] ;
e[65] = d[64];
d[65] = c[64];
c[65] = {b[64][1:0],b[64][31:2]};
b[65] = a[64];
a[65] = temp[64];
temp[65] = {a[65][26:0],a[65][31:27]} + (b[65]^c[65]^d[65]) + e[65] + w[65] + k[3] ;
e[66] = d[65];
d[66] = c[65];
c[66] = {b[65][1:0],b[65][31:2]};
b[66] = a[65];
a[66] = temp[65];
temp[66] = {a[66][26:0],a[66][31:27]} + (b[66]^c[66]^d[66]) + e[66] + w[66] + k[3] ;
e[67] = d[66];
d[67] = c[66];
c[67] = {b[66][1:0],b[66][31:2]};
b[67] = a[66];
a[67] = temp[66];
temp[67] = {a[67][26:0],a[67][31:27]} + (b[67]^c[67]^d[67]) + e[67] + w[67] + k[3] ;
e[68] = d[67];
d[68] = c[67];
c[68] = {b[67][1:0],b[67][31:2]};
b[68] = a[67];
a[68] = temp[67];
temp[68] = {a[68][26:0],a[68][31:27]} + (b[68]^c[68]^d[68]) + e[68] + w[68] + k[3] ;
e[69] = d[68];
d[69] = c[68];
c[69] = {b[68][1:0],b[68][31:2]};
b[69] = a[68];
a[69] = temp[68];
temp[69] = {a[69][26:0],a[69][31:27]} + (b[69]^c[69]^d[69]) + e[69] + w[69] + k[3] ;
e[70] = d[69];
d[70] = c[69];
c[70] = {b[69][1:0],b[69][31:2]};
b[70] = a[69];
a[70] = temp[69];
temp[70] = {a[70][26:0],a[70][31:27]} + (b[70]^c[70]^d[70]) + e[70] + w[70] + k[3] ;
e[71] = d[70];
d[71] = c[70];
c[71] = {b[70][1:0],b[70][31:2]};
b[71] = a[70];
a[71] = temp[70];
temp[71] = {a[71][26:0],a[71][31:27]} + (b[71]^c[71]^d[71]) + e[71] + w[71] + k[3] ;
e[72] = d[71];
d[72] = c[71];
c[72] = {b[71][1:0],b[71][31:2]};
b[72] = a[71];
a[72] = temp[71];
temp[72] = {a[72][26:0],a[72][31:27]} + (b[72]^c[72]^d[72]) + e[72] + w[72] + k[3] ;
e[73] = d[72];
d[73] = c[72];
c[73] = {b[72][1:0],b[72][31:2]};
b[73] = a[72];
a[73] = temp[72];
temp[73] = {a[73][26:0],a[73][31:27]} + (b[73]^c[73]^d[73]) + e[73] + w[73] + k[3] ;
e[74] = d[73];
d[74] = c[73];
c[74] = {b[73][1:0],b[73][31:2]};
b[74] = a[73];
a[74] = temp[73];
temp[74] = {a[74][26:0],a[74][31:27]} + (b[74]^c[74]^d[74]) + e[74] + w[74] + k[3] ;
e[75] = d[74];
d[75] = c[74];
c[75] = {b[74][1:0],b[74][31:2]};
b[75] = a[74];
a[75] = temp[74];
temp[75] = {a[75][26:0],a[75][31:27]} + (b[75]^c[75]^d[75]) + e[75] + w[75] + k[3] ;
e[76] = d[75];
d[76] = c[75];
c[76] = {b[75][1:0],b[75][31:2]};
b[76] = a[75];
a[76] = temp[75];
temp[76] = {a[76][26:0],a[76][31:27]} + (b[76]^c[76]^d[76]) + e[76] + w[76] + k[3] ;
e[77] = d[76];
d[77] = c[76];
c[77] = {b[76][1:0],b[76][31:2]};
b[77] = a[76];
a[77] = temp[76];
temp[77] = {a[77][26:0],a[77][31:27]} + (b[77]^c[77]^d[77]) + e[77] + w[77] + k[3] ;
e[78] = d[77];
d[78] = c[77];
c[78] = {b[77][1:0],b[77][31:2]};
b[78] = a[77];
a[78] = temp[77];
temp[78] = {a[78][26:0],a[78][31:27]} + (b[78]^c[78]^d[78]) + e[78] + w[78] + k[3] ;
e[79] = d[78];
d[79] = c[78];
c[79] = {b[78][1:0],b[78][31:2]};
b[79] = a[78];
a[79] = temp[78];
temp[79] = {a[79][26:0],a[79][31:27]} + (b[79]^c[79]^d[79]) + e[79] + w[79] + k[3] ;
e[80] = d[79];
d[80] = c[79];
c[80] = {b[79][1:0],b[79][31:2]};
b[80] = a[79];
a[80] = temp[79];
flag = 8;
end else if(curr_state == SHA1_FINAL) begin
hash[0] = h[0] + a[80];
hash[1] = h[1] + b[80];
hash[2] = h[2] + c[80];
hash[3] = h[3] + d[80];
hash[4] = h[4] + e[80];
flag = 9;
end else if(curr_state == SHA1_DIGEST) begin
digest_out = {hash[0],hash[1],hash[2],hash[3],hash[4]};
digest_done = 1;
end else begin end
end
endmodule | 0 |
140,963 | data/full_repos/permissive/93120196/4bit_adder.v | 93,120,196 | 4bit_adder.v | v | 20 | 60 | [] | [] | [] | [(1, 20)] | null | null | 1: b"%Error: data/full_repos/permissive/93120196/4bit_adder.v:15: Cannot find file containing module: 'Full_Adder'\nFull_Adder C1(Sum[0], w[0], A[0], B[0], Cin);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/Full_Adder\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/Full_Adder.v\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/Full_Adder.sv\n Full_Adder\n Full_Adder.v\n Full_Adder.sv\n obj_dir/Full_Adder\n obj_dir/Full_Adder.v\n obj_dir/Full_Adder.sv\n%Error: data/full_repos/permissive/93120196/4bit_adder.v:16: Cannot find file containing module: 'Full_Adder'\nFull_Adder C2(Sum[1], w[1], A[1], B[1], w[0]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/93120196/4bit_adder.v:17: Cannot find file containing module: 'Full_Adder'\nFull_Adder C3(Sum[2], w[2], A[2], B[2], w[1]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/93120196/4bit_adder.v:18: Cannot find file containing module: 'Full_Adder'\nFull_Adder C4(Sum[3], Cout, A[3], B[3], w[2]);\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 310,569 | module | module FourBit_Adder(Sum, Cout, A, B, Cin);
output [3:0]Sum;
output Cout;
input [3:0]A;
input [3:0]B;
input Cin;
wire [2:0]w;
Full_Adder C1(Sum[0], w[0], A[0], B[0], Cin);
Full_Adder C2(Sum[1], w[1], A[1], B[1], w[0]);
Full_Adder C3(Sum[2], w[2], A[2], B[2], w[1]);
Full_Adder C4(Sum[3], Cout, A[3], B[3], w[2]);
endmodule | module FourBit_Adder(Sum, Cout, A, B, Cin); |
output [3:0]Sum;
output Cout;
input [3:0]A;
input [3:0]B;
input Cin;
wire [2:0]w;
Full_Adder C1(Sum[0], w[0], A[0], B[0], Cin);
Full_Adder C2(Sum[1], w[1], A[1], B[1], w[0]);
Full_Adder C3(Sum[2], w[2], A[2], B[2], w[1]);
Full_Adder C4(Sum[3], Cout, A[3], B[3], w[2]);
endmodule | 0 |
140,964 | data/full_repos/permissive/93120196/4bit_adder_ha.v | 93,120,196 | 4bit_adder_ha.v | v | 18 | 48 | [] | [] | [] | [(1, 18)] | null | null | 1: b"%Error: data/full_repos/permissive/93120196/4bit_adder_ha.v:14: Cannot find file containing module: 'HA'\nHA C1(Sum[0], w[0], A[0], B[0]);\n^~\n ... Looked in:\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/HA\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/HA.v\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/HA.sv\n HA\n HA.v\n HA.sv\n obj_dir/HA\n obj_dir/HA.v\n obj_dir/HA.sv\n%Error: data/full_repos/permissive/93120196/4bit_adder_ha.v:15: Cannot find file containing module: 'Full_Adder'\nFull_Adder C2(Sum[1], w[1], A[1], B[1], w[0]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/93120196/4bit_adder_ha.v:16: Cannot find file containing module: 'Full_Adder'\nFull_Adder C3(Sum[2], w[2], A[2], B[2], w[1]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/93120196/4bit_adder_ha.v:17: Cannot find file containing module: 'Full_Adder'\nFull_Adder C4(Sum[3], Carry, A[3], B[3], w[2]);\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 310,570 | module | module FourBit_Adder_HA(Sum, Carry, A, B);
output [3:0]Sum;
output Carry;
input [3:0]A;
input [3:0]B;
wire [2:0]w;
HA C1(Sum[0], w[0], A[0], B[0]);
Full_Adder C2(Sum[1], w[1], A[1], B[1], w[0]);
Full_Adder C3(Sum[2], w[2], A[2], B[2], w[1]);
Full_Adder C4(Sum[3], Carry, A[3], B[3], w[2]);
endmodule | module FourBit_Adder_HA(Sum, Carry, A, B); |
output [3:0]Sum;
output Carry;
input [3:0]A;
input [3:0]B;
wire [2:0]w;
HA C1(Sum[0], w[0], A[0], B[0]);
Full_Adder C2(Sum[1], w[1], A[1], B[1], w[0]);
Full_Adder C3(Sum[2], w[2], A[2], B[2], w[1]);
Full_Adder C4(Sum[3], Carry, A[3], B[3], w[2]);
endmodule | 0 |
140,965 | data/full_repos/permissive/93120196/8bit_adder.v | 93,120,196 | 8bit_adder.v | v | 18 | 60 | [] | [] | [] | [(1, 18)] | null | null | 1: b"%Error: data/full_repos/permissive/93120196/8bit_adder.v:15: Cannot find file containing module: 'FourBit_Adder'\nFourBit_Adder C1(Sum[3:0], w0, A[3:0], B[3:0], Cin);\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/FourBit_Adder\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/FourBit_Adder.v\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/FourBit_Adder.sv\n FourBit_Adder\n FourBit_Adder.v\n FourBit_Adder.sv\n obj_dir/FourBit_Adder\n obj_dir/FourBit_Adder.v\n obj_dir/FourBit_Adder.sv\n%Error: data/full_repos/permissive/93120196/8bit_adder.v:16: Cannot find file containing module: 'FourBit_Adder'\nFourBit_Adder C2(Sum[7:4], Cout, A[7:4], B[7:4], w0);\n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 310,571 | module | module EightBit_Adder(Sum, Cout, A, B, Cin);
output [7:0]Sum;
output Cout;
input [7:0]A;
input [7:0]B;
input Cin;
wire w0;
FourBit_Adder C1(Sum[3:0], w0, A[3:0], B[3:0], Cin);
FourBit_Adder C2(Sum[7:4], Cout, A[7:4], B[7:4], w0);
endmodule | module EightBit_Adder(Sum, Cout, A, B, Cin); |
output [7:0]Sum;
output Cout;
input [7:0]A;
input [7:0]B;
input Cin;
wire w0;
FourBit_Adder C1(Sum[3:0], w0, A[3:0], B[3:0], Cin);
FourBit_Adder C2(Sum[7:4], Cout, A[7:4], B[7:4], w0);
endmodule | 0 |
140,966 | data/full_repos/permissive/93120196/alu_example.v | 93,120,196 | alu_example.v | v | 20 | 36 | [] | [] | [] | null | line:2: before: "output" | null | 1: b"%Error: data/full_repos/permissive/93120196/alu_example.v:2: syntax error, unexpected output, expecting ';'\noutput [7:0]out;\n^~~~~~\n%Error: data/full_repos/permissive/93120196/alu_example.v:4: syntax error, unexpected input\ninput [3:0]A,B;\n^~~~~\n%Error: Exiting due to 2 error(s)\n" | 310,572 | module | module alu_example()
output [7:0]out;
reg [7:0]out;
input [3:0]A,B;
input [1:0]Sel;
always @(A or B or Sel)
begin
if(Sel[1] == 1'b0 & Sel[0] == 1'b0
Out = A + B;
else if (Sel == 2'b01)
Out = A - B;
else if (Sel == 2'b10)
Out = A*B;
else if (Sel == 2'b11)
Out = A/B;
else
end
endmodule | module alu_example()
output [7:0]out; |
reg [7:0]out;
input [3:0]A,B;
input [1:0]Sel;
always @(A or B or Sel)
begin
if(Sel[1] == 1'b0 & Sel[0] == 1'b0
Out = A + B;
else if (Sel == 2'b01)
Out = A - B;
else if (Sel == 2'b10)
Out = A*B;
else if (Sel == 2'b11)
Out = A/B;
else
end
endmodule | 0 |
140,967 | data/full_repos/permissive/93120196/counter_dir_load_init.v | 93,120,196 | counter_dir_load_init.v | v | 23 | 66 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f6e02dc2-6f89-436f-afda-2240c17c4e06.xml | null | 310,574 | module | module counter_up_down_with_load(out, clk, reset, dir, load, in);
output [2:0] out;
reg [2:0] out;
input clk, reset, load, dir;
input [2:0] in;
initial
begin
out <= 3'b0;
end
always @(posedge clk or reset)
begin
if (reset == 1'b1)
out <= 3'b000;
else if (load == 1'b1)
out <= in;
else if (dir == 1'b1)
out <= out + 1;
else
out <= out - 1;
end
endmodule | module counter_up_down_with_load(out, clk, reset, dir, load, in); |
output [2:0] out;
reg [2:0] out;
input clk, reset, load, dir;
input [2:0] in;
initial
begin
out <= 3'b0;
end
always @(posedge clk or reset)
begin
if (reset == 1'b1)
out <= 3'b000;
else if (load == 1'b1)
out <= in;
else if (dir == 1'b1)
out <= out + 1;
else
out <= out - 1;
end
endmodule | 0 |
140,968 | data/full_repos/permissive/93120196/counter_up.v | 93,120,196 | counter_up.v | v | 14 | 36 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/81c7e8f8-54a1-4e4f-9e42-a0878003e35b.xml | null | 310,575 | module | module counter_up(out, clk, reset);
output [2:0] out;
reg [2:0] out;
input clk, reset;
always @(posedge clk)
begin
if (reset == 1'b1)
out <= 3'b000;
else
out <= out + 1;
end
endmodule | module counter_up(out, clk, reset); |
output [2:0] out;
reg [2:0] out;
input clk, reset;
always @(posedge clk)
begin
if (reset == 1'b1)
out <= 3'b000;
else
out <= out + 1;
end
endmodule | 0 |
140,969 | data/full_repos/permissive/93120196/d_flipflop.v | 93,120,196 | d_flipflop.v | v | 32 | 38 | [] | [] | [] | null | line:12: before: "reset" | data/verilator_xmls/e5cb2684-b4a8-41a7-8c68-611f0dbe8f9c.xml | null | 310,577 | module | module d_flipflop (q, d, clk, reset);
input d, clk, reset;
output q;
reg q;
always @(posedge clk or reset)
begin
if (reset == 1'b1)
q <= 1'b0;
else
q <= d;
end
endmodule | module d_flipflop (q, d, clk, reset); |
input d, clk, reset;
output q;
reg q;
always @(posedge clk or reset)
begin
if (reset == 1'b1)
q <= 1'b0;
else
q <= d;
end
endmodule | 0 |
140,970 | data/full_repos/permissive/93120196/full_adder.v | 93,120,196 | full_adder.v | v | 16 | 54 | [] | [] | [] | [(1, 16)] | null | null | 1: b"%Error: data/full_repos/permissive/93120196/full_adder.v:12: Cannot find file containing module: 'HA'\nHA C1(w1, w2, A, B);\n^~\n ... Looked in:\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/HA\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/HA.v\n data/full_repos/permissive/93120196,data/full_repos/permissive/93120196/HA.sv\n HA\n HA.v\n HA.sv\n obj_dir/HA\n obj_dir/HA.v\n obj_dir/HA.sv\n%Error: data/full_repos/permissive/93120196/full_adder.v:13: Cannot find file containing module: 'HA'\nHA C2(Sum, w3, w1, C);\n^~\n%Error: Exiting due to 2 error(s)\n" | 310,578 | module | module Full_Adder (Sum, Carry, A, B, C);
output Sum, Carry;
input A, B, C;
wire w1, w2, w3;
HA C1(w1, w2, A, B);
HA C2(Sum, w3, w1, C);
or C3(Carry, w2, w3);
endmodule | module Full_Adder (Sum, Carry, A, B, C); |
output Sum, Carry;
input A, B, C;
wire w1, w2, w3;
HA C1(w1, w2, A, B);
HA C2(Sum, w3, w1, C);
or C3(Carry, w2, w3);
endmodule | 0 |
140,971 | data/full_repos/permissive/93120196/half_adder.v | 93,120,196 | half_adder.v | v | 8 | 30 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/76711d9a-1e03-4413-884c-d875950ec43f.xml | null | 310,579 | module | module HA (Sum, Carry, A, B);
output Sum, Carry;
input A, B;
and c1 (Carry, A, B);
xor c2 (Sum, A, B);
endmodule | module HA (Sum, Carry, A, B); |
output Sum, Carry;
input A, B;
and c1 (Carry, A, B);
xor c2 (Sum, A, B);
endmodule | 0 |
140,972 | data/full_repos/permissive/93120196/Half_Adder_Stimulus.v | 93,120,196 | Half_Adder_Stimulus.v | v | 26 | 79 | [] | [] | [] | null | line:18: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/Half_Adder_Stimulus.v:15: Unsupported: Ignoring delay on this delayed statement.\n #5 A = 1\'b0; B = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/Half_Adder_Stimulus.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 A = 1\'b1; B = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/Half_Adder_Stimulus.v:17: Unsupported: Ignoring delay on this delayed statement.\n #5 A = 1\'b1; B = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/Half_Adder_Stimulus.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/Half_Adder_Stimulus.v:23: Unsupported or unknown PLI call: $monitor\n $monitor($time, "Sum = %b, Carry = %b, A = %b, B = %b \\n", Sum, Carry, A, B);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,580 | module | module stimulus_HA;
reg A, B;
wire Sum, Carry;
HA C1(Sum, Carry, A, B);
initial
begin
A = 1'b0;
B = 1'b0;
end
initial
begin
#5 A = 1'b0; B = 1'b1;
#5 A = 1'b1; B = 1'b0;
#5 A = 1'b1; B = 1'b1;
#10 $finish;
end
initial
begin
$monitor($time, "Sum = %b, Carry = %b, A = %b, B = %b \n", Sum, Carry, A, B);
end
endmodule | module stimulus_HA; |
reg A, B;
wire Sum, Carry;
HA C1(Sum, Carry, A, B);
initial
begin
A = 1'b0;
B = 1'b0;
end
initial
begin
#5 A = 1'b0; B = 1'b1;
#5 A = 1'b1; B = 1'b0;
#5 A = 1'b1; B = 1'b1;
#10 $finish;
end
initial
begin
$monitor($time, "Sum = %b, Carry = %b, A = %b, B = %b \n", Sum, Carry, A, B);
end
endmodule | 0 |
140,973 | data/full_repos/permissive/93120196/mux_16to1.v | 93,120,196 | mux_16to1.v | v | 8 | 249 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/eaa7c3c1-a12b-431e-9cbb-f9de8295e1df.xml | null | 310,581 | module | module mux_16to1(Out, In, Sel);
output Out;
input [15:0]In;
input [3:0]Sel;
assign Out = Sel[3]?(Sel[2]?(Sel[1]?(Sel[0]?In[15]:In[14]):(Sel[0]?In[13]:In[12])):(Sel[1]?(Sel[0]?In[11]:In[10]):(Sel[0]?In[9]:In[8]))):(Sel[2]?(Sel[1]?(Sel[0]?In[7]:In[6]):(Sel[0]?In[5]:In[4])):(Sel[1]?(Sel[0]?In[3]:In[2]):(Sel[0]?In[1]:In[0])));
endmodule | module mux_16to1(Out, In, Sel); |
output Out;
input [15:0]In;
input [3:0]Sel;
assign Out = Sel[3]?(Sel[2]?(Sel[1]?(Sel[0]?In[15]:In[14]):(Sel[0]?In[13]:In[12])):(Sel[1]?(Sel[0]?In[11]:In[10]):(Sel[0]?In[9]:In[8]))):(Sel[2]?(Sel[1]?(Sel[0]?In[7]:In[6]):(Sel[0]?In[5]:In[4])):(Sel[1]?(Sel[0]?In[3]:In[2]):(Sel[0]?In[1]:In[0])));
endmodule | 0 |
140,974 | data/full_repos/permissive/93120196/mux_16to1_stimulus.v | 93,120,196 | mux_16to1_stimulus.v | v | 43 | 51 | [] | [] | [] | null | line:34: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:19: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b0001;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:20: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b0011;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b0100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b0101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b0110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:25: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b0111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:27: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1011;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:32: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5 Sel = 4\'b1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/mux_16to1_stimulus.v:40: Unsupported or unknown PLI call: $monitor\n $monitor($time, " Out = %b, Sel = %d", Out, Sel);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,582 | module | module stimulus_mux_16to1;
reg [15:0]In;
reg [3:0]Sel;
wire Out;
mux_16to1 C1(Out, In, Sel);
initial
begin
Sel = 4'b0000;
In = 16'b1010101010101010;
end
initial
begin
#5 Sel = 4'b0001;
#5 Sel = 4'b0010;
#5 Sel = 4'b0011;
#5 Sel = 4'b0100;
#5 Sel = 4'b0101;
#5 Sel = 4'b0110;
#5 Sel = 4'b0111;
#5 Sel = 4'b1000;
#5 Sel = 4'b1001;
#5 Sel = 4'b1010;
#5 Sel = 4'b1011;
#5 Sel = 4'b1100;
#5 Sel = 4'b1101;
#5 Sel = 4'b1110;
#5 Sel = 4'b1111;
#10 $finish;
end
initial
begin
$monitor($time, " Out = %b, Sel = %d", Out, Sel);
end
endmodule | module stimulus_mux_16to1; |
reg [15:0]In;
reg [3:0]Sel;
wire Out;
mux_16to1 C1(Out, In, Sel);
initial
begin
Sel = 4'b0000;
In = 16'b1010101010101010;
end
initial
begin
#5 Sel = 4'b0001;
#5 Sel = 4'b0010;
#5 Sel = 4'b0011;
#5 Sel = 4'b0100;
#5 Sel = 4'b0101;
#5 Sel = 4'b0110;
#5 Sel = 4'b0111;
#5 Sel = 4'b1000;
#5 Sel = 4'b1001;
#5 Sel = 4'b1010;
#5 Sel = 4'b1011;
#5 Sel = 4'b1100;
#5 Sel = 4'b1101;
#5 Sel = 4'b1110;
#5 Sel = 4'b1111;
#10 $finish;
end
initial
begin
$monitor($time, " Out = %b, Sel = %d", Out, Sel);
end
endmodule | 0 |
140,975 | data/full_repos/permissive/93120196/mux_2to1.v | 93,120,196 | mux_2to1.v | v | 8 | 34 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/a076b92a-75c5-4dd4-87f4-ae185a9d612c.xml | null | 310,583 | module | module mux_2to1 (Out, In, Sel);
output Out;
input [1:0] In;
input Sel;
assign Out = Sel ? In[1] : In[0];
endmodule | module mux_2to1 (Out, In, Sel); |
output Out;
input [1:0] In;
input Sel;
assign Out = Sel ? In[1] : In[0];
endmodule | 0 |
140,976 | data/full_repos/permissive/93120196/mux_4to1.v | 93,120,196 | mux_4to1.v | v | 8 | 75 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/eb9d37d9-1895-42a0-be27-27bb78031507.xml | null | 310,584 | module | module mux_4to1 (Out, In, Sel);
output Out;
input [3:0]In;
input [1:0]Sel;
assign Out = Sel[1] ? (Sel[0] ? In[3] : In[2]) : (Sel[0] ? In[1] : In[0]);
endmodule | module mux_4to1 (Out, In, Sel); |
output Out;
input [3:0]In;
input [1:0]Sel;
assign Out = Sel[1] ? (Sel[0] ? In[3] : In[2]) : (Sel[0] ? In[1] : In[0]);
endmodule | 0 |
140,977 | data/full_repos/permissive/93120196/clock/ac_four_digit.v | 93,120,196 | ac_four_digit.v | v | 70 | 88 | [] | [] | [] | [(1, 70)] | null | null | 1: b"%Error: data/full_repos/permissive/93120196/clock/ac_four_digit.v:28: Cannot find file containing module: 'keypad_scanner'\nkeypad_scanner C1(return_digit, key_row_req, key_col_req, key_stim);\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93120196/clock,data/full_repos/permissive/93120196/keypad_scanner\n data/full_repos/permissive/93120196/clock,data/full_repos/permissive/93120196/keypad_scanner.v\n data/full_repos/permissive/93120196/clock,data/full_repos/permissive/93120196/keypad_scanner.sv\n keypad_scanner\n keypad_scanner.v\n keypad_scanner.sv\n obj_dir/keypad_scanner\n obj_dir/keypad_scanner.v\n obj_dir/keypad_scanner.sv\n%Error: Exiting due to 1 error(s)\n" | 310,586 | module | module ac_four_digit(key_buffer_out, key_buffer_in, keypad_int, clk, key_row, key_col);
output [15:0]key_buffer_out;
reg [15:0]key_buffer_out;
reg i;
input clk, keypad_int;
input [1:0]key_row;
input [1:0]key_col;
wire [1:0]key_row;
wire [1:0]key_col;
input [15:0]key_buffer_in;
reg [1:0]key_row_req;
reg [1:0]key_col_req;
wire [3:0]return_digit;
reg key_stim;
wire [3:0]cur_digit;
keypad_scanner C1(return_digit, key_row_req, key_col_req, key_stim);
always@(posedge keypad_int)
begin
key_buffer_out = key_buffer_in;
key_row_req = key_row;
key_col_req = key_col;
key_stim = 1'b0;
key_stim = 1'b1;
key_stim = 1'b0;
key_buffer_out = key_buffer_out<<4;
key_buffer_out[3] = return_digit[3];
key_buffer_out[2] = return_digit[2];
key_buffer_out[1] = return_digit[1];
key_buffer_out[0] = return_digit[0];
end
endmodule | module ac_four_digit(key_buffer_out, key_buffer_in, keypad_int, clk, key_row, key_col); |
output [15:0]key_buffer_out;
reg [15:0]key_buffer_out;
reg i;
input clk, keypad_int;
input [1:0]key_row;
input [1:0]key_col;
wire [1:0]key_row;
wire [1:0]key_col;
input [15:0]key_buffer_in;
reg [1:0]key_row_req;
reg [1:0]key_col_req;
wire [3:0]return_digit;
reg key_stim;
wire [3:0]cur_digit;
keypad_scanner C1(return_digit, key_row_req, key_col_req, key_stim);
always@(posedge keypad_int)
begin
key_buffer_out = key_buffer_in;
key_row_req = key_row;
key_col_req = key_col;
key_stim = 1'b0;
key_stim = 1'b1;
key_stim = 1'b0;
key_buffer_out = key_buffer_out<<4;
key_buffer_out[3] = return_digit[3];
key_buffer_out[2] = return_digit[2];
key_buffer_out[1] = return_digit[1];
key_buffer_out[0] = return_digit[0];
end
endmodule | 0 |
140,978 | data/full_repos/permissive/93120196/clock/ac_keypadScanner.v | 93,120,196 | ac_keypadScanner.v | v | 121 | 58 | [] | [] | [] | [(1, 121)] | null | data/verilator_xmls/6d666718-dc04-44ab-8ed8-8172cbf3a99e.xml | null | 310,587 | module | module keypad_scanner(value, key_row, key_col, stimulus);
input stimulus;
input [1:0]key_row;
input [1:0]key_col;
output [3:0]value;
reg [3:0]value;
always@ (posedge stimulus)
if (key_col == 2'b00)
begin
if (key_row == 2'b00)
begin
value <= 4'b0001;
end
else if (key_row == 2'b01)
begin
value <= 4'b0100;
end
else if (key_row == 2'b10)
begin
value <= 4'b0111;
end
else
begin
value <= 4'b1010;
end
end
else if (key_col == 2'b01)
begin
if (key_row == 2'b00)
begin
value <= 4'b0010;
end
else if (key_row == 2'b01)
begin
value <= 4'b0101;
end
else if (key_row == 2'b10)
begin
value <= 4'b1000;
end
else
begin
value <= 4'b0000;
end
end
else if (key_col == 2'b10)
begin
if (key_row == 2'b00)
begin
value <= 4'b0011;
end
else if (key_row == 2'b01)
begin
value = 4'b0110;
end
else if (key_row == 2'b10)
begin
value <= 4'b1001;
end
else
begin
value <= 4'b1011;
end
end
else
begin
value <= 4'b1111;
end
endmodule | module keypad_scanner(value, key_row, key_col, stimulus); |
input stimulus;
input [1:0]key_row;
input [1:0]key_col;
output [3:0]value;
reg [3:0]value;
always@ (posedge stimulus)
if (key_col == 2'b00)
begin
if (key_row == 2'b00)
begin
value <= 4'b0001;
end
else if (key_row == 2'b01)
begin
value <= 4'b0100;
end
else if (key_row == 2'b10)
begin
value <= 4'b0111;
end
else
begin
value <= 4'b1010;
end
end
else if (key_col == 2'b01)
begin
if (key_row == 2'b00)
begin
value <= 4'b0010;
end
else if (key_row == 2'b01)
begin
value <= 4'b0101;
end
else if (key_row == 2'b10)
begin
value <= 4'b1000;
end
else
begin
value <= 4'b0000;
end
end
else if (key_col == 2'b10)
begin
if (key_row == 2'b00)
begin
value <= 4'b0011;
end
else if (key_row == 2'b01)
begin
value = 4'b0110;
end
else if (key_row == 2'b10)
begin
value <= 4'b1001;
end
else
begin
value <= 4'b1011;
end
end
else
begin
value <= 4'b1111;
end
endmodule | 0 |
140,979 | data/full_repos/permissive/93120196/clock/comparator_stimulus.v | 93,120,196 | comparator_stimulus.v | v | 32 | 109 | [] | [] | [] | null | line:24: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/comparator_stimulus.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0010;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/comparator_stimulus.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/comparator_stimulus.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/comparator_stimulus.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/comparator_stimulus.v:29: Unsupported or unknown PLI call: $monitor\n $monitor($time, "alarm_time = %d, current_time = %d, alarm = %b\\n", alarm_time, current_time, sound_alarm);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,588 | module | module comparator_stimulus;
reg [3:0] alarm_time, current_time;
reg show_a;
wire [3:0] display_time;
wire sound_alarm;
comp_dismux C1(alarm_time, current_time, show_a, sound_alarm, display_time);
initial
begin
show_a = 1'b0;
alarm_time = 4'b0000;
current_time = 4'b1111;
end
initial
begin
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 alarm_time = 4'b0001; current_time = 4'b0001;
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 $finish;
end
initial
begin
$monitor($time, "alarm_time = %d, current_time = %d, alarm = %b\n", alarm_time, current_time, sound_alarm);
end
endmodule | module comparator_stimulus; |
reg [3:0] alarm_time, current_time;
reg show_a;
wire [3:0] display_time;
wire sound_alarm;
comp_dismux C1(alarm_time, current_time, show_a, sound_alarm, display_time);
initial
begin
show_a = 1'b0;
alarm_time = 4'b0000;
current_time = 4'b1111;
end
initial
begin
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 alarm_time = 4'b0001; current_time = 4'b0001;
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 $finish;
end
initial
begin
$monitor($time, "alarm_time = %d, current_time = %d, alarm = %b\n", alarm_time, current_time, sound_alarm);
end
endmodule | 0 |
140,980 | data/full_repos/permissive/93120196/clock/compartor.v | 93,120,196 | compartor.v | v | 23 | 84 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/2b8c29ae-353d-426d-a078-24d8e1d32adc.xml | null | 310,589 | module | module comp_dismux(alarm_time, current_time, show_a, sound_alarm, display_time);
input [3:0] alarm_time, current_time;
input show_a;
output [3:0] display_time;
output sound_alarm;
wire [3:0] display_time;
wire [3:0] show_a_vector;
reg sound_alarm;
assign show_a_vector = {4{show_a}};
assign display_time = (alarm_time & show_a_vector | current_time & ~show_a_vector);
always@(alarm_time or current_time)
begin
if (alarm_time == current_time)
sound_alarm <= 1;
else
sound_alarm <= 0;
end
endmodule | module comp_dismux(alarm_time, current_time, show_a, sound_alarm, display_time); |
input [3:0] alarm_time, current_time;
input show_a;
output [3:0] display_time;
output sound_alarm;
wire [3:0] display_time;
wire [3:0] show_a_vector;
reg sound_alarm;
assign show_a_vector = {4{show_a}};
assign display_time = (alarm_time & show_a_vector | current_time & ~show_a_vector);
always@(alarm_time or current_time)
begin
if (alarm_time == current_time)
sound_alarm <= 1;
else
sound_alarm <= 0;
end
endmodule | 0 |
140,981 | data/full_repos/permissive/93120196/clock/counting_logic.v | 93,120,196 | counting_logic.v | v | 97 | 72 | [] | [] | [] | [(1, 97)] | null | data/verilator_xmls/4da53617-1e84-43b0-9790-ab77acd8f22c.xml | null | 310,590 | module | module counting_logic(new_current_time_ls_min, new_current_time_ms_min,
new_current_time_ls_hr, new_current_time_ms_hr, new_current_time_AM,
load_new_c, reset, clk, one_minute,
current_time_ls_min, current_time_ms_min,
current_time_ls_hr, current_time_ms_hr, current_time_AM);
input [3:0] new_current_time_ls_min,
new_current_time_ms_min,
new_current_time_ls_hr,
new_current_time_ms_hr;
input new_current_time_AM;
input load_new_c, reset, clk, one_minute;
output [3:0] current_time_ls_min,
current_time_ms_min,
current_time_ls_hr,
current_time_ms_hr;
output current_time_AM;
reg [3:0] ls_min, ms_min, ls_hr, ms_hr;
reg AM;
wire [3:0] current_time_ls_min,
current_time_ms_min,
current_time_ls_hr,
current_time_ms_hr;
wire current_time_AM;
always@ (posedge clk or posedge reset)
begin
if (reset)
begin
ls_min <= 4'b0000;
ms_min <= 4'b0000;
ls_hr <= 4'b0000;
ms_hr <= 4'b0000;
AM <= 1'b0;
end
else if (load_new_c)
begin
ls_min <= new_current_time_ls_min;
ms_min <= new_current_time_ms_min;
ls_hr <= new_current_time_ls_hr;
ms_hr <= new_current_time_ms_hr;
AM <= new_current_time_AM;
end
else
begin
if(one_minute)
begin
if (ls_min == 9)
begin
ls_min <= 0;
if (ms_min == 5)
begin
ms_min <= 0;
if (ls_hr == 2)
begin
if(ms_hr == 1)
begin
ms_hr <= 0;
ls_hr <= 1;
AM <= ~AM;
end
end
else if (ls_hr == 9)
begin
ms_hr <= ms_hr + 1;
ls_hr <= 0;
end
else
begin
ls_hr <= ls_hr+1;
end
end
else
begin
ms_min <= ms_min + 1;
end
end
else
begin
ls_min <= ls_min + 1;
end
end
end
end
assign current_time_ls_min = ls_min;
assign current_time_ms_min = ms_min;
assign current_time_ls_hr = ls_hr;
assign current_time_ms_hr = ms_hr;
assign current_time_AM = AM;
endmodule | module counting_logic(new_current_time_ls_min, new_current_time_ms_min,
new_current_time_ls_hr, new_current_time_ms_hr, new_current_time_AM,
load_new_c, reset, clk, one_minute,
current_time_ls_min, current_time_ms_min,
current_time_ls_hr, current_time_ms_hr, current_time_AM); |
input [3:0] new_current_time_ls_min,
new_current_time_ms_min,
new_current_time_ls_hr,
new_current_time_ms_hr;
input new_current_time_AM;
input load_new_c, reset, clk, one_minute;
output [3:0] current_time_ls_min,
current_time_ms_min,
current_time_ls_hr,
current_time_ms_hr;
output current_time_AM;
reg [3:0] ls_min, ms_min, ls_hr, ms_hr;
reg AM;
wire [3:0] current_time_ls_min,
current_time_ms_min,
current_time_ls_hr,
current_time_ms_hr;
wire current_time_AM;
always@ (posedge clk or posedge reset)
begin
if (reset)
begin
ls_min <= 4'b0000;
ms_min <= 4'b0000;
ls_hr <= 4'b0000;
ms_hr <= 4'b0000;
AM <= 1'b0;
end
else if (load_new_c)
begin
ls_min <= new_current_time_ls_min;
ms_min <= new_current_time_ms_min;
ls_hr <= new_current_time_ls_hr;
ms_hr <= new_current_time_ms_hr;
AM <= new_current_time_AM;
end
else
begin
if(one_minute)
begin
if (ls_min == 9)
begin
ls_min <= 0;
if (ms_min == 5)
begin
ms_min <= 0;
if (ls_hr == 2)
begin
if(ms_hr == 1)
begin
ms_hr <= 0;
ls_hr <= 1;
AM <= ~AM;
end
end
else if (ls_hr == 9)
begin
ms_hr <= ms_hr + 1;
ls_hr <= 0;
end
else
begin
ls_hr <= ls_hr+1;
end
end
else
begin
ms_min <= ms_min + 1;
end
end
else
begin
ls_min <= ls_min + 1;
end
end
end
end
assign current_time_ls_min = ls_min;
assign current_time_ms_min = ms_min;
assign current_time_ls_hr = ls_hr;
assign current_time_ms_hr = ms_hr;
assign current_time_AM = AM;
endmodule | 0 |
140,982 | data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v | 93,120,196 | counting_logic_stimulus.v | v | 74 | 200 | [] | [] | [] | null | line:65: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:52: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:53: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5 load_new_c = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:57: Unsupported: Ignoring delay on this delayed statement.\n #5 new_current_time_ms_hr = 4\'b0001; new_current_time_ls_hr = 4\'b0010; new_current_time_ms_min = 4\'b0101; new_current_time_ls_min = 4\'b1000; new_current_time_AM = 1\'b1; load_new_c = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:58: Unsupported: Ignoring delay on this delayed statement.\n #5 load_new_c = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:60: Unsupported: Ignoring delay on this delayed statement.\n #1 one_minute = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:62: Unsupported: Ignoring delay on this delayed statement.\n #20 one_minute = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:63: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:64: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/counting_logic_stimulus.v:70: Unsupported or unknown PLI call: $monitor\n $monitor($time, "c_time = [%d][%d]:[%d][%d][AM=%b], load_c = %d, reset = %d\\n", current_time_ms_hr, current_time_ls_hr, current_time_ms_min, current_time_ls_min, current_time_AM, load_new_c, reset);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,591 | module | module counting_logic_stimulus;
reg [3:0] new_current_time_ls_min,
new_current_time_ms_min,
new_current_time_ls_hr,
new_current_time_ms_hr;
reg new_current_time_AM;
reg load_new_c, reset, clk, one_minute;
wire [3:0] current_time_ls_min,
current_time_ms_min,
current_time_ls_hr,
current_time_ms_hr;
wire current_time_AM;
counting_logic C1(new_current_time_ls_min, new_current_time_ms_min,
new_current_time_ls_hr, new_current_time_ms_hr, new_current_time_AM,
load_new_c, reset, clk, one_minute,
current_time_ls_min, current_time_ms_min,
current_time_ls_hr, current_time_ms_hr, current_time_AM);
initial
begin
reset = 1'b0;
clk = 1'b0;
one_minute = 1'b0;
new_current_time_ls_min = 4'b0000;
new_current_time_ms_min = 4'b0000;
new_current_time_ls_hr = 4'b0000;
new_current_time_ms_hr = 4'b0000;
new_current_time_ms_hr = 1'b0;
new_current_time_AM = 1'b0;
load_new_c = 1'b0;
end
initial
begin
forever
begin
#1 clk = ~clk;
end
end
initial
begin
#5 reset = 1'b1;
#5 reset = 1'b0;
#5 load_new_c = 1'b0;
#5 new_current_time_ms_hr = 4'b0001; new_current_time_ls_hr = 4'b0010; new_current_time_ms_min = 4'b0101; new_current_time_ls_min = 4'b1000; new_current_time_AM = 1'b1; load_new_c = 1'b1;
#5 load_new_c = 1'b0;
#1 one_minute = 1'b1;
#20 one_minute = 1'b0;
#1 reset = 1'b1;
#1 reset = 1'b0;
#10 $finish;
end
initial
begin
$monitor($time, "c_time = [%d][%d]:[%d][%d][AM=%b], load_c = %d, reset = %d\n", current_time_ms_hr, current_time_ls_hr, current_time_ms_min, current_time_ls_min, current_time_AM, load_new_c, reset);
end
endmodule | module counting_logic_stimulus; |
reg [3:0] new_current_time_ls_min,
new_current_time_ms_min,
new_current_time_ls_hr,
new_current_time_ms_hr;
reg new_current_time_AM;
reg load_new_c, reset, clk, one_minute;
wire [3:0] current_time_ls_min,
current_time_ms_min,
current_time_ls_hr,
current_time_ms_hr;
wire current_time_AM;
counting_logic C1(new_current_time_ls_min, new_current_time_ms_min,
new_current_time_ls_hr, new_current_time_ms_hr, new_current_time_AM,
load_new_c, reset, clk, one_minute,
current_time_ls_min, current_time_ms_min,
current_time_ls_hr, current_time_ms_hr, current_time_AM);
initial
begin
reset = 1'b0;
clk = 1'b0;
one_minute = 1'b0;
new_current_time_ls_min = 4'b0000;
new_current_time_ms_min = 4'b0000;
new_current_time_ls_hr = 4'b0000;
new_current_time_ms_hr = 4'b0000;
new_current_time_ms_hr = 1'b0;
new_current_time_AM = 1'b0;
load_new_c = 1'b0;
end
initial
begin
forever
begin
#1 clk = ~clk;
end
end
initial
begin
#5 reset = 1'b1;
#5 reset = 1'b0;
#5 load_new_c = 1'b0;
#5 new_current_time_ms_hr = 4'b0001; new_current_time_ls_hr = 4'b0010; new_current_time_ms_min = 4'b0101; new_current_time_ls_min = 4'b1000; new_current_time_AM = 1'b1; load_new_c = 1'b1;
#5 load_new_c = 1'b0;
#1 one_minute = 1'b1;
#20 one_minute = 1'b0;
#1 reset = 1'b1;
#1 reset = 1'b0;
#10 $finish;
end
initial
begin
$monitor($time, "c_time = [%d][%d]:[%d][%d][AM=%b], load_c = %d, reset = %d\n", current_time_ms_hr, current_time_ls_hr, current_time_ms_min, current_time_ls_min, current_time_AM, load_new_c, reset);
end
endmodule | 0 |
140,983 | data/full_repos/permissive/93120196/clock/display_time.v | 93,120,196 | display_time.v | v | 59 | 77 | [] | [] | [] | [(1, 54)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:41: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'zero_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0000: display <= zero_seg;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:42: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'one_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0001: display <= one_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:43: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'two_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0010: display <= two_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:44: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'three_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0011: display <= three_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:45: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'four_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0100: display <= four_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:46: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'five_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0101: display <= five_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:47: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'six_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0110: display <= six_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:48: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'seven_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b0111: display <= seven_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:49: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'eight_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b1000: display <= eight_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:50: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'nine_seg\' generates 7 bits.\n : ... In instance display_time\n 4\'b1001: display <= nine_seg;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/93120196/clock/display_time.v:51: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'err_seg\' generates 7 bits.\n : ... In instance display_time\n default: display <= err_seg;\n ^~\n%Error: Exiting due to 11 warning(s)\n' | 310,592 | module | module display_time(alarm_time, current_time, show_a, sound_alarm, display);
input [3:0] alarm_time, current_time;
input show_a;
output sound_alarm;
output [7:0] display;
parameter zero_seg = 7'b0111111,
one_seg = 7'b0000011,
two_seg = 7'b1101101,
three_seg = 7'b1100111,
four_seg = 7'b1010011,
five_seg = 7'b1110110,
six_seg = 7'b1111110,
seven_seg = 7'b0100011,
eight_seg = 7'b1111111,
nine_seg = 7'b1110111,
err_seg = 7'b1000000;
reg sound_alarm;
reg [3:0] display_time;
reg [6:0] display;
always@(alarm_time or current_time or show_a)
begin
if (show_a)
display_time <= alarm_time;
else
display_time <= current_time;
if (alarm_time == current_time)
sound_alarm <= 1;
else
sound_alarm <= 0;
end
always @ (display_time)
begin
case (display_time)
4'b0000: display <= zero_seg;
4'b0001: display <= one_seg;
4'b0010: display <= two_seg;
4'b0011: display <= three_seg;
4'b0100: display <= four_seg;
4'b0101: display <= five_seg;
4'b0110: display <= six_seg;
4'b0111: display <= seven_seg;
4'b1000: display <= eight_seg;
4'b1001: display <= nine_seg;
default: display <= err_seg;
endcase
end
endmodule | module display_time(alarm_time, current_time, show_a, sound_alarm, display); |
input [3:0] alarm_time, current_time;
input show_a;
output sound_alarm;
output [7:0] display;
parameter zero_seg = 7'b0111111,
one_seg = 7'b0000011,
two_seg = 7'b1101101,
three_seg = 7'b1100111,
four_seg = 7'b1010011,
five_seg = 7'b1110110,
six_seg = 7'b1111110,
seven_seg = 7'b0100011,
eight_seg = 7'b1111111,
nine_seg = 7'b1110111,
err_seg = 7'b1000000;
reg sound_alarm;
reg [3:0] display_time;
reg [6:0] display;
always@(alarm_time or current_time or show_a)
begin
if (show_a)
display_time <= alarm_time;
else
display_time <= current_time;
if (alarm_time == current_time)
sound_alarm <= 1;
else
sound_alarm <= 0;
end
always @ (display_time)
begin
case (display_time)
4'b0000: display <= zero_seg;
4'b0001: display <= one_seg;
4'b0010: display <= two_seg;
4'b0011: display <= three_seg;
4'b0100: display <= four_seg;
4'b0101: display <= five_seg;
4'b0110: display <= six_seg;
4'b0111: display <= seven_seg;
4'b1000: display <= eight_seg;
4'b1001: display <= nine_seg;
default: display <= err_seg;
endcase
end
endmodule | 0 |
140,984 | data/full_repos/permissive/93120196/clock/display_time_stimulus.v | 93,120,196 | display_time_stimulus.v | v | 34 | 150 | [] | [] | [] | null | line:26: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/display_time_stimulus.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0010;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/display_time_stimulus.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 show_a = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/display_time_stimulus.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 show_a = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/display_time_stimulus.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/display_time_stimulus.v:25: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/display_time_stimulus.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/display_time_stimulus.v:31: Unsupported or unknown PLI call: $monitor\n $monitor($time, "display time = %b, a_time = %b, cur_time = %b, alarm = %b, show_a = %b\\n", display, alarm_time, current_time, sound_alarm, show_a);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,593 | module | module display_time_stimulus;
reg [3:0] alarm_time, current_time;
reg show_a;
wire sound_alarm;
wire [7:0] display;
display_time C1(alarm_time, current_time, show_a, sound_alarm, display);
initial
begin
show_a = 1'b0;
alarm_time = 4'b0001;
current_time = 4'b0111;
end
initial
begin
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 show_a = 1'b1;
#5 show_a = 1'b0;
#5 alarm_time = 4'b0001; current_time = 4'b0001;
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 $finish;
end
initial
begin
$monitor($time, "display time = %b, a_time = %b, cur_time = %b, alarm = %b, show_a = %b\n", display, alarm_time, current_time, sound_alarm, show_a);
end
endmodule | module display_time_stimulus; |
reg [3:0] alarm_time, current_time;
reg show_a;
wire sound_alarm;
wire [7:0] display;
display_time C1(alarm_time, current_time, show_a, sound_alarm, display);
initial
begin
show_a = 1'b0;
alarm_time = 4'b0001;
current_time = 4'b0111;
end
initial
begin
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 show_a = 1'b1;
#5 show_a = 1'b0;
#5 alarm_time = 4'b0001; current_time = 4'b0001;
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 $finish;
end
initial
begin
$monitor($time, "display time = %b, a_time = %b, cur_time = %b, alarm = %b, show_a = %b\n", display, alarm_time, current_time, sound_alarm, show_a);
end
endmodule | 0 |
140,985 | data/full_repos/permissive/93120196/clock/fsm.v | 93,120,196 | fsm.v | v | 236 | 125 | [] | [] | [] | null | line:79: before: "reset" | null | 1: b"%Error: data/full_repos/permissive/93120196/clock/fsm.v:41: syntax error, unexpected '(', expecting IDENTIFIER\nmultiplexer(alarm_time, current_time, show_a, display_time);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93120196/clock/fsm.v:178: syntax error, unexpected ';', expecting ',' or ':'\n MM_seg;\n ^\n%Error: data/full_repos/permissive/93120196/clock/fsm.v:184: syntax error, unexpected ':'\n key_stored:\n ^\n%Error: data/full_repos/permissive/93120196/clock/fsm.v:233: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: Cannot continue\n" | 310,594 | module | module fsm(clk, reset, key, alarm_button, time_button, one_second, load_new_a, show_a, show_new_time, load_new_c, shift);
input clk, reset, alarm_button, time_button, one_second;
input [3:0] key;
output load_new_a, show_a, show_new_time, load_new_c, shift;
parameter show_time = 3'b000,
key_entry = 3'b001,
key_stored = 3'b010,
show_alarm = 3'b011,
set_alarm_time = 3'b100,
set_current_time = 3'b101,
key_waited = 3'b110,
flashing = 3'b111;
wire load_new_a, show_a, show_new_time, load_new_c, shift;
reg [2:0] present_state;
reg [2:0] next_state;
reg [3:0] num_keys;
reg [3:0] wait_time;
display_time C1(alarm_time, current_time, show_a, sound_alarm, display);
multiplexer(alarm_time, current_time, show_a, display_time);
comp_dismux(alarm_time, current_time, show_a, sound_alarm, display_time);
counting_logic C2(new_current_time_ls_min, new_current_time_ms_min,
new_current_time_ls_hr, new_current_time_ms_hr, new_current_time_AM,
load_new_c, reset, clk, one_minute,
current_time_ls_min, current_time_ms_min,
current_time_ls_hr, current_time_ms_hr, current_time_AM);
keypad C3(key, columns, rows);
keyscan C5(clk, reset, shift, rows, columns, key,
key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3,
time_button, alarm_button);
register_alarm_clock C4(new_current_alarm_ls_min, new_current_alarm_ms_min,
new_current_alarm_ls_hr, new_current_alarm_ms_hr, new_current_alarm_AM,
load_new_a, reset_a,
current_alarm_ls_min, current_alarm_ms_min,
current_alarm_ls_hr, current_alarm_ms_hr, current_alarm_AM);
timegen C6(clk, reset, stopwatch, one_second, one_minute);
seven_segment LM(LM_digit, LM_seg);
seven_segment MM(MM_digit, MM_seg);
seven_segment LH(LH_digit, LH_seg);
seven_segment MH(MH_digit, MH_seg);
always @(posedge clk or reset)
begin
if (reset == 1'b1)
present_state = show_time;
else
present_state = next_state;
end
always @(posedge clk or data_in)
begin
case(present_state)
show_time:
if (key)
next_state = key_entry;
else if (show_a)
next_state = show_alarm;
else
next_state = show_time;
key_entry:
if(num_keys == 3'b100)
if (key == 4'b1010)
next_state = set_alarm_time;
else if (key == 4'b1011)
next_state = set_current_time;
else
next_state = show_time;
else if(key == 4'b1010)
next_state = show_time;
else if(key == 4'b1011)
next_state = show_alarm;
else
next_state = key_waited;
key_stored:
if(num_keys == 3'b100)
if(load_new_a)
next_state = set_alarm_time;
else if (load_new_c)
next_state = set_current_time;
else
next_state = show_time;
else if(key)
next_state = key_entry;
show_alarm:
if(key)
next_state = key_entry;
set_alarm_time:
next_state = show_time;
set_current_time:
next_state = show_time;
key_waited:
if(key)
next_state = key_stored;
else
next_state = key_entry;
flashing:
if(key)
next_state = key_entry;
endcase
end
always@(posedge clk or data_in)
begin
case (present_state)
show_time:
LM_seg;
MM_seg;
LH_seg;
MH_seg;
key_entry:
key_stored:
if(num_keys == 3'b100)
if (key == 4'b1010)
next_state = set_alarm_time;
else if (key == 4'b1011)
next_state = set_current_time;
show_alarm:
LM_seg;
MM_seg;
LH_seg;
MH_seg;
set_alarm_time:
LM_digit = new_current_alarm_ls_min;
MM_digit = new_current_alarm_ms_min;
LH_digit = new_current_alarm_ls_hr;
MH_digit = new_current_alarm_ms_hr;
set_current_time:
LM_digit = new_current_time_ls_min;
MM_digit = new_current_time_ms_min;
LH_digit = new_current_time_ls_hr;
MH_digit = new_current_time_ms_hr;
key_waited:
if(num_keys == 3'b000)
num_keys = 3'b001;
else if(num_keys == 3'b001)
num_keys = 3'b010;
else if(num_keys == 3'b010)
num_keys = 3'b011;
else if(num_keys == 3'b011)
num_keys = 3'b100;
else
num_keys = 3'b000;
flashing:
endcase
end
endmodule | module fsm(clk, reset, key, alarm_button, time_button, one_second, load_new_a, show_a, show_new_time, load_new_c, shift); |
input clk, reset, alarm_button, time_button, one_second;
input [3:0] key;
output load_new_a, show_a, show_new_time, load_new_c, shift;
parameter show_time = 3'b000,
key_entry = 3'b001,
key_stored = 3'b010,
show_alarm = 3'b011,
set_alarm_time = 3'b100,
set_current_time = 3'b101,
key_waited = 3'b110,
flashing = 3'b111;
wire load_new_a, show_a, show_new_time, load_new_c, shift;
reg [2:0] present_state;
reg [2:0] next_state;
reg [3:0] num_keys;
reg [3:0] wait_time;
display_time C1(alarm_time, current_time, show_a, sound_alarm, display);
multiplexer(alarm_time, current_time, show_a, display_time);
comp_dismux(alarm_time, current_time, show_a, sound_alarm, display_time);
counting_logic C2(new_current_time_ls_min, new_current_time_ms_min,
new_current_time_ls_hr, new_current_time_ms_hr, new_current_time_AM,
load_new_c, reset, clk, one_minute,
current_time_ls_min, current_time_ms_min,
current_time_ls_hr, current_time_ms_hr, current_time_AM);
keypad C3(key, columns, rows);
keyscan C5(clk, reset, shift, rows, columns, key,
key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3,
time_button, alarm_button);
register_alarm_clock C4(new_current_alarm_ls_min, new_current_alarm_ms_min,
new_current_alarm_ls_hr, new_current_alarm_ms_hr, new_current_alarm_AM,
load_new_a, reset_a,
current_alarm_ls_min, current_alarm_ms_min,
current_alarm_ls_hr, current_alarm_ms_hr, current_alarm_AM);
timegen C6(clk, reset, stopwatch, one_second, one_minute);
seven_segment LM(LM_digit, LM_seg);
seven_segment MM(MM_digit, MM_seg);
seven_segment LH(LH_digit, LH_seg);
seven_segment MH(MH_digit, MH_seg);
always @(posedge clk or reset)
begin
if (reset == 1'b1)
present_state = show_time;
else
present_state = next_state;
end
always @(posedge clk or data_in)
begin
case(present_state)
show_time:
if (key)
next_state = key_entry;
else if (show_a)
next_state = show_alarm;
else
next_state = show_time;
key_entry:
if(num_keys == 3'b100)
if (key == 4'b1010)
next_state = set_alarm_time;
else if (key == 4'b1011)
next_state = set_current_time;
else
next_state = show_time;
else if(key == 4'b1010)
next_state = show_time;
else if(key == 4'b1011)
next_state = show_alarm;
else
next_state = key_waited;
key_stored:
if(num_keys == 3'b100)
if(load_new_a)
next_state = set_alarm_time;
else if (load_new_c)
next_state = set_current_time;
else
next_state = show_time;
else if(key)
next_state = key_entry;
show_alarm:
if(key)
next_state = key_entry;
set_alarm_time:
next_state = show_time;
set_current_time:
next_state = show_time;
key_waited:
if(key)
next_state = key_stored;
else
next_state = key_entry;
flashing:
if(key)
next_state = key_entry;
endcase
end
always@(posedge clk or data_in)
begin
case (present_state)
show_time:
LM_seg;
MM_seg;
LH_seg;
MH_seg;
key_entry:
key_stored:
if(num_keys == 3'b100)
if (key == 4'b1010)
next_state = set_alarm_time;
else if (key == 4'b1011)
next_state = set_current_time;
show_alarm:
LM_seg;
MM_seg;
LH_seg;
MH_seg;
set_alarm_time:
LM_digit = new_current_alarm_ls_min;
MM_digit = new_current_alarm_ms_min;
LH_digit = new_current_alarm_ls_hr;
MH_digit = new_current_alarm_ms_hr;
set_current_time:
LM_digit = new_current_time_ls_min;
MM_digit = new_current_time_ms_min;
LH_digit = new_current_time_ls_hr;
MH_digit = new_current_time_ms_hr;
key_waited:
if(num_keys == 3'b000)
num_keys = 3'b001;
else if(num_keys == 3'b001)
num_keys = 3'b010;
else if(num_keys == 3'b010)
num_keys = 3'b011;
else if(num_keys == 3'b011)
num_keys = 3'b100;
else
num_keys = 3'b000;
flashing:
endcase
end
endmodule | 0 |
140,986 | data/full_repos/permissive/93120196/clock/keypad.v | 93,120,196 | keypad.v | v | 31 | 66 | [] | [] | [] | [(4, 31)] | null | data/verilator_xmls/48225abd-537d-4786-b45d-db51b9ac5dbd.xml | null | 310,595 | module | module keypad (key, columns, rows);
input [3:0] key;
input [2:0] columns;
output [3:0] rows;
reg [3:0] rows;
always @ (key or columns)
begin
rows <= 4'b0000;
case (key)
0 : rows[0] <= columns[1];
1 : rows[3] <= columns[2];
2 : rows[3] <= columns[1];
3 : rows[3] <= columns[0];
4 : rows[2] <= columns[2];
5 : rows[2] <= columns[1];
6 : rows[2] <= columns[0];
7 : rows[1] <= columns[2];
8 : rows[1] <= columns[1];
9 : rows[1] <= columns[0];
10 : rows[0] <= columns[2];
11 : rows[0] <= columns[0];
endcase
end
endmodule | module keypad (key, columns, rows); |
input [3:0] key;
input [2:0] columns;
output [3:0] rows;
reg [3:0] rows;
always @ (key or columns)
begin
rows <= 4'b0000;
case (key)
0 : rows[0] <= columns[1];
1 : rows[3] <= columns[2];
2 : rows[3] <= columns[1];
3 : rows[3] <= columns[0];
4 : rows[2] <= columns[2];
5 : rows[2] <= columns[1];
6 : rows[2] <= columns[0];
7 : rows[1] <= columns[2];
8 : rows[1] <= columns[1];
9 : rows[1] <= columns[0];
10 : rows[0] <= columns[2];
11 : rows[0] <= columns[0];
endcase
end
endmodule | 0 |
140,987 | data/full_repos/permissive/93120196/clock/keypad_stimulus.v | 93,120,196 | keypad_stimulus.v | v | 35 | 89 | [] | [] | [] | null | line:27: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keypad_stimulus.v:19: Unsupported: Ignoring delay on this delayed statement.\n #5 key_a = 4\'b0100; columns_a = 3\'b100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keypad_stimulus.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 key_a = 4\'b1000; columns_a = 3\'b010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keypad_stimulus.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 key_a = 4\'b0010; columns_a = 3\'b010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keypad_stimulus.v:25: Unsupported: Ignoring delay on this delayed statement.\n #5 key_a = 4\'b0001; columns_a = 3\'b100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keypad_stimulus.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/keypad_stimulus.v:32: Unsupported or unknown PLI call: $monitor\n $monitor($time, "key_row = %b, key_col = %b, value = %d \\n", rows_a, columns_a, key_a);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,596 | module | module keypad_stimulus;
reg [2:0] columns_a;
reg [3:0] key_a;
wire [3:0] rows_a;
keypad C1(key_a, columns_a, rows_a);
initial
begin
columns_a = 3'b000;
key_a = 4'b0000;
end
initial
begin
#5 key_a = 4'b0100; columns_a = 3'b100;
#5 key_a = 4'b1000; columns_a = 3'b010;
#5 key_a = 4'b0010; columns_a = 3'b010;
#5 key_a = 4'b0001; columns_a = 3'b100;
#10 $finish;
end
initial
begin
$monitor($time, "key_row = %b, key_col = %b, value = %d \n", rows_a, columns_a, key_a);
end
endmodule | module keypad_stimulus; |
reg [2:0] columns_a;
reg [3:0] key_a;
wire [3:0] rows_a;
keypad C1(key_a, columns_a, rows_a);
initial
begin
columns_a = 3'b000;
key_a = 4'b0000;
end
initial
begin
#5 key_a = 4'b0100; columns_a = 3'b100;
#5 key_a = 4'b1000; columns_a = 3'b010;
#5 key_a = 4'b0010; columns_a = 3'b010;
#5 key_a = 4'b0001; columns_a = 3'b100;
#10 $finish;
end
initial
begin
$monitor($time, "key_row = %b, key_col = %b, value = %d \n", rows_a, columns_a, key_a);
end
endmodule | 0 |
140,988 | data/full_repos/permissive/93120196/clock/keyscan.v | 93,120,196 | keyscan.v | v | 125 | 139 | [] | [] | [] | [(13, 125)] | null | data/verilator_xmls/e5f4e39c-9295-4bde-8cbb-c5dbddb9f2e2.xml | null | 310,597 | module | module keyscan (clk, reset, shift, rows, columns, key, key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3, time_button, alarm_button);
input clk, reset, shift;
input [3:0] rows;
output [2:0] columns;
output [3:0] key;
output [3:0] key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3;
output time_button, alarm_button;
parameter nokey = 4'b1010;
reg [3:0] new_row, old_row;
reg [2:0] new_column, old_column;
reg [2:0] columns;
reg [3:0] key;
reg [3:0] key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3;
reg time_button, alarm_button;
always@(posedge clk)
begin
if(reset)
columns <=0;
else
case (columns)
3'b111 : columns <= 3'b011;
3'b011 : columns <= 3'b101;
3'b101 : columns <= 3'b110;
3'b110 : columns <= 3'b111;
default: columns <= 3'b111;
endcase
end
always@(posedge clk)
begin
if (reset)
begin
new_row <= 0;
old_row <=0;
new_column <=0;
old_column <=0;
key <= nokey;
time_button <= 0;
alarm_button <=0;
end
else
begin
if (rows[0] == 0 | rows[1] == 0|rows[2] == 0 | rows[3] == 0)
begin
new_row <= rows;
new_column <= columns;
end
if(columns == 3'b111)
begin
time_button <=0;
alarm_button <= 0;
key <= nokey;
if ((new_row == old_row) & (new_column==old_column))
case (old_column)
3'b011:
case(old_row)
4'b0111: key <=4'b0001;
4'b1011: key <=4'b0100;
4'b1101: key <=4'b0111;
4'b1110: alarm_button <=1;
endcase
3'b101:
case(old_row)
4'b0111: key <=4'b0010;
4'b1011: key <=4'b0101;
4'b1101: key <=4'b1000;
4'b1110: key <=4'b0000;
endcase
3'b110:
case(old_row)
4'b0111: key <=4'b0011;
4'b1011: key <=4'b0110;
4'b1101: key <=4'b1001;
4'b1110: time_button <=1;
endcase
endcase
old_row <= new_row;
old_column <= new_column;
new_row <= 4'b1111;
new_column <= 3'b111;
end
end
end
always@(posedge clk)
begin
if(reset)
begin
key_buffer_0 <=0;
key_buffer_1 <=0;
key_buffer_2 <=0;
key_buffer_3 <=0;
end
else
if(shift==1)
begin
key_buffer_3 <=key_buffer_2;
key_buffer_2 <=key_buffer_1;
key_buffer_1 <=key_buffer_0;
key_buffer_0 <=key;
end
end
endmodule | module keyscan (clk, reset, shift, rows, columns, key, key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3, time_button, alarm_button); |
input clk, reset, shift;
input [3:0] rows;
output [2:0] columns;
output [3:0] key;
output [3:0] key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3;
output time_button, alarm_button;
parameter nokey = 4'b1010;
reg [3:0] new_row, old_row;
reg [2:0] new_column, old_column;
reg [2:0] columns;
reg [3:0] key;
reg [3:0] key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3;
reg time_button, alarm_button;
always@(posedge clk)
begin
if(reset)
columns <=0;
else
case (columns)
3'b111 : columns <= 3'b011;
3'b011 : columns <= 3'b101;
3'b101 : columns <= 3'b110;
3'b110 : columns <= 3'b111;
default: columns <= 3'b111;
endcase
end
always@(posedge clk)
begin
if (reset)
begin
new_row <= 0;
old_row <=0;
new_column <=0;
old_column <=0;
key <= nokey;
time_button <= 0;
alarm_button <=0;
end
else
begin
if (rows[0] == 0 | rows[1] == 0|rows[2] == 0 | rows[3] == 0)
begin
new_row <= rows;
new_column <= columns;
end
if(columns == 3'b111)
begin
time_button <=0;
alarm_button <= 0;
key <= nokey;
if ((new_row == old_row) & (new_column==old_column))
case (old_column)
3'b011:
case(old_row)
4'b0111: key <=4'b0001;
4'b1011: key <=4'b0100;
4'b1101: key <=4'b0111;
4'b1110: alarm_button <=1;
endcase
3'b101:
case(old_row)
4'b0111: key <=4'b0010;
4'b1011: key <=4'b0101;
4'b1101: key <=4'b1000;
4'b1110: key <=4'b0000;
endcase
3'b110:
case(old_row)
4'b0111: key <=4'b0011;
4'b1011: key <=4'b0110;
4'b1101: key <=4'b1001;
4'b1110: time_button <=1;
endcase
endcase
old_row <= new_row;
old_column <= new_column;
new_row <= 4'b1111;
new_column <= 3'b111;
end
end
end
always@(posedge clk)
begin
if(reset)
begin
key_buffer_0 <=0;
key_buffer_1 <=0;
key_buffer_2 <=0;
key_buffer_3 <=0;
end
else
if(shift==1)
begin
key_buffer_3 <=key_buffer_2;
key_buffer_2 <=key_buffer_1;
key_buffer_1 <=key_buffer_0;
key_buffer_0 <=key;
end
end
endmodule | 0 |
140,989 | data/full_repos/permissive/93120196/clock/keyscan_stimulus.v | 93,120,196 | keyscan_stimulus.v | v | 53 | 148 | [] | [] | [] | null | line:45: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keyscan_stimulus.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keyscan_stimulus.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5 shift = 1\'b0; rows = 3\'b100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keyscan_stimulus.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5 shift = 1\'b1; rows = 3\'b010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keyscan_stimulus.v:41: Unsupported: Ignoring delay on this delayed statement.\n #5 shift = 1\'b1; rows = 3\'b100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keyscan_stimulus.v:43: Unsupported: Ignoring delay on this delayed statement.\n #5 shift = 1\'b1; rows = 3\'b100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/keyscan_stimulus.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/keyscan_stimulus.v:50: Unsupported or unknown PLI call: $monitor\n $monitor($time, "rows = %b, shift = %b, key = %d, [%d][%d][%d][%d] \\n", rows, shift, key, key_buffer_3, key_buffer_2, key_buffer_1, key_buffer_0);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,598 | module | module keyscan_stimulus;
reg clk, reset, shift;
reg [3:0] rows;
wire [2:0] columns;
wire [3:0] key;
wire [3:0] key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3;
wire time_button, alarm_button;
keyscan C1(clk, reset, shift, rows, columns, key,
key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3,
time_button, alarm_button);
initial
begin
reset = 1'b0;
shift = 1'b0;
rows = 3'b000;
clk = 1'b0;
end
initial
begin
forever
begin
#1 clk = ~clk;
end
end
initial
begin
#5 shift = 1'b0; rows = 3'b100;
#5 shift = 1'b1; rows = 3'b010;
#5 shift = 1'b1; rows = 3'b100;
#5 shift = 1'b1; rows = 3'b100;
#10 $finish;
end
initial
begin
$monitor($time, "rows = %b, shift = %b, key = %d, [%d][%d][%d][%d] \n", rows, shift, key, key_buffer_3, key_buffer_2, key_buffer_1, key_buffer_0);
end
endmodule | module keyscan_stimulus; |
reg clk, reset, shift;
reg [3:0] rows;
wire [2:0] columns;
wire [3:0] key;
wire [3:0] key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3;
wire time_button, alarm_button;
keyscan C1(clk, reset, shift, rows, columns, key,
key_buffer_0, key_buffer_1, key_buffer_2, key_buffer_3,
time_button, alarm_button);
initial
begin
reset = 1'b0;
shift = 1'b0;
rows = 3'b000;
clk = 1'b0;
end
initial
begin
forever
begin
#1 clk = ~clk;
end
end
initial
begin
#5 shift = 1'b0; rows = 3'b100;
#5 shift = 1'b1; rows = 3'b010;
#5 shift = 1'b1; rows = 3'b100;
#5 shift = 1'b1; rows = 3'b100;
#10 $finish;
end
initial
begin
$monitor($time, "rows = %b, shift = %b, key = %d, [%d][%d][%d][%d] \n", rows, shift, key, key_buffer_3, key_buffer_2, key_buffer_1, key_buffer_0);
end
endmodule | 0 |
140,990 | data/full_repos/permissive/93120196/clock/multiplexer.v | 93,120,196 | multiplexer.v | v | 14 | 84 | [] | [] | [] | [(1, 14)] | null | data/verilator_xmls/9971b97f-2d77-4847-a6dd-2de0b9582f90.xml | null | 310,599 | module | module multiplexer(alarm_time, current_time, show_a, display_time);
input [3:0] alarm_time, current_time;
input show_a;
output [3:0] display_time;
wire [3:0] display_time;
wire [3:0] show_a_vector;
assign show_a_vector = {4{show_a}};
assign display_time = (alarm_time & show_a_vector)|(current_time & ~show_a_vector);
endmodule | module multiplexer(alarm_time, current_time, show_a, display_time); |
input [3:0] alarm_time, current_time;
input show_a;
output [3:0] display_time;
wire [3:0] display_time;
wire [3:0] show_a_vector;
assign show_a_vector = {4{show_a}};
assign display_time = (alarm_time & show_a_vector)|(current_time & ~show_a_vector);
endmodule | 0 |
140,991 | data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v | 93,120,196 | multiplexer_stimulus.v | v | 33 | 130 | [] | [] | [] | null | line:25: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v:20: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0010;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 show_a = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 show_a = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 alarm_time = 4\'b0001; current_time = 4\'b0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v:25: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/multiplexer_stimulus.v:30: Unsupported or unknown PLI call: $monitor\n $monitor($time, "display time = %b, a_time = %b, cur_time = %b, show_a = %b\\n", display_time, alarm_time, current_time, show_a);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,600 | module | module multiplexer_stimulus;
reg [3:0] alarm_time, current_time;
reg show_a;
wire [3:0] display_time;
multiplexer C1(alarm_time, current_time, show_a, display_time);
initial
begin
show_a = 1'b0;
alarm_time = 4'b0000;
current_time = 4'b1111;
end
initial
begin
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 show_a = 1'b1;
#5 show_a = 1'b0;
#5 alarm_time = 4'b0001; current_time = 4'b0001;
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 $finish;
end
initial
begin
$monitor($time, "display time = %b, a_time = %b, cur_time = %b, show_a = %b\n", display_time, alarm_time, current_time, show_a);
end
endmodule | module multiplexer_stimulus; |
reg [3:0] alarm_time, current_time;
reg show_a;
wire [3:0] display_time;
multiplexer C1(alarm_time, current_time, show_a, display_time);
initial
begin
show_a = 1'b0;
alarm_time = 4'b0000;
current_time = 4'b1111;
end
initial
begin
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 show_a = 1'b1;
#5 show_a = 1'b0;
#5 alarm_time = 4'b0001; current_time = 4'b0001;
#5 alarm_time = 4'b0001; current_time = 4'b0010;
#5 $finish;
end
initial
begin
$monitor($time, "display time = %b, a_time = %b, cur_time = %b, show_a = %b\n", display_time, alarm_time, current_time, show_a);
end
endmodule | 0 |
140,992 | data/full_repos/permissive/93120196/clock/register_alarm_clock.v | 93,120,196 | register_alarm_clock.v | v | 60 | 80 | [] | [] | [] | [(1, 60)] | null | data/verilator_xmls/4f19c3d3-f1b3-4277-8cbd-6ce340de8448.xml | null | 310,601 | module | module register_alarm_clock(new_current_alarm_ls_min, new_current_alarm_ms_min,
new_current_alarm_ls_hr, new_current_alarm_ms_hr, new_current_alarm_AM,
load_new_a, reset_a,
current_alarm_ls_min, current_alarm_ms_min,
current_alarm_ls_hr, current_alarm_ms_hr, current_alarm_AM);
input [3:0] new_current_alarm_ls_min,
new_current_alarm_ms_min,
new_current_alarm_ls_hr,
new_current_alarm_ms_hr;
input load_new_a, reset_a, new_current_alarm_AM;
output [3:0] current_alarm_ls_min,
current_alarm_ms_min,
current_alarm_ls_hr,
current_alarm_ms_hr;
output current_alarm_AM;
reg [3:0] ls_a_min, ms_a_min, ls_a_hr, ms_a_hr;
reg a_AM;
wire [3:0] current_alarm_ls_min,
current_alarm_ms_min,
current_alarm_ls_hr,
current_alarm_ms_hr;
wire current_alarm_AM;
always@ (posedge reset_a or posedge load_new_a)
begin
if (reset_a)
begin
ls_a_min <= 4'b0000;
ms_a_min <= 4'b0000;
ls_a_hr <= 4'b0000;
ms_a_hr <= 4'b0000;
a_AM <= 1'b0;
end
else if (load_new_a)
begin
ls_a_min <= new_current_alarm_ls_min;
ms_a_min <= new_current_alarm_ms_min;
ls_a_hr <= new_current_alarm_ls_hr;
ms_a_hr <= new_current_alarm_ms_hr;
a_AM <= new_current_alarm_AM;
end
end
assign current_alarm_ls_min = ls_a_min;
assign current_alarm_ms_min = ms_a_min;
assign current_alarm_ls_hr = ls_a_hr;
assign current_alarm_ms_hr = ms_a_hr;
assign current_alarm_AM = a_AM;
endmodule | module register_alarm_clock(new_current_alarm_ls_min, new_current_alarm_ms_min,
new_current_alarm_ls_hr, new_current_alarm_ms_hr, new_current_alarm_AM,
load_new_a, reset_a,
current_alarm_ls_min, current_alarm_ms_min,
current_alarm_ls_hr, current_alarm_ms_hr, current_alarm_AM); |
input [3:0] new_current_alarm_ls_min,
new_current_alarm_ms_min,
new_current_alarm_ls_hr,
new_current_alarm_ms_hr;
input load_new_a, reset_a, new_current_alarm_AM;
output [3:0] current_alarm_ls_min,
current_alarm_ms_min,
current_alarm_ls_hr,
current_alarm_ms_hr;
output current_alarm_AM;
reg [3:0] ls_a_min, ms_a_min, ls_a_hr, ms_a_hr;
reg a_AM;
wire [3:0] current_alarm_ls_min,
current_alarm_ms_min,
current_alarm_ls_hr,
current_alarm_ms_hr;
wire current_alarm_AM;
always@ (posedge reset_a or posedge load_new_a)
begin
if (reset_a)
begin
ls_a_min <= 4'b0000;
ms_a_min <= 4'b0000;
ls_a_hr <= 4'b0000;
ms_a_hr <= 4'b0000;
a_AM <= 1'b0;
end
else if (load_new_a)
begin
ls_a_min <= new_current_alarm_ls_min;
ms_a_min <= new_current_alarm_ms_min;
ls_a_hr <= new_current_alarm_ls_hr;
ms_a_hr <= new_current_alarm_ms_hr;
a_AM <= new_current_alarm_AM;
end
end
assign current_alarm_ls_min = ls_a_min;
assign current_alarm_ms_min = ms_a_min;
assign current_alarm_ls_hr = ls_a_hr;
assign current_alarm_ms_hr = ms_a_hr;
assign current_alarm_AM = a_AM;
endmodule | 0 |
140,993 | data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v | 93,120,196 | register_alarm_clock_stimulus.v | v | 58 | 217 | [] | [] | [] | null | line:46: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5 reset_a = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5 reset_a = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5 load_new_a = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5 new_current_alarm_ls_min = 4\'b0010; new_current_alarm_ms_min = 4\'b0100; new_current_alarm_ls_hr = 4\'b0010; new_current_alarm_ms_hr = 4\'b0001; new_current_alarm_am = 1\'b1; load_new_a = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:43: Unsupported: Ignoring delay on this delayed statement.\n #5 load_new_a = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 reset_a = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5 reset_a = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/register_alarm_clock_stimulus.v:51: Unsupported or unknown PLI call: $monitor\n $monitor($time, "display_a_time = [%d][%d]:[%d][%d][AM=%b], load_a = %d, reset_a = %d\\n", current_alarm_ms_hr, current_alarm_ls_hr, current_alarm_ms_min, current_alarm_ls_min, current_alarm_am, load_new_a, reset_a);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,602 | module | module register_alarm_clock_stimulus;
reg [3:0] new_current_alarm_ls_min,
new_current_alarm_ms_min,
new_current_alarm_ls_hr,
new_current_alarm_ms_hr;
reg new_current_alarm_am;
reg load_new_a, reset_a;
wire [3:0] current_alarm_ls_min,
current_alarm_ms_min,
current_alarm_ls_hr,
current_alarm_ms_hr;
wire current_alarm_am;
register_alarm_clock C1(new_current_alarm_ls_min, new_current_alarm_ms_min,
new_current_alarm_ls_hr, new_current_alarm_ms_hr, new_current_alarm_am,
load_new_a, reset_a,
current_alarm_ls_min, current_alarm_ms_min,
current_alarm_ls_hr, current_alarm_ms_hr, current_alarm_am);
initial
begin
new_current_alarm_ls_min = 4'b0000;
new_current_alarm_ms_min = 4'b0000;
new_current_alarm_ls_hr = 4'b0000;
new_current_alarm_ms_hr = 4'b0000;
new_current_alarm_am = 1'b0;
load_new_a = 1'b0;
reset_a = 1'b0;
end
initial
begin
#5 reset_a = 1'b1;
#5 reset_a = 1'b0;
#5 load_new_a = 1'b0;
#5 new_current_alarm_ls_min = 4'b0010; new_current_alarm_ms_min = 4'b0100; new_current_alarm_ls_hr = 4'b0010; new_current_alarm_ms_hr = 4'b0001; new_current_alarm_am = 1'b1; load_new_a = 1'b1;
#5 load_new_a = 1'b0;
#5 reset_a = 1'b1;
#5 reset_a = 1'b0;
#10 $finish;
end
initial
begin
$monitor($time, "display_a_time = [%d][%d]:[%d][%d][AM=%b], load_a = %d, reset_a = %d\n", current_alarm_ms_hr, current_alarm_ls_hr, current_alarm_ms_min, current_alarm_ls_min, current_alarm_am, load_new_a, reset_a);
end
endmodule | module register_alarm_clock_stimulus; |
reg [3:0] new_current_alarm_ls_min,
new_current_alarm_ms_min,
new_current_alarm_ls_hr,
new_current_alarm_ms_hr;
reg new_current_alarm_am;
reg load_new_a, reset_a;
wire [3:0] current_alarm_ls_min,
current_alarm_ms_min,
current_alarm_ls_hr,
current_alarm_ms_hr;
wire current_alarm_am;
register_alarm_clock C1(new_current_alarm_ls_min, new_current_alarm_ms_min,
new_current_alarm_ls_hr, new_current_alarm_ms_hr, new_current_alarm_am,
load_new_a, reset_a,
current_alarm_ls_min, current_alarm_ms_min,
current_alarm_ls_hr, current_alarm_ms_hr, current_alarm_am);
initial
begin
new_current_alarm_ls_min = 4'b0000;
new_current_alarm_ms_min = 4'b0000;
new_current_alarm_ls_hr = 4'b0000;
new_current_alarm_ms_hr = 4'b0000;
new_current_alarm_am = 1'b0;
load_new_a = 1'b0;
reset_a = 1'b0;
end
initial
begin
#5 reset_a = 1'b1;
#5 reset_a = 1'b0;
#5 load_new_a = 1'b0;
#5 new_current_alarm_ls_min = 4'b0010; new_current_alarm_ms_min = 4'b0100; new_current_alarm_ls_hr = 4'b0010; new_current_alarm_ms_hr = 4'b0001; new_current_alarm_am = 1'b1; load_new_a = 1'b1;
#5 load_new_a = 1'b0;
#5 reset_a = 1'b1;
#5 reset_a = 1'b0;
#10 $finish;
end
initial
begin
$monitor($time, "display_a_time = [%d][%d]:[%d][%d][AM=%b], load_a = %d, reset_a = %d\n", current_alarm_ms_hr, current_alarm_ls_hr, current_alarm_ms_min, current_alarm_ls_min, current_alarm_am, load_new_a, reset_a);
end
endmodule | 0 |
140,994 | data/full_repos/permissive/93120196/clock/seven_segment.v | 93,120,196 | seven_segment.v | v | 42 | 44 | [] | [] | [] | null | line:3: before: "input" | null | 1: b"%Error: data/full_repos/permissive/93120196/clock/seven_segment.v:3: syntax error, unexpected input, expecting ';'\ninput [3:0]digit;\n^~~~~\n%Error: data/full_repos/permissive/93120196/clock/seven_segment.v:22: syntax error, unexpected always\nalways @ (digit)\n^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 310,603 | module | module seven_segment(digit, seven_seg_vals)
input [3:0]digit;
output [3:0]seven_seg_vals;
parameter zero_seg = 7'b0111111,
one_seg = 7'b0000011,
two_seg = 7'b1101101,
three_seg = 7'b1100111,
four_seg = 7'b1010011,
five_seg = 7'b1110110,
six_seg = 7'b1111110,
seven_seg = 7'b0100011,
eight_seg = 7'b1111111,
nine_seg = 7'b1110111,
err_seg = 7'b1000000,
none_seg = 7'b0000000;
always @ (digit)
begin
case (digit)
4'b0000: seven_seg_vals <= zero_seg;
4'b0001: seven_seg_vals <= one_seg;
4'b0010: seven_seg_vals <= two_seg;
4'b0011: seven_seg_vals <= three_seg;
4'b0100: seven_seg_vals <= four_seg;
4'b0101: seven_seg_vals <= five_seg;
4'b0110: seven_seg_vals <= six_seg;
4'b0111: seven_seg_vals <= seven_seg;
4'b1000: seven_seg_vals <= eight_seg;
4'b1001: seven_seg_vals <= nine_seg;
4'b1111: seven_seg_vals <= nine_seg;
default: seven_seg_vals <= err_seg;
endcase
end
endmodule | module seven_segment(digit, seven_seg_vals)
input [3:0]digit; |
output [3:0]seven_seg_vals;
parameter zero_seg = 7'b0111111,
one_seg = 7'b0000011,
two_seg = 7'b1101101,
three_seg = 7'b1100111,
four_seg = 7'b1010011,
five_seg = 7'b1110110,
six_seg = 7'b1111110,
seven_seg = 7'b0100011,
eight_seg = 7'b1111111,
nine_seg = 7'b1110111,
err_seg = 7'b1000000,
none_seg = 7'b0000000;
always @ (digit)
begin
case (digit)
4'b0000: seven_seg_vals <= zero_seg;
4'b0001: seven_seg_vals <= one_seg;
4'b0010: seven_seg_vals <= two_seg;
4'b0011: seven_seg_vals <= three_seg;
4'b0100: seven_seg_vals <= four_seg;
4'b0101: seven_seg_vals <= five_seg;
4'b0110: seven_seg_vals <= six_seg;
4'b0111: seven_seg_vals <= seven_seg;
4'b1000: seven_seg_vals <= eight_seg;
4'b1001: seven_seg_vals <= nine_seg;
4'b1111: seven_seg_vals <= nine_seg;
default: seven_seg_vals <= err_seg;
endcase
end
endmodule | 0 |
140,995 | data/full_repos/permissive/93120196/clock/stimulus_four_digit.v | 93,120,196 | stimulus_four_digit.v | v | 50 | 179 | [] | [] | [] | null | line:42: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row <= 2\'b01; key_col <= 2\'b00;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:27: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row <= 2\'b00; key_col <= 2\'b10; key_buffer_in <= key_buffer_out;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:32: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row <= 2\'b10; key_col <= 2\'b01; key_buffer_in <= key_buffer_out;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:36: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row <= 2\'b11; key_col <= 2\'b01; key_buffer_in <= key_buffer_out;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5 keypad_int = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/stimulus_four_digit.v:47: Unsupported or unknown PLI call: $monitor\n $monitor($time, "key_row = %b, key_col = %b, value = %b [%b][%b][%b] \\n", key_row, key_col, key_buffer_out[15:12],key_buffer_out[11:8],key_buffer_out[7:4],key_buffer_out[3:0]);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,604 | module | module stimulus_ac_four_digit;
reg [1:0]key_row;
reg [1:0]key_col;
reg keypad_int;
reg clk;
reg [15:0]key_buffer_in;
wire [15:0]key_buffer_out;
ac_four_digit C1(key_buffer_out, key_buffer_in, keypad_int, clk, key_row, key_col);
initial
begin
key_row = 2'b00;
key_col = 2'b00;
keypad_int = 1'b0;
key_buffer_in = 16'b0000000000000000;
end
initial
begin
#5 key_row <= 2'b01; key_col <= 2'b00;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#5 key_row <= 2'b00; key_col <= 2'b10; key_buffer_in <= key_buffer_out;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#5 key_row <= 2'b10; key_col <= 2'b01; key_buffer_in <= key_buffer_out;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#5 key_row <= 2'b11; key_col <= 2'b01; key_buffer_in <= key_buffer_out;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#10 $finish;
end
initial
begin
$monitor($time, "key_row = %b, key_col = %b, value = %b [%b][%b][%b] \n", key_row, key_col, key_buffer_out[15:12],key_buffer_out[11:8],key_buffer_out[7:4],key_buffer_out[3:0]);
end
endmodule | module stimulus_ac_four_digit; |
reg [1:0]key_row;
reg [1:0]key_col;
reg keypad_int;
reg clk;
reg [15:0]key_buffer_in;
wire [15:0]key_buffer_out;
ac_four_digit C1(key_buffer_out, key_buffer_in, keypad_int, clk, key_row, key_col);
initial
begin
key_row = 2'b00;
key_col = 2'b00;
keypad_int = 1'b0;
key_buffer_in = 16'b0000000000000000;
end
initial
begin
#5 key_row <= 2'b01; key_col <= 2'b00;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#5 key_row <= 2'b00; key_col <= 2'b10; key_buffer_in <= key_buffer_out;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#5 key_row <= 2'b10; key_col <= 2'b01; key_buffer_in <= key_buffer_out;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#5 key_row <= 2'b11; key_col <= 2'b01; key_buffer_in <= key_buffer_out;
#5 keypad_int = 1'b1;
#5 keypad_int = 1'b0;
#10 $finish;
end
initial
begin
$monitor($time, "key_row = %b, key_col = %b, value = %b [%b][%b][%b] \n", key_row, key_col, key_buffer_out[15:12],key_buffer_out[11:8],key_buffer_out[7:4],key_buffer_out[3:0]);
end
endmodule | 0 |
140,996 | data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v | 93,120,196 | stimulus_keypad_scanner.v | v | 45 | 88 | [] | [] | [] | null | line:37: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:20: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row = 2\'b01; key_col = 2\'b00;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row = 2\'b00; key_col = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:25: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row = 2\'b10; key_col = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:32: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row = 2\'b11; key_col = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5 stimulus = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:36: Unsupported: Ignoring delay on this delayed statement.\n #5 key_row = 2\'b10; key_col = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/stimulus_keypad_scanner.v:42: Unsupported or unknown PLI call: $monitor\n $monitor($time, "key_row = %b, key_col = %b, value = %d \\n", key_row, key_col, value);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 14 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,605 | module | module stimulus_keypad_scanner;
reg [1:0]key_row;
reg [1:0]key_col;
reg stimulus;
wire [3:0]value;
keypad_scanner C1(value, key_row, key_col, stimulus);
initial
begin
key_row = 2'b00;
key_col = 2'b00;
stimulus = 1'b0;
end
initial
begin
#5 key_row = 2'b01; key_col = 2'b00;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b00; key_col = 2'b10;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b10; key_col = 2'b01;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b11; key_col = 2'b01;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b10; key_col = 2'b01;
#10 $finish;
end
initial
begin
$monitor($time, "key_row = %b, key_col = %b, value = %d \n", key_row, key_col, value);
end
endmodule | module stimulus_keypad_scanner; |
reg [1:0]key_row;
reg [1:0]key_col;
reg stimulus;
wire [3:0]value;
keypad_scanner C1(value, key_row, key_col, stimulus);
initial
begin
key_row = 2'b00;
key_col = 2'b00;
stimulus = 1'b0;
end
initial
begin
#5 key_row = 2'b01; key_col = 2'b00;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b00; key_col = 2'b10;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b10; key_col = 2'b01;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b11; key_col = 2'b01;
#5 stimulus = 1'b1;
#5 stimulus = 1'b0;
#5 key_row = 2'b10; key_col = 2'b01;
#10 $finish;
end
initial
begin
$monitor($time, "key_row = %b, key_col = %b, value = %d \n", key_row, key_col, value);
end
endmodule | 0 |
140,997 | data/full_repos/permissive/93120196/clock/timegen.v | 93,120,196 | timegen.v | v | 42 | 84 | [] | [] | [] | [(1, 42)] | null | data/verilator_xmls/23d531ec-28e2-4be4-a1ef-b849617de7ae.xml | null | 310,606 | module | module timegen (clk, reset, stopwatch, one_second, one_minute);
input clk, reset, stopwatch;
output one_second, one_minute;
parameter LIMIT = ((256*60)-1);
reg one_second, one_minute;
reg [13:0]one_minute_count;
always @(posedge clk or posedge reset)
begin
if(reset)
one_minute_count <= 0;
else
one_minute_count <= (one_minute_count == LIMIT) ? 0: one_minute_count+1;
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
one_second <= 0;
end
else
begin
one_second <= (one_minute_count[7:0] == 0);
one_minute <= stopwatch ? (one_minute_count[7:0] == 0) : (one_minute_count == 0);
end
end
endmodule | module timegen (clk, reset, stopwatch, one_second, one_minute); |
input clk, reset, stopwatch;
output one_second, one_minute;
parameter LIMIT = ((256*60)-1);
reg one_second, one_minute;
reg [13:0]one_minute_count;
always @(posedge clk or posedge reset)
begin
if(reset)
one_minute_count <= 0;
else
one_minute_count <= (one_minute_count == LIMIT) ? 0: one_minute_count+1;
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
one_second <= 0;
end
else
begin
one_second <= (one_minute_count[7:0] == 0);
one_minute <= stopwatch ? (one_minute_count[7:0] == 0) : (one_minute_count == 0);
end
end
endmodule | 0 |
140,998 | data/full_repos/permissive/93120196/clock/timegen_stimulus.v | 93,120,196 | timegen_stimulus.v | v | 36 | 81 | [] | [] | [] | null | line:28: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/timegen_stimulus.v:21: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/timegen_stimulus.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93120196/clock/timegen_stimulus.v:28: Unsupported: Ignoring delay on this delayed statement.\n #60000 $finish;\n ^\n%Error: data/full_repos/permissive/93120196/clock/timegen_stimulus.v:33: Unsupported or unknown PLI call: $monitor\n $monitor($time, "one_second = %d, one_minute = %d \\n", one_second, one_minute);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,607 | module | module timegen_stimulus;
reg clk, reset, stopwatch;
wire one_second, one_minute;
timegen C1(clk, reset, stopwatch, one_second, one_minute);
initial
begin
reset = 1'b1;
stopwatch = 1'b0;
clk = 1'b0;
end
initial
begin
forever
begin
#1 clk = ~clk;
end
end
initial
begin
#2 reset = 1'b0;
#60000 $finish;
end
initial
begin
$monitor($time, "one_second = %d, one_minute = %d \n", one_second, one_minute);
end
endmodule | module timegen_stimulus; |
reg clk, reset, stopwatch;
wire one_second, one_minute;
timegen C1(clk, reset, stopwatch, one_second, one_minute);
initial
begin
reset = 1'b1;
stopwatch = 1'b0;
clk = 1'b0;
end
initial
begin
forever
begin
#1 clk = ~clk;
end
end
initial
begin
#2 reset = 1'b0;
#60000 $finish;
end
initial
begin
$monitor($time, "one_second = %d, one_minute = %d \n", one_second, one_minute);
end
endmodule | 0 |
140,999 | data/full_repos/permissive/93120196/state_machine/mealy_sm_1001.v | 93,120,196 | mealy_sm_1001.v | v | 65 | 55 | [] | [] | [] | null | line:13: before: "reset" | data/verilator_xmls/b3295763-f224-42ee-9006-c33a328970f3.xml | null | 310,608 | module | module mealy_sm_1001(data_out, data_in, clock, reset);
output data_out;
reg data_out;
input data_in, reset, clock;
reg [1:0] present_state, next_state;
parameter S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;
always @(posedge clock or reset)
begin
if (reset == 1'b1)
present_state = S0;
else
present_state = next_state;
end
always @(posedge clock or data_in)
begin
case(present_state)
S0:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S1;
S1:
if(data_in == 1'b0)
next_state = S2;
else
next_state = S1;
S2:
if(data_in == 1'b0)
next_state = S3;
else
next_state = S1;
S3:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S0;
endcase
end
always@(posedge clock or data_in)
begin
case (present_state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b0;
S2:
data_out = 1'b0;
S3:
if (data_in == 1'b0)
data_out = 1'b0;
else
data_out = 1'b1;
endcase
end
endmodule | module mealy_sm_1001(data_out, data_in, clock, reset); |
output data_out;
reg data_out;
input data_in, reset, clock;
reg [1:0] present_state, next_state;
parameter S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;
always @(posedge clock or reset)
begin
if (reset == 1'b1)
present_state = S0;
else
present_state = next_state;
end
always @(posedge clock or data_in)
begin
case(present_state)
S0:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S1;
S1:
if(data_in == 1'b0)
next_state = S2;
else
next_state = S1;
S2:
if(data_in == 1'b0)
next_state = S3;
else
next_state = S1;
S3:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S0;
endcase
end
always@(posedge clock or data_in)
begin
case (present_state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b0;
S2:
data_out = 1'b0;
S3:
if (data_in == 1'b0)
data_out = 1'b0;
else
data_out = 1'b1;
endcase
end
endmodule | 0 |
141,000 | data/full_repos/permissive/93120196/state_machine/moore_sm_1001.v | 93,120,196 | moore_sm_1001.v | v | 67 | 55 | [] | [] | [] | null | line:13: before: "reset" | data/verilator_xmls/9c2d7fb0-71b0-4b24-8f9d-b592f3309e4a.xml | null | 310,609 | module | module moore_sm_1001(data_out, data_in, clock, reset);
output data_out;
reg data_out;
input data_in, reset, clock;
reg [2:0] present_state, next_state;
parameter S0 = 3'b000,
S1 = 3'b001,
S2 = 3'b010,
S3 = 3'b011,
S4 = 3'b100;
always@(posedge clock or reset)
begin
if (reset)
present_state = S0;
else
present_state = next_state;
end
always@(posedge clock or data_in)
begin
case (present_state)
S0:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S1;
S1:
if(data_in == 1'b0)
next_state = S2;
else
next_state = S1;
S2:
if(data_in == 1'b0)
next_state = S3;
else
next_state = S1;
S3:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S4;
S4:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S1;
endcase
end
always@(present_state)
begin
case(present_state)
S0: data_out = 1'b0;
S1: data_out = 1'b0;
S2: data_out = 1'b0;
S3: data_out = 1'b0;
S4: data_out = 1'b1;
endcase
end
endmodule | module moore_sm_1001(data_out, data_in, clock, reset); |
output data_out;
reg data_out;
input data_in, reset, clock;
reg [2:0] present_state, next_state;
parameter S0 = 3'b000,
S1 = 3'b001,
S2 = 3'b010,
S3 = 3'b011,
S4 = 3'b100;
always@(posedge clock or reset)
begin
if (reset)
present_state = S0;
else
present_state = next_state;
end
always@(posedge clock or data_in)
begin
case (present_state)
S0:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S1;
S1:
if(data_in == 1'b0)
next_state = S2;
else
next_state = S1;
S2:
if(data_in == 1'b0)
next_state = S3;
else
next_state = S1;
S3:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S4;
S4:
if(data_in == 1'b0)
next_state = S0;
else
next_state = S1;
endcase
end
always@(present_state)
begin
case(present_state)
S0: data_out = 1'b0;
S1: data_out = 1'b0;
S2: data_out = 1'b0;
S3: data_out = 1'b0;
S4: data_out = 1'b1;
endcase
end
endmodule | 0 |
141,001 | data/full_repos/permissive/93128889/synthX/audio_out.v | 93,128,889 | audio_out.v | v | 71 | 77 | [] | [] | [] | [(7, 70)] | null | null | 1: b"%Error: data/full_repos/permissive/93128889/synthX/audio_out.v:24: Cannot find file containing module: 'pll_audio'\n pll_audio PLL_AUDIO\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/pll_audio\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/pll_audio.v\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/pll_audio.sv\n pll_audio\n pll_audio.v\n pll_audio.sv\n obj_dir/pll_audio\n obj_dir/pll_audio.v\n obj_dir/pll_audio.sv\n%Error: data/full_repos/permissive/93128889/synthX/audio_out.v:43: Cannot find file containing module: 'dcfifo_audio'\n dcfifo_audio DCFIFO_AUDIO\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/93128889/synthX/audio_out.v:59: Cannot find file containing module: 'i2s_tx'\n i2s_tx I2S_TX\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 310,610 | module | module audio_out
(
input clk,
input aclr,
input [63:0] sample,
input wrreq,
output wrfull,
output lrck,
output bck,
output dout,
output sck
);
wire pll_locked;
wire clk_48kHz, clk_96kHz, clk_3MHz;
pll_audio PLL_AUDIO
(
.areset(aclr),
.inclk0(clk),
.c0 (clk_3MHz),
.c1 (clk_48kHz),
.c2 (clk_96kHz),
.locked(pll_locked)
);
assign bck = clk_3MHz;
assign sck = clk;
wire [63:0] sample_out;
wire i2s_ready_for_sample;
wire rdempty;
wire sample_ready;
dcfifo_audio DCFIFO_AUDIO
(
.aclr(aclr),
.data(sample),
.rdclk(clk_3MHz),
.rdreq(i2s_ready_for_sample),
.wrclk(clk),
.wrreq(wrreq),
.q(sample_out),
.rdempty(rdempty),
.wrfull(wrfull)
);
assign sample_ready = !rdempty;
i2s_tx I2S_TX
(
.sclk(clk_3MHz),
.aclr(aclr),
.lrck(lrck),
.dout(dout),
.ready(i2s_ready_for_sample),
.sample_ready(sample_ready),
.sample(sample_out)
);
endmodule | module audio_out
(
input clk,
input aclr,
input [63:0] sample,
input wrreq,
output wrfull,
output lrck,
output bck,
output dout,
output sck
); |
wire pll_locked;
wire clk_48kHz, clk_96kHz, clk_3MHz;
pll_audio PLL_AUDIO
(
.areset(aclr),
.inclk0(clk),
.c0 (clk_3MHz),
.c1 (clk_48kHz),
.c2 (clk_96kHz),
.locked(pll_locked)
);
assign bck = clk_3MHz;
assign sck = clk;
wire [63:0] sample_out;
wire i2s_ready_for_sample;
wire rdempty;
wire sample_ready;
dcfifo_audio DCFIFO_AUDIO
(
.aclr(aclr),
.data(sample),
.rdclk(clk_3MHz),
.rdreq(i2s_ready_for_sample),
.wrclk(clk),
.wrreq(wrreq),
.q(sample_out),
.rdempty(rdempty),
.wrfull(wrfull)
);
assign sample_ready = !rdempty;
i2s_tx I2S_TX
(
.sclk(clk_3MHz),
.aclr(aclr),
.lrck(lrck),
.dout(dout),
.ready(i2s_ready_for_sample),
.sample_ready(sample_ready),
.sample(sample_out)
);
endmodule | 0 |
141,002 | data/full_repos/permissive/93128889/synthX/audio_out_tb.v | 93,128,889 | audio_out_tb.v | v | 65 | 42 | [] | [] | [] | null | line:41: before: "#" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_PERIOD_NS/2) clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #150 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 2 * 2700)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 2 * 5400)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Error: data/full_repos/permissive/93128889/synthX/audio_out_tb.v:18: Cannot find file containing module: \'audio_out\'\n audio_out MUT\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/audio_out\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/audio_out.v\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/audio_out.sv\n audio_out\n audio_out.v\n audio_out.sv\n obj_dir/audio_out\n obj_dir/audio_out.v\n obj_dir/audio_out.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,611 | module | module audio_out_tb();
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
reg aclr = 0;
reg wrreq = 0;
reg [63:0] sample = 64'd0;
wire wrfull;
wire lrck;
wire bck;
wire dout;
wire sck;
audio_out MUT
(
.clk(clk),
.aclr(aclr),
.sample(sample),
.wrreq(wrreq),
.wrfull(wrfull),
.lrck(lrck),
.bck(bck),
.dout(dout),
.sck(sck)
);
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1;
#CLOCK_PERIOD_NS
aclr <= 0;
#CLOCK_PERIOD_NS
sample[63:32] <= 1024;
sample[31:0] <= 4000;
#150
#CLOCK_PERIOD_NS
wrreq <= 1;
#CLOCK_PERIOD_NS
wrreq <= 0;
#(CLOCK_PERIOD_NS * 2 * 2700)
sample[63:32] <= 3743;
sample[31:0] <= 255;
wrreq <= 1;
#CLOCK_PERIOD_NS
wrreq <= 0;
#CLOCK_PERIOD_NS
sample[63:32] <= 255;
sample[31:0] <= 3743;
wrreq <= 1;
#CLOCK_PERIOD_NS
wrreq <= 0;
#CLOCK_PERIOD_NS
#(CLOCK_PERIOD_NS * 2 * 5400)
$finish;
end
endmodule | module audio_out_tb(); |
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
reg aclr = 0;
reg wrreq = 0;
reg [63:0] sample = 64'd0;
wire wrfull;
wire lrck;
wire bck;
wire dout;
wire sck;
audio_out MUT
(
.clk(clk),
.aclr(aclr),
.sample(sample),
.wrreq(wrreq),
.wrfull(wrfull),
.lrck(lrck),
.bck(bck),
.dout(dout),
.sck(sck)
);
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1;
#CLOCK_PERIOD_NS
aclr <= 0;
#CLOCK_PERIOD_NS
sample[63:32] <= 1024;
sample[31:0] <= 4000;
#150
#CLOCK_PERIOD_NS
wrreq <= 1;
#CLOCK_PERIOD_NS
wrreq <= 0;
#(CLOCK_PERIOD_NS * 2 * 2700)
sample[63:32] <= 3743;
sample[31:0] <= 255;
wrreq <= 1;
#CLOCK_PERIOD_NS
wrreq <= 0;
#CLOCK_PERIOD_NS
sample[63:32] <= 255;
sample[31:0] <= 3743;
wrreq <= 1;
#CLOCK_PERIOD_NS
wrreq <= 0;
#CLOCK_PERIOD_NS
#(CLOCK_PERIOD_NS * 2 * 5400)
$finish;
end
endmodule | 0 |
141,003 | data/full_repos/permissive/93128889/synthX/i2s_tx.v | 93,128,889 | i2s_tx.v | v | 96 | 72 | [] | [] | [] | [(1, 95)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93128889/synthX/i2s_tx.v:20: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance i2s_tx\n bits <= 1\'b1;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93128889/synthX/i2s_tx.v:22: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance i2s_tx\n bits <= 1\'b1;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 310,615 | module | module i2s_tx
(
input sclk,
input aclr,
output reg lrck,
output reg dout,
output reg ready,
input sample_ready,
input [63:0] sample
);
reg [5:0] bits;
reg [31:0] left;
reg [31:0] right;
reg sample_valid;
always @(negedge sclk or posedge aclr)
begin
if (aclr)
bits <= 1'b1;
else if (bits == 32)
bits <= 1'b1;
else
bits <= bits + 1'b1;
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
begin
left <= 32'd0;
right <= 32'd0;
end
else if (bits == 32 && lrck)
begin
if (sample_valid)
begin
left <= sample[63:32];
right <= sample[31:0];
end
else
begin
left <= 32'd0;
right <= 32'd0;
end
end
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
begin
ready <= 1;
end
else if (bits == 32 && lrck)
begin
ready <= 1;
end
else
begin
ready <= 0;
end
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
sample_valid <= 0;
else if (bits == 32 && lrck)
sample_valid <= sample_ready;
else
sample_valid <= sample_valid;
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
begin
lrck <= 1;
end
else if (bits == 32)
begin
lrck <= !lrck;
end
end
always @(negedge sclk)
begin
dout <= lrck ? right[32 - bits] : left[32 - bits];
end
endmodule | module i2s_tx
(
input sclk,
input aclr,
output reg lrck,
output reg dout,
output reg ready,
input sample_ready,
input [63:0] sample
); |
reg [5:0] bits;
reg [31:0] left;
reg [31:0] right;
reg sample_valid;
always @(negedge sclk or posedge aclr)
begin
if (aclr)
bits <= 1'b1;
else if (bits == 32)
bits <= 1'b1;
else
bits <= bits + 1'b1;
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
begin
left <= 32'd0;
right <= 32'd0;
end
else if (bits == 32 && lrck)
begin
if (sample_valid)
begin
left <= sample[63:32];
right <= sample[31:0];
end
else
begin
left <= 32'd0;
right <= 32'd0;
end
end
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
begin
ready <= 1;
end
else if (bits == 32 && lrck)
begin
ready <= 1;
end
else
begin
ready <= 0;
end
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
sample_valid <= 0;
else if (bits == 32 && lrck)
sample_valid <= sample_ready;
else
sample_valid <= sample_valid;
end
always @(negedge sclk or posedge aclr)
begin
if (aclr)
begin
lrck <= 1;
end
else if (bits == 32)
begin
lrck <= !lrck;
end
end
always @(negedge sclk)
begin
dout <= lrck ? right[32 - bits] : left[32 - bits];
end
endmodule | 0 |
141,004 | data/full_repos/permissive/93128889/synthX/karplus_strong.v | 93,128,889 | karplus_strong.v | v | 176 | 90 | [] | [] | [] | [(1, 175)] | null | null | 1: b"%Error: data/full_repos/permissive/93128889/synthX/karplus_strong.v:158: Cannot find file containing module: 'shift_reg'\n shift_reg KS1\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/shift_reg\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/shift_reg.v\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/shift_reg.sv\n shift_reg\n shift_reg.v\n shift_reg.sv\n obj_dir/shift_reg\n obj_dir/shift_reg.v\n obj_dir/shift_reg.sv\n%Error: data/full_repos/permissive/93128889/synthX/karplus_strong.v:168: Cannot find file containing module: 'signed_mult'\n signed_mult GAINFACTOR\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 310,616 | module | module karplus_strong
(
input clk,
input aclr,
input clk_sample,
input trigger,
input [11:0] tone,
input [2:0] cutoff,
output [15:0] sample
);
reg last_trigger;
reg [11:0] trigger_count;
reg [3:0] state;
reg last_clk;
wire [17:0] gain;
assign gain = 18'h0_7EB8;
reg [11:0] ptr_in, ptr_out;
reg we;
wire [17:0] sr_data;
reg [17:0] write_data;
reg [11:0] addr_reg;
reg [17:0] out, in_data, out_data;
wire [17:0] new_out;
assign sample = out[17:2];
wire x_low_bit;
reg [30:0] x_rand;
wire [17:0] new_lopass;
reg [17:0] lopass;
assign x_low_bit = x_rand[27] ^ x_rand[30];
assign new_lopass = lopass + ((( (x_low_bit)?18'h1_0000:18'h3_0000) - lopass)>>>cutoff);
always @(posedge clk_sample or posedge aclr)
begin
if (aclr)
begin
x_rand <= 31'h55555555;
lopass <= 18'h0;
end
else
begin
x_rand <= { x_rand[29:0], x_low_bit };
lopass <= new_lopass;
end
end
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
ptr_out <= 12'h1;
ptr_in <= 12'h0;
we <= 1'b0;
state <= 4'd9;
last_clk <= 1'b1;
trigger_count <= 12'd0;
last_trigger <= 1'b0;
end
else
begin
case (state)
1:
begin
addr_reg <= ptr_out;
we <= 1'b0;
state <= 4'd2;
end
2:
begin
out_data <= sr_data;
addr_reg <= ptr_in;
we <= 1'b0;
state <= 4'd3;
end
3:
begin
in_data <= sr_data;
state <= 4'd4;
end
4:
begin
out <= new_out;
addr_reg <= ptr_in;
we <= 1'b1;
if (trigger)
begin
if (last_trigger == 0)
begin
trigger_count <= 12'd0;
last_trigger <= 1'd1;
end
else if (trigger_count < tone)
begin
trigger_count <= trigger_count + 12'd1;
write_data <= new_lopass;
end
else
write_data <= new_out;
end
else
begin
last_trigger <= 1'd0;
write_data <= new_out;
end
state <= 4'd5;
end
5:
begin
we <= 1'b0;
if (ptr_in == tone)
ptr_in <= 12'h0;
else
ptr_in <= ptr_in + 12'h1;
if (ptr_out == tone)
ptr_out <= 12'h0;
else
ptr_out <= ptr_out + 12'h1;
state <= 4'd9;
end
9:
begin
if (clk_sample && last_clk)
begin
state <= 4'd1;
last_clk <= 1'h0;
end
else if (!clk_sample)
begin
last_clk <= 1'h1;
end
end
endcase
end
end
shift_reg KS1
(
.out(sr_data),
.addr(addr_reg),
.in(write_data),
.wren(we),
.clk(clk),
.aclr(aclr)
);
signed_mult GAINFACTOR
(
.out(new_out),
.a(gain),
.b((out_data + in_data))
);
endmodule | module karplus_strong
(
input clk,
input aclr,
input clk_sample,
input trigger,
input [11:0] tone,
input [2:0] cutoff,
output [15:0] sample
); |
reg last_trigger;
reg [11:0] trigger_count;
reg [3:0] state;
reg last_clk;
wire [17:0] gain;
assign gain = 18'h0_7EB8;
reg [11:0] ptr_in, ptr_out;
reg we;
wire [17:0] sr_data;
reg [17:0] write_data;
reg [11:0] addr_reg;
reg [17:0] out, in_data, out_data;
wire [17:0] new_out;
assign sample = out[17:2];
wire x_low_bit;
reg [30:0] x_rand;
wire [17:0] new_lopass;
reg [17:0] lopass;
assign x_low_bit = x_rand[27] ^ x_rand[30];
assign new_lopass = lopass + ((( (x_low_bit)?18'h1_0000:18'h3_0000) - lopass)>>>cutoff);
always @(posedge clk_sample or posedge aclr)
begin
if (aclr)
begin
x_rand <= 31'h55555555;
lopass <= 18'h0;
end
else
begin
x_rand <= { x_rand[29:0], x_low_bit };
lopass <= new_lopass;
end
end
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
ptr_out <= 12'h1;
ptr_in <= 12'h0;
we <= 1'b0;
state <= 4'd9;
last_clk <= 1'b1;
trigger_count <= 12'd0;
last_trigger <= 1'b0;
end
else
begin
case (state)
1:
begin
addr_reg <= ptr_out;
we <= 1'b0;
state <= 4'd2;
end
2:
begin
out_data <= sr_data;
addr_reg <= ptr_in;
we <= 1'b0;
state <= 4'd3;
end
3:
begin
in_data <= sr_data;
state <= 4'd4;
end
4:
begin
out <= new_out;
addr_reg <= ptr_in;
we <= 1'b1;
if (trigger)
begin
if (last_trigger == 0)
begin
trigger_count <= 12'd0;
last_trigger <= 1'd1;
end
else if (trigger_count < tone)
begin
trigger_count <= trigger_count + 12'd1;
write_data <= new_lopass;
end
else
write_data <= new_out;
end
else
begin
last_trigger <= 1'd0;
write_data <= new_out;
end
state <= 4'd5;
end
5:
begin
we <= 1'b0;
if (ptr_in == tone)
ptr_in <= 12'h0;
else
ptr_in <= ptr_in + 12'h1;
if (ptr_out == tone)
ptr_out <= 12'h0;
else
ptr_out <= ptr_out + 12'h1;
state <= 4'd9;
end
9:
begin
if (clk_sample && last_clk)
begin
state <= 4'd1;
last_clk <= 1'h0;
end
else if (!clk_sample)
begin
last_clk <= 1'h1;
end
end
endcase
end
end
shift_reg KS1
(
.out(sr_data),
.addr(addr_reg),
.in(write_data),
.wren(we),
.clk(clk),
.aclr(aclr)
);
signed_mult GAINFACTOR
(
.out(new_out),
.a(gain),
.b((out_data + in_data))
);
endmodule | 0 |
141,005 | data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v | 93,128,889 | karplus_strong_tb.v | v | 68 | 49 | [] | [] | [] | null | line:63: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_PERIOD_NS/2) clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 6 * 12\'b111010101010)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 6 * 12\'b111010101010)\n ^\n%Warning-WIDTH: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance karplus_strong_tb\n reg [3:0] clk_sample_count = 3\'d0;\n ^~~~\n%Error: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:17: Cannot find file containing module: \'karplus_strong\'\n karplus_strong MUT\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/karplus_strong\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/karplus_strong.v\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/karplus_strong.sv\n karplus_strong\n karplus_strong.v\n karplus_strong.sv\n obj_dir/karplus_strong\n obj_dir/karplus_strong.v\n obj_dir/karplus_strong.sv\n%Warning-WIDTH: data/full_repos/permissive/93128889/synthX/karplus_strong_tb.v:38: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance karplus_strong_tb\n if (clk_sample_count == 3\'d3)\n ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,617 | module | module karplus_strong_tb();
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
reg aclr = 0;
reg clk_sample = 0;
reg [3:0] clk_sample_count = 3'd0;
reg trigger = 0;
reg [2:0] cutoff = 3'd0;
wire [15:0] sample;
reg [11:0] tone = 0;
karplus_strong MUT
(
.clk(clk),
.aclr(aclr),
.clk_sample(clk_sample),
.trigger(trigger),
.tone(tone),
.cutoff(cutoff),
.sample(sample)
);
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
clk_sample <= 0;
clk_sample_count <= 0;
end
else
begin
if (clk_sample_count == 3'd3)
begin
clk_sample_count <= 0;
clk_sample = !clk_sample;
end
else
begin
clk_sample_count <= clk_sample_count + 1;
clk_sample <= clk_sample;
end
end
end
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1'b1;
#CLOCK_PERIOD_NS
aclr <= 1'b0;
tone <= 12'b010101010101;
trigger <= 1;
cutoff <= 3'b011;
#(CLOCK_PERIOD_NS * 6 * 12'b111010101010)
trigger <= 0;
#(CLOCK_PERIOD_NS * 6 * 12'b111010101010)
$finish;
end
endmodule | module karplus_strong_tb(); |
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
reg aclr = 0;
reg clk_sample = 0;
reg [3:0] clk_sample_count = 3'd0;
reg trigger = 0;
reg [2:0] cutoff = 3'd0;
wire [15:0] sample;
reg [11:0] tone = 0;
karplus_strong MUT
(
.clk(clk),
.aclr(aclr),
.clk_sample(clk_sample),
.trigger(trigger),
.tone(tone),
.cutoff(cutoff),
.sample(sample)
);
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
clk_sample <= 0;
clk_sample_count <= 0;
end
else
begin
if (clk_sample_count == 3'd3)
begin
clk_sample_count <= 0;
clk_sample = !clk_sample;
end
else
begin
clk_sample_count <= clk_sample_count + 1;
clk_sample <= clk_sample;
end
end
end
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1'b1;
#CLOCK_PERIOD_NS
aclr <= 1'b0;
tone <= 12'b010101010101;
trigger <= 1;
cutoff <= 3'b011;
#(CLOCK_PERIOD_NS * 6 * 12'b111010101010)
trigger <= 0;
#(CLOCK_PERIOD_NS * 6 * 12'b111010101010)
$finish;
end
endmodule | 0 |
141,006 | data/full_repos/permissive/93128889/synthX/shift_reg.v | 93,128,889 | shift_reg.v | v | 35 | 64 | [] | [] | [] | null | line:19: before: "(" | data/verilator_xmls/3e38928c-3031-4f41-8c24-cbad6f632dde.xml | null | 310,621 | module | module shift_reg
(
input [17:0] in,
output [17:0] out,
input [11:0] addr,
input wren,
input clk,
input aclr
);
reg [11:0] read_addr = 12'd0;
reg [17:0] memory [4095:0];
always @(posedge clk or posedge(aclr))
begin
if (aclr)
begin
read_addr <= 0;
end
else
if (wren)
memory[addr] <= in;
else
read_addr <= addr;
end
assign out = memory[read_addr];
endmodule | module shift_reg
(
input [17:0] in,
output [17:0] out,
input [11:0] addr,
input wren,
input clk,
input aclr
); |
reg [11:0] read_addr = 12'd0;
reg [17:0] memory [4095:0];
always @(posedge clk or posedge(aclr))
begin
if (aclr)
begin
read_addr <= 0;
end
else
if (wren)
memory[addr] <= in;
else
read_addr <= addr;
end
assign out = memory[read_addr];
endmodule | 0 |
141,007 | data/full_repos/permissive/93128889/synthX/signed_mult.v | 93,128,889 | signed_mult.v | v | 19 | 52 | [] | [] | [] | [(5, 18)] | null | data/verilator_xmls/7624042b-c0e6-4e5d-8a73-e4fc31af308b.xml | null | 310,622 | module | module signed_mult
(
output wire signed [17:0] out,
input signed [17:0] a,
input signed [17:0] b
);
wire signed [35:0] mult_out;
assign mult_out = a * b;
assign out = { mult_out[35], mult_out[32:16] };
endmodule | module signed_mult
(
output wire signed [17:0] out,
input signed [17:0] a,
input signed [17:0] b
); |
wire signed [35:0] mult_out;
assign mult_out = a * b;
assign out = { mult_out[35], mult_out[32:16] };
endmodule | 0 |
141,008 | data/full_repos/permissive/93128889/synthX/top.v | 93,128,889 | top.v | v | 86 | 59 | [] | [] | [] | [(1, 85)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93128889/synthX/top.v:19: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance top\n reg [3:0] clk_sample_count = 3\'d0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/93128889/synthX/top.v:25: Cannot find file containing module: \'karplus_strong\'\n karplus_strong KS1\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/karplus_strong\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/karplus_strong.v\n data/full_repos/permissive/93128889/synthX,data/full_repos/permissive/93128889/karplus_strong.sv\n karplus_strong\n karplus_strong.v\n karplus_strong.sv\n obj_dir/karplus_strong\n obj_dir/karplus_strong.v\n obj_dir/karplus_strong.sv\n%Error: data/full_repos/permissive/93128889/synthX/top.v:43: Cannot find file containing module: \'audio_out\'\n audio_out I2S\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93128889/synthX/top.v:67: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance top\n if (clk_sample_count == 3\'d3)\n ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 310,623 | module | module top
(
input clk,
input aclr_,
input trigger_,
output i2s_sck,
output i2s_bck,
output i2s_lrck,
output i2s_dout
);
wire aclr;
assign aclr = !aclr_;
wire trigger;
assign trigger = !trigger_;
reg clk_sample = 0;
reg [3:0] clk_sample_count = 3'd0;
reg [2:0] cutoff = 3'b011;
wire [15:0] sample;
reg [11:0] tone = 12'd699;
karplus_strong KS1
(
.clk(clk),
.aclr(aclr),
.clk_sample(clk_sample),
.trigger(trigger),
.tone(tone),
.cutoff(cutoff),
.sample(sample)
);
wire wrreq;
assign wrreq = clk_sample;
wire [63:0] lrsample;
assign lrsample[15:0] = sample;
assign lrsample[47:32] = sample;
wire wrfull;
audio_out I2S
(
.clk(clk),
.aclr(aclr),
.sample(lrsample),
.wrreq(wrreq),
.wrfull(wrfull),
.lrck(i2s_lrck),
.bck(i2s_bck),
.dout(i2s_dout),
.sck(i2s_sck)
);
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
clk_sample <= 0;
clk_sample_count <= 0;
end
else
begin
if (!wrfull)
if (clk_sample_count == 3'd3)
begin
clk_sample_count <= 0;
clk_sample = 1'b1;
end
else
begin
clk_sample_count <= clk_sample_count + 1;
clk_sample <= 1'b0;
end
else
begin
clk_sample_count <= clk_sample_count;
clk_sample <= 1'b0;
end
end
end
endmodule | module top
(
input clk,
input aclr_,
input trigger_,
output i2s_sck,
output i2s_bck,
output i2s_lrck,
output i2s_dout
); |
wire aclr;
assign aclr = !aclr_;
wire trigger;
assign trigger = !trigger_;
reg clk_sample = 0;
reg [3:0] clk_sample_count = 3'd0;
reg [2:0] cutoff = 3'b011;
wire [15:0] sample;
reg [11:0] tone = 12'd699;
karplus_strong KS1
(
.clk(clk),
.aclr(aclr),
.clk_sample(clk_sample),
.trigger(trigger),
.tone(tone),
.cutoff(cutoff),
.sample(sample)
);
wire wrreq;
assign wrreq = clk_sample;
wire [63:0] lrsample;
assign lrsample[15:0] = sample;
assign lrsample[47:32] = sample;
wire wrfull;
audio_out I2S
(
.clk(clk),
.aclr(aclr),
.sample(lrsample),
.wrreq(wrreq),
.wrfull(wrfull),
.lrck(i2s_lrck),
.bck(i2s_bck),
.dout(i2s_dout),
.sck(i2s_sck)
);
always @(posedge clk or posedge aclr)
begin
if (aclr)
begin
clk_sample <= 0;
clk_sample_count <= 0;
end
else
begin
if (!wrfull)
if (clk_sample_count == 3'd3)
begin
clk_sample_count <= 0;
clk_sample = 1'b1;
end
else
begin
clk_sample_count <= clk_sample_count + 1;
clk_sample <= 1'b0;
end
else
begin
clk_sample_count <= clk_sample_count;
clk_sample <= 1'b0;
end
end
end
endmodule | 0 |
141,010 | data/full_repos/permissive/93316915/src/ARMAria.v | 93,316,915 | ARMAria.v | v | 153 | 71 | [] | [] | [] | [(1, 152)] | null | null | 1: b"%Error: data/full_repos/permissive/93316915/src/ARMAria.v:41: Cannot find file containing module: 'DeBounce'\n DeBounce dbc(fast_clock, confirmation_button, confirmation);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93316915/src,data/full_repos/permissive/93316915/DeBounce\n data/full_repos/permissive/93316915/src,data/full_repos/permissive/93316915/DeBounce.v\n data/full_repos/permissive/93316915/src,data/full_repos/permissive/93316915/DeBounce.sv\n DeBounce\n DeBounce.v\n DeBounce.sv\n obj_dir/DeBounce\n obj_dir/DeBounce.v\n obj_dir/DeBounce.sv\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:42: Cannot find file containing module: 'DeBounce'\n DeBounce dbr(fast_clock, reset_button, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:43: Cannot find file containing module: 'DeBounce'\n DeBounce dbco(fast_clock, continue_button, continue_debounced);\n ^~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:44: Cannot find file containing module: 'DeBounce'\n DeBounce dbur(fast_clock, request_os_button, user_request);\n ^~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:48: Cannot find file containing module: 'FrequencyDivider'\n FrequencyDivider fd(fast_clock, slow_clock);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:52: Cannot find file containing module: 'Control'\n Control control_unit(\n ^~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:69: Cannot find file containing module: 'MemoryUnit'\n MemoryUnit mu(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:77: Cannot find file containing module: 'IOmodule'\n IOmodule enterescape(\n ^~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:86: Cannot find file containing module: 'MemoryAddressHandler'\n MemoryAddressHandler mah(\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:95: Cannot find file containing module: 'MemoryDataHandler'\n MemoryDataHandler mdh(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:101: Cannot find file containing module: 'SignExtend'\n SignExtend load_sign_extend_unit(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:107: Cannot find file containing module: 'RegBank'\n RegBank ARMARIAbank(\n ^~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:118: Cannot find file containing module: 'MUXBS'\n MUXBS muxbusb(\n ^~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:124: Cannot find file containing module: 'SignExtend'\n SignExtend channel_B_sign_extend_unit(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:130: Cannot find file containing module: 'BarrelShifter'\n BarrelShifter NiagaraFalls(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:137: Cannot find file containing module: 'ALU'\n ALU arithmeticlogicunit(\n ^~~\n%Error: data/full_repos/permissive/93316915/src/ARMAria.v:146: Cannot find file containing module: 'Watchdog'\n Watchdog pitbull(\n ^~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 310,625 | module | module ARMAria
#(
parameter WORD_SIZE = 32,
parameter INSTRUCTION_WIDTH = 16,
parameter FLAG_COUNT = 5,
parameter IO_WIDTH = 16,
parameter SEGMENTS_COUNT = 7*8,
parameter OFFSET_WIDTH = 12
)(
input fast_clock, confirmation_button, reset_button,
input continue_button, request_os_button,
input [(IO_WIDTH - 1) : 0] sw,
output [(IO_WIDTH - 1) : 0] rled,
output [(FLAG_COUNT - 1) : 0] gled,
output [(SEGMENTS_COUNT - 1) : 0] sseg,
output slow_clock, reset,
output is_input, is_output, enable
);
wire alu_negative, alu_zero, alu_carry, alu_overflow;
wire bs_negative, bs_zero, bs_carry, confirmation;
wire continue_debounced, n_flag, z_flag, should_branch;
wire c_flag, v_flag, is_os, is_memory_write;
wire should_fill_b_offset, is_bios, user_request;
wire [1 : 0] interruption;
wire [2 : 0] controlMAH, b_sign_extend;
wire [2 : 0] load_sign_extend, controlRB;
wire [3 : 0] RegD, RegA, RegB, controlALU, controlBS;
wire [(OFFSET_WIDTH - 1) : 0] OffImmed;
wire [(INSTRUCTION_WIDTH -1) : 0] Instruction;
wire [(WORD_SIZE - 1) : 0] instruction_address, next_PC;
wire [(WORD_SIZE - 1) : 0] data_address, ALU_result, final_result;
wire [(WORD_SIZE - 1) : 0] PC, SP, memory_read_data, Bse;
wire [(WORD_SIZE - 1) : 0] PreMemIn, MemIn, Bbus, IData, PreB;
wire [(WORD_SIZE - 1) : 0] next_SP, Abus, MemOut, Bsh;
DeBounce dbc(fast_clock, confirmation_button, confirmation);
DeBounce dbr(fast_clock, reset_button, reset);
DeBounce dbco(fast_clock, continue_button, continue_debounced);
DeBounce dbur(fast_clock, request_os_button, user_request);
FrequencyDivider fd(fast_clock, slow_clock);
Control control_unit(
Instruction,
alu_negative, alu_carry, alu_overflow,
alu_zero, continue_debounced, bs_negative,
bs_zero, bs_carry, reset, slow_clock,
confirmation,
interruption,
OffImmed,
RegD, RegA, RegB,
controlBS, controlALU,
controlRB, controlMAH,
b_sign_extend, load_sign_extend,
is_memory_write, should_fill_b_offset,
n_flag, z_flag, c_flag, v_flag, is_os, enable,
should_branch, is_input, is_output, is_bios
);
MemoryUnit mu(
is_memory_write, slow_clock, fast_clock,
data_address, instruction_address, MemOut,
is_bios,
Instruction,
memory_read_data
);
IOmodule enterescape(
slow_clock, fast_clock,
is_output & (~is_input),
reset, enable,
MemOut, IData, sw,
n_flag, z_flag, c_flag, v_flag, is_os,
rled, gled, sseg, instruction_address
);
MemoryAddressHandler mah(
is_os, should_branch, reset,
controlMAH,
ALU_result, PC, SP,
next_SP, data_address,
final_result, next_PC,
instruction_address
);
MemoryDataHandler mdh(
(is_input && !is_output),
IData, memory_read_data,
PreMemIn
);
SignExtend load_sign_extend_unit(
PreMemIn,
load_sign_extend,
MemIn
);
RegBank ARMARIAbank(
enable, reset, slow_clock, fast_clock,
controlRB,
RegA, RegB, RegD,
final_result, MemIn,
next_SP, next_PC,
Abus, Bbus,
PC, SP, MemOut,
{n_flag, z_flag, c_flag, v_flag}
);
MUXBS muxbusb(
should_fill_b_offset,
Bbus, OffImmed,
PreB
);
SignExtend channel_B_sign_extend_unit(
PreB,
b_sign_extend,
Bse
);
BarrelShifter NiagaraFalls(
Abus, Bse,
controlBS,
Bsh,
bs_negative, bs_zero, bs_carry
);
ALU arithmeticlogicunit(
Abus, Bsh,
ALU_result,
controlALU,
c_flag,
alu_negative, alu_zero, alu_carry, alu_overflow
);
Watchdog pitbull(
slow_clock, fast_clock,
user_request,
interruption
);
endmodule | module ARMAria
#(
parameter WORD_SIZE = 32,
parameter INSTRUCTION_WIDTH = 16,
parameter FLAG_COUNT = 5,
parameter IO_WIDTH = 16,
parameter SEGMENTS_COUNT = 7*8,
parameter OFFSET_WIDTH = 12
)(
input fast_clock, confirmation_button, reset_button,
input continue_button, request_os_button,
input [(IO_WIDTH - 1) : 0] sw,
output [(IO_WIDTH - 1) : 0] rled,
output [(FLAG_COUNT - 1) : 0] gled,
output [(SEGMENTS_COUNT - 1) : 0] sseg,
output slow_clock, reset,
output is_input, is_output, enable
); |
wire alu_negative, alu_zero, alu_carry, alu_overflow;
wire bs_negative, bs_zero, bs_carry, confirmation;
wire continue_debounced, n_flag, z_flag, should_branch;
wire c_flag, v_flag, is_os, is_memory_write;
wire should_fill_b_offset, is_bios, user_request;
wire [1 : 0] interruption;
wire [2 : 0] controlMAH, b_sign_extend;
wire [2 : 0] load_sign_extend, controlRB;
wire [3 : 0] RegD, RegA, RegB, controlALU, controlBS;
wire [(OFFSET_WIDTH - 1) : 0] OffImmed;
wire [(INSTRUCTION_WIDTH -1) : 0] Instruction;
wire [(WORD_SIZE - 1) : 0] instruction_address, next_PC;
wire [(WORD_SIZE - 1) : 0] data_address, ALU_result, final_result;
wire [(WORD_SIZE - 1) : 0] PC, SP, memory_read_data, Bse;
wire [(WORD_SIZE - 1) : 0] PreMemIn, MemIn, Bbus, IData, PreB;
wire [(WORD_SIZE - 1) : 0] next_SP, Abus, MemOut, Bsh;
DeBounce dbc(fast_clock, confirmation_button, confirmation);
DeBounce dbr(fast_clock, reset_button, reset);
DeBounce dbco(fast_clock, continue_button, continue_debounced);
DeBounce dbur(fast_clock, request_os_button, user_request);
FrequencyDivider fd(fast_clock, slow_clock);
Control control_unit(
Instruction,
alu_negative, alu_carry, alu_overflow,
alu_zero, continue_debounced, bs_negative,
bs_zero, bs_carry, reset, slow_clock,
confirmation,
interruption,
OffImmed,
RegD, RegA, RegB,
controlBS, controlALU,
controlRB, controlMAH,
b_sign_extend, load_sign_extend,
is_memory_write, should_fill_b_offset,
n_flag, z_flag, c_flag, v_flag, is_os, enable,
should_branch, is_input, is_output, is_bios
);
MemoryUnit mu(
is_memory_write, slow_clock, fast_clock,
data_address, instruction_address, MemOut,
is_bios,
Instruction,
memory_read_data
);
IOmodule enterescape(
slow_clock, fast_clock,
is_output & (~is_input),
reset, enable,
MemOut, IData, sw,
n_flag, z_flag, c_flag, v_flag, is_os,
rled, gled, sseg, instruction_address
);
MemoryAddressHandler mah(
is_os, should_branch, reset,
controlMAH,
ALU_result, PC, SP,
next_SP, data_address,
final_result, next_PC,
instruction_address
);
MemoryDataHandler mdh(
(is_input && !is_output),
IData, memory_read_data,
PreMemIn
);
SignExtend load_sign_extend_unit(
PreMemIn,
load_sign_extend,
MemIn
);
RegBank ARMARIAbank(
enable, reset, slow_clock, fast_clock,
controlRB,
RegA, RegB, RegD,
final_result, MemIn,
next_SP, next_PC,
Abus, Bbus,
PC, SP, MemOut,
{n_flag, z_flag, c_flag, v_flag}
);
MUXBS muxbusb(
should_fill_b_offset,
Bbus, OffImmed,
PreB
);
SignExtend channel_B_sign_extend_unit(
PreB,
b_sign_extend,
Bse
);
BarrelShifter NiagaraFalls(
Abus, Bse,
controlBS,
Bsh,
bs_negative, bs_zero, bs_carry
);
ALU arithmeticlogicunit(
Abus, Bsh,
ALU_result,
controlALU,
c_flag,
alu_negative, alu_zero, alu_carry, alu_overflow
);
Watchdog pitbull(
slow_clock, fast_clock,
user_request,
interruption
);
endmodule | 1 |
141,012 | data/full_repos/permissive/93316915/src/FrequencyDivider.v | 93,316,915 | FrequencyDivider.v | v | 19 | 55 | [] | [] | [] | [(1, 19)] | null | data/verilator_xmls/f626bf65-966e-4ea5-a9da-5c6576bdcdb5.xml | null | 310,627 | module | module FrequencyDivider
#(
parameter COUNTER_WIDTH = 15,
parameter MAX_COUNTER_VALUE = 2**COUNTER_WIDTH - 1
)(
input clock_50mhz,
output reg divided_clock
);
reg [COUNTER_WIDTH-1:0] counter;
always @ (posedge clock_50mhz) begin
counter <= counter + 1;
if (counter == MAX_COUNTER_VALUE) begin
counter <= 0;
divided_clock <= !divided_clock;
end
end
endmodule | module FrequencyDivider
#(
parameter COUNTER_WIDTH = 15,
parameter MAX_COUNTER_VALUE = 2**COUNTER_WIDTH - 1
)(
input clock_50mhz,
output reg divided_clock
); |
reg [COUNTER_WIDTH-1:0] counter;
always @ (posedge clock_50mhz) begin
counter <= counter + 1;
if (counter == MAX_COUNTER_VALUE) begin
counter <= 0;
divided_clock <= !divided_clock;
end
end
endmodule | 1 |
141,016 | data/full_repos/permissive/93316915/src/RegBank.v | 93,316,915 | RegBank.v | v | 92 | 81 | [] | [] | [] | [(1, 91)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93316915/src/RegBank.v:75: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'special_register\' generates 4 bits.\n : ... In instance RegBank\n Bank[register_Dest] <= special_register;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 310,631 | module | module RegBank
#(
parameter WORD_SIZE = 32,
parameter MAX_NUMBER = 32'hffffffff,
parameter PC_REGISTER = 15,
parameter SP_REGISTER = 14,
parameter SPECREG_LENGTH = 4,
parameter KERNEL_STACK = 7167,
parameter USER_STACK = 8191,
parameter OS_START = 3072,
parameter SP_KEEPER_REGISTER = 6,
parameter SYSTEM_CALL_REGISTER = 7,
parameter PC_KEEPER_REGISTER = 13
)(
input enable, reset, slow_clock, fast_clock,
input [2:0] control,
input [3:0] register_source_A, register_source_B, register_Dest,
input [(WORD_SIZE - 1) : 0] ALU_result, data_from_memory,
input [(WORD_SIZE - 1) : 0] new_SP, new_PC,
output reg [(WORD_SIZE - 1) : 0] read_data_A, read_data_B,
output reg [(WORD_SIZE - 1) : 0] current_PC, current_SP, memory_output,
input [(SPECREG_LENGTH - 1) : 0] special_register
);
reg [(WORD_SIZE - 1) : 0] Bank [15:0];
wire RD_isnt_special;
assign RD_isnt_special = register_Dest != PC_REGISTER && register_Dest!= 14;
always @ (posedge fast_clock) begin
read_data_A <= Bank[register_source_A];
read_data_B <= Bank[register_source_B];
current_PC <= Bank[PC_REGISTER];
current_SP <= Bank[SP_REGISTER];
memory_output <= Bank[register_Dest];
end
always @ (posedge slow_clock) begin
if (reset) begin
Bank[SP_REGISTER] <= USER_STACK;
Bank[PC_REGISTER] <= 0;
end else begin
if (enable) begin
case (control)
1:begin
if(RD_isnt_special) begin
Bank[register_Dest] <= ALU_result;
end
Bank[PC_REGISTER] <= new_PC;
Bank[SP_REGISTER] <= new_SP;
end
2:begin
if(RD_isnt_special)begin
Bank[register_Dest] <= data_from_memory;
end
Bank[SP_REGISTER] <= new_SP;
Bank[PC_REGISTER] <= new_PC;
end
3:begin
Bank[SP_KEEPER_REGISTER] <= Bank[SP_REGISTER];
Bank[PC_KEEPER_REGISTER] <= Bank[PC_REGISTER];
Bank[PC_REGISTER] <= OS_START;
Bank[SP_REGISTER] <= KERNEL_STACK;
Bank[SYSTEM_CALL_REGISTER] <= ALU_result;
end
4:begin
Bank[SP_REGISTER] <= Bank[SP_KEEPER_REGISTER];
Bank[PC_REGISTER] <= Bank[PC_KEEPER_REGISTER];
end
5:begin
if(RD_isnt_special)
Bank[register_Dest] <= special_register;
Bank[PC_REGISTER] <= new_PC;
Bank[SP_REGISTER] <= new_SP;
end
default:begin
Bank[SP_REGISTER] <= new_SP;
Bank[PC_REGISTER] <= new_PC;
end
endcase
end
end
end
endmodule | module RegBank
#(
parameter WORD_SIZE = 32,
parameter MAX_NUMBER = 32'hffffffff,
parameter PC_REGISTER = 15,
parameter SP_REGISTER = 14,
parameter SPECREG_LENGTH = 4,
parameter KERNEL_STACK = 7167,
parameter USER_STACK = 8191,
parameter OS_START = 3072,
parameter SP_KEEPER_REGISTER = 6,
parameter SYSTEM_CALL_REGISTER = 7,
parameter PC_KEEPER_REGISTER = 13
)(
input enable, reset, slow_clock, fast_clock,
input [2:0] control,
input [3:0] register_source_A, register_source_B, register_Dest,
input [(WORD_SIZE - 1) : 0] ALU_result, data_from_memory,
input [(WORD_SIZE - 1) : 0] new_SP, new_PC,
output reg [(WORD_SIZE - 1) : 0] read_data_A, read_data_B,
output reg [(WORD_SIZE - 1) : 0] current_PC, current_SP, memory_output,
input [(SPECREG_LENGTH - 1) : 0] special_register
); |
reg [(WORD_SIZE - 1) : 0] Bank [15:0];
wire RD_isnt_special;
assign RD_isnt_special = register_Dest != PC_REGISTER && register_Dest!= 14;
always @ (posedge fast_clock) begin
read_data_A <= Bank[register_source_A];
read_data_B <= Bank[register_source_B];
current_PC <= Bank[PC_REGISTER];
current_SP <= Bank[SP_REGISTER];
memory_output <= Bank[register_Dest];
end
always @ (posedge slow_clock) begin
if (reset) begin
Bank[SP_REGISTER] <= USER_STACK;
Bank[PC_REGISTER] <= 0;
end else begin
if (enable) begin
case (control)
1:begin
if(RD_isnt_special) begin
Bank[register_Dest] <= ALU_result;
end
Bank[PC_REGISTER] <= new_PC;
Bank[SP_REGISTER] <= new_SP;
end
2:begin
if(RD_isnt_special)begin
Bank[register_Dest] <= data_from_memory;
end
Bank[SP_REGISTER] <= new_SP;
Bank[PC_REGISTER] <= new_PC;
end
3:begin
Bank[SP_KEEPER_REGISTER] <= Bank[SP_REGISTER];
Bank[PC_KEEPER_REGISTER] <= Bank[PC_REGISTER];
Bank[PC_REGISTER] <= OS_START;
Bank[SP_REGISTER] <= KERNEL_STACK;
Bank[SYSTEM_CALL_REGISTER] <= ALU_result;
end
4:begin
Bank[SP_REGISTER] <= Bank[SP_KEEPER_REGISTER];
Bank[PC_REGISTER] <= Bank[PC_KEEPER_REGISTER];
end
5:begin
if(RD_isnt_special)
Bank[register_Dest] <= special_register;
Bank[PC_REGISTER] <= new_PC;
Bank[SP_REGISTER] <= new_SP;
end
default:begin
Bank[SP_REGISTER] <= new_SP;
Bank[PC_REGISTER] <= new_PC;
end
endcase
end
end
end
endmodule | 1 |
141,017 | data/full_repos/permissive/93316915/src/SignExtend.v | 93,316,915 | SignExtend.v | v | 32 | 75 | [] | [] | [] | [(1, 31)] | null | data/verilator_xmls/ae5c0749-c2e5-4a0f-b95a-8dc4f4b0a8ff.xml | null | 310,632 | module | module SignExtend
#(
parameter DATA_WIDTH = 32
)(
input [DATA_WIDTH -1:0] Input,
input [2:0] control,
output reg [DATA_WIDTH -1:0] outputSE
);
always @ ( * ) begin
case (control)
1:begin
outputSE = (Input[15])? {16'hffff,Input[15:0]} : {16'h0, Input[15:0]};
end
2:begin
outputSE = (Input[7])? {24'hffffff, Input[7:0]} : {24'h0, Input[7:0]};
end
3:begin
outputSE = {16'h0, Input[15:0]};
end
4:begin
outputSE = {24'h0, Input[7:0]};
end
default:begin
outputSE = Input;
end
endcase
end
endmodule | module SignExtend
#(
parameter DATA_WIDTH = 32
)(
input [DATA_WIDTH -1:0] Input,
input [2:0] control,
output reg [DATA_WIDTH -1:0] outputSE
); |
always @ ( * ) begin
case (control)
1:begin
outputSE = (Input[15])? {16'hffff,Input[15:0]} : {16'h0, Input[15:0]};
end
2:begin
outputSE = (Input[7])? {24'hffffff, Input[7:0]} : {24'h0, Input[7:0]};
end
3:begin
outputSE = {16'h0, Input[15:0]};
end
4:begin
outputSE = {24'h0, Input[7:0]};
end
default:begin
outputSE = Input;
end
endcase
end
endmodule | 1 |
141,020 | data/full_repos/permissive/93316915/src/ControlUnit/controlcore.v | 93,316,915 | controlcore.v | v | 412 | 90 | [] | [] | [] | [(1, 411)] | null | data/verilator_xmls/f4b24dc3-6b29-4d4c-8d8f-a65b55c255f4.xml | null | 310,635 | module | module ControlCore(
input confirmation, continue_button, mode_flag,
input [6 : 0] ID,
output reg enable, allow_write_on_memory, should_fill_channel_b_with_offset,
output reg is_input, is_output,
output reg [2 : 0] control_channel_B_sign_extend_unit, control_load_sign_extend_unit,
output reg [2 : 0] controlRB, controlMAH,
output reg [3 : 0] controlALU, controlBS, specreg_update_mode
);
always @ ( * ) begin
controlALU = 12;
controlBS = 0;
controlRB = 1;
control_channel_B_sign_extend_unit = 0;
control_load_sign_extend_unit = 0;
controlMAH = 0;
allow_write_on_memory = 0;
should_fill_channel_b_with_offset = 0;
enable = 1;
specreg_update_mode = 0;
is_input = 0;
is_output = 0;
case (ID)
1:begin
controlBS=3;
should_fill_channel_b_with_offset=1;
specreg_update_mode = 1;
end
2:begin
controlBS = 4;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 1;
end
3:begin
controlBS = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 1;
end
4:begin
controlALU = 2;
specreg_update_mode = 2;
end
5:begin
controlALU = 5;
specreg_update_mode = 2;
end
6:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
7:begin
controlALU = 5;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
8:begin
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 3;
end
9:begin
controlALU = 5;
controlRB = 0;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
10:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
11:begin
controlALU = 5;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
12:begin
controlALU = 3;
specreg_update_mode = 3;
end
13:begin
controlALU = 13;
specreg_update_mode = 3;
end
14:begin
controlBS = 3;
specreg_update_mode = 1;
end
15:begin
controlBS = 4;
specreg_update_mode = 1;
end
16:begin
controlBS = 2;
specreg_update_mode = 1;
end
17:begin
controlALU = 1;
specreg_update_mode = 2;
end
18:begin
controlALU = 8;
specreg_update_mode = 2;
end
19:begin
controlBS = 5;
specreg_update_mode = 1;
end
20:begin
controlALU = 14;
specreg_update_mode = 3;
end
21:begin
controlALU = 6;
specreg_update_mode = 2;
end
22:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
23:begin
controlALU = 2;
controlRB = 0;
specreg_update_mode = 2;
end
24:begin
controlALU = 7;
specreg_update_mode = 3;
end
25:begin
controlALU = 9;
specreg_update_mode = 3;
end
26:begin
controlALU = 4;
specreg_update_mode = 3;
end
27:begin
specreg_update_mode = 3;
end
28:begin
controlALU = 2;
end
29:begin
controlALU = 2;
end
30:begin
controlALU = 2;
controlRB = 0;
end
31:begin
controlALU = 5;
specreg_update_mode = 2;
end
32:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
33:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
34:begin
controlALU = 10;
specreg_update_mode = 4;
end
35:begin
end
36:begin
end
37:begin
end
38:begin
controlALU = 2;
controlBS = 0;
control_channel_B_sign_extend_unit = 0;
controlRB = 0;
should_fill_channel_b_with_offset = 0;
controlMAH = 4;
end
39:begin
controlALU = 2;
controlBS = 1;
should_fill_channel_b_with_offset = 1;
controlRB = 2;
end
40:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
41:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
42:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
43:begin
controlALU = 2;
control_load_sign_extend_unit = 2;
controlRB = 2;
end
44:begin
controlALU = 2;
controlRB = 2;
end
45:begin
controlALU = 2;
control_load_sign_extend_unit = 3;
controlRB = 2;
end
46:begin
controlALU = 2;
control_load_sign_extend_unit = 4;
controlRB = 2;
end
47:begin
controlALU = 2;
control_load_sign_extend_unit = 1;
controlRB = 2;
end
48:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
49:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 2;
end
50:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
51:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
control_load_sign_extend_unit = 4;
controlRB = 2;
end
52:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
53:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 2;
control_load_sign_extend_unit = 3;
end
54:begin
should_fill_channel_b_with_offset = 1;
control_channel_B_sign_extend_unit = 2;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
55:begin
should_fill_channel_b_with_offset =1;
control_channel_B_sign_extend_unit = 2;
controlALU = 2;
controlRB = 2;
end
56:begin
should_fill_channel_b_with_offset = 1;
control_channel_B_sign_extend_unit = 0;
controlBS = 0;
controlALU = 2;
controlRB = 1;
end
57:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
end
58:begin
controlRB = 5;
end
59:begin
control_channel_B_sign_extend_unit = 1;
end
60:begin
control_channel_B_sign_extend_unit = 2;
end
61:begin
control_channel_B_sign_extend_unit = 3;
end
62:begin
control_channel_B_sign_extend_unit = 4;
end
63:begin
controlBS = 6;
end
64:begin
controlBS = 7;
end
65:begin
controlALU = 11;
specreg_update_mode = 4;
end
66:begin
controlBS = 8;
end
67:begin
controlMAH = 1;
allow_write_on_memory = 1;
controlRB = 0;
end
68:begin
controlMAH = 2;
controlRB = 2;
control_load_sign_extend_unit = 0;
end
69:begin
controlRB = 0;
enable = confirmation;
is_output = 1;
end
70: begin
controlRB = 0;
enable = continue_button;
specreg_update_mode = 0;
is_input = 1;
is_output = 1;
end
71:begin
controlBS = 0;
controlRB = 2;
control_channel_B_sign_extend_unit = 0;
control_load_sign_extend_unit = 3;
should_fill_channel_b_with_offset = 0;
allow_write_on_memory = 0;
is_input = 1;
enable = confirmation;
end
72:begin
specreg_update_mode = 5;
should_fill_channel_b_with_offset = 1;
controlRB = mode_flag ? 4 : 3;
end
73:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlBS = 0;
control_channel_B_sign_extend_unit = 2;
controlRB = 0;
controlMAH = 4;
end
74:begin
controlRB = 0;
end
75:begin
controlRB = 0;
enable = 0;
specreg_update_mode = 0;
end
76:begin
controlALU = 15;
specreg_update_mode = 2;
controlRB = 0;
end
77:begin
controlMAH = 3;
should_fill_channel_b_with_offset = 1;
controlALU = 5;
controlRB = 0;
end
78:begin
controlMAH = 3;
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 0;
end
79: begin
controlALU = 2;
controlRB = 1;
controlMAH = 4;
end
80:begin
controlRB = 0;
controlMAH = 4;
end
default: controlRB = 0;
endcase
end
endmodule | module ControlCore(
input confirmation, continue_button, mode_flag,
input [6 : 0] ID,
output reg enable, allow_write_on_memory, should_fill_channel_b_with_offset,
output reg is_input, is_output,
output reg [2 : 0] control_channel_B_sign_extend_unit, control_load_sign_extend_unit,
output reg [2 : 0] controlRB, controlMAH,
output reg [3 : 0] controlALU, controlBS, specreg_update_mode
); |
always @ ( * ) begin
controlALU = 12;
controlBS = 0;
controlRB = 1;
control_channel_B_sign_extend_unit = 0;
control_load_sign_extend_unit = 0;
controlMAH = 0;
allow_write_on_memory = 0;
should_fill_channel_b_with_offset = 0;
enable = 1;
specreg_update_mode = 0;
is_input = 0;
is_output = 0;
case (ID)
1:begin
controlBS=3;
should_fill_channel_b_with_offset=1;
specreg_update_mode = 1;
end
2:begin
controlBS = 4;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 1;
end
3:begin
controlBS = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 1;
end
4:begin
controlALU = 2;
specreg_update_mode = 2;
end
5:begin
controlALU = 5;
specreg_update_mode = 2;
end
6:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
7:begin
controlALU = 5;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
8:begin
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 3;
end
9:begin
controlALU = 5;
controlRB = 0;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
10:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
11:begin
controlALU = 5;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
12:begin
controlALU = 3;
specreg_update_mode = 3;
end
13:begin
controlALU = 13;
specreg_update_mode = 3;
end
14:begin
controlBS = 3;
specreg_update_mode = 1;
end
15:begin
controlBS = 4;
specreg_update_mode = 1;
end
16:begin
controlBS = 2;
specreg_update_mode = 1;
end
17:begin
controlALU = 1;
specreg_update_mode = 2;
end
18:begin
controlALU = 8;
specreg_update_mode = 2;
end
19:begin
controlBS = 5;
specreg_update_mode = 1;
end
20:begin
controlALU = 14;
specreg_update_mode = 3;
end
21:begin
controlALU = 6;
specreg_update_mode = 2;
end
22:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
23:begin
controlALU = 2;
controlRB = 0;
specreg_update_mode = 2;
end
24:begin
controlALU = 7;
specreg_update_mode = 3;
end
25:begin
controlALU = 9;
specreg_update_mode = 3;
end
26:begin
controlALU = 4;
specreg_update_mode = 3;
end
27:begin
specreg_update_mode = 3;
end
28:begin
controlALU = 2;
end
29:begin
controlALU = 2;
end
30:begin
controlALU = 2;
controlRB = 0;
end
31:begin
controlALU = 5;
specreg_update_mode = 2;
end
32:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
33:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
34:begin
controlALU = 10;
specreg_update_mode = 4;
end
35:begin
end
36:begin
end
37:begin
end
38:begin
controlALU = 2;
controlBS = 0;
control_channel_B_sign_extend_unit = 0;
controlRB = 0;
should_fill_channel_b_with_offset = 0;
controlMAH = 4;
end
39:begin
controlALU = 2;
controlBS = 1;
should_fill_channel_b_with_offset = 1;
controlRB = 2;
end
40:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
41:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
42:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
43:begin
controlALU = 2;
control_load_sign_extend_unit = 2;
controlRB = 2;
end
44:begin
controlALU = 2;
controlRB = 2;
end
45:begin
controlALU = 2;
control_load_sign_extend_unit = 3;
controlRB = 2;
end
46:begin
controlALU = 2;
control_load_sign_extend_unit = 4;
controlRB = 2;
end
47:begin
controlALU = 2;
control_load_sign_extend_unit = 1;
controlRB = 2;
end
48:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
49:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 2;
end
50:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
51:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
control_load_sign_extend_unit = 4;
controlRB = 2;
end
52:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
53:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 2;
control_load_sign_extend_unit = 3;
end
54:begin
should_fill_channel_b_with_offset = 1;
control_channel_B_sign_extend_unit = 2;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
55:begin
should_fill_channel_b_with_offset =1;
control_channel_B_sign_extend_unit = 2;
controlALU = 2;
controlRB = 2;
end
56:begin
should_fill_channel_b_with_offset = 1;
control_channel_B_sign_extend_unit = 0;
controlBS = 0;
controlALU = 2;
controlRB = 1;
end
57:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
end
58:begin
controlRB = 5;
end
59:begin
control_channel_B_sign_extend_unit = 1;
end
60:begin
control_channel_B_sign_extend_unit = 2;
end
61:begin
control_channel_B_sign_extend_unit = 3;
end
62:begin
control_channel_B_sign_extend_unit = 4;
end
63:begin
controlBS = 6;
end
64:begin
controlBS = 7;
end
65:begin
controlALU = 11;
specreg_update_mode = 4;
end
66:begin
controlBS = 8;
end
67:begin
controlMAH = 1;
allow_write_on_memory = 1;
controlRB = 0;
end
68:begin
controlMAH = 2;
controlRB = 2;
control_load_sign_extend_unit = 0;
end
69:begin
controlRB = 0;
enable = confirmation;
is_output = 1;
end
70: begin
controlRB = 0;
enable = continue_button;
specreg_update_mode = 0;
is_input = 1;
is_output = 1;
end
71:begin
controlBS = 0;
controlRB = 2;
control_channel_B_sign_extend_unit = 0;
control_load_sign_extend_unit = 3;
should_fill_channel_b_with_offset = 0;
allow_write_on_memory = 0;
is_input = 1;
enable = confirmation;
end
72:begin
specreg_update_mode = 5;
should_fill_channel_b_with_offset = 1;
controlRB = mode_flag ? 4 : 3;
end
73:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlBS = 0;
control_channel_B_sign_extend_unit = 2;
controlRB = 0;
controlMAH = 4;
end
74:begin
controlRB = 0;
end
75:begin
controlRB = 0;
enable = 0;
specreg_update_mode = 0;
end
76:begin
controlALU = 15;
specreg_update_mode = 2;
controlRB = 0;
end
77:begin
controlMAH = 3;
should_fill_channel_b_with_offset = 1;
controlALU = 5;
controlRB = 0;
end
78:begin
controlMAH = 3;
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 0;
end
79: begin
controlALU = 2;
controlRB = 1;
controlMAH = 4;
end
80:begin
controlRB = 0;
controlMAH = 4;
end
default: controlRB = 0;
endcase
end
endmodule | 1 |
141,023 | data/full_repos/permissive/93316915/src/ControlUnit/Ramifier.v | 93,316,915 | Ramifier.v | v | 65 | 73 | [] | [] | [] | [(1, 64)] | null | data/verilator_xmls/e003bb19-a885-4a62-a8cb-18064eee948f.xml | null | 310,638 | module | module Ramifier
#(
parameter BRANCH_CONDITION_WIDTH = 4
)(
input [(BRANCH_CONDITION_WIDTH - 1):0] condition,
input negative_flag, zero_flag, carry_flag, overflow_flag,
output reg take
);
always @ ( * ) begin
case (condition)
0:begin
take = zero_flag;
end
1:begin
take = !zero_flag;
end
2:begin
take = carry_flag;
end
3:begin
take = !carry_flag;
end
4:begin
take = negative_flag;
end
5:begin
take = !(negative_flag);
end
6:begin
take = overflow_flag;
end
7:begin
take = !(overflow_flag);
end
8:begin
take = (carry_flag) && (!zero_flag);
end
9:begin
take = (!carry_flag) || (zero_flag);
end
10:begin
take = (negative_flag ^~ overflow_flag) ;
end
11:begin
take = (negative_flag ^ overflow_flag);
end
12:begin
take = (!zero_flag) && (negative_flag ^~ overflow_flag);
end
13:begin
take = (zero_flag) || (negative_flag ^ overflow_flag);
end
14:begin
take = 1;
end
default: begin
take = 0;
end
endcase
end
endmodule | module Ramifier
#(
parameter BRANCH_CONDITION_WIDTH = 4
)(
input [(BRANCH_CONDITION_WIDTH - 1):0] condition,
input negative_flag, zero_flag, carry_flag, overflow_flag,
output reg take
); |
always @ ( * ) begin
case (condition)
0:begin
take = zero_flag;
end
1:begin
take = !zero_flag;
end
2:begin
take = carry_flag;
end
3:begin
take = !carry_flag;
end
4:begin
take = negative_flag;
end
5:begin
take = !(negative_flag);
end
6:begin
take = overflow_flag;
end
7:begin
take = !(overflow_flag);
end
8:begin
take = (carry_flag) && (!zero_flag);
end
9:begin
take = (!carry_flag) || (zero_flag);
end
10:begin
take = (negative_flag ^~ overflow_flag) ;
end
11:begin
take = (negative_flag ^ overflow_flag);
end
12:begin
take = (!zero_flag) && (negative_flag ^~ overflow_flag);
end
13:begin
take = (zero_flag) || (negative_flag ^ overflow_flag);
end
14:begin
take = 1;
end
default: begin
take = 0;
end
endcase
end
endmodule | 1 |
141,024 | data/full_repos/permissive/93316915/src/ControlUnit/SpecReg.v | 93,316,915 | SpecReg.v | v | 63 | 91 | [] | [] | [] | [(1, 62)] | null | data/verilator_xmls/69ab85f4-364a-4255-9689-0b6369bf90d0.xml | null | 310,639 | module | module SpecReg(
input clock, reset, enable,
input [3:0] update_mode,
output negative_flag, zero_flag, carry_flag, overflow_flag, mode_flag,
input alu_negative, alu_zero, alu_carry, alu_overflow,
input bs_negative, bs_zero, bs_carry,
output reg is_bios
);
reg [4:0] SPECREG;
assign {negative_flag, zero_flag, carry_flag, overflow_flag, mode_flag} = SPECREG;
initial begin
SPECREG <= 0;
is_bios <= 1;
end
always @ ( posedge clock ) begin
if (reset) begin
SPECREG <= 0;
is_bios <= 1;
end else begin
if(enable)
begin
case (update_mode)
1: begin
SPECREG [4:2] <= {bs_negative, bs_zero, bs_carry};
end
2: begin
SPECREG[4:1] <= {alu_negative, alu_zero, alu_carry, alu_overflow};
end
3: begin
SPECREG[4:3] <= {alu_negative, alu_zero};
end
4: begin
SPECREG[1] <= alu_overflow;
end
5: begin
SPECREG[0] <= ~SPECREG[0];
is_bios <= 0;
end
endcase
end
end
end
endmodule | module SpecReg(
input clock, reset, enable,
input [3:0] update_mode,
output negative_flag, zero_flag, carry_flag, overflow_flag, mode_flag,
input alu_negative, alu_zero, alu_carry, alu_overflow,
input bs_negative, bs_zero, bs_carry,
output reg is_bios
); |
reg [4:0] SPECREG;
assign {negative_flag, zero_flag, carry_flag, overflow_flag, mode_flag} = SPECREG;
initial begin
SPECREG <= 0;
is_bios <= 1;
end
always @ ( posedge clock ) begin
if (reset) begin
SPECREG <= 0;
is_bios <= 1;
end else begin
if(enable)
begin
case (update_mode)
1: begin
SPECREG [4:2] <= {bs_negative, bs_zero, bs_carry};
end
2: begin
SPECREG[4:1] <= {alu_negative, alu_zero, alu_carry, alu_overflow};
end
3: begin
SPECREG[4:3] <= {alu_negative, alu_zero};
end
4: begin
SPECREG[1] <= alu_overflow;
end
5: begin
SPECREG[0] <= ~SPECREG[0];
is_bios <= 0;
end
endcase
end
end
end
endmodule | 1 |
141,026 | data/full_repos/permissive/93316915/src/IOmodule/IOmodule.v | 93,316,915 | IOmodule.v | v | 51 | 69 | [] | [] | [] | [(1, 50)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93316915/src/IOmodule/IOmodule.v:25: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'instruction_address\' generates 14 bits.\n : ... In instance IOmodule\n assign RedLEDs = instruction_address;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/93316915/src/IOmodule/IOmodule.v:48: Cannot find file containing module: \'SevenSegDisp\'\n SevenSegDisp ssd(q, SevenSegDisplays);\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93316915/src/IOmodule,data/full_repos/permissive/93316915/SevenSegDisp\n data/full_repos/permissive/93316915/src/IOmodule,data/full_repos/permissive/93316915/SevenSegDisp.v\n data/full_repos/permissive/93316915/src/IOmodule,data/full_repos/permissive/93316915/SevenSegDisp.sv\n SevenSegDisp\n SevenSegDisp.v\n SevenSegDisp.sv\n obj_dir/SevenSegDisp\n obj_dir/SevenSegDisp.v\n obj_dir/SevenSegDisp.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 310,642 | module | module IOmodule #(
parameter DISPLAY_SIZE = 32,
parameter SWITCH_SIZE = 16,
parameter DATA_SIZE = 32,
parameter SPECREG_LEN = 5,
parameter SEGMENT_COUNT = 56,
parameter INSTRUCTION_ADDR_LEN = 14,
parameter INSTRUCTION_LEN = 16
)(
input slow_clock, fast_clock,
input should_update_display,
input reset, enable,
input [(DATA_SIZE - 1) : 0] exported_data,
output [(DATA_SIZE - 1) : 0] imported_data,
input [(SWITCH_SIZE - 1) : 0] switches,
input Neg, Zero, Carry, V, M,
output [(SWITCH_SIZE - 2) : 0] RedLEDs,
output [(SPECREG_LEN - 1) : 0] GreenLEDs,
output [(SEGMENT_COUNT - 1) : 0] SevenSegDisplays,
input [(INSTRUCTION_ADDR_LEN - 1) : 0] instruction_address
);
reg [31:0] info, q;
assign RedLEDs = instruction_address;
assign GreenLEDs[4 : 1] = enable ? {Neg, Zero, Carry, V} : 4'hf;
assign GreenLEDs[0] = M;
assign imported_data = {16'h0, switches[15 : 0]};
initial begin
info = 0;
end
always @ ( posedge slow_clock ) begin
if (reset) begin
info <= 0;
end else begin
if (should_update_display)
info <= exported_data;
end
end
always @ (posedge fast_clock ) begin
q <= info;
end
SevenSegDisp ssd(q, SevenSegDisplays);
endmodule | module IOmodule #(
parameter DISPLAY_SIZE = 32,
parameter SWITCH_SIZE = 16,
parameter DATA_SIZE = 32,
parameter SPECREG_LEN = 5,
parameter SEGMENT_COUNT = 56,
parameter INSTRUCTION_ADDR_LEN = 14,
parameter INSTRUCTION_LEN = 16
)(
input slow_clock, fast_clock,
input should_update_display,
input reset, enable,
input [(DATA_SIZE - 1) : 0] exported_data,
output [(DATA_SIZE - 1) : 0] imported_data,
input [(SWITCH_SIZE - 1) : 0] switches,
input Neg, Zero, Carry, V, M,
output [(SWITCH_SIZE - 2) : 0] RedLEDs,
output [(SPECREG_LEN - 1) : 0] GreenLEDs,
output [(SEGMENT_COUNT - 1) : 0] SevenSegDisplays,
input [(INSTRUCTION_ADDR_LEN - 1) : 0] instruction_address
); |
reg [31:0] info, q;
assign RedLEDs = instruction_address;
assign GreenLEDs[4 : 1] = enable ? {Neg, Zero, Carry, V} : 4'hf;
assign GreenLEDs[0] = M;
assign imported_data = {16'h0, switches[15 : 0]};
initial begin
info = 0;
end
always @ ( posedge slow_clock ) begin
if (reset) begin
info <= 0;
end else begin
if (should_update_display)
info <= exported_data;
end
end
always @ (posedge fast_clock ) begin
q <= info;
end
SevenSegDisp ssd(q, SevenSegDisplays);
endmodule | 1 |
141,027 | data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v | 93,316,915 | SevenSegDisp.v | v | 41 | 34 | [] | [] | [] | [(1, 40)] | null | null | 1: b"%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:7: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp0 (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93316915/src/IOmodule,data/full_repos/permissive/93316915/HexDecoder\n data/full_repos/permissive/93316915/src/IOmodule,data/full_repos/permissive/93316915/HexDecoder.v\n data/full_repos/permissive/93316915/src/IOmodule,data/full_repos/permissive/93316915/HexDecoder.sv\n HexDecoder\n HexDecoder.v\n HexDecoder.sv\n obj_dir/HexDecoder\n obj_dir/HexDecoder.v\n obj_dir/HexDecoder.sv\n%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:11: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp1 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:15: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp2 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:19: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp3 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:23: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp4 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:27: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp5 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:31: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp6 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/93316915/src/IOmodule/SevenSegDisp.v:35: Cannot find file containing module: 'HexDecoder'\n HexDecoder dsp7 (\n ^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 310,643 | module | module SevenSegDisp(
Display7, SevenSegDisplays
);
input [31:0] Display7;
output [55:0] SevenSegDisplays;
HexDecoder dsp0 (
Display7[3:0],
SevenSegDisplays[6:0]
);
HexDecoder dsp1 (
Display7[7:4],
SevenSegDisplays[13:7]
);
HexDecoder dsp2 (
Display7[11:8],
SevenSegDisplays[20:14]
);
HexDecoder dsp3 (
Display7[15:12],
SevenSegDisplays[27:21]
);
HexDecoder dsp4 (
Display7[19:16],
SevenSegDisplays[34:28]
);
HexDecoder dsp5 (
Display7[23:20],
SevenSegDisplays[41:35]
);
HexDecoder dsp6 (
Display7[27:24],
SevenSegDisplays[48:42]
);
HexDecoder dsp7 (
Display7[31:28],
SevenSegDisplays[55:49]
);
endmodule | module SevenSegDisp(
Display7, SevenSegDisplays
); |
input [31:0] Display7;
output [55:0] SevenSegDisplays;
HexDecoder dsp0 (
Display7[3:0],
SevenSegDisplays[6:0]
);
HexDecoder dsp1 (
Display7[7:4],
SevenSegDisplays[13:7]
);
HexDecoder dsp2 (
Display7[11:8],
SevenSegDisplays[20:14]
);
HexDecoder dsp3 (
Display7[15:12],
SevenSegDisplays[27:21]
);
HexDecoder dsp4 (
Display7[19:16],
SevenSegDisplays[34:28]
);
HexDecoder dsp5 (
Display7[23:20],
SevenSegDisplays[41:35]
);
HexDecoder dsp6 (
Display7[27:24],
SevenSegDisplays[48:42]
);
HexDecoder dsp7 (
Display7[31:28],
SevenSegDisplays[55:49]
);
endmodule | 1 |
141,028 | data/full_repos/permissive/93316915/src/MemoryUnit/BIOS.v | 93,316,915 | BIOS.v | v | 24 | 49 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/938c6d60-1156-485d-b6f2-58d81aa0a8f7.xml | null | 310,644 | module | module BIOS
#(
parameter DATA_WIDTH=16,
parameter ADDR_WIDTH=8
)(
input clk,
input [(ADDR_WIDTH-1):0] addr,
output reg [(DATA_WIDTH-1):0] q
);
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
initial
begin
$readmemb("./biosInitiationAddress.txt", rom);
end
always @ (posedge clk)
begin
q <= rom[addr];
end
endmodule | module BIOS
#(
parameter DATA_WIDTH=16,
parameter ADDR_WIDTH=8
)(
input clk,
input [(ADDR_WIDTH-1):0] addr,
output reg [(DATA_WIDTH-1):0] q
); |
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
initial
begin
$readmemb("./biosInitiationAddress.txt", rom);
end
always @ (posedge clk)
begin
q <= rom[addr];
end
endmodule | 1 |
141,029 | data/full_repos/permissive/93316915/src/MemoryUnit/Memory.v | 93,316,915 | Memory.v | v | 41 | 61 | [] | [] | [] | null | line:5: before: ";" | null | 1: b"%Error: data/full_repos/permissive/93316915/src/MemoryUnit/Memory.v:5: syntax error, unexpected ';', expecting ')' or ','\n parameter INSTRUCTION_SIZE = 16;\n ^\n%Error: data/full_repos/permissive/93316915/src/MemoryUnit/Memory.v:7: syntax error, unexpected ')', expecting ';'\n)(\n^\n%Error: data/full_repos/permissive/93316915/src/MemoryUnit/Memory.v:13: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/93316915/src/MemoryUnit/Memory.v:16: syntax error, unexpected assign\n assign instruction = fetched_instruction[15:0];\n ^~~~~~\n%Error: data/full_repos/permissive/93316915/src/MemoryUnit/Memory.v:22: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 310,645 | module | module Memory
#(
parameter DW=32,
parameter ADDR_WIDTH=13,
parameter INSTRUCTION_SIZE = 16;
parameter inputFile = "Program.txt"
)(
input [(DW-1):0] input_data,
input [(ADDR_WIDTH-1):0] instruction_address, data_address,
input write_enable, read_clock, write_clock,
output [(INSTRUCTION_SIZE - 1):0] instruction,
output reg [(DW-1):0] output_data
);
reg [(DW-1):0] fetched_instruction;
assign instruction = fetched_instruction[15:0];
reg [DW-1:0] ram[2**ADDR_WIDTH-1:0];
initial begin
$readmemb(inputFile, ram);
end
always @ (posedge read_clock)
begin
fetched_instruction = ram[instruction_address];
output_data = ram[data_address];
end
always @ (posedge write_clock)
begin
if (write_enable)
ram[data_address] <= input_data;
end
endmodule | module Memory
#(
parameter DW=32,
parameter ADDR_WIDTH=13,
parameter INSTRUCTION_SIZE = 16; |
parameter inputFile = "Program.txt"
)(
input [(DW-1):0] input_data,
input [(ADDR_WIDTH-1):0] instruction_address, data_address,
input write_enable, read_clock, write_clock,
output [(INSTRUCTION_SIZE - 1):0] instruction,
output reg [(DW-1):0] output_data
);
reg [(DW-1):0] fetched_instruction;
assign instruction = fetched_instruction[15:0];
reg [DW-1:0] ram[2**ADDR_WIDTH-1:0];
initial begin
$readmemb(inputFile, ram);
end
always @ (posedge read_clock)
begin
fetched_instruction = ram[instruction_address];
output_data = ram[data_address];
end
always @ (posedge write_clock)
begin
if (write_enable)
ram[data_address] <= input_data;
end
endmodule | 1 |
141,037 | data/full_repos/permissive/9338313/pixel_alu.v | 9,338,313 | pixel_alu.v | v | 134 | 76 | [] | ['apache license'] | [] | [(22, 132)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:76: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'srca\' generates 3 bits.\n : ... In instance pixel_alu\n casez (srca)\n ^~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:76: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'bzz\' generates 3 bits.\n : ... In instance pixel_alu\n casez (srca)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:88: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'srcb\' generates 3 bits.\n : ... In instance pixel_alu\n casez (srcb)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:88: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'bzz\' generates 3 bits.\n : ... In instance pixel_alu\n casez (srcb)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:114: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'equal\' generates 1 bits.\n : ... In instance pixel_alu\n OP_EQ: result = equal;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:115: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n : ... In instance pixel_alu\n OP_NEQ: result = !equal;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:116: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n : ... In instance pixel_alu\n OP_GT: result = !equal && !less;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:117: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n : ... In instance pixel_alu\n OP_GTE: result = !less;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:118: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'less\' generates 1 bits.\n : ... In instance pixel_alu\n OP_LT: result = less;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:119: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n : ... In instance pixel_alu\n OP_LTE: result = less || equal;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_alu.v:129: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'dest\' generates 3 bits.\n : ... In instance pixel_alu\n if (dest == REG_RESULT)\n ^~\n%Error: Exiting due to 11 warning(s)\n' | 310,661 | module | module pixel_alu(
input clk,
input[45:0] instruction,
input[31:0] x_coord,
input[31:0] y_coord,
input[31:0] f_number,
output reg[11:0] output_value);
localparam OP_AND = 0;
localparam OP_XOR = 1;
localparam OP_OR = 2;
localparam OP_ADD = 3;
localparam OP_SUB = 4;
localparam OP_MUL = 5;
localparam OP_SHL = 6;
localparam OP_SHR = 7;
localparam OP_MOV = 8;
localparam OP_EQ = 9;
localparam OP_NEQ = 10;
localparam OP_GT = 11;
localparam OP_GTE = 12;
localparam OP_LT = 13;
localparam OP_LTE = 14;
localparam REG_X = 4'd4;
localparam REG_Y = 4'd5;
localparam REG_F = 4'd6;
localparam REG_RESULT = 4'd7;
reg[31:0] registers[0:3];
wire[2:0] dest = instruction[45:43];
wire[2:0] srca = instruction[42:40];
wire[2:0] srcb = instruction[39:37];
wire[3:0] operation = instruction[36:33];
wire use_const = instruction[32];
wire[31:0] const_val = instruction[31:0];
reg[31:0] operand1;
reg[31:0] operand2;
reg[31:0] result;
wire[31:0] difference;
wire equal;
wire less;
integer i;
initial
begin
output_value = 0;
for (i = 0; i < 4; i = i + 1)
registers[i] = 0;
end
always @*
begin
casez (srca)
3'b0??: operand1 = registers[srca[1:0]];
REG_X: operand1 = x_coord;
REG_Y: operand1 = y_coord;
REG_F: operand1 = f_number;
default: operand1 = 32'dX;
endcase
if (use_const)
operand2 = const_val;
else
begin
casez (srcb)
3'b0??: operand2 = registers[srcb[1:0]];
REG_X: operand2 = x_coord;
REG_Y: operand2 = y_coord;
REG_F: operand2 = f_number;
default: operand2 = 32'dX;
endcase
end
end
assign difference = operand1 - operand2;
assign equal = difference == 0;
assign less = difference[31];
always @*
begin
case (operation)
OP_AND: result = operand1 & operand2;
OP_XOR: result = operand1 ^ operand2;
OP_OR: result = operand1 | operand2;
OP_ADD: result = operand1 + operand2;
OP_SUB: result = difference;
OP_MUL: result = operand1 * operand2;
OP_SHL: result = operand1 << operand2;
OP_SHR: result = operand1 >> operand2;
OP_MOV: result = operand2;
OP_EQ: result = equal;
OP_NEQ: result = !equal;
OP_GT: result = !equal && !less;
OP_GTE: result = !less;
OP_LT: result = less;
OP_LTE: result = less || equal;
default: result = 32'dX;
endcase
end
always @(posedge clk)
begin
if (!dest[2])
registers[dest[1:0]] <= result;
if (dest == REG_RESULT)
output_value <= { result[23:20], result[15:12], result[7:4] };
end
endmodule | module pixel_alu(
input clk,
input[45:0] instruction,
input[31:0] x_coord,
input[31:0] y_coord,
input[31:0] f_number,
output reg[11:0] output_value); |
localparam OP_AND = 0;
localparam OP_XOR = 1;
localparam OP_OR = 2;
localparam OP_ADD = 3;
localparam OP_SUB = 4;
localparam OP_MUL = 5;
localparam OP_SHL = 6;
localparam OP_SHR = 7;
localparam OP_MOV = 8;
localparam OP_EQ = 9;
localparam OP_NEQ = 10;
localparam OP_GT = 11;
localparam OP_GTE = 12;
localparam OP_LT = 13;
localparam OP_LTE = 14;
localparam REG_X = 4'd4;
localparam REG_Y = 4'd5;
localparam REG_F = 4'd6;
localparam REG_RESULT = 4'd7;
reg[31:0] registers[0:3];
wire[2:0] dest = instruction[45:43];
wire[2:0] srca = instruction[42:40];
wire[2:0] srcb = instruction[39:37];
wire[3:0] operation = instruction[36:33];
wire use_const = instruction[32];
wire[31:0] const_val = instruction[31:0];
reg[31:0] operand1;
reg[31:0] operand2;
reg[31:0] result;
wire[31:0] difference;
wire equal;
wire less;
integer i;
initial
begin
output_value = 0;
for (i = 0; i < 4; i = i + 1)
registers[i] = 0;
end
always @*
begin
casez (srca)
3'b0??: operand1 = registers[srca[1:0]];
REG_X: operand1 = x_coord;
REG_Y: operand1 = y_coord;
REG_F: operand1 = f_number;
default: operand1 = 32'dX;
endcase
if (use_const)
operand2 = const_val;
else
begin
casez (srcb)
3'b0??: operand2 = registers[srcb[1:0]];
REG_X: operand2 = x_coord;
REG_Y: operand2 = y_coord;
REG_F: operand2 = f_number;
default: operand2 = 32'dX;
endcase
end
end
assign difference = operand1 - operand2;
assign equal = difference == 0;
assign less = difference[31];
always @*
begin
case (operation)
OP_AND: result = operand1 & operand2;
OP_XOR: result = operand1 ^ operand2;
OP_OR: result = operand1 | operand2;
OP_ADD: result = operand1 + operand2;
OP_SUB: result = difference;
OP_MUL: result = operand1 * operand2;
OP_SHL: result = operand1 << operand2;
OP_SHR: result = operand1 >> operand2;
OP_MOV: result = operand2;
OP_EQ: result = equal;
OP_NEQ: result = !equal;
OP_GT: result = !equal && !less;
OP_GTE: result = !less;
OP_LT: result = less;
OP_LTE: result = less || equal;
default: result = 32'dX;
endcase
end
always @(posedge clk)
begin
if (!dest[2])
registers[dest[1:0]] <= result;
if (dest == REG_RESULT)
output_value <= { result[23:20], result[15:12], result[7:4] };
end
endmodule | 12 |
141,039 | data/full_repos/permissive/9338313/pixel_processor.v | 9,338,313 | pixel_processor.v | v | 96 | 76 | [] | ['apache license'] | [] | [(18, 95)] | null | null | 1: b'%Error: data/full_repos/permissive/9338313/pixel_processor.v:50: Cannot find file containing module: \'pixel_alu\'\n pixel_alu pixel_alu0(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9338313,data/full_repos/permissive/9338313/pixel_alu\n data/full_repos/permissive/9338313,data/full_repos/permissive/9338313/pixel_alu.v\n data/full_repos/permissive/9338313,data/full_repos/permissive/9338313/pixel_alu.sv\n pixel_alu\n pixel_alu.v\n pixel_alu.sv\n obj_dir/pixel_alu\n obj_dir/pixel_alu.v\n obj_dir/pixel_alu.sv\n%Error: data/full_repos/permissive/9338313/pixel_processor.v:62: Cannot find file containing module: \'sram_1r1w\'\n sram_1r1w #(INSTRUCTION_WIDTH, MAX_INSTRUCTIONS) instruction_mem(\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9338313/pixel_processor.v:83: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance pixel_processor\n pc <= 5\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 310,663 | module | module pixel_processor
#(parameter NUM_PIXELS = 8,
parameter PIXEL_WIDTH = 12,
parameter OUTPUT_WIDTH = NUM_PIXELS * PIXEL_WIDTH)
(input clk,
input new_frame,
input start_next_batch,
output[OUTPUT_WIDTH - 1:0] result,
output result_ready);
localparam INSTRUCTION_WIDTH = 46;
reg[3:0] pc;
wire[INSTRUCTION_WIDTH - 1:0] instruction;
reg[31:0] y_coord;
reg[31:0] f_number;
genvar lane;
generate
for (lane = 0; lane < NUM_PIXELS; lane = lane + 1)
begin : pixel_compute
reg[31:0] x_coord = 0;
always @(posedge clk)
begin
if (new_frame || (end_of_line && start_next_batch))
x_coord <= lane;
else if (start_next_batch)
x_coord <= x_coord + NUM_PIXELS;
end
pixel_alu pixel_alu0(
.clk(clk),
.instruction(instruction),
.x_coord(x_coord),
.y_coord(y_coord),
.f_number(f_number),
.output_value(result[lane * PIXEL_WIDTH+:PIXEL_WIDTH]));
end
endgenerate
localparam MAX_INSTRUCTIONS = NUM_PIXELS * 2;
sram_1r1w #(INSTRUCTION_WIDTH, MAX_INSTRUCTIONS) instruction_mem(
.clk(clk),
.rd_addr(pc),
.rd_data(instruction),
.wr_enable(0),
.wr_addr(0),
.wr_data({INSTRUCTION_WIDTH{1'b0}}));
initial
begin
pc = 0;
y_coord = 0;
f_number = 0;
end
assign result_ready = pc == MAX_INSTRUCTIONS - 1;
wire end_of_line = pixel_compute[0].x_coord == 640 - NUM_PIXELS;
always @(posedge clk)
begin
if (new_frame || start_next_batch)
pc <= 5'd0;
else if (!result_ready)
pc <= pc + 1;
if (new_frame)
begin
f_number <= f_number + 1;
y_coord <= 0;
end
else if (end_of_line && start_next_batch)
y_coord <= y_coord + 1;
end
endmodule | module pixel_processor
#(parameter NUM_PIXELS = 8,
parameter PIXEL_WIDTH = 12,
parameter OUTPUT_WIDTH = NUM_PIXELS * PIXEL_WIDTH)
(input clk,
input new_frame,
input start_next_batch,
output[OUTPUT_WIDTH - 1:0] result,
output result_ready); |
localparam INSTRUCTION_WIDTH = 46;
reg[3:0] pc;
wire[INSTRUCTION_WIDTH - 1:0] instruction;
reg[31:0] y_coord;
reg[31:0] f_number;
genvar lane;
generate
for (lane = 0; lane < NUM_PIXELS; lane = lane + 1)
begin : pixel_compute
reg[31:0] x_coord = 0;
always @(posedge clk)
begin
if (new_frame || (end_of_line && start_next_batch))
x_coord <= lane;
else if (start_next_batch)
x_coord <= x_coord + NUM_PIXELS;
end
pixel_alu pixel_alu0(
.clk(clk),
.instruction(instruction),
.x_coord(x_coord),
.y_coord(y_coord),
.f_number(f_number),
.output_value(result[lane * PIXEL_WIDTH+:PIXEL_WIDTH]));
end
endgenerate
localparam MAX_INSTRUCTIONS = NUM_PIXELS * 2;
sram_1r1w #(INSTRUCTION_WIDTH, MAX_INSTRUCTIONS) instruction_mem(
.clk(clk),
.rd_addr(pc),
.rd_data(instruction),
.wr_enable(0),
.wr_addr(0),
.wr_data({INSTRUCTION_WIDTH{1'b0}}));
initial
begin
pc = 0;
y_coord = 0;
f_number = 0;
end
assign result_ready = pc == MAX_INSTRUCTIONS - 1;
wire end_of_line = pixel_compute[0].x_coord == 640 - NUM_PIXELS;
always @(posedge clk)
begin
if (new_frame || start_next_batch)
pc <= 5'd0;
else if (!result_ready)
pc <= pc + 1;
if (new_frame)
begin
f_number <= f_number + 1;
y_coord <= 0;
end
else if (end_of_line && start_next_batch)
y_coord <= y_coord + 1;
end
endmodule | 12 |
141,040 | data/full_repos/permissive/9338313/sram_1r1w.v | 9,338,313 | sram_1r1w.v | v | 53 | 76 | [] | ['apache license'] | [] | null | line:25: before: "=" | data/verilator_xmls/25fd6932-1da1-4efa-b471-7608da6c1dce.xml | null | 310,664 | module | module sram_1r1w
#(parameter DATA_WIDTH = 32,
parameter SIZE = 1024,
parameter ADDR_WIDTH = $clog2(SIZE))
(input clk,
input [ADDR_WIDTH - 1:0] rd_addr,
output reg[DATA_WIDTH - 1:0] rd_data = 0,
input wr_enable,
input [ADDR_WIDTH - 1:0] wr_addr,
input [DATA_WIDTH - 1:0] wr_data);
reg[DATA_WIDTH - 1:0] data[0:SIZE - 1];
integer i;
initial
begin
for (i = 0; i < SIZE; i = i + 1)
data[i] = 0;
rd_data = 0;
$readmemh("microcode.hex", data);
end
always @(posedge clk)
begin
if (wr_enable)
data[wr_addr] <= wr_data;
if (wr_addr == rd_addr && wr_enable)
rd_data <= wr_data;
else
rd_data <= data[rd_addr];
end
endmodule | module sram_1r1w
#(parameter DATA_WIDTH = 32,
parameter SIZE = 1024,
parameter ADDR_WIDTH = $clog2(SIZE))
(input clk,
input [ADDR_WIDTH - 1:0] rd_addr,
output reg[DATA_WIDTH - 1:0] rd_data = 0,
input wr_enable,
input [ADDR_WIDTH - 1:0] wr_addr,
input [DATA_WIDTH - 1:0] wr_data); |
reg[DATA_WIDTH - 1:0] data[0:SIZE - 1];
integer i;
initial
begin
for (i = 0; i < SIZE; i = i + 1)
data[i] = 0;
rd_data = 0;
$readmemh("microcode.hex", data);
end
always @(posedge clk)
begin
if (wr_enable)
data[wr_addr] <= wr_data;
if (wr_addr == rd_addr && wr_enable)
rd_data <= wr_data;
else
rd_data <= data[rd_addr];
end
endmodule | 12 |
141,041 | data/full_repos/permissive/9338313/testbench.v | 9,338,313 | testbench.v | v | 45 | 76 | [] | ['apache license'] | [] | [(17, 44)] | null | null | 1: b'%Error: data/full_repos/permissive/9338313/testbench.v:37: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("trace.lxt");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9338313/testbench.v:38: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9338313/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,665 | module | module testbench;
integer i;
reg clk;
wire vsync;
wire hsync;
wire[3:0] red;
wire[3:0] blue;
wire[3:0] green;
top top(
.clk(clk),
.vsync_o(vsync),
.hsync_o(hsync),
.red_o(red),
.blue_o(blue),
.green_o(green));
initial
begin
$dumpfile("trace.lxt");
$dumpvars;
clk = 0;
for (i = 0; i < 400000; i = i + 1)
#5 clk = !clk;
end
endmodule | module testbench; |
integer i;
reg clk;
wire vsync;
wire hsync;
wire[3:0] red;
wire[3:0] blue;
wire[3:0] green;
top top(
.clk(clk),
.vsync_o(vsync),
.hsync_o(hsync),
.red_o(red),
.blue_o(blue),
.green_o(green));
initial
begin
$dumpfile("trace.lxt");
$dumpvars;
clk = 0;
for (i = 0; i < 400000; i = i + 1)
#5 clk = !clk;
end
endmodule | 12 |
141,043 | data/full_repos/permissive/9338313/vga_timing_generator.v | 9,338,313 | vga_timing_generator.v | v | 113 | 76 | [] | ['apache license'] | [] | [(19, 112)] | null | data/verilator_xmls/fdc35cc6-0605-45e4-b29a-0c3169e32726.xml | null | 310,667 | module | module vga_timing_generator(
input clk,
output reg vsync_o,
output reg hsync_o,
output in_visible_region,
output pixel_out,
output new_frame);
parameter HSYNC_START = 16;
parameter HSYNC_END = HSYNC_START + 96;
parameter HVISIBLE_START = HSYNC_END + 48;
parameter HVISIBLE_END = HVISIBLE_START + 640;
parameter VSYNC_START = 10;
parameter VSYNC_END = VSYNC_START + 2;
parameter VVISIBLE_START = VSYNC_END + 33;
parameter VVISIBLE_END = VVISIBLE_START + 480;
reg hvisible;
reg vvisible;
reg[10:0] horizontal_counter;
reg[10:0] vertical_counter;
reg dot_enable = 0;
assign pixel_out = dot_enable && in_visible_region;
assign in_visible_region = hvisible && vvisible;
initial
begin
vsync_o = 0;
hsync_o = 0;
hvisible = 0;
vvisible = 0;
horizontal_counter = 0;
vertical_counter = 0;
end
wire hvisible_end = horizontal_counter == HVISIBLE_END;
wire vvisible_end = vertical_counter == VVISIBLE_END;
assign new_frame = horizontal_counter == 0 && vertical_counter == 0;
always @(posedge clk)
begin
dot_enable <= !dot_enable;
if (dot_enable)
begin
if (hvisible_end)
begin
horizontal_counter <= 0;
hvisible <= 0;
if (vvisible_end)
begin
vvisible <= 0;
vertical_counter <= 0;
end
else
vertical_counter <= vertical_counter + 1;
end
else
horizontal_counter <= horizontal_counter + 1;
if (vertical_counter == VSYNC_START)
vsync_o <= 0;
else if (vertical_counter == VSYNC_END)
vsync_o <= 1;
else if (vertical_counter == VVISIBLE_START)
vvisible <= 1;
if (horizontal_counter == HSYNC_START)
hsync_o <= 0;
else if (horizontal_counter == HSYNC_END)
hsync_o <= 1;
else if (horizontal_counter == HVISIBLE_START)
hvisible <= 1;
end
end
endmodule | module vga_timing_generator(
input clk,
output reg vsync_o,
output reg hsync_o,
output in_visible_region,
output pixel_out,
output new_frame); |
parameter HSYNC_START = 16;
parameter HSYNC_END = HSYNC_START + 96;
parameter HVISIBLE_START = HSYNC_END + 48;
parameter HVISIBLE_END = HVISIBLE_START + 640;
parameter VSYNC_START = 10;
parameter VSYNC_END = VSYNC_START + 2;
parameter VVISIBLE_START = VSYNC_END + 33;
parameter VVISIBLE_END = VVISIBLE_START + 480;
reg hvisible;
reg vvisible;
reg[10:0] horizontal_counter;
reg[10:0] vertical_counter;
reg dot_enable = 0;
assign pixel_out = dot_enable && in_visible_region;
assign in_visible_region = hvisible && vvisible;
initial
begin
vsync_o = 0;
hsync_o = 0;
hvisible = 0;
vvisible = 0;
horizontal_counter = 0;
vertical_counter = 0;
end
wire hvisible_end = horizontal_counter == HVISIBLE_END;
wire vvisible_end = vertical_counter == VVISIBLE_END;
assign new_frame = horizontal_counter == 0 && vertical_counter == 0;
always @(posedge clk)
begin
dot_enable <= !dot_enable;
if (dot_enable)
begin
if (hvisible_end)
begin
horizontal_counter <= 0;
hvisible <= 0;
if (vvisible_end)
begin
vvisible <= 0;
vertical_counter <= 0;
end
else
vertical_counter <= vertical_counter + 1;
end
else
horizontal_counter <= horizontal_counter + 1;
if (vertical_counter == VSYNC_START)
vsync_o <= 0;
else if (vertical_counter == VSYNC_END)
vsync_o <= 1;
else if (vertical_counter == VVISIBLE_START)
vvisible <= 1;
if (horizontal_counter == HSYNC_START)
hsync_o <= 0;
else if (horizontal_counter == HSYNC_END)
hsync_o <= 1;
else if (horizontal_counter == HVISIBLE_START)
hvisible <= 1;
end
end
endmodule | 12 |
141,046 | data/full_repos/permissive/93413349/FPGA_Project/DelayTesterSystem/synthesis/submodules/timer_module.sv | 93,413,349 | timer_module.sv | sv | 22 | 34 | [] | [] | [] | [(1, 22)] | null | data/verilator_xmls/adae75ff-ded7-4ebe-a4e5-f90c716b5f11.xml | null | 310,835 | module | module timer_module #(
parameter WIDTH = 32
)(
input wire srst_n_i,
input wire clk_i,
output logic [WIDTH-1:0] count_o
);
logic [WIDTH-1:0] count_val;
always_ff @(posedge clk_i)
begin
if ( ~srst_n_i )
count_val <= 'b0;
else
count_val <= count_val + 1'b1;
end
assign count_o = count_val;
endmodule | module timer_module #(
parameter WIDTH = 32
)(
input wire srst_n_i,
input wire clk_i,
output logic [WIDTH-1:0] count_o
); |
logic [WIDTH-1:0] count_val;
always_ff @(posedge clk_i)
begin
if ( ~srst_n_i )
count_val <= 'b0;
else
count_val <= count_val + 1'b1;
end
assign count_o = count_val;
endmodule | 1 |
141,047 | data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Timer/timer_tb.sv | 93,413,349 | timer_tb.sv | sv | 37 | 45 | [] | [] | [] | null | line:33: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Timer/timer_tb.sv:21: Unsupported: Ignoring delay on this delayed statement.\n forever #CLK_HALF_PERIOD clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Timer/timer_tb.sv:27: Unsupported: Ignoring delay on this delayed statement.\n #( CLK_HALF_PERIOD + 1 ) reset_n = 1\'b1;\n ^\n%Error: data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Timer/timer_tb.sv:33: syntax error, unexpected \'@\'\n repeat (20) @( posedge clk );\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,839 | module | module timer_tb;
localparam WIDTH = 32;
localparam CLK_HALF_PERIOD = 5;
logic clk;
logic reset_n;
logic [WIDTH-1:0] timer_out;
timer dut_timer (
.clk_clk (clk),
.reset_reset_n (reset_n),
.simple_timer_0_timer_out_value (timer_out)
);
initial
begin : clk_generator
clk = 1'b0;
forever #CLK_HALF_PERIOD clk = ~clk;
end
initial
begin : sync_reset_generator
reset_n = 1'b0;
#( CLK_HALF_PERIOD + 1 ) reset_n = 1'b1;
end
initial
begin : test_sequence_generator
repeat (20) @( posedge clk );
$stop;
end
endmodule | module timer_tb; |
localparam WIDTH = 32;
localparam CLK_HALF_PERIOD = 5;
logic clk;
logic reset_n;
logic [WIDTH-1:0] timer_out;
timer dut_timer (
.clk_clk (clk),
.reset_reset_n (reset_n),
.simple_timer_0_timer_out_value (timer_out)
);
initial
begin : clk_generator
clk = 1'b0;
forever #CLK_HALF_PERIOD clk = ~clk;
end
initial
begin : sync_reset_generator
reset_n = 1'b0;
#( CLK_HALF_PERIOD + 1 ) reset_n = 1'b1;
end
initial
begin : test_sequence_generator
repeat (20) @( posedge clk );
$stop;
end
endmodule | 1 |
141,050 | data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Transmitter/top_transmitter.sv | 93,413,349 | top_transmitter.sv | sv | 42 | 180 | [] | [] | [] | [(2, 42)] | null | null | 1: b"%Error: data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Transmitter/top_transmitter.sv:23: Cannot find file containing module: 'transmitter'\n transmitter u0 (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Transmitter,data/full_repos/permissive/93413349/transmitter\n data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Transmitter,data/full_repos/permissive/93413349/transmitter.v\n data/full_repos/permissive/93413349/FPGA_Project/rtl/ip/Transmitter,data/full_repos/permissive/93413349/transmitter.sv\n transmitter\n transmitter.v\n transmitter.sv\n obj_dir/transmitter\n obj_dir/transmitter.v\n obj_dir/transmitter.sv\n%Error: Exiting due to 1 error(s)\n" | 310,847 | module | module top_transmitter(
input logic clk_i,
input logic reset_n,
input logic [31:0] timer_in,
input logic amm_wr,
input logic amm_rd,
input logic [31:0] amm_address,
input logic [31:0] amm_wrdata,
output logic [31:0] amm_rddata,
output logic amm_rddatavalid,
input logic [31:0] ast_data,
input logic [1:0] ast_empty,
input logic ast_ready,
input logic ast_sop,
input logic ast_eop,
input logic ast_val
);
transmitter u0 (
.clk_clk (clk_i),
.reset_reset_n (reset_n),
.packet_transmitter_0_avalon_slave_write (amm_wr),
.packet_transmitter_0_avalon_slave_readdata (amm_rddata),
.packet_transmitter_0_avalon_slave_read (amm_rd),
.packet_transmitter_0_avalon_slave_address (amm_address),
.packet_transmitter_0_avalon_slave_writedata (amm_wrdata),
.packet_transmitter_0_conduit_end_export (timer_in),
.packet_transmitter_0_avalon_streaming_source_data (ast_data),
.packet_transmitter_0_avalon_streaming_source_empty (ast_empty),
.packet_transmitter_0_avalon_streaming_source_ready (ast_ready),
.packet_transmitter_0_avalon_streaming_source_endofpacket (ast_eop),
.packet_transmitter_0_avalon_streaming_source_startofpacket (ast_sop),
.packet_transmitter_0_avalon_streaming_source_valid (ast_val)
);
endmodule | module top_transmitter(
input logic clk_i,
input logic reset_n,
input logic [31:0] timer_in,
input logic amm_wr,
input logic amm_rd,
input logic [31:0] amm_address,
input logic [31:0] amm_wrdata,
output logic [31:0] amm_rddata,
output logic amm_rddatavalid,
input logic [31:0] ast_data,
input logic [1:0] ast_empty,
input logic ast_ready,
input logic ast_sop,
input logic ast_eop,
input logic ast_val
); |
transmitter u0 (
.clk_clk (clk_i),
.reset_reset_n (reset_n),
.packet_transmitter_0_avalon_slave_write (amm_wr),
.packet_transmitter_0_avalon_slave_readdata (amm_rddata),
.packet_transmitter_0_avalon_slave_read (amm_rd),
.packet_transmitter_0_avalon_slave_address (amm_address),
.packet_transmitter_0_avalon_slave_writedata (amm_wrdata),
.packet_transmitter_0_conduit_end_export (timer_in),
.packet_transmitter_0_avalon_streaming_source_data (ast_data),
.packet_transmitter_0_avalon_streaming_source_empty (ast_empty),
.packet_transmitter_0_avalon_streaming_source_ready (ast_ready),
.packet_transmitter_0_avalon_streaming_source_endofpacket (ast_eop),
.packet_transmitter_0_avalon_streaming_source_startofpacket (ast_sop),
.packet_transmitter_0_avalon_streaming_source_valid (ast_val)
);
endmodule | 1 |
141,053 | data/full_repos/permissive/93424147/001_pushbuttons_leds/always/pushbuttons_leds.v | 93,424,147 | pushbuttons_leds.v | v | 20 | 82 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/cff298fa-f045-4ea5-a481-9ba5cf73db1d.xml | null | 310,856 | module | module pushbuttons_leds(
input PB0_n,
input PB1_n,
output reg LED0,
output reg LED1
);
wire PB0 = ~PB0_n;
wire PB1 = ~PB1_n;
always @(PB0 or PB1)
begin
LED0 = PB0;
LED1 = PB1;
end
endmodule | module pushbuttons_leds(
input PB0_n,
input PB1_n,
output reg LED0,
output reg LED1
); |
wire PB0 = ~PB0_n;
wire PB1 = ~PB1_n;
always @(PB0 or PB1)
begin
LED0 = PB0;
LED1 = PB1;
end
endmodule | 0 |
141,054 | data/full_repos/permissive/93424147/001_pushbuttons_leds/assign/pushbuttons_leds.v | 93,424,147 | pushbuttons_leds.v | v | 16 | 82 | [] | [] | [] | [(2, 15)] | null | data/verilator_xmls/20ba6e2a-e572-4419-9bee-c48609005410.xml | null | 310,857 | module | module pushbuttons_leds_assign(
input PB0_n,
input PB1_n,
output LED0,
output LED1
);
wire PB0 = ~PB0_n;
wire PB1 = ~PB1_n;
assign LED0 = PB0;
assign LED1 = PB1;
endmodule | module pushbuttons_leds_assign(
input PB0_n,
input PB1_n,
output LED0,
output LED1
); |
wire PB0 = ~PB0_n;
wire PB1 = ~PB1_n;
assign LED0 = PB0;
assign LED1 = PB1;
endmodule | 0 |
141,055 | data/full_repos/permissive/93424147/Icarus/OpenSolicium08/essai.v | 93,424,147 | essai.v | v | 11 | 44 | [] | [] | [] | [(1, 10)] | null | data/verilator_xmls/bcb7a0ef-a062-42b2-b857-cef94c7f1747.xml | null | 310,858 | module | module essai();
initial
begin
$display("Debut de la simulation");
$finish;
end
endmodule | module essai(); |
initial
begin
$display("Debut de la simulation");
$finish;
end
endmodule | 0 |
141,056 | data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier.v | 93,424,147 | premier.v | v | 48 | 49 | [] | [] | [] | null | line:48: before: "endmodule" | null | 1: b"%Error: data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier.v:48: syntax error, unexpected endmodule, expecting ',' or ';'\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n" | 310,859 | module | module Premier
(
input wire MCLK50M,
output wire led1,
output wire led2,
output wire led3
);
blink instled1 (MCLK50M, led1);
blink #(32'd6499999) instled2 (MCLK50M,led2);
blink #(32'd3499999) instled3 (MCLK50M,led3);
endmodule | module Premier
(
input wire MCLK50M,
output wire led1,
output wire led2,
output wire led3
); |
blink instled1 (MCLK50M, led1);
blink #(32'd6499999) instled2 (MCLK50M,led2);
blink #(32'd3499999) instled3 (MCLK50M,led3);
endmodule | 0 |
Subsets and Splits