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140,629 | data/full_repos/permissive/90852660/Exp 11/ram.v | 90,852,660 | ram.v | v | 17 | 33 | [] | [] | [] | [(1, 17)] | null | null | 1: b'%Error: Cannot find file containing module: 11,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/11,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/11,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/11,data/full_repos/permissive/90852660.sv\n 11,data/full_repos/permissive/90852660\n 11,data/full_repos/permissive/90852660.v\n 11,data/full_repos/permissive/90852660.sv\n obj_dir/11,data/full_repos/permissive/90852660\n obj_dir/11,data/full_repos/permissive/90852660.v\n obj_dir/11,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 11/ram.v\n%Error: Exiting due to 3 error(s)\n' | 309,384 | module | module ram(add,di,do,cs,we);
input [3:0]di,add;
input cs,we;
output [3:0]do;
reg [3:0]RAM[15:0];
reg [3:0]do;
always @(cs or we or add or di)
begin
if(cs==0 &we==0)
begin
RAM[add]=di;
do='bz;
end
else if(cs==0 & we==1)
do=RAM[add];
end
endmodule | module ram(add,di,do,cs,we); |
input [3:0]di,add;
input cs,we;
output [3:0]do;
reg [3:0]RAM[15:0];
reg [3:0]do;
always @(cs or we or add or di)
begin
if(cs==0 &we==0)
begin
RAM[add]=di;
do='bz;
end
else if(cs==0 & we==1)
do=RAM[add];
end
endmodule | 3 |
140,631 | data/full_repos/permissive/90852660/Exp 12/alu.v | 90,852,660 | alu.v | v | 24 | 30 | [] | [] | [] | [(1, 24)] | null | null | 1: b'%Error: Cannot find file containing module: 12,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/12,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/12,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/12,data/full_repos/permissive/90852660.sv\n 12,data/full_repos/permissive/90852660\n 12,data/full_repos/permissive/90852660.v\n 12,data/full_repos/permissive/90852660.sv\n obj_dir/12,data/full_repos/permissive/90852660\n obj_dir/12,data/full_repos/permissive/90852660.v\n obj_dir/12,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 12/alu.v\n%Error: Exiting due to 3 error(s)\n' | 309,386 | module | module alu(a,b,s,y);
input[3:0]a;
input[3:0]b;
input[2:0]s;
output[7:0]y;
reg[7:0]y;
always@(a,b,s)
begin
case(s)
3'b000:y=a+b;
3'b001:y=a-b;
3'b010:y=a&b;
3'b011:y=a|b;
3'b100:y=4'b1111^a;
3'b101:y=(4'b1111^a)+1'b1;
3'b110:y=a*b;
3'b111:
begin
y=a;
y=y>>1'b1;
end
endcase
end
endmodule | module alu(a,b,s,y); |
input[3:0]a;
input[3:0]b;
input[2:0]s;
output[7:0]y;
reg[7:0]y;
always@(a,b,s)
begin
case(s)
3'b000:y=a+b;
3'b001:y=a-b;
3'b010:y=a&b;
3'b011:y=a|b;
3'b100:y=4'b1111^a;
3'b101:y=(4'b1111^a)+1'b1;
3'b110:y=a*b;
3'b111:
begin
y=a;
y=y>>1'b1;
end
endcase
end
endmodule | 3 |
140,635 | data/full_repos/permissive/90852660/Exp 2/unidirectionalbus.v | 90,852,660 | unidirectionalbus.v | v | 8 | 94 | [] | [] | [] | [(1, 7)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/2,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/2,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/2,data/full_repos/permissive/90852660.sv\n 2,data/full_repos/permissive/90852660\n 2,data/full_repos/permissive/90852660.v\n 2,data/full_repos/permissive/90852660.sv\n obj_dir/2,data/full_repos/permissive/90852660\n obj_dir/2,data/full_repos/permissive/90852660.v\n obj_dir/2,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 2/unidirectionalbus.v\n%Error: Exiting due to 3 error(s)\n' | 309,390 | module | module unidirectionalbus(I, CNT, Z);
input [3:0] I;
input CNT;
output [3:0] Z;
tristate t1(I[0], CNT, Z[0]), a2(I[1], CNT, Z[1]), a3(I[2], CNT, Z[2]), a4(I[3], CNT, Z[3]);
endmodule | module unidirectionalbus(I, CNT, Z); |
input [3:0] I;
input CNT;
output [3:0] Z;
tristate t1(I[0], CNT, Z[0]), a2(I[1], CNT, Z[1]), a3(I[2], CNT, Z[2]), a4(I[3], CNT, Z[3]);
endmodule | 3 |
140,636 | data/full_repos/permissive/90852660/Exp 2/unidirectionalbus_tb.v | 90,852,660 | unidirectionalbus_tb.v | v | 12 | 29 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/2,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/2,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/2,data/full_repos/permissive/90852660.sv\n 2,data/full_repos/permissive/90852660\n 2,data/full_repos/permissive/90852660.v\n 2,data/full_repos/permissive/90852660.sv\n obj_dir/2,data/full_repos/permissive/90852660\n obj_dir/2,data/full_repos/permissive/90852660.v\n obj_dir/2,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 2/unidirectionalbus_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,391 | module | module unidirectionalbus_tb;
reg [3:0] I;
reg CNT;
wire [3:0]Z;
initial
begin
I=4; CNT=1; #100;
I=10; CNT=0; #100;
I=15; CNT=1; #100;
I=8; CNT=0; #100;
end
endmodule | module unidirectionalbus_tb; |
reg [3:0] I;
reg CNT;
wire [3:0]Z;
initial
begin
I=4; CNT=1; #100;
I=10; CNT=0; #100;
I=15; CNT=1; #100;
I=8; CNT=0; #100;
end
endmodule | 3 |
140,638 | data/full_repos/permissive/90852660/Exp 3/function1_tb.v | 90,852,660 | function1_tb.v | v | 12 | 24 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660.sv\n 3,data/full_repos/permissive/90852660\n 3,data/full_repos/permissive/90852660.v\n 3,data/full_repos/permissive/90852660.sv\n obj_dir/3,data/full_repos/permissive/90852660\n obj_dir/3,data/full_repos/permissive/90852660.v\n obj_dir/3,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 3/function1_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,393 | module | module function1_tb;
reg [3:0]inp;
wire f;
integer i;
function1 f1(inp, f);
initial begin
for(i=0; i<16; i=i+1)
begin
inp=i; #100;
end
end
endmodule | module function1_tb; |
reg [3:0]inp;
wire f;
integer i;
function1 f1(inp, f);
initial begin
for(i=0; i<16; i=i+1)
begin
inp=i; #100;
end
end
endmodule | 3 |
140,640 | data/full_repos/permissive/90852660/Exp 3/function2_tb.v | 90,852,660 | function2_tb.v | v | 12 | 23 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660.sv\n 3,data/full_repos/permissive/90852660\n 3,data/full_repos/permissive/90852660.v\n 3,data/full_repos/permissive/90852660.sv\n obj_dir/3,data/full_repos/permissive/90852660\n obj_dir/3,data/full_repos/permissive/90852660.v\n obj_dir/3,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 3/function2_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,395 | module | module function2_tb;
reg [2:0]inp;
wire [2:0]f;
integer i;
function2 f1(inp, f);
initial begin
for(i=0; i<8; i=i+1)
begin
inp=i; #100;
end
end
endmodule | module function2_tb; |
reg [2:0]inp;
wire [2:0]f;
integer i;
function2 f1(inp, f);
initial begin
for(i=0; i<8; i=i+1)
begin
inp=i; #100;
end
end
endmodule | 3 |
140,642 | data/full_repos/permissive/90852660/Exp 3/majority_tb.v | 90,852,660 | majority_tb.v | v | 12 | 23 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/3,data/full_repos/permissive/90852660.sv\n 3,data/full_repos/permissive/90852660\n 3,data/full_repos/permissive/90852660.v\n 3,data/full_repos/permissive/90852660.sv\n obj_dir/3,data/full_repos/permissive/90852660\n obj_dir/3,data/full_repos/permissive/90852660.v\n obj_dir/3,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 3/majority_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,397 | module | module majority_tb;
reg [2:0]A;
wire Z;
integer i;
majority m1(A, Z);
initial begin
for(i=0; i<8; i=i+1)
begin
A=i; #100;
end
end
endmodule | module majority_tb; |
reg [2:0]A;
wire Z;
integer i;
majority m1(A, Z);
initial begin
for(i=0; i<8; i=i+1)
begin
A=i; #100;
end
end
endmodule | 3 |
140,649 | data/full_repos/permissive/90852660/Exp 4/mux41_tb.v | 90,852,660 | mux41_tb.v | v | 19 | 29 | [] | [] | [] | [(1, 18)] | null | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/4,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/4,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/4,data/full_repos/permissive/90852660.sv\n 4,data/full_repos/permissive/90852660\n 4,data/full_repos/permissive/90852660.v\n 4,data/full_repos/permissive/90852660.sv\n obj_dir/4,data/full_repos/permissive/90852660\n obj_dir/4,data/full_repos/permissive/90852660.v\n obj_dir/4,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 4/mux41_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,403 | module | module mux41_tb();
reg [3:0]d;
reg [1:0]s;
wire q;
integer i;
mux41 m1(s,d,q);
initial
begin
for(i=0; i<16; i=i+1)
begin
d=i;
s=0; #100;
s=1; #100;
s=2; #100;
s=3; #100;
end
end
endmodule | module mux41_tb(); |
reg [3:0]d;
reg [1:0]s;
wire q;
integer i;
mux41 m1(s,d,q);
initial
begin
for(i=0; i<16; i=i+1)
begin
d=i;
s=0; #100;
s=1; #100;
s=2; #100;
s=3; #100;
end
end
endmodule | 3 |
140,651 | data/full_repos/permissive/90852660/Exp 4/mux81_tb.v | 90,852,660 | mux81_tb.v | v | 23 | 29 | [] | [] | [] | [(1, 22)] | null | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/4,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/4,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/4,data/full_repos/permissive/90852660.sv\n 4,data/full_repos/permissive/90852660\n 4,data/full_repos/permissive/90852660.v\n 4,data/full_repos/permissive/90852660.sv\n obj_dir/4,data/full_repos/permissive/90852660\n obj_dir/4,data/full_repos/permissive/90852660.v\n obj_dir/4,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 4/mux81_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,405 | module | module mux81_tb();
reg [7:0]d;
reg [2:0]s;
wire q;
integer i;
mux81 m1(s,d,q);
initial
begin
for(i=0; i<64; i=i+4)
begin
d=i;
s=0; #100;
s=1; #100;
s=2; #100;
s=3; #100;
s=4; #100;
s=5; #100;
s=6; #100;
s=7; #100;
end
end
endmodule | module mux81_tb(); |
reg [7:0]d;
reg [2:0]s;
wire q;
integer i;
mux81 m1(s,d,q);
initial
begin
for(i=0; i<64; i=i+4)
begin
d=i;
s=0; #100;
s=1; #100;
s=2; #100;
s=3; #100;
s=4; #100;
s=5; #100;
s=6; #100;
s=7; #100;
end
end
endmodule | 3 |
140,652 | data/full_repos/permissive/90852660/Exp 5/function.v | 90,852,660 | function.v | v | 23 | 45 | [] | [] | [] | null | line:16: before: "function" | null | 1: b'%Error: Cannot find file containing module: 5,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.sv\n 5,data/full_repos/permissive/90852660\n 5,data/full_repos/permissive/90852660.v\n 5,data/full_repos/permissive/90852660.sv\n obj_dir/5,data/full_repos/permissive/90852660\n obj_dir/5,data/full_repos/permissive/90852660.v\n obj_dir/5,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 5/function.v\n%Error: Exiting due to 3 error(s)\n' | 309,406 | module | module nand3gate(A,B,C,D);
input A, B, C;
output D;
assign D = !(A&B&C);
endmodule | module nand3gate(A,B,C,D); |
input A, B, C;
output D;
assign D = !(A&B&C);
endmodule | 3 |
140,653 | data/full_repos/permissive/90852660/Exp 5/function.v | 90,852,660 | function.v | v | 23 | 45 | [] | [] | [] | null | line:16: before: "function" | null | 1: b'%Error: Cannot find file containing module: 5,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.sv\n 5,data/full_repos/permissive/90852660\n 5,data/full_repos/permissive/90852660.v\n 5,data/full_repos/permissive/90852660.sv\n obj_dir/5,data/full_repos/permissive/90852660\n obj_dir/5,data/full_repos/permissive/90852660.v\n obj_dir/5,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 5/function.v\n%Error: Exiting due to 3 error(s)\n' | 309,406 | module | module function(a,f1,f2,f3);
input [2:0]a;
output f1,f2,f3;
wire [7:0]c;
decoder38 d1(a,c);
nand3gate n1(c[2], c[4], c[7], f1);
nand2gate n2(c[0], c[3], f2), n3(f1,f2,f3);
endmodule | module function(a,f1,f2,f3); |
input [2:0]a;
output f1,f2,f3;
wire [7:0]c;
decoder38 d1(a,c);
nand3gate n1(c[2], c[4], c[7], f1);
nand2gate n2(c[0], c[3], f2), n3(f1,f2,f3);
endmodule | 3 |
140,654 | data/full_repos/permissive/90852660/Exp 5/function_tb.v | 90,852,660 | function_tb.v | v | 13 | 26 | [] | [] | [] | null | line:5: before: "(" | null | 1: b'%Error: Cannot find file containing module: 5,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.sv\n 5,data/full_repos/permissive/90852660\n 5,data/full_repos/permissive/90852660.v\n 5,data/full_repos/permissive/90852660.sv\n obj_dir/5,data/full_repos/permissive/90852660\n obj_dir/5,data/full_repos/permissive/90852660.v\n obj_dir/5,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 5/function_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,407 | module | module function_tb;
reg [2:0]a;
wire f1,f2,f3;
integer i;
function f1(a,f1,f2,f3);
initial begin
for(i=0; i<8; i=i+1)
begin
a=i; #100;
end
end
endmodule | module function_tb; |
reg [2:0]a;
wire f1,f2,f3;
integer i;
function f1(a,f1,f2,f3);
initial begin
for(i=0; i<8; i=i+1)
begin
a=i; #100;
end
end
endmodule | 3 |
140,656 | data/full_repos/permissive/90852660/Exp 5/mag_comp_tb.v | 90,852,660 | mag_comp_tb.v | v | 19 | 33 | [] | [] | [] | [(1, 18)] | null | null | 1: b'%Error: Cannot find file containing module: 5,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/5,data/full_repos/permissive/90852660.sv\n 5,data/full_repos/permissive/90852660\n 5,data/full_repos/permissive/90852660.v\n 5,data/full_repos/permissive/90852660.sv\n obj_dir/5,data/full_repos/permissive/90852660\n obj_dir/5,data/full_repos/permissive/90852660.v\n obj_dir/5,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 5/mag_comp_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,409 | module | module mag_comp_tb();
reg [3:0]a,b;
wire gt,eq,lt;
integer i,j;
mag_comp m1(a,b,gt,eq,lt);
initial
begin
for(i=0; i<16; i=i+1)
begin
for(j=0; j<16; j=j+1)
begin
a=i;
b=j;
#100;
end
end
end
endmodule | module mag_comp_tb(); |
reg [3:0]a,b;
wire gt,eq,lt;
integer i,j;
mag_comp m1(a,b,gt,eq,lt);
initial
begin
for(i=0; i<16; i=i+1)
begin
for(j=0; j<16; j=j+1)
begin
a=i;
b=j;
#100;
end
end
end
endmodule | 3 |
140,659 | data/full_repos/permissive/90852660/Exp 6/bcd2gray.v | 90,852,660 | bcd2gray.v | v | 11 | 31 | [] | [] | [] | [(1, 10)] | null | null | 1: b'%Error: Cannot find file containing module: 6,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.sv\n 6,data/full_repos/permissive/90852660\n 6,data/full_repos/permissive/90852660.v\n 6,data/full_repos/permissive/90852660.sv\n obj_dir/6,data/full_repos/permissive/90852660\n obj_dir/6,data/full_repos/permissive/90852660.v\n obj_dir/6,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 6/bcd2gray.v\n%Error: Exiting due to 3 error(s)\n' | 309,412 | module | module bcd2gray (a,b);
input [4:0]a;
output [3:0]b;
wire [3:0]p;
assign p= (a>9)?(a-6):a;
assign b[3] = p[3];
assign b[2] = p[3]^p[2];
assign b[1] = p[2]^p[1];
assign b[0] = p[1]^p[0];
endmodule | module bcd2gray (a,b); |
input [4:0]a;
output [3:0]b;
wire [3:0]p;
assign p= (a>9)?(a-6):a;
assign b[3] = p[3];
assign b[2] = p[3]^p[2];
assign b[1] = p[2]^p[1];
assign b[0] = p[1]^p[0];
endmodule | 3 |
140,662 | data/full_repos/permissive/90852660/Exp 6/bin2bcd_tb.v | 90,852,660 | bin2bcd_tb.v | v | 15 | 29 | [] | [] | [] | [(1, 14)] | null | null | 1: b'%Error: Cannot find file containing module: 6,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.sv\n 6,data/full_repos/permissive/90852660\n 6,data/full_repos/permissive/90852660.v\n 6,data/full_repos/permissive/90852660.sv\n obj_dir/6,data/full_repos/permissive/90852660\n obj_dir/6,data/full_repos/permissive/90852660.v\n obj_dir/6,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 6/bin2bcd_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,415 | module | module bin2bcd_tb();
reg[3:0]bin;
wire[7:0]bcd;
integer i;
bin2bcd bin1(bin,bcd);
initial
begin
for(i=0; i<16; i=i+1)
begin
bin=i;
#100;
end
end
endmodule | module bin2bcd_tb(); |
reg[3:0]bin;
wire[7:0]bcd;
integer i;
bin2bcd bin1(bin,bcd);
initial
begin
for(i=0; i<16; i=i+1)
begin
bin=i;
#100;
end
end
endmodule | 3 |
140,663 | data/full_repos/permissive/90852660/Exp 6/bin2gray_tb.v | 90,852,660 | bin2gray_tb.v | v | 15 | 29 | [] | [] | [] | [(1, 14)] | null | null | 1: b'%Error: Cannot find file containing module: 6,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.sv\n 6,data/full_repos/permissive/90852660\n 6,data/full_repos/permissive/90852660.v\n 6,data/full_repos/permissive/90852660.sv\n obj_dir/6,data/full_repos/permissive/90852660\n obj_dir/6,data/full_repos/permissive/90852660.v\n obj_dir/6,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 6/bin2gray_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,417 | module | module bin2gray_tb();
reg[3:0]b;
wire[3:0]g;
integer i;
bin2gray b1(b,g);
initial
begin
for(i=0; i<16; i=i+1)
begin
b=i;
#100;
end
end
endmodule | module bin2gray_tb(); |
reg[3:0]b;
wire[3:0]g;
integer i;
bin2gray b1(b,g);
initial
begin
for(i=0; i<16; i=i+1)
begin
b=i;
#100;
end
end
endmodule | 3 |
140,667 | data/full_repos/permissive/90852660/Exp 6/gray2bin.v | 90,852,660 | gray2bin.v | v | 7 | 50 | [] | [] | [] | [(1, 6)] | null | null | 1: b'%Error: Cannot find file containing module: 6,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.sv\n 6,data/full_repos/permissive/90852660\n 6,data/full_repos/permissive/90852660.v\n 6,data/full_repos/permissive/90852660.sv\n obj_dir/6,data/full_repos/permissive/90852660\n obj_dir/6,data/full_repos/permissive/90852660.v\n obj_dir/6,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 6/gray2bin.v\n%Error: Exiting due to 3 error(s)\n' | 309,422 | module | module gray2bin_4(input[3:0]g, output[3:0]b);
assign b[3] = g[3];
assign b[2] = b[3]^g[2];
assign b[1] = b[2]^g[1];
assign b[0] = b[1]^g[0];
endmodule | module gray2bin_4(input[3:0]g, output[3:0]b); |
assign b[3] = g[3];
assign b[2] = b[3]^g[2];
assign b[1] = b[2]^g[1];
assign b[0] = b[1]^g[0];
endmodule | 3 |
140,668 | data/full_repos/permissive/90852660/Exp 6/gray2bin_tb.v | 90,852,660 | gray2bin_tb.v | v | 15 | 29 | [] | [] | [] | [(1, 14)] | null | null | 1: b'%Error: Cannot find file containing module: 6,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/6,data/full_repos/permissive/90852660.sv\n 6,data/full_repos/permissive/90852660\n 6,data/full_repos/permissive/90852660.v\n 6,data/full_repos/permissive/90852660.sv\n obj_dir/6,data/full_repos/permissive/90852660\n obj_dir/6,data/full_repos/permissive/90852660.v\n obj_dir/6,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 6/gray2bin_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,423 | module | module gray2bin_tb();
reg[3:0]g;
wire[3:0]b;
integer i;
gray2bin g(g,b);
initial
begin
for(i=0; i<16; i=i+1)
begin
g=i;
#100;
end
end
endmodule | module gray2bin_tb(); |
reg[3:0]g;
wire[3:0]b;
integer i;
gray2bin g(g,b);
initial
begin
for(i=0; i<16; i=i+1)
begin
g=i;
#100;
end
end
endmodule | 3 |
140,669 | data/full_repos/permissive/90852660/Exp 7/add_sub.v | 90,852,660 | add_sub.v | v | 8 | 37 | [] | [] | [] | [(1, 6)] | null | null | 1: b'%Error: Cannot find file containing module: 7,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.sv\n 7,data/full_repos/permissive/90852660\n 7,data/full_repos/permissive/90852660.v\n 7,data/full_repos/permissive/90852660.sv\n obj_dir/7,data/full_repos/permissive/90852660\n obj_dir/7,data/full_repos/permissive/90852660.v\n obj_dir/7,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 7/add_sub.v\n%Error: Exiting due to 3 error(s)\n' | 309,424 | module | module add_sub (a,b,m,s);
input [3:0] a,b;
input m;
output [4:0]s;
assign s=(m==0)?(a+b):(a-b);
endmodule | module add_sub (a,b,m,s); |
input [3:0] a,b;
input m;
output [4:0]s;
assign s=(m==0)?(a+b):(a-b);
endmodule | 3 |
140,675 | data/full_repos/permissive/90852660/Exp 7/half_adder.v | 90,852,660 | half_adder.v | v | 6 | 55 | [] | [] | [] | [(1, 4)] | null | null | 1: b'%Error: Cannot find file containing module: 7,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.sv\n 7,data/full_repos/permissive/90852660\n 7,data/full_repos/permissive/90852660.v\n 7,data/full_repos/permissive/90852660.sv\n obj_dir/7,data/full_repos/permissive/90852660\n obj_dir/7,data/full_repos/permissive/90852660.v\n obj_dir/7,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 7/half_adder.v\n%Error: Exiting due to 3 error(s)\n' | 309,430 | module | module half_adder(input a,input b,output S,output Co);
assign S=a^b;
assign Co=a&b;
endmodule | module half_adder(input a,input b,output S,output Co); |
assign S=a^b;
assign Co=a&b;
endmodule | 3 |
140,677 | data/full_repos/permissive/90852660/Exp 7/increment.v | 90,852,660 | increment.v | v | 7 | 110 | [] | [] | [] | [(1, 7)] | null | null | 1: b'%Error: Cannot find file containing module: 7,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.sv\n 7,data/full_repos/permissive/90852660\n 7,data/full_repos/permissive/90852660.v\n 7,data/full_repos/permissive/90852660.sv\n obj_dir/7,data/full_repos/permissive/90852660\n obj_dir/7,data/full_repos/permissive/90852660.v\n obj_dir/7,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 7/increment.v\n%Error: Exiting due to 3 error(s)\n' | 309,432 | module | module increment(a,s,c);
input [3:0]a;
output [3:0]s;
output c;
wire c1,c2,c3;
half_adder ha1(a[0], 1, s[0], c1), ha2(a[1], c1, s[1], c2), ha3(a[2], c2, s[2], c3), ha4(a[3], c3, s[3], c);
endmodule | module increment(a,s,c); |
input [3:0]a;
output [3:0]s;
output c;
wire c1,c2,c3;
half_adder ha1(a[0], 1, s[0], c1), ha2(a[1], c1, s[1], c2), ha3(a[2], c2, s[2], c3), ha4(a[3], c3, s[3], c);
endmodule | 3 |
140,678 | data/full_repos/permissive/90852660/Exp 7/increment_tb.v | 90,852,660 | increment_tb.v | v | 14 | 26 | [] | [] | [] | [(1, 13)] | null | null | 1: b'%Error: Cannot find file containing module: 7,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/7,data/full_repos/permissive/90852660.sv\n 7,data/full_repos/permissive/90852660\n 7,data/full_repos/permissive/90852660.v\n 7,data/full_repos/permissive/90852660.sv\n obj_dir/7,data/full_repos/permissive/90852660\n obj_dir/7,data/full_repos/permissive/90852660.v\n obj_dir/7,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 7/increment_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,433 | module | module increment_tb();
reg [3:0]a;
wire [3:0]s;
wire c;
increment i1(a,s,c);
integer i;
initial begin
for(i=0; i<8; i=i+1)
begin
a=i; #100;
end
end
endmodule | module increment_tb(); |
reg [3:0]a;
wire [3:0]s;
wire c;
increment i1(a,s,c);
integer i;
initial begin
for(i=0; i<8; i=i+1)
begin
a=i; #100;
end
end
endmodule | 3 |
140,680 | data/full_repos/permissive/90852660/Exp 8/d_flip_flop_tb.v | 90,852,660 | d_flip_flop_tb.v | v | 10 | 32 | [] | [] | [] | null | line:9: before: "end" | null | 1: b'%Error: Cannot find file containing module: 8,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.sv\n 8,data/full_repos/permissive/90852660\n 8,data/full_repos/permissive/90852660.v\n 8,data/full_repos/permissive/90852660.sv\n obj_dir/8,data/full_repos/permissive/90852660\n obj_dir/8,data/full_repos/permissive/90852660.v\n obj_dir/8,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 8/d_flip_flop_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,435 | module | module d_flip_flop_tb;
reg d, clk;
wire q, q1;
d_flip_flop d1(d, clk, q, q1);
always #100 clk=~clk;
initial begin
d=0; #100;
d=1; #100
end
endmodule | module d_flip_flop_tb; |
reg d, clk;
wire q, q1;
d_flip_flop d1(d, clk, q, q1);
always #100 clk=~clk;
initial begin
d=0; #100;
d=1; #100
end
endmodule | 3 |
140,681 | data/full_repos/permissive/90852660/Exp 8/jk_flip_flop.v | 90,852,660 | jk_flip_flop.v | v | 20 | 51 | [] | [] | [] | null | line:10: before: "j" | null | 1: b'%Error: Cannot find file containing module: 8,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.sv\n 8,data/full_repos/permissive/90852660\n 8,data/full_repos/permissive/90852660.v\n 8,data/full_repos/permissive/90852660.sv\n obj_dir/8,data/full_repos/permissive/90852660\n obj_dir/8,data/full_repos/permissive/90852660.v\n obj_dir/8,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 8/jk_flip_flop.v\n%Error: Exiting due to 3 error(s)\n' | 309,436 | module | module jk_flip_flop(j,k,clk,q,q1);
input j,k,clk;
output q,q1;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk, j,k,q,q1)
begin
case({j,k})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=q1; q1=q; end
endcase
end
endmodule | module jk_flip_flop(j,k,clk,q,q1); |
input j,k,clk;
output q,q1;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk, j,k,q,q1)
begin
case({j,k})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=q1; q1=q; end
endcase
end
endmodule | 3 |
140,682 | data/full_repos/permissive/90852660/Exp 8/jk_flip_flop_tb.v | 90,852,660 | jk_flip_flop_tb.v | v | 12 | 37 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: 8,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.sv\n 8,data/full_repos/permissive/90852660\n 8,data/full_repos/permissive/90852660.v\n 8,data/full_repos/permissive/90852660.sv\n obj_dir/8,data/full_repos/permissive/90852660\n obj_dir/8,data/full_repos/permissive/90852660.v\n obj_dir/8,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 8/jk_flip_flop_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,437 | module | module jk_flip_flop_tb;
reg j,k, clk;
wire q, q1;
jk_flip_flop jk1(j, k, clk, q, q1);
always #100 clk=~clk;
initial begin
j=0; k=0; #100;
j=0; k=1; #100;
j=1; k=0; #100;
j=1; k=1; #100;
end
endmodule | module jk_flip_flop_tb; |
reg j,k, clk;
wire q, q1;
jk_flip_flop jk1(j, k, clk, q, q1);
always #100 clk=~clk;
initial begin
j=0; k=0; #100;
j=0; k=1; #100;
j=1; k=0; #100;
j=1; k=1; #100;
end
endmodule | 3 |
140,683 | data/full_repos/permissive/90852660/Exp 8/sr_flip_flop_tb.v | 90,852,660 | sr_flip_flop_tb.v | v | 12 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: 8,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/8,data/full_repos/permissive/90852660.sv\n 8,data/full_repos/permissive/90852660\n 8,data/full_repos/permissive/90852660.v\n 8,data/full_repos/permissive/90852660.sv\n obj_dir/8,data/full_repos/permissive/90852660\n obj_dir/8,data/full_repos/permissive/90852660.v\n obj_dir/8,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 8/sr_flip_flop_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,439 | module | module sr_flip_flop_tb;
reg s,r, clk;
wire q, q1;
sr_flip_flop sr1(s, r, clk, q, q1);
always #100 clk=~clk;
initial begin
s=0; r=0; #100;
s=0; r=1; #100;
s=1; r=0; #100;
s=1; r=1; #100;
end
endmodule | module sr_flip_flop_tb; |
reg s,r, clk;
wire q, q1;
sr_flip_flop sr1(s, r, clk, q, q1);
always #100 clk=~clk;
initial begin
s=0; r=0; #100;
s=0; r=1; #100;
s=1; r=0; #100;
s=1; r=1; #100;
end
endmodule | 3 |
140,686 | data/full_repos/permissive/90852660/Exp 9/johnson_counter.v | 90,852,660 | johnson_counter.v | v | 20 | 61 | [] | [] | [] | [(1, 19)] | null | null | 1: b'%Error: Cannot find file containing module: 9,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.sv\n 9,data/full_repos/permissive/90852660\n 9,data/full_repos/permissive/90852660.v\n 9,data/full_repos/permissive/90852660.sv\n obj_dir/9,data/full_repos/permissive/90852660\n obj_dir/9,data/full_repos/permissive/90852660.v\n obj_dir/9,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 9/johnson_counter.v\n%Error: Exiting due to 3 error(s)\n' | 309,442 | module | module johnson_counter(Clock, Reset, Count_out);
input Clock;
input Reset;
output [3:0] Count_out;
reg [3:0] Count_temp;
always @(posedge Clock,posedge Reset )
begin
if(Reset == 1'b1) begin
Count_temp = 4'b0000;
end
else if(Clock == 1'b1) begin
Count_temp = {Count_temp[2:0],~Count_temp[3]};
end
end
assign Count_out = Count_temp;
endmodule | module johnson_counter(Clock, Reset, Count_out); |
input Clock;
input Reset;
output [3:0] Count_out;
reg [3:0] Count_temp;
always @(posedge Clock,posedge Reset )
begin
if(Reset == 1'b1) begin
Count_temp = 4'b0000;
end
else if(Clock == 1'b1) begin
Count_temp = {Count_temp[2:0],~Count_temp[3]};
end
end
assign Count_out = Count_temp;
endmodule | 3 |
140,687 | data/full_repos/permissive/90852660/Exp 9/johnson_counter_tb.v | 90,852,660 | johnson_counter_tb.v | v | 15 | 48 | [] | [] | [] | [(1, 15)] | null | null | 1: b'%Error: Cannot find file containing module: 9,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.sv\n 9,data/full_repos/permissive/90852660\n 9,data/full_repos/permissive/90852660.v\n 9,data/full_repos/permissive/90852660.sv\n obj_dir/9,data/full_repos/permissive/90852660\n obj_dir/9,data/full_repos/permissive/90852660.v\n obj_dir/9,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 9/johnson_counter_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,443 | module | module johnson_counter_tb;
reg Clock;
reg Reset;
wire [3:0] Count_out;
johnson_counter jc1s(Clock, Reset, Count_out);
initial Clock = 0;
always #10 Clock = ~Clock;
initial begin
Reset = 1;
#50;
Reset = 0;
end
endmodule | module johnson_counter_tb; |
reg Clock;
reg Reset;
wire [3:0] Count_out;
johnson_counter jc1s(Clock, Reset, Count_out);
initial Clock = 0;
always #10 Clock = ~Clock;
initial begin
Reset = 1;
#50;
Reset = 0;
end
endmodule | 3 |
140,688 | data/full_repos/permissive/90852660/Exp 9/mod10_counter.v | 90,852,660 | mod10_counter.v | v | 18 | 35 | [] | [] | [] | [(1, 17)] | null | null | 1: b'%Error: Cannot find file containing module: 9,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.sv\n 9,data/full_repos/permissive/90852660\n 9,data/full_repos/permissive/90852660.v\n 9,data/full_repos/permissive/90852660.sv\n obj_dir/9,data/full_repos/permissive/90852660\n obj_dir/9,data/full_repos/permissive/90852660.v\n obj_dir/9,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 9/mod10_counter.v\n%Error: Exiting due to 3 error(s)\n' | 309,444 | module | module mod10_counter(clk, rst, q);
input clk, rst;
output [3:0]q;
reg [3:0]q;
initial begin
q=0;
end
always @ (posedge clk)
begin
if (rst==0)
q=0;
else if(rst==1 && q==9)
q=0;
else
q=q+1;
end
endmodule | module mod10_counter(clk, rst, q); |
input clk, rst;
output [3:0]q;
reg [3:0]q;
initial begin
q=0;
end
always @ (posedge clk)
begin
if (rst==0)
q=0;
else if(rst==1 && q==9)
q=0;
else
q=q+1;
end
endmodule | 3 |
140,689 | data/full_repos/permissive/90852660/Exp 9/mod10_counter_tb.v | 90,852,660 | mod10_counter_tb.v | v | 12 | 32 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: 9,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.sv\n 9,data/full_repos/permissive/90852660\n 9,data/full_repos/permissive/90852660.v\n 9,data/full_repos/permissive/90852660.sv\n obj_dir/9,data/full_repos/permissive/90852660\n obj_dir/9,data/full_repos/permissive/90852660.v\n obj_dir/9,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 9/mod10_counter_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,445 | module | module mod10_counter_tb;
reg clk, rst;
wire [3:0] q;
initial begin
clk=1;
end
mod10_counter mc(clk, rst, q);
always #100 clk=~clk;
initial begin
rst=1;#100;
end
endmodule | module mod10_counter_tb; |
reg clk, rst;
wire [3:0] q;
initial begin
clk=1;
end
mod10_counter mc(clk, rst, q);
always #100 clk=~clk;
initial begin
rst=1;#100;
end
endmodule | 3 |
140,690 | data/full_repos/permissive/90852660/Exp 9/ring_counter.v | 90,852,660 | ring_counter.v | v | 13 | 32 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: 9,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.sv\n 9,data/full_repos/permissive/90852660\n 9,data/full_repos/permissive/90852660.v\n 9,data/full_repos/permissive/90852660.sv\n obj_dir/9,data/full_repos/permissive/90852660\n obj_dir/9,data/full_repos/permissive/90852660.v\n obj_dir/9,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 9/ring_counter.v\n%Error: Exiting due to 3 error(s)\n' | 309,446 | module | module ring_counter(clk,rst,q);
input clk,rst;
output [3:0]q;
reg [3:0]q;
always@(posedge clk)
begin
if(rst==1)
q=1;
else
q={q[2:0],q[3]};
end
endmodule | module ring_counter(clk,rst,q); |
input clk,rst;
output [3:0]q;
reg [3:0]q;
always@(posedge clk)
begin
if(rst==1)
q=1;
else
q={q[2:0],q[3]};
end
endmodule | 3 |
140,693 | data/full_repos/permissive/90852660/Exp 9/up_down_tb.v | 90,852,660 | up_down_tb.v | v | 19 | 36 | [] | [] | [] | [(1, 19)] | null | null | 1: b'%Error: Cannot find file containing module: 9,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/9,data/full_repos/permissive/90852660.sv\n 9,data/full_repos/permissive/90852660\n 9,data/full_repos/permissive/90852660.v\n 9,data/full_repos/permissive/90852660.sv\n obj_dir/9,data/full_repos/permissive/90852660\n obj_dir/9,data/full_repos/permissive/90852660.v\n obj_dir/9,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 9/up_down_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,449 | module | module up_down_tb;
reg clk,reset,up_down;
wire [3:0]q;
initial begin
clk=1;
end
up_down ud1(clk,reset,up_down, q);
always #100 clk=~clk;
initial begin
reset=1;
up_down=1; #100;
up_down=1; #100;
up_down=1; #100;
up_down=1; #100;
up_down=0; #100;
up_down=0; #100;
reset=0; up_down=1; #100;
end
endmodule | module up_down_tb; |
reg clk,reset,up_down;
wire [3:0]q;
initial begin
clk=1;
end
up_down ud1(clk,reset,up_down, q);
always #100 clk=~clk;
initial begin
reset=1;
up_down=1; #100;
up_down=1; #100;
up_down=1; #100;
up_down=1; #100;
up_down=0; #100;
up_down=0; #100;
reset=0; up_down=1; #100;
end
endmodule | 3 |
140,694 | data/full_repos/permissive/90862816/Project/DP_RAM/design/dp_ram.v | 90,862,816 | dp_ram.v | v | 114 | 134 | [] | [] | [] | [(1, 114)] | null | data/verilator_xmls/fb13bb43-97a5-4b31-9080-5c5c63889bd3.xml | null | 309,450 | module | module dp_ram(
input wire w_clk,
input wire r_clk,
input wire w_en,
input wire [7:0] w_data,
output reg [7:0] r_data,
input wire [3:0] w_addr,
input wire [3:0] r_addr
);
reg [7:0] en;
reg [7:0] r_en;
reg [63:0] data;
reg [63:0] data1;
always @(w_addr[2:0])
begin
case(w_addr[2:0])
3'b000: begin
en[0] = 1'b1; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b001: begin
en[0] = 1'b0; en[1] = 1'b1; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b010: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b1; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b011: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b1; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b100: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b1; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b101: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b1; en[6] = 1'b0; en[7] = 1'b0;
end
3'b110: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b1; en[7] = 1'b0;
end
3'b111: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b1;
end
endcase
end
generate
genvar i;
for(i=0;i<8;i=i+1)
begin:write_data
always @(posedge w_clk)
if(w_en)
begin
if(en[i])
data[(8*i+7):(8*i)] <= w_data[7:0];
else
data[(8*i+7):(8*i)] <= data[(8*i+7):(8*i)];
end
else
data <= data;
end
endgenerate
always @(posedge r_clk)
begin
data1 <= data;
end
always @(r_addr[2:0])
begin
case(r_addr[2:0])
3'b000: begin
r_en[0] = 1'b1; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b001: begin
r_en[0] = 1'b0; r_en[1] = 1'b1; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b010: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b1; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b011: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b1; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b100: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b1; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b101: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b1; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b110: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b1; r_en[7] = 1'b0;
end
3'b111: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b1;
end
endcase
end
always @(posedge r_clk)
begin
case(r_en)
8'b0000_0001:r_data <= data1[7:0];
8'b0000_0010:r_data <= data1[15:8];
8'b0000_0100:r_data <= data1[23:16];
8'b0000_1000:r_data <= data1[31:24];
8'b0001_0000:r_data <= data1[39:32];
8'b0010_0000:r_data <= data1[47:40];
8'b0100_0000:r_data <= data1[55:48];
8'b1000_0000:r_data <= data1[63:56];
default:r_data <= 8'b0000_0000;
endcase
end
endmodule | module dp_ram(
input wire w_clk,
input wire r_clk,
input wire w_en,
input wire [7:0] w_data,
output reg [7:0] r_data,
input wire [3:0] w_addr,
input wire [3:0] r_addr
); |
reg [7:0] en;
reg [7:0] r_en;
reg [63:0] data;
reg [63:0] data1;
always @(w_addr[2:0])
begin
case(w_addr[2:0])
3'b000: begin
en[0] = 1'b1; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b001: begin
en[0] = 1'b0; en[1] = 1'b1; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b010: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b1; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b011: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b1; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b100: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b1; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b101: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b1; en[6] = 1'b0; en[7] = 1'b0;
end
3'b110: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b1; en[7] = 1'b0;
end
3'b111: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b1;
end
endcase
end
generate
genvar i;
for(i=0;i<8;i=i+1)
begin:write_data
always @(posedge w_clk)
if(w_en)
begin
if(en[i])
data[(8*i+7):(8*i)] <= w_data[7:0];
else
data[(8*i+7):(8*i)] <= data[(8*i+7):(8*i)];
end
else
data <= data;
end
endgenerate
always @(posedge r_clk)
begin
data1 <= data;
end
always @(r_addr[2:0])
begin
case(r_addr[2:0])
3'b000: begin
r_en[0] = 1'b1; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b001: begin
r_en[0] = 1'b0; r_en[1] = 1'b1; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b010: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b1; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b011: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b1; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b100: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b1; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b101: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b1; r_en[6] = 1'b0; r_en[7] = 1'b0;
end
3'b110: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b1; r_en[7] = 1'b0;
end
3'b111: begin
r_en[0] = 1'b0; r_en[1] = 1'b0; r_en[2] = 1'b0; r_en[3] = 1'b0; r_en[4] = 1'b0; r_en[5] = 1'b0; r_en[6] = 1'b0; r_en[7] = 1'b1;
end
endcase
end
always @(posedge r_clk)
begin
case(r_en)
8'b0000_0001:r_data <= data1[7:0];
8'b0000_0010:r_data <= data1[15:8];
8'b0000_0100:r_data <= data1[23:16];
8'b0000_1000:r_data <= data1[31:24];
8'b0001_0000:r_data <= data1[39:32];
8'b0010_0000:r_data <= data1[47:40];
8'b0100_0000:r_data <= data1[55:48];
8'b1000_0000:r_data <= data1[63:56];
default:r_data <= 8'b0000_0000;
endcase
end
endmodule | 0 |
140,695 | data/full_repos/permissive/90862816/Project/DP_RAM/design/r_ctrl.v | 90,862,816 | r_ctrl.v | v | 52 | 77 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb6 in position 47: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90862816/Project/DP_RAM/design/r_ctrl.v:31: Operator NOT expects 4 bits on the LHS, but LHS\'s VARREF \'r_empty\' generates 1 bits.\n : ... In instance r_ctrl\nassign addr_wire = addr + ((~r_empty)&r_en);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/DP_RAM/design/r_ctrl.v:31: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'r_en\' generates 1 bits.\n : ... In instance r_ctrl\nassign addr_wire = addr + ((~r_empty)&r_en);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,453 | module | module r_ctrl(
input wire r_clk,
input wire rst_n,
input wire r_en,
input wire [3:0] w_gaddr,
output reg r_empty,
output wire [3:0] r_addr,
output wire [3:0] r_gaddr
);
reg [3:0] addr;
reg [3:0] gaddr;
wire [3:0] addr_wire;
wire [3:0] gaddr_wire;
reg [3:0] w_gaddr_d1,w_gaddr_d2;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
{w_gaddr_d2,w_gaddr_d1} <= 8'b0;
else
{w_gaddr_d2,w_gaddr_d1} <= {w_gaddr_d1,w_gaddr};
assign r_addr = addr;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'd0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~r_empty)&r_en);
assign r_gaddr = gaddr;
assign gaddr_wire = (addr_wire>>1)^addr_wire;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
gaddr <= 4'd0;
else
gaddr <= gaddr_wire;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
r_empty <= 1'b0;
else if (gaddr_wire == w_gaddr_d2)
r_empty <= 1'b1;
else
r_empty <= 1'b0;
endmodule | module r_ctrl(
input wire r_clk,
input wire rst_n,
input wire r_en,
input wire [3:0] w_gaddr,
output reg r_empty,
output wire [3:0] r_addr,
output wire [3:0] r_gaddr
); |
reg [3:0] addr;
reg [3:0] gaddr;
wire [3:0] addr_wire;
wire [3:0] gaddr_wire;
reg [3:0] w_gaddr_d1,w_gaddr_d2;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
{w_gaddr_d2,w_gaddr_d1} <= 8'b0;
else
{w_gaddr_d2,w_gaddr_d1} <= {w_gaddr_d1,w_gaddr};
assign r_addr = addr;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'd0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~r_empty)&r_en);
assign r_gaddr = gaddr;
assign gaddr_wire = (addr_wire>>1)^addr_wire;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
gaddr <= 4'd0;
else
gaddr <= gaddr_wire;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
r_empty <= 1'b0;
else if (gaddr_wire == w_gaddr_d2)
r_empty <= 1'b1;
else
r_empty <= 1'b0;
endmodule | 0 |
140,696 | data/full_repos/permissive/90862816/Project/DP_RAM/design/w_ctrl.v | 90,862,816 | w_ctrl.v | v | 50 | 71 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 53: invalid continuation byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90862816/Project/DP_RAM/design/w_ctrl.v:31: Operator NOT expects 4 bits on the LHS, but LHS\'s VARREF \'w_full\' generates 1 bits.\n : ... In instance w_ctrl\nassign addr_wire = addr + ((~w_full)&w_en);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/DP_RAM/design/w_ctrl.v:31: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'w_en\' generates 1 bits.\n : ... In instance w_ctrl\nassign addr_wire = addr + ((~w_full)&w_en);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,454 | module | module w_ctrl(
input wire w_clk,
input wire rst_n,
input wire w_en,
input wire [3:0] r_gaddr,
output reg w_full,
output wire [3:0] w_addr,
output wire [3:0] w_gaddr
);
reg [3:0] addr;
reg [3:0] gaddr;
wire [3:0] addr_wire;
wire [3:0] gaddr_wire;
reg [3:0] r_gaddr_d1,r_gaddr_d2;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
{r_gaddr_d2,r_gaddr_d1} <= 8'b0;
else
{r_gaddr_d2,r_gaddr_d1} <= {r_gaddr_d1,r_gaddr};
assign w_gaddr = gaddr;
assign w_addr = addr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'b0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~w_full)&w_en);
assign gaddr_wire = (addr_wire>>1)^addr_wire;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
gaddr <= 4'b0;
else
gaddr <= gaddr_wire;
assign w_gaddr = gaddr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
w_full <= 1'b0;
else if({~gaddr_wire[3:2],gaddr_wire[1:0]}==r_gaddr_d2)
w_full <= 1'b1;
else
w_full <= 1'b0;
endmodule | module w_ctrl(
input wire w_clk,
input wire rst_n,
input wire w_en,
input wire [3:0] r_gaddr,
output reg w_full,
output wire [3:0] w_addr,
output wire [3:0] w_gaddr
); |
reg [3:0] addr;
reg [3:0] gaddr;
wire [3:0] addr_wire;
wire [3:0] gaddr_wire;
reg [3:0] r_gaddr_d1,r_gaddr_d2;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
{r_gaddr_d2,r_gaddr_d1} <= 8'b0;
else
{r_gaddr_d2,r_gaddr_d1} <= {r_gaddr_d1,r_gaddr};
assign w_gaddr = gaddr;
assign w_addr = addr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'b0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~w_full)&w_en);
assign gaddr_wire = (addr_wire>>1)^addr_wire;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
gaddr <= 4'b0;
else
gaddr <= gaddr_wire;
assign w_gaddr = gaddr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
w_full <= 1'b0;
else if({~gaddr_wire[3:2],gaddr_wire[1:0]}==r_gaddr_d2)
w_full <= 1'b1;
else
w_full <= 1'b0;
endmodule | 0 |
140,697 | data/full_repos/permissive/90862816/Project/DP_RAM/sim/dp_ram test/tb_dp_ram.v | 90,862,816 | tb_dp_ram.v | v | 77 | 35 | [] | [] | [] | null | line:25: before: "(" | null | 1: b'%Error: Cannot find file containing module: test,data/full_repos/permissive/90862816\n ... Looked in:\n data/full_repos/permissive/90862816/Project/DP_RAM/sim/dp_ram/test,data/full_repos/permissive/90862816\n data/full_repos/permissive/90862816/Project/DP_RAM/sim/dp_ram/test,data/full_repos/permissive/90862816.v\n data/full_repos/permissive/90862816/Project/DP_RAM/sim/dp_ram/test,data/full_repos/permissive/90862816.sv\n test,data/full_repos/permissive/90862816\n test,data/full_repos/permissive/90862816.v\n test,data/full_repos/permissive/90862816.sv\n obj_dir/test,data/full_repos/permissive/90862816\n obj_dir/test,data/full_repos/permissive/90862816.v\n obj_dir/test,data/full_repos/permissive/90862816.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90862816/Project/DP_RAM/sim/dp_ram\n%Error: Cannot find file containing module: test/tb_dp_ram.v\n%Error: Exiting due to 3 error(s)\n' | 309,456 | module | module tb_dp_ram;
reg w_en;
reg w_clk;
reg r_clk;
reg [3:0] w_addr;
reg [3:0] r_addr;
reg [7:0] w_data;
wire [7:0] r_data;
parameter CLK = 20;
initial begin
w_clk = 0;
r_clk = 0;
end
initial begin
w_en = 0;
w_addr = 0;
w_data = 0;
#100
write_data(7);
end
initial begin
r_addr = 0;
#500
read_data(7);
end
always #(CLK/2) w_clk = ~ w_clk;
always #(CLK/2) r_clk = ~ r_clk;
dp_ram dp_ram_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (w_en),
.w_data (w_data),
.r_data (r_data),
.w_addr (w_addr),
.r_addr (r_addr)
);
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk)
w_en = 1;
w_addr = w_addr + 1;
w_data = w_addr;
end
@(posedge w_clk)
w_en = 0;
w_addr = 0;
w_data = 0;
end
endtask
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge r_clk)
r_addr = r_addr + 1;
end
@(posedge r_clk)
r_addr = 0;
end
endtask
endmodule | module tb_dp_ram; |
reg w_en;
reg w_clk;
reg r_clk;
reg [3:0] w_addr;
reg [3:0] r_addr;
reg [7:0] w_data;
wire [7:0] r_data;
parameter CLK = 20;
initial begin
w_clk = 0;
r_clk = 0;
end
initial begin
w_en = 0;
w_addr = 0;
w_data = 0;
#100
write_data(7);
end
initial begin
r_addr = 0;
#500
read_data(7);
end
always #(CLK/2) w_clk = ~ w_clk;
always #(CLK/2) r_clk = ~ r_clk;
dp_ram dp_ram_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (w_en),
.w_data (w_data),
.r_data (r_data),
.w_addr (w_addr),
.r_addr (r_addr)
);
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk)
w_en = 1;
w_addr = w_addr + 1;
w_data = w_addr;
end
@(posedge w_clk)
w_en = 0;
w_addr = 0;
w_data = 0;
end
endtask
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge r_clk)
r_addr = r_addr + 1;
end
@(posedge r_clk)
r_addr = 0;
end
endtask
endmodule | 0 |
140,698 | data/full_repos/permissive/90862816/Project/FIFO/design/fifo.v | 90,862,816 | fifo.v | v | 52 | 55 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 452: invalid continuation byte | null | 1: b"%Error: data/full_repos/permissive/90862816/Project/FIFO/design/fifo.v:17: Cannot find file containing module: 'w_ctrl'\nw_ctrl w_ctrl_inst(\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/90862816/Project/FIFO/design,data/full_repos/permissive/90862816/w_ctrl\n data/full_repos/permissive/90862816/Project/FIFO/design,data/full_repos/permissive/90862816/w_ctrl.v\n data/full_repos/permissive/90862816/Project/FIFO/design,data/full_repos/permissive/90862816/w_ctrl.sv\n w_ctrl\n w_ctrl.v\n w_ctrl.sv\n obj_dir/w_ctrl\n obj_dir/w_ctrl.v\n obj_dir/w_ctrl.sv\n%Error: data/full_repos/permissive/90862816/Project/FIFO/design/fifo.v:27: Cannot find file containing module: 'fifomen'\nfifomen fifomen_inst(\n^~~~~~~\n%Error: data/full_repos/permissive/90862816/Project/FIFO/design/fifo.v:39: Cannot find file containing module: 'r_ctrl'\nr_ctrl r_ctrl_inst(\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 309,457 | module | module fifo(
input wire w_clk,
input wire r_clk,
input wire rst_n,
input wire w_en,
input wire [7:0] w_data,
input wire r_en,
output wire w_full,
output wire [7:0] r_data,
output wire r_empty
);
wire [8:0] r_gaddr;
wire [8:0] w_addr;
wire [8:0] w_gaddr;
wire [8:0] r_addr;
w_ctrl w_ctrl_inst(
.w_clk (w_clk),
.rst_n (rst_n),
.w_en (w_en),
.r_gaddr (r_gaddr),
.w_full (w_full),
.w_addr (w_addr),
.w_gaddr (w_gaddr)
);
fifomen fifomen_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (w_en),
.w_full (w_full),
.w_data (w_data),
.w_addr (w_addr),
.r_empty (r_empty),
.r_addr (r_addr),
.r_data (r_data)
);
r_ctrl r_ctrl_inst(
.r_clk (r_clk),
.rst_n (rst_n),
.r_en (r_en),
.w_gaddr (w_gaddr),
.r_empty (r_empty),
.r_addr (r_addr),
.r_gaddr (r_gaddr)
);
endmodule | module fifo(
input wire w_clk,
input wire r_clk,
input wire rst_n,
input wire w_en,
input wire [7:0] w_data,
input wire r_en,
output wire w_full,
output wire [7:0] r_data,
output wire r_empty
); |
wire [8:0] r_gaddr;
wire [8:0] w_addr;
wire [8:0] w_gaddr;
wire [8:0] r_addr;
w_ctrl w_ctrl_inst(
.w_clk (w_clk),
.rst_n (rst_n),
.w_en (w_en),
.r_gaddr (r_gaddr),
.w_full (w_full),
.w_addr (w_addr),
.w_gaddr (w_gaddr)
);
fifomen fifomen_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (w_en),
.w_full (w_full),
.w_data (w_data),
.w_addr (w_addr),
.r_empty (r_empty),
.r_addr (r_addr),
.r_data (r_data)
);
r_ctrl r_ctrl_inst(
.r_clk (r_clk),
.rst_n (rst_n),
.r_en (r_en),
.w_gaddr (w_gaddr),
.r_empty (r_empty),
.r_addr (r_addr),
.r_gaddr (r_gaddr)
);
endmodule | 0 |
140,699 | data/full_repos/permissive/90862816/Project/FIFO/design/fifomem.v | 90,862,816 | fifomem.v | v | 29 | 55 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc0 in position 109: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/90862816/Project/FIFO/design/fifomem.v:17: Cannot find file containing module: 'dp_ram_512_8_swsr'\ndp_ram_512_8_swsr dp_ram_512_8_swsr_inst (\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90862816/Project/FIFO/design,data/full_repos/permissive/90862816/dp_ram_512_8_swsr\n data/full_repos/permissive/90862816/Project/FIFO/design,data/full_repos/permissive/90862816/dp_ram_512_8_swsr.v\n data/full_repos/permissive/90862816/Project/FIFO/design,data/full_repos/permissive/90862816/dp_ram_512_8_swsr.sv\n dp_ram_512_8_swsr\n dp_ram_512_8_swsr.v\n dp_ram_512_8_swsr.sv\n obj_dir/dp_ram_512_8_swsr\n obj_dir/dp_ram_512_8_swsr.v\n obj_dir/dp_ram_512_8_swsr.sv\n%Error: Exiting due to 1 error(s)\n" | 309,458 | module | module fifomen(
input wire w_clk,
input wire r_clk,
input wire w_en,
input wire w_full,
input wire [7:0] w_data,
input wire [8:0] w_addr,
input wire r_empty,
input wire [8:0] r_addr,
output wire [7:0] r_data
);
wire ram_w_en;
assign ram_w_en = w_en &(~w_full);
dp_ram_512_8_swsr dp_ram_512_8_swsr_inst (
.wrclock ( w_clk ),
.wren ( ram_w_en ),
.wraddress ( w_addr[7:0] ),
.data ( w_data ),
.rdclock ( r_clk ),
.rdaddress ( r_addr[7:0] ),
.q ( r_data )
);
endmodule | module fifomen(
input wire w_clk,
input wire r_clk,
input wire w_en,
input wire w_full,
input wire [7:0] w_data,
input wire [8:0] w_addr,
input wire r_empty,
input wire [8:0] r_addr,
output wire [7:0] r_data
); |
wire ram_w_en;
assign ram_w_en = w_en &(~w_full);
dp_ram_512_8_swsr dp_ram_512_8_swsr_inst (
.wrclock ( w_clk ),
.wren ( ram_w_en ),
.wraddress ( w_addr[7:0] ),
.data ( w_data ),
.rdclock ( r_clk ),
.rdaddress ( r_addr[7:0] ),
.q ( r_data )
);
endmodule | 0 |
140,700 | data/full_repos/permissive/90862816/Project/FIFO/design/w_ctrl.v | 90,862,816 | w_ctrl.v | v | 49 | 60 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 53: invalid continuation byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90862816/Project/FIFO/design/w_ctrl.v:31: Operator NOT expects 9 bits on the LHS, but LHS\'s VARREF \'w_full\' generates 1 bits.\n : ... In instance w_ctrl\nassign addr_wire = addr + ((~w_full)&w_en);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/FIFO/design/w_ctrl.v:31: Operator AND expects 9 bits on the RHS, but RHS\'s VARREF \'w_en\' generates 1 bits.\n : ... In instance w_ctrl\nassign addr_wire = addr + ((~w_full)&w_en);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,460 | module | module w_ctrl(
input wire w_clk,
input wire rst_n,
input wire w_en,
input wire [8:0] r_gaddr,
output reg w_full,
output wire [8:0] w_addr,
output wire [8:0] w_gaddr
);
reg [8:0] addr;
reg [8:0] gaddr;
wire [8:0] addr_wire;
wire [8:0] gaddr_wire;
reg [8:0] r_gaddr_d1,r_gaddr_d2;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
{r_gaddr_d2,r_gaddr_d1} <= 18'b0;
else
{r_gaddr_d2,r_gaddr_d1} <= {r_gaddr_d1,r_gaddr};
assign w_gaddr = gaddr;
assign w_addr = addr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 9'b0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~w_full)&w_en);
assign gaddr_wire = (addr_wire>>1)^addr_wire;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
gaddr <= 9'b0;
else
gaddr <= gaddr_wire;
assign w_gaddr = gaddr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
w_full <= 1'b0;
else if({~gaddr_wire[8:7],gaddr_wire[6:0]}==r_gaddr_d2)
w_full <= 1'b1;
else
w_full <= 1'b0;
endmodule | module w_ctrl(
input wire w_clk,
input wire rst_n,
input wire w_en,
input wire [8:0] r_gaddr,
output reg w_full,
output wire [8:0] w_addr,
output wire [8:0] w_gaddr
); |
reg [8:0] addr;
reg [8:0] gaddr;
wire [8:0] addr_wire;
wire [8:0] gaddr_wire;
reg [8:0] r_gaddr_d1,r_gaddr_d2;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
{r_gaddr_d2,r_gaddr_d1} <= 18'b0;
else
{r_gaddr_d2,r_gaddr_d1} <= {r_gaddr_d1,r_gaddr};
assign w_gaddr = gaddr;
assign w_addr = addr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 9'b0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~w_full)&w_en);
assign gaddr_wire = (addr_wire>>1)^addr_wire;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
gaddr <= 9'b0;
else
gaddr <= gaddr_wire;
assign w_gaddr = gaddr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
w_full <= 1'b0;
else if({~gaddr_wire[8:7],gaddr_wire[6:0]}==r_gaddr_d2)
w_full <= 1'b1;
else
w_full <= 1'b0;
endmodule | 0 |
140,701 | data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v | 90,862,816 | tb_fifo.v | v | 79 | 35 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 357: invalid start byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:17: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:24: Unsupported: Ignoring delay on this delayed statement.\n #300\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:30: syntax error, unexpected \'@\'\n @(posedge w_full);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:31: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:34: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_R/2) r_clk = ~r_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_W/2) w_clk = ~w_clk;\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:54: syntax error, unexpected \'@\'\n @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:57: syntax error, unexpected \'@\'\n @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:67: syntax error, unexpected \'@\'\n @(posedge w_clk);\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO/sim/tb_fifo.v:71: syntax error, unexpected \'@\'\n @(posedge w_clk);\n ^\n%Error: Exiting due to 5 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,463 | module | module tb_fifo;
reg r_clk,w_clk,rst_n;
reg w_en;
reg [7:0] w_data;
reg r_en;
wire w_full;
wire r_empty;
wire [7:0] r_data;
parameter CLK_W = 12;
parameter CLK_R = 11;
initial begin
r_clk = 0;
w_clk = 0;
rst_n = 0;
#200
rst_n = 1;
end
initial begin
w_en = 1'b0;
w_data = 0;
#300
write_data(258);
end
initial begin
r_en = 1'b0;
@(posedge w_full);
#40;
read_data(258);
end
always #(CLK_R/2) r_clk = ~r_clk;
always #(CLK_W/2) w_clk = ~w_clk;
fifo fifo_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.rst_n (rst_n),
.w_en (w_en),
.w_data (w_data),
.r_en (r_en),
.w_full (w_full),
.r_data (r_data),
.r_empty (r_empty)
);
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge r_clk);
r_en = 1'b1;
end
@(posedge r_clk);
r_en = 1'b0;
end
endtask
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk);
w_en = 1'b1;
w_data = i;
end
@(posedge w_clk);
w_en = 1'b0;
w_data = 0;
end
endtask
endmodule | module tb_fifo; |
reg r_clk,w_clk,rst_n;
reg w_en;
reg [7:0] w_data;
reg r_en;
wire w_full;
wire r_empty;
wire [7:0] r_data;
parameter CLK_W = 12;
parameter CLK_R = 11;
initial begin
r_clk = 0;
w_clk = 0;
rst_n = 0;
#200
rst_n = 1;
end
initial begin
w_en = 1'b0;
w_data = 0;
#300
write_data(258);
end
initial begin
r_en = 1'b0;
@(posedge w_full);
#40;
read_data(258);
end
always #(CLK_R/2) r_clk = ~r_clk;
always #(CLK_W/2) w_clk = ~w_clk;
fifo fifo_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.rst_n (rst_n),
.w_en (w_en),
.w_data (w_data),
.r_en (r_en),
.w_full (w_full),
.r_data (r_data),
.r_empty (r_empty)
);
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge r_clk);
r_en = 1'b1;
end
@(posedge r_clk);
r_en = 1'b0;
end
endtask
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk);
w_en = 1'b1;
w_data = i;
end
@(posedge w_clk);
w_en = 1'b0;
w_data = 0;
end
endtask
endmodule | 0 |
140,702 | data/full_repos/permissive/90862816/Project/fifo_b/design/fifomem.v | 90,862,816 | fifomem.v | v | 26 | 55 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc0 in position 109: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/90862816/Project/fifo_b/design/fifomem.v:16: Cannot find file containing module: 'dp_ram'\ndp_ram dp_ram_inst(\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/90862816/Project/fifo_b/design,data/full_repos/permissive/90862816/dp_ram\n data/full_repos/permissive/90862816/Project/fifo_b/design,data/full_repos/permissive/90862816/dp_ram.v\n data/full_repos/permissive/90862816/Project/fifo_b/design,data/full_repos/permissive/90862816/dp_ram.sv\n dp_ram\n dp_ram.v\n dp_ram.sv\n obj_dir/dp_ram\n obj_dir/dp_ram.v\n obj_dir/dp_ram.sv\n%Error: Exiting due to 1 error(s)\n" | 309,467 | module | module fifomen(
input wire w_clk,
input wire r_clk,
input wire w_en,
input wire w_full,
input wire [7:0] w_data,
input wire [2:0] w_addr,
input wire r_empty,
input wire [2:0] r_addr,
output wire [7:0] r_data
);
wire ram_w_en;
assign ram_w_en = w_en &(~w_full);
dp_ram dp_ram_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (ram_w_en),
.w_data (w_data),
.r_data (r_data),
.w_addr (w_addr),
.r_addr (r_addr)
);
endmodule | module fifomen(
input wire w_clk,
input wire r_clk,
input wire w_en,
input wire w_full,
input wire [7:0] w_data,
input wire [2:0] w_addr,
input wire r_empty,
input wire [2:0] r_addr,
output wire [7:0] r_data
); |
wire ram_w_en;
assign ram_w_en = w_en &(~w_full);
dp_ram dp_ram_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (ram_w_en),
.w_data (w_data),
.r_data (r_data),
.w_addr (w_addr),
.r_addr (r_addr)
);
endmodule | 0 |
140,703 | data/full_repos/permissive/90862816/Project/fifo_b/design/r_ctrl.v | 90,862,816 | r_ctrl.v | v | 40 | 75 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb6 in position 47: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90862816/Project/fifo_b/design/r_ctrl.v:28: Operator NOT expects 4 bits on the LHS, but LHS\'s VARREF \'r_empty\' generates 1 bits.\n : ... In instance r_ctrl\nassign addr_wire = addr + ((~r_empty)&r_en);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/fifo_b/design/r_ctrl.v:28: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'r_en\' generates 1 bits.\n : ... In instance r_ctrl\nassign addr_wire = addr + ((~r_empty)&r_en);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,468 | module | module r_ctrl(
input wire r_clk,
input wire rst_n,
input wire r_en,
input wire [3:0] w_addr,
output reg r_empty,
output wire [3:0] r_addr
);
reg [3:0] addr;
wire [3:0] addr_wire;
reg [3:0] w_addr_d1,w_addr_d2;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
{w_addr_d2,w_addr_d1} <= 8'b0;
else
{w_addr_d2,w_addr_d1} <= {w_addr_d1,w_addr};
assign r_addr = addr;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'd0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~r_empty)&r_en);
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
r_empty <= 1'b0;
else if (addr_wire == w_addr_d2)
r_empty <= 1'b1;
else
r_empty <= 1'b0;
endmodule | module r_ctrl(
input wire r_clk,
input wire rst_n,
input wire r_en,
input wire [3:0] w_addr,
output reg r_empty,
output wire [3:0] r_addr
); |
reg [3:0] addr;
wire [3:0] addr_wire;
reg [3:0] w_addr_d1,w_addr_d2;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
{w_addr_d2,w_addr_d1} <= 8'b0;
else
{w_addr_d2,w_addr_d1} <= {w_addr_d1,w_addr};
assign r_addr = addr;
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'd0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~r_empty)&r_en);
always @(posedge r_clk or negedge rst_n)
if(rst_n == 1'b0)
r_empty <= 1'b0;
else if (addr_wire == w_addr_d2)
r_empty <= 1'b1;
else
r_empty <= 1'b0;
endmodule | 0 |
140,704 | data/full_repos/permissive/90862816/Project/fifo_b/design/w_ctrl.v | 90,862,816 | w_ctrl.v | v | 39 | 71 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 53: invalid continuation byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90862816/Project/fifo_b/design/w_ctrl.v:27: Operator NOT expects 4 bits on the LHS, but LHS\'s VARREF \'w_full\' generates 1 bits.\n : ... In instance w_ctrl\nassign addr_wire = addr + ((~w_full)&w_en);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/fifo_b/design/w_ctrl.v:27: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'w_en\' generates 1 bits.\n : ... In instance w_ctrl\nassign addr_wire = addr + ((~w_full)&w_en);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,469 | module | module w_ctrl(
input wire w_clk,
input wire rst_n,
input wire w_en,
input wire [3:0] r_addr,
output reg w_full,
output wire [3:0] w_addr
);
reg [3:0] addr;
wire [3:0] addr_wire;
reg [3:0] r_addr_d1,r_addr_d2;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
{r_addr_d2,r_addr_d1} <= 8'b0;
else
{r_addr_d2,r_addr_d1} <= {r_addr_d1,r_addr};
assign w_addr = addr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'b0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~w_full)&w_en);
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
w_full <= 1'b0;
else if({addr_wire[3],addr_wire[2:0]}==r_addr_d2)
w_full <= 1'b1;
else
w_full <= 1'b0;
endmodule | module w_ctrl(
input wire w_clk,
input wire rst_n,
input wire w_en,
input wire [3:0] r_addr,
output reg w_full,
output wire [3:0] w_addr
); |
reg [3:0] addr;
wire [3:0] addr_wire;
reg [3:0] r_addr_d1,r_addr_d2;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
{r_addr_d2,r_addr_d1} <= 8'b0;
else
{r_addr_d2,r_addr_d1} <= {r_addr_d1,r_addr};
assign w_addr = addr;
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
addr <= 4'b0;
else
addr <= addr_wire;
assign addr_wire = addr + ((~w_full)&w_en);
always @(posedge w_clk or negedge rst_n)
if(rst_n == 1'b0)
w_full <= 1'b0;
else if({addr_wire[3],addr_wire[2:0]}==r_addr_d2)
w_full <= 1'b1;
else
w_full <= 1'b0;
endmodule | 0 |
140,705 | data/full_repos/permissive/90862816/Project/fifo_b/sim/tb_fifo.v | 90,862,816 | tb_fifo.v | v | 118 | 57 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 947: invalid start byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/fifo_b/sim/tb_fifo.v:48: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/fifo_b/sim/tb_fifo.v:72: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_W/2) w_clk = ~w_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/fifo_b/sim/tb_fifo.v:73: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_R/2) r_clk = ~r_clk;\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/90862816/Project/fifo_b/sim/tb_fifo.v:40: Signal definition not found, creating implicitly: \'error\'\nassign error = (r_data == counter_check) ? 1\'b0 : 1\'b1;\n ^~~~~\n%Error: data/full_repos/permissive/90862816/Project/fifo_b/sim/tb_fifo.v:76: Cannot find file containing module: \'fifo\'\nfifo fifo_inst(\n^~~~\n ... Looked in:\n data/full_repos/permissive/90862816/Project/fifo_b/sim,data/full_repos/permissive/90862816/fifo\n data/full_repos/permissive/90862816/Project/fifo_b/sim,data/full_repos/permissive/90862816/fifo.v\n data/full_repos/permissive/90862816/Project/fifo_b/sim,data/full_repos/permissive/90862816/fifo.sv\n fifo\n fifo.v\n fifo.sv\n obj_dir/fifo\n obj_dir/fifo.v\n obj_dir/fifo.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,470 | module | module tb_fifo;
reg r_clk,w_clk,rst_n;
reg w_en;
wire [7:0] w_data;
reg r_en;
wire w_full;
wire r_empty;
wire [7:0] r_data;
parameter CLK_W = 12;
parameter CLK_R = 11;
reg [7:0] counter = 8'h00;
always @ (posedge w_clk or negedge rst_n)
begin
if(~rst_n)
counter <= 8'h00;
else
if(~w_full)
counter <= counter + 1'b1;
else
counter <= counter;
end
reg [7:0] counter_check = 8'h00;
always @ (posedge r_clk or negedge rst_n)
begin
if(~rst_n)
counter_check <= 8'h00;
else
if(~r_empty)
counter_check <= counter_check + 1'b1;
else
counter_check <= counter_check;
end
assign w_data = counter;
assign error = (r_data == counter_check) ? 1'b0 : 1'b1;
initial begin
w_en = 0;
r_en = 0;
r_clk = 0;
w_clk = 0;
rst_n = 0;
#200
rst_n = 1;
w_en = 1;
r_en = 1;
end
always #(CLK_W/2) w_clk = ~w_clk;
always #(CLK_R/2) r_clk = ~r_clk;
fifo fifo_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.rst_n (rst_n),
.w_en (w_en),
.w_data (w_data),
.r_en (r_en),
.w_full (w_full),
.r_data (r_data),
.r_empty (r_empty)
);
endmodule | module tb_fifo; |
reg r_clk,w_clk,rst_n;
reg w_en;
wire [7:0] w_data;
reg r_en;
wire w_full;
wire r_empty;
wire [7:0] r_data;
parameter CLK_W = 12;
parameter CLK_R = 11;
reg [7:0] counter = 8'h00;
always @ (posedge w_clk or negedge rst_n)
begin
if(~rst_n)
counter <= 8'h00;
else
if(~w_full)
counter <= counter + 1'b1;
else
counter <= counter;
end
reg [7:0] counter_check = 8'h00;
always @ (posedge r_clk or negedge rst_n)
begin
if(~rst_n)
counter_check <= 8'h00;
else
if(~r_empty)
counter_check <= counter_check + 1'b1;
else
counter_check <= counter_check;
end
assign w_data = counter;
assign error = (r_data == counter_check) ? 1'b0 : 1'b1;
initial begin
w_en = 0;
r_en = 0;
r_clk = 0;
w_clk = 0;
rst_n = 0;
#200
rst_n = 1;
w_en = 1;
r_en = 1;
end
always #(CLK_W/2) w_clk = ~w_clk;
always #(CLK_R/2) r_clk = ~r_clk;
fifo fifo_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.rst_n (rst_n),
.w_en (w_en),
.w_data (w_data),
.r_en (r_en),
.w_full (w_full),
.r_data (r_data),
.r_empty (r_empty)
);
endmodule | 0 |
140,706 | data/full_repos/permissive/90862816/Project/FIFO_IP/design/fifo.v | 90,862,816 | fifo.v | v | 24 | 29 | [] | [] | [] | [(1, 23)] | null | null | 1: b"%Error: data/full_repos/permissive/90862816/Project/FIFO_IP/design/fifo.v:13: Cannot find file containing module: 'fifo_256_8'\nfifo_256_8 fifo_256_8_inst (\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90862816/Project/FIFO_IP/design,data/full_repos/permissive/90862816/fifo_256_8\n data/full_repos/permissive/90862816/Project/FIFO_IP/design,data/full_repos/permissive/90862816/fifo_256_8.v\n data/full_repos/permissive/90862816/Project/FIFO_IP/design,data/full_repos/permissive/90862816/fifo_256_8.sv\n fifo_256_8\n fifo_256_8.v\n fifo_256_8.sv\n obj_dir/fifo_256_8\n obj_dir/fifo_256_8.v\n obj_dir/fifo_256_8.sv\n%Error: Exiting due to 1 error(s)\n" | 309,471 | module | module fifo(
input w_clk,
input r_clk,
input w_en,
input r_en,
input [7:0] w_data,
output [7:0] r_data,
output w_full,
output r_empty
);
fifo_256_8 fifo_256_8_inst (
.data ( w_data ),
.rdclk ( r_clk ),
.rdreq ( r_en ),
.wrclk ( w_clk ),
.wrreq ( w_en ),
.q ( r_data ),
.rdempty ( r_empty ),
.wrfull ( w_full )
);
endmodule | module fifo(
input w_clk,
input r_clk,
input w_en,
input r_en,
input [7:0] w_data,
output [7:0] r_data,
output w_full,
output r_empty
); |
fifo_256_8 fifo_256_8_inst (
.data ( w_data ),
.rdclk ( r_clk ),
.rdreq ( r_en ),
.wrclk ( w_clk ),
.wrreq ( w_en ),
.q ( r_data ),
.rdempty ( r_empty ),
.wrfull ( w_full )
);
endmodule | 0 |
140,707 | data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v | 90,862,816 | tb_fifo.v | v | 75 | 35 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 307: invalid start byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:21: Unsupported: Ignoring delay on this delayed statement.\n #300\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:27: syntax error, unexpected \'@\'\n @(posedge w_full);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:28: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways #(R_CLK/2) r_clk = ~r_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:32: Unsupported: Ignoring delay on this delayed statement.\nalways #(W_CLK/2) w_clk = ~w_clk;\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:50: syntax error, unexpected \'@\'\n @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:53: syntax error, unexpected \'@\'\n @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:63: syntax error, unexpected \'@\'\n @(posedge w_clk);\n ^\n%Error: data/full_repos/permissive/90862816/Project/FIFO_IP/sim/tb_fifo.v:67: syntax error, unexpected \'@\'\n @(posedge w_clk);\n ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,474 | module | module tb_fifo;
reg r_clk,w_clk;
reg w_en;
reg [7:0] w_data;
reg r_en;
wire w_full;
wire r_empty;
wire [7:0] r_data;
parameter W_CLK = 20;
parameter R_CLK = 17;
initial begin
r_clk = 0;
w_clk = 0;
end
initial begin
w_en = 1'b0;
w_data = 0;
#300
write_data(256);
end
initial begin
r_en = 1'b0;
@(posedge w_full);
#40;
read_data(256);
end
always #(R_CLK/2) r_clk = ~r_clk;
always #(W_CLK/2) w_clk = ~w_clk;
fifo fifo_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (w_en),
.w_data (w_data),
.r_en (r_en),
.w_full (w_full),
.r_data (r_data),
.r_empty (r_empty)
);
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge r_clk);
r_en = 1'b1;
end
@(posedge r_clk);
r_en = 1'b0;
end
endtask
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk);
w_en = 1'b1;
w_data = i;
end
@(posedge w_clk);
w_en = 1'b0;
w_data = 0;
end
endtask
endmodule | module tb_fifo; |
reg r_clk,w_clk;
reg w_en;
reg [7:0] w_data;
reg r_en;
wire w_full;
wire r_empty;
wire [7:0] r_data;
parameter W_CLK = 20;
parameter R_CLK = 17;
initial begin
r_clk = 0;
w_clk = 0;
end
initial begin
w_en = 1'b0;
w_data = 0;
#300
write_data(256);
end
initial begin
r_en = 1'b0;
@(posedge w_full);
#40;
read_data(256);
end
always #(R_CLK/2) r_clk = ~r_clk;
always #(W_CLK/2) w_clk = ~w_clk;
fifo fifo_inst(
.w_clk (w_clk),
.r_clk (r_clk),
.w_en (w_en),
.w_data (w_data),
.r_en (r_en),
.w_full (w_full),
.r_data (r_data),
.r_empty (r_empty)
);
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge r_clk);
r_en = 1'b1;
end
@(posedge r_clk);
r_en = 1'b0;
end
endtask
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk);
w_en = 1'b1;
w_data = i;
end
@(posedge w_clk);
w_en = 1'b0;
w_data = 0;
end
endtask
endmodule | 0 |
140,708 | data/full_repos/permissive/90862816/Project/MULTI/design/multi.v | 90,862,816 | multi.v | v | 24 | 40 | [] | [] | [] | [(1, 24)] | null | null | 1: b"%Error: data/full_repos/permissive/90862816/Project/MULTI/design/multi.v:16: Cannot find file containing module: 'divider_16d8_l3'\ndivider_16d8_l3 divider_16d8_l3_inst (\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90862816/Project/MULTI/design,data/full_repos/permissive/90862816/divider_16d8_l3\n data/full_repos/permissive/90862816/Project/MULTI/design,data/full_repos/permissive/90862816/divider_16d8_l3.v\n data/full_repos/permissive/90862816/Project/MULTI/design,data/full_repos/permissive/90862816/divider_16d8_l3.sv\n divider_16d8_l3\n divider_16d8_l3.v\n divider_16d8_l3.sv\n obj_dir/divider_16d8_l3\n obj_dir/divider_16d8_l3.v\n obj_dir/divider_16d8_l3.sv\n%Error: Exiting due to 1 error(s)\n" | 309,476 | module | module multi(
input wire sclk,
input wire rst_n,
input wire [15:0] in_a,
input wire [15:0] in_b,
output wire [31:0] out_rlst
);
divider_16d8_l3 divider_16d8_l3_inst (
.clock ( sclk ),
.denom ( in_b[7:0] ),
.numer ( in_a ),
.quotient ( out_rlst[15:0] ),
.remain ( remain_sig )
);
endmodule | module multi(
input wire sclk,
input wire rst_n,
input wire [15:0] in_a,
input wire [15:0] in_b,
output wire [31:0] out_rlst
); |
divider_16d8_l3 divider_16d8_l3_inst (
.clock ( sclk ),
.denom ( in_b[7:0] ),
.numer ( in_a ),
.quotient ( out_rlst[15:0] ),
.remain ( remain_sig )
);
endmodule | 0 |
140,709 | data/full_repos/permissive/90862816/Project/MULTI/sim/tb_multi.v | 90,862,816 | tb_multi.v | v | 37 | 43 | [] | [] | [] | null | line:12: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/MULTI/sim/tb_multi.v:11: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/MULTI/sim/tb_multi.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #10 sclk = ~sclk;\n ^\n%Error: data/full_repos/permissive/90862816/Project/MULTI/sim/tb_multi.v:30: syntax error, unexpected \'@\'\n @(posedge sclk)\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,481 | module | module tb_multi;
reg sclk,rst_n;
reg [15:0] in_d;
wire [31:0] rslt;
initial begin
rst_n = 1'b0;
sclk = 1'b0;
#100
gen_data();
end
always #10 sclk = ~sclk;
multi multi_inst(
.sclk (sclk),
.rst_n (rst_n),
.in_a (in_d),
.in_b (in_d),
.out_rlst (rslt)
);
task gen_data();
integer i;
begin
for(i=0;i<255;i=i+1)
begin
@(posedge sclk)
in_d <= {$random} % 32768;
end
end
endtask
endmodule | module tb_multi; |
reg sclk,rst_n;
reg [15:0] in_d;
wire [31:0] rslt;
initial begin
rst_n = 1'b0;
sclk = 1'b0;
#100
gen_data();
end
always #10 sclk = ~sclk;
multi multi_inst(
.sclk (sclk),
.rst_n (rst_n),
.in_a (in_d),
.in_b (in_d),
.out_rlst (rslt)
);
task gen_data();
integer i;
begin
for(i=0;i<255;i=i+1)
begin
@(posedge sclk)
in_d <= {$random} % 32768;
end
end
endtask
endmodule | 0 |
140,710 | data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v | 90,862,816 | parall_interf.v | v | 92 | 218 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb1 in position 214: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:39: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_0 <= 8\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:40: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_1 <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:41: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_2 <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:42: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_3 <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:43: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_4 <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:44: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_5 <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:45: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_6 <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:46: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n data_7 <= 8\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/Parall_Interface/design/parall_interf.v:74: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance parall_interf\n r_data <= 8\'d0;\n ^~\n%Error: Exiting due to 9 warning(s)\n' | 309,483 | module | module parall_interf(
input wire sclk,
input wire rst_n,
input wire cs_n,
input wire rd_n,
input wire wr_n,
inout tri [15:0] data,
input wire [7:0] addr
);
reg [15:0] data_0,data_1,data_2,data_3,data_4,data_5,data_6,data_7;
reg [2:0] cs_n_r,rd_n_r,wr_n_r;
reg [47:0] data_r;
reg [23:0] addr_r;
reg [15:0] r_data;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
{cs_n_r,rd_n_r,wr_n_r} <= 9'h1ff;
else
{cs_n_r,rd_n_r,wr_n_r} <= {{cs_n_r[1:0],cs_n},{rd_n_r[1:0],rd_n},{wr_n_r[1:0],wr_n}};
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)begin
data_r <= 48'd0;
addr_r <= 24'd0;
end
else begin
data_r <= {data_r[31:0],data};
addr_r <= {addr_r[15:0],addr};
end
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0) begin
data_0 <= 8'd0;
data_1 <= 8'd0;
data_2 <= 8'd0;
data_3 <= 8'd0;
data_4 <= 8'd0;
data_5 <= 8'd0;
data_6 <= 8'd0;
data_7 <= 8'd0;
end
else if(cs_n_r[2] == 1'b0 && rd_n_r[2] == 1'b1 && wr_n_r[2] == 1'b0)begin
case(addr_r[23:16])
8'd0:data_0 <= data_r[47:32];
8'd1:data_1 <= data_r[47:32];
8'd2:data_2 <= data_r[47:32];
8'd3:data_3 <= data_r[47:32];
8'd4:data_4 <= data_r[47:32];
8'd5:data_5 <= data_r[47:32];
8'd6:data_6 <= data_r[47:32];
8'd7:data_7 <= data_r[47:32];
default:begin
data_0 <= data_0;
data_1 <= data_1;
data_2 <= data_2;
data_3 <= data_3;
data_4 <= data_4;
data_5 <= data_5;
data_6 <= data_6;
data_7 <= data_7;
end
endcase
end
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
r_data <= 8'd0;
else if(cs_n_r[2] == 1'b0 && wr_n_r[2] == 1'b1)begin
case(addr_r[23:16])
8'd0:r_data <= data_0;
8'd1:r_data <= data_1;
8'd2:r_data <= data_2;
8'd3:r_data <= data_3;
8'd4:r_data <= data_4;
8'd5:r_data <= data_5;
8'd6:r_data <= data_6;
8'd7:r_data <= data_7;
default:r_data <= 16'd0;
endcase
end
assign data = (cs_n_r[2] == 1'b0 && rd_n_r[2] == 1'b0)?r_data:16'hzzzz;
endmodule | module parall_interf(
input wire sclk,
input wire rst_n,
input wire cs_n,
input wire rd_n,
input wire wr_n,
inout tri [15:0] data,
input wire [7:0] addr
); |
reg [15:0] data_0,data_1,data_2,data_3,data_4,data_5,data_6,data_7;
reg [2:0] cs_n_r,rd_n_r,wr_n_r;
reg [47:0] data_r;
reg [23:0] addr_r;
reg [15:0] r_data;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
{cs_n_r,rd_n_r,wr_n_r} <= 9'h1ff;
else
{cs_n_r,rd_n_r,wr_n_r} <= {{cs_n_r[1:0],cs_n},{rd_n_r[1:0],rd_n},{wr_n_r[1:0],wr_n}};
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)begin
data_r <= 48'd0;
addr_r <= 24'd0;
end
else begin
data_r <= {data_r[31:0],data};
addr_r <= {addr_r[15:0],addr};
end
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0) begin
data_0 <= 8'd0;
data_1 <= 8'd0;
data_2 <= 8'd0;
data_3 <= 8'd0;
data_4 <= 8'd0;
data_5 <= 8'd0;
data_6 <= 8'd0;
data_7 <= 8'd0;
end
else if(cs_n_r[2] == 1'b0 && rd_n_r[2] == 1'b1 && wr_n_r[2] == 1'b0)begin
case(addr_r[23:16])
8'd0:data_0 <= data_r[47:32];
8'd1:data_1 <= data_r[47:32];
8'd2:data_2 <= data_r[47:32];
8'd3:data_3 <= data_r[47:32];
8'd4:data_4 <= data_r[47:32];
8'd5:data_5 <= data_r[47:32];
8'd6:data_6 <= data_r[47:32];
8'd7:data_7 <= data_r[47:32];
default:begin
data_0 <= data_0;
data_1 <= data_1;
data_2 <= data_2;
data_3 <= data_3;
data_4 <= data_4;
data_5 <= data_5;
data_6 <= data_6;
data_7 <= data_7;
end
endcase
end
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
r_data <= 8'd0;
else if(cs_n_r[2] == 1'b0 && wr_n_r[2] == 1'b1)begin
case(addr_r[23:16])
8'd0:r_data <= data_0;
8'd1:r_data <= data_1;
8'd2:r_data <= data_2;
8'd3:r_data <= data_3;
8'd4:r_data <= data_4;
8'd5:r_data <= data_5;
8'd6:r_data <= data_6;
8'd7:r_data <= data_7;
default:r_data <= 16'd0;
endcase
end
assign data = (cs_n_r[2] == 1'b0 && rd_n_r[2] == 1'b0)?r_data:16'hzzzz;
endmodule | 0 |
140,711 | data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v | 90,862,816 | tb_parall_interf.v | v | 126 | 89 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd3 in position 167: invalid continuation byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:18: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:28: syntax error, unexpected \'@\'\n @(posedge rst_n)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:31: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #10 sclk = ~sclk;\n ^\n%Error: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:92: syntax error, unexpected \'@\'\n @(posedge sclk); \n ^\n%Error: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:102: syntax error, unexpected \'@\'\n @(posedge sclk); \n ^\n%Error: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:112: syntax error, unexpected \'@\'\n @(posedge sclk); \n ^\n%Error: data/full_repos/permissive/90862816/Project/Parall_Interface/sim/tb_parall_interf.v:122: syntax error, unexpected \'@\'\n @(posedge sclk); \n ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,484 | module | module tb_parall_interf();
parameter setup_time = 2;
parameter hold_time = 2;
parameter data_time = 4;
parameter read_wait = 5;
reg sclk,rst_n;
reg cs_n,rd_n,wr_n;
reg [15:0] data;
reg [7:0] addr;
tri [15:0] w_data;
initial begin
sclk = 0;
rst_n = 0;
#200
rst_n = 1;
end
initial begin
cs_n = 1;
rd_n = 1;
wr_n = 1;
data = 16'd0;
addr = 8'd0;
@(posedge rst_n)
#100;
write_data(8);
#100
read_data(8);
end
always #10 sclk = ~sclk;
parall_interf parall_interf_inst(
.sclk (sclk),
.rst_n (rst_n),
.cs_n (cs_n),
.rd_n (rd_n),
.wr_n (wr_n),
.data (w_data),
.addr (addr)
);
assign w_data = (wr_n==1'b0)?data:16'hzzzz;
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
cs_n = 0;
data = i[15:0];
addr = i[7:0];
setup_dly();
wr_n = 0;
data_dly();
wr_n = 1;
hold_dly();
end
cs_n = 1;
end
endtask
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
cs_n = 0;
addr = i[7:0];
read_dly();
rd_n = 0;
data_dly();
$display("read data addr is %d data is %d",i,w_data);
rd_n = 1;
end
cs_n = 1;
end
endtask
task setup_dly();
integer i;
begin
for(i=0;i<setup_time;i=i+1)
begin
@(posedge sclk);
end
end
endtask
task hold_dly();
integer i;
begin
for(i=0;i<hold_time;i=i+1)
begin
@(posedge sclk);
end
end
endtask
task data_dly();
integer i;
begin
for(i=0;i<data_time;i=i+1)
begin
@(posedge sclk);
end
end
endtask
task read_dly();
integer i;
begin
for(i=0;i<read_wait;i=i+1)
begin
@(posedge sclk);
end
end
endtask
endmodule | module tb_parall_interf(); |
parameter setup_time = 2;
parameter hold_time = 2;
parameter data_time = 4;
parameter read_wait = 5;
reg sclk,rst_n;
reg cs_n,rd_n,wr_n;
reg [15:0] data;
reg [7:0] addr;
tri [15:0] w_data;
initial begin
sclk = 0;
rst_n = 0;
#200
rst_n = 1;
end
initial begin
cs_n = 1;
rd_n = 1;
wr_n = 1;
data = 16'd0;
addr = 8'd0;
@(posedge rst_n)
#100;
write_data(8);
#100
read_data(8);
end
always #10 sclk = ~sclk;
parall_interf parall_interf_inst(
.sclk (sclk),
.rst_n (rst_n),
.cs_n (cs_n),
.rd_n (rd_n),
.wr_n (wr_n),
.data (w_data),
.addr (addr)
);
assign w_data = (wr_n==1'b0)?data:16'hzzzz;
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
cs_n = 0;
data = i[15:0];
addr = i[7:0];
setup_dly();
wr_n = 0;
data_dly();
wr_n = 1;
hold_dly();
end
cs_n = 1;
end
endtask
task read_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
cs_n = 0;
addr = i[7:0];
read_dly();
rd_n = 0;
data_dly();
$display("read data addr is %d data is %d",i,w_data);
rd_n = 1;
end
cs_n = 1;
end
endtask
task setup_dly();
integer i;
begin
for(i=0;i<setup_time;i=i+1)
begin
@(posedge sclk);
end
end
endtask
task hold_dly();
integer i;
begin
for(i=0;i<hold_time;i=i+1)
begin
@(posedge sclk);
end
end
endtask
task data_dly();
integer i;
begin
for(i=0;i<data_time;i=i+1)
begin
@(posedge sclk);
end
end
endtask
task read_dly();
integer i;
begin
for(i=0;i<read_wait;i=i+1)
begin
@(posedge sclk);
end
end
endtask
endmodule | 0 |
140,712 | data/full_repos/permissive/90862816/Project/RAM/design/RAM.v | 90,862,816 | RAM.v | v | 66 | 118 | [] | [] | [] | [(1, 66)] | null | data/verilator_xmls/8ea054fa-bec2-42af-809c-e0882083984d.xml | null | 309,485 | module | module RAM(
input wire w_clk,
input wire [7:0] din,
input wire [3:0] w_addr,
output reg [63:0] data
);
reg [7:0] en;
always @(w_addr[2:0])
begin
case(w_addr[2:0])
3'b000: begin
en[0] = 1'b1; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b001: begin
en[0] = 1'b0; en[1] = 1'b1; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b010: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b1; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b011: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b1; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b100: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b1; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b101: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b1; en[6] = 1'b0; en[7] = 1'b0;
end
3'b110: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b1; en[7] = 1'b0;
end
3'b111: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b1;
end
endcase
end
generate
genvar i;
for(i=0;i<8;i=i+1)
begin:data_processing
always @(posedge w_clk)
begin
if(en[i])
data[(8*i+7):(8*i)] <= din[7:0];
else
data[(8*i+7):(8*i)] <= data[(8*i+7):(8*i)];
end
end
endgenerate
endmodule | module RAM(
input wire w_clk,
input wire [7:0] din,
input wire [3:0] w_addr,
output reg [63:0] data
); |
reg [7:0] en;
always @(w_addr[2:0])
begin
case(w_addr[2:0])
3'b000: begin
en[0] = 1'b1; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b001: begin
en[0] = 1'b0; en[1] = 1'b1; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b010: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b1; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b011: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b1; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b100: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b1; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b0;
end
3'b101: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b1; en[6] = 1'b0; en[7] = 1'b0;
end
3'b110: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b1; en[7] = 1'b0;
end
3'b111: begin
en[0] = 1'b0; en[1] = 1'b0; en[2] = 1'b0; en[3] = 1'b0; en[4] = 1'b0; en[5] = 1'b0; en[6] = 1'b0; en[7] = 1'b1;
end
endcase
end
generate
genvar i;
for(i=0;i<8;i=i+1)
begin:data_processing
always @(posedge w_clk)
begin
if(en[i])
data[(8*i+7):(8*i)] <= din[7:0];
else
data[(8*i+7):(8*i)] <= data[(8*i+7):(8*i)];
end
end
endgenerate
endmodule | 0 |
140,713 | data/full_repos/permissive/90862816/Project/RAM/sim/tb_RAM.v | 90,862,816 | tb_RAM.v | v | 44 | 33 | [] | [] | [] | null | line:18: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/RAM/sim/tb_RAM.v:17: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/RAM/sim/tb_RAM.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK/2) w_clk = ~ w_clk;\n ^\n%Error: data/full_repos/permissive/90862816/Project/RAM/sim/tb_RAM.v:34: syntax error, unexpected \'@\'\n @(posedge w_clk)\n ^\n%Error: data/full_repos/permissive/90862816/Project/RAM/sim/tb_RAM.v:38: syntax error, unexpected \'@\'\n @(posedge w_clk)\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,486 | module | module tb_RAM;
reg w_clk;
reg [3:0] w_addr;
reg [7:0] din;
wire [63:0] data;
parameter CLK = 20;
initial begin
w_clk = 0;
end
initial begin
w_addr = 0;
din = 0;
#100
write_data(8);
end
always #(CLK/2) w_clk = ~ w_clk;
RAM RAM_inst(
.w_clk (w_clk),
.din (din),
.w_addr (w_addr),
.data (data)
);
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk)
w_addr = w_addr + 1;
din = w_addr;
end
@(posedge w_clk)
w_addr = 0;
din = 0;
end
endtask
endmodule | module tb_RAM; |
reg w_clk;
reg [3:0] w_addr;
reg [7:0] din;
wire [63:0] data;
parameter CLK = 20;
initial begin
w_clk = 0;
end
initial begin
w_addr = 0;
din = 0;
#100
write_data(8);
end
always #(CLK/2) w_clk = ~ w_clk;
RAM RAM_inst(
.w_clk (w_clk),
.din (din),
.w_addr (w_addr),
.data (data)
);
task write_data(len);
integer i,len;
begin
for(i=0;i<len;i=i+1)
begin
@(posedge w_clk)
w_addr = w_addr + 1;
din = w_addr;
end
@(posedge w_clk)
w_addr = 0;
din = 0;
end
endtask
endmodule | 0 |
140,714 | data/full_repos/permissive/90862816/Project/SPI/design/spi_ctrl.v | 90,862,816 | spi_ctrl.v | v | 172 | 159 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb4 in position 129: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90862816/Project/SPI/design/spi_ctrl.v:103: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance spi_ctrl\n r_addr <= 4\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90862816/Project/SPI/design/spi_ctrl.v:110: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance spi_ctrl\n data_end <= 5\'d0;\n ^~\n%Error: data/full_repos/permissive/90862816/Project/SPI/design/spi_ctrl.v:163: Cannot find file containing module: \'ram_16_32_sr\'\nram_16_32_sr ram_16_32_sr_inst (\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90862816/Project/SPI/design,data/full_repos/permissive/90862816/ram_16_32_sr\n data/full_repos/permissive/90862816/Project/SPI/design,data/full_repos/permissive/90862816/ram_16_32_sr.v\n data/full_repos/permissive/90862816/Project/SPI/design,data/full_repos/permissive/90862816/ram_16_32_sr.sv\n ram_16_32_sr\n ram_16_32_sr.v\n ram_16_32_sr.sv\n obj_dir/ram_16_32_sr\n obj_dir/ram_16_32_sr.v\n obj_dir/ram_16_32_sr.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 309,487 | module | module spi_ctrl(
input wire sclk,
input wire rst_n,
input wire work_en,
output reg conf_end,
output wire spi_clk,
output wire spi_sdi,
output wire spi_csn,
input wire spi_sdo
);
parameter IDLE = 5'b0_0001;
parameter WAIT = 5'b0_0010;
parameter R_MEM= 5'b0_0100;
parameter W_REG= 5'b0_1000;
parameter STOP = 5'b1_0000;
parameter H_DIV_CYC = 5'd25-1;
reg [4:0] state;
reg [4:0] div_cnt;
reg clk_p = 1'b0;
wire clk_n;
reg pose_flag;
reg [3:0] wait_cnt;
reg [3:0] shift_cnt;
reg [4:0] r_addr;
wire [15:0] r_data;
wire wren;
reg [15:0] shift_buf;
reg data_end;
reg sdi;
reg csn;
reg tck;
always @(posedge sclk or negedge rst_n)
begin
if (rst_n == 1'b0)
div_cnt <= 5'd0;
else if(div_cnt == H_DIV_CYC)
div_cnt <= 5'd0;
else
div_cnt <= div_cnt + 1'b1;
end
always @(posedge sclk or negedge rst_n)
begin
if(rst_n == 1'b0)
clk_p <= 1'b0;
else if(div_cnt == H_DIV_CYC)
clk_p <= ~clk_p;
end
assign clk_n = ~clk_p;
always @(posedge sclk or negedge rst_n)
begin
if(rst_n == 1'b0)
pose_flag <= 1'b0;
else if(clk_p == 1'b0 && div_cnt == H_DIV_CYC)
pose_flag <= 1'b1;
else pose_flag <= 1'b0;
end
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
wait_cnt <= 4'd0;
else if (state == WAIT && pose_flag == 1'b1)
wait_cnt <= wait_cnt + 1'b1;
else if(state != WAIT)
wait_cnt <= 4'd0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
state <= IDLE;
else case(state)
IDLE: if(work_en == 1'b1)
state <= WAIT;
WAIT: if(wait_cnt[3] == 1'b1)
state <= R_MEM;
R_MEM: state <= W_REG;
W_REG:if((shift_cnt == 4'd15) && (pose_flag == 1'b1 )&& (data_end != 1'b1))
state <= WAIT;
else if((shift_cnt == 4'd15) && (pose_flag == 1'b1 )&& (data_end == 1'b1))
state <= STOP;
STOP: state <= STOP;
default: state <= IDLE;
endcase
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
shift_cnt <= 4'd0;
else if(state == W_REG && pose_flag == 1'b1)
shift_cnt <= shift_cnt + 1'b1;
else if(state != W_REG)
shift_cnt <= 4'd0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
r_addr <= 4'd0;
else if(state == R_MEM)
r_addr <= r_addr + 1'b1;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
data_end <= 5'd0;
else if(state == R_MEM && (&r_addr) == 1'b1)
data_end <= 1'b1;
assign wren = 1'b0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
shift_buf <= 16'd0;
else if(state == R_MEM)
shift_buf <= r_data;
else if(state == W_REG && pose_flag == 1'b1)
shift_buf <= {shift_buf[14:0],1'b1};
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
sdi <= 1'b0;
else if(state == W_REG)
sdi <= shift_buf[15];
else if(state != W_REG)
sdi <= 1'b0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
csn <= 1'b1;
else if(state == W_REG)
csn <= 1'b0;
else
csn <= 1'b1;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
tck <= 1'b0;
else if(state == W_REG)
tck <= clk_n;
else
tck <= 1'b0;
assign spi_clk = tck;
assign spi_csn = csn;
assign spi_sdi = sdi;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
conf_end <= 1'b0;
else if(state == STOP)
conf_end <= 1'b1;
ram_16_32_sr ram_16_32_sr_inst (
.address ( r_addr ),
.clock ( sclk ),
.data ( 16'd0 ),
.wren ( wren ),
.q ( r_data )
);
endmodule | module spi_ctrl(
input wire sclk,
input wire rst_n,
input wire work_en,
output reg conf_end,
output wire spi_clk,
output wire spi_sdi,
output wire spi_csn,
input wire spi_sdo
); |
parameter IDLE = 5'b0_0001;
parameter WAIT = 5'b0_0010;
parameter R_MEM= 5'b0_0100;
parameter W_REG= 5'b0_1000;
parameter STOP = 5'b1_0000;
parameter H_DIV_CYC = 5'd25-1;
reg [4:0] state;
reg [4:0] div_cnt;
reg clk_p = 1'b0;
wire clk_n;
reg pose_flag;
reg [3:0] wait_cnt;
reg [3:0] shift_cnt;
reg [4:0] r_addr;
wire [15:0] r_data;
wire wren;
reg [15:0] shift_buf;
reg data_end;
reg sdi;
reg csn;
reg tck;
always @(posedge sclk or negedge rst_n)
begin
if (rst_n == 1'b0)
div_cnt <= 5'd0;
else if(div_cnt == H_DIV_CYC)
div_cnt <= 5'd0;
else
div_cnt <= div_cnt + 1'b1;
end
always @(posedge sclk or negedge rst_n)
begin
if(rst_n == 1'b0)
clk_p <= 1'b0;
else if(div_cnt == H_DIV_CYC)
clk_p <= ~clk_p;
end
assign clk_n = ~clk_p;
always @(posedge sclk or negedge rst_n)
begin
if(rst_n == 1'b0)
pose_flag <= 1'b0;
else if(clk_p == 1'b0 && div_cnt == H_DIV_CYC)
pose_flag <= 1'b1;
else pose_flag <= 1'b0;
end
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
wait_cnt <= 4'd0;
else if (state == WAIT && pose_flag == 1'b1)
wait_cnt <= wait_cnt + 1'b1;
else if(state != WAIT)
wait_cnt <= 4'd0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
state <= IDLE;
else case(state)
IDLE: if(work_en == 1'b1)
state <= WAIT;
WAIT: if(wait_cnt[3] == 1'b1)
state <= R_MEM;
R_MEM: state <= W_REG;
W_REG:if((shift_cnt == 4'd15) && (pose_flag == 1'b1 )&& (data_end != 1'b1))
state <= WAIT;
else if((shift_cnt == 4'd15) && (pose_flag == 1'b1 )&& (data_end == 1'b1))
state <= STOP;
STOP: state <= STOP;
default: state <= IDLE;
endcase
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
shift_cnt <= 4'd0;
else if(state == W_REG && pose_flag == 1'b1)
shift_cnt <= shift_cnt + 1'b1;
else if(state != W_REG)
shift_cnt <= 4'd0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
r_addr <= 4'd0;
else if(state == R_MEM)
r_addr <= r_addr + 1'b1;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
data_end <= 5'd0;
else if(state == R_MEM && (&r_addr) == 1'b1)
data_end <= 1'b1;
assign wren = 1'b0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
shift_buf <= 16'd0;
else if(state == R_MEM)
shift_buf <= r_data;
else if(state == W_REG && pose_flag == 1'b1)
shift_buf <= {shift_buf[14:0],1'b1};
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
sdi <= 1'b0;
else if(state == W_REG)
sdi <= shift_buf[15];
else if(state != W_REG)
sdi <= 1'b0;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
csn <= 1'b1;
else if(state == W_REG)
csn <= 1'b0;
else
csn <= 1'b1;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
tck <= 1'b0;
else if(state == W_REG)
tck <= clk_n;
else
tck <= 1'b0;
assign spi_clk = tck;
assign spi_csn = csn;
assign spi_sdi = sdi;
always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
conf_end <= 1'b0;
else if(state == STOP)
conf_end <= 1'b1;
ram_16_32_sr ram_16_32_sr_inst (
.address ( r_addr ),
.clock ( sclk ),
.data ( 16'd0 ),
.wren ( wren ),
.q ( r_data )
);
endmodule | 0 |
140,715 | data/full_repos/permissive/90862816/Project/SPI/sim/tb_spi.v | 90,862,816 | tb_spi.v | v | 60 | 154 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbd in position 408: invalid start byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/SPI/sim/tb_spi.v:13: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/SPI/sim/tb_spi.v:19: Unsupported: Ignoring delay on this delayed statement.\n #150;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90862816/Project/SPI/sim/tb_spi.v:27: Unsupported: Ignoring delay on this delayed statement.\nalways #10 sclk = ~ sclk;\n ^\n%Error: data/full_repos/permissive/90862816/Project/SPI/sim/tb_spi.v:49: syntax error, unexpected \'@\'\n @(posedge spi_clk);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,490 | module | module tb_spi;
reg sclk,rst_n;
reg work_en;
wire spi_clk,spi_csn,spi_sdi;
reg [15:0] send_mem[31:0];
reg [15:0] shift_buf;
initial begin
rst_n = 0;
sclk = 0;
#100;
rst_n = 1;
end
initial begin
work_en = 0;
#150;
work_en = 1;
end
initial begin
$readmemb("dac_ini_16_32.mif",send_mem);
end
always #10 sclk = ~ sclk;
initial begin
rec_spi();
end
spi_ctrl spi_ctrl_inst(
.sclk (sclk),
.rst_n (rst_n),
.work_en (work_en),
.conf_end (conf_end),
.spi_clk (spi_clk),
.spi_sdi (spi_sdi),
.spi_csn (spi_csn),
.spi_sdo ()
);
task rec_spi();
integer i,j;
begin
for(i=0;i<32;i=i+1)begin
for(j=0;j<16;j=j+1)begin
@(posedge spi_clk);
shift_buf = {shift_buf[14:0],spi_sdi};
if(j==15 && shift_buf == send_mem[i])
$display("ok data index is %d rec_d=%d send_d=%d",i,shift_buf,send_mem[i]);
else if(j == 15)
$display("error");
end
end
end
endtask
endmodule | module tb_spi; |
reg sclk,rst_n;
reg work_en;
wire spi_clk,spi_csn,spi_sdi;
reg [15:0] send_mem[31:0];
reg [15:0] shift_buf;
initial begin
rst_n = 0;
sclk = 0;
#100;
rst_n = 1;
end
initial begin
work_en = 0;
#150;
work_en = 1;
end
initial begin
$readmemb("dac_ini_16_32.mif",send_mem);
end
always #10 sclk = ~ sclk;
initial begin
rec_spi();
end
spi_ctrl spi_ctrl_inst(
.sclk (sclk),
.rst_n (rst_n),
.work_en (work_en),
.conf_end (conf_end),
.spi_clk (spi_clk),
.spi_sdi (spi_sdi),
.spi_csn (spi_csn),
.spi_sdo ()
);
task rec_spi();
integer i,j;
begin
for(i=0;i<32;i=i+1)begin
for(j=0;j<16;j=j+1)begin
@(posedge spi_clk);
shift_buf = {shift_buf[14:0],spi_sdi};
if(j==15 && shift_buf == send_mem[i])
$display("ok data index is %d rec_d=%d send_d=%d",i,shift_buf,send_mem[i]);
else if(j == 15)
$display("error");
end
end
end
endtask
endmodule | 0 |
140,717 | data/full_repos/permissive/91168366/arbiter_tb.v | 91,168,366 | arbiter_tb.v | v | 40 | 29 | [] | [] | [] | null | line:32: before: "$" | null | 1: b'%Error: data/full_repos/permissive/91168366/arbiter_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91168366/arbiter_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,arbiter_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91168366/arbiter_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91168366/arbiter_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish();\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/arbiter_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,589 | module | module arbiter_tb();
reg clock;
reg reset;
reg [3:0] request;
wire [3:0] grant;
round_robin_4 rr
(
.clock(clock),
.reset(reset),
.request(request),
.grant(grant)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,arbiter_tb);
end
initial
begin
clock = 0;
reset = 1;
request = 0;
#20 reset = 0;
request = 5;
#20 $finish();
end
always
#5 clock = ~clock;
endmodule | module arbiter_tb(); |
reg clock;
reg reset;
reg [3:0] request;
wire [3:0] grant;
round_robin_4 rr
(
.clock(clock),
.reset(reset),
.request(request),
.grant(grant)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,arbiter_tb);
end
initial
begin
clock = 0;
reset = 1;
request = 0;
#20 reset = 0;
request = 5;
#20 $finish();
end
always
#5 clock = ~clock;
endmodule | 12 |
140,721 | data/full_repos/permissive/91168366/gmii.v | 91,168,366 | gmii.v | v | 44 | 38 | [] | [] | [] | [(1, 43)] | null | data/verilator_xmls/2d3986b5-73f8-4859-8ed5-dc2f35191a04.xml | null | 309,592 | module | module gmii
(
input wire reset,
input wire clock_125MHz,
output wire phy_tx_er,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_gtx_clk,
input wire phy_col,
input wire [7:0] phy_rxd,
input wire phy_rx_er,
input wire phy_rx_clk,
input wire phy_crs,
input wire phy_rx_dv,
input wire mac_tx_er,
input wire [7:0] mac_txd,
input wire mac_tx_en,
output wire mac_tx_clk,
output wire mac_col,
output wire [7:0] mac_rxd,
output wire mac_rx_er,
output wire mac_rx_clk,
output wire mac_crs,
output wire mac_rx_dv
);
assign phy_tx_er = mac_tx_er;
assign phy_txd = mac_txd;
assign phy_tx_en = mac_tx_en;
assign phy_gtx_clk = clock_125MHz;
assign mac_col = phy_col;
assign mac_rxd = phy_rxd;
assign mac_rx_er = phy_rx_er;
assign mac_rx_clk = phy_rx_clk;
assign mac_crs = phy_crs;
assign mac_rx_dv = phy_rx_dv;
assign mac_tx_clk = clock_125MHz;
endmodule | module gmii
(
input wire reset,
input wire clock_125MHz,
output wire phy_tx_er,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_gtx_clk,
input wire phy_col,
input wire [7:0] phy_rxd,
input wire phy_rx_er,
input wire phy_rx_clk,
input wire phy_crs,
input wire phy_rx_dv,
input wire mac_tx_er,
input wire [7:0] mac_txd,
input wire mac_tx_en,
output wire mac_tx_clk,
output wire mac_col,
output wire [7:0] mac_rxd,
output wire mac_rx_er,
output wire mac_rx_clk,
output wire mac_crs,
output wire mac_rx_dv
); |
assign phy_tx_er = mac_tx_er;
assign phy_txd = mac_txd;
assign phy_tx_en = mac_tx_en;
assign phy_gtx_clk = clock_125MHz;
assign mac_col = phy_col;
assign mac_rxd = phy_rxd;
assign mac_rx_er = phy_rx_er;
assign mac_rx_clk = phy_rx_clk;
assign mac_crs = phy_crs;
assign mac_rx_dv = phy_rx_dv;
assign mac_tx_clk = clock_125MHz;
endmodule | 12 |
140,723 | data/full_repos/permissive/91168366/priority_encoder.v | 91,168,366 | priority_encoder.v | v | 25 | 46 | [] | [] | [] | [(1, 24)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91168366/priority_encoder.v:17: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'out\' generates 4 bits.\n : ... In instance priority_encoder\n if(in[i] && !out)\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 309,594 | module | module priority_encoder
# (
parameter NO_INPUTS = 4
)(
input wire enable,
input wire [NO_INPUTS-1:0] in,
output reg [NO_INPUTS-1:0] out
);
integer i;
always @(*)
if (enable)
begin
for (i = 0; i < NO_INPUTS; i = i + 1)
begin
if(in[i] && !out)
out = 1 << i;
end
end
else
out = 0;
endmodule | module priority_encoder
# (
parameter NO_INPUTS = 4
)(
input wire enable,
input wire [NO_INPUTS-1:0] in,
output reg [NO_INPUTS-1:0] out
); |
integer i;
always @(*)
if (enable)
begin
for (i = 0; i < NO_INPUTS; i = i + 1)
begin
if(in[i] && !out)
out = 1 << i;
end
end
else
out = 0;
endmodule | 12 |
140,724 | data/full_repos/permissive/91168366/random.v | 91,168,366 | random.v | v | 62 | 92 | [] | [] | [] | [(1, 59)] | null | data/verilator_xmls/ed0785ef-68c7-4534-a958-b04d80c14449.xml | null | 309,595 | module | module random_gen(
input reset,
input clock,
input init,
input [3:0] retry_count,
output reg trigger
);
reg [9:0] random_sequence;
reg [9:0] random;
reg [9:0] random_counter;
reg [7:0] slot_time_counter;
always @ (posedge clock)
if (reset)
random_sequence <= 0;
else
random_sequence <= {random_sequence[8:0],~(random_sequence[2]^random_sequence[9])};
always @ (*)
case (retry_count)
4'h0 : random = {9'b0, random_sequence[0]};
4'h1 : random = {8'b0, random_sequence[1:0]};
4'h2 : random = {7'b0, random_sequence[2:0]};
4'h3 : random = {6'b0, random_sequence[3:0]};
4'h4 : random = {5'b0, random_sequence[4:0]};
4'h5 : random = {4'b0, random_sequence[5:0]};
4'h6 : random = {3'b0, random_sequence[6:0]};
4'h7 : random = {2'b0, random_sequence[7:0]};
4'h8 : random = {1'b0, random_sequence[8:0]};
4'h9 : random = { random_sequence[9:0]};
default : random = { random_sequence[9:0]};
endcase
always @ (posedge clock)
if (reset)
slot_time_counter <= 0;
else if(init)
slot_time_counter <= 0;
else if(!trigger)
slot_time_counter <= slot_time_counter + 1;
always @ (posedge clock)
if (reset)
random_counter <= 0;
else if (init)
random_counter <= random;
else if (random_counter != 0 && slot_time_counter == 255)
random_counter <= random_counter - 1;
always @ (posedge clock)
if (reset)
trigger <= 1;
else if (init)
trigger <= 0;
else if (random_counter == 0)
trigger <= 1;
endmodule | module random_gen(
input reset,
input clock,
input init,
input [3:0] retry_count,
output reg trigger
); |
reg [9:0] random_sequence;
reg [9:0] random;
reg [9:0] random_counter;
reg [7:0] slot_time_counter;
always @ (posedge clock)
if (reset)
random_sequence <= 0;
else
random_sequence <= {random_sequence[8:0],~(random_sequence[2]^random_sequence[9])};
always @ (*)
case (retry_count)
4'h0 : random = {9'b0, random_sequence[0]};
4'h1 : random = {8'b0, random_sequence[1:0]};
4'h2 : random = {7'b0, random_sequence[2:0]};
4'h3 : random = {6'b0, random_sequence[3:0]};
4'h4 : random = {5'b0, random_sequence[4:0]};
4'h5 : random = {4'b0, random_sequence[5:0]};
4'h6 : random = {3'b0, random_sequence[6:0]};
4'h7 : random = {2'b0, random_sequence[7:0]};
4'h8 : random = {1'b0, random_sequence[8:0]};
4'h9 : random = { random_sequence[9:0]};
default : random = { random_sequence[9:0]};
endcase
always @ (posedge clock)
if (reset)
slot_time_counter <= 0;
else if(init)
slot_time_counter <= 0;
else if(!trigger)
slot_time_counter <= slot_time_counter + 1;
always @ (posedge clock)
if (reset)
random_counter <= 0;
else if (init)
random_counter <= random;
else if (random_counter != 0 && slot_time_counter == 255)
random_counter <= random_counter - 1;
always @ (posedge clock)
if (reset)
trigger <= 1;
else if (init)
trigger <= 0;
else if (random_counter == 0)
trigger <= 1;
endmodule | 12 |
140,726 | data/full_repos/permissive/91168366/rmii.v | 91,168,366 | rmii.v | v | 103 | 46 | [] | [] | [] | [(1, 102)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/91168366/rmii.v:28: Signal definition not found, creating implicitly: \'phy_tx_er\'\n : ... Suggested alternative: \'phy_tx_en\'\nassign phy_tx_er = mac_tx_er;\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91168366/rmii.v:35: Cannot find file containing module: \'clock_divider\'\nclock_divider #(.DIVIDER(4)) clk_div\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/91168366,data/full_repos/permissive/91168366/clock_divider\n data/full_repos/permissive/91168366,data/full_repos/permissive/91168366/clock_divider.v\n data/full_repos/permissive/91168366,data/full_repos/permissive/91168366/clock_divider.sv\n clock_divider\n clock_divider.v\n clock_divider.sv\n obj_dir/clock_divider\n obj_dir/clock_divider.v\n obj_dir/clock_divider.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 309,597 | module | module rmii
(
input wire reset,
input wire phy_ref_clk,
output reg [1:0] phy_txd,
output wire phy_tx_en,
input wire [1:0] phy_rxd,
input wire phy_rx_er,
input wire phy_crs_dv,
input wire mac_tx_er,
input wire [7:0] mac_txd,
input wire mac_tx_en,
output wire mac_tx_clk,
output wire mac_col,
output reg [7:0] mac_rxd,
output wire mac_rx_er,
output wire mac_rx_clk,
output wire mac_crs,
output wire mac_rx_dv
);
reg [1:0] tx_index;
reg [1:0] rx_index;
assign phy_tx_er = mac_tx_er;
assign phy_tx_en = mac_tx_en;
assign mac_col = phy_crs_dv & mac_tx_en;
assign mac_rx_er = phy_rx_er;
assign mac_crs = phy_crs_dv;
assign mac_rx_dv = phy_crs_dv;
clock_divider #(.DIVIDER(4)) clk_div
(
.reset(reset),
.clock_in(phy_ref_clk),
.clock_out(mac_tx_clk)
);
assign mac_rx_clk = mac_tx_clk;
always @(posedge phy_ref_clk)
begin
if (reset)
begin
tx_index <= 0;
end
else if (mac_tx_en && tx_index < 3)
begin
tx_index <= tx_index + 1;
end
else
begin
tx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
phy_txd <= 0;
end
else
begin
phy_txd <= mac_txd[tx_index*2+:2];
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
rx_index <= 0;
end
else if (phy_crs_dv && rx_index < 3)
begin
rx_index <= rx_index + 1;
end
else
begin
rx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
mac_rxd <= 0;
end
else
begin
mac_rxd[rx_index*2+:2] <= phy_rxd;
end
end
endmodule | module rmii
(
input wire reset,
input wire phy_ref_clk,
output reg [1:0] phy_txd,
output wire phy_tx_en,
input wire [1:0] phy_rxd,
input wire phy_rx_er,
input wire phy_crs_dv,
input wire mac_tx_er,
input wire [7:0] mac_txd,
input wire mac_tx_en,
output wire mac_tx_clk,
output wire mac_col,
output reg [7:0] mac_rxd,
output wire mac_rx_er,
output wire mac_rx_clk,
output wire mac_crs,
output wire mac_rx_dv
); |
reg [1:0] tx_index;
reg [1:0] rx_index;
assign phy_tx_er = mac_tx_er;
assign phy_tx_en = mac_tx_en;
assign mac_col = phy_crs_dv & mac_tx_en;
assign mac_rx_er = phy_rx_er;
assign mac_crs = phy_crs_dv;
assign mac_rx_dv = phy_crs_dv;
clock_divider #(.DIVIDER(4)) clk_div
(
.reset(reset),
.clock_in(phy_ref_clk),
.clock_out(mac_tx_clk)
);
assign mac_rx_clk = mac_tx_clk;
always @(posedge phy_ref_clk)
begin
if (reset)
begin
tx_index <= 0;
end
else if (mac_tx_en && tx_index < 3)
begin
tx_index <= tx_index + 1;
end
else
begin
tx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
phy_txd <= 0;
end
else
begin
phy_txd <= mac_txd[tx_index*2+:2];
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
rx_index <= 0;
end
else if (phy_crs_dv && rx_index < 3)
begin
rx_index <= rx_index + 1;
end
else
begin
rx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
mac_rxd <= 0;
end
else
begin
mac_rxd[rx_index*2+:2] <= phy_rxd;
end
end
endmodule | 12 |
140,729 | data/full_repos/permissive/91168366/station_management_tb.v | 91,168,366 | station_management_tb.v | v | 90 | 43 | [] | [] | [] | null | line:62: before: "for" | null | 1: b'%Error: data/full_repos/permissive/91168366/station_management_tb.v:40: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91168366/station_management_tb.v:41: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,station_management_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91168366/station_management_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91168366/station_management_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #20 begin_transaction = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/station_management_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #10 begin_transaction = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/station_management_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #490\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/station_management_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/station_management_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock;\n ^\n%Error: data/full_repos/permissive/91168366/station_management_tb.v:77: syntax error, unexpected \';\', expecting IDENTIFIER\n input bit;\n ^\n%Error: data/full_repos/permissive/91168366/station_management_tb.v:79: syntax error, unexpected \';\', expecting "\'{"\n mdi = bit;\n ^\n%Error: data/full_repos/permissive/91168366/station_management_tb.v:86: syntax error, unexpected \'@\'\n @(posedge mdc);\n ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,602 | module | module station_management_tb ();
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(mdi),
.mdo(mdo),
.mode(mode),
.begin_transaction(begin_transaction),
.phy_address(phy_address),
.reg_address(reg_address),
.data_in(data_in),
.data_out(data_out)
);
integer i;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,station_management_tb);
end
initial
begin
mdi = 0;
reset = 1;
clock = 1;
mode = 0;
begin_transaction = 0;
phy_address = 5'b00001;
reg_address = 5'b00010;
data_in = 16'hFEDC;
#20 reset = 0;
#20 begin_transaction = 1;
#10 begin_transaction = 0;
#490
for (i=0; i<16; i = i + 1)
begin
reading_bit((i%2)? 1'b1 : 1'b0);
end
mdi = 0;
#50
$finish();
end
always
#5 clock = ~clock;
task reading_bit;
input bit;
begin
mdi = bit;
@(posedge mdc);
end
endtask
task writing_bit;
begin
@(posedge mdc);
end
endtask
endmodule | module station_management_tb (); |
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(mdi),
.mdo(mdo),
.mode(mode),
.begin_transaction(begin_transaction),
.phy_address(phy_address),
.reg_address(reg_address),
.data_in(data_in),
.data_out(data_out)
);
integer i;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,station_management_tb);
end
initial
begin
mdi = 0;
reset = 1;
clock = 1;
mode = 0;
begin_transaction = 0;
phy_address = 5'b00001;
reg_address = 5'b00010;
data_in = 16'hFEDC;
#20 reset = 0;
#20 begin_transaction = 1;
#10 begin_transaction = 0;
#490
for (i=0; i<16; i = i + 1)
begin
reading_bit((i%2)? 1'b1 : 1'b0);
end
mdi = 0;
#50
$finish();
end
always
#5 clock = ~clock;
task reading_bit;
input bit;
begin
mdi = bit;
@(posedge mdc);
end
endtask
task writing_bit;
begin
@(posedge mdc);
end
endtask
endmodule | 12 |
140,730 | data/full_repos/permissive/91168366/MAC/rtl/tx_sm.v | 91,168,366 | tx_sm.v | v | 277 | 155 | [] | [] | [] | [(1, 276)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/tx_sm.v:77: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fifo_count\' generates 7 bits.\n : ... In instance tx_sm\n else if ((mode == FULL_DUPLEX && fifo_count) || (mode == HALF_DUPLEX && !carrier_sense && fifo_count))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/tx_sm.v:77: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fifo_count\' generates 7 bits.\n : ... In instance tx_sm\n else if ((mode == FULL_DUPLEX && fifo_count) || (mode == HALF_DUPLEX && !carrier_sense && fifo_count))\n ^~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/tx_sm.v:256: Cannot find file containing module: \'crc\'\ncrc U_crc(\n^~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl,data/full_repos/permissive/91168366/crc\n data/full_repos/permissive/91168366/MAC/rtl,data/full_repos/permissive/91168366/crc.v\n data/full_repos/permissive/91168366/MAC/rtl,data/full_repos/permissive/91168366/crc.sv\n crc\n crc.v\n crc.sv\n obj_dir/crc\n obj_dir/crc.v\n obj_dir/crc.sv\n%Error: data/full_repos/permissive/91168366/MAC/rtl/tx_sm.v:268: Cannot find file containing module: \'random_gen\'\nrandom_gen U_random_gen(\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 309,604 | module | module tx_sm #(
parameter STATE_DEFER = 4'h0,
parameter STATE_IFG = 4'h1,
parameter STATE_IDLE = 4'h2,
parameter STATE_PREAMBLE = 4'h3,
parameter STATE_SFD = 4'h4,
parameter STATE_DATA = 4'h5,
parameter STATE_PAD = 4'h6,
parameter STATE_JAM = 4'h7,
parameter STATE_BACKOFF = 4'h8,
parameter STATE_FCS = 4'h9,
parameter STATE_JAM_DROP = 4'hA,
parameter STATE_NEXT = 4'hB
)(
input wire reset,
input wire clock,
input wire [7:0] fifo_data,
output reg fifo_data_read,
input wire fifo_data_start,
input wire fifo_data_end,
input wire [6:0] fifo_count,
output reg fifo_retry,
input wire mode,
input wire carrier_sense,
input wire collision,
output reg tx_enable,
output reg [7:0] tx_data
);
localparam HALF_DUPLEX = 0;
localparam FULL_DUPLEX = 1;
reg [3:0] state;
reg [3:0] next_state;
reg [7:0] frame_length_count;
reg [5:0] padding_length_count;
reg [4:0] jam_length_count;
reg [3:0] inter_frame_gap_count;
reg [3:0] preamble_count;
reg [3:0] retry_count;
reg crc_init;
reg crc_enable;
reg crc_read;
wire [7:0] crc_out;
wire crc_end;
wire crc_error;
reg random_init;
wire random_trigger;
always @(posedge clock or posedge reset)
if (reset)
state <= STATE_DEFER;
else
state <= next_state;
always @ (*)
case (state)
STATE_DEFER:
if ((mode == FULL_DUPLEX) || (mode == HALF_DUPLEX && !carrier_sense))
next_state = STATE_IFG;
STATE_IFG:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && inter_frame_gap_count == 12-4) || (mode == HALF_DUPLEX && !carrier_sense && inter_frame_gap_count==12-4))
next_state = STATE_IDLE;
STATE_IDLE:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && fifo_count) || (mode == HALF_DUPLEX && !carrier_sense && fifo_count))
next_state = STATE_PREAMBLE;
STATE_PREAMBLE:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if ((mode == FULL_DUPLEX && preamble_count == 6) || (mode == HALF_DUPLEX && !collision && preamble_count == 6))
next_state = STATE_SFD;
STATE_SFD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else
next_state = STATE_DATA;
STATE_DATA:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (fifo_data_end && frame_length_count >= 59 )
next_state = STATE_FCS;
else if (fifo_data_end)
next_state = STATE_PAD;
STATE_PAD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (frame_length_count >= 59)
next_state = STATE_FCS;
STATE_JAM:
if (retry_count <= 2 && jam_length_count == 16)
next_state = STATE_BACKOFF;
else if (retry_count > 2)
next_state = STATE_JAM_DROP;
STATE_BACKOFF:
if (random_trigger)
next_state = STATE_DEFER;
STATE_FCS:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (crc_end)
next_state = STATE_NEXT;
STATE_JAM_DROP:
if (fifo_data_end)
next_state = STATE_NEXT;
STATE_NEXT:
next_state = STATE_DEFER;
default:
next_state = STATE_DEFER;
endcase
always @(posedge clock or posedge reset)
if (reset)
frame_length_count <= 0;
else if (state == STATE_DEFER)
frame_length_count <= 0;
else if (state == STATE_DATA || state == STATE_PAD)
frame_length_count <= frame_length_count+1;
always @(posedge clock or posedge reset)
if (reset)
padding_length_count <=0;
else if (state != STATE_PAD)
padding_length_count <= 0;
else
padding_length_count <= padding_length_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
jam_length_count <= 0;
else if (state != STATE_JAM)
jam_length_count <= 0;
else
jam_length_count <= jam_length_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
inter_frame_gap_count <= 0;
else if (state != STATE_IFG)
inter_frame_gap_count <= 0;
else
inter_frame_gap_count <= inter_frame_gap_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
preamble_count <= 0;
else if (state != STATE_PREAMBLE)
preamble_count <= 0;
else
preamble_count <= preamble_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
retry_count <= 0;
else if (state == STATE_NEXT)
retry_count <= 0;
else if (state == STATE_JAM && next_state == STATE_BACKOFF)
retry_count <= retry_count + 1;
always @ (*)
if (state == STATE_DATA ||
state == STATE_SFD ||
state == STATE_JAM_DROP)
fifo_data_read = 1;
else
fifo_data_read = 0;
always @ (state)
if (state == STATE_JAM)
fifo_retry = 1;
else
fifo_retry = 0;
always @(state)
if (state == STATE_PREAMBLE ||
state == STATE_SFD ||
state == STATE_DATA ||
state == STATE_FCS ||
state == STATE_PAD ||
state == STATE_JAM )
tx_enable <= 1;
else
tx_enable <= 0;
always @(*)
case (state)
STATE_PREAMBLE:
tx_data = 8'h55;
STATE_SFD:
tx_data = 8'hD5;
STATE_DATA:
tx_data = fifo_data;
STATE_PAD:
tx_data = 8'h00;
STATE_JAM:
tx_data = 8'h01;
STATE_FCS:
tx_data = crc_out;
default:
tx_data = 8'b00;
endcase
always @(state)
if (state == STATE_SFD)
crc_init = 1;
else
crc_init = 0;
always @(state)
if (state == STATE_DATA || state == STATE_PAD)
crc_enable = 1;
else
crc_enable = 0;
always @(state)
if (state == STATE_FCS)
crc_read = 1;
else
crc_read = 0;
always @(state or next_state)
if (state == STATE_JAM && next_state == STATE_BACKOFF)
random_init = 1;
else
random_init = 0;
crc U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(tx_data),
.data_enable(crc_enable),
.read(crc_read),
.crc_out(crc_out),
.crc_end(crc_end),
.error(crc_error)
);
random_gen U_random_gen(
.reset(reset),
.clock(clock),
.init(random_init),
.retry_count(retry_count),
.trigger(random_trigger)
);
endmodule | module tx_sm #(
parameter STATE_DEFER = 4'h0,
parameter STATE_IFG = 4'h1,
parameter STATE_IDLE = 4'h2,
parameter STATE_PREAMBLE = 4'h3,
parameter STATE_SFD = 4'h4,
parameter STATE_DATA = 4'h5,
parameter STATE_PAD = 4'h6,
parameter STATE_JAM = 4'h7,
parameter STATE_BACKOFF = 4'h8,
parameter STATE_FCS = 4'h9,
parameter STATE_JAM_DROP = 4'hA,
parameter STATE_NEXT = 4'hB
)(
input wire reset,
input wire clock,
input wire [7:0] fifo_data,
output reg fifo_data_read,
input wire fifo_data_start,
input wire fifo_data_end,
input wire [6:0] fifo_count,
output reg fifo_retry,
input wire mode,
input wire carrier_sense,
input wire collision,
output reg tx_enable,
output reg [7:0] tx_data
); |
localparam HALF_DUPLEX = 0;
localparam FULL_DUPLEX = 1;
reg [3:0] state;
reg [3:0] next_state;
reg [7:0] frame_length_count;
reg [5:0] padding_length_count;
reg [4:0] jam_length_count;
reg [3:0] inter_frame_gap_count;
reg [3:0] preamble_count;
reg [3:0] retry_count;
reg crc_init;
reg crc_enable;
reg crc_read;
wire [7:0] crc_out;
wire crc_end;
wire crc_error;
reg random_init;
wire random_trigger;
always @(posedge clock or posedge reset)
if (reset)
state <= STATE_DEFER;
else
state <= next_state;
always @ (*)
case (state)
STATE_DEFER:
if ((mode == FULL_DUPLEX) || (mode == HALF_DUPLEX && !carrier_sense))
next_state = STATE_IFG;
STATE_IFG:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && inter_frame_gap_count == 12-4) || (mode == HALF_DUPLEX && !carrier_sense && inter_frame_gap_count==12-4))
next_state = STATE_IDLE;
STATE_IDLE:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && fifo_count) || (mode == HALF_DUPLEX && !carrier_sense && fifo_count))
next_state = STATE_PREAMBLE;
STATE_PREAMBLE:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if ((mode == FULL_DUPLEX && preamble_count == 6) || (mode == HALF_DUPLEX && !collision && preamble_count == 6))
next_state = STATE_SFD;
STATE_SFD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else
next_state = STATE_DATA;
STATE_DATA:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (fifo_data_end && frame_length_count >= 59 )
next_state = STATE_FCS;
else if (fifo_data_end)
next_state = STATE_PAD;
STATE_PAD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (frame_length_count >= 59)
next_state = STATE_FCS;
STATE_JAM:
if (retry_count <= 2 && jam_length_count == 16)
next_state = STATE_BACKOFF;
else if (retry_count > 2)
next_state = STATE_JAM_DROP;
STATE_BACKOFF:
if (random_trigger)
next_state = STATE_DEFER;
STATE_FCS:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (crc_end)
next_state = STATE_NEXT;
STATE_JAM_DROP:
if (fifo_data_end)
next_state = STATE_NEXT;
STATE_NEXT:
next_state = STATE_DEFER;
default:
next_state = STATE_DEFER;
endcase
always @(posedge clock or posedge reset)
if (reset)
frame_length_count <= 0;
else if (state == STATE_DEFER)
frame_length_count <= 0;
else if (state == STATE_DATA || state == STATE_PAD)
frame_length_count <= frame_length_count+1;
always @(posedge clock or posedge reset)
if (reset)
padding_length_count <=0;
else if (state != STATE_PAD)
padding_length_count <= 0;
else
padding_length_count <= padding_length_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
jam_length_count <= 0;
else if (state != STATE_JAM)
jam_length_count <= 0;
else
jam_length_count <= jam_length_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
inter_frame_gap_count <= 0;
else if (state != STATE_IFG)
inter_frame_gap_count <= 0;
else
inter_frame_gap_count <= inter_frame_gap_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
preamble_count <= 0;
else if (state != STATE_PREAMBLE)
preamble_count <= 0;
else
preamble_count <= preamble_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
retry_count <= 0;
else if (state == STATE_NEXT)
retry_count <= 0;
else if (state == STATE_JAM && next_state == STATE_BACKOFF)
retry_count <= retry_count + 1;
always @ (*)
if (state == STATE_DATA ||
state == STATE_SFD ||
state == STATE_JAM_DROP)
fifo_data_read = 1;
else
fifo_data_read = 0;
always @ (state)
if (state == STATE_JAM)
fifo_retry = 1;
else
fifo_retry = 0;
always @(state)
if (state == STATE_PREAMBLE ||
state == STATE_SFD ||
state == STATE_DATA ||
state == STATE_FCS ||
state == STATE_PAD ||
state == STATE_JAM )
tx_enable <= 1;
else
tx_enable <= 0;
always @(*)
case (state)
STATE_PREAMBLE:
tx_data = 8'h55;
STATE_SFD:
tx_data = 8'hD5;
STATE_DATA:
tx_data = fifo_data;
STATE_PAD:
tx_data = 8'h00;
STATE_JAM:
tx_data = 8'h01;
STATE_FCS:
tx_data = crc_out;
default:
tx_data = 8'b00;
endcase
always @(state)
if (state == STATE_SFD)
crc_init = 1;
else
crc_init = 0;
always @(state)
if (state == STATE_DATA || state == STATE_PAD)
crc_enable = 1;
else
crc_enable = 0;
always @(state)
if (state == STATE_FCS)
crc_read = 1;
else
crc_read = 0;
always @(state or next_state)
if (state == STATE_JAM && next_state == STATE_BACKOFF)
random_init = 1;
else
random_init = 0;
crc U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(tx_data),
.data_enable(crc_enable),
.read(crc_read),
.crc_out(crc_out),
.crc_end(crc_end),
.error(crc_error)
);
random_gen U_random_gen(
.reset(reset),
.clock(clock),
.init(random_init),
.retry_count(retry_count),
.trigger(random_trigger)
);
endmodule | 12 |
140,734 | data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_1.v | 91,168,366 | crc_tb_ETHERNET_1.v | v | 28 | 64 | [] | [] | [] | null | line:55: before: "(" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_1.v:10: Cannot find include file: dut.v\n`include "dut.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v.sv\n dut.v\n dut.v.v\n dut.v.sv\n obj_dir/dut.v\n obj_dir/dut.v.v\n obj_dir/dut.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_1.v:14: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_1.v:18: syntax error, unexpected assert\n util.assert(tempdata == 32\'hdea580d8, "CRC == 0xdea580d8");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_1.v:21: syntax error, unexpected assert\n util.assert(tempdata == 32\'h5630b33b, "CRC == 0x5630b33b");\n ^~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 309,609 | module | module crc_tb #(
parameter CRC_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter POLYNOMIAL = 32'h04C11DB7,
parameter SEED = 32'h00000000
)();
`include "dut.v"
initial
begin
#15 reset = 0;
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 32'hdea580d8, "CRC == 0xdea580d8");
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 32'h5630b33b, "CRC == 0x5630b33b");
$finish;
end
endmodule | module crc_tb #(
parameter CRC_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter POLYNOMIAL = 32'h04C11DB7,
parameter SEED = 32'h00000000
)(); |
`include "dut.v"
initial
begin
#15 reset = 0;
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 32'hdea580d8, "CRC == 0xdea580d8");
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 32'h5630b33b, "CRC == 0x5630b33b");
$finish;
end
endmodule | 12 |
140,735 | data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_2.v | 91,168,366 | crc_tb_ETHERNET_2.v | v | 37 | 64 | [] | [] | [] | null | line:64: before: "(" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_2.v:10: Cannot find include file: dut.v\n`include "dut.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v.sv\n dut.v\n dut.v.v\n dut.v.sv\n obj_dir/dut.v\n obj_dir/dut.v.v\n obj_dir/dut.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_2.v:19: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_ETHERNET_2.v:30: syntax error, unexpected assert\n util.assert(tempdata == 32\'hc704dd7b, "CRC == 0xc704dd7b");\n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 309,610 | module | module crc_tb #(
parameter CRC_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter POLYNOMIAL = 32'h04C11DB7,
parameter SEED = 32'hFFFFFFFF
)();
`include "dut.v"
reg [7:0] packet [0:95];
integer i;
integer j;
reg [7:0] temp;
initial
begin
#15 reset = 0;
$readmemh("packet.hex", packet);
for(i = 0; i < 96; i = i + 1)
begin
util.sync_write(packet[i]);
end
util.sync_read(tempdata);
util.assert(tempdata == 32'hc704dd7b, "CRC == 0xc704dd7b");
$finish;
end
endmodule | module crc_tb #(
parameter CRC_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter POLYNOMIAL = 32'h04C11DB7,
parameter SEED = 32'hFFFFFFFF
)(); |
`include "dut.v"
reg [7:0] packet [0:95];
integer i;
integer j;
reg [7:0] temp;
initial
begin
#15 reset = 0;
$readmemh("packet.hex", packet);
for(i = 0; i < 96; i = i + 1)
begin
util.sync_write(packet[i]);
end
util.sync_read(tempdata);
util.assert(tempdata == 32'hc704dd7b, "CRC == 0xc704dd7b");
$finish;
end
endmodule | 12 |
140,736 | data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_USB.v | 91,168,366 | crc_tb_USB.v | v | 28 | 42 | [] | [] | [] | null | line:55: before: "(" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_USB.v:10: Cannot find include file: dut.v\n`include "dut.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb,data/full_repos/permissive/91168366/dut.v.sv\n dut.v\n dut.v.v\n dut.v.sv\n obj_dir/dut.v\n obj_dir/dut.v.v\n obj_dir/dut.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_USB.v:14: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_USB.v:18: syntax error, unexpected assert\n util.assert(tempdata == 5\'b11000, 1);\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/crc/tb/crc_tb_USB.v:21: syntax error, unexpected assert\n util.assert(tempdata == 5\'b10001, 2);\n ^~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 309,611 | module | module crc_tb #(
parameter CRC_WIDTH = 5,
parameter DATA_WIDTH = 8,
parameter POLYNOMIAL = 5'b00101,
parameter SEED = 0
)();
`include "dut.v"
initial
begin
#15 reset = 0;
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 5'b11000, 1);
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 5'b10001, 2);
$finish;
end
endmodule | module crc_tb #(
parameter CRC_WIDTH = 5,
parameter DATA_WIDTH = 8,
parameter POLYNOMIAL = 5'b00101,
parameter SEED = 0
)(); |
`include "dut.v"
initial
begin
#15 reset = 0;
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 5'b11000, 1);
util.sync_write(8'hAA);
util.sync_read(tempdata);
util.assert(tempdata == 5'b10001, 2);
$finish;
end
endmodule | 12 |
140,737 | data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/fifo.v | 91,168,366 | fifo.v | v | 99 | 114 | [] | [] | [] | [(3, 98)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/fifo.v:38: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'count\' generates 13 bits.\n : ... In instance fifo\n if ( count && (data_in_address == data_out_address - 1 ))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/fifo.v:52: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'count\' generates 13 bits.\n : ... In instance fifo\n if ( data_out_address != data_in_address || (data_out_address == data_in_address && !count))\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,613 | module | module fifo
#(
parameter DATA_WIDTH = 8,
parameter FIFO_DEPTH = 12
)
(
input wire reset,
output reg [FIFO_DEPTH:0] count,
output reg full,
input wire [DATA_WIDTH-1:0] data_in,
input wire data_in_clock,
input wire data_in_enable,
input wire data_in_start,
input wire data_in_end,
output reg [FIFO_DEPTH-1:0] data_in_address,
input wire data_in_reset,
input wire [FIFO_DEPTH-1:0] data_in_reset_address,
output reg [DATA_WIDTH-1:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output reg data_out_start,
output reg data_out_end,
output reg [FIFO_DEPTH-1:0] data_out_address,
input wire data_out_reset,
input wire [FIFO_DEPTH-1:0] data_out_reset_address
);
reg [DATA_WIDTH + 1:0] mem[(2**FIFO_DEPTH) - 1:0];
always @(posedge data_in_clock)
begin
if ( count && (data_in_address == data_out_address - 1 ))
begin
full <= 1;
end
else
begin
full <= 0;
end
end
always @(posedge data_in_clock)
begin
if( data_in_enable )
begin
if ( data_out_address != data_in_address || (data_out_address == data_in_address && !count))
mem[ data_in_address ]<= { data_in, data_in_start, data_in_end };
end
end
always @(posedge data_in_clock or posedge reset)
begin
if( reset )
begin
data_in_address <= 0;
count <= 0;
end
else if (data_in_reset)
begin
count = count - (data_in_address - data_in_reset_address);
data_in_address = data_in_reset_address;
end
else
begin
if( data_in_enable )
begin
count <= count + 1;
data_in_address <= data_in_address + 1;
end
end
end
always @(posedge data_out_clock or posedge reset)
begin
if (reset)
begin
data_out <= 0;
data_out_address <= 0;
end
else if (data_out_reset)
begin
data_out_address <= data_out_reset_address;
end
else if (data_out_enable)
begin
{ data_out, data_out_start, data_out_end } <= mem[data_out_address];
data_out_address <= data_out_address + 1;
count <= count - 1;
end
end
endmodule | module fifo
#(
parameter DATA_WIDTH = 8,
parameter FIFO_DEPTH = 12
)
(
input wire reset,
output reg [FIFO_DEPTH:0] count,
output reg full,
input wire [DATA_WIDTH-1:0] data_in,
input wire data_in_clock,
input wire data_in_enable,
input wire data_in_start,
input wire data_in_end,
output reg [FIFO_DEPTH-1:0] data_in_address,
input wire data_in_reset,
input wire [FIFO_DEPTH-1:0] data_in_reset_address,
output reg [DATA_WIDTH-1:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output reg data_out_start,
output reg data_out_end,
output reg [FIFO_DEPTH-1:0] data_out_address,
input wire data_out_reset,
input wire [FIFO_DEPTH-1:0] data_out_reset_address
); |
reg [DATA_WIDTH + 1:0] mem[(2**FIFO_DEPTH) - 1:0];
always @(posedge data_in_clock)
begin
if ( count && (data_in_address == data_out_address - 1 ))
begin
full <= 1;
end
else
begin
full <= 0;
end
end
always @(posedge data_in_clock)
begin
if( data_in_enable )
begin
if ( data_out_address != data_in_address || (data_out_address == data_in_address && !count))
mem[ data_in_address ]<= { data_in, data_in_start, data_in_end };
end
end
always @(posedge data_in_clock or posedge reset)
begin
if( reset )
begin
data_in_address <= 0;
count <= 0;
end
else if (data_in_reset)
begin
count = count - (data_in_address - data_in_reset_address);
data_in_address = data_in_reset_address;
end
else
begin
if( data_in_enable )
begin
count <= count + 1;
data_in_address <= data_in_address + 1;
end
end
end
always @(posedge data_out_clock or posedge reset)
begin
if (reset)
begin
data_out <= 0;
data_out_address <= 0;
end
else if (data_out_reset)
begin
data_out_address <= data_out_reset_address;
end
else if (data_out_enable)
begin
{ data_out, data_out_start, data_out_end } <= mem[data_out_address];
data_out_address <= data_out_address + 1;
count <= count - 1;
end
end
endmodule | 12 |
140,738 | data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v | 91,168,366 | fifo_tb.v | v | 70 | 59 | [] | [] | [] | null | line:138: before: "(" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:8: Cannot find include file: dut.v\n`include "dut.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb,data/full_repos/permissive/91168366/dut.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb,data/full_repos/permissive/91168366/dut.v.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb,data/full_repos/permissive/91168366/dut.v.sv\n dut.v\n dut.v.v\n dut.v.sv\n obj_dir/dut.v\n obj_dir/dut.v.v\n obj_dir/dut.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:19: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:29: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:34: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:40: syntax error, unexpected assert\n util.assert(tempdata == 8\'hAA, "Reading FIFO Data");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:41: syntax error, unexpected assert\n util.assert(tempstart == 1, "Reading FIFO Start");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:42: syntax error, unexpected assert\n util.assert(tempend == 0, "Reading FIFO End");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:46: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:51: syntax error, unexpected assert\n util.assert(tempdata == i, "Reading FIFO Data");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:52: syntax error, unexpected assert\n util.assert(tempstart == 0, "Reading FIFO Start");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:53: syntax error, unexpected assert\n util.assert(tempend == 0, "Reading FIFO End");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:56: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:62: syntax error, unexpected assert\n util.assert(tempdata == 8\'hAB, "Reading FIFO Data");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:63: syntax error, unexpected assert\n util.assert(tempstart == 0, "Reading FIFO Start");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/fifo/tb/fifo_tb.v:64: syntax error, unexpected assert\n util.assert(tempend == 1, "Reading FIFO End");\n ^~~~~~\n%Error: Exiting due to 15 error(s), 1 warning(s)\n' | 309,615 | module | module fifo_test();
parameter WIDTH = 8;
parameter DEPTH = 12;
`include "dut.v"
integer i;
reg [WIDTH-1:0] tempdata;
reg tempstart;
reg tempend;
initial
begin
#15 reset = 0;
fork
data_in.sync_write(8'hAA);
data_in_start.sync_write(1);
join
for ( i = 1; i < 100; i = i + 1)
begin
data_in.sync_write(i);
end
fork
data_in.sync_write(8'hAB);
data_in_end.sync_write(1);
join
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == 8'hAA, "Reading FIFO Data");
util.assert(tempstart == 1, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
for ( i = 1; i < 100; i = i + 1)
begin
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == i, "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
end
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == 8'hAB, "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 1, "Reading FIFO End");
$finish;
end
endmodule | module fifo_test(); |
parameter WIDTH = 8;
parameter DEPTH = 12;
`include "dut.v"
integer i;
reg [WIDTH-1:0] tempdata;
reg tempstart;
reg tempend;
initial
begin
#15 reset = 0;
fork
data_in.sync_write(8'hAA);
data_in_start.sync_write(1);
join
for ( i = 1; i < 100; i = i + 1)
begin
data_in.sync_write(i);
end
fork
data_in.sync_write(8'hAB);
data_in_end.sync_write(1);
join
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == 8'hAA, "Reading FIFO Data");
util.assert(tempstart == 1, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
for ( i = 1; i < 100; i = i + 1)
begin
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == i, "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
end
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == 8'hAB, "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 1, "Reading FIFO End");
$finish;
end
endmodule | 12 |
140,741 | data/full_repos/permissive/91168366/MAC/rtl/mac/rx/rx_sm.v | 91,168,366 | rx_sm.v | v | 252 | 116 | [] | [] | [] | [(1, 251)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/rx_sm.v:111: Operator ASSIGNDLY expects 40 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance rx_sm\n data <= 32\'h00000000;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/rx_sm.v:115: Operator ASSIGNDLY expects 40 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance rx_sm\n data <= 32\'h00000000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/rx_sm.v:133: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'fifo_count\' generates 13 bits.\n : ... In instance rx_sm\n else if (!fifo_count)\n ^\n%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/rx_sm.v:129: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'fifo_count\' generates 13 bits.\n : ... In instance rx_sm\n if (fifo_count && state == STATE_OK)\n ^~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/rx_sm.v:208: Cannot find file containing module: \'crc\'\ncrc #( .POLYNOMIAL(CRC_POLYNOMIAL),\n^~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/rx,data/full_repos/permissive/91168366/crc\n data/full_repos/permissive/91168366/MAC/rtl/mac/rx,data/full_repos/permissive/91168366/crc.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/rx,data/full_repos/permissive/91168366/crc.sv\n crc\n crc.v\n crc.sv\n obj_dir/crc\n obj_dir/crc.v\n obj_dir/crc.sv\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/rx_sm.v:222: Cannot find file containing module: \'fifo\'\nfifo #(\n^~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n' | 309,618 | module | module rx_sm #(
parameter STATE_IDLE = 3'h0,
parameter STATE_PREAMBLE = 3'h1,
parameter STATE_DATA = 3'h2,
parameter STATE_OK = 3'h3,
parameter STATE_DROP = 3'h4,
parameter STATE_ERROR = 3'h5,
parameter FIFO_DEPTH = 12
)(
input reset,
input clock,
input rx_data_valid,
input [7:0] rx_data,
input rx_error,
output wire [7:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output wire data_out_start,
output wire data_out_end,
output wire [FIFO_DEPTH-1:0] data_out_address,
input wire data_out_reset,
input wire [FIFO_DEPTH-1:0] data_out_reset_address,
output reg data_available,
output wire fifo_full
);
localparam CRC_RESIDUE = 32'hC704DD7B;
localparam CRC_POLYNOMIAL = 32'h04C11DB7;
localparam CRC_SEED = 32'hFFFFFFFF;
localparam MAX_SIZE = 1518;
localparam MIN_SIZE = 64;
wire [FIFO_DEPTH:0] fifo_count;
wire [FIFO_DEPTH-1:0] data_in_address;
reg [FIFO_DEPTH-1:0] data_in_reset_address;
reg start_of_frame;
reg end_of_frame;
reg error;
reg [2:0] state;
reg [2:0] next_state;
reg [15:0] frame_length_counter;
reg [15:0] data_counter;
reg data_write_enable;
reg too_long;
reg too_short;
reg crc_init;
reg data_enable;
wire [31:0] crc_out;
reg [39:0] data;
always @ (posedge reset or posedge clock)
if (reset)
state <= STATE_IDLE;
else
state <= next_state;
always @ (*)
case (state)
STATE_IDLE:
if (rx_data_valid && rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_IDLE;
STATE_PREAMBLE:
if (!rx_data_valid)
next_state = STATE_ERROR;
else if (rx_error)
next_state = STATE_DROP;
else if (rx_data == 8'hd5)
next_state = STATE_DATA;
else if (rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_DROP;
STATE_DATA:
if (!rx_data_valid && !too_short && !too_long && crc_out == CRC_RESIDUE)
next_state = STATE_OK;
else if ((!rx_data_valid && (too_short || too_long)) || (!rx_data_valid && crc_out != CRC_RESIDUE))
next_state = STATE_ERROR;
else if (fifo_full)
next_state = STATE_DROP;
else if (rx_error || too_long)
next_state = STATE_DROP;
else
next_state = STATE_DATA;
STATE_DROP:
if (!rx_data_valid)
next_state = STATE_ERROR;
else
next_state = STATE_DROP;
STATE_OK:
next_state = STATE_IDLE;
STATE_ERROR:
next_state = STATE_IDLE;
default:
next_state = STATE_IDLE;
endcase
always @(posedge clock or posedge reset)
begin
if (reset)
begin
data <= 32'h00000000;
end
else if (state == STATE_IDLE)
begin
data <= 32'h00000000;
end
else
begin
data[39-:8] <= data[31-:8];
data[31-:8] <= data[23-:8];
data[23-:8] <= data[15-:8];
data[15-:8] <= data[7-:8];
data[7-:8] <= rx_data;
end
end
always @ ( state or fifo_count )
begin
if (fifo_count && state == STATE_OK)
begin
data_available <= 1;
end
else if (!fifo_count)
begin
data_available <= 0;
end
end
always @ (posedge clock or posedge reset)
if (reset)
data_counter <= 0;
else if (state == STATE_DATA)
data_counter = data_counter + 1;
else
data_counter = 0;
always @ (data_counter or state)
if (data_counter > 4 && state == STATE_DATA && next_state == STATE_DATA)
data_write_enable = 1;
else
data_write_enable = 0;
always @(data_counter)
if (data_counter == 5)
start_of_frame = 1;
else
start_of_frame = 0;
always @(state or next_state)
if (state == STATE_DATA && next_state != STATE_DATA)
end_of_frame = 1;
else
end_of_frame = 0;
always @(state)
if (state == STATE_ERROR)
error = 1;
else
error = 0;
always @(state)
if (state == STATE_DATA)
data_enable = 1;
else
data_enable = 0;
always @(state or next_state)
if (state == STATE_PREAMBLE && next_state == STATE_DATA)
begin
crc_init <= 1;
data_in_reset_address <= data_in_address;
end
else
crc_init = 0;
always @ (posedge clock or posedge reset)
if (reset)
frame_length_counter <= 0;
else if (state == STATE_DATA)
frame_length_counter = frame_length_counter + 1;
else
frame_length_counter = 0;
always @ (frame_length_counter)
if (frame_length_counter < MIN_SIZE)
too_short = 1;
else
too_short = 0;
always @ (frame_length_counter)
if (frame_length_counter > MAX_SIZE)
too_long = 1;
else
too_long = 0;
crc #( .POLYNOMIAL(CRC_POLYNOMIAL),
.DATA_WIDTH(8),
.CRC_WIDTH(32),
.SEED(CRC_SEED))
U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(rx_data),
.data_enable(data_enable),
.crc_out(crc_out)
);
fifo #(
.DATA_WIDTH (8),
.FIFO_DEPTH (FIFO_DEPTH)
)
U_fifo (
.reset(reset),
.count(fifo_count),
.full(fifo_full),
.data_in(data[39-:8]),
.data_in_start(start_of_frame),
.data_in_end(end_of_frame),
.data_in_clock(clock),
.data_in_enable(data_write_enable),
.data_in_address(data_in_address),
.data_in_reset(error),
.data_in_reset_address(data_in_reset_address),
.data_out(data_out),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_address(data_out_address),
.data_out_reset(data_out_reset),
.data_out_reset_address(data_out_reset_address)
);
endmodule | module rx_sm #(
parameter STATE_IDLE = 3'h0,
parameter STATE_PREAMBLE = 3'h1,
parameter STATE_DATA = 3'h2,
parameter STATE_OK = 3'h3,
parameter STATE_DROP = 3'h4,
parameter STATE_ERROR = 3'h5,
parameter FIFO_DEPTH = 12
)(
input reset,
input clock,
input rx_data_valid,
input [7:0] rx_data,
input rx_error,
output wire [7:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output wire data_out_start,
output wire data_out_end,
output wire [FIFO_DEPTH-1:0] data_out_address,
input wire data_out_reset,
input wire [FIFO_DEPTH-1:0] data_out_reset_address,
output reg data_available,
output wire fifo_full
); |
localparam CRC_RESIDUE = 32'hC704DD7B;
localparam CRC_POLYNOMIAL = 32'h04C11DB7;
localparam CRC_SEED = 32'hFFFFFFFF;
localparam MAX_SIZE = 1518;
localparam MIN_SIZE = 64;
wire [FIFO_DEPTH:0] fifo_count;
wire [FIFO_DEPTH-1:0] data_in_address;
reg [FIFO_DEPTH-1:0] data_in_reset_address;
reg start_of_frame;
reg end_of_frame;
reg error;
reg [2:0] state;
reg [2:0] next_state;
reg [15:0] frame_length_counter;
reg [15:0] data_counter;
reg data_write_enable;
reg too_long;
reg too_short;
reg crc_init;
reg data_enable;
wire [31:0] crc_out;
reg [39:0] data;
always @ (posedge reset or posedge clock)
if (reset)
state <= STATE_IDLE;
else
state <= next_state;
always @ (*)
case (state)
STATE_IDLE:
if (rx_data_valid && rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_IDLE;
STATE_PREAMBLE:
if (!rx_data_valid)
next_state = STATE_ERROR;
else if (rx_error)
next_state = STATE_DROP;
else if (rx_data == 8'hd5)
next_state = STATE_DATA;
else if (rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_DROP;
STATE_DATA:
if (!rx_data_valid && !too_short && !too_long && crc_out == CRC_RESIDUE)
next_state = STATE_OK;
else if ((!rx_data_valid && (too_short || too_long)) || (!rx_data_valid && crc_out != CRC_RESIDUE))
next_state = STATE_ERROR;
else if (fifo_full)
next_state = STATE_DROP;
else if (rx_error || too_long)
next_state = STATE_DROP;
else
next_state = STATE_DATA;
STATE_DROP:
if (!rx_data_valid)
next_state = STATE_ERROR;
else
next_state = STATE_DROP;
STATE_OK:
next_state = STATE_IDLE;
STATE_ERROR:
next_state = STATE_IDLE;
default:
next_state = STATE_IDLE;
endcase
always @(posedge clock or posedge reset)
begin
if (reset)
begin
data <= 32'h00000000;
end
else if (state == STATE_IDLE)
begin
data <= 32'h00000000;
end
else
begin
data[39-:8] <= data[31-:8];
data[31-:8] <= data[23-:8];
data[23-:8] <= data[15-:8];
data[15-:8] <= data[7-:8];
data[7-:8] <= rx_data;
end
end
always @ ( state or fifo_count )
begin
if (fifo_count && state == STATE_OK)
begin
data_available <= 1;
end
else if (!fifo_count)
begin
data_available <= 0;
end
end
always @ (posedge clock or posedge reset)
if (reset)
data_counter <= 0;
else if (state == STATE_DATA)
data_counter = data_counter + 1;
else
data_counter = 0;
always @ (data_counter or state)
if (data_counter > 4 && state == STATE_DATA && next_state == STATE_DATA)
data_write_enable = 1;
else
data_write_enable = 0;
always @(data_counter)
if (data_counter == 5)
start_of_frame = 1;
else
start_of_frame = 0;
always @(state or next_state)
if (state == STATE_DATA && next_state != STATE_DATA)
end_of_frame = 1;
else
end_of_frame = 0;
always @(state)
if (state == STATE_ERROR)
error = 1;
else
error = 0;
always @(state)
if (state == STATE_DATA)
data_enable = 1;
else
data_enable = 0;
always @(state or next_state)
if (state == STATE_PREAMBLE && next_state == STATE_DATA)
begin
crc_init <= 1;
data_in_reset_address <= data_in_address;
end
else
crc_init = 0;
always @ (posedge clock or posedge reset)
if (reset)
frame_length_counter <= 0;
else if (state == STATE_DATA)
frame_length_counter = frame_length_counter + 1;
else
frame_length_counter = 0;
always @ (frame_length_counter)
if (frame_length_counter < MIN_SIZE)
too_short = 1;
else
too_short = 0;
always @ (frame_length_counter)
if (frame_length_counter > MAX_SIZE)
too_long = 1;
else
too_long = 0;
crc #( .POLYNOMIAL(CRC_POLYNOMIAL),
.DATA_WIDTH(8),
.CRC_WIDTH(32),
.SEED(CRC_SEED))
U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(rx_data),
.data_enable(data_enable),
.crc_out(crc_out)
);
fifo #(
.DATA_WIDTH (8),
.FIFO_DEPTH (FIFO_DEPTH)
)
U_fifo (
.reset(reset),
.count(fifo_count),
.full(fifo_full),
.data_in(data[39-:8]),
.data_in_start(start_of_frame),
.data_in_end(end_of_frame),
.data_in_clock(clock),
.data_in_enable(data_write_enable),
.data_in_address(data_in_address),
.data_in_reset(error),
.data_in_reset_address(data_in_reset_address),
.data_out(data_out),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_address(data_out_address),
.data_out_reset(data_out_reset),
.data_out_reset_address(data_out_reset_address)
);
endmodule | 12 |
140,743 | data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v | 91,168,366 | rx_sm_tb.v | v | 277 | 69 | [] | [] | [] | null | line:123: before: "(" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:5: Cannot find include file: dut.v\n`include "dut.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb,data/full_repos/permissive/91168366/dut.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb,data/full_repos/permissive/91168366/dut.v.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb,data/full_repos/permissive/91168366/dut.v.sv\n dut.v\n dut.v.v\n dut.v.sv\n obj_dir/dut.v\n obj_dir/dut.v.v\n obj_dir/dut.v.sv\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:17: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:18: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,rx_sm_tb,U_rx_sm);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:27: syntax error, unexpected assert\n util.assert(data_available == 0, "Data available not set");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:37: syntax error, unexpected assert\n util.assert(data_available == 1, "Data available set");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:40: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:46: syntax error, unexpected assert\n util.assert(tempdata == packet[8], "Reading FIFO Data");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:47: syntax error, unexpected assert\n util.assert(tempstart == 1, "Reading FIFO Start");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:48: syntax error, unexpected assert\n util.assert(tempend == 0, "Reading FIFO End");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:52: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:57: syntax error, unexpected assert\n util.assert(tempdata == packet[i], "Reading FIFO Data");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:58: syntax error, unexpected assert\n util.assert(tempstart == 0, "Reading FIFO Start");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:59: syntax error, unexpected assert\n util.assert(tempend == 0, "Reading FIFO End");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:62: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:68: syntax error, unexpected assert\n util.assert(tempdata == packet[99], "Reading FIFO Data");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:69: syntax error, unexpected assert\n util.assert(tempstart == 0, "Reading FIFO Start");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:70: syntax error, unexpected assert\n util.assert(tempend == 1, "Reading FIFO End");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/rx/tb/rx_sm_tb.v:72: syntax error, unexpected assert\n util.assert(data_available == 0, "Data available not set");\n ^~~~~~\n%Error: Exiting due to 18 error(s), 2 warning(s)\n' | 309,621 | module | module rx_sm_tb ();
`include "dut.v"
integer i;
integer j;
reg [7:0] packet [0:1518];
reg [7:0] tempdata;
reg tempstart;
reg tempend;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,rx_sm_tb,U_rx_sm);
end
initial
begin
#15 reset = 0;
$readmemh("packet.hex", packet);
util.assert(data_available == 0, "Data available not set");
for(i = 0; i < 104; i = i + 1)
begin
data.sync_write(packet[i]);
end
#1000
util.assert(data_available == 1, "Data available set");
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == packet[8], "Reading FIFO Data");
util.assert(tempstart == 1, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
for ( i = 9; i < 99; i = i + 1)
begin
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == packet[i], "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
end
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == packet[99], "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 1, "Reading FIFO End");
util.assert(data_available == 0, "Data available not set");
util.display();
$finish;
end
endmodule | module rx_sm_tb (); |
`include "dut.v"
integer i;
integer j;
reg [7:0] packet [0:1518];
reg [7:0] tempdata;
reg tempstart;
reg tempend;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,rx_sm_tb,U_rx_sm);
end
initial
begin
#15 reset = 0;
$readmemh("packet.hex", packet);
util.assert(data_available == 0, "Data available not set");
for(i = 0; i < 104; i = i + 1)
begin
data.sync_write(packet[i]);
end
#1000
util.assert(data_available == 1, "Data available set");
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == packet[8], "Reading FIFO Data");
util.assert(tempstart == 1, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
for ( i = 9; i < 99; i = i + 1)
begin
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == packet[i], "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 0, "Reading FIFO End");
end
fork
data_out.sync_read(tempdata);
data_out_start.sync_read(tempstart);
data_out_end.sync_read(tempend);
join
util.assert(tempdata == packet[99], "Reading FIFO Data");
util.assert(tempstart == 0, "Reading FIFO Start");
util.assert(tempend == 1, "Reading FIFO End");
util.assert(data_available == 0, "Data available not set");
util.display();
$finish;
end
endmodule | 12 |
140,745 | data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tx_sm.v | 91,168,366 | tx_sm.v | v | 328 | 214 | [] | [] | [] | [(1, 327)] | null | null | 1: b"%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tx_sm.v:306: Cannot find file containing module: 'crc'\ncrc #( .POLYNOMIAL(CRC_POLYNOMIAL),\n^~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/tx,data/full_repos/permissive/91168366/crc\n data/full_repos/permissive/91168366/MAC/rtl/mac/tx,data/full_repos/permissive/91168366/crc.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/tx,data/full_repos/permissive/91168366/crc.sv\n crc\n crc.v\n crc.sv\n obj_dir/crc\n obj_dir/crc.v\n obj_dir/crc.sv\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tx_sm.v:319: Cannot find file containing module: 'random_gen'\nrandom_gen U_random_gen(\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,625 | module | module tx_sm #(
parameter STATE_DEFER = 4'h0,
parameter STATE_IFG = 4'h1,
parameter STATE_IDLE = 4'h2,
parameter STATE_PREAMBLE = 4'h3,
parameter STATE_SFD = 4'h4,
parameter STATE_DATA = 4'h5,
parameter STATE_PAD = 4'h6,
parameter STATE_JAM = 4'h7,
parameter STATE_BACKOFF = 4'h8,
parameter STATE_FCS = 4'h9,
parameter STATE_JAM_DROP = 4'hA,
parameter STATE_NEXT = 4'hB
)(
input wire reset,
input wire clock,
input wire [7:0] fifo_data,
output reg fifo_data_read,
input wire fifo_data_start,
input wire fifo_data_end,
input wire fifo_data_available,
output reg fifo_retry,
input wire mode,
input wire carrier_sense,
input wire collision,
output reg tx_enable,
output reg [7:0] tx_data
);
localparam HALF_DUPLEX = 0;
localparam FULL_DUPLEX = 1;
localparam CRC_POLYNOMIAL = 32'h04C11DB7;
localparam CRC_SEED = 32'hFFFFFFFF;
localparam MAX_SIZE = 1518;
localparam MIN_SIZE = 64;
reg [3:0] state;
reg [3:0] prev_state;
reg [3:0] next_state;
reg [7:0] frame_length_count;
reg [5:0] padding_length_count;
reg [4:0] jam_length_count;
reg [3:0] inter_frame_gap_count;
reg [3:0] preamble_count;
reg [3:0] retry_count;
reg crc_init;
reg crc_enable;
wire [31:0] crc_out;
wire [31:0] crc_rev;
integer crc_index;
reg random_init;
wire random_trigger;
always @(posedge clock or posedge reset)
if (reset)
state <= STATE_DEFER;
else
begin
prev_state = state;
state = next_state;
end
always @ (*)
case (state)
STATE_DEFER:
if ((mode == FULL_DUPLEX) || (mode == HALF_DUPLEX && !carrier_sense))
next_state = STATE_IFG;
else
next_state = STATE_DEFER;
STATE_IFG:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && inter_frame_gap_count == 12 - 4) || (mode == HALF_DUPLEX && !carrier_sense && inter_frame_gap_count == 12 - 4))
next_state = STATE_IDLE;
else
next_state = STATE_IFG;
STATE_IDLE:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && fifo_data_available) || (mode == HALF_DUPLEX && !carrier_sense && fifo_data_available))
next_state = STATE_PREAMBLE;
else
next_state = STATE_IDLE;
STATE_PREAMBLE:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if ((mode == FULL_DUPLEX && preamble_count == 7) || (mode == HALF_DUPLEX && !collision && preamble_count == 7))
next_state = STATE_SFD;
else
next_state = STATE_PREAMBLE;
STATE_SFD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else
next_state = STATE_DATA;
STATE_DATA:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (fifo_data_end && frame_length_count >= 59 )
next_state = STATE_FCS;
else if (fifo_data_end)
next_state = STATE_PAD;
else
next_state = STATE_DATA;
STATE_PAD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (frame_length_count >= 59)
next_state = STATE_FCS;
else
next_state = STATE_PAD;
STATE_JAM:
if (retry_count <= 2 && jam_length_count == 16)
next_state = STATE_BACKOFF;
else if (retry_count > 2)
next_state = STATE_JAM_DROP;
else
next_state = STATE_JAM;
STATE_BACKOFF:
if (random_trigger)
next_state = STATE_DEFER;
else
next_state = STATE_BACKOFF;
STATE_FCS:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (crc_index > 24)
next_state = STATE_NEXT;
else
next_state = STATE_FCS;
STATE_JAM_DROP:
if (fifo_data_end)
next_state = STATE_NEXT;
else
next_state = STATE_JAM_DROP;
STATE_NEXT:
next_state = STATE_DEFER;
default:
next_state = STATE_DEFER;
endcase
genvar j;
generate
for (j = 31; j >= 0; j = j - 1)
begin : crc_reverse
assign crc_rev[31-j] = crc_out[j];
end
endgenerate
always @(posedge clock or posedge reset)
if (reset)
frame_length_count <= 0;
else if (state == STATE_DEFER)
frame_length_count <= 0;
else if (state == STATE_DATA || state == STATE_PAD)
frame_length_count <= frame_length_count+1;
always @(posedge clock or posedge reset)
if (reset)
padding_length_count <=0;
else if (state != STATE_PAD)
padding_length_count <= 0;
else
padding_length_count <= padding_length_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
jam_length_count <= 0;
else if (state == STATE_JAM || next_state == STATE_JAM)
jam_length_count <= jam_length_count + 1;
else
jam_length_count <= 0;
always @ (posedge clock or posedge reset)
if (reset)
inter_frame_gap_count <= 0;
else if (state != STATE_IFG)
inter_frame_gap_count <= 0;
else
inter_frame_gap_count <= inter_frame_gap_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
preamble_count <= 0;
else if (state != STATE_PREAMBLE)
preamble_count <= 0;
else
preamble_count <= preamble_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
retry_count <= 0;
else if (state == STATE_NEXT)
retry_count <= 0;
else if (state == STATE_JAM && next_state == STATE_BACKOFF)
retry_count <= retry_count + 1;
always @ (*)
if ((state == STATE_DATA ||
state == STATE_SFD ||
state == STATE_JAM_DROP ) &&
next_state != STATE_FCS)
fifo_data_read = 1;
else
fifo_data_read = 0;
always @ (state)
if (state == STATE_JAM)
fifo_retry = 1;
else
fifo_retry = 0;
always @(prev_state)
if (prev_state == STATE_PREAMBLE ||
prev_state == STATE_SFD ||
prev_state == STATE_DATA ||
prev_state == STATE_FCS ||
prev_state == STATE_PAD ||
prev_state == STATE_JAM )
tx_enable <= 1;
else
tx_enable <= 0;
reg [7:0] tx_data_tmp;
always @(posedge clock)
case (state)
STATE_PREAMBLE:
tx_data_tmp <= 8'h55;
STATE_SFD:
tx_data_tmp <= 8'hD5;
STATE_DATA:
tx_data_tmp <= fifo_data;
STATE_PAD:
tx_data_tmp <= 8'h00;
STATE_JAM:
tx_data_tmp <= 8'h01;
STATE_FCS:
$display("CRC: %x", ~crc_rev);
default:
tx_data_tmp <= 8'b00;
endcase
always @(posedge clock)
if (prev_state == STATE_FCS)
tx_data <= ~crc_rev[crc_index+:8];
else
tx_data <= tx_data_tmp;
always @(posedge clock)
if(prev_state == STATE_FCS)
crc_index <= crc_index + 8;
else
crc_index <= 0;
always @(state)
if (state == STATE_SFD)
crc_init = 1;
else
crc_init = 0;
reg crc_enable_tmp;
always @(state)
if (state == STATE_DATA || state == STATE_PAD)
crc_enable_tmp = 1;
else
crc_enable_tmp = 0;
always @ (posedge clock)
crc_enable <= crc_enable_tmp;
always @(state or next_state)
if (state == STATE_JAM && next_state == STATE_BACKOFF)
random_init = 1;
else
random_init = 0;
crc #( .POLYNOMIAL(CRC_POLYNOMIAL),
.DATA_WIDTH(8),
.CRC_WIDTH(32),
.SEED(CRC_SEED))
U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(tx_data_tmp),
.data_enable(crc_enable),
.crc_out(crc_out)
);
random_gen U_random_gen(
.reset(reset),
.clock(clock),
.init(random_init),
.retry_count(retry_count),
.trigger(random_trigger)
);
endmodule | module tx_sm #(
parameter STATE_DEFER = 4'h0,
parameter STATE_IFG = 4'h1,
parameter STATE_IDLE = 4'h2,
parameter STATE_PREAMBLE = 4'h3,
parameter STATE_SFD = 4'h4,
parameter STATE_DATA = 4'h5,
parameter STATE_PAD = 4'h6,
parameter STATE_JAM = 4'h7,
parameter STATE_BACKOFF = 4'h8,
parameter STATE_FCS = 4'h9,
parameter STATE_JAM_DROP = 4'hA,
parameter STATE_NEXT = 4'hB
)(
input wire reset,
input wire clock,
input wire [7:0] fifo_data,
output reg fifo_data_read,
input wire fifo_data_start,
input wire fifo_data_end,
input wire fifo_data_available,
output reg fifo_retry,
input wire mode,
input wire carrier_sense,
input wire collision,
output reg tx_enable,
output reg [7:0] tx_data
); |
localparam HALF_DUPLEX = 0;
localparam FULL_DUPLEX = 1;
localparam CRC_POLYNOMIAL = 32'h04C11DB7;
localparam CRC_SEED = 32'hFFFFFFFF;
localparam MAX_SIZE = 1518;
localparam MIN_SIZE = 64;
reg [3:0] state;
reg [3:0] prev_state;
reg [3:0] next_state;
reg [7:0] frame_length_count;
reg [5:0] padding_length_count;
reg [4:0] jam_length_count;
reg [3:0] inter_frame_gap_count;
reg [3:0] preamble_count;
reg [3:0] retry_count;
reg crc_init;
reg crc_enable;
wire [31:0] crc_out;
wire [31:0] crc_rev;
integer crc_index;
reg random_init;
wire random_trigger;
always @(posedge clock or posedge reset)
if (reset)
state <= STATE_DEFER;
else
begin
prev_state = state;
state = next_state;
end
always @ (*)
case (state)
STATE_DEFER:
if ((mode == FULL_DUPLEX) || (mode == HALF_DUPLEX && !carrier_sense))
next_state = STATE_IFG;
else
next_state = STATE_DEFER;
STATE_IFG:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && inter_frame_gap_count == 12 - 4) || (mode == HALF_DUPLEX && !carrier_sense && inter_frame_gap_count == 12 - 4))
next_state = STATE_IDLE;
else
next_state = STATE_IFG;
STATE_IDLE:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && fifo_data_available) || (mode == HALF_DUPLEX && !carrier_sense && fifo_data_available))
next_state = STATE_PREAMBLE;
else
next_state = STATE_IDLE;
STATE_PREAMBLE:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if ((mode == FULL_DUPLEX && preamble_count == 7) || (mode == HALF_DUPLEX && !collision && preamble_count == 7))
next_state = STATE_SFD;
else
next_state = STATE_PREAMBLE;
STATE_SFD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else
next_state = STATE_DATA;
STATE_DATA:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (fifo_data_end && frame_length_count >= 59 )
next_state = STATE_FCS;
else if (fifo_data_end)
next_state = STATE_PAD;
else
next_state = STATE_DATA;
STATE_PAD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (frame_length_count >= 59)
next_state = STATE_FCS;
else
next_state = STATE_PAD;
STATE_JAM:
if (retry_count <= 2 && jam_length_count == 16)
next_state = STATE_BACKOFF;
else if (retry_count > 2)
next_state = STATE_JAM_DROP;
else
next_state = STATE_JAM;
STATE_BACKOFF:
if (random_trigger)
next_state = STATE_DEFER;
else
next_state = STATE_BACKOFF;
STATE_FCS:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (crc_index > 24)
next_state = STATE_NEXT;
else
next_state = STATE_FCS;
STATE_JAM_DROP:
if (fifo_data_end)
next_state = STATE_NEXT;
else
next_state = STATE_JAM_DROP;
STATE_NEXT:
next_state = STATE_DEFER;
default:
next_state = STATE_DEFER;
endcase
genvar j;
generate
for (j = 31; j >= 0; j = j - 1)
begin : crc_reverse
assign crc_rev[31-j] = crc_out[j];
end
endgenerate
always @(posedge clock or posedge reset)
if (reset)
frame_length_count <= 0;
else if (state == STATE_DEFER)
frame_length_count <= 0;
else if (state == STATE_DATA || state == STATE_PAD)
frame_length_count <= frame_length_count+1;
always @(posedge clock or posedge reset)
if (reset)
padding_length_count <=0;
else if (state != STATE_PAD)
padding_length_count <= 0;
else
padding_length_count <= padding_length_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
jam_length_count <= 0;
else if (state == STATE_JAM || next_state == STATE_JAM)
jam_length_count <= jam_length_count + 1;
else
jam_length_count <= 0;
always @ (posedge clock or posedge reset)
if (reset)
inter_frame_gap_count <= 0;
else if (state != STATE_IFG)
inter_frame_gap_count <= 0;
else
inter_frame_gap_count <= inter_frame_gap_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
preamble_count <= 0;
else if (state != STATE_PREAMBLE)
preamble_count <= 0;
else
preamble_count <= preamble_count + 1;
always @ (posedge clock or posedge reset)
if (reset)
retry_count <= 0;
else if (state == STATE_NEXT)
retry_count <= 0;
else if (state == STATE_JAM && next_state == STATE_BACKOFF)
retry_count <= retry_count + 1;
always @ (*)
if ((state == STATE_DATA ||
state == STATE_SFD ||
state == STATE_JAM_DROP ) &&
next_state != STATE_FCS)
fifo_data_read = 1;
else
fifo_data_read = 0;
always @ (state)
if (state == STATE_JAM)
fifo_retry = 1;
else
fifo_retry = 0;
always @(prev_state)
if (prev_state == STATE_PREAMBLE ||
prev_state == STATE_SFD ||
prev_state == STATE_DATA ||
prev_state == STATE_FCS ||
prev_state == STATE_PAD ||
prev_state == STATE_JAM )
tx_enable <= 1;
else
tx_enable <= 0;
reg [7:0] tx_data_tmp;
always @(posedge clock)
case (state)
STATE_PREAMBLE:
tx_data_tmp <= 8'h55;
STATE_SFD:
tx_data_tmp <= 8'hD5;
STATE_DATA:
tx_data_tmp <= fifo_data;
STATE_PAD:
tx_data_tmp <= 8'h00;
STATE_JAM:
tx_data_tmp <= 8'h01;
STATE_FCS:
$display("CRC: %x", ~crc_rev);
default:
tx_data_tmp <= 8'b00;
endcase
always @(posedge clock)
if (prev_state == STATE_FCS)
tx_data <= ~crc_rev[crc_index+:8];
else
tx_data <= tx_data_tmp;
always @(posedge clock)
if(prev_state == STATE_FCS)
crc_index <= crc_index + 8;
else
crc_index <= 0;
always @(state)
if (state == STATE_SFD)
crc_init = 1;
else
crc_init = 0;
reg crc_enable_tmp;
always @(state)
if (state == STATE_DATA || state == STATE_PAD)
crc_enable_tmp = 1;
else
crc_enable_tmp = 0;
always @ (posedge clock)
crc_enable <= crc_enable_tmp;
always @(state or next_state)
if (state == STATE_JAM && next_state == STATE_BACKOFF)
random_init = 1;
else
random_init = 0;
crc #( .POLYNOMIAL(CRC_POLYNOMIAL),
.DATA_WIDTH(8),
.CRC_WIDTH(32),
.SEED(CRC_SEED))
U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(tx_data_tmp),
.data_enable(crc_enable),
.crc_out(crc_out)
);
random_gen U_random_gen(
.reset(reset),
.clock(clock),
.init(random_init),
.retry_count(retry_count),
.trigger(random_trigger)
);
endmodule | 12 |
140,746 | data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v | 91,168,366 | tx_sm_half_duplex_tb.v | v | 209 | 103 | [] | [] | [] | null | line:133: before: "(" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:5: Cannot find include file: dut.v\n`include "dut.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb,data/full_repos/permissive/91168366/dut.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb,data/full_repos/permissive/91168366/dut.v.v\n data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb,data/full_repos/permissive/91168366/dut.v.sv\n dut.v\n dut.v.v\n dut.v.sv\n obj_dir/dut.v\n obj_dir/dut.v.v\n obj_dir/dut.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #110 \n ^\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:36: syntax error, unexpected assert\n data.assert(tempdata == 8\'h55, "Preamble");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:43: syntax error, unexpected assert\n data.assert(tempdata == 8\'hD5, "SFD");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:47: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:52: syntax error, unexpected assert\n data.assert(tx_data == 0, "DATA START"); \n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:57: syntax error, unexpected assert\n data.assert(tx_data == i, "DATA");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:60: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:65: syntax error, unexpected assert\n data.assert(tx_data == 8\'h09, "DATA END"); \n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:72: syntax error, unexpected assert\n data.assert(tempdata == 0, "PADDING");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:78: syntax error, unexpected assert\n data.assert(tempdata == 8\'hAA, "CRC");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:81: syntax error, unexpected assert\n data.assert(tempdata == 8\'hAA, "CRC");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:84: syntax error, unexpected assert\n data.assert(tempdata == 8\'h91, "CRC");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:87: syntax error, unexpected assert\n data.assert(tempdata == 8\'h91, "CRC");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n #120\n ^\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:101: syntax error, unexpected assert\n data.assert(tempdata == 8\'h55, "Preamble");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:108: syntax error, unexpected assert\n data.assert(tempdata == 8\'hD5, "SFD");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:112: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:117: syntax error, unexpected assert\n data.assert(tx_data == 0, "DATA START"); \n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:122: syntax error, unexpected assert\n data.assert(tx_data == i, "DATA");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:125: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:130: syntax error, unexpected assert\n data.assert(tx_data == 8\'h09, "DATA END"); \n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:137: syntax error, unexpected assert\n data.assert(tempdata == 0, "PADDING");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:143: syntax error, unexpected assert\n data.assert(tempdata == 8\'hAA, "CRC");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:146: syntax error, unexpected assert\n data.assert(tempdata == 8\'hAA, "CRC");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:149: syntax error, unexpected assert\n data.assert(tempdata == 8\'h91, "CRC");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:152: syntax error, unexpected assert\n data.assert(tempdata == 8\'h91, "CRC");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n #110\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n #110\n ^\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:178: syntax error, unexpected assert\n data.assert(tempdata == 8\'h55, "Preamble");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:187: syntax error, unexpected assert\n data.assert(tempdata == 8\'hD5, "SFD");\n ^~~~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/tx/tb/tx_sm_half_duplex_tb.v:193: syntax error, unexpected assert\n data.assert(tempdata == 8\'h01, "COLLISION DETECTED- JAMMING");\n ^~~~~~\n%Error: Exiting due to 28 error(s), 6 warning(s)\n' | 309,628 | module | module tx_sm_tb ();
`include "dut.v"
integer i;
initial
begin
end
initial
begin
#15 reset = 0;
mode = 0;
fifo_count = 1;
#110
expected_tx_enable = 1;
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
fork
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
#120
expected_tx_enable = 1;
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
fork
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
#110
carrier_sense = 1;
#1000
carrier_sense = 0;
#110
expected_tx_enable = 1;
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
collision = 1;
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
for (i = 0; i < 16; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h01, "COLLISION DETECTED- JAMMING");
end
expected_tx_enable = 0;
collision = 0;
$finish;
end
endmodule | module tx_sm_tb (); |
`include "dut.v"
integer i;
initial
begin
end
initial
begin
#15 reset = 0;
mode = 0;
fifo_count = 1;
#110
expected_tx_enable = 1;
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
fork
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
#120
expected_tx_enable = 1;
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
fork
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
#110
carrier_sense = 1;
#1000
carrier_sense = 0;
#110
expected_tx_enable = 1;
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
collision = 1;
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
for (i = 0; i < 16; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h01, "COLLISION DETECTED- JAMMING");
end
expected_tx_enable = 0;
collision = 0;
$finish;
end
endmodule | 12 |
140,747 | data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/monitor.v | 91,168,366 | monitor.v | v | 18 | 40 | [] | [] | [] | [(1, 17)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/monitor.v:11: Operator NEQ expects 8 bits on the RHS, but RHS\'s VARREF \'expected\' generates 1 bits.\n : ... In instance monitor\n if (data != expected)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 309,629 | module | module monitor #(
parameter WIDTH = 8
)(
input wire [WIDTH-1:0] data,
input wire expected,
input wire clock
);
always @(posedge clock)
begin
if (data != expected)
begin
$display("MONITOR FAILED");
end
end
endmodule | module monitor #(
parameter WIDTH = 8
)(
input wire [WIDTH-1:0] data,
input wire expected,
input wire clock
); |
always @(posedge clock)
begin
if (data != expected)
begin
$display("MONITOR FAILED");
end
end
endmodule | 12 |
140,748 | data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v | 91,168,366 | utilities.v | v | 92 | 69 | [] | [] | [] | null | line:34: before: "if" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v:33: syntax error, unexpected \'@\'\n @(posedge clock)\n ^\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v:39: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v:43: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v:69: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v:70: Unsupported: Ignoring delay on this delayed statement.\n #1 data_out_enable = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v:81: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/rtl/mac/utilities/utilities.v:82: Unsupported: Ignoring delay on this delayed statement.\n #1 data = data_in;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 309,630 | module | module utilities #(
parameter IN_WIDTH = 8,
parameter OUT_WIDTH = 8,
parameter DEBUG = 0
)(
output reg [OUT_WIDTH-1:0] data_out,
output reg data_out_enable,
input wire [IN_WIDTH-1:0] data_in,
output reg data_in_enable,
input wire clock
);
integer passes;
integer fails;
initial
begin
data_out = 0;
data_out_enable = 0;
data_in_enable = 0;
passes = 0;
fails = 0;
end
task display;
begin
$display("PASSES:%d FAILS:%d", passes, fails);
end
endtask
task sync_assert;
input condition;
input [100*8:0] message;
begin
@(posedge clock)
if (condition)
begin
$display("ASSERTION PASSED | %0s", message);
passes = passes + 1;
end
else
begin
$display("ASSERTION FAILED | %0s", message);
fails = fails + 1;
end
end
endtask
task assert;
input condition;
input [100*8:0] message;
begin
if (condition)
begin
$display("ASSERTION PASSED | %0s", message);
passes = passes + 1;
end
else
begin
$display("ASSERTION FAILED | %0s", message);
fails = fails + 1;
end
end
endtask
task sync_write;
input [OUT_WIDTH-1:0] data;
begin
data_out = data;
data_out_enable = 1;
@(posedge clock);
#1 data_out_enable = 0;
data_out = 0;
if (DEBUG)
$display("Wrote: 0x%0x | 0b%0b | %0d",data, data, data);
end
endtask
task sync_read;
output [IN_WIDTH-1:0] data;
begin
data_in_enable = 1;
@(posedge clock);
#1 data = data_in;
data_in_enable = 0;
if (DEBUG)
$display("Read: 0x%0x | 0b%0b | %0d", data, data, data);
end
endtask
endmodule | module utilities #(
parameter IN_WIDTH = 8,
parameter OUT_WIDTH = 8,
parameter DEBUG = 0
)(
output reg [OUT_WIDTH-1:0] data_out,
output reg data_out_enable,
input wire [IN_WIDTH-1:0] data_in,
output reg data_in_enable,
input wire clock
); |
integer passes;
integer fails;
initial
begin
data_out = 0;
data_out_enable = 0;
data_in_enable = 0;
passes = 0;
fails = 0;
end
task display;
begin
$display("PASSES:%d FAILS:%d", passes, fails);
end
endtask
task sync_assert;
input condition;
input [100*8:0] message;
begin
@(posedge clock)
if (condition)
begin
$display("ASSERTION PASSED | %0s", message);
passes = passes + 1;
end
else
begin
$display("ASSERTION FAILED | %0s", message);
fails = fails + 1;
end
end
endtask
task assert;
input condition;
input [100*8:0] message;
begin
if (condition)
begin
$display("ASSERTION PASSED | %0s", message);
passes = passes + 1;
end
else
begin
$display("ASSERTION FAILED | %0s", message);
fails = fails + 1;
end
end
endtask
task sync_write;
input [OUT_WIDTH-1:0] data;
begin
data_out = data;
data_out_enable = 1;
@(posedge clock);
#1 data_out_enable = 0;
data_out = 0;
if (DEBUG)
$display("Wrote: 0x%0x | 0b%0b | %0d",data, data, data);
end
endtask
task sync_read;
output [IN_WIDTH-1:0] data;
begin
data_in_enable = 1;
@(posedge clock);
#1 data = data_in;
data_in_enable = 0;
if (DEBUG)
$display("Read: 0x%0x | 0b%0b | %0d", data, data, data);
end
endtask
endmodule | 12 |
140,751 | data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v | 91,168,366 | mac_fifo_tb2.v | v | 161 | 81 | [] | [] | [] | null | line:71: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v:69: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v:123: Unsupported: Ignoring delay on this delayed statement.\n #5 data_in_clock = ~data_in_clock;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v:126: Unsupported: Ignoring delay on this delayed statement.\n #40 data_out_clock = ~data_out_clock;\n ^\n%Error: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v:139: syntax error, unexpected \'@\'\n @(posedge data_in_clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v:140: Unsupported: Ignoring delay on this delayed statement.\n #1 data_in_enable = 0;\n ^\n%Error: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v:152: syntax error, unexpected \'@\'\n @(posedge data_out_clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/mac_fifo_tb2.v:153: Unsupported: Ignoring delay on this delayed statement.\n #1 data_out_enable = 0;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,634 | module | module mac_fifo_test();
parameter IN_WIDTH = 8;
parameter OUT_WIDTH = 32;
reg reset;
reg [IN_WIDTH-1:0] data_in;
reg data_in_clock;
reg data_in_enable;
reg data_in_start;
reg data_in_end;
wire [OUT_WIDTH-1:0] data_out;
reg data_out_clock;
reg data_out_enable;
wire data_out_start;
wire data_out_end;
reg error;
reg retry;
reg [OUT_WIDTH-1:0] tempdata;
integer i;
mac_fifo #(
.DATA_IN_WIDTH (IN_WIDTH),
.DATA_OUT_WIDTH (OUT_WIDTH),
.FIFO_DEPTH (12)
)
ff (
.reset(reset),
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start),
.data_in_end(data_in_end),
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.retry(retry),
.error(error)
);
initial
begin
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
data_out_clock = 0;
data_out_enable = 0;
data_in_start = 0;
data_in_end = 0;
error = 0;
retry = 0;
tempdata = 0;
#15 reset = 0;
push(8'h01,1,0,0);
push(8'h02,0,0,0);
push(8'h03,0,0,0);
push(8'h04,0,0,0);
push(8'h05,0,0,0);
push(8'h06,0,0,0);
push(8'h07,0,0,0);
push(8'h08,0,0,0);
push(8'h09,0,0,0);
push(8'h0A,0,0,0);
push(8'h0B,0,0,0);
push(8'h0C,0,0,0);
push(8'h0D,0,0,0);
push(8'h0E,0,0,0);
push(8'h0F,0,0,0);
push(8'h10,0,0,0);
push(8'h11,0,0,0);
push(8'h12,0,0,0);
push(8'h13,0,0,0);
push(8'h14,0,1,0);
push(8'h11,1,0,0);
push(8'h22,0,0,0);
push(8'h33,0,0,0);
push(8'h44,0,0,1);
push(8'h55,1,0,0);
push(8'h66,0,0,0);
push(8'h77,0,0,0);
push(8'h88,0,0,0);
push(8'h99,0,0,0);
push(8'hAA,0,0,0);
push(8'hBB,0,0,0);
push(8'hCC,0,0,0);
push(8'hDD,0,0,0);
push(8'hEE,0,0,0);
push(8'hFF,0,1,0);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
$finish;
end
always
#5 data_in_clock = ~data_in_clock;
always
#40 data_out_clock = ~data_out_clock;
task push;
input[IN_WIDTH-1:0] data;
input data_start;
input data_end;
input frame_error;
begin
data_in = data;
data_in_enable = 1;
data_in_start = data_start;
data_in_end = data_end;
error = frame_error;
@(posedge data_in_clock);
#1 data_in_enable = 0;
data_in_start = 0;
data_in_end = 0;
error = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
task pop;
output [OUT_WIDTH-1:0] data;
begin
data_out_enable = 1;
@(posedge data_out_clock);
#1 data_out_enable = 0;
data = data_out;
$display("Popped %x Start: %b End: %b", data, data_out_start, data_out_end);
end
endtask
endmodule | module mac_fifo_test(); |
parameter IN_WIDTH = 8;
parameter OUT_WIDTH = 32;
reg reset;
reg [IN_WIDTH-1:0] data_in;
reg data_in_clock;
reg data_in_enable;
reg data_in_start;
reg data_in_end;
wire [OUT_WIDTH-1:0] data_out;
reg data_out_clock;
reg data_out_enable;
wire data_out_start;
wire data_out_end;
reg error;
reg retry;
reg [OUT_WIDTH-1:0] tempdata;
integer i;
mac_fifo #(
.DATA_IN_WIDTH (IN_WIDTH),
.DATA_OUT_WIDTH (OUT_WIDTH),
.FIFO_DEPTH (12)
)
ff (
.reset(reset),
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start),
.data_in_end(data_in_end),
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.retry(retry),
.error(error)
);
initial
begin
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
data_out_clock = 0;
data_out_enable = 0;
data_in_start = 0;
data_in_end = 0;
error = 0;
retry = 0;
tempdata = 0;
#15 reset = 0;
push(8'h01,1,0,0);
push(8'h02,0,0,0);
push(8'h03,0,0,0);
push(8'h04,0,0,0);
push(8'h05,0,0,0);
push(8'h06,0,0,0);
push(8'h07,0,0,0);
push(8'h08,0,0,0);
push(8'h09,0,0,0);
push(8'h0A,0,0,0);
push(8'h0B,0,0,0);
push(8'h0C,0,0,0);
push(8'h0D,0,0,0);
push(8'h0E,0,0,0);
push(8'h0F,0,0,0);
push(8'h10,0,0,0);
push(8'h11,0,0,0);
push(8'h12,0,0,0);
push(8'h13,0,0,0);
push(8'h14,0,1,0);
push(8'h11,1,0,0);
push(8'h22,0,0,0);
push(8'h33,0,0,0);
push(8'h44,0,0,1);
push(8'h55,1,0,0);
push(8'h66,0,0,0);
push(8'h77,0,0,0);
push(8'h88,0,0,0);
push(8'h99,0,0,0);
push(8'hAA,0,0,0);
push(8'hBB,0,0,0);
push(8'hCC,0,0,0);
push(8'hDD,0,0,0);
push(8'hEE,0,0,0);
push(8'hFF,0,1,0);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
$finish;
end
always
#5 data_in_clock = ~data_in_clock;
always
#40 data_out_clock = ~data_out_clock;
task push;
input[IN_WIDTH-1:0] data;
input data_start;
input data_end;
input frame_error;
begin
data_in = data;
data_in_enable = 1;
data_in_start = data_start;
data_in_end = data_end;
error = frame_error;
@(posedge data_in_clock);
#1 data_in_enable = 0;
data_in_start = 0;
data_in_end = 0;
error = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
task pop;
output [OUT_WIDTH-1:0] data;
begin
data_out_enable = 1;
@(posedge data_out_clock);
#1 data_out_enable = 0;
data = data_out;
$display("Popped %x Start: %b End: %b", data, data_out_start, data_out_end);
end
endtask
endmodule | 12 |
140,752 | data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v | 91,168,366 | fifo_tb.v | v | 105 | 58 | [] | [] | [] | null | line:57: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #5 data_in_clock = ~data_in_clock;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #40 data_out_clock = ~data_out_clock;\n ^\n%Error: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v:86: syntax error, unexpected \'@\'\n @(posedge data_in_clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #1 data_in_enable = 0;\n ^\n%Error: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v:96: syntax error, unexpected \'@\'\n @(posedge data_out_clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC/tb/mac/mac_fifo/fifo/fifo_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #1 data_out_enable = 0;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,635 | module | module fifo_test();
parameter IN_WIDTH = 32;
parameter OUT_WIDTH = 4;
reg reset;
reg [IN_WIDTH-1:0] data_in;
reg data_in_clock;
reg data_in_enable;
wire [OUT_WIDTH-1:0] data_out;
reg data_out_clock;
reg data_out_enable;
reg [OUT_WIDTH-1:0] tempdata;
integer i;
fifo #(
.DATA_IN_WIDTH (IN_WIDTH),
.DATA_OUT_WIDTH (OUT_WIDTH),
.FIFO_DEPTH (12)
)
ff (
.reset(reset),
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable)
);
initial
begin
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
data_out_clock = 0;
data_out_enable = 0;
tempdata = 0;
#15 reset = 0;
if (OUT_WIDTH > IN_WIDTH)
begin
for ( i = 0; i < (OUT_WIDTH/IN_WIDTH); i = i + 1)
begin
push(i);
end
pop(tempdata);
end
else
begin
push(1);
for ( i = 0; i < (IN_WIDTH/OUT_WIDTH); i = i + 1)
begin
pop(tempdata);
end
end
$finish;
end
always
#5 data_in_clock = ~data_in_clock;
always
#40 data_out_clock = ~data_out_clock;
task push;
input[IN_WIDTH-1:0] data;
begin
data_in = data;
data_in_enable = 1;
@(posedge data_in_clock);
#1 data_in_enable = 0;
$display("Pushed %x",data );
end
endtask
task pop;
output [OUT_WIDTH-1:0] data;
begin
data_out_enable = 1;
@(posedge data_out_clock);
#1 data_out_enable = 0;
data = data_out;
$display("Popped %x", data);
end
endtask
endmodule | module fifo_test(); |
parameter IN_WIDTH = 32;
parameter OUT_WIDTH = 4;
reg reset;
reg [IN_WIDTH-1:0] data_in;
reg data_in_clock;
reg data_in_enable;
wire [OUT_WIDTH-1:0] data_out;
reg data_out_clock;
reg data_out_enable;
reg [OUT_WIDTH-1:0] tempdata;
integer i;
fifo #(
.DATA_IN_WIDTH (IN_WIDTH),
.DATA_OUT_WIDTH (OUT_WIDTH),
.FIFO_DEPTH (12)
)
ff (
.reset(reset),
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable)
);
initial
begin
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
data_out_clock = 0;
data_out_enable = 0;
tempdata = 0;
#15 reset = 0;
if (OUT_WIDTH > IN_WIDTH)
begin
for ( i = 0; i < (OUT_WIDTH/IN_WIDTH); i = i + 1)
begin
push(i);
end
pop(tempdata);
end
else
begin
push(1);
for ( i = 0; i < (IN_WIDTH/OUT_WIDTH); i = i + 1)
begin
pop(tempdata);
end
end
$finish;
end
always
#5 data_in_clock = ~data_in_clock;
always
#40 data_out_clock = ~data_out_clock;
task push;
input[IN_WIDTH-1:0] data;
begin
data_in = data;
data_in_enable = 1;
@(posedge data_in_clock);
#1 data_in_enable = 0;
$display("Pushed %x",data );
end
endtask
task pop;
output [OUT_WIDTH-1:0] data;
begin
data_out_enable = 1;
@(posedge data_out_clock);
#1 data_out_enable = 0;
data = data_out;
$display("Popped %x", data);
end
endtask
endmodule | 12 |
140,754 | data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v | 91,168,366 | tx_tb.v | v | 102 | 74 | [] | [] | [] | null | line:60: before: "(" | null | 1: b'%Error: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:43: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tx_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #2 clock = ~clock;\n ^\n%Error: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:87: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1 fifo_data_start = 0;\n ^\n%Error: data/full_repos/permissive/91168366/MAC_components/state_machines/tx_tb.v:96: syntax error, unexpected \'@\'\n @(posedge fifo_data_read);\n ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,648 | module | module tx_tb();
reg reset;
reg clock;
wire [7:0] tx_data;
wire tx_enable;
reg fifo_data_start;
reg fifo_data_end;
reg [7:0] fifo_data;
wire fifo_data_read;
reg [7:0] packet [0:1518];
reg data_available;
integer i;
tx_sm U_tx_sm (
.reset(reset),
.clock(clock),
.fifo_data(fifo_data),
.fifo_data_read(fifo_data_read),
.fifo_data_start(fifo_data_start),
.fifo_data_end(fifo_data_end),
.fifo_data_available(data_available),
.fifo_retry(retry),
.mode(1'b1),
.carrier_sense(),
.collision(),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, tx_tb);
end
initial
begin
reset = 1;
clock = 0;
fifo_data = 0;
data_available = 0;
$readmemh("packet.hex", packet);
#15 reset = 0;
data_available = 1;
wait_for_read();
push(packet[8], 1, 0);
for(i = 9; i < 99; i = i + 1)
begin
push(packet[i], 0, 0);
end
push(packet[i], 0, 1);
#100
$finish;
end
always
#2 clock = ~clock;
task push;
input [7:0] data;
input data_start;
input data_end;
begin
fifo_data = data;
fifo_data_start = data_start;
fifo_data_end = data_end;
@(posedge clock);
#1 fifo_data_start = 0;
fifo_data_end = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
task wait_for_read;
begin
@(posedge fifo_data_read);
end
endtask
endmodule | module tx_tb(); |
reg reset;
reg clock;
wire [7:0] tx_data;
wire tx_enable;
reg fifo_data_start;
reg fifo_data_end;
reg [7:0] fifo_data;
wire fifo_data_read;
reg [7:0] packet [0:1518];
reg data_available;
integer i;
tx_sm U_tx_sm (
.reset(reset),
.clock(clock),
.fifo_data(fifo_data),
.fifo_data_read(fifo_data_read),
.fifo_data_start(fifo_data_start),
.fifo_data_end(fifo_data_end),
.fifo_data_available(data_available),
.fifo_retry(retry),
.mode(1'b1),
.carrier_sense(),
.collision(),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, tx_tb);
end
initial
begin
reset = 1;
clock = 0;
fifo_data = 0;
data_available = 0;
$readmemh("packet.hex", packet);
#15 reset = 0;
data_available = 1;
wait_for_read();
push(packet[8], 1, 0);
for(i = 9; i < 99; i = i + 1)
begin
push(packet[i], 0, 0);
end
push(packet[i], 0, 1);
#100
$finish;
end
always
#2 clock = ~clock;
task push;
input [7:0] data;
input data_start;
input data_end;
begin
fifo_data = data;
fifo_data_start = data_start;
fifo_data_end = data_end;
@(posedge clock);
#1 fifo_data_start = 0;
fifo_data_end = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
task wait_for_read;
begin
@(posedge fifo_data_read);
end
endtask
endmodule | 12 |
140,755 | data/full_repos/permissive/91223831/chargen.v | 91,223,831 | chargen.v | v | 25 | 32 | [] | [] | [] | null | line:5: before: "=" | data/verilator_xmls/d24fb61b-987a-4a9a-85d1-a43d3cfb275b.xml | null | 309,649 | module | module chargen
(
input i_clk,
input wire i_tx_rdy,
output reg [7:0] o_char = 33,
output reg o_char_rdy = 0
);
endmodule | module chargen
(
input i_clk,
input wire i_tx_rdy,
output reg [7:0] o_char = 33,
output reg o_char_rdy = 0
); |
endmodule | 0 |
140,756 | data/full_repos/permissive/91223831/loopback.v | 91,223,831 | loopback.v | v | 23 | 43 | [] | [] | [] | [(1, 22)] | null | data/verilator_xmls/acfb24fe-bc01-4a32-aa07-c80ae154013e.xml | null | 309,650 | module | module loopback
(
input i_clk,
input i_rx_byte_rdy,
input [7:0] i_rx_byte,
output o_tx_byte_rdy,
output [7:0] o_tx_byte
);
reg r_tx_byte_rdy;
reg [7:0] r_tx_byte;
always @(i_rx_byte_rdy)
begin
r_tx_byte <= i_rx_byte;
r_tx_byte_rdy = i_rx_byte_rdy;
end
assign o_tx_byte_rdy = r_tx_byte_rdy;
assign o_tx_byte = r_tx_byte;
endmodule | module loopback
(
input i_clk,
input i_rx_byte_rdy,
input [7:0] i_rx_byte,
output o_tx_byte_rdy,
output [7:0] o_tx_byte
); |
reg r_tx_byte_rdy;
reg [7:0] r_tx_byte;
always @(i_rx_byte_rdy)
begin
r_tx_byte <= i_rx_byte;
r_tx_byte_rdy = i_rx_byte_rdy;
end
assign o_tx_byte_rdy = r_tx_byte_rdy;
assign o_tx_byte = r_tx_byte;
endmodule | 0 |
140,757 | data/full_repos/permissive/91223831/rxtester.v | 91,223,831 | rxtester.v | v | 20 | 33 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/106f2d33-18ef-4305-a3c9-30bae0d140b0.xml | null | 309,651 | module | module rxtester
(
input i_rx_byte_rdy,
input [7:0] i_rx_byte,
output o_led
);
reg r_led = 1'b1;
always @(posedge i_rx_byte_rdy)
begin
if (i_rx_byte == 65)
r_led = 1'b0;
else
r_led = 1'b1;
end
assign o_led = r_led;
endmodule | module rxtester
(
input i_rx_byte_rdy,
input [7:0] i_rx_byte,
output o_led
); |
reg r_led = 1'b1;
always @(posedge i_rx_byte_rdy)
begin
if (i_rx_byte == 65)
r_led = 1'b0;
else
r_led = 1'b1;
end
assign o_led = r_led;
endmodule | 0 |
140,758 | data/full_repos/permissive/91223831/status.v | 91,223,831 | status.v | v | 21 | 40 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/f6c0b2eb-3b22-4416-91ac-7b4dd2a82406.xml | null | 309,652 | module | module status
(
input i_clk,
output reg o_hz_clk
);
reg [31:0] r_count;
always @(posedge i_clk) begin
if (r_count <= 25000000)
begin
r_count <= r_count + 1;
end
else
begin
r_count <= 0;
o_hz_clk <= ~o_hz_clk;
end
end
endmodule | module status
(
input i_clk,
output reg o_hz_clk
); |
reg [31:0] r_count;
always @(posedge i_clk) begin
if (r_count <= 25000000)
begin
r_count <= r_count + 1;
end
else
begin
r_count <= 0;
o_hz_clk <= ~o_hz_clk;
end
end
endmodule | 0 |
140,759 | data/full_repos/permissive/91223831/uart.v | 91,223,831 | uart.v | v | 39 | 80 | [] | [] | [] | [(3, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/91223831/uart.v:19: Cannot find file containing module: 'uart_tx'\n uart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_TX_I1\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91223831,data/full_repos/permissive/91223831/uart_tx\n data/full_repos/permissive/91223831,data/full_repos/permissive/91223831/uart_tx.v\n data/full_repos/permissive/91223831,data/full_repos/permissive/91223831/uart_tx.sv\n uart_tx\n uart_tx.v\n uart_tx.sv\n obj_dir/uart_tx\n obj_dir/uart_tx.v\n obj_dir/uart_tx.sv\n%Error: data/full_repos/permissive/91223831/uart.v:28: Cannot find file containing module: 'uart_rx'\n uart_rx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_RX_I1\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,653 | module | module uart
(
input wire i_clk,
input wire i_rx,
output wire o_tx,
input wire i_tx_byte_rdy,
input wire [7:0] i_tx_byte,
output wire o_tx_busy,
output wire o_rx_byte_rdy,
output wire [7:0] o_rx_byte
);
localparam CLOCK_PERIOD_NS = 20, CLKS_PER_BIT = 434, BIT_PERIOD = 434 * 20;
uart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_TX_I1
(
.i_clk(i_clk),
.i_tx_byte_rdy(i_tx_byte_rdy),
.i_tx_byte(i_tx_byte),
.o_tx_busy(o_tx_busy),
.o_tx(o_tx)
);
uart_rx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_RX_I1
(
.i_clk(i_clk),
.i_rx(i_rx),
.o_rx_byte_rdy(o_rx_byte_rdy),
.o_rx_byte_rdy(),
.o_rx_byte(o_rx_byte)
);
endmodule | module uart
(
input wire i_clk,
input wire i_rx,
output wire o_tx,
input wire i_tx_byte_rdy,
input wire [7:0] i_tx_byte,
output wire o_tx_busy,
output wire o_rx_byte_rdy,
output wire [7:0] o_rx_byte
); |
localparam CLOCK_PERIOD_NS = 20, CLKS_PER_BIT = 434, BIT_PERIOD = 434 * 20;
uart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_TX_I1
(
.i_clk(i_clk),
.i_tx_byte_rdy(i_tx_byte_rdy),
.i_tx_byte(i_tx_byte),
.o_tx_busy(o_tx_busy),
.o_tx(o_tx)
);
uart_rx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_RX_I1
(
.i_clk(i_clk),
.i_rx(i_rx),
.o_rx_byte_rdy(o_rx_byte_rdy),
.o_rx_byte_rdy(),
.o_rx_byte(o_rx_byte)
);
endmodule | 0 |
140,760 | data/full_repos/permissive/91223831/uart_rx.v | 91,223,831 | uart_rx.v | v | 123 | 84 | [] | [] | [] | null | line:4: before: ")" | null | 1: b"%Error: data/full_repos/permissive/91223831/uart_rx.v:4: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'CLKS_PER_BIT'\n : ... In instance uart_rx\n #(parameter CLKS_PER_BIT)\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,654 | module | module uart_rx
#(parameter CLKS_PER_BIT)
(
input i_clk,
input i_rx,
output o_rx_byte_rdy,
output [7:0] o_rx_byte
);
localparam STATE_IDLE=5'b00001, STATE_START=5'b00010, STATE_DATA=5'b00100,
STATE_STOP=5'b01000, STATE_RESET=5'b10000;
reg r_rx_data_r = 1'b1;
reg r_rx_data = 1'b1;
reg [13:0] r_count = 0;
reg [2:0] r_bit_idx = 0;
reg [7:0] r_rx_byte = 0;
reg r_rx_byte_rdy = 0;
reg [4:0] r_state = STATE_IDLE;
always @(posedge i_clk)
begin
r_rx_data_r <= i_rx;
r_rx_data <= r_rx_data_r;
end
always @(posedge i_clk)
begin
case (r_state)
STATE_IDLE:
begin
r_rx_byte_rdy <= 1'b0;
r_count <= 0;
r_bit_idx <= 0;
if (r_rx_data == 1'b0)
r_state <= STATE_START;
else
r_state <= STATE_IDLE;
end
STATE_START:
begin
if (r_count == (CLKS_PER_BIT-1)/2)
begin
if (r_rx_data == 1'b0)
begin
r_count <= 0;
r_state <= STATE_DATA;
end
else
r_state <= STATE_IDLE;
end
else
begin
r_count <= r_count + 1;
r_state <= STATE_START;
end
end
STATE_DATA:
begin
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_DATA;
end
else
begin
r_count <= 0;
r_rx_byte[r_bit_idx] <= r_rx_data;
if (r_bit_idx < 7)
begin
r_bit_idx <= r_bit_idx + 1;
r_state <= STATE_DATA;
end
else
begin
r_bit_idx <= 0;
r_state <= STATE_STOP;
end
end
end
STATE_STOP:
begin
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_STOP;
end
else
begin
r_rx_byte_rdy <= 1'b1;
r_count <= 0;
r_state <= STATE_RESET;
end
end
STATE_RESET:
begin
r_state <= STATE_IDLE;
r_rx_byte_rdy <= 1'b0;
end
default:
r_state <= STATE_IDLE;
endcase
end
assign o_rx_byte_rdy = r_rx_byte_rdy;
assign o_rx_byte = r_rx_byte;
endmodule | module uart_rx
#(parameter CLKS_PER_BIT)
(
input i_clk,
input i_rx,
output o_rx_byte_rdy,
output [7:0] o_rx_byte
); |
localparam STATE_IDLE=5'b00001, STATE_START=5'b00010, STATE_DATA=5'b00100,
STATE_STOP=5'b01000, STATE_RESET=5'b10000;
reg r_rx_data_r = 1'b1;
reg r_rx_data = 1'b1;
reg [13:0] r_count = 0;
reg [2:0] r_bit_idx = 0;
reg [7:0] r_rx_byte = 0;
reg r_rx_byte_rdy = 0;
reg [4:0] r_state = STATE_IDLE;
always @(posedge i_clk)
begin
r_rx_data_r <= i_rx;
r_rx_data <= r_rx_data_r;
end
always @(posedge i_clk)
begin
case (r_state)
STATE_IDLE:
begin
r_rx_byte_rdy <= 1'b0;
r_count <= 0;
r_bit_idx <= 0;
if (r_rx_data == 1'b0)
r_state <= STATE_START;
else
r_state <= STATE_IDLE;
end
STATE_START:
begin
if (r_count == (CLKS_PER_BIT-1)/2)
begin
if (r_rx_data == 1'b0)
begin
r_count <= 0;
r_state <= STATE_DATA;
end
else
r_state <= STATE_IDLE;
end
else
begin
r_count <= r_count + 1;
r_state <= STATE_START;
end
end
STATE_DATA:
begin
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_DATA;
end
else
begin
r_count <= 0;
r_rx_byte[r_bit_idx] <= r_rx_data;
if (r_bit_idx < 7)
begin
r_bit_idx <= r_bit_idx + 1;
r_state <= STATE_DATA;
end
else
begin
r_bit_idx <= 0;
r_state <= STATE_STOP;
end
end
end
STATE_STOP:
begin
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_STOP;
end
else
begin
r_rx_byte_rdy <= 1'b1;
r_count <= 0;
r_state <= STATE_RESET;
end
end
STATE_RESET:
begin
r_state <= STATE_IDLE;
r_rx_byte_rdy <= 1'b0;
end
default:
r_state <= STATE_IDLE;
endcase
end
assign o_rx_byte_rdy = r_rx_byte_rdy;
assign o_rx_byte = r_rx_byte;
endmodule | 0 |
140,761 | data/full_repos/permissive/91223831/uart_tb.v | 91,223,831 | uart_tb.v | v | 90 | 80 | [] | [] | [] | null | line:77: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #(BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91223831/uart_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_PERIOD_NS/2) r_clk <= !r_clk;\n ^\n%Error: data/full_repos/permissive/91223831/uart_tb.v:68: syntax error, unexpected \'@\'\n @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/91223831/uart_tb.v:72: syntax error, unexpected \'@\'\n @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/91223831/uart_tb.v:74: syntax error, unexpected \'@\'\n @(posedge w_tx_done);\n ^\n%Error: data/full_repos/permissive/91223831/uart_tb.v:78: syntax error, unexpected \'@\'\n @(posedge r_clk);\n ^\n%Error: Exiting due to 4 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,655 | module | module uart_tb();
localparam CLOCK_PERIOD_NS = 20, CLKS_PER_BIT = 434, BIT_PERIOD = 434 * 20;
reg r_clk = 0;
reg r_tx_byte_rdy = 0;
wire w_tx_done;
reg [7:0] r_tx_byte = 0;
reg r_rx = 1;
wire [7:0] w_rx_byte;
task WRITE;
input [7:0] i_byte;
begin
r_rx <= 1'b0;
#(BIT_PERIOD);
#1000
r_rx <= i_byte[0];
#(BIT_PERIOD);
r_rx <= i_byte[1];
#(BIT_PERIOD);
r_rx <= i_byte[2];
#(BIT_PERIOD);
r_rx <= i_byte[3];
#(BIT_PERIOD);
r_rx <= i_byte[4];
#(BIT_PERIOD);
r_rx <= i_byte[5];
#(BIT_PERIOD);
r_rx <= i_byte[6];
#(BIT_PERIOD);
r_rx <= i_byte[7];
#(BIT_PERIOD);
r_rx <= 1'b1;
#(BIT_PERIOD);
end
endtask
uart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_TX_I1
(
.i_clk(r_clk),
.i_tx_byte_rdy(r_tx_byte_rdy),
.i_tx_byte(r_tx_byte),
.o_tx_busy(),
.o_tx(),
.o_tx_done(w_tx_done)
);
uart_rx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_RX_I1
(
.i_clk(r_clk),
.i_rx(r_rx),
.o_rx_byte_rdy(),
.o_rx_byte(w_rx_byte)
);
always #(CLOCK_PERIOD_NS/2) r_clk <= !r_clk;
initial
begin
@(posedge r_clk);
@(posedge r_clk);
r_tx_byte <= 8'hAB;
r_tx_byte_rdy <= 1'b1;
@(posedge r_clk);
r_tx_byte_rdy <= 1'b0;
@(posedge w_tx_done);
@(posedge r_clk);
WRITE(8'h3F);
@(posedge r_clk);
if (w_rx_byte == 8'h3F)
$display("tx/rx test passed");
else
$display("tx/rx test failed");
$finish;
end
endmodule | module uart_tb(); |
localparam CLOCK_PERIOD_NS = 20, CLKS_PER_BIT = 434, BIT_PERIOD = 434 * 20;
reg r_clk = 0;
reg r_tx_byte_rdy = 0;
wire w_tx_done;
reg [7:0] r_tx_byte = 0;
reg r_rx = 1;
wire [7:0] w_rx_byte;
task WRITE;
input [7:0] i_byte;
begin
r_rx <= 1'b0;
#(BIT_PERIOD);
#1000
r_rx <= i_byte[0];
#(BIT_PERIOD);
r_rx <= i_byte[1];
#(BIT_PERIOD);
r_rx <= i_byte[2];
#(BIT_PERIOD);
r_rx <= i_byte[3];
#(BIT_PERIOD);
r_rx <= i_byte[4];
#(BIT_PERIOD);
r_rx <= i_byte[5];
#(BIT_PERIOD);
r_rx <= i_byte[6];
#(BIT_PERIOD);
r_rx <= i_byte[7];
#(BIT_PERIOD);
r_rx <= 1'b1;
#(BIT_PERIOD);
end
endtask
uart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_TX_I1
(
.i_clk(r_clk),
.i_tx_byte_rdy(r_tx_byte_rdy),
.i_tx_byte(r_tx_byte),
.o_tx_busy(),
.o_tx(),
.o_tx_done(w_tx_done)
);
uart_rx #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_RX_I1
(
.i_clk(r_clk),
.i_rx(r_rx),
.o_rx_byte_rdy(),
.o_rx_byte(w_rx_byte)
);
always #(CLOCK_PERIOD_NS/2) r_clk <= !r_clk;
initial
begin
@(posedge r_clk);
@(posedge r_clk);
r_tx_byte <= 8'hAB;
r_tx_byte_rdy <= 1'b1;
@(posedge r_clk);
r_tx_byte_rdy <= 1'b0;
@(posedge w_tx_done);
@(posedge r_clk);
WRITE(8'h3F);
@(posedge r_clk);
if (w_rx_byte == 8'h3F)
$display("tx/rx test passed");
else
$display("tx/rx test failed");
$finish;
end
endmodule | 0 |
140,762 | data/full_repos/permissive/91223831/uart_tx.v | 91,223,831 | uart_tx.v | v | 109 | 92 | [] | [] | [] | null | line:4: before: ")" | null | 1: b"%Error: data/full_repos/permissive/91223831/uart_tx.v:4: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'CLKS_PER_BIT'\n : ... In instance uart_tx\n #(parameter CLKS_PER_BIT)\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,656 | module | module uart_tx
#(parameter CLKS_PER_BIT)
(
input i_clk,
input i_tx_byte_rdy,
input [7:0] i_tx_byte,
output o_tx_busy,
output reg o_tx
);
localparam STATE_IDLE=5'b00001, STATE_START=5'b00010, STATE_DATA=5'b00100,
STATE_STOP=5'b01000, STATE_RESET=5'b10000;
reg [13:0] r_count = 0;
reg [2:0] r_bit_idx = 0;
reg [7:0] r_tx_byte;
reg r_tx_busy = 0;
reg [4:0] r_state = STATE_IDLE;
always @(posedge i_clk)
begin
case (r_state)
STATE_IDLE:
begin
o_tx <= 1'b1;
r_count <= 0;
r_bit_idx <= 0;
if (i_tx_byte_rdy == 1'b1)
begin
r_tx_busy <= 1'b1;
r_tx_byte <= i_tx_byte;
r_state <= STATE_START;
end
else
r_state <= STATE_IDLE;
end
STATE_START:
begin
o_tx <= 1'b0;
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_START;
end
else
begin
r_count <= 0;
r_state <= STATE_DATA;
end
end
STATE_DATA:
begin
o_tx <= r_tx_byte[r_bit_idx];
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_DATA;
end
else
begin
r_count <= 0;
if (r_bit_idx < 7)
begin
r_bit_idx <= r_bit_idx + 1;
r_state <= STATE_DATA;
end
else
begin
r_bit_idx <= 0;
r_state <= STATE_STOP;
end
end
end
STATE_STOP:
begin
o_tx <= 1'b1;
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_STOP;
end
else
begin
r_count = 0;
r_state = STATE_RESET;
end
end
STATE_RESET:
begin
r_tx_busy <= 1'b0;
r_state <= STATE_IDLE;
end
default:
r_state <= STATE_IDLE;
endcase
end
assign o_tx_busy = r_tx_busy;
endmodule | module uart_tx
#(parameter CLKS_PER_BIT)
(
input i_clk,
input i_tx_byte_rdy,
input [7:0] i_tx_byte,
output o_tx_busy,
output reg o_tx
); |
localparam STATE_IDLE=5'b00001, STATE_START=5'b00010, STATE_DATA=5'b00100,
STATE_STOP=5'b01000, STATE_RESET=5'b10000;
reg [13:0] r_count = 0;
reg [2:0] r_bit_idx = 0;
reg [7:0] r_tx_byte;
reg r_tx_busy = 0;
reg [4:0] r_state = STATE_IDLE;
always @(posedge i_clk)
begin
case (r_state)
STATE_IDLE:
begin
o_tx <= 1'b1;
r_count <= 0;
r_bit_idx <= 0;
if (i_tx_byte_rdy == 1'b1)
begin
r_tx_busy <= 1'b1;
r_tx_byte <= i_tx_byte;
r_state <= STATE_START;
end
else
r_state <= STATE_IDLE;
end
STATE_START:
begin
o_tx <= 1'b0;
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_START;
end
else
begin
r_count <= 0;
r_state <= STATE_DATA;
end
end
STATE_DATA:
begin
o_tx <= r_tx_byte[r_bit_idx];
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_DATA;
end
else
begin
r_count <= 0;
if (r_bit_idx < 7)
begin
r_bit_idx <= r_bit_idx + 1;
r_state <= STATE_DATA;
end
else
begin
r_bit_idx <= 0;
r_state <= STATE_STOP;
end
end
end
STATE_STOP:
begin
o_tx <= 1'b1;
if (r_count < (CLKS_PER_BIT-1))
begin
r_count <= r_count + 1;
r_state <= STATE_STOP;
end
else
begin
r_count = 0;
r_state = STATE_RESET;
end
end
STATE_RESET:
begin
r_tx_busy <= 1'b0;
r_state <= STATE_IDLE;
end
default:
r_state <= STATE_IDLE;
endcase
end
assign o_tx_busy = r_tx_busy;
endmodule | 0 |
140,763 | data/full_repos/permissive/91223831/vx.v | 91,223,831 | vx.v | v | 49 | 43 | [] | [] | [] | [(6, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/91223831/vx.v:22: Cannot find file containing module: 'uart'\n uart UART_I1 \n ^~~~\n ... Looked in:\n data/full_repos/permissive/91223831,data/full_repos/permissive/91223831/uart\n data/full_repos/permissive/91223831,data/full_repos/permissive/91223831/uart.v\n data/full_repos/permissive/91223831,data/full_repos/permissive/91223831/uart.sv\n uart\n uart.v\n uart.sv\n obj_dir/uart\n obj_dir/uart.v\n obj_dir/uart.sv\n%Error: data/full_repos/permissive/91223831/vx.v:35: Cannot find file containing module: 'fifo'\n fifo LOOPFIFO\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 309,657 | module | module vx
(
input wire i_clk,
input wire i_rx,
output wire o_tx,
output wire o_tx_busy
);
wire w_tx_byte_rdy;
wire [7:0] w_tx_byte;
wire w_tx_done;
wire w_rx_byte_rdy;
wire [7:0] w_rx_byte;
uart UART_I1
(
.i_clk(i_clk),
.i_rx(i_rw),
.o_tx(o_tx),
.i_tx_byte_rdy(w_tx_byte_rdy),
.i_tx_byte(w_tx_byte),
.o_tx_busy(o_tx_busy),
.o_tx_done(w_tx_done),
.o_rx_byte_rdy(w_rx_byte_rdy),
.o_rx_byte(w_rx_byte)
);
fifo LOOPFIFO
(
.clk(i_clk),
.rst(),
.buf_in(w_rx_byte),
.buf_out(w_tx_byte),
.wr_en(w_rx_byte_rdy),
.rd_en(w_tx_byte_rdy),
.buf_empty(),
.buf_full(),
.fifo_counter()
);
endmodule | module vx
(
input wire i_clk,
input wire i_rx,
output wire o_tx,
output wire o_tx_busy
); |
wire w_tx_byte_rdy;
wire [7:0] w_tx_byte;
wire w_tx_done;
wire w_rx_byte_rdy;
wire [7:0] w_rx_byte;
uart UART_I1
(
.i_clk(i_clk),
.i_rx(i_rw),
.o_tx(o_tx),
.i_tx_byte_rdy(w_tx_byte_rdy),
.i_tx_byte(w_tx_byte),
.o_tx_busy(o_tx_busy),
.o_tx_done(w_tx_done),
.o_rx_byte_rdy(w_rx_byte_rdy),
.o_rx_byte(w_rx_byte)
);
fifo LOOPFIFO
(
.clk(i_clk),
.rst(),
.buf_in(w_rx_byte),
.buf_out(w_tx_byte),
.wr_en(w_rx_byte_rdy),
.rd_en(w_tx_byte_rdy),
.buf_empty(),
.buf_full(),
.fifo_counter()
);
endmodule | 0 |
140,766 | data/full_repos/permissive/91359513/buffer_test.v | 91,359,513 | buffer_test.v | v | 59 | 44 | [] | [] | [] | [(5, 58)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91359513/buffer_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91359513/buffer_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91359513/buffer_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91359513/buffer_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91359513/buffer_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/91359513/buffer_test.v:43: Cannot find file containing module: \'buffer\'\n buffer #(B) b1\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/91359513,data/full_repos/permissive/91359513/buffer\n data/full_repos/permissive/91359513,data/full_repos/permissive/91359513/buffer.v\n data/full_repos/permissive/91359513,data/full_repos/permissive/91359513/buffer.sv\n buffer\n buffer.v\n buffer.sv\n obj_dir/buffer\n obj_dir/buffer.v\n obj_dir/buffer.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,662 | module | module buffer_test();
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#50
counter = counter + 1;
new_sample_val = 1'b1;
#10
new_sample_val = 1'b0;
end
buffer #(B) b1
(
.clk(CLOCK_50),
.rst(rst),
.delta(8'b01000000),
.new_sample_val(new_sample_val),
.new_sample_data(counter),
.out_sel(1'b0),
.delta_mode(1'b0),
.pitch_shift_out(pitch_shift_out),
.pitch_shift_val(pitch_shift_val)
);
endmodule | module buffer_test(); |
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#50
counter = counter + 1;
new_sample_val = 1'b1;
#10
new_sample_val = 1'b0;
end
buffer #(B) b1
(
.clk(CLOCK_50),
.rst(rst),
.delta(8'b01000000),
.new_sample_val(new_sample_val),
.new_sample_data(counter),
.out_sel(1'b0),
.delta_mode(1'b0),
.pitch_shift_out(pitch_shift_out),
.pitch_shift_val(pitch_shift_val)
);
endmodule | 17 |
140,773 | data/full_repos/permissive/91359513/EBABWrapper.v | 91,359,513 | EBABWrapper.v | v | 265 | 99 | [] | [] | [] | [(4, 264)] | null | null | 1: b'%Error: data/full_repos/permissive/91359513/EBABWrapper.v:44: Cannot find file containing module: \'buffer\'\n buffer #(1024) left_buffer\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/91359513,data/full_repos/permissive/91359513/buffer\n data/full_repos/permissive/91359513,data/full_repos/permissive/91359513/buffer.v\n data/full_repos/permissive/91359513,data/full_repos/permissive/91359513/buffer.sv\n buffer\n buffer.v\n buffer.sv\n obj_dir/buffer\n obj_dir/buffer.v\n obj_dir/buffer.sv\n%Error: data/full_repos/permissive/91359513/EBABWrapper.v:60: Cannot find file containing module: \'buffer\'\n buffer #(1024) right_buffer\n ^~~~~~\n%Error: data/full_repos/permissive/91359513/EBABWrapper.v:76: Cannot find file containing module: \'IIR6_32bit_fixed\'\n IIR6_32bit_fixed filter_left(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91359513/EBABWrapper.v:99: Cannot find file containing module: \'IIR6_32bit_fixed\'\n IIR6_32bit_fixed filter_right(\n ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91359513/EBABWrapper.v:145: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n : ... In instance EBABWrapper\n fifo_space <= (bus_read_data>>24);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91359513/EBABWrapper.v:208: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n : ... In instance EBABWrapper\n fifo_space <= bus_read_data & 8\'hff;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91359513/EBABWrapper.v:208: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n : ... In instance EBABWrapper\n fifo_space <= bus_read_data & 8\'hff;\n ^~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 309,667 | module | module EBABWrapper
(
bus_byte_enable, bus_read, bus_write, bus_write_data, bus_addr,
clk, rst, out_sel, delta_mode_left, delta_mode_right, bus_ack,
bus_read_data, delta_left, delta_right, triangle_wave_max_left,
triangle_wave_max_right
);
input clk, rst, out_sel, delta_mode_left, delta_mode_right;
input bus_ack;
input [31:0] bus_read_data;
input [31:0] delta_left, delta_right;
input [9:0] triangle_wave_max_left, triangle_wave_max_right;
output reg [3:0] bus_byte_enable;
output reg bus_read;
output reg bus_write;
output reg [31:0] bus_write_data;
output reg [31:0] bus_addr;
wire [31:0] audio_base_address = 32'h00003040;
wire [31:0] audio_fifo_address = 32'h00003044;
wire [31:0] audio_data_left_address = 32'h00003048;
wire [31:0] audio_data_right_address = 32'h0000304c;
reg [3:0] state;
reg [7:0] fifo_space;
reg [31:0] right_audio_input, left_audio_input;
reg audio_input_valid;
wire [31:0] right_audio_output, left_audio_output, pitch_shift_out[0:1], filter_out[0:1];
wire pitch_shift_val[0:1], audio_out_val[0:1];
assign left_audio_output = (audio_out_val[0]) ? filter_out[0] : left_audio_output;
assign right_audio_output = (audio_out_val[1]) ? filter_out[1] : right_audio_output;
buffer #(1024) left_buffer
(
.clk(clk),
.rst(rst),
.delta(delta_left),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_left),
.triangle_wave_max(triangle_wave_max_left),
.pitch_shift_out(pitch_shift_out[0]),
.pitch_shift_val(pitch_shift_val[0])
);
buffer #(1024) right_buffer
(
.clk(clk),
.rst(rst),
.delta(delta_right),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_right),
.triangle_wave_max(triangle_wave_max_right),
.pitch_shift_out(pitch_shift_out[1]),
.pitch_shift_val(pitch_shift_val[1])
);
IIR6_32bit_fixed filter_left(
.audio_out (filter_out[0]),
.audio_in (pitch_shift_out[0]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[0]),
.rst(rst),
.audio_out_val(audio_out_val[0])
) ;
IIR6_32bit_fixed filter_right(
.audio_out (filter_out[1]),
.audio_in (pitch_shift_out[1]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[1]),
.rst(rst),
.audio_out_val(audio_out_val[1])
) ;
always @(posedge clk) begin
if (rst) begin
state <= 0;
bus_read <= 0;
bus_write <= 0;
end
if (state==4'd0) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd1;
end
if (state==4'd1 && bus_ack==1) begin
state <= 4'd2;
fifo_space <= (bus_read_data>>24);
bus_read <= 1'b0;
end
if (state==4'd2 && fifo_space>8'd2) begin
state <= 4'd3;
bus_write_data <= left_audio_output;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_write <= 1'b1;
end
else if (state==4'd2 && fifo_space<=8'd2) begin
state <= 4'b0;
end
if (state==4'd3 && bus_ack==1) begin
state <= 4'd4;
bus_write <= 0;
end
if (state==4'd4) begin
state <= 4'd5;
bus_write_data <= right_audio_output;
bus_addr <= audio_data_right_address;
bus_write <= 1'b1;
end
if (state==4'd5 && bus_ack==1) begin
state <= 4'd6;
bus_write <= 0;
end
if (state==4'd6 ) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd7;
end
if (state==4'd7 && bus_ack==1) begin
state <= 4'd8;
fifo_space <= bus_read_data & 8'hff;
bus_read <= 1'b0;
end
if (state==4'd8 && fifo_space>8'd0) begin
state <= 4'd9;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
else if (state==4'd8 && fifo_space<=8'd0) begin
state <= 4'b0;
end
if (state==4'd9 && bus_ack==1) begin
state <= 4'd10;
left_audio_input <= bus_read_data;
bus_read <= 0;
end
if (state==4'd10) begin
state <= 4'd11;
bus_addr <= audio_data_right_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
if (state==4'd11 && bus_ack==1) begin
state <= 4'd12;
right_audio_input <= bus_read_data;
audio_input_valid <= 1'b1;
bus_read <= 0;
end
if (state==4'd12) begin
state <= 4'd0;
audio_input_valid <= 1'b0;
end
end
endmodule | module EBABWrapper
(
bus_byte_enable, bus_read, bus_write, bus_write_data, bus_addr,
clk, rst, out_sel, delta_mode_left, delta_mode_right, bus_ack,
bus_read_data, delta_left, delta_right, triangle_wave_max_left,
triangle_wave_max_right
); |
input clk, rst, out_sel, delta_mode_left, delta_mode_right;
input bus_ack;
input [31:0] bus_read_data;
input [31:0] delta_left, delta_right;
input [9:0] triangle_wave_max_left, triangle_wave_max_right;
output reg [3:0] bus_byte_enable;
output reg bus_read;
output reg bus_write;
output reg [31:0] bus_write_data;
output reg [31:0] bus_addr;
wire [31:0] audio_base_address = 32'h00003040;
wire [31:0] audio_fifo_address = 32'h00003044;
wire [31:0] audio_data_left_address = 32'h00003048;
wire [31:0] audio_data_right_address = 32'h0000304c;
reg [3:0] state;
reg [7:0] fifo_space;
reg [31:0] right_audio_input, left_audio_input;
reg audio_input_valid;
wire [31:0] right_audio_output, left_audio_output, pitch_shift_out[0:1], filter_out[0:1];
wire pitch_shift_val[0:1], audio_out_val[0:1];
assign left_audio_output = (audio_out_val[0]) ? filter_out[0] : left_audio_output;
assign right_audio_output = (audio_out_val[1]) ? filter_out[1] : right_audio_output;
buffer #(1024) left_buffer
(
.clk(clk),
.rst(rst),
.delta(delta_left),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_left),
.triangle_wave_max(triangle_wave_max_left),
.pitch_shift_out(pitch_shift_out[0]),
.pitch_shift_val(pitch_shift_val[0])
);
buffer #(1024) right_buffer
(
.clk(clk),
.rst(rst),
.delta(delta_right),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_right),
.triangle_wave_max(triangle_wave_max_right),
.pitch_shift_out(pitch_shift_out[1]),
.pitch_shift_val(pitch_shift_val[1])
);
IIR6_32bit_fixed filter_left(
.audio_out (filter_out[0]),
.audio_in (pitch_shift_out[0]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[0]),
.rst(rst),
.audio_out_val(audio_out_val[0])
) ;
IIR6_32bit_fixed filter_right(
.audio_out (filter_out[1]),
.audio_in (pitch_shift_out[1]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[1]),
.rst(rst),
.audio_out_val(audio_out_val[1])
) ;
always @(posedge clk) begin
if (rst) begin
state <= 0;
bus_read <= 0;
bus_write <= 0;
end
if (state==4'd0) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd1;
end
if (state==4'd1 && bus_ack==1) begin
state <= 4'd2;
fifo_space <= (bus_read_data>>24);
bus_read <= 1'b0;
end
if (state==4'd2 && fifo_space>8'd2) begin
state <= 4'd3;
bus_write_data <= left_audio_output;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_write <= 1'b1;
end
else if (state==4'd2 && fifo_space<=8'd2) begin
state <= 4'b0;
end
if (state==4'd3 && bus_ack==1) begin
state <= 4'd4;
bus_write <= 0;
end
if (state==4'd4) begin
state <= 4'd5;
bus_write_data <= right_audio_output;
bus_addr <= audio_data_right_address;
bus_write <= 1'b1;
end
if (state==4'd5 && bus_ack==1) begin
state <= 4'd6;
bus_write <= 0;
end
if (state==4'd6 ) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd7;
end
if (state==4'd7 && bus_ack==1) begin
state <= 4'd8;
fifo_space <= bus_read_data & 8'hff;
bus_read <= 1'b0;
end
if (state==4'd8 && fifo_space>8'd0) begin
state <= 4'd9;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
else if (state==4'd8 && fifo_space<=8'd0) begin
state <= 4'b0;
end
if (state==4'd9 && bus_ack==1) begin
state <= 4'd10;
left_audio_input <= bus_read_data;
bus_read <= 0;
end
if (state==4'd10) begin
state <= 4'd11;
bus_addr <= audio_data_right_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
if (state==4'd11 && bus_ack==1) begin
state <= 4'd12;
right_audio_input <= bus_read_data;
audio_input_valid <= 1'b1;
bus_read <= 0;
end
if (state==4'd12) begin
state <= 4'd0;
audio_input_valid <= 1'b0;
end
end
endmodule | 17 |
140,777 | data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v | 91,684,990 | phantom_dummy_4_v1_0_tb.v | v | 306 | 170 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:4: Cannot find include file: phantom_dummy_4_v1_0_tb_include.vh\n`include "phantom_dummy_4_v1_0_tb_include.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design,data/full_repos/permissive/91684990/phantom_dummy_4_v1_0_tb_include.vh\n data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design,data/full_repos/permissive/91684990/phantom_dummy_4_v1_0_tb_include.vh.v\n data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design,data/full_repos/permissive/91684990/phantom_dummy_4_v1_0_tb_include.vh.sv\n phantom_dummy_4_v1_0_tb_include.vh\n phantom_dummy_4_v1_0_tb_include.vh.v\n phantom_dummy_4_v1_0_tb_include.vh.sv\n obj_dir/phantom_dummy_4_v1_0_tb_include.vh\n obj_dir/phantom_dummy_4_v1_0_tb_include.vh.v\n obj_dir/phantom_dummy_4_v1_0_tb_include.vh.sv\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:40: Define or directive not defined: \'`BD_WRAPPER\'\n `BD_WRAPPER dut (.ACLK(tb_ACLK),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:40: syntax error, unexpected \'(\', expecting IDENTIFIER\n `BD_WRAPPER dut (.ACLK(tb_ACLK),\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #500;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:73: syntax error, unexpected \'@\'\n @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:75: syntax error, unexpected \'@\'\n @(posedge tb_ACLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #10 tb_ACLK = !tb_ACLK;\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:145: Define or directive not defined: \'`S00_AXI_SLAVE_ADDRESS\'\n S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:145: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:153: Define or directive not defined: \'`BD_INST_NAME\'\n dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:153: syntax error, unexpected \'.\'\n dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:160: Define or directive not defined: \'`BD_INST_NAME\'\n dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:160: syntax error, unexpected \'.\'\n dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:185: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:185: Unsupported: wait statements\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:186: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:186: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:187: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:187: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:188: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:188: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:189: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:189: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:191: Define or directive not defined: \'`BD_INST_NAME\'\n dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:191: syntax error, unexpected \'.\'\n dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:203: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:203: Unsupported: wait statements\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:204: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:204: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:205: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:205: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:206: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:206: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:207: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:207: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:216: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:216: Unsupported: wait statements\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:217: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:217: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:218: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:218: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:219: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:219: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:220: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:220: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n #500 M00_AXI_INIT_AXI_TXN = 1\'b1;\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:226: Unsupported: wait statements\n wait( M00_AXI_TXN_DONE == 1\'b1);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:239: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:239: Unsupported: wait statements\n wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:240: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:240: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n ^~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:241: syntax error, unexpected \'@\'\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/example_designs/bfm_design/phantom_dummy_4_v1_0_tb.v:241: Unsupported: wait statements\n wait(tb_ARESETn === 1) @(posedge tb_ACLK); \n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 309,686 | module | module phantom_dummy_4_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M00_AXI_INIT_AXI_TXN;
wire M00_AXI_TXN_DONE;
wire M00_AXI_ERROR;
reg M01_AXI_INIT_AXI_TXN;
wire M01_AXI_TXN_DONE;
wire M01_AXI_ERROR;
reg M02_AXI_INIT_AXI_TXN;
wire M02_AXI_TXN_DONE;
wire M02_AXI_ERROR;
reg M03_AXI_INIT_AXI_TXN;
wire M03_AXI_TXN_DONE;
wire M03_AXI_ERROR;
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
.M00_AXI_ERROR(M00_AXI_ERROR),
.M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN),
.M01_AXI_TXN_DONE(M01_AXI_TXN_DONE),
.M01_AXI_ERROR(M01_AXI_ERROR),
.M01_AXI_INIT_AXI_TXN(M01_AXI_INIT_AXI_TXN),
.M02_AXI_TXN_DONE(M02_AXI_TXN_DONE),
.M02_AXI_ERROR(M02_AXI_ERROR),
.M02_AXI_INIT_AXI_TXN(M02_AXI_INIT_AXI_TXN),
.M03_AXI_TXN_DONE(M03_AXI_TXN_DONE),
.M03_AXI_ERROR(M03_AXI_ERROR),
.M03_AXI_INIT_AXI_TXN(M03_AXI_INIT_AXI_TXN));
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite;
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
initial begin
tb_ARESETn = 1'b0;
#500;
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M00_AXI_INIT_AXI_TXN = 1'b0;
#500 M00_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M00_AXI:");
wait( M00_AXI_TXN_DONE == 1'b1);
$display("M00_AXI: PTGEN_TEST_FINISHED!");
if ( M00_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M01_AXI_INIT_AXI_TXN = 1'b0;
#500 M01_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M01_AXI:");
wait( M01_AXI_TXN_DONE == 1'b1);
$display("M01_AXI: PTGEN_TEST_FINISHED!");
if ( M01_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M02_AXI_INIT_AXI_TXN = 1'b0;
#500 M02_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M02_AXI:");
wait( M02_AXI_TXN_DONE == 1'b1);
$display("M02_AXI: PTGEN_TEST_FINISHED!");
if ( M02_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M03_AXI_INIT_AXI_TXN = 1'b0;
#500 M03_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M03_AXI:");
wait( M03_AXI_TXN_DONE == 1'b1);
$display("M03_AXI: PTGEN_TEST_FINISHED!");
if ( M03_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
endmodule | module phantom_dummy_4_v1_0_tb; |
reg tb_ACLK;
reg tb_ARESETn;
reg M00_AXI_INIT_AXI_TXN;
wire M00_AXI_TXN_DONE;
wire M00_AXI_ERROR;
reg M01_AXI_INIT_AXI_TXN;
wire M01_AXI_TXN_DONE;
wire M01_AXI_ERROR;
reg M02_AXI_INIT_AXI_TXN;
wire M02_AXI_TXN_DONE;
wire M02_AXI_ERROR;
reg M03_AXI_INIT_AXI_TXN;
wire M03_AXI_TXN_DONE;
wire M03_AXI_ERROR;
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
.M00_AXI_ERROR(M00_AXI_ERROR),
.M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN),
.M01_AXI_TXN_DONE(M01_AXI_TXN_DONE),
.M01_AXI_ERROR(M01_AXI_ERROR),
.M01_AXI_INIT_AXI_TXN(M01_AXI_INIT_AXI_TXN),
.M02_AXI_TXN_DONE(M02_AXI_TXN_DONE),
.M02_AXI_ERROR(M02_AXI_ERROR),
.M02_AXI_INIT_AXI_TXN(M02_AXI_INIT_AXI_TXN),
.M03_AXI_TXN_DONE(M03_AXI_TXN_DONE),
.M03_AXI_ERROR(M03_AXI_ERROR),
.M03_AXI_INIT_AXI_TXN(M03_AXI_INIT_AXI_TXN));
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite;
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
initial begin
tb_ARESETn = 1'b0;
#500;
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M00_AXI_INIT_AXI_TXN = 1'b0;
#500 M00_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M00_AXI:");
wait( M00_AXI_TXN_DONE == 1'b1);
$display("M00_AXI: PTGEN_TEST_FINISHED!");
if ( M00_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M01_AXI_INIT_AXI_TXN = 1'b0;
#500 M01_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M01_AXI:");
wait( M01_AXI_TXN_DONE == 1'b1);
$display("M01_AXI: PTGEN_TEST_FINISHED!");
if ( M01_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M02_AXI_INIT_AXI_TXN = 1'b0;
#500 M02_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M02_AXI:");
wait( M02_AXI_TXN_DONE == 1'b1);
$display("M02_AXI: PTGEN_TEST_FINISHED!");
if ( M02_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
initial begin
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M03_AXI_INIT_AXI_TXN = 1'b0;
#500 M03_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M03_AXI:");
wait( M03_AXI_TXN_DONE == 1'b1);
$display("M03_AXI: PTGEN_TEST_FINISHED!");
if ( M03_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
endmodule | 1 |
140,778 | data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v | 91,684,990 | phantom_dummy_4_v1_0.v | v | 571 | 65 | [] | [] | [] | [(4, 570)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:86: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:92: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:97: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:109: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:116: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:135: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M01_AXI_AWUSER_WIDTH-1 : 0] m01_axi_awuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:141: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M01_AXI_WUSER_WIDTH-1 : 0] m01_axi_wuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:146: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M01_AXI_BUSER_WIDTH-1 : 0] m01_axi_buser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:158: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M01_AXI_ARUSER_WIDTH-1 : 0] m01_axi_aruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:165: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M01_AXI_RUSER_WIDTH-1 : 0] m01_axi_ruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:184: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M02_AXI_AWUSER_WIDTH-1 : 0] m02_axi_awuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:190: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M02_AXI_WUSER_WIDTH-1 : 0] m02_axi_wuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:195: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M02_AXI_BUSER_WIDTH-1 : 0] m02_axi_buser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:207: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M02_AXI_ARUSER_WIDTH-1 : 0] m02_axi_aruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:214: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M02_AXI_RUSER_WIDTH-1 : 0] m02_axi_ruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:233: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M03_AXI_AWUSER_WIDTH-1 : 0] m03_axi_awuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:239: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M03_AXI_WUSER_WIDTH-1 : 0] m03_axi_wuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:244: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M03_AXI_BUSER_WIDTH-1 : 0] m03_axi_buser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:256: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M03_AXI_ARUSER_WIDTH-1 : 0] m03_axi_aruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:263: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M03_AXI_RUSER_WIDTH-1 : 0] m03_axi_ruser,\n ^\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:291: Cannot find file containing module: \'phantom_dummy_4_v1_0_M00_AXI\'\n phantom_dummy_4_v1_0_M00_AXI # ( \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl,data/full_repos/permissive/91684990/phantom_dummy_4_v1_0_M00_AXI\n data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl,data/full_repos/permissive/91684990/phantom_dummy_4_v1_0_M00_AXI.v\n data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl,data/full_repos/permissive/91684990/phantom_dummy_4_v1_0_M00_AXI.sv\n phantom_dummy_4_v1_0_M00_AXI\n phantom_dummy_4_v1_0_M00_AXI.v\n phantom_dummy_4_v1_0_M00_AXI.sv\n obj_dir/phantom_dummy_4_v1_0_M00_AXI\n obj_dir/phantom_dummy_4_v1_0_M00_AXI.v\n obj_dir/phantom_dummy_4_v1_0_M00_AXI.sv\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:353: Cannot find file containing module: \'phantom_dummy_4_v1_0_M01_AXI\'\n phantom_dummy_4_v1_0_M01_AXI # ( \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:415: Cannot find file containing module: \'phantom_dummy_4_v1_0_M02_AXI\'\n phantom_dummy_4_v1_0_M02_AXI # ( \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:477: Cannot find file containing module: \'phantom_dummy_4_v1_0_M03_AXI\'\n phantom_dummy_4_v1_0_M03_AXI # ( \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/91684990/arch/phantom_ip/phantom_dummy_4_1.0/hdl/phantom_dummy_4_v1_0.v:539: Cannot find file containing module: \'phantom_dummy_4_v1_0_S00_AXI\'\n phantom_dummy_4_v1_0_S00_AXI # ( \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 20 warning(s)\n' | 309,687 | module | module phantom_dummy_4_v1_0 #
(
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0,
parameter C_M01_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M01_AXI_BURST_LEN = 16,
parameter integer C_M01_AXI_ID_WIDTH = 1,
parameter integer C_M01_AXI_ADDR_WIDTH = 32,
parameter integer C_M01_AXI_DATA_WIDTH = 32,
parameter integer C_M01_AXI_AWUSER_WIDTH = 0,
parameter integer C_M01_AXI_ARUSER_WIDTH = 0,
parameter integer C_M01_AXI_WUSER_WIDTH = 0,
parameter integer C_M01_AXI_RUSER_WIDTH = 0,
parameter integer C_M01_AXI_BUSER_WIDTH = 0,
parameter C_M02_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M02_AXI_BURST_LEN = 16,
parameter integer C_M02_AXI_ID_WIDTH = 1,
parameter integer C_M02_AXI_ADDR_WIDTH = 32,
parameter integer C_M02_AXI_DATA_WIDTH = 32,
parameter integer C_M02_AXI_AWUSER_WIDTH = 0,
parameter integer C_M02_AXI_ARUSER_WIDTH = 0,
parameter integer C_M02_AXI_WUSER_WIDTH = 0,
parameter integer C_M02_AXI_RUSER_WIDTH = 0,
parameter integer C_M02_AXI_BUSER_WIDTH = 0,
parameter C_M03_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M03_AXI_BURST_LEN = 16,
parameter integer C_M03_AXI_ID_WIDTH = 1,
parameter integer C_M03_AXI_ADDR_WIDTH = 32,
parameter integer C_M03_AXI_DATA_WIDTH = 32,
parameter integer C_M03_AXI_AWUSER_WIDTH = 0,
parameter integer C_M03_AXI_ARUSER_WIDTH = 0,
parameter integer C_M03_AXI_WUSER_WIDTH = 0,
parameter integer C_M03_AXI_RUSER_WIDTH = 0,
parameter integer C_M03_AXI_BUSER_WIDTH = 0,
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
input wire m00_axi_init_axi_txn,
output wire m00_axi_txn_done,
output wire m00_axi_error,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready,
input wire m01_axi_init_axi_txn,
output wire m01_axi_txn_done,
output wire m01_axi_error,
input wire m01_axi_aclk,
input wire m01_axi_aresetn,
output wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_awid,
output wire [C_M01_AXI_ADDR_WIDTH-1 : 0] m01_axi_awaddr,
output wire [7 : 0] m01_axi_awlen,
output wire [2 : 0] m01_axi_awsize,
output wire [1 : 0] m01_axi_awburst,
output wire m01_axi_awlock,
output wire [3 : 0] m01_axi_awcache,
output wire [2 : 0] m01_axi_awprot,
output wire [3 : 0] m01_axi_awqos,
output wire [C_M01_AXI_AWUSER_WIDTH-1 : 0] m01_axi_awuser,
output wire m01_axi_awvalid,
input wire m01_axi_awready,
output wire [C_M01_AXI_DATA_WIDTH-1 : 0] m01_axi_wdata,
output wire [C_M01_AXI_DATA_WIDTH/8-1 : 0] m01_axi_wstrb,
output wire m01_axi_wlast,
output wire [C_M01_AXI_WUSER_WIDTH-1 : 0] m01_axi_wuser,
output wire m01_axi_wvalid,
input wire m01_axi_wready,
input wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_bid,
input wire [1 : 0] m01_axi_bresp,
input wire [C_M01_AXI_BUSER_WIDTH-1 : 0] m01_axi_buser,
input wire m01_axi_bvalid,
output wire m01_axi_bready,
output wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_arid,
output wire [C_M01_AXI_ADDR_WIDTH-1 : 0] m01_axi_araddr,
output wire [7 : 0] m01_axi_arlen,
output wire [2 : 0] m01_axi_arsize,
output wire [1 : 0] m01_axi_arburst,
output wire m01_axi_arlock,
output wire [3 : 0] m01_axi_arcache,
output wire [2 : 0] m01_axi_arprot,
output wire [3 : 0] m01_axi_arqos,
output wire [C_M01_AXI_ARUSER_WIDTH-1 : 0] m01_axi_aruser,
output wire m01_axi_arvalid,
input wire m01_axi_arready,
input wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_rid,
input wire [C_M01_AXI_DATA_WIDTH-1 : 0] m01_axi_rdata,
input wire [1 : 0] m01_axi_rresp,
input wire m01_axi_rlast,
input wire [C_M01_AXI_RUSER_WIDTH-1 : 0] m01_axi_ruser,
input wire m01_axi_rvalid,
output wire m01_axi_rready,
input wire m02_axi_init_axi_txn,
output wire m02_axi_txn_done,
output wire m02_axi_error,
input wire m02_axi_aclk,
input wire m02_axi_aresetn,
output wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_awid,
output wire [C_M02_AXI_ADDR_WIDTH-1 : 0] m02_axi_awaddr,
output wire [7 : 0] m02_axi_awlen,
output wire [2 : 0] m02_axi_awsize,
output wire [1 : 0] m02_axi_awburst,
output wire m02_axi_awlock,
output wire [3 : 0] m02_axi_awcache,
output wire [2 : 0] m02_axi_awprot,
output wire [3 : 0] m02_axi_awqos,
output wire [C_M02_AXI_AWUSER_WIDTH-1 : 0] m02_axi_awuser,
output wire m02_axi_awvalid,
input wire m02_axi_awready,
output wire [C_M02_AXI_DATA_WIDTH-1 : 0] m02_axi_wdata,
output wire [C_M02_AXI_DATA_WIDTH/8-1 : 0] m02_axi_wstrb,
output wire m02_axi_wlast,
output wire [C_M02_AXI_WUSER_WIDTH-1 : 0] m02_axi_wuser,
output wire m02_axi_wvalid,
input wire m02_axi_wready,
input wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_bid,
input wire [1 : 0] m02_axi_bresp,
input wire [C_M02_AXI_BUSER_WIDTH-1 : 0] m02_axi_buser,
input wire m02_axi_bvalid,
output wire m02_axi_bready,
output wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_arid,
output wire [C_M02_AXI_ADDR_WIDTH-1 : 0] m02_axi_araddr,
output wire [7 : 0] m02_axi_arlen,
output wire [2 : 0] m02_axi_arsize,
output wire [1 : 0] m02_axi_arburst,
output wire m02_axi_arlock,
output wire [3 : 0] m02_axi_arcache,
output wire [2 : 0] m02_axi_arprot,
output wire [3 : 0] m02_axi_arqos,
output wire [C_M02_AXI_ARUSER_WIDTH-1 : 0] m02_axi_aruser,
output wire m02_axi_arvalid,
input wire m02_axi_arready,
input wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_rid,
input wire [C_M02_AXI_DATA_WIDTH-1 : 0] m02_axi_rdata,
input wire [1 : 0] m02_axi_rresp,
input wire m02_axi_rlast,
input wire [C_M02_AXI_RUSER_WIDTH-1 : 0] m02_axi_ruser,
input wire m02_axi_rvalid,
output wire m02_axi_rready,
input wire m03_axi_init_axi_txn,
output wire m03_axi_txn_done,
output wire m03_axi_error,
input wire m03_axi_aclk,
input wire m03_axi_aresetn,
output wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_awid,
output wire [C_M03_AXI_ADDR_WIDTH-1 : 0] m03_axi_awaddr,
output wire [7 : 0] m03_axi_awlen,
output wire [2 : 0] m03_axi_awsize,
output wire [1 : 0] m03_axi_awburst,
output wire m03_axi_awlock,
output wire [3 : 0] m03_axi_awcache,
output wire [2 : 0] m03_axi_awprot,
output wire [3 : 0] m03_axi_awqos,
output wire [C_M03_AXI_AWUSER_WIDTH-1 : 0] m03_axi_awuser,
output wire m03_axi_awvalid,
input wire m03_axi_awready,
output wire [C_M03_AXI_DATA_WIDTH-1 : 0] m03_axi_wdata,
output wire [C_M03_AXI_DATA_WIDTH/8-1 : 0] m03_axi_wstrb,
output wire m03_axi_wlast,
output wire [C_M03_AXI_WUSER_WIDTH-1 : 0] m03_axi_wuser,
output wire m03_axi_wvalid,
input wire m03_axi_wready,
input wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_bid,
input wire [1 : 0] m03_axi_bresp,
input wire [C_M03_AXI_BUSER_WIDTH-1 : 0] m03_axi_buser,
input wire m03_axi_bvalid,
output wire m03_axi_bready,
output wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_arid,
output wire [C_M03_AXI_ADDR_WIDTH-1 : 0] m03_axi_araddr,
output wire [7 : 0] m03_axi_arlen,
output wire [2 : 0] m03_axi_arsize,
output wire [1 : 0] m03_axi_arburst,
output wire m03_axi_arlock,
output wire [3 : 0] m03_axi_arcache,
output wire [2 : 0] m03_axi_arprot,
output wire [3 : 0] m03_axi_arqos,
output wire [C_M03_AXI_ARUSER_WIDTH-1 : 0] m03_axi_aruser,
output wire m03_axi_arvalid,
input wire m03_axi_arready,
input wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_rid,
input wire [C_M03_AXI_DATA_WIDTH-1 : 0] m03_axi_rdata,
input wire [1 : 0] m03_axi_rresp,
input wire m03_axi_rlast,
input wire [C_M03_AXI_RUSER_WIDTH-1 : 0] m03_axi_ruser,
input wire m03_axi_rvalid,
output wire m03_axi_rready,
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
phantom_dummy_4_v1_0_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M00_AXI_inst (
.INIT_AXI_TXN(m00_axi_init_axi_txn),
.TXN_DONE(m00_axi_txn_done),
.ERROR(m00_axi_error),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
phantom_dummy_4_v1_0_M01_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M01_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M01_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M01_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M01_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M01_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M01_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M01_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M01_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M01_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M01_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M01_AXI_inst (
.INIT_AXI_TXN(m01_axi_init_axi_txn),
.TXN_DONE(m01_axi_txn_done),
.ERROR(m01_axi_error),
.M_AXI_ACLK(m01_axi_aclk),
.M_AXI_ARESETN(m01_axi_aresetn),
.M_AXI_AWID(m01_axi_awid),
.M_AXI_AWADDR(m01_axi_awaddr),
.M_AXI_AWLEN(m01_axi_awlen),
.M_AXI_AWSIZE(m01_axi_awsize),
.M_AXI_AWBURST(m01_axi_awburst),
.M_AXI_AWLOCK(m01_axi_awlock),
.M_AXI_AWCACHE(m01_axi_awcache),
.M_AXI_AWPROT(m01_axi_awprot),
.M_AXI_AWQOS(m01_axi_awqos),
.M_AXI_AWUSER(m01_axi_awuser),
.M_AXI_AWVALID(m01_axi_awvalid),
.M_AXI_AWREADY(m01_axi_awready),
.M_AXI_WDATA(m01_axi_wdata),
.M_AXI_WSTRB(m01_axi_wstrb),
.M_AXI_WLAST(m01_axi_wlast),
.M_AXI_WUSER(m01_axi_wuser),
.M_AXI_WVALID(m01_axi_wvalid),
.M_AXI_WREADY(m01_axi_wready),
.M_AXI_BID(m01_axi_bid),
.M_AXI_BRESP(m01_axi_bresp),
.M_AXI_BUSER(m01_axi_buser),
.M_AXI_BVALID(m01_axi_bvalid),
.M_AXI_BREADY(m01_axi_bready),
.M_AXI_ARID(m01_axi_arid),
.M_AXI_ARADDR(m01_axi_araddr),
.M_AXI_ARLEN(m01_axi_arlen),
.M_AXI_ARSIZE(m01_axi_arsize),
.M_AXI_ARBURST(m01_axi_arburst),
.M_AXI_ARLOCK(m01_axi_arlock),
.M_AXI_ARCACHE(m01_axi_arcache),
.M_AXI_ARPROT(m01_axi_arprot),
.M_AXI_ARQOS(m01_axi_arqos),
.M_AXI_ARUSER(m01_axi_aruser),
.M_AXI_ARVALID(m01_axi_arvalid),
.M_AXI_ARREADY(m01_axi_arready),
.M_AXI_RID(m01_axi_rid),
.M_AXI_RDATA(m01_axi_rdata),
.M_AXI_RRESP(m01_axi_rresp),
.M_AXI_RLAST(m01_axi_rlast),
.M_AXI_RUSER(m01_axi_ruser),
.M_AXI_RVALID(m01_axi_rvalid),
.M_AXI_RREADY(m01_axi_rready)
);
phantom_dummy_4_v1_0_M02_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M02_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M02_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M02_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M02_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M02_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M02_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M02_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M02_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M02_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M02_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M02_AXI_inst (
.INIT_AXI_TXN(m02_axi_init_axi_txn),
.TXN_DONE(m02_axi_txn_done),
.ERROR(m02_axi_error),
.M_AXI_ACLK(m02_axi_aclk),
.M_AXI_ARESETN(m02_axi_aresetn),
.M_AXI_AWID(m02_axi_awid),
.M_AXI_AWADDR(m02_axi_awaddr),
.M_AXI_AWLEN(m02_axi_awlen),
.M_AXI_AWSIZE(m02_axi_awsize),
.M_AXI_AWBURST(m02_axi_awburst),
.M_AXI_AWLOCK(m02_axi_awlock),
.M_AXI_AWCACHE(m02_axi_awcache),
.M_AXI_AWPROT(m02_axi_awprot),
.M_AXI_AWQOS(m02_axi_awqos),
.M_AXI_AWUSER(m02_axi_awuser),
.M_AXI_AWVALID(m02_axi_awvalid),
.M_AXI_AWREADY(m02_axi_awready),
.M_AXI_WDATA(m02_axi_wdata),
.M_AXI_WSTRB(m02_axi_wstrb),
.M_AXI_WLAST(m02_axi_wlast),
.M_AXI_WUSER(m02_axi_wuser),
.M_AXI_WVALID(m02_axi_wvalid),
.M_AXI_WREADY(m02_axi_wready),
.M_AXI_BID(m02_axi_bid),
.M_AXI_BRESP(m02_axi_bresp),
.M_AXI_BUSER(m02_axi_buser),
.M_AXI_BVALID(m02_axi_bvalid),
.M_AXI_BREADY(m02_axi_bready),
.M_AXI_ARID(m02_axi_arid),
.M_AXI_ARADDR(m02_axi_araddr),
.M_AXI_ARLEN(m02_axi_arlen),
.M_AXI_ARSIZE(m02_axi_arsize),
.M_AXI_ARBURST(m02_axi_arburst),
.M_AXI_ARLOCK(m02_axi_arlock),
.M_AXI_ARCACHE(m02_axi_arcache),
.M_AXI_ARPROT(m02_axi_arprot),
.M_AXI_ARQOS(m02_axi_arqos),
.M_AXI_ARUSER(m02_axi_aruser),
.M_AXI_ARVALID(m02_axi_arvalid),
.M_AXI_ARREADY(m02_axi_arready),
.M_AXI_RID(m02_axi_rid),
.M_AXI_RDATA(m02_axi_rdata),
.M_AXI_RRESP(m02_axi_rresp),
.M_AXI_RLAST(m02_axi_rlast),
.M_AXI_RUSER(m02_axi_ruser),
.M_AXI_RVALID(m02_axi_rvalid),
.M_AXI_RREADY(m02_axi_rready)
);
phantom_dummy_4_v1_0_M03_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M03_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M03_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M03_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M03_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M03_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M03_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M03_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M03_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M03_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M03_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M03_AXI_inst (
.INIT_AXI_TXN(m03_axi_init_axi_txn),
.TXN_DONE(m03_axi_txn_done),
.ERROR(m03_axi_error),
.M_AXI_ACLK(m03_axi_aclk),
.M_AXI_ARESETN(m03_axi_aresetn),
.M_AXI_AWID(m03_axi_awid),
.M_AXI_AWADDR(m03_axi_awaddr),
.M_AXI_AWLEN(m03_axi_awlen),
.M_AXI_AWSIZE(m03_axi_awsize),
.M_AXI_AWBURST(m03_axi_awburst),
.M_AXI_AWLOCK(m03_axi_awlock),
.M_AXI_AWCACHE(m03_axi_awcache),
.M_AXI_AWPROT(m03_axi_awprot),
.M_AXI_AWQOS(m03_axi_awqos),
.M_AXI_AWUSER(m03_axi_awuser),
.M_AXI_AWVALID(m03_axi_awvalid),
.M_AXI_AWREADY(m03_axi_awready),
.M_AXI_WDATA(m03_axi_wdata),
.M_AXI_WSTRB(m03_axi_wstrb),
.M_AXI_WLAST(m03_axi_wlast),
.M_AXI_WUSER(m03_axi_wuser),
.M_AXI_WVALID(m03_axi_wvalid),
.M_AXI_WREADY(m03_axi_wready),
.M_AXI_BID(m03_axi_bid),
.M_AXI_BRESP(m03_axi_bresp),
.M_AXI_BUSER(m03_axi_buser),
.M_AXI_BVALID(m03_axi_bvalid),
.M_AXI_BREADY(m03_axi_bready),
.M_AXI_ARID(m03_axi_arid),
.M_AXI_ARADDR(m03_axi_araddr),
.M_AXI_ARLEN(m03_axi_arlen),
.M_AXI_ARSIZE(m03_axi_arsize),
.M_AXI_ARBURST(m03_axi_arburst),
.M_AXI_ARLOCK(m03_axi_arlock),
.M_AXI_ARCACHE(m03_axi_arcache),
.M_AXI_ARPROT(m03_axi_arprot),
.M_AXI_ARQOS(m03_axi_arqos),
.M_AXI_ARUSER(m03_axi_aruser),
.M_AXI_ARVALID(m03_axi_arvalid),
.M_AXI_ARREADY(m03_axi_arready),
.M_AXI_RID(m03_axi_rid),
.M_AXI_RDATA(m03_axi_rdata),
.M_AXI_RRESP(m03_axi_rresp),
.M_AXI_RLAST(m03_axi_rlast),
.M_AXI_RUSER(m03_axi_ruser),
.M_AXI_RVALID(m03_axi_rvalid),
.M_AXI_RREADY(m03_axi_rready)
);
phantom_dummy_4_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) phantom_dummy_4_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
endmodule | module phantom_dummy_4_v1_0 #
(
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0,
parameter C_M01_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M01_AXI_BURST_LEN = 16,
parameter integer C_M01_AXI_ID_WIDTH = 1,
parameter integer C_M01_AXI_ADDR_WIDTH = 32,
parameter integer C_M01_AXI_DATA_WIDTH = 32,
parameter integer C_M01_AXI_AWUSER_WIDTH = 0,
parameter integer C_M01_AXI_ARUSER_WIDTH = 0,
parameter integer C_M01_AXI_WUSER_WIDTH = 0,
parameter integer C_M01_AXI_RUSER_WIDTH = 0,
parameter integer C_M01_AXI_BUSER_WIDTH = 0,
parameter C_M02_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M02_AXI_BURST_LEN = 16,
parameter integer C_M02_AXI_ID_WIDTH = 1,
parameter integer C_M02_AXI_ADDR_WIDTH = 32,
parameter integer C_M02_AXI_DATA_WIDTH = 32,
parameter integer C_M02_AXI_AWUSER_WIDTH = 0,
parameter integer C_M02_AXI_ARUSER_WIDTH = 0,
parameter integer C_M02_AXI_WUSER_WIDTH = 0,
parameter integer C_M02_AXI_RUSER_WIDTH = 0,
parameter integer C_M02_AXI_BUSER_WIDTH = 0,
parameter C_M03_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M03_AXI_BURST_LEN = 16,
parameter integer C_M03_AXI_ID_WIDTH = 1,
parameter integer C_M03_AXI_ADDR_WIDTH = 32,
parameter integer C_M03_AXI_DATA_WIDTH = 32,
parameter integer C_M03_AXI_AWUSER_WIDTH = 0,
parameter integer C_M03_AXI_ARUSER_WIDTH = 0,
parameter integer C_M03_AXI_WUSER_WIDTH = 0,
parameter integer C_M03_AXI_RUSER_WIDTH = 0,
parameter integer C_M03_AXI_BUSER_WIDTH = 0,
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
input wire m00_axi_init_axi_txn,
output wire m00_axi_txn_done,
output wire m00_axi_error,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready,
input wire m01_axi_init_axi_txn,
output wire m01_axi_txn_done,
output wire m01_axi_error,
input wire m01_axi_aclk,
input wire m01_axi_aresetn,
output wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_awid,
output wire [C_M01_AXI_ADDR_WIDTH-1 : 0] m01_axi_awaddr,
output wire [7 : 0] m01_axi_awlen,
output wire [2 : 0] m01_axi_awsize,
output wire [1 : 0] m01_axi_awburst,
output wire m01_axi_awlock,
output wire [3 : 0] m01_axi_awcache,
output wire [2 : 0] m01_axi_awprot,
output wire [3 : 0] m01_axi_awqos,
output wire [C_M01_AXI_AWUSER_WIDTH-1 : 0] m01_axi_awuser,
output wire m01_axi_awvalid,
input wire m01_axi_awready,
output wire [C_M01_AXI_DATA_WIDTH-1 : 0] m01_axi_wdata,
output wire [C_M01_AXI_DATA_WIDTH/8-1 : 0] m01_axi_wstrb,
output wire m01_axi_wlast,
output wire [C_M01_AXI_WUSER_WIDTH-1 : 0] m01_axi_wuser,
output wire m01_axi_wvalid,
input wire m01_axi_wready,
input wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_bid,
input wire [1 : 0] m01_axi_bresp,
input wire [C_M01_AXI_BUSER_WIDTH-1 : 0] m01_axi_buser,
input wire m01_axi_bvalid,
output wire m01_axi_bready,
output wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_arid,
output wire [C_M01_AXI_ADDR_WIDTH-1 : 0] m01_axi_araddr,
output wire [7 : 0] m01_axi_arlen,
output wire [2 : 0] m01_axi_arsize,
output wire [1 : 0] m01_axi_arburst,
output wire m01_axi_arlock,
output wire [3 : 0] m01_axi_arcache,
output wire [2 : 0] m01_axi_arprot,
output wire [3 : 0] m01_axi_arqos,
output wire [C_M01_AXI_ARUSER_WIDTH-1 : 0] m01_axi_aruser,
output wire m01_axi_arvalid,
input wire m01_axi_arready,
input wire [C_M01_AXI_ID_WIDTH-1 : 0] m01_axi_rid,
input wire [C_M01_AXI_DATA_WIDTH-1 : 0] m01_axi_rdata,
input wire [1 : 0] m01_axi_rresp,
input wire m01_axi_rlast,
input wire [C_M01_AXI_RUSER_WIDTH-1 : 0] m01_axi_ruser,
input wire m01_axi_rvalid,
output wire m01_axi_rready,
input wire m02_axi_init_axi_txn,
output wire m02_axi_txn_done,
output wire m02_axi_error,
input wire m02_axi_aclk,
input wire m02_axi_aresetn,
output wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_awid,
output wire [C_M02_AXI_ADDR_WIDTH-1 : 0] m02_axi_awaddr,
output wire [7 : 0] m02_axi_awlen,
output wire [2 : 0] m02_axi_awsize,
output wire [1 : 0] m02_axi_awburst,
output wire m02_axi_awlock,
output wire [3 : 0] m02_axi_awcache,
output wire [2 : 0] m02_axi_awprot,
output wire [3 : 0] m02_axi_awqos,
output wire [C_M02_AXI_AWUSER_WIDTH-1 : 0] m02_axi_awuser,
output wire m02_axi_awvalid,
input wire m02_axi_awready,
output wire [C_M02_AXI_DATA_WIDTH-1 : 0] m02_axi_wdata,
output wire [C_M02_AXI_DATA_WIDTH/8-1 : 0] m02_axi_wstrb,
output wire m02_axi_wlast,
output wire [C_M02_AXI_WUSER_WIDTH-1 : 0] m02_axi_wuser,
output wire m02_axi_wvalid,
input wire m02_axi_wready,
input wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_bid,
input wire [1 : 0] m02_axi_bresp,
input wire [C_M02_AXI_BUSER_WIDTH-1 : 0] m02_axi_buser,
input wire m02_axi_bvalid,
output wire m02_axi_bready,
output wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_arid,
output wire [C_M02_AXI_ADDR_WIDTH-1 : 0] m02_axi_araddr,
output wire [7 : 0] m02_axi_arlen,
output wire [2 : 0] m02_axi_arsize,
output wire [1 : 0] m02_axi_arburst,
output wire m02_axi_arlock,
output wire [3 : 0] m02_axi_arcache,
output wire [2 : 0] m02_axi_arprot,
output wire [3 : 0] m02_axi_arqos,
output wire [C_M02_AXI_ARUSER_WIDTH-1 : 0] m02_axi_aruser,
output wire m02_axi_arvalid,
input wire m02_axi_arready,
input wire [C_M02_AXI_ID_WIDTH-1 : 0] m02_axi_rid,
input wire [C_M02_AXI_DATA_WIDTH-1 : 0] m02_axi_rdata,
input wire [1 : 0] m02_axi_rresp,
input wire m02_axi_rlast,
input wire [C_M02_AXI_RUSER_WIDTH-1 : 0] m02_axi_ruser,
input wire m02_axi_rvalid,
output wire m02_axi_rready,
input wire m03_axi_init_axi_txn,
output wire m03_axi_txn_done,
output wire m03_axi_error,
input wire m03_axi_aclk,
input wire m03_axi_aresetn,
output wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_awid,
output wire [C_M03_AXI_ADDR_WIDTH-1 : 0] m03_axi_awaddr,
output wire [7 : 0] m03_axi_awlen,
output wire [2 : 0] m03_axi_awsize,
output wire [1 : 0] m03_axi_awburst,
output wire m03_axi_awlock,
output wire [3 : 0] m03_axi_awcache,
output wire [2 : 0] m03_axi_awprot,
output wire [3 : 0] m03_axi_awqos,
output wire [C_M03_AXI_AWUSER_WIDTH-1 : 0] m03_axi_awuser,
output wire m03_axi_awvalid,
input wire m03_axi_awready,
output wire [C_M03_AXI_DATA_WIDTH-1 : 0] m03_axi_wdata,
output wire [C_M03_AXI_DATA_WIDTH/8-1 : 0] m03_axi_wstrb,
output wire m03_axi_wlast,
output wire [C_M03_AXI_WUSER_WIDTH-1 : 0] m03_axi_wuser,
output wire m03_axi_wvalid,
input wire m03_axi_wready,
input wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_bid,
input wire [1 : 0] m03_axi_bresp,
input wire [C_M03_AXI_BUSER_WIDTH-1 : 0] m03_axi_buser,
input wire m03_axi_bvalid,
output wire m03_axi_bready,
output wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_arid,
output wire [C_M03_AXI_ADDR_WIDTH-1 : 0] m03_axi_araddr,
output wire [7 : 0] m03_axi_arlen,
output wire [2 : 0] m03_axi_arsize,
output wire [1 : 0] m03_axi_arburst,
output wire m03_axi_arlock,
output wire [3 : 0] m03_axi_arcache,
output wire [2 : 0] m03_axi_arprot,
output wire [3 : 0] m03_axi_arqos,
output wire [C_M03_AXI_ARUSER_WIDTH-1 : 0] m03_axi_aruser,
output wire m03_axi_arvalid,
input wire m03_axi_arready,
input wire [C_M03_AXI_ID_WIDTH-1 : 0] m03_axi_rid,
input wire [C_M03_AXI_DATA_WIDTH-1 : 0] m03_axi_rdata,
input wire [1 : 0] m03_axi_rresp,
input wire m03_axi_rlast,
input wire [C_M03_AXI_RUSER_WIDTH-1 : 0] m03_axi_ruser,
input wire m03_axi_rvalid,
output wire m03_axi_rready,
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
); |
phantom_dummy_4_v1_0_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M00_AXI_inst (
.INIT_AXI_TXN(m00_axi_init_axi_txn),
.TXN_DONE(m00_axi_txn_done),
.ERROR(m00_axi_error),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
phantom_dummy_4_v1_0_M01_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M01_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M01_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M01_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M01_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M01_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M01_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M01_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M01_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M01_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M01_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M01_AXI_inst (
.INIT_AXI_TXN(m01_axi_init_axi_txn),
.TXN_DONE(m01_axi_txn_done),
.ERROR(m01_axi_error),
.M_AXI_ACLK(m01_axi_aclk),
.M_AXI_ARESETN(m01_axi_aresetn),
.M_AXI_AWID(m01_axi_awid),
.M_AXI_AWADDR(m01_axi_awaddr),
.M_AXI_AWLEN(m01_axi_awlen),
.M_AXI_AWSIZE(m01_axi_awsize),
.M_AXI_AWBURST(m01_axi_awburst),
.M_AXI_AWLOCK(m01_axi_awlock),
.M_AXI_AWCACHE(m01_axi_awcache),
.M_AXI_AWPROT(m01_axi_awprot),
.M_AXI_AWQOS(m01_axi_awqos),
.M_AXI_AWUSER(m01_axi_awuser),
.M_AXI_AWVALID(m01_axi_awvalid),
.M_AXI_AWREADY(m01_axi_awready),
.M_AXI_WDATA(m01_axi_wdata),
.M_AXI_WSTRB(m01_axi_wstrb),
.M_AXI_WLAST(m01_axi_wlast),
.M_AXI_WUSER(m01_axi_wuser),
.M_AXI_WVALID(m01_axi_wvalid),
.M_AXI_WREADY(m01_axi_wready),
.M_AXI_BID(m01_axi_bid),
.M_AXI_BRESP(m01_axi_bresp),
.M_AXI_BUSER(m01_axi_buser),
.M_AXI_BVALID(m01_axi_bvalid),
.M_AXI_BREADY(m01_axi_bready),
.M_AXI_ARID(m01_axi_arid),
.M_AXI_ARADDR(m01_axi_araddr),
.M_AXI_ARLEN(m01_axi_arlen),
.M_AXI_ARSIZE(m01_axi_arsize),
.M_AXI_ARBURST(m01_axi_arburst),
.M_AXI_ARLOCK(m01_axi_arlock),
.M_AXI_ARCACHE(m01_axi_arcache),
.M_AXI_ARPROT(m01_axi_arprot),
.M_AXI_ARQOS(m01_axi_arqos),
.M_AXI_ARUSER(m01_axi_aruser),
.M_AXI_ARVALID(m01_axi_arvalid),
.M_AXI_ARREADY(m01_axi_arready),
.M_AXI_RID(m01_axi_rid),
.M_AXI_RDATA(m01_axi_rdata),
.M_AXI_RRESP(m01_axi_rresp),
.M_AXI_RLAST(m01_axi_rlast),
.M_AXI_RUSER(m01_axi_ruser),
.M_AXI_RVALID(m01_axi_rvalid),
.M_AXI_RREADY(m01_axi_rready)
);
phantom_dummy_4_v1_0_M02_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M02_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M02_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M02_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M02_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M02_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M02_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M02_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M02_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M02_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M02_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M02_AXI_inst (
.INIT_AXI_TXN(m02_axi_init_axi_txn),
.TXN_DONE(m02_axi_txn_done),
.ERROR(m02_axi_error),
.M_AXI_ACLK(m02_axi_aclk),
.M_AXI_ARESETN(m02_axi_aresetn),
.M_AXI_AWID(m02_axi_awid),
.M_AXI_AWADDR(m02_axi_awaddr),
.M_AXI_AWLEN(m02_axi_awlen),
.M_AXI_AWSIZE(m02_axi_awsize),
.M_AXI_AWBURST(m02_axi_awburst),
.M_AXI_AWLOCK(m02_axi_awlock),
.M_AXI_AWCACHE(m02_axi_awcache),
.M_AXI_AWPROT(m02_axi_awprot),
.M_AXI_AWQOS(m02_axi_awqos),
.M_AXI_AWUSER(m02_axi_awuser),
.M_AXI_AWVALID(m02_axi_awvalid),
.M_AXI_AWREADY(m02_axi_awready),
.M_AXI_WDATA(m02_axi_wdata),
.M_AXI_WSTRB(m02_axi_wstrb),
.M_AXI_WLAST(m02_axi_wlast),
.M_AXI_WUSER(m02_axi_wuser),
.M_AXI_WVALID(m02_axi_wvalid),
.M_AXI_WREADY(m02_axi_wready),
.M_AXI_BID(m02_axi_bid),
.M_AXI_BRESP(m02_axi_bresp),
.M_AXI_BUSER(m02_axi_buser),
.M_AXI_BVALID(m02_axi_bvalid),
.M_AXI_BREADY(m02_axi_bready),
.M_AXI_ARID(m02_axi_arid),
.M_AXI_ARADDR(m02_axi_araddr),
.M_AXI_ARLEN(m02_axi_arlen),
.M_AXI_ARSIZE(m02_axi_arsize),
.M_AXI_ARBURST(m02_axi_arburst),
.M_AXI_ARLOCK(m02_axi_arlock),
.M_AXI_ARCACHE(m02_axi_arcache),
.M_AXI_ARPROT(m02_axi_arprot),
.M_AXI_ARQOS(m02_axi_arqos),
.M_AXI_ARUSER(m02_axi_aruser),
.M_AXI_ARVALID(m02_axi_arvalid),
.M_AXI_ARREADY(m02_axi_arready),
.M_AXI_RID(m02_axi_rid),
.M_AXI_RDATA(m02_axi_rdata),
.M_AXI_RRESP(m02_axi_rresp),
.M_AXI_RLAST(m02_axi_rlast),
.M_AXI_RUSER(m02_axi_ruser),
.M_AXI_RVALID(m02_axi_rvalid),
.M_AXI_RREADY(m02_axi_rready)
);
phantom_dummy_4_v1_0_M03_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M03_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M03_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M03_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M03_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M03_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M03_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M03_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M03_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M03_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M03_AXI_BUSER_WIDTH)
) phantom_dummy_4_v1_0_M03_AXI_inst (
.INIT_AXI_TXN(m03_axi_init_axi_txn),
.TXN_DONE(m03_axi_txn_done),
.ERROR(m03_axi_error),
.M_AXI_ACLK(m03_axi_aclk),
.M_AXI_ARESETN(m03_axi_aresetn),
.M_AXI_AWID(m03_axi_awid),
.M_AXI_AWADDR(m03_axi_awaddr),
.M_AXI_AWLEN(m03_axi_awlen),
.M_AXI_AWSIZE(m03_axi_awsize),
.M_AXI_AWBURST(m03_axi_awburst),
.M_AXI_AWLOCK(m03_axi_awlock),
.M_AXI_AWCACHE(m03_axi_awcache),
.M_AXI_AWPROT(m03_axi_awprot),
.M_AXI_AWQOS(m03_axi_awqos),
.M_AXI_AWUSER(m03_axi_awuser),
.M_AXI_AWVALID(m03_axi_awvalid),
.M_AXI_AWREADY(m03_axi_awready),
.M_AXI_WDATA(m03_axi_wdata),
.M_AXI_WSTRB(m03_axi_wstrb),
.M_AXI_WLAST(m03_axi_wlast),
.M_AXI_WUSER(m03_axi_wuser),
.M_AXI_WVALID(m03_axi_wvalid),
.M_AXI_WREADY(m03_axi_wready),
.M_AXI_BID(m03_axi_bid),
.M_AXI_BRESP(m03_axi_bresp),
.M_AXI_BUSER(m03_axi_buser),
.M_AXI_BVALID(m03_axi_bvalid),
.M_AXI_BREADY(m03_axi_bready),
.M_AXI_ARID(m03_axi_arid),
.M_AXI_ARADDR(m03_axi_araddr),
.M_AXI_ARLEN(m03_axi_arlen),
.M_AXI_ARSIZE(m03_axi_arsize),
.M_AXI_ARBURST(m03_axi_arburst),
.M_AXI_ARLOCK(m03_axi_arlock),
.M_AXI_ARCACHE(m03_axi_arcache),
.M_AXI_ARPROT(m03_axi_arprot),
.M_AXI_ARQOS(m03_axi_arqos),
.M_AXI_ARUSER(m03_axi_aruser),
.M_AXI_ARVALID(m03_axi_arvalid),
.M_AXI_ARREADY(m03_axi_arready),
.M_AXI_RID(m03_axi_rid),
.M_AXI_RDATA(m03_axi_rdata),
.M_AXI_RRESP(m03_axi_rresp),
.M_AXI_RLAST(m03_axi_rlast),
.M_AXI_RUSER(m03_axi_ruser),
.M_AXI_RVALID(m03_axi_rvalid),
.M_AXI_RREADY(m03_axi_rready)
);
phantom_dummy_4_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) phantom_dummy_4_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
endmodule | 1 |
140,779 | data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v | 91,688,960 | recon_io.v | v | 294 | 138 | [] | [] | [] | [(36, 291)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:123: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance recon_io\n 3 : read_mux_reg <= 32\'h0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:124: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance recon_io\n 4 : read_mux_reg <= 32\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:131: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'pwm_period\' generates 9 bits.\n : ... In instance recon_io\n 12: read_mux_reg <= pwm_period;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:135: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'read_mux_reg\' generates 16 bits.\n : ... In instance recon_io\n assign readdata = {32\'b0 | read_mux_reg};\n ^\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:160: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'writedata\' generates 32 bits.\n : ... In instance recon_io\n pin_mode <= writedata;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:163: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'writedata\' generates 32 bits.\n : ... In instance recon_io\n pwm_ena <= writedata;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:166: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'writedata\' generates 32 bits.\n : ... In instance recon_io\n irq_redge <= writedata;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:169: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'writedata\' generates 32 bits.\n : ... In instance recon_io\n irq_fedge <= writedata;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:172: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'writedata\' generates 32 bits.\n : ... In instance recon_io\n pwm_period <= writedata;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:251: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'writedata\' generates 32 bits.\n : ... In instance recon_io\n pwm_values[I] <= writedata;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:249: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'address\' generates 6 bits.\n : ... In instance recon_io\n if (chipselect && write && address==(I+16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:267: Operator EQ expects 9 bits on the LHS, but LHS\'s VARREF \'pwm_cntr\' generates 8 bits.\n : ... In instance recon_io\n if (pwm_cntr == pwm_period) pwm_cntr <= 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/io/recon_io.v:274: Operator LT expects 9 bits on the LHS, but LHS\'s VARREF \'pwm_cntr\' generates 8 bits.\n : ... In instance recon_io\n if (pwm_cntr<pwm_values[I]) \n ^\n%Error: Exiting due to 13 warning(s)\n' | 309,693 | module | module recon_io (
address,
chipselect,
clk,
reset_n,
write,
read,
writedata,
readdata,
irq,
io_out ,
io_in ,
io_oe ,
io_opdrn
)
;
parameter PORT_WIDTH = 16;
parameter PWM_CNTR_WIDTH = 8;
output [ 31: 0] readdata;
input [ 5: 0] address;
input chipselect;
input clk;
input reset_n;
input write;
input read;
input [ 31: 0] writedata;
output [PORT_WIDTH-1:0] io_out;
output [PORT_WIDTH-1:0] io_oe;
output [PORT_WIDTH-1:0] io_opdrn;
input [PORT_WIDTH-1:0] io_in;
output irq;
wire [ 31: 0] readdata;
wire clk_en;
reg [ PORT_WIDTH-1: 0] data_out;
wire [ PORT_WIDTH-1: 0] out_port;
reg [ PORT_WIDTH-1: 0] read_mux_reg;
reg [ PORT_WIDTH-1: 0] pin_mode;
reg [ PORT_WIDTH-1: 0] pin_opdrn;
reg [ PORT_WIDTH-1: 0] data_in;
reg [ PORT_WIDTH-1: 0] data_in_r1;
reg [ PORT_WIDTH-1: 0] data_in_r2;
reg [ PORT_WIDTH-1: 0] data_in_event;
reg [ PORT_WIDTH-1: 0] pwm_ena;
reg [ PORT_WIDTH-1: 0] pwm_out;
wire [ PORT_WIDTH-1: 0] irq_ena;
reg [ PORT_WIDTH-1: 0] irq_redge;
reg [ PORT_WIDTH-1: 0] irq_fedge;
reg [ PORT_WIDTH-1: 0] irq_status;
reg [ PWM_CNTR_WIDTH : 0] pwm_values[PORT_WIDTH-1:0];
reg [ PWM_CNTR_WIDTH-1: 0] pwm_cntr;
reg [ PWM_CNTR_WIDTH : 0] pwm_period;
assign clk_en = 1;
initial
begin
pwm_ena <= 0;
end
always@(posedge clk)
begin
if (chipselect && read)
case(address)
`DIR_OFFSET : read_mux_reg <= pin_mode;
`OUT_OFFSET : read_mux_reg <= data_out;
`IN_OFFSET : read_mux_reg <= data_in;
`OUT_SET_OFFSET : read_mux_reg <= 32'h0;
`OUT_CLR_OFFSET : read_mux_reg <= 32'h0;
`OPENDRN_OFFSET : read_mux_reg <= pin_opdrn;
`IRQ_ENA_OFFSET : read_mux_reg <= irq_ena;
`PWM_ENA_OFFSET : read_mux_reg <= pwm_ena;
`IRQ_STATUS_OFFSET: read_mux_reg <= irq_status;
`IRQ_REDGE_OFFSET : read_mux_reg <= irq_redge;
`IRQ_FEDGE_OFFSET : read_mux_reg <= irq_fedge;
`PWM_PERIOD_OFFSET: read_mux_reg <= pwm_period;
default : read_mux_reg <= data_in;
endcase
end
assign readdata = {32'b0 | read_mux_reg};
integer I;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0) begin
pin_mode <= 0;
pwm_ena <= 0;
irq_redge<= 0;
irq_fedge<= 0;
pwm_period[PWM_CNTR_WIDTH] <= 1'b1;
pwm_period[PWM_CNTR_WIDTH-1:0] <= 0;
end
else begin
if (chipselect && write && (address == `DIR_OFFSET)) begin
pin_mode <= writedata;
end
if (chipselect && write && (address == `PWM_ENA_OFFSET)) begin
pwm_ena <= writedata;
end
if (chipselect && write && (address == `IRQ_REDGE_OFFSET)) begin
irq_redge <= writedata;
end
if (chipselect && write && (address == `IRQ_FEDGE_OFFSET)) begin
irq_fedge <= writedata;
end
if (chipselect && write && (address == `PWM_PERIOD_OFFSET)) begin
pwm_period <= writedata;
end
end
end
assign irq_ena = irq_redge | irq_fedge;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
for(I=0;I<PORT_WIDTH;I=I+1)
begin
if (chipselect && write && (address == `OUT_OFFSET))
data_out[I] <= writedata[I];
else if (chipselect && write && (address == `OUT_SET_OFFSET))
begin
if (writedata[I]==1'b1) data_out[I] <= 1'b1;
end
else if (chipselect && write && (address == `OUT_CLR_OFFSET))
begin
if (writedata[I]==1'b1) data_out[I] <= 1'b0;
end
end
end
always@(posedge clk)
begin
data_in <= io_in;
data_in_r1 <= data_in;
data_in_r2 <= data_in_r1;
data_in_event <= (irq_redge & (data_in_r1 & ~data_in_r2))|
(irq_fedge & (~data_in_r1 & data_in_r2));
for(I=0;I<PORT_WIDTH;I=I+1)
if(data_in_event[I]==1'b1 && irq_ena[I]==1'b1)
irq_status[I] <= 1'b1;
else if (chipselect && write && address == `IRQ_STATUS_OFFSET && writedata[I]==1'b1)
irq_status[I] <= 1'b0;
end
assign irq = | irq_status;
always@(posedge clk)
begin
for(I=0;I<PORT_WIDTH;I=I+1)
if (chipselect && write && address==(I+16))
begin
pwm_values[I] <= writedata;
end
end
always@(posedge clk)
begin
pwm_cntr <= pwm_cntr + 1;
if (pwm_cntr == pwm_period) pwm_cntr <= 0;
for(I=0;I<PORT_WIDTH;I=I+1)
if (pwm_cntr<pwm_values[I])
pwm_out[I] <= pwm_ena[I];
else
pwm_out[I] <= 1'b0;
end
genvar IO;
generate
for(IO=0;IO<PORT_WIDTH;IO=IO+1)
begin: assignpins
assign io_oe[IO] = pin_mode[IO]|pwm_ena[IO];
assign io_out[IO] = pwm_ena[IO]?pwm_out[IO]:data_out[IO];
assign io_opdrn[IO]= pin_opdrn[IO];
end
endgenerate
endmodule | module recon_io (
address,
chipselect,
clk,
reset_n,
write,
read,
writedata,
readdata,
irq,
io_out ,
io_in ,
io_oe ,
io_opdrn
)
; |
parameter PORT_WIDTH = 16;
parameter PWM_CNTR_WIDTH = 8;
output [ 31: 0] readdata;
input [ 5: 0] address;
input chipselect;
input clk;
input reset_n;
input write;
input read;
input [ 31: 0] writedata;
output [PORT_WIDTH-1:0] io_out;
output [PORT_WIDTH-1:0] io_oe;
output [PORT_WIDTH-1:0] io_opdrn;
input [PORT_WIDTH-1:0] io_in;
output irq;
wire [ 31: 0] readdata;
wire clk_en;
reg [ PORT_WIDTH-1: 0] data_out;
wire [ PORT_WIDTH-1: 0] out_port;
reg [ PORT_WIDTH-1: 0] read_mux_reg;
reg [ PORT_WIDTH-1: 0] pin_mode;
reg [ PORT_WIDTH-1: 0] pin_opdrn;
reg [ PORT_WIDTH-1: 0] data_in;
reg [ PORT_WIDTH-1: 0] data_in_r1;
reg [ PORT_WIDTH-1: 0] data_in_r2;
reg [ PORT_WIDTH-1: 0] data_in_event;
reg [ PORT_WIDTH-1: 0] pwm_ena;
reg [ PORT_WIDTH-1: 0] pwm_out;
wire [ PORT_WIDTH-1: 0] irq_ena;
reg [ PORT_WIDTH-1: 0] irq_redge;
reg [ PORT_WIDTH-1: 0] irq_fedge;
reg [ PORT_WIDTH-1: 0] irq_status;
reg [ PWM_CNTR_WIDTH : 0] pwm_values[PORT_WIDTH-1:0];
reg [ PWM_CNTR_WIDTH-1: 0] pwm_cntr;
reg [ PWM_CNTR_WIDTH : 0] pwm_period;
assign clk_en = 1;
initial
begin
pwm_ena <= 0;
end
always@(posedge clk)
begin
if (chipselect && read)
case(address)
`DIR_OFFSET : read_mux_reg <= pin_mode;
`OUT_OFFSET : read_mux_reg <= data_out;
`IN_OFFSET : read_mux_reg <= data_in;
`OUT_SET_OFFSET : read_mux_reg <= 32'h0;
`OUT_CLR_OFFSET : read_mux_reg <= 32'h0;
`OPENDRN_OFFSET : read_mux_reg <= pin_opdrn;
`IRQ_ENA_OFFSET : read_mux_reg <= irq_ena;
`PWM_ENA_OFFSET : read_mux_reg <= pwm_ena;
`IRQ_STATUS_OFFSET: read_mux_reg <= irq_status;
`IRQ_REDGE_OFFSET : read_mux_reg <= irq_redge;
`IRQ_FEDGE_OFFSET : read_mux_reg <= irq_fedge;
`PWM_PERIOD_OFFSET: read_mux_reg <= pwm_period;
default : read_mux_reg <= data_in;
endcase
end
assign readdata = {32'b0 | read_mux_reg};
integer I;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0) begin
pin_mode <= 0;
pwm_ena <= 0;
irq_redge<= 0;
irq_fedge<= 0;
pwm_period[PWM_CNTR_WIDTH] <= 1'b1;
pwm_period[PWM_CNTR_WIDTH-1:0] <= 0;
end
else begin
if (chipselect && write && (address == `DIR_OFFSET)) begin
pin_mode <= writedata;
end
if (chipselect && write && (address == `PWM_ENA_OFFSET)) begin
pwm_ena <= writedata;
end
if (chipselect && write && (address == `IRQ_REDGE_OFFSET)) begin
irq_redge <= writedata;
end
if (chipselect && write && (address == `IRQ_FEDGE_OFFSET)) begin
irq_fedge <= writedata;
end
if (chipselect && write && (address == `PWM_PERIOD_OFFSET)) begin
pwm_period <= writedata;
end
end
end
assign irq_ena = irq_redge | irq_fedge;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
for(I=0;I<PORT_WIDTH;I=I+1)
begin
if (chipselect && write && (address == `OUT_OFFSET))
data_out[I] <= writedata[I];
else if (chipselect && write && (address == `OUT_SET_OFFSET))
begin
if (writedata[I]==1'b1) data_out[I] <= 1'b1;
end
else if (chipselect && write && (address == `OUT_CLR_OFFSET))
begin
if (writedata[I]==1'b1) data_out[I] <= 1'b0;
end
end
end
always@(posedge clk)
begin
data_in <= io_in;
data_in_r1 <= data_in;
data_in_r2 <= data_in_r1;
data_in_event <= (irq_redge & (data_in_r1 & ~data_in_r2))|
(irq_fedge & (~data_in_r1 & data_in_r2));
for(I=0;I<PORT_WIDTH;I=I+1)
if(data_in_event[I]==1'b1 && irq_ena[I]==1'b1)
irq_status[I] <= 1'b1;
else if (chipselect && write && address == `IRQ_STATUS_OFFSET && writedata[I]==1'b1)
irq_status[I] <= 1'b0;
end
assign irq = | irq_status;
always@(posedge clk)
begin
for(I=0;I<PORT_WIDTH;I=I+1)
if (chipselect && write && address==(I+16))
begin
pwm_values[I] <= writedata;
end
end
always@(posedge clk)
begin
pwm_cntr <= pwm_cntr + 1;
if (pwm_cntr == pwm_period) pwm_cntr <= 0;
for(I=0;I<PORT_WIDTH;I=I+1)
if (pwm_cntr<pwm_values[I])
pwm_out[I] <= pwm_ena[I];
else
pwm_out[I] <= 1'b0;
end
genvar IO;
generate
for(IO=0;IO<PORT_WIDTH;IO=IO+1)
begin: assignpins
assign io_oe[IO] = pin_mode[IO]|pwm_ena[IO];
assign io_out[IO] = pwm_ena[IO]?pwm_out[IO]:data_out[IO];
assign io_opdrn[IO]= pin_opdrn[IO];
end
endgenerate
endmodule | 21 |
140,780 | data/full_repos/permissive/91688960/hw/cmn/timer/recon_timer.v | 91,688,960 | recon_timer.v | v | 165 | 91 | [] | [] | [] | [(24, 162)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/timer/recon_timer.v:106: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'timer\' generates 10 bits.\n : ... In instance recon_timer\n if (timer == MICROSEC) begin \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/timer/recon_timer.v:126: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'writedata\' generates 32 bits.\n : ... In instance recon_timer\n ctrl_reg <= writedata;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 309,694 | module | module recon_timer (
address,
chipselect,
clk,
reset_n,
write,
read,
writedata,
readdata,
irq,
microsec_tick,
millisec_tick,
second_tick
);
parameter CLK_FREQ = 50000000;
parameter MILLISEC = CLK_FREQ/1000-1;
parameter MICROSEC = CLK_FREQ/1000000-1;
output [ 31: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write;
input read;
input [ 31: 0] writedata;
output irq;
output reg microsec_tick;
output reg millisec_tick;
output reg second_tick;
wire [ 31: 0] readdata;
reg [ 31: 0] read_mux_reg;
reg [ 9: 0] microsec;
reg [ 31: 0] millisec;
reg [ 31: 0] next_millisec;
reg [ 31: 0] second;
reg [ 3: 0] ctrl_reg;
reg [ 31: 0] irq_timer;
reg [ 31: 0] irq_time;
reg [ 9: 0] timer;
reg irq_active;
reg irq_active_d;
reg irq_pulse;
always@(posedge clk)
begin
if (chipselect && read)
case(address)
`MILLISEC_OFFSET : read_mux_reg <= millisec;
`SECOND_OFFSET : read_mux_reg <= second;
`IRQ_TIME_OFFSET : read_mux_reg <= irq_time;
`CTRL_OFFSET : read_mux_reg <= {28'h0, ctrl_reg};
`IRQ_STATUS_OFFSET : read_mux_reg <= {31'h0, irq_pulse};
default : read_mux_reg <= 32'h0;
endcase
end
assign readdata = read_mux_reg;
always@(posedge clk or negedge reset_n)
if (~reset_n) begin
millisec <= 0;
second <= 0;
next_millisec <= 999;
microsec_tick <= 1'b0;
millisec_tick <= 1'b0;
second_tick <= 1'b0;
end else begin
timer <= timer + 1;
millisec_tick <= 1'b0;
second_tick <= 1'b0;
microsec_tick <= 1'b0;
if (timer == MICROSEC) begin
timer <= 0;
microsec <= microsec + 1;
microsec_tick <= 1'b1;
if (microsec == 999) begin
microsec <= 0;
millisec <= millisec + 1;
millisec_tick <= 1'b1;
if (millisec == next_millisec) begin
second <= second+1;
next_millisec <= next_millisec + 1000;
second_tick <= 1'b1;
end
end
end
if (chipselect && write && address==`CTRL_OFFSET)
ctrl_reg <= writedata;
if (chipselect && write && address==`IRQ_TIME_OFFSET)
irq_time <= writedata;
if (irq_active)
irq_pulse <= 1'b1;
else if (chipselect && write && address == `IRQ_STATUS_OFFSET && writedata[0]==1'b1)
irq_pulse <= 1'b0;
irq_active <= 1'b0;
if (ctrl_reg[`IRQ_COUNTDOWN_ENA_BIT]==1'b1) begin
if (millisec_tick == 1'b1) begin
irq_timer <= irq_timer + 1;
if (irq_timer == irq_time) begin
irq_active <= 1'b1;
if (ctrl_reg[`IRQ_TIMER_CONTINUOUS_BIT]==1'b1) begin
irq_timer <= 0;
end
end
end
end else
if (ctrl_reg[`IRQ_TIMER_MATCH_ENA_BIT]==1'b1) begin
if (millisec == irq_time) begin
irq_active <= 1'b1;
end
end
end
assign irq = irq_pulse;
endmodule | module recon_timer (
address,
chipselect,
clk,
reset_n,
write,
read,
writedata,
readdata,
irq,
microsec_tick,
millisec_tick,
second_tick
); |
parameter CLK_FREQ = 50000000;
parameter MILLISEC = CLK_FREQ/1000-1;
parameter MICROSEC = CLK_FREQ/1000000-1;
output [ 31: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write;
input read;
input [ 31: 0] writedata;
output irq;
output reg microsec_tick;
output reg millisec_tick;
output reg second_tick;
wire [ 31: 0] readdata;
reg [ 31: 0] read_mux_reg;
reg [ 9: 0] microsec;
reg [ 31: 0] millisec;
reg [ 31: 0] next_millisec;
reg [ 31: 0] second;
reg [ 3: 0] ctrl_reg;
reg [ 31: 0] irq_timer;
reg [ 31: 0] irq_time;
reg [ 9: 0] timer;
reg irq_active;
reg irq_active_d;
reg irq_pulse;
always@(posedge clk)
begin
if (chipselect && read)
case(address)
`MILLISEC_OFFSET : read_mux_reg <= millisec;
`SECOND_OFFSET : read_mux_reg <= second;
`IRQ_TIME_OFFSET : read_mux_reg <= irq_time;
`CTRL_OFFSET : read_mux_reg <= {28'h0, ctrl_reg};
`IRQ_STATUS_OFFSET : read_mux_reg <= {31'h0, irq_pulse};
default : read_mux_reg <= 32'h0;
endcase
end
assign readdata = read_mux_reg;
always@(posedge clk or negedge reset_n)
if (~reset_n) begin
millisec <= 0;
second <= 0;
next_millisec <= 999;
microsec_tick <= 1'b0;
millisec_tick <= 1'b0;
second_tick <= 1'b0;
end else begin
timer <= timer + 1;
millisec_tick <= 1'b0;
second_tick <= 1'b0;
microsec_tick <= 1'b0;
if (timer == MICROSEC) begin
timer <= 0;
microsec <= microsec + 1;
microsec_tick <= 1'b1;
if (microsec == 999) begin
microsec <= 0;
millisec <= millisec + 1;
millisec_tick <= 1'b1;
if (millisec == next_millisec) begin
second <= second+1;
next_millisec <= next_millisec + 1000;
second_tick <= 1'b1;
end
end
end
if (chipselect && write && address==`CTRL_OFFSET)
ctrl_reg <= writedata;
if (chipselect && write && address==`IRQ_TIME_OFFSET)
irq_time <= writedata;
if (irq_active)
irq_pulse <= 1'b1;
else if (chipselect && write && address == `IRQ_STATUS_OFFSET && writedata[0]==1'b1)
irq_pulse <= 1'b0;
irq_active <= 1'b0;
if (ctrl_reg[`IRQ_COUNTDOWN_ENA_BIT]==1'b1) begin
if (millisec_tick == 1'b1) begin
irq_timer <= irq_timer + 1;
if (irq_timer == irq_time) begin
irq_active <= 1'b1;
if (ctrl_reg[`IRQ_TIMER_CONTINUOUS_BIT]==1'b1) begin
irq_timer <= 0;
end
end
end
end else
if (ctrl_reg[`IRQ_TIMER_MATCH_ENA_BIT]==1'b1) begin
if (millisec == irq_time) begin
irq_active <= 1'b1;
end
end
end
assign irq = irq_pulse;
endmodule | 21 |
140,781 | data/full_repos/permissive/91688960/hw/cmn/util/buttonDebouncer.v | 91,688,960 | buttonDebouncer.v | v | 82 | 137 | [] | [] | [] | [(7, 79)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/91688960/hw/cmn/util/buttonDebouncer.v:76: Signal definition not found, creating implicitly: \'buttonTick\'\n : ... Suggested alternative: \'buttonTck\'\n assign buttonTick = buttonTck;\n ^~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/util/buttonDebouncer.v:50: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n : ... In instance buttonDebouncer\n debouncer <= pDEBOUNCE_PERIOD/pCLKIN_PERIOD;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/91688960/hw/cmn/util/buttonDebouncer.v:76: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'buttonTck\' generates 2 bits.\n : ... In instance buttonDebouncer\n assign buttonTick = buttonTck;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 309,695 | module | module buttonDebouncer
#(
parameter pDEBOUNCE_PERIOD = 100_000_000,
parameter pCLKIN_PERIOD = 20,
parameter pARRAY_SIZE = 2,
parameter pPOLARITY = 0)(
input clk ,
input [ pARRAY_SIZE-1:0] buttons ,
output [ pARRAY_SIZE-1:0] buttonState,
output reg [ pARRAY_SIZE-1:0] buttonUpTick,
output reg [ pARRAY_SIZE-1:0] buttonDwTick
);
reg [pARRAY_SIZE-1:0] buttonsReg0;
reg [pARRAY_SIZE-1:0] buttonsReg1;
reg [pARRAY_SIZE-1:0] buttonsReg2;
reg [23:0] debouncer;
reg [pARRAY_SIZE-1:0] buttonsDebounced;
reg [pARRAY_SIZE-1:0] buttonsDebouncedReg;
reg [pARRAY_SIZE-1:0] buttonTck;
integer I;
always@(posedge clk)
begin
buttonsReg0 <= buttons;
buttonsReg1 <= buttonsReg0;
buttonsReg2 <= buttonsReg1;
if (buttonsReg2 != buttonsReg1)
begin
debouncer <= pDEBOUNCE_PERIOD/pCLKIN_PERIOD;
end
else if (debouncer != 0)
begin
debouncer <= debouncer - 1;
end
else begin
buttonsDebounced <= buttonsReg2;
end
buttonsDebouncedReg <= buttonsDebounced;
for(I = 0; I<pARRAY_SIZE; I = I + 1)
begin
if (pPOLARITY==0) begin
buttonDwTick[I] <= buttonsDebouncedReg[I] & (~buttonsDebounced[I]);
buttonUpTick[I] <= ~buttonsDebouncedReg[I] & buttonsDebounced[I];
end
else begin
buttonUpTick[I] <= buttonsDebouncedReg[I] & (~buttonsDebounced[I]);
buttonDwTick[I] <= ~buttonsDebouncedReg[I] & buttonsDebounced[I];
end
end
end
assign buttonTick = buttonTck;
assign buttonState = buttonsDebouncedReg;
endmodule | module buttonDebouncer
#(
parameter pDEBOUNCE_PERIOD = 100_000_000,
parameter pCLKIN_PERIOD = 20,
parameter pARRAY_SIZE = 2,
parameter pPOLARITY = 0)(
input clk ,
input [ pARRAY_SIZE-1:0] buttons ,
output [ pARRAY_SIZE-1:0] buttonState,
output reg [ pARRAY_SIZE-1:0] buttonUpTick,
output reg [ pARRAY_SIZE-1:0] buttonDwTick
); |
reg [pARRAY_SIZE-1:0] buttonsReg0;
reg [pARRAY_SIZE-1:0] buttonsReg1;
reg [pARRAY_SIZE-1:0] buttonsReg2;
reg [23:0] debouncer;
reg [pARRAY_SIZE-1:0] buttonsDebounced;
reg [pARRAY_SIZE-1:0] buttonsDebouncedReg;
reg [pARRAY_SIZE-1:0] buttonTck;
integer I;
always@(posedge clk)
begin
buttonsReg0 <= buttons;
buttonsReg1 <= buttonsReg0;
buttonsReg2 <= buttonsReg1;
if (buttonsReg2 != buttonsReg1)
begin
debouncer <= pDEBOUNCE_PERIOD/pCLKIN_PERIOD;
end
else if (debouncer != 0)
begin
debouncer <= debouncer - 1;
end
else begin
buttonsDebounced <= buttonsReg2;
end
buttonsDebouncedReg <= buttonsDebounced;
for(I = 0; I<pARRAY_SIZE; I = I + 1)
begin
if (pPOLARITY==0) begin
buttonDwTick[I] <= buttonsDebouncedReg[I] & (~buttonsDebounced[I]);
buttonUpTick[I] <= ~buttonsDebouncedReg[I] & buttonsDebounced[I];
end
else begin
buttonUpTick[I] <= buttonsDebouncedReg[I] & (~buttonsDebounced[I]);
buttonDwTick[I] <= ~buttonsDebouncedReg[I] & buttonsDebounced[I];
end
end
end
assign buttonTick = buttonTck;
assign buttonState = buttonsDebouncedReg;
endmodule | 21 |
140,782 | data/full_repos/permissive/91688960/hw/cmn/util/metaSync.v | 91,688,960 | metaSync.v | v | 33 | 38 | [] | [] | [] | [(2, 32)] | null | data/verilator_xmls/575f7b64-e790-49bd-bc85-85263eca8034.xml | null | 309,696 | module | module metaSync (iClk, iRst,in,out);
parameter pSTAGE = 3;
parameter pRSTVAL = 1'b0;
parameter pRESET = 1'b0;
input iClk;
input in;
input iRst;
output out;
reg [pSTAGE-1:0] dff;
integer I;
wire reset;
assign reset = iRst^pRESET;
always@(posedge iClk or posedge iRst)
if (iRst)
begin
for(I=0;I<pSTAGE;I=I+1)
begin
dff[I] <= pRSTVAL;
end
end
else
begin
dff <= {dff[pSTAGE-2:0], in};
end
assign out = dff[pSTAGE-1];
endmodule | module metaSync (iClk, iRst,in,out); |
parameter pSTAGE = 3;
parameter pRSTVAL = 1'b0;
parameter pRESET = 1'b0;
input iClk;
input in;
input iRst;
output out;
reg [pSTAGE-1:0] dff;
integer I;
wire reset;
assign reset = iRst^pRESET;
always@(posedge iClk or posedge iRst)
if (iRst)
begin
for(I=0;I<pSTAGE;I=I+1)
begin
dff[I] <= pRSTVAL;
end
end
else
begin
dff <= {dff[pSTAGE-2:0], in};
end
assign out = dff[pSTAGE-1];
endmodule | 21 |
140,783 | data/full_repos/permissive/91688960/hw/recon_0a/recon_0a_top.v | 91,688,960 | recon_0a_top.v | v | 81 | 133 | [] | [] | [] | [(8, 80)] | null | null | 1: b"%Error: data/full_repos/permissive/91688960/hw/recon_0a/recon_0a_top.v:56: syntax error, unexpected '(', expecting IDENTIFIER\n .adc_0_adc_pll_input_export (locked),\n ^\n%Error: Exiting due to 1 error(s)\n" | 309,700 | module | module recon_0a_top #(parameter PORT_0_WIDTH = 16) (
input sys_clk,
input sys_rstn,
inout [ PORT_0_WIDTH-1:0] port_0_io,
output uart_0_txd,
input uart_0_rxd
);
wire [PORT_0_WIDTH-1:0] port_0_out;
wire [PORT_0_WIDTH-1:0] port_0_in;
wire [PORT_0_WIDTH-1:0] port_0_oe;
wire [PORT_0_WIDTH-1:0] port_0_opdrn;
wire cpu_clk, locked;
alt_pll pll(
.areset (~sys_rstn),
.inclk0 (sys_clk),
.c0 (cpu_clk),
.locked (locked));
buttonDebouncer
#(
.pDEBOUNCE_PERIOD (100_000_000),
.pCLKIN_PERIOD (20 ),
.pARRAY_SIZE (1 ),
.pPOLARITY (0)) resetDebounce
(
.clk (sys_clk),
.buttons (sys_rstn),
.buttonState (sys_rstn_db),
.buttonUpTick (),
.buttonDwTick ()
);
recon_0a (
.adc_0_adc_pll_input_export (locked),
.clk_clk (cpu_clk),
.recon_io_0_io_port_io_out (port_0_out),
.recon_io_0_io_port_io_opdrn (port_0_opdrn),
.recon_io_0_io_port_io_in (port_0_in),
.recon_io_0_io_port_io_oe (port_0_oe),
.recon_timer_0_clock_tick_second (),
.recon_timer_0_clock_tick_millisecond (),
.recon_timer_0_clock_tick_microsec (),
.reset_reset_n (sys_rstn_db),
.uart_0_rxd (uart_0_rxd),
.uart_0_txd (uart_0_txd)
);
genvar IO;
generate
for (IO = 0; IO<PORT_0_WIDTH;IO=IO+1)
begin : assign_io
assign port_0_io[IO] = (port_0_oe[IO]==1'b0||(port_0_out[IO]==1'b1&&port_0_opdrn[IO]==1'b1))?1'bz:port_0_out[IO];
assign port_0_in[IO] = port_0_io[IO];
end
endgenerate
endmodule | module recon_0a_top #(parameter PORT_0_WIDTH = 16) (
input sys_clk,
input sys_rstn,
inout [ PORT_0_WIDTH-1:0] port_0_io,
output uart_0_txd,
input uart_0_rxd
); |
wire [PORT_0_WIDTH-1:0] port_0_out;
wire [PORT_0_WIDTH-1:0] port_0_in;
wire [PORT_0_WIDTH-1:0] port_0_oe;
wire [PORT_0_WIDTH-1:0] port_0_opdrn;
wire cpu_clk, locked;
alt_pll pll(
.areset (~sys_rstn),
.inclk0 (sys_clk),
.c0 (cpu_clk),
.locked (locked));
buttonDebouncer
#(
.pDEBOUNCE_PERIOD (100_000_000),
.pCLKIN_PERIOD (20 ),
.pARRAY_SIZE (1 ),
.pPOLARITY (0)) resetDebounce
(
.clk (sys_clk),
.buttons (sys_rstn),
.buttonState (sys_rstn_db),
.buttonUpTick (),
.buttonDwTick ()
);
recon_0a (
.adc_0_adc_pll_input_export (locked),
.clk_clk (cpu_clk),
.recon_io_0_io_port_io_out (port_0_out),
.recon_io_0_io_port_io_opdrn (port_0_opdrn),
.recon_io_0_io_port_io_in (port_0_in),
.recon_io_0_io_port_io_oe (port_0_oe),
.recon_timer_0_clock_tick_second (),
.recon_timer_0_clock_tick_millisecond (),
.recon_timer_0_clock_tick_microsec (),
.reset_reset_n (sys_rstn_db),
.uart_0_rxd (uart_0_rxd),
.uart_0_txd (uart_0_txd)
);
genvar IO;
generate
for (IO = 0; IO<PORT_0_WIDTH;IO=IO+1)
begin : assign_io
assign port_0_io[IO] = (port_0_oe[IO]==1'b0||(port_0_out[IO]==1'b1&&port_0_opdrn[IO]==1'b1))?1'bz:port_0_out[IO];
assign port_0_in[IO] = port_0_io[IO];
end
endgenerate
endmodule | 21 |
140,784 | data/full_repos/permissive/91688960/hw/recon_1/recon_1_top.v | 91,688,960 | recon_1_top.v | v | 79 | 133 | [] | [] | [] | [(8, 78)] | null | null | 1: b"%Error: data/full_repos/permissive/91688960/hw/recon_1/recon_1_top.v:49: syntax error, unexpected '(', expecting IDENTIFIER\n .altpll_0_locked_export ( ), \n ^\n%Error: Exiting due to 1 error(s)\n" | 309,702 | module | module recon_1_top #(parameter PORT_0_WIDTH = 32) (
input sys_clk,
input sys_rstn,
inout [ PORT_0_WIDTH-1:0] port_0_io,
output uart_0_txd,
input uart_0_rxd,
output wire epcs_0_dclk,
output wire epcs_0_sce,
output wire epcs_0_sdo,
input wire epcs_0_data0
);
wire [PORT_0_WIDTH-1:0] port_0_out;
wire [PORT_0_WIDTH-1:0] port_0_in;
wire [PORT_0_WIDTH-1:0] port_0_oe;
wire [PORT_0_WIDTH-1:0] port_0_opdrn;
buttonDebouncer
#(
.pDEBOUNCE_PERIOD (100_000_000),
.pCLKIN_PERIOD (20 ),
.pARRAY_SIZE (1 ),
.pPOLARITY (0)) resetDebounce
(
.clk (sys_clk),
.buttons (sys_rstn),
.buttonState (sys_rstn_db),
.buttonUpTick (),
.buttonDwTick ()
);
recon_1 (
.altpll_0_locked_export ( ),
.clk_clk (sys_clk),
.recon_io_0_io_port_io_out (port_0_out),
.recon_io_0_io_port_io_opdrn (port_0_opdrn),
.recon_io_0_io_port_io_in (port_0_in),
.recon_io_0_io_port_io_oe (port_0_oe),
.recon_timer_0_clock_tick_second (),
.recon_timer_0_clock_tick_millisecond (),
.recon_timer_0_clock_tick_microsec (),
.reset_reset_n (sys_rstn_db),
.uart_0_rxd (uart_0_rxd),
.uart_0_txd (uart_0_txd),
.epcs_0_dclk (epcs_0_dclk),
.epcs_0_sce (epcs_0_sce),
.epcs_0_sdo (epcs_0_sdo),
.epcs_0_data0 (epcs_0_data0)
);
genvar IO;
generate
for (IO = 0; IO<PORT_0_WIDTH;IO=IO+1)
begin : assign_io
assign port_0_io[IO] = (port_0_oe[IO]==1'b0||(port_0_out[IO]==1'b1&&port_0_opdrn[IO]==1'b1))?1'bz:port_0_out[IO];
assign port_0_in[IO] = port_0_io[IO];
end
endgenerate
endmodule | module recon_1_top #(parameter PORT_0_WIDTH = 32) (
input sys_clk,
input sys_rstn,
inout [ PORT_0_WIDTH-1:0] port_0_io,
output uart_0_txd,
input uart_0_rxd,
output wire epcs_0_dclk,
output wire epcs_0_sce,
output wire epcs_0_sdo,
input wire epcs_0_data0
); |
wire [PORT_0_WIDTH-1:0] port_0_out;
wire [PORT_0_WIDTH-1:0] port_0_in;
wire [PORT_0_WIDTH-1:0] port_0_oe;
wire [PORT_0_WIDTH-1:0] port_0_opdrn;
buttonDebouncer
#(
.pDEBOUNCE_PERIOD (100_000_000),
.pCLKIN_PERIOD (20 ),
.pARRAY_SIZE (1 ),
.pPOLARITY (0)) resetDebounce
(
.clk (sys_clk),
.buttons (sys_rstn),
.buttonState (sys_rstn_db),
.buttonUpTick (),
.buttonDwTick ()
);
recon_1 (
.altpll_0_locked_export ( ),
.clk_clk (sys_clk),
.recon_io_0_io_port_io_out (port_0_out),
.recon_io_0_io_port_io_opdrn (port_0_opdrn),
.recon_io_0_io_port_io_in (port_0_in),
.recon_io_0_io_port_io_oe (port_0_oe),
.recon_timer_0_clock_tick_second (),
.recon_timer_0_clock_tick_millisecond (),
.recon_timer_0_clock_tick_microsec (),
.reset_reset_n (sys_rstn_db),
.uart_0_rxd (uart_0_rxd),
.uart_0_txd (uart_0_txd),
.epcs_0_dclk (epcs_0_dclk),
.epcs_0_sce (epcs_0_sce),
.epcs_0_sdo (epcs_0_sdo),
.epcs_0_data0 (epcs_0_data0)
);
genvar IO;
generate
for (IO = 0; IO<PORT_0_WIDTH;IO=IO+1)
begin : assign_io
assign port_0_io[IO] = (port_0_oe[IO]==1'b0||(port_0_out[IO]==1'b1&&port_0_opdrn[IO]==1'b1))?1'bz:port_0_out[IO];
assign port_0_in[IO] = port_0_io[IO];
end
endgenerate
endmodule | 21 |
140,786 | data/full_repos/permissive/91778934/ALU/alu.v | 91,778,934 | alu.v | v | 40 | 102 | [] | [] | [] | null | line:34: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/ALU/alu.v:30: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("alu.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/ALU/alu.v:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/ALU/alu.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/ALU/alu.v:38: Unsupported: Ignoring delay on this delayed statement.\n initial #1000 $finish; \n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,706 | module | module alu(input [7:0] a, input [7:0] b, input [2:0] op, output reg [7:0] y);
always@(a or b or op) begin
case(op)
3'b000: y = a + b;
3'b001: y = a - b;
3'b010: y = a * b;
3'b011: y = a / b;
3'b100: y = a & b;
3'b101: y = a | b;
3'b110: y = ~a;
3'b111: y = a ^ b;
endcase
$display("base 10 : %dns : op=%d a=%d b=%d y=%d", $stime, op, a, b, y);
$display("base 2 : %dns : op=%b a=%b b=%b y=%b", $stime, op, a, b, y);
end
endmodule | module alu(input [7:0] a, input [7:0] b, input [2:0] op, output reg [7:0] y); |
always@(a or b or op) begin
case(op)
3'b000: y = a + b;
3'b001: y = a - b;
3'b010: y = a * b;
3'b011: y = a / b;
3'b100: y = a & b;
3'b101: y = a | b;
3'b110: y = ~a;
3'b111: y = a ^ b;
endcase
$display("base 10 : %dns : op=%d a=%d b=%d y=%d", $stime, op, a, b, y);
$display("base 2 : %dns : op=%b a=%b b=%b y=%b", $stime, op, a, b, y);
end
endmodule | 0 |
140,787 | data/full_repos/permissive/91778934/ALU/alu.v | 91,778,934 | alu.v | v | 40 | 102 | [] | [] | [] | null | line:34: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/ALU/alu.v:30: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("alu.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/ALU/alu.v:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/ALU/alu.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/ALU/alu.v:38: Unsupported: Ignoring delay on this delayed statement.\n initial #1000 $finish; \n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,706 | module | module main;
reg [7:0] a, b;
wire [7:0] y;
reg [2:0] op;
alu alu1(a, b, op, y);
initial begin
a = 8'h07;
b = 8'h03;
op = 3'b000;
$dumpfile("alu.vcd");
$dumpvars;
end
always #50 begin
op = op + 1;
end
initial #1000 $finish;
endmodule | module main; |
reg [7:0] a, b;
wire [7:0] y;
reg [2:0] op;
alu alu1(a, b, op, y);
initial begin
a = 8'h07;
b = 8'h03;
op = 3'b000;
$dumpfile("alu.vcd");
$dumpvars;
end
always #50 begin
op = op + 1;
end
initial #1000 $finish;
endmodule | 0 |
140,788 | data/full_repos/permissive/91778934/Counter/counter.v | 91,778,934 | counter.v | v | 37 | 37 | [] | [] | [] | null | line:7: before: "rst" | null | 1: b'%Error: data/full_repos/permissive/91778934/Counter/counter.v:24: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("counter.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/Counter/counter.v:25: Unsupported or unknown PLI call: $dumpvars\n $dumpvars; \n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:28: Unsupported: Ignoring delay on this delayed statement.\n initial #100 rst = 0; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = clk + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:30: Unsupported: Ignoring delay on this delayed statement.\n initial #500 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:31: Unsupported: Ignoring delay on this delayed statement.\n initial #525 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:33: Unsupported: Ignoring delay on this delayed statement.\n initial #2000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,707 | module | module counter(
input clk,
input rst,
output reg [2:0] out
);
always @(posedge clk or rst) begin
if (rst) out = 3'b000;
else out = out + 1;
end
endmodule | module counter(
input clk,
input rst,
output reg [2:0] out
); |
always @(posedge clk or rst) begin
if (rst) out = 3'b000;
else out = out + 1;
end
endmodule | 0 |
140,789 | data/full_repos/permissive/91778934/Counter/counter.v | 91,778,934 | counter.v | v | 37 | 37 | [] | [] | [] | null | line:7: before: "rst" | null | 1: b'%Error: data/full_repos/permissive/91778934/Counter/counter.v:24: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("counter.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/Counter/counter.v:25: Unsupported or unknown PLI call: $dumpvars\n $dumpvars; \n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:28: Unsupported: Ignoring delay on this delayed statement.\n initial #100 rst = 0; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = clk + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:30: Unsupported: Ignoring delay on this delayed statement.\n initial #500 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:31: Unsupported: Ignoring delay on this delayed statement.\n initial #525 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Counter/counter.v:33: Unsupported: Ignoring delay on this delayed statement.\n initial #2000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,707 | module | module main;
reg clk;
reg rst;
wire [2:0] out;
counter DUT (clk, rst, out);
initial begin
clk = 0;
rst = 1;
$dumpfile("counter.vcd");
$dumpvars;
end
initial #100 rst = 0;
always #50 clk = clk + 1;
initial #500 rst = 1;
initial #525 rst = 0;
initial #2000 $finish;
endmodule | module main; |
reg clk;
reg rst;
wire [2:0] out;
counter DUT (clk, rst, out);
initial begin
clk = 0;
rst = 1;
$dumpfile("counter.vcd");
$dumpvars;
end
initial #100 rst = 0;
always #50 clk = clk + 1;
initial #500 rst = 1;
initial #525 rst = 0;
initial #2000 $finish;
endmodule | 0 |
140,790 | data/full_repos/permissive/91778934/Decode2_4/deco2_4.v | 91,778,934 | deco2_4.v | v | 29 | 52 | [] | [] | [] | [(3, 8), (10, 29)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91778934/Decode2_4/deco2_4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91778934/Decode2_4/deco2_4.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("deco2_4.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/Decode2_4/deco2_4.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,708 | module | module deco2_4(input a, input b, output [3:0] y);
assign y[0] = ({a, b} == 2'b00);
assign y[1] = ({a, b} == 2'b01);
assign y[2] = ({a, b} == 2'b10);
assign y[3] = ({a, b} == 2'b11);
endmodule | module deco2_4(input a, input b, output [3:0] y); |
assign y[0] = ({a, b} == 2'b00);
assign y[1] = ({a, b} == 2'b01);
assign y[2] = ({a, b} == 2'b10);
assign y[3] = ({a, b} == 2'b11);
endmodule | 0 |
140,791 | data/full_repos/permissive/91778934/Decode2_4/deco2_4.v | 91,778,934 | deco2_4.v | v | 29 | 52 | [] | [] | [] | [(3, 8), (10, 29)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91778934/Decode2_4/deco2_4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91778934/Decode2_4/deco2_4.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("deco2_4.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/Decode2_4/deco2_4.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,708 | module | module main;
reg a, b;
wire [3:0] y;
deco2_4 d24(a, b, y);
integer i;
initial begin
for(i = 0; i <= 16; i = i + 1) begin
{a, b} = i;
#10;
end
end
initial begin
$dumpfile("deco2_4.vcd");
$dumpvars;
end
endmodule | module main; |
reg a, b;
wire [3:0] y;
deco2_4 d24(a, b, y);
integer i;
initial begin
for(i = 0; i <= 16; i = i + 1) begin
{a, b} = i;
#10;
end
end
initial begin
$dumpfile("deco2_4.vcd");
$dumpvars;
end
endmodule | 0 |
Subsets and Splits